]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
106 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
107 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
108 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
109 | int num_connectors); | |
e7457a9a | 110 | |
0e32b39c DA |
111 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
112 | { | |
113 | if (!connector->mst_port) | |
114 | return connector->encoder; | |
115 | else | |
116 | return &connector->mst_port->mst_encoders[pipe]->base; | |
117 | } | |
118 | ||
79e53945 | 119 | typedef struct { |
0206e353 | 120 | int min, max; |
79e53945 JB |
121 | } intel_range_t; |
122 | ||
123 | typedef struct { | |
0206e353 AJ |
124 | int dot_limit; |
125 | int p2_slow, p2_fast; | |
79e53945 JB |
126 | } intel_p2_t; |
127 | ||
d4906093 ML |
128 | typedef struct intel_limit intel_limit_t; |
129 | struct intel_limit { | |
0206e353 AJ |
130 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
131 | intel_p2_t p2; | |
d4906093 | 132 | }; |
79e53945 | 133 | |
d2acd215 DV |
134 | int |
135 | intel_pch_rawclk(struct drm_device *dev) | |
136 | { | |
137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
138 | ||
139 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
140 | ||
141 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
142 | } | |
143 | ||
021357ac CW |
144 | static inline u32 /* units of 100MHz */ |
145 | intel_fdi_link_freq(struct drm_device *dev) | |
146 | { | |
8b99e68c CW |
147 | if (IS_GEN5(dev)) { |
148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
149 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
150 | } else | |
151 | return 27; | |
021357ac CW |
152 | } |
153 | ||
5d536e28 | 154 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 155 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 156 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 157 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
158 | .m = { .min = 96, .max = 140 }, |
159 | .m1 = { .min = 18, .max = 26 }, | |
160 | .m2 = { .min = 6, .max = 16 }, | |
161 | .p = { .min = 4, .max = 128 }, | |
162 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
163 | .p2 = { .dot_limit = 165000, |
164 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
165 | }; |
166 | ||
5d536e28 DV |
167 | static const intel_limit_t intel_limits_i8xx_dvo = { |
168 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 169 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 170 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
171 | .m = { .min = 96, .max = 140 }, |
172 | .m1 = { .min = 18, .max = 26 }, | |
173 | .m2 = { .min = 6, .max = 16 }, | |
174 | .p = { .min = 4, .max = 128 }, | |
175 | .p1 = { .min = 2, .max = 33 }, | |
176 | .p2 = { .dot_limit = 165000, | |
177 | .p2_slow = 4, .p2_fast = 4 }, | |
178 | }; | |
179 | ||
e4b36699 | 180 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 181 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 182 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 183 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
184 | .m = { .min = 96, .max = 140 }, |
185 | .m1 = { .min = 18, .max = 26 }, | |
186 | .m2 = { .min = 6, .max = 16 }, | |
187 | .p = { .min = 4, .max = 128 }, | |
188 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
189 | .p2 = { .dot_limit = 165000, |
190 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 191 | }; |
273e27ca | 192 | |
e4b36699 | 193 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
194 | .dot = { .min = 20000, .max = 400000 }, |
195 | .vco = { .min = 1400000, .max = 2800000 }, | |
196 | .n = { .min = 1, .max = 6 }, | |
197 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
198 | .m1 = { .min = 8, .max = 18 }, |
199 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
200 | .p = { .min = 5, .max = 80 }, |
201 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
202 | .p2 = { .dot_limit = 200000, |
203 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
204 | }; |
205 | ||
206 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
207 | .dot = { .min = 20000, .max = 400000 }, |
208 | .vco = { .min = 1400000, .max = 2800000 }, | |
209 | .n = { .min = 1, .max = 6 }, | |
210 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
211 | .m1 = { .min = 8, .max = 18 }, |
212 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
213 | .p = { .min = 7, .max = 98 }, |
214 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
215 | .p2 = { .dot_limit = 112000, |
216 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
217 | }; |
218 | ||
273e27ca | 219 | |
e4b36699 | 220 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
221 | .dot = { .min = 25000, .max = 270000 }, |
222 | .vco = { .min = 1750000, .max = 3500000}, | |
223 | .n = { .min = 1, .max = 4 }, | |
224 | .m = { .min = 104, .max = 138 }, | |
225 | .m1 = { .min = 17, .max = 23 }, | |
226 | .m2 = { .min = 5, .max = 11 }, | |
227 | .p = { .min = 10, .max = 30 }, | |
228 | .p1 = { .min = 1, .max = 3}, | |
229 | .p2 = { .dot_limit = 270000, | |
230 | .p2_slow = 10, | |
231 | .p2_fast = 10 | |
044c7c41 | 232 | }, |
e4b36699 KP |
233 | }; |
234 | ||
235 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
236 | .dot = { .min = 22000, .max = 400000 }, |
237 | .vco = { .min = 1750000, .max = 3500000}, | |
238 | .n = { .min = 1, .max = 4 }, | |
239 | .m = { .min = 104, .max = 138 }, | |
240 | .m1 = { .min = 16, .max = 23 }, | |
241 | .m2 = { .min = 5, .max = 11 }, | |
242 | .p = { .min = 5, .max = 80 }, | |
243 | .p1 = { .min = 1, .max = 8}, | |
244 | .p2 = { .dot_limit = 165000, | |
245 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
246 | }; |
247 | ||
248 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
249 | .dot = { .min = 20000, .max = 115000 }, |
250 | .vco = { .min = 1750000, .max = 3500000 }, | |
251 | .n = { .min = 1, .max = 3 }, | |
252 | .m = { .min = 104, .max = 138 }, | |
253 | .m1 = { .min = 17, .max = 23 }, | |
254 | .m2 = { .min = 5, .max = 11 }, | |
255 | .p = { .min = 28, .max = 112 }, | |
256 | .p1 = { .min = 2, .max = 8 }, | |
257 | .p2 = { .dot_limit = 0, | |
258 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 259 | }, |
e4b36699 KP |
260 | }; |
261 | ||
262 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
263 | .dot = { .min = 80000, .max = 224000 }, |
264 | .vco = { .min = 1750000, .max = 3500000 }, | |
265 | .n = { .min = 1, .max = 3 }, | |
266 | .m = { .min = 104, .max = 138 }, | |
267 | .m1 = { .min = 17, .max = 23 }, | |
268 | .m2 = { .min = 5, .max = 11 }, | |
269 | .p = { .min = 14, .max = 42 }, | |
270 | .p1 = { .min = 2, .max = 6 }, | |
271 | .p2 = { .dot_limit = 0, | |
272 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 273 | }, |
e4b36699 KP |
274 | }; |
275 | ||
f2b115e6 | 276 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
277 | .dot = { .min = 20000, .max = 400000}, |
278 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 279 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
280 | .n = { .min = 3, .max = 6 }, |
281 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 282 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
283 | .m1 = { .min = 0, .max = 0 }, |
284 | .m2 = { .min = 0, .max = 254 }, | |
285 | .p = { .min = 5, .max = 80 }, | |
286 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
287 | .p2 = { .dot_limit = 200000, |
288 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
289 | }; |
290 | ||
f2b115e6 | 291 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
292 | .dot = { .min = 20000, .max = 400000 }, |
293 | .vco = { .min = 1700000, .max = 3500000 }, | |
294 | .n = { .min = 3, .max = 6 }, | |
295 | .m = { .min = 2, .max = 256 }, | |
296 | .m1 = { .min = 0, .max = 0 }, | |
297 | .m2 = { .min = 0, .max = 254 }, | |
298 | .p = { .min = 7, .max = 112 }, | |
299 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
300 | .p2 = { .dot_limit = 112000, |
301 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
302 | }; |
303 | ||
273e27ca EA |
304 | /* Ironlake / Sandybridge |
305 | * | |
306 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
307 | * the range value for them is (actual_value - 2). | |
308 | */ | |
b91ad0ec | 309 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
310 | .dot = { .min = 25000, .max = 350000 }, |
311 | .vco = { .min = 1760000, .max = 3510000 }, | |
312 | .n = { .min = 1, .max = 5 }, | |
313 | .m = { .min = 79, .max = 127 }, | |
314 | .m1 = { .min = 12, .max = 22 }, | |
315 | .m2 = { .min = 5, .max = 9 }, | |
316 | .p = { .min = 5, .max = 80 }, | |
317 | .p1 = { .min = 1, .max = 8 }, | |
318 | .p2 = { .dot_limit = 225000, | |
319 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
320 | }; |
321 | ||
b91ad0ec | 322 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
323 | .dot = { .min = 25000, .max = 350000 }, |
324 | .vco = { .min = 1760000, .max = 3510000 }, | |
325 | .n = { .min = 1, .max = 3 }, | |
326 | .m = { .min = 79, .max = 118 }, | |
327 | .m1 = { .min = 12, .max = 22 }, | |
328 | .m2 = { .min = 5, .max = 9 }, | |
329 | .p = { .min = 28, .max = 112 }, | |
330 | .p1 = { .min = 2, .max = 8 }, | |
331 | .p2 = { .dot_limit = 225000, | |
332 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
333 | }; |
334 | ||
335 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
336 | .dot = { .min = 25000, .max = 350000 }, |
337 | .vco = { .min = 1760000, .max = 3510000 }, | |
338 | .n = { .min = 1, .max = 3 }, | |
339 | .m = { .min = 79, .max = 127 }, | |
340 | .m1 = { .min = 12, .max = 22 }, | |
341 | .m2 = { .min = 5, .max = 9 }, | |
342 | .p = { .min = 14, .max = 56 }, | |
343 | .p1 = { .min = 2, .max = 8 }, | |
344 | .p2 = { .dot_limit = 225000, | |
345 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
346 | }; |
347 | ||
273e27ca | 348 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 349 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
350 | .dot = { .min = 25000, .max = 350000 }, |
351 | .vco = { .min = 1760000, .max = 3510000 }, | |
352 | .n = { .min = 1, .max = 2 }, | |
353 | .m = { .min = 79, .max = 126 }, | |
354 | .m1 = { .min = 12, .max = 22 }, | |
355 | .m2 = { .min = 5, .max = 9 }, | |
356 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 357 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
358 | .p2 = { .dot_limit = 225000, |
359 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
360 | }; |
361 | ||
362 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
363 | .dot = { .min = 25000, .max = 350000 }, |
364 | .vco = { .min = 1760000, .max = 3510000 }, | |
365 | .n = { .min = 1, .max = 3 }, | |
366 | .m = { .min = 79, .max = 126 }, | |
367 | .m1 = { .min = 12, .max = 22 }, | |
368 | .m2 = { .min = 5, .max = 9 }, | |
369 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 370 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
371 | .p2 = { .dot_limit = 225000, |
372 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
373 | }; |
374 | ||
dc730512 | 375 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
376 | /* |
377 | * These are the data rate limits (measured in fast clocks) | |
378 | * since those are the strictest limits we have. The fast | |
379 | * clock and actual rate limits are more relaxed, so checking | |
380 | * them would make no difference. | |
381 | */ | |
382 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 383 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 384 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
385 | .m1 = { .min = 2, .max = 3 }, |
386 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 387 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 388 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
389 | }; |
390 | ||
ef9348c8 CML |
391 | static const intel_limit_t intel_limits_chv = { |
392 | /* | |
393 | * These are the data rate limits (measured in fast clocks) | |
394 | * since those are the strictest limits we have. The fast | |
395 | * clock and actual rate limits are more relaxed, so checking | |
396 | * them would make no difference. | |
397 | */ | |
398 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 399 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
400 | .n = { .min = 1, .max = 1 }, |
401 | .m1 = { .min = 2, .max = 2 }, | |
402 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
403 | .p1 = { .min = 2, .max = 4 }, | |
404 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
405 | }; | |
406 | ||
5ab7b0b7 ID |
407 | static const intel_limit_t intel_limits_bxt = { |
408 | /* FIXME: find real dot limits */ | |
409 | .dot = { .min = 0, .max = INT_MAX }, | |
410 | .vco = { .min = 4800000, .max = 6480000 }, | |
411 | .n = { .min = 1, .max = 1 }, | |
412 | .m1 = { .min = 2, .max = 2 }, | |
413 | /* FIXME: find real m2 limits */ | |
414 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
415 | .p1 = { .min = 2, .max = 4 }, | |
416 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
417 | }; | |
418 | ||
6b4bf1c4 VS |
419 | static void vlv_clock(int refclk, intel_clock_t *clock) |
420 | { | |
421 | clock->m = clock->m1 * clock->m2; | |
422 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
423 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
424 | return; | |
fb03ac01 VS |
425 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
426 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
427 | } |
428 | ||
e0638cdf PZ |
429 | /** |
430 | * Returns whether any output on the specified pipe is of the specified type | |
431 | */ | |
4093561b | 432 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 433 | { |
409ee761 | 434 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
435 | struct intel_encoder *encoder; |
436 | ||
409ee761 | 437 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
438 | if (encoder->type == type) |
439 | return true; | |
440 | ||
441 | return false; | |
442 | } | |
443 | ||
d0737e1d ACO |
444 | /** |
445 | * Returns whether any output on the specified pipe will have the specified | |
446 | * type after a staged modeset is complete, i.e., the same as | |
447 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
448 | * encoder->crtc. | |
449 | */ | |
a93e255f ACO |
450 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
451 | int type) | |
d0737e1d | 452 | { |
a93e255f ACO |
453 | struct drm_atomic_state *state = crtc_state->base.state; |
454 | struct drm_connector_state *connector_state; | |
d0737e1d | 455 | struct intel_encoder *encoder; |
a93e255f ACO |
456 | int i, num_connectors = 0; |
457 | ||
458 | for (i = 0; i < state->num_connector; i++) { | |
459 | if (!state->connectors[i]) | |
460 | continue; | |
461 | ||
462 | connector_state = state->connector_states[i]; | |
463 | if (connector_state->crtc != crtc_state->base.crtc) | |
464 | continue; | |
465 | ||
466 | num_connectors++; | |
d0737e1d | 467 | |
a93e255f ACO |
468 | encoder = to_intel_encoder(connector_state->best_encoder); |
469 | if (encoder->type == type) | |
d0737e1d | 470 | return true; |
a93e255f ACO |
471 | } |
472 | ||
473 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
474 | |
475 | return false; | |
476 | } | |
477 | ||
a93e255f ACO |
478 | static const intel_limit_t * |
479 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 480 | { |
a93e255f | 481 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 482 | const intel_limit_t *limit; |
b91ad0ec | 483 | |
a93e255f | 484 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 485 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 486 | if (refclk == 100000) |
b91ad0ec ZW |
487 | limit = &intel_limits_ironlake_dual_lvds_100m; |
488 | else | |
489 | limit = &intel_limits_ironlake_dual_lvds; | |
490 | } else { | |
1b894b59 | 491 | if (refclk == 100000) |
b91ad0ec ZW |
492 | limit = &intel_limits_ironlake_single_lvds_100m; |
493 | else | |
494 | limit = &intel_limits_ironlake_single_lvds; | |
495 | } | |
c6bb3538 | 496 | } else |
b91ad0ec | 497 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
498 | |
499 | return limit; | |
500 | } | |
501 | ||
a93e255f ACO |
502 | static const intel_limit_t * |
503 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 504 | { |
a93e255f | 505 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
506 | const intel_limit_t *limit; |
507 | ||
a93e255f | 508 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 509 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 510 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 511 | else |
e4b36699 | 512 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
513 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
514 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 515 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 516 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 517 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 518 | } else /* The option is for other outputs */ |
e4b36699 | 519 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
520 | |
521 | return limit; | |
522 | } | |
523 | ||
a93e255f ACO |
524 | static const intel_limit_t * |
525 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 526 | { |
a93e255f | 527 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
528 | const intel_limit_t *limit; |
529 | ||
5ab7b0b7 ID |
530 | if (IS_BROXTON(dev)) |
531 | limit = &intel_limits_bxt; | |
532 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 533 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 534 | else if (IS_G4X(dev)) { |
a93e255f | 535 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 536 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 537 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 538 | limit = &intel_limits_pineview_lvds; |
2177832f | 539 | else |
f2b115e6 | 540 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
541 | } else if (IS_CHERRYVIEW(dev)) { |
542 | limit = &intel_limits_chv; | |
a0c4da24 | 543 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 544 | limit = &intel_limits_vlv; |
a6c45cf0 | 545 | } else if (!IS_GEN2(dev)) { |
a93e255f | 546 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
547 | limit = &intel_limits_i9xx_lvds; |
548 | else | |
549 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 550 | } else { |
a93e255f | 551 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 552 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 553 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 554 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
555 | else |
556 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
557 | } |
558 | return limit; | |
559 | } | |
560 | ||
f2b115e6 AJ |
561 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
562 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 563 | { |
2177832f SL |
564 | clock->m = clock->m2 + 2; |
565 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
566 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
567 | return; | |
fb03ac01 VS |
568 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
569 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
570 | } |
571 | ||
7429e9d4 DV |
572 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
573 | { | |
574 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
575 | } | |
576 | ||
ac58c3f0 | 577 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 578 | { |
7429e9d4 | 579 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 580 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
581 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
582 | return; | |
fb03ac01 VS |
583 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
584 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
585 | } |
586 | ||
ef9348c8 CML |
587 | static void chv_clock(int refclk, intel_clock_t *clock) |
588 | { | |
589 | clock->m = clock->m1 * clock->m2; | |
590 | clock->p = clock->p1 * clock->p2; | |
591 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
592 | return; | |
593 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
594 | clock->n << 22); | |
595 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
596 | } | |
597 | ||
7c04d1d9 | 598 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
599 | /** |
600 | * Returns whether the given set of divisors are valid for a given refclk with | |
601 | * the given connectors. | |
602 | */ | |
603 | ||
1b894b59 CW |
604 | static bool intel_PLL_is_valid(struct drm_device *dev, |
605 | const intel_limit_t *limit, | |
606 | const intel_clock_t *clock) | |
79e53945 | 607 | { |
f01b7962 VS |
608 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
609 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 610 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 611 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 612 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 613 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 614 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 615 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 616 | |
5ab7b0b7 | 617 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
5ab7b0b7 | 621 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
623 | INTELPllInvalid("p out of range\n"); | |
624 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
625 | INTELPllInvalid("m out of range\n"); | |
626 | } | |
627 | ||
79e53945 | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 629 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
631 | * connector, etc., rather than just a single range. | |
632 | */ | |
633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 634 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
635 | |
636 | return true; | |
637 | } | |
638 | ||
d4906093 | 639 | static bool |
a93e255f ACO |
640 | i9xx_find_best_dpll(const intel_limit_t *limit, |
641 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
642 | int target, int refclk, intel_clock_t *match_clock, |
643 | intel_clock_t *best_clock) | |
79e53945 | 644 | { |
a93e255f | 645 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 646 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 647 | intel_clock_t clock; |
79e53945 JB |
648 | int err = target; |
649 | ||
a93e255f | 650 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 651 | /* |
a210b028 DV |
652 | * For LVDS just rely on its current settings for dual-channel. |
653 | * We haven't figured out how to reliably set up different | |
654 | * single/dual channel state, if we even can. | |
79e53945 | 655 | */ |
1974cad0 | 656 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
657 | clock.p2 = limit->p2.p2_fast; |
658 | else | |
659 | clock.p2 = limit->p2.p2_slow; | |
660 | } else { | |
661 | if (target < limit->p2.dot_limit) | |
662 | clock.p2 = limit->p2.p2_slow; | |
663 | else | |
664 | clock.p2 = limit->p2.p2_fast; | |
665 | } | |
666 | ||
0206e353 | 667 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 668 | |
42158660 ZY |
669 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
670 | clock.m1++) { | |
671 | for (clock.m2 = limit->m2.min; | |
672 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 673 | if (clock.m2 >= clock.m1) |
42158660 ZY |
674 | break; |
675 | for (clock.n = limit->n.min; | |
676 | clock.n <= limit->n.max; clock.n++) { | |
677 | for (clock.p1 = limit->p1.min; | |
678 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
679 | int this_err; |
680 | ||
ac58c3f0 DV |
681 | i9xx_clock(refclk, &clock); |
682 | if (!intel_PLL_is_valid(dev, limit, | |
683 | &clock)) | |
684 | continue; | |
685 | if (match_clock && | |
686 | clock.p != match_clock->p) | |
687 | continue; | |
688 | ||
689 | this_err = abs(clock.dot - target); | |
690 | if (this_err < err) { | |
691 | *best_clock = clock; | |
692 | err = this_err; | |
693 | } | |
694 | } | |
695 | } | |
696 | } | |
697 | } | |
698 | ||
699 | return (err != target); | |
700 | } | |
701 | ||
702 | static bool | |
a93e255f ACO |
703 | pnv_find_best_dpll(const intel_limit_t *limit, |
704 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
705 | int target, int refclk, intel_clock_t *match_clock, |
706 | intel_clock_t *best_clock) | |
79e53945 | 707 | { |
a93e255f | 708 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 709 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 710 | intel_clock_t clock; |
79e53945 JB |
711 | int err = target; |
712 | ||
a93e255f | 713 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 714 | /* |
a210b028 DV |
715 | * For LVDS just rely on its current settings for dual-channel. |
716 | * We haven't figured out how to reliably set up different | |
717 | * single/dual channel state, if we even can. | |
79e53945 | 718 | */ |
1974cad0 | 719 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
720 | clock.p2 = limit->p2.p2_fast; |
721 | else | |
722 | clock.p2 = limit->p2.p2_slow; | |
723 | } else { | |
724 | if (target < limit->p2.dot_limit) | |
725 | clock.p2 = limit->p2.p2_slow; | |
726 | else | |
727 | clock.p2 = limit->p2.p2_fast; | |
728 | } | |
729 | ||
0206e353 | 730 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 731 | |
42158660 ZY |
732 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
733 | clock.m1++) { | |
734 | for (clock.m2 = limit->m2.min; | |
735 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
736 | for (clock.n = limit->n.min; |
737 | clock.n <= limit->n.max; clock.n++) { | |
738 | for (clock.p1 = limit->p1.min; | |
739 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
740 | int this_err; |
741 | ||
ac58c3f0 | 742 | pineview_clock(refclk, &clock); |
1b894b59 CW |
743 | if (!intel_PLL_is_valid(dev, limit, |
744 | &clock)) | |
79e53945 | 745 | continue; |
cec2f356 SP |
746 | if (match_clock && |
747 | clock.p != match_clock->p) | |
748 | continue; | |
79e53945 JB |
749 | |
750 | this_err = abs(clock.dot - target); | |
751 | if (this_err < err) { | |
752 | *best_clock = clock; | |
753 | err = this_err; | |
754 | } | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
760 | return (err != target); | |
761 | } | |
762 | ||
d4906093 | 763 | static bool |
a93e255f ACO |
764 | g4x_find_best_dpll(const intel_limit_t *limit, |
765 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
766 | int target, int refclk, intel_clock_t *match_clock, |
767 | intel_clock_t *best_clock) | |
d4906093 | 768 | { |
a93e255f | 769 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 770 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
771 | intel_clock_t clock; |
772 | int max_n; | |
773 | bool found; | |
6ba770dc AJ |
774 | /* approximately equals target * 0.00585 */ |
775 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
776 | found = false; |
777 | ||
a93e255f | 778 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 779 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
780 | clock.p2 = limit->p2.p2_fast; |
781 | else | |
782 | clock.p2 = limit->p2.p2_slow; | |
783 | } else { | |
784 | if (target < limit->p2.dot_limit) | |
785 | clock.p2 = limit->p2.p2_slow; | |
786 | else | |
787 | clock.p2 = limit->p2.p2_fast; | |
788 | } | |
789 | ||
790 | memset(best_clock, 0, sizeof(*best_clock)); | |
791 | max_n = limit->n.max; | |
f77f13e2 | 792 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 793 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 794 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
795 | for (clock.m1 = limit->m1.max; |
796 | clock.m1 >= limit->m1.min; clock.m1--) { | |
797 | for (clock.m2 = limit->m2.max; | |
798 | clock.m2 >= limit->m2.min; clock.m2--) { | |
799 | for (clock.p1 = limit->p1.max; | |
800 | clock.p1 >= limit->p1.min; clock.p1--) { | |
801 | int this_err; | |
802 | ||
ac58c3f0 | 803 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
804 | if (!intel_PLL_is_valid(dev, limit, |
805 | &clock)) | |
d4906093 | 806 | continue; |
1b894b59 CW |
807 | |
808 | this_err = abs(clock.dot - target); | |
d4906093 ML |
809 | if (this_err < err_most) { |
810 | *best_clock = clock; | |
811 | err_most = this_err; | |
812 | max_n = clock.n; | |
813 | found = true; | |
814 | } | |
815 | } | |
816 | } | |
817 | } | |
818 | } | |
2c07245f ZW |
819 | return found; |
820 | } | |
821 | ||
d5dd62bd ID |
822 | /* |
823 | * Check if the calculated PLL configuration is more optimal compared to the | |
824 | * best configuration and error found so far. Return the calculated error. | |
825 | */ | |
826 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
827 | const intel_clock_t *calculated_clock, | |
828 | const intel_clock_t *best_clock, | |
829 | unsigned int best_error_ppm, | |
830 | unsigned int *error_ppm) | |
831 | { | |
9ca3ba01 ID |
832 | /* |
833 | * For CHV ignore the error and consider only the P value. | |
834 | * Prefer a bigger P value based on HW requirements. | |
835 | */ | |
836 | if (IS_CHERRYVIEW(dev)) { | |
837 | *error_ppm = 0; | |
838 | ||
839 | return calculated_clock->p > best_clock->p; | |
840 | } | |
841 | ||
24be4e46 ID |
842 | if (WARN_ON_ONCE(!target_freq)) |
843 | return false; | |
844 | ||
d5dd62bd ID |
845 | *error_ppm = div_u64(1000000ULL * |
846 | abs(target_freq - calculated_clock->dot), | |
847 | target_freq); | |
848 | /* | |
849 | * Prefer a better P value over a better (smaller) error if the error | |
850 | * is small. Ensure this preference for future configurations too by | |
851 | * setting the error to 0. | |
852 | */ | |
853 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
854 | *error_ppm = 0; | |
855 | ||
856 | return true; | |
857 | } | |
858 | ||
859 | return *error_ppm + 10 < best_error_ppm; | |
860 | } | |
861 | ||
a0c4da24 | 862 | static bool |
a93e255f ACO |
863 | vlv_find_best_dpll(const intel_limit_t *limit, |
864 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
865 | int target, int refclk, intel_clock_t *match_clock, |
866 | intel_clock_t *best_clock) | |
a0c4da24 | 867 | { |
a93e255f | 868 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 869 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 870 | intel_clock_t clock; |
69e4f900 | 871 | unsigned int bestppm = 1000000; |
27e639bf VS |
872 | /* min update 19.2 MHz */ |
873 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 874 | bool found = false; |
a0c4da24 | 875 | |
6b4bf1c4 VS |
876 | target *= 5; /* fast clock */ |
877 | ||
878 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
879 | |
880 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 881 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 882 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 883 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 884 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 885 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 886 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 887 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 888 | unsigned int ppm; |
69e4f900 | 889 | |
6b4bf1c4 VS |
890 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
891 | refclk * clock.m1); | |
892 | ||
893 | vlv_clock(refclk, &clock); | |
43b0ac53 | 894 | |
f01b7962 VS |
895 | if (!intel_PLL_is_valid(dev, limit, |
896 | &clock)) | |
43b0ac53 VS |
897 | continue; |
898 | ||
d5dd62bd ID |
899 | if (!vlv_PLL_is_optimal(dev, target, |
900 | &clock, | |
901 | best_clock, | |
902 | bestppm, &ppm)) | |
903 | continue; | |
6b4bf1c4 | 904 | |
d5dd62bd ID |
905 | *best_clock = clock; |
906 | bestppm = ppm; | |
907 | found = true; | |
a0c4da24 JB |
908 | } |
909 | } | |
910 | } | |
911 | } | |
a0c4da24 | 912 | |
49e497ef | 913 | return found; |
a0c4da24 | 914 | } |
a4fc5ed6 | 915 | |
ef9348c8 | 916 | static bool |
a93e255f ACO |
917 | chv_find_best_dpll(const intel_limit_t *limit, |
918 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
919 | int target, int refclk, intel_clock_t *match_clock, |
920 | intel_clock_t *best_clock) | |
921 | { | |
a93e255f | 922 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 923 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 924 | unsigned int best_error_ppm; |
ef9348c8 CML |
925 | intel_clock_t clock; |
926 | uint64_t m2; | |
927 | int found = false; | |
928 | ||
929 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 930 | best_error_ppm = 1000000; |
ef9348c8 CML |
931 | |
932 | /* | |
933 | * Based on hardware doc, the n always set to 1, and m1 always | |
934 | * set to 2. If requires to support 200Mhz refclk, we need to | |
935 | * revisit this because n may not 1 anymore. | |
936 | */ | |
937 | clock.n = 1, clock.m1 = 2; | |
938 | target *= 5; /* fast clock */ | |
939 | ||
940 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
941 | for (clock.p2 = limit->p2.p2_fast; | |
942 | clock.p2 >= limit->p2.p2_slow; | |
943 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 944 | unsigned int error_ppm; |
ef9348c8 CML |
945 | |
946 | clock.p = clock.p1 * clock.p2; | |
947 | ||
948 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
949 | clock.n) << 22, refclk * clock.m1); | |
950 | ||
951 | if (m2 > INT_MAX/clock.m1) | |
952 | continue; | |
953 | ||
954 | clock.m2 = m2; | |
955 | ||
956 | chv_clock(refclk, &clock); | |
957 | ||
958 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
959 | continue; | |
960 | ||
9ca3ba01 ID |
961 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
962 | best_error_ppm, &error_ppm)) | |
963 | continue; | |
964 | ||
965 | *best_clock = clock; | |
966 | best_error_ppm = error_ppm; | |
967 | found = true; | |
ef9348c8 CML |
968 | } |
969 | } | |
970 | ||
971 | return found; | |
972 | } | |
973 | ||
5ab7b0b7 ID |
974 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
975 | intel_clock_t *best_clock) | |
976 | { | |
977 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
978 | ||
979 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
980 | target_clock, refclk, NULL, best_clock); | |
981 | } | |
982 | ||
20ddf665 VS |
983 | bool intel_crtc_active(struct drm_crtc *crtc) |
984 | { | |
985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
986 | ||
987 | /* Be paranoid as we can arrive here with only partial | |
988 | * state retrieved from the hardware during setup. | |
989 | * | |
241bfc38 | 990 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
991 | * as Haswell has gained clock readout/fastboot support. |
992 | * | |
66e514c1 | 993 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 994 | * properly reconstruct framebuffers. |
c3d1f436 MR |
995 | * |
996 | * FIXME: The intel_crtc->active here should be switched to | |
997 | * crtc->state->active once we have proper CRTC states wired up | |
998 | * for atomic. | |
20ddf665 | 999 | */ |
c3d1f436 | 1000 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1001 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1002 | } |
1003 | ||
a5c961d1 PZ |
1004 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1005 | enum pipe pipe) | |
1006 | { | |
1007 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1009 | ||
6e3c9717 | 1010 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1011 | } |
1012 | ||
fbf49ea2 VS |
1013 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1014 | { | |
1015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1016 | u32 reg = PIPEDSL(pipe); | |
1017 | u32 line1, line2; | |
1018 | u32 line_mask; | |
1019 | ||
1020 | if (IS_GEN2(dev)) | |
1021 | line_mask = DSL_LINEMASK_GEN2; | |
1022 | else | |
1023 | line_mask = DSL_LINEMASK_GEN3; | |
1024 | ||
1025 | line1 = I915_READ(reg) & line_mask; | |
1026 | mdelay(5); | |
1027 | line2 = I915_READ(reg) & line_mask; | |
1028 | ||
1029 | return line1 == line2; | |
1030 | } | |
1031 | ||
ab7ad7f6 KP |
1032 | /* |
1033 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1034 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1035 | * |
1036 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1037 | * spinning on the vblank interrupt status bit, since we won't actually | |
1038 | * see an interrupt when the pipe is disabled. | |
1039 | * | |
ab7ad7f6 KP |
1040 | * On Gen4 and above: |
1041 | * wait for the pipe register state bit to turn off | |
1042 | * | |
1043 | * Otherwise: | |
1044 | * wait for the display line value to settle (it usually | |
1045 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1046 | * |
9d0498a2 | 1047 | */ |
575f7ab7 | 1048 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1049 | { |
575f7ab7 | 1050 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1051 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1052 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1053 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1054 | |
1055 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1056 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1057 | |
1058 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1059 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1060 | 100)) | |
284637d9 | 1061 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1062 | } else { |
ab7ad7f6 | 1063 | /* Wait for the display line to settle */ |
fbf49ea2 | 1064 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1065 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1066 | } |
79e53945 JB |
1067 | } |
1068 | ||
b0ea7d37 DL |
1069 | /* |
1070 | * ibx_digital_port_connected - is the specified port connected? | |
1071 | * @dev_priv: i915 private structure | |
1072 | * @port: the port to test | |
1073 | * | |
1074 | * Returns true if @port is connected, false otherwise. | |
1075 | */ | |
1076 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1077 | struct intel_digital_port *port) | |
1078 | { | |
1079 | u32 bit; | |
1080 | ||
c36346e3 | 1081 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1082 | switch (port->port) { |
c36346e3 DL |
1083 | case PORT_B: |
1084 | bit = SDE_PORTB_HOTPLUG; | |
1085 | break; | |
1086 | case PORT_C: | |
1087 | bit = SDE_PORTC_HOTPLUG; | |
1088 | break; | |
1089 | case PORT_D: | |
1090 | bit = SDE_PORTD_HOTPLUG; | |
1091 | break; | |
1092 | default: | |
1093 | return true; | |
1094 | } | |
1095 | } else { | |
eba905b2 | 1096 | switch (port->port) { |
c36346e3 DL |
1097 | case PORT_B: |
1098 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1099 | break; | |
1100 | case PORT_C: | |
1101 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1102 | break; | |
1103 | case PORT_D: | |
1104 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1105 | break; | |
1106 | default: | |
1107 | return true; | |
1108 | } | |
b0ea7d37 DL |
1109 | } |
1110 | ||
1111 | return I915_READ(SDEISR) & bit; | |
1112 | } | |
1113 | ||
b24e7179 JB |
1114 | static const char *state_string(bool enabled) |
1115 | { | |
1116 | return enabled ? "on" : "off"; | |
1117 | } | |
1118 | ||
1119 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1120 | void assert_pll(struct drm_i915_private *dev_priv, |
1121 | enum pipe pipe, bool state) | |
b24e7179 JB |
1122 | { |
1123 | int reg; | |
1124 | u32 val; | |
1125 | bool cur_state; | |
1126 | ||
1127 | reg = DPLL(pipe); | |
1128 | val = I915_READ(reg); | |
1129 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1130 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1131 | "PLL state assertion failure (expected %s, current %s)\n", |
1132 | state_string(state), state_string(cur_state)); | |
1133 | } | |
b24e7179 | 1134 | |
23538ef1 JN |
1135 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1136 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1137 | { | |
1138 | u32 val; | |
1139 | bool cur_state; | |
1140 | ||
1141 | mutex_lock(&dev_priv->dpio_lock); | |
1142 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1143 | mutex_unlock(&dev_priv->dpio_lock); | |
1144 | ||
1145 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1146 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1147 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1148 | state_string(state), state_string(cur_state)); | |
1149 | } | |
1150 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1151 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1152 | ||
55607e8a | 1153 | struct intel_shared_dpll * |
e2b78267 DV |
1154 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1155 | { | |
1156 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1157 | ||
6e3c9717 | 1158 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1159 | return NULL; |
1160 | ||
6e3c9717 | 1161 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1162 | } |
1163 | ||
040484af | 1164 | /* For ILK+ */ |
55607e8a DV |
1165 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1166 | struct intel_shared_dpll *pll, | |
1167 | bool state) | |
040484af | 1168 | { |
040484af | 1169 | bool cur_state; |
5358901f | 1170 | struct intel_dpll_hw_state hw_state; |
040484af | 1171 | |
92b27b08 | 1172 | if (WARN (!pll, |
46edb027 | 1173 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1174 | return; |
ee7b9f93 | 1175 | |
5358901f | 1176 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1177 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1178 | "%s assertion failure (expected %s, current %s)\n", |
1179 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1180 | } |
040484af JB |
1181 | |
1182 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1183 | enum pipe pipe, bool state) | |
1184 | { | |
1185 | int reg; | |
1186 | u32 val; | |
1187 | bool cur_state; | |
ad80a810 PZ |
1188 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1189 | pipe); | |
040484af | 1190 | |
affa9354 PZ |
1191 | if (HAS_DDI(dev_priv->dev)) { |
1192 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1193 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1194 | val = I915_READ(reg); |
ad80a810 | 1195 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1196 | } else { |
1197 | reg = FDI_TX_CTL(pipe); | |
1198 | val = I915_READ(reg); | |
1199 | cur_state = !!(val & FDI_TX_ENABLE); | |
1200 | } | |
e2c719b7 | 1201 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1202 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1203 | state_string(state), state_string(cur_state)); | |
1204 | } | |
1205 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1206 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1207 | ||
1208 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1209 | enum pipe pipe, bool state) | |
1210 | { | |
1211 | int reg; | |
1212 | u32 val; | |
1213 | bool cur_state; | |
1214 | ||
d63fa0dc PZ |
1215 | reg = FDI_RX_CTL(pipe); |
1216 | val = I915_READ(reg); | |
1217 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1218 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1219 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1220 | state_string(state), state_string(cur_state)); | |
1221 | } | |
1222 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1223 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1224 | ||
1225 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1226 | enum pipe pipe) | |
1227 | { | |
1228 | int reg; | |
1229 | u32 val; | |
1230 | ||
1231 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1232 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1233 | return; |
1234 | ||
bf507ef7 | 1235 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1236 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1237 | return; |
1238 | ||
040484af JB |
1239 | reg = FDI_TX_CTL(pipe); |
1240 | val = I915_READ(reg); | |
e2c719b7 | 1241 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1242 | } |
1243 | ||
55607e8a DV |
1244 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1245 | enum pipe pipe, bool state) | |
040484af JB |
1246 | { |
1247 | int reg; | |
1248 | u32 val; | |
55607e8a | 1249 | bool cur_state; |
040484af JB |
1250 | |
1251 | reg = FDI_RX_CTL(pipe); | |
1252 | val = I915_READ(reg); | |
55607e8a | 1253 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1254 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1255 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1256 | state_string(state), state_string(cur_state)); | |
040484af JB |
1257 | } |
1258 | ||
b680c37a DV |
1259 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1260 | enum pipe pipe) | |
ea0760cf | 1261 | { |
bedd4dba JN |
1262 | struct drm_device *dev = dev_priv->dev; |
1263 | int pp_reg; | |
ea0760cf JB |
1264 | u32 val; |
1265 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1266 | bool locked = true; |
ea0760cf | 1267 | |
bedd4dba JN |
1268 | if (WARN_ON(HAS_DDI(dev))) |
1269 | return; | |
1270 | ||
1271 | if (HAS_PCH_SPLIT(dev)) { | |
1272 | u32 port_sel; | |
1273 | ||
ea0760cf | 1274 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1275 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1276 | ||
1277 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1278 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1279 | panel_pipe = PIPE_B; | |
1280 | /* XXX: else fix for eDP */ | |
1281 | } else if (IS_VALLEYVIEW(dev)) { | |
1282 | /* presumably write lock depends on pipe, not port select */ | |
1283 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1284 | panel_pipe = pipe; | |
ea0760cf JB |
1285 | } else { |
1286 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1287 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1288 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1289 | } |
1290 | ||
1291 | val = I915_READ(pp_reg); | |
1292 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1293 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1294 | locked = false; |
1295 | ||
e2c719b7 | 1296 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1297 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1298 | pipe_name(pipe)); |
ea0760cf JB |
1299 | } |
1300 | ||
93ce0ba6 JN |
1301 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1302 | enum pipe pipe, bool state) | |
1303 | { | |
1304 | struct drm_device *dev = dev_priv->dev; | |
1305 | bool cur_state; | |
1306 | ||
d9d82081 | 1307 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1308 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1309 | else |
5efb3e28 | 1310 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1311 | |
e2c719b7 | 1312 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1313 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1314 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1315 | } | |
1316 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1317 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1318 | ||
b840d907 JB |
1319 | void assert_pipe(struct drm_i915_private *dev_priv, |
1320 | enum pipe pipe, bool state) | |
b24e7179 JB |
1321 | { |
1322 | int reg; | |
1323 | u32 val; | |
63d7bbe9 | 1324 | bool cur_state; |
702e7a56 PZ |
1325 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1326 | pipe); | |
b24e7179 | 1327 | |
b6b5d049 VS |
1328 | /* if we need the pipe quirk it must be always on */ |
1329 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1330 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1331 | state = true; |
1332 | ||
f458ebbc | 1333 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1334 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1335 | cur_state = false; |
1336 | } else { | |
1337 | reg = PIPECONF(cpu_transcoder); | |
1338 | val = I915_READ(reg); | |
1339 | cur_state = !!(val & PIPECONF_ENABLE); | |
1340 | } | |
1341 | ||
e2c719b7 | 1342 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1343 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1344 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1345 | } |
1346 | ||
931872fc CW |
1347 | static void assert_plane(struct drm_i915_private *dev_priv, |
1348 | enum plane plane, bool state) | |
b24e7179 JB |
1349 | { |
1350 | int reg; | |
1351 | u32 val; | |
931872fc | 1352 | bool cur_state; |
b24e7179 JB |
1353 | |
1354 | reg = DSPCNTR(plane); | |
1355 | val = I915_READ(reg); | |
931872fc | 1356 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1357 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1358 | "plane %c assertion failure (expected %s, current %s)\n", |
1359 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1360 | } |
1361 | ||
931872fc CW |
1362 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1363 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1364 | ||
b24e7179 JB |
1365 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1366 | enum pipe pipe) | |
1367 | { | |
653e1026 | 1368 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1369 | int reg, i; |
1370 | u32 val; | |
1371 | int cur_pipe; | |
1372 | ||
653e1026 VS |
1373 | /* Primary planes are fixed to pipes on gen4+ */ |
1374 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1375 | reg = DSPCNTR(pipe); |
1376 | val = I915_READ(reg); | |
e2c719b7 | 1377 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1378 | "plane %c assertion failure, should be disabled but not\n", |
1379 | plane_name(pipe)); | |
19ec1358 | 1380 | return; |
28c05794 | 1381 | } |
19ec1358 | 1382 | |
b24e7179 | 1383 | /* Need to check both planes against the pipe */ |
055e393f | 1384 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1385 | reg = DSPCNTR(i); |
1386 | val = I915_READ(reg); | |
1387 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1388 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1389 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1390 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1391 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1392 | } |
1393 | } | |
1394 | ||
19332d7a JB |
1395 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1396 | enum pipe pipe) | |
1397 | { | |
20674eef | 1398 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1399 | int reg, sprite; |
19332d7a JB |
1400 | u32 val; |
1401 | ||
7feb8b88 | 1402 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1403 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1404 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1405 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1406 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1407 | sprite, pipe_name(pipe)); | |
1408 | } | |
1409 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1410 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1411 | reg = SPCNTR(pipe, sprite); |
20674eef | 1412 | val = I915_READ(reg); |
e2c719b7 | 1413 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1414 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1415 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1416 | } |
1417 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1418 | reg = SPRCTL(pipe); | |
19332d7a | 1419 | val = I915_READ(reg); |
e2c719b7 | 1420 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1421 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1422 | plane_name(pipe), pipe_name(pipe)); |
1423 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1424 | reg = DVSCNTR(pipe); | |
19332d7a | 1425 | val = I915_READ(reg); |
e2c719b7 | 1426 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1427 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1428 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1429 | } |
1430 | } | |
1431 | ||
08c71e5e VS |
1432 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1433 | { | |
e2c719b7 | 1434 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1435 | drm_crtc_vblank_put(crtc); |
1436 | } | |
1437 | ||
89eff4be | 1438 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1439 | { |
1440 | u32 val; | |
1441 | bool enabled; | |
1442 | ||
e2c719b7 | 1443 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1444 | |
92f2584a JB |
1445 | val = I915_READ(PCH_DREF_CONTROL); |
1446 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1447 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1448 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1449 | } |
1450 | ||
ab9412ba DV |
1451 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1452 | enum pipe pipe) | |
92f2584a JB |
1453 | { |
1454 | int reg; | |
1455 | u32 val; | |
1456 | bool enabled; | |
1457 | ||
ab9412ba | 1458 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1459 | val = I915_READ(reg); |
1460 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1461 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1462 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1463 | pipe_name(pipe)); | |
92f2584a JB |
1464 | } |
1465 | ||
4e634389 KP |
1466 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1467 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1468 | { |
1469 | if ((val & DP_PORT_EN) == 0) | |
1470 | return false; | |
1471 | ||
1472 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1473 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1474 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1475 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1476 | return false; | |
44f37d1f CML |
1477 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1478 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1479 | return false; | |
f0575e92 KP |
1480 | } else { |
1481 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1482 | return false; | |
1483 | } | |
1484 | return true; | |
1485 | } | |
1486 | ||
1519b995 KP |
1487 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1488 | enum pipe pipe, u32 val) | |
1489 | { | |
dc0fa718 | 1490 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1491 | return false; |
1492 | ||
1493 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1494 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1495 | return false; |
44f37d1f CML |
1496 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1497 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1498 | return false; | |
1519b995 | 1499 | } else { |
dc0fa718 | 1500 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1501 | return false; |
1502 | } | |
1503 | return true; | |
1504 | } | |
1505 | ||
1506 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1507 | enum pipe pipe, u32 val) | |
1508 | { | |
1509 | if ((val & LVDS_PORT_EN) == 0) | |
1510 | return false; | |
1511 | ||
1512 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1513 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1514 | return false; | |
1515 | } else { | |
1516 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1517 | return false; | |
1518 | } | |
1519 | return true; | |
1520 | } | |
1521 | ||
1522 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1523 | enum pipe pipe, u32 val) | |
1524 | { | |
1525 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1526 | return false; | |
1527 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1528 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1529 | return false; | |
1530 | } else { | |
1531 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1532 | return false; | |
1533 | } | |
1534 | return true; | |
1535 | } | |
1536 | ||
291906f1 | 1537 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1538 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1539 | { |
47a05eca | 1540 | u32 val = I915_READ(reg); |
e2c719b7 | 1541 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1542 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1543 | reg, pipe_name(pipe)); |
de9a35ab | 1544 | |
e2c719b7 | 1545 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1546 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1547 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1548 | } |
1549 | ||
1550 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1551 | enum pipe pipe, int reg) | |
1552 | { | |
47a05eca | 1553 | u32 val = I915_READ(reg); |
e2c719b7 | 1554 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1555 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1556 | reg, pipe_name(pipe)); |
de9a35ab | 1557 | |
e2c719b7 | 1558 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1559 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1560 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1561 | } |
1562 | ||
1563 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1564 | enum pipe pipe) | |
1565 | { | |
1566 | int reg; | |
1567 | u32 val; | |
291906f1 | 1568 | |
f0575e92 KP |
1569 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1570 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1571 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1572 | |
1573 | reg = PCH_ADPA; | |
1574 | val = I915_READ(reg); | |
e2c719b7 | 1575 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1576 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1577 | pipe_name(pipe)); |
291906f1 JB |
1578 | |
1579 | reg = PCH_LVDS; | |
1580 | val = I915_READ(reg); | |
e2c719b7 | 1581 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1582 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1583 | pipe_name(pipe)); |
291906f1 | 1584 | |
e2debe91 PZ |
1585 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1586 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1587 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1588 | } |
1589 | ||
40e9cf64 JB |
1590 | static void intel_init_dpio(struct drm_device *dev) |
1591 | { | |
1592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1593 | ||
1594 | if (!IS_VALLEYVIEW(dev)) | |
1595 | return; | |
1596 | ||
a09caddd CML |
1597 | /* |
1598 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1599 | * CHV x1 PHY (DP/HDMI D) | |
1600 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1601 | */ | |
1602 | if (IS_CHERRYVIEW(dev)) { | |
1603 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1604 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1605 | } else { | |
1606 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1607 | } | |
5382f5f3 JB |
1608 | } |
1609 | ||
d288f65f | 1610 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1611 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1612 | { |
426115cf DV |
1613 | struct drm_device *dev = crtc->base.dev; |
1614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1615 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1616 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1617 | |
426115cf | 1618 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1619 | |
1620 | /* No really, not for ILK+ */ | |
1621 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1622 | ||
1623 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1624 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1625 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1626 | |
426115cf DV |
1627 | I915_WRITE(reg, dpll); |
1628 | POSTING_READ(reg); | |
1629 | udelay(150); | |
1630 | ||
1631 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1632 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1633 | ||
d288f65f | 1634 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1635 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1636 | |
1637 | /* We do this three times for luck */ | |
426115cf | 1638 | I915_WRITE(reg, dpll); |
87442f73 DV |
1639 | POSTING_READ(reg); |
1640 | udelay(150); /* wait for warmup */ | |
426115cf | 1641 | I915_WRITE(reg, dpll); |
87442f73 DV |
1642 | POSTING_READ(reg); |
1643 | udelay(150); /* wait for warmup */ | |
426115cf | 1644 | I915_WRITE(reg, dpll); |
87442f73 DV |
1645 | POSTING_READ(reg); |
1646 | udelay(150); /* wait for warmup */ | |
1647 | } | |
1648 | ||
d288f65f | 1649 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1650 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1651 | { |
1652 | struct drm_device *dev = crtc->base.dev; | |
1653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1654 | int pipe = crtc->pipe; | |
1655 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1656 | u32 tmp; |
1657 | ||
1658 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1659 | ||
1660 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1661 | ||
1662 | mutex_lock(&dev_priv->dpio_lock); | |
1663 | ||
1664 | /* Enable back the 10bit clock to display controller */ | |
1665 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1666 | tmp |= DPIO_DCLKP_EN; | |
1667 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1668 | ||
1669 | /* | |
1670 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1671 | */ | |
1672 | udelay(1); | |
1673 | ||
1674 | /* Enable PLL */ | |
d288f65f | 1675 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1676 | |
1677 | /* Check PLL is locked */ | |
a11b0703 | 1678 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1679 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1680 | ||
a11b0703 | 1681 | /* not sure when this should be written */ |
d288f65f | 1682 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1683 | POSTING_READ(DPLL_MD(pipe)); |
1684 | ||
9d556c99 CML |
1685 | mutex_unlock(&dev_priv->dpio_lock); |
1686 | } | |
1687 | ||
1c4e0274 VS |
1688 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1689 | { | |
1690 | struct intel_crtc *crtc; | |
1691 | int count = 0; | |
1692 | ||
1693 | for_each_intel_crtc(dev, crtc) | |
1694 | count += crtc->active && | |
409ee761 | 1695 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1696 | |
1697 | return count; | |
1698 | } | |
1699 | ||
66e3d5c0 | 1700 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1701 | { |
66e3d5c0 DV |
1702 | struct drm_device *dev = crtc->base.dev; |
1703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1704 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1705 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1706 | |
66e3d5c0 | 1707 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1708 | |
63d7bbe9 | 1709 | /* No really, not for ILK+ */ |
3d13ef2e | 1710 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1711 | |
1712 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1713 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1714 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1715 | |
1c4e0274 VS |
1716 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1717 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1718 | /* | |
1719 | * It appears to be important that we don't enable this | |
1720 | * for the current pipe before otherwise configuring the | |
1721 | * PLL. No idea how this should be handled if multiple | |
1722 | * DVO outputs are enabled simultaneosly. | |
1723 | */ | |
1724 | dpll |= DPLL_DVO_2X_MODE; | |
1725 | I915_WRITE(DPLL(!crtc->pipe), | |
1726 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1727 | } | |
66e3d5c0 DV |
1728 | |
1729 | /* Wait for the clocks to stabilize. */ | |
1730 | POSTING_READ(reg); | |
1731 | udelay(150); | |
1732 | ||
1733 | if (INTEL_INFO(dev)->gen >= 4) { | |
1734 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1735 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1736 | } else { |
1737 | /* The pixel multiplier can only be updated once the | |
1738 | * DPLL is enabled and the clocks are stable. | |
1739 | * | |
1740 | * So write it again. | |
1741 | */ | |
1742 | I915_WRITE(reg, dpll); | |
1743 | } | |
63d7bbe9 JB |
1744 | |
1745 | /* We do this three times for luck */ | |
66e3d5c0 | 1746 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1747 | POSTING_READ(reg); |
1748 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1749 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1750 | POSTING_READ(reg); |
1751 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1752 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1753 | POSTING_READ(reg); |
1754 | udelay(150); /* wait for warmup */ | |
1755 | } | |
1756 | ||
1757 | /** | |
50b44a44 | 1758 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1759 | * @dev_priv: i915 private structure |
1760 | * @pipe: pipe PLL to disable | |
1761 | * | |
1762 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1763 | * | |
1764 | * Note! This is for pre-ILK only. | |
1765 | */ | |
1c4e0274 | 1766 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1767 | { |
1c4e0274 VS |
1768 | struct drm_device *dev = crtc->base.dev; |
1769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1770 | enum pipe pipe = crtc->pipe; | |
1771 | ||
1772 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1773 | if (IS_I830(dev) && | |
409ee761 | 1774 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1775 | intel_num_dvo_pipes(dev) == 1) { |
1776 | I915_WRITE(DPLL(PIPE_B), | |
1777 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1778 | I915_WRITE(DPLL(PIPE_A), | |
1779 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1780 | } | |
1781 | ||
b6b5d049 VS |
1782 | /* Don't disable pipe or pipe PLLs if needed */ |
1783 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1784 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1785 | return; |
1786 | ||
1787 | /* Make sure the pipe isn't still relying on us */ | |
1788 | assert_pipe_disabled(dev_priv, pipe); | |
1789 | ||
50b44a44 DV |
1790 | I915_WRITE(DPLL(pipe), 0); |
1791 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1792 | } |
1793 | ||
f6071166 JB |
1794 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1795 | { | |
1796 | u32 val = 0; | |
1797 | ||
1798 | /* Make sure the pipe isn't still relying on us */ | |
1799 | assert_pipe_disabled(dev_priv, pipe); | |
1800 | ||
e5cbfbfb ID |
1801 | /* |
1802 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1803 | * The latter is needed for VGA hotplug / manual detection. | |
1804 | */ | |
f6071166 | 1805 | if (pipe == PIPE_B) |
e5cbfbfb | 1806 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1807 | I915_WRITE(DPLL(pipe), val); |
1808 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1809 | |
1810 | } | |
1811 | ||
1812 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1813 | { | |
d752048d | 1814 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1815 | u32 val; |
1816 | ||
a11b0703 VS |
1817 | /* Make sure the pipe isn't still relying on us */ |
1818 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1819 | |
a11b0703 | 1820 | /* Set PLL en = 0 */ |
d17ec4ce | 1821 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1822 | if (pipe != PIPE_A) |
1823 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1824 | I915_WRITE(DPLL(pipe), val); | |
1825 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1826 | |
1827 | mutex_lock(&dev_priv->dpio_lock); | |
1828 | ||
1829 | /* Disable 10bit clock to display controller */ | |
1830 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1831 | val &= ~DPIO_DCLKP_EN; | |
1832 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1833 | ||
61407f6d VS |
1834 | /* disable left/right clock distribution */ |
1835 | if (pipe != PIPE_B) { | |
1836 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1837 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1838 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1839 | } else { | |
1840 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1841 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1842 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1843 | } | |
1844 | ||
d752048d | 1845 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1846 | } |
1847 | ||
e4607fcf CML |
1848 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1849 | struct intel_digital_port *dport) | |
89b667f8 JB |
1850 | { |
1851 | u32 port_mask; | |
00fc31b7 | 1852 | int dpll_reg; |
89b667f8 | 1853 | |
e4607fcf CML |
1854 | switch (dport->port) { |
1855 | case PORT_B: | |
89b667f8 | 1856 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1857 | dpll_reg = DPLL(0); |
e4607fcf CML |
1858 | break; |
1859 | case PORT_C: | |
89b667f8 | 1860 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1861 | dpll_reg = DPLL(0); |
1862 | break; | |
1863 | case PORT_D: | |
1864 | port_mask = DPLL_PORTD_READY_MASK; | |
1865 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1866 | break; |
1867 | default: | |
1868 | BUG(); | |
1869 | } | |
89b667f8 | 1870 | |
00fc31b7 | 1871 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1872 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1873 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1874 | } |
1875 | ||
b14b1055 DV |
1876 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1877 | { | |
1878 | struct drm_device *dev = crtc->base.dev; | |
1879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1880 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1881 | ||
be19f0ff CW |
1882 | if (WARN_ON(pll == NULL)) |
1883 | return; | |
1884 | ||
3e369b76 | 1885 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1886 | if (pll->active == 0) { |
1887 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1888 | WARN_ON(pll->on); | |
1889 | assert_shared_dpll_disabled(dev_priv, pll); | |
1890 | ||
1891 | pll->mode_set(dev_priv, pll); | |
1892 | } | |
1893 | } | |
1894 | ||
92f2584a | 1895 | /** |
85b3894f | 1896 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1897 | * @dev_priv: i915 private structure |
1898 | * @pipe: pipe PLL to enable | |
1899 | * | |
1900 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1901 | * drives the transcoder clock. | |
1902 | */ | |
85b3894f | 1903 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1904 | { |
3d13ef2e DL |
1905 | struct drm_device *dev = crtc->base.dev; |
1906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1907 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1908 | |
87a875bb | 1909 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1910 | return; |
1911 | ||
3e369b76 | 1912 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1913 | return; |
ee7b9f93 | 1914 | |
74dd6928 | 1915 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1916 | pll->name, pll->active, pll->on, |
e2b78267 | 1917 | crtc->base.base.id); |
92f2584a | 1918 | |
cdbd2316 DV |
1919 | if (pll->active++) { |
1920 | WARN_ON(!pll->on); | |
e9d6944e | 1921 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1922 | return; |
1923 | } | |
f4a091c7 | 1924 | WARN_ON(pll->on); |
ee7b9f93 | 1925 | |
bd2bb1b9 PZ |
1926 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1927 | ||
46edb027 | 1928 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1929 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1930 | pll->on = true; |
92f2584a JB |
1931 | } |
1932 | ||
f6daaec2 | 1933 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1934 | { |
3d13ef2e DL |
1935 | struct drm_device *dev = crtc->base.dev; |
1936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1937 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1938 | |
92f2584a | 1939 | /* PCH only available on ILK+ */ |
3d13ef2e | 1940 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1941 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1942 | return; |
92f2584a | 1943 | |
3e369b76 | 1944 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1945 | return; |
7a419866 | 1946 | |
46edb027 DV |
1947 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1948 | pll->name, pll->active, pll->on, | |
e2b78267 | 1949 | crtc->base.base.id); |
7a419866 | 1950 | |
48da64a8 | 1951 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1952 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1953 | return; |
1954 | } | |
1955 | ||
e9d6944e | 1956 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1957 | WARN_ON(!pll->on); |
cdbd2316 | 1958 | if (--pll->active) |
7a419866 | 1959 | return; |
ee7b9f93 | 1960 | |
46edb027 | 1961 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1962 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1963 | pll->on = false; |
bd2bb1b9 PZ |
1964 | |
1965 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1966 | } |
1967 | ||
b8a4f404 PZ |
1968 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1969 | enum pipe pipe) | |
040484af | 1970 | { |
23670b32 | 1971 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1972 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1974 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1975 | |
1976 | /* PCH only available on ILK+ */ | |
55522f37 | 1977 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1978 | |
1979 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1980 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1981 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1982 | |
1983 | /* FDI must be feeding us bits for PCH ports */ | |
1984 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1985 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1986 | ||
23670b32 DV |
1987 | if (HAS_PCH_CPT(dev)) { |
1988 | /* Workaround: Set the timing override bit before enabling the | |
1989 | * pch transcoder. */ | |
1990 | reg = TRANS_CHICKEN2(pipe); | |
1991 | val = I915_READ(reg); | |
1992 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1993 | I915_WRITE(reg, val); | |
59c859d6 | 1994 | } |
23670b32 | 1995 | |
ab9412ba | 1996 | reg = PCH_TRANSCONF(pipe); |
040484af | 1997 | val = I915_READ(reg); |
5f7f726d | 1998 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1999 | |
2000 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2001 | /* | |
2002 | * make the BPC in transcoder be consistent with | |
2003 | * that in pipeconf reg. | |
2004 | */ | |
dfd07d72 DV |
2005 | val &= ~PIPECONF_BPC_MASK; |
2006 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2007 | } |
5f7f726d PZ |
2008 | |
2009 | val &= ~TRANS_INTERLACE_MASK; | |
2010 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2011 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2012 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2013 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2014 | else | |
2015 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2016 | else |
2017 | val |= TRANS_PROGRESSIVE; | |
2018 | ||
040484af JB |
2019 | I915_WRITE(reg, val | TRANS_ENABLE); |
2020 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2021 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2022 | } |
2023 | ||
8fb033d7 | 2024 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2025 | enum transcoder cpu_transcoder) |
040484af | 2026 | { |
8fb033d7 | 2027 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2028 | |
2029 | /* PCH only available on ILK+ */ | |
55522f37 | 2030 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2031 | |
8fb033d7 | 2032 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2033 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2034 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2035 | |
223a6fdf PZ |
2036 | /* Workaround: set timing override bit. */ |
2037 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2038 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2039 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2040 | ||
25f3ef11 | 2041 | val = TRANS_ENABLE; |
937bb610 | 2042 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2043 | |
9a76b1c6 PZ |
2044 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2045 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2046 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2047 | else |
2048 | val |= TRANS_PROGRESSIVE; | |
2049 | ||
ab9412ba DV |
2050 | I915_WRITE(LPT_TRANSCONF, val); |
2051 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2052 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2053 | } |
2054 | ||
b8a4f404 PZ |
2055 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2056 | enum pipe pipe) | |
040484af | 2057 | { |
23670b32 DV |
2058 | struct drm_device *dev = dev_priv->dev; |
2059 | uint32_t reg, val; | |
040484af JB |
2060 | |
2061 | /* FDI relies on the transcoder */ | |
2062 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2063 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2064 | ||
291906f1 JB |
2065 | /* Ports must be off as well */ |
2066 | assert_pch_ports_disabled(dev_priv, pipe); | |
2067 | ||
ab9412ba | 2068 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2069 | val = I915_READ(reg); |
2070 | val &= ~TRANS_ENABLE; | |
2071 | I915_WRITE(reg, val); | |
2072 | /* wait for PCH transcoder off, transcoder state */ | |
2073 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2074 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2075 | |
2076 | if (!HAS_PCH_IBX(dev)) { | |
2077 | /* Workaround: Clear the timing override chicken bit again. */ | |
2078 | reg = TRANS_CHICKEN2(pipe); | |
2079 | val = I915_READ(reg); | |
2080 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2081 | I915_WRITE(reg, val); | |
2082 | } | |
040484af JB |
2083 | } |
2084 | ||
ab4d966c | 2085 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2086 | { |
8fb033d7 PZ |
2087 | u32 val; |
2088 | ||
ab9412ba | 2089 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2090 | val &= ~TRANS_ENABLE; |
ab9412ba | 2091 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2092 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2093 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2094 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2095 | |
2096 | /* Workaround: clear timing override bit. */ | |
2097 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2098 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2099 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2100 | } |
2101 | ||
b24e7179 | 2102 | /** |
309cfea8 | 2103 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2104 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2105 | * |
0372264a | 2106 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2107 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2108 | */ |
e1fdc473 | 2109 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2110 | { |
0372264a PZ |
2111 | struct drm_device *dev = crtc->base.dev; |
2112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2113 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2114 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2115 | pipe); | |
1a240d4d | 2116 | enum pipe pch_transcoder; |
b24e7179 JB |
2117 | int reg; |
2118 | u32 val; | |
2119 | ||
58c6eaa2 | 2120 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2121 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2122 | assert_sprites_disabled(dev_priv, pipe); |
2123 | ||
681e5811 | 2124 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2125 | pch_transcoder = TRANSCODER_A; |
2126 | else | |
2127 | pch_transcoder = pipe; | |
2128 | ||
b24e7179 JB |
2129 | /* |
2130 | * A pipe without a PLL won't actually be able to drive bits from | |
2131 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2132 | * need the check. | |
2133 | */ | |
2134 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2135 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2136 | assert_dsi_pll_enabled(dev_priv); |
2137 | else | |
2138 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2139 | else { |
6e3c9717 | 2140 | if (crtc->config->has_pch_encoder) { |
040484af | 2141 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2142 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2143 | assert_fdi_tx_pll_enabled(dev_priv, |
2144 | (enum pipe) cpu_transcoder); | |
040484af JB |
2145 | } |
2146 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2147 | } | |
b24e7179 | 2148 | |
702e7a56 | 2149 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2150 | val = I915_READ(reg); |
7ad25d48 | 2151 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2152 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2153 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2154 | return; |
7ad25d48 | 2155 | } |
00d70b15 CW |
2156 | |
2157 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2158 | POSTING_READ(reg); |
b24e7179 JB |
2159 | } |
2160 | ||
2161 | /** | |
309cfea8 | 2162 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2163 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2164 | * |
575f7ab7 VS |
2165 | * Disable the pipe of @crtc, making sure that various hardware |
2166 | * specific requirements are met, if applicable, e.g. plane | |
2167 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2168 | * |
2169 | * Will wait until the pipe has shut down before returning. | |
2170 | */ | |
575f7ab7 | 2171 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2172 | { |
575f7ab7 | 2173 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2174 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2175 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2176 | int reg; |
2177 | u32 val; | |
2178 | ||
2179 | /* | |
2180 | * Make sure planes won't keep trying to pump pixels to us, | |
2181 | * or we might hang the display. | |
2182 | */ | |
2183 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2184 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2185 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2186 | |
702e7a56 | 2187 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2188 | val = I915_READ(reg); |
00d70b15 CW |
2189 | if ((val & PIPECONF_ENABLE) == 0) |
2190 | return; | |
2191 | ||
67adc644 VS |
2192 | /* |
2193 | * Double wide has implications for planes | |
2194 | * so best keep it disabled when not needed. | |
2195 | */ | |
6e3c9717 | 2196 | if (crtc->config->double_wide) |
67adc644 VS |
2197 | val &= ~PIPECONF_DOUBLE_WIDE; |
2198 | ||
2199 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2200 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2201 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2202 | val &= ~PIPECONF_ENABLE; |
2203 | ||
2204 | I915_WRITE(reg, val); | |
2205 | if ((val & PIPECONF_ENABLE) == 0) | |
2206 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2207 | } |
2208 | ||
d74362c9 KP |
2209 | /* |
2210 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2211 | * trigger in order to latch. The display address reg provides this. | |
2212 | */ | |
1dba99f4 VS |
2213 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2214 | enum plane plane) | |
d74362c9 | 2215 | { |
3d13ef2e DL |
2216 | struct drm_device *dev = dev_priv->dev; |
2217 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2218 | |
2219 | I915_WRITE(reg, I915_READ(reg)); | |
2220 | POSTING_READ(reg); | |
d74362c9 KP |
2221 | } |
2222 | ||
b24e7179 | 2223 | /** |
262ca2b0 | 2224 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2225 | * @plane: plane to be enabled |
2226 | * @crtc: crtc for the plane | |
b24e7179 | 2227 | * |
fdd508a6 | 2228 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2229 | */ |
fdd508a6 VS |
2230 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2231 | struct drm_crtc *crtc) | |
b24e7179 | 2232 | { |
fdd508a6 VS |
2233 | struct drm_device *dev = plane->dev; |
2234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2236 | |
2237 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2238 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2239 | |
98ec7739 VS |
2240 | if (intel_crtc->primary_enabled) |
2241 | return; | |
0037f71c | 2242 | |
4c445e0e | 2243 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2244 | |
fdd508a6 VS |
2245 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2246 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2247 | |
2248 | /* | |
2249 | * BDW signals flip done immediately if the plane | |
2250 | * is disabled, even if the plane enable is already | |
2251 | * armed to occur at the next vblank :( | |
2252 | */ | |
2253 | if (IS_BROADWELL(dev)) | |
2254 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2255 | } |
2256 | ||
b24e7179 | 2257 | /** |
262ca2b0 | 2258 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2259 | * @plane: plane to be disabled |
2260 | * @crtc: crtc for the plane | |
b24e7179 | 2261 | * |
fdd508a6 | 2262 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2263 | */ |
fdd508a6 VS |
2264 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2265 | struct drm_crtc *crtc) | |
b24e7179 | 2266 | { |
fdd508a6 VS |
2267 | struct drm_device *dev = plane->dev; |
2268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2270 | ||
32b7eeec MR |
2271 | if (WARN_ON(!intel_crtc->active)) |
2272 | return; | |
b24e7179 | 2273 | |
98ec7739 VS |
2274 | if (!intel_crtc->primary_enabled) |
2275 | return; | |
0037f71c | 2276 | |
4c445e0e | 2277 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2278 | |
fdd508a6 VS |
2279 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2280 | crtc->x, crtc->y); | |
b24e7179 JB |
2281 | } |
2282 | ||
693db184 CW |
2283 | static bool need_vtd_wa(struct drm_device *dev) |
2284 | { | |
2285 | #ifdef CONFIG_INTEL_IOMMU | |
2286 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2287 | return true; | |
2288 | #endif | |
2289 | return false; | |
2290 | } | |
2291 | ||
50470bb0 | 2292 | unsigned int |
6761dd31 TU |
2293 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2294 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2295 | { |
6761dd31 TU |
2296 | unsigned int tile_height; |
2297 | uint32_t pixel_bytes; | |
a57ce0b2 | 2298 | |
b5d0e9bf DL |
2299 | switch (fb_format_modifier) { |
2300 | case DRM_FORMAT_MOD_NONE: | |
2301 | tile_height = 1; | |
2302 | break; | |
2303 | case I915_FORMAT_MOD_X_TILED: | |
2304 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2305 | break; | |
2306 | case I915_FORMAT_MOD_Y_TILED: | |
2307 | tile_height = 32; | |
2308 | break; | |
2309 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2310 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2311 | switch (pixel_bytes) { | |
b5d0e9bf | 2312 | default: |
6761dd31 | 2313 | case 1: |
b5d0e9bf DL |
2314 | tile_height = 64; |
2315 | break; | |
6761dd31 TU |
2316 | case 2: |
2317 | case 4: | |
b5d0e9bf DL |
2318 | tile_height = 32; |
2319 | break; | |
6761dd31 | 2320 | case 8: |
b5d0e9bf DL |
2321 | tile_height = 16; |
2322 | break; | |
6761dd31 | 2323 | case 16: |
b5d0e9bf DL |
2324 | WARN_ONCE(1, |
2325 | "128-bit pixels are not supported for display!"); | |
2326 | tile_height = 16; | |
2327 | break; | |
2328 | } | |
2329 | break; | |
2330 | default: | |
2331 | MISSING_CASE(fb_format_modifier); | |
2332 | tile_height = 1; | |
2333 | break; | |
2334 | } | |
091df6cb | 2335 | |
6761dd31 TU |
2336 | return tile_height; |
2337 | } | |
2338 | ||
2339 | unsigned int | |
2340 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2341 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2342 | { | |
2343 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2344 | fb_format_modifier)); | |
a57ce0b2 JB |
2345 | } |
2346 | ||
f64b98cd TU |
2347 | static int |
2348 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2349 | const struct drm_plane_state *plane_state) | |
2350 | { | |
50470bb0 | 2351 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2352 | |
f64b98cd TU |
2353 | *view = i915_ggtt_view_normal; |
2354 | ||
50470bb0 TU |
2355 | if (!plane_state) |
2356 | return 0; | |
2357 | ||
121920fa | 2358 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2359 | return 0; |
2360 | ||
9abc4648 | 2361 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2362 | |
2363 | info->height = fb->height; | |
2364 | info->pixel_format = fb->pixel_format; | |
2365 | info->pitch = fb->pitches[0]; | |
2366 | info->fb_modifier = fb->modifier[0]; | |
2367 | ||
f64b98cd TU |
2368 | return 0; |
2369 | } | |
2370 | ||
127bd2ac | 2371 | int |
850c4cdc TU |
2372 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2373 | struct drm_framebuffer *fb, | |
82bc3b2d | 2374 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2375 | struct intel_engine_cs *pipelined) |
6b95a207 | 2376 | { |
850c4cdc | 2377 | struct drm_device *dev = fb->dev; |
ce453d81 | 2378 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2379 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2380 | struct i915_ggtt_view view; |
6b95a207 KH |
2381 | u32 alignment; |
2382 | int ret; | |
2383 | ||
ebcdd39e MR |
2384 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2385 | ||
7b911adc TU |
2386 | switch (fb->modifier[0]) { |
2387 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2388 | if (INTEL_INFO(dev)->gen >= 9) |
2389 | alignment = 256 * 1024; | |
2390 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2391 | alignment = 128 * 1024; |
a6c45cf0 | 2392 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2393 | alignment = 4 * 1024; |
2394 | else | |
2395 | alignment = 64 * 1024; | |
6b95a207 | 2396 | break; |
7b911adc | 2397 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2398 | if (INTEL_INFO(dev)->gen >= 9) |
2399 | alignment = 256 * 1024; | |
2400 | else { | |
2401 | /* pin() will align the object as required by fence */ | |
2402 | alignment = 0; | |
2403 | } | |
6b95a207 | 2404 | break; |
7b911adc | 2405 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2406 | case I915_FORMAT_MOD_Yf_TILED: |
2407 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2408 | "Y tiling bo slipped through, driver bug!\n")) | |
2409 | return -EINVAL; | |
2410 | alignment = 1 * 1024 * 1024; | |
2411 | break; | |
6b95a207 | 2412 | default: |
7b911adc TU |
2413 | MISSING_CASE(fb->modifier[0]); |
2414 | return -EINVAL; | |
6b95a207 KH |
2415 | } |
2416 | ||
f64b98cd TU |
2417 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2418 | if (ret) | |
2419 | return ret; | |
2420 | ||
693db184 CW |
2421 | /* Note that the w/a also requires 64 PTE of padding following the |
2422 | * bo. We currently fill all unused PTE with the shadow page and so | |
2423 | * we should always have valid PTE following the scanout preventing | |
2424 | * the VT-d warning. | |
2425 | */ | |
2426 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2427 | alignment = 256 * 1024; | |
2428 | ||
d6dd6843 PZ |
2429 | /* |
2430 | * Global gtt pte registers are special registers which actually forward | |
2431 | * writes to a chunk of system memory. Which means that there is no risk | |
2432 | * that the register values disappear as soon as we call | |
2433 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2434 | * pin/unpin/fence and not more. | |
2435 | */ | |
2436 | intel_runtime_pm_get(dev_priv); | |
2437 | ||
ce453d81 | 2438 | dev_priv->mm.interruptible = false; |
e6617330 | 2439 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2440 | &view); |
48b956c5 | 2441 | if (ret) |
ce453d81 | 2442 | goto err_interruptible; |
6b95a207 KH |
2443 | |
2444 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2445 | * fence, whereas 965+ only requires a fence if using | |
2446 | * framebuffer compression. For simplicity, we always install | |
2447 | * a fence as the cost is not that onerous. | |
2448 | */ | |
06d98131 | 2449 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2450 | if (ret) |
2451 | goto err_unpin; | |
1690e1eb | 2452 | |
9a5a53b3 | 2453 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2454 | |
ce453d81 | 2455 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2456 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2457 | return 0; |
48b956c5 CW |
2458 | |
2459 | err_unpin: | |
f64b98cd | 2460 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2461 | err_interruptible: |
2462 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2463 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2464 | return ret; |
6b95a207 KH |
2465 | } |
2466 | ||
82bc3b2d TU |
2467 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2468 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2469 | { |
82bc3b2d | 2470 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2471 | struct i915_ggtt_view view; |
2472 | int ret; | |
82bc3b2d | 2473 | |
ebcdd39e MR |
2474 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2475 | ||
f64b98cd TU |
2476 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2477 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2478 | ||
1690e1eb | 2479 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2480 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2481 | } |
2482 | ||
c2c75131 DV |
2483 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2484 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2485 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2486 | unsigned int tiling_mode, | |
2487 | unsigned int cpp, | |
2488 | unsigned int pitch) | |
c2c75131 | 2489 | { |
bc752862 CW |
2490 | if (tiling_mode != I915_TILING_NONE) { |
2491 | unsigned int tile_rows, tiles; | |
c2c75131 | 2492 | |
bc752862 CW |
2493 | tile_rows = *y / 8; |
2494 | *y %= 8; | |
c2c75131 | 2495 | |
bc752862 CW |
2496 | tiles = *x / (512/cpp); |
2497 | *x %= 512/cpp; | |
2498 | ||
2499 | return tile_rows * pitch * 8 + tiles * 4096; | |
2500 | } else { | |
2501 | unsigned int offset; | |
2502 | ||
2503 | offset = *y * pitch + *x * cpp; | |
2504 | *y = 0; | |
2505 | *x = (offset & 4095) / cpp; | |
2506 | return offset & -4096; | |
2507 | } | |
c2c75131 DV |
2508 | } |
2509 | ||
b35d63fa | 2510 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2511 | { |
2512 | switch (format) { | |
2513 | case DISPPLANE_8BPP: | |
2514 | return DRM_FORMAT_C8; | |
2515 | case DISPPLANE_BGRX555: | |
2516 | return DRM_FORMAT_XRGB1555; | |
2517 | case DISPPLANE_BGRX565: | |
2518 | return DRM_FORMAT_RGB565; | |
2519 | default: | |
2520 | case DISPPLANE_BGRX888: | |
2521 | return DRM_FORMAT_XRGB8888; | |
2522 | case DISPPLANE_RGBX888: | |
2523 | return DRM_FORMAT_XBGR8888; | |
2524 | case DISPPLANE_BGRX101010: | |
2525 | return DRM_FORMAT_XRGB2101010; | |
2526 | case DISPPLANE_RGBX101010: | |
2527 | return DRM_FORMAT_XBGR2101010; | |
2528 | } | |
2529 | } | |
2530 | ||
bc8d7dff DL |
2531 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2532 | { | |
2533 | switch (format) { | |
2534 | case PLANE_CTL_FORMAT_RGB_565: | |
2535 | return DRM_FORMAT_RGB565; | |
2536 | default: | |
2537 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2538 | if (rgb_order) { | |
2539 | if (alpha) | |
2540 | return DRM_FORMAT_ABGR8888; | |
2541 | else | |
2542 | return DRM_FORMAT_XBGR8888; | |
2543 | } else { | |
2544 | if (alpha) | |
2545 | return DRM_FORMAT_ARGB8888; | |
2546 | else | |
2547 | return DRM_FORMAT_XRGB8888; | |
2548 | } | |
2549 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2550 | if (rgb_order) | |
2551 | return DRM_FORMAT_XBGR2101010; | |
2552 | else | |
2553 | return DRM_FORMAT_XRGB2101010; | |
2554 | } | |
2555 | } | |
2556 | ||
5724dbd1 | 2557 | static bool |
f6936e29 DV |
2558 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2559 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2560 | { |
2561 | struct drm_device *dev = crtc->base.dev; | |
2562 | struct drm_i915_gem_object *obj = NULL; | |
2563 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2564 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2565 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2566 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2567 | PAGE_SIZE); | |
2568 | ||
2569 | size_aligned -= base_aligned; | |
46f297fb | 2570 | |
ff2652ea CW |
2571 | if (plane_config->size == 0) |
2572 | return false; | |
2573 | ||
f37b5c2b DV |
2574 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2575 | base_aligned, | |
2576 | base_aligned, | |
2577 | size_aligned); | |
46f297fb | 2578 | if (!obj) |
484b41dd | 2579 | return false; |
46f297fb | 2580 | |
49af449b DL |
2581 | obj->tiling_mode = plane_config->tiling; |
2582 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2583 | obj->stride = fb->pitches[0]; |
46f297fb | 2584 | |
6bf129df DL |
2585 | mode_cmd.pixel_format = fb->pixel_format; |
2586 | mode_cmd.width = fb->width; | |
2587 | mode_cmd.height = fb->height; | |
2588 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2589 | mode_cmd.modifier[0] = fb->modifier[0]; |
2590 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2591 | |
2592 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2593 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2594 | &mode_cmd, obj)) { |
46f297fb JB |
2595 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2596 | goto out_unref_obj; | |
2597 | } | |
46f297fb | 2598 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2599 | |
f6936e29 | 2600 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2601 | return true; |
46f297fb JB |
2602 | |
2603 | out_unref_obj: | |
2604 | drm_gem_object_unreference(&obj->base); | |
2605 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2606 | return false; |
2607 | } | |
2608 | ||
afd65eb4 MR |
2609 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2610 | static void | |
2611 | update_state_fb(struct drm_plane *plane) | |
2612 | { | |
2613 | if (plane->fb == plane->state->fb) | |
2614 | return; | |
2615 | ||
2616 | if (plane->state->fb) | |
2617 | drm_framebuffer_unreference(plane->state->fb); | |
2618 | plane->state->fb = plane->fb; | |
2619 | if (plane->state->fb) | |
2620 | drm_framebuffer_reference(plane->state->fb); | |
2621 | } | |
2622 | ||
5724dbd1 | 2623 | static void |
f6936e29 DV |
2624 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2625 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2626 | { |
2627 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2628 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2629 | struct drm_crtc *c; |
2630 | struct intel_crtc *i; | |
2ff8fde1 | 2631 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2632 | struct drm_plane *primary = intel_crtc->base.primary; |
2633 | struct drm_framebuffer *fb; | |
484b41dd | 2634 | |
2d14030b | 2635 | if (!plane_config->fb) |
484b41dd JB |
2636 | return; |
2637 | ||
f6936e29 | 2638 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2639 | fb = &plane_config->fb->base; |
2640 | goto valid_fb; | |
f55548b5 | 2641 | } |
484b41dd | 2642 | |
2d14030b | 2643 | kfree(plane_config->fb); |
484b41dd JB |
2644 | |
2645 | /* | |
2646 | * Failed to alloc the obj, check to see if we should share | |
2647 | * an fb with another CRTC instead | |
2648 | */ | |
70e1e0ec | 2649 | for_each_crtc(dev, c) { |
484b41dd JB |
2650 | i = to_intel_crtc(c); |
2651 | ||
2652 | if (c == &intel_crtc->base) | |
2653 | continue; | |
2654 | ||
2ff8fde1 MR |
2655 | if (!i->active) |
2656 | continue; | |
2657 | ||
88595ac9 DV |
2658 | fb = c->primary->fb; |
2659 | if (!fb) | |
484b41dd JB |
2660 | continue; |
2661 | ||
88595ac9 | 2662 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2663 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2664 | drm_framebuffer_reference(fb); |
2665 | goto valid_fb; | |
484b41dd JB |
2666 | } |
2667 | } | |
88595ac9 DV |
2668 | |
2669 | return; | |
2670 | ||
2671 | valid_fb: | |
2672 | obj = intel_fb_obj(fb); | |
2673 | if (obj->tiling_mode != I915_TILING_NONE) | |
2674 | dev_priv->preserve_bios_swizzle = true; | |
2675 | ||
2676 | primary->fb = fb; | |
2677 | primary->state->crtc = &intel_crtc->base; | |
2678 | primary->crtc = &intel_crtc->base; | |
2679 | update_state_fb(primary); | |
2680 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2681 | } |
2682 | ||
29b9bde6 DV |
2683 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2684 | struct drm_framebuffer *fb, | |
2685 | int x, int y) | |
81255565 JB |
2686 | { |
2687 | struct drm_device *dev = crtc->dev; | |
2688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2690 | struct drm_i915_gem_object *obj; |
81255565 | 2691 | int plane = intel_crtc->plane; |
e506a0c6 | 2692 | unsigned long linear_offset; |
81255565 | 2693 | u32 dspcntr; |
f45651ba | 2694 | u32 reg = DSPCNTR(plane); |
48404c1e | 2695 | int pixel_size; |
f45651ba | 2696 | |
fdd508a6 VS |
2697 | if (!intel_crtc->primary_enabled) { |
2698 | I915_WRITE(reg, 0); | |
2699 | if (INTEL_INFO(dev)->gen >= 4) | |
2700 | I915_WRITE(DSPSURF(plane), 0); | |
2701 | else | |
2702 | I915_WRITE(DSPADDR(plane), 0); | |
2703 | POSTING_READ(reg); | |
2704 | return; | |
2705 | } | |
2706 | ||
c9ba6fad VS |
2707 | obj = intel_fb_obj(fb); |
2708 | if (WARN_ON(obj == NULL)) | |
2709 | return; | |
2710 | ||
2711 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2712 | ||
f45651ba VS |
2713 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2714 | ||
fdd508a6 | 2715 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2716 | |
2717 | if (INTEL_INFO(dev)->gen < 4) { | |
2718 | if (intel_crtc->pipe == PIPE_B) | |
2719 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2720 | ||
2721 | /* pipesrc and dspsize control the size that is scaled from, | |
2722 | * which should always be the user's requested size. | |
2723 | */ | |
2724 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2725 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2726 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2727 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2728 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2729 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2730 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2731 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2732 | I915_WRITE(PRIMPOS(plane), 0); |
2733 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2734 | } |
81255565 | 2735 | |
57779d06 VS |
2736 | switch (fb->pixel_format) { |
2737 | case DRM_FORMAT_C8: | |
81255565 JB |
2738 | dspcntr |= DISPPLANE_8BPP; |
2739 | break; | |
57779d06 VS |
2740 | case DRM_FORMAT_XRGB1555: |
2741 | case DRM_FORMAT_ARGB1555: | |
2742 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2743 | break; |
57779d06 VS |
2744 | case DRM_FORMAT_RGB565: |
2745 | dspcntr |= DISPPLANE_BGRX565; | |
2746 | break; | |
2747 | case DRM_FORMAT_XRGB8888: | |
2748 | case DRM_FORMAT_ARGB8888: | |
2749 | dspcntr |= DISPPLANE_BGRX888; | |
2750 | break; | |
2751 | case DRM_FORMAT_XBGR8888: | |
2752 | case DRM_FORMAT_ABGR8888: | |
2753 | dspcntr |= DISPPLANE_RGBX888; | |
2754 | break; | |
2755 | case DRM_FORMAT_XRGB2101010: | |
2756 | case DRM_FORMAT_ARGB2101010: | |
2757 | dspcntr |= DISPPLANE_BGRX101010; | |
2758 | break; | |
2759 | case DRM_FORMAT_XBGR2101010: | |
2760 | case DRM_FORMAT_ABGR2101010: | |
2761 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2762 | break; |
2763 | default: | |
baba133a | 2764 | BUG(); |
81255565 | 2765 | } |
57779d06 | 2766 | |
f45651ba VS |
2767 | if (INTEL_INFO(dev)->gen >= 4 && |
2768 | obj->tiling_mode != I915_TILING_NONE) | |
2769 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2770 | |
de1aa629 VS |
2771 | if (IS_G4X(dev)) |
2772 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2773 | ||
b9897127 | 2774 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2775 | |
c2c75131 DV |
2776 | if (INTEL_INFO(dev)->gen >= 4) { |
2777 | intel_crtc->dspaddr_offset = | |
bc752862 | 2778 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2779 | pixel_size, |
bc752862 | 2780 | fb->pitches[0]); |
c2c75131 DV |
2781 | linear_offset -= intel_crtc->dspaddr_offset; |
2782 | } else { | |
e506a0c6 | 2783 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2784 | } |
e506a0c6 | 2785 | |
8e7d688b | 2786 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2787 | dspcntr |= DISPPLANE_ROTATE_180; |
2788 | ||
6e3c9717 ACO |
2789 | x += (intel_crtc->config->pipe_src_w - 1); |
2790 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2791 | |
2792 | /* Finding the last pixel of the last line of the display | |
2793 | data and adding to linear_offset*/ | |
2794 | linear_offset += | |
6e3c9717 ACO |
2795 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2796 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2797 | } |
2798 | ||
2799 | I915_WRITE(reg, dspcntr); | |
2800 | ||
01f2c773 | 2801 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2802 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2803 | I915_WRITE(DSPSURF(plane), |
2804 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2805 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2806 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2807 | } else |
f343c5f6 | 2808 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2809 | POSTING_READ(reg); |
17638cd6 JB |
2810 | } |
2811 | ||
29b9bde6 DV |
2812 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2813 | struct drm_framebuffer *fb, | |
2814 | int x, int y) | |
17638cd6 JB |
2815 | { |
2816 | struct drm_device *dev = crtc->dev; | |
2817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2819 | struct drm_i915_gem_object *obj; |
17638cd6 | 2820 | int plane = intel_crtc->plane; |
e506a0c6 | 2821 | unsigned long linear_offset; |
17638cd6 | 2822 | u32 dspcntr; |
f45651ba | 2823 | u32 reg = DSPCNTR(plane); |
48404c1e | 2824 | int pixel_size; |
f45651ba | 2825 | |
fdd508a6 VS |
2826 | if (!intel_crtc->primary_enabled) { |
2827 | I915_WRITE(reg, 0); | |
2828 | I915_WRITE(DSPSURF(plane), 0); | |
2829 | POSTING_READ(reg); | |
2830 | return; | |
2831 | } | |
2832 | ||
c9ba6fad VS |
2833 | obj = intel_fb_obj(fb); |
2834 | if (WARN_ON(obj == NULL)) | |
2835 | return; | |
2836 | ||
2837 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2838 | ||
f45651ba VS |
2839 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2840 | ||
fdd508a6 | 2841 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2842 | |
2843 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2844 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2845 | |
57779d06 VS |
2846 | switch (fb->pixel_format) { |
2847 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2848 | dspcntr |= DISPPLANE_8BPP; |
2849 | break; | |
57779d06 VS |
2850 | case DRM_FORMAT_RGB565: |
2851 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2852 | break; |
57779d06 VS |
2853 | case DRM_FORMAT_XRGB8888: |
2854 | case DRM_FORMAT_ARGB8888: | |
2855 | dspcntr |= DISPPLANE_BGRX888; | |
2856 | break; | |
2857 | case DRM_FORMAT_XBGR8888: | |
2858 | case DRM_FORMAT_ABGR8888: | |
2859 | dspcntr |= DISPPLANE_RGBX888; | |
2860 | break; | |
2861 | case DRM_FORMAT_XRGB2101010: | |
2862 | case DRM_FORMAT_ARGB2101010: | |
2863 | dspcntr |= DISPPLANE_BGRX101010; | |
2864 | break; | |
2865 | case DRM_FORMAT_XBGR2101010: | |
2866 | case DRM_FORMAT_ABGR2101010: | |
2867 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2868 | break; |
2869 | default: | |
baba133a | 2870 | BUG(); |
17638cd6 JB |
2871 | } |
2872 | ||
2873 | if (obj->tiling_mode != I915_TILING_NONE) | |
2874 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2875 | |
f45651ba | 2876 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2877 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2878 | |
b9897127 | 2879 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2880 | intel_crtc->dspaddr_offset = |
bc752862 | 2881 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2882 | pixel_size, |
bc752862 | 2883 | fb->pitches[0]); |
c2c75131 | 2884 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2885 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2886 | dspcntr |= DISPPLANE_ROTATE_180; |
2887 | ||
2888 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2889 | x += (intel_crtc->config->pipe_src_w - 1); |
2890 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2891 | |
2892 | /* Finding the last pixel of the last line of the display | |
2893 | data and adding to linear_offset*/ | |
2894 | linear_offset += | |
6e3c9717 ACO |
2895 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2896 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2897 | } |
2898 | } | |
2899 | ||
2900 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2901 | |
01f2c773 | 2902 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2903 | I915_WRITE(DSPSURF(plane), |
2904 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2905 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2906 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2907 | } else { | |
2908 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2909 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2910 | } | |
17638cd6 | 2911 | POSTING_READ(reg); |
17638cd6 JB |
2912 | } |
2913 | ||
b321803d DL |
2914 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2915 | uint32_t pixel_format) | |
2916 | { | |
2917 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2918 | ||
2919 | /* | |
2920 | * The stride is either expressed as a multiple of 64 bytes | |
2921 | * chunks for linear buffers or in number of tiles for tiled | |
2922 | * buffers. | |
2923 | */ | |
2924 | switch (fb_modifier) { | |
2925 | case DRM_FORMAT_MOD_NONE: | |
2926 | return 64; | |
2927 | case I915_FORMAT_MOD_X_TILED: | |
2928 | if (INTEL_INFO(dev)->gen == 2) | |
2929 | return 128; | |
2930 | return 512; | |
2931 | case I915_FORMAT_MOD_Y_TILED: | |
2932 | /* No need to check for old gens and Y tiling since this is | |
2933 | * about the display engine and those will be blocked before | |
2934 | * we get here. | |
2935 | */ | |
2936 | return 128; | |
2937 | case I915_FORMAT_MOD_Yf_TILED: | |
2938 | if (bits_per_pixel == 8) | |
2939 | return 64; | |
2940 | else | |
2941 | return 128; | |
2942 | default: | |
2943 | MISSING_CASE(fb_modifier); | |
2944 | return 64; | |
2945 | } | |
2946 | } | |
2947 | ||
121920fa TU |
2948 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2949 | struct drm_i915_gem_object *obj) | |
2950 | { | |
9abc4648 | 2951 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2952 | |
2953 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2954 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2955 | |
2956 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2957 | } | |
2958 | ||
a1b2278e CK |
2959 | /* |
2960 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2961 | */ | |
2962 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2963 | { | |
2964 | struct drm_device *dev; | |
2965 | struct drm_i915_private *dev_priv; | |
2966 | struct intel_crtc_scaler_state *scaler_state; | |
2967 | int i; | |
2968 | ||
2969 | if (!intel_crtc || !intel_crtc->config) | |
2970 | return; | |
2971 | ||
2972 | dev = intel_crtc->base.dev; | |
2973 | dev_priv = dev->dev_private; | |
2974 | scaler_state = &intel_crtc->config->scaler_state; | |
2975 | ||
2976 | /* loop through and disable scalers that aren't in use */ | |
2977 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2978 | if (!scaler_state->scalers[i].in_use) { | |
2979 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2980 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2981 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2982 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2983 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2984 | } | |
2985 | } | |
2986 | } | |
2987 | ||
70d21f0e DL |
2988 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2989 | struct drm_framebuffer *fb, | |
2990 | int x, int y) | |
2991 | { | |
2992 | struct drm_device *dev = crtc->dev; | |
2993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2995 | struct drm_i915_gem_object *obj; |
2996 | int pipe = intel_crtc->pipe; | |
3b7a5119 SJ |
2997 | u32 plane_ctl, stride_div, stride; |
2998 | u32 tile_height, plane_offset, plane_size; | |
2999 | unsigned int rotation; | |
3000 | int x_offset, y_offset; | |
121920fa | 3001 | unsigned long surf_addr; |
3b7a5119 | 3002 | struct drm_plane *plane; |
70d21f0e DL |
3003 | |
3004 | if (!intel_crtc->primary_enabled) { | |
3005 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
3006 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3007 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3008 | return; | |
3009 | } | |
3010 | ||
3011 | plane_ctl = PLANE_CTL_ENABLE | | |
3012 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3013 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3014 | ||
3015 | switch (fb->pixel_format) { | |
3016 | case DRM_FORMAT_RGB565: | |
3017 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
3018 | break; | |
3019 | case DRM_FORMAT_XRGB8888: | |
3020 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
3021 | break; | |
f75fb42a JN |
3022 | case DRM_FORMAT_ARGB8888: |
3023 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
3024 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
3025 | break; | |
70d21f0e DL |
3026 | case DRM_FORMAT_XBGR8888: |
3027 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
3028 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
3029 | break; | |
f75fb42a JN |
3030 | case DRM_FORMAT_ABGR8888: |
3031 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
3032 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
3033 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
3034 | break; | |
70d21f0e DL |
3035 | case DRM_FORMAT_XRGB2101010: |
3036 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
3037 | break; | |
3038 | case DRM_FORMAT_XBGR2101010: | |
3039 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
3040 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
3041 | break; | |
3042 | default: | |
3043 | BUG(); | |
3044 | } | |
3045 | ||
30af77c4 DV |
3046 | switch (fb->modifier[0]) { |
3047 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 3048 | break; |
30af77c4 | 3049 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 3050 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
3051 | break; |
3052 | case I915_FORMAT_MOD_Y_TILED: | |
3053 | plane_ctl |= PLANE_CTL_TILED_Y; | |
3054 | break; | |
3055 | case I915_FORMAT_MOD_Yf_TILED: | |
3056 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
3057 | break; |
3058 | default: | |
b321803d | 3059 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
3060 | } |
3061 | ||
3062 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3b7a5119 SJ |
3063 | |
3064 | plane = crtc->primary; | |
3065 | rotation = plane->state->rotation; | |
3066 | switch (rotation) { | |
3067 | case BIT(DRM_ROTATE_90): | |
3068 | plane_ctl |= PLANE_CTL_ROTATE_90; | |
3069 | break; | |
3070 | ||
3071 | case BIT(DRM_ROTATE_180): | |
1447dde0 | 3072 | plane_ctl |= PLANE_CTL_ROTATE_180; |
3b7a5119 SJ |
3073 | break; |
3074 | ||
3075 | case BIT(DRM_ROTATE_270): | |
3076 | plane_ctl |= PLANE_CTL_ROTATE_270; | |
3077 | break; | |
3078 | } | |
70d21f0e | 3079 | |
b321803d DL |
3080 | obj = intel_fb_obj(fb); |
3081 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3082 | fb->pixel_format); | |
3b7a5119 SJ |
3083 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3084 | ||
3085 | if (intel_rotation_90_or_270(rotation)) { | |
3086 | /* stride = Surface height in tiles */ | |
3087 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, | |
3088 | fb->modifier[0]); | |
3089 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
3090 | x_offset = stride * tile_height - y - (plane->state->src_h >> 16); | |
3091 | y_offset = x; | |
3092 | plane_size = ((plane->state->src_w >> 16) - 1) << 16 | | |
3093 | ((plane->state->src_h >> 16) - 1); | |
3094 | } else { | |
3095 | stride = fb->pitches[0] / stride_div; | |
3096 | x_offset = x; | |
3097 | y_offset = y; | |
3098 | plane_size = ((plane->state->src_h >> 16) - 1) << 16 | | |
3099 | ((plane->state->src_w >> 16) - 1); | |
3100 | } | |
3101 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3102 | |
70d21f0e | 3103 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
70d21f0e | 3104 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
3b7a5119 SJ |
3105 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3106 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3107 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
121920fa | 3108 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3109 | |
3110 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3111 | } | |
3112 | ||
17638cd6 JB |
3113 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3114 | static int | |
3115 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3116 | int x, int y, enum mode_set_atomic state) | |
3117 | { | |
3118 | struct drm_device *dev = crtc->dev; | |
3119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3120 | |
6b8e6ed0 CW |
3121 | if (dev_priv->display.disable_fbc) |
3122 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3123 | |
29b9bde6 DV |
3124 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3125 | ||
3126 | return 0; | |
81255565 JB |
3127 | } |
3128 | ||
7514747d | 3129 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3130 | { |
96a02917 VS |
3131 | struct drm_crtc *crtc; |
3132 | ||
70e1e0ec | 3133 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3135 | enum plane plane = intel_crtc->plane; | |
3136 | ||
3137 | intel_prepare_page_flip(dev, plane); | |
3138 | intel_finish_page_flip_plane(dev, plane); | |
3139 | } | |
7514747d VS |
3140 | } |
3141 | ||
3142 | static void intel_update_primary_planes(struct drm_device *dev) | |
3143 | { | |
3144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3145 | struct drm_crtc *crtc; | |
96a02917 | 3146 | |
70e1e0ec | 3147 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3149 | ||
51fd371b | 3150 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3151 | /* |
3152 | * FIXME: Once we have proper support for primary planes (and | |
3153 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3154 | * a NULL crtc->primary->fb. |
947fdaad | 3155 | */ |
f4510a27 | 3156 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3157 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3158 | crtc->primary->fb, |
262ca2b0 MR |
3159 | crtc->x, |
3160 | crtc->y); | |
51fd371b | 3161 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3162 | } |
3163 | } | |
3164 | ||
7514747d VS |
3165 | void intel_prepare_reset(struct drm_device *dev) |
3166 | { | |
f98ce92f VS |
3167 | struct drm_i915_private *dev_priv = to_i915(dev); |
3168 | struct intel_crtc *crtc; | |
3169 | ||
7514747d VS |
3170 | /* no reset support for gen2 */ |
3171 | if (IS_GEN2(dev)) | |
3172 | return; | |
3173 | ||
3174 | /* reset doesn't touch the display */ | |
3175 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3176 | return; | |
3177 | ||
3178 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3179 | |
3180 | /* | |
3181 | * Disabling the crtcs gracefully seems nicer. Also the | |
3182 | * g33 docs say we should at least disable all the planes. | |
3183 | */ | |
3184 | for_each_intel_crtc(dev, crtc) { | |
3185 | if (crtc->active) | |
3186 | dev_priv->display.crtc_disable(&crtc->base); | |
3187 | } | |
7514747d VS |
3188 | } |
3189 | ||
3190 | void intel_finish_reset(struct drm_device *dev) | |
3191 | { | |
3192 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3193 | ||
3194 | /* | |
3195 | * Flips in the rings will be nuked by the reset, | |
3196 | * so complete all pending flips so that user space | |
3197 | * will get its events and not get stuck. | |
3198 | */ | |
3199 | intel_complete_page_flips(dev); | |
3200 | ||
3201 | /* no reset support for gen2 */ | |
3202 | if (IS_GEN2(dev)) | |
3203 | return; | |
3204 | ||
3205 | /* reset doesn't touch the display */ | |
3206 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3207 | /* | |
3208 | * Flips in the rings have been nuked by the reset, | |
3209 | * so update the base address of all primary | |
3210 | * planes to the the last fb to make sure we're | |
3211 | * showing the correct fb after a reset. | |
3212 | */ | |
3213 | intel_update_primary_planes(dev); | |
3214 | return; | |
3215 | } | |
3216 | ||
3217 | /* | |
3218 | * The display has been reset as well, | |
3219 | * so need a full re-initialization. | |
3220 | */ | |
3221 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3222 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3223 | ||
3224 | intel_modeset_init_hw(dev); | |
3225 | ||
3226 | spin_lock_irq(&dev_priv->irq_lock); | |
3227 | if (dev_priv->display.hpd_irq_setup) | |
3228 | dev_priv->display.hpd_irq_setup(dev); | |
3229 | spin_unlock_irq(&dev_priv->irq_lock); | |
3230 | ||
3231 | intel_modeset_setup_hw_state(dev, true); | |
3232 | ||
3233 | intel_hpd_init(dev_priv); | |
3234 | ||
3235 | drm_modeset_unlock_all(dev); | |
3236 | } | |
3237 | ||
14667a4b CW |
3238 | static int |
3239 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3240 | { | |
2ff8fde1 | 3241 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3242 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3243 | bool was_interruptible = dev_priv->mm.interruptible; | |
3244 | int ret; | |
3245 | ||
14667a4b CW |
3246 | /* Big Hammer, we also need to ensure that any pending |
3247 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3248 | * current scanout is retired before unpinning the old | |
3249 | * framebuffer. | |
3250 | * | |
3251 | * This should only fail upon a hung GPU, in which case we | |
3252 | * can safely continue. | |
3253 | */ | |
3254 | dev_priv->mm.interruptible = false; | |
3255 | ret = i915_gem_object_finish_gpu(obj); | |
3256 | dev_priv->mm.interruptible = was_interruptible; | |
3257 | ||
3258 | return ret; | |
3259 | } | |
3260 | ||
7d5e3799 CW |
3261 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3262 | { | |
3263 | struct drm_device *dev = crtc->dev; | |
3264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3266 | bool pending; |
3267 | ||
3268 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3269 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3270 | return false; | |
3271 | ||
5e2d7afc | 3272 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3273 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3274 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3275 | |
3276 | return pending; | |
3277 | } | |
3278 | ||
e30e8f75 GP |
3279 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3280 | { | |
3281 | struct drm_device *dev = crtc->base.dev; | |
3282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3283 | const struct drm_display_mode *adjusted_mode; | |
3284 | ||
3285 | if (!i915.fastboot) | |
3286 | return; | |
3287 | ||
3288 | /* | |
3289 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3290 | * that in compute_mode_changes we check the native mode (not the pfit | |
3291 | * mode) to see if we can flip rather than do a full mode set. In the | |
3292 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3293 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3294 | * sized surface. | |
3295 | * | |
3296 | * To fix this properly, we need to hoist the checks up into | |
3297 | * compute_mode_changes (or above), check the actual pfit state and | |
3298 | * whether the platform allows pfit disable with pipe active, and only | |
3299 | * then update the pipesrc and pfit state, even on the flip path. | |
3300 | */ | |
3301 | ||
6e3c9717 | 3302 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3303 | |
3304 | I915_WRITE(PIPESRC(crtc->pipe), | |
3305 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3306 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3307 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3308 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3309 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3310 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3311 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3312 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3313 | } | |
6e3c9717 ACO |
3314 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3315 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3316 | } |
3317 | ||
5e84e1a4 ZW |
3318 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3319 | { | |
3320 | struct drm_device *dev = crtc->dev; | |
3321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3323 | int pipe = intel_crtc->pipe; | |
3324 | u32 reg, temp; | |
3325 | ||
3326 | /* enable normal train */ | |
3327 | reg = FDI_TX_CTL(pipe); | |
3328 | temp = I915_READ(reg); | |
61e499bf | 3329 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3330 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3331 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3332 | } else { |
3333 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3334 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3335 | } |
5e84e1a4 ZW |
3336 | I915_WRITE(reg, temp); |
3337 | ||
3338 | reg = FDI_RX_CTL(pipe); | |
3339 | temp = I915_READ(reg); | |
3340 | if (HAS_PCH_CPT(dev)) { | |
3341 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3342 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3343 | } else { | |
3344 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3345 | temp |= FDI_LINK_TRAIN_NONE; | |
3346 | } | |
3347 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3348 | ||
3349 | /* wait one idle pattern time */ | |
3350 | POSTING_READ(reg); | |
3351 | udelay(1000); | |
357555c0 JB |
3352 | |
3353 | /* IVB wants error correction enabled */ | |
3354 | if (IS_IVYBRIDGE(dev)) | |
3355 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3356 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3357 | } |
3358 | ||
8db9d77b ZW |
3359 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3360 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3361 | { | |
3362 | struct drm_device *dev = crtc->dev; | |
3363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3364 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3365 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3366 | u32 reg, temp, tries; |
8db9d77b | 3367 | |
1c8562f6 | 3368 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3369 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3370 | |
e1a44743 AJ |
3371 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3372 | for train result */ | |
5eddb70b CW |
3373 | reg = FDI_RX_IMR(pipe); |
3374 | temp = I915_READ(reg); | |
e1a44743 AJ |
3375 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3376 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3377 | I915_WRITE(reg, temp); |
3378 | I915_READ(reg); | |
e1a44743 AJ |
3379 | udelay(150); |
3380 | ||
8db9d77b | 3381 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3382 | reg = FDI_TX_CTL(pipe); |
3383 | temp = I915_READ(reg); | |
627eb5a3 | 3384 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3385 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3386 | temp &= ~FDI_LINK_TRAIN_NONE; |
3387 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3388 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3389 | |
5eddb70b CW |
3390 | reg = FDI_RX_CTL(pipe); |
3391 | temp = I915_READ(reg); | |
8db9d77b ZW |
3392 | temp &= ~FDI_LINK_TRAIN_NONE; |
3393 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3394 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3395 | ||
3396 | POSTING_READ(reg); | |
8db9d77b ZW |
3397 | udelay(150); |
3398 | ||
5b2adf89 | 3399 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3400 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3401 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3402 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3403 | |
5eddb70b | 3404 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3405 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3406 | temp = I915_READ(reg); |
8db9d77b ZW |
3407 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3408 | ||
3409 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3410 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3411 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3412 | break; |
3413 | } | |
8db9d77b | 3414 | } |
e1a44743 | 3415 | if (tries == 5) |
5eddb70b | 3416 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3417 | |
3418 | /* Train 2 */ | |
5eddb70b CW |
3419 | reg = FDI_TX_CTL(pipe); |
3420 | temp = I915_READ(reg); | |
8db9d77b ZW |
3421 | temp &= ~FDI_LINK_TRAIN_NONE; |
3422 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3423 | I915_WRITE(reg, temp); |
8db9d77b | 3424 | |
5eddb70b CW |
3425 | reg = FDI_RX_CTL(pipe); |
3426 | temp = I915_READ(reg); | |
8db9d77b ZW |
3427 | temp &= ~FDI_LINK_TRAIN_NONE; |
3428 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3429 | I915_WRITE(reg, temp); |
8db9d77b | 3430 | |
5eddb70b CW |
3431 | POSTING_READ(reg); |
3432 | udelay(150); | |
8db9d77b | 3433 | |
5eddb70b | 3434 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3435 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3436 | temp = I915_READ(reg); |
8db9d77b ZW |
3437 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3438 | ||
3439 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3440 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3441 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3442 | break; | |
3443 | } | |
8db9d77b | 3444 | } |
e1a44743 | 3445 | if (tries == 5) |
5eddb70b | 3446 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3447 | |
3448 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3449 | |
8db9d77b ZW |
3450 | } |
3451 | ||
0206e353 | 3452 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3453 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3454 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3455 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3456 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3457 | }; | |
3458 | ||
3459 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3460 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3461 | { | |
3462 | struct drm_device *dev = crtc->dev; | |
3463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3464 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3465 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3466 | u32 reg, temp, i, retry; |
8db9d77b | 3467 | |
e1a44743 AJ |
3468 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3469 | for train result */ | |
5eddb70b CW |
3470 | reg = FDI_RX_IMR(pipe); |
3471 | temp = I915_READ(reg); | |
e1a44743 AJ |
3472 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3473 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3474 | I915_WRITE(reg, temp); |
3475 | ||
3476 | POSTING_READ(reg); | |
e1a44743 AJ |
3477 | udelay(150); |
3478 | ||
8db9d77b | 3479 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3480 | reg = FDI_TX_CTL(pipe); |
3481 | temp = I915_READ(reg); | |
627eb5a3 | 3482 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3483 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3484 | temp &= ~FDI_LINK_TRAIN_NONE; |
3485 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3486 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3487 | /* SNB-B */ | |
3488 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3489 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3490 | |
d74cf324 DV |
3491 | I915_WRITE(FDI_RX_MISC(pipe), |
3492 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3493 | ||
5eddb70b CW |
3494 | reg = FDI_RX_CTL(pipe); |
3495 | temp = I915_READ(reg); | |
8db9d77b ZW |
3496 | if (HAS_PCH_CPT(dev)) { |
3497 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3498 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3499 | } else { | |
3500 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3501 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3502 | } | |
5eddb70b CW |
3503 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3504 | ||
3505 | POSTING_READ(reg); | |
8db9d77b ZW |
3506 | udelay(150); |
3507 | ||
0206e353 | 3508 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3509 | reg = FDI_TX_CTL(pipe); |
3510 | temp = I915_READ(reg); | |
8db9d77b ZW |
3511 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3512 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3513 | I915_WRITE(reg, temp); |
3514 | ||
3515 | POSTING_READ(reg); | |
8db9d77b ZW |
3516 | udelay(500); |
3517 | ||
fa37d39e SP |
3518 | for (retry = 0; retry < 5; retry++) { |
3519 | reg = FDI_RX_IIR(pipe); | |
3520 | temp = I915_READ(reg); | |
3521 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3522 | if (temp & FDI_RX_BIT_LOCK) { | |
3523 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3524 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3525 | break; | |
3526 | } | |
3527 | udelay(50); | |
8db9d77b | 3528 | } |
fa37d39e SP |
3529 | if (retry < 5) |
3530 | break; | |
8db9d77b ZW |
3531 | } |
3532 | if (i == 4) | |
5eddb70b | 3533 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3534 | |
3535 | /* Train 2 */ | |
5eddb70b CW |
3536 | reg = FDI_TX_CTL(pipe); |
3537 | temp = I915_READ(reg); | |
8db9d77b ZW |
3538 | temp &= ~FDI_LINK_TRAIN_NONE; |
3539 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3540 | if (IS_GEN6(dev)) { | |
3541 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3542 | /* SNB-B */ | |
3543 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3544 | } | |
5eddb70b | 3545 | I915_WRITE(reg, temp); |
8db9d77b | 3546 | |
5eddb70b CW |
3547 | reg = FDI_RX_CTL(pipe); |
3548 | temp = I915_READ(reg); | |
8db9d77b ZW |
3549 | if (HAS_PCH_CPT(dev)) { |
3550 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3551 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3552 | } else { | |
3553 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3554 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3555 | } | |
5eddb70b CW |
3556 | I915_WRITE(reg, temp); |
3557 | ||
3558 | POSTING_READ(reg); | |
8db9d77b ZW |
3559 | udelay(150); |
3560 | ||
0206e353 | 3561 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3562 | reg = FDI_TX_CTL(pipe); |
3563 | temp = I915_READ(reg); | |
8db9d77b ZW |
3564 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3565 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3566 | I915_WRITE(reg, temp); |
3567 | ||
3568 | POSTING_READ(reg); | |
8db9d77b ZW |
3569 | udelay(500); |
3570 | ||
fa37d39e SP |
3571 | for (retry = 0; retry < 5; retry++) { |
3572 | reg = FDI_RX_IIR(pipe); | |
3573 | temp = I915_READ(reg); | |
3574 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3575 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3576 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3577 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3578 | break; | |
3579 | } | |
3580 | udelay(50); | |
8db9d77b | 3581 | } |
fa37d39e SP |
3582 | if (retry < 5) |
3583 | break; | |
8db9d77b ZW |
3584 | } |
3585 | if (i == 4) | |
5eddb70b | 3586 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3587 | |
3588 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3589 | } | |
3590 | ||
357555c0 JB |
3591 | /* Manual link training for Ivy Bridge A0 parts */ |
3592 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3593 | { | |
3594 | struct drm_device *dev = crtc->dev; | |
3595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3597 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3598 | u32 reg, temp, i, j; |
357555c0 JB |
3599 | |
3600 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3601 | for train result */ | |
3602 | reg = FDI_RX_IMR(pipe); | |
3603 | temp = I915_READ(reg); | |
3604 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3605 | temp &= ~FDI_RX_BIT_LOCK; | |
3606 | I915_WRITE(reg, temp); | |
3607 | ||
3608 | POSTING_READ(reg); | |
3609 | udelay(150); | |
3610 | ||
01a415fd DV |
3611 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3612 | I915_READ(FDI_RX_IIR(pipe))); | |
3613 | ||
139ccd3f JB |
3614 | /* Try each vswing and preemphasis setting twice before moving on */ |
3615 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3616 | /* disable first in case we need to retry */ | |
3617 | reg = FDI_TX_CTL(pipe); | |
3618 | temp = I915_READ(reg); | |
3619 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3620 | temp &= ~FDI_TX_ENABLE; | |
3621 | I915_WRITE(reg, temp); | |
357555c0 | 3622 | |
139ccd3f JB |
3623 | reg = FDI_RX_CTL(pipe); |
3624 | temp = I915_READ(reg); | |
3625 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3626 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3627 | temp &= ~FDI_RX_ENABLE; | |
3628 | I915_WRITE(reg, temp); | |
357555c0 | 3629 | |
139ccd3f | 3630 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3631 | reg = FDI_TX_CTL(pipe); |
3632 | temp = I915_READ(reg); | |
139ccd3f | 3633 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3634 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3635 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3636 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3637 | temp |= snb_b_fdi_train_param[j/2]; |
3638 | temp |= FDI_COMPOSITE_SYNC; | |
3639 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3640 | |
139ccd3f JB |
3641 | I915_WRITE(FDI_RX_MISC(pipe), |
3642 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3643 | |
139ccd3f | 3644 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3645 | temp = I915_READ(reg); |
139ccd3f JB |
3646 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3647 | temp |= FDI_COMPOSITE_SYNC; | |
3648 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3649 | |
139ccd3f JB |
3650 | POSTING_READ(reg); |
3651 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3652 | |
139ccd3f JB |
3653 | for (i = 0; i < 4; i++) { |
3654 | reg = FDI_RX_IIR(pipe); | |
3655 | temp = I915_READ(reg); | |
3656 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3657 | |
139ccd3f JB |
3658 | if (temp & FDI_RX_BIT_LOCK || |
3659 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3660 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3661 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3662 | i); | |
3663 | break; | |
3664 | } | |
3665 | udelay(1); /* should be 0.5us */ | |
3666 | } | |
3667 | if (i == 4) { | |
3668 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3669 | continue; | |
3670 | } | |
357555c0 | 3671 | |
139ccd3f | 3672 | /* Train 2 */ |
357555c0 JB |
3673 | reg = FDI_TX_CTL(pipe); |
3674 | temp = I915_READ(reg); | |
139ccd3f JB |
3675 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3676 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3677 | I915_WRITE(reg, temp); | |
3678 | ||
3679 | reg = FDI_RX_CTL(pipe); | |
3680 | temp = I915_READ(reg); | |
3681 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3682 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3683 | I915_WRITE(reg, temp); |
3684 | ||
3685 | POSTING_READ(reg); | |
139ccd3f | 3686 | udelay(2); /* should be 1.5us */ |
357555c0 | 3687 | |
139ccd3f JB |
3688 | for (i = 0; i < 4; i++) { |
3689 | reg = FDI_RX_IIR(pipe); | |
3690 | temp = I915_READ(reg); | |
3691 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3692 | |
139ccd3f JB |
3693 | if (temp & FDI_RX_SYMBOL_LOCK || |
3694 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3695 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3696 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3697 | i); | |
3698 | goto train_done; | |
3699 | } | |
3700 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3701 | } |
139ccd3f JB |
3702 | if (i == 4) |
3703 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3704 | } |
357555c0 | 3705 | |
139ccd3f | 3706 | train_done: |
357555c0 JB |
3707 | DRM_DEBUG_KMS("FDI train done.\n"); |
3708 | } | |
3709 | ||
88cefb6c | 3710 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3711 | { |
88cefb6c | 3712 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3713 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3714 | int pipe = intel_crtc->pipe; |
5eddb70b | 3715 | u32 reg, temp; |
79e53945 | 3716 | |
c64e311e | 3717 | |
c98e9dcf | 3718 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3719 | reg = FDI_RX_CTL(pipe); |
3720 | temp = I915_READ(reg); | |
627eb5a3 | 3721 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3722 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3723 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3724 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3725 | ||
3726 | POSTING_READ(reg); | |
c98e9dcf JB |
3727 | udelay(200); |
3728 | ||
3729 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3730 | temp = I915_READ(reg); |
3731 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3732 | ||
3733 | POSTING_READ(reg); | |
c98e9dcf JB |
3734 | udelay(200); |
3735 | ||
20749730 PZ |
3736 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3737 | reg = FDI_TX_CTL(pipe); | |
3738 | temp = I915_READ(reg); | |
3739 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3740 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3741 | |
20749730 PZ |
3742 | POSTING_READ(reg); |
3743 | udelay(100); | |
6be4a607 | 3744 | } |
0e23b99d JB |
3745 | } |
3746 | ||
88cefb6c DV |
3747 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3748 | { | |
3749 | struct drm_device *dev = intel_crtc->base.dev; | |
3750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3751 | int pipe = intel_crtc->pipe; | |
3752 | u32 reg, temp; | |
3753 | ||
3754 | /* Switch from PCDclk to Rawclk */ | |
3755 | reg = FDI_RX_CTL(pipe); | |
3756 | temp = I915_READ(reg); | |
3757 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3758 | ||
3759 | /* Disable CPU FDI TX PLL */ | |
3760 | reg = FDI_TX_CTL(pipe); | |
3761 | temp = I915_READ(reg); | |
3762 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3763 | ||
3764 | POSTING_READ(reg); | |
3765 | udelay(100); | |
3766 | ||
3767 | reg = FDI_RX_CTL(pipe); | |
3768 | temp = I915_READ(reg); | |
3769 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3770 | ||
3771 | /* Wait for the clocks to turn off. */ | |
3772 | POSTING_READ(reg); | |
3773 | udelay(100); | |
3774 | } | |
3775 | ||
0fc932b8 JB |
3776 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3777 | { | |
3778 | struct drm_device *dev = crtc->dev; | |
3779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3781 | int pipe = intel_crtc->pipe; | |
3782 | u32 reg, temp; | |
3783 | ||
3784 | /* disable CPU FDI tx and PCH FDI rx */ | |
3785 | reg = FDI_TX_CTL(pipe); | |
3786 | temp = I915_READ(reg); | |
3787 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3788 | POSTING_READ(reg); | |
3789 | ||
3790 | reg = FDI_RX_CTL(pipe); | |
3791 | temp = I915_READ(reg); | |
3792 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3793 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3794 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3795 | ||
3796 | POSTING_READ(reg); | |
3797 | udelay(100); | |
3798 | ||
3799 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3800 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3801 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3802 | |
3803 | /* still set train pattern 1 */ | |
3804 | reg = FDI_TX_CTL(pipe); | |
3805 | temp = I915_READ(reg); | |
3806 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3807 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3808 | I915_WRITE(reg, temp); | |
3809 | ||
3810 | reg = FDI_RX_CTL(pipe); | |
3811 | temp = I915_READ(reg); | |
3812 | if (HAS_PCH_CPT(dev)) { | |
3813 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3814 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3815 | } else { | |
3816 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3817 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3818 | } | |
3819 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3820 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3821 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3822 | I915_WRITE(reg, temp); |
3823 | ||
3824 | POSTING_READ(reg); | |
3825 | udelay(100); | |
3826 | } | |
3827 | ||
5dce5b93 CW |
3828 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3829 | { | |
3830 | struct intel_crtc *crtc; | |
3831 | ||
3832 | /* Note that we don't need to be called with mode_config.lock here | |
3833 | * as our list of CRTC objects is static for the lifetime of the | |
3834 | * device and so cannot disappear as we iterate. Similarly, we can | |
3835 | * happily treat the predicates as racy, atomic checks as userspace | |
3836 | * cannot claim and pin a new fb without at least acquring the | |
3837 | * struct_mutex and so serialising with us. | |
3838 | */ | |
d3fcc808 | 3839 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3840 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3841 | continue; | |
3842 | ||
3843 | if (crtc->unpin_work) | |
3844 | intel_wait_for_vblank(dev, crtc->pipe); | |
3845 | ||
3846 | return true; | |
3847 | } | |
3848 | ||
3849 | return false; | |
3850 | } | |
3851 | ||
d6bbafa1 CW |
3852 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3853 | { | |
3854 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3855 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3856 | ||
3857 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3858 | smp_rmb(); | |
3859 | intel_crtc->unpin_work = NULL; | |
3860 | ||
3861 | if (work->event) | |
3862 | drm_send_vblank_event(intel_crtc->base.dev, | |
3863 | intel_crtc->pipe, | |
3864 | work->event); | |
3865 | ||
3866 | drm_crtc_vblank_put(&intel_crtc->base); | |
3867 | ||
3868 | wake_up_all(&dev_priv->pending_flip_queue); | |
3869 | queue_work(dev_priv->wq, &work->work); | |
3870 | ||
3871 | trace_i915_flip_complete(intel_crtc->plane, | |
3872 | work->pending_flip_obj); | |
3873 | } | |
3874 | ||
46a55d30 | 3875 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3876 | { |
0f91128d | 3877 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3878 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3879 | |
2c10d571 | 3880 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3881 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3882 | !intel_crtc_has_pending_flip(crtc), | |
3883 | 60*HZ) == 0)) { | |
3884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3885 | |
5e2d7afc | 3886 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3887 | if (intel_crtc->unpin_work) { |
3888 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3889 | page_flip_completed(intel_crtc); | |
3890 | } | |
5e2d7afc | 3891 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3892 | } |
5bb61643 | 3893 | |
975d568a CW |
3894 | if (crtc->primary->fb) { |
3895 | mutex_lock(&dev->struct_mutex); | |
3896 | intel_finish_fb(crtc->primary->fb); | |
3897 | mutex_unlock(&dev->struct_mutex); | |
3898 | } | |
e6c3a2a6 CW |
3899 | } |
3900 | ||
e615efe4 ED |
3901 | /* Program iCLKIP clock to the desired frequency */ |
3902 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3903 | { | |
3904 | struct drm_device *dev = crtc->dev; | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3906 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3907 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3908 | u32 temp; | |
3909 | ||
09153000 DV |
3910 | mutex_lock(&dev_priv->dpio_lock); |
3911 | ||
e615efe4 ED |
3912 | /* It is necessary to ungate the pixclk gate prior to programming |
3913 | * the divisors, and gate it back when it is done. | |
3914 | */ | |
3915 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3916 | ||
3917 | /* Disable SSCCTL */ | |
3918 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3919 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3920 | SBI_SSCCTL_DISABLE, | |
3921 | SBI_ICLK); | |
e615efe4 ED |
3922 | |
3923 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3924 | if (clock == 20000) { |
e615efe4 ED |
3925 | auxdiv = 1; |
3926 | divsel = 0x41; | |
3927 | phaseinc = 0x20; | |
3928 | } else { | |
3929 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3930 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3931 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3932 | * convert the virtual clock precision to KHz here for higher |
3933 | * precision. | |
3934 | */ | |
3935 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3936 | u32 iclk_pi_range = 64; | |
3937 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3938 | ||
12d7ceed | 3939 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3940 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3941 | pi_value = desired_divisor % iclk_pi_range; | |
3942 | ||
3943 | auxdiv = 0; | |
3944 | divsel = msb_divisor_value - 2; | |
3945 | phaseinc = pi_value; | |
3946 | } | |
3947 | ||
3948 | /* This should not happen with any sane values */ | |
3949 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3950 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3951 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3952 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3953 | ||
3954 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3955 | clock, |
e615efe4 ED |
3956 | auxdiv, |
3957 | divsel, | |
3958 | phasedir, | |
3959 | phaseinc); | |
3960 | ||
3961 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3962 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3963 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3964 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3965 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3966 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3967 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3968 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3969 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3970 | |
3971 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3972 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3973 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3974 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3975 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3976 | |
3977 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3978 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3979 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3980 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3981 | |
3982 | /* Wait for initialization time */ | |
3983 | udelay(24); | |
3984 | ||
3985 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3986 | |
3987 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3988 | } |
3989 | ||
275f01b2 DV |
3990 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3991 | enum pipe pch_transcoder) | |
3992 | { | |
3993 | struct drm_device *dev = crtc->base.dev; | |
3994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3995 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3996 | |
3997 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3998 | I915_READ(HTOTAL(cpu_transcoder))); | |
3999 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4000 | I915_READ(HBLANK(cpu_transcoder))); | |
4001 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4002 | I915_READ(HSYNC(cpu_transcoder))); | |
4003 | ||
4004 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4005 | I915_READ(VTOTAL(cpu_transcoder))); | |
4006 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4007 | I915_READ(VBLANK(cpu_transcoder))); | |
4008 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4009 | I915_READ(VSYNC(cpu_transcoder))); | |
4010 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4011 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4012 | } | |
4013 | ||
003632d9 | 4014 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4015 | { |
4016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4017 | uint32_t temp; | |
4018 | ||
4019 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4020 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4021 | return; |
4022 | ||
4023 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4024 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4025 | ||
003632d9 ACO |
4026 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4027 | if (enable) | |
4028 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4029 | ||
4030 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4031 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4032 | POSTING_READ(SOUTH_CHICKEN1); | |
4033 | } | |
4034 | ||
4035 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4036 | { | |
4037 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4038 | |
4039 | switch (intel_crtc->pipe) { | |
4040 | case PIPE_A: | |
4041 | break; | |
4042 | case PIPE_B: | |
6e3c9717 | 4043 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4044 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4045 | else |
003632d9 | 4046 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4047 | |
4048 | break; | |
4049 | case PIPE_C: | |
003632d9 | 4050 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4051 | |
4052 | break; | |
4053 | default: | |
4054 | BUG(); | |
4055 | } | |
4056 | } | |
4057 | ||
f67a559d JB |
4058 | /* |
4059 | * Enable PCH resources required for PCH ports: | |
4060 | * - PCH PLLs | |
4061 | * - FDI training & RX/TX | |
4062 | * - update transcoder timings | |
4063 | * - DP transcoding bits | |
4064 | * - transcoder | |
4065 | */ | |
4066 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4067 | { |
4068 | struct drm_device *dev = crtc->dev; | |
4069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4071 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4072 | u32 reg, temp; |
2c07245f | 4073 | |
ab9412ba | 4074 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4075 | |
1fbc0d78 DV |
4076 | if (IS_IVYBRIDGE(dev)) |
4077 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4078 | ||
cd986abb DV |
4079 | /* Write the TU size bits before fdi link training, so that error |
4080 | * detection works. */ | |
4081 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4082 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4083 | ||
c98e9dcf | 4084 | /* For PCH output, training FDI link */ |
674cf967 | 4085 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4086 | |
3ad8a208 DV |
4087 | /* We need to program the right clock selection before writing the pixel |
4088 | * mutliplier into the DPLL. */ | |
303b81e0 | 4089 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4090 | u32 sel; |
4b645f14 | 4091 | |
c98e9dcf | 4092 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4093 | temp |= TRANS_DPLL_ENABLE(pipe); |
4094 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4095 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4096 | temp |= sel; |
4097 | else | |
4098 | temp &= ~sel; | |
c98e9dcf | 4099 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4100 | } |
5eddb70b | 4101 | |
3ad8a208 DV |
4102 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4103 | * transcoder, and we actually should do this to not upset any PCH | |
4104 | * transcoder that already use the clock when we share it. | |
4105 | * | |
4106 | * Note that enable_shared_dpll tries to do the right thing, but | |
4107 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4108 | * the right LVDS enable sequence. */ | |
85b3894f | 4109 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4110 | |
d9b6cb56 JB |
4111 | /* set transcoder timing, panel must allow it */ |
4112 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4113 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4114 | |
303b81e0 | 4115 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4116 | |
c98e9dcf | 4117 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4118 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4119 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4120 | reg = TRANS_DP_CTL(pipe); |
4121 | temp = I915_READ(reg); | |
4122 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4123 | TRANS_DP_SYNC_MASK | |
4124 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4125 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4126 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4127 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4128 | |
4129 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4130 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4131 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4132 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4133 | |
4134 | switch (intel_trans_dp_port_sel(crtc)) { | |
4135 | case PCH_DP_B: | |
5eddb70b | 4136 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4137 | break; |
4138 | case PCH_DP_C: | |
5eddb70b | 4139 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4140 | break; |
4141 | case PCH_DP_D: | |
5eddb70b | 4142 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4143 | break; |
4144 | default: | |
e95d41e1 | 4145 | BUG(); |
32f9d658 | 4146 | } |
2c07245f | 4147 | |
5eddb70b | 4148 | I915_WRITE(reg, temp); |
6be4a607 | 4149 | } |
b52eb4dc | 4150 | |
b8a4f404 | 4151 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4152 | } |
4153 | ||
1507e5bd PZ |
4154 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4155 | { | |
4156 | struct drm_device *dev = crtc->dev; | |
4157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4159 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4160 | |
ab9412ba | 4161 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4162 | |
8c52b5e8 | 4163 | lpt_program_iclkip(crtc); |
1507e5bd | 4164 | |
0540e488 | 4165 | /* Set transcoder timing. */ |
275f01b2 | 4166 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4167 | |
937bb610 | 4168 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4169 | } |
4170 | ||
716c2e55 | 4171 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4172 | { |
e2b78267 | 4173 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4174 | |
4175 | if (pll == NULL) | |
4176 | return; | |
4177 | ||
3e369b76 | 4178 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4179 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4180 | return; |
4181 | } | |
4182 | ||
3e369b76 ACO |
4183 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4184 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4185 | WARN_ON(pll->on); |
4186 | WARN_ON(pll->active); | |
4187 | } | |
4188 | ||
6e3c9717 | 4189 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4190 | } |
4191 | ||
190f68c5 ACO |
4192 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4193 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4194 | { |
e2b78267 | 4195 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4196 | struct intel_shared_dpll *pll; |
e2b78267 | 4197 | enum intel_dpll_id i; |
ee7b9f93 | 4198 | |
98b6bd99 DV |
4199 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4200 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4201 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4202 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4203 | |
46edb027 DV |
4204 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4205 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4206 | |
8bd31e67 | 4207 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4208 | |
98b6bd99 DV |
4209 | goto found; |
4210 | } | |
4211 | ||
bcddf610 S |
4212 | if (IS_BROXTON(dev_priv->dev)) { |
4213 | /* PLL is attached to port in bxt */ | |
4214 | struct intel_encoder *encoder; | |
4215 | struct intel_digital_port *intel_dig_port; | |
4216 | ||
4217 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4218 | if (WARN_ON(!encoder)) | |
4219 | return NULL; | |
4220 | ||
4221 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4222 | /* 1:1 mapping between ports and PLLs */ | |
4223 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4224 | pll = &dev_priv->shared_dplls[i]; | |
4225 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4226 | crtc->base.base.id, pll->name); | |
4227 | WARN_ON(pll->new_config->crtc_mask); | |
4228 | ||
4229 | goto found; | |
4230 | } | |
4231 | ||
e72f9fbf DV |
4232 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4233 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4234 | |
4235 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4236 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4237 | continue; |
4238 | ||
190f68c5 | 4239 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4240 | &pll->new_config->hw_state, |
4241 | sizeof(pll->new_config->hw_state)) == 0) { | |
4242 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4243 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4244 | pll->new_config->crtc_mask, |
4245 | pll->active); | |
ee7b9f93 JB |
4246 | goto found; |
4247 | } | |
4248 | } | |
4249 | ||
4250 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4251 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4252 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4253 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4254 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4255 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4256 | goto found; |
4257 | } | |
4258 | } | |
4259 | ||
4260 | return NULL; | |
4261 | ||
4262 | found: | |
8bd31e67 | 4263 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4264 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4265 | |
190f68c5 | 4266 | crtc_state->shared_dpll = i; |
46edb027 DV |
4267 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4268 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4269 | |
8bd31e67 | 4270 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4271 | |
ee7b9f93 JB |
4272 | return pll; |
4273 | } | |
4274 | ||
8bd31e67 ACO |
4275 | /** |
4276 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4277 | * @dev_priv: DRM device | |
4278 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4279 | * | |
4280 | * Starts a new PLL staged config, copying the current config but | |
4281 | * releasing the references of pipes specified in clear_pipes. | |
4282 | */ | |
4283 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4284 | unsigned clear_pipes) | |
4285 | { | |
4286 | struct intel_shared_dpll *pll; | |
4287 | enum intel_dpll_id i; | |
4288 | ||
4289 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4290 | pll = &dev_priv->shared_dplls[i]; | |
4291 | ||
4292 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4293 | GFP_KERNEL); | |
4294 | if (!pll->new_config) | |
4295 | goto cleanup; | |
4296 | ||
4297 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4298 | } | |
4299 | ||
4300 | return 0; | |
4301 | ||
4302 | cleanup: | |
4303 | while (--i >= 0) { | |
4304 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4305 | kfree(pll->new_config); |
8bd31e67 ACO |
4306 | pll->new_config = NULL; |
4307 | } | |
4308 | ||
4309 | return -ENOMEM; | |
4310 | } | |
4311 | ||
4312 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4313 | { | |
4314 | struct intel_shared_dpll *pll; | |
4315 | enum intel_dpll_id i; | |
4316 | ||
4317 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4318 | pll = &dev_priv->shared_dplls[i]; | |
4319 | ||
4320 | WARN_ON(pll->new_config == &pll->config); | |
4321 | ||
4322 | pll->config = *pll->new_config; | |
4323 | kfree(pll->new_config); | |
4324 | pll->new_config = NULL; | |
4325 | } | |
4326 | } | |
4327 | ||
4328 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4329 | { | |
4330 | struct intel_shared_dpll *pll; | |
4331 | enum intel_dpll_id i; | |
4332 | ||
4333 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4334 | pll = &dev_priv->shared_dplls[i]; | |
4335 | ||
4336 | WARN_ON(pll->new_config == &pll->config); | |
4337 | ||
4338 | kfree(pll->new_config); | |
4339 | pll->new_config = NULL; | |
4340 | } | |
4341 | } | |
4342 | ||
a1520318 | 4343 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4344 | { |
4345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4346 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4347 | u32 temp; |
4348 | ||
4349 | temp = I915_READ(dslreg); | |
4350 | udelay(500); | |
4351 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4352 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4353 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4354 | } |
4355 | } | |
4356 | ||
a1b2278e CK |
4357 | /** |
4358 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4359 | * @intel_crtc: crtc | |
4360 | * @crtc_state: crtc_state | |
4361 | * @plane: plane (NULL indicates crtc is requesting update) | |
4362 | * @plane_state: plane's state | |
4363 | * @force_detach: request unconditional detachment of scaler | |
4364 | * | |
4365 | * This function updates scaler state for requested plane or crtc. | |
4366 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4367 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4368 | * as NULL. | |
4369 | * | |
4370 | * Return | |
4371 | * 0 - scaler_usage updated successfully | |
4372 | * error - requested scaling cannot be supported or other error condition | |
4373 | */ | |
4374 | int | |
4375 | skl_update_scaler_users( | |
4376 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4377 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4378 | int force_detach) | |
4379 | { | |
4380 | int need_scaling; | |
4381 | int idx; | |
4382 | int src_w, src_h, dst_w, dst_h; | |
4383 | int *scaler_id; | |
4384 | struct drm_framebuffer *fb; | |
4385 | struct intel_crtc_scaler_state *scaler_state; | |
4386 | ||
4387 | if (!intel_crtc || !crtc_state) | |
4388 | return 0; | |
4389 | ||
4390 | scaler_state = &crtc_state->scaler_state; | |
4391 | ||
4392 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4393 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4394 | ||
4395 | if (intel_plane) { | |
4396 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4397 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4398 | dst_w = drm_rect_width(&plane_state->dst); | |
4399 | dst_h = drm_rect_height(&plane_state->dst); | |
4400 | scaler_id = &plane_state->scaler_id; | |
4401 | } else { | |
4402 | struct drm_display_mode *adjusted_mode = | |
4403 | &crtc_state->base.adjusted_mode; | |
4404 | src_w = crtc_state->pipe_src_w; | |
4405 | src_h = crtc_state->pipe_src_h; | |
4406 | dst_w = adjusted_mode->hdisplay; | |
4407 | dst_h = adjusted_mode->vdisplay; | |
4408 | scaler_id = &scaler_state->scaler_id; | |
4409 | } | |
4410 | need_scaling = (src_w != dst_w || src_h != dst_h); | |
4411 | ||
4412 | /* | |
4413 | * if plane is being disabled or scaler is no more required or force detach | |
4414 | * - free scaler binded to this plane/crtc | |
4415 | * - in order to do this, update crtc->scaler_usage | |
4416 | * | |
4417 | * Here scaler state in crtc_state is set free so that | |
4418 | * scaler can be assigned to other user. Actual register | |
4419 | * update to free the scaler is done in plane/panel-fit programming. | |
4420 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4421 | */ | |
4422 | if (force_detach || !need_scaling || (intel_plane && | |
4423 | (!fb || !plane_state->visible))) { | |
4424 | if (*scaler_id >= 0) { | |
4425 | scaler_state->scaler_users &= ~(1 << idx); | |
4426 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4427 | ||
4428 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4429 | "crtc_state = %p scaler_users = 0x%x\n", | |
4430 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4431 | intel_plane ? intel_plane->base.base.id : | |
4432 | intel_crtc->base.base.id, crtc_state, | |
4433 | scaler_state->scaler_users); | |
4434 | *scaler_id = -1; | |
4435 | } | |
4436 | return 0; | |
4437 | } | |
4438 | ||
4439 | /* range checks */ | |
4440 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4441 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4442 | ||
4443 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4444 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4445 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4446 | "size is out of scaler range\n", | |
4447 | intel_plane ? "PLANE" : "CRTC", | |
4448 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4449 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4450 | return -EINVAL; | |
4451 | } | |
4452 | ||
4453 | /* check colorkey */ | |
4454 | if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { | |
4455 | DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", | |
4456 | intel_plane->base.base.id); | |
4457 | return -EINVAL; | |
4458 | } | |
4459 | ||
4460 | /* Check src format */ | |
4461 | if (intel_plane) { | |
4462 | switch (fb->pixel_format) { | |
4463 | case DRM_FORMAT_RGB565: | |
4464 | case DRM_FORMAT_XBGR8888: | |
4465 | case DRM_FORMAT_XRGB8888: | |
4466 | case DRM_FORMAT_ABGR8888: | |
4467 | case DRM_FORMAT_ARGB8888: | |
4468 | case DRM_FORMAT_XRGB2101010: | |
4469 | case DRM_FORMAT_ARGB2101010: | |
4470 | case DRM_FORMAT_XBGR2101010: | |
4471 | case DRM_FORMAT_ABGR2101010: | |
4472 | case DRM_FORMAT_YUYV: | |
4473 | case DRM_FORMAT_YVYU: | |
4474 | case DRM_FORMAT_UYVY: | |
4475 | case DRM_FORMAT_VYUY: | |
4476 | break; | |
4477 | default: | |
4478 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4479 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4480 | return -EINVAL; | |
4481 | } | |
4482 | } | |
4483 | ||
4484 | /* mark this plane as a scaler user in crtc_state */ | |
4485 | scaler_state->scaler_users |= (1 << idx); | |
4486 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4487 | "crtc_state = %p scaler_users = 0x%x\n", | |
4488 | intel_plane ? "PLANE" : "CRTC", | |
4489 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4490 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4491 | return 0; | |
4492 | } | |
4493 | ||
4494 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4495 | { |
4496 | struct drm_device *dev = crtc->base.dev; | |
4497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4498 | int pipe = crtc->pipe; | |
a1b2278e CK |
4499 | struct intel_crtc_scaler_state *scaler_state = |
4500 | &crtc->config->scaler_state; | |
4501 | ||
4502 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4503 | ||
4504 | /* To update pfit, first update scaler state */ | |
4505 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4506 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4507 | skl_detach_scalers(crtc); | |
4508 | if (!enable) | |
4509 | return; | |
bd2e244f | 4510 | |
6e3c9717 | 4511 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4512 | int id; |
4513 | ||
4514 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4515 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4516 | return; | |
4517 | } | |
4518 | ||
4519 | id = scaler_state->scaler_id; | |
4520 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4521 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4522 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4523 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4524 | ||
4525 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4526 | } |
4527 | } | |
4528 | ||
b074cec8 JB |
4529 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4530 | { | |
4531 | struct drm_device *dev = crtc->base.dev; | |
4532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4533 | int pipe = crtc->pipe; | |
4534 | ||
6e3c9717 | 4535 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4536 | /* Force use of hard-coded filter coefficients |
4537 | * as some pre-programmed values are broken, | |
4538 | * e.g. x201. | |
4539 | */ | |
4540 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4541 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4542 | PF_PIPE_SEL_IVB(pipe)); | |
4543 | else | |
4544 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4545 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4546 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4547 | } |
4548 | } | |
4549 | ||
4a3b8769 | 4550 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4551 | { |
4552 | struct drm_device *dev = crtc->dev; | |
4553 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4554 | struct drm_plane *plane; |
bb53d4ae VS |
4555 | struct intel_plane *intel_plane; |
4556 | ||
af2b653b MR |
4557 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4558 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4559 | if (intel_plane->pipe == pipe) |
4560 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4561 | } |
bb53d4ae VS |
4562 | } |
4563 | ||
0d703d4e MR |
4564 | /* |
4565 | * Disable a plane internally without actually modifying the plane's state. | |
4566 | * This will allow us to easily restore the plane later by just reprogramming | |
4567 | * its state. | |
4568 | */ | |
4569 | static void disable_plane_internal(struct drm_plane *plane) | |
4570 | { | |
4571 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4572 | struct drm_plane_state *state = | |
4573 | plane->funcs->atomic_duplicate_state(plane); | |
4574 | struct intel_plane_state *intel_state = to_intel_plane_state(state); | |
4575 | ||
4576 | intel_state->visible = false; | |
4577 | intel_plane->commit_plane(plane, intel_state); | |
4578 | ||
4579 | intel_plane_destroy_state(plane, state); | |
4580 | } | |
4581 | ||
4a3b8769 | 4582 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4583 | { |
4584 | struct drm_device *dev = crtc->dev; | |
4585 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4586 | struct drm_plane *plane; |
bb53d4ae VS |
4587 | struct intel_plane *intel_plane; |
4588 | ||
af2b653b MR |
4589 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4590 | intel_plane = to_intel_plane(plane); | |
0d703d4e MR |
4591 | if (plane->fb && intel_plane->pipe == pipe) |
4592 | disable_plane_internal(plane); | |
af2b653b | 4593 | } |
bb53d4ae VS |
4594 | } |
4595 | ||
20bc8673 | 4596 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4597 | { |
cea165c3 VS |
4598 | struct drm_device *dev = crtc->base.dev; |
4599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4600 | |
6e3c9717 | 4601 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4602 | return; |
4603 | ||
cea165c3 VS |
4604 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4605 | intel_wait_for_vblank(dev, crtc->pipe); | |
4606 | ||
d77e4531 | 4607 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4608 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4609 | mutex_lock(&dev_priv->rps.hw_lock); |
4610 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4611 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4612 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4613 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4614 | * mailbox." Moreover, the mailbox may return a bogus state, |
4615 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4616 | */ |
4617 | } else { | |
4618 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4619 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4620 | * is essentially intel_wait_for_vblank. If we don't have this | |
4621 | * and don't wait for vblanks until the end of crtc_enable, then | |
4622 | * the HW state readout code will complain that the expected | |
4623 | * IPS_CTL value is not the one we read. */ | |
4624 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4625 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4626 | } | |
d77e4531 PZ |
4627 | } |
4628 | ||
20bc8673 | 4629 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4630 | { |
4631 | struct drm_device *dev = crtc->base.dev; | |
4632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4633 | ||
6e3c9717 | 4634 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4635 | return; |
4636 | ||
4637 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4638 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4639 | mutex_lock(&dev_priv->rps.hw_lock); |
4640 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4641 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4642 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4643 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4644 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4645 | } else { |
2a114cc1 | 4646 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4647 | POSTING_READ(IPS_CTL); |
4648 | } | |
d77e4531 PZ |
4649 | |
4650 | /* We need to wait for a vblank before we can disable the plane. */ | |
4651 | intel_wait_for_vblank(dev, crtc->pipe); | |
4652 | } | |
4653 | ||
4654 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4655 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4656 | { | |
4657 | struct drm_device *dev = crtc->dev; | |
4658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4659 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4660 | enum pipe pipe = intel_crtc->pipe; | |
4661 | int palreg = PALETTE(pipe); | |
4662 | int i; | |
4663 | bool reenable_ips = false; | |
4664 | ||
4665 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4666 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4667 | return; |
4668 | ||
4669 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4670 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4671 | assert_dsi_pll_enabled(dev_priv); |
4672 | else | |
4673 | assert_pll_enabled(dev_priv, pipe); | |
4674 | } | |
4675 | ||
4676 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4677 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4678 | palreg = LGC_PALETTE(pipe); |
4679 | ||
4680 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4681 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4682 | */ | |
6e3c9717 | 4683 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4684 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4685 | GAMMA_MODE_MODE_SPLIT)) { | |
4686 | hsw_disable_ips(intel_crtc); | |
4687 | reenable_ips = true; | |
4688 | } | |
4689 | ||
4690 | for (i = 0; i < 256; i++) { | |
4691 | I915_WRITE(palreg + 4 * i, | |
4692 | (intel_crtc->lut_r[i] << 16) | | |
4693 | (intel_crtc->lut_g[i] << 8) | | |
4694 | intel_crtc->lut_b[i]); | |
4695 | } | |
4696 | ||
4697 | if (reenable_ips) | |
4698 | hsw_enable_ips(intel_crtc); | |
4699 | } | |
4700 | ||
d3eedb1a VS |
4701 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4702 | { | |
4703 | if (!enable && intel_crtc->overlay) { | |
4704 | struct drm_device *dev = intel_crtc->base.dev; | |
4705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4706 | ||
4707 | mutex_lock(&dev->struct_mutex); | |
4708 | dev_priv->mm.interruptible = false; | |
4709 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4710 | dev_priv->mm.interruptible = true; | |
4711 | mutex_unlock(&dev->struct_mutex); | |
4712 | } | |
4713 | ||
4714 | /* Let userspace switch the overlay on again. In most cases userspace | |
4715 | * has to recompute where to put it anyway. | |
4716 | */ | |
4717 | } | |
4718 | ||
d3eedb1a | 4719 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4720 | { |
4721 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4723 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4724 | |
fdd508a6 | 4725 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4726 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4727 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4728 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4729 | |
4730 | hsw_enable_ips(intel_crtc); | |
4731 | ||
4732 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4733 | intel_fbc_update(dev); |
a5c4d7bc | 4734 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4735 | |
4736 | /* | |
4737 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4738 | * to compute the mask of flip planes precisely. For the time being | |
4739 | * consider this a flip from a NULL plane. | |
4740 | */ | |
4741 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4742 | } |
4743 | ||
d3eedb1a | 4744 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4745 | { |
4746 | struct drm_device *dev = crtc->dev; | |
4747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4748 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4749 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4750 | |
4751 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4752 | |
e35fef21 | 4753 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4754 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4755 | |
4756 | hsw_disable_ips(intel_crtc); | |
4757 | ||
d3eedb1a | 4758 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4759 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4760 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4761 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4762 | |
f99d7069 DV |
4763 | /* |
4764 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4765 | * to compute the mask of flip planes precisely. For the time being | |
4766 | * consider this a flip to a NULL plane. | |
4767 | */ | |
4768 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4769 | } |
4770 | ||
f67a559d JB |
4771 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4772 | { | |
4773 | struct drm_device *dev = crtc->dev; | |
4774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4776 | struct intel_encoder *encoder; |
f67a559d | 4777 | int pipe = intel_crtc->pipe; |
f67a559d | 4778 | |
83d65738 | 4779 | WARN_ON(!crtc->state->enable); |
08a48469 | 4780 | |
f67a559d JB |
4781 | if (intel_crtc->active) |
4782 | return; | |
4783 | ||
6e3c9717 | 4784 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4785 | intel_prepare_shared_dpll(intel_crtc); |
4786 | ||
6e3c9717 | 4787 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4788 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4789 | |
4790 | intel_set_pipe_timings(intel_crtc); | |
4791 | ||
6e3c9717 | 4792 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4793 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4794 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4795 | } |
4796 | ||
4797 | ironlake_set_pipeconf(crtc); | |
4798 | ||
f67a559d | 4799 | intel_crtc->active = true; |
8664281b | 4800 | |
a72e4c9f DV |
4801 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4802 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4803 | |
f6736a1a | 4804 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4805 | if (encoder->pre_enable) |
4806 | encoder->pre_enable(encoder); | |
f67a559d | 4807 | |
6e3c9717 | 4808 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4809 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4810 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4811 | * enabling. */ | |
88cefb6c | 4812 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4813 | } else { |
4814 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4815 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4816 | } | |
f67a559d | 4817 | |
b074cec8 | 4818 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4819 | |
9c54c0dd JB |
4820 | /* |
4821 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4822 | * clocks enabled | |
4823 | */ | |
4824 | intel_crtc_load_lut(crtc); | |
4825 | ||
f37fcc2a | 4826 | intel_update_watermarks(crtc); |
e1fdc473 | 4827 | intel_enable_pipe(intel_crtc); |
f67a559d | 4828 | |
6e3c9717 | 4829 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4830 | ironlake_pch_enable(crtc); |
c98e9dcf | 4831 | |
f9b61ff6 DV |
4832 | assert_vblank_disabled(crtc); |
4833 | drm_crtc_vblank_on(crtc); | |
4834 | ||
fa5c73b1 DV |
4835 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4836 | encoder->enable(encoder); | |
61b77ddd DV |
4837 | |
4838 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4839 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4840 | |
d3eedb1a | 4841 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4842 | } |
4843 | ||
42db64ef PZ |
4844 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4845 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4846 | { | |
f5adf94e | 4847 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4848 | } |
4849 | ||
e4916946 PZ |
4850 | /* |
4851 | * This implements the workaround described in the "notes" section of the mode | |
4852 | * set sequence documentation. When going from no pipes or single pipe to | |
4853 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4854 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4855 | */ | |
4856 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4857 | { | |
4858 | struct drm_device *dev = crtc->base.dev; | |
4859 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4860 | ||
4861 | /* We want to get the other_active_crtc only if there's only 1 other | |
4862 | * active crtc. */ | |
d3fcc808 | 4863 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4864 | if (!crtc_it->active || crtc_it == crtc) |
4865 | continue; | |
4866 | ||
4867 | if (other_active_crtc) | |
4868 | return; | |
4869 | ||
4870 | other_active_crtc = crtc_it; | |
4871 | } | |
4872 | if (!other_active_crtc) | |
4873 | return; | |
4874 | ||
4875 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4876 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4877 | } | |
4878 | ||
4f771f10 PZ |
4879 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4880 | { | |
4881 | struct drm_device *dev = crtc->dev; | |
4882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4883 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4884 | struct intel_encoder *encoder; | |
4885 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4886 | |
83d65738 | 4887 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4888 | |
4889 | if (intel_crtc->active) | |
4890 | return; | |
4891 | ||
df8ad70c DV |
4892 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4893 | intel_enable_shared_dpll(intel_crtc); | |
4894 | ||
6e3c9717 | 4895 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4896 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4897 | |
4898 | intel_set_pipe_timings(intel_crtc); | |
4899 | ||
6e3c9717 ACO |
4900 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4901 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4902 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4903 | } |
4904 | ||
6e3c9717 | 4905 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4906 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4907 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4908 | } |
4909 | ||
4910 | haswell_set_pipeconf(crtc); | |
4911 | ||
4912 | intel_set_pipe_csc(crtc); | |
4913 | ||
4f771f10 | 4914 | intel_crtc->active = true; |
8664281b | 4915 | |
a72e4c9f | 4916 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4917 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4918 | if (encoder->pre_enable) | |
4919 | encoder->pre_enable(encoder); | |
4920 | ||
6e3c9717 | 4921 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4922 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4923 | true); | |
4fe9467d ID |
4924 | dev_priv->display.fdi_link_train(crtc); |
4925 | } | |
4926 | ||
1f544388 | 4927 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4928 | |
ff6d9f55 | 4929 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 4930 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 4931 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 4932 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
4933 | else |
4934 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
4935 | |
4936 | /* | |
4937 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4938 | * clocks enabled | |
4939 | */ | |
4940 | intel_crtc_load_lut(crtc); | |
4941 | ||
1f544388 | 4942 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4943 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4944 | |
f37fcc2a | 4945 | intel_update_watermarks(crtc); |
e1fdc473 | 4946 | intel_enable_pipe(intel_crtc); |
42db64ef | 4947 | |
6e3c9717 | 4948 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4949 | lpt_pch_enable(crtc); |
4f771f10 | 4950 | |
6e3c9717 | 4951 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4952 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4953 | ||
f9b61ff6 DV |
4954 | assert_vblank_disabled(crtc); |
4955 | drm_crtc_vblank_on(crtc); | |
4956 | ||
8807e55b | 4957 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4958 | encoder->enable(encoder); |
8807e55b JN |
4959 | intel_opregion_notify_encoder(encoder, true); |
4960 | } | |
4f771f10 | 4961 | |
e4916946 PZ |
4962 | /* If we change the relative order between pipe/planes enabling, we need |
4963 | * to change the workaround. */ | |
4964 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4965 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4966 | } |
4967 | ||
3f8dce3a DV |
4968 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4969 | { | |
4970 | struct drm_device *dev = crtc->base.dev; | |
4971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4972 | int pipe = crtc->pipe; | |
4973 | ||
4974 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4975 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4976 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4977 | I915_WRITE(PF_CTL(pipe), 0); |
4978 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4979 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4980 | } | |
4981 | } | |
4982 | ||
6be4a607 JB |
4983 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4984 | { | |
4985 | struct drm_device *dev = crtc->dev; | |
4986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4987 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4988 | struct intel_encoder *encoder; |
6be4a607 | 4989 | int pipe = intel_crtc->pipe; |
5eddb70b | 4990 | u32 reg, temp; |
b52eb4dc | 4991 | |
f7abfe8b CW |
4992 | if (!intel_crtc->active) |
4993 | return; | |
4994 | ||
d3eedb1a | 4995 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4996 | |
ea9d758d DV |
4997 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4998 | encoder->disable(encoder); | |
4999 | ||
f9b61ff6 DV |
5000 | drm_crtc_vblank_off(crtc); |
5001 | assert_vblank_disabled(crtc); | |
5002 | ||
6e3c9717 | 5003 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5004 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5005 | |
575f7ab7 | 5006 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5007 | |
3f8dce3a | 5008 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5009 | |
bf49ec8c DV |
5010 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5011 | if (encoder->post_disable) | |
5012 | encoder->post_disable(encoder); | |
2c07245f | 5013 | |
6e3c9717 | 5014 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5015 | ironlake_fdi_disable(crtc); |
913d8d11 | 5016 | |
d925c59a | 5017 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5018 | |
d925c59a DV |
5019 | if (HAS_PCH_CPT(dev)) { |
5020 | /* disable TRANS_DP_CTL */ | |
5021 | reg = TRANS_DP_CTL(pipe); | |
5022 | temp = I915_READ(reg); | |
5023 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5024 | TRANS_DP_PORT_SEL_MASK); | |
5025 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5026 | I915_WRITE(reg, temp); | |
5027 | ||
5028 | /* disable DPLL_SEL */ | |
5029 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5030 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5031 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5032 | } |
e3421a18 | 5033 | |
d925c59a | 5034 | /* disable PCH DPLL */ |
e72f9fbf | 5035 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5036 | |
d925c59a DV |
5037 | ironlake_fdi_pll_disable(intel_crtc); |
5038 | } | |
6b383a7f | 5039 | |
f7abfe8b | 5040 | intel_crtc->active = false; |
46ba614c | 5041 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5042 | |
5043 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5044 | intel_fbc_update(dev); |
d1ebd816 | 5045 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5046 | } |
1b3c7a47 | 5047 | |
4f771f10 | 5048 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5049 | { |
4f771f10 PZ |
5050 | struct drm_device *dev = crtc->dev; |
5051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5053 | struct intel_encoder *encoder; |
6e3c9717 | 5054 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5055 | |
4f771f10 PZ |
5056 | if (!intel_crtc->active) |
5057 | return; | |
5058 | ||
d3eedb1a | 5059 | intel_crtc_disable_planes(crtc); |
dda9a66a | 5060 | |
8807e55b JN |
5061 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5062 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5063 | encoder->disable(encoder); |
8807e55b | 5064 | } |
4f771f10 | 5065 | |
f9b61ff6 DV |
5066 | drm_crtc_vblank_off(crtc); |
5067 | assert_vblank_disabled(crtc); | |
5068 | ||
6e3c9717 | 5069 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5070 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5071 | false); | |
575f7ab7 | 5072 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5073 | |
6e3c9717 | 5074 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5075 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5076 | ||
ad80a810 | 5077 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5078 | |
ff6d9f55 | 5079 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5080 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5081 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5082 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5083 | else |
5084 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5085 | |
1f544388 | 5086 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5087 | |
6e3c9717 | 5088 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5089 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5090 | intel_ddi_fdi_disable(crtc); |
83616634 | 5091 | } |
4f771f10 | 5092 | |
97b040aa ID |
5093 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5094 | if (encoder->post_disable) | |
5095 | encoder->post_disable(encoder); | |
5096 | ||
4f771f10 | 5097 | intel_crtc->active = false; |
46ba614c | 5098 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5099 | |
5100 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5101 | intel_fbc_update(dev); |
4f771f10 | 5102 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5103 | |
5104 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5105 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5106 | } |
5107 | ||
ee7b9f93 JB |
5108 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5109 | { | |
5110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5111 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5112 | } |
5113 | ||
6441ab5f | 5114 | |
2dd24552 JB |
5115 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5116 | { | |
5117 | struct drm_device *dev = crtc->base.dev; | |
5118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5119 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5120 | |
681a8504 | 5121 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5122 | return; |
5123 | ||
2dd24552 | 5124 | /* |
c0b03411 DV |
5125 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5126 | * according to register description and PRM. | |
2dd24552 | 5127 | */ |
c0b03411 DV |
5128 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5129 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5130 | |
b074cec8 JB |
5131 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5132 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5133 | |
5134 | /* Border color in case we don't scale up to the full screen. Black by | |
5135 | * default, change to something else for debugging. */ | |
5136 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5137 | } |
5138 | ||
d05410f9 DA |
5139 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5140 | { | |
5141 | switch (port) { | |
5142 | case PORT_A: | |
5143 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5144 | case PORT_B: | |
5145 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5146 | case PORT_C: | |
5147 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5148 | case PORT_D: | |
5149 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5150 | default: | |
5151 | WARN_ON_ONCE(1); | |
5152 | return POWER_DOMAIN_PORT_OTHER; | |
5153 | } | |
5154 | } | |
5155 | ||
77d22dca ID |
5156 | #define for_each_power_domain(domain, mask) \ |
5157 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5158 | if ((1 << (domain)) & (mask)) | |
5159 | ||
319be8ae ID |
5160 | enum intel_display_power_domain |
5161 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5162 | { | |
5163 | struct drm_device *dev = intel_encoder->base.dev; | |
5164 | struct intel_digital_port *intel_dig_port; | |
5165 | ||
5166 | switch (intel_encoder->type) { | |
5167 | case INTEL_OUTPUT_UNKNOWN: | |
5168 | /* Only DDI platforms should ever use this output type */ | |
5169 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5170 | case INTEL_OUTPUT_DISPLAYPORT: | |
5171 | case INTEL_OUTPUT_HDMI: | |
5172 | case INTEL_OUTPUT_EDP: | |
5173 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5174 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5175 | case INTEL_OUTPUT_DP_MST: |
5176 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5177 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5178 | case INTEL_OUTPUT_ANALOG: |
5179 | return POWER_DOMAIN_PORT_CRT; | |
5180 | case INTEL_OUTPUT_DSI: | |
5181 | return POWER_DOMAIN_PORT_DSI; | |
5182 | default: | |
5183 | return POWER_DOMAIN_PORT_OTHER; | |
5184 | } | |
5185 | } | |
5186 | ||
5187 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5188 | { |
319be8ae ID |
5189 | struct drm_device *dev = crtc->dev; |
5190 | struct intel_encoder *intel_encoder; | |
5191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5192 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5193 | unsigned long mask; |
5194 | enum transcoder transcoder; | |
5195 | ||
5196 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5197 | ||
5198 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5199 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5200 | if (intel_crtc->config->pch_pfit.enabled || |
5201 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5202 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5203 | ||
319be8ae ID |
5204 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5205 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5206 | ||
77d22dca ID |
5207 | return mask; |
5208 | } | |
5209 | ||
679dacd4 | 5210 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5211 | { |
679dacd4 | 5212 | struct drm_device *dev = state->dev; |
77d22dca ID |
5213 | struct drm_i915_private *dev_priv = dev->dev_private; |
5214 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5215 | struct intel_crtc *crtc; | |
5216 | ||
5217 | /* | |
5218 | * First get all needed power domains, then put all unneeded, to avoid | |
5219 | * any unnecessary toggling of the power wells. | |
5220 | */ | |
d3fcc808 | 5221 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5222 | enum intel_display_power_domain domain; |
5223 | ||
83d65738 | 5224 | if (!crtc->base.state->enable) |
77d22dca ID |
5225 | continue; |
5226 | ||
319be8ae | 5227 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5228 | |
5229 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5230 | intel_display_power_get(dev_priv, domain); | |
5231 | } | |
5232 | ||
50f6e502 | 5233 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5234 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5235 | |
d3fcc808 | 5236 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5237 | enum intel_display_power_domain domain; |
5238 | ||
5239 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5240 | intel_display_power_put(dev_priv, domain); | |
5241 | ||
5242 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5243 | } | |
5244 | ||
5245 | intel_display_set_init_power(dev_priv, false); | |
5246 | } | |
5247 | ||
f8437dd1 VK |
5248 | void broxton_set_cdclk(struct drm_device *dev, int frequency) |
5249 | { | |
5250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5251 | uint32_t divider; | |
5252 | uint32_t ratio; | |
5253 | uint32_t current_freq; | |
5254 | int ret; | |
5255 | ||
5256 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5257 | switch (frequency) { | |
5258 | case 144000: | |
5259 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5260 | ratio = BXT_DE_PLL_RATIO(60); | |
5261 | break; | |
5262 | case 288000: | |
5263 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5264 | ratio = BXT_DE_PLL_RATIO(60); | |
5265 | break; | |
5266 | case 384000: | |
5267 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5268 | ratio = BXT_DE_PLL_RATIO(60); | |
5269 | break; | |
5270 | case 576000: | |
5271 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5272 | ratio = BXT_DE_PLL_RATIO(60); | |
5273 | break; | |
5274 | case 624000: | |
5275 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5276 | ratio = BXT_DE_PLL_RATIO(65); | |
5277 | break; | |
5278 | case 19200: | |
5279 | /* | |
5280 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5281 | * to suppress GCC warning. | |
5282 | */ | |
5283 | ratio = 0; | |
5284 | divider = 0; | |
5285 | break; | |
5286 | default: | |
5287 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5288 | ||
5289 | return; | |
5290 | } | |
5291 | ||
5292 | mutex_lock(&dev_priv->rps.hw_lock); | |
5293 | /* Inform power controller of upcoming frequency change */ | |
5294 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5295 | 0x80000000); | |
5296 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5297 | ||
5298 | if (ret) { | |
5299 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5300 | ret, frequency); | |
5301 | return; | |
5302 | } | |
5303 | ||
5304 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5305 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5306 | current_freq = current_freq * 500 + 1000; | |
5307 | ||
5308 | /* | |
5309 | * DE PLL has to be disabled when | |
5310 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5311 | * - before setting to 624MHz (PLL needs toggling) | |
5312 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5313 | */ | |
5314 | if (frequency == 19200 || frequency == 624000 || | |
5315 | current_freq == 624000) { | |
5316 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5317 | /* Timeout 200us */ | |
5318 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5319 | 1)) | |
5320 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5321 | } | |
5322 | ||
5323 | if (frequency != 19200) { | |
5324 | uint32_t val; | |
5325 | ||
5326 | val = I915_READ(BXT_DE_PLL_CTL); | |
5327 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5328 | val |= ratio; | |
5329 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5330 | ||
5331 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5332 | /* Timeout 200us */ | |
5333 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5334 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5335 | ||
5336 | val = I915_READ(CDCLK_CTL); | |
5337 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5338 | val |= divider; | |
5339 | /* | |
5340 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5341 | * enable otherwise. | |
5342 | */ | |
5343 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5344 | if (frequency >= 500000) | |
5345 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5346 | ||
5347 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5348 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5349 | val |= (frequency - 1000) / 500; | |
5350 | I915_WRITE(CDCLK_CTL, val); | |
5351 | } | |
5352 | ||
5353 | mutex_lock(&dev_priv->rps.hw_lock); | |
5354 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5355 | DIV_ROUND_UP(frequency, 25000)); | |
5356 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5357 | ||
5358 | if (ret) { | |
5359 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5360 | ret, frequency); | |
5361 | return; | |
5362 | } | |
5363 | ||
5364 | dev_priv->cdclk_freq = frequency; | |
5365 | } | |
5366 | ||
5367 | void broxton_init_cdclk(struct drm_device *dev) | |
5368 | { | |
5369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5370 | uint32_t val; | |
5371 | ||
5372 | /* | |
5373 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5374 | * or else the reset will hang because there is no PCH to respond. | |
5375 | * Move the handshake programming to initialization sequence. | |
5376 | * Previously was left up to BIOS. | |
5377 | */ | |
5378 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5379 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5380 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5381 | ||
5382 | /* Enable PG1 for cdclk */ | |
5383 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5384 | ||
5385 | /* check if cd clock is enabled */ | |
5386 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5387 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5388 | return; | |
5389 | } | |
5390 | ||
5391 | /* | |
5392 | * FIXME: | |
5393 | * - The initial CDCLK needs to be read from VBT. | |
5394 | * Need to make this change after VBT has changes for BXT. | |
5395 | * - check if setting the max (or any) cdclk freq is really necessary | |
5396 | * here, it belongs to modeset time | |
5397 | */ | |
5398 | broxton_set_cdclk(dev, 624000); | |
5399 | ||
5400 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5401 | udelay(10); | |
5402 | ||
5403 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5404 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5405 | } | |
5406 | ||
5407 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5408 | { | |
5409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5410 | ||
5411 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5412 | udelay(10); | |
5413 | ||
5414 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5415 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5416 | ||
5417 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5418 | broxton_set_cdclk(dev, 19200); | |
5419 | ||
5420 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5421 | } | |
5422 | ||
dfcab17e | 5423 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5424 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5425 | { |
586f49dc | 5426 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5427 | |
586f49dc JB |
5428 | /* Obtain SKU information */ |
5429 | mutex_lock(&dev_priv->dpio_lock); | |
5430 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5431 | CCK_FUSE_HPLL_FREQ_MASK; | |
5432 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5433 | |
dfcab17e | 5434 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5435 | } |
5436 | ||
f8bf63fd VS |
5437 | static void vlv_update_cdclk(struct drm_device *dev) |
5438 | { | |
5439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5440 | ||
164dfd28 | 5441 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
43dc52c3 | 5442 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
164dfd28 | 5443 | dev_priv->cdclk_freq); |
f8bf63fd VS |
5444 | |
5445 | /* | |
5446 | * Program the gmbus_freq based on the cdclk frequency. | |
5447 | * BSpec erroneously claims we should aim for 4MHz, but | |
5448 | * in fact 1MHz is the correct frequency. | |
5449 | */ | |
164dfd28 | 5450 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
f8bf63fd VS |
5451 | } |
5452 | ||
30a970c6 JB |
5453 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5454 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5455 | { | |
5456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5457 | u32 val, cmd; | |
5458 | ||
164dfd28 VK |
5459 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5460 | != dev_priv->cdclk_freq); | |
d60c4473 | 5461 | |
dfcab17e | 5462 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5463 | cmd = 2; |
dfcab17e | 5464 | else if (cdclk == 266667) |
30a970c6 JB |
5465 | cmd = 1; |
5466 | else | |
5467 | cmd = 0; | |
5468 | ||
5469 | mutex_lock(&dev_priv->rps.hw_lock); | |
5470 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5471 | val &= ~DSPFREQGUAR_MASK; | |
5472 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5473 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5474 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5475 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5476 | 50)) { | |
5477 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5478 | } | |
5479 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5480 | ||
dfcab17e | 5481 | if (cdclk == 400000) { |
6bcda4f0 | 5482 | u32 divider; |
30a970c6 | 5483 | |
6bcda4f0 | 5484 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5485 | |
5486 | mutex_lock(&dev_priv->dpio_lock); | |
5487 | /* adjust cdclk divider */ | |
5488 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5489 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5490 | val |= divider; |
5491 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5492 | |
5493 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5494 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5495 | 50)) | |
5496 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5497 | mutex_unlock(&dev_priv->dpio_lock); |
5498 | } | |
5499 | ||
5500 | mutex_lock(&dev_priv->dpio_lock); | |
5501 | /* adjust self-refresh exit latency value */ | |
5502 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5503 | val &= ~0x7f; | |
5504 | ||
5505 | /* | |
5506 | * For high bandwidth configs, we set a higher latency in the bunit | |
5507 | * so that the core display fetch happens in time to avoid underruns. | |
5508 | */ | |
dfcab17e | 5509 | if (cdclk == 400000) |
30a970c6 JB |
5510 | val |= 4500 / 250; /* 4.5 usec */ |
5511 | else | |
5512 | val |= 3000 / 250; /* 3.0 usec */ | |
5513 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5514 | mutex_unlock(&dev_priv->dpio_lock); | |
5515 | ||
f8bf63fd | 5516 | vlv_update_cdclk(dev); |
30a970c6 JB |
5517 | } |
5518 | ||
383c5a6a VS |
5519 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5520 | { | |
5521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5522 | u32 val, cmd; | |
5523 | ||
164dfd28 VK |
5524 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5525 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5526 | |
5527 | switch (cdclk) { | |
383c5a6a VS |
5528 | case 333333: |
5529 | case 320000: | |
383c5a6a | 5530 | case 266667: |
383c5a6a | 5531 | case 200000: |
383c5a6a VS |
5532 | break; |
5533 | default: | |
5f77eeb0 | 5534 | MISSING_CASE(cdclk); |
383c5a6a VS |
5535 | return; |
5536 | } | |
5537 | ||
9d0d3fda VS |
5538 | /* |
5539 | * Specs are full of misinformation, but testing on actual | |
5540 | * hardware has shown that we just need to write the desired | |
5541 | * CCK divider into the Punit register. | |
5542 | */ | |
5543 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5544 | ||
383c5a6a VS |
5545 | mutex_lock(&dev_priv->rps.hw_lock); |
5546 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5547 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5548 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5549 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5550 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5551 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5552 | 50)) { | |
5553 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5554 | } | |
5555 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5556 | ||
5557 | vlv_update_cdclk(dev); | |
5558 | } | |
5559 | ||
30a970c6 JB |
5560 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5561 | int max_pixclk) | |
5562 | { | |
6bcda4f0 | 5563 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5564 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5565 | |
30a970c6 JB |
5566 | /* |
5567 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5568 | * 200MHz | |
5569 | * 267MHz | |
29dc7ef3 | 5570 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5571 | * 400MHz (VLV only) |
5572 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5573 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5574 | * |
5575 | * We seem to get an unstable or solid color picture at 200MHz. | |
5576 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5577 | * are off. | |
30a970c6 | 5578 | */ |
6cca3195 VS |
5579 | if (!IS_CHERRYVIEW(dev_priv) && |
5580 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5581 | return 400000; |
6cca3195 | 5582 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5583 | return freq_320; |
e37c67a1 | 5584 | else if (max_pixclk > 0) |
dfcab17e | 5585 | return 266667; |
e37c67a1 VS |
5586 | else |
5587 | return 200000; | |
30a970c6 JB |
5588 | } |
5589 | ||
f8437dd1 VK |
5590 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5591 | int max_pixclk) | |
5592 | { | |
5593 | /* | |
5594 | * FIXME: | |
5595 | * - remove the guardband, it's not needed on BXT | |
5596 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5597 | */ | |
5598 | if (max_pixclk > 576000*9/10) | |
5599 | return 624000; | |
5600 | else if (max_pixclk > 384000*9/10) | |
5601 | return 576000; | |
5602 | else if (max_pixclk > 288000*9/10) | |
5603 | return 384000; | |
5604 | else if (max_pixclk > 144000*9/10) | |
5605 | return 288000; | |
5606 | else | |
5607 | return 144000; | |
5608 | } | |
5609 | ||
2f2d7aa1 | 5610 | /* compute the max pixel clock for new configuration */ |
304603f4 | 5611 | static int intel_mode_max_pixclk(struct drm_atomic_state *state) |
30a970c6 | 5612 | { |
304603f4 | 5613 | struct drm_device *dev = state->dev; |
30a970c6 | 5614 | struct intel_crtc *intel_crtc; |
304603f4 | 5615 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5616 | int max_pixclk = 0; |
5617 | ||
d3fcc808 | 5618 | for_each_intel_crtc(dev, intel_crtc) { |
304603f4 ACO |
5619 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
5620 | if (IS_ERR(crtc_state)) | |
5621 | return PTR_ERR(crtc_state); | |
5622 | ||
5623 | if (!crtc_state->base.enable) | |
5624 | continue; | |
5625 | ||
5626 | max_pixclk = max(max_pixclk, | |
5627 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5628 | } |
5629 | ||
5630 | return max_pixclk; | |
5631 | } | |
5632 | ||
304603f4 | 5633 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, |
2f2d7aa1 | 5634 | unsigned *prepare_pipes) |
30a970c6 | 5635 | { |
304603f4 | 5636 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
30a970c6 | 5637 | struct intel_crtc *intel_crtc; |
304603f4 | 5638 | int max_pixclk = intel_mode_max_pixclk(state); |
f8437dd1 | 5639 | int cdclk; |
304603f4 ACO |
5640 | |
5641 | if (max_pixclk < 0) | |
5642 | return max_pixclk; | |
30a970c6 | 5643 | |
f8437dd1 VK |
5644 | if (IS_VALLEYVIEW(dev_priv)) |
5645 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5646 | else | |
5647 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5648 | ||
5649 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5650 | return 0; |
30a970c6 | 5651 | |
2f2d7aa1 | 5652 | /* disable/enable all currently active pipes while we change cdclk */ |
304603f4 | 5653 | for_each_intel_crtc(state->dev, intel_crtc) |
83d65738 | 5654 | if (intel_crtc->base.state->enable) |
30a970c6 | 5655 | *prepare_pipes |= (1 << intel_crtc->pipe); |
304603f4 ACO |
5656 | |
5657 | return 0; | |
30a970c6 JB |
5658 | } |
5659 | ||
1e69cd74 VS |
5660 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5661 | { | |
5662 | unsigned int credits, default_credits; | |
5663 | ||
5664 | if (IS_CHERRYVIEW(dev_priv)) | |
5665 | default_credits = PFI_CREDIT(12); | |
5666 | else | |
5667 | default_credits = PFI_CREDIT(8); | |
5668 | ||
164dfd28 | 5669 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5670 | /* CHV suggested value is 31 or 63 */ |
5671 | if (IS_CHERRYVIEW(dev_priv)) | |
5672 | credits = PFI_CREDIT_31; | |
5673 | else | |
5674 | credits = PFI_CREDIT(15); | |
5675 | } else { | |
5676 | credits = default_credits; | |
5677 | } | |
5678 | ||
5679 | /* | |
5680 | * WA - write default credits before re-programming | |
5681 | * FIXME: should we also set the resend bit here? | |
5682 | */ | |
5683 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5684 | default_credits); | |
5685 | ||
5686 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5687 | credits | PFI_CREDIT_RESEND); | |
5688 | ||
5689 | /* | |
5690 | * FIXME is this guaranteed to clear | |
5691 | * immediately or should we poll for it? | |
5692 | */ | |
5693 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5694 | } | |
5695 | ||
679dacd4 | 5696 | static void valleyview_modeset_global_resources(struct drm_atomic_state *state) |
30a970c6 | 5697 | { |
679dacd4 | 5698 | struct drm_device *dev = state->dev; |
30a970c6 | 5699 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 ACO |
5700 | int max_pixclk = intel_mode_max_pixclk(state); |
5701 | int req_cdclk; | |
5702 | ||
5703 | /* The only reason this can fail is if we fail to add the crtc_state | |
5704 | * to the atomic state. But that can't happen since the call to | |
5705 | * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which | |
5706 | * can't have failed otherwise the mode set would be aborted) added all | |
5707 | * the states already. */ | |
5708 | if (WARN_ON(max_pixclk < 0)) | |
5709 | return; | |
5710 | ||
5711 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
30a970c6 | 5712 | |
164dfd28 | 5713 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
5714 | /* |
5715 | * FIXME: We can end up here with all power domains off, yet | |
5716 | * with a CDCLK frequency other than the minimum. To account | |
5717 | * for this take the PIPE-A power domain, which covers the HW | |
5718 | * blocks needed for the following programming. This can be | |
5719 | * removed once it's guaranteed that we get here either with | |
5720 | * the minimum CDCLK set, or the required power domains | |
5721 | * enabled. | |
5722 | */ | |
5723 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5724 | ||
383c5a6a VS |
5725 | if (IS_CHERRYVIEW(dev)) |
5726 | cherryview_set_cdclk(dev, req_cdclk); | |
5727 | else | |
5728 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5729 | |
1e69cd74 VS |
5730 | vlv_program_pfi_credits(dev_priv); |
5731 | ||
738c05c0 | 5732 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5733 | } |
30a970c6 JB |
5734 | } |
5735 | ||
89b667f8 JB |
5736 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5737 | { | |
5738 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5739 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5741 | struct intel_encoder *encoder; | |
5742 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5743 | bool is_dsi; |
89b667f8 | 5744 | |
83d65738 | 5745 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5746 | |
5747 | if (intel_crtc->active) | |
5748 | return; | |
5749 | ||
409ee761 | 5750 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5751 | |
1ae0d137 VS |
5752 | if (!is_dsi) { |
5753 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5754 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5755 | else |
6e3c9717 | 5756 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5757 | } |
5b18e57c | 5758 | |
6e3c9717 | 5759 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5760 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5761 | |
5762 | intel_set_pipe_timings(intel_crtc); | |
5763 | ||
c14b0485 VS |
5764 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5766 | ||
5767 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5768 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5769 | } | |
5770 | ||
5b18e57c DV |
5771 | i9xx_set_pipeconf(intel_crtc); |
5772 | ||
89b667f8 | 5773 | intel_crtc->active = true; |
89b667f8 | 5774 | |
a72e4c9f | 5775 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5776 | |
89b667f8 JB |
5777 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5778 | if (encoder->pre_pll_enable) | |
5779 | encoder->pre_pll_enable(encoder); | |
5780 | ||
9d556c99 CML |
5781 | if (!is_dsi) { |
5782 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5783 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5784 | else |
6e3c9717 | 5785 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5786 | } |
89b667f8 JB |
5787 | |
5788 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5789 | if (encoder->pre_enable) | |
5790 | encoder->pre_enable(encoder); | |
5791 | ||
2dd24552 JB |
5792 | i9xx_pfit_enable(intel_crtc); |
5793 | ||
63cbb074 VS |
5794 | intel_crtc_load_lut(crtc); |
5795 | ||
f37fcc2a | 5796 | intel_update_watermarks(crtc); |
e1fdc473 | 5797 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5798 | |
4b3a9526 VS |
5799 | assert_vblank_disabled(crtc); |
5800 | drm_crtc_vblank_on(crtc); | |
5801 | ||
f9b61ff6 DV |
5802 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5803 | encoder->enable(encoder); | |
5804 | ||
9ab0460b | 5805 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5806 | |
56b80e1f | 5807 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5808 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5809 | } |
5810 | ||
f13c2ef3 DV |
5811 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5812 | { | |
5813 | struct drm_device *dev = crtc->base.dev; | |
5814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5815 | ||
6e3c9717 ACO |
5816 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5817 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5818 | } |
5819 | ||
0b8765c6 | 5820 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5821 | { |
5822 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5823 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5825 | struct intel_encoder *encoder; |
79e53945 | 5826 | int pipe = intel_crtc->pipe; |
79e53945 | 5827 | |
83d65738 | 5828 | WARN_ON(!crtc->state->enable); |
08a48469 | 5829 | |
f7abfe8b CW |
5830 | if (intel_crtc->active) |
5831 | return; | |
5832 | ||
f13c2ef3 DV |
5833 | i9xx_set_pll_dividers(intel_crtc); |
5834 | ||
6e3c9717 | 5835 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5836 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5837 | |
5838 | intel_set_pipe_timings(intel_crtc); | |
5839 | ||
5b18e57c DV |
5840 | i9xx_set_pipeconf(intel_crtc); |
5841 | ||
f7abfe8b | 5842 | intel_crtc->active = true; |
6b383a7f | 5843 | |
4a3436e8 | 5844 | if (!IS_GEN2(dev)) |
a72e4c9f | 5845 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5846 | |
9d6d9f19 MK |
5847 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5848 | if (encoder->pre_enable) | |
5849 | encoder->pre_enable(encoder); | |
5850 | ||
f6736a1a DV |
5851 | i9xx_enable_pll(intel_crtc); |
5852 | ||
2dd24552 JB |
5853 | i9xx_pfit_enable(intel_crtc); |
5854 | ||
63cbb074 VS |
5855 | intel_crtc_load_lut(crtc); |
5856 | ||
f37fcc2a | 5857 | intel_update_watermarks(crtc); |
e1fdc473 | 5858 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5859 | |
4b3a9526 VS |
5860 | assert_vblank_disabled(crtc); |
5861 | drm_crtc_vblank_on(crtc); | |
5862 | ||
f9b61ff6 DV |
5863 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5864 | encoder->enable(encoder); | |
5865 | ||
9ab0460b | 5866 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5867 | |
4a3436e8 VS |
5868 | /* |
5869 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5870 | * So don't enable underrun reporting before at least some planes | |
5871 | * are enabled. | |
5872 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5873 | * but leave the pipe running. | |
5874 | */ | |
5875 | if (IS_GEN2(dev)) | |
a72e4c9f | 5876 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5877 | |
56b80e1f | 5878 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5879 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5880 | } |
79e53945 | 5881 | |
87476d63 DV |
5882 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5883 | { | |
5884 | struct drm_device *dev = crtc->base.dev; | |
5885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5886 | |
6e3c9717 | 5887 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5888 | return; |
87476d63 | 5889 | |
328d8e82 | 5890 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5891 | |
328d8e82 DV |
5892 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5893 | I915_READ(PFIT_CONTROL)); | |
5894 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5895 | } |
5896 | ||
0b8765c6 JB |
5897 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5898 | { | |
5899 | struct drm_device *dev = crtc->dev; | |
5900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5902 | struct intel_encoder *encoder; |
0b8765c6 | 5903 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5904 | |
f7abfe8b CW |
5905 | if (!intel_crtc->active) |
5906 | return; | |
5907 | ||
4a3436e8 VS |
5908 | /* |
5909 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5910 | * So diasble underrun reporting before all the planes get disabled. | |
5911 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5912 | * but leave the pipe running. | |
5913 | */ | |
5914 | if (IS_GEN2(dev)) | |
a72e4c9f | 5915 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5916 | |
564ed191 ID |
5917 | /* |
5918 | * Vblank time updates from the shadow to live plane control register | |
5919 | * are blocked if the memory self-refresh mode is active at that | |
5920 | * moment. So to make sure the plane gets truly disabled, disable | |
5921 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5922 | * will be checked/applied by the HW only at the next frame start | |
5923 | * event which is after the vblank start event, so we need to have a | |
5924 | * wait-for-vblank between disabling the plane and the pipe. | |
5925 | */ | |
5926 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5927 | intel_crtc_disable_planes(crtc); |
5928 | ||
6304cd91 VS |
5929 | /* |
5930 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5931 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5932 | * We also need to wait on all gmch platforms because of the |
5933 | * self-refresh mode constraint explained above. | |
6304cd91 | 5934 | */ |
564ed191 | 5935 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5936 | |
4b3a9526 VS |
5937 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5938 | encoder->disable(encoder); | |
5939 | ||
f9b61ff6 DV |
5940 | drm_crtc_vblank_off(crtc); |
5941 | assert_vblank_disabled(crtc); | |
5942 | ||
575f7ab7 | 5943 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5944 | |
87476d63 | 5945 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5946 | |
89b667f8 JB |
5947 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5948 | if (encoder->post_disable) | |
5949 | encoder->post_disable(encoder); | |
5950 | ||
409ee761 | 5951 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5952 | if (IS_CHERRYVIEW(dev)) |
5953 | chv_disable_pll(dev_priv, pipe); | |
5954 | else if (IS_VALLEYVIEW(dev)) | |
5955 | vlv_disable_pll(dev_priv, pipe); | |
5956 | else | |
1c4e0274 | 5957 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5958 | } |
0b8765c6 | 5959 | |
4a3436e8 | 5960 | if (!IS_GEN2(dev)) |
a72e4c9f | 5961 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5962 | |
f7abfe8b | 5963 | intel_crtc->active = false; |
46ba614c | 5964 | intel_update_watermarks(crtc); |
f37fcc2a | 5965 | |
efa9624e | 5966 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5967 | intel_fbc_update(dev); |
efa9624e | 5968 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5969 | } |
5970 | ||
ee7b9f93 JB |
5971 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5972 | { | |
5973 | } | |
5974 | ||
b04c5bd6 BF |
5975 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5976 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5977 | { |
5978 | struct drm_device *dev = crtc->dev; | |
5979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5981 | enum intel_display_power_domain domain; |
5982 | unsigned long domains; | |
976f8a20 | 5983 | |
0e572fe7 DV |
5984 | if (enable) { |
5985 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5986 | domains = get_crtc_power_domains(crtc); |
5987 | for_each_power_domain(domain, domains) | |
5988 | intel_display_power_get(dev_priv, domain); | |
5989 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5990 | |
5991 | dev_priv->display.crtc_enable(crtc); | |
5992 | } | |
5993 | } else { | |
5994 | if (intel_crtc->active) { | |
5995 | dev_priv->display.crtc_disable(crtc); | |
5996 | ||
e1e9fb84 DV |
5997 | domains = intel_crtc->enabled_power_domains; |
5998 | for_each_power_domain(domain, domains) | |
5999 | intel_display_power_put(dev_priv, domain); | |
6000 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
6001 | } |
6002 | } | |
b04c5bd6 BF |
6003 | } |
6004 | ||
6005 | /** | |
6006 | * Sets the power management mode of the pipe and plane. | |
6007 | */ | |
6008 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6009 | { | |
6010 | struct drm_device *dev = crtc->dev; | |
6011 | struct intel_encoder *intel_encoder; | |
6012 | bool enable = false; | |
6013 | ||
6014 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6015 | enable |= intel_encoder->connectors_active; | |
6016 | ||
6017 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
6018 | } |
6019 | ||
cdd59983 CW |
6020 | static void intel_crtc_disable(struct drm_crtc *crtc) |
6021 | { | |
cdd59983 | 6022 | struct drm_device *dev = crtc->dev; |
976f8a20 | 6023 | struct drm_connector *connector; |
ee7b9f93 | 6024 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 6025 | |
976f8a20 | 6026 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 6027 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
6028 | |
6029 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
6030 | dev_priv->display.off(crtc); |
6031 | ||
70a101f8 | 6032 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
6033 | |
6034 | /* Update computed state. */ | |
6035 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6036 | if (!connector->encoder || !connector->encoder->crtc) | |
6037 | continue; | |
6038 | ||
6039 | if (connector->encoder->crtc != crtc) | |
6040 | continue; | |
6041 | ||
6042 | connector->dpms = DRM_MODE_DPMS_OFF; | |
6043 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
6044 | } |
6045 | } | |
6046 | ||
ea5b213a | 6047 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6048 | { |
4ef69c7a | 6049 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6050 | |
ea5b213a CW |
6051 | drm_encoder_cleanup(encoder); |
6052 | kfree(intel_encoder); | |
7e7d76c3 JB |
6053 | } |
6054 | ||
9237329d | 6055 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6056 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6057 | * state of the entire output pipe. */ | |
9237329d | 6058 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6059 | { |
5ab432ef DV |
6060 | if (mode == DRM_MODE_DPMS_ON) { |
6061 | encoder->connectors_active = true; | |
6062 | ||
b2cabb0e | 6063 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6064 | } else { |
6065 | encoder->connectors_active = false; | |
6066 | ||
b2cabb0e | 6067 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6068 | } |
79e53945 JB |
6069 | } |
6070 | ||
0a91ca29 DV |
6071 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6072 | * internal consistency). */ | |
b980514c | 6073 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6074 | { |
0a91ca29 DV |
6075 | if (connector->get_hw_state(connector)) { |
6076 | struct intel_encoder *encoder = connector->encoder; | |
6077 | struct drm_crtc *crtc; | |
6078 | bool encoder_enabled; | |
6079 | enum pipe pipe; | |
6080 | ||
6081 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6082 | connector->base.base.id, | |
c23cc417 | 6083 | connector->base.name); |
0a91ca29 | 6084 | |
0e32b39c DA |
6085 | /* there is no real hw state for MST connectors */ |
6086 | if (connector->mst_port) | |
6087 | return; | |
6088 | ||
e2c719b7 | 6089 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6090 | "wrong connector dpms state\n"); |
e2c719b7 | 6091 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6092 | "active connector not linked to encoder\n"); |
0a91ca29 | 6093 | |
36cd7444 | 6094 | if (encoder) { |
e2c719b7 | 6095 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6096 | "encoder->connectors_active not set\n"); |
6097 | ||
6098 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6099 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6100 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6101 | return; |
0a91ca29 | 6102 | |
36cd7444 | 6103 | crtc = encoder->base.crtc; |
0a91ca29 | 6104 | |
83d65738 MR |
6105 | I915_STATE_WARN(!crtc->state->enable, |
6106 | "crtc not enabled\n"); | |
e2c719b7 RC |
6107 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6108 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6109 | "encoder active on the wrong pipe\n"); |
6110 | } | |
0a91ca29 | 6111 | } |
79e53945 JB |
6112 | } |
6113 | ||
9bdbd0b9 ACO |
6114 | int intel_connector_init(struct intel_connector *connector) |
6115 | { | |
6116 | struct drm_connector_state *connector_state; | |
6117 | ||
6118 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6119 | if (!connector_state) | |
6120 | return -ENOMEM; | |
6121 | ||
6122 | connector->base.state = connector_state; | |
6123 | return 0; | |
6124 | } | |
6125 | ||
6126 | struct intel_connector *intel_connector_alloc(void) | |
6127 | { | |
6128 | struct intel_connector *connector; | |
6129 | ||
6130 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6131 | if (!connector) | |
6132 | return NULL; | |
6133 | ||
6134 | if (intel_connector_init(connector) < 0) { | |
6135 | kfree(connector); | |
6136 | return NULL; | |
6137 | } | |
6138 | ||
6139 | return connector; | |
6140 | } | |
6141 | ||
5ab432ef DV |
6142 | /* Even simpler default implementation, if there's really no special case to |
6143 | * consider. */ | |
6144 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6145 | { |
5ab432ef DV |
6146 | /* All the simple cases only support two dpms states. */ |
6147 | if (mode != DRM_MODE_DPMS_ON) | |
6148 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6149 | |
5ab432ef DV |
6150 | if (mode == connector->dpms) |
6151 | return; | |
6152 | ||
6153 | connector->dpms = mode; | |
6154 | ||
6155 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6156 | if (connector->encoder) |
6157 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6158 | |
b980514c | 6159 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6160 | } |
6161 | ||
f0947c37 DV |
6162 | /* Simple connector->get_hw_state implementation for encoders that support only |
6163 | * one connector and no cloning and hence the encoder state determines the state | |
6164 | * of the connector. */ | |
6165 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6166 | { |
24929352 | 6167 | enum pipe pipe = 0; |
f0947c37 | 6168 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6169 | |
f0947c37 | 6170 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6171 | } |
6172 | ||
6d293983 | 6173 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6174 | { |
6d293983 ACO |
6175 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6176 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6177 | |
6178 | return 0; | |
6179 | } | |
6180 | ||
6d293983 | 6181 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6182 | struct intel_crtc_state *pipe_config) |
1857e1da | 6183 | { |
6d293983 ACO |
6184 | struct drm_atomic_state *state = pipe_config->base.state; |
6185 | struct intel_crtc *other_crtc; | |
6186 | struct intel_crtc_state *other_crtc_state; | |
6187 | ||
1857e1da DV |
6188 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6189 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6190 | if (pipe_config->fdi_lanes > 4) { | |
6191 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6192 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6193 | return -EINVAL; |
1857e1da DV |
6194 | } |
6195 | ||
bafb6553 | 6196 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6197 | if (pipe_config->fdi_lanes > 2) { |
6198 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6199 | pipe_config->fdi_lanes); | |
6d293983 | 6200 | return -EINVAL; |
1857e1da | 6201 | } else { |
6d293983 | 6202 | return 0; |
1857e1da DV |
6203 | } |
6204 | } | |
6205 | ||
6206 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6207 | return 0; |
1857e1da DV |
6208 | |
6209 | /* Ivybridge 3 pipe is really complicated */ | |
6210 | switch (pipe) { | |
6211 | case PIPE_A: | |
6d293983 | 6212 | return 0; |
1857e1da | 6213 | case PIPE_B: |
6d293983 ACO |
6214 | if (pipe_config->fdi_lanes <= 2) |
6215 | return 0; | |
6216 | ||
6217 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6218 | other_crtc_state = | |
6219 | intel_atomic_get_crtc_state(state, other_crtc); | |
6220 | if (IS_ERR(other_crtc_state)) | |
6221 | return PTR_ERR(other_crtc_state); | |
6222 | ||
6223 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6224 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6225 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6226 | return -EINVAL; |
1857e1da | 6227 | } |
6d293983 | 6228 | return 0; |
1857e1da | 6229 | case PIPE_C: |
251cc67c VS |
6230 | if (pipe_config->fdi_lanes > 2) { |
6231 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6232 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6233 | return -EINVAL; |
251cc67c | 6234 | } |
6d293983 ACO |
6235 | |
6236 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6237 | other_crtc_state = | |
6238 | intel_atomic_get_crtc_state(state, other_crtc); | |
6239 | if (IS_ERR(other_crtc_state)) | |
6240 | return PTR_ERR(other_crtc_state); | |
6241 | ||
6242 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6243 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6244 | return -EINVAL; |
1857e1da | 6245 | } |
6d293983 | 6246 | return 0; |
1857e1da DV |
6247 | default: |
6248 | BUG(); | |
6249 | } | |
6250 | } | |
6251 | ||
e29c22c0 DV |
6252 | #define RETRY 1 |
6253 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6254 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6255 | { |
1857e1da | 6256 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6257 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6258 | int lane, link_bw, fdi_dotclock, ret; |
6259 | bool needs_recompute = false; | |
877d48d5 | 6260 | |
e29c22c0 | 6261 | retry: |
877d48d5 DV |
6262 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6263 | * each output octet as 10 bits. The actual frequency | |
6264 | * is stored as a divider into a 100MHz clock, and the | |
6265 | * mode pixel clock is stored in units of 1KHz. | |
6266 | * Hence the bw of each lane in terms of the mode signal | |
6267 | * is: | |
6268 | */ | |
6269 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6270 | ||
241bfc38 | 6271 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6272 | |
2bd89a07 | 6273 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6274 | pipe_config->pipe_bpp); |
6275 | ||
6276 | pipe_config->fdi_lanes = lane; | |
6277 | ||
2bd89a07 | 6278 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6279 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6280 | |
6d293983 ACO |
6281 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6282 | intel_crtc->pipe, pipe_config); | |
6283 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6284 | pipe_config->pipe_bpp -= 2*3; |
6285 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6286 | pipe_config->pipe_bpp); | |
6287 | needs_recompute = true; | |
6288 | pipe_config->bw_constrained = true; | |
6289 | ||
6290 | goto retry; | |
6291 | } | |
6292 | ||
6293 | if (needs_recompute) | |
6294 | return RETRY; | |
6295 | ||
6d293983 | 6296 | return ret; |
877d48d5 DV |
6297 | } |
6298 | ||
42db64ef | 6299 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6300 | struct intel_crtc_state *pipe_config) |
42db64ef | 6301 | { |
d330a953 | 6302 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 6303 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 6304 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
6305 | } |
6306 | ||
a43f6e0f | 6307 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6308 | struct intel_crtc_state *pipe_config) |
79e53945 | 6309 | { |
a43f6e0f | 6310 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6311 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6312 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6313 | int ret; |
89749350 | 6314 | |
ad3a4479 | 6315 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6316 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
6317 | int clock_limit = |
6318 | dev_priv->display.get_display_clock_speed(dev); | |
6319 | ||
6320 | /* | |
6321 | * Enable pixel doubling when the dot clock | |
6322 | * is > 90% of the (display) core speed. | |
6323 | * | |
b397c96b VS |
6324 | * GDG double wide on either pipe, |
6325 | * otherwise pipe A only. | |
cf532bb2 | 6326 | */ |
b397c96b | 6327 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6328 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6329 | clock_limit *= 2; |
cf532bb2 | 6330 | pipe_config->double_wide = true; |
ad3a4479 VS |
6331 | } |
6332 | ||
241bfc38 | 6333 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6334 | return -EINVAL; |
2c07245f | 6335 | } |
89749350 | 6336 | |
1d1d0e27 VS |
6337 | /* |
6338 | * Pipe horizontal size must be even in: | |
6339 | * - DVO ganged mode | |
6340 | * - LVDS dual channel mode | |
6341 | * - Double wide pipe | |
6342 | */ | |
a93e255f | 6343 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6344 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6345 | pipe_config->pipe_src_w &= ~1; | |
6346 | ||
8693a824 DL |
6347 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6348 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6349 | */ |
6350 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6351 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6352 | return -EINVAL; |
44f46b42 | 6353 | |
f5adf94e | 6354 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6355 | hsw_compute_ips_config(crtc, pipe_config); |
6356 | ||
877d48d5 | 6357 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6358 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6359 | |
d03c93d4 CK |
6360 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6361 | * related checks called from atomic_crtc_check function */ | |
6362 | ret = 0; | |
6363 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6364 | crtc, pipe_config->base.state); | |
6365 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6366 | ||
6367 | return ret; | |
79e53945 JB |
6368 | } |
6369 | ||
1652d19e VS |
6370 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6371 | { | |
6372 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6373 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6374 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6375 | uint32_t linkrate; | |
6376 | ||
6377 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
6378 | WARN(1, "LCPLL1 not enabled\n"); | |
6379 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6380 | } | |
6381 | ||
6382 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6383 | return 540000; | |
6384 | ||
6385 | linkrate = (I915_READ(DPLL_CTRL1) & | |
6386 | DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; | |
6387 | ||
6388 | if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || | |
6389 | linkrate == DPLL_CRTL1_LINK_RATE_1080) { | |
6390 | /* vco 8640 */ | |
6391 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6392 | case CDCLK_FREQ_450_432: | |
6393 | return 432000; | |
6394 | case CDCLK_FREQ_337_308: | |
6395 | return 308570; | |
6396 | case CDCLK_FREQ_675_617: | |
6397 | return 617140; | |
6398 | default: | |
6399 | WARN(1, "Unknown cd freq selection\n"); | |
6400 | } | |
6401 | } else { | |
6402 | /* vco 8100 */ | |
6403 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6404 | case CDCLK_FREQ_450_432: | |
6405 | return 450000; | |
6406 | case CDCLK_FREQ_337_308: | |
6407 | return 337500; | |
6408 | case CDCLK_FREQ_675_617: | |
6409 | return 675000; | |
6410 | default: | |
6411 | WARN(1, "Unknown cd freq selection\n"); | |
6412 | } | |
6413 | } | |
6414 | ||
6415 | /* error case, do as if DPLL0 isn't enabled */ | |
6416 | return 24000; | |
6417 | } | |
6418 | ||
6419 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6420 | { | |
6421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6422 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6423 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6424 | ||
6425 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6426 | return 800000; | |
6427 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6428 | return 450000; | |
6429 | else if (freq == LCPLL_CLK_FREQ_450) | |
6430 | return 450000; | |
6431 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6432 | return 540000; | |
6433 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6434 | return 337500; | |
6435 | else | |
6436 | return 675000; | |
6437 | } | |
6438 | ||
6439 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6440 | { | |
6441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6442 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6443 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6444 | ||
6445 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6446 | return 800000; | |
6447 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6448 | return 450000; | |
6449 | else if (freq == LCPLL_CLK_FREQ_450) | |
6450 | return 450000; | |
6451 | else if (IS_HSW_ULT(dev)) | |
6452 | return 337500; | |
6453 | else | |
6454 | return 540000; | |
6455 | } | |
6456 | ||
25eb05fc JB |
6457 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6458 | { | |
d197b7d3 | 6459 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6460 | u32 val; |
6461 | int divider; | |
6462 | ||
6bcda4f0 VS |
6463 | if (dev_priv->hpll_freq == 0) |
6464 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6465 | ||
d197b7d3 VS |
6466 | mutex_lock(&dev_priv->dpio_lock); |
6467 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6468 | mutex_unlock(&dev_priv->dpio_lock); | |
6469 | ||
6470 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6471 | ||
7d007f40 VS |
6472 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6473 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6474 | "cdclk change in progress\n"); | |
6475 | ||
6bcda4f0 | 6476 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6477 | } |
6478 | ||
b37a6434 VS |
6479 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6480 | { | |
6481 | return 450000; | |
6482 | } | |
6483 | ||
e70236a8 JB |
6484 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6485 | { | |
6486 | return 400000; | |
6487 | } | |
79e53945 | 6488 | |
e70236a8 | 6489 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6490 | { |
e907f170 | 6491 | return 333333; |
e70236a8 | 6492 | } |
79e53945 | 6493 | |
e70236a8 JB |
6494 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6495 | { | |
6496 | return 200000; | |
6497 | } | |
79e53945 | 6498 | |
257a7ffc DV |
6499 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6500 | { | |
6501 | u16 gcfgc = 0; | |
6502 | ||
6503 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6504 | ||
6505 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6506 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6507 | return 266667; |
257a7ffc | 6508 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6509 | return 333333; |
257a7ffc | 6510 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6511 | return 444444; |
257a7ffc DV |
6512 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6513 | return 200000; | |
6514 | default: | |
6515 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6516 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6517 | return 133333; |
257a7ffc | 6518 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6519 | return 166667; |
257a7ffc DV |
6520 | } |
6521 | } | |
6522 | ||
e70236a8 JB |
6523 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6524 | { | |
6525 | u16 gcfgc = 0; | |
79e53945 | 6526 | |
e70236a8 JB |
6527 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6528 | ||
6529 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6530 | return 133333; |
e70236a8 JB |
6531 | else { |
6532 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6533 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6534 | return 333333; |
e70236a8 JB |
6535 | default: |
6536 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6537 | return 190000; | |
79e53945 | 6538 | } |
e70236a8 JB |
6539 | } |
6540 | } | |
6541 | ||
6542 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6543 | { | |
e907f170 | 6544 | return 266667; |
e70236a8 JB |
6545 | } |
6546 | ||
6547 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6548 | { | |
6549 | u16 hpllcc = 0; | |
6550 | /* Assume that the hardware is in the high speed state. This | |
6551 | * should be the default. | |
6552 | */ | |
6553 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6554 | case GC_CLOCK_133_200: | |
6555 | case GC_CLOCK_100_200: | |
6556 | return 200000; | |
6557 | case GC_CLOCK_166_250: | |
6558 | return 250000; | |
6559 | case GC_CLOCK_100_133: | |
e907f170 | 6560 | return 133333; |
e70236a8 | 6561 | } |
79e53945 | 6562 | |
e70236a8 JB |
6563 | /* Shouldn't happen */ |
6564 | return 0; | |
6565 | } | |
79e53945 | 6566 | |
e70236a8 JB |
6567 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6568 | { | |
e907f170 | 6569 | return 133333; |
79e53945 JB |
6570 | } |
6571 | ||
2c07245f | 6572 | static void |
a65851af | 6573 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6574 | { |
a65851af VS |
6575 | while (*num > DATA_LINK_M_N_MASK || |
6576 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6577 | *num >>= 1; |
6578 | *den >>= 1; | |
6579 | } | |
6580 | } | |
6581 | ||
a65851af VS |
6582 | static void compute_m_n(unsigned int m, unsigned int n, |
6583 | uint32_t *ret_m, uint32_t *ret_n) | |
6584 | { | |
6585 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6586 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6587 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6588 | } | |
6589 | ||
e69d0bc1 DV |
6590 | void |
6591 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6592 | int pixel_clock, int link_clock, | |
6593 | struct intel_link_m_n *m_n) | |
2c07245f | 6594 | { |
e69d0bc1 | 6595 | m_n->tu = 64; |
a65851af VS |
6596 | |
6597 | compute_m_n(bits_per_pixel * pixel_clock, | |
6598 | link_clock * nlanes * 8, | |
6599 | &m_n->gmch_m, &m_n->gmch_n); | |
6600 | ||
6601 | compute_m_n(pixel_clock, link_clock, | |
6602 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6603 | } |
6604 | ||
a7615030 CW |
6605 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6606 | { | |
d330a953 JN |
6607 | if (i915.panel_use_ssc >= 0) |
6608 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6609 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6610 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6611 | } |
6612 | ||
a93e255f ACO |
6613 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6614 | int num_connectors) | |
c65d77d8 | 6615 | { |
a93e255f | 6616 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6617 | struct drm_i915_private *dev_priv = dev->dev_private; |
6618 | int refclk; | |
6619 | ||
a93e255f ACO |
6620 | WARN_ON(!crtc_state->base.state); |
6621 | ||
5ab7b0b7 | 6622 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 6623 | refclk = 100000; |
a93e255f | 6624 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6625 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6626 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6627 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6628 | } else if (!IS_GEN2(dev)) { |
6629 | refclk = 96000; | |
6630 | } else { | |
6631 | refclk = 48000; | |
6632 | } | |
6633 | ||
6634 | return refclk; | |
6635 | } | |
6636 | ||
7429e9d4 | 6637 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6638 | { |
7df00d7a | 6639 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6640 | } |
f47709a9 | 6641 | |
7429e9d4 DV |
6642 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6643 | { | |
6644 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6645 | } |
6646 | ||
f47709a9 | 6647 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6648 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6649 | intel_clock_t *reduced_clock) |
6650 | { | |
f47709a9 | 6651 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6652 | u32 fp, fp2 = 0; |
6653 | ||
6654 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6655 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6656 | if (reduced_clock) |
7429e9d4 | 6657 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6658 | } else { |
190f68c5 | 6659 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6660 | if (reduced_clock) |
7429e9d4 | 6661 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6662 | } |
6663 | ||
190f68c5 | 6664 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6665 | |
f47709a9 | 6666 | crtc->lowfreq_avail = false; |
a93e255f | 6667 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6668 | reduced_clock) { |
190f68c5 | 6669 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6670 | crtc->lowfreq_avail = true; |
a7516a05 | 6671 | } else { |
190f68c5 | 6672 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6673 | } |
6674 | } | |
6675 | ||
5e69f97f CML |
6676 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6677 | pipe) | |
89b667f8 JB |
6678 | { |
6679 | u32 reg_val; | |
6680 | ||
6681 | /* | |
6682 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6683 | * and set it to a reasonable value instead. | |
6684 | */ | |
ab3c759a | 6685 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6686 | reg_val &= 0xffffff00; |
6687 | reg_val |= 0x00000030; | |
ab3c759a | 6688 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6689 | |
ab3c759a | 6690 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6691 | reg_val &= 0x8cffffff; |
6692 | reg_val = 0x8c000000; | |
ab3c759a | 6693 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6694 | |
ab3c759a | 6695 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6696 | reg_val &= 0xffffff00; |
ab3c759a | 6697 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6698 | |
ab3c759a | 6699 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6700 | reg_val &= 0x00ffffff; |
6701 | reg_val |= 0xb0000000; | |
ab3c759a | 6702 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6703 | } |
6704 | ||
b551842d DV |
6705 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6706 | struct intel_link_m_n *m_n) | |
6707 | { | |
6708 | struct drm_device *dev = crtc->base.dev; | |
6709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6710 | int pipe = crtc->pipe; | |
6711 | ||
e3b95f1e DV |
6712 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6713 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6714 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6715 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6716 | } |
6717 | ||
6718 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6719 | struct intel_link_m_n *m_n, |
6720 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6721 | { |
6722 | struct drm_device *dev = crtc->base.dev; | |
6723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6724 | int pipe = crtc->pipe; | |
6e3c9717 | 6725 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6726 | |
6727 | if (INTEL_INFO(dev)->gen >= 5) { | |
6728 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6729 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6730 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6731 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6732 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6733 | * for gen < 8) and if DRRS is supported (to make sure the | |
6734 | * registers are not unnecessarily accessed). | |
6735 | */ | |
44395bfe | 6736 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6737 | crtc->config->has_drrs) { |
f769cd24 VK |
6738 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6739 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6740 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6741 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6742 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6743 | } | |
b551842d | 6744 | } else { |
e3b95f1e DV |
6745 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6746 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6747 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6748 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6749 | } |
6750 | } | |
6751 | ||
fe3cd48d | 6752 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6753 | { |
fe3cd48d R |
6754 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6755 | ||
6756 | if (m_n == M1_N1) { | |
6757 | dp_m_n = &crtc->config->dp_m_n; | |
6758 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6759 | } else if (m_n == M2_N2) { | |
6760 | ||
6761 | /* | |
6762 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6763 | * needs to be programmed into M1_N1. | |
6764 | */ | |
6765 | dp_m_n = &crtc->config->dp_m2_n2; | |
6766 | } else { | |
6767 | DRM_ERROR("Unsupported divider value\n"); | |
6768 | return; | |
6769 | } | |
6770 | ||
6e3c9717 ACO |
6771 | if (crtc->config->has_pch_encoder) |
6772 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6773 | else |
fe3cd48d | 6774 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6775 | } |
6776 | ||
d288f65f | 6777 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6778 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6779 | { |
6780 | u32 dpll, dpll_md; | |
6781 | ||
6782 | /* | |
6783 | * Enable DPIO clock input. We should never disable the reference | |
6784 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6785 | * on it. | |
6786 | */ | |
6787 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6788 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6789 | /* We should never disable this, set it here for state tracking */ | |
6790 | if (crtc->pipe == PIPE_B) | |
6791 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6792 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6793 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6794 | |
d288f65f | 6795 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6796 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6797 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6798 | } |
6799 | ||
d288f65f | 6800 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6801 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6802 | { |
f47709a9 | 6803 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6804 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6805 | int pipe = crtc->pipe; |
bdd4b6a6 | 6806 | u32 mdiv; |
a0c4da24 | 6807 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6808 | u32 coreclk, reg_val; |
a0c4da24 | 6809 | |
09153000 DV |
6810 | mutex_lock(&dev_priv->dpio_lock); |
6811 | ||
d288f65f VS |
6812 | bestn = pipe_config->dpll.n; |
6813 | bestm1 = pipe_config->dpll.m1; | |
6814 | bestm2 = pipe_config->dpll.m2; | |
6815 | bestp1 = pipe_config->dpll.p1; | |
6816 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6817 | |
89b667f8 JB |
6818 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6819 | ||
6820 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6821 | if (pipe == PIPE_B) |
5e69f97f | 6822 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6823 | |
6824 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6825 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6826 | |
6827 | /* Disable target IRef on PLL */ | |
ab3c759a | 6828 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6829 | reg_val &= 0x00ffffff; |
ab3c759a | 6830 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6831 | |
6832 | /* Disable fast lock */ | |
ab3c759a | 6833 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6834 | |
6835 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6836 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6837 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6838 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6839 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6840 | |
6841 | /* | |
6842 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6843 | * but we don't support that). | |
6844 | * Note: don't use the DAC post divider as it seems unstable. | |
6845 | */ | |
6846 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6847 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6848 | |
a0c4da24 | 6849 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6850 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6851 | |
89b667f8 | 6852 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6853 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6854 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6855 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6856 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6857 | 0x009f0003); |
89b667f8 | 6858 | else |
ab3c759a | 6859 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6860 | 0x00d0000f); |
6861 | ||
681a8504 | 6862 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6863 | /* Use SSC source */ |
bdd4b6a6 | 6864 | if (pipe == PIPE_A) |
ab3c759a | 6865 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6866 | 0x0df40000); |
6867 | else | |
ab3c759a | 6868 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6869 | 0x0df70000); |
6870 | } else { /* HDMI or VGA */ | |
6871 | /* Use bend source */ | |
bdd4b6a6 | 6872 | if (pipe == PIPE_A) |
ab3c759a | 6873 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6874 | 0x0df70000); |
6875 | else | |
ab3c759a | 6876 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6877 | 0x0df40000); |
6878 | } | |
a0c4da24 | 6879 | |
ab3c759a | 6880 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6881 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6882 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6883 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6884 | coreclk |= 0x01000000; |
ab3c759a | 6885 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6886 | |
ab3c759a | 6887 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6888 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6889 | } |
6890 | ||
d288f65f | 6891 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6892 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6893 | { |
d288f65f | 6894 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6895 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6896 | DPLL_VCO_ENABLE; | |
6897 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6898 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6899 | |
d288f65f VS |
6900 | pipe_config->dpll_hw_state.dpll_md = |
6901 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6902 | } |
6903 | ||
d288f65f | 6904 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6905 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6906 | { |
6907 | struct drm_device *dev = crtc->base.dev; | |
6908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6909 | int pipe = crtc->pipe; | |
6910 | int dpll_reg = DPLL(crtc->pipe); | |
6911 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6912 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6913 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6914 | u32 dpio_val; |
9cbe40c1 | 6915 | int vco; |
9d556c99 | 6916 | |
d288f65f VS |
6917 | bestn = pipe_config->dpll.n; |
6918 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6919 | bestm1 = pipe_config->dpll.m1; | |
6920 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6921 | bestp1 = pipe_config->dpll.p1; | |
6922 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6923 | vco = pipe_config->dpll.vco; |
a945ce7e | 6924 | dpio_val = 0; |
9cbe40c1 | 6925 | loopfilter = 0; |
9d556c99 CML |
6926 | |
6927 | /* | |
6928 | * Enable Refclk and SSC | |
6929 | */ | |
a11b0703 | 6930 | I915_WRITE(dpll_reg, |
d288f65f | 6931 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6932 | |
6933 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6934 | |
9d556c99 CML |
6935 | /* p1 and p2 divider */ |
6936 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6937 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6938 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6939 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6940 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6941 | ||
6942 | /* Feedback post-divider - m2 */ | |
6943 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6944 | ||
6945 | /* Feedback refclk divider - n and m1 */ | |
6946 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6947 | DPIO_CHV_M1_DIV_BY_2 | | |
6948 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6949 | ||
6950 | /* M2 fraction division */ | |
a945ce7e VP |
6951 | if (bestm2_frac) |
6952 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6953 | |
6954 | /* M2 fraction division enable */ | |
a945ce7e VP |
6955 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6956 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6957 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6958 | if (bestm2_frac) | |
6959 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6960 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6961 | |
de3a0fde VP |
6962 | /* Program digital lock detect threshold */ |
6963 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6964 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6965 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6966 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6967 | if (!bestm2_frac) | |
6968 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6969 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6970 | ||
9d556c99 | 6971 | /* Loop filter */ |
9cbe40c1 VP |
6972 | if (vco == 5400000) { |
6973 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6974 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6975 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6976 | tribuf_calcntr = 0x9; | |
6977 | } else if (vco <= 6200000) { | |
6978 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6979 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6980 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6981 | tribuf_calcntr = 0x9; | |
6982 | } else if (vco <= 6480000) { | |
6983 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6984 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6985 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6986 | tribuf_calcntr = 0x8; | |
6987 | } else { | |
6988 | /* Not supported. Apply the same limits as in the max case */ | |
6989 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6990 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6991 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6992 | tribuf_calcntr = 0; | |
6993 | } | |
9d556c99 CML |
6994 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6995 | ||
968040b2 | 6996 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6997 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6998 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6999 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7000 | ||
9d556c99 CML |
7001 | /* AFC Recal */ |
7002 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7003 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7004 | DPIO_AFC_RECAL); | |
7005 | ||
7006 | mutex_unlock(&dev_priv->dpio_lock); | |
7007 | } | |
7008 | ||
d288f65f VS |
7009 | /** |
7010 | * vlv_force_pll_on - forcibly enable just the PLL | |
7011 | * @dev_priv: i915 private structure | |
7012 | * @pipe: pipe PLL to enable | |
7013 | * @dpll: PLL configuration | |
7014 | * | |
7015 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7016 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7017 | * be enabled. | |
7018 | */ | |
7019 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7020 | const struct dpll *dpll) | |
7021 | { | |
7022 | struct intel_crtc *crtc = | |
7023 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7024 | struct intel_crtc_state pipe_config = { |
a93e255f | 7025 | .base.crtc = &crtc->base, |
d288f65f VS |
7026 | .pixel_multiplier = 1, |
7027 | .dpll = *dpll, | |
7028 | }; | |
7029 | ||
7030 | if (IS_CHERRYVIEW(dev)) { | |
7031 | chv_update_pll(crtc, &pipe_config); | |
7032 | chv_prepare_pll(crtc, &pipe_config); | |
7033 | chv_enable_pll(crtc, &pipe_config); | |
7034 | } else { | |
7035 | vlv_update_pll(crtc, &pipe_config); | |
7036 | vlv_prepare_pll(crtc, &pipe_config); | |
7037 | vlv_enable_pll(crtc, &pipe_config); | |
7038 | } | |
7039 | } | |
7040 | ||
7041 | /** | |
7042 | * vlv_force_pll_off - forcibly disable just the PLL | |
7043 | * @dev_priv: i915 private structure | |
7044 | * @pipe: pipe PLL to disable | |
7045 | * | |
7046 | * Disable the PLL for @pipe. To be used in cases where we need | |
7047 | * the PLL enabled even when @pipe is not going to be enabled. | |
7048 | */ | |
7049 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7050 | { | |
7051 | if (IS_CHERRYVIEW(dev)) | |
7052 | chv_disable_pll(to_i915(dev), pipe); | |
7053 | else | |
7054 | vlv_disable_pll(to_i915(dev), pipe); | |
7055 | } | |
7056 | ||
f47709a9 | 7057 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7058 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7059 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7060 | int num_connectors) |
7061 | { | |
f47709a9 | 7062 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7063 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7064 | u32 dpll; |
7065 | bool is_sdvo; | |
190f68c5 | 7066 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7067 | |
190f68c5 | 7068 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7069 | |
a93e255f ACO |
7070 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7071 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7072 | |
7073 | dpll = DPLL_VGA_MODE_DIS; | |
7074 | ||
a93e255f | 7075 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7076 | dpll |= DPLLB_MODE_LVDS; |
7077 | else | |
7078 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7079 | |
ef1b460d | 7080 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7081 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7082 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7083 | } |
198a037f DV |
7084 | |
7085 | if (is_sdvo) | |
4a33e48d | 7086 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7087 | |
190f68c5 | 7088 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7089 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7090 | |
7091 | /* compute bitmask from p1 value */ | |
7092 | if (IS_PINEVIEW(dev)) | |
7093 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7094 | else { | |
7095 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7096 | if (IS_G4X(dev) && reduced_clock) | |
7097 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7098 | } | |
7099 | switch (clock->p2) { | |
7100 | case 5: | |
7101 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7102 | break; | |
7103 | case 7: | |
7104 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7105 | break; | |
7106 | case 10: | |
7107 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7108 | break; | |
7109 | case 14: | |
7110 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7111 | break; | |
7112 | } | |
7113 | if (INTEL_INFO(dev)->gen >= 4) | |
7114 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7115 | ||
190f68c5 | 7116 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7117 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7118 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7119 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7120 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7121 | else | |
7122 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7123 | ||
7124 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7125 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7126 | |
eb1cbe48 | 7127 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7128 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7129 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7130 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7131 | } |
7132 | } | |
7133 | ||
f47709a9 | 7134 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7135 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7136 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7137 | int num_connectors) |
7138 | { | |
f47709a9 | 7139 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7140 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7141 | u32 dpll; |
190f68c5 | 7142 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7143 | |
190f68c5 | 7144 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7145 | |
eb1cbe48 DV |
7146 | dpll = DPLL_VGA_MODE_DIS; |
7147 | ||
a93e255f | 7148 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7149 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7150 | } else { | |
7151 | if (clock->p1 == 2) | |
7152 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7153 | else | |
7154 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7155 | if (clock->p2 == 4) | |
7156 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7157 | } | |
7158 | ||
a93e255f | 7159 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7160 | dpll |= DPLL_DVO_2X_MODE; |
7161 | ||
a93e255f | 7162 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7163 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7164 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7165 | else | |
7166 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7167 | ||
7168 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7169 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7170 | } |
7171 | ||
8a654f3b | 7172 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7173 | { |
7174 | struct drm_device *dev = intel_crtc->base.dev; | |
7175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7176 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7177 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7178 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7179 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7180 | uint32_t crtc_vtotal, crtc_vblank_end; |
7181 | int vsyncshift = 0; | |
4d8a62ea DV |
7182 | |
7183 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7184 | * the hw state checker will get angry at the mismatch. */ | |
7185 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7186 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7187 | |
609aeaca | 7188 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7189 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7190 | crtc_vtotal -= 1; |
7191 | crtc_vblank_end -= 1; | |
609aeaca | 7192 | |
409ee761 | 7193 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7194 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7195 | else | |
7196 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7197 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7198 | if (vsyncshift < 0) |
7199 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7200 | } |
7201 | ||
7202 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7203 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7204 | |
fe2b8f9d | 7205 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7206 | (adjusted_mode->crtc_hdisplay - 1) | |
7207 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7208 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7209 | (adjusted_mode->crtc_hblank_start - 1) | |
7210 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7211 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7212 | (adjusted_mode->crtc_hsync_start - 1) | |
7213 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7214 | ||
fe2b8f9d | 7215 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7216 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7217 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7218 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7219 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7220 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7221 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7222 | (adjusted_mode->crtc_vsync_start - 1) | |
7223 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7224 | ||
b5e508d4 PZ |
7225 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7226 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7227 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7228 | * bits. */ | |
7229 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7230 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7231 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7232 | ||
b0e77b9c PZ |
7233 | /* pipesrc controls the size that is scaled from, which should |
7234 | * always be the user's requested size. | |
7235 | */ | |
7236 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7237 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7238 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7239 | } |
7240 | ||
1bd1bd80 | 7241 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7242 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7243 | { |
7244 | struct drm_device *dev = crtc->base.dev; | |
7245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7246 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7247 | uint32_t tmp; | |
7248 | ||
7249 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7250 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7251 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7252 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7253 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7254 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7255 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7256 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7257 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7258 | |
7259 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7260 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7261 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7262 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7263 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7264 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7265 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7266 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7267 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7268 | |
7269 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7270 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7271 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7272 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7273 | } |
7274 | ||
7275 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7276 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7277 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7278 | ||
2d112de7 ACO |
7279 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7280 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7281 | } |
7282 | ||
f6a83288 | 7283 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7284 | struct intel_crtc_state *pipe_config) |
babea61d | 7285 | { |
2d112de7 ACO |
7286 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7287 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7288 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7289 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7290 | |
2d112de7 ACO |
7291 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7292 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7293 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7294 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7295 | |
2d112de7 | 7296 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7297 | |
2d112de7 ACO |
7298 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7299 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7300 | } |
7301 | ||
84b046f3 DV |
7302 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7303 | { | |
7304 | struct drm_device *dev = intel_crtc->base.dev; | |
7305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7306 | uint32_t pipeconf; | |
7307 | ||
9f11a9e4 | 7308 | pipeconf = 0; |
84b046f3 | 7309 | |
b6b5d049 VS |
7310 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7311 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7312 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7313 | |
6e3c9717 | 7314 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7315 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7316 | |
ff9ce46e DV |
7317 | /* only g4x and later have fancy bpc/dither controls */ |
7318 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7319 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7320 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7321 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7322 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7323 | |
6e3c9717 | 7324 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7325 | case 18: |
7326 | pipeconf |= PIPECONF_6BPC; | |
7327 | break; | |
7328 | case 24: | |
7329 | pipeconf |= PIPECONF_8BPC; | |
7330 | break; | |
7331 | case 30: | |
7332 | pipeconf |= PIPECONF_10BPC; | |
7333 | break; | |
7334 | default: | |
7335 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7336 | BUG(); | |
84b046f3 DV |
7337 | } |
7338 | } | |
7339 | ||
7340 | if (HAS_PIPE_CXSR(dev)) { | |
7341 | if (intel_crtc->lowfreq_avail) { | |
7342 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7343 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7344 | } else { | |
7345 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7346 | } |
7347 | } | |
7348 | ||
6e3c9717 | 7349 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7350 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7351 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7352 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7353 | else | |
7354 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7355 | } else | |
84b046f3 DV |
7356 | pipeconf |= PIPECONF_PROGRESSIVE; |
7357 | ||
6e3c9717 | 7358 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7359 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7360 | |
84b046f3 DV |
7361 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7362 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7363 | } | |
7364 | ||
190f68c5 ACO |
7365 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7366 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7367 | { |
c7653199 | 7368 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7369 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7370 | int refclk, num_connectors = 0; |
652c393a | 7371 | intel_clock_t clock, reduced_clock; |
a16af721 | 7372 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7373 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7374 | struct intel_encoder *encoder; |
d4906093 | 7375 | const intel_limit_t *limit; |
55bb9992 ACO |
7376 | struct drm_atomic_state *state = crtc_state->base.state; |
7377 | struct drm_connector_state *connector_state; | |
7378 | int i; | |
79e53945 | 7379 | |
55bb9992 ACO |
7380 | for (i = 0; i < state->num_connector; i++) { |
7381 | if (!state->connectors[i]) | |
d0737e1d ACO |
7382 | continue; |
7383 | ||
55bb9992 ACO |
7384 | connector_state = state->connector_states[i]; |
7385 | if (connector_state->crtc != &crtc->base) | |
7386 | continue; | |
7387 | ||
7388 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7389 | ||
5eddb70b | 7390 | switch (encoder->type) { |
79e53945 JB |
7391 | case INTEL_OUTPUT_LVDS: |
7392 | is_lvds = true; | |
7393 | break; | |
e9fd1c02 JN |
7394 | case INTEL_OUTPUT_DSI: |
7395 | is_dsi = true; | |
7396 | break; | |
6847d71b PZ |
7397 | default: |
7398 | break; | |
79e53945 | 7399 | } |
43565a06 | 7400 | |
c751ce4f | 7401 | num_connectors++; |
79e53945 JB |
7402 | } |
7403 | ||
f2335330 | 7404 | if (is_dsi) |
5b18e57c | 7405 | return 0; |
f2335330 | 7406 | |
190f68c5 | 7407 | if (!crtc_state->clock_set) { |
a93e255f | 7408 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7409 | |
e9fd1c02 JN |
7410 | /* |
7411 | * Returns a set of divisors for the desired target clock with | |
7412 | * the given refclk, or FALSE. The returned values represent | |
7413 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7414 | * 2) / p1 / p2. | |
7415 | */ | |
a93e255f ACO |
7416 | limit = intel_limit(crtc_state, refclk); |
7417 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7418 | crtc_state->port_clock, |
e9fd1c02 | 7419 | refclk, NULL, &clock); |
f2335330 | 7420 | if (!ok) { |
e9fd1c02 JN |
7421 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7422 | return -EINVAL; | |
7423 | } | |
79e53945 | 7424 | |
f2335330 JN |
7425 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7426 | /* | |
7427 | * Ensure we match the reduced clock's P to the target | |
7428 | * clock. If the clocks don't match, we can't switch | |
7429 | * the display clock by using the FP0/FP1. In such case | |
7430 | * we will disable the LVDS downclock feature. | |
7431 | */ | |
7432 | has_reduced_clock = | |
a93e255f | 7433 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7434 | dev_priv->lvds_downclock, |
7435 | refclk, &clock, | |
7436 | &reduced_clock); | |
7437 | } | |
7438 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7439 | crtc_state->dpll.n = clock.n; |
7440 | crtc_state->dpll.m1 = clock.m1; | |
7441 | crtc_state->dpll.m2 = clock.m2; | |
7442 | crtc_state->dpll.p1 = clock.p1; | |
7443 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7444 | } |
7026d4ac | 7445 | |
e9fd1c02 | 7446 | if (IS_GEN2(dev)) { |
190f68c5 | 7447 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7448 | has_reduced_clock ? &reduced_clock : NULL, |
7449 | num_connectors); | |
9d556c99 | 7450 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7451 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7452 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7453 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7454 | } else { |
190f68c5 | 7455 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7456 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7457 | num_connectors); |
e9fd1c02 | 7458 | } |
79e53945 | 7459 | |
c8f7a0db | 7460 | return 0; |
f564048e EA |
7461 | } |
7462 | ||
2fa2fe9a | 7463 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7464 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7465 | { |
7466 | struct drm_device *dev = crtc->base.dev; | |
7467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7468 | uint32_t tmp; | |
7469 | ||
dc9e7dec VS |
7470 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7471 | return; | |
7472 | ||
2fa2fe9a | 7473 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7474 | if (!(tmp & PFIT_ENABLE)) |
7475 | return; | |
2fa2fe9a | 7476 | |
06922821 | 7477 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7478 | if (INTEL_INFO(dev)->gen < 4) { |
7479 | if (crtc->pipe != PIPE_B) | |
7480 | return; | |
2fa2fe9a DV |
7481 | } else { |
7482 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7483 | return; | |
7484 | } | |
7485 | ||
06922821 | 7486 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7487 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7488 | if (INTEL_INFO(dev)->gen < 5) | |
7489 | pipe_config->gmch_pfit.lvds_border_bits = | |
7490 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7491 | } | |
7492 | ||
acbec814 | 7493 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7494 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7495 | { |
7496 | struct drm_device *dev = crtc->base.dev; | |
7497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7498 | int pipe = pipe_config->cpu_transcoder; | |
7499 | intel_clock_t clock; | |
7500 | u32 mdiv; | |
662c6ecb | 7501 | int refclk = 100000; |
acbec814 | 7502 | |
f573de5a SK |
7503 | /* In case of MIPI DPLL will not even be used */ |
7504 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7505 | return; | |
7506 | ||
acbec814 | 7507 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7508 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7509 | mutex_unlock(&dev_priv->dpio_lock); |
7510 | ||
7511 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7512 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7513 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7514 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7515 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7516 | ||
f646628b | 7517 | vlv_clock(refclk, &clock); |
acbec814 | 7518 | |
f646628b VS |
7519 | /* clock.dot is the fast clock */ |
7520 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7521 | } |
7522 | ||
5724dbd1 DL |
7523 | static void |
7524 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7525 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7526 | { |
7527 | struct drm_device *dev = crtc->base.dev; | |
7528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7529 | u32 val, base, offset; | |
7530 | int pipe = crtc->pipe, plane = crtc->plane; | |
7531 | int fourcc, pixel_format; | |
6761dd31 | 7532 | unsigned int aligned_height; |
b113d5ee | 7533 | struct drm_framebuffer *fb; |
1b842c89 | 7534 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7535 | |
42a7b088 DL |
7536 | val = I915_READ(DSPCNTR(plane)); |
7537 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7538 | return; | |
7539 | ||
d9806c9f | 7540 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7541 | if (!intel_fb) { |
1ad292b5 JB |
7542 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7543 | return; | |
7544 | } | |
7545 | ||
1b842c89 DL |
7546 | fb = &intel_fb->base; |
7547 | ||
18c5247e DV |
7548 | if (INTEL_INFO(dev)->gen >= 4) { |
7549 | if (val & DISPPLANE_TILED) { | |
49af449b | 7550 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7551 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7552 | } | |
7553 | } | |
1ad292b5 JB |
7554 | |
7555 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7556 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7557 | fb->pixel_format = fourcc; |
7558 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7559 | |
7560 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7561 | if (plane_config->tiling) |
1ad292b5 JB |
7562 | offset = I915_READ(DSPTILEOFF(plane)); |
7563 | else | |
7564 | offset = I915_READ(DSPLINOFF(plane)); | |
7565 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7566 | } else { | |
7567 | base = I915_READ(DSPADDR(plane)); | |
7568 | } | |
7569 | plane_config->base = base; | |
7570 | ||
7571 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7572 | fb->width = ((val >> 16) & 0xfff) + 1; |
7573 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7574 | |
7575 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7576 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7577 | |
b113d5ee | 7578 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7579 | fb->pixel_format, |
7580 | fb->modifier[0]); | |
1ad292b5 | 7581 | |
f37b5c2b | 7582 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7583 | |
2844a921 DL |
7584 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7585 | pipe_name(pipe), plane, fb->width, fb->height, | |
7586 | fb->bits_per_pixel, base, fb->pitches[0], | |
7587 | plane_config->size); | |
1ad292b5 | 7588 | |
2d14030b | 7589 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7590 | } |
7591 | ||
70b23a98 | 7592 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7593 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7594 | { |
7595 | struct drm_device *dev = crtc->base.dev; | |
7596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7597 | int pipe = pipe_config->cpu_transcoder; | |
7598 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7599 | intel_clock_t clock; | |
7600 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7601 | int refclk = 100000; | |
7602 | ||
7603 | mutex_lock(&dev_priv->dpio_lock); | |
7604 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7605 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7606 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7607 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7608 | mutex_unlock(&dev_priv->dpio_lock); | |
7609 | ||
7610 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7611 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7612 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7613 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7614 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7615 | ||
7616 | chv_clock(refclk, &clock); | |
7617 | ||
7618 | /* clock.dot is the fast clock */ | |
7619 | pipe_config->port_clock = clock.dot / 5; | |
7620 | } | |
7621 | ||
0e8ffe1b | 7622 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7623 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7624 | { |
7625 | struct drm_device *dev = crtc->base.dev; | |
7626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7627 | uint32_t tmp; | |
7628 | ||
f458ebbc DV |
7629 | if (!intel_display_power_is_enabled(dev_priv, |
7630 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7631 | return false; |
7632 | ||
e143a21c | 7633 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7634 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7635 | |
0e8ffe1b DV |
7636 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7637 | if (!(tmp & PIPECONF_ENABLE)) | |
7638 | return false; | |
7639 | ||
42571aef VS |
7640 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7641 | switch (tmp & PIPECONF_BPC_MASK) { | |
7642 | case PIPECONF_6BPC: | |
7643 | pipe_config->pipe_bpp = 18; | |
7644 | break; | |
7645 | case PIPECONF_8BPC: | |
7646 | pipe_config->pipe_bpp = 24; | |
7647 | break; | |
7648 | case PIPECONF_10BPC: | |
7649 | pipe_config->pipe_bpp = 30; | |
7650 | break; | |
7651 | default: | |
7652 | break; | |
7653 | } | |
7654 | } | |
7655 | ||
b5a9fa09 DV |
7656 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7657 | pipe_config->limited_color_range = true; | |
7658 | ||
282740f7 VS |
7659 | if (INTEL_INFO(dev)->gen < 4) |
7660 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7661 | ||
1bd1bd80 DV |
7662 | intel_get_pipe_timings(crtc, pipe_config); |
7663 | ||
2fa2fe9a DV |
7664 | i9xx_get_pfit_config(crtc, pipe_config); |
7665 | ||
6c49f241 DV |
7666 | if (INTEL_INFO(dev)->gen >= 4) { |
7667 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7668 | pipe_config->pixel_multiplier = | |
7669 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7670 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7671 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7672 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7673 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7674 | pipe_config->pixel_multiplier = | |
7675 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7676 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7677 | } else { | |
7678 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7679 | * port and will be fixed up in the encoder->get_config | |
7680 | * function. */ | |
7681 | pipe_config->pixel_multiplier = 1; | |
7682 | } | |
8bcc2795 DV |
7683 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7684 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7685 | /* |
7686 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7687 | * on 830. Filter it out here so that we don't | |
7688 | * report errors due to that. | |
7689 | */ | |
7690 | if (IS_I830(dev)) | |
7691 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7692 | ||
8bcc2795 DV |
7693 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7694 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7695 | } else { |
7696 | /* Mask out read-only status bits. */ | |
7697 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7698 | DPLL_PORTC_READY_MASK | | |
7699 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7700 | } |
6c49f241 | 7701 | |
70b23a98 VS |
7702 | if (IS_CHERRYVIEW(dev)) |
7703 | chv_crtc_clock_get(crtc, pipe_config); | |
7704 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7705 | vlv_crtc_clock_get(crtc, pipe_config); |
7706 | else | |
7707 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7708 | |
0e8ffe1b DV |
7709 | return true; |
7710 | } | |
7711 | ||
dde86e2d | 7712 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7713 | { |
7714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7715 | struct intel_encoder *encoder; |
74cfd7ac | 7716 | u32 val, final; |
13d83a67 | 7717 | bool has_lvds = false; |
199e5d79 | 7718 | bool has_cpu_edp = false; |
199e5d79 | 7719 | bool has_panel = false; |
99eb6a01 KP |
7720 | bool has_ck505 = false; |
7721 | bool can_ssc = false; | |
13d83a67 JB |
7722 | |
7723 | /* We need to take the global config into account */ | |
b2784e15 | 7724 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7725 | switch (encoder->type) { |
7726 | case INTEL_OUTPUT_LVDS: | |
7727 | has_panel = true; | |
7728 | has_lvds = true; | |
7729 | break; | |
7730 | case INTEL_OUTPUT_EDP: | |
7731 | has_panel = true; | |
2de6905f | 7732 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7733 | has_cpu_edp = true; |
7734 | break; | |
6847d71b PZ |
7735 | default: |
7736 | break; | |
13d83a67 JB |
7737 | } |
7738 | } | |
7739 | ||
99eb6a01 | 7740 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7741 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7742 | can_ssc = has_ck505; |
7743 | } else { | |
7744 | has_ck505 = false; | |
7745 | can_ssc = true; | |
7746 | } | |
7747 | ||
2de6905f ID |
7748 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7749 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7750 | |
7751 | /* Ironlake: try to setup display ref clock before DPLL | |
7752 | * enabling. This is only under driver's control after | |
7753 | * PCH B stepping, previous chipset stepping should be | |
7754 | * ignoring this setting. | |
7755 | */ | |
74cfd7ac CW |
7756 | val = I915_READ(PCH_DREF_CONTROL); |
7757 | ||
7758 | /* As we must carefully and slowly disable/enable each source in turn, | |
7759 | * compute the final state we want first and check if we need to | |
7760 | * make any changes at all. | |
7761 | */ | |
7762 | final = val; | |
7763 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7764 | if (has_ck505) | |
7765 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7766 | else | |
7767 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7768 | ||
7769 | final &= ~DREF_SSC_SOURCE_MASK; | |
7770 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7771 | final &= ~DREF_SSC1_ENABLE; | |
7772 | ||
7773 | if (has_panel) { | |
7774 | final |= DREF_SSC_SOURCE_ENABLE; | |
7775 | ||
7776 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7777 | final |= DREF_SSC1_ENABLE; | |
7778 | ||
7779 | if (has_cpu_edp) { | |
7780 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7781 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7782 | else | |
7783 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7784 | } else | |
7785 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7786 | } else { | |
7787 | final |= DREF_SSC_SOURCE_DISABLE; | |
7788 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7789 | } | |
7790 | ||
7791 | if (final == val) | |
7792 | return; | |
7793 | ||
13d83a67 | 7794 | /* Always enable nonspread source */ |
74cfd7ac | 7795 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7796 | |
99eb6a01 | 7797 | if (has_ck505) |
74cfd7ac | 7798 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7799 | else |
74cfd7ac | 7800 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7801 | |
199e5d79 | 7802 | if (has_panel) { |
74cfd7ac CW |
7803 | val &= ~DREF_SSC_SOURCE_MASK; |
7804 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7805 | |
199e5d79 | 7806 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7807 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7808 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7809 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7810 | } else |
74cfd7ac | 7811 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7812 | |
7813 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7814 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7815 | POSTING_READ(PCH_DREF_CONTROL); |
7816 | udelay(200); | |
7817 | ||
74cfd7ac | 7818 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7819 | |
7820 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7821 | if (has_cpu_edp) { |
99eb6a01 | 7822 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7823 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7824 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7825 | } else |
74cfd7ac | 7826 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7827 | } else |
74cfd7ac | 7828 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7829 | |
74cfd7ac | 7830 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7831 | POSTING_READ(PCH_DREF_CONTROL); |
7832 | udelay(200); | |
7833 | } else { | |
7834 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7835 | ||
74cfd7ac | 7836 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7837 | |
7838 | /* Turn off CPU output */ | |
74cfd7ac | 7839 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7840 | |
74cfd7ac | 7841 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7842 | POSTING_READ(PCH_DREF_CONTROL); |
7843 | udelay(200); | |
7844 | ||
7845 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7846 | val &= ~DREF_SSC_SOURCE_MASK; |
7847 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7848 | |
7849 | /* Turn off SSC1 */ | |
74cfd7ac | 7850 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7851 | |
74cfd7ac | 7852 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7853 | POSTING_READ(PCH_DREF_CONTROL); |
7854 | udelay(200); | |
7855 | } | |
74cfd7ac CW |
7856 | |
7857 | BUG_ON(val != final); | |
13d83a67 JB |
7858 | } |
7859 | ||
f31f2d55 | 7860 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7861 | { |
f31f2d55 | 7862 | uint32_t tmp; |
dde86e2d | 7863 | |
0ff066a9 PZ |
7864 | tmp = I915_READ(SOUTH_CHICKEN2); |
7865 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7866 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7867 | |
0ff066a9 PZ |
7868 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7869 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7870 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7871 | |
0ff066a9 PZ |
7872 | tmp = I915_READ(SOUTH_CHICKEN2); |
7873 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7874 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7875 | |
0ff066a9 PZ |
7876 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7877 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7878 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7879 | } |
7880 | ||
7881 | /* WaMPhyProgramming:hsw */ | |
7882 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7883 | { | |
7884 | uint32_t tmp; | |
dde86e2d PZ |
7885 | |
7886 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7887 | tmp &= ~(0xFF << 24); | |
7888 | tmp |= (0x12 << 24); | |
7889 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7890 | ||
dde86e2d PZ |
7891 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7892 | tmp |= (1 << 11); | |
7893 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7894 | ||
7895 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7896 | tmp |= (1 << 11); | |
7897 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7898 | ||
dde86e2d PZ |
7899 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7900 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7901 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7902 | ||
7903 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7904 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7905 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7906 | ||
0ff066a9 PZ |
7907 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7908 | tmp &= ~(7 << 13); | |
7909 | tmp |= (5 << 13); | |
7910 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7911 | |
0ff066a9 PZ |
7912 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7913 | tmp &= ~(7 << 13); | |
7914 | tmp |= (5 << 13); | |
7915 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7916 | |
7917 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7918 | tmp &= ~0xFF; | |
7919 | tmp |= 0x1C; | |
7920 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7921 | ||
7922 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7923 | tmp &= ~0xFF; | |
7924 | tmp |= 0x1C; | |
7925 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7926 | ||
7927 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7928 | tmp &= ~(0xFF << 16); | |
7929 | tmp |= (0x1C << 16); | |
7930 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7931 | ||
7932 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7933 | tmp &= ~(0xFF << 16); | |
7934 | tmp |= (0x1C << 16); | |
7935 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7936 | ||
0ff066a9 PZ |
7937 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7938 | tmp |= (1 << 27); | |
7939 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7940 | |
0ff066a9 PZ |
7941 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7942 | tmp |= (1 << 27); | |
7943 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7944 | |
0ff066a9 PZ |
7945 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7946 | tmp &= ~(0xF << 28); | |
7947 | tmp |= (4 << 28); | |
7948 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7949 | |
0ff066a9 PZ |
7950 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7951 | tmp &= ~(0xF << 28); | |
7952 | tmp |= (4 << 28); | |
7953 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7954 | } |
7955 | ||
2fa86a1f PZ |
7956 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7957 | * Programming" based on the parameters passed: | |
7958 | * - Sequence to enable CLKOUT_DP | |
7959 | * - Sequence to enable CLKOUT_DP without spread | |
7960 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7961 | */ | |
7962 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7963 | bool with_fdi) | |
f31f2d55 PZ |
7964 | { |
7965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7966 | uint32_t reg, tmp; |
7967 | ||
7968 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7969 | with_spread = true; | |
7970 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7971 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7972 | with_fdi = false; | |
f31f2d55 PZ |
7973 | |
7974 | mutex_lock(&dev_priv->dpio_lock); | |
7975 | ||
7976 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7977 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7978 | tmp |= SBI_SSCCTL_PATHALT; | |
7979 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7980 | ||
7981 | udelay(24); | |
7982 | ||
2fa86a1f PZ |
7983 | if (with_spread) { |
7984 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7985 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7986 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7987 | |
2fa86a1f PZ |
7988 | if (with_fdi) { |
7989 | lpt_reset_fdi_mphy(dev_priv); | |
7990 | lpt_program_fdi_mphy(dev_priv); | |
7991 | } | |
7992 | } | |
dde86e2d | 7993 | |
2fa86a1f PZ |
7994 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7995 | SBI_GEN0 : SBI_DBUFF0; | |
7996 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7997 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7998 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7999 | |
8000 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
8001 | } |
8002 | ||
47701c3b PZ |
8003 | /* Sequence to disable CLKOUT_DP */ |
8004 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8005 | { | |
8006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8007 | uint32_t reg, tmp; | |
8008 | ||
8009 | mutex_lock(&dev_priv->dpio_lock); | |
8010 | ||
8011 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8012 | SBI_GEN0 : SBI_DBUFF0; | |
8013 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8014 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8015 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8016 | ||
8017 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8018 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8019 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8020 | tmp |= SBI_SSCCTL_PATHALT; | |
8021 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8022 | udelay(32); | |
8023 | } | |
8024 | tmp |= SBI_SSCCTL_DISABLE; | |
8025 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8026 | } | |
8027 | ||
8028 | mutex_unlock(&dev_priv->dpio_lock); | |
8029 | } | |
8030 | ||
bf8fa3d3 PZ |
8031 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8032 | { | |
bf8fa3d3 PZ |
8033 | struct intel_encoder *encoder; |
8034 | bool has_vga = false; | |
8035 | ||
b2784e15 | 8036 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8037 | switch (encoder->type) { |
8038 | case INTEL_OUTPUT_ANALOG: | |
8039 | has_vga = true; | |
8040 | break; | |
6847d71b PZ |
8041 | default: |
8042 | break; | |
bf8fa3d3 PZ |
8043 | } |
8044 | } | |
8045 | ||
47701c3b PZ |
8046 | if (has_vga) |
8047 | lpt_enable_clkout_dp(dev, true, true); | |
8048 | else | |
8049 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8050 | } |
8051 | ||
dde86e2d PZ |
8052 | /* |
8053 | * Initialize reference clocks when the driver loads | |
8054 | */ | |
8055 | void intel_init_pch_refclk(struct drm_device *dev) | |
8056 | { | |
8057 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8058 | ironlake_init_pch_refclk(dev); | |
8059 | else if (HAS_PCH_LPT(dev)) | |
8060 | lpt_init_pch_refclk(dev); | |
8061 | } | |
8062 | ||
55bb9992 | 8063 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8064 | { |
55bb9992 | 8065 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8066 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 ACO |
8067 | struct drm_atomic_state *state = crtc_state->base.state; |
8068 | struct drm_connector_state *connector_state; | |
d9d444cb | 8069 | struct intel_encoder *encoder; |
55bb9992 | 8070 | int num_connectors = 0, i; |
d9d444cb JB |
8071 | bool is_lvds = false; |
8072 | ||
55bb9992 ACO |
8073 | for (i = 0; i < state->num_connector; i++) { |
8074 | if (!state->connectors[i]) | |
d0737e1d ACO |
8075 | continue; |
8076 | ||
55bb9992 ACO |
8077 | connector_state = state->connector_states[i]; |
8078 | if (connector_state->crtc != crtc_state->base.crtc) | |
8079 | continue; | |
8080 | ||
8081 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8082 | ||
d9d444cb JB |
8083 | switch (encoder->type) { |
8084 | case INTEL_OUTPUT_LVDS: | |
8085 | is_lvds = true; | |
8086 | break; | |
6847d71b PZ |
8087 | default: |
8088 | break; | |
d9d444cb JB |
8089 | } |
8090 | num_connectors++; | |
8091 | } | |
8092 | ||
8093 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8094 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8095 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8096 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8097 | } |
8098 | ||
8099 | return 120000; | |
8100 | } | |
8101 | ||
6ff93609 | 8102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8103 | { |
c8203565 | 8104 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8105 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8107 | uint32_t val; |
8108 | ||
78114071 | 8109 | val = 0; |
c8203565 | 8110 | |
6e3c9717 | 8111 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8112 | case 18: |
dfd07d72 | 8113 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8114 | break; |
8115 | case 24: | |
dfd07d72 | 8116 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8117 | break; |
8118 | case 30: | |
dfd07d72 | 8119 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8120 | break; |
8121 | case 36: | |
dfd07d72 | 8122 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8123 | break; |
8124 | default: | |
cc769b62 PZ |
8125 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8126 | BUG(); | |
c8203565 PZ |
8127 | } |
8128 | ||
6e3c9717 | 8129 | if (intel_crtc->config->dither) |
c8203565 PZ |
8130 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8131 | ||
6e3c9717 | 8132 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8133 | val |= PIPECONF_INTERLACED_ILK; |
8134 | else | |
8135 | val |= PIPECONF_PROGRESSIVE; | |
8136 | ||
6e3c9717 | 8137 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8138 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8139 | |
c8203565 PZ |
8140 | I915_WRITE(PIPECONF(pipe), val); |
8141 | POSTING_READ(PIPECONF(pipe)); | |
8142 | } | |
8143 | ||
86d3efce VS |
8144 | /* |
8145 | * Set up the pipe CSC unit. | |
8146 | * | |
8147 | * Currently only full range RGB to limited range RGB conversion | |
8148 | * is supported, but eventually this should handle various | |
8149 | * RGB<->YCbCr scenarios as well. | |
8150 | */ | |
50f3b016 | 8151 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8152 | { |
8153 | struct drm_device *dev = crtc->dev; | |
8154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8156 | int pipe = intel_crtc->pipe; | |
8157 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8158 | ||
8159 | /* | |
8160 | * TODO: Check what kind of values actually come out of the pipe | |
8161 | * with these coeff/postoff values and adjust to get the best | |
8162 | * accuracy. Perhaps we even need to take the bpc value into | |
8163 | * consideration. | |
8164 | */ | |
8165 | ||
6e3c9717 | 8166 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8167 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8168 | ||
8169 | /* | |
8170 | * GY/GU and RY/RU should be the other way around according | |
8171 | * to BSpec, but reality doesn't agree. Just set them up in | |
8172 | * a way that results in the correct picture. | |
8173 | */ | |
8174 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8175 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8176 | ||
8177 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8178 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8179 | ||
8180 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8181 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8182 | ||
8183 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8184 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8185 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8186 | ||
8187 | if (INTEL_INFO(dev)->gen > 6) { | |
8188 | uint16_t postoff = 0; | |
8189 | ||
6e3c9717 | 8190 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8191 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8192 | |
8193 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8194 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8195 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8196 | ||
8197 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8198 | } else { | |
8199 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8200 | ||
6e3c9717 | 8201 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8202 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8203 | ||
8204 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8205 | } | |
8206 | } | |
8207 | ||
6ff93609 | 8208 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8209 | { |
756f85cf PZ |
8210 | struct drm_device *dev = crtc->dev; |
8211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8213 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8214 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8215 | uint32_t val; |
8216 | ||
3eff4faa | 8217 | val = 0; |
ee2b0b38 | 8218 | |
6e3c9717 | 8219 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8220 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8221 | ||
6e3c9717 | 8222 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8223 | val |= PIPECONF_INTERLACED_ILK; |
8224 | else | |
8225 | val |= PIPECONF_PROGRESSIVE; | |
8226 | ||
702e7a56 PZ |
8227 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8228 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8229 | |
8230 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8231 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8232 | |
3cdf122c | 8233 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8234 | val = 0; |
8235 | ||
6e3c9717 | 8236 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8237 | case 18: |
8238 | val |= PIPEMISC_DITHER_6_BPC; | |
8239 | break; | |
8240 | case 24: | |
8241 | val |= PIPEMISC_DITHER_8_BPC; | |
8242 | break; | |
8243 | case 30: | |
8244 | val |= PIPEMISC_DITHER_10_BPC; | |
8245 | break; | |
8246 | case 36: | |
8247 | val |= PIPEMISC_DITHER_12_BPC; | |
8248 | break; | |
8249 | default: | |
8250 | /* Case prevented by pipe_config_set_bpp. */ | |
8251 | BUG(); | |
8252 | } | |
8253 | ||
6e3c9717 | 8254 | if (intel_crtc->config->dither) |
756f85cf PZ |
8255 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8256 | ||
8257 | I915_WRITE(PIPEMISC(pipe), val); | |
8258 | } | |
ee2b0b38 PZ |
8259 | } |
8260 | ||
6591c6e4 | 8261 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8262 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8263 | intel_clock_t *clock, |
8264 | bool *has_reduced_clock, | |
8265 | intel_clock_t *reduced_clock) | |
8266 | { | |
8267 | struct drm_device *dev = crtc->dev; | |
8268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8269 | int refclk; |
d4906093 | 8270 | const intel_limit_t *limit; |
a16af721 | 8271 | bool ret, is_lvds = false; |
79e53945 | 8272 | |
a93e255f | 8273 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8274 | |
55bb9992 | 8275 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8276 | |
d4906093 ML |
8277 | /* |
8278 | * Returns a set of divisors for the desired target clock with the given | |
8279 | * refclk, or FALSE. The returned values represent the clock equation: | |
8280 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8281 | */ | |
a93e255f ACO |
8282 | limit = intel_limit(crtc_state, refclk); |
8283 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8284 | crtc_state->port_clock, |
ee9300bb | 8285 | refclk, NULL, clock); |
6591c6e4 PZ |
8286 | if (!ret) |
8287 | return false; | |
cda4b7d3 | 8288 | |
ddc9003c | 8289 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8290 | /* |
8291 | * Ensure we match the reduced clock's P to the target clock. | |
8292 | * If the clocks don't match, we can't switch the display clock | |
8293 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8294 | * downclock feature. | |
8295 | */ | |
ee9300bb | 8296 | *has_reduced_clock = |
a93e255f | 8297 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8298 | dev_priv->lvds_downclock, |
8299 | refclk, clock, | |
8300 | reduced_clock); | |
652c393a | 8301 | } |
61e9653f | 8302 | |
6591c6e4 PZ |
8303 | return true; |
8304 | } | |
8305 | ||
d4b1931c PZ |
8306 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8307 | { | |
8308 | /* | |
8309 | * Account for spread spectrum to avoid | |
8310 | * oversubscribing the link. Max center spread | |
8311 | * is 2.5%; use 5% for safety's sake. | |
8312 | */ | |
8313 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8314 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8315 | } |
8316 | ||
7429e9d4 | 8317 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8318 | { |
7429e9d4 | 8319 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8320 | } |
8321 | ||
de13a2e3 | 8322 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8323 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8324 | u32 *fp, |
9a7c7890 | 8325 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8326 | { |
de13a2e3 | 8327 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8328 | struct drm_device *dev = crtc->dev; |
8329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 ACO |
8330 | struct drm_atomic_state *state = crtc_state->base.state; |
8331 | struct drm_connector_state *connector_state; | |
8332 | struct intel_encoder *encoder; | |
de13a2e3 | 8333 | uint32_t dpll; |
55bb9992 | 8334 | int factor, num_connectors = 0, i; |
09ede541 | 8335 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8336 | |
55bb9992 ACO |
8337 | for (i = 0; i < state->num_connector; i++) { |
8338 | if (!state->connectors[i]) | |
d0737e1d ACO |
8339 | continue; |
8340 | ||
55bb9992 ACO |
8341 | connector_state = state->connector_states[i]; |
8342 | if (connector_state->crtc != crtc_state->base.crtc) | |
8343 | continue; | |
8344 | ||
8345 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8346 | ||
8347 | switch (encoder->type) { | |
79e53945 JB |
8348 | case INTEL_OUTPUT_LVDS: |
8349 | is_lvds = true; | |
8350 | break; | |
8351 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8352 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8353 | is_sdvo = true; |
79e53945 | 8354 | break; |
6847d71b PZ |
8355 | default: |
8356 | break; | |
79e53945 | 8357 | } |
43565a06 | 8358 | |
c751ce4f | 8359 | num_connectors++; |
79e53945 | 8360 | } |
79e53945 | 8361 | |
c1858123 | 8362 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8363 | factor = 21; |
8364 | if (is_lvds) { | |
8365 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8366 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8367 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8368 | factor = 25; |
190f68c5 | 8369 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8370 | factor = 20; |
c1858123 | 8371 | |
190f68c5 | 8372 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8373 | *fp |= FP_CB_TUNE; |
2c07245f | 8374 | |
9a7c7890 DV |
8375 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8376 | *fp2 |= FP_CB_TUNE; | |
8377 | ||
5eddb70b | 8378 | dpll = 0; |
2c07245f | 8379 | |
a07d6787 EA |
8380 | if (is_lvds) |
8381 | dpll |= DPLLB_MODE_LVDS; | |
8382 | else | |
8383 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8384 | |
190f68c5 | 8385 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8386 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8387 | |
8388 | if (is_sdvo) | |
4a33e48d | 8389 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8390 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8391 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8392 | |
a07d6787 | 8393 | /* compute bitmask from p1 value */ |
190f68c5 | 8394 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8395 | /* also FPA1 */ |
190f68c5 | 8396 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8397 | |
190f68c5 | 8398 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8399 | case 5: |
8400 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8401 | break; | |
8402 | case 7: | |
8403 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8404 | break; | |
8405 | case 10: | |
8406 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8407 | break; | |
8408 | case 14: | |
8409 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8410 | break; | |
79e53945 JB |
8411 | } |
8412 | ||
b4c09f3b | 8413 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8414 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8415 | else |
8416 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8417 | ||
959e16d6 | 8418 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8419 | } |
8420 | ||
190f68c5 ACO |
8421 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8422 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8423 | { |
c7653199 | 8424 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8425 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8426 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8427 | bool ok, has_reduced_clock = false; |
8b47047b | 8428 | bool is_lvds = false; |
e2b78267 | 8429 | struct intel_shared_dpll *pll; |
de13a2e3 | 8430 | |
409ee761 | 8431 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8432 | |
5dc5298b PZ |
8433 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8434 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8435 | |
190f68c5 | 8436 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8437 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8438 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8439 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8440 | return -EINVAL; | |
79e53945 | 8441 | } |
f47709a9 | 8442 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8443 | if (!crtc_state->clock_set) { |
8444 | crtc_state->dpll.n = clock.n; | |
8445 | crtc_state->dpll.m1 = clock.m1; | |
8446 | crtc_state->dpll.m2 = clock.m2; | |
8447 | crtc_state->dpll.p1 = clock.p1; | |
8448 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8449 | } |
79e53945 | 8450 | |
5dc5298b | 8451 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8452 | if (crtc_state->has_pch_encoder) { |
8453 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8454 | if (has_reduced_clock) |
7429e9d4 | 8455 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8456 | |
190f68c5 | 8457 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8458 | &fp, &reduced_clock, |
8459 | has_reduced_clock ? &fp2 : NULL); | |
8460 | ||
190f68c5 ACO |
8461 | crtc_state->dpll_hw_state.dpll = dpll; |
8462 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8463 | if (has_reduced_clock) |
190f68c5 | 8464 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8465 | else |
190f68c5 | 8466 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8467 | |
190f68c5 | 8468 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8469 | if (pll == NULL) { |
84f44ce7 | 8470 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8471 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8472 | return -EINVAL; |
8473 | } | |
3fb37703 | 8474 | } |
79e53945 | 8475 | |
ab585dea | 8476 | if (is_lvds && has_reduced_clock) |
c7653199 | 8477 | crtc->lowfreq_avail = true; |
bcd644e0 | 8478 | else |
c7653199 | 8479 | crtc->lowfreq_avail = false; |
e2b78267 | 8480 | |
c8f7a0db | 8481 | return 0; |
79e53945 JB |
8482 | } |
8483 | ||
eb14cb74 VS |
8484 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8485 | struct intel_link_m_n *m_n) | |
8486 | { | |
8487 | struct drm_device *dev = crtc->base.dev; | |
8488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8489 | enum pipe pipe = crtc->pipe; | |
8490 | ||
8491 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8492 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8493 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8494 | & ~TU_SIZE_MASK; | |
8495 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8496 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8497 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8498 | } | |
8499 | ||
8500 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8501 | enum transcoder transcoder, | |
b95af8be VK |
8502 | struct intel_link_m_n *m_n, |
8503 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8504 | { |
8505 | struct drm_device *dev = crtc->base.dev; | |
8506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8507 | enum pipe pipe = crtc->pipe; |
72419203 | 8508 | |
eb14cb74 VS |
8509 | if (INTEL_INFO(dev)->gen >= 5) { |
8510 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8511 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8512 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8513 | & ~TU_SIZE_MASK; | |
8514 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8515 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8516 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8517 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8518 | * gen < 8) and if DRRS is supported (to make sure the | |
8519 | * registers are not unnecessarily read). | |
8520 | */ | |
8521 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8522 | crtc->config->has_drrs) { |
b95af8be VK |
8523 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8524 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8525 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8526 | & ~TU_SIZE_MASK; | |
8527 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8528 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8529 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8530 | } | |
eb14cb74 VS |
8531 | } else { |
8532 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8533 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8534 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8535 | & ~TU_SIZE_MASK; | |
8536 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8537 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8538 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8539 | } | |
8540 | } | |
8541 | ||
8542 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8543 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8544 | { |
681a8504 | 8545 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8546 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8547 | else | |
8548 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8549 | &pipe_config->dp_m_n, |
8550 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8551 | } |
72419203 | 8552 | |
eb14cb74 | 8553 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8554 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8555 | { |
8556 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8557 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8558 | } |
8559 | ||
bd2e244f | 8560 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8561 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8562 | { |
8563 | struct drm_device *dev = crtc->base.dev; | |
8564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8565 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8566 | uint32_t ps_ctrl = 0; | |
8567 | int id = -1; | |
8568 | int i; | |
bd2e244f | 8569 | |
a1b2278e CK |
8570 | /* find scaler attached to this pipe */ |
8571 | for (i = 0; i < crtc->num_scalers; i++) { | |
8572 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8573 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8574 | id = i; | |
8575 | pipe_config->pch_pfit.enabled = true; | |
8576 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8577 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8578 | break; | |
8579 | } | |
8580 | } | |
bd2e244f | 8581 | |
a1b2278e CK |
8582 | scaler_state->scaler_id = id; |
8583 | if (id >= 0) { | |
8584 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8585 | } else { | |
8586 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8587 | } |
8588 | } | |
8589 | ||
5724dbd1 DL |
8590 | static void |
8591 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8592 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8593 | { |
8594 | struct drm_device *dev = crtc->base.dev; | |
8595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8596 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8597 | int pipe = crtc->pipe; |
8598 | int fourcc, pixel_format; | |
6761dd31 | 8599 | unsigned int aligned_height; |
bc8d7dff | 8600 | struct drm_framebuffer *fb; |
1b842c89 | 8601 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8602 | |
d9806c9f | 8603 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8604 | if (!intel_fb) { |
bc8d7dff DL |
8605 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8606 | return; | |
8607 | } | |
8608 | ||
1b842c89 DL |
8609 | fb = &intel_fb->base; |
8610 | ||
bc8d7dff | 8611 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8612 | if (!(val & PLANE_CTL_ENABLE)) |
8613 | goto error; | |
8614 | ||
bc8d7dff DL |
8615 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8616 | fourcc = skl_format_to_fourcc(pixel_format, | |
8617 | val & PLANE_CTL_ORDER_RGBX, | |
8618 | val & PLANE_CTL_ALPHA_MASK); | |
8619 | fb->pixel_format = fourcc; | |
8620 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8621 | ||
40f46283 DL |
8622 | tiling = val & PLANE_CTL_TILED_MASK; |
8623 | switch (tiling) { | |
8624 | case PLANE_CTL_TILED_LINEAR: | |
8625 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8626 | break; | |
8627 | case PLANE_CTL_TILED_X: | |
8628 | plane_config->tiling = I915_TILING_X; | |
8629 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8630 | break; | |
8631 | case PLANE_CTL_TILED_Y: | |
8632 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8633 | break; | |
8634 | case PLANE_CTL_TILED_YF: | |
8635 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8636 | break; | |
8637 | default: | |
8638 | MISSING_CASE(tiling); | |
8639 | goto error; | |
8640 | } | |
8641 | ||
bc8d7dff DL |
8642 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8643 | plane_config->base = base; | |
8644 | ||
8645 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8646 | ||
8647 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8648 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8649 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8650 | ||
8651 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8652 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8653 | fb->pixel_format); | |
bc8d7dff DL |
8654 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8655 | ||
8656 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8657 | fb->pixel_format, |
8658 | fb->modifier[0]); | |
bc8d7dff | 8659 | |
f37b5c2b | 8660 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8661 | |
8662 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8663 | pipe_name(pipe), fb->width, fb->height, | |
8664 | fb->bits_per_pixel, base, fb->pitches[0], | |
8665 | plane_config->size); | |
8666 | ||
2d14030b | 8667 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8668 | return; |
8669 | ||
8670 | error: | |
8671 | kfree(fb); | |
8672 | } | |
8673 | ||
2fa2fe9a | 8674 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8675 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8676 | { |
8677 | struct drm_device *dev = crtc->base.dev; | |
8678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8679 | uint32_t tmp; | |
8680 | ||
8681 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8682 | ||
8683 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8684 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8685 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8686 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8687 | |
8688 | /* We currently do not free assignements of panel fitters on | |
8689 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8690 | * differentiates them) so just WARN about this case for now. */ | |
8691 | if (IS_GEN7(dev)) { | |
8692 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8693 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8694 | } | |
2fa2fe9a | 8695 | } |
79e53945 JB |
8696 | } |
8697 | ||
5724dbd1 DL |
8698 | static void |
8699 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8700 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8701 | { |
8702 | struct drm_device *dev = crtc->base.dev; | |
8703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8704 | u32 val, base, offset; | |
aeee5a49 | 8705 | int pipe = crtc->pipe; |
4c6baa59 | 8706 | int fourcc, pixel_format; |
6761dd31 | 8707 | unsigned int aligned_height; |
b113d5ee | 8708 | struct drm_framebuffer *fb; |
1b842c89 | 8709 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8710 | |
42a7b088 DL |
8711 | val = I915_READ(DSPCNTR(pipe)); |
8712 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8713 | return; | |
8714 | ||
d9806c9f | 8715 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8716 | if (!intel_fb) { |
4c6baa59 JB |
8717 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8718 | return; | |
8719 | } | |
8720 | ||
1b842c89 DL |
8721 | fb = &intel_fb->base; |
8722 | ||
18c5247e DV |
8723 | if (INTEL_INFO(dev)->gen >= 4) { |
8724 | if (val & DISPPLANE_TILED) { | |
49af449b | 8725 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8726 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8727 | } | |
8728 | } | |
4c6baa59 JB |
8729 | |
8730 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8731 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8732 | fb->pixel_format = fourcc; |
8733 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8734 | |
aeee5a49 | 8735 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8736 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8737 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8738 | } else { |
49af449b | 8739 | if (plane_config->tiling) |
aeee5a49 | 8740 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8741 | else |
aeee5a49 | 8742 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8743 | } |
8744 | plane_config->base = base; | |
8745 | ||
8746 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8747 | fb->width = ((val >> 16) & 0xfff) + 1; |
8748 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8749 | |
8750 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8751 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8752 | |
b113d5ee | 8753 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8754 | fb->pixel_format, |
8755 | fb->modifier[0]); | |
4c6baa59 | 8756 | |
f37b5c2b | 8757 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8758 | |
2844a921 DL |
8759 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8760 | pipe_name(pipe), fb->width, fb->height, | |
8761 | fb->bits_per_pixel, base, fb->pitches[0], | |
8762 | plane_config->size); | |
b113d5ee | 8763 | |
2d14030b | 8764 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8765 | } |
8766 | ||
0e8ffe1b | 8767 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8768 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8769 | { |
8770 | struct drm_device *dev = crtc->base.dev; | |
8771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8772 | uint32_t tmp; | |
8773 | ||
f458ebbc DV |
8774 | if (!intel_display_power_is_enabled(dev_priv, |
8775 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8776 | return false; |
8777 | ||
e143a21c | 8778 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8779 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8780 | |
0e8ffe1b DV |
8781 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8782 | if (!(tmp & PIPECONF_ENABLE)) | |
8783 | return false; | |
8784 | ||
42571aef VS |
8785 | switch (tmp & PIPECONF_BPC_MASK) { |
8786 | case PIPECONF_6BPC: | |
8787 | pipe_config->pipe_bpp = 18; | |
8788 | break; | |
8789 | case PIPECONF_8BPC: | |
8790 | pipe_config->pipe_bpp = 24; | |
8791 | break; | |
8792 | case PIPECONF_10BPC: | |
8793 | pipe_config->pipe_bpp = 30; | |
8794 | break; | |
8795 | case PIPECONF_12BPC: | |
8796 | pipe_config->pipe_bpp = 36; | |
8797 | break; | |
8798 | default: | |
8799 | break; | |
8800 | } | |
8801 | ||
b5a9fa09 DV |
8802 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8803 | pipe_config->limited_color_range = true; | |
8804 | ||
ab9412ba | 8805 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8806 | struct intel_shared_dpll *pll; |
8807 | ||
88adfff1 DV |
8808 | pipe_config->has_pch_encoder = true; |
8809 | ||
627eb5a3 DV |
8810 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8811 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8812 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8813 | |
8814 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8815 | |
c0d43d62 | 8816 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8817 | pipe_config->shared_dpll = |
8818 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8819 | } else { |
8820 | tmp = I915_READ(PCH_DPLL_SEL); | |
8821 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8822 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8823 | else | |
8824 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8825 | } | |
66e985c0 DV |
8826 | |
8827 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8828 | ||
8829 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8830 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8831 | |
8832 | tmp = pipe_config->dpll_hw_state.dpll; | |
8833 | pipe_config->pixel_multiplier = | |
8834 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8835 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8836 | |
8837 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8838 | } else { |
8839 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8840 | } |
8841 | ||
1bd1bd80 DV |
8842 | intel_get_pipe_timings(crtc, pipe_config); |
8843 | ||
2fa2fe9a DV |
8844 | ironlake_get_pfit_config(crtc, pipe_config); |
8845 | ||
0e8ffe1b DV |
8846 | return true; |
8847 | } | |
8848 | ||
be256dc7 PZ |
8849 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8850 | { | |
8851 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8852 | struct intel_crtc *crtc; |
be256dc7 | 8853 | |
d3fcc808 | 8854 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8855 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8856 | pipe_name(crtc->pipe)); |
8857 | ||
e2c719b7 RC |
8858 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8859 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8860 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8861 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8862 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8863 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8864 | "CPU PWM1 enabled\n"); |
c5107b87 | 8865 | if (IS_HASWELL(dev)) |
e2c719b7 | 8866 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8867 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8868 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8869 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8870 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8871 | "Utility pin enabled\n"); |
e2c719b7 | 8872 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8873 | |
9926ada1 PZ |
8874 | /* |
8875 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8876 | * interrupts remain enabled. We used to check for that, but since it's | |
8877 | * gen-specific and since we only disable LCPLL after we fully disable | |
8878 | * the interrupts, the check below should be enough. | |
8879 | */ | |
e2c719b7 | 8880 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8881 | } |
8882 | ||
9ccd5aeb PZ |
8883 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8884 | { | |
8885 | struct drm_device *dev = dev_priv->dev; | |
8886 | ||
8887 | if (IS_HASWELL(dev)) | |
8888 | return I915_READ(D_COMP_HSW); | |
8889 | else | |
8890 | return I915_READ(D_COMP_BDW); | |
8891 | } | |
8892 | ||
3c4c9b81 PZ |
8893 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8894 | { | |
8895 | struct drm_device *dev = dev_priv->dev; | |
8896 | ||
8897 | if (IS_HASWELL(dev)) { | |
8898 | mutex_lock(&dev_priv->rps.hw_lock); | |
8899 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8900 | val)) | |
f475dadf | 8901 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8902 | mutex_unlock(&dev_priv->rps.hw_lock); |
8903 | } else { | |
9ccd5aeb PZ |
8904 | I915_WRITE(D_COMP_BDW, val); |
8905 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8906 | } |
be256dc7 PZ |
8907 | } |
8908 | ||
8909 | /* | |
8910 | * This function implements pieces of two sequences from BSpec: | |
8911 | * - Sequence for display software to disable LCPLL | |
8912 | * - Sequence for display software to allow package C8+ | |
8913 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8914 | * register. Callers should take care of disabling all the display engine | |
8915 | * functions, doing the mode unset, fixing interrupts, etc. | |
8916 | */ | |
6ff58d53 PZ |
8917 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8918 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8919 | { |
8920 | uint32_t val; | |
8921 | ||
8922 | assert_can_disable_lcpll(dev_priv); | |
8923 | ||
8924 | val = I915_READ(LCPLL_CTL); | |
8925 | ||
8926 | if (switch_to_fclk) { | |
8927 | val |= LCPLL_CD_SOURCE_FCLK; | |
8928 | I915_WRITE(LCPLL_CTL, val); | |
8929 | ||
8930 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8931 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8932 | DRM_ERROR("Switching to FCLK failed\n"); | |
8933 | ||
8934 | val = I915_READ(LCPLL_CTL); | |
8935 | } | |
8936 | ||
8937 | val |= LCPLL_PLL_DISABLE; | |
8938 | I915_WRITE(LCPLL_CTL, val); | |
8939 | POSTING_READ(LCPLL_CTL); | |
8940 | ||
8941 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8942 | DRM_ERROR("LCPLL still locked\n"); | |
8943 | ||
9ccd5aeb | 8944 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8945 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8946 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8947 | ndelay(100); |
8948 | ||
9ccd5aeb PZ |
8949 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8950 | 1)) | |
be256dc7 PZ |
8951 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8952 | ||
8953 | if (allow_power_down) { | |
8954 | val = I915_READ(LCPLL_CTL); | |
8955 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8956 | I915_WRITE(LCPLL_CTL, val); | |
8957 | POSTING_READ(LCPLL_CTL); | |
8958 | } | |
8959 | } | |
8960 | ||
8961 | /* | |
8962 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8963 | * source. | |
8964 | */ | |
6ff58d53 | 8965 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8966 | { |
8967 | uint32_t val; | |
8968 | ||
8969 | val = I915_READ(LCPLL_CTL); | |
8970 | ||
8971 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8972 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8973 | return; | |
8974 | ||
a8a8bd54 PZ |
8975 | /* |
8976 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8977 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8978 | */ |
59bad947 | 8979 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8980 | |
be256dc7 PZ |
8981 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8982 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8983 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8984 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8985 | } |
8986 | ||
9ccd5aeb | 8987 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8988 | val |= D_COMP_COMP_FORCE; |
8989 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8990 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8991 | |
8992 | val = I915_READ(LCPLL_CTL); | |
8993 | val &= ~LCPLL_PLL_DISABLE; | |
8994 | I915_WRITE(LCPLL_CTL, val); | |
8995 | ||
8996 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8997 | DRM_ERROR("LCPLL not locked yet\n"); | |
8998 | ||
8999 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9000 | val = I915_READ(LCPLL_CTL); | |
9001 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9002 | I915_WRITE(LCPLL_CTL, val); | |
9003 | ||
9004 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9005 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9006 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9007 | } | |
215733fa | 9008 | |
59bad947 | 9009 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
9010 | } |
9011 | ||
765dab67 PZ |
9012 | /* |
9013 | * Package states C8 and deeper are really deep PC states that can only be | |
9014 | * reached when all the devices on the system allow it, so even if the graphics | |
9015 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9016 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9017 | * | |
9018 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9019 | * well is disabled and most interrupts are disabled, and these are also | |
9020 | * requirements for runtime PM. When these conditions are met, we manually do | |
9021 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9022 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9023 | * hang the machine. | |
9024 | * | |
9025 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9026 | * the state of some registers, so when we come back from PC8+ we need to | |
9027 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9028 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9029 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9030 | * because of the runtime PM support). | |
9031 | * | |
9032 | * For more, read "Display Sequences for Package C8" on the hardware | |
9033 | * documentation. | |
9034 | */ | |
a14cb6fc | 9035 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9036 | { |
c67a470b PZ |
9037 | struct drm_device *dev = dev_priv->dev; |
9038 | uint32_t val; | |
9039 | ||
c67a470b PZ |
9040 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9041 | ||
c67a470b PZ |
9042 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9043 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9044 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9045 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9046 | } | |
9047 | ||
9048 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9049 | hsw_disable_lcpll(dev_priv, true, true); |
9050 | } | |
9051 | ||
a14cb6fc | 9052 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9053 | { |
9054 | struct drm_device *dev = dev_priv->dev; | |
9055 | uint32_t val; | |
9056 | ||
c67a470b PZ |
9057 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9058 | ||
9059 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9060 | lpt_init_pch_refclk(dev); |
9061 | ||
9062 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9063 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9064 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9065 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9066 | } | |
9067 | ||
9068 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9069 | } |
9070 | ||
f8437dd1 VK |
9071 | static void broxton_modeset_global_resources(struct drm_atomic_state *state) |
9072 | { | |
9073 | struct drm_device *dev = state->dev; | |
9074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9075 | int max_pixclk = intel_mode_max_pixclk(state); | |
9076 | int req_cdclk; | |
9077 | ||
9078 | /* see the comment in valleyview_modeset_global_resources */ | |
9079 | if (WARN_ON(max_pixclk < 0)) | |
9080 | return; | |
9081 | ||
9082 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9083 | ||
9084 | if (req_cdclk != dev_priv->cdclk_freq) | |
9085 | broxton_set_cdclk(dev, req_cdclk); | |
9086 | } | |
9087 | ||
190f68c5 ACO |
9088 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9089 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9090 | { |
190f68c5 | 9091 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9092 | return -EINVAL; |
716c2e55 | 9093 | |
c7653199 | 9094 | crtc->lowfreq_avail = false; |
644cef34 | 9095 | |
c8f7a0db | 9096 | return 0; |
79e53945 JB |
9097 | } |
9098 | ||
96b7dfb7 S |
9099 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9100 | enum port port, | |
5cec258b | 9101 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9102 | { |
3148ade7 | 9103 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9104 | |
9105 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9106 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9107 | ||
9108 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9109 | case SKL_DPLL0: |
9110 | /* | |
9111 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9112 | * of the shared DPLL framework and thus needs to be read out | |
9113 | * separately | |
9114 | */ | |
9115 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9116 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9117 | break; | |
96b7dfb7 S |
9118 | case SKL_DPLL1: |
9119 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9120 | break; | |
9121 | case SKL_DPLL2: | |
9122 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9123 | break; | |
9124 | case SKL_DPLL3: | |
9125 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9126 | break; | |
96b7dfb7 S |
9127 | } |
9128 | } | |
9129 | ||
7d2c8175 DL |
9130 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9131 | enum port port, | |
5cec258b | 9132 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9133 | { |
9134 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9135 | ||
9136 | switch (pipe_config->ddi_pll_sel) { | |
9137 | case PORT_CLK_SEL_WRPLL1: | |
9138 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9139 | break; | |
9140 | case PORT_CLK_SEL_WRPLL2: | |
9141 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9142 | break; | |
9143 | } | |
9144 | } | |
9145 | ||
26804afd | 9146 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9147 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9148 | { |
9149 | struct drm_device *dev = crtc->base.dev; | |
9150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9151 | struct intel_shared_dpll *pll; |
26804afd DV |
9152 | enum port port; |
9153 | uint32_t tmp; | |
9154 | ||
9155 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9156 | ||
9157 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9158 | ||
96b7dfb7 S |
9159 | if (IS_SKYLAKE(dev)) |
9160 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
9161 | else | |
9162 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9163 | |
d452c5b6 DV |
9164 | if (pipe_config->shared_dpll >= 0) { |
9165 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9166 | ||
9167 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9168 | &pipe_config->dpll_hw_state)); | |
9169 | } | |
9170 | ||
26804afd DV |
9171 | /* |
9172 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9173 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9174 | * the PCH transcoder is on. | |
9175 | */ | |
ca370455 DL |
9176 | if (INTEL_INFO(dev)->gen < 9 && |
9177 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9178 | pipe_config->has_pch_encoder = true; |
9179 | ||
9180 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9181 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9182 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9183 | ||
9184 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9185 | } | |
9186 | } | |
9187 | ||
0e8ffe1b | 9188 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9189 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9190 | { |
9191 | struct drm_device *dev = crtc->base.dev; | |
9192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9193 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9194 | uint32_t tmp; |
9195 | ||
f458ebbc | 9196 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9197 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9198 | return false; | |
9199 | ||
e143a21c | 9200 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9201 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9202 | ||
eccb140b DV |
9203 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9204 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9205 | enum pipe trans_edp_pipe; | |
9206 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9207 | default: | |
9208 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9209 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9210 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9211 | trans_edp_pipe = PIPE_A; | |
9212 | break; | |
9213 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9214 | trans_edp_pipe = PIPE_B; | |
9215 | break; | |
9216 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9217 | trans_edp_pipe = PIPE_C; | |
9218 | break; | |
9219 | } | |
9220 | ||
9221 | if (trans_edp_pipe == crtc->pipe) | |
9222 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9223 | } | |
9224 | ||
f458ebbc | 9225 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9226 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9227 | return false; |
9228 | ||
eccb140b | 9229 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9230 | if (!(tmp & PIPECONF_ENABLE)) |
9231 | return false; | |
9232 | ||
26804afd | 9233 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9234 | |
1bd1bd80 DV |
9235 | intel_get_pipe_timings(crtc, pipe_config); |
9236 | ||
a1b2278e CK |
9237 | if (INTEL_INFO(dev)->gen >= 9) { |
9238 | skl_init_scalers(dev, crtc, pipe_config); | |
9239 | } | |
9240 | ||
2fa2fe9a | 9241 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f | 9242 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9243 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9244 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9245 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9246 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9247 | else |
9248 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
9249 | ||
a1b2278e CK |
9250 | } else { |
9251 | pipe_config->scaler_state.scaler_id = -1; | |
9252 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f | 9253 | } |
88adfff1 | 9254 | |
e59150dc JB |
9255 | if (IS_HASWELL(dev)) |
9256 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9257 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9258 | |
ebb69c95 CT |
9259 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9260 | pipe_config->pixel_multiplier = | |
9261 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9262 | } else { | |
9263 | pipe_config->pixel_multiplier = 1; | |
9264 | } | |
6c49f241 | 9265 | |
0e8ffe1b DV |
9266 | return true; |
9267 | } | |
9268 | ||
560b85bb CW |
9269 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9270 | { | |
9271 | struct drm_device *dev = crtc->dev; | |
9272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9273 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9274 | uint32_t cntl = 0, size = 0; |
560b85bb | 9275 | |
dc41c154 | 9276 | if (base) { |
3dd512fb MR |
9277 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9278 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9279 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9280 | ||
9281 | switch (stride) { | |
9282 | default: | |
9283 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9284 | width, stride); | |
9285 | stride = 256; | |
9286 | /* fallthrough */ | |
9287 | case 256: | |
9288 | case 512: | |
9289 | case 1024: | |
9290 | case 2048: | |
9291 | break; | |
4b0e333e CW |
9292 | } |
9293 | ||
dc41c154 VS |
9294 | cntl |= CURSOR_ENABLE | |
9295 | CURSOR_GAMMA_ENABLE | | |
9296 | CURSOR_FORMAT_ARGB | | |
9297 | CURSOR_STRIDE(stride); | |
9298 | ||
9299 | size = (height << 12) | width; | |
4b0e333e | 9300 | } |
560b85bb | 9301 | |
dc41c154 VS |
9302 | if (intel_crtc->cursor_cntl != 0 && |
9303 | (intel_crtc->cursor_base != base || | |
9304 | intel_crtc->cursor_size != size || | |
9305 | intel_crtc->cursor_cntl != cntl)) { | |
9306 | /* On these chipsets we can only modify the base/size/stride | |
9307 | * whilst the cursor is disabled. | |
9308 | */ | |
9309 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9310 | POSTING_READ(_CURACNTR); |
dc41c154 | 9311 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9312 | } |
560b85bb | 9313 | |
99d1f387 | 9314 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9315 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9316 | intel_crtc->cursor_base = base; |
9317 | } | |
4726e0b0 | 9318 | |
dc41c154 VS |
9319 | if (intel_crtc->cursor_size != size) { |
9320 | I915_WRITE(CURSIZE, size); | |
9321 | intel_crtc->cursor_size = size; | |
4b0e333e | 9322 | } |
560b85bb | 9323 | |
4b0e333e | 9324 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9325 | I915_WRITE(_CURACNTR, cntl); |
9326 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9327 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9328 | } |
560b85bb CW |
9329 | } |
9330 | ||
560b85bb | 9331 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9332 | { |
9333 | struct drm_device *dev = crtc->dev; | |
9334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9336 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9337 | uint32_t cntl; |
9338 | ||
9339 | cntl = 0; | |
9340 | if (base) { | |
9341 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9342 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9343 | case 64: |
9344 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9345 | break; | |
9346 | case 128: | |
9347 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9348 | break; | |
9349 | case 256: | |
9350 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9351 | break; | |
9352 | default: | |
3dd512fb | 9353 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9354 | return; |
65a21cd6 | 9355 | } |
4b0e333e | 9356 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9357 | |
9358 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9359 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9360 | } |
65a21cd6 | 9361 | |
8e7d688b | 9362 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9363 | cntl |= CURSOR_ROTATE_180; |
9364 | ||
4b0e333e CW |
9365 | if (intel_crtc->cursor_cntl != cntl) { |
9366 | I915_WRITE(CURCNTR(pipe), cntl); | |
9367 | POSTING_READ(CURCNTR(pipe)); | |
9368 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9369 | } |
4b0e333e | 9370 | |
65a21cd6 | 9371 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9372 | I915_WRITE(CURBASE(pipe), base); |
9373 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9374 | |
9375 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9376 | } |
9377 | ||
cda4b7d3 | 9378 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9379 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9380 | bool on) | |
cda4b7d3 CW |
9381 | { |
9382 | struct drm_device *dev = crtc->dev; | |
9383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9385 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9386 | int x = crtc->cursor_x; |
9387 | int y = crtc->cursor_y; | |
d6e4db15 | 9388 | u32 base = 0, pos = 0; |
cda4b7d3 | 9389 | |
d6e4db15 | 9390 | if (on) |
cda4b7d3 | 9391 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9392 | |
6e3c9717 | 9393 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9394 | base = 0; |
9395 | ||
6e3c9717 | 9396 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9397 | base = 0; |
9398 | ||
9399 | if (x < 0) { | |
3dd512fb | 9400 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
9401 | base = 0; |
9402 | ||
9403 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9404 | x = -x; | |
9405 | } | |
9406 | pos |= x << CURSOR_X_SHIFT; | |
9407 | ||
9408 | if (y < 0) { | |
3dd512fb | 9409 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
9410 | base = 0; |
9411 | ||
9412 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9413 | y = -y; | |
9414 | } | |
9415 | pos |= y << CURSOR_Y_SHIFT; | |
9416 | ||
4b0e333e | 9417 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9418 | return; |
9419 | ||
5efb3e28 VS |
9420 | I915_WRITE(CURPOS(pipe), pos); |
9421 | ||
4398ad45 VS |
9422 | /* ILK+ do this automagically */ |
9423 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9424 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
9425 | base += (intel_crtc->base.cursor->state->crtc_h * |
9426 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
9427 | } |
9428 | ||
8ac54669 | 9429 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9430 | i845_update_cursor(crtc, base); |
9431 | else | |
9432 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9433 | } |
9434 | ||
dc41c154 VS |
9435 | static bool cursor_size_ok(struct drm_device *dev, |
9436 | uint32_t width, uint32_t height) | |
9437 | { | |
9438 | if (width == 0 || height == 0) | |
9439 | return false; | |
9440 | ||
9441 | /* | |
9442 | * 845g/865g are special in that they are only limited by | |
9443 | * the width of their cursors, the height is arbitrary up to | |
9444 | * the precision of the register. Everything else requires | |
9445 | * square cursors, limited to a few power-of-two sizes. | |
9446 | */ | |
9447 | if (IS_845G(dev) || IS_I865G(dev)) { | |
9448 | if ((width & 63) != 0) | |
9449 | return false; | |
9450 | ||
9451 | if (width > (IS_845G(dev) ? 64 : 512)) | |
9452 | return false; | |
9453 | ||
9454 | if (height > 1023) | |
9455 | return false; | |
9456 | } else { | |
9457 | switch (width | height) { | |
9458 | case 256: | |
9459 | case 128: | |
9460 | if (IS_GEN2(dev)) | |
9461 | return false; | |
9462 | case 64: | |
9463 | break; | |
9464 | default: | |
9465 | return false; | |
9466 | } | |
9467 | } | |
9468 | ||
9469 | return true; | |
9470 | } | |
9471 | ||
79e53945 | 9472 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9473 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9474 | { |
7203425a | 9475 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9476 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9477 | |
7203425a | 9478 | for (i = start; i < end; i++) { |
79e53945 JB |
9479 | intel_crtc->lut_r[i] = red[i] >> 8; |
9480 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9481 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9482 | } | |
9483 | ||
9484 | intel_crtc_load_lut(crtc); | |
9485 | } | |
9486 | ||
79e53945 JB |
9487 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9488 | static struct drm_display_mode load_detect_mode = { | |
9489 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9490 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9491 | }; | |
9492 | ||
a8bb6818 DV |
9493 | struct drm_framebuffer * |
9494 | __intel_framebuffer_create(struct drm_device *dev, | |
9495 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9496 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9497 | { |
9498 | struct intel_framebuffer *intel_fb; | |
9499 | int ret; | |
9500 | ||
9501 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9502 | if (!intel_fb) { | |
6ccb81f2 | 9503 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9504 | return ERR_PTR(-ENOMEM); |
9505 | } | |
9506 | ||
9507 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9508 | if (ret) |
9509 | goto err; | |
d2dff872 CW |
9510 | |
9511 | return &intel_fb->base; | |
dd4916c5 | 9512 | err: |
6ccb81f2 | 9513 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9514 | kfree(intel_fb); |
9515 | ||
9516 | return ERR_PTR(ret); | |
d2dff872 CW |
9517 | } |
9518 | ||
b5ea642a | 9519 | static struct drm_framebuffer * |
a8bb6818 DV |
9520 | intel_framebuffer_create(struct drm_device *dev, |
9521 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9522 | struct drm_i915_gem_object *obj) | |
9523 | { | |
9524 | struct drm_framebuffer *fb; | |
9525 | int ret; | |
9526 | ||
9527 | ret = i915_mutex_lock_interruptible(dev); | |
9528 | if (ret) | |
9529 | return ERR_PTR(ret); | |
9530 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9531 | mutex_unlock(&dev->struct_mutex); | |
9532 | ||
9533 | return fb; | |
9534 | } | |
9535 | ||
d2dff872 CW |
9536 | static u32 |
9537 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9538 | { | |
9539 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9540 | return ALIGN(pitch, 64); | |
9541 | } | |
9542 | ||
9543 | static u32 | |
9544 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9545 | { | |
9546 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9547 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9548 | } |
9549 | ||
9550 | static struct drm_framebuffer * | |
9551 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9552 | struct drm_display_mode *mode, | |
9553 | int depth, int bpp) | |
9554 | { | |
9555 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9556 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9557 | |
9558 | obj = i915_gem_alloc_object(dev, | |
9559 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9560 | if (obj == NULL) | |
9561 | return ERR_PTR(-ENOMEM); | |
9562 | ||
9563 | mode_cmd.width = mode->hdisplay; | |
9564 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9565 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9566 | bpp); | |
5ca0c34a | 9567 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9568 | |
9569 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9570 | } | |
9571 | ||
9572 | static struct drm_framebuffer * | |
9573 | mode_fits_in_fbdev(struct drm_device *dev, | |
9574 | struct drm_display_mode *mode) | |
9575 | { | |
4520f53a | 9576 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9577 | struct drm_i915_private *dev_priv = dev->dev_private; |
9578 | struct drm_i915_gem_object *obj; | |
9579 | struct drm_framebuffer *fb; | |
9580 | ||
4c0e5528 | 9581 | if (!dev_priv->fbdev) |
d2dff872 CW |
9582 | return NULL; |
9583 | ||
4c0e5528 | 9584 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9585 | return NULL; |
9586 | ||
4c0e5528 DV |
9587 | obj = dev_priv->fbdev->fb->obj; |
9588 | BUG_ON(!obj); | |
9589 | ||
8bcd4553 | 9590 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9591 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9592 | fb->bits_per_pixel)) | |
d2dff872 CW |
9593 | return NULL; |
9594 | ||
01f2c773 | 9595 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9596 | return NULL; |
9597 | ||
9598 | return fb; | |
4520f53a DV |
9599 | #else |
9600 | return NULL; | |
9601 | #endif | |
d2dff872 CW |
9602 | } |
9603 | ||
d2434ab7 | 9604 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9605 | struct drm_display_mode *mode, |
51fd371b RC |
9606 | struct intel_load_detect_pipe *old, |
9607 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9608 | { |
9609 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9610 | struct intel_encoder *intel_encoder = |
9611 | intel_attached_encoder(connector); | |
79e53945 | 9612 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9613 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9614 | struct drm_crtc *crtc = NULL; |
9615 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9616 | struct drm_framebuffer *fb; |
51fd371b | 9617 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9618 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9619 | struct drm_connector_state *connector_state; |
51fd371b | 9620 | int ret, i = -1; |
79e53945 | 9621 | |
d2dff872 | 9622 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9623 | connector->base.id, connector->name, |
8e329a03 | 9624 | encoder->base.id, encoder->name); |
d2dff872 | 9625 | |
51fd371b RC |
9626 | retry: |
9627 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9628 | if (ret) | |
9629 | goto fail_unlock; | |
6e9f798d | 9630 | |
79e53945 JB |
9631 | /* |
9632 | * Algorithm gets a little messy: | |
7a5e4805 | 9633 | * |
79e53945 JB |
9634 | * - if the connector already has an assigned crtc, use it (but make |
9635 | * sure it's on first) | |
7a5e4805 | 9636 | * |
79e53945 JB |
9637 | * - try to find the first unused crtc that can drive this connector, |
9638 | * and use that if we find one | |
79e53945 JB |
9639 | */ |
9640 | ||
9641 | /* See if we already have a CRTC for this connector */ | |
9642 | if (encoder->crtc) { | |
9643 | crtc = encoder->crtc; | |
8261b191 | 9644 | |
51fd371b | 9645 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9646 | if (ret) |
9647 | goto fail_unlock; | |
9648 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9649 | if (ret) |
9650 | goto fail_unlock; | |
7b24056b | 9651 | |
24218aac | 9652 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9653 | old->load_detect_temp = false; |
9654 | ||
9655 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9656 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9657 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9658 | |
7173188d | 9659 | return true; |
79e53945 JB |
9660 | } |
9661 | ||
9662 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9663 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9664 | i++; |
9665 | if (!(encoder->possible_crtcs & (1 << i))) | |
9666 | continue; | |
83d65738 | 9667 | if (possible_crtc->state->enable) |
a459249c VS |
9668 | continue; |
9669 | /* This can occur when applying the pipe A quirk on resume. */ | |
9670 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9671 | continue; | |
9672 | ||
9673 | crtc = possible_crtc; | |
9674 | break; | |
79e53945 JB |
9675 | } |
9676 | ||
9677 | /* | |
9678 | * If we didn't find an unused CRTC, don't use any. | |
9679 | */ | |
9680 | if (!crtc) { | |
7173188d | 9681 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9682 | goto fail_unlock; |
79e53945 JB |
9683 | } |
9684 | ||
51fd371b RC |
9685 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9686 | if (ret) | |
4d02e2de DV |
9687 | goto fail_unlock; |
9688 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9689 | if (ret) | |
51fd371b | 9690 | goto fail_unlock; |
fc303101 DV |
9691 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9692 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9693 | |
9694 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9695 | intel_crtc->new_enabled = true; |
24218aac | 9696 | old->dpms_mode = connector->dpms; |
8261b191 | 9697 | old->load_detect_temp = true; |
d2dff872 | 9698 | old->release_fb = NULL; |
79e53945 | 9699 | |
83a57153 ACO |
9700 | state = drm_atomic_state_alloc(dev); |
9701 | if (!state) | |
9702 | return false; | |
9703 | ||
9704 | state->acquire_ctx = ctx; | |
9705 | ||
944b0c76 ACO |
9706 | connector_state = drm_atomic_get_connector_state(state, connector); |
9707 | if (IS_ERR(connector_state)) { | |
9708 | ret = PTR_ERR(connector_state); | |
9709 | goto fail; | |
9710 | } | |
9711 | ||
9712 | connector_state->crtc = crtc; | |
9713 | connector_state->best_encoder = &intel_encoder->base; | |
9714 | ||
6492711d CW |
9715 | if (!mode) |
9716 | mode = &load_detect_mode; | |
79e53945 | 9717 | |
d2dff872 CW |
9718 | /* We need a framebuffer large enough to accommodate all accesses |
9719 | * that the plane may generate whilst we perform load detection. | |
9720 | * We can not rely on the fbcon either being present (we get called | |
9721 | * during its initialisation to detect all boot displays, or it may | |
9722 | * not even exist) or that it is large enough to satisfy the | |
9723 | * requested mode. | |
9724 | */ | |
94352cf9 DV |
9725 | fb = mode_fits_in_fbdev(dev, mode); |
9726 | if (fb == NULL) { | |
d2dff872 | 9727 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9728 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9729 | old->release_fb = fb; | |
d2dff872 CW |
9730 | } else |
9731 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9732 | if (IS_ERR(fb)) { |
d2dff872 | 9733 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9734 | goto fail; |
79e53945 | 9735 | } |
79e53945 | 9736 | |
83a57153 | 9737 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9738 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9739 | if (old->release_fb) |
9740 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9741 | goto fail; |
79e53945 | 9742 | } |
9128b040 | 9743 | crtc->primary->crtc = crtc; |
7173188d | 9744 | |
79e53945 | 9745 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9746 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9747 | return true; |
412b61d8 VS |
9748 | |
9749 | fail: | |
83d65738 | 9750 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9751 | fail_unlock: |
83a57153 ACO |
9752 | if (state) { |
9753 | drm_atomic_state_free(state); | |
9754 | state = NULL; | |
9755 | } | |
9756 | ||
51fd371b RC |
9757 | if (ret == -EDEADLK) { |
9758 | drm_modeset_backoff(ctx); | |
9759 | goto retry; | |
9760 | } | |
9761 | ||
412b61d8 | 9762 | return false; |
79e53945 JB |
9763 | } |
9764 | ||
d2434ab7 | 9765 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9766 | struct intel_load_detect_pipe *old, |
9767 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9768 | { |
83a57153 | 9769 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9770 | struct intel_encoder *intel_encoder = |
9771 | intel_attached_encoder(connector); | |
4ef69c7a | 9772 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9773 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9775 | struct drm_atomic_state *state; |
944b0c76 | 9776 | struct drm_connector_state *connector_state; |
79e53945 | 9777 | |
d2dff872 | 9778 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9779 | connector->base.id, connector->name, |
8e329a03 | 9780 | encoder->base.id, encoder->name); |
d2dff872 | 9781 | |
8261b191 | 9782 | if (old->load_detect_temp) { |
83a57153 | 9783 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9784 | if (!state) |
9785 | goto fail; | |
83a57153 ACO |
9786 | |
9787 | state->acquire_ctx = ctx; | |
9788 | ||
944b0c76 ACO |
9789 | connector_state = drm_atomic_get_connector_state(state, connector); |
9790 | if (IS_ERR(connector_state)) | |
9791 | goto fail; | |
9792 | ||
fc303101 DV |
9793 | to_intel_connector(connector)->new_encoder = NULL; |
9794 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9795 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9796 | |
9797 | connector_state->best_encoder = NULL; | |
9798 | connector_state->crtc = NULL; | |
9799 | ||
83a57153 ACO |
9800 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9801 | ||
9802 | drm_atomic_state_free(state); | |
d2dff872 | 9803 | |
36206361 DV |
9804 | if (old->release_fb) { |
9805 | drm_framebuffer_unregister_private(old->release_fb); | |
9806 | drm_framebuffer_unreference(old->release_fb); | |
9807 | } | |
d2dff872 | 9808 | |
0622a53c | 9809 | return; |
79e53945 JB |
9810 | } |
9811 | ||
c751ce4f | 9812 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9813 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9814 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9815 | |
9816 | return; | |
9817 | fail: | |
9818 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9819 | drm_atomic_state_free(state); | |
79e53945 JB |
9820 | } |
9821 | ||
da4a1efa | 9822 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9823 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9824 | { |
9825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9826 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9827 | ||
9828 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9829 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9830 | else if (HAS_PCH_SPLIT(dev)) |
9831 | return 120000; | |
9832 | else if (!IS_GEN2(dev)) | |
9833 | return 96000; | |
9834 | else | |
9835 | return 48000; | |
9836 | } | |
9837 | ||
79e53945 | 9838 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9839 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9840 | struct intel_crtc_state *pipe_config) |
79e53945 | 9841 | { |
f1f644dc | 9842 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9843 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9844 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9845 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9846 | u32 fp; |
9847 | intel_clock_t clock; | |
da4a1efa | 9848 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9849 | |
9850 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9851 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9852 | else |
293623f7 | 9853 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9854 | |
9855 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9856 | if (IS_PINEVIEW(dev)) { |
9857 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9858 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9859 | } else { |
9860 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9861 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9862 | } | |
9863 | ||
a6c45cf0 | 9864 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9865 | if (IS_PINEVIEW(dev)) |
9866 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9867 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9868 | else |
9869 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9870 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9871 | ||
9872 | switch (dpll & DPLL_MODE_MASK) { | |
9873 | case DPLLB_MODE_DAC_SERIAL: | |
9874 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9875 | 5 : 10; | |
9876 | break; | |
9877 | case DPLLB_MODE_LVDS: | |
9878 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9879 | 7 : 14; | |
9880 | break; | |
9881 | default: | |
28c97730 | 9882 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9883 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9884 | return; |
79e53945 JB |
9885 | } |
9886 | ||
ac58c3f0 | 9887 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9888 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9889 | else |
da4a1efa | 9890 | i9xx_clock(refclk, &clock); |
79e53945 | 9891 | } else { |
0fb58223 | 9892 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9893 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9894 | |
9895 | if (is_lvds) { | |
9896 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9897 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9898 | |
9899 | if (lvds & LVDS_CLKB_POWER_UP) | |
9900 | clock.p2 = 7; | |
9901 | else | |
9902 | clock.p2 = 14; | |
79e53945 JB |
9903 | } else { |
9904 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9905 | clock.p1 = 2; | |
9906 | else { | |
9907 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9908 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9909 | } | |
9910 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9911 | clock.p2 = 4; | |
9912 | else | |
9913 | clock.p2 = 2; | |
79e53945 | 9914 | } |
da4a1efa VS |
9915 | |
9916 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9917 | } |
9918 | ||
18442d08 VS |
9919 | /* |
9920 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9921 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9922 | * encoder's get_config() function. |
9923 | */ | |
9924 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9925 | } |
9926 | ||
6878da05 VS |
9927 | int intel_dotclock_calculate(int link_freq, |
9928 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9929 | { |
f1f644dc JB |
9930 | /* |
9931 | * The calculation for the data clock is: | |
1041a02f | 9932 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9933 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9934 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9935 | * |
9936 | * and the link clock is simpler: | |
1041a02f | 9937 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9938 | */ |
9939 | ||
6878da05 VS |
9940 | if (!m_n->link_n) |
9941 | return 0; | |
f1f644dc | 9942 | |
6878da05 VS |
9943 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9944 | } | |
f1f644dc | 9945 | |
18442d08 | 9946 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9947 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9948 | { |
9949 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9950 | |
18442d08 VS |
9951 | /* read out port_clock from the DPLL */ |
9952 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9953 | |
f1f644dc | 9954 | /* |
18442d08 | 9955 | * This value does not include pixel_multiplier. |
241bfc38 | 9956 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9957 | * agree once we know their relationship in the encoder's |
9958 | * get_config() function. | |
79e53945 | 9959 | */ |
2d112de7 | 9960 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9961 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9962 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9963 | } |
9964 | ||
9965 | /** Returns the currently programmed mode of the given pipe. */ | |
9966 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9967 | struct drm_crtc *crtc) | |
9968 | { | |
548f245b | 9969 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9971 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9972 | struct drm_display_mode *mode; |
5cec258b | 9973 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9974 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9975 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9976 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9977 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9978 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9979 | |
9980 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9981 | if (!mode) | |
9982 | return NULL; | |
9983 | ||
f1f644dc JB |
9984 | /* |
9985 | * Construct a pipe_config sufficient for getting the clock info | |
9986 | * back out of crtc_clock_get. | |
9987 | * | |
9988 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9989 | * to use a real value here instead. | |
9990 | */ | |
293623f7 | 9991 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9992 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9993 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9994 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9995 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9996 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9997 | ||
773ae034 | 9998 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9999 | mode->hdisplay = (htot & 0xffff) + 1; |
10000 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10001 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10002 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10003 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10004 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10005 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10006 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10007 | ||
10008 | drm_mode_set_name(mode); | |
79e53945 JB |
10009 | |
10010 | return mode; | |
10011 | } | |
10012 | ||
652c393a JB |
10013 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10014 | { | |
10015 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10016 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10018 | |
baff296c | 10019 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10020 | return; |
10021 | ||
10022 | if (!dev_priv->lvds_downclock_avail) | |
10023 | return; | |
10024 | ||
10025 | /* | |
10026 | * Since this is called by a timer, we should never get here in | |
10027 | * the manual case. | |
10028 | */ | |
10029 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10030 | int pipe = intel_crtc->pipe; |
10031 | int dpll_reg = DPLL(pipe); | |
10032 | int dpll; | |
f6e5b160 | 10033 | |
44d98a61 | 10034 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10035 | |
8ac5a6d5 | 10036 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10037 | |
dc257cf1 | 10038 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10039 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10040 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10041 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10042 | dpll = I915_READ(dpll_reg); |
10043 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10044 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10045 | } |
10046 | ||
10047 | } | |
10048 | ||
f047e395 CW |
10049 | void intel_mark_busy(struct drm_device *dev) |
10050 | { | |
c67a470b PZ |
10051 | struct drm_i915_private *dev_priv = dev->dev_private; |
10052 | ||
f62a0076 CW |
10053 | if (dev_priv->mm.busy) |
10054 | return; | |
10055 | ||
43694d69 | 10056 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10057 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10058 | if (INTEL_INFO(dev)->gen >= 6) |
10059 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10060 | dev_priv->mm.busy = true; |
f047e395 CW |
10061 | } |
10062 | ||
10063 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10064 | { |
c67a470b | 10065 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10066 | struct drm_crtc *crtc; |
652c393a | 10067 | |
f62a0076 CW |
10068 | if (!dev_priv->mm.busy) |
10069 | return; | |
10070 | ||
10071 | dev_priv->mm.busy = false; | |
10072 | ||
70e1e0ec | 10073 | for_each_crtc(dev, crtc) { |
f4510a27 | 10074 | if (!crtc->primary->fb) |
652c393a JB |
10075 | continue; |
10076 | ||
725a5b54 | 10077 | intel_decrease_pllclock(crtc); |
652c393a | 10078 | } |
b29c19b6 | 10079 | |
3d13ef2e | 10080 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10081 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10082 | |
43694d69 | 10083 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10084 | } |
10085 | ||
f5de6e07 ACO |
10086 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
10087 | struct intel_crtc_state *crtc_state) | |
10088 | { | |
10089 | kfree(crtc->config); | |
10090 | crtc->config = crtc_state; | |
16f3f658 | 10091 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
10092 | } |
10093 | ||
79e53945 JB |
10094 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10095 | { | |
10096 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10097 | struct drm_device *dev = crtc->dev; |
10098 | struct intel_unpin_work *work; | |
67e77c5a | 10099 | |
5e2d7afc | 10100 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10101 | work = intel_crtc->unpin_work; |
10102 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10103 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10104 | |
10105 | if (work) { | |
10106 | cancel_work_sync(&work->work); | |
10107 | kfree(work); | |
10108 | } | |
79e53945 | 10109 | |
f5de6e07 | 10110 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 10111 | drm_crtc_cleanup(crtc); |
67e77c5a | 10112 | |
79e53945 JB |
10113 | kfree(intel_crtc); |
10114 | } | |
10115 | ||
6b95a207 KH |
10116 | static void intel_unpin_work_fn(struct work_struct *__work) |
10117 | { | |
10118 | struct intel_unpin_work *work = | |
10119 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10120 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10121 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10122 | |
b4a98e57 | 10123 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10124 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10125 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10126 | |
7ff0ebcc | 10127 | intel_fbc_update(dev); |
f06cc1b9 JH |
10128 | |
10129 | if (work->flip_queued_req) | |
146d84f0 | 10130 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10131 | mutex_unlock(&dev->struct_mutex); |
10132 | ||
f99d7069 | 10133 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10134 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10135 | |
b4a98e57 CW |
10136 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10137 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10138 | ||
6b95a207 KH |
10139 | kfree(work); |
10140 | } | |
10141 | ||
1afe3e9d | 10142 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10143 | struct drm_crtc *crtc) |
6b95a207 | 10144 | { |
6b95a207 KH |
10145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10146 | struct intel_unpin_work *work; | |
6b95a207 KH |
10147 | unsigned long flags; |
10148 | ||
10149 | /* Ignore early vblank irqs */ | |
10150 | if (intel_crtc == NULL) | |
10151 | return; | |
10152 | ||
f326038a DV |
10153 | /* |
10154 | * This is called both by irq handlers and the reset code (to complete | |
10155 | * lost pageflips) so needs the full irqsave spinlocks. | |
10156 | */ | |
6b95a207 KH |
10157 | spin_lock_irqsave(&dev->event_lock, flags); |
10158 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10159 | |
10160 | /* Ensure we don't miss a work->pending update ... */ | |
10161 | smp_rmb(); | |
10162 | ||
10163 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10164 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10165 | return; | |
10166 | } | |
10167 | ||
d6bbafa1 | 10168 | page_flip_completed(intel_crtc); |
0af7e4df | 10169 | |
6b95a207 | 10170 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10171 | } |
10172 | ||
1afe3e9d JB |
10173 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10174 | { | |
fbee40df | 10175 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10176 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10177 | ||
49b14a5c | 10178 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10179 | } |
10180 | ||
10181 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10182 | { | |
fbee40df | 10183 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10184 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10185 | ||
49b14a5c | 10186 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10187 | } |
10188 | ||
75f7f3ec VS |
10189 | /* Is 'a' after or equal to 'b'? */ |
10190 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10191 | { | |
10192 | return !((a - b) & 0x80000000); | |
10193 | } | |
10194 | ||
10195 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10196 | { | |
10197 | struct drm_device *dev = crtc->base.dev; | |
10198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10199 | ||
bdfa7542 VS |
10200 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10201 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10202 | return true; | |
10203 | ||
75f7f3ec VS |
10204 | /* |
10205 | * The relevant registers doen't exist on pre-ctg. | |
10206 | * As the flip done interrupt doesn't trigger for mmio | |
10207 | * flips on gmch platforms, a flip count check isn't | |
10208 | * really needed there. But since ctg has the registers, | |
10209 | * include it in the check anyway. | |
10210 | */ | |
10211 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10212 | return true; | |
10213 | ||
10214 | /* | |
10215 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10216 | * used the same base address. In that case the mmio flip might | |
10217 | * have completed, but the CS hasn't even executed the flip yet. | |
10218 | * | |
10219 | * A flip count check isn't enough as the CS might have updated | |
10220 | * the base address just after start of vblank, but before we | |
10221 | * managed to process the interrupt. This means we'd complete the | |
10222 | * CS flip too soon. | |
10223 | * | |
10224 | * Combining both checks should get us a good enough result. It may | |
10225 | * still happen that the CS flip has been executed, but has not | |
10226 | * yet actually completed. But in case the base address is the same | |
10227 | * anyway, we don't really care. | |
10228 | */ | |
10229 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10230 | crtc->unpin_work->gtt_offset && | |
10231 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10232 | crtc->unpin_work->flip_count); | |
10233 | } | |
10234 | ||
6b95a207 KH |
10235 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10236 | { | |
fbee40df | 10237 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10238 | struct intel_crtc *intel_crtc = |
10239 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10240 | unsigned long flags; | |
10241 | ||
f326038a DV |
10242 | |
10243 | /* | |
10244 | * This is called both by irq handlers and the reset code (to complete | |
10245 | * lost pageflips) so needs the full irqsave spinlocks. | |
10246 | * | |
10247 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10248 | * generate a page-flip completion irq, i.e. every modeset |
10249 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10250 | */ | |
6b95a207 | 10251 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10252 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10253 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10254 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10255 | } | |
10256 | ||
eba905b2 | 10257 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10258 | { |
10259 | /* Ensure that the work item is consistent when activating it ... */ | |
10260 | smp_wmb(); | |
10261 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10262 | /* and that it is marked active as soon as the irq could fire. */ | |
10263 | smp_wmb(); | |
10264 | } | |
10265 | ||
8c9f3aaf JB |
10266 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10267 | struct drm_crtc *crtc, | |
10268 | struct drm_framebuffer *fb, | |
ed8d1975 | 10269 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10270 | struct intel_engine_cs *ring, |
ed8d1975 | 10271 | uint32_t flags) |
8c9f3aaf | 10272 | { |
8c9f3aaf | 10273 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10274 | u32 flip_mask; |
10275 | int ret; | |
10276 | ||
6d90c952 | 10277 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10278 | if (ret) |
4fa62c89 | 10279 | return ret; |
8c9f3aaf JB |
10280 | |
10281 | /* Can't queue multiple flips, so wait for the previous | |
10282 | * one to finish before executing the next. | |
10283 | */ | |
10284 | if (intel_crtc->plane) | |
10285 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10286 | else | |
10287 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10288 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10289 | intel_ring_emit(ring, MI_NOOP); | |
10290 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10291 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10292 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10293 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10294 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10295 | |
10296 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10297 | __intel_ring_advance(ring); |
83d4092b | 10298 | return 0; |
8c9f3aaf JB |
10299 | } |
10300 | ||
10301 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10302 | struct drm_crtc *crtc, | |
10303 | struct drm_framebuffer *fb, | |
ed8d1975 | 10304 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10305 | struct intel_engine_cs *ring, |
ed8d1975 | 10306 | uint32_t flags) |
8c9f3aaf | 10307 | { |
8c9f3aaf | 10308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10309 | u32 flip_mask; |
10310 | int ret; | |
10311 | ||
6d90c952 | 10312 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10313 | if (ret) |
4fa62c89 | 10314 | return ret; |
8c9f3aaf JB |
10315 | |
10316 | if (intel_crtc->plane) | |
10317 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10318 | else | |
10319 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10320 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10321 | intel_ring_emit(ring, MI_NOOP); | |
10322 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10323 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10324 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10325 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10326 | intel_ring_emit(ring, MI_NOOP); |
10327 | ||
e7d841ca | 10328 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 10329 | __intel_ring_advance(ring); |
83d4092b | 10330 | return 0; |
8c9f3aaf JB |
10331 | } |
10332 | ||
10333 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10334 | struct drm_crtc *crtc, | |
10335 | struct drm_framebuffer *fb, | |
ed8d1975 | 10336 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10337 | struct intel_engine_cs *ring, |
ed8d1975 | 10338 | uint32_t flags) |
8c9f3aaf JB |
10339 | { |
10340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10342 | uint32_t pf, pipesrc; | |
10343 | int ret; | |
10344 | ||
6d90c952 | 10345 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10346 | if (ret) |
4fa62c89 | 10347 | return ret; |
8c9f3aaf JB |
10348 | |
10349 | /* i965+ uses the linear or tiled offsets from the | |
10350 | * Display Registers (which do not change across a page-flip) | |
10351 | * so we need only reprogram the base address. | |
10352 | */ | |
6d90c952 DV |
10353 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10354 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10355 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10356 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10357 | obj->tiling_mode); |
8c9f3aaf JB |
10358 | |
10359 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10360 | * untested on non-native modes, so ignore it for now. | |
10361 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10362 | */ | |
10363 | pf = 0; | |
10364 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10365 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10366 | |
10367 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10368 | __intel_ring_advance(ring); |
83d4092b | 10369 | return 0; |
8c9f3aaf JB |
10370 | } |
10371 | ||
10372 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10373 | struct drm_crtc *crtc, | |
10374 | struct drm_framebuffer *fb, | |
ed8d1975 | 10375 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10376 | struct intel_engine_cs *ring, |
ed8d1975 | 10377 | uint32_t flags) |
8c9f3aaf JB |
10378 | { |
10379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10381 | uint32_t pf, pipesrc; | |
10382 | int ret; | |
10383 | ||
6d90c952 | 10384 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10385 | if (ret) |
4fa62c89 | 10386 | return ret; |
8c9f3aaf | 10387 | |
6d90c952 DV |
10388 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10389 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10390 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10391 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10392 | |
dc257cf1 DV |
10393 | /* Contrary to the suggestions in the documentation, |
10394 | * "Enable Panel Fitter" does not seem to be required when page | |
10395 | * flipping with a non-native mode, and worse causes a normal | |
10396 | * modeset to fail. | |
10397 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10398 | */ | |
10399 | pf = 0; | |
8c9f3aaf | 10400 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10401 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10402 | |
10403 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10404 | __intel_ring_advance(ring); |
83d4092b | 10405 | return 0; |
8c9f3aaf JB |
10406 | } |
10407 | ||
7c9017e5 JB |
10408 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10409 | struct drm_crtc *crtc, | |
10410 | struct drm_framebuffer *fb, | |
ed8d1975 | 10411 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10412 | struct intel_engine_cs *ring, |
ed8d1975 | 10413 | uint32_t flags) |
7c9017e5 | 10414 | { |
7c9017e5 | 10415 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10416 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10417 | int len, ret; |
10418 | ||
eba905b2 | 10419 | switch (intel_crtc->plane) { |
cb05d8de DV |
10420 | case PLANE_A: |
10421 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10422 | break; | |
10423 | case PLANE_B: | |
10424 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10425 | break; | |
10426 | case PLANE_C: | |
10427 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10428 | break; | |
10429 | default: | |
10430 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10431 | return -ENODEV; |
cb05d8de DV |
10432 | } |
10433 | ||
ffe74d75 | 10434 | len = 4; |
f476828a | 10435 | if (ring->id == RCS) { |
ffe74d75 | 10436 | len += 6; |
f476828a DL |
10437 | /* |
10438 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10439 | * 48bits addresses, and we need a NOOP for the batch size to | |
10440 | * stay even. | |
10441 | */ | |
10442 | if (IS_GEN8(dev)) | |
10443 | len += 2; | |
10444 | } | |
ffe74d75 | 10445 | |
f66fab8e VS |
10446 | /* |
10447 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10448 | * "The full packet must be contained within the same cache line." | |
10449 | * | |
10450 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10451 | * cacheline, if we ever start emitting more commands before | |
10452 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10453 | * then do the cacheline alignment, and finally emit the | |
10454 | * MI_DISPLAY_FLIP. | |
10455 | */ | |
10456 | ret = intel_ring_cacheline_align(ring); | |
10457 | if (ret) | |
4fa62c89 | 10458 | return ret; |
f66fab8e | 10459 | |
ffe74d75 | 10460 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10461 | if (ret) |
4fa62c89 | 10462 | return ret; |
7c9017e5 | 10463 | |
ffe74d75 CW |
10464 | /* Unmask the flip-done completion message. Note that the bspec says that |
10465 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10466 | * more than one flip event at any time (or ensure that one flip message | |
10467 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10468 | * Experimentation says that BCS works despite DERRMR masking all | |
10469 | * flip-done completion events and that unmasking all planes at once | |
10470 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10471 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10472 | */ | |
10473 | if (ring->id == RCS) { | |
10474 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10475 | intel_ring_emit(ring, DERRMR); | |
10476 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10477 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10478 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10479 | if (IS_GEN8(dev)) |
10480 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10481 | MI_SRM_LRM_GLOBAL_GTT); | |
10482 | else | |
10483 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10484 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10485 | intel_ring_emit(ring, DERRMR); |
10486 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10487 | if (IS_GEN8(dev)) { |
10488 | intel_ring_emit(ring, 0); | |
10489 | intel_ring_emit(ring, MI_NOOP); | |
10490 | } | |
ffe74d75 CW |
10491 | } |
10492 | ||
cb05d8de | 10493 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10494 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10495 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10496 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10497 | |
10498 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10499 | __intel_ring_advance(ring); |
83d4092b | 10500 | return 0; |
7c9017e5 JB |
10501 | } |
10502 | ||
84c33a64 SG |
10503 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10504 | struct drm_i915_gem_object *obj) | |
10505 | { | |
10506 | /* | |
10507 | * This is not being used for older platforms, because | |
10508 | * non-availability of flip done interrupt forces us to use | |
10509 | * CS flips. Older platforms derive flip done using some clever | |
10510 | * tricks involving the flip_pending status bits and vblank irqs. | |
10511 | * So using MMIO flips there would disrupt this mechanism. | |
10512 | */ | |
10513 | ||
8e09bf83 CW |
10514 | if (ring == NULL) |
10515 | return true; | |
10516 | ||
84c33a64 SG |
10517 | if (INTEL_INFO(ring->dev)->gen < 5) |
10518 | return false; | |
10519 | ||
10520 | if (i915.use_mmio_flip < 0) | |
10521 | return false; | |
10522 | else if (i915.use_mmio_flip > 0) | |
10523 | return true; | |
14bf993e OM |
10524 | else if (i915.enable_execlists) |
10525 | return true; | |
84c33a64 | 10526 | else |
41c52415 | 10527 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10528 | } |
10529 | ||
ff944564 DL |
10530 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10531 | { | |
10532 | struct drm_device *dev = intel_crtc->base.dev; | |
10533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10534 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
10535 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
10536 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10537 | const enum pipe pipe = intel_crtc->pipe; | |
10538 | u32 ctl, stride; | |
10539 | ||
10540 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10541 | ctl &= ~PLANE_CTL_TILED_MASK; | |
10542 | if (obj->tiling_mode == I915_TILING_X) | |
10543 | ctl |= PLANE_CTL_TILED_X; | |
10544 | ||
10545 | /* | |
10546 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10547 | * linear buffers or in number of tiles for tiled buffers. | |
10548 | */ | |
10549 | stride = fb->pitches[0] >> 6; | |
10550 | if (obj->tiling_mode == I915_TILING_X) | |
10551 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
10552 | ||
10553 | /* | |
10554 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10555 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10556 | */ | |
10557 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10558 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10559 | ||
10560 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10561 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10562 | } | |
10563 | ||
10564 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10565 | { |
10566 | struct drm_device *dev = intel_crtc->base.dev; | |
10567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10568 | struct intel_framebuffer *intel_fb = | |
10569 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10570 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10571 | u32 dspcntr; | |
10572 | u32 reg; | |
10573 | ||
84c33a64 SG |
10574 | reg = DSPCNTR(intel_crtc->plane); |
10575 | dspcntr = I915_READ(reg); | |
10576 | ||
c5d97472 DL |
10577 | if (obj->tiling_mode != I915_TILING_NONE) |
10578 | dspcntr |= DISPPLANE_TILED; | |
10579 | else | |
10580 | dspcntr &= ~DISPPLANE_TILED; | |
10581 | ||
84c33a64 SG |
10582 | I915_WRITE(reg, dspcntr); |
10583 | ||
10584 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10585 | intel_crtc->unpin_work->gtt_offset); | |
10586 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10587 | |
ff944564 DL |
10588 | } |
10589 | ||
10590 | /* | |
10591 | * XXX: This is the temporary way to update the plane registers until we get | |
10592 | * around to using the usual plane update functions for MMIO flips | |
10593 | */ | |
10594 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10595 | { | |
10596 | struct drm_device *dev = intel_crtc->base.dev; | |
10597 | bool atomic_update; | |
10598 | u32 start_vbl_count; | |
10599 | ||
10600 | intel_mark_page_flip_active(intel_crtc); | |
10601 | ||
10602 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10603 | ||
10604 | if (INTEL_INFO(dev)->gen >= 9) | |
10605 | skl_do_mmio_flip(intel_crtc); | |
10606 | else | |
10607 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10608 | ilk_do_mmio_flip(intel_crtc); | |
10609 | ||
9362c7c5 ACO |
10610 | if (atomic_update) |
10611 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10612 | } |
10613 | ||
9362c7c5 | 10614 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10615 | { |
cc8c4cc2 | 10616 | struct intel_crtc *crtc = |
9362c7c5 | 10617 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 10618 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 10619 | |
cc8c4cc2 JH |
10620 | mmio_flip = &crtc->mmio_flip; |
10621 | if (mmio_flip->req) | |
9c654818 JH |
10622 | WARN_ON(__i915_wait_request(mmio_flip->req, |
10623 | crtc->reset_counter, | |
10624 | false, NULL, NULL) != 0); | |
84c33a64 | 10625 | |
cc8c4cc2 JH |
10626 | intel_do_mmio_flip(crtc); |
10627 | if (mmio_flip->req) { | |
10628 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 10629 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
10630 | mutex_unlock(&crtc->base.dev->struct_mutex); |
10631 | } | |
84c33a64 SG |
10632 | } |
10633 | ||
10634 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10635 | struct drm_crtc *crtc, | |
10636 | struct drm_framebuffer *fb, | |
10637 | struct drm_i915_gem_object *obj, | |
10638 | struct intel_engine_cs *ring, | |
10639 | uint32_t flags) | |
10640 | { | |
84c33a64 | 10641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 10642 | |
cc8c4cc2 JH |
10643 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
10644 | obj->last_write_req); | |
536f5b5e ACO |
10645 | |
10646 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 10647 | |
84c33a64 SG |
10648 | return 0; |
10649 | } | |
10650 | ||
8c9f3aaf JB |
10651 | static int intel_default_queue_flip(struct drm_device *dev, |
10652 | struct drm_crtc *crtc, | |
10653 | struct drm_framebuffer *fb, | |
ed8d1975 | 10654 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10655 | struct intel_engine_cs *ring, |
ed8d1975 | 10656 | uint32_t flags) |
8c9f3aaf JB |
10657 | { |
10658 | return -ENODEV; | |
10659 | } | |
10660 | ||
d6bbafa1 CW |
10661 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10662 | struct drm_crtc *crtc) | |
10663 | { | |
10664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10665 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10666 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10667 | u32 addr; | |
10668 | ||
10669 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10670 | return true; | |
10671 | ||
10672 | if (!work->enable_stall_check) | |
10673 | return false; | |
10674 | ||
10675 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10676 | if (work->flip_queued_req && |
10677 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10678 | return false; |
10679 | ||
1e3feefd | 10680 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10681 | } |
10682 | ||
1e3feefd | 10683 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10684 | return false; |
10685 | ||
10686 | /* Potential stall - if we see that the flip has happened, | |
10687 | * assume a missed interrupt. */ | |
10688 | if (INTEL_INFO(dev)->gen >= 4) | |
10689 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10690 | else | |
10691 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10692 | ||
10693 | /* There is a potential issue here with a false positive after a flip | |
10694 | * to the same address. We could address this by checking for a | |
10695 | * non-incrementing frame counter. | |
10696 | */ | |
10697 | return addr == work->gtt_offset; | |
10698 | } | |
10699 | ||
10700 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10701 | { | |
10702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10703 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10705 | struct intel_unpin_work *work; |
f326038a | 10706 | |
6c51d46f | 10707 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10708 | |
10709 | if (crtc == NULL) | |
10710 | return; | |
10711 | ||
f326038a | 10712 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10713 | work = intel_crtc->unpin_work; |
10714 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10715 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10716 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10717 | page_flip_completed(intel_crtc); |
6ad790c0 | 10718 | work = NULL; |
d6bbafa1 | 10719 | } |
6ad790c0 CW |
10720 | if (work != NULL && |
10721 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10722 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10723 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10724 | } |
10725 | ||
6b95a207 KH |
10726 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10727 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10728 | struct drm_pending_vblank_event *event, |
10729 | uint32_t page_flip_flags) | |
6b95a207 KH |
10730 | { |
10731 | struct drm_device *dev = crtc->dev; | |
10732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10733 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10734 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10735 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10736 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10737 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10738 | struct intel_unpin_work *work; |
a4872ba6 | 10739 | struct intel_engine_cs *ring; |
cf5d8a46 | 10740 | bool mmio_flip; |
52e68630 | 10741 | int ret; |
6b95a207 | 10742 | |
2ff8fde1 MR |
10743 | /* |
10744 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10745 | * check to be safe. In the future we may enable pageflipping from | |
10746 | * a disabled primary plane. | |
10747 | */ | |
10748 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10749 | return -EBUSY; | |
10750 | ||
e6a595d2 | 10751 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10752 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10753 | return -EINVAL; |
10754 | ||
10755 | /* | |
10756 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10757 | * Note that pitch changes could also affect these register. | |
10758 | */ | |
10759 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10760 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10761 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10762 | return -EINVAL; |
10763 | ||
f900db47 CW |
10764 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10765 | goto out_hang; | |
10766 | ||
b14c5679 | 10767 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10768 | if (work == NULL) |
10769 | return -ENOMEM; | |
10770 | ||
6b95a207 | 10771 | work->event = event; |
b4a98e57 | 10772 | work->crtc = crtc; |
ab8d6675 | 10773 | work->old_fb = old_fb; |
6b95a207 KH |
10774 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10775 | ||
87b6b101 | 10776 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10777 | if (ret) |
10778 | goto free_work; | |
10779 | ||
6b95a207 | 10780 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10781 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10782 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10783 | /* Before declaring the flip queue wedged, check if |
10784 | * the hardware completed the operation behind our backs. | |
10785 | */ | |
10786 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10787 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10788 | page_flip_completed(intel_crtc); | |
10789 | } else { | |
10790 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10791 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10792 | |
d6bbafa1 CW |
10793 | drm_crtc_vblank_put(crtc); |
10794 | kfree(work); | |
10795 | return -EBUSY; | |
10796 | } | |
6b95a207 KH |
10797 | } |
10798 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10799 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10800 | |
b4a98e57 CW |
10801 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10802 | flush_workqueue(dev_priv->wq); | |
10803 | ||
75dfca80 | 10804 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10805 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10806 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10807 | |
f4510a27 | 10808 | crtc->primary->fb = fb; |
afd65eb4 | 10809 | update_state_fb(crtc->primary); |
1ed1f968 | 10810 | |
e1f99ce6 | 10811 | work->pending_flip_obj = obj; |
e1f99ce6 | 10812 | |
89ed88ba CW |
10813 | ret = i915_mutex_lock_interruptible(dev); |
10814 | if (ret) | |
10815 | goto cleanup; | |
10816 | ||
b4a98e57 | 10817 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10818 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10819 | |
75f7f3ec | 10820 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10821 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10822 | |
4fa62c89 VS |
10823 | if (IS_VALLEYVIEW(dev)) { |
10824 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10825 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10826 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10827 | ring = NULL; | |
48bf5b2d | 10828 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10829 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10830 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10831 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10832 | if (ring == NULL || ring->id != RCS) |
10833 | ring = &dev_priv->ring[BCS]; | |
10834 | } else { | |
10835 | ring = &dev_priv->ring[RCS]; | |
10836 | } | |
10837 | ||
cf5d8a46 CW |
10838 | mmio_flip = use_mmio_flip(ring, obj); |
10839 | ||
10840 | /* When using CS flips, we want to emit semaphores between rings. | |
10841 | * However, when using mmio flips we will create a task to do the | |
10842 | * synchronisation, so all we want here is to pin the framebuffer | |
10843 | * into the display plane and skip any waits. | |
10844 | */ | |
82bc3b2d | 10845 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
10846 | crtc->primary->state, |
10847 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
10848 | if (ret) |
10849 | goto cleanup_pending; | |
6b95a207 | 10850 | |
121920fa TU |
10851 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10852 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10853 | |
cf5d8a46 | 10854 | if (mmio_flip) { |
84c33a64 SG |
10855 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10856 | page_flip_flags); | |
d6bbafa1 CW |
10857 | if (ret) |
10858 | goto cleanup_unpin; | |
10859 | ||
f06cc1b9 JH |
10860 | i915_gem_request_assign(&work->flip_queued_req, |
10861 | obj->last_write_req); | |
d6bbafa1 | 10862 | } else { |
84c33a64 | 10863 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10864 | page_flip_flags); |
10865 | if (ret) | |
10866 | goto cleanup_unpin; | |
10867 | ||
f06cc1b9 JH |
10868 | i915_gem_request_assign(&work->flip_queued_req, |
10869 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10870 | } |
10871 | ||
1e3feefd | 10872 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10873 | work->enable_stall_check = true; |
4fa62c89 | 10874 | |
ab8d6675 | 10875 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10876 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10877 | ||
7ff0ebcc | 10878 | intel_fbc_disable(dev); |
f99d7069 | 10879 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10880 | mutex_unlock(&dev->struct_mutex); |
10881 | ||
e5510fac JB |
10882 | trace_i915_flip_request(intel_crtc->plane, obj); |
10883 | ||
6b95a207 | 10884 | return 0; |
96b099fd | 10885 | |
4fa62c89 | 10886 | cleanup_unpin: |
82bc3b2d | 10887 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10888 | cleanup_pending: |
b4a98e57 | 10889 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10890 | mutex_unlock(&dev->struct_mutex); |
10891 | cleanup: | |
f4510a27 | 10892 | crtc->primary->fb = old_fb; |
afd65eb4 | 10893 | update_state_fb(crtc->primary); |
89ed88ba CW |
10894 | |
10895 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10896 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10897 | |
5e2d7afc | 10898 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10899 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10900 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10901 | |
87b6b101 | 10902 | drm_crtc_vblank_put(crtc); |
7317c75e | 10903 | free_work: |
96b099fd CW |
10904 | kfree(work); |
10905 | ||
f900db47 CW |
10906 | if (ret == -EIO) { |
10907 | out_hang: | |
53a366b9 | 10908 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10909 | if (ret == 0 && event) { |
5e2d7afc | 10910 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10911 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10912 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10913 | } |
f900db47 | 10914 | } |
96b099fd | 10915 | return ret; |
6b95a207 KH |
10916 | } |
10917 | ||
f6e5b160 | 10918 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10919 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10920 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10921 | .atomic_begin = intel_begin_crtc_commit, |
10922 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10923 | }; |
10924 | ||
9a935856 DV |
10925 | /** |
10926 | * intel_modeset_update_staged_output_state | |
10927 | * | |
10928 | * Updates the staged output configuration state, e.g. after we've read out the | |
10929 | * current hw state. | |
10930 | */ | |
10931 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10932 | { |
7668851f | 10933 | struct intel_crtc *crtc; |
9a935856 DV |
10934 | struct intel_encoder *encoder; |
10935 | struct intel_connector *connector; | |
f6e5b160 | 10936 | |
3a3371ff | 10937 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10938 | connector->new_encoder = |
10939 | to_intel_encoder(connector->base.encoder); | |
10940 | } | |
f6e5b160 | 10941 | |
b2784e15 | 10942 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10943 | encoder->new_crtc = |
10944 | to_intel_crtc(encoder->base.crtc); | |
10945 | } | |
7668851f | 10946 | |
d3fcc808 | 10947 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10948 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 10949 | } |
f6e5b160 CW |
10950 | } |
10951 | ||
d29b2f9d ACO |
10952 | /* Transitional helper to copy current connector/encoder state to |
10953 | * connector->state. This is needed so that code that is partially | |
10954 | * converted to atomic does the right thing. | |
10955 | */ | |
10956 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
10957 | { | |
10958 | struct intel_connector *connector; | |
10959 | ||
10960 | for_each_intel_connector(dev, connector) { | |
10961 | if (connector->base.encoder) { | |
10962 | connector->base.state->best_encoder = | |
10963 | connector->base.encoder; | |
10964 | connector->base.state->crtc = | |
10965 | connector->base.encoder->crtc; | |
10966 | } else { | |
10967 | connector->base.state->best_encoder = NULL; | |
10968 | connector->base.state->crtc = NULL; | |
10969 | } | |
10970 | } | |
10971 | } | |
10972 | ||
9a935856 DV |
10973 | /** |
10974 | * intel_modeset_commit_output_state | |
10975 | * | |
10976 | * This function copies the stage display pipe configuration to the real one. | |
10977 | */ | |
10978 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10979 | { | |
7668851f | 10980 | struct intel_crtc *crtc; |
9a935856 DV |
10981 | struct intel_encoder *encoder; |
10982 | struct intel_connector *connector; | |
f6e5b160 | 10983 | |
3a3371ff | 10984 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10985 | connector->base.encoder = &connector->new_encoder->base; |
10986 | } | |
f6e5b160 | 10987 | |
b2784e15 | 10988 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10989 | encoder->base.crtc = &encoder->new_crtc->base; |
10990 | } | |
7668851f | 10991 | |
d3fcc808 | 10992 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10993 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10994 | crtc->base.enabled = crtc->new_enabled; |
10995 | } | |
d29b2f9d ACO |
10996 | |
10997 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
10998 | } |
10999 | ||
050f7aeb | 11000 | static void |
eba905b2 | 11001 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11002 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11003 | { |
11004 | int bpp = pipe_config->pipe_bpp; | |
11005 | ||
11006 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11007 | connector->base.base.id, | |
c23cc417 | 11008 | connector->base.name); |
050f7aeb DV |
11009 | |
11010 | /* Don't use an invalid EDID bpc value */ | |
11011 | if (connector->base.display_info.bpc && | |
11012 | connector->base.display_info.bpc * 3 < bpp) { | |
11013 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11014 | bpp, connector->base.display_info.bpc*3); | |
11015 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11016 | } | |
11017 | ||
11018 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11019 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11020 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11021 | bpp); | |
11022 | pipe_config->pipe_bpp = 24; | |
11023 | } | |
11024 | } | |
11025 | ||
4e53c2e0 | 11026 | static int |
050f7aeb | 11027 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11028 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11029 | { |
050f7aeb | 11030 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11031 | struct drm_atomic_state *state; |
050f7aeb | 11032 | struct intel_connector *connector; |
1486017f | 11033 | int bpp, i; |
4e53c2e0 | 11034 | |
d328c9d7 | 11035 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11036 | bpp = 10*3; |
d328c9d7 DV |
11037 | else if (INTEL_INFO(dev)->gen >= 5) |
11038 | bpp = 12*3; | |
11039 | else | |
11040 | bpp = 8*3; | |
11041 | ||
4e53c2e0 | 11042 | |
4e53c2e0 DV |
11043 | pipe_config->pipe_bpp = bpp; |
11044 | ||
1486017f ACO |
11045 | state = pipe_config->base.state; |
11046 | ||
4e53c2e0 | 11047 | /* Clamp display bpp to EDID value */ |
1486017f ACO |
11048 | for (i = 0; i < state->num_connector; i++) { |
11049 | if (!state->connectors[i]) | |
11050 | continue; | |
11051 | ||
11052 | connector = to_intel_connector(state->connectors[i]); | |
11053 | if (state->connector_states[i]->crtc != &crtc->base) | |
4e53c2e0 DV |
11054 | continue; |
11055 | ||
050f7aeb | 11056 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
11057 | } |
11058 | ||
11059 | return bpp; | |
11060 | } | |
11061 | ||
644db711 DV |
11062 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11063 | { | |
11064 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11065 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11066 | mode->crtc_clock, |
644db711 DV |
11067 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11068 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11069 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11070 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11071 | } | |
11072 | ||
c0b03411 | 11073 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11074 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11075 | const char *context) |
11076 | { | |
6a60cd87 CK |
11077 | struct drm_device *dev = crtc->base.dev; |
11078 | struct drm_plane *plane; | |
11079 | struct intel_plane *intel_plane; | |
11080 | struct intel_plane_state *state; | |
11081 | struct drm_framebuffer *fb; | |
11082 | ||
11083 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11084 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11085 | |
11086 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11087 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11088 | pipe_config->pipe_bpp, pipe_config->dither); | |
11089 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11090 | pipe_config->has_pch_encoder, | |
11091 | pipe_config->fdi_lanes, | |
11092 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11093 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11094 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11095 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11096 | pipe_config->has_dp_encoder, | |
11097 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11098 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11099 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11100 | |
11101 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11102 | pipe_config->has_dp_encoder, | |
11103 | pipe_config->dp_m2_n2.gmch_m, | |
11104 | pipe_config->dp_m2_n2.gmch_n, | |
11105 | pipe_config->dp_m2_n2.link_m, | |
11106 | pipe_config->dp_m2_n2.link_n, | |
11107 | pipe_config->dp_m2_n2.tu); | |
11108 | ||
55072d19 DV |
11109 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11110 | pipe_config->has_audio, | |
11111 | pipe_config->has_infoframe); | |
11112 | ||
c0b03411 | 11113 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11114 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11115 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11116 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11117 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11118 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11119 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11120 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
6a60cd87 CK |
11121 | DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); |
11122 | DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); | |
11123 | DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11124 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11125 | pipe_config->gmch_pfit.control, | |
11126 | pipe_config->gmch_pfit.pgm_ratios, | |
11127 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11128 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11129 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11130 | pipe_config->pch_pfit.size, |
11131 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11132 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11133 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 CK |
11134 | |
11135 | DRM_DEBUG_KMS("planes on this crtc\n"); | |
11136 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11137 | intel_plane = to_intel_plane(plane); | |
11138 | if (intel_plane->pipe != crtc->pipe) | |
11139 | continue; | |
11140 | ||
11141 | state = to_intel_plane_state(plane->state); | |
11142 | fb = state->base.fb; | |
11143 | if (!fb) { | |
11144 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11145 | "disabled, scaler_id = %d\n", | |
11146 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11147 | plane->base.id, intel_plane->pipe, | |
11148 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11149 | drm_plane_index(plane), state->scaler_id); | |
11150 | continue; | |
11151 | } | |
11152 | ||
11153 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11154 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11155 | plane->base.id, intel_plane->pipe, | |
11156 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11157 | drm_plane_index(plane)); | |
11158 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11159 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11160 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11161 | state->scaler_id, | |
11162 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11163 | drm_rect_width(&state->src) >> 16, | |
11164 | drm_rect_height(&state->src) >> 16, | |
11165 | state->dst.x1, state->dst.y1, | |
11166 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11167 | } | |
c0b03411 DV |
11168 | } |
11169 | ||
bc079e8b VS |
11170 | static bool encoders_cloneable(const struct intel_encoder *a, |
11171 | const struct intel_encoder *b) | |
accfc0c5 | 11172 | { |
bc079e8b VS |
11173 | /* masks could be asymmetric, so check both ways */ |
11174 | return a == b || (a->cloneable & (1 << b->type) && | |
11175 | b->cloneable & (1 << a->type)); | |
11176 | } | |
11177 | ||
98a221da ACO |
11178 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11179 | struct intel_crtc *crtc, | |
bc079e8b VS |
11180 | struct intel_encoder *encoder) |
11181 | { | |
bc079e8b | 11182 | struct intel_encoder *source_encoder; |
98a221da ACO |
11183 | struct drm_connector_state *connector_state; |
11184 | int i; | |
11185 | ||
11186 | for (i = 0; i < state->num_connector; i++) { | |
11187 | if (!state->connectors[i]) | |
11188 | continue; | |
bc079e8b | 11189 | |
98a221da ACO |
11190 | connector_state = state->connector_states[i]; |
11191 | if (connector_state->crtc != &crtc->base) | |
bc079e8b VS |
11192 | continue; |
11193 | ||
98a221da ACO |
11194 | source_encoder = |
11195 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11196 | if (!encoders_cloneable(encoder, source_encoder)) |
11197 | return false; | |
11198 | } | |
11199 | ||
11200 | return true; | |
11201 | } | |
11202 | ||
98a221da ACO |
11203 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11204 | struct intel_crtc *crtc) | |
bc079e8b | 11205 | { |
accfc0c5 | 11206 | struct intel_encoder *encoder; |
98a221da ACO |
11207 | struct drm_connector_state *connector_state; |
11208 | int i; | |
accfc0c5 | 11209 | |
98a221da ACO |
11210 | for (i = 0; i < state->num_connector; i++) { |
11211 | if (!state->connectors[i]) | |
accfc0c5 DV |
11212 | continue; |
11213 | ||
98a221da ACO |
11214 | connector_state = state->connector_states[i]; |
11215 | if (connector_state->crtc != &crtc->base) | |
11216 | continue; | |
11217 | ||
11218 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11219 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11220 | return false; |
accfc0c5 DV |
11221 | } |
11222 | ||
bc079e8b | 11223 | return true; |
accfc0c5 DV |
11224 | } |
11225 | ||
5448a00d | 11226 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11227 | { |
5448a00d ACO |
11228 | struct drm_device *dev = state->dev; |
11229 | struct intel_encoder *encoder; | |
11230 | struct drm_connector_state *connector_state; | |
00f0b378 | 11231 | unsigned int used_ports = 0; |
5448a00d | 11232 | int i; |
00f0b378 VS |
11233 | |
11234 | /* | |
11235 | * Walk the connector list instead of the encoder | |
11236 | * list to detect the problem on ddi platforms | |
11237 | * where there's just one encoder per digital port. | |
11238 | */ | |
5448a00d ACO |
11239 | for (i = 0; i < state->num_connector; i++) { |
11240 | if (!state->connectors[i]) | |
11241 | continue; | |
00f0b378 | 11242 | |
5448a00d ACO |
11243 | connector_state = state->connector_states[i]; |
11244 | if (!connector_state->best_encoder) | |
00f0b378 VS |
11245 | continue; |
11246 | ||
5448a00d ACO |
11247 | encoder = to_intel_encoder(connector_state->best_encoder); |
11248 | ||
11249 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11250 | |
11251 | switch (encoder->type) { | |
11252 | unsigned int port_mask; | |
11253 | case INTEL_OUTPUT_UNKNOWN: | |
11254 | if (WARN_ON(!HAS_DDI(dev))) | |
11255 | break; | |
11256 | case INTEL_OUTPUT_DISPLAYPORT: | |
11257 | case INTEL_OUTPUT_HDMI: | |
11258 | case INTEL_OUTPUT_EDP: | |
11259 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11260 | ||
11261 | /* the same port mustn't appear more than once */ | |
11262 | if (used_ports & port_mask) | |
11263 | return false; | |
11264 | ||
11265 | used_ports |= port_mask; | |
11266 | default: | |
11267 | break; | |
11268 | } | |
11269 | } | |
11270 | ||
11271 | return true; | |
11272 | } | |
11273 | ||
83a57153 ACO |
11274 | static void |
11275 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11276 | { | |
11277 | struct drm_crtc_state tmp_state; | |
663a3640 | 11278 | struct intel_crtc_scaler_state scaler_state; |
83a57153 | 11279 | |
663a3640 | 11280 | /* Clear only the intel specific part of the crtc state excluding scalers */ |
83a57153 | 11281 | tmp_state = crtc_state->base; |
663a3640 | 11282 | scaler_state = crtc_state->scaler_state; |
83a57153 ACO |
11283 | memset(crtc_state, 0, sizeof *crtc_state); |
11284 | crtc_state->base = tmp_state; | |
663a3640 | 11285 | crtc_state->scaler_state = scaler_state; |
83a57153 ACO |
11286 | } |
11287 | ||
5cec258b | 11288 | static struct intel_crtc_state * |
b8cecdf5 | 11289 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
83a57153 ACO |
11290 | struct drm_display_mode *mode, |
11291 | struct drm_atomic_state *state) | |
ee7b9f93 | 11292 | { |
7758a113 | 11293 | struct intel_encoder *encoder; |
0b901879 ACO |
11294 | struct intel_connector *connector; |
11295 | struct drm_connector_state *connector_state; | |
5cec258b | 11296 | struct intel_crtc_state *pipe_config; |
d328c9d7 | 11297 | int base_bpp, ret = -EINVAL; |
0b901879 | 11298 | int i; |
e29c22c0 | 11299 | bool retry = true; |
ee7b9f93 | 11300 | |
98a221da | 11301 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 DV |
11302 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
11303 | return ERR_PTR(-EINVAL); | |
11304 | } | |
11305 | ||
5448a00d | 11306 | if (!check_digital_port_conflicts(state)) { |
00f0b378 VS |
11307 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
11308 | return ERR_PTR(-EINVAL); | |
11309 | } | |
11310 | ||
83a57153 ACO |
11311 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
11312 | if (IS_ERR(pipe_config)) | |
11313 | return pipe_config; | |
11314 | ||
11315 | clear_intel_crtc_state(pipe_config); | |
7758a113 | 11316 | |
07878248 | 11317 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
11318 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
11319 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 11320 | |
e143a21c DV |
11321 | pipe_config->cpu_transcoder = |
11322 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 11323 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 11324 | |
2960bc9c ID |
11325 | /* |
11326 | * Sanitize sync polarity flags based on requested ones. If neither | |
11327 | * positive or negative polarity is requested, treat this as meaning | |
11328 | * negative polarity. | |
11329 | */ | |
2d112de7 | 11330 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11331 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11332 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11333 | |
2d112de7 | 11334 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11335 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11336 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11337 | |
050f7aeb DV |
11338 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
11339 | * plane pixel format and any sink constraints into account. Returns the | |
11340 | * source plane bpp so that dithering can be selected on mismatches | |
11341 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
11342 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11343 | pipe_config); | |
11344 | if (base_bpp < 0) | |
4e53c2e0 DV |
11345 | goto fail; |
11346 | ||
e41a56be VS |
11347 | /* |
11348 | * Determine the real pipe dimensions. Note that stereo modes can | |
11349 | * increase the actual pipe size due to the frame doubling and | |
11350 | * insertion of additional space for blanks between the frame. This | |
11351 | * is stored in the crtc timings. We use the requested mode to do this | |
11352 | * computation to clearly distinguish it from the adjusted mode, which | |
11353 | * can be changed by the connectors in the below retry loop. | |
11354 | */ | |
2d112de7 | 11355 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11356 | &pipe_config->pipe_src_w, |
11357 | &pipe_config->pipe_src_h); | |
e41a56be | 11358 | |
e29c22c0 | 11359 | encoder_retry: |
ef1b460d | 11360 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11361 | pipe_config->port_clock = 0; |
ef1b460d | 11362 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11363 | |
135c81b8 | 11364 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11365 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11366 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11367 | |
7758a113 DV |
11368 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11369 | * adjust it according to limitations or connector properties, and also | |
11370 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11371 | */ |
0b901879 ACO |
11372 | for (i = 0; i < state->num_connector; i++) { |
11373 | connector = to_intel_connector(state->connectors[i]); | |
11374 | if (!connector) | |
11375 | continue; | |
47f1c6c9 | 11376 | |
0b901879 ACO |
11377 | connector_state = state->connector_states[i]; |
11378 | if (connector_state->crtc != crtc) | |
7758a113 | 11379 | continue; |
7ae89233 | 11380 | |
0b901879 ACO |
11381 | encoder = to_intel_encoder(connector_state->best_encoder); |
11382 | ||
efea6e8e DV |
11383 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11384 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11385 | goto fail; |
11386 | } | |
ee7b9f93 | 11387 | } |
47f1c6c9 | 11388 | |
ff9a6750 DV |
11389 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11390 | * done afterwards in case the encoder adjusts the mode. */ | |
11391 | if (!pipe_config->port_clock) | |
2d112de7 | 11392 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11393 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11394 | |
a43f6e0f | 11395 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11396 | if (ret < 0) { |
7758a113 DV |
11397 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11398 | goto fail; | |
ee7b9f93 | 11399 | } |
e29c22c0 DV |
11400 | |
11401 | if (ret == RETRY) { | |
11402 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11403 | ret = -EINVAL; | |
11404 | goto fail; | |
11405 | } | |
11406 | ||
11407 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11408 | retry = false; | |
11409 | goto encoder_retry; | |
11410 | } | |
11411 | ||
d328c9d7 | 11412 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 11413 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11414 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11415 | |
b8cecdf5 | 11416 | return pipe_config; |
7758a113 | 11417 | fail: |
e29c22c0 | 11418 | return ERR_PTR(ret); |
ee7b9f93 | 11419 | } |
47f1c6c9 | 11420 | |
e2e1ed41 DV |
11421 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
11422 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
11423 | static void | |
11424 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
11425 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
11426 | { |
11427 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
11428 | struct drm_device *dev = crtc->dev; |
11429 | struct intel_encoder *encoder; | |
11430 | struct intel_connector *connector; | |
11431 | struct drm_crtc *tmp_crtc; | |
79e53945 | 11432 | |
e2e1ed41 | 11433 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 11434 | |
e2e1ed41 DV |
11435 | /* Check which crtcs have changed outputs connected to them, these need |
11436 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
11437 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
11438 | * bit set at most. */ | |
3a3371ff | 11439 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
11440 | if (connector->base.encoder == &connector->new_encoder->base) |
11441 | continue; | |
79e53945 | 11442 | |
e2e1ed41 DV |
11443 | if (connector->base.encoder) { |
11444 | tmp_crtc = connector->base.encoder->crtc; | |
11445 | ||
11446 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11447 | } | |
11448 | ||
11449 | if (connector->new_encoder) | |
11450 | *prepare_pipes |= | |
11451 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
11452 | } |
11453 | ||
b2784e15 | 11454 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
11455 | if (encoder->base.crtc == &encoder->new_crtc->base) |
11456 | continue; | |
11457 | ||
11458 | if (encoder->base.crtc) { | |
11459 | tmp_crtc = encoder->base.crtc; | |
11460 | ||
11461 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11462 | } | |
11463 | ||
11464 | if (encoder->new_crtc) | |
11465 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
11466 | } |
11467 | ||
7668851f | 11468 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 11469 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11470 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 11471 | continue; |
7e7d76c3 | 11472 | |
7668851f | 11473 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 11474 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
11475 | else |
11476 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
11477 | } |
11478 | ||
e2e1ed41 DV |
11479 | |
11480 | /* set_mode is also used to update properties on life display pipes. */ | |
11481 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 11482 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
11483 | *prepare_pipes |= 1 << intel_crtc->pipe; |
11484 | ||
b6c5164d DV |
11485 | /* |
11486 | * For simplicity do a full modeset on any pipe where the output routing | |
11487 | * changed. We could be more clever, but that would require us to be | |
11488 | * more careful with calling the relevant encoder->mode_set functions. | |
11489 | */ | |
e2e1ed41 DV |
11490 | if (*prepare_pipes) |
11491 | *modeset_pipes = *prepare_pipes; | |
11492 | ||
11493 | /* ... and mask these out. */ | |
11494 | *modeset_pipes &= ~(*disable_pipes); | |
11495 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
11496 | |
11497 | /* | |
11498 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
11499 | * obies this rule, but the modeset restore mode of | |
11500 | * intel_modeset_setup_hw_state does not. | |
11501 | */ | |
11502 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
11503 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
11504 | |
11505 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
11506 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 11507 | } |
79e53945 | 11508 | |
ea9d758d | 11509 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11510 | { |
ea9d758d | 11511 | struct drm_encoder *encoder; |
f6e5b160 | 11512 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11513 | |
ea9d758d DV |
11514 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11515 | if (encoder->crtc == crtc) | |
11516 | return true; | |
11517 | ||
11518 | return false; | |
11519 | } | |
11520 | ||
11521 | static void | |
11522 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
11523 | { | |
ba41c0de | 11524 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
11525 | struct intel_encoder *intel_encoder; |
11526 | struct intel_crtc *intel_crtc; | |
11527 | struct drm_connector *connector; | |
11528 | ||
ba41c0de DV |
11529 | intel_shared_dpll_commit(dev_priv); |
11530 | ||
b2784e15 | 11531 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11532 | if (!intel_encoder->base.crtc) |
11533 | continue; | |
11534 | ||
11535 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
11536 | ||
11537 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
11538 | intel_encoder->connectors_active = false; | |
11539 | } | |
11540 | ||
11541 | intel_modeset_commit_output_state(dev); | |
11542 | ||
7668851f | 11543 | /* Double check state. */ |
d3fcc808 | 11544 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11545 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
ea9d758d DV |
11546 | } |
11547 | ||
11548 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11549 | if (!connector->encoder || !connector->encoder->crtc) | |
11550 | continue; | |
11551 | ||
11552 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
11553 | ||
11554 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
11555 | struct drm_property *dpms_property = |
11556 | dev->mode_config.dpms_property; | |
11557 | ||
ea9d758d | 11558 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11559 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11560 | dpms_property, |
11561 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11562 | |
11563 | intel_encoder = to_intel_encoder(connector->encoder); | |
11564 | intel_encoder->connectors_active = true; | |
11565 | } | |
11566 | } | |
11567 | ||
11568 | } | |
11569 | ||
3bd26263 | 11570 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11571 | { |
3bd26263 | 11572 | int diff; |
f1f644dc JB |
11573 | |
11574 | if (clock1 == clock2) | |
11575 | return true; | |
11576 | ||
11577 | if (!clock1 || !clock2) | |
11578 | return false; | |
11579 | ||
11580 | diff = abs(clock1 - clock2); | |
11581 | ||
11582 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11583 | return true; | |
11584 | ||
11585 | return false; | |
11586 | } | |
11587 | ||
25c5b266 DV |
11588 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11589 | list_for_each_entry((intel_crtc), \ | |
11590 | &(dev)->mode_config.crtc_list, \ | |
11591 | base.head) \ | |
0973f18f | 11592 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11593 | |
0e8ffe1b | 11594 | static bool |
2fa2fe9a | 11595 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11596 | struct intel_crtc_state *current_config, |
11597 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11598 | { |
66e985c0 DV |
11599 | #define PIPE_CONF_CHECK_X(name) \ |
11600 | if (current_config->name != pipe_config->name) { \ | |
11601 | DRM_ERROR("mismatch in " #name " " \ | |
11602 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11603 | current_config->name, \ | |
11604 | pipe_config->name); \ | |
11605 | return false; \ | |
11606 | } | |
11607 | ||
08a24034 DV |
11608 | #define PIPE_CONF_CHECK_I(name) \ |
11609 | if (current_config->name != pipe_config->name) { \ | |
11610 | DRM_ERROR("mismatch in " #name " " \ | |
11611 | "(expected %i, found %i)\n", \ | |
11612 | current_config->name, \ | |
11613 | pipe_config->name); \ | |
11614 | return false; \ | |
88adfff1 DV |
11615 | } |
11616 | ||
b95af8be VK |
11617 | /* This is required for BDW+ where there is only one set of registers for |
11618 | * switching between high and low RR. | |
11619 | * This macro can be used whenever a comparison has to be made between one | |
11620 | * hw state and multiple sw state variables. | |
11621 | */ | |
11622 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11623 | if ((current_config->name != pipe_config->name) && \ | |
11624 | (current_config->alt_name != pipe_config->name)) { \ | |
11625 | DRM_ERROR("mismatch in " #name " " \ | |
11626 | "(expected %i or %i, found %i)\n", \ | |
11627 | current_config->name, \ | |
11628 | current_config->alt_name, \ | |
11629 | pipe_config->name); \ | |
11630 | return false; \ | |
11631 | } | |
11632 | ||
1bd1bd80 DV |
11633 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11634 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11635 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11636 | "(expected %i, found %i)\n", \ |
11637 | current_config->name & (mask), \ | |
11638 | pipe_config->name & (mask)); \ | |
11639 | return false; \ | |
11640 | } | |
11641 | ||
5e550656 VS |
11642 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11643 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11644 | DRM_ERROR("mismatch in " #name " " \ | |
11645 | "(expected %i, found %i)\n", \ | |
11646 | current_config->name, \ | |
11647 | pipe_config->name); \ | |
11648 | return false; \ | |
11649 | } | |
11650 | ||
bb760063 DV |
11651 | #define PIPE_CONF_QUIRK(quirk) \ |
11652 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11653 | ||
eccb140b DV |
11654 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11655 | ||
08a24034 DV |
11656 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11657 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11658 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11659 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11660 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11661 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11662 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11663 | |
eb14cb74 | 11664 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11665 | |
11666 | if (INTEL_INFO(dev)->gen < 8) { | |
11667 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11668 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11669 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11670 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11671 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11672 | ||
11673 | if (current_config->has_drrs) { | |
11674 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11675 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11676 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11677 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11678 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11679 | } | |
11680 | } else { | |
11681 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11682 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11683 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11684 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11685 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11686 | } | |
eb14cb74 | 11687 | |
2d112de7 ACO |
11688 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11689 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11690 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11691 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11692 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11693 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11694 | |
2d112de7 ACO |
11695 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11696 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11697 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11698 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11699 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11700 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11701 | |
c93f54cf | 11702 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11703 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11704 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11705 | IS_VALLEYVIEW(dev)) | |
11706 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11707 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11708 | |
9ed109a7 DV |
11709 | PIPE_CONF_CHECK_I(has_audio); |
11710 | ||
2d112de7 | 11711 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11712 | DRM_MODE_FLAG_INTERLACE); |
11713 | ||
bb760063 | 11714 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11715 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11716 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11717 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11718 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11719 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11720 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11721 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11722 | DRM_MODE_FLAG_NVSYNC); |
11723 | } | |
045ac3b5 | 11724 | |
37327abd VS |
11725 | PIPE_CONF_CHECK_I(pipe_src_w); |
11726 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11727 | |
9953599b DV |
11728 | /* |
11729 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11730 | * screen. Since we don't yet re-compute the pipe config when moving | |
11731 | * just the lvds port away to another pipe the sw tracking won't match. | |
11732 | * | |
11733 | * Proper atomic modesets with recomputed global state will fix this. | |
11734 | * Until then just don't check gmch state for inherited modes. | |
11735 | */ | |
11736 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11737 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11738 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11739 | if (INTEL_INFO(dev)->gen < 4) | |
11740 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11741 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11742 | } | |
11743 | ||
fd4daa9c CW |
11744 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11745 | if (current_config->pch_pfit.enabled) { | |
11746 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11747 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11748 | } | |
2fa2fe9a | 11749 | |
a1b2278e CK |
11750 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
11751 | ||
e59150dc JB |
11752 | /* BDW+ don't expose a synchronous way to read the state */ |
11753 | if (IS_HASWELL(dev)) | |
11754 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11755 | |
282740f7 VS |
11756 | PIPE_CONF_CHECK_I(double_wide); |
11757 | ||
26804afd DV |
11758 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11759 | ||
c0d43d62 | 11760 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11761 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11762 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11763 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11764 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11765 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11766 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11767 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11768 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11769 | |
42571aef VS |
11770 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11771 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11772 | ||
2d112de7 | 11773 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11774 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11775 | |
66e985c0 | 11776 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11777 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11778 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11779 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11780 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11781 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11782 | |
0e8ffe1b DV |
11783 | return true; |
11784 | } | |
11785 | ||
08db6652 DL |
11786 | static void check_wm_state(struct drm_device *dev) |
11787 | { | |
11788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11789 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11790 | struct intel_crtc *intel_crtc; | |
11791 | int plane; | |
11792 | ||
11793 | if (INTEL_INFO(dev)->gen < 9) | |
11794 | return; | |
11795 | ||
11796 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11797 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11798 | ||
11799 | for_each_intel_crtc(dev, intel_crtc) { | |
11800 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11801 | const enum pipe pipe = intel_crtc->pipe; | |
11802 | ||
11803 | if (!intel_crtc->active) | |
11804 | continue; | |
11805 | ||
11806 | /* planes */ | |
dd740780 | 11807 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11808 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11809 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11810 | ||
11811 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11812 | continue; | |
11813 | ||
11814 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11815 | "(expected (%u,%u), found (%u,%u))\n", | |
11816 | pipe_name(pipe), plane + 1, | |
11817 | sw_entry->start, sw_entry->end, | |
11818 | hw_entry->start, hw_entry->end); | |
11819 | } | |
11820 | ||
11821 | /* cursor */ | |
11822 | hw_entry = &hw_ddb.cursor[pipe]; | |
11823 | sw_entry = &sw_ddb->cursor[pipe]; | |
11824 | ||
11825 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11826 | continue; | |
11827 | ||
11828 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11829 | "(expected (%u,%u), found (%u,%u))\n", | |
11830 | pipe_name(pipe), | |
11831 | sw_entry->start, sw_entry->end, | |
11832 | hw_entry->start, hw_entry->end); | |
11833 | } | |
11834 | } | |
11835 | ||
91d1b4bd DV |
11836 | static void |
11837 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11838 | { |
8af6cf88 DV |
11839 | struct intel_connector *connector; |
11840 | ||
3a3371ff | 11841 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11842 | /* This also checks the encoder/connector hw state with the |
11843 | * ->get_hw_state callbacks. */ | |
11844 | intel_connector_check_state(connector); | |
11845 | ||
e2c719b7 | 11846 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11847 | "connector's staged encoder doesn't match current encoder\n"); |
11848 | } | |
91d1b4bd DV |
11849 | } |
11850 | ||
11851 | static void | |
11852 | check_encoder_state(struct drm_device *dev) | |
11853 | { | |
11854 | struct intel_encoder *encoder; | |
11855 | struct intel_connector *connector; | |
8af6cf88 | 11856 | |
b2784e15 | 11857 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11858 | bool enabled = false; |
11859 | bool active = false; | |
11860 | enum pipe pipe, tracked_pipe; | |
11861 | ||
11862 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11863 | encoder->base.base.id, | |
8e329a03 | 11864 | encoder->base.name); |
8af6cf88 | 11865 | |
e2c719b7 | 11866 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11867 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11868 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11869 | "encoder's active_connectors set, but no crtc\n"); |
11870 | ||
3a3371ff | 11871 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11872 | if (connector->base.encoder != &encoder->base) |
11873 | continue; | |
11874 | enabled = true; | |
11875 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11876 | active = true; | |
11877 | } | |
0e32b39c DA |
11878 | /* |
11879 | * for MST connectors if we unplug the connector is gone | |
11880 | * away but the encoder is still connected to a crtc | |
11881 | * until a modeset happens in response to the hotplug. | |
11882 | */ | |
11883 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11884 | continue; | |
11885 | ||
e2c719b7 | 11886 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11887 | "encoder's enabled state mismatch " |
11888 | "(expected %i, found %i)\n", | |
11889 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11890 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11891 | "active encoder with no crtc\n"); |
11892 | ||
e2c719b7 | 11893 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11894 | "encoder's computed active state doesn't match tracked active state " |
11895 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11896 | ||
11897 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11898 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11899 | "encoder's hw state doesn't match sw tracking " |
11900 | "(expected %i, found %i)\n", | |
11901 | encoder->connectors_active, active); | |
11902 | ||
11903 | if (!encoder->base.crtc) | |
11904 | continue; | |
11905 | ||
11906 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11907 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11908 | "active encoder's pipe doesn't match" |
11909 | "(expected %i, found %i)\n", | |
11910 | tracked_pipe, pipe); | |
11911 | ||
11912 | } | |
91d1b4bd DV |
11913 | } |
11914 | ||
11915 | static void | |
11916 | check_crtc_state(struct drm_device *dev) | |
11917 | { | |
fbee40df | 11918 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11919 | struct intel_crtc *crtc; |
11920 | struct intel_encoder *encoder; | |
5cec258b | 11921 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11922 | |
d3fcc808 | 11923 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11924 | bool enabled = false; |
11925 | bool active = false; | |
11926 | ||
045ac3b5 JB |
11927 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11928 | ||
8af6cf88 DV |
11929 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
11930 | crtc->base.base.id); | |
11931 | ||
83d65738 | 11932 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
11933 | "active crtc, but not enabled in sw tracking\n"); |
11934 | ||
b2784e15 | 11935 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11936 | if (encoder->base.crtc != &crtc->base) |
11937 | continue; | |
11938 | enabled = true; | |
11939 | if (encoder->connectors_active) | |
11940 | active = true; | |
11941 | } | |
6c49f241 | 11942 | |
e2c719b7 | 11943 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
11944 | "crtc's computed active state doesn't match tracked active state " |
11945 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 11946 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 11947 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
11948 | "(expected %i, found %i)\n", enabled, |
11949 | crtc->base.state->enable); | |
8af6cf88 | 11950 | |
0e8ffe1b DV |
11951 | active = dev_priv->display.get_pipe_config(crtc, |
11952 | &pipe_config); | |
d62cf62a | 11953 | |
b6b5d049 VS |
11954 | /* hw state is inconsistent with the pipe quirk */ |
11955 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11956 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
11957 | active = crtc->active; |
11958 | ||
b2784e15 | 11959 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 11960 | enum pipe pipe; |
6c49f241 DV |
11961 | if (encoder->base.crtc != &crtc->base) |
11962 | continue; | |
1d37b689 | 11963 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
11964 | encoder->get_config(encoder, &pipe_config); |
11965 | } | |
11966 | ||
e2c719b7 | 11967 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
11968 | "crtc active state doesn't match with hw state " |
11969 | "(expected %i, found %i)\n", crtc->active, active); | |
11970 | ||
c0b03411 | 11971 | if (active && |
6e3c9717 | 11972 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 11973 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
11974 | intel_dump_pipe_config(crtc, &pipe_config, |
11975 | "[hw state]"); | |
6e3c9717 | 11976 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
11977 | "[sw state]"); |
11978 | } | |
8af6cf88 DV |
11979 | } |
11980 | } | |
11981 | ||
91d1b4bd DV |
11982 | static void |
11983 | check_shared_dpll_state(struct drm_device *dev) | |
11984 | { | |
fbee40df | 11985 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11986 | struct intel_crtc *crtc; |
11987 | struct intel_dpll_hw_state dpll_hw_state; | |
11988 | int i; | |
5358901f DV |
11989 | |
11990 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
11991 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11992 | int enabled_crtcs = 0, active_crtcs = 0; | |
11993 | bool active; | |
11994 | ||
11995 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
11996 | ||
11997 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11998 | ||
11999 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12000 | ||
e2c719b7 | 12001 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12002 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12003 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12004 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12005 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12006 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12007 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12008 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12009 | "pll on state mismatch (expected %i, found %i)\n", |
12010 | pll->on, active); | |
12011 | ||
d3fcc808 | 12012 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12013 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12014 | enabled_crtcs++; |
12015 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12016 | active_crtcs++; | |
12017 | } | |
e2c719b7 | 12018 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12019 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12020 | pll->active, active_crtcs); | |
e2c719b7 | 12021 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12022 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12023 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12024 | |
e2c719b7 | 12025 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12026 | sizeof(dpll_hw_state)), |
12027 | "pll hw state mismatch\n"); | |
5358901f | 12028 | } |
8af6cf88 DV |
12029 | } |
12030 | ||
91d1b4bd DV |
12031 | void |
12032 | intel_modeset_check_state(struct drm_device *dev) | |
12033 | { | |
08db6652 | 12034 | check_wm_state(dev); |
91d1b4bd DV |
12035 | check_connector_state(dev); |
12036 | check_encoder_state(dev); | |
12037 | check_crtc_state(dev); | |
12038 | check_shared_dpll_state(dev); | |
12039 | } | |
12040 | ||
5cec258b | 12041 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12042 | int dotclock) |
12043 | { | |
12044 | /* | |
12045 | * FDI already provided one idea for the dotclock. | |
12046 | * Yell if the encoder disagrees. | |
12047 | */ | |
2d112de7 | 12048 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12049 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12050 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12051 | } |
12052 | ||
80715b2f VS |
12053 | static void update_scanline_offset(struct intel_crtc *crtc) |
12054 | { | |
12055 | struct drm_device *dev = crtc->base.dev; | |
12056 | ||
12057 | /* | |
12058 | * The scanline counter increments at the leading edge of hsync. | |
12059 | * | |
12060 | * On most platforms it starts counting from vtotal-1 on the | |
12061 | * first active line. That means the scanline counter value is | |
12062 | * always one less than what we would expect. Ie. just after | |
12063 | * start of vblank, which also occurs at start of hsync (on the | |
12064 | * last active line), the scanline counter will read vblank_start-1. | |
12065 | * | |
12066 | * On gen2 the scanline counter starts counting from 1 instead | |
12067 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12068 | * to keep the value positive), instead of adding one. | |
12069 | * | |
12070 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12071 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12072 | * there's an extra 1 line difference. So we need to add two instead of | |
12073 | * one to the value. | |
12074 | */ | |
12075 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12076 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12077 | int vtotal; |
12078 | ||
12079 | vtotal = mode->crtc_vtotal; | |
12080 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12081 | vtotal /= 2; | |
12082 | ||
12083 | crtc->scanline_offset = vtotal - 1; | |
12084 | } else if (HAS_DDI(dev) && | |
409ee761 | 12085 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12086 | crtc->scanline_offset = 2; |
12087 | } else | |
12088 | crtc->scanline_offset = 1; | |
12089 | } | |
12090 | ||
5cec258b | 12091 | static struct intel_crtc_state * |
7f27126e JB |
12092 | intel_modeset_compute_config(struct drm_crtc *crtc, |
12093 | struct drm_display_mode *mode, | |
83a57153 | 12094 | struct drm_atomic_state *state, |
7f27126e JB |
12095 | unsigned *modeset_pipes, |
12096 | unsigned *prepare_pipes, | |
12097 | unsigned *disable_pipes) | |
12098 | { | |
db7542dd | 12099 | struct drm_device *dev = crtc->dev; |
5cec258b | 12100 | struct intel_crtc_state *pipe_config = NULL; |
db7542dd | 12101 | struct intel_crtc *intel_crtc; |
0b901879 ACO |
12102 | int ret = 0; |
12103 | ||
12104 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12105 | if (ret) | |
12106 | return ERR_PTR(ret); | |
7f27126e JB |
12107 | |
12108 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
12109 | prepare_pipes, disable_pipes); | |
12110 | ||
db7542dd ACO |
12111 | for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { |
12112 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12113 | if (IS_ERR(pipe_config)) | |
12114 | return pipe_config; | |
12115 | ||
12116 | pipe_config->base.enable = false; | |
12117 | } | |
7f27126e JB |
12118 | |
12119 | /* | |
12120 | * Note this needs changes when we start tracking multiple modes | |
12121 | * and crtcs. At that point we'll need to compute the whole config | |
12122 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12123 | * for this crtc. | |
12124 | */ | |
db7542dd ACO |
12125 | for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { |
12126 | /* FIXME: For now we still expect modeset_pipes has at most | |
12127 | * one bit set. */ | |
12128 | if (WARN_ON(&intel_crtc->base != crtc)) | |
12129 | continue; | |
83a57153 | 12130 | |
8805aa71 | 12131 | pipe_config = intel_modeset_pipe_config(crtc, mode, state); |
db7542dd ACO |
12132 | if (IS_ERR(pipe_config)) |
12133 | return pipe_config; | |
7f27126e | 12134 | |
304603f4 ACO |
12135 | pipe_config->base.enable = true; |
12136 | ||
db7542dd ACO |
12137 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12138 | "[modeset]"); | |
12139 | } | |
12140 | ||
12141 | return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; | |
7f27126e JB |
12142 | } |
12143 | ||
225da59b | 12144 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, |
ed6739ef ACO |
12145 | unsigned modeset_pipes, |
12146 | unsigned disable_pipes) | |
12147 | { | |
225da59b | 12148 | struct drm_device *dev = state->dev; |
ed6739ef ACO |
12149 | struct drm_i915_private *dev_priv = to_i915(dev); |
12150 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
12151 | struct intel_crtc *intel_crtc; | |
12152 | int ret = 0; | |
12153 | ||
12154 | if (!dev_priv->display.crtc_compute_clock) | |
12155 | return 0; | |
12156 | ||
12157 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
12158 | if (ret) | |
12159 | goto done; | |
12160 | ||
12161 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
225da59b ACO |
12162 | struct intel_crtc_state *crtc_state = |
12163 | intel_atomic_get_crtc_state(state, intel_crtc); | |
12164 | ||
12165 | /* Modeset pipes should have a new state by now */ | |
12166 | if (WARN_ON(IS_ERR(crtc_state))) | |
12167 | continue; | |
12168 | ||
ed6739ef | 12169 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
225da59b | 12170 | crtc_state); |
ed6739ef ACO |
12171 | if (ret) { |
12172 | intel_shared_dpll_abort_config(dev_priv); | |
12173 | goto done; | |
12174 | } | |
12175 | } | |
12176 | ||
12177 | done: | |
12178 | return ret; | |
12179 | } | |
12180 | ||
f30da187 DV |
12181 | static int __intel_set_mode(struct drm_crtc *crtc, |
12182 | struct drm_display_mode *mode, | |
7f27126e | 12183 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 12184 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12185 | unsigned modeset_pipes, |
12186 | unsigned prepare_pipes, | |
12187 | unsigned disable_pipes) | |
a6778b3c DV |
12188 | { |
12189 | struct drm_device *dev = crtc->dev; | |
fbee40df | 12190 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 12191 | struct drm_display_mode *saved_mode; |
304603f4 | 12192 | struct drm_atomic_state *state = pipe_config->base.state; |
83a57153 | 12193 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 12194 | struct intel_crtc *intel_crtc; |
c0c36b94 | 12195 | int ret = 0; |
a6778b3c | 12196 | |
4b4b9238 | 12197 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
12198 | if (!saved_mode) |
12199 | return -ENOMEM; | |
a6778b3c | 12200 | |
83a57153 ACO |
12201 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
12202 | if (!crtc_state_copy) { | |
12203 | ret = -ENOMEM; | |
12204 | goto done; | |
12205 | } | |
12206 | ||
3ac18232 | 12207 | *saved_mode = crtc->mode; |
a6778b3c | 12208 | |
30a970c6 JB |
12209 | /* |
12210 | * See if the config requires any additional preparation, e.g. | |
12211 | * to adjust global state with pipes off. We need to do this | |
12212 | * here so we can get the modeset_pipe updated config for the new | |
12213 | * mode set on this crtc. For other crtcs we need to use the | |
12214 | * adjusted_mode bits in the crtc directly. | |
12215 | */ | |
f8437dd1 | 12216 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
304603f4 ACO |
12217 | ret = valleyview_modeset_global_pipes(state, &prepare_pipes); |
12218 | if (ret) | |
12219 | goto done; | |
30a970c6 | 12220 | |
c164f833 VS |
12221 | /* may have added more to prepare_pipes than we should */ |
12222 | prepare_pipes &= ~disable_pipes; | |
12223 | } | |
12224 | ||
225da59b | 12225 | ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); |
ed6739ef ACO |
12226 | if (ret) |
12227 | goto done; | |
8bd31e67 | 12228 | |
460da916 DV |
12229 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
12230 | intel_crtc_disable(&intel_crtc->base); | |
12231 | ||
ea9d758d | 12232 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 12233 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
12234 | dev_priv->display.crtc_disable(&intel_crtc->base); |
12235 | } | |
a6778b3c | 12236 | |
6c4c86f5 DV |
12237 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
12238 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
12239 | * |
12240 | * Note we'll need to fix this up when we start tracking multiple | |
12241 | * pipes; here we assume a single modeset_pipe and only track the | |
12242 | * single crtc and mode. | |
f6e5b160 | 12243 | */ |
b8cecdf5 | 12244 | if (modeset_pipes) { |
25c5b266 | 12245 | crtc->mode = *mode; |
b8cecdf5 DV |
12246 | /* mode_set/enable/disable functions rely on a correct pipe |
12247 | * config. */ | |
f5de6e07 | 12248 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
12249 | |
12250 | /* | |
12251 | * Calculate and store various constants which | |
12252 | * are later needed by vblank and swap-completion | |
12253 | * timestamping. They are derived from true hwmode. | |
12254 | */ | |
12255 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 12256 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 12257 | } |
7758a113 | 12258 | |
ea9d758d DV |
12259 | /* Only after disabling all output pipelines that will be changed can we |
12260 | * update the the output configuration. */ | |
12261 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 12262 | |
304603f4 | 12263 | modeset_update_crtc_power_domains(state); |
47fab737 | 12264 | |
25c5b266 | 12265 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
12266 | struct drm_plane *primary = intel_crtc->base.primary; |
12267 | int vdisplay, hdisplay; | |
4c10794f | 12268 | |
455a6808 | 12269 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12270 | ret = drm_plane_helper_update(primary, &intel_crtc->base, |
12271 | fb, 0, 0, | |
12272 | hdisplay, vdisplay, | |
12273 | x << 16, y << 16, | |
12274 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
12275 | } |
12276 | ||
12277 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
12278 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
12279 | update_scanline_offset(intel_crtc); | |
12280 | ||
25c5b266 | 12281 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 12282 | } |
a6778b3c | 12283 | |
a6778b3c DV |
12284 | /* FIXME: add subpixel order */ |
12285 | done: | |
83d65738 | 12286 | if (ret && crtc->state->enable) |
3ac18232 | 12287 | crtc->mode = *saved_mode; |
a6778b3c | 12288 | |
83a57153 ACO |
12289 | if (ret == 0 && pipe_config) { |
12290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12291 | ||
12292 | /* The pipe_config will be freed with the atomic state, so | |
12293 | * make a copy. */ | |
12294 | memcpy(crtc_state_copy, intel_crtc->config, | |
12295 | sizeof *crtc_state_copy); | |
12296 | intel_crtc->config = crtc_state_copy; | |
12297 | intel_crtc->base.state = &crtc_state_copy->base; | |
83a57153 ACO |
12298 | } else { |
12299 | kfree(crtc_state_copy); | |
12300 | } | |
12301 | ||
3ac18232 | 12302 | kfree(saved_mode); |
a6778b3c | 12303 | return ret; |
f6e5b160 CW |
12304 | } |
12305 | ||
7f27126e JB |
12306 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
12307 | struct drm_display_mode *mode, | |
12308 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 12309 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12310 | unsigned modeset_pipes, |
12311 | unsigned prepare_pipes, | |
12312 | unsigned disable_pipes) | |
f30da187 DV |
12313 | { |
12314 | int ret; | |
12315 | ||
7f27126e JB |
12316 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
12317 | prepare_pipes, disable_pipes); | |
f30da187 DV |
12318 | |
12319 | if (ret == 0) | |
12320 | intel_modeset_check_state(crtc->dev); | |
12321 | ||
12322 | return ret; | |
12323 | } | |
12324 | ||
7f27126e JB |
12325 | static int intel_set_mode(struct drm_crtc *crtc, |
12326 | struct drm_display_mode *mode, | |
83a57153 ACO |
12327 | int x, int y, struct drm_framebuffer *fb, |
12328 | struct drm_atomic_state *state) | |
7f27126e | 12329 | { |
5cec258b | 12330 | struct intel_crtc_state *pipe_config; |
7f27126e | 12331 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 12332 | int ret = 0; |
7f27126e | 12333 | |
8805aa71 | 12334 | pipe_config = intel_modeset_compute_config(crtc, mode, state, |
7f27126e JB |
12335 | &modeset_pipes, |
12336 | &prepare_pipes, | |
12337 | &disable_pipes); | |
12338 | ||
83a57153 ACO |
12339 | if (IS_ERR(pipe_config)) { |
12340 | ret = PTR_ERR(pipe_config); | |
12341 | goto out; | |
12342 | } | |
12343 | ||
12344 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
12345 | modeset_pipes, prepare_pipes, | |
12346 | disable_pipes); | |
12347 | if (ret) | |
12348 | goto out; | |
7f27126e | 12349 | |
83a57153 ACO |
12350 | out: |
12351 | return ret; | |
7f27126e JB |
12352 | } |
12353 | ||
c0c36b94 CW |
12354 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
12355 | { | |
83a57153 ACO |
12356 | struct drm_device *dev = crtc->dev; |
12357 | struct drm_atomic_state *state; | |
12358 | struct intel_encoder *encoder; | |
12359 | struct intel_connector *connector; | |
12360 | struct drm_connector_state *connector_state; | |
12361 | ||
12362 | state = drm_atomic_state_alloc(dev); | |
12363 | if (!state) { | |
12364 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
12365 | crtc->base.id); | |
12366 | return; | |
12367 | } | |
12368 | ||
12369 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12370 | ||
12371 | /* The force restore path in the HW readout code relies on the staged | |
12372 | * config still keeping the user requested config while the actual | |
12373 | * state has been overwritten by the configuration read from HW. We | |
12374 | * need to copy the staged config to the atomic state, otherwise the | |
12375 | * mode set will just reapply the state the HW is already in. */ | |
12376 | for_each_intel_encoder(dev, encoder) { | |
12377 | if (&encoder->new_crtc->base != crtc) | |
12378 | continue; | |
12379 | ||
12380 | for_each_intel_connector(dev, connector) { | |
12381 | if (connector->new_encoder != encoder) | |
12382 | continue; | |
12383 | ||
12384 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
12385 | if (IS_ERR(connector_state)) { | |
12386 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
12387 | connector->base.base.id, | |
12388 | connector->base.name, | |
12389 | PTR_ERR(connector_state)); | |
12390 | continue; | |
12391 | } | |
12392 | ||
12393 | connector_state->crtc = crtc; | |
12394 | connector_state->best_encoder = &encoder->base; | |
12395 | } | |
12396 | } | |
12397 | ||
12398 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, | |
12399 | state); | |
12400 | ||
12401 | drm_atomic_state_free(state); | |
c0c36b94 CW |
12402 | } |
12403 | ||
25c5b266 DV |
12404 | #undef for_each_intel_crtc_masked |
12405 | ||
d9e55608 DV |
12406 | static void intel_set_config_free(struct intel_set_config *config) |
12407 | { | |
12408 | if (!config) | |
12409 | return; | |
12410 | ||
1aa4b628 DV |
12411 | kfree(config->save_connector_encoders); |
12412 | kfree(config->save_encoder_crtcs); | |
7668851f | 12413 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
12414 | kfree(config); |
12415 | } | |
12416 | ||
85f9eb71 DV |
12417 | static int intel_set_config_save_state(struct drm_device *dev, |
12418 | struct intel_set_config *config) | |
12419 | { | |
7668851f | 12420 | struct drm_crtc *crtc; |
85f9eb71 DV |
12421 | struct drm_encoder *encoder; |
12422 | struct drm_connector *connector; | |
12423 | int count; | |
12424 | ||
7668851f VS |
12425 | config->save_crtc_enabled = |
12426 | kcalloc(dev->mode_config.num_crtc, | |
12427 | sizeof(bool), GFP_KERNEL); | |
12428 | if (!config->save_crtc_enabled) | |
12429 | return -ENOMEM; | |
12430 | ||
1aa4b628 DV |
12431 | config->save_encoder_crtcs = |
12432 | kcalloc(dev->mode_config.num_encoder, | |
12433 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
12434 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
12435 | return -ENOMEM; |
12436 | ||
1aa4b628 DV |
12437 | config->save_connector_encoders = |
12438 | kcalloc(dev->mode_config.num_connector, | |
12439 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
12440 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
12441 | return -ENOMEM; |
12442 | ||
12443 | /* Copy data. Note that driver private data is not affected. | |
12444 | * Should anything bad happen only the expected state is | |
12445 | * restored, not the drivers personal bookkeeping. | |
12446 | */ | |
7668851f | 12447 | count = 0; |
70e1e0ec | 12448 | for_each_crtc(dev, crtc) { |
83d65738 | 12449 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
12450 | } |
12451 | ||
85f9eb71 DV |
12452 | count = 0; |
12453 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 12454 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
12455 | } |
12456 | ||
12457 | count = 0; | |
12458 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 12459 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
12460 | } |
12461 | ||
12462 | return 0; | |
12463 | } | |
12464 | ||
12465 | static void intel_set_config_restore_state(struct drm_device *dev, | |
12466 | struct intel_set_config *config) | |
12467 | { | |
7668851f | 12468 | struct intel_crtc *crtc; |
9a935856 DV |
12469 | struct intel_encoder *encoder; |
12470 | struct intel_connector *connector; | |
85f9eb71 DV |
12471 | int count; |
12472 | ||
7668851f | 12473 | count = 0; |
d3fcc808 | 12474 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12475 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
12476 | } | |
12477 | ||
85f9eb71 | 12478 | count = 0; |
b2784e15 | 12479 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
12480 | encoder->new_crtc = |
12481 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
12482 | } |
12483 | ||
12484 | count = 0; | |
3a3371ff | 12485 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12486 | connector->new_encoder = |
12487 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
12488 | } |
12489 | } | |
12490 | ||
e3de42b6 | 12491 | static bool |
2e57f47d | 12492 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
12493 | { |
12494 | int i; | |
12495 | ||
2e57f47d CW |
12496 | if (set->num_connectors == 0) |
12497 | return false; | |
12498 | ||
12499 | if (WARN_ON(set->connectors == NULL)) | |
12500 | return false; | |
12501 | ||
12502 | for (i = 0; i < set->num_connectors; i++) | |
12503 | if (set->connectors[i]->encoder && | |
12504 | set->connectors[i]->encoder->crtc == set->crtc && | |
12505 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
12506 | return true; |
12507 | ||
12508 | return false; | |
12509 | } | |
12510 | ||
5e2b584e DV |
12511 | static void |
12512 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
12513 | struct intel_set_config *config) | |
12514 | { | |
12515 | ||
12516 | /* We should be able to check here if the fb has the same properties | |
12517 | * and then just flip_or_move it */ | |
2e57f47d CW |
12518 | if (is_crtc_connector_off(set)) { |
12519 | config->mode_changed = true; | |
f4510a27 | 12520 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
12521 | /* |
12522 | * If we have no fb, we can only flip as long as the crtc is | |
12523 | * active, otherwise we need a full mode set. The crtc may | |
12524 | * be active if we've only disabled the primary plane, or | |
12525 | * in fastboot situations. | |
12526 | */ | |
f4510a27 | 12527 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
12528 | struct intel_crtc *intel_crtc = |
12529 | to_intel_crtc(set->crtc); | |
12530 | ||
3b150f08 | 12531 | if (intel_crtc->active) { |
319d9827 JB |
12532 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
12533 | config->fb_changed = true; | |
12534 | } else { | |
12535 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
12536 | config->mode_changed = true; | |
12537 | } | |
5e2b584e DV |
12538 | } else if (set->fb == NULL) { |
12539 | config->mode_changed = true; | |
72f4901e | 12540 | } else if (set->fb->pixel_format != |
f4510a27 | 12541 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 12542 | config->mode_changed = true; |
e3de42b6 | 12543 | } else { |
5e2b584e | 12544 | config->fb_changed = true; |
e3de42b6 | 12545 | } |
5e2b584e DV |
12546 | } |
12547 | ||
835c5873 | 12548 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
12549 | config->fb_changed = true; |
12550 | ||
12551 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
12552 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
12553 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
12554 | drm_mode_debug_printmodeline(set->mode); | |
12555 | config->mode_changed = true; | |
12556 | } | |
a1d95703 CW |
12557 | |
12558 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
12559 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
12560 | } |
12561 | ||
2e431051 | 12562 | static int |
9a935856 DV |
12563 | intel_modeset_stage_output_state(struct drm_device *dev, |
12564 | struct drm_mode_set *set, | |
944b0c76 ACO |
12565 | struct intel_set_config *config, |
12566 | struct drm_atomic_state *state) | |
50f56119 | 12567 | { |
9a935856 | 12568 | struct intel_connector *connector; |
944b0c76 | 12569 | struct drm_connector_state *connector_state; |
9a935856 | 12570 | struct intel_encoder *encoder; |
7668851f | 12571 | struct intel_crtc *crtc; |
f3f08572 | 12572 | int ro; |
50f56119 | 12573 | |
9abdda74 | 12574 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12575 | * of connectors. For paranoia, double-check this. */ |
12576 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12577 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12578 | ||
3a3371ff | 12579 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12580 | /* Otherwise traverse passed in connector list and get encoders |
12581 | * for them. */ | |
50f56119 | 12582 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 12583 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 12584 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
12585 | break; |
12586 | } | |
12587 | } | |
12588 | ||
9a935856 DV |
12589 | /* If we disable the crtc, disable all its connectors. Also, if |
12590 | * the connector is on the changing crtc but not on the new | |
12591 | * connector list, disable it. */ | |
12592 | if ((!set->fb || ro == set->num_connectors) && | |
12593 | connector->base.encoder && | |
12594 | connector->base.encoder->crtc == set->crtc) { | |
12595 | connector->new_encoder = NULL; | |
12596 | ||
12597 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12598 | connector->base.base.id, | |
c23cc417 | 12599 | connector->base.name); |
9a935856 DV |
12600 | } |
12601 | ||
12602 | ||
12603 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
12604 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
12605 | connector->base.base.id, | |
12606 | connector->base.name); | |
5e2b584e | 12607 | config->mode_changed = true; |
50f56119 DV |
12608 | } |
12609 | } | |
9a935856 | 12610 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12611 | |
9a935856 | 12612 | /* Update crtc of enabled connectors. */ |
3a3371ff | 12613 | for_each_intel_connector(dev, connector) { |
7668851f VS |
12614 | struct drm_crtc *new_crtc; |
12615 | ||
9a935856 | 12616 | if (!connector->new_encoder) |
50f56119 DV |
12617 | continue; |
12618 | ||
9a935856 | 12619 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
12620 | |
12621 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 12622 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
12623 | new_crtc = set->crtc; |
12624 | } | |
12625 | ||
12626 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
12627 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
12628 | new_crtc)) { | |
5e2b584e | 12629 | return -EINVAL; |
50f56119 | 12630 | } |
0e32b39c | 12631 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 12632 | |
944b0c76 ACO |
12633 | connector_state = |
12634 | drm_atomic_get_connector_state(state, &connector->base); | |
12635 | if (IS_ERR(connector_state)) | |
12636 | return PTR_ERR(connector_state); | |
12637 | ||
12638 | connector_state->crtc = new_crtc; | |
12639 | connector_state->best_encoder = &connector->new_encoder->base; | |
12640 | ||
9a935856 DV |
12641 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12642 | connector->base.base.id, | |
c23cc417 | 12643 | connector->base.name, |
9a935856 DV |
12644 | new_crtc->base.id); |
12645 | } | |
12646 | ||
12647 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 12648 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 12649 | int num_connectors = 0; |
3a3371ff | 12650 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12651 | if (connector->new_encoder == encoder) { |
12652 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 12653 | num_connectors++; |
9a935856 DV |
12654 | } |
12655 | } | |
5a65f358 PZ |
12656 | |
12657 | if (num_connectors == 0) | |
12658 | encoder->new_crtc = NULL; | |
12659 | else if (num_connectors > 1) | |
12660 | return -EINVAL; | |
12661 | ||
9a935856 DV |
12662 | /* Only now check for crtc changes so we don't miss encoders |
12663 | * that will be disabled. */ | |
12664 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
12665 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
12666 | encoder->base.base.id, | |
12667 | encoder->base.name); | |
5e2b584e | 12668 | config->mode_changed = true; |
50f56119 DV |
12669 | } |
12670 | } | |
9a935856 | 12671 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 12672 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
12673 | connector_state = |
12674 | drm_atomic_get_connector_state(state, &connector->base); | |
9d918c15 ACO |
12675 | if (IS_ERR(connector_state)) |
12676 | return PTR_ERR(connector_state); | |
944b0c76 ACO |
12677 | |
12678 | if (connector->new_encoder) { | |
0e32b39c DA |
12679 | if (connector->new_encoder != connector->encoder) |
12680 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
12681 | } else { |
12682 | connector_state->crtc = NULL; | |
f61cccf3 | 12683 | connector_state->best_encoder = NULL; |
944b0c76 | 12684 | } |
0e32b39c | 12685 | } |
d3fcc808 | 12686 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12687 | crtc->new_enabled = false; |
12688 | ||
b2784e15 | 12689 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
12690 | if (encoder->new_crtc == crtc) { |
12691 | crtc->new_enabled = true; | |
12692 | break; | |
12693 | } | |
12694 | } | |
12695 | ||
83d65738 | 12696 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
12697 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
12698 | crtc->base.base.id, | |
7668851f VS |
12699 | crtc->new_enabled ? "en" : "dis"); |
12700 | config->mode_changed = true; | |
12701 | } | |
12702 | } | |
12703 | ||
2e431051 DV |
12704 | return 0; |
12705 | } | |
12706 | ||
7d00a1f5 VS |
12707 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
12708 | { | |
12709 | struct drm_device *dev = crtc->base.dev; | |
12710 | struct intel_encoder *encoder; | |
12711 | struct intel_connector *connector; | |
12712 | ||
12713 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
12714 | pipe_name(crtc->pipe)); | |
12715 | ||
3a3371ff | 12716 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
12717 | if (connector->new_encoder && |
12718 | connector->new_encoder->new_crtc == crtc) | |
12719 | connector->new_encoder = NULL; | |
12720 | } | |
12721 | ||
b2784e15 | 12722 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
12723 | if (encoder->new_crtc == crtc) |
12724 | encoder->new_crtc = NULL; | |
12725 | } | |
12726 | ||
12727 | crtc->new_enabled = false; | |
12728 | } | |
12729 | ||
2e431051 DV |
12730 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12731 | { | |
12732 | struct drm_device *dev; | |
2e431051 | 12733 | struct drm_mode_set save_set; |
83a57153 | 12734 | struct drm_atomic_state *state = NULL; |
2e431051 | 12735 | struct intel_set_config *config; |
5cec258b | 12736 | struct intel_crtc_state *pipe_config; |
50f52756 | 12737 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 12738 | int ret; |
2e431051 | 12739 | |
8d3e375e DV |
12740 | BUG_ON(!set); |
12741 | BUG_ON(!set->crtc); | |
12742 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12743 | |
7e53f3a4 DV |
12744 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12745 | BUG_ON(!set->mode && set->fb); | |
12746 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12747 | |
2e431051 DV |
12748 | if (set->fb) { |
12749 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12750 | set->crtc->base.id, set->fb->base.id, | |
12751 | (int)set->num_connectors, set->x, set->y); | |
12752 | } else { | |
12753 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12754 | } |
12755 | ||
12756 | dev = set->crtc->dev; | |
12757 | ||
12758 | ret = -ENOMEM; | |
12759 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12760 | if (!config) | |
12761 | goto out_config; | |
12762 | ||
12763 | ret = intel_set_config_save_state(dev, config); | |
12764 | if (ret) | |
12765 | goto out_config; | |
12766 | ||
12767 | save_set.crtc = set->crtc; | |
12768 | save_set.mode = &set->crtc->mode; | |
12769 | save_set.x = set->crtc->x; | |
12770 | save_set.y = set->crtc->y; | |
f4510a27 | 12771 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
12772 | |
12773 | /* Compute whether we need a full modeset, only an fb base update or no | |
12774 | * change at all. In the future we might also check whether only the | |
12775 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12776 | * such cases. */ | |
12777 | intel_set_config_compute_mode_changes(set, config); | |
12778 | ||
83a57153 ACO |
12779 | state = drm_atomic_state_alloc(dev); |
12780 | if (!state) { | |
12781 | ret = -ENOMEM; | |
12782 | goto out_config; | |
12783 | } | |
12784 | ||
12785 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12786 | ||
944b0c76 | 12787 | ret = intel_modeset_stage_output_state(dev, set, config, state); |
2e431051 DV |
12788 | if (ret) |
12789 | goto fail; | |
12790 | ||
50f52756 | 12791 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
8805aa71 | 12792 | state, |
50f52756 JB |
12793 | &modeset_pipes, |
12794 | &prepare_pipes, | |
12795 | &disable_pipes); | |
20664591 | 12796 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12797 | ret = PTR_ERR(pipe_config); |
50f52756 | 12798 | goto fail; |
20664591 | 12799 | } else if (pipe_config) { |
b9950a13 | 12800 | if (pipe_config->has_audio != |
6e3c9717 | 12801 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12802 | config->mode_changed = true; |
12803 | ||
af15d2ce JB |
12804 | /* |
12805 | * Note we have an issue here with infoframes: current code | |
12806 | * only updates them on the full mode set path per hw | |
12807 | * requirements. So here we should be checking for any | |
12808 | * required changes and forcing a mode set. | |
12809 | */ | |
20664591 | 12810 | } |
50f52756 | 12811 | |
1f9954d0 JB |
12812 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12813 | ||
5e2b584e | 12814 | if (config->mode_changed) { |
50f52756 JB |
12815 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12816 | set->x, set->y, set->fb, pipe_config, | |
12817 | modeset_pipes, prepare_pipes, | |
12818 | disable_pipes); | |
5e2b584e | 12819 | } else if (config->fb_changed) { |
3b150f08 | 12820 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
12821 | struct drm_plane *primary = set->crtc->primary; |
12822 | int vdisplay, hdisplay; | |
3b150f08 | 12823 | |
455a6808 | 12824 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12825 | ret = drm_plane_helper_update(primary, set->crtc, set->fb, |
12826 | 0, 0, hdisplay, vdisplay, | |
12827 | set->x << 16, set->y << 16, | |
12828 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12829 | |
12830 | /* | |
12831 | * We need to make sure the primary plane is re-enabled if it | |
12832 | * has previously been turned off. | |
12833 | */ | |
12834 | if (!intel_crtc->primary_enabled && ret == 0) { | |
12835 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 12836 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
12837 | } |
12838 | ||
7ca51a3a JB |
12839 | /* |
12840 | * In the fastboot case this may be our only check of the | |
12841 | * state after boot. It would be better to only do it on | |
12842 | * the first update, but we don't have a nice way of doing that | |
12843 | * (and really, set_config isn't used much for high freq page | |
12844 | * flipping, so increasing its cost here shouldn't be a big | |
12845 | * deal). | |
12846 | */ | |
d330a953 | 12847 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12848 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12849 | } |
12850 | ||
2d05eae1 | 12851 | if (ret) { |
bf67dfeb DV |
12852 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12853 | set->crtc->base.id, ret); | |
50f56119 | 12854 | fail: |
2d05eae1 | 12855 | intel_set_config_restore_state(dev, config); |
50f56119 | 12856 | |
83a57153 ACO |
12857 | drm_atomic_state_clear(state); |
12858 | ||
7d00a1f5 VS |
12859 | /* |
12860 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12861 | * force the pipe off to avoid oopsing in the modeset code | |
12862 | * due to fb==NULL. This should only happen during boot since | |
12863 | * we don't yet reconstruct the FB from the hardware state. | |
12864 | */ | |
12865 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12866 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
12867 | ||
2d05eae1 CW |
12868 | /* Try to restore the config */ |
12869 | if (config->mode_changed && | |
12870 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
12871 | save_set.x, save_set.y, save_set.fb, |
12872 | state)) | |
2d05eae1 CW |
12873 | DRM_ERROR("failed to restore config after modeset failure\n"); |
12874 | } | |
50f56119 | 12875 | |
d9e55608 | 12876 | out_config: |
83a57153 ACO |
12877 | if (state) |
12878 | drm_atomic_state_free(state); | |
12879 | ||
d9e55608 | 12880 | intel_set_config_free(config); |
50f56119 DV |
12881 | return ret; |
12882 | } | |
f6e5b160 CW |
12883 | |
12884 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12885 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12886 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12887 | .destroy = intel_crtc_destroy, |
12888 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12889 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12890 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12891 | }; |
12892 | ||
5358901f DV |
12893 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12894 | struct intel_shared_dpll *pll, | |
12895 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12896 | { |
5358901f | 12897 | uint32_t val; |
ee7b9f93 | 12898 | |
f458ebbc | 12899 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12900 | return false; |
12901 | ||
5358901f | 12902 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12903 | hw_state->dpll = val; |
12904 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12905 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12906 | |
12907 | return val & DPLL_VCO_ENABLE; | |
12908 | } | |
12909 | ||
15bdd4cf DV |
12910 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12911 | struct intel_shared_dpll *pll) | |
12912 | { | |
3e369b76 ACO |
12913 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12914 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12915 | } |
12916 | ||
e7b903d2 DV |
12917 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12918 | struct intel_shared_dpll *pll) | |
12919 | { | |
e7b903d2 | 12920 | /* PCH refclock must be enabled first */ |
89eff4be | 12921 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12922 | |
3e369b76 | 12923 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12924 | |
12925 | /* Wait for the clocks to stabilize. */ | |
12926 | POSTING_READ(PCH_DPLL(pll->id)); | |
12927 | udelay(150); | |
12928 | ||
12929 | /* The pixel multiplier can only be updated once the | |
12930 | * DPLL is enabled and the clocks are stable. | |
12931 | * | |
12932 | * So write it again. | |
12933 | */ | |
3e369b76 | 12934 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12935 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12936 | udelay(200); |
12937 | } | |
12938 | ||
12939 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12940 | struct intel_shared_dpll *pll) | |
12941 | { | |
12942 | struct drm_device *dev = dev_priv->dev; | |
12943 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12944 | |
12945 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12946 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12947 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12948 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12949 | } |
12950 | ||
15bdd4cf DV |
12951 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12952 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12953 | udelay(200); |
12954 | } | |
12955 | ||
46edb027 DV |
12956 | static char *ibx_pch_dpll_names[] = { |
12957 | "PCH DPLL A", | |
12958 | "PCH DPLL B", | |
12959 | }; | |
12960 | ||
7c74ade1 | 12961 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12962 | { |
e7b903d2 | 12963 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12964 | int i; |
12965 | ||
7c74ade1 | 12966 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12967 | |
e72f9fbf | 12968 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12969 | dev_priv->shared_dplls[i].id = i; |
12970 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12971 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12972 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12973 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12974 | dev_priv->shared_dplls[i].get_hw_state = |
12975 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12976 | } |
12977 | } | |
12978 | ||
7c74ade1 DV |
12979 | static void intel_shared_dpll_init(struct drm_device *dev) |
12980 | { | |
e7b903d2 | 12981 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12982 | |
9cd86933 DV |
12983 | if (HAS_DDI(dev)) |
12984 | intel_ddi_pll_init(dev); | |
12985 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12986 | ibx_pch_dpll_init(dev); |
12987 | else | |
12988 | dev_priv->num_shared_dpll = 0; | |
12989 | ||
12990 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12991 | } |
12992 | ||
1fc0a8f7 TU |
12993 | /** |
12994 | * intel_wm_need_update - Check whether watermarks need updating | |
12995 | * @plane: drm plane | |
12996 | * @state: new plane state | |
12997 | * | |
12998 | * Check current plane state versus the new one to determine whether | |
12999 | * watermarks need to be recalculated. | |
13000 | * | |
13001 | * Returns true or false. | |
13002 | */ | |
13003 | bool intel_wm_need_update(struct drm_plane *plane, | |
13004 | struct drm_plane_state *state) | |
13005 | { | |
13006 | /* Update watermarks on tiling changes. */ | |
13007 | if (!plane->state->fb || !state->fb || | |
13008 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
13009 | plane->state->rotation != state->rotation) | |
13010 | return true; | |
13011 | ||
13012 | return false; | |
13013 | } | |
13014 | ||
6beb8c23 MR |
13015 | /** |
13016 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13017 | * @plane: drm plane to prepare for | |
13018 | * @fb: framebuffer to prepare for presentation | |
13019 | * | |
13020 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13021 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13022 | * bits. Some older platforms need special physical address handling for | |
13023 | * cursor planes. | |
13024 | * | |
13025 | * Returns 0 on success, negative error code on failure. | |
13026 | */ | |
13027 | int | |
13028 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13029 | struct drm_framebuffer *fb, |
13030 | const struct drm_plane_state *new_state) | |
465c120c MR |
13031 | { |
13032 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
13033 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13034 | enum pipe pipe = intel_plane->pipe; | |
13035 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13036 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
13037 | unsigned frontbuffer_bits = 0; | |
13038 | int ret = 0; | |
465c120c | 13039 | |
ea2c67bb | 13040 | if (!obj) |
465c120c MR |
13041 | return 0; |
13042 | ||
6beb8c23 MR |
13043 | switch (plane->type) { |
13044 | case DRM_PLANE_TYPE_PRIMARY: | |
13045 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
13046 | break; | |
13047 | case DRM_PLANE_TYPE_CURSOR: | |
13048 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
13049 | break; | |
13050 | case DRM_PLANE_TYPE_OVERLAY: | |
13051 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
13052 | break; | |
13053 | } | |
465c120c | 13054 | |
6beb8c23 | 13055 | mutex_lock(&dev->struct_mutex); |
465c120c | 13056 | |
6beb8c23 MR |
13057 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13058 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13059 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13060 | ret = i915_gem_object_attach_phys(obj, align); | |
13061 | if (ret) | |
13062 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13063 | } else { | |
82bc3b2d | 13064 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 13065 | } |
465c120c | 13066 | |
6beb8c23 MR |
13067 | if (ret == 0) |
13068 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 13069 | |
4c34574f | 13070 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13071 | |
6beb8c23 MR |
13072 | return ret; |
13073 | } | |
13074 | ||
38f3ce3a MR |
13075 | /** |
13076 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13077 | * @plane: drm plane to clean up for | |
13078 | * @fb: old framebuffer that was on plane | |
13079 | * | |
13080 | * Cleans up a framebuffer that has just been removed from a plane. | |
13081 | */ | |
13082 | void | |
13083 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13084 | struct drm_framebuffer *fb, |
13085 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13086 | { |
13087 | struct drm_device *dev = plane->dev; | |
13088 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13089 | ||
13090 | if (WARN_ON(!obj)) | |
13091 | return; | |
13092 | ||
13093 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13094 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13095 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13096 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13097 | mutex_unlock(&dev->struct_mutex); |
13098 | } | |
465c120c MR |
13099 | } |
13100 | ||
13101 | static int | |
3c692a41 GP |
13102 | intel_check_primary_plane(struct drm_plane *plane, |
13103 | struct intel_plane_state *state) | |
13104 | { | |
32b7eeec MR |
13105 | struct drm_device *dev = plane->dev; |
13106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13107 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13108 | struct intel_crtc *intel_crtc; |
2b875c22 | 13109 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13110 | struct drm_rect *dest = &state->dst; |
13111 | struct drm_rect *src = &state->src; | |
13112 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13113 | bool can_position = false; |
465c120c MR |
13114 | int ret; |
13115 | ||
ea2c67bb MR |
13116 | crtc = crtc ? crtc : plane->crtc; |
13117 | intel_crtc = to_intel_crtc(crtc); | |
13118 | ||
d8106366 SJ |
13119 | if (INTEL_INFO(dev)->gen >= 9) |
13120 | can_position = true; | |
13121 | ||
c59cb179 MR |
13122 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13123 | src, dest, clip, | |
13124 | DRM_PLANE_HELPER_NO_SCALING, | |
13125 | DRM_PLANE_HELPER_NO_SCALING, | |
d8106366 SJ |
13126 | can_position, true, |
13127 | &state->visible); | |
c59cb179 MR |
13128 | if (ret) |
13129 | return ret; | |
465c120c | 13130 | |
32b7eeec MR |
13131 | if (intel_crtc->active) { |
13132 | intel_crtc->atomic.wait_for_flips = true; | |
13133 | ||
13134 | /* | |
13135 | * FBC does not work on some platforms for rotated | |
13136 | * planes, so disable it when rotation is not 0 and | |
13137 | * update it when rotation is set back to 0. | |
13138 | * | |
13139 | * FIXME: This is redundant with the fbc update done in | |
13140 | * the primary plane enable function except that that | |
13141 | * one is done too late. We eventually need to unify | |
13142 | * this. | |
13143 | */ | |
13144 | if (intel_crtc->primary_enabled && | |
13145 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 13146 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13147 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13148 | intel_crtc->atomic.disable_fbc = true; |
13149 | } | |
13150 | ||
13151 | if (state->visible) { | |
13152 | /* | |
13153 | * BDW signals flip done immediately if the plane | |
13154 | * is disabled, even if the plane enable is already | |
13155 | * armed to occur at the next vblank :( | |
13156 | */ | |
13157 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
13158 | intel_crtc->atomic.wait_vblank = true; | |
13159 | } | |
13160 | ||
13161 | intel_crtc->atomic.fb_bits |= | |
13162 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13163 | ||
13164 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13165 | |
1fc0a8f7 | 13166 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13167 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13168 | } |
13169 | ||
14af293f GP |
13170 | return 0; |
13171 | } | |
13172 | ||
13173 | static void | |
13174 | intel_commit_primary_plane(struct drm_plane *plane, | |
13175 | struct intel_plane_state *state) | |
13176 | { | |
2b875c22 MR |
13177 | struct drm_crtc *crtc = state->base.crtc; |
13178 | struct drm_framebuffer *fb = state->base.fb; | |
13179 | struct drm_device *dev = plane->dev; | |
14af293f | 13180 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13181 | struct intel_crtc *intel_crtc; |
14af293f GP |
13182 | struct drm_rect *src = &state->src; |
13183 | ||
ea2c67bb MR |
13184 | crtc = crtc ? crtc : plane->crtc; |
13185 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13186 | |
13187 | plane->fb = fb; | |
9dc806fc MR |
13188 | crtc->x = src->x1 >> 16; |
13189 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13190 | |
ccc759dc | 13191 | if (intel_crtc->active) { |
ccc759dc | 13192 | if (state->visible) { |
ccc759dc GP |
13193 | /* FIXME: kill this fastboot hack */ |
13194 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13195 | |
ccc759dc | 13196 | intel_crtc->primary_enabled = true; |
465c120c | 13197 | |
ccc759dc GP |
13198 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13199 | crtc->x, crtc->y); | |
ccc759dc GP |
13200 | } else { |
13201 | /* | |
13202 | * If clipping results in a non-visible primary plane, | |
13203 | * we'll disable the primary plane. Note that this is | |
13204 | * a bit different than what happens if userspace | |
13205 | * explicitly disables the plane by passing fb=0 | |
13206 | * because plane->fb still gets set and pinned. | |
13207 | */ | |
13208 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 13209 | } |
ccc759dc | 13210 | } |
465c120c MR |
13211 | } |
13212 | ||
32b7eeec | 13213 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13214 | { |
32b7eeec | 13215 | struct drm_device *dev = crtc->dev; |
140fd38d | 13216 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13217 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13218 | struct intel_plane *intel_plane; |
13219 | struct drm_plane *p; | |
13220 | unsigned fb_bits = 0; | |
13221 | ||
13222 | /* Track fb's for any planes being disabled */ | |
13223 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13224 | intel_plane = to_intel_plane(p); | |
13225 | ||
13226 | if (intel_crtc->atomic.disabled_planes & | |
13227 | (1 << drm_plane_index(p))) { | |
13228 | switch (p->type) { | |
13229 | case DRM_PLANE_TYPE_PRIMARY: | |
13230 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13231 | break; | |
13232 | case DRM_PLANE_TYPE_CURSOR: | |
13233 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13234 | break; | |
13235 | case DRM_PLANE_TYPE_OVERLAY: | |
13236 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13237 | break; | |
13238 | } | |
3c692a41 | 13239 | |
ea2c67bb MR |
13240 | mutex_lock(&dev->struct_mutex); |
13241 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13242 | mutex_unlock(&dev->struct_mutex); | |
13243 | } | |
13244 | } | |
3c692a41 | 13245 | |
32b7eeec MR |
13246 | if (intel_crtc->atomic.wait_for_flips) |
13247 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13248 | |
32b7eeec MR |
13249 | if (intel_crtc->atomic.disable_fbc) |
13250 | intel_fbc_disable(dev); | |
3c692a41 | 13251 | |
32b7eeec MR |
13252 | if (intel_crtc->atomic.pre_disable_primary) |
13253 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13254 | |
32b7eeec MR |
13255 | if (intel_crtc->atomic.update_wm) |
13256 | intel_update_watermarks(crtc); | |
3c692a41 | 13257 | |
32b7eeec | 13258 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13259 | |
c34c9ee4 MR |
13260 | /* Perform vblank evasion around commit operation */ |
13261 | if (intel_crtc->active) | |
13262 | intel_crtc->atomic.evade = | |
13263 | intel_pipe_update_start(intel_crtc, | |
13264 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13265 | } |
13266 | ||
13267 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13268 | { | |
13269 | struct drm_device *dev = crtc->dev; | |
13270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13272 | struct drm_plane *p; | |
13273 | ||
c34c9ee4 MR |
13274 | if (intel_crtc->atomic.evade) |
13275 | intel_pipe_update_end(intel_crtc, | |
13276 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13277 | |
140fd38d | 13278 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13279 | |
32b7eeec MR |
13280 | if (intel_crtc->atomic.wait_vblank) |
13281 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13282 | ||
13283 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13284 | ||
13285 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13286 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13287 | intel_fbc_update(dev); |
ccc759dc | 13288 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13289 | } |
3c692a41 | 13290 | |
32b7eeec MR |
13291 | if (intel_crtc->atomic.post_enable_primary) |
13292 | intel_post_enable_primary(crtc); | |
3c692a41 | 13293 | |
32b7eeec MR |
13294 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13295 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13296 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13297 | false, false); | |
13298 | ||
13299 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13300 | } |
13301 | ||
cf4c7c12 | 13302 | /** |
4a3b8769 MR |
13303 | * intel_plane_destroy - destroy a plane |
13304 | * @plane: plane to destroy | |
cf4c7c12 | 13305 | * |
4a3b8769 MR |
13306 | * Common destruction function for all types of planes (primary, cursor, |
13307 | * sprite). | |
cf4c7c12 | 13308 | */ |
4a3b8769 | 13309 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13310 | { |
13311 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13312 | drm_plane_cleanup(plane); | |
13313 | kfree(intel_plane); | |
13314 | } | |
13315 | ||
65a3fea0 | 13316 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13317 | .update_plane = drm_atomic_helper_update_plane, |
13318 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13319 | .destroy = intel_plane_destroy, |
c196e1d6 | 13320 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13321 | .atomic_get_property = intel_plane_atomic_get_property, |
13322 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13323 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13324 | .atomic_destroy_state = intel_plane_destroy_state, | |
13325 | ||
465c120c MR |
13326 | }; |
13327 | ||
13328 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13329 | int pipe) | |
13330 | { | |
13331 | struct intel_plane *primary; | |
8e7d688b | 13332 | struct intel_plane_state *state; |
465c120c MR |
13333 | const uint32_t *intel_primary_formats; |
13334 | int num_formats; | |
13335 | ||
13336 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13337 | if (primary == NULL) | |
13338 | return NULL; | |
13339 | ||
8e7d688b MR |
13340 | state = intel_create_plane_state(&primary->base); |
13341 | if (!state) { | |
ea2c67bb MR |
13342 | kfree(primary); |
13343 | return NULL; | |
13344 | } | |
8e7d688b | 13345 | primary->base.state = &state->base; |
ea2c67bb | 13346 | |
465c120c MR |
13347 | primary->can_scale = false; |
13348 | primary->max_downscale = 1; | |
549e2bfb | 13349 | state->scaler_id = -1; |
465c120c MR |
13350 | primary->pipe = pipe; |
13351 | primary->plane = pipe; | |
c59cb179 MR |
13352 | primary->check_plane = intel_check_primary_plane; |
13353 | primary->commit_plane = intel_commit_primary_plane; | |
08e221fb | 13354 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13355 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13356 | primary->plane = !pipe; | |
13357 | ||
13358 | if (INTEL_INFO(dev)->gen <= 3) { | |
13359 | intel_primary_formats = intel_primary_formats_gen2; | |
13360 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
13361 | } else { | |
13362 | intel_primary_formats = intel_primary_formats_gen4; | |
13363 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
13364 | } | |
13365 | ||
13366 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13367 | &intel_plane_funcs, |
465c120c MR |
13368 | intel_primary_formats, num_formats, |
13369 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13370 | |
3b7a5119 SJ |
13371 | if (INTEL_INFO(dev)->gen >= 4) |
13372 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13373 | |
ea2c67bb MR |
13374 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13375 | ||
465c120c MR |
13376 | return &primary->base; |
13377 | } | |
13378 | ||
3b7a5119 SJ |
13379 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13380 | { | |
13381 | if (!dev->mode_config.rotation_property) { | |
13382 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13383 | BIT(DRM_ROTATE_180); | |
13384 | ||
13385 | if (INTEL_INFO(dev)->gen >= 9) | |
13386 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13387 | ||
13388 | dev->mode_config.rotation_property = | |
13389 | drm_mode_create_rotation_property(dev, flags); | |
13390 | } | |
13391 | if (dev->mode_config.rotation_property) | |
13392 | drm_object_attach_property(&plane->base.base, | |
13393 | dev->mode_config.rotation_property, | |
13394 | plane->base.state->rotation); | |
13395 | } | |
13396 | ||
3d7d6510 | 13397 | static int |
852e787c GP |
13398 | intel_check_cursor_plane(struct drm_plane *plane, |
13399 | struct intel_plane_state *state) | |
3d7d6510 | 13400 | { |
2b875c22 | 13401 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13402 | struct drm_device *dev = plane->dev; |
2b875c22 | 13403 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13404 | struct drm_rect *dest = &state->dst; |
13405 | struct drm_rect *src = &state->src; | |
13406 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13407 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13408 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13409 | unsigned stride; |
13410 | int ret; | |
3d7d6510 | 13411 | |
ea2c67bb MR |
13412 | crtc = crtc ? crtc : plane->crtc; |
13413 | intel_crtc = to_intel_crtc(crtc); | |
13414 | ||
757f9a3e | 13415 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13416 | src, dest, clip, |
3d7d6510 MR |
13417 | DRM_PLANE_HELPER_NO_SCALING, |
13418 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13419 | true, true, &state->visible); |
757f9a3e GP |
13420 | if (ret) |
13421 | return ret; | |
13422 | ||
13423 | ||
13424 | /* if we want to turn off the cursor ignore width and height */ | |
13425 | if (!obj) | |
32b7eeec | 13426 | goto finish; |
757f9a3e | 13427 | |
757f9a3e | 13428 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13429 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13430 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13431 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13432 | return -EINVAL; |
13433 | } | |
13434 | ||
ea2c67bb MR |
13435 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13436 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13437 | DRM_DEBUG_KMS("buffer is too small\n"); |
13438 | return -ENOMEM; | |
13439 | } | |
13440 | ||
3a656b54 | 13441 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13442 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13443 | ret = -EINVAL; | |
13444 | } | |
757f9a3e | 13445 | |
32b7eeec MR |
13446 | finish: |
13447 | if (intel_crtc->active) { | |
3749f463 | 13448 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13449 | intel_crtc->atomic.update_wm = true; |
13450 | ||
13451 | intel_crtc->atomic.fb_bits |= | |
13452 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13453 | } | |
13454 | ||
757f9a3e | 13455 | return ret; |
852e787c | 13456 | } |
3d7d6510 | 13457 | |
f4a2cf29 | 13458 | static void |
852e787c GP |
13459 | intel_commit_cursor_plane(struct drm_plane *plane, |
13460 | struct intel_plane_state *state) | |
13461 | { | |
2b875c22 | 13462 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13463 | struct drm_device *dev = plane->dev; |
13464 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13465 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13466 | uint32_t addr; |
852e787c | 13467 | |
ea2c67bb MR |
13468 | crtc = crtc ? crtc : plane->crtc; |
13469 | intel_crtc = to_intel_crtc(crtc); | |
13470 | ||
2b875c22 | 13471 | plane->fb = state->base.fb; |
ea2c67bb MR |
13472 | crtc->cursor_x = state->base.crtc_x; |
13473 | crtc->cursor_y = state->base.crtc_y; | |
13474 | ||
a912f12f GP |
13475 | if (intel_crtc->cursor_bo == obj) |
13476 | goto update; | |
4ed91096 | 13477 | |
f4a2cf29 | 13478 | if (!obj) |
a912f12f | 13479 | addr = 0; |
f4a2cf29 | 13480 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13481 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13482 | else |
a912f12f | 13483 | addr = obj->phys_handle->busaddr; |
852e787c | 13484 | |
a912f12f GP |
13485 | intel_crtc->cursor_addr = addr; |
13486 | intel_crtc->cursor_bo = obj; | |
13487 | update: | |
852e787c | 13488 | |
32b7eeec | 13489 | if (intel_crtc->active) |
a912f12f | 13490 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13491 | } |
13492 | ||
3d7d6510 MR |
13493 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13494 | int pipe) | |
13495 | { | |
13496 | struct intel_plane *cursor; | |
8e7d688b | 13497 | struct intel_plane_state *state; |
3d7d6510 MR |
13498 | |
13499 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13500 | if (cursor == NULL) | |
13501 | return NULL; | |
13502 | ||
8e7d688b MR |
13503 | state = intel_create_plane_state(&cursor->base); |
13504 | if (!state) { | |
ea2c67bb MR |
13505 | kfree(cursor); |
13506 | return NULL; | |
13507 | } | |
8e7d688b | 13508 | cursor->base.state = &state->base; |
ea2c67bb | 13509 | |
3d7d6510 MR |
13510 | cursor->can_scale = false; |
13511 | cursor->max_downscale = 1; | |
13512 | cursor->pipe = pipe; | |
13513 | cursor->plane = pipe; | |
549e2bfb | 13514 | state->scaler_id = -1; |
c59cb179 MR |
13515 | cursor->check_plane = intel_check_cursor_plane; |
13516 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
13517 | |
13518 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13519 | &intel_plane_funcs, |
3d7d6510 MR |
13520 | intel_cursor_formats, |
13521 | ARRAY_SIZE(intel_cursor_formats), | |
13522 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13523 | |
13524 | if (INTEL_INFO(dev)->gen >= 4) { | |
13525 | if (!dev->mode_config.rotation_property) | |
13526 | dev->mode_config.rotation_property = | |
13527 | drm_mode_create_rotation_property(dev, | |
13528 | BIT(DRM_ROTATE_0) | | |
13529 | BIT(DRM_ROTATE_180)); | |
13530 | if (dev->mode_config.rotation_property) | |
13531 | drm_object_attach_property(&cursor->base.base, | |
13532 | dev->mode_config.rotation_property, | |
8e7d688b | 13533 | state->base.rotation); |
4398ad45 VS |
13534 | } |
13535 | ||
ea2c67bb MR |
13536 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13537 | ||
3d7d6510 MR |
13538 | return &cursor->base; |
13539 | } | |
13540 | ||
549e2bfb CK |
13541 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13542 | struct intel_crtc_state *crtc_state) | |
13543 | { | |
13544 | int i; | |
13545 | struct intel_scaler *intel_scaler; | |
13546 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13547 | ||
13548 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13549 | intel_scaler = &scaler_state->scalers[i]; | |
13550 | intel_scaler->in_use = 0; | |
13551 | intel_scaler->id = i; | |
13552 | ||
13553 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13554 | } | |
13555 | ||
13556 | scaler_state->scaler_id = -1; | |
13557 | } | |
13558 | ||
b358d0a6 | 13559 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13560 | { |
fbee40df | 13561 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13562 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13563 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13564 | struct drm_plane *primary = NULL; |
13565 | struct drm_plane *cursor = NULL; | |
465c120c | 13566 | int i, ret; |
79e53945 | 13567 | |
955382f3 | 13568 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13569 | if (intel_crtc == NULL) |
13570 | return; | |
13571 | ||
f5de6e07 ACO |
13572 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13573 | if (!crtc_state) | |
13574 | goto fail; | |
13575 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 13576 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13577 | |
549e2bfb CK |
13578 | /* initialize shared scalers */ |
13579 | if (INTEL_INFO(dev)->gen >= 9) { | |
13580 | if (pipe == PIPE_C) | |
13581 | intel_crtc->num_scalers = 1; | |
13582 | else | |
13583 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13584 | ||
13585 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13586 | } | |
13587 | ||
465c120c | 13588 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13589 | if (!primary) |
13590 | goto fail; | |
13591 | ||
13592 | cursor = intel_cursor_plane_create(dev, pipe); | |
13593 | if (!cursor) | |
13594 | goto fail; | |
13595 | ||
465c120c | 13596 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13597 | cursor, &intel_crtc_funcs); |
13598 | if (ret) | |
13599 | goto fail; | |
79e53945 JB |
13600 | |
13601 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13602 | for (i = 0; i < 256; i++) { |
13603 | intel_crtc->lut_r[i] = i; | |
13604 | intel_crtc->lut_g[i] = i; | |
13605 | intel_crtc->lut_b[i] = i; | |
13606 | } | |
13607 | ||
1f1c2e24 VS |
13608 | /* |
13609 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13610 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13611 | */ |
80824003 JB |
13612 | intel_crtc->pipe = pipe; |
13613 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13614 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13615 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13616 | intel_crtc->plane = !pipe; |
80824003 JB |
13617 | } |
13618 | ||
4b0e333e CW |
13619 | intel_crtc->cursor_base = ~0; |
13620 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13621 | intel_crtc->cursor_size = ~0; |
8d7849db | 13622 | |
22fd0fab JB |
13623 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13624 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13625 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13626 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13627 | ||
9362c7c5 ACO |
13628 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
13629 | ||
79e53945 | 13630 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13631 | |
13632 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13633 | return; |
13634 | ||
13635 | fail: | |
13636 | if (primary) | |
13637 | drm_plane_cleanup(primary); | |
13638 | if (cursor) | |
13639 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13640 | kfree(crtc_state); |
3d7d6510 | 13641 | kfree(intel_crtc); |
79e53945 JB |
13642 | } |
13643 | ||
752aa88a JB |
13644 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13645 | { | |
13646 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13647 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13648 | |
51fd371b | 13649 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13650 | |
d3babd3f | 13651 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13652 | return INVALID_PIPE; |
13653 | ||
13654 | return to_intel_crtc(encoder->crtc)->pipe; | |
13655 | } | |
13656 | ||
08d7b3d1 | 13657 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13658 | struct drm_file *file) |
08d7b3d1 | 13659 | { |
08d7b3d1 | 13660 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13661 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13662 | struct intel_crtc *crtc; |
08d7b3d1 | 13663 | |
7707e653 | 13664 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13665 | |
7707e653 | 13666 | if (!drmmode_crtc) { |
08d7b3d1 | 13667 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13668 | return -ENOENT; |
08d7b3d1 CW |
13669 | } |
13670 | ||
7707e653 | 13671 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13672 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13673 | |
c05422d5 | 13674 | return 0; |
08d7b3d1 CW |
13675 | } |
13676 | ||
66a9278e | 13677 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13678 | { |
66a9278e DV |
13679 | struct drm_device *dev = encoder->base.dev; |
13680 | struct intel_encoder *source_encoder; | |
79e53945 | 13681 | int index_mask = 0; |
79e53945 JB |
13682 | int entry = 0; |
13683 | ||
b2784e15 | 13684 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13685 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13686 | index_mask |= (1 << entry); |
13687 | ||
79e53945 JB |
13688 | entry++; |
13689 | } | |
4ef69c7a | 13690 | |
79e53945 JB |
13691 | return index_mask; |
13692 | } | |
13693 | ||
4d302442 CW |
13694 | static bool has_edp_a(struct drm_device *dev) |
13695 | { | |
13696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13697 | ||
13698 | if (!IS_MOBILE(dev)) | |
13699 | return false; | |
13700 | ||
13701 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13702 | return false; | |
13703 | ||
e3589908 | 13704 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13705 | return false; |
13706 | ||
13707 | return true; | |
13708 | } | |
13709 | ||
84b4e042 JB |
13710 | static bool intel_crt_present(struct drm_device *dev) |
13711 | { | |
13712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13713 | ||
884497ed DL |
13714 | if (INTEL_INFO(dev)->gen >= 9) |
13715 | return false; | |
13716 | ||
cf404ce4 | 13717 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13718 | return false; |
13719 | ||
13720 | if (IS_CHERRYVIEW(dev)) | |
13721 | return false; | |
13722 | ||
13723 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13724 | return false; | |
13725 | ||
13726 | return true; | |
13727 | } | |
13728 | ||
79e53945 JB |
13729 | static void intel_setup_outputs(struct drm_device *dev) |
13730 | { | |
725e30ad | 13731 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13732 | struct intel_encoder *encoder; |
cb0953d7 | 13733 | bool dpd_is_edp = false; |
79e53945 | 13734 | |
c9093354 | 13735 | intel_lvds_init(dev); |
79e53945 | 13736 | |
84b4e042 | 13737 | if (intel_crt_present(dev)) |
79935fca | 13738 | intel_crt_init(dev); |
cb0953d7 | 13739 | |
c776eb2e VK |
13740 | if (IS_BROXTON(dev)) { |
13741 | /* | |
13742 | * FIXME: Broxton doesn't support port detection via the | |
13743 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13744 | * detect the ports. | |
13745 | */ | |
13746 | intel_ddi_init(dev, PORT_A); | |
13747 | intel_ddi_init(dev, PORT_B); | |
13748 | intel_ddi_init(dev, PORT_C); | |
13749 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13750 | int found; |
13751 | ||
de31facd JB |
13752 | /* |
13753 | * Haswell uses DDI functions to detect digital outputs. | |
13754 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13755 | * it's there. | |
13756 | */ | |
0e72a5b5 | 13757 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13758 | /* WaIgnoreDDIAStrap: skl */ |
13759 | if (found || | |
13760 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13761 | intel_ddi_init(dev, PORT_A); |
13762 | ||
13763 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13764 | * register */ | |
13765 | found = I915_READ(SFUSE_STRAP); | |
13766 | ||
13767 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13768 | intel_ddi_init(dev, PORT_B); | |
13769 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13770 | intel_ddi_init(dev, PORT_C); | |
13771 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13772 | intel_ddi_init(dev, PORT_D); | |
13773 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13774 | int found; |
5d8a7752 | 13775 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13776 | |
13777 | if (has_edp_a(dev)) | |
13778 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13779 | |
dc0fa718 | 13780 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13781 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13782 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13783 | if (!found) |
e2debe91 | 13784 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13785 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13786 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13787 | } |
13788 | ||
dc0fa718 | 13789 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13790 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13791 | |
dc0fa718 | 13792 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13793 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13794 | |
5eb08b69 | 13795 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13796 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13797 | |
270b3042 | 13798 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13799 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13800 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13801 | /* |
13802 | * The DP_DETECTED bit is the latched state of the DDC | |
13803 | * SDA pin at boot. However since eDP doesn't require DDC | |
13804 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13805 | * eDP ports may have been muxed to an alternate function. | |
13806 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13807 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13808 | * detect eDP ports. | |
13809 | */ | |
d2182a66 VS |
13810 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13811 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13812 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13813 | PORT_B); | |
e17ac6db VS |
13814 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13815 | intel_dp_is_edp(dev, PORT_B)) | |
13816 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13817 | |
d2182a66 VS |
13818 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13819 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13820 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13821 | PORT_C); | |
e17ac6db VS |
13822 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13823 | intel_dp_is_edp(dev, PORT_C)) | |
13824 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13825 | |
9418c1f1 | 13826 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13827 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13828 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13829 | PORT_D); | |
e17ac6db VS |
13830 | /* eDP not supported on port D, so don't check VBT */ |
13831 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13832 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13833 | } |
13834 | ||
3cfca973 | 13835 | intel_dsi_init(dev); |
103a196f | 13836 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13837 | bool found = false; |
7d57382e | 13838 | |
e2debe91 | 13839 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13840 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13841 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13842 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13843 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13844 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13845 | } |
27185ae1 | 13846 | |
e7281eab | 13847 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13848 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13849 | } |
13520b05 KH |
13850 | |
13851 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13852 | |
e2debe91 | 13853 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13854 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13855 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13856 | } |
27185ae1 | 13857 | |
e2debe91 | 13858 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13859 | |
b01f2c3a JB |
13860 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13861 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13862 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13863 | } |
e7281eab | 13864 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13865 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13866 | } |
27185ae1 | 13867 | |
b01f2c3a | 13868 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13869 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13870 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13871 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13872 | intel_dvo_init(dev); |
13873 | ||
103a196f | 13874 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13875 | intel_tv_init(dev); |
13876 | ||
0bc12bcb | 13877 | intel_psr_init(dev); |
7c8f8a70 | 13878 | |
b2784e15 | 13879 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13880 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13881 | encoder->base.possible_clones = | |
66a9278e | 13882 | intel_encoder_clones(encoder); |
79e53945 | 13883 | } |
47356eb6 | 13884 | |
dde86e2d | 13885 | intel_init_pch_refclk(dev); |
270b3042 DV |
13886 | |
13887 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13888 | } |
13889 | ||
13890 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13891 | { | |
60a5ca01 | 13892 | struct drm_device *dev = fb->dev; |
79e53945 | 13893 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13894 | |
ef2d633e | 13895 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13896 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13897 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13898 | drm_gem_object_unreference(&intel_fb->obj->base); |
13899 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13900 | kfree(intel_fb); |
13901 | } | |
13902 | ||
13903 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13904 | struct drm_file *file, |
79e53945 JB |
13905 | unsigned int *handle) |
13906 | { | |
13907 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13908 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13909 | |
05394f39 | 13910 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13911 | } |
13912 | ||
13913 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13914 | .destroy = intel_user_framebuffer_destroy, | |
13915 | .create_handle = intel_user_framebuffer_create_handle, | |
13916 | }; | |
13917 | ||
b321803d DL |
13918 | static |
13919 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13920 | uint32_t pixel_format) | |
13921 | { | |
13922 | u32 gen = INTEL_INFO(dev)->gen; | |
13923 | ||
13924 | if (gen >= 9) { | |
13925 | /* "The stride in bytes must not exceed the of the size of 8K | |
13926 | * pixels and 32K bytes." | |
13927 | */ | |
13928 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13929 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13930 | return 32*1024; | |
13931 | } else if (gen >= 4) { | |
13932 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13933 | return 16*1024; | |
13934 | else | |
13935 | return 32*1024; | |
13936 | } else if (gen >= 3) { | |
13937 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13938 | return 8*1024; | |
13939 | else | |
13940 | return 16*1024; | |
13941 | } else { | |
13942 | /* XXX DSPC is limited to 4k tiled */ | |
13943 | return 8*1024; | |
13944 | } | |
13945 | } | |
13946 | ||
b5ea642a DV |
13947 | static int intel_framebuffer_init(struct drm_device *dev, |
13948 | struct intel_framebuffer *intel_fb, | |
13949 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13950 | struct drm_i915_gem_object *obj) | |
79e53945 | 13951 | { |
6761dd31 | 13952 | unsigned int aligned_height; |
79e53945 | 13953 | int ret; |
b321803d | 13954 | u32 pitch_limit, stride_alignment; |
79e53945 | 13955 | |
dd4916c5 DV |
13956 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13957 | ||
2a80eada DV |
13958 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13959 | /* Enforce that fb modifier and tiling mode match, but only for | |
13960 | * X-tiled. This is needed for FBC. */ | |
13961 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13962 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13963 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13964 | return -EINVAL; | |
13965 | } | |
13966 | } else { | |
13967 | if (obj->tiling_mode == I915_TILING_X) | |
13968 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13969 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13970 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13971 | return -EINVAL; | |
13972 | } | |
13973 | } | |
13974 | ||
9a8f0a12 TU |
13975 | /* Passed in modifier sanity checking. */ |
13976 | switch (mode_cmd->modifier[0]) { | |
13977 | case I915_FORMAT_MOD_Y_TILED: | |
13978 | case I915_FORMAT_MOD_Yf_TILED: | |
13979 | if (INTEL_INFO(dev)->gen < 9) { | |
13980 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13981 | mode_cmd->modifier[0]); | |
13982 | return -EINVAL; | |
13983 | } | |
13984 | case DRM_FORMAT_MOD_NONE: | |
13985 | case I915_FORMAT_MOD_X_TILED: | |
13986 | break; | |
13987 | default: | |
c0f40428 JB |
13988 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13989 | mode_cmd->modifier[0]); | |
57cd6508 | 13990 | return -EINVAL; |
c16ed4be | 13991 | } |
57cd6508 | 13992 | |
b321803d DL |
13993 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13994 | mode_cmd->pixel_format); | |
13995 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13996 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13997 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13998 | return -EINVAL; |
c16ed4be | 13999 | } |
57cd6508 | 14000 | |
b321803d DL |
14001 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14002 | mode_cmd->pixel_format); | |
a35cdaa0 | 14003 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14004 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14005 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14006 | "tiled" : "linear", |
a35cdaa0 | 14007 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14008 | return -EINVAL; |
c16ed4be | 14009 | } |
5d7bd705 | 14010 | |
2a80eada | 14011 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14012 | mode_cmd->pitches[0] != obj->stride) { |
14013 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14014 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14015 | return -EINVAL; |
c16ed4be | 14016 | } |
5d7bd705 | 14017 | |
57779d06 | 14018 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14019 | switch (mode_cmd->pixel_format) { |
57779d06 | 14020 | case DRM_FORMAT_C8: |
04b3924d VS |
14021 | case DRM_FORMAT_RGB565: |
14022 | case DRM_FORMAT_XRGB8888: | |
14023 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14024 | break; |
14025 | case DRM_FORMAT_XRGB1555: | |
14026 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 14027 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14028 | DRM_DEBUG("unsupported pixel format: %s\n", |
14029 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14030 | return -EINVAL; |
c16ed4be | 14031 | } |
57779d06 VS |
14032 | break; |
14033 | case DRM_FORMAT_XBGR8888: | |
14034 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
14035 | case DRM_FORMAT_XRGB2101010: |
14036 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
14037 | case DRM_FORMAT_XBGR2101010: |
14038 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 14039 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14040 | DRM_DEBUG("unsupported pixel format: %s\n", |
14041 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14042 | return -EINVAL; |
c16ed4be | 14043 | } |
b5626747 | 14044 | break; |
04b3924d VS |
14045 | case DRM_FORMAT_YUYV: |
14046 | case DRM_FORMAT_UYVY: | |
14047 | case DRM_FORMAT_YVYU: | |
14048 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14049 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14050 | DRM_DEBUG("unsupported pixel format: %s\n", |
14051 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14052 | return -EINVAL; |
c16ed4be | 14053 | } |
57cd6508 CW |
14054 | break; |
14055 | default: | |
4ee62c76 VS |
14056 | DRM_DEBUG("unsupported pixel format: %s\n", |
14057 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14058 | return -EINVAL; |
14059 | } | |
14060 | ||
90f9a336 VS |
14061 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14062 | if (mode_cmd->offsets[0] != 0) | |
14063 | return -EINVAL; | |
14064 | ||
ec2c981e | 14065 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14066 | mode_cmd->pixel_format, |
14067 | mode_cmd->modifier[0]); | |
53155c0a DV |
14068 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14069 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14070 | return -EINVAL; | |
14071 | ||
c7d73f6a DV |
14072 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14073 | intel_fb->obj = obj; | |
80075d49 | 14074 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14075 | |
79e53945 JB |
14076 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14077 | if (ret) { | |
14078 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14079 | return ret; | |
14080 | } | |
14081 | ||
79e53945 JB |
14082 | return 0; |
14083 | } | |
14084 | ||
79e53945 JB |
14085 | static struct drm_framebuffer * |
14086 | intel_user_framebuffer_create(struct drm_device *dev, | |
14087 | struct drm_file *filp, | |
308e5bcb | 14088 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14089 | { |
05394f39 | 14090 | struct drm_i915_gem_object *obj; |
79e53945 | 14091 | |
308e5bcb JB |
14092 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14093 | mode_cmd->handles[0])); | |
c8725226 | 14094 | if (&obj->base == NULL) |
cce13ff7 | 14095 | return ERR_PTR(-ENOENT); |
79e53945 | 14096 | |
d2dff872 | 14097 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14098 | } |
14099 | ||
4520f53a | 14100 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14101 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14102 | { |
14103 | } | |
14104 | #endif | |
14105 | ||
79e53945 | 14106 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14107 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14108 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14109 | .atomic_check = intel_atomic_check, |
14110 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14111 | }; |
14112 | ||
e70236a8 JB |
14113 | /* Set up chip specific display functions */ |
14114 | static void intel_init_display(struct drm_device *dev) | |
14115 | { | |
14116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14117 | ||
ee9300bb DV |
14118 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14119 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14120 | else if (IS_CHERRYVIEW(dev)) |
14121 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14122 | else if (IS_VALLEYVIEW(dev)) |
14123 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14124 | else if (IS_PINEVIEW(dev)) | |
14125 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14126 | else | |
14127 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14128 | ||
bc8d7dff DL |
14129 | if (INTEL_INFO(dev)->gen >= 9) { |
14130 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14131 | dev_priv->display.get_initial_plane_config = |
14132 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14133 | dev_priv->display.crtc_compute_clock = |
14134 | haswell_crtc_compute_clock; | |
14135 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14136 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14137 | dev_priv->display.off = ironlake_crtc_off; | |
14138 | dev_priv->display.update_primary_plane = | |
14139 | skylake_update_primary_plane; | |
14140 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14141 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14142 | dev_priv->display.get_initial_plane_config = |
14143 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14144 | dev_priv->display.crtc_compute_clock = |
14145 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14146 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14147 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14148 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14149 | dev_priv->display.update_primary_plane = |
14150 | ironlake_update_primary_plane; | |
09b4ddf9 | 14151 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14152 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14153 | dev_priv->display.get_initial_plane_config = |
14154 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14155 | dev_priv->display.crtc_compute_clock = |
14156 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14157 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14158 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14159 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14160 | dev_priv->display.update_primary_plane = |
14161 | ironlake_update_primary_plane; | |
89b667f8 JB |
14162 | } else if (IS_VALLEYVIEW(dev)) { |
14163 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14164 | dev_priv->display.get_initial_plane_config = |
14165 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14166 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14167 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14168 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14169 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14170 | dev_priv->display.update_primary_plane = |
14171 | i9xx_update_primary_plane; | |
f564048e | 14172 | } else { |
0e8ffe1b | 14173 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14174 | dev_priv->display.get_initial_plane_config = |
14175 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14176 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14177 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14178 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14179 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14180 | dev_priv->display.update_primary_plane = |
14181 | i9xx_update_primary_plane; | |
f564048e | 14182 | } |
e70236a8 | 14183 | |
e70236a8 | 14184 | /* Returns the core display clock speed */ |
1652d19e VS |
14185 | if (IS_SKYLAKE(dev)) |
14186 | dev_priv->display.get_display_clock_speed = | |
14187 | skylake_get_display_clock_speed; | |
14188 | else if (IS_BROADWELL(dev)) | |
14189 | dev_priv->display.get_display_clock_speed = | |
14190 | broadwell_get_display_clock_speed; | |
14191 | else if (IS_HASWELL(dev)) | |
14192 | dev_priv->display.get_display_clock_speed = | |
14193 | haswell_get_display_clock_speed; | |
14194 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14195 | dev_priv->display.get_display_clock_speed = |
14196 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14197 | else if (IS_GEN5(dev)) |
14198 | dev_priv->display.get_display_clock_speed = | |
14199 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
14200 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
14201 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
14202 | dev_priv->display.get_display_clock_speed = |
14203 | i945_get_display_clock_speed; | |
14204 | else if (IS_I915G(dev)) | |
14205 | dev_priv->display.get_display_clock_speed = | |
14206 | i915_get_display_clock_speed; | |
257a7ffc | 14207 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14208 | dev_priv->display.get_display_clock_speed = |
14209 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14210 | else if (IS_PINEVIEW(dev)) |
14211 | dev_priv->display.get_display_clock_speed = | |
14212 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14213 | else if (IS_I915GM(dev)) |
14214 | dev_priv->display.get_display_clock_speed = | |
14215 | i915gm_get_display_clock_speed; | |
14216 | else if (IS_I865G(dev)) | |
14217 | dev_priv->display.get_display_clock_speed = | |
14218 | i865_get_display_clock_speed; | |
f0f8a9ce | 14219 | else if (IS_I85X(dev)) |
e70236a8 JB |
14220 | dev_priv->display.get_display_clock_speed = |
14221 | i855_get_display_clock_speed; | |
14222 | else /* 852, 830 */ | |
14223 | dev_priv->display.get_display_clock_speed = | |
14224 | i830_get_display_clock_speed; | |
14225 | ||
7c10a2b5 | 14226 | if (IS_GEN5(dev)) { |
3bb11b53 | 14227 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14228 | } else if (IS_GEN6(dev)) { |
14229 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14230 | } else if (IS_IVYBRIDGE(dev)) { |
14231 | /* FIXME: detect B0+ stepping and use auto training */ | |
14232 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14233 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14234 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
14235 | } else if (IS_VALLEYVIEW(dev)) { |
14236 | dev_priv->display.modeset_global_resources = | |
14237 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14238 | } else if (IS_BROXTON(dev)) { |
14239 | dev_priv->display.modeset_global_resources = | |
14240 | broxton_modeset_global_resources; | |
e70236a8 | 14241 | } |
8c9f3aaf | 14242 | |
8c9f3aaf JB |
14243 | switch (INTEL_INFO(dev)->gen) { |
14244 | case 2: | |
14245 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14246 | break; | |
14247 | ||
14248 | case 3: | |
14249 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14250 | break; | |
14251 | ||
14252 | case 4: | |
14253 | case 5: | |
14254 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14255 | break; | |
14256 | ||
14257 | case 6: | |
14258 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14259 | break; | |
7c9017e5 | 14260 | case 7: |
4e0bbc31 | 14261 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14262 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14263 | break; | |
830c81db | 14264 | case 9: |
ba343e02 TU |
14265 | /* Drop through - unsupported since execlist only. */ |
14266 | default: | |
14267 | /* Default just returns -ENODEV to indicate unsupported */ | |
14268 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14269 | } |
7bd688cd JN |
14270 | |
14271 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14272 | |
14273 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14274 | } |
14275 | ||
b690e96c JB |
14276 | /* |
14277 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14278 | * resume, or other times. This quirk makes sure that's the case for | |
14279 | * affected systems. | |
14280 | */ | |
0206e353 | 14281 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14282 | { |
14283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14284 | ||
14285 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14286 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14287 | } |
14288 | ||
b6b5d049 VS |
14289 | static void quirk_pipeb_force(struct drm_device *dev) |
14290 | { | |
14291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14292 | ||
14293 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14294 | DRM_INFO("applying pipe b force quirk\n"); | |
14295 | } | |
14296 | ||
435793df KP |
14297 | /* |
14298 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14299 | */ | |
14300 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14301 | { | |
14302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14303 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14304 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14305 | } |
14306 | ||
4dca20ef | 14307 | /* |
5a15ab5b CE |
14308 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14309 | * brightness value | |
4dca20ef CE |
14310 | */ |
14311 | static void quirk_invert_brightness(struct drm_device *dev) | |
14312 | { | |
14313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14314 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14315 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14316 | } |
14317 | ||
9c72cc6f SD |
14318 | /* Some VBT's incorrectly indicate no backlight is present */ |
14319 | static void quirk_backlight_present(struct drm_device *dev) | |
14320 | { | |
14321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14322 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14323 | DRM_INFO("applying backlight present quirk\n"); | |
14324 | } | |
14325 | ||
b690e96c JB |
14326 | struct intel_quirk { |
14327 | int device; | |
14328 | int subsystem_vendor; | |
14329 | int subsystem_device; | |
14330 | void (*hook)(struct drm_device *dev); | |
14331 | }; | |
14332 | ||
5f85f176 EE |
14333 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14334 | struct intel_dmi_quirk { | |
14335 | void (*hook)(struct drm_device *dev); | |
14336 | const struct dmi_system_id (*dmi_id_list)[]; | |
14337 | }; | |
14338 | ||
14339 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14340 | { | |
14341 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14342 | return 1; | |
14343 | } | |
14344 | ||
14345 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14346 | { | |
14347 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14348 | { | |
14349 | .callback = intel_dmi_reverse_brightness, | |
14350 | .ident = "NCR Corporation", | |
14351 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14352 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14353 | }, | |
14354 | }, | |
14355 | { } /* terminating entry */ | |
14356 | }, | |
14357 | .hook = quirk_invert_brightness, | |
14358 | }, | |
14359 | }; | |
14360 | ||
c43b5634 | 14361 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 14362 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 14363 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 14364 | |
b690e96c JB |
14365 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14366 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14367 | ||
b690e96c JB |
14368 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14369 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14370 | ||
5f080c0f VS |
14371 | /* 830 needs to leave pipe A & dpll A up */ |
14372 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14373 | ||
b6b5d049 VS |
14374 | /* 830 needs to leave pipe B & dpll B up */ |
14375 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14376 | ||
435793df KP |
14377 | /* Lenovo U160 cannot use SSC on LVDS */ |
14378 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14379 | |
14380 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14381 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14382 | |
be505f64 AH |
14383 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14384 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14385 | ||
14386 | /* Acer/eMachines G725 */ | |
14387 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14388 | ||
14389 | /* Acer/eMachines e725 */ | |
14390 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14391 | ||
14392 | /* Acer/Packard Bell NCL20 */ | |
14393 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14394 | ||
14395 | /* Acer Aspire 4736Z */ | |
14396 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14397 | |
14398 | /* Acer Aspire 5336 */ | |
14399 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14400 | |
14401 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14402 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14403 | |
dfb3d47b SD |
14404 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14405 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14406 | ||
b2a9601c | 14407 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14408 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14409 | ||
d4967d8c SD |
14410 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14411 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14412 | |
14413 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14414 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14415 | |
14416 | /* Dell Chromebook 11 */ | |
14417 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14418 | }; |
14419 | ||
14420 | static void intel_init_quirks(struct drm_device *dev) | |
14421 | { | |
14422 | struct pci_dev *d = dev->pdev; | |
14423 | int i; | |
14424 | ||
14425 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14426 | struct intel_quirk *q = &intel_quirks[i]; | |
14427 | ||
14428 | if (d->device == q->device && | |
14429 | (d->subsystem_vendor == q->subsystem_vendor || | |
14430 | q->subsystem_vendor == PCI_ANY_ID) && | |
14431 | (d->subsystem_device == q->subsystem_device || | |
14432 | q->subsystem_device == PCI_ANY_ID)) | |
14433 | q->hook(dev); | |
14434 | } | |
5f85f176 EE |
14435 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14436 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14437 | intel_dmi_quirks[i].hook(dev); | |
14438 | } | |
b690e96c JB |
14439 | } |
14440 | ||
9cce37f4 JB |
14441 | /* Disable the VGA plane that we never use */ |
14442 | static void i915_disable_vga(struct drm_device *dev) | |
14443 | { | |
14444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14445 | u8 sr1; | |
766aa1c4 | 14446 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14447 | |
2b37c616 | 14448 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14449 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14450 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14451 | sr1 = inb(VGA_SR_DATA); |
14452 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14453 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14454 | udelay(300); | |
14455 | ||
01f5a626 | 14456 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14457 | POSTING_READ(vga_reg); |
14458 | } | |
14459 | ||
f817586c DV |
14460 | void intel_modeset_init_hw(struct drm_device *dev) |
14461 | { | |
a8f78b58 ED |
14462 | intel_prepare_ddi(dev); |
14463 | ||
f8bf63fd VS |
14464 | if (IS_VALLEYVIEW(dev)) |
14465 | vlv_update_cdclk(dev); | |
14466 | ||
f817586c DV |
14467 | intel_init_clock_gating(dev); |
14468 | ||
8090c6b9 | 14469 | intel_enable_gt_powersave(dev); |
f817586c DV |
14470 | } |
14471 | ||
79e53945 JB |
14472 | void intel_modeset_init(struct drm_device *dev) |
14473 | { | |
652c393a | 14474 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14475 | int sprite, ret; |
8cc87b75 | 14476 | enum pipe pipe; |
46f297fb | 14477 | struct intel_crtc *crtc; |
79e53945 JB |
14478 | |
14479 | drm_mode_config_init(dev); | |
14480 | ||
14481 | dev->mode_config.min_width = 0; | |
14482 | dev->mode_config.min_height = 0; | |
14483 | ||
019d96cb DA |
14484 | dev->mode_config.preferred_depth = 24; |
14485 | dev->mode_config.prefer_shadow = 1; | |
14486 | ||
25bab385 TU |
14487 | dev->mode_config.allow_fb_modifiers = true; |
14488 | ||
e6ecefaa | 14489 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14490 | |
b690e96c JB |
14491 | intel_init_quirks(dev); |
14492 | ||
1fa61106 ED |
14493 | intel_init_pm(dev); |
14494 | ||
e3c74757 BW |
14495 | if (INTEL_INFO(dev)->num_pipes == 0) |
14496 | return; | |
14497 | ||
e70236a8 | 14498 | intel_init_display(dev); |
7c10a2b5 | 14499 | intel_init_audio(dev); |
e70236a8 | 14500 | |
a6c45cf0 CW |
14501 | if (IS_GEN2(dev)) { |
14502 | dev->mode_config.max_width = 2048; | |
14503 | dev->mode_config.max_height = 2048; | |
14504 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14505 | dev->mode_config.max_width = 4096; |
14506 | dev->mode_config.max_height = 4096; | |
79e53945 | 14507 | } else { |
a6c45cf0 CW |
14508 | dev->mode_config.max_width = 8192; |
14509 | dev->mode_config.max_height = 8192; | |
79e53945 | 14510 | } |
068be561 | 14511 | |
dc41c154 VS |
14512 | if (IS_845G(dev) || IS_I865G(dev)) { |
14513 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14514 | dev->mode_config.cursor_height = 1023; | |
14515 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14516 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14517 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14518 | } else { | |
14519 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14520 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14521 | } | |
14522 | ||
5d4545ae | 14523 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14524 | |
28c97730 | 14525 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14526 | INTEL_INFO(dev)->num_pipes, |
14527 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14528 | |
055e393f | 14529 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14530 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14531 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14532 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14533 | if (ret) |
06da8da2 | 14534 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14535 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14536 | } |
79e53945 JB |
14537 | } |
14538 | ||
f42bb70d JB |
14539 | intel_init_dpio(dev); |
14540 | ||
e72f9fbf | 14541 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14542 | |
9cce37f4 JB |
14543 | /* Just disable it once at startup */ |
14544 | i915_disable_vga(dev); | |
79e53945 | 14545 | intel_setup_outputs(dev); |
11be49eb CW |
14546 | |
14547 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14548 | intel_fbc_disable(dev); |
fa9fa083 | 14549 | |
6e9f798d | 14550 | drm_modeset_lock_all(dev); |
fa9fa083 | 14551 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14552 | drm_modeset_unlock_all(dev); |
46f297fb | 14553 | |
d3fcc808 | 14554 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14555 | if (!crtc->active) |
14556 | continue; | |
14557 | ||
46f297fb | 14558 | /* |
46f297fb JB |
14559 | * Note that reserving the BIOS fb up front prevents us |
14560 | * from stuffing other stolen allocations like the ring | |
14561 | * on top. This prevents some ugliness at boot time, and | |
14562 | * can even allow for smooth boot transitions if the BIOS | |
14563 | * fb is large enough for the active pipe configuration. | |
14564 | */ | |
5724dbd1 DL |
14565 | if (dev_priv->display.get_initial_plane_config) { |
14566 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14567 | &crtc->plane_config); |
14568 | /* | |
14569 | * If the fb is shared between multiple heads, we'll | |
14570 | * just get the first one. | |
14571 | */ | |
f6936e29 | 14572 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14573 | } |
46f297fb | 14574 | } |
2c7111db CW |
14575 | } |
14576 | ||
7fad798e DV |
14577 | static void intel_enable_pipe_a(struct drm_device *dev) |
14578 | { | |
14579 | struct intel_connector *connector; | |
14580 | struct drm_connector *crt = NULL; | |
14581 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14582 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14583 | |
14584 | /* We can't just switch on the pipe A, we need to set things up with a | |
14585 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14586 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14587 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14588 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14589 | crt = &connector->base; | |
14590 | break; | |
14591 | } | |
14592 | } | |
14593 | ||
14594 | if (!crt) | |
14595 | return; | |
14596 | ||
208bf9fd | 14597 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14598 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14599 | } |
14600 | ||
fa555837 DV |
14601 | static bool |
14602 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14603 | { | |
7eb552ae BW |
14604 | struct drm_device *dev = crtc->base.dev; |
14605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14606 | u32 reg, val; |
14607 | ||
7eb552ae | 14608 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14609 | return true; |
14610 | ||
14611 | reg = DSPCNTR(!crtc->plane); | |
14612 | val = I915_READ(reg); | |
14613 | ||
14614 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14615 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14616 | return false; | |
14617 | ||
14618 | return true; | |
14619 | } | |
14620 | ||
24929352 DV |
14621 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14622 | { | |
14623 | struct drm_device *dev = crtc->base.dev; | |
14624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14625 | u32 reg; |
24929352 | 14626 | |
24929352 | 14627 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14628 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14629 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14630 | ||
d3eaf884 | 14631 | /* restore vblank interrupts to correct state */ |
9625604c | 14632 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14633 | if (crtc->active) { |
14634 | update_scanline_offset(crtc); | |
9625604c DV |
14635 | drm_crtc_vblank_on(&crtc->base); |
14636 | } | |
d3eaf884 | 14637 | |
24929352 | 14638 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14639 | * disable the crtc (and hence change the state) if it is wrong. Note |
14640 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14641 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14642 | struct intel_connector *connector; |
14643 | bool plane; | |
14644 | ||
24929352 DV |
14645 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14646 | crtc->base.base.id); | |
14647 | ||
14648 | /* Pipe has the wrong plane attached and the plane is active. | |
14649 | * Temporarily change the plane mapping and disable everything | |
14650 | * ... */ | |
14651 | plane = crtc->plane; | |
14652 | crtc->plane = !plane; | |
9c8958bc | 14653 | crtc->primary_enabled = true; |
24929352 DV |
14654 | dev_priv->display.crtc_disable(&crtc->base); |
14655 | crtc->plane = plane; | |
14656 | ||
14657 | /* ... and break all links. */ | |
3a3371ff | 14658 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14659 | if (connector->encoder->base.crtc != &crtc->base) |
14660 | continue; | |
14661 | ||
7f1950fb EE |
14662 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14663 | connector->base.encoder = NULL; | |
24929352 | 14664 | } |
7f1950fb EE |
14665 | /* multiple connectors may have the same encoder: |
14666 | * handle them and break crtc link separately */ | |
3a3371ff | 14667 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14668 | if (connector->encoder->base.crtc == &crtc->base) { |
14669 | connector->encoder->base.crtc = NULL; | |
14670 | connector->encoder->connectors_active = false; | |
14671 | } | |
24929352 DV |
14672 | |
14673 | WARN_ON(crtc->active); | |
83d65738 | 14674 | crtc->base.state->enable = false; |
24929352 DV |
14675 | crtc->base.enabled = false; |
14676 | } | |
24929352 | 14677 | |
7fad798e DV |
14678 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14679 | crtc->pipe == PIPE_A && !crtc->active) { | |
14680 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14681 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14682 | * call below we restore the pipe to the right state, but leave | |
14683 | * the required bits on. */ | |
14684 | intel_enable_pipe_a(dev); | |
14685 | } | |
14686 | ||
24929352 DV |
14687 | /* Adjust the state of the output pipe according to whether we |
14688 | * have active connectors/encoders. */ | |
14689 | intel_crtc_update_dpms(&crtc->base); | |
14690 | ||
83d65738 | 14691 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14692 | struct intel_encoder *encoder; |
14693 | ||
14694 | /* This can happen either due to bugs in the get_hw_state | |
14695 | * functions or because the pipe is force-enabled due to the | |
14696 | * pipe A quirk. */ | |
14697 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14698 | crtc->base.base.id, | |
83d65738 | 14699 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14700 | crtc->active ? "enabled" : "disabled"); |
14701 | ||
83d65738 | 14702 | crtc->base.state->enable = crtc->active; |
24929352 DV |
14703 | crtc->base.enabled = crtc->active; |
14704 | ||
14705 | /* Because we only establish the connector -> encoder -> | |
14706 | * crtc links if something is active, this means the | |
14707 | * crtc is now deactivated. Break the links. connector | |
14708 | * -> encoder links are only establish when things are | |
14709 | * actually up, hence no need to break them. */ | |
14710 | WARN_ON(crtc->active); | |
14711 | ||
14712 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14713 | WARN_ON(encoder->connectors_active); | |
14714 | encoder->base.crtc = NULL; | |
14715 | } | |
14716 | } | |
c5ab3bc0 | 14717 | |
a3ed6aad | 14718 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14719 | /* |
14720 | * We start out with underrun reporting disabled to avoid races. | |
14721 | * For correct bookkeeping mark this on active crtcs. | |
14722 | * | |
c5ab3bc0 DV |
14723 | * Also on gmch platforms we dont have any hardware bits to |
14724 | * disable the underrun reporting. Which means we need to start | |
14725 | * out with underrun reporting disabled also on inactive pipes, | |
14726 | * since otherwise we'll complain about the garbage we read when | |
14727 | * e.g. coming up after runtime pm. | |
14728 | * | |
4cc31489 DV |
14729 | * No protection against concurrent access is required - at |
14730 | * worst a fifo underrun happens which also sets this to false. | |
14731 | */ | |
14732 | crtc->cpu_fifo_underrun_disabled = true; | |
14733 | crtc->pch_fifo_underrun_disabled = true; | |
14734 | } | |
24929352 DV |
14735 | } |
14736 | ||
14737 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14738 | { | |
14739 | struct intel_connector *connector; | |
14740 | struct drm_device *dev = encoder->base.dev; | |
14741 | ||
14742 | /* We need to check both for a crtc link (meaning that the | |
14743 | * encoder is active and trying to read from a pipe) and the | |
14744 | * pipe itself being active. */ | |
14745 | bool has_active_crtc = encoder->base.crtc && | |
14746 | to_intel_crtc(encoder->base.crtc)->active; | |
14747 | ||
14748 | if (encoder->connectors_active && !has_active_crtc) { | |
14749 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14750 | encoder->base.base.id, | |
8e329a03 | 14751 | encoder->base.name); |
24929352 DV |
14752 | |
14753 | /* Connector is active, but has no active pipe. This is | |
14754 | * fallout from our resume register restoring. Disable | |
14755 | * the encoder manually again. */ | |
14756 | if (encoder->base.crtc) { | |
14757 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14758 | encoder->base.base.id, | |
8e329a03 | 14759 | encoder->base.name); |
24929352 | 14760 | encoder->disable(encoder); |
a62d1497 VS |
14761 | if (encoder->post_disable) |
14762 | encoder->post_disable(encoder); | |
24929352 | 14763 | } |
7f1950fb EE |
14764 | encoder->base.crtc = NULL; |
14765 | encoder->connectors_active = false; | |
24929352 DV |
14766 | |
14767 | /* Inconsistent output/port/pipe state happens presumably due to | |
14768 | * a bug in one of the get_hw_state functions. Or someplace else | |
14769 | * in our code, like the register restore mess on resume. Clamp | |
14770 | * things to off as a safer default. */ | |
3a3371ff | 14771 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14772 | if (connector->encoder != encoder) |
14773 | continue; | |
7f1950fb EE |
14774 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14775 | connector->base.encoder = NULL; | |
24929352 DV |
14776 | } |
14777 | } | |
14778 | /* Enabled encoders without active connectors will be fixed in | |
14779 | * the crtc fixup. */ | |
14780 | } | |
14781 | ||
04098753 | 14782 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14783 | { |
14784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14785 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14786 | |
04098753 ID |
14787 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14788 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14789 | i915_disable_vga(dev); | |
14790 | } | |
14791 | } | |
14792 | ||
14793 | void i915_redisable_vga(struct drm_device *dev) | |
14794 | { | |
14795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14796 | ||
8dc8a27c PZ |
14797 | /* This function can be called both from intel_modeset_setup_hw_state or |
14798 | * at a very early point in our resume sequence, where the power well | |
14799 | * structures are not yet restored. Since this function is at a very | |
14800 | * paranoid "someone might have enabled VGA while we were not looking" | |
14801 | * level, just check if the power well is enabled instead of trying to | |
14802 | * follow the "don't touch the power well if we don't need it" policy | |
14803 | * the rest of the driver uses. */ | |
f458ebbc | 14804 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14805 | return; |
14806 | ||
04098753 | 14807 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14808 | } |
14809 | ||
98ec7739 VS |
14810 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14811 | { | |
14812 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14813 | ||
14814 | if (!crtc->active) | |
14815 | return false; | |
14816 | ||
14817 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14818 | } | |
14819 | ||
30e984df | 14820 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14821 | { |
14822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14823 | enum pipe pipe; | |
24929352 DV |
14824 | struct intel_crtc *crtc; |
14825 | struct intel_encoder *encoder; | |
14826 | struct intel_connector *connector; | |
5358901f | 14827 | int i; |
24929352 | 14828 | |
d3fcc808 | 14829 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 14830 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14831 | |
6e3c9717 | 14832 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14833 | |
0e8ffe1b | 14834 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14835 | crtc->config); |
24929352 | 14836 | |
83d65738 | 14837 | crtc->base.state->enable = crtc->active; |
24929352 | 14838 | crtc->base.enabled = crtc->active; |
98ec7739 | 14839 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
14840 | |
14841 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14842 | crtc->base.base.id, | |
14843 | crtc->active ? "enabled" : "disabled"); | |
14844 | } | |
14845 | ||
5358901f DV |
14846 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14847 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14848 | ||
3e369b76 ACO |
14849 | pll->on = pll->get_hw_state(dev_priv, pll, |
14850 | &pll->config.hw_state); | |
5358901f | 14851 | pll->active = 0; |
3e369b76 | 14852 | pll->config.crtc_mask = 0; |
d3fcc808 | 14853 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14854 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14855 | pll->active++; |
3e369b76 | 14856 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14857 | } |
5358901f | 14858 | } |
5358901f | 14859 | |
1e6f2ddc | 14860 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14861 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14862 | |
3e369b76 | 14863 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14864 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14865 | } |
14866 | ||
b2784e15 | 14867 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14868 | pipe = 0; |
14869 | ||
14870 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14871 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14872 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14873 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14874 | } else { |
14875 | encoder->base.crtc = NULL; | |
14876 | } | |
14877 | ||
14878 | encoder->connectors_active = false; | |
6f2bcceb | 14879 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14880 | encoder->base.base.id, |
8e329a03 | 14881 | encoder->base.name, |
24929352 | 14882 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14883 | pipe_name(pipe)); |
24929352 DV |
14884 | } |
14885 | ||
3a3371ff | 14886 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14887 | if (connector->get_hw_state(connector)) { |
14888 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14889 | connector->encoder->connectors_active = true; | |
14890 | connector->base.encoder = &connector->encoder->base; | |
14891 | } else { | |
14892 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14893 | connector->base.encoder = NULL; | |
14894 | } | |
14895 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14896 | connector->base.base.id, | |
c23cc417 | 14897 | connector->base.name, |
24929352 DV |
14898 | connector->base.encoder ? "enabled" : "disabled"); |
14899 | } | |
30e984df DV |
14900 | } |
14901 | ||
14902 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14903 | * and i915 state tracking structures. */ | |
14904 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14905 | bool force_restore) | |
14906 | { | |
14907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14908 | enum pipe pipe; | |
30e984df DV |
14909 | struct intel_crtc *crtc; |
14910 | struct intel_encoder *encoder; | |
35c95375 | 14911 | int i; |
30e984df DV |
14912 | |
14913 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14914 | |
babea61d JB |
14915 | /* |
14916 | * Now that we have the config, copy it to each CRTC struct | |
14917 | * Note that this could go away if we move to using crtc_config | |
14918 | * checking everywhere. | |
14919 | */ | |
d3fcc808 | 14920 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14921 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14922 | intel_mode_from_pipe_config(&crtc->base.mode, |
14923 | crtc->config); | |
babea61d JB |
14924 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14925 | crtc->base.base.id); | |
14926 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14927 | } | |
14928 | } | |
14929 | ||
24929352 | 14930 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14931 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14932 | intel_sanitize_encoder(encoder); |
14933 | } | |
14934 | ||
055e393f | 14935 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14936 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14937 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14938 | intel_dump_pipe_config(crtc, crtc->config, |
14939 | "[setup_hw_state]"); | |
24929352 | 14940 | } |
9a935856 | 14941 | |
d29b2f9d ACO |
14942 | intel_modeset_update_connector_atomic_state(dev); |
14943 | ||
35c95375 DV |
14944 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14945 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14946 | ||
14947 | if (!pll->on || pll->active) | |
14948 | continue; | |
14949 | ||
14950 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14951 | ||
14952 | pll->disable(dev_priv, pll); | |
14953 | pll->on = false; | |
14954 | } | |
14955 | ||
3078999f PB |
14956 | if (IS_GEN9(dev)) |
14957 | skl_wm_get_hw_state(dev); | |
14958 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14959 | ilk_wm_get_hw_state(dev); |
14960 | ||
45e2b5f6 | 14961 | if (force_restore) { |
7d0bc1ea VS |
14962 | i915_redisable_vga(dev); |
14963 | ||
f30da187 DV |
14964 | /* |
14965 | * We need to use raw interfaces for restoring state to avoid | |
14966 | * checking (bogus) intermediate states. | |
14967 | */ | |
055e393f | 14968 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14969 | struct drm_crtc *crtc = |
14970 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14971 | |
83a57153 | 14972 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14973 | } |
14974 | } else { | |
14975 | intel_modeset_update_staged_output_state(dev); | |
14976 | } | |
8af6cf88 DV |
14977 | |
14978 | intel_modeset_check_state(dev); | |
2c7111db CW |
14979 | } |
14980 | ||
14981 | void intel_modeset_gem_init(struct drm_device *dev) | |
14982 | { | |
92122789 | 14983 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14984 | struct drm_crtc *c; |
2ff8fde1 | 14985 | struct drm_i915_gem_object *obj; |
484b41dd | 14986 | |
ae48434c ID |
14987 | mutex_lock(&dev->struct_mutex); |
14988 | intel_init_gt_powersave(dev); | |
14989 | mutex_unlock(&dev->struct_mutex); | |
14990 | ||
92122789 JB |
14991 | /* |
14992 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14993 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14994 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14995 | * indicates as much. | |
14996 | */ | |
14997 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14998 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14999 | DREF_SSC1_ENABLE); | |
15000 | ||
1833b134 | 15001 | intel_modeset_init_hw(dev); |
02e792fb DV |
15002 | |
15003 | intel_setup_overlay(dev); | |
484b41dd JB |
15004 | |
15005 | /* | |
15006 | * Make sure any fbs we allocated at startup are properly | |
15007 | * pinned & fenced. When we do the allocation it's too early | |
15008 | * for this. | |
15009 | */ | |
15010 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 15011 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15012 | obj = intel_fb_obj(c->primary->fb); |
15013 | if (obj == NULL) | |
484b41dd JB |
15014 | continue; |
15015 | ||
850c4cdc TU |
15016 | if (intel_pin_and_fence_fb_obj(c->primary, |
15017 | c->primary->fb, | |
82bc3b2d | 15018 | c->primary->state, |
850c4cdc | 15019 | NULL)) { |
484b41dd JB |
15020 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15021 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15022 | drm_framebuffer_unreference(c->primary->fb); |
15023 | c->primary->fb = NULL; | |
afd65eb4 | 15024 | update_state_fb(c->primary); |
484b41dd JB |
15025 | } |
15026 | } | |
15027 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
15028 | |
15029 | intel_backlight_register(dev); | |
79e53945 JB |
15030 | } |
15031 | ||
4932e2c3 ID |
15032 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15033 | { | |
15034 | struct drm_connector *connector = &intel_connector->base; | |
15035 | ||
15036 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15037 | drm_connector_unregister(connector); |
4932e2c3 ID |
15038 | } |
15039 | ||
79e53945 JB |
15040 | void intel_modeset_cleanup(struct drm_device *dev) |
15041 | { | |
652c393a | 15042 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15043 | struct drm_connector *connector; |
652c393a | 15044 | |
2eb5252e ID |
15045 | intel_disable_gt_powersave(dev); |
15046 | ||
0962c3c9 VS |
15047 | intel_backlight_unregister(dev); |
15048 | ||
fd0c0642 DV |
15049 | /* |
15050 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15051 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15052 | * experience fancy races otherwise. |
15053 | */ | |
2aeb7d3a | 15054 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15055 | |
fd0c0642 DV |
15056 | /* |
15057 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15058 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15059 | */ | |
f87ea761 | 15060 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15061 | |
652c393a JB |
15062 | mutex_lock(&dev->struct_mutex); |
15063 | ||
723bfd70 JB |
15064 | intel_unregister_dsm_handler(); |
15065 | ||
7ff0ebcc | 15066 | intel_fbc_disable(dev); |
e70236a8 | 15067 | |
69341a5e KH |
15068 | mutex_unlock(&dev->struct_mutex); |
15069 | ||
1630fe75 CW |
15070 | /* flush any delayed tasks or pending work */ |
15071 | flush_scheduled_work(); | |
15072 | ||
db31af1d JN |
15073 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15074 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15075 | struct intel_connector *intel_connector; |
15076 | ||
15077 | intel_connector = to_intel_connector(connector); | |
15078 | intel_connector->unregister(intel_connector); | |
db31af1d | 15079 | } |
d9255d57 | 15080 | |
79e53945 | 15081 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15082 | |
15083 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15084 | |
15085 | mutex_lock(&dev->struct_mutex); | |
15086 | intel_cleanup_gt_powersave(dev); | |
15087 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15088 | } |
15089 | ||
f1c79df3 ZW |
15090 | /* |
15091 | * Return which encoder is currently attached for connector. | |
15092 | */ | |
df0e9248 | 15093 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15094 | { |
df0e9248 CW |
15095 | return &intel_attached_encoder(connector)->base; |
15096 | } | |
f1c79df3 | 15097 | |
df0e9248 CW |
15098 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15099 | struct intel_encoder *encoder) | |
15100 | { | |
15101 | connector->encoder = encoder; | |
15102 | drm_mode_connector_attach_encoder(&connector->base, | |
15103 | &encoder->base); | |
79e53945 | 15104 | } |
28d52043 DA |
15105 | |
15106 | /* | |
15107 | * set vga decode state - true == enable VGA decode | |
15108 | */ | |
15109 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15110 | { | |
15111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15112 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15113 | u16 gmch_ctrl; |
15114 | ||
75fa041d CW |
15115 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15116 | DRM_ERROR("failed to read control word\n"); | |
15117 | return -EIO; | |
15118 | } | |
15119 | ||
c0cc8a55 CW |
15120 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15121 | return 0; | |
15122 | ||
28d52043 DA |
15123 | if (state) |
15124 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15125 | else | |
15126 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15127 | |
15128 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15129 | DRM_ERROR("failed to write control word\n"); | |
15130 | return -EIO; | |
15131 | } | |
15132 | ||
28d52043 DA |
15133 | return 0; |
15134 | } | |
c4a1d9e4 | 15135 | |
c4a1d9e4 | 15136 | struct intel_display_error_state { |
ff57f1b0 PZ |
15137 | |
15138 | u32 power_well_driver; | |
15139 | ||
63b66e5b CW |
15140 | int num_transcoders; |
15141 | ||
c4a1d9e4 CW |
15142 | struct intel_cursor_error_state { |
15143 | u32 control; | |
15144 | u32 position; | |
15145 | u32 base; | |
15146 | u32 size; | |
52331309 | 15147 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15148 | |
15149 | struct intel_pipe_error_state { | |
ddf9c536 | 15150 | bool power_domain_on; |
c4a1d9e4 | 15151 | u32 source; |
f301b1e1 | 15152 | u32 stat; |
52331309 | 15153 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15154 | |
15155 | struct intel_plane_error_state { | |
15156 | u32 control; | |
15157 | u32 stride; | |
15158 | u32 size; | |
15159 | u32 pos; | |
15160 | u32 addr; | |
15161 | u32 surface; | |
15162 | u32 tile_offset; | |
52331309 | 15163 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15164 | |
15165 | struct intel_transcoder_error_state { | |
ddf9c536 | 15166 | bool power_domain_on; |
63b66e5b CW |
15167 | enum transcoder cpu_transcoder; |
15168 | ||
15169 | u32 conf; | |
15170 | ||
15171 | u32 htotal; | |
15172 | u32 hblank; | |
15173 | u32 hsync; | |
15174 | u32 vtotal; | |
15175 | u32 vblank; | |
15176 | u32 vsync; | |
15177 | } transcoder[4]; | |
c4a1d9e4 CW |
15178 | }; |
15179 | ||
15180 | struct intel_display_error_state * | |
15181 | intel_display_capture_error_state(struct drm_device *dev) | |
15182 | { | |
fbee40df | 15183 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15184 | struct intel_display_error_state *error; |
63b66e5b CW |
15185 | int transcoders[] = { |
15186 | TRANSCODER_A, | |
15187 | TRANSCODER_B, | |
15188 | TRANSCODER_C, | |
15189 | TRANSCODER_EDP, | |
15190 | }; | |
c4a1d9e4 CW |
15191 | int i; |
15192 | ||
63b66e5b CW |
15193 | if (INTEL_INFO(dev)->num_pipes == 0) |
15194 | return NULL; | |
15195 | ||
9d1cb914 | 15196 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15197 | if (error == NULL) |
15198 | return NULL; | |
15199 | ||
190be112 | 15200 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15201 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15202 | ||
055e393f | 15203 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15204 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15205 | __intel_display_power_is_enabled(dev_priv, |
15206 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15207 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15208 | continue; |
15209 | ||
5efb3e28 VS |
15210 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15211 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15212 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15213 | |
15214 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15215 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15216 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15217 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15218 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15219 | } | |
ca291363 PZ |
15220 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15221 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15222 | if (INTEL_INFO(dev)->gen >= 4) { |
15223 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15224 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15225 | } | |
15226 | ||
c4a1d9e4 | 15227 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15228 | |
3abfce77 | 15229 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15230 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15231 | } |
15232 | ||
15233 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15234 | if (HAS_DDI(dev_priv->dev)) | |
15235 | error->num_transcoders++; /* Account for eDP. */ | |
15236 | ||
15237 | for (i = 0; i < error->num_transcoders; i++) { | |
15238 | enum transcoder cpu_transcoder = transcoders[i]; | |
15239 | ||
ddf9c536 | 15240 | error->transcoder[i].power_domain_on = |
f458ebbc | 15241 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15242 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15243 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15244 | continue; |
15245 | ||
63b66e5b CW |
15246 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15247 | ||
15248 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15249 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15250 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15251 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15252 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15253 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15254 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15255 | } |
15256 | ||
15257 | return error; | |
15258 | } | |
15259 | ||
edc3d884 MK |
15260 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15261 | ||
c4a1d9e4 | 15262 | void |
edc3d884 | 15263 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15264 | struct drm_device *dev, |
15265 | struct intel_display_error_state *error) | |
15266 | { | |
055e393f | 15267 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15268 | int i; |
15269 | ||
63b66e5b CW |
15270 | if (!error) |
15271 | return; | |
15272 | ||
edc3d884 | 15273 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15274 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15275 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15276 | error->power_well_driver); |
055e393f | 15277 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15278 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15279 | err_printf(m, " Power: %s\n", |
15280 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15281 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15282 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15283 | |
15284 | err_printf(m, "Plane [%d]:\n", i); | |
15285 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15286 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15287 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15288 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15289 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15290 | } |
4b71a570 | 15291 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15292 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15293 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15294 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15295 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15296 | } |
15297 | ||
edc3d884 MK |
15298 | err_printf(m, "Cursor [%d]:\n", i); |
15299 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15300 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15301 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15302 | } |
63b66e5b CW |
15303 | |
15304 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15305 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15306 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15307 | err_printf(m, " Power: %s\n", |
15308 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15309 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15310 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15311 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15312 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15313 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15314 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15315 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15316 | } | |
c4a1d9e4 | 15317 | } |
e2fcdaa9 VS |
15318 | |
15319 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15320 | { | |
15321 | struct intel_crtc *crtc; | |
15322 | ||
15323 | for_each_intel_crtc(dev, crtc) { | |
15324 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15325 | |
5e2d7afc | 15326 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15327 | |
15328 | work = crtc->unpin_work; | |
15329 | ||
15330 | if (work && work->event && | |
15331 | work->event->base.file_priv == file) { | |
15332 | kfree(work->event); | |
15333 | work->event = NULL; | |
15334 | } | |
15335 | ||
5e2d7afc | 15336 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15337 | } |
15338 | } |