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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
54 | static int intel_framebuffer_init(struct drm_device *dev, |
55 | struct intel_framebuffer *ifb, | |
56 | struct drm_mode_fb_cmd2 *mode_cmd, | |
57 | struct drm_i915_gem_object *obj); | |
e7457a9a | 58 | |
79e53945 | 59 | typedef struct { |
0206e353 | 60 | int min, max; |
79e53945 JB |
61 | } intel_range_t; |
62 | ||
63 | typedef struct { | |
0206e353 AJ |
64 | int dot_limit; |
65 | int p2_slow, p2_fast; | |
79e53945 JB |
66 | } intel_p2_t; |
67 | ||
d4906093 ML |
68 | typedef struct intel_limit intel_limit_t; |
69 | struct intel_limit { | |
0206e353 AJ |
70 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
71 | intel_p2_t p2; | |
d4906093 | 72 | }; |
79e53945 | 73 | |
d2acd215 DV |
74 | int |
75 | intel_pch_rawclk(struct drm_device *dev) | |
76 | { | |
77 | struct drm_i915_private *dev_priv = dev->dev_private; | |
78 | ||
79 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
80 | ||
81 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
82 | } | |
83 | ||
021357ac CW |
84 | static inline u32 /* units of 100MHz */ |
85 | intel_fdi_link_freq(struct drm_device *dev) | |
86 | { | |
8b99e68c CW |
87 | if (IS_GEN5(dev)) { |
88 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
90 | } else | |
91 | return 27; | |
021357ac CW |
92 | } |
93 | ||
5d536e28 | 94 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 95 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 96 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 97 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
98 | .m = { .min = 96, .max = 140 }, |
99 | .m1 = { .min = 18, .max = 26 }, | |
100 | .m2 = { .min = 6, .max = 16 }, | |
101 | .p = { .min = 4, .max = 128 }, | |
102 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
103 | .p2 = { .dot_limit = 165000, |
104 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
105 | }; |
106 | ||
5d536e28 DV |
107 | static const intel_limit_t intel_limits_i8xx_dvo = { |
108 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 109 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 110 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
111 | .m = { .min = 96, .max = 140 }, |
112 | .m1 = { .min = 18, .max = 26 }, | |
113 | .m2 = { .min = 6, .max = 16 }, | |
114 | .p = { .min = 4, .max = 128 }, | |
115 | .p1 = { .min = 2, .max = 33 }, | |
116 | .p2 = { .dot_limit = 165000, | |
117 | .p2_slow = 4, .p2_fast = 4 }, | |
118 | }; | |
119 | ||
e4b36699 | 120 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 121 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 122 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 123 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
124 | .m = { .min = 96, .max = 140 }, |
125 | .m1 = { .min = 18, .max = 26 }, | |
126 | .m2 = { .min = 6, .max = 16 }, | |
127 | .p = { .min = 4, .max = 128 }, | |
128 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
129 | .p2 = { .dot_limit = 165000, |
130 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 131 | }; |
273e27ca | 132 | |
e4b36699 | 133 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
134 | .dot = { .min = 20000, .max = 400000 }, |
135 | .vco = { .min = 1400000, .max = 2800000 }, | |
136 | .n = { .min = 1, .max = 6 }, | |
137 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
138 | .m1 = { .min = 8, .max = 18 }, |
139 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
140 | .p = { .min = 5, .max = 80 }, |
141 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
142 | .p2 = { .dot_limit = 200000, |
143 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
144 | }; |
145 | ||
146 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
147 | .dot = { .min = 20000, .max = 400000 }, |
148 | .vco = { .min = 1400000, .max = 2800000 }, | |
149 | .n = { .min = 1, .max = 6 }, | |
150 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
151 | .m1 = { .min = 8, .max = 18 }, |
152 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
153 | .p = { .min = 7, .max = 98 }, |
154 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
155 | .p2 = { .dot_limit = 112000, |
156 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
157 | }; |
158 | ||
273e27ca | 159 | |
e4b36699 | 160 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
161 | .dot = { .min = 25000, .max = 270000 }, |
162 | .vco = { .min = 1750000, .max = 3500000}, | |
163 | .n = { .min = 1, .max = 4 }, | |
164 | .m = { .min = 104, .max = 138 }, | |
165 | .m1 = { .min = 17, .max = 23 }, | |
166 | .m2 = { .min = 5, .max = 11 }, | |
167 | .p = { .min = 10, .max = 30 }, | |
168 | .p1 = { .min = 1, .max = 3}, | |
169 | .p2 = { .dot_limit = 270000, | |
170 | .p2_slow = 10, | |
171 | .p2_fast = 10 | |
044c7c41 | 172 | }, |
e4b36699 KP |
173 | }; |
174 | ||
175 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
176 | .dot = { .min = 22000, .max = 400000 }, |
177 | .vco = { .min = 1750000, .max = 3500000}, | |
178 | .n = { .min = 1, .max = 4 }, | |
179 | .m = { .min = 104, .max = 138 }, | |
180 | .m1 = { .min = 16, .max = 23 }, | |
181 | .m2 = { .min = 5, .max = 11 }, | |
182 | .p = { .min = 5, .max = 80 }, | |
183 | .p1 = { .min = 1, .max = 8}, | |
184 | .p2 = { .dot_limit = 165000, | |
185 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
186 | }; |
187 | ||
188 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
189 | .dot = { .min = 20000, .max = 115000 }, |
190 | .vco = { .min = 1750000, .max = 3500000 }, | |
191 | .n = { .min = 1, .max = 3 }, | |
192 | .m = { .min = 104, .max = 138 }, | |
193 | .m1 = { .min = 17, .max = 23 }, | |
194 | .m2 = { .min = 5, .max = 11 }, | |
195 | .p = { .min = 28, .max = 112 }, | |
196 | .p1 = { .min = 2, .max = 8 }, | |
197 | .p2 = { .dot_limit = 0, | |
198 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 199 | }, |
e4b36699 KP |
200 | }; |
201 | ||
202 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
203 | .dot = { .min = 80000, .max = 224000 }, |
204 | .vco = { .min = 1750000, .max = 3500000 }, | |
205 | .n = { .min = 1, .max = 3 }, | |
206 | .m = { .min = 104, .max = 138 }, | |
207 | .m1 = { .min = 17, .max = 23 }, | |
208 | .m2 = { .min = 5, .max = 11 }, | |
209 | .p = { .min = 14, .max = 42 }, | |
210 | .p1 = { .min = 2, .max = 6 }, | |
211 | .p2 = { .dot_limit = 0, | |
212 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 213 | }, |
e4b36699 KP |
214 | }; |
215 | ||
f2b115e6 | 216 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
217 | .dot = { .min = 20000, .max = 400000}, |
218 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 219 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
220 | .n = { .min = 3, .max = 6 }, |
221 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 222 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
223 | .m1 = { .min = 0, .max = 0 }, |
224 | .m2 = { .min = 0, .max = 254 }, | |
225 | .p = { .min = 5, .max = 80 }, | |
226 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
227 | .p2 = { .dot_limit = 200000, |
228 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
229 | }; |
230 | ||
f2b115e6 | 231 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
232 | .dot = { .min = 20000, .max = 400000 }, |
233 | .vco = { .min = 1700000, .max = 3500000 }, | |
234 | .n = { .min = 3, .max = 6 }, | |
235 | .m = { .min = 2, .max = 256 }, | |
236 | .m1 = { .min = 0, .max = 0 }, | |
237 | .m2 = { .min = 0, .max = 254 }, | |
238 | .p = { .min = 7, .max = 112 }, | |
239 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
240 | .p2 = { .dot_limit = 112000, |
241 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
242 | }; |
243 | ||
273e27ca EA |
244 | /* Ironlake / Sandybridge |
245 | * | |
246 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
247 | * the range value for them is (actual_value - 2). | |
248 | */ | |
b91ad0ec | 249 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
250 | .dot = { .min = 25000, .max = 350000 }, |
251 | .vco = { .min = 1760000, .max = 3510000 }, | |
252 | .n = { .min = 1, .max = 5 }, | |
253 | .m = { .min = 79, .max = 127 }, | |
254 | .m1 = { .min = 12, .max = 22 }, | |
255 | .m2 = { .min = 5, .max = 9 }, | |
256 | .p = { .min = 5, .max = 80 }, | |
257 | .p1 = { .min = 1, .max = 8 }, | |
258 | .p2 = { .dot_limit = 225000, | |
259 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
260 | }; |
261 | ||
b91ad0ec | 262 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
263 | .dot = { .min = 25000, .max = 350000 }, |
264 | .vco = { .min = 1760000, .max = 3510000 }, | |
265 | .n = { .min = 1, .max = 3 }, | |
266 | .m = { .min = 79, .max = 118 }, | |
267 | .m1 = { .min = 12, .max = 22 }, | |
268 | .m2 = { .min = 5, .max = 9 }, | |
269 | .p = { .min = 28, .max = 112 }, | |
270 | .p1 = { .min = 2, .max = 8 }, | |
271 | .p2 = { .dot_limit = 225000, | |
272 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
273 | }; |
274 | ||
275 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
276 | .dot = { .min = 25000, .max = 350000 }, |
277 | .vco = { .min = 1760000, .max = 3510000 }, | |
278 | .n = { .min = 1, .max = 3 }, | |
279 | .m = { .min = 79, .max = 127 }, | |
280 | .m1 = { .min = 12, .max = 22 }, | |
281 | .m2 = { .min = 5, .max = 9 }, | |
282 | .p = { .min = 14, .max = 56 }, | |
283 | .p1 = { .min = 2, .max = 8 }, | |
284 | .p2 = { .dot_limit = 225000, | |
285 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
286 | }; |
287 | ||
273e27ca | 288 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 289 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
290 | .dot = { .min = 25000, .max = 350000 }, |
291 | .vco = { .min = 1760000, .max = 3510000 }, | |
292 | .n = { .min = 1, .max = 2 }, | |
293 | .m = { .min = 79, .max = 126 }, | |
294 | .m1 = { .min = 12, .max = 22 }, | |
295 | .m2 = { .min = 5, .max = 9 }, | |
296 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 297 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
298 | .p2 = { .dot_limit = 225000, |
299 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
300 | }; |
301 | ||
302 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 350000 }, |
304 | .vco = { .min = 1760000, .max = 3510000 }, | |
305 | .n = { .min = 1, .max = 3 }, | |
306 | .m = { .min = 79, .max = 126 }, | |
307 | .m1 = { .min = 12, .max = 22 }, | |
308 | .m2 = { .min = 5, .max = 9 }, | |
309 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 310 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
311 | .p2 = { .dot_limit = 225000, |
312 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
313 | }; |
314 | ||
dc730512 | 315 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
316 | /* |
317 | * These are the data rate limits (measured in fast clocks) | |
318 | * since those are the strictest limits we have. The fast | |
319 | * clock and actual rate limits are more relaxed, so checking | |
320 | * them would make no difference. | |
321 | */ | |
322 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 323 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 324 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
325 | .m1 = { .min = 2, .max = 3 }, |
326 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 327 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 328 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
329 | }; |
330 | ||
6b4bf1c4 VS |
331 | static void vlv_clock(int refclk, intel_clock_t *clock) |
332 | { | |
333 | clock->m = clock->m1 * clock->m2; | |
334 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
335 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
336 | return; | |
fb03ac01 VS |
337 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
338 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
339 | } |
340 | ||
e0638cdf PZ |
341 | /** |
342 | * Returns whether any output on the specified pipe is of the specified type | |
343 | */ | |
344 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
345 | { | |
346 | struct drm_device *dev = crtc->dev; | |
347 | struct intel_encoder *encoder; | |
348 | ||
349 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
350 | if (encoder->type == type) | |
351 | return true; | |
352 | ||
353 | return false; | |
354 | } | |
355 | ||
1b894b59 CW |
356 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
357 | int refclk) | |
2c07245f | 358 | { |
b91ad0ec | 359 | struct drm_device *dev = crtc->dev; |
2c07245f | 360 | const intel_limit_t *limit; |
b91ad0ec ZW |
361 | |
362 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 363 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 364 | if (refclk == 100000) |
b91ad0ec ZW |
365 | limit = &intel_limits_ironlake_dual_lvds_100m; |
366 | else | |
367 | limit = &intel_limits_ironlake_dual_lvds; | |
368 | } else { | |
1b894b59 | 369 | if (refclk == 100000) |
b91ad0ec ZW |
370 | limit = &intel_limits_ironlake_single_lvds_100m; |
371 | else | |
372 | limit = &intel_limits_ironlake_single_lvds; | |
373 | } | |
c6bb3538 | 374 | } else |
b91ad0ec | 375 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
376 | |
377 | return limit; | |
378 | } | |
379 | ||
044c7c41 ML |
380 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
381 | { | |
382 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
383 | const intel_limit_t *limit; |
384 | ||
385 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 386 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 387 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 388 | else |
e4b36699 | 389 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
390 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
391 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 392 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 393 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 394 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 395 | } else /* The option is for other outputs */ |
e4b36699 | 396 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
397 | |
398 | return limit; | |
399 | } | |
400 | ||
1b894b59 | 401 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
402 | { |
403 | struct drm_device *dev = crtc->dev; | |
404 | const intel_limit_t *limit; | |
405 | ||
bad720ff | 406 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 407 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 408 | else if (IS_G4X(dev)) { |
044c7c41 | 409 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 410 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 411 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 412 | limit = &intel_limits_pineview_lvds; |
2177832f | 413 | else |
f2b115e6 | 414 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 415 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 416 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
417 | } else if (!IS_GEN2(dev)) { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
419 | limit = &intel_limits_i9xx_lvds; | |
420 | else | |
421 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
422 | } else { |
423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 424 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 425 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 426 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
427 | else |
428 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
429 | } |
430 | return limit; | |
431 | } | |
432 | ||
f2b115e6 AJ |
433 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
434 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 435 | { |
2177832f SL |
436 | clock->m = clock->m2 + 2; |
437 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
438 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
439 | return; | |
fb03ac01 VS |
440 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
441 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
442 | } |
443 | ||
7429e9d4 DV |
444 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
445 | { | |
446 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
447 | } | |
448 | ||
ac58c3f0 | 449 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 450 | { |
7429e9d4 | 451 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 452 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
453 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
454 | return; | |
fb03ac01 VS |
455 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
456 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
457 | } |
458 | ||
7c04d1d9 | 459 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
460 | /** |
461 | * Returns whether the given set of divisors are valid for a given refclk with | |
462 | * the given connectors. | |
463 | */ | |
464 | ||
1b894b59 CW |
465 | static bool intel_PLL_is_valid(struct drm_device *dev, |
466 | const intel_limit_t *limit, | |
467 | const intel_clock_t *clock) | |
79e53945 | 468 | { |
f01b7962 VS |
469 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
470 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 471 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 472 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 473 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 474 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 475 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 476 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
477 | |
478 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
479 | if (clock->m1 <= clock->m2) | |
480 | INTELPllInvalid("m1 <= m2\n"); | |
481 | ||
482 | if (!IS_VALLEYVIEW(dev)) { | |
483 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
484 | INTELPllInvalid("p out of range\n"); | |
485 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
486 | INTELPllInvalid("m out of range\n"); | |
487 | } | |
488 | ||
79e53945 | 489 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 490 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
491 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
492 | * connector, etc., rather than just a single range. | |
493 | */ | |
494 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 495 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
496 | |
497 | return true; | |
498 | } | |
499 | ||
d4906093 | 500 | static bool |
ee9300bb | 501 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
502 | int target, int refclk, intel_clock_t *match_clock, |
503 | intel_clock_t *best_clock) | |
79e53945 JB |
504 | { |
505 | struct drm_device *dev = crtc->dev; | |
79e53945 | 506 | intel_clock_t clock; |
79e53945 JB |
507 | int err = target; |
508 | ||
a210b028 | 509 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 510 | /* |
a210b028 DV |
511 | * For LVDS just rely on its current settings for dual-channel. |
512 | * We haven't figured out how to reliably set up different | |
513 | * single/dual channel state, if we even can. | |
79e53945 | 514 | */ |
1974cad0 | 515 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
516 | clock.p2 = limit->p2.p2_fast; |
517 | else | |
518 | clock.p2 = limit->p2.p2_slow; | |
519 | } else { | |
520 | if (target < limit->p2.dot_limit) | |
521 | clock.p2 = limit->p2.p2_slow; | |
522 | else | |
523 | clock.p2 = limit->p2.p2_fast; | |
524 | } | |
525 | ||
0206e353 | 526 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 527 | |
42158660 ZY |
528 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
529 | clock.m1++) { | |
530 | for (clock.m2 = limit->m2.min; | |
531 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 532 | if (clock.m2 >= clock.m1) |
42158660 ZY |
533 | break; |
534 | for (clock.n = limit->n.min; | |
535 | clock.n <= limit->n.max; clock.n++) { | |
536 | for (clock.p1 = limit->p1.min; | |
537 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
538 | int this_err; |
539 | ||
ac58c3f0 DV |
540 | i9xx_clock(refclk, &clock); |
541 | if (!intel_PLL_is_valid(dev, limit, | |
542 | &clock)) | |
543 | continue; | |
544 | if (match_clock && | |
545 | clock.p != match_clock->p) | |
546 | continue; | |
547 | ||
548 | this_err = abs(clock.dot - target); | |
549 | if (this_err < err) { | |
550 | *best_clock = clock; | |
551 | err = this_err; | |
552 | } | |
553 | } | |
554 | } | |
555 | } | |
556 | } | |
557 | ||
558 | return (err != target); | |
559 | } | |
560 | ||
561 | static bool | |
ee9300bb DV |
562 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
563 | int target, int refclk, intel_clock_t *match_clock, | |
564 | intel_clock_t *best_clock) | |
79e53945 JB |
565 | { |
566 | struct drm_device *dev = crtc->dev; | |
79e53945 | 567 | intel_clock_t clock; |
79e53945 JB |
568 | int err = target; |
569 | ||
a210b028 | 570 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 571 | /* |
a210b028 DV |
572 | * For LVDS just rely on its current settings for dual-channel. |
573 | * We haven't figured out how to reliably set up different | |
574 | * single/dual channel state, if we even can. | |
79e53945 | 575 | */ |
1974cad0 | 576 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
577 | clock.p2 = limit->p2.p2_fast; |
578 | else | |
579 | clock.p2 = limit->p2.p2_slow; | |
580 | } else { | |
581 | if (target < limit->p2.dot_limit) | |
582 | clock.p2 = limit->p2.p2_slow; | |
583 | else | |
584 | clock.p2 = limit->p2.p2_fast; | |
585 | } | |
586 | ||
0206e353 | 587 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 588 | |
42158660 ZY |
589 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
590 | clock.m1++) { | |
591 | for (clock.m2 = limit->m2.min; | |
592 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
593 | for (clock.n = limit->n.min; |
594 | clock.n <= limit->n.max; clock.n++) { | |
595 | for (clock.p1 = limit->p1.min; | |
596 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
597 | int this_err; |
598 | ||
ac58c3f0 | 599 | pineview_clock(refclk, &clock); |
1b894b59 CW |
600 | if (!intel_PLL_is_valid(dev, limit, |
601 | &clock)) | |
79e53945 | 602 | continue; |
cec2f356 SP |
603 | if (match_clock && |
604 | clock.p != match_clock->p) | |
605 | continue; | |
79e53945 JB |
606 | |
607 | this_err = abs(clock.dot - target); | |
608 | if (this_err < err) { | |
609 | *best_clock = clock; | |
610 | err = this_err; | |
611 | } | |
612 | } | |
613 | } | |
614 | } | |
615 | } | |
616 | ||
617 | return (err != target); | |
618 | } | |
619 | ||
d4906093 | 620 | static bool |
ee9300bb DV |
621 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
622 | int target, int refclk, intel_clock_t *match_clock, | |
623 | intel_clock_t *best_clock) | |
d4906093 ML |
624 | { |
625 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
626 | intel_clock_t clock; |
627 | int max_n; | |
628 | bool found; | |
6ba770dc AJ |
629 | /* approximately equals target * 0.00585 */ |
630 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
631 | found = false; |
632 | ||
633 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 634 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
635 | clock.p2 = limit->p2.p2_fast; |
636 | else | |
637 | clock.p2 = limit->p2.p2_slow; | |
638 | } else { | |
639 | if (target < limit->p2.dot_limit) | |
640 | clock.p2 = limit->p2.p2_slow; | |
641 | else | |
642 | clock.p2 = limit->p2.p2_fast; | |
643 | } | |
644 | ||
645 | memset(best_clock, 0, sizeof(*best_clock)); | |
646 | max_n = limit->n.max; | |
f77f13e2 | 647 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 648 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 649 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
650 | for (clock.m1 = limit->m1.max; |
651 | clock.m1 >= limit->m1.min; clock.m1--) { | |
652 | for (clock.m2 = limit->m2.max; | |
653 | clock.m2 >= limit->m2.min; clock.m2--) { | |
654 | for (clock.p1 = limit->p1.max; | |
655 | clock.p1 >= limit->p1.min; clock.p1--) { | |
656 | int this_err; | |
657 | ||
ac58c3f0 | 658 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
659 | if (!intel_PLL_is_valid(dev, limit, |
660 | &clock)) | |
d4906093 | 661 | continue; |
1b894b59 CW |
662 | |
663 | this_err = abs(clock.dot - target); | |
d4906093 ML |
664 | if (this_err < err_most) { |
665 | *best_clock = clock; | |
666 | err_most = this_err; | |
667 | max_n = clock.n; | |
668 | found = true; | |
669 | } | |
670 | } | |
671 | } | |
672 | } | |
673 | } | |
2c07245f ZW |
674 | return found; |
675 | } | |
676 | ||
a0c4da24 | 677 | static bool |
ee9300bb DV |
678 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
679 | int target, int refclk, intel_clock_t *match_clock, | |
680 | intel_clock_t *best_clock) | |
a0c4da24 | 681 | { |
f01b7962 | 682 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 683 | intel_clock_t clock; |
69e4f900 | 684 | unsigned int bestppm = 1000000; |
27e639bf VS |
685 | /* min update 19.2 MHz */ |
686 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 687 | bool found = false; |
a0c4da24 | 688 | |
6b4bf1c4 VS |
689 | target *= 5; /* fast clock */ |
690 | ||
691 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
692 | |
693 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 694 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 695 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 696 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 697 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 698 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 699 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 700 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
701 | unsigned int ppm, diff; |
702 | ||
6b4bf1c4 VS |
703 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
704 | refclk * clock.m1); | |
705 | ||
706 | vlv_clock(refclk, &clock); | |
43b0ac53 | 707 | |
f01b7962 VS |
708 | if (!intel_PLL_is_valid(dev, limit, |
709 | &clock)) | |
43b0ac53 VS |
710 | continue; |
711 | ||
6b4bf1c4 VS |
712 | diff = abs(clock.dot - target); |
713 | ppm = div_u64(1000000ULL * diff, target); | |
714 | ||
715 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 716 | bestppm = 0; |
6b4bf1c4 | 717 | *best_clock = clock; |
49e497ef | 718 | found = true; |
43b0ac53 | 719 | } |
6b4bf1c4 | 720 | |
c686122c | 721 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 722 | bestppm = ppm; |
6b4bf1c4 | 723 | *best_clock = clock; |
49e497ef | 724 | found = true; |
a0c4da24 JB |
725 | } |
726 | } | |
727 | } | |
728 | } | |
729 | } | |
a0c4da24 | 730 | |
49e497ef | 731 | return found; |
a0c4da24 | 732 | } |
a4fc5ed6 | 733 | |
20ddf665 VS |
734 | bool intel_crtc_active(struct drm_crtc *crtc) |
735 | { | |
736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
737 | ||
738 | /* Be paranoid as we can arrive here with only partial | |
739 | * state retrieved from the hardware during setup. | |
740 | * | |
241bfc38 | 741 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
742 | * as Haswell has gained clock readout/fastboot support. |
743 | * | |
744 | * We can ditch the crtc->fb check as soon as we can | |
745 | * properly reconstruct framebuffers. | |
746 | */ | |
747 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 748 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
749 | } |
750 | ||
a5c961d1 PZ |
751 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
752 | enum pipe pipe) | |
753 | { | |
754 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756 | ||
3b117c8f | 757 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
758 | } |
759 | ||
57e22f4a | 760 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
761 | { |
762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 763 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
764 | |
765 | frame = I915_READ(frame_reg); | |
766 | ||
767 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
768 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
769 | } | |
770 | ||
9d0498a2 JB |
771 | /** |
772 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
773 | * @dev: drm device | |
774 | * @pipe: pipe to wait for | |
775 | * | |
776 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
777 | * mode setting code. | |
778 | */ | |
779 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 780 | { |
9d0498a2 | 781 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 782 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 783 | |
57e22f4a VS |
784 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
785 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
786 | return; |
787 | } | |
788 | ||
300387c0 CW |
789 | /* Clear existing vblank status. Note this will clear any other |
790 | * sticky status fields as well. | |
791 | * | |
792 | * This races with i915_driver_irq_handler() with the result | |
793 | * that either function could miss a vblank event. Here it is not | |
794 | * fatal, as we will either wait upon the next vblank interrupt or | |
795 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
796 | * called during modeset at which time the GPU should be idle and | |
797 | * should *not* be performing page flips and thus not waiting on | |
798 | * vblanks... | |
799 | * Currently, the result of us stealing a vblank from the irq | |
800 | * handler is that a single frame will be skipped during swapbuffers. | |
801 | */ | |
802 | I915_WRITE(pipestat_reg, | |
803 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
804 | ||
9d0498a2 | 805 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
806 | if (wait_for(I915_READ(pipestat_reg) & |
807 | PIPE_VBLANK_INTERRUPT_STATUS, | |
808 | 50)) | |
9d0498a2 JB |
809 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
810 | } | |
811 | ||
fbf49ea2 VS |
812 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
813 | { | |
814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
815 | u32 reg = PIPEDSL(pipe); | |
816 | u32 line1, line2; | |
817 | u32 line_mask; | |
818 | ||
819 | if (IS_GEN2(dev)) | |
820 | line_mask = DSL_LINEMASK_GEN2; | |
821 | else | |
822 | line_mask = DSL_LINEMASK_GEN3; | |
823 | ||
824 | line1 = I915_READ(reg) & line_mask; | |
825 | mdelay(5); | |
826 | line2 = I915_READ(reg) & line_mask; | |
827 | ||
828 | return line1 == line2; | |
829 | } | |
830 | ||
ab7ad7f6 KP |
831 | /* |
832 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
833 | * @dev: drm device |
834 | * @pipe: pipe to wait for | |
835 | * | |
836 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
837 | * spinning on the vblank interrupt status bit, since we won't actually | |
838 | * see an interrupt when the pipe is disabled. | |
839 | * | |
ab7ad7f6 KP |
840 | * On Gen4 and above: |
841 | * wait for the pipe register state bit to turn off | |
842 | * | |
843 | * Otherwise: | |
844 | * wait for the display line value to settle (it usually | |
845 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 846 | * |
9d0498a2 | 847 | */ |
58e10eb9 | 848 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
849 | { |
850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
851 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
852 | pipe); | |
ab7ad7f6 KP |
853 | |
854 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 855 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
856 | |
857 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
858 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
859 | 100)) | |
284637d9 | 860 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 861 | } else { |
ab7ad7f6 | 862 | /* Wait for the display line to settle */ |
fbf49ea2 | 863 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 864 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 865 | } |
79e53945 JB |
866 | } |
867 | ||
b0ea7d37 DL |
868 | /* |
869 | * ibx_digital_port_connected - is the specified port connected? | |
870 | * @dev_priv: i915 private structure | |
871 | * @port: the port to test | |
872 | * | |
873 | * Returns true if @port is connected, false otherwise. | |
874 | */ | |
875 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
876 | struct intel_digital_port *port) | |
877 | { | |
878 | u32 bit; | |
879 | ||
c36346e3 DL |
880 | if (HAS_PCH_IBX(dev_priv->dev)) { |
881 | switch(port->port) { | |
882 | case PORT_B: | |
883 | bit = SDE_PORTB_HOTPLUG; | |
884 | break; | |
885 | case PORT_C: | |
886 | bit = SDE_PORTC_HOTPLUG; | |
887 | break; | |
888 | case PORT_D: | |
889 | bit = SDE_PORTD_HOTPLUG; | |
890 | break; | |
891 | default: | |
892 | return true; | |
893 | } | |
894 | } else { | |
895 | switch(port->port) { | |
896 | case PORT_B: | |
897 | bit = SDE_PORTB_HOTPLUG_CPT; | |
898 | break; | |
899 | case PORT_C: | |
900 | bit = SDE_PORTC_HOTPLUG_CPT; | |
901 | break; | |
902 | case PORT_D: | |
903 | bit = SDE_PORTD_HOTPLUG_CPT; | |
904 | break; | |
905 | default: | |
906 | return true; | |
907 | } | |
b0ea7d37 DL |
908 | } |
909 | ||
910 | return I915_READ(SDEISR) & bit; | |
911 | } | |
912 | ||
b24e7179 JB |
913 | static const char *state_string(bool enabled) |
914 | { | |
915 | return enabled ? "on" : "off"; | |
916 | } | |
917 | ||
918 | /* Only for pre-ILK configs */ | |
55607e8a DV |
919 | void assert_pll(struct drm_i915_private *dev_priv, |
920 | enum pipe pipe, bool state) | |
b24e7179 JB |
921 | { |
922 | int reg; | |
923 | u32 val; | |
924 | bool cur_state; | |
925 | ||
926 | reg = DPLL(pipe); | |
927 | val = I915_READ(reg); | |
928 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
929 | WARN(cur_state != state, | |
930 | "PLL state assertion failure (expected %s, current %s)\n", | |
931 | state_string(state), state_string(cur_state)); | |
932 | } | |
b24e7179 | 933 | |
23538ef1 JN |
934 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
935 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
936 | { | |
937 | u32 val; | |
938 | bool cur_state; | |
939 | ||
940 | mutex_lock(&dev_priv->dpio_lock); | |
941 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
942 | mutex_unlock(&dev_priv->dpio_lock); | |
943 | ||
944 | cur_state = val & DSI_PLL_VCO_EN; | |
945 | WARN(cur_state != state, | |
946 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
947 | state_string(state), state_string(cur_state)); | |
948 | } | |
949 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
950 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
951 | ||
55607e8a | 952 | struct intel_shared_dpll * |
e2b78267 DV |
953 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
954 | { | |
955 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
956 | ||
a43f6e0f | 957 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
958 | return NULL; |
959 | ||
a43f6e0f | 960 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
961 | } |
962 | ||
040484af | 963 | /* For ILK+ */ |
55607e8a DV |
964 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
965 | struct intel_shared_dpll *pll, | |
966 | bool state) | |
040484af | 967 | { |
040484af | 968 | bool cur_state; |
5358901f | 969 | struct intel_dpll_hw_state hw_state; |
040484af | 970 | |
9d82aa17 ED |
971 | if (HAS_PCH_LPT(dev_priv->dev)) { |
972 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
973 | return; | |
974 | } | |
975 | ||
92b27b08 | 976 | if (WARN (!pll, |
46edb027 | 977 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 978 | return; |
ee7b9f93 | 979 | |
5358901f | 980 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 981 | WARN(cur_state != state, |
5358901f DV |
982 | "%s assertion failure (expected %s, current %s)\n", |
983 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 984 | } |
040484af JB |
985 | |
986 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
987 | enum pipe pipe, bool state) | |
988 | { | |
989 | int reg; | |
990 | u32 val; | |
991 | bool cur_state; | |
ad80a810 PZ |
992 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
993 | pipe); | |
040484af | 994 | |
affa9354 PZ |
995 | if (HAS_DDI(dev_priv->dev)) { |
996 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 997 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 998 | val = I915_READ(reg); |
ad80a810 | 999 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1000 | } else { |
1001 | reg = FDI_TX_CTL(pipe); | |
1002 | val = I915_READ(reg); | |
1003 | cur_state = !!(val & FDI_TX_ENABLE); | |
1004 | } | |
040484af JB |
1005 | WARN(cur_state != state, |
1006 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1007 | state_string(state), state_string(cur_state)); | |
1008 | } | |
1009 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1010 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1011 | ||
1012 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1013 | enum pipe pipe, bool state) | |
1014 | { | |
1015 | int reg; | |
1016 | u32 val; | |
1017 | bool cur_state; | |
1018 | ||
d63fa0dc PZ |
1019 | reg = FDI_RX_CTL(pipe); |
1020 | val = I915_READ(reg); | |
1021 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1022 | WARN(cur_state != state, |
1023 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1024 | state_string(state), state_string(cur_state)); | |
1025 | } | |
1026 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1027 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1028 | ||
1029 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1030 | enum pipe pipe) | |
1031 | { | |
1032 | int reg; | |
1033 | u32 val; | |
1034 | ||
1035 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1036 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1037 | return; |
1038 | ||
bf507ef7 | 1039 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1040 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1041 | return; |
1042 | ||
040484af JB |
1043 | reg = FDI_TX_CTL(pipe); |
1044 | val = I915_READ(reg); | |
1045 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1046 | } | |
1047 | ||
55607e8a DV |
1048 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1049 | enum pipe pipe, bool state) | |
040484af JB |
1050 | { |
1051 | int reg; | |
1052 | u32 val; | |
55607e8a | 1053 | bool cur_state; |
040484af JB |
1054 | |
1055 | reg = FDI_RX_CTL(pipe); | |
1056 | val = I915_READ(reg); | |
55607e8a DV |
1057 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1058 | WARN(cur_state != state, | |
1059 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1060 | state_string(state), state_string(cur_state)); | |
040484af JB |
1061 | } |
1062 | ||
ea0760cf JB |
1063 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1064 | enum pipe pipe) | |
1065 | { | |
1066 | int pp_reg, lvds_reg; | |
1067 | u32 val; | |
1068 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1069 | bool locked = true; |
ea0760cf JB |
1070 | |
1071 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1072 | pp_reg = PCH_PP_CONTROL; | |
1073 | lvds_reg = PCH_LVDS; | |
1074 | } else { | |
1075 | pp_reg = PP_CONTROL; | |
1076 | lvds_reg = LVDS; | |
1077 | } | |
1078 | ||
1079 | val = I915_READ(pp_reg); | |
1080 | if (!(val & PANEL_POWER_ON) || | |
1081 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1082 | locked = false; | |
1083 | ||
1084 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1085 | panel_pipe = PIPE_B; | |
1086 | ||
1087 | WARN(panel_pipe == pipe && locked, | |
1088 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1089 | pipe_name(pipe)); |
ea0760cf JB |
1090 | } |
1091 | ||
93ce0ba6 JN |
1092 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1093 | enum pipe pipe, bool state) | |
1094 | { | |
1095 | struct drm_device *dev = dev_priv->dev; | |
1096 | bool cur_state; | |
1097 | ||
1098 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1099 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1100 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1101 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1102 | else | |
1103 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1104 | ||
1105 | WARN(cur_state != state, | |
1106 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1107 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1108 | } | |
1109 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1110 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1111 | ||
b840d907 JB |
1112 | void assert_pipe(struct drm_i915_private *dev_priv, |
1113 | enum pipe pipe, bool state) | |
b24e7179 JB |
1114 | { |
1115 | int reg; | |
1116 | u32 val; | |
63d7bbe9 | 1117 | bool cur_state; |
702e7a56 PZ |
1118 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1119 | pipe); | |
b24e7179 | 1120 | |
8e636784 DV |
1121 | /* if we need the pipe A quirk it must be always on */ |
1122 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1123 | state = true; | |
1124 | ||
da7e29bd | 1125 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1126 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1127 | cur_state = false; |
1128 | } else { | |
1129 | reg = PIPECONF(cpu_transcoder); | |
1130 | val = I915_READ(reg); | |
1131 | cur_state = !!(val & PIPECONF_ENABLE); | |
1132 | } | |
1133 | ||
63d7bbe9 JB |
1134 | WARN(cur_state != state, |
1135 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1136 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1137 | } |
1138 | ||
931872fc CW |
1139 | static void assert_plane(struct drm_i915_private *dev_priv, |
1140 | enum plane plane, bool state) | |
b24e7179 JB |
1141 | { |
1142 | int reg; | |
1143 | u32 val; | |
931872fc | 1144 | bool cur_state; |
b24e7179 JB |
1145 | |
1146 | reg = DSPCNTR(plane); | |
1147 | val = I915_READ(reg); | |
931872fc CW |
1148 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1149 | WARN(cur_state != state, | |
1150 | "plane %c assertion failure (expected %s, current %s)\n", | |
1151 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1152 | } |
1153 | ||
931872fc CW |
1154 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1155 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1156 | ||
b24e7179 JB |
1157 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1158 | enum pipe pipe) | |
1159 | { | |
653e1026 | 1160 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1161 | int reg, i; |
1162 | u32 val; | |
1163 | int cur_pipe; | |
1164 | ||
653e1026 VS |
1165 | /* Primary planes are fixed to pipes on gen4+ */ |
1166 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1167 | reg = DSPCNTR(pipe); |
1168 | val = I915_READ(reg); | |
1169 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1170 | "plane %c assertion failure, should be disabled but not\n", | |
1171 | plane_name(pipe)); | |
19ec1358 | 1172 | return; |
28c05794 | 1173 | } |
19ec1358 | 1174 | |
b24e7179 | 1175 | /* Need to check both planes against the pipe */ |
08e2a7de | 1176 | for_each_pipe(i) { |
b24e7179 JB |
1177 | reg = DSPCNTR(i); |
1178 | val = I915_READ(reg); | |
1179 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1180 | DISPPLANE_SEL_PIPE_SHIFT; | |
1181 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1182 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1183 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1184 | } |
1185 | } | |
1186 | ||
19332d7a JB |
1187 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1188 | enum pipe pipe) | |
1189 | { | |
20674eef | 1190 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1191 | int reg, sprite; |
19332d7a JB |
1192 | u32 val; |
1193 | ||
20674eef | 1194 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1195 | for_each_sprite(pipe, sprite) { |
1196 | reg = SPCNTR(pipe, sprite); | |
20674eef VS |
1197 | val = I915_READ(reg); |
1198 | WARN((val & SP_ENABLE), | |
1199 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1fe47785 | 1200 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1201 | } |
1202 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1203 | reg = SPRCTL(pipe); | |
19332d7a | 1204 | val = I915_READ(reg); |
20674eef | 1205 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1206 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1207 | plane_name(pipe), pipe_name(pipe)); |
1208 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1209 | reg = DVSCNTR(pipe); | |
19332d7a | 1210 | val = I915_READ(reg); |
20674eef | 1211 | WARN((val & DVS_ENABLE), |
06da8da2 | 1212 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1213 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1214 | } |
1215 | } | |
1216 | ||
89eff4be | 1217 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1218 | { |
1219 | u32 val; | |
1220 | bool enabled; | |
1221 | ||
89eff4be | 1222 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1223 | |
92f2584a JB |
1224 | val = I915_READ(PCH_DREF_CONTROL); |
1225 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1226 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1227 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1228 | } | |
1229 | ||
ab9412ba DV |
1230 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe) | |
92f2584a JB |
1232 | { |
1233 | int reg; | |
1234 | u32 val; | |
1235 | bool enabled; | |
1236 | ||
ab9412ba | 1237 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1238 | val = I915_READ(reg); |
1239 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1240 | WARN(enabled, |
1241 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1242 | pipe_name(pipe)); | |
92f2584a JB |
1243 | } |
1244 | ||
4e634389 KP |
1245 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1247 | { |
1248 | if ((val & DP_PORT_EN) == 0) | |
1249 | return false; | |
1250 | ||
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1252 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1253 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1254 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1255 | return false; | |
1256 | } else { | |
1257 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1258 | return false; | |
1259 | } | |
1260 | return true; | |
1261 | } | |
1262 | ||
1519b995 KP |
1263 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1264 | enum pipe pipe, u32 val) | |
1265 | { | |
dc0fa718 | 1266 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1267 | return false; |
1268 | ||
1269 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1270 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1271 | return false; |
1272 | } else { | |
dc0fa718 | 1273 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1274 | return false; |
1275 | } | |
1276 | return true; | |
1277 | } | |
1278 | ||
1279 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1280 | enum pipe pipe, u32 val) | |
1281 | { | |
1282 | if ((val & LVDS_PORT_EN) == 0) | |
1283 | return false; | |
1284 | ||
1285 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1286 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1287 | return false; | |
1288 | } else { | |
1289 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1290 | return false; | |
1291 | } | |
1292 | return true; | |
1293 | } | |
1294 | ||
1295 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1296 | enum pipe pipe, u32 val) | |
1297 | { | |
1298 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1299 | return false; | |
1300 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1301 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1302 | return false; | |
1303 | } else { | |
1304 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1305 | return false; | |
1306 | } | |
1307 | return true; | |
1308 | } | |
1309 | ||
291906f1 | 1310 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1311 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1312 | { |
47a05eca | 1313 | u32 val = I915_READ(reg); |
4e634389 | 1314 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1315 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1316 | reg, pipe_name(pipe)); |
de9a35ab | 1317 | |
75c5da27 DV |
1318 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1319 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1320 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1321 | } |
1322 | ||
1323 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1324 | enum pipe pipe, int reg) | |
1325 | { | |
47a05eca | 1326 | u32 val = I915_READ(reg); |
b70ad586 | 1327 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1328 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1329 | reg, pipe_name(pipe)); |
de9a35ab | 1330 | |
dc0fa718 | 1331 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1332 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1333 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1334 | } |
1335 | ||
1336 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1337 | enum pipe pipe) | |
1338 | { | |
1339 | int reg; | |
1340 | u32 val; | |
291906f1 | 1341 | |
f0575e92 KP |
1342 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1343 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1344 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1345 | |
1346 | reg = PCH_ADPA; | |
1347 | val = I915_READ(reg); | |
b70ad586 | 1348 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1349 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1350 | pipe_name(pipe)); |
291906f1 JB |
1351 | |
1352 | reg = PCH_LVDS; | |
1353 | val = I915_READ(reg); | |
b70ad586 | 1354 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1355 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1356 | pipe_name(pipe)); |
291906f1 | 1357 | |
e2debe91 PZ |
1358 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1359 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1360 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1361 | } |
1362 | ||
40e9cf64 JB |
1363 | static void intel_init_dpio(struct drm_device *dev) |
1364 | { | |
1365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1366 | ||
1367 | if (!IS_VALLEYVIEW(dev)) | |
1368 | return; | |
1369 | ||
e4607fcf | 1370 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
5382f5f3 JB |
1371 | } |
1372 | ||
1373 | static void intel_reset_dpio(struct drm_device *dev) | |
1374 | { | |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1376 | ||
1377 | if (!IS_VALLEYVIEW(dev)) | |
1378 | return; | |
1379 | ||
e5cbfbfb ID |
1380 | /* |
1381 | * Enable the CRI clock source so we can get at the display and the | |
1382 | * reference clock for VGA hotplug / manual detection. | |
1383 | */ | |
404faabc | 1384 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1385 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1386 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1387 | ||
40e9cf64 JB |
1388 | /* |
1389 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1390 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1391 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1392 | * b. The other bits such as sfr settings / modesel may all be set | |
1393 | * to 0. | |
1394 | * | |
1395 | * This should only be done on init and resume from S3 with both | |
1396 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1397 | */ | |
1398 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1399 | } | |
1400 | ||
426115cf | 1401 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1402 | { |
426115cf DV |
1403 | struct drm_device *dev = crtc->base.dev; |
1404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1405 | int reg = DPLL(crtc->pipe); | |
1406 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1407 | |
426115cf | 1408 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1409 | |
1410 | /* No really, not for ILK+ */ | |
1411 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1412 | ||
1413 | /* PLL is protected by panel, make sure we can write it */ | |
1414 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1415 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1416 | |
426115cf DV |
1417 | I915_WRITE(reg, dpll); |
1418 | POSTING_READ(reg); | |
1419 | udelay(150); | |
1420 | ||
1421 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1422 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1423 | ||
1424 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1425 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1426 | |
1427 | /* We do this three times for luck */ | |
426115cf | 1428 | I915_WRITE(reg, dpll); |
87442f73 DV |
1429 | POSTING_READ(reg); |
1430 | udelay(150); /* wait for warmup */ | |
426115cf | 1431 | I915_WRITE(reg, dpll); |
87442f73 DV |
1432 | POSTING_READ(reg); |
1433 | udelay(150); /* wait for warmup */ | |
426115cf | 1434 | I915_WRITE(reg, dpll); |
87442f73 DV |
1435 | POSTING_READ(reg); |
1436 | udelay(150); /* wait for warmup */ | |
1437 | } | |
1438 | ||
66e3d5c0 | 1439 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1440 | { |
66e3d5c0 DV |
1441 | struct drm_device *dev = crtc->base.dev; |
1442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1443 | int reg = DPLL(crtc->pipe); | |
1444 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1445 | |
66e3d5c0 | 1446 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1447 | |
63d7bbe9 | 1448 | /* No really, not for ILK+ */ |
3d13ef2e | 1449 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1450 | |
1451 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1452 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1453 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1454 | |
66e3d5c0 DV |
1455 | I915_WRITE(reg, dpll); |
1456 | ||
1457 | /* Wait for the clocks to stabilize. */ | |
1458 | POSTING_READ(reg); | |
1459 | udelay(150); | |
1460 | ||
1461 | if (INTEL_INFO(dev)->gen >= 4) { | |
1462 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1463 | crtc->config.dpll_hw_state.dpll_md); | |
1464 | } else { | |
1465 | /* The pixel multiplier can only be updated once the | |
1466 | * DPLL is enabled and the clocks are stable. | |
1467 | * | |
1468 | * So write it again. | |
1469 | */ | |
1470 | I915_WRITE(reg, dpll); | |
1471 | } | |
63d7bbe9 JB |
1472 | |
1473 | /* We do this three times for luck */ | |
66e3d5c0 | 1474 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1475 | POSTING_READ(reg); |
1476 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1477 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1478 | POSTING_READ(reg); |
1479 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1480 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1481 | POSTING_READ(reg); |
1482 | udelay(150); /* wait for warmup */ | |
1483 | } | |
1484 | ||
1485 | /** | |
50b44a44 | 1486 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1487 | * @dev_priv: i915 private structure |
1488 | * @pipe: pipe PLL to disable | |
1489 | * | |
1490 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1491 | * | |
1492 | * Note! This is for pre-ILK only. | |
1493 | */ | |
50b44a44 | 1494 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1495 | { |
63d7bbe9 JB |
1496 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1497 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1498 | return; | |
1499 | ||
1500 | /* Make sure the pipe isn't still relying on us */ | |
1501 | assert_pipe_disabled(dev_priv, pipe); | |
1502 | ||
50b44a44 DV |
1503 | I915_WRITE(DPLL(pipe), 0); |
1504 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1505 | } |
1506 | ||
f6071166 JB |
1507 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1508 | { | |
1509 | u32 val = 0; | |
1510 | ||
1511 | /* Make sure the pipe isn't still relying on us */ | |
1512 | assert_pipe_disabled(dev_priv, pipe); | |
1513 | ||
e5cbfbfb ID |
1514 | /* |
1515 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1516 | * The latter is needed for VGA hotplug / manual detection. | |
1517 | */ | |
f6071166 | 1518 | if (pipe == PIPE_B) |
e5cbfbfb | 1519 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1520 | I915_WRITE(DPLL(pipe), val); |
1521 | POSTING_READ(DPLL(pipe)); | |
1522 | } | |
1523 | ||
e4607fcf CML |
1524 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1525 | struct intel_digital_port *dport) | |
89b667f8 JB |
1526 | { |
1527 | u32 port_mask; | |
1528 | ||
e4607fcf CML |
1529 | switch (dport->port) { |
1530 | case PORT_B: | |
89b667f8 | 1531 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1532 | break; |
1533 | case PORT_C: | |
89b667f8 | 1534 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1535 | break; |
1536 | default: | |
1537 | BUG(); | |
1538 | } | |
89b667f8 JB |
1539 | |
1540 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1541 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
be46ffd4 | 1542 | port_name(dport->port), I915_READ(DPLL(0))); |
89b667f8 JB |
1543 | } |
1544 | ||
92f2584a | 1545 | /** |
e72f9fbf | 1546 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1547 | * @dev_priv: i915 private structure |
1548 | * @pipe: pipe PLL to enable | |
1549 | * | |
1550 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1551 | * drives the transcoder clock. | |
1552 | */ | |
e2b78267 | 1553 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1554 | { |
3d13ef2e DL |
1555 | struct drm_device *dev = crtc->base.dev; |
1556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1557 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1558 | |
48da64a8 | 1559 | /* PCH PLLs only available on ILK, SNB and IVB */ |
3d13ef2e | 1560 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1561 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1562 | return; |
1563 | ||
1564 | if (WARN_ON(pll->refcount == 0)) | |
1565 | return; | |
ee7b9f93 | 1566 | |
46edb027 DV |
1567 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1568 | pll->name, pll->active, pll->on, | |
e2b78267 | 1569 | crtc->base.base.id); |
92f2584a | 1570 | |
cdbd2316 DV |
1571 | if (pll->active++) { |
1572 | WARN_ON(!pll->on); | |
e9d6944e | 1573 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1574 | return; |
1575 | } | |
f4a091c7 | 1576 | WARN_ON(pll->on); |
ee7b9f93 | 1577 | |
46edb027 | 1578 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1579 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1580 | pll->on = true; |
92f2584a JB |
1581 | } |
1582 | ||
e2b78267 | 1583 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1584 | { |
3d13ef2e DL |
1585 | struct drm_device *dev = crtc->base.dev; |
1586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1587 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1588 | |
92f2584a | 1589 | /* PCH only available on ILK+ */ |
3d13ef2e | 1590 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1591 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1592 | return; |
92f2584a | 1593 | |
48da64a8 CW |
1594 | if (WARN_ON(pll->refcount == 0)) |
1595 | return; | |
7a419866 | 1596 | |
46edb027 DV |
1597 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1598 | pll->name, pll->active, pll->on, | |
e2b78267 | 1599 | crtc->base.base.id); |
7a419866 | 1600 | |
48da64a8 | 1601 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1602 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1603 | return; |
1604 | } | |
1605 | ||
e9d6944e | 1606 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1607 | WARN_ON(!pll->on); |
cdbd2316 | 1608 | if (--pll->active) |
7a419866 | 1609 | return; |
ee7b9f93 | 1610 | |
46edb027 | 1611 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1612 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1613 | pll->on = false; |
92f2584a JB |
1614 | } |
1615 | ||
b8a4f404 PZ |
1616 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1617 | enum pipe pipe) | |
040484af | 1618 | { |
23670b32 | 1619 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1620 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1622 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1623 | |
1624 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1625 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1626 | |
1627 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1628 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1629 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1630 | |
1631 | /* FDI must be feeding us bits for PCH ports */ | |
1632 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1633 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1634 | ||
23670b32 DV |
1635 | if (HAS_PCH_CPT(dev)) { |
1636 | /* Workaround: Set the timing override bit before enabling the | |
1637 | * pch transcoder. */ | |
1638 | reg = TRANS_CHICKEN2(pipe); | |
1639 | val = I915_READ(reg); | |
1640 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1641 | I915_WRITE(reg, val); | |
59c859d6 | 1642 | } |
23670b32 | 1643 | |
ab9412ba | 1644 | reg = PCH_TRANSCONF(pipe); |
040484af | 1645 | val = I915_READ(reg); |
5f7f726d | 1646 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1647 | |
1648 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1649 | /* | |
1650 | * make the BPC in transcoder be consistent with | |
1651 | * that in pipeconf reg. | |
1652 | */ | |
dfd07d72 DV |
1653 | val &= ~PIPECONF_BPC_MASK; |
1654 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1655 | } |
5f7f726d PZ |
1656 | |
1657 | val &= ~TRANS_INTERLACE_MASK; | |
1658 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1659 | if (HAS_PCH_IBX(dev_priv->dev) && |
1660 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1661 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1662 | else | |
1663 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1664 | else |
1665 | val |= TRANS_PROGRESSIVE; | |
1666 | ||
040484af JB |
1667 | I915_WRITE(reg, val | TRANS_ENABLE); |
1668 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1669 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1670 | } |
1671 | ||
8fb033d7 | 1672 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1673 | enum transcoder cpu_transcoder) |
040484af | 1674 | { |
8fb033d7 | 1675 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1676 | |
1677 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1678 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1679 | |
8fb033d7 | 1680 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1681 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1682 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1683 | |
223a6fdf PZ |
1684 | /* Workaround: set timing override bit. */ |
1685 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1686 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1687 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1688 | ||
25f3ef11 | 1689 | val = TRANS_ENABLE; |
937bb610 | 1690 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1691 | |
9a76b1c6 PZ |
1692 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1693 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1694 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1695 | else |
1696 | val |= TRANS_PROGRESSIVE; | |
1697 | ||
ab9412ba DV |
1698 | I915_WRITE(LPT_TRANSCONF, val); |
1699 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1700 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1701 | } |
1702 | ||
b8a4f404 PZ |
1703 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1704 | enum pipe pipe) | |
040484af | 1705 | { |
23670b32 DV |
1706 | struct drm_device *dev = dev_priv->dev; |
1707 | uint32_t reg, val; | |
040484af JB |
1708 | |
1709 | /* FDI relies on the transcoder */ | |
1710 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1711 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1712 | ||
291906f1 JB |
1713 | /* Ports must be off as well */ |
1714 | assert_pch_ports_disabled(dev_priv, pipe); | |
1715 | ||
ab9412ba | 1716 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1717 | val = I915_READ(reg); |
1718 | val &= ~TRANS_ENABLE; | |
1719 | I915_WRITE(reg, val); | |
1720 | /* wait for PCH transcoder off, transcoder state */ | |
1721 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1722 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1723 | |
1724 | if (!HAS_PCH_IBX(dev)) { | |
1725 | /* Workaround: Clear the timing override chicken bit again. */ | |
1726 | reg = TRANS_CHICKEN2(pipe); | |
1727 | val = I915_READ(reg); | |
1728 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1729 | I915_WRITE(reg, val); | |
1730 | } | |
040484af JB |
1731 | } |
1732 | ||
ab4d966c | 1733 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1734 | { |
8fb033d7 PZ |
1735 | u32 val; |
1736 | ||
ab9412ba | 1737 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1738 | val &= ~TRANS_ENABLE; |
ab9412ba | 1739 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1740 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1741 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1742 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1743 | |
1744 | /* Workaround: clear timing override bit. */ | |
1745 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1746 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1747 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1748 | } |
1749 | ||
b24e7179 | 1750 | /** |
309cfea8 | 1751 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1752 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1753 | * |
0372264a | 1754 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1755 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1756 | */ |
e1fdc473 | 1757 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1758 | { |
0372264a PZ |
1759 | struct drm_device *dev = crtc->base.dev; |
1760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1761 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1762 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1763 | pipe); | |
1a240d4d | 1764 | enum pipe pch_transcoder; |
b24e7179 JB |
1765 | int reg; |
1766 | u32 val; | |
1767 | ||
58c6eaa2 | 1768 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1769 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1770 | assert_sprites_disabled(dev_priv, pipe); |
1771 | ||
681e5811 | 1772 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1773 | pch_transcoder = TRANSCODER_A; |
1774 | else | |
1775 | pch_transcoder = pipe; | |
1776 | ||
b24e7179 JB |
1777 | /* |
1778 | * A pipe without a PLL won't actually be able to drive bits from | |
1779 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1780 | * need the check. | |
1781 | */ | |
1782 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 1783 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1784 | assert_dsi_pll_enabled(dev_priv); |
1785 | else | |
1786 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1787 | else { |
30421c4f | 1788 | if (crtc->config.has_pch_encoder) { |
040484af | 1789 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1790 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1791 | assert_fdi_tx_pll_enabled(dev_priv, |
1792 | (enum pipe) cpu_transcoder); | |
040484af JB |
1793 | } |
1794 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1795 | } | |
b24e7179 | 1796 | |
702e7a56 | 1797 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1798 | val = I915_READ(reg); |
7ad25d48 PZ |
1799 | if (val & PIPECONF_ENABLE) { |
1800 | WARN_ON(!(pipe == PIPE_A && | |
1801 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 1802 | return; |
7ad25d48 | 1803 | } |
00d70b15 CW |
1804 | |
1805 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1806 | POSTING_READ(reg); |
e1fdc473 PZ |
1807 | |
1808 | /* | |
1809 | * There's no guarantee the pipe will really start running now. It | |
1810 | * depends on the Gen, the output type and the relative order between | |
1811 | * pipe and plane enabling. Avoid waiting on HSW+ since it's not | |
1812 | * necessary. | |
1813 | * TODO: audit the previous gens. | |
1814 | */ | |
1815 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) | |
851855d8 | 1816 | intel_wait_for_vblank(dev_priv->dev, pipe); |
b24e7179 JB |
1817 | } |
1818 | ||
1819 | /** | |
309cfea8 | 1820 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1821 | * @dev_priv: i915 private structure |
1822 | * @pipe: pipe to disable | |
1823 | * | |
1824 | * Disable @pipe, making sure that various hardware specific requirements | |
1825 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1826 | * | |
1827 | * @pipe should be %PIPE_A or %PIPE_B. | |
1828 | * | |
1829 | * Will wait until the pipe has shut down before returning. | |
1830 | */ | |
1831 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1832 | enum pipe pipe) | |
1833 | { | |
702e7a56 PZ |
1834 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1835 | pipe); | |
b24e7179 JB |
1836 | int reg; |
1837 | u32 val; | |
1838 | ||
1839 | /* | |
1840 | * Make sure planes won't keep trying to pump pixels to us, | |
1841 | * or we might hang the display. | |
1842 | */ | |
1843 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1844 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1845 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1846 | |
1847 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1848 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1849 | return; | |
1850 | ||
702e7a56 | 1851 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1852 | val = I915_READ(reg); |
00d70b15 CW |
1853 | if ((val & PIPECONF_ENABLE) == 0) |
1854 | return; | |
1855 | ||
1856 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1857 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1858 | } | |
1859 | ||
d74362c9 KP |
1860 | /* |
1861 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1862 | * trigger in order to latch. The display address reg provides this. | |
1863 | */ | |
1dba99f4 VS |
1864 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1865 | enum plane plane) | |
d74362c9 | 1866 | { |
3d13ef2e DL |
1867 | struct drm_device *dev = dev_priv->dev; |
1868 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
1869 | |
1870 | I915_WRITE(reg, I915_READ(reg)); | |
1871 | POSTING_READ(reg); | |
d74362c9 KP |
1872 | } |
1873 | ||
b24e7179 | 1874 | /** |
d1de00ef | 1875 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1876 | * @dev_priv: i915 private structure |
1877 | * @plane: plane to enable | |
1878 | * @pipe: pipe being fed | |
1879 | * | |
1880 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1881 | */ | |
d1de00ef VS |
1882 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1883 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1884 | { |
939c2fe8 VS |
1885 | struct intel_crtc *intel_crtc = |
1886 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1887 | int reg; |
1888 | u32 val; | |
1889 | ||
1890 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1891 | assert_pipe_enabled(dev_priv, pipe); | |
1892 | ||
4c445e0e | 1893 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1894 | |
4c445e0e | 1895 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1896 | |
b24e7179 JB |
1897 | reg = DSPCNTR(plane); |
1898 | val = I915_READ(reg); | |
00d70b15 CW |
1899 | if (val & DISPLAY_PLANE_ENABLE) |
1900 | return; | |
1901 | ||
1902 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1903 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1904 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1905 | } | |
1906 | ||
b24e7179 | 1907 | /** |
d1de00ef | 1908 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1909 | * @dev_priv: i915 private structure |
1910 | * @plane: plane to disable | |
1911 | * @pipe: pipe consuming the data | |
1912 | * | |
1913 | * Disable @plane; should be an independent operation. | |
1914 | */ | |
d1de00ef VS |
1915 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1916 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1917 | { |
939c2fe8 VS |
1918 | struct intel_crtc *intel_crtc = |
1919 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1920 | int reg; |
1921 | u32 val; | |
1922 | ||
4c445e0e | 1923 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1924 | |
4c445e0e | 1925 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1926 | |
b24e7179 JB |
1927 | reg = DSPCNTR(plane); |
1928 | val = I915_READ(reg); | |
00d70b15 CW |
1929 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1930 | return; | |
1931 | ||
1932 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1933 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1934 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1935 | } | |
1936 | ||
693db184 CW |
1937 | static bool need_vtd_wa(struct drm_device *dev) |
1938 | { | |
1939 | #ifdef CONFIG_INTEL_IOMMU | |
1940 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1941 | return true; | |
1942 | #endif | |
1943 | return false; | |
1944 | } | |
1945 | ||
a57ce0b2 JB |
1946 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
1947 | { | |
1948 | int tile_height; | |
1949 | ||
1950 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
1951 | return ALIGN(height, tile_height); | |
1952 | } | |
1953 | ||
127bd2ac | 1954 | int |
48b956c5 | 1955 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1956 | struct drm_i915_gem_object *obj, |
919926ae | 1957 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1958 | { |
ce453d81 | 1959 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1960 | u32 alignment; |
1961 | int ret; | |
1962 | ||
05394f39 | 1963 | switch (obj->tiling_mode) { |
6b95a207 | 1964 | case I915_TILING_NONE: |
534843da CW |
1965 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1966 | alignment = 128 * 1024; | |
a6c45cf0 | 1967 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1968 | alignment = 4 * 1024; |
1969 | else | |
1970 | alignment = 64 * 1024; | |
6b95a207 KH |
1971 | break; |
1972 | case I915_TILING_X: | |
1973 | /* pin() will align the object as required by fence */ | |
1974 | alignment = 0; | |
1975 | break; | |
1976 | case I915_TILING_Y: | |
80075d49 | 1977 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1978 | return -EINVAL; |
1979 | default: | |
1980 | BUG(); | |
1981 | } | |
1982 | ||
693db184 CW |
1983 | /* Note that the w/a also requires 64 PTE of padding following the |
1984 | * bo. We currently fill all unused PTE with the shadow page and so | |
1985 | * we should always have valid PTE following the scanout preventing | |
1986 | * the VT-d warning. | |
1987 | */ | |
1988 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1989 | alignment = 256 * 1024; | |
1990 | ||
ce453d81 | 1991 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1992 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1993 | if (ret) |
ce453d81 | 1994 | goto err_interruptible; |
6b95a207 KH |
1995 | |
1996 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1997 | * fence, whereas 965+ only requires a fence if using | |
1998 | * framebuffer compression. For simplicity, we always install | |
1999 | * a fence as the cost is not that onerous. | |
2000 | */ | |
06d98131 | 2001 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2002 | if (ret) |
2003 | goto err_unpin; | |
1690e1eb | 2004 | |
9a5a53b3 | 2005 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2006 | |
ce453d81 | 2007 | dev_priv->mm.interruptible = true; |
6b95a207 | 2008 | return 0; |
48b956c5 CW |
2009 | |
2010 | err_unpin: | |
cc98b413 | 2011 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2012 | err_interruptible: |
2013 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2014 | return ret; |
6b95a207 KH |
2015 | } |
2016 | ||
1690e1eb CW |
2017 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2018 | { | |
2019 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2020 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2021 | } |
2022 | ||
c2c75131 DV |
2023 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2024 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2025 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2026 | unsigned int tiling_mode, | |
2027 | unsigned int cpp, | |
2028 | unsigned int pitch) | |
c2c75131 | 2029 | { |
bc752862 CW |
2030 | if (tiling_mode != I915_TILING_NONE) { |
2031 | unsigned int tile_rows, tiles; | |
c2c75131 | 2032 | |
bc752862 CW |
2033 | tile_rows = *y / 8; |
2034 | *y %= 8; | |
c2c75131 | 2035 | |
bc752862 CW |
2036 | tiles = *x / (512/cpp); |
2037 | *x %= 512/cpp; | |
2038 | ||
2039 | return tile_rows * pitch * 8 + tiles * 4096; | |
2040 | } else { | |
2041 | unsigned int offset; | |
2042 | ||
2043 | offset = *y * pitch + *x * cpp; | |
2044 | *y = 0; | |
2045 | *x = (offset & 4095) / cpp; | |
2046 | return offset & -4096; | |
2047 | } | |
c2c75131 DV |
2048 | } |
2049 | ||
17638cd6 JB |
2050 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2051 | int x, int y) | |
81255565 JB |
2052 | { |
2053 | struct drm_device *dev = crtc->dev; | |
2054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2056 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2057 | struct drm_i915_gem_object *obj; |
81255565 | 2058 | int plane = intel_crtc->plane; |
e506a0c6 | 2059 | unsigned long linear_offset; |
81255565 | 2060 | u32 dspcntr; |
5eddb70b | 2061 | u32 reg; |
81255565 JB |
2062 | |
2063 | switch (plane) { | |
2064 | case 0: | |
2065 | case 1: | |
2066 | break; | |
2067 | default: | |
84f44ce7 | 2068 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2069 | return -EINVAL; |
2070 | } | |
2071 | ||
2072 | intel_fb = to_intel_framebuffer(fb); | |
2073 | obj = intel_fb->obj; | |
81255565 | 2074 | |
5eddb70b CW |
2075 | reg = DSPCNTR(plane); |
2076 | dspcntr = I915_READ(reg); | |
81255565 JB |
2077 | /* Mask out pixel format bits in case we change it */ |
2078 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2079 | switch (fb->pixel_format) { |
2080 | case DRM_FORMAT_C8: | |
81255565 JB |
2081 | dspcntr |= DISPPLANE_8BPP; |
2082 | break; | |
57779d06 VS |
2083 | case DRM_FORMAT_XRGB1555: |
2084 | case DRM_FORMAT_ARGB1555: | |
2085 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2086 | break; |
57779d06 VS |
2087 | case DRM_FORMAT_RGB565: |
2088 | dspcntr |= DISPPLANE_BGRX565; | |
2089 | break; | |
2090 | case DRM_FORMAT_XRGB8888: | |
2091 | case DRM_FORMAT_ARGB8888: | |
2092 | dspcntr |= DISPPLANE_BGRX888; | |
2093 | break; | |
2094 | case DRM_FORMAT_XBGR8888: | |
2095 | case DRM_FORMAT_ABGR8888: | |
2096 | dspcntr |= DISPPLANE_RGBX888; | |
2097 | break; | |
2098 | case DRM_FORMAT_XRGB2101010: | |
2099 | case DRM_FORMAT_ARGB2101010: | |
2100 | dspcntr |= DISPPLANE_BGRX101010; | |
2101 | break; | |
2102 | case DRM_FORMAT_XBGR2101010: | |
2103 | case DRM_FORMAT_ABGR2101010: | |
2104 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2105 | break; |
2106 | default: | |
baba133a | 2107 | BUG(); |
81255565 | 2108 | } |
57779d06 | 2109 | |
a6c45cf0 | 2110 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2111 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2112 | dspcntr |= DISPPLANE_TILED; |
2113 | else | |
2114 | dspcntr &= ~DISPPLANE_TILED; | |
2115 | } | |
2116 | ||
de1aa629 VS |
2117 | if (IS_G4X(dev)) |
2118 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2119 | ||
5eddb70b | 2120 | I915_WRITE(reg, dspcntr); |
81255565 | 2121 | |
e506a0c6 | 2122 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2123 | |
c2c75131 DV |
2124 | if (INTEL_INFO(dev)->gen >= 4) { |
2125 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2126 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2127 | fb->bits_per_pixel / 8, | |
2128 | fb->pitches[0]); | |
c2c75131 DV |
2129 | linear_offset -= intel_crtc->dspaddr_offset; |
2130 | } else { | |
e506a0c6 | 2131 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2132 | } |
e506a0c6 | 2133 | |
f343c5f6 BW |
2134 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2135 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2136 | fb->pitches[0]); | |
01f2c773 | 2137 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2138 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2139 | I915_WRITE(DSPSURF(plane), |
2140 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2141 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2142 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2143 | } else |
f343c5f6 | 2144 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2145 | POSTING_READ(reg); |
81255565 | 2146 | |
17638cd6 JB |
2147 | return 0; |
2148 | } | |
2149 | ||
2150 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2151 | struct drm_framebuffer *fb, int x, int y) | |
2152 | { | |
2153 | struct drm_device *dev = crtc->dev; | |
2154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2156 | struct intel_framebuffer *intel_fb; | |
2157 | struct drm_i915_gem_object *obj; | |
2158 | int plane = intel_crtc->plane; | |
e506a0c6 | 2159 | unsigned long linear_offset; |
17638cd6 JB |
2160 | u32 dspcntr; |
2161 | u32 reg; | |
2162 | ||
2163 | switch (plane) { | |
2164 | case 0: | |
2165 | case 1: | |
27f8227b | 2166 | case 2: |
17638cd6 JB |
2167 | break; |
2168 | default: | |
84f44ce7 | 2169 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2170 | return -EINVAL; |
2171 | } | |
2172 | ||
2173 | intel_fb = to_intel_framebuffer(fb); | |
2174 | obj = intel_fb->obj; | |
2175 | ||
2176 | reg = DSPCNTR(plane); | |
2177 | dspcntr = I915_READ(reg); | |
2178 | /* Mask out pixel format bits in case we change it */ | |
2179 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2180 | switch (fb->pixel_format) { |
2181 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2182 | dspcntr |= DISPPLANE_8BPP; |
2183 | break; | |
57779d06 VS |
2184 | case DRM_FORMAT_RGB565: |
2185 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2186 | break; |
57779d06 VS |
2187 | case DRM_FORMAT_XRGB8888: |
2188 | case DRM_FORMAT_ARGB8888: | |
2189 | dspcntr |= DISPPLANE_BGRX888; | |
2190 | break; | |
2191 | case DRM_FORMAT_XBGR8888: | |
2192 | case DRM_FORMAT_ABGR8888: | |
2193 | dspcntr |= DISPPLANE_RGBX888; | |
2194 | break; | |
2195 | case DRM_FORMAT_XRGB2101010: | |
2196 | case DRM_FORMAT_ARGB2101010: | |
2197 | dspcntr |= DISPPLANE_BGRX101010; | |
2198 | break; | |
2199 | case DRM_FORMAT_XBGR2101010: | |
2200 | case DRM_FORMAT_ABGR2101010: | |
2201 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2202 | break; |
2203 | default: | |
baba133a | 2204 | BUG(); |
17638cd6 JB |
2205 | } |
2206 | ||
2207 | if (obj->tiling_mode != I915_TILING_NONE) | |
2208 | dspcntr |= DISPPLANE_TILED; | |
2209 | else | |
2210 | dspcntr &= ~DISPPLANE_TILED; | |
2211 | ||
b42c6009 | 2212 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2213 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2214 | else | |
2215 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2216 | |
2217 | I915_WRITE(reg, dspcntr); | |
2218 | ||
e506a0c6 | 2219 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2220 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2221 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2222 | fb->bits_per_pixel / 8, | |
2223 | fb->pitches[0]); | |
c2c75131 | 2224 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2225 | |
f343c5f6 BW |
2226 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2227 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2228 | fb->pitches[0]); | |
01f2c773 | 2229 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2230 | I915_WRITE(DSPSURF(plane), |
2231 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2232 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2233 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2234 | } else { | |
2235 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2236 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2237 | } | |
17638cd6 JB |
2238 | POSTING_READ(reg); |
2239 | ||
2240 | return 0; | |
2241 | } | |
2242 | ||
2243 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2244 | static int | |
2245 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2246 | int x, int y, enum mode_set_atomic state) | |
2247 | { | |
2248 | struct drm_device *dev = crtc->dev; | |
2249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2250 | |
6b8e6ed0 CW |
2251 | if (dev_priv->display.disable_fbc) |
2252 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2253 | intel_increase_pllclock(crtc); |
81255565 | 2254 | |
6b8e6ed0 | 2255 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2256 | } |
2257 | ||
96a02917 VS |
2258 | void intel_display_handle_reset(struct drm_device *dev) |
2259 | { | |
2260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2261 | struct drm_crtc *crtc; | |
2262 | ||
2263 | /* | |
2264 | * Flips in the rings have been nuked by the reset, | |
2265 | * so complete all pending flips so that user space | |
2266 | * will get its events and not get stuck. | |
2267 | * | |
2268 | * Also update the base address of all primary | |
2269 | * planes to the the last fb to make sure we're | |
2270 | * showing the correct fb after a reset. | |
2271 | * | |
2272 | * Need to make two loops over the crtcs so that we | |
2273 | * don't try to grab a crtc mutex before the | |
2274 | * pending_flip_queue really got woken up. | |
2275 | */ | |
2276 | ||
2277 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2279 | enum plane plane = intel_crtc->plane; | |
2280 | ||
2281 | intel_prepare_page_flip(dev, plane); | |
2282 | intel_finish_page_flip_plane(dev, plane); | |
2283 | } | |
2284 | ||
2285 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2287 | ||
2288 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2289 | /* |
2290 | * FIXME: Once we have proper support for primary planes (and | |
2291 | * disabling them without disabling the entire crtc) allow again | |
2292 | * a NULL crtc->fb. | |
2293 | */ | |
2294 | if (intel_crtc->active && crtc->fb) | |
96a02917 VS |
2295 | dev_priv->display.update_plane(crtc, crtc->fb, |
2296 | crtc->x, crtc->y); | |
2297 | mutex_unlock(&crtc->mutex); | |
2298 | } | |
2299 | } | |
2300 | ||
14667a4b CW |
2301 | static int |
2302 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2303 | { | |
2304 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2305 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2306 | bool was_interruptible = dev_priv->mm.interruptible; | |
2307 | int ret; | |
2308 | ||
14667a4b CW |
2309 | /* Big Hammer, we also need to ensure that any pending |
2310 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2311 | * current scanout is retired before unpinning the old | |
2312 | * framebuffer. | |
2313 | * | |
2314 | * This should only fail upon a hung GPU, in which case we | |
2315 | * can safely continue. | |
2316 | */ | |
2317 | dev_priv->mm.interruptible = false; | |
2318 | ret = i915_gem_object_finish_gpu(obj); | |
2319 | dev_priv->mm.interruptible = was_interruptible; | |
2320 | ||
2321 | return ret; | |
2322 | } | |
2323 | ||
7d5e3799 CW |
2324 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2325 | { | |
2326 | struct drm_device *dev = crtc->dev; | |
2327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2329 | unsigned long flags; | |
2330 | bool pending; | |
2331 | ||
2332 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2333 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2334 | return false; | |
2335 | ||
2336 | spin_lock_irqsave(&dev->event_lock, flags); | |
2337 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2338 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2339 | ||
2340 | return pending; | |
2341 | } | |
2342 | ||
5c3b82e2 | 2343 | static int |
3c4fdcfb | 2344 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2345 | struct drm_framebuffer *fb) |
79e53945 JB |
2346 | { |
2347 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2348 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2350 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2351 | int ret; |
79e53945 | 2352 | |
7d5e3799 CW |
2353 | if (intel_crtc_has_pending_flip(crtc)) { |
2354 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2355 | return -EBUSY; | |
2356 | } | |
2357 | ||
79e53945 | 2358 | /* no fb bound */ |
94352cf9 | 2359 | if (!fb) { |
a5071c2f | 2360 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2361 | return 0; |
2362 | } | |
2363 | ||
7eb552ae | 2364 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2365 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2366 | plane_name(intel_crtc->plane), | |
2367 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2368 | return -EINVAL; |
79e53945 JB |
2369 | } |
2370 | ||
5c3b82e2 | 2371 | mutex_lock(&dev->struct_mutex); |
265db958 | 2372 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2373 | to_intel_framebuffer(fb)->obj, |
919926ae | 2374 | NULL); |
5c3b82e2 CW |
2375 | if (ret != 0) { |
2376 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2377 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2378 | return ret; |
2379 | } | |
79e53945 | 2380 | |
bb2043de DL |
2381 | /* |
2382 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2383 | * that in compute_mode_changes we check the native mode (not the pfit | |
2384 | * mode) to see if we can flip rather than do a full mode set. In the | |
2385 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2386 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2387 | * sized surface. | |
2388 | * | |
2389 | * To fix this properly, we need to hoist the checks up into | |
2390 | * compute_mode_changes (or above), check the actual pfit state and | |
2391 | * whether the platform allows pfit disable with pipe active, and only | |
2392 | * then update the pipesrc and pfit state, even on the flip path. | |
2393 | */ | |
d330a953 | 2394 | if (i915.fastboot) { |
d7bf63f2 DL |
2395 | const struct drm_display_mode *adjusted_mode = |
2396 | &intel_crtc->config.adjusted_mode; | |
2397 | ||
4d6a3e63 | 2398 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2399 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2400 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2401 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2402 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2403 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2404 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2405 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2406 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2407 | } | |
0637d60d JB |
2408 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2409 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2410 | } |
2411 | ||
94352cf9 | 2412 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2413 | if (ret) { |
94352cf9 | 2414 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2415 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2416 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2417 | return ret; |
79e53945 | 2418 | } |
3c4fdcfb | 2419 | |
94352cf9 DV |
2420 | old_fb = crtc->fb; |
2421 | crtc->fb = fb; | |
6c4c86f5 DV |
2422 | crtc->x = x; |
2423 | crtc->y = y; | |
94352cf9 | 2424 | |
b7f1de28 | 2425 | if (old_fb) { |
d7697eea DV |
2426 | if (intel_crtc->active && old_fb != fb) |
2427 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2428 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2429 | } |
652c393a | 2430 | |
6b8e6ed0 | 2431 | intel_update_fbc(dev); |
4906557e | 2432 | intel_edp_psr_update(dev); |
5c3b82e2 | 2433 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2434 | |
5c3b82e2 | 2435 | return 0; |
79e53945 JB |
2436 | } |
2437 | ||
5e84e1a4 ZW |
2438 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2439 | { | |
2440 | struct drm_device *dev = crtc->dev; | |
2441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2442 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2443 | int pipe = intel_crtc->pipe; | |
2444 | u32 reg, temp; | |
2445 | ||
2446 | /* enable normal train */ | |
2447 | reg = FDI_TX_CTL(pipe); | |
2448 | temp = I915_READ(reg); | |
61e499bf | 2449 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2450 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2451 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2452 | } else { |
2453 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2454 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2455 | } |
5e84e1a4 ZW |
2456 | I915_WRITE(reg, temp); |
2457 | ||
2458 | reg = FDI_RX_CTL(pipe); | |
2459 | temp = I915_READ(reg); | |
2460 | if (HAS_PCH_CPT(dev)) { | |
2461 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2462 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2463 | } else { | |
2464 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2465 | temp |= FDI_LINK_TRAIN_NONE; | |
2466 | } | |
2467 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2468 | ||
2469 | /* wait one idle pattern time */ | |
2470 | POSTING_READ(reg); | |
2471 | udelay(1000); | |
357555c0 JB |
2472 | |
2473 | /* IVB wants error correction enabled */ | |
2474 | if (IS_IVYBRIDGE(dev)) | |
2475 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2476 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2477 | } |
2478 | ||
1fbc0d78 | 2479 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2480 | { |
1fbc0d78 DV |
2481 | return crtc->base.enabled && crtc->active && |
2482 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2483 | } |
2484 | ||
01a415fd DV |
2485 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2486 | { | |
2487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2488 | struct intel_crtc *pipe_B_crtc = | |
2489 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2490 | struct intel_crtc *pipe_C_crtc = | |
2491 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2492 | uint32_t temp; | |
2493 | ||
1e833f40 DV |
2494 | /* |
2495 | * When everything is off disable fdi C so that we could enable fdi B | |
2496 | * with all lanes. Note that we don't care about enabled pipes without | |
2497 | * an enabled pch encoder. | |
2498 | */ | |
2499 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2500 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2501 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2502 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2503 | ||
2504 | temp = I915_READ(SOUTH_CHICKEN1); | |
2505 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2506 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2507 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2508 | } | |
2509 | } | |
2510 | ||
8db9d77b ZW |
2511 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2512 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2513 | { | |
2514 | struct drm_device *dev = crtc->dev; | |
2515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2516 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2517 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2518 | int plane = intel_crtc->plane; |
5eddb70b | 2519 | u32 reg, temp, tries; |
8db9d77b | 2520 | |
0fc932b8 JB |
2521 | /* FDI needs bits from pipe & plane first */ |
2522 | assert_pipe_enabled(dev_priv, pipe); | |
2523 | assert_plane_enabled(dev_priv, plane); | |
2524 | ||
e1a44743 AJ |
2525 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2526 | for train result */ | |
5eddb70b CW |
2527 | reg = FDI_RX_IMR(pipe); |
2528 | temp = I915_READ(reg); | |
e1a44743 AJ |
2529 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2530 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2531 | I915_WRITE(reg, temp); |
2532 | I915_READ(reg); | |
e1a44743 AJ |
2533 | udelay(150); |
2534 | ||
8db9d77b | 2535 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2536 | reg = FDI_TX_CTL(pipe); |
2537 | temp = I915_READ(reg); | |
627eb5a3 DV |
2538 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2539 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2540 | temp &= ~FDI_LINK_TRAIN_NONE; |
2541 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2542 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2543 | |
5eddb70b CW |
2544 | reg = FDI_RX_CTL(pipe); |
2545 | temp = I915_READ(reg); | |
8db9d77b ZW |
2546 | temp &= ~FDI_LINK_TRAIN_NONE; |
2547 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2548 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2549 | ||
2550 | POSTING_READ(reg); | |
8db9d77b ZW |
2551 | udelay(150); |
2552 | ||
5b2adf89 | 2553 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2554 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2555 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2556 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2557 | |
5eddb70b | 2558 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2559 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2560 | temp = I915_READ(reg); |
8db9d77b ZW |
2561 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2562 | ||
2563 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2564 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2565 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2566 | break; |
2567 | } | |
8db9d77b | 2568 | } |
e1a44743 | 2569 | if (tries == 5) |
5eddb70b | 2570 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2571 | |
2572 | /* Train 2 */ | |
5eddb70b CW |
2573 | reg = FDI_TX_CTL(pipe); |
2574 | temp = I915_READ(reg); | |
8db9d77b ZW |
2575 | temp &= ~FDI_LINK_TRAIN_NONE; |
2576 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2577 | I915_WRITE(reg, temp); |
8db9d77b | 2578 | |
5eddb70b CW |
2579 | reg = FDI_RX_CTL(pipe); |
2580 | temp = I915_READ(reg); | |
8db9d77b ZW |
2581 | temp &= ~FDI_LINK_TRAIN_NONE; |
2582 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2583 | I915_WRITE(reg, temp); |
8db9d77b | 2584 | |
5eddb70b CW |
2585 | POSTING_READ(reg); |
2586 | udelay(150); | |
8db9d77b | 2587 | |
5eddb70b | 2588 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2589 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2590 | temp = I915_READ(reg); |
8db9d77b ZW |
2591 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2592 | ||
2593 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2594 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2595 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2596 | break; | |
2597 | } | |
8db9d77b | 2598 | } |
e1a44743 | 2599 | if (tries == 5) |
5eddb70b | 2600 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2601 | |
2602 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2603 | |
8db9d77b ZW |
2604 | } |
2605 | ||
0206e353 | 2606 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2607 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2608 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2609 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2610 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2611 | }; | |
2612 | ||
2613 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2614 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2615 | { | |
2616 | struct drm_device *dev = crtc->dev; | |
2617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2618 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2619 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2620 | u32 reg, temp, i, retry; |
8db9d77b | 2621 | |
e1a44743 AJ |
2622 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2623 | for train result */ | |
5eddb70b CW |
2624 | reg = FDI_RX_IMR(pipe); |
2625 | temp = I915_READ(reg); | |
e1a44743 AJ |
2626 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2627 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2628 | I915_WRITE(reg, temp); |
2629 | ||
2630 | POSTING_READ(reg); | |
e1a44743 AJ |
2631 | udelay(150); |
2632 | ||
8db9d77b | 2633 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2634 | reg = FDI_TX_CTL(pipe); |
2635 | temp = I915_READ(reg); | |
627eb5a3 DV |
2636 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2637 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2638 | temp &= ~FDI_LINK_TRAIN_NONE; |
2639 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2640 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2641 | /* SNB-B */ | |
2642 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2643 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2644 | |
d74cf324 DV |
2645 | I915_WRITE(FDI_RX_MISC(pipe), |
2646 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2647 | ||
5eddb70b CW |
2648 | reg = FDI_RX_CTL(pipe); |
2649 | temp = I915_READ(reg); | |
8db9d77b ZW |
2650 | if (HAS_PCH_CPT(dev)) { |
2651 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2652 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2653 | } else { | |
2654 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2655 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2656 | } | |
5eddb70b CW |
2657 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2658 | ||
2659 | POSTING_READ(reg); | |
8db9d77b ZW |
2660 | udelay(150); |
2661 | ||
0206e353 | 2662 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2663 | reg = FDI_TX_CTL(pipe); |
2664 | temp = I915_READ(reg); | |
8db9d77b ZW |
2665 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2666 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2667 | I915_WRITE(reg, temp); |
2668 | ||
2669 | POSTING_READ(reg); | |
8db9d77b ZW |
2670 | udelay(500); |
2671 | ||
fa37d39e SP |
2672 | for (retry = 0; retry < 5; retry++) { |
2673 | reg = FDI_RX_IIR(pipe); | |
2674 | temp = I915_READ(reg); | |
2675 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2676 | if (temp & FDI_RX_BIT_LOCK) { | |
2677 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2678 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2679 | break; | |
2680 | } | |
2681 | udelay(50); | |
8db9d77b | 2682 | } |
fa37d39e SP |
2683 | if (retry < 5) |
2684 | break; | |
8db9d77b ZW |
2685 | } |
2686 | if (i == 4) | |
5eddb70b | 2687 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2688 | |
2689 | /* Train 2 */ | |
5eddb70b CW |
2690 | reg = FDI_TX_CTL(pipe); |
2691 | temp = I915_READ(reg); | |
8db9d77b ZW |
2692 | temp &= ~FDI_LINK_TRAIN_NONE; |
2693 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2694 | if (IS_GEN6(dev)) { | |
2695 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2696 | /* SNB-B */ | |
2697 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2698 | } | |
5eddb70b | 2699 | I915_WRITE(reg, temp); |
8db9d77b | 2700 | |
5eddb70b CW |
2701 | reg = FDI_RX_CTL(pipe); |
2702 | temp = I915_READ(reg); | |
8db9d77b ZW |
2703 | if (HAS_PCH_CPT(dev)) { |
2704 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2705 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2706 | } else { | |
2707 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2708 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2709 | } | |
5eddb70b CW |
2710 | I915_WRITE(reg, temp); |
2711 | ||
2712 | POSTING_READ(reg); | |
8db9d77b ZW |
2713 | udelay(150); |
2714 | ||
0206e353 | 2715 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2716 | reg = FDI_TX_CTL(pipe); |
2717 | temp = I915_READ(reg); | |
8db9d77b ZW |
2718 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2719 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2720 | I915_WRITE(reg, temp); |
2721 | ||
2722 | POSTING_READ(reg); | |
8db9d77b ZW |
2723 | udelay(500); |
2724 | ||
fa37d39e SP |
2725 | for (retry = 0; retry < 5; retry++) { |
2726 | reg = FDI_RX_IIR(pipe); | |
2727 | temp = I915_READ(reg); | |
2728 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2729 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2730 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2731 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2732 | break; | |
2733 | } | |
2734 | udelay(50); | |
8db9d77b | 2735 | } |
fa37d39e SP |
2736 | if (retry < 5) |
2737 | break; | |
8db9d77b ZW |
2738 | } |
2739 | if (i == 4) | |
5eddb70b | 2740 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2741 | |
2742 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2743 | } | |
2744 | ||
357555c0 JB |
2745 | /* Manual link training for Ivy Bridge A0 parts */ |
2746 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2747 | { | |
2748 | struct drm_device *dev = crtc->dev; | |
2749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2751 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2752 | u32 reg, temp, i, j; |
357555c0 JB |
2753 | |
2754 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2755 | for train result */ | |
2756 | reg = FDI_RX_IMR(pipe); | |
2757 | temp = I915_READ(reg); | |
2758 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2759 | temp &= ~FDI_RX_BIT_LOCK; | |
2760 | I915_WRITE(reg, temp); | |
2761 | ||
2762 | POSTING_READ(reg); | |
2763 | udelay(150); | |
2764 | ||
01a415fd DV |
2765 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2766 | I915_READ(FDI_RX_IIR(pipe))); | |
2767 | ||
139ccd3f JB |
2768 | /* Try each vswing and preemphasis setting twice before moving on */ |
2769 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2770 | /* disable first in case we need to retry */ | |
2771 | reg = FDI_TX_CTL(pipe); | |
2772 | temp = I915_READ(reg); | |
2773 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2774 | temp &= ~FDI_TX_ENABLE; | |
2775 | I915_WRITE(reg, temp); | |
357555c0 | 2776 | |
139ccd3f JB |
2777 | reg = FDI_RX_CTL(pipe); |
2778 | temp = I915_READ(reg); | |
2779 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2780 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2781 | temp &= ~FDI_RX_ENABLE; | |
2782 | I915_WRITE(reg, temp); | |
357555c0 | 2783 | |
139ccd3f | 2784 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2785 | reg = FDI_TX_CTL(pipe); |
2786 | temp = I915_READ(reg); | |
139ccd3f JB |
2787 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2788 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2789 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2790 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2791 | temp |= snb_b_fdi_train_param[j/2]; |
2792 | temp |= FDI_COMPOSITE_SYNC; | |
2793 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2794 | |
139ccd3f JB |
2795 | I915_WRITE(FDI_RX_MISC(pipe), |
2796 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2797 | |
139ccd3f | 2798 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2799 | temp = I915_READ(reg); |
139ccd3f JB |
2800 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2801 | temp |= FDI_COMPOSITE_SYNC; | |
2802 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2803 | |
139ccd3f JB |
2804 | POSTING_READ(reg); |
2805 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2806 | |
139ccd3f JB |
2807 | for (i = 0; i < 4; i++) { |
2808 | reg = FDI_RX_IIR(pipe); | |
2809 | temp = I915_READ(reg); | |
2810 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2811 | |
139ccd3f JB |
2812 | if (temp & FDI_RX_BIT_LOCK || |
2813 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2814 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2815 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2816 | i); | |
2817 | break; | |
2818 | } | |
2819 | udelay(1); /* should be 0.5us */ | |
2820 | } | |
2821 | if (i == 4) { | |
2822 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2823 | continue; | |
2824 | } | |
357555c0 | 2825 | |
139ccd3f | 2826 | /* Train 2 */ |
357555c0 JB |
2827 | reg = FDI_TX_CTL(pipe); |
2828 | temp = I915_READ(reg); | |
139ccd3f JB |
2829 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2830 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2831 | I915_WRITE(reg, temp); | |
2832 | ||
2833 | reg = FDI_RX_CTL(pipe); | |
2834 | temp = I915_READ(reg); | |
2835 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2836 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2837 | I915_WRITE(reg, temp); |
2838 | ||
2839 | POSTING_READ(reg); | |
139ccd3f | 2840 | udelay(2); /* should be 1.5us */ |
357555c0 | 2841 | |
139ccd3f JB |
2842 | for (i = 0; i < 4; i++) { |
2843 | reg = FDI_RX_IIR(pipe); | |
2844 | temp = I915_READ(reg); | |
2845 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2846 | |
139ccd3f JB |
2847 | if (temp & FDI_RX_SYMBOL_LOCK || |
2848 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2849 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2850 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2851 | i); | |
2852 | goto train_done; | |
2853 | } | |
2854 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2855 | } |
139ccd3f JB |
2856 | if (i == 4) |
2857 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2858 | } |
357555c0 | 2859 | |
139ccd3f | 2860 | train_done: |
357555c0 JB |
2861 | DRM_DEBUG_KMS("FDI train done.\n"); |
2862 | } | |
2863 | ||
88cefb6c | 2864 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2865 | { |
88cefb6c | 2866 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2867 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2868 | int pipe = intel_crtc->pipe; |
5eddb70b | 2869 | u32 reg, temp; |
79e53945 | 2870 | |
c64e311e | 2871 | |
c98e9dcf | 2872 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2873 | reg = FDI_RX_CTL(pipe); |
2874 | temp = I915_READ(reg); | |
627eb5a3 DV |
2875 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2876 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2877 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2878 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2879 | ||
2880 | POSTING_READ(reg); | |
c98e9dcf JB |
2881 | udelay(200); |
2882 | ||
2883 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2884 | temp = I915_READ(reg); |
2885 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2886 | ||
2887 | POSTING_READ(reg); | |
c98e9dcf JB |
2888 | udelay(200); |
2889 | ||
20749730 PZ |
2890 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2891 | reg = FDI_TX_CTL(pipe); | |
2892 | temp = I915_READ(reg); | |
2893 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2894 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2895 | |
20749730 PZ |
2896 | POSTING_READ(reg); |
2897 | udelay(100); | |
6be4a607 | 2898 | } |
0e23b99d JB |
2899 | } |
2900 | ||
88cefb6c DV |
2901 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2902 | { | |
2903 | struct drm_device *dev = intel_crtc->base.dev; | |
2904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2905 | int pipe = intel_crtc->pipe; | |
2906 | u32 reg, temp; | |
2907 | ||
2908 | /* Switch from PCDclk to Rawclk */ | |
2909 | reg = FDI_RX_CTL(pipe); | |
2910 | temp = I915_READ(reg); | |
2911 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2912 | ||
2913 | /* Disable CPU FDI TX PLL */ | |
2914 | reg = FDI_TX_CTL(pipe); | |
2915 | temp = I915_READ(reg); | |
2916 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2917 | ||
2918 | POSTING_READ(reg); | |
2919 | udelay(100); | |
2920 | ||
2921 | reg = FDI_RX_CTL(pipe); | |
2922 | temp = I915_READ(reg); | |
2923 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2924 | ||
2925 | /* Wait for the clocks to turn off. */ | |
2926 | POSTING_READ(reg); | |
2927 | udelay(100); | |
2928 | } | |
2929 | ||
0fc932b8 JB |
2930 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2931 | { | |
2932 | struct drm_device *dev = crtc->dev; | |
2933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2934 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2935 | int pipe = intel_crtc->pipe; | |
2936 | u32 reg, temp; | |
2937 | ||
2938 | /* disable CPU FDI tx and PCH FDI rx */ | |
2939 | reg = FDI_TX_CTL(pipe); | |
2940 | temp = I915_READ(reg); | |
2941 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2942 | POSTING_READ(reg); | |
2943 | ||
2944 | reg = FDI_RX_CTL(pipe); | |
2945 | temp = I915_READ(reg); | |
2946 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2947 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2948 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2949 | ||
2950 | POSTING_READ(reg); | |
2951 | udelay(100); | |
2952 | ||
2953 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2954 | if (HAS_PCH_IBX(dev)) { |
2955 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2956 | } |
0fc932b8 JB |
2957 | |
2958 | /* still set train pattern 1 */ | |
2959 | reg = FDI_TX_CTL(pipe); | |
2960 | temp = I915_READ(reg); | |
2961 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2962 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2963 | I915_WRITE(reg, temp); | |
2964 | ||
2965 | reg = FDI_RX_CTL(pipe); | |
2966 | temp = I915_READ(reg); | |
2967 | if (HAS_PCH_CPT(dev)) { | |
2968 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2969 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2970 | } else { | |
2971 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2972 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2973 | } | |
2974 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2975 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2976 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2977 | I915_WRITE(reg, temp); |
2978 | ||
2979 | POSTING_READ(reg); | |
2980 | udelay(100); | |
2981 | } | |
2982 | ||
5dce5b93 CW |
2983 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
2984 | { | |
2985 | struct intel_crtc *crtc; | |
2986 | ||
2987 | /* Note that we don't need to be called with mode_config.lock here | |
2988 | * as our list of CRTC objects is static for the lifetime of the | |
2989 | * device and so cannot disappear as we iterate. Similarly, we can | |
2990 | * happily treat the predicates as racy, atomic checks as userspace | |
2991 | * cannot claim and pin a new fb without at least acquring the | |
2992 | * struct_mutex and so serialising with us. | |
2993 | */ | |
2994 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
2995 | if (atomic_read(&crtc->unpin_work_count) == 0) | |
2996 | continue; | |
2997 | ||
2998 | if (crtc->unpin_work) | |
2999 | intel_wait_for_vblank(dev, crtc->pipe); | |
3000 | ||
3001 | return true; | |
3002 | } | |
3003 | ||
3004 | return false; | |
3005 | } | |
3006 | ||
e6c3a2a6 CW |
3007 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3008 | { | |
0f91128d | 3009 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3010 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
3011 | |
3012 | if (crtc->fb == NULL) | |
3013 | return; | |
3014 | ||
2c10d571 DV |
3015 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3016 | ||
5bb61643 CW |
3017 | wait_event(dev_priv->pending_flip_queue, |
3018 | !intel_crtc_has_pending_flip(crtc)); | |
3019 | ||
0f91128d CW |
3020 | mutex_lock(&dev->struct_mutex); |
3021 | intel_finish_fb(crtc->fb); | |
3022 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
3023 | } |
3024 | ||
e615efe4 ED |
3025 | /* Program iCLKIP clock to the desired frequency */ |
3026 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3027 | { | |
3028 | struct drm_device *dev = crtc->dev; | |
3029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3030 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3031 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3032 | u32 temp; | |
3033 | ||
09153000 DV |
3034 | mutex_lock(&dev_priv->dpio_lock); |
3035 | ||
e615efe4 ED |
3036 | /* It is necessary to ungate the pixclk gate prior to programming |
3037 | * the divisors, and gate it back when it is done. | |
3038 | */ | |
3039 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3040 | ||
3041 | /* Disable SSCCTL */ | |
3042 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3043 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3044 | SBI_SSCCTL_DISABLE, | |
3045 | SBI_ICLK); | |
e615efe4 ED |
3046 | |
3047 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3048 | if (clock == 20000) { |
e615efe4 ED |
3049 | auxdiv = 1; |
3050 | divsel = 0x41; | |
3051 | phaseinc = 0x20; | |
3052 | } else { | |
3053 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3054 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3055 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3056 | * convert the virtual clock precision to KHz here for higher |
3057 | * precision. | |
3058 | */ | |
3059 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3060 | u32 iclk_pi_range = 64; | |
3061 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3062 | ||
12d7ceed | 3063 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3064 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3065 | pi_value = desired_divisor % iclk_pi_range; | |
3066 | ||
3067 | auxdiv = 0; | |
3068 | divsel = msb_divisor_value - 2; | |
3069 | phaseinc = pi_value; | |
3070 | } | |
3071 | ||
3072 | /* This should not happen with any sane values */ | |
3073 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3074 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3075 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3076 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3077 | ||
3078 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3079 | clock, |
e615efe4 ED |
3080 | auxdiv, |
3081 | divsel, | |
3082 | phasedir, | |
3083 | phaseinc); | |
3084 | ||
3085 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3086 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3087 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3088 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3089 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3090 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3091 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3092 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3093 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3094 | |
3095 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3096 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3097 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3098 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3099 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3100 | |
3101 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3102 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3103 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3104 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3105 | |
3106 | /* Wait for initialization time */ | |
3107 | udelay(24); | |
3108 | ||
3109 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3110 | |
3111 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3112 | } |
3113 | ||
275f01b2 DV |
3114 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3115 | enum pipe pch_transcoder) | |
3116 | { | |
3117 | struct drm_device *dev = crtc->base.dev; | |
3118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3119 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3120 | ||
3121 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3122 | I915_READ(HTOTAL(cpu_transcoder))); | |
3123 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3124 | I915_READ(HBLANK(cpu_transcoder))); | |
3125 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3126 | I915_READ(HSYNC(cpu_transcoder))); | |
3127 | ||
3128 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3129 | I915_READ(VTOTAL(cpu_transcoder))); | |
3130 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3131 | I915_READ(VBLANK(cpu_transcoder))); | |
3132 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3133 | I915_READ(VSYNC(cpu_transcoder))); | |
3134 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3135 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3136 | } | |
3137 | ||
1fbc0d78 DV |
3138 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3139 | { | |
3140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3141 | uint32_t temp; | |
3142 | ||
3143 | temp = I915_READ(SOUTH_CHICKEN1); | |
3144 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3145 | return; | |
3146 | ||
3147 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3148 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3149 | ||
3150 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3151 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3152 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3153 | POSTING_READ(SOUTH_CHICKEN1); | |
3154 | } | |
3155 | ||
3156 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3157 | { | |
3158 | struct drm_device *dev = intel_crtc->base.dev; | |
3159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3160 | ||
3161 | switch (intel_crtc->pipe) { | |
3162 | case PIPE_A: | |
3163 | break; | |
3164 | case PIPE_B: | |
3165 | if (intel_crtc->config.fdi_lanes > 2) | |
3166 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3167 | else | |
3168 | cpt_enable_fdi_bc_bifurcation(dev); | |
3169 | ||
3170 | break; | |
3171 | case PIPE_C: | |
3172 | cpt_enable_fdi_bc_bifurcation(dev); | |
3173 | ||
3174 | break; | |
3175 | default: | |
3176 | BUG(); | |
3177 | } | |
3178 | } | |
3179 | ||
f67a559d JB |
3180 | /* |
3181 | * Enable PCH resources required for PCH ports: | |
3182 | * - PCH PLLs | |
3183 | * - FDI training & RX/TX | |
3184 | * - update transcoder timings | |
3185 | * - DP transcoding bits | |
3186 | * - transcoder | |
3187 | */ | |
3188 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3189 | { |
3190 | struct drm_device *dev = crtc->dev; | |
3191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3192 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3193 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3194 | u32 reg, temp; |
2c07245f | 3195 | |
ab9412ba | 3196 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3197 | |
1fbc0d78 DV |
3198 | if (IS_IVYBRIDGE(dev)) |
3199 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3200 | ||
cd986abb DV |
3201 | /* Write the TU size bits before fdi link training, so that error |
3202 | * detection works. */ | |
3203 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3204 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3205 | ||
c98e9dcf | 3206 | /* For PCH output, training FDI link */ |
674cf967 | 3207 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3208 | |
3ad8a208 DV |
3209 | /* We need to program the right clock selection before writing the pixel |
3210 | * mutliplier into the DPLL. */ | |
303b81e0 | 3211 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3212 | u32 sel; |
4b645f14 | 3213 | |
c98e9dcf | 3214 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3215 | temp |= TRANS_DPLL_ENABLE(pipe); |
3216 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3217 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3218 | temp |= sel; |
3219 | else | |
3220 | temp &= ~sel; | |
c98e9dcf | 3221 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3222 | } |
5eddb70b | 3223 | |
3ad8a208 DV |
3224 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3225 | * transcoder, and we actually should do this to not upset any PCH | |
3226 | * transcoder that already use the clock when we share it. | |
3227 | * | |
3228 | * Note that enable_shared_dpll tries to do the right thing, but | |
3229 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3230 | * the right LVDS enable sequence. */ | |
3231 | ironlake_enable_shared_dpll(intel_crtc); | |
3232 | ||
d9b6cb56 JB |
3233 | /* set transcoder timing, panel must allow it */ |
3234 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3235 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3236 | |
303b81e0 | 3237 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3238 | |
c98e9dcf JB |
3239 | /* For PCH DP, enable TRANS_DP_CTL */ |
3240 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3241 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3242 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3243 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3244 | reg = TRANS_DP_CTL(pipe); |
3245 | temp = I915_READ(reg); | |
3246 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3247 | TRANS_DP_SYNC_MASK | |
3248 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3249 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3250 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3251 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3252 | |
3253 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3254 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3255 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3256 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3257 | |
3258 | switch (intel_trans_dp_port_sel(crtc)) { | |
3259 | case PCH_DP_B: | |
5eddb70b | 3260 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3261 | break; |
3262 | case PCH_DP_C: | |
5eddb70b | 3263 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3264 | break; |
3265 | case PCH_DP_D: | |
5eddb70b | 3266 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3267 | break; |
3268 | default: | |
e95d41e1 | 3269 | BUG(); |
32f9d658 | 3270 | } |
2c07245f | 3271 | |
5eddb70b | 3272 | I915_WRITE(reg, temp); |
6be4a607 | 3273 | } |
b52eb4dc | 3274 | |
b8a4f404 | 3275 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3276 | } |
3277 | ||
1507e5bd PZ |
3278 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3279 | { | |
3280 | struct drm_device *dev = crtc->dev; | |
3281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3283 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3284 | |
ab9412ba | 3285 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3286 | |
8c52b5e8 | 3287 | lpt_program_iclkip(crtc); |
1507e5bd | 3288 | |
0540e488 | 3289 | /* Set transcoder timing. */ |
275f01b2 | 3290 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3291 | |
937bb610 | 3292 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3293 | } |
3294 | ||
e2b78267 | 3295 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3296 | { |
e2b78267 | 3297 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3298 | |
3299 | if (pll == NULL) | |
3300 | return; | |
3301 | ||
3302 | if (pll->refcount == 0) { | |
46edb027 | 3303 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3304 | return; |
3305 | } | |
3306 | ||
f4a091c7 DV |
3307 | if (--pll->refcount == 0) { |
3308 | WARN_ON(pll->on); | |
3309 | WARN_ON(pll->active); | |
3310 | } | |
3311 | ||
a43f6e0f | 3312 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3313 | } |
3314 | ||
b89a1d39 | 3315 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3316 | { |
e2b78267 DV |
3317 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3318 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3319 | enum intel_dpll_id i; | |
ee7b9f93 | 3320 | |
ee7b9f93 | 3321 | if (pll) { |
46edb027 DV |
3322 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3323 | crtc->base.base.id, pll->name); | |
e2b78267 | 3324 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3325 | } |
3326 | ||
98b6bd99 DV |
3327 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3328 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3329 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3330 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3331 | |
46edb027 DV |
3332 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3333 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3334 | |
3335 | goto found; | |
3336 | } | |
3337 | ||
e72f9fbf DV |
3338 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3339 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3340 | |
3341 | /* Only want to check enabled timings first */ | |
3342 | if (pll->refcount == 0) | |
3343 | continue; | |
3344 | ||
b89a1d39 DV |
3345 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3346 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3347 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3348 | crtc->base.base.id, |
46edb027 | 3349 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3350 | |
3351 | goto found; | |
3352 | } | |
3353 | } | |
3354 | ||
3355 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3356 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3357 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3358 | if (pll->refcount == 0) { |
46edb027 DV |
3359 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3360 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3361 | goto found; |
3362 | } | |
3363 | } | |
3364 | ||
3365 | return NULL; | |
3366 | ||
3367 | found: | |
a43f6e0f | 3368 | crtc->config.shared_dpll = i; |
46edb027 DV |
3369 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3370 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3371 | |
cdbd2316 | 3372 | if (pll->active == 0) { |
66e985c0 DV |
3373 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3374 | sizeof(pll->hw_state)); | |
3375 | ||
46edb027 | 3376 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3377 | WARN_ON(pll->on); |
e9d6944e | 3378 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3379 | |
15bdd4cf | 3380 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3381 | } |
3382 | pll->refcount++; | |
e04c7350 | 3383 | |
ee7b9f93 JB |
3384 | return pll; |
3385 | } | |
3386 | ||
a1520318 | 3387 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3388 | { |
3389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3390 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3391 | u32 temp; |
3392 | ||
3393 | temp = I915_READ(dslreg); | |
3394 | udelay(500); | |
3395 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3396 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3397 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3398 | } |
3399 | } | |
3400 | ||
b074cec8 JB |
3401 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3402 | { | |
3403 | struct drm_device *dev = crtc->base.dev; | |
3404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3405 | int pipe = crtc->pipe; | |
3406 | ||
fd4daa9c | 3407 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3408 | /* Force use of hard-coded filter coefficients |
3409 | * as some pre-programmed values are broken, | |
3410 | * e.g. x201. | |
3411 | */ | |
3412 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3413 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3414 | PF_PIPE_SEL_IVB(pipe)); | |
3415 | else | |
3416 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3417 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3418 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3419 | } |
3420 | } | |
3421 | ||
bb53d4ae VS |
3422 | static void intel_enable_planes(struct drm_crtc *crtc) |
3423 | { | |
3424 | struct drm_device *dev = crtc->dev; | |
3425 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3426 | struct intel_plane *intel_plane; | |
3427 | ||
3428 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3429 | if (intel_plane->pipe == pipe) | |
3430 | intel_plane_restore(&intel_plane->base); | |
3431 | } | |
3432 | ||
3433 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3434 | { | |
3435 | struct drm_device *dev = crtc->dev; | |
3436 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3437 | struct intel_plane *intel_plane; | |
3438 | ||
3439 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3440 | if (intel_plane->pipe == pipe) | |
3441 | intel_plane_disable(&intel_plane->base); | |
3442 | } | |
3443 | ||
20bc8673 | 3444 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3445 | { |
3446 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3447 | ||
3448 | if (!crtc->config.ips_enabled) | |
3449 | return; | |
3450 | ||
3451 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3452 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3453 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3454 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3455 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3456 | if (IS_BROADWELL(crtc->base.dev)) { |
3457 | mutex_lock(&dev_priv->rps.hw_lock); | |
3458 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3459 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3460 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3461 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3462 | * mailbox." Moreover, the mailbox may return a bogus state, |
3463 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3464 | */ |
3465 | } else { | |
3466 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3467 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3468 | * is essentially intel_wait_for_vblank. If we don't have this | |
3469 | * and don't wait for vblanks until the end of crtc_enable, then | |
3470 | * the HW state readout code will complain that the expected | |
3471 | * IPS_CTL value is not the one we read. */ | |
3472 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3473 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3474 | } | |
d77e4531 PZ |
3475 | } |
3476 | ||
20bc8673 | 3477 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3478 | { |
3479 | struct drm_device *dev = crtc->base.dev; | |
3480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3481 | ||
3482 | if (!crtc->config.ips_enabled) | |
3483 | return; | |
3484 | ||
3485 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3486 | if (IS_BROADWELL(crtc->base.dev)) { |
3487 | mutex_lock(&dev_priv->rps.hw_lock); | |
3488 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3489 | mutex_unlock(&dev_priv->rps.hw_lock); | |
e59150dc | 3490 | } else { |
2a114cc1 | 3491 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3492 | POSTING_READ(IPS_CTL); |
3493 | } | |
d77e4531 PZ |
3494 | |
3495 | /* We need to wait for a vblank before we can disable the plane. */ | |
3496 | intel_wait_for_vblank(dev, crtc->pipe); | |
3497 | } | |
3498 | ||
3499 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3500 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3501 | { | |
3502 | struct drm_device *dev = crtc->dev; | |
3503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3505 | enum pipe pipe = intel_crtc->pipe; | |
3506 | int palreg = PALETTE(pipe); | |
3507 | int i; | |
3508 | bool reenable_ips = false; | |
3509 | ||
3510 | /* The clocks have to be on to load the palette. */ | |
3511 | if (!crtc->enabled || !intel_crtc->active) | |
3512 | return; | |
3513 | ||
3514 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3515 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3516 | assert_dsi_pll_enabled(dev_priv); | |
3517 | else | |
3518 | assert_pll_enabled(dev_priv, pipe); | |
3519 | } | |
3520 | ||
3521 | /* use legacy palette for Ironlake */ | |
3522 | if (HAS_PCH_SPLIT(dev)) | |
3523 | palreg = LGC_PALETTE(pipe); | |
3524 | ||
3525 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3526 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3527 | */ | |
41e6fc4c | 3528 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3529 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3530 | GAMMA_MODE_MODE_SPLIT)) { | |
3531 | hsw_disable_ips(intel_crtc); | |
3532 | reenable_ips = true; | |
3533 | } | |
3534 | ||
3535 | for (i = 0; i < 256; i++) { | |
3536 | I915_WRITE(palreg + 4 * i, | |
3537 | (intel_crtc->lut_r[i] << 16) | | |
3538 | (intel_crtc->lut_g[i] << 8) | | |
3539 | intel_crtc->lut_b[i]); | |
3540 | } | |
3541 | ||
3542 | if (reenable_ips) | |
3543 | hsw_enable_ips(intel_crtc); | |
3544 | } | |
3545 | ||
f67a559d JB |
3546 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3547 | { | |
3548 | struct drm_device *dev = crtc->dev; | |
3549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3551 | struct intel_encoder *encoder; |
f67a559d JB |
3552 | int pipe = intel_crtc->pipe; |
3553 | int plane = intel_crtc->plane; | |
f67a559d | 3554 | |
08a48469 DV |
3555 | WARN_ON(!crtc->enabled); |
3556 | ||
f67a559d JB |
3557 | if (intel_crtc->active) |
3558 | return; | |
3559 | ||
3560 | intel_crtc->active = true; | |
8664281b PZ |
3561 | |
3562 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3563 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3564 | ||
f6736a1a | 3565 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3566 | if (encoder->pre_enable) |
3567 | encoder->pre_enable(encoder); | |
f67a559d | 3568 | |
5bfe2ac0 | 3569 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3570 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3571 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3572 | * enabling. */ | |
88cefb6c | 3573 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3574 | } else { |
3575 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3576 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3577 | } | |
f67a559d | 3578 | |
b074cec8 | 3579 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3580 | |
9c54c0dd JB |
3581 | /* |
3582 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3583 | * clocks enabled | |
3584 | */ | |
3585 | intel_crtc_load_lut(crtc); | |
3586 | ||
f37fcc2a | 3587 | intel_update_watermarks(crtc); |
e1fdc473 | 3588 | intel_enable_pipe(intel_crtc); |
d1de00ef | 3589 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3590 | intel_enable_planes(crtc); |
5c38d48c | 3591 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3592 | |
5bfe2ac0 | 3593 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3594 | ironlake_pch_enable(crtc); |
c98e9dcf | 3595 | |
d1ebd816 | 3596 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3597 | intel_update_fbc(dev); |
d1ebd816 BW |
3598 | mutex_unlock(&dev->struct_mutex); |
3599 | ||
fa5c73b1 DV |
3600 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3601 | encoder->enable(encoder); | |
61b77ddd DV |
3602 | |
3603 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3604 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3605 | |
3606 | /* | |
3607 | * There seems to be a race in PCH platform hw (at least on some | |
3608 | * outputs) where an enabled pipe still completes any pageflip right | |
3609 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3610 | * as the first vblank happend, everything works as expected. Hence just | |
3611 | * wait for one vblank before returning to avoid strange things | |
3612 | * happening. | |
3613 | */ | |
3614 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3615 | } |
3616 | ||
42db64ef PZ |
3617 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3618 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3619 | { | |
f5adf94e | 3620 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3621 | } |
3622 | ||
dda9a66a VS |
3623 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3624 | { | |
3625 | struct drm_device *dev = crtc->dev; | |
3626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3628 | int pipe = intel_crtc->pipe; | |
3629 | int plane = intel_crtc->plane; | |
3630 | ||
d1de00ef | 3631 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3632 | intel_enable_planes(crtc); |
3633 | intel_crtc_update_cursor(crtc, true); | |
3634 | ||
3635 | hsw_enable_ips(intel_crtc); | |
3636 | ||
3637 | mutex_lock(&dev->struct_mutex); | |
3638 | intel_update_fbc(dev); | |
3639 | mutex_unlock(&dev->struct_mutex); | |
3640 | } | |
3641 | ||
3642 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3643 | { | |
3644 | struct drm_device *dev = crtc->dev; | |
3645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3646 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3647 | int pipe = intel_crtc->pipe; | |
3648 | int plane = intel_crtc->plane; | |
3649 | ||
3650 | intel_crtc_wait_for_pending_flips(crtc); | |
3651 | drm_vblank_off(dev, pipe); | |
3652 | ||
3653 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3654 | if (dev_priv->fbc.plane == plane) | |
3655 | intel_disable_fbc(dev); | |
3656 | ||
3657 | hsw_disable_ips(intel_crtc); | |
3658 | ||
3659 | intel_crtc_update_cursor(crtc, false); | |
3660 | intel_disable_planes(crtc); | |
d1de00ef | 3661 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3662 | } |
3663 | ||
e4916946 PZ |
3664 | /* |
3665 | * This implements the workaround described in the "notes" section of the mode | |
3666 | * set sequence documentation. When going from no pipes or single pipe to | |
3667 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3668 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3669 | */ | |
3670 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3671 | { | |
3672 | struct drm_device *dev = crtc->base.dev; | |
3673 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3674 | ||
3675 | /* We want to get the other_active_crtc only if there's only 1 other | |
3676 | * active crtc. */ | |
3677 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3678 | if (!crtc_it->active || crtc_it == crtc) | |
3679 | continue; | |
3680 | ||
3681 | if (other_active_crtc) | |
3682 | return; | |
3683 | ||
3684 | other_active_crtc = crtc_it; | |
3685 | } | |
3686 | if (!other_active_crtc) | |
3687 | return; | |
3688 | ||
3689 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3690 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3691 | } | |
3692 | ||
4f771f10 PZ |
3693 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3694 | { | |
3695 | struct drm_device *dev = crtc->dev; | |
3696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3697 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3698 | struct intel_encoder *encoder; | |
3699 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3700 | |
3701 | WARN_ON(!crtc->enabled); | |
3702 | ||
3703 | if (intel_crtc->active) | |
3704 | return; | |
3705 | ||
3706 | intel_crtc->active = true; | |
8664281b PZ |
3707 | |
3708 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3709 | if (intel_crtc->config.has_pch_encoder) | |
3710 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3711 | ||
5bfe2ac0 | 3712 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3713 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3714 | |
3715 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3716 | if (encoder->pre_enable) | |
3717 | encoder->pre_enable(encoder); | |
3718 | ||
1f544388 | 3719 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3720 | |
b074cec8 | 3721 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3722 | |
3723 | /* | |
3724 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3725 | * clocks enabled | |
3726 | */ | |
3727 | intel_crtc_load_lut(crtc); | |
3728 | ||
1f544388 | 3729 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3730 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3731 | |
f37fcc2a | 3732 | intel_update_watermarks(crtc); |
e1fdc473 | 3733 | intel_enable_pipe(intel_crtc); |
42db64ef | 3734 | |
5bfe2ac0 | 3735 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3736 | lpt_pch_enable(crtc); |
4f771f10 | 3737 | |
8807e55b | 3738 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3739 | encoder->enable(encoder); |
8807e55b JN |
3740 | intel_opregion_notify_encoder(encoder, true); |
3741 | } | |
4f771f10 | 3742 | |
e4916946 PZ |
3743 | /* If we change the relative order between pipe/planes enabling, we need |
3744 | * to change the workaround. */ | |
3745 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a | 3746 | haswell_crtc_enable_planes(crtc); |
4f771f10 PZ |
3747 | } |
3748 | ||
3f8dce3a DV |
3749 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3750 | { | |
3751 | struct drm_device *dev = crtc->base.dev; | |
3752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3753 | int pipe = crtc->pipe; | |
3754 | ||
3755 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3756 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3757 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3758 | I915_WRITE(PF_CTL(pipe), 0); |
3759 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3760 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3761 | } | |
3762 | } | |
3763 | ||
6be4a607 JB |
3764 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3765 | { | |
3766 | struct drm_device *dev = crtc->dev; | |
3767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3769 | struct intel_encoder *encoder; |
6be4a607 JB |
3770 | int pipe = intel_crtc->pipe; |
3771 | int plane = intel_crtc->plane; | |
5eddb70b | 3772 | u32 reg, temp; |
b52eb4dc | 3773 | |
ef9c3aee | 3774 | |
f7abfe8b CW |
3775 | if (!intel_crtc->active) |
3776 | return; | |
3777 | ||
ea9d758d DV |
3778 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3779 | encoder->disable(encoder); | |
3780 | ||
e6c3a2a6 | 3781 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3782 | drm_vblank_off(dev, pipe); |
913d8d11 | 3783 | |
5c3fe8b0 | 3784 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3785 | intel_disable_fbc(dev); |
2c07245f | 3786 | |
0d5b8c61 | 3787 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3788 | intel_disable_planes(crtc); |
d1de00ef | 3789 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3790 | |
d925c59a DV |
3791 | if (intel_crtc->config.has_pch_encoder) |
3792 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3793 | ||
b24e7179 | 3794 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3795 | |
3f8dce3a | 3796 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3797 | |
bf49ec8c DV |
3798 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3799 | if (encoder->post_disable) | |
3800 | encoder->post_disable(encoder); | |
2c07245f | 3801 | |
d925c59a DV |
3802 | if (intel_crtc->config.has_pch_encoder) { |
3803 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3804 | |
d925c59a DV |
3805 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3806 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3807 | |
d925c59a DV |
3808 | if (HAS_PCH_CPT(dev)) { |
3809 | /* disable TRANS_DP_CTL */ | |
3810 | reg = TRANS_DP_CTL(pipe); | |
3811 | temp = I915_READ(reg); | |
3812 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3813 | TRANS_DP_PORT_SEL_MASK); | |
3814 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3815 | I915_WRITE(reg, temp); | |
3816 | ||
3817 | /* disable DPLL_SEL */ | |
3818 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3819 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3820 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3821 | } |
e3421a18 | 3822 | |
d925c59a | 3823 | /* disable PCH DPLL */ |
e72f9fbf | 3824 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3825 | |
d925c59a DV |
3826 | ironlake_fdi_pll_disable(intel_crtc); |
3827 | } | |
6b383a7f | 3828 | |
f7abfe8b | 3829 | intel_crtc->active = false; |
46ba614c | 3830 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3831 | |
3832 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3833 | intel_update_fbc(dev); |
d1ebd816 | 3834 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3835 | } |
1b3c7a47 | 3836 | |
4f771f10 | 3837 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3838 | { |
4f771f10 PZ |
3839 | struct drm_device *dev = crtc->dev; |
3840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3842 | struct intel_encoder *encoder; |
3843 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3844 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3845 | |
4f771f10 PZ |
3846 | if (!intel_crtc->active) |
3847 | return; | |
3848 | ||
dda9a66a VS |
3849 | haswell_crtc_disable_planes(crtc); |
3850 | ||
8807e55b JN |
3851 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3852 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3853 | encoder->disable(encoder); |
8807e55b | 3854 | } |
4f771f10 | 3855 | |
8664281b PZ |
3856 | if (intel_crtc->config.has_pch_encoder) |
3857 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3858 | intel_disable_pipe(dev_priv, pipe); |
3859 | ||
ad80a810 | 3860 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3861 | |
3f8dce3a | 3862 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3863 | |
1f544388 | 3864 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3865 | |
3866 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3867 | if (encoder->post_disable) | |
3868 | encoder->post_disable(encoder); | |
3869 | ||
88adfff1 | 3870 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3871 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3872 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3873 | intel_ddi_fdi_disable(crtc); |
83616634 | 3874 | } |
4f771f10 PZ |
3875 | |
3876 | intel_crtc->active = false; | |
46ba614c | 3877 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3878 | |
3879 | mutex_lock(&dev->struct_mutex); | |
3880 | intel_update_fbc(dev); | |
3881 | mutex_unlock(&dev->struct_mutex); | |
3882 | } | |
3883 | ||
ee7b9f93 JB |
3884 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3885 | { | |
3886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3887 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3888 | } |
3889 | ||
6441ab5f PZ |
3890 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3891 | { | |
3892 | intel_ddi_put_crtc_pll(crtc); | |
3893 | } | |
3894 | ||
02e792fb DV |
3895 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3896 | { | |
02e792fb | 3897 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3898 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3899 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3900 | |
23f09ce3 | 3901 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3902 | dev_priv->mm.interruptible = false; |
3903 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3904 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3905 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3906 | } |
02e792fb | 3907 | |
5dcdbcb0 CW |
3908 | /* Let userspace switch the overlay on again. In most cases userspace |
3909 | * has to recompute where to put it anyway. | |
3910 | */ | |
02e792fb DV |
3911 | } |
3912 | ||
61bc95c1 EE |
3913 | /** |
3914 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3915 | * cursor plane briefly if not already running after enabling the display | |
3916 | * plane. | |
3917 | * This workaround avoids occasional blank screens when self refresh is | |
3918 | * enabled. | |
3919 | */ | |
3920 | static void | |
3921 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3922 | { | |
3923 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3924 | ||
3925 | if ((cntl & CURSOR_MODE) == 0) { | |
3926 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3927 | ||
3928 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3929 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3930 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3931 | I915_WRITE(CURCNTR(pipe), cntl); | |
3932 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3933 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3934 | } | |
3935 | } | |
3936 | ||
2dd24552 JB |
3937 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3938 | { | |
3939 | struct drm_device *dev = crtc->base.dev; | |
3940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3941 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3942 | ||
328d8e82 | 3943 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3944 | return; |
3945 | ||
2dd24552 | 3946 | /* |
c0b03411 DV |
3947 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3948 | * according to register description and PRM. | |
2dd24552 | 3949 | */ |
c0b03411 DV |
3950 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3951 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3952 | |
b074cec8 JB |
3953 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3954 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3955 | |
3956 | /* Border color in case we don't scale up to the full screen. Black by | |
3957 | * default, change to something else for debugging. */ | |
3958 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3959 | } |
3960 | ||
77d22dca ID |
3961 | #define for_each_power_domain(domain, mask) \ |
3962 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
3963 | if ((1 << (domain)) & (mask)) | |
3964 | ||
319be8ae ID |
3965 | enum intel_display_power_domain |
3966 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
3967 | { | |
3968 | struct drm_device *dev = intel_encoder->base.dev; | |
3969 | struct intel_digital_port *intel_dig_port; | |
3970 | ||
3971 | switch (intel_encoder->type) { | |
3972 | case INTEL_OUTPUT_UNKNOWN: | |
3973 | /* Only DDI platforms should ever use this output type */ | |
3974 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
3975 | case INTEL_OUTPUT_DISPLAYPORT: | |
3976 | case INTEL_OUTPUT_HDMI: | |
3977 | case INTEL_OUTPUT_EDP: | |
3978 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
3979 | switch (intel_dig_port->port) { | |
3980 | case PORT_A: | |
3981 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
3982 | case PORT_B: | |
3983 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
3984 | case PORT_C: | |
3985 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
3986 | case PORT_D: | |
3987 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
3988 | default: | |
3989 | WARN_ON_ONCE(1); | |
3990 | return POWER_DOMAIN_PORT_OTHER; | |
3991 | } | |
3992 | case INTEL_OUTPUT_ANALOG: | |
3993 | return POWER_DOMAIN_PORT_CRT; | |
3994 | case INTEL_OUTPUT_DSI: | |
3995 | return POWER_DOMAIN_PORT_DSI; | |
3996 | default: | |
3997 | return POWER_DOMAIN_PORT_OTHER; | |
3998 | } | |
3999 | } | |
4000 | ||
4001 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4002 | { |
319be8ae ID |
4003 | struct drm_device *dev = crtc->dev; |
4004 | struct intel_encoder *intel_encoder; | |
4005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4006 | enum pipe pipe = intel_crtc->pipe; | |
4007 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4008 | unsigned long mask; |
4009 | enum transcoder transcoder; | |
4010 | ||
4011 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4012 | ||
4013 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4014 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4015 | if (pfit_enabled) | |
4016 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4017 | ||
319be8ae ID |
4018 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4019 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4020 | ||
77d22dca ID |
4021 | return mask; |
4022 | } | |
4023 | ||
4024 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4025 | bool enable) | |
4026 | { | |
4027 | if (dev_priv->power_domains.init_power_on == enable) | |
4028 | return; | |
4029 | ||
4030 | if (enable) | |
4031 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4032 | else | |
4033 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4034 | ||
4035 | dev_priv->power_domains.init_power_on = enable; | |
4036 | } | |
4037 | ||
4038 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4039 | { | |
4040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4041 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4042 | struct intel_crtc *crtc; | |
4043 | ||
4044 | /* | |
4045 | * First get all needed power domains, then put all unneeded, to avoid | |
4046 | * any unnecessary toggling of the power wells. | |
4047 | */ | |
4048 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
4049 | enum intel_display_power_domain domain; | |
4050 | ||
4051 | if (!crtc->base.enabled) | |
4052 | continue; | |
4053 | ||
319be8ae | 4054 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4055 | |
4056 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4057 | intel_display_power_get(dev_priv, domain); | |
4058 | } | |
4059 | ||
4060 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
4061 | enum intel_display_power_domain domain; | |
4062 | ||
4063 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4064 | intel_display_power_put(dev_priv, domain); | |
4065 | ||
4066 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4067 | } | |
4068 | ||
4069 | intel_display_set_init_power(dev_priv, false); | |
4070 | } | |
4071 | ||
586f49dc | 4072 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4073 | { |
586f49dc | 4074 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4075 | |
586f49dc JB |
4076 | /* Obtain SKU information */ |
4077 | mutex_lock(&dev_priv->dpio_lock); | |
4078 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4079 | CCK_FUSE_HPLL_FREQ_MASK; | |
4080 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4081 | |
586f49dc | 4082 | return vco_freq[hpll_freq]; |
30a970c6 JB |
4083 | } |
4084 | ||
4085 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4086 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4087 | { | |
4088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4089 | u32 val, cmd; | |
4090 | ||
4091 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
4092 | cmd = 2; | |
4093 | else if (cdclk == 266) | |
4094 | cmd = 1; | |
4095 | else | |
4096 | cmd = 0; | |
4097 | ||
4098 | mutex_lock(&dev_priv->rps.hw_lock); | |
4099 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4100 | val &= ~DSPFREQGUAR_MASK; | |
4101 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4102 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4103 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4104 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4105 | 50)) { | |
4106 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4107 | } | |
4108 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4109 | ||
4110 | if (cdclk == 400) { | |
4111 | u32 divider, vco; | |
4112 | ||
4113 | vco = valleyview_get_vco(dev_priv); | |
4114 | divider = ((vco << 1) / cdclk) - 1; | |
4115 | ||
4116 | mutex_lock(&dev_priv->dpio_lock); | |
4117 | /* adjust cdclk divider */ | |
4118 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4119 | val &= ~0xf; | |
4120 | val |= divider; | |
4121 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4122 | mutex_unlock(&dev_priv->dpio_lock); | |
4123 | } | |
4124 | ||
4125 | mutex_lock(&dev_priv->dpio_lock); | |
4126 | /* adjust self-refresh exit latency value */ | |
4127 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4128 | val &= ~0x7f; | |
4129 | ||
4130 | /* | |
4131 | * For high bandwidth configs, we set a higher latency in the bunit | |
4132 | * so that the core display fetch happens in time to avoid underruns. | |
4133 | */ | |
4134 | if (cdclk == 400) | |
4135 | val |= 4500 / 250; /* 4.5 usec */ | |
4136 | else | |
4137 | val |= 3000 / 250; /* 3.0 usec */ | |
4138 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4139 | mutex_unlock(&dev_priv->dpio_lock); | |
4140 | ||
4141 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4142 | intel_i2c_reset(dev); | |
4143 | } | |
4144 | ||
4145 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
4146 | { | |
4147 | int cur_cdclk, vco; | |
4148 | int divider; | |
4149 | ||
4150 | vco = valleyview_get_vco(dev_priv); | |
4151 | ||
4152 | mutex_lock(&dev_priv->dpio_lock); | |
4153 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4154 | mutex_unlock(&dev_priv->dpio_lock); | |
4155 | ||
4156 | divider &= 0xf; | |
4157 | ||
4158 | cur_cdclk = (vco << 1) / (divider + 1); | |
4159 | ||
4160 | return cur_cdclk; | |
4161 | } | |
4162 | ||
4163 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4164 | int max_pixclk) | |
4165 | { | |
4166 | int cur_cdclk; | |
4167 | ||
4168 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4169 | ||
4170 | /* | |
4171 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4172 | * 200MHz | |
4173 | * 267MHz | |
4174 | * 320MHz | |
4175 | * 400MHz | |
4176 | * So we check to see whether we're above 90% of the lower bin and | |
4177 | * adjust if needed. | |
4178 | */ | |
4179 | if (max_pixclk > 288000) { | |
4180 | return 400; | |
4181 | } else if (max_pixclk > 240000) { | |
4182 | return 320; | |
4183 | } else | |
4184 | return 266; | |
4185 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4186 | } | |
4187 | ||
2f2d7aa1 VS |
4188 | /* compute the max pixel clock for new configuration */ |
4189 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4190 | { |
4191 | struct drm_device *dev = dev_priv->dev; | |
4192 | struct intel_crtc *intel_crtc; | |
4193 | int max_pixclk = 0; | |
4194 | ||
4195 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4196 | base.head) { | |
2f2d7aa1 | 4197 | if (intel_crtc->new_enabled) |
30a970c6 | 4198 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4199 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4200 | } |
4201 | ||
4202 | return max_pixclk; | |
4203 | } | |
4204 | ||
4205 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4206 | unsigned *prepare_pipes) |
30a970c6 JB |
4207 | { |
4208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4209 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4210 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4211 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4212 | ||
4213 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4214 | return; | |
4215 | ||
2f2d7aa1 | 4216 | /* disable/enable all currently active pipes while we change cdclk */ |
30a970c6 JB |
4217 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4218 | base.head) | |
4219 | if (intel_crtc->base.enabled) | |
4220 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4221 | } | |
4222 | ||
4223 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4224 | { | |
4225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4226 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4227 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4228 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4229 | ||
4230 | if (req_cdclk != cur_cdclk) | |
4231 | valleyview_set_cdclk(dev, req_cdclk); | |
77961eb9 | 4232 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4233 | } |
4234 | ||
89b667f8 JB |
4235 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4236 | { | |
4237 | struct drm_device *dev = crtc->dev; | |
4238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4240 | struct intel_encoder *encoder; | |
4241 | int pipe = intel_crtc->pipe; | |
4242 | int plane = intel_crtc->plane; | |
23538ef1 | 4243 | bool is_dsi; |
89b667f8 JB |
4244 | |
4245 | WARN_ON(!crtc->enabled); | |
4246 | ||
4247 | if (intel_crtc->active) | |
4248 | return; | |
4249 | ||
4250 | intel_crtc->active = true; | |
89b667f8 | 4251 | |
89b667f8 JB |
4252 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4253 | if (encoder->pre_pll_enable) | |
4254 | encoder->pre_pll_enable(encoder); | |
4255 | ||
23538ef1 JN |
4256 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4257 | ||
e9fd1c02 JN |
4258 | if (!is_dsi) |
4259 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4260 | |
4261 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4262 | if (encoder->pre_enable) | |
4263 | encoder->pre_enable(encoder); | |
4264 | ||
2dd24552 JB |
4265 | i9xx_pfit_enable(intel_crtc); |
4266 | ||
63cbb074 VS |
4267 | intel_crtc_load_lut(crtc); |
4268 | ||
f37fcc2a | 4269 | intel_update_watermarks(crtc); |
e1fdc473 | 4270 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4271 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4272 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4273 | intel_enable_planes(crtc); |
5c38d48c | 4274 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4275 | |
89b667f8 | 4276 | intel_update_fbc(dev); |
5004945f JN |
4277 | |
4278 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4279 | encoder->enable(encoder); | |
89b667f8 JB |
4280 | } |
4281 | ||
0b8765c6 | 4282 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4283 | { |
4284 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4285 | struct drm_i915_private *dev_priv = dev->dev_private; |
4286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4287 | struct intel_encoder *encoder; |
79e53945 | 4288 | int pipe = intel_crtc->pipe; |
80824003 | 4289 | int plane = intel_crtc->plane; |
79e53945 | 4290 | |
08a48469 DV |
4291 | WARN_ON(!crtc->enabled); |
4292 | ||
f7abfe8b CW |
4293 | if (intel_crtc->active) |
4294 | return; | |
4295 | ||
4296 | intel_crtc->active = true; | |
6b383a7f | 4297 | |
9d6d9f19 MK |
4298 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4299 | if (encoder->pre_enable) | |
4300 | encoder->pre_enable(encoder); | |
4301 | ||
f6736a1a DV |
4302 | i9xx_enable_pll(intel_crtc); |
4303 | ||
2dd24552 JB |
4304 | i9xx_pfit_enable(intel_crtc); |
4305 | ||
63cbb074 VS |
4306 | intel_crtc_load_lut(crtc); |
4307 | ||
f37fcc2a | 4308 | intel_update_watermarks(crtc); |
e1fdc473 | 4309 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4310 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4311 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4312 | intel_enable_planes(crtc); |
22e407d7 | 4313 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4314 | if (IS_G4X(dev)) |
4315 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4316 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4317 | |
0b8765c6 JB |
4318 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4319 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4320 | |
f440eb13 | 4321 | intel_update_fbc(dev); |
ef9c3aee | 4322 | |
fa5c73b1 DV |
4323 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4324 | encoder->enable(encoder); | |
0b8765c6 | 4325 | } |
79e53945 | 4326 | |
87476d63 DV |
4327 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4328 | { | |
4329 | struct drm_device *dev = crtc->base.dev; | |
4330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4331 | |
328d8e82 DV |
4332 | if (!crtc->config.gmch_pfit.control) |
4333 | return; | |
87476d63 | 4334 | |
328d8e82 | 4335 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4336 | |
328d8e82 DV |
4337 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4338 | I915_READ(PFIT_CONTROL)); | |
4339 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4340 | } |
4341 | ||
0b8765c6 JB |
4342 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4343 | { | |
4344 | struct drm_device *dev = crtc->dev; | |
4345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4347 | struct intel_encoder *encoder; |
0b8765c6 JB |
4348 | int pipe = intel_crtc->pipe; |
4349 | int plane = intel_crtc->plane; | |
ef9c3aee | 4350 | |
f7abfe8b CW |
4351 | if (!intel_crtc->active) |
4352 | return; | |
4353 | ||
ea9d758d DV |
4354 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4355 | encoder->disable(encoder); | |
4356 | ||
0b8765c6 | 4357 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4358 | intel_crtc_wait_for_pending_flips(crtc); |
4359 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4360 | |
5c3fe8b0 | 4361 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4362 | intel_disable_fbc(dev); |
79e53945 | 4363 | |
0d5b8c61 VS |
4364 | intel_crtc_dpms_overlay(intel_crtc, false); |
4365 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4366 | intel_disable_planes(crtc); |
d1de00ef | 4367 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4368 | |
2d9d2b0b | 4369 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 4370 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4371 | |
87476d63 | 4372 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4373 | |
89b667f8 JB |
4374 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4375 | if (encoder->post_disable) | |
4376 | encoder->post_disable(encoder); | |
4377 | ||
f6071166 JB |
4378 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4379 | vlv_disable_pll(dev_priv, pipe); | |
4380 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4381 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4382 | |
f7abfe8b | 4383 | intel_crtc->active = false; |
46ba614c | 4384 | intel_update_watermarks(crtc); |
f37fcc2a | 4385 | |
6b383a7f | 4386 | intel_update_fbc(dev); |
0b8765c6 JB |
4387 | } |
4388 | ||
ee7b9f93 JB |
4389 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4390 | { | |
4391 | } | |
4392 | ||
976f8a20 DV |
4393 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4394 | bool enabled) | |
2c07245f ZW |
4395 | { |
4396 | struct drm_device *dev = crtc->dev; | |
4397 | struct drm_i915_master_private *master_priv; | |
4398 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4399 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4400 | |
4401 | if (!dev->primary->master) | |
4402 | return; | |
4403 | ||
4404 | master_priv = dev->primary->master->driver_priv; | |
4405 | if (!master_priv->sarea_priv) | |
4406 | return; | |
4407 | ||
79e53945 JB |
4408 | switch (pipe) { |
4409 | case 0: | |
4410 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4411 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4412 | break; | |
4413 | case 1: | |
4414 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4415 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4416 | break; | |
4417 | default: | |
9db4a9c7 | 4418 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4419 | break; |
4420 | } | |
79e53945 JB |
4421 | } |
4422 | ||
976f8a20 DV |
4423 | /** |
4424 | * Sets the power management mode of the pipe and plane. | |
4425 | */ | |
4426 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4427 | { | |
4428 | struct drm_device *dev = crtc->dev; | |
4429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4430 | struct intel_encoder *intel_encoder; | |
4431 | bool enable = false; | |
4432 | ||
4433 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4434 | enable |= intel_encoder->connectors_active; | |
4435 | ||
4436 | if (enable) | |
4437 | dev_priv->display.crtc_enable(crtc); | |
4438 | else | |
4439 | dev_priv->display.crtc_disable(crtc); | |
4440 | ||
4441 | intel_crtc_update_sarea(crtc, enable); | |
4442 | } | |
4443 | ||
cdd59983 CW |
4444 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4445 | { | |
cdd59983 | 4446 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4447 | struct drm_connector *connector; |
ee7b9f93 | 4448 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4449 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4450 | |
976f8a20 DV |
4451 | /* crtc should still be enabled when we disable it. */ |
4452 | WARN_ON(!crtc->enabled); | |
4453 | ||
4454 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4455 | intel_crtc->eld_vld = false; |
976f8a20 | 4456 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4457 | dev_priv->display.off(crtc); |
4458 | ||
931872fc | 4459 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4460 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4461 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4462 | |
4463 | if (crtc->fb) { | |
4464 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4465 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4466 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4467 | crtc->fb = NULL; |
4468 | } | |
4469 | ||
4470 | /* Update computed state. */ | |
4471 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4472 | if (!connector->encoder || !connector->encoder->crtc) | |
4473 | continue; | |
4474 | ||
4475 | if (connector->encoder->crtc != crtc) | |
4476 | continue; | |
4477 | ||
4478 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4479 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4480 | } |
4481 | } | |
4482 | ||
ea5b213a | 4483 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4484 | { |
4ef69c7a | 4485 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4486 | |
ea5b213a CW |
4487 | drm_encoder_cleanup(encoder); |
4488 | kfree(intel_encoder); | |
7e7d76c3 JB |
4489 | } |
4490 | ||
9237329d | 4491 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4492 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4493 | * state of the entire output pipe. */ | |
9237329d | 4494 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4495 | { |
5ab432ef DV |
4496 | if (mode == DRM_MODE_DPMS_ON) { |
4497 | encoder->connectors_active = true; | |
4498 | ||
b2cabb0e | 4499 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4500 | } else { |
4501 | encoder->connectors_active = false; | |
4502 | ||
b2cabb0e | 4503 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4504 | } |
79e53945 JB |
4505 | } |
4506 | ||
0a91ca29 DV |
4507 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4508 | * internal consistency). */ | |
b980514c | 4509 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4510 | { |
0a91ca29 DV |
4511 | if (connector->get_hw_state(connector)) { |
4512 | struct intel_encoder *encoder = connector->encoder; | |
4513 | struct drm_crtc *crtc; | |
4514 | bool encoder_enabled; | |
4515 | enum pipe pipe; | |
4516 | ||
4517 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4518 | connector->base.base.id, | |
4519 | drm_get_connector_name(&connector->base)); | |
4520 | ||
4521 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4522 | "wrong connector dpms state\n"); | |
4523 | WARN(connector->base.encoder != &encoder->base, | |
4524 | "active connector not linked to encoder\n"); | |
4525 | WARN(!encoder->connectors_active, | |
4526 | "encoder->connectors_active not set\n"); | |
4527 | ||
4528 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4529 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4530 | if (WARN_ON(!encoder->base.crtc)) | |
4531 | return; | |
4532 | ||
4533 | crtc = encoder->base.crtc; | |
4534 | ||
4535 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4536 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4537 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4538 | "encoder active on the wrong pipe\n"); | |
4539 | } | |
79e53945 JB |
4540 | } |
4541 | ||
5ab432ef DV |
4542 | /* Even simpler default implementation, if there's really no special case to |
4543 | * consider. */ | |
4544 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4545 | { |
5ab432ef DV |
4546 | /* All the simple cases only support two dpms states. */ |
4547 | if (mode != DRM_MODE_DPMS_ON) | |
4548 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4549 | |
5ab432ef DV |
4550 | if (mode == connector->dpms) |
4551 | return; | |
4552 | ||
4553 | connector->dpms = mode; | |
4554 | ||
4555 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4556 | if (connector->encoder) |
4557 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4558 | |
b980514c | 4559 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4560 | } |
4561 | ||
f0947c37 DV |
4562 | /* Simple connector->get_hw_state implementation for encoders that support only |
4563 | * one connector and no cloning and hence the encoder state determines the state | |
4564 | * of the connector. */ | |
4565 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4566 | { |
24929352 | 4567 | enum pipe pipe = 0; |
f0947c37 | 4568 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4569 | |
f0947c37 | 4570 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4571 | } |
4572 | ||
1857e1da DV |
4573 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4574 | struct intel_crtc_config *pipe_config) | |
4575 | { | |
4576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4577 | struct intel_crtc *pipe_B_crtc = | |
4578 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4579 | ||
4580 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4581 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4582 | if (pipe_config->fdi_lanes > 4) { | |
4583 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4584 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4585 | return false; | |
4586 | } | |
4587 | ||
bafb6553 | 4588 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4589 | if (pipe_config->fdi_lanes > 2) { |
4590 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4591 | pipe_config->fdi_lanes); | |
4592 | return false; | |
4593 | } else { | |
4594 | return true; | |
4595 | } | |
4596 | } | |
4597 | ||
4598 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4599 | return true; | |
4600 | ||
4601 | /* Ivybridge 3 pipe is really complicated */ | |
4602 | switch (pipe) { | |
4603 | case PIPE_A: | |
4604 | return true; | |
4605 | case PIPE_B: | |
4606 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4607 | pipe_config->fdi_lanes > 2) { | |
4608 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4609 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4610 | return false; | |
4611 | } | |
4612 | return true; | |
4613 | case PIPE_C: | |
1e833f40 | 4614 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4615 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4616 | if (pipe_config->fdi_lanes > 2) { | |
4617 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4618 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4619 | return false; | |
4620 | } | |
4621 | } else { | |
4622 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4623 | return false; | |
4624 | } | |
4625 | return true; | |
4626 | default: | |
4627 | BUG(); | |
4628 | } | |
4629 | } | |
4630 | ||
e29c22c0 DV |
4631 | #define RETRY 1 |
4632 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4633 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4634 | { |
1857e1da | 4635 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4636 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4637 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4638 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4639 | |
e29c22c0 | 4640 | retry: |
877d48d5 DV |
4641 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4642 | * each output octet as 10 bits. The actual frequency | |
4643 | * is stored as a divider into a 100MHz clock, and the | |
4644 | * mode pixel clock is stored in units of 1KHz. | |
4645 | * Hence the bw of each lane in terms of the mode signal | |
4646 | * is: | |
4647 | */ | |
4648 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4649 | ||
241bfc38 | 4650 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4651 | |
2bd89a07 | 4652 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4653 | pipe_config->pipe_bpp); |
4654 | ||
4655 | pipe_config->fdi_lanes = lane; | |
4656 | ||
2bd89a07 | 4657 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4658 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4659 | |
e29c22c0 DV |
4660 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4661 | intel_crtc->pipe, pipe_config); | |
4662 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4663 | pipe_config->pipe_bpp -= 2*3; | |
4664 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4665 | pipe_config->pipe_bpp); | |
4666 | needs_recompute = true; | |
4667 | pipe_config->bw_constrained = true; | |
4668 | ||
4669 | goto retry; | |
4670 | } | |
4671 | ||
4672 | if (needs_recompute) | |
4673 | return RETRY; | |
4674 | ||
4675 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4676 | } |
4677 | ||
42db64ef PZ |
4678 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4679 | struct intel_crtc_config *pipe_config) | |
4680 | { | |
d330a953 | 4681 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 4682 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 4683 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4684 | } |
4685 | ||
a43f6e0f | 4686 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4687 | struct intel_crtc_config *pipe_config) |
79e53945 | 4688 | { |
a43f6e0f | 4689 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4690 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4691 | |
ad3a4479 | 4692 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4693 | if (INTEL_INFO(dev)->gen < 4) { |
4694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4695 | int clock_limit = | |
4696 | dev_priv->display.get_display_clock_speed(dev); | |
4697 | ||
4698 | /* | |
4699 | * Enable pixel doubling when the dot clock | |
4700 | * is > 90% of the (display) core speed. | |
4701 | * | |
b397c96b VS |
4702 | * GDG double wide on either pipe, |
4703 | * otherwise pipe A only. | |
cf532bb2 | 4704 | */ |
b397c96b | 4705 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4706 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4707 | clock_limit *= 2; |
cf532bb2 | 4708 | pipe_config->double_wide = true; |
ad3a4479 VS |
4709 | } |
4710 | ||
241bfc38 | 4711 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4712 | return -EINVAL; |
2c07245f | 4713 | } |
89749350 | 4714 | |
1d1d0e27 VS |
4715 | /* |
4716 | * Pipe horizontal size must be even in: | |
4717 | * - DVO ganged mode | |
4718 | * - LVDS dual channel mode | |
4719 | * - Double wide pipe | |
4720 | */ | |
4721 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4722 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4723 | pipe_config->pipe_src_w &= ~1; | |
4724 | ||
8693a824 DL |
4725 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4726 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4727 | */ |
4728 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4729 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4730 | return -EINVAL; |
44f46b42 | 4731 | |
bd080ee5 | 4732 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4733 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4734 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4735 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4736 | * for lvds. */ | |
4737 | pipe_config->pipe_bpp = 8*3; | |
4738 | } | |
4739 | ||
f5adf94e | 4740 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4741 | hsw_compute_ips_config(crtc, pipe_config); |
4742 | ||
4743 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4744 | * clock survives for now. */ | |
4745 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4746 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4747 | |
877d48d5 | 4748 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4749 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4750 | |
e29c22c0 | 4751 | return 0; |
79e53945 JB |
4752 | } |
4753 | ||
25eb05fc JB |
4754 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4755 | { | |
4756 | return 400000; /* FIXME */ | |
4757 | } | |
4758 | ||
e70236a8 JB |
4759 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4760 | { | |
4761 | return 400000; | |
4762 | } | |
79e53945 | 4763 | |
e70236a8 | 4764 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4765 | { |
e70236a8 JB |
4766 | return 333000; |
4767 | } | |
79e53945 | 4768 | |
e70236a8 JB |
4769 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4770 | { | |
4771 | return 200000; | |
4772 | } | |
79e53945 | 4773 | |
257a7ffc DV |
4774 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4775 | { | |
4776 | u16 gcfgc = 0; | |
4777 | ||
4778 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4779 | ||
4780 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4781 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4782 | return 267000; | |
4783 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4784 | return 333000; | |
4785 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4786 | return 444000; | |
4787 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4788 | return 200000; | |
4789 | default: | |
4790 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4791 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4792 | return 133000; | |
4793 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4794 | return 167000; | |
4795 | } | |
4796 | } | |
4797 | ||
e70236a8 JB |
4798 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4799 | { | |
4800 | u16 gcfgc = 0; | |
79e53945 | 4801 | |
e70236a8 JB |
4802 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4803 | ||
4804 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4805 | return 133000; | |
4806 | else { | |
4807 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4808 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4809 | return 333000; | |
4810 | default: | |
4811 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4812 | return 190000; | |
79e53945 | 4813 | } |
e70236a8 JB |
4814 | } |
4815 | } | |
4816 | ||
4817 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4818 | { | |
4819 | return 266000; | |
4820 | } | |
4821 | ||
4822 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4823 | { | |
4824 | u16 hpllcc = 0; | |
4825 | /* Assume that the hardware is in the high speed state. This | |
4826 | * should be the default. | |
4827 | */ | |
4828 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4829 | case GC_CLOCK_133_200: | |
4830 | case GC_CLOCK_100_200: | |
4831 | return 200000; | |
4832 | case GC_CLOCK_166_250: | |
4833 | return 250000; | |
4834 | case GC_CLOCK_100_133: | |
79e53945 | 4835 | return 133000; |
e70236a8 | 4836 | } |
79e53945 | 4837 | |
e70236a8 JB |
4838 | /* Shouldn't happen */ |
4839 | return 0; | |
4840 | } | |
79e53945 | 4841 | |
e70236a8 JB |
4842 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4843 | { | |
4844 | return 133000; | |
79e53945 JB |
4845 | } |
4846 | ||
2c07245f | 4847 | static void |
a65851af | 4848 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4849 | { |
a65851af VS |
4850 | while (*num > DATA_LINK_M_N_MASK || |
4851 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4852 | *num >>= 1; |
4853 | *den >>= 1; | |
4854 | } | |
4855 | } | |
4856 | ||
a65851af VS |
4857 | static void compute_m_n(unsigned int m, unsigned int n, |
4858 | uint32_t *ret_m, uint32_t *ret_n) | |
4859 | { | |
4860 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4861 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4862 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4863 | } | |
4864 | ||
e69d0bc1 DV |
4865 | void |
4866 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4867 | int pixel_clock, int link_clock, | |
4868 | struct intel_link_m_n *m_n) | |
2c07245f | 4869 | { |
e69d0bc1 | 4870 | m_n->tu = 64; |
a65851af VS |
4871 | |
4872 | compute_m_n(bits_per_pixel * pixel_clock, | |
4873 | link_clock * nlanes * 8, | |
4874 | &m_n->gmch_m, &m_n->gmch_n); | |
4875 | ||
4876 | compute_m_n(pixel_clock, link_clock, | |
4877 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4878 | } |
4879 | ||
a7615030 CW |
4880 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4881 | { | |
d330a953 JN |
4882 | if (i915.panel_use_ssc >= 0) |
4883 | return i915.panel_use_ssc != 0; | |
41aa3448 | 4884 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4885 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4886 | } |
4887 | ||
c65d77d8 JB |
4888 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4889 | { | |
4890 | struct drm_device *dev = crtc->dev; | |
4891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4892 | int refclk; | |
4893 | ||
a0c4da24 | 4894 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4895 | refclk = 100000; |
a0c4da24 | 4896 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4897 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
4898 | refclk = dev_priv->vbt.lvds_ssc_freq; |
4899 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
4900 | } else if (!IS_GEN2(dev)) { |
4901 | refclk = 96000; | |
4902 | } else { | |
4903 | refclk = 48000; | |
4904 | } | |
4905 | ||
4906 | return refclk; | |
4907 | } | |
4908 | ||
7429e9d4 | 4909 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4910 | { |
7df00d7a | 4911 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4912 | } |
f47709a9 | 4913 | |
7429e9d4 DV |
4914 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4915 | { | |
4916 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4917 | } |
4918 | ||
f47709a9 | 4919 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4920 | intel_clock_t *reduced_clock) |
4921 | { | |
f47709a9 | 4922 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4923 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4924 | int pipe = crtc->pipe; |
a7516a05 JB |
4925 | u32 fp, fp2 = 0; |
4926 | ||
4927 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4928 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4929 | if (reduced_clock) |
7429e9d4 | 4930 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4931 | } else { |
7429e9d4 | 4932 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4933 | if (reduced_clock) |
7429e9d4 | 4934 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4935 | } |
4936 | ||
4937 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4938 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4939 | |
f47709a9 DV |
4940 | crtc->lowfreq_avail = false; |
4941 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 4942 | reduced_clock && i915.powersave) { |
a7516a05 | 4943 | I915_WRITE(FP1(pipe), fp2); |
8bcc2795 | 4944 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4945 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4946 | } else { |
4947 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4948 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4949 | } |
4950 | } | |
4951 | ||
5e69f97f CML |
4952 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4953 | pipe) | |
89b667f8 JB |
4954 | { |
4955 | u32 reg_val; | |
4956 | ||
4957 | /* | |
4958 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4959 | * and set it to a reasonable value instead. | |
4960 | */ | |
ab3c759a | 4961 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
4962 | reg_val &= 0xffffff00; |
4963 | reg_val |= 0x00000030; | |
ab3c759a | 4964 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4965 | |
ab3c759a | 4966 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4967 | reg_val &= 0x8cffffff; |
4968 | reg_val = 0x8c000000; | |
ab3c759a | 4969 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 4970 | |
ab3c759a | 4971 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 4972 | reg_val &= 0xffffff00; |
ab3c759a | 4973 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4974 | |
ab3c759a | 4975 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4976 | reg_val &= 0x00ffffff; |
4977 | reg_val |= 0xb0000000; | |
ab3c759a | 4978 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
4979 | } |
4980 | ||
b551842d DV |
4981 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4982 | struct intel_link_m_n *m_n) | |
4983 | { | |
4984 | struct drm_device *dev = crtc->base.dev; | |
4985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4986 | int pipe = crtc->pipe; | |
4987 | ||
e3b95f1e DV |
4988 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4989 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4990 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4991 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4992 | } |
4993 | ||
4994 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4995 | struct intel_link_m_n *m_n) | |
4996 | { | |
4997 | struct drm_device *dev = crtc->base.dev; | |
4998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4999 | int pipe = crtc->pipe; | |
5000 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5001 | ||
5002 | if (INTEL_INFO(dev)->gen >= 5) { | |
5003 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5004 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5005 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5006 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5007 | } else { | |
e3b95f1e DV |
5008 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5009 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5010 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5011 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5012 | } |
5013 | } | |
5014 | ||
03afc4a2 DV |
5015 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5016 | { | |
5017 | if (crtc->config.has_pch_encoder) | |
5018 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5019 | else | |
5020 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5021 | } | |
5022 | ||
f47709a9 | 5023 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 5024 | { |
f47709a9 | 5025 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5026 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5027 | int pipe = crtc->pipe; |
89b667f8 | 5028 | u32 dpll, mdiv; |
a0c4da24 | 5029 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 5030 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 5031 | |
09153000 DV |
5032 | mutex_lock(&dev_priv->dpio_lock); |
5033 | ||
f47709a9 DV |
5034 | bestn = crtc->config.dpll.n; |
5035 | bestm1 = crtc->config.dpll.m1; | |
5036 | bestm2 = crtc->config.dpll.m2; | |
5037 | bestp1 = crtc->config.dpll.p1; | |
5038 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5039 | |
89b667f8 JB |
5040 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5041 | ||
5042 | /* PLL B needs special handling */ | |
5043 | if (pipe) | |
5e69f97f | 5044 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5045 | |
5046 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5047 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5048 | |
5049 | /* Disable target IRef on PLL */ | |
ab3c759a | 5050 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5051 | reg_val &= 0x00ffffff; |
ab3c759a | 5052 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5053 | |
5054 | /* Disable fast lock */ | |
ab3c759a | 5055 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5056 | |
5057 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5058 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5059 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5060 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5061 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5062 | |
5063 | /* | |
5064 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5065 | * but we don't support that). | |
5066 | * Note: don't use the DAC post divider as it seems unstable. | |
5067 | */ | |
5068 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5069 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5070 | |
a0c4da24 | 5071 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5072 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5073 | |
89b667f8 | 5074 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5075 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5076 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5077 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5078 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5079 | 0x009f0003); |
89b667f8 | 5080 | else |
ab3c759a | 5081 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5082 | 0x00d0000f); |
5083 | ||
5084 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5085 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5086 | /* Use SSC source */ | |
5087 | if (!pipe) | |
ab3c759a | 5088 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5089 | 0x0df40000); |
5090 | else | |
ab3c759a | 5091 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5092 | 0x0df70000); |
5093 | } else { /* HDMI or VGA */ | |
5094 | /* Use bend source */ | |
5095 | if (!pipe) | |
ab3c759a | 5096 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5097 | 0x0df70000); |
5098 | else | |
ab3c759a | 5099 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5100 | 0x0df40000); |
5101 | } | |
a0c4da24 | 5102 | |
ab3c759a | 5103 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5104 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5105 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5106 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5107 | coreclk |= 0x01000000; | |
ab3c759a | 5108 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5109 | |
ab3c759a | 5110 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 5111 | |
e5cbfbfb ID |
5112 | /* |
5113 | * Enable DPIO clock input. We should never disable the reference | |
5114 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5115 | * on it. | |
5116 | */ | |
89b667f8 JB |
5117 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
5118 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
5119 | /* We should never disable this, set it here for state tracking */ |
5120 | if (pipe == PIPE_B) | |
89b667f8 | 5121 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 5122 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
5123 | crtc->config.dpll_hw_state.dpll = dpll; |
5124 | ||
ef1b460d DV |
5125 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5126 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
5127 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5128 | ||
89b667f8 JB |
5129 | if (crtc->config.has_dp_encoder) |
5130 | intel_dp_set_m_n(crtc); | |
09153000 DV |
5131 | |
5132 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
5133 | } |
5134 | ||
f47709a9 DV |
5135 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5136 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5137 | int num_connectors) |
5138 | { | |
f47709a9 | 5139 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5140 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5141 | u32 dpll; |
5142 | bool is_sdvo; | |
f47709a9 | 5143 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5144 | |
f47709a9 | 5145 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5146 | |
f47709a9 DV |
5147 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5148 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5149 | |
5150 | dpll = DPLL_VGA_MODE_DIS; | |
5151 | ||
f47709a9 | 5152 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5153 | dpll |= DPLLB_MODE_LVDS; |
5154 | else | |
5155 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5156 | |
ef1b460d | 5157 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5158 | dpll |= (crtc->config.pixel_multiplier - 1) |
5159 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5160 | } |
198a037f DV |
5161 | |
5162 | if (is_sdvo) | |
4a33e48d | 5163 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5164 | |
f47709a9 | 5165 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5166 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5167 | |
5168 | /* compute bitmask from p1 value */ | |
5169 | if (IS_PINEVIEW(dev)) | |
5170 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5171 | else { | |
5172 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5173 | if (IS_G4X(dev) && reduced_clock) | |
5174 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5175 | } | |
5176 | switch (clock->p2) { | |
5177 | case 5: | |
5178 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5179 | break; | |
5180 | case 7: | |
5181 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5182 | break; | |
5183 | case 10: | |
5184 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5185 | break; | |
5186 | case 14: | |
5187 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5188 | break; | |
5189 | } | |
5190 | if (INTEL_INFO(dev)->gen >= 4) | |
5191 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5192 | ||
09ede541 | 5193 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5194 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5195 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5196 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5197 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5198 | else | |
5199 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5200 | ||
5201 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5202 | crtc->config.dpll_hw_state.dpll = dpll; |
5203 | ||
eb1cbe48 | 5204 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5205 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5206 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5207 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5208 | } |
66e3d5c0 DV |
5209 | |
5210 | if (crtc->config.has_dp_encoder) | |
5211 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5212 | } |
5213 | ||
f47709a9 | 5214 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5215 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5216 | int num_connectors) |
5217 | { | |
f47709a9 | 5218 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5219 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5220 | u32 dpll; |
f47709a9 | 5221 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5222 | |
f47709a9 | 5223 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5224 | |
eb1cbe48 DV |
5225 | dpll = DPLL_VGA_MODE_DIS; |
5226 | ||
f47709a9 | 5227 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5228 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5229 | } else { | |
5230 | if (clock->p1 == 2) | |
5231 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5232 | else | |
5233 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5234 | if (clock->p2 == 4) | |
5235 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5236 | } | |
5237 | ||
4a33e48d DV |
5238 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5239 | dpll |= DPLL_DVO_2X_MODE; | |
5240 | ||
f47709a9 | 5241 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5242 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5243 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5244 | else | |
5245 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5246 | ||
5247 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5248 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5249 | } |
5250 | ||
8a654f3b | 5251 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5252 | { |
5253 | struct drm_device *dev = intel_crtc->base.dev; | |
5254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5255 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5256 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5257 | struct drm_display_mode *adjusted_mode = |
5258 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5259 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5260 | ||
5261 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5262 | * the hw state checker will get angry at the mismatch. */ | |
5263 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5264 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5265 | |
5266 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5267 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5268 | crtc_vtotal -= 1; |
5269 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5270 | vsyncshift = adjusted_mode->crtc_hsync_start |
5271 | - adjusted_mode->crtc_htotal / 2; | |
5272 | } else { | |
5273 | vsyncshift = 0; | |
5274 | } | |
5275 | ||
5276 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5277 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5278 | |
fe2b8f9d | 5279 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5280 | (adjusted_mode->crtc_hdisplay - 1) | |
5281 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5282 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5283 | (adjusted_mode->crtc_hblank_start - 1) | |
5284 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5285 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5286 | (adjusted_mode->crtc_hsync_start - 1) | |
5287 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5288 | ||
fe2b8f9d | 5289 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5290 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5291 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5292 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5293 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5294 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5295 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5296 | (adjusted_mode->crtc_vsync_start - 1) | |
5297 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5298 | ||
b5e508d4 PZ |
5299 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5300 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5301 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5302 | * bits. */ | |
5303 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5304 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5305 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5306 | ||
b0e77b9c PZ |
5307 | /* pipesrc controls the size that is scaled from, which should |
5308 | * always be the user's requested size. | |
5309 | */ | |
5310 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5311 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5312 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5313 | } |
5314 | ||
1bd1bd80 DV |
5315 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5316 | struct intel_crtc_config *pipe_config) | |
5317 | { | |
5318 | struct drm_device *dev = crtc->base.dev; | |
5319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5320 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5321 | uint32_t tmp; | |
5322 | ||
5323 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5324 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5325 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5326 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5327 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5328 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5329 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5330 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5331 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5332 | ||
5333 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5334 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5335 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5336 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5337 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5338 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5339 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5340 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5341 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5342 | ||
5343 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5344 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5345 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5346 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5347 | } | |
5348 | ||
5349 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5350 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5351 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5352 | ||
5353 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5354 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5355 | } |
5356 | ||
f6a83288 DV |
5357 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5358 | struct intel_crtc_config *pipe_config) | |
babea61d | 5359 | { |
f6a83288 DV |
5360 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5361 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5362 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5363 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5364 | |
f6a83288 DV |
5365 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5366 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5367 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5368 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5369 | |
f6a83288 | 5370 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5371 | |
f6a83288 DV |
5372 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5373 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5374 | } |
5375 | ||
84b046f3 DV |
5376 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5377 | { | |
5378 | struct drm_device *dev = intel_crtc->base.dev; | |
5379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5380 | uint32_t pipeconf; | |
5381 | ||
9f11a9e4 | 5382 | pipeconf = 0; |
84b046f3 | 5383 | |
67c72a12 DV |
5384 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5385 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5386 | pipeconf |= PIPECONF_ENABLE; | |
5387 | ||
cf532bb2 VS |
5388 | if (intel_crtc->config.double_wide) |
5389 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5390 | |
ff9ce46e DV |
5391 | /* only g4x and later have fancy bpc/dither controls */ |
5392 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5393 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5394 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5395 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5396 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5397 | |
ff9ce46e DV |
5398 | switch (intel_crtc->config.pipe_bpp) { |
5399 | case 18: | |
5400 | pipeconf |= PIPECONF_6BPC; | |
5401 | break; | |
5402 | case 24: | |
5403 | pipeconf |= PIPECONF_8BPC; | |
5404 | break; | |
5405 | case 30: | |
5406 | pipeconf |= PIPECONF_10BPC; | |
5407 | break; | |
5408 | default: | |
5409 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5410 | BUG(); | |
84b046f3 DV |
5411 | } |
5412 | } | |
5413 | ||
5414 | if (HAS_PIPE_CXSR(dev)) { | |
5415 | if (intel_crtc->lowfreq_avail) { | |
5416 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5417 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5418 | } else { | |
5419 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5420 | } |
5421 | } | |
5422 | ||
84b046f3 DV |
5423 | if (!IS_GEN2(dev) && |
5424 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5425 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5426 | else | |
5427 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5428 | ||
9f11a9e4 DV |
5429 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5430 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5431 | |
84b046f3 DV |
5432 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5433 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5434 | } | |
5435 | ||
f564048e | 5436 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5437 | int x, int y, |
94352cf9 | 5438 | struct drm_framebuffer *fb) |
79e53945 JB |
5439 | { |
5440 | struct drm_device *dev = crtc->dev; | |
5441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5442 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5443 | int pipe = intel_crtc->pipe; | |
80824003 | 5444 | int plane = intel_crtc->plane; |
c751ce4f | 5445 | int refclk, num_connectors = 0; |
652c393a | 5446 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5447 | u32 dspcntr; |
a16af721 | 5448 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5449 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5450 | struct intel_encoder *encoder; |
d4906093 | 5451 | const intel_limit_t *limit; |
5c3b82e2 | 5452 | int ret; |
79e53945 | 5453 | |
6c2b7c12 | 5454 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5455 | switch (encoder->type) { |
79e53945 JB |
5456 | case INTEL_OUTPUT_LVDS: |
5457 | is_lvds = true; | |
5458 | break; | |
e9fd1c02 JN |
5459 | case INTEL_OUTPUT_DSI: |
5460 | is_dsi = true; | |
5461 | break; | |
79e53945 | 5462 | } |
43565a06 | 5463 | |
c751ce4f | 5464 | num_connectors++; |
79e53945 JB |
5465 | } |
5466 | ||
f2335330 JN |
5467 | if (is_dsi) |
5468 | goto skip_dpll; | |
5469 | ||
5470 | if (!intel_crtc->config.clock_set) { | |
5471 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5472 | |
e9fd1c02 JN |
5473 | /* |
5474 | * Returns a set of divisors for the desired target clock with | |
5475 | * the given refclk, or FALSE. The returned values represent | |
5476 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5477 | * 2) / p1 / p2. | |
5478 | */ | |
5479 | limit = intel_limit(crtc, refclk); | |
5480 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5481 | intel_crtc->config.port_clock, | |
5482 | refclk, NULL, &clock); | |
f2335330 | 5483 | if (!ok) { |
e9fd1c02 JN |
5484 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5485 | return -EINVAL; | |
5486 | } | |
79e53945 | 5487 | |
f2335330 JN |
5488 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5489 | /* | |
5490 | * Ensure we match the reduced clock's P to the target | |
5491 | * clock. If the clocks don't match, we can't switch | |
5492 | * the display clock by using the FP0/FP1. In such case | |
5493 | * we will disable the LVDS downclock feature. | |
5494 | */ | |
5495 | has_reduced_clock = | |
5496 | dev_priv->display.find_dpll(limit, crtc, | |
5497 | dev_priv->lvds_downclock, | |
5498 | refclk, &clock, | |
5499 | &reduced_clock); | |
5500 | } | |
5501 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5502 | intel_crtc->config.dpll.n = clock.n; |
5503 | intel_crtc->config.dpll.m1 = clock.m1; | |
5504 | intel_crtc->config.dpll.m2 = clock.m2; | |
5505 | intel_crtc->config.dpll.p1 = clock.p1; | |
5506 | intel_crtc->config.dpll.p2 = clock.p2; | |
5507 | } | |
7026d4ac | 5508 | |
e9fd1c02 | 5509 | if (IS_GEN2(dev)) { |
8a654f3b | 5510 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5511 | has_reduced_clock ? &reduced_clock : NULL, |
5512 | num_connectors); | |
e9fd1c02 | 5513 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5514 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5515 | } else { |
f47709a9 | 5516 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5517 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5518 | num_connectors); |
e9fd1c02 | 5519 | } |
79e53945 | 5520 | |
f2335330 | 5521 | skip_dpll: |
79e53945 JB |
5522 | /* Set up the display plane register */ |
5523 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5524 | ||
da6ecc5d JB |
5525 | if (!IS_VALLEYVIEW(dev)) { |
5526 | if (pipe == 0) | |
5527 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5528 | else | |
5529 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5530 | } | |
79e53945 | 5531 | |
8a654f3b | 5532 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5533 | |
5534 | /* pipesrc and dspsize control the size that is scaled from, | |
5535 | * which should always be the user's requested size. | |
79e53945 | 5536 | */ |
929c77fb | 5537 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5538 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5539 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5540 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5541 | |
84b046f3 DV |
5542 | i9xx_set_pipeconf(intel_crtc); |
5543 | ||
f564048e EA |
5544 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5545 | POSTING_READ(DSPCNTR(plane)); | |
5546 | ||
94352cf9 | 5547 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5548 | |
f564048e EA |
5549 | return ret; |
5550 | } | |
5551 | ||
2fa2fe9a DV |
5552 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5553 | struct intel_crtc_config *pipe_config) | |
5554 | { | |
5555 | struct drm_device *dev = crtc->base.dev; | |
5556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5557 | uint32_t tmp; | |
5558 | ||
dc9e7dec VS |
5559 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5560 | return; | |
5561 | ||
2fa2fe9a | 5562 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
5563 | if (!(tmp & PFIT_ENABLE)) |
5564 | return; | |
2fa2fe9a | 5565 | |
06922821 | 5566 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5567 | if (INTEL_INFO(dev)->gen < 4) { |
5568 | if (crtc->pipe != PIPE_B) | |
5569 | return; | |
2fa2fe9a DV |
5570 | } else { |
5571 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5572 | return; | |
5573 | } | |
5574 | ||
06922821 | 5575 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5576 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5577 | if (INTEL_INFO(dev)->gen < 5) | |
5578 | pipe_config->gmch_pfit.lvds_border_bits = | |
5579 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5580 | } | |
5581 | ||
acbec814 JB |
5582 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5583 | struct intel_crtc_config *pipe_config) | |
5584 | { | |
5585 | struct drm_device *dev = crtc->base.dev; | |
5586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5587 | int pipe = pipe_config->cpu_transcoder; | |
5588 | intel_clock_t clock; | |
5589 | u32 mdiv; | |
662c6ecb | 5590 | int refclk = 100000; |
acbec814 JB |
5591 | |
5592 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5593 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5594 | mutex_unlock(&dev_priv->dpio_lock); |
5595 | ||
5596 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5597 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5598 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5599 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5600 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5601 | ||
f646628b | 5602 | vlv_clock(refclk, &clock); |
acbec814 | 5603 | |
f646628b VS |
5604 | /* clock.dot is the fast clock */ |
5605 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5606 | } |
5607 | ||
0e8ffe1b DV |
5608 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5609 | struct intel_crtc_config *pipe_config) | |
5610 | { | |
5611 | struct drm_device *dev = crtc->base.dev; | |
5612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5613 | uint32_t tmp; | |
5614 | ||
b5482bd0 ID |
5615 | if (!intel_display_power_enabled(dev_priv, |
5616 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
5617 | return false; | |
5618 | ||
e143a21c | 5619 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5620 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5621 | |
0e8ffe1b DV |
5622 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5623 | if (!(tmp & PIPECONF_ENABLE)) | |
5624 | return false; | |
5625 | ||
42571aef VS |
5626 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5627 | switch (tmp & PIPECONF_BPC_MASK) { | |
5628 | case PIPECONF_6BPC: | |
5629 | pipe_config->pipe_bpp = 18; | |
5630 | break; | |
5631 | case PIPECONF_8BPC: | |
5632 | pipe_config->pipe_bpp = 24; | |
5633 | break; | |
5634 | case PIPECONF_10BPC: | |
5635 | pipe_config->pipe_bpp = 30; | |
5636 | break; | |
5637 | default: | |
5638 | break; | |
5639 | } | |
5640 | } | |
5641 | ||
282740f7 VS |
5642 | if (INTEL_INFO(dev)->gen < 4) |
5643 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5644 | ||
1bd1bd80 DV |
5645 | intel_get_pipe_timings(crtc, pipe_config); |
5646 | ||
2fa2fe9a DV |
5647 | i9xx_get_pfit_config(crtc, pipe_config); |
5648 | ||
6c49f241 DV |
5649 | if (INTEL_INFO(dev)->gen >= 4) { |
5650 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5651 | pipe_config->pixel_multiplier = | |
5652 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5653 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5654 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5655 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5656 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5657 | pipe_config->pixel_multiplier = | |
5658 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5659 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5660 | } else { | |
5661 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5662 | * port and will be fixed up in the encoder->get_config | |
5663 | * function. */ | |
5664 | pipe_config->pixel_multiplier = 1; | |
5665 | } | |
8bcc2795 DV |
5666 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5667 | if (!IS_VALLEYVIEW(dev)) { | |
5668 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5669 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5670 | } else { |
5671 | /* Mask out read-only status bits. */ | |
5672 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5673 | DPLL_PORTC_READY_MASK | | |
5674 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5675 | } |
6c49f241 | 5676 | |
acbec814 JB |
5677 | if (IS_VALLEYVIEW(dev)) |
5678 | vlv_crtc_clock_get(crtc, pipe_config); | |
5679 | else | |
5680 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5681 | |
0e8ffe1b DV |
5682 | return true; |
5683 | } | |
5684 | ||
dde86e2d | 5685 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5686 | { |
5687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5688 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5689 | struct intel_encoder *encoder; |
74cfd7ac | 5690 | u32 val, final; |
13d83a67 | 5691 | bool has_lvds = false; |
199e5d79 | 5692 | bool has_cpu_edp = false; |
199e5d79 | 5693 | bool has_panel = false; |
99eb6a01 KP |
5694 | bool has_ck505 = false; |
5695 | bool can_ssc = false; | |
13d83a67 JB |
5696 | |
5697 | /* We need to take the global config into account */ | |
199e5d79 KP |
5698 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5699 | base.head) { | |
5700 | switch (encoder->type) { | |
5701 | case INTEL_OUTPUT_LVDS: | |
5702 | has_panel = true; | |
5703 | has_lvds = true; | |
5704 | break; | |
5705 | case INTEL_OUTPUT_EDP: | |
5706 | has_panel = true; | |
2de6905f | 5707 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5708 | has_cpu_edp = true; |
5709 | break; | |
13d83a67 JB |
5710 | } |
5711 | } | |
5712 | ||
99eb6a01 | 5713 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5714 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5715 | can_ssc = has_ck505; |
5716 | } else { | |
5717 | has_ck505 = false; | |
5718 | can_ssc = true; | |
5719 | } | |
5720 | ||
2de6905f ID |
5721 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5722 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5723 | |
5724 | /* Ironlake: try to setup display ref clock before DPLL | |
5725 | * enabling. This is only under driver's control after | |
5726 | * PCH B stepping, previous chipset stepping should be | |
5727 | * ignoring this setting. | |
5728 | */ | |
74cfd7ac CW |
5729 | val = I915_READ(PCH_DREF_CONTROL); |
5730 | ||
5731 | /* As we must carefully and slowly disable/enable each source in turn, | |
5732 | * compute the final state we want first and check if we need to | |
5733 | * make any changes at all. | |
5734 | */ | |
5735 | final = val; | |
5736 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5737 | if (has_ck505) | |
5738 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5739 | else | |
5740 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5741 | ||
5742 | final &= ~DREF_SSC_SOURCE_MASK; | |
5743 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5744 | final &= ~DREF_SSC1_ENABLE; | |
5745 | ||
5746 | if (has_panel) { | |
5747 | final |= DREF_SSC_SOURCE_ENABLE; | |
5748 | ||
5749 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5750 | final |= DREF_SSC1_ENABLE; | |
5751 | ||
5752 | if (has_cpu_edp) { | |
5753 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5754 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5755 | else | |
5756 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5757 | } else | |
5758 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5759 | } else { | |
5760 | final |= DREF_SSC_SOURCE_DISABLE; | |
5761 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5762 | } | |
5763 | ||
5764 | if (final == val) | |
5765 | return; | |
5766 | ||
13d83a67 | 5767 | /* Always enable nonspread source */ |
74cfd7ac | 5768 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5769 | |
99eb6a01 | 5770 | if (has_ck505) |
74cfd7ac | 5771 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5772 | else |
74cfd7ac | 5773 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5774 | |
199e5d79 | 5775 | if (has_panel) { |
74cfd7ac CW |
5776 | val &= ~DREF_SSC_SOURCE_MASK; |
5777 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5778 | |
199e5d79 | 5779 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5780 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5781 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5782 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5783 | } else |
74cfd7ac | 5784 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5785 | |
5786 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5787 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5788 | POSTING_READ(PCH_DREF_CONTROL); |
5789 | udelay(200); | |
5790 | ||
74cfd7ac | 5791 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5792 | |
5793 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5794 | if (has_cpu_edp) { |
99eb6a01 | 5795 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5796 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5797 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5798 | } |
13d83a67 | 5799 | else |
74cfd7ac | 5800 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5801 | } else |
74cfd7ac | 5802 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5803 | |
74cfd7ac | 5804 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5805 | POSTING_READ(PCH_DREF_CONTROL); |
5806 | udelay(200); | |
5807 | } else { | |
5808 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5809 | ||
74cfd7ac | 5810 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5811 | |
5812 | /* Turn off CPU output */ | |
74cfd7ac | 5813 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5814 | |
74cfd7ac | 5815 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5816 | POSTING_READ(PCH_DREF_CONTROL); |
5817 | udelay(200); | |
5818 | ||
5819 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5820 | val &= ~DREF_SSC_SOURCE_MASK; |
5821 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5822 | |
5823 | /* Turn off SSC1 */ | |
74cfd7ac | 5824 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5825 | |
74cfd7ac | 5826 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5827 | POSTING_READ(PCH_DREF_CONTROL); |
5828 | udelay(200); | |
5829 | } | |
74cfd7ac CW |
5830 | |
5831 | BUG_ON(val != final); | |
13d83a67 JB |
5832 | } |
5833 | ||
f31f2d55 | 5834 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5835 | { |
f31f2d55 | 5836 | uint32_t tmp; |
dde86e2d | 5837 | |
0ff066a9 PZ |
5838 | tmp = I915_READ(SOUTH_CHICKEN2); |
5839 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5840 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5841 | |
0ff066a9 PZ |
5842 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5843 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5844 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5845 | |
0ff066a9 PZ |
5846 | tmp = I915_READ(SOUTH_CHICKEN2); |
5847 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5848 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5849 | |
0ff066a9 PZ |
5850 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5851 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5852 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5853 | } |
5854 | ||
5855 | /* WaMPhyProgramming:hsw */ | |
5856 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5857 | { | |
5858 | uint32_t tmp; | |
dde86e2d PZ |
5859 | |
5860 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5861 | tmp &= ~(0xFF << 24); | |
5862 | tmp |= (0x12 << 24); | |
5863 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5864 | ||
dde86e2d PZ |
5865 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5866 | tmp |= (1 << 11); | |
5867 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5868 | ||
5869 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5870 | tmp |= (1 << 11); | |
5871 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5872 | ||
dde86e2d PZ |
5873 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5874 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5875 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5876 | ||
5877 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5878 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5879 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5880 | ||
0ff066a9 PZ |
5881 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5882 | tmp &= ~(7 << 13); | |
5883 | tmp |= (5 << 13); | |
5884 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5885 | |
0ff066a9 PZ |
5886 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5887 | tmp &= ~(7 << 13); | |
5888 | tmp |= (5 << 13); | |
5889 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5890 | |
5891 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5892 | tmp &= ~0xFF; | |
5893 | tmp |= 0x1C; | |
5894 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5895 | ||
5896 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5897 | tmp &= ~0xFF; | |
5898 | tmp |= 0x1C; | |
5899 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5900 | ||
5901 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5902 | tmp &= ~(0xFF << 16); | |
5903 | tmp |= (0x1C << 16); | |
5904 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5905 | ||
5906 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5907 | tmp &= ~(0xFF << 16); | |
5908 | tmp |= (0x1C << 16); | |
5909 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5910 | ||
0ff066a9 PZ |
5911 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5912 | tmp |= (1 << 27); | |
5913 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5914 | |
0ff066a9 PZ |
5915 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5916 | tmp |= (1 << 27); | |
5917 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5918 | |
0ff066a9 PZ |
5919 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5920 | tmp &= ~(0xF << 28); | |
5921 | tmp |= (4 << 28); | |
5922 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5923 | |
0ff066a9 PZ |
5924 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5925 | tmp &= ~(0xF << 28); | |
5926 | tmp |= (4 << 28); | |
5927 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5928 | } |
5929 | ||
2fa86a1f PZ |
5930 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5931 | * Programming" based on the parameters passed: | |
5932 | * - Sequence to enable CLKOUT_DP | |
5933 | * - Sequence to enable CLKOUT_DP without spread | |
5934 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5935 | */ | |
5936 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5937 | bool with_fdi) | |
f31f2d55 PZ |
5938 | { |
5939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5940 | uint32_t reg, tmp; |
5941 | ||
5942 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5943 | with_spread = true; | |
5944 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5945 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5946 | with_fdi = false; | |
f31f2d55 PZ |
5947 | |
5948 | mutex_lock(&dev_priv->dpio_lock); | |
5949 | ||
5950 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5951 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5952 | tmp |= SBI_SSCCTL_PATHALT; | |
5953 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5954 | ||
5955 | udelay(24); | |
5956 | ||
2fa86a1f PZ |
5957 | if (with_spread) { |
5958 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5959 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5960 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5961 | |
2fa86a1f PZ |
5962 | if (with_fdi) { |
5963 | lpt_reset_fdi_mphy(dev_priv); | |
5964 | lpt_program_fdi_mphy(dev_priv); | |
5965 | } | |
5966 | } | |
dde86e2d | 5967 | |
2fa86a1f PZ |
5968 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5969 | SBI_GEN0 : SBI_DBUFF0; | |
5970 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5971 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5972 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5973 | |
5974 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5975 | } |
5976 | ||
47701c3b PZ |
5977 | /* Sequence to disable CLKOUT_DP */ |
5978 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5979 | { | |
5980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5981 | uint32_t reg, tmp; | |
5982 | ||
5983 | mutex_lock(&dev_priv->dpio_lock); | |
5984 | ||
5985 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5986 | SBI_GEN0 : SBI_DBUFF0; | |
5987 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5988 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5989 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5990 | ||
5991 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5992 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5993 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5994 | tmp |= SBI_SSCCTL_PATHALT; | |
5995 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5996 | udelay(32); | |
5997 | } | |
5998 | tmp |= SBI_SSCCTL_DISABLE; | |
5999 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6000 | } | |
6001 | ||
6002 | mutex_unlock(&dev_priv->dpio_lock); | |
6003 | } | |
6004 | ||
bf8fa3d3 PZ |
6005 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6006 | { | |
6007 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6008 | struct intel_encoder *encoder; | |
6009 | bool has_vga = false; | |
6010 | ||
6011 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6012 | switch (encoder->type) { | |
6013 | case INTEL_OUTPUT_ANALOG: | |
6014 | has_vga = true; | |
6015 | break; | |
6016 | } | |
6017 | } | |
6018 | ||
47701c3b PZ |
6019 | if (has_vga) |
6020 | lpt_enable_clkout_dp(dev, true, true); | |
6021 | else | |
6022 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6023 | } |
6024 | ||
dde86e2d PZ |
6025 | /* |
6026 | * Initialize reference clocks when the driver loads | |
6027 | */ | |
6028 | void intel_init_pch_refclk(struct drm_device *dev) | |
6029 | { | |
6030 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6031 | ironlake_init_pch_refclk(dev); | |
6032 | else if (HAS_PCH_LPT(dev)) | |
6033 | lpt_init_pch_refclk(dev); | |
6034 | } | |
6035 | ||
d9d444cb JB |
6036 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6037 | { | |
6038 | struct drm_device *dev = crtc->dev; | |
6039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6040 | struct intel_encoder *encoder; | |
d9d444cb JB |
6041 | int num_connectors = 0; |
6042 | bool is_lvds = false; | |
6043 | ||
6c2b7c12 | 6044 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6045 | switch (encoder->type) { |
6046 | case INTEL_OUTPUT_LVDS: | |
6047 | is_lvds = true; | |
6048 | break; | |
d9d444cb JB |
6049 | } |
6050 | num_connectors++; | |
6051 | } | |
6052 | ||
6053 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6054 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6055 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6056 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6057 | } |
6058 | ||
6059 | return 120000; | |
6060 | } | |
6061 | ||
6ff93609 | 6062 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6063 | { |
c8203565 | 6064 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6065 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6066 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6067 | uint32_t val; |
6068 | ||
78114071 | 6069 | val = 0; |
c8203565 | 6070 | |
965e0c48 | 6071 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6072 | case 18: |
dfd07d72 | 6073 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6074 | break; |
6075 | case 24: | |
dfd07d72 | 6076 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6077 | break; |
6078 | case 30: | |
dfd07d72 | 6079 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6080 | break; |
6081 | case 36: | |
dfd07d72 | 6082 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6083 | break; |
6084 | default: | |
cc769b62 PZ |
6085 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6086 | BUG(); | |
c8203565 PZ |
6087 | } |
6088 | ||
d8b32247 | 6089 | if (intel_crtc->config.dither) |
c8203565 PZ |
6090 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6091 | ||
6ff93609 | 6092 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6093 | val |= PIPECONF_INTERLACED_ILK; |
6094 | else | |
6095 | val |= PIPECONF_PROGRESSIVE; | |
6096 | ||
50f3b016 | 6097 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6098 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6099 | |
c8203565 PZ |
6100 | I915_WRITE(PIPECONF(pipe), val); |
6101 | POSTING_READ(PIPECONF(pipe)); | |
6102 | } | |
6103 | ||
86d3efce VS |
6104 | /* |
6105 | * Set up the pipe CSC unit. | |
6106 | * | |
6107 | * Currently only full range RGB to limited range RGB conversion | |
6108 | * is supported, but eventually this should handle various | |
6109 | * RGB<->YCbCr scenarios as well. | |
6110 | */ | |
50f3b016 | 6111 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6112 | { |
6113 | struct drm_device *dev = crtc->dev; | |
6114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6115 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6116 | int pipe = intel_crtc->pipe; | |
6117 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6118 | ||
6119 | /* | |
6120 | * TODO: Check what kind of values actually come out of the pipe | |
6121 | * with these coeff/postoff values and adjust to get the best | |
6122 | * accuracy. Perhaps we even need to take the bpc value into | |
6123 | * consideration. | |
6124 | */ | |
6125 | ||
50f3b016 | 6126 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6127 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6128 | ||
6129 | /* | |
6130 | * GY/GU and RY/RU should be the other way around according | |
6131 | * to BSpec, but reality doesn't agree. Just set them up in | |
6132 | * a way that results in the correct picture. | |
6133 | */ | |
6134 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6135 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6136 | ||
6137 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6138 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6139 | ||
6140 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6141 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6142 | ||
6143 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6144 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6145 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6146 | ||
6147 | if (INTEL_INFO(dev)->gen > 6) { | |
6148 | uint16_t postoff = 0; | |
6149 | ||
50f3b016 | 6150 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6151 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6152 | |
6153 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6154 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6155 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6156 | ||
6157 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6158 | } else { | |
6159 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6160 | ||
50f3b016 | 6161 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6162 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6163 | ||
6164 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6165 | } | |
6166 | } | |
6167 | ||
6ff93609 | 6168 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6169 | { |
756f85cf PZ |
6170 | struct drm_device *dev = crtc->dev; |
6171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6173 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6174 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6175 | uint32_t val; |
6176 | ||
3eff4faa | 6177 | val = 0; |
ee2b0b38 | 6178 | |
756f85cf | 6179 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6180 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6181 | ||
6ff93609 | 6182 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6183 | val |= PIPECONF_INTERLACED_ILK; |
6184 | else | |
6185 | val |= PIPECONF_PROGRESSIVE; | |
6186 | ||
702e7a56 PZ |
6187 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6188 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6189 | |
6190 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6191 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6192 | |
6193 | if (IS_BROADWELL(dev)) { | |
6194 | val = 0; | |
6195 | ||
6196 | switch (intel_crtc->config.pipe_bpp) { | |
6197 | case 18: | |
6198 | val |= PIPEMISC_DITHER_6_BPC; | |
6199 | break; | |
6200 | case 24: | |
6201 | val |= PIPEMISC_DITHER_8_BPC; | |
6202 | break; | |
6203 | case 30: | |
6204 | val |= PIPEMISC_DITHER_10_BPC; | |
6205 | break; | |
6206 | case 36: | |
6207 | val |= PIPEMISC_DITHER_12_BPC; | |
6208 | break; | |
6209 | default: | |
6210 | /* Case prevented by pipe_config_set_bpp. */ | |
6211 | BUG(); | |
6212 | } | |
6213 | ||
6214 | if (intel_crtc->config.dither) | |
6215 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6216 | ||
6217 | I915_WRITE(PIPEMISC(pipe), val); | |
6218 | } | |
ee2b0b38 PZ |
6219 | } |
6220 | ||
6591c6e4 | 6221 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6222 | intel_clock_t *clock, |
6223 | bool *has_reduced_clock, | |
6224 | intel_clock_t *reduced_clock) | |
6225 | { | |
6226 | struct drm_device *dev = crtc->dev; | |
6227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6228 | struct intel_encoder *intel_encoder; | |
6229 | int refclk; | |
d4906093 | 6230 | const intel_limit_t *limit; |
a16af721 | 6231 | bool ret, is_lvds = false; |
79e53945 | 6232 | |
6591c6e4 PZ |
6233 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6234 | switch (intel_encoder->type) { | |
79e53945 JB |
6235 | case INTEL_OUTPUT_LVDS: |
6236 | is_lvds = true; | |
6237 | break; | |
79e53945 JB |
6238 | } |
6239 | } | |
6240 | ||
d9d444cb | 6241 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6242 | |
d4906093 ML |
6243 | /* |
6244 | * Returns a set of divisors for the desired target clock with the given | |
6245 | * refclk, or FALSE. The returned values represent the clock equation: | |
6246 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6247 | */ | |
1b894b59 | 6248 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6249 | ret = dev_priv->display.find_dpll(limit, crtc, |
6250 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6251 | refclk, NULL, clock); |
6591c6e4 PZ |
6252 | if (!ret) |
6253 | return false; | |
cda4b7d3 | 6254 | |
ddc9003c | 6255 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6256 | /* |
6257 | * Ensure we match the reduced clock's P to the target clock. | |
6258 | * If the clocks don't match, we can't switch the display clock | |
6259 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6260 | * downclock feature. | |
6261 | */ | |
ee9300bb DV |
6262 | *has_reduced_clock = |
6263 | dev_priv->display.find_dpll(limit, crtc, | |
6264 | dev_priv->lvds_downclock, | |
6265 | refclk, clock, | |
6266 | reduced_clock); | |
652c393a | 6267 | } |
61e9653f | 6268 | |
6591c6e4 PZ |
6269 | return true; |
6270 | } | |
6271 | ||
d4b1931c PZ |
6272 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6273 | { | |
6274 | /* | |
6275 | * Account for spread spectrum to avoid | |
6276 | * oversubscribing the link. Max center spread | |
6277 | * is 2.5%; use 5% for safety's sake. | |
6278 | */ | |
6279 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6280 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6281 | } |
6282 | ||
7429e9d4 | 6283 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6284 | { |
7429e9d4 | 6285 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6286 | } |
6287 | ||
de13a2e3 | 6288 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6289 | u32 *fp, |
9a7c7890 | 6290 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6291 | { |
de13a2e3 | 6292 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6293 | struct drm_device *dev = crtc->dev; |
6294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6295 | struct intel_encoder *intel_encoder; |
6296 | uint32_t dpll; | |
6cc5f341 | 6297 | int factor, num_connectors = 0; |
09ede541 | 6298 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6299 | |
de13a2e3 PZ |
6300 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6301 | switch (intel_encoder->type) { | |
79e53945 JB |
6302 | case INTEL_OUTPUT_LVDS: |
6303 | is_lvds = true; | |
6304 | break; | |
6305 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6306 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6307 | is_sdvo = true; |
79e53945 | 6308 | break; |
79e53945 | 6309 | } |
43565a06 | 6310 | |
c751ce4f | 6311 | num_connectors++; |
79e53945 | 6312 | } |
79e53945 | 6313 | |
c1858123 | 6314 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6315 | factor = 21; |
6316 | if (is_lvds) { | |
6317 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6318 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6319 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6320 | factor = 25; |
09ede541 | 6321 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6322 | factor = 20; |
c1858123 | 6323 | |
7429e9d4 | 6324 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6325 | *fp |= FP_CB_TUNE; |
2c07245f | 6326 | |
9a7c7890 DV |
6327 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6328 | *fp2 |= FP_CB_TUNE; | |
6329 | ||
5eddb70b | 6330 | dpll = 0; |
2c07245f | 6331 | |
a07d6787 EA |
6332 | if (is_lvds) |
6333 | dpll |= DPLLB_MODE_LVDS; | |
6334 | else | |
6335 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6336 | |
ef1b460d DV |
6337 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6338 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6339 | |
6340 | if (is_sdvo) | |
4a33e48d | 6341 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6342 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6343 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6344 | |
a07d6787 | 6345 | /* compute bitmask from p1 value */ |
7429e9d4 | 6346 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6347 | /* also FPA1 */ |
7429e9d4 | 6348 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6349 | |
7429e9d4 | 6350 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6351 | case 5: |
6352 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6353 | break; | |
6354 | case 7: | |
6355 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6356 | break; | |
6357 | case 10: | |
6358 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6359 | break; | |
6360 | case 14: | |
6361 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6362 | break; | |
79e53945 JB |
6363 | } |
6364 | ||
b4c09f3b | 6365 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6366 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6367 | else |
6368 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6369 | ||
959e16d6 | 6370 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6371 | } |
6372 | ||
6373 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6374 | int x, int y, |
6375 | struct drm_framebuffer *fb) | |
6376 | { | |
6377 | struct drm_device *dev = crtc->dev; | |
6378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6379 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6380 | int pipe = intel_crtc->pipe; | |
6381 | int plane = intel_crtc->plane; | |
6382 | int num_connectors = 0; | |
6383 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6384 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6385 | bool ok, has_reduced_clock = false; |
8b47047b | 6386 | bool is_lvds = false; |
de13a2e3 | 6387 | struct intel_encoder *encoder; |
e2b78267 | 6388 | struct intel_shared_dpll *pll; |
de13a2e3 | 6389 | int ret; |
de13a2e3 PZ |
6390 | |
6391 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6392 | switch (encoder->type) { | |
6393 | case INTEL_OUTPUT_LVDS: | |
6394 | is_lvds = true; | |
6395 | break; | |
de13a2e3 PZ |
6396 | } |
6397 | ||
6398 | num_connectors++; | |
a07d6787 | 6399 | } |
79e53945 | 6400 | |
5dc5298b PZ |
6401 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6402 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6403 | |
ff9a6750 | 6404 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6405 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6406 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6407 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6408 | return -EINVAL; | |
79e53945 | 6409 | } |
f47709a9 DV |
6410 | /* Compat-code for transition, will disappear. */ |
6411 | if (!intel_crtc->config.clock_set) { | |
6412 | intel_crtc->config.dpll.n = clock.n; | |
6413 | intel_crtc->config.dpll.m1 = clock.m1; | |
6414 | intel_crtc->config.dpll.m2 = clock.m2; | |
6415 | intel_crtc->config.dpll.p1 = clock.p1; | |
6416 | intel_crtc->config.dpll.p2 = clock.p2; | |
6417 | } | |
79e53945 | 6418 | |
5dc5298b | 6419 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6420 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6421 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6422 | if (has_reduced_clock) |
7429e9d4 | 6423 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6424 | |
7429e9d4 | 6425 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6426 | &fp, &reduced_clock, |
6427 | has_reduced_clock ? &fp2 : NULL); | |
6428 | ||
959e16d6 | 6429 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6430 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6431 | if (has_reduced_clock) | |
6432 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6433 | else | |
6434 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6435 | ||
b89a1d39 | 6436 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6437 | if (pll == NULL) { |
84f44ce7 VS |
6438 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6439 | pipe_name(pipe)); | |
4b645f14 JB |
6440 | return -EINVAL; |
6441 | } | |
ee7b9f93 | 6442 | } else |
e72f9fbf | 6443 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6444 | |
03afc4a2 DV |
6445 | if (intel_crtc->config.has_dp_encoder) |
6446 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6447 | |
d330a953 | 6448 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
6449 | intel_crtc->lowfreq_avail = true; |
6450 | else | |
6451 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6452 | |
8a654f3b | 6453 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6454 | |
ca3a0ff8 | 6455 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6456 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6457 | &intel_crtc->config.fdi_m_n); | |
6458 | } | |
2c07245f | 6459 | |
6ff93609 | 6460 | ironlake_set_pipeconf(crtc); |
79e53945 | 6461 | |
a1f9e77e PZ |
6462 | /* Set up the display plane register */ |
6463 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6464 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6465 | |
94352cf9 | 6466 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6467 | |
1857e1da | 6468 | return ret; |
79e53945 JB |
6469 | } |
6470 | ||
eb14cb74 VS |
6471 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6472 | struct intel_link_m_n *m_n) | |
6473 | { | |
6474 | struct drm_device *dev = crtc->base.dev; | |
6475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6476 | enum pipe pipe = crtc->pipe; | |
6477 | ||
6478 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6479 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6480 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6481 | & ~TU_SIZE_MASK; | |
6482 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6483 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6484 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6485 | } | |
6486 | ||
6487 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6488 | enum transcoder transcoder, | |
6489 | struct intel_link_m_n *m_n) | |
72419203 DV |
6490 | { |
6491 | struct drm_device *dev = crtc->base.dev; | |
6492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6493 | enum pipe pipe = crtc->pipe; |
72419203 | 6494 | |
eb14cb74 VS |
6495 | if (INTEL_INFO(dev)->gen >= 5) { |
6496 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6497 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6498 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6499 | & ~TU_SIZE_MASK; | |
6500 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6501 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6502 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6503 | } else { | |
6504 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6505 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6506 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6507 | & ~TU_SIZE_MASK; | |
6508 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6509 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6510 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6511 | } | |
6512 | } | |
6513 | ||
6514 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6515 | struct intel_crtc_config *pipe_config) | |
6516 | { | |
6517 | if (crtc->config.has_pch_encoder) | |
6518 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6519 | else | |
6520 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6521 | &pipe_config->dp_m_n); | |
6522 | } | |
72419203 | 6523 | |
eb14cb74 VS |
6524 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6525 | struct intel_crtc_config *pipe_config) | |
6526 | { | |
6527 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6528 | &pipe_config->fdi_m_n); | |
72419203 DV |
6529 | } |
6530 | ||
2fa2fe9a DV |
6531 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6532 | struct intel_crtc_config *pipe_config) | |
6533 | { | |
6534 | struct drm_device *dev = crtc->base.dev; | |
6535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6536 | uint32_t tmp; | |
6537 | ||
6538 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6539 | ||
6540 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6541 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6542 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6543 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6544 | |
6545 | /* We currently do not free assignements of panel fitters on | |
6546 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6547 | * differentiates them) so just WARN about this case for now. */ | |
6548 | if (IS_GEN7(dev)) { | |
6549 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6550 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6551 | } | |
2fa2fe9a | 6552 | } |
79e53945 JB |
6553 | } |
6554 | ||
0e8ffe1b DV |
6555 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6556 | struct intel_crtc_config *pipe_config) | |
6557 | { | |
6558 | struct drm_device *dev = crtc->base.dev; | |
6559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6560 | uint32_t tmp; | |
6561 | ||
e143a21c | 6562 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6563 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6564 | |
0e8ffe1b DV |
6565 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6566 | if (!(tmp & PIPECONF_ENABLE)) | |
6567 | return false; | |
6568 | ||
42571aef VS |
6569 | switch (tmp & PIPECONF_BPC_MASK) { |
6570 | case PIPECONF_6BPC: | |
6571 | pipe_config->pipe_bpp = 18; | |
6572 | break; | |
6573 | case PIPECONF_8BPC: | |
6574 | pipe_config->pipe_bpp = 24; | |
6575 | break; | |
6576 | case PIPECONF_10BPC: | |
6577 | pipe_config->pipe_bpp = 30; | |
6578 | break; | |
6579 | case PIPECONF_12BPC: | |
6580 | pipe_config->pipe_bpp = 36; | |
6581 | break; | |
6582 | default: | |
6583 | break; | |
6584 | } | |
6585 | ||
ab9412ba | 6586 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6587 | struct intel_shared_dpll *pll; |
6588 | ||
88adfff1 DV |
6589 | pipe_config->has_pch_encoder = true; |
6590 | ||
627eb5a3 DV |
6591 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6592 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6593 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6594 | |
6595 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6596 | |
c0d43d62 | 6597 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6598 | pipe_config->shared_dpll = |
6599 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6600 | } else { |
6601 | tmp = I915_READ(PCH_DPLL_SEL); | |
6602 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6603 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6604 | else | |
6605 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6606 | } | |
66e985c0 DV |
6607 | |
6608 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6609 | ||
6610 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6611 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6612 | |
6613 | tmp = pipe_config->dpll_hw_state.dpll; | |
6614 | pipe_config->pixel_multiplier = | |
6615 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6616 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6617 | |
6618 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6619 | } else { |
6620 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6621 | } |
6622 | ||
1bd1bd80 DV |
6623 | intel_get_pipe_timings(crtc, pipe_config); |
6624 | ||
2fa2fe9a DV |
6625 | ironlake_get_pfit_config(crtc, pipe_config); |
6626 | ||
0e8ffe1b DV |
6627 | return true; |
6628 | } | |
6629 | ||
be256dc7 PZ |
6630 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6631 | { | |
6632 | struct drm_device *dev = dev_priv->dev; | |
6633 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6634 | struct intel_crtc *crtc; | |
6635 | unsigned long irqflags; | |
bd633a7c | 6636 | uint32_t val; |
be256dc7 PZ |
6637 | |
6638 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
798183c5 | 6639 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
6640 | pipe_name(crtc->pipe)); |
6641 | ||
6642 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6643 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6644 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6645 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6646 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6647 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6648 | "CPU PWM1 enabled\n"); | |
6649 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6650 | "CPU PWM2 enabled\n"); | |
6651 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6652 | "PCH PWM1 enabled\n"); | |
6653 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6654 | "Utility pin enabled\n"); | |
6655 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6656 | ||
6657 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6658 | val = I915_READ(DEIMR); | |
6806e63f | 6659 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
be256dc7 PZ |
6660 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6661 | val = I915_READ(SDEIMR); | |
bd633a7c | 6662 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6663 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6664 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6665 | } | |
6666 | ||
6667 | /* | |
6668 | * This function implements pieces of two sequences from BSpec: | |
6669 | * - Sequence for display software to disable LCPLL | |
6670 | * - Sequence for display software to allow package C8+ | |
6671 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6672 | * register. Callers should take care of disabling all the display engine | |
6673 | * functions, doing the mode unset, fixing interrupts, etc. | |
6674 | */ | |
6ff58d53 PZ |
6675 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6676 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6677 | { |
6678 | uint32_t val; | |
6679 | ||
6680 | assert_can_disable_lcpll(dev_priv); | |
6681 | ||
6682 | val = I915_READ(LCPLL_CTL); | |
6683 | ||
6684 | if (switch_to_fclk) { | |
6685 | val |= LCPLL_CD_SOURCE_FCLK; | |
6686 | I915_WRITE(LCPLL_CTL, val); | |
6687 | ||
6688 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6689 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6690 | DRM_ERROR("Switching to FCLK failed\n"); | |
6691 | ||
6692 | val = I915_READ(LCPLL_CTL); | |
6693 | } | |
6694 | ||
6695 | val |= LCPLL_PLL_DISABLE; | |
6696 | I915_WRITE(LCPLL_CTL, val); | |
6697 | POSTING_READ(LCPLL_CTL); | |
6698 | ||
6699 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6700 | DRM_ERROR("LCPLL still locked\n"); | |
6701 | ||
6702 | val = I915_READ(D_COMP); | |
6703 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6704 | mutex_lock(&dev_priv->rps.hw_lock); |
6705 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6706 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6707 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6708 | POSTING_READ(D_COMP); |
6709 | ndelay(100); | |
6710 | ||
6711 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6712 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6713 | ||
6714 | if (allow_power_down) { | |
6715 | val = I915_READ(LCPLL_CTL); | |
6716 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6717 | I915_WRITE(LCPLL_CTL, val); | |
6718 | POSTING_READ(LCPLL_CTL); | |
6719 | } | |
6720 | } | |
6721 | ||
6722 | /* | |
6723 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6724 | * source. | |
6725 | */ | |
6ff58d53 | 6726 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6727 | { |
6728 | uint32_t val; | |
6729 | ||
6730 | val = I915_READ(LCPLL_CTL); | |
6731 | ||
6732 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6733 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6734 | return; | |
6735 | ||
215733fa PZ |
6736 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6737 | * we'll hang the machine! */ | |
0d9d349d | 6738 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 6739 | |
be256dc7 PZ |
6740 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6741 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6742 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6743 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6744 | } |
6745 | ||
6746 | val = I915_READ(D_COMP); | |
6747 | val |= D_COMP_COMP_FORCE; | |
6748 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6749 | mutex_lock(&dev_priv->rps.hw_lock); |
6750 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6751 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6752 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6753 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6754 | |
6755 | val = I915_READ(LCPLL_CTL); | |
6756 | val &= ~LCPLL_PLL_DISABLE; | |
6757 | I915_WRITE(LCPLL_CTL, val); | |
6758 | ||
6759 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6760 | DRM_ERROR("LCPLL not locked yet\n"); | |
6761 | ||
6762 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6763 | val = I915_READ(LCPLL_CTL); | |
6764 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6765 | I915_WRITE(LCPLL_CTL, val); | |
6766 | ||
6767 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6768 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6769 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6770 | } | |
215733fa | 6771 | |
0d9d349d | 6772 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
6773 | } |
6774 | ||
c67a470b PZ |
6775 | void hsw_enable_pc8_work(struct work_struct *__work) |
6776 | { | |
6777 | struct drm_i915_private *dev_priv = | |
6778 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6779 | pc8.enable_work); | |
6780 | struct drm_device *dev = dev_priv->dev; | |
6781 | uint32_t val; | |
6782 | ||
7125ecb8 PZ |
6783 | WARN_ON(!HAS_PC8(dev)); |
6784 | ||
c67a470b PZ |
6785 | if (dev_priv->pc8.enabled) |
6786 | return; | |
6787 | ||
6788 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6789 | ||
6790 | dev_priv->pc8.enabled = true; | |
6791 | ||
6792 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6793 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6794 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6795 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6796 | } | |
6797 | ||
6798 | lpt_disable_clkout_dp(dev); | |
6799 | hsw_pc8_disable_interrupts(dev); | |
6800 | hsw_disable_lcpll(dev_priv, true, true); | |
8771a7f8 PZ |
6801 | |
6802 | intel_runtime_pm_put(dev_priv); | |
c67a470b PZ |
6803 | } |
6804 | ||
6805 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6806 | { | |
6807 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6808 | WARN(dev_priv->pc8.disable_count < 1, | |
6809 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6810 | ||
6811 | dev_priv->pc8.disable_count--; | |
6812 | if (dev_priv->pc8.disable_count != 0) | |
6813 | return; | |
6814 | ||
6815 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
d330a953 | 6816 | msecs_to_jiffies(i915.pc8_timeout)); |
c67a470b PZ |
6817 | } |
6818 | ||
6819 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6820 | { | |
6821 | struct drm_device *dev = dev_priv->dev; | |
6822 | uint32_t val; | |
6823 | ||
6824 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6825 | WARN(dev_priv->pc8.disable_count < 0, | |
6826 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6827 | ||
6828 | dev_priv->pc8.disable_count++; | |
6829 | if (dev_priv->pc8.disable_count != 1) | |
6830 | return; | |
6831 | ||
7125ecb8 PZ |
6832 | WARN_ON(!HAS_PC8(dev)); |
6833 | ||
c67a470b PZ |
6834 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6835 | if (!dev_priv->pc8.enabled) | |
6836 | return; | |
6837 | ||
6838 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6839 | ||
8771a7f8 PZ |
6840 | intel_runtime_pm_get(dev_priv); |
6841 | ||
c67a470b PZ |
6842 | hsw_restore_lcpll(dev_priv); |
6843 | hsw_pc8_restore_interrupts(dev); | |
6844 | lpt_init_pch_refclk(dev); | |
6845 | ||
6846 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6847 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6848 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6849 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6850 | } | |
6851 | ||
6852 | intel_prepare_ddi(dev); | |
6853 | i915_gem_init_swizzling(dev); | |
6854 | mutex_lock(&dev_priv->rps.hw_lock); | |
6855 | gen6_update_ring_freq(dev); | |
6856 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6857 | dev_priv->pc8.enabled = false; | |
6858 | } | |
6859 | ||
6860 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6861 | { | |
7c6c2652 CW |
6862 | if (!HAS_PC8(dev_priv->dev)) |
6863 | return; | |
6864 | ||
c67a470b PZ |
6865 | mutex_lock(&dev_priv->pc8.lock); |
6866 | __hsw_enable_package_c8(dev_priv); | |
6867 | mutex_unlock(&dev_priv->pc8.lock); | |
6868 | } | |
6869 | ||
6870 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6871 | { | |
7c6c2652 CW |
6872 | if (!HAS_PC8(dev_priv->dev)) |
6873 | return; | |
6874 | ||
c67a470b PZ |
6875 | mutex_lock(&dev_priv->pc8.lock); |
6876 | __hsw_disable_package_c8(dev_priv); | |
6877 | mutex_unlock(&dev_priv->pc8.lock); | |
6878 | } | |
6879 | ||
6880 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6881 | { | |
6882 | struct drm_device *dev = dev_priv->dev; | |
6883 | struct intel_crtc *crtc; | |
6884 | uint32_t val; | |
6885 | ||
6886 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6887 | if (crtc->base.enabled) | |
6888 | return false; | |
6889 | ||
6890 | /* This case is still possible since we have the i915.disable_power_well | |
6891 | * parameter and also the KVMr or something else might be requesting the | |
6892 | * power well. */ | |
6893 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6894 | if (val != 0) { | |
6895 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6896 | return false; | |
6897 | } | |
6898 | ||
6899 | return true; | |
6900 | } | |
6901 | ||
6902 | /* Since we're called from modeset_global_resources there's no way to | |
6903 | * symmetrically increase and decrease the refcount, so we use | |
6904 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6905 | * or not. | |
6906 | */ | |
6907 | static void hsw_update_package_c8(struct drm_device *dev) | |
6908 | { | |
6909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6910 | bool allow; | |
6911 | ||
7c6c2652 CW |
6912 | if (!HAS_PC8(dev_priv->dev)) |
6913 | return; | |
6914 | ||
d330a953 | 6915 | if (!i915.enable_pc8) |
c67a470b PZ |
6916 | return; |
6917 | ||
6918 | mutex_lock(&dev_priv->pc8.lock); | |
6919 | ||
6920 | allow = hsw_can_enable_package_c8(dev_priv); | |
6921 | ||
6922 | if (allow == dev_priv->pc8.requirements_met) | |
6923 | goto done; | |
6924 | ||
6925 | dev_priv->pc8.requirements_met = allow; | |
6926 | ||
6927 | if (allow) | |
6928 | __hsw_enable_package_c8(dev_priv); | |
6929 | else | |
6930 | __hsw_disable_package_c8(dev_priv); | |
6931 | ||
6932 | done: | |
6933 | mutex_unlock(&dev_priv->pc8.lock); | |
6934 | } | |
6935 | ||
4f074129 ID |
6936 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6937 | { | |
da723569 | 6938 | modeset_update_crtc_power_domains(dev); |
c67a470b | 6939 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
6940 | } |
6941 | ||
09b4ddf9 | 6942 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6943 | int x, int y, |
6944 | struct drm_framebuffer *fb) | |
6945 | { | |
6946 | struct drm_device *dev = crtc->dev; | |
6947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6949 | int plane = intel_crtc->plane; |
09b4ddf9 | 6950 | int ret; |
09b4ddf9 | 6951 | |
566b734a | 6952 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 6953 | return -EINVAL; |
566b734a | 6954 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 6955 | |
03afc4a2 DV |
6956 | if (intel_crtc->config.has_dp_encoder) |
6957 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6958 | |
6959 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6960 | |
8a654f3b | 6961 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6962 | |
ca3a0ff8 | 6963 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6964 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6965 | &intel_crtc->config.fdi_m_n); | |
6966 | } | |
09b4ddf9 | 6967 | |
6ff93609 | 6968 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6969 | |
50f3b016 | 6970 | intel_set_pipe_csc(crtc); |
86d3efce | 6971 | |
09b4ddf9 | 6972 | /* Set up the display plane register */ |
86d3efce | 6973 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6974 | POSTING_READ(DSPCNTR(plane)); |
6975 | ||
6976 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6977 | ||
1f803ee5 | 6978 | return ret; |
79e53945 JB |
6979 | } |
6980 | ||
0e8ffe1b DV |
6981 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6982 | struct intel_crtc_config *pipe_config) | |
6983 | { | |
6984 | struct drm_device *dev = crtc->base.dev; | |
6985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6986 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6987 | uint32_t tmp; |
6988 | ||
b5482bd0 ID |
6989 | if (!intel_display_power_enabled(dev_priv, |
6990 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6991 | return false; | |
6992 | ||
e143a21c | 6993 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6994 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6995 | ||
eccb140b DV |
6996 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6997 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6998 | enum pipe trans_edp_pipe; | |
6999 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7000 | default: | |
7001 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7002 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7003 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7004 | trans_edp_pipe = PIPE_A; | |
7005 | break; | |
7006 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7007 | trans_edp_pipe = PIPE_B; | |
7008 | break; | |
7009 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7010 | trans_edp_pipe = PIPE_C; | |
7011 | break; | |
7012 | } | |
7013 | ||
7014 | if (trans_edp_pipe == crtc->pipe) | |
7015 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7016 | } | |
7017 | ||
da7e29bd | 7018 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7019 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7020 | return false; |
7021 | ||
eccb140b | 7022 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7023 | if (!(tmp & PIPECONF_ENABLE)) |
7024 | return false; | |
7025 | ||
88adfff1 | 7026 | /* |
f196e6be | 7027 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7028 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7029 | * the PCH transcoder is on. | |
7030 | */ | |
eccb140b | 7031 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7032 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7033 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7034 | pipe_config->has_pch_encoder = true; |
7035 | ||
627eb5a3 DV |
7036 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7037 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7038 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7039 | |
7040 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7041 | } |
7042 | ||
1bd1bd80 DV |
7043 | intel_get_pipe_timings(crtc, pipe_config); |
7044 | ||
2fa2fe9a | 7045 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7046 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7047 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7048 | |
e59150dc JB |
7049 | if (IS_HASWELL(dev)) |
7050 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7051 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7052 | |
6c49f241 DV |
7053 | pipe_config->pixel_multiplier = 1; |
7054 | ||
0e8ffe1b DV |
7055 | return true; |
7056 | } | |
7057 | ||
f564048e | 7058 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 7059 | int x, int y, |
94352cf9 | 7060 | struct drm_framebuffer *fb) |
f564048e EA |
7061 | { |
7062 | struct drm_device *dev = crtc->dev; | |
7063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 7064 | struct intel_encoder *encoder; |
0b701d27 | 7065 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 7066 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 7067 | int pipe = intel_crtc->pipe; |
f564048e EA |
7068 | int ret; |
7069 | ||
0b701d27 | 7070 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 7071 | |
b8cecdf5 DV |
7072 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
7073 | ||
79e53945 | 7074 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 7075 | |
9256aa19 DV |
7076 | if (ret != 0) |
7077 | return ret; | |
7078 | ||
7079 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7080 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
7081 | encoder->base.base.id, | |
7082 | drm_get_encoder_name(&encoder->base), | |
7083 | mode->base.id, mode->name); | |
36f2d1f1 | 7084 | encoder->mode_set(encoder); |
9256aa19 DV |
7085 | } |
7086 | ||
7087 | return 0; | |
79e53945 JB |
7088 | } |
7089 | ||
1a91510d JN |
7090 | static struct { |
7091 | int clock; | |
7092 | u32 config; | |
7093 | } hdmi_audio_clock[] = { | |
7094 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7095 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7096 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7097 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7098 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7099 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7100 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7101 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7102 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7103 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7104 | }; | |
7105 | ||
7106 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7107 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7108 | { | |
7109 | int i; | |
7110 | ||
7111 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7112 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7113 | break; | |
7114 | } | |
7115 | ||
7116 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7117 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7118 | i = 1; | |
7119 | } | |
7120 | ||
7121 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7122 | hdmi_audio_clock[i].clock, | |
7123 | hdmi_audio_clock[i].config); | |
7124 | ||
7125 | return hdmi_audio_clock[i].config; | |
7126 | } | |
7127 | ||
3a9627f4 WF |
7128 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7129 | int reg_eldv, uint32_t bits_eldv, | |
7130 | int reg_elda, uint32_t bits_elda, | |
7131 | int reg_edid) | |
7132 | { | |
7133 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7134 | uint8_t *eld = connector->eld; | |
7135 | uint32_t i; | |
7136 | ||
7137 | i = I915_READ(reg_eldv); | |
7138 | i &= bits_eldv; | |
7139 | ||
7140 | if (!eld[0]) | |
7141 | return !i; | |
7142 | ||
7143 | if (!i) | |
7144 | return false; | |
7145 | ||
7146 | i = I915_READ(reg_elda); | |
7147 | i &= ~bits_elda; | |
7148 | I915_WRITE(reg_elda, i); | |
7149 | ||
7150 | for (i = 0; i < eld[2]; i++) | |
7151 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7152 | return false; | |
7153 | ||
7154 | return true; | |
7155 | } | |
7156 | ||
e0dac65e | 7157 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7158 | struct drm_crtc *crtc, |
7159 | struct drm_display_mode *mode) | |
e0dac65e WF |
7160 | { |
7161 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7162 | uint8_t *eld = connector->eld; | |
7163 | uint32_t eldv; | |
7164 | uint32_t len; | |
7165 | uint32_t i; | |
7166 | ||
7167 | i = I915_READ(G4X_AUD_VID_DID); | |
7168 | ||
7169 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7170 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7171 | else | |
7172 | eldv = G4X_ELDV_DEVCTG; | |
7173 | ||
3a9627f4 WF |
7174 | if (intel_eld_uptodate(connector, |
7175 | G4X_AUD_CNTL_ST, eldv, | |
7176 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7177 | G4X_HDMIW_HDMIEDID)) | |
7178 | return; | |
7179 | ||
e0dac65e WF |
7180 | i = I915_READ(G4X_AUD_CNTL_ST); |
7181 | i &= ~(eldv | G4X_ELD_ADDR); | |
7182 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7183 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7184 | ||
7185 | if (!eld[0]) | |
7186 | return; | |
7187 | ||
7188 | len = min_t(uint8_t, eld[2], len); | |
7189 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7190 | for (i = 0; i < len; i++) | |
7191 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7192 | ||
7193 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7194 | i |= eldv; | |
7195 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7196 | } | |
7197 | ||
83358c85 | 7198 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7199 | struct drm_crtc *crtc, |
7200 | struct drm_display_mode *mode) | |
83358c85 WX |
7201 | { |
7202 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7203 | uint8_t *eld = connector->eld; | |
7204 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7206 | uint32_t eldv; |
7207 | uint32_t i; | |
7208 | int len; | |
7209 | int pipe = to_intel_crtc(crtc)->pipe; | |
7210 | int tmp; | |
7211 | ||
7212 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7213 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7214 | int aud_config = HSW_AUD_CFG(pipe); | |
7215 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7216 | ||
7217 | ||
7218 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7219 | ||
7220 | /* Audio output enable */ | |
7221 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7222 | tmp = I915_READ(aud_cntrl_st2); | |
7223 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7224 | I915_WRITE(aud_cntrl_st2, tmp); | |
7225 | ||
7226 | /* Wait for 1 vertical blank */ | |
7227 | intel_wait_for_vblank(dev, pipe); | |
7228 | ||
7229 | /* Set ELD valid state */ | |
7230 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7231 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7232 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7233 | I915_WRITE(aud_cntrl_st2, tmp); | |
7234 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7235 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7236 | |
7237 | /* Enable HDMI mode */ | |
7238 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7239 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7240 | /* clear N_programing_enable and N_value_index */ |
7241 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7242 | I915_WRITE(aud_config, tmp); | |
7243 | ||
7244 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7245 | ||
7246 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7247 | intel_crtc->eld_vld = true; |
83358c85 WX |
7248 | |
7249 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7250 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7251 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7252 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7253 | } else { |
7254 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7255 | } | |
83358c85 WX |
7256 | |
7257 | if (intel_eld_uptodate(connector, | |
7258 | aud_cntrl_st2, eldv, | |
7259 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7260 | hdmiw_hdmiedid)) | |
7261 | return; | |
7262 | ||
7263 | i = I915_READ(aud_cntrl_st2); | |
7264 | i &= ~eldv; | |
7265 | I915_WRITE(aud_cntrl_st2, i); | |
7266 | ||
7267 | if (!eld[0]) | |
7268 | return; | |
7269 | ||
7270 | i = I915_READ(aud_cntl_st); | |
7271 | i &= ~IBX_ELD_ADDRESS; | |
7272 | I915_WRITE(aud_cntl_st, i); | |
7273 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7274 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7275 | ||
7276 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7277 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7278 | for (i = 0; i < len; i++) | |
7279 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7280 | ||
7281 | i = I915_READ(aud_cntrl_st2); | |
7282 | i |= eldv; | |
7283 | I915_WRITE(aud_cntrl_st2, i); | |
7284 | ||
7285 | } | |
7286 | ||
e0dac65e | 7287 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7288 | struct drm_crtc *crtc, |
7289 | struct drm_display_mode *mode) | |
e0dac65e WF |
7290 | { |
7291 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7292 | uint8_t *eld = connector->eld; | |
7293 | uint32_t eldv; | |
7294 | uint32_t i; | |
7295 | int len; | |
7296 | int hdmiw_hdmiedid; | |
b6daa025 | 7297 | int aud_config; |
e0dac65e WF |
7298 | int aud_cntl_st; |
7299 | int aud_cntrl_st2; | |
9b138a83 | 7300 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7301 | |
b3f33cbf | 7302 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7303 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7304 | aud_config = IBX_AUD_CFG(pipe); | |
7305 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7306 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7307 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7308 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7309 | aud_config = VLV_AUD_CFG(pipe); | |
7310 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7311 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7312 | } else { |
9b138a83 WX |
7313 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7314 | aud_config = CPT_AUD_CFG(pipe); | |
7315 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7316 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7317 | } |
7318 | ||
9b138a83 | 7319 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7320 | |
9ca2fe73 ML |
7321 | if (IS_VALLEYVIEW(connector->dev)) { |
7322 | struct intel_encoder *intel_encoder; | |
7323 | struct intel_digital_port *intel_dig_port; | |
7324 | ||
7325 | intel_encoder = intel_attached_encoder(connector); | |
7326 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7327 | i = intel_dig_port->port; | |
7328 | } else { | |
7329 | i = I915_READ(aud_cntl_st); | |
7330 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7331 | /* DIP_Port_Select, 0x1 = PortB */ | |
7332 | } | |
7333 | ||
e0dac65e WF |
7334 | if (!i) { |
7335 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7336 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7337 | eldv = IBX_ELD_VALIDB; |
7338 | eldv |= IBX_ELD_VALIDB << 4; | |
7339 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7340 | } else { |
2582a850 | 7341 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7342 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7343 | } |
7344 | ||
3a9627f4 WF |
7345 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7346 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7347 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7348 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7349 | } else { |
7350 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7351 | } | |
e0dac65e | 7352 | |
3a9627f4 WF |
7353 | if (intel_eld_uptodate(connector, |
7354 | aud_cntrl_st2, eldv, | |
7355 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7356 | hdmiw_hdmiedid)) | |
7357 | return; | |
7358 | ||
e0dac65e WF |
7359 | i = I915_READ(aud_cntrl_st2); |
7360 | i &= ~eldv; | |
7361 | I915_WRITE(aud_cntrl_st2, i); | |
7362 | ||
7363 | if (!eld[0]) | |
7364 | return; | |
7365 | ||
e0dac65e | 7366 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7367 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7368 | I915_WRITE(aud_cntl_st, i); |
7369 | ||
7370 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7371 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7372 | for (i = 0; i < len; i++) | |
7373 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7374 | ||
7375 | i = I915_READ(aud_cntrl_st2); | |
7376 | i |= eldv; | |
7377 | I915_WRITE(aud_cntrl_st2, i); | |
7378 | } | |
7379 | ||
7380 | void intel_write_eld(struct drm_encoder *encoder, | |
7381 | struct drm_display_mode *mode) | |
7382 | { | |
7383 | struct drm_crtc *crtc = encoder->crtc; | |
7384 | struct drm_connector *connector; | |
7385 | struct drm_device *dev = encoder->dev; | |
7386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7387 | ||
7388 | connector = drm_select_eld(encoder, mode); | |
7389 | if (!connector) | |
7390 | return; | |
7391 | ||
7392 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7393 | connector->base.id, | |
7394 | drm_get_connector_name(connector), | |
7395 | connector->encoder->base.id, | |
7396 | drm_get_encoder_name(connector->encoder)); | |
7397 | ||
7398 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7399 | ||
7400 | if (dev_priv->display.write_eld) | |
34427052 | 7401 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7402 | } |
7403 | ||
560b85bb CW |
7404 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7405 | { | |
7406 | struct drm_device *dev = crtc->dev; | |
7407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7409 | bool visible = base != 0; | |
7410 | u32 cntl; | |
7411 | ||
7412 | if (intel_crtc->cursor_visible == visible) | |
7413 | return; | |
7414 | ||
9db4a9c7 | 7415 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7416 | if (visible) { |
7417 | /* On these chipsets we can only modify the base whilst | |
7418 | * the cursor is disabled. | |
7419 | */ | |
9db4a9c7 | 7420 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7421 | |
7422 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7423 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7424 | cntl |= CURSOR_ENABLE | | |
7425 | CURSOR_GAMMA_ENABLE | | |
7426 | CURSOR_FORMAT_ARGB; | |
7427 | } else | |
7428 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7429 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7430 | |
7431 | intel_crtc->cursor_visible = visible; | |
7432 | } | |
7433 | ||
7434 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7435 | { | |
7436 | struct drm_device *dev = crtc->dev; | |
7437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7438 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7439 | int pipe = intel_crtc->pipe; | |
7440 | bool visible = base != 0; | |
7441 | ||
7442 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7443 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7444 | if (base) { |
7445 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7446 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7447 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7448 | } else { | |
7449 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7450 | cntl |= CURSOR_MODE_DISABLE; | |
7451 | } | |
9db4a9c7 | 7452 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7453 | |
7454 | intel_crtc->cursor_visible = visible; | |
7455 | } | |
7456 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7457 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7458 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7459 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7460 | } |
7461 | ||
65a21cd6 JB |
7462 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7463 | { | |
7464 | struct drm_device *dev = crtc->dev; | |
7465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7467 | int pipe = intel_crtc->pipe; | |
7468 | bool visible = base != 0; | |
7469 | ||
7470 | if (intel_crtc->cursor_visible != visible) { | |
7471 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7472 | if (base) { | |
7473 | cntl &= ~CURSOR_MODE; | |
7474 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7475 | } else { | |
7476 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7477 | cntl |= CURSOR_MODE_DISABLE; | |
7478 | } | |
6bbfa1c5 | 7479 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7480 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7481 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7482 | } | |
65a21cd6 JB |
7483 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7484 | ||
7485 | intel_crtc->cursor_visible = visible; | |
7486 | } | |
7487 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7488 | POSTING_READ(CURCNTR_IVB(pipe)); |
65a21cd6 | 7489 | I915_WRITE(CURBASE_IVB(pipe), base); |
b2ea8ef5 | 7490 | POSTING_READ(CURBASE_IVB(pipe)); |
65a21cd6 JB |
7491 | } |
7492 | ||
cda4b7d3 | 7493 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7494 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7495 | bool on) | |
cda4b7d3 CW |
7496 | { |
7497 | struct drm_device *dev = crtc->dev; | |
7498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7499 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7500 | int pipe = intel_crtc->pipe; | |
7501 | int x = intel_crtc->cursor_x; | |
7502 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7503 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7504 | bool visible; |
7505 | ||
d6e4db15 | 7506 | if (on) |
cda4b7d3 | 7507 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7508 | |
d6e4db15 VS |
7509 | if (x >= intel_crtc->config.pipe_src_w) |
7510 | base = 0; | |
7511 | ||
7512 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7513 | base = 0; |
7514 | ||
7515 | if (x < 0) { | |
efc9064e | 7516 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7517 | base = 0; |
7518 | ||
7519 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7520 | x = -x; | |
7521 | } | |
7522 | pos |= x << CURSOR_X_SHIFT; | |
7523 | ||
7524 | if (y < 0) { | |
efc9064e | 7525 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7526 | base = 0; |
7527 | ||
7528 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7529 | y = -y; | |
7530 | } | |
7531 | pos |= y << CURSOR_Y_SHIFT; | |
7532 | ||
7533 | visible = base != 0; | |
560b85bb | 7534 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7535 | return; |
7536 | ||
b3dc685e | 7537 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7538 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7539 | ivb_update_cursor(crtc, base); | |
7540 | } else { | |
7541 | I915_WRITE(CURPOS(pipe), pos); | |
7542 | if (IS_845G(dev) || IS_I865G(dev)) | |
7543 | i845_update_cursor(crtc, base); | |
7544 | else | |
7545 | i9xx_update_cursor(crtc, base); | |
7546 | } | |
cda4b7d3 CW |
7547 | } |
7548 | ||
79e53945 | 7549 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7550 | struct drm_file *file, |
79e53945 JB |
7551 | uint32_t handle, |
7552 | uint32_t width, uint32_t height) | |
7553 | { | |
7554 | struct drm_device *dev = crtc->dev; | |
7555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7556 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7557 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7558 | uint32_t addr; |
3f8bc370 | 7559 | int ret; |
79e53945 | 7560 | |
79e53945 JB |
7561 | /* if we want to turn off the cursor ignore width and height */ |
7562 | if (!handle) { | |
28c97730 | 7563 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7564 | addr = 0; |
05394f39 | 7565 | obj = NULL; |
5004417d | 7566 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7567 | goto finish; |
79e53945 JB |
7568 | } |
7569 | ||
7570 | /* Currently we only support 64x64 cursors */ | |
7571 | if (width != 64 || height != 64) { | |
7572 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7573 | return -EINVAL; | |
7574 | } | |
7575 | ||
05394f39 | 7576 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7577 | if (&obj->base == NULL) |
79e53945 JB |
7578 | return -ENOENT; |
7579 | ||
05394f39 | 7580 | if (obj->base.size < width * height * 4) { |
3b25b31f | 7581 | DRM_DEBUG_KMS("buffer is to small\n"); |
34b8686e DA |
7582 | ret = -ENOMEM; |
7583 | goto fail; | |
79e53945 JB |
7584 | } |
7585 | ||
71acb5eb | 7586 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7587 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 7588 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
7589 | unsigned alignment; |
7590 | ||
d9e86c0e | 7591 | if (obj->tiling_mode) { |
3b25b31f | 7592 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
7593 | ret = -EINVAL; |
7594 | goto fail_locked; | |
7595 | } | |
7596 | ||
693db184 CW |
7597 | /* Note that the w/a also requires 2 PTE of padding following |
7598 | * the bo. We currently fill all unused PTE with the shadow | |
7599 | * page and so we should always have valid PTE following the | |
7600 | * cursor preventing the VT-d warning. | |
7601 | */ | |
7602 | alignment = 0; | |
7603 | if (need_vtd_wa(dev)) | |
7604 | alignment = 64*1024; | |
7605 | ||
7606 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 7607 | if (ret) { |
3b25b31f | 7608 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 7609 | goto fail_locked; |
e7b526bb CW |
7610 | } |
7611 | ||
d9e86c0e CW |
7612 | ret = i915_gem_object_put_fence(obj); |
7613 | if (ret) { | |
3b25b31f | 7614 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
7615 | goto fail_unpin; |
7616 | } | |
7617 | ||
f343c5f6 | 7618 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7619 | } else { |
6eeefaf3 | 7620 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7621 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7622 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7623 | align); | |
71acb5eb | 7624 | if (ret) { |
3b25b31f | 7625 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 7626 | goto fail_locked; |
71acb5eb | 7627 | } |
05394f39 | 7628 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7629 | } |
7630 | ||
a6c45cf0 | 7631 | if (IS_GEN2(dev)) |
14b60391 JB |
7632 | I915_WRITE(CURSIZE, (height << 12) | width); |
7633 | ||
3f8bc370 | 7634 | finish: |
3f8bc370 | 7635 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 7636 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 7637 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7638 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7639 | } else | |
cc98b413 | 7640 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7641 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7642 | } |
80824003 | 7643 | |
7f9872e0 | 7644 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7645 | |
7646 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7647 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7648 | intel_crtc->cursor_width = width; |
7649 | intel_crtc->cursor_height = height; | |
7650 | ||
f2f5f771 VS |
7651 | if (intel_crtc->active) |
7652 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7653 | |
79e53945 | 7654 | return 0; |
e7b526bb | 7655 | fail_unpin: |
cc98b413 | 7656 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7657 | fail_locked: |
34b8686e | 7658 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7659 | fail: |
05394f39 | 7660 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7661 | return ret; |
79e53945 JB |
7662 | } |
7663 | ||
7664 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7665 | { | |
79e53945 | 7666 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7667 | |
92e76c8c VS |
7668 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7669 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7670 | |
f2f5f771 VS |
7671 | if (intel_crtc->active) |
7672 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7673 | |
7674 | return 0; | |
b8c00ac5 DA |
7675 | } |
7676 | ||
79e53945 | 7677 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7678 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7679 | { |
7203425a | 7680 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7682 | |
7203425a | 7683 | for (i = start; i < end; i++) { |
79e53945 JB |
7684 | intel_crtc->lut_r[i] = red[i] >> 8; |
7685 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7686 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7687 | } | |
7688 | ||
7689 | intel_crtc_load_lut(crtc); | |
7690 | } | |
7691 | ||
79e53945 JB |
7692 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7693 | static struct drm_display_mode load_detect_mode = { | |
7694 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7695 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7696 | }; | |
7697 | ||
a8bb6818 DV |
7698 | struct drm_framebuffer * |
7699 | __intel_framebuffer_create(struct drm_device *dev, | |
7700 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7701 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
7702 | { |
7703 | struct intel_framebuffer *intel_fb; | |
7704 | int ret; | |
7705 | ||
7706 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7707 | if (!intel_fb) { | |
7708 | drm_gem_object_unreference_unlocked(&obj->base); | |
7709 | return ERR_PTR(-ENOMEM); | |
7710 | } | |
7711 | ||
7712 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
7713 | if (ret) |
7714 | goto err; | |
d2dff872 CW |
7715 | |
7716 | return &intel_fb->base; | |
dd4916c5 DV |
7717 | err: |
7718 | drm_gem_object_unreference_unlocked(&obj->base); | |
7719 | kfree(intel_fb); | |
7720 | ||
7721 | return ERR_PTR(ret); | |
d2dff872 CW |
7722 | } |
7723 | ||
b5ea642a | 7724 | static struct drm_framebuffer * |
a8bb6818 DV |
7725 | intel_framebuffer_create(struct drm_device *dev, |
7726 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7727 | struct drm_i915_gem_object *obj) | |
7728 | { | |
7729 | struct drm_framebuffer *fb; | |
7730 | int ret; | |
7731 | ||
7732 | ret = i915_mutex_lock_interruptible(dev); | |
7733 | if (ret) | |
7734 | return ERR_PTR(ret); | |
7735 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
7736 | mutex_unlock(&dev->struct_mutex); | |
7737 | ||
7738 | return fb; | |
7739 | } | |
7740 | ||
d2dff872 CW |
7741 | static u32 |
7742 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7743 | { | |
7744 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7745 | return ALIGN(pitch, 64); | |
7746 | } | |
7747 | ||
7748 | static u32 | |
7749 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7750 | { | |
7751 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7752 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7753 | } | |
7754 | ||
7755 | static struct drm_framebuffer * | |
7756 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7757 | struct drm_display_mode *mode, | |
7758 | int depth, int bpp) | |
7759 | { | |
7760 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7761 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7762 | |
7763 | obj = i915_gem_alloc_object(dev, | |
7764 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7765 | if (obj == NULL) | |
7766 | return ERR_PTR(-ENOMEM); | |
7767 | ||
7768 | mode_cmd.width = mode->hdisplay; | |
7769 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7770 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7771 | bpp); | |
5ca0c34a | 7772 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7773 | |
7774 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7775 | } | |
7776 | ||
7777 | static struct drm_framebuffer * | |
7778 | mode_fits_in_fbdev(struct drm_device *dev, | |
7779 | struct drm_display_mode *mode) | |
7780 | { | |
4520f53a | 7781 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7782 | struct drm_i915_private *dev_priv = dev->dev_private; |
7783 | struct drm_i915_gem_object *obj; | |
7784 | struct drm_framebuffer *fb; | |
7785 | ||
4c0e5528 | 7786 | if (!dev_priv->fbdev) |
d2dff872 CW |
7787 | return NULL; |
7788 | ||
4c0e5528 | 7789 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
7790 | return NULL; |
7791 | ||
4c0e5528 DV |
7792 | obj = dev_priv->fbdev->fb->obj; |
7793 | BUG_ON(!obj); | |
7794 | ||
8bcd4553 | 7795 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
7796 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7797 | fb->bits_per_pixel)) | |
d2dff872 CW |
7798 | return NULL; |
7799 | ||
01f2c773 | 7800 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7801 | return NULL; |
7802 | ||
7803 | return fb; | |
4520f53a DV |
7804 | #else |
7805 | return NULL; | |
7806 | #endif | |
d2dff872 CW |
7807 | } |
7808 | ||
d2434ab7 | 7809 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7810 | struct drm_display_mode *mode, |
8261b191 | 7811 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7812 | { |
7813 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7814 | struct intel_encoder *intel_encoder = |
7815 | intel_attached_encoder(connector); | |
79e53945 | 7816 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7817 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7818 | struct drm_crtc *crtc = NULL; |
7819 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7820 | struct drm_framebuffer *fb; |
79e53945 JB |
7821 | int i = -1; |
7822 | ||
d2dff872 CW |
7823 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7824 | connector->base.id, drm_get_connector_name(connector), | |
7825 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7826 | ||
79e53945 JB |
7827 | /* |
7828 | * Algorithm gets a little messy: | |
7a5e4805 | 7829 | * |
79e53945 JB |
7830 | * - if the connector already has an assigned crtc, use it (but make |
7831 | * sure it's on first) | |
7a5e4805 | 7832 | * |
79e53945 JB |
7833 | * - try to find the first unused crtc that can drive this connector, |
7834 | * and use that if we find one | |
79e53945 JB |
7835 | */ |
7836 | ||
7837 | /* See if we already have a CRTC for this connector */ | |
7838 | if (encoder->crtc) { | |
7839 | crtc = encoder->crtc; | |
8261b191 | 7840 | |
7b24056b DV |
7841 | mutex_lock(&crtc->mutex); |
7842 | ||
24218aac | 7843 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7844 | old->load_detect_temp = false; |
7845 | ||
7846 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7847 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7848 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7849 | |
7173188d | 7850 | return true; |
79e53945 JB |
7851 | } |
7852 | ||
7853 | /* Find an unused one (if possible) */ | |
7854 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7855 | i++; | |
7856 | if (!(encoder->possible_crtcs & (1 << i))) | |
7857 | continue; | |
7858 | if (!possible_crtc->enabled) { | |
7859 | crtc = possible_crtc; | |
7860 | break; | |
7861 | } | |
79e53945 JB |
7862 | } |
7863 | ||
7864 | /* | |
7865 | * If we didn't find an unused CRTC, don't use any. | |
7866 | */ | |
7867 | if (!crtc) { | |
7173188d CW |
7868 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7869 | return false; | |
79e53945 JB |
7870 | } |
7871 | ||
7b24056b | 7872 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7873 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7874 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7875 | |
7876 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
7877 | intel_crtc->new_enabled = true; |
7878 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 7879 | old->dpms_mode = connector->dpms; |
8261b191 | 7880 | old->load_detect_temp = true; |
d2dff872 | 7881 | old->release_fb = NULL; |
79e53945 | 7882 | |
6492711d CW |
7883 | if (!mode) |
7884 | mode = &load_detect_mode; | |
79e53945 | 7885 | |
d2dff872 CW |
7886 | /* We need a framebuffer large enough to accommodate all accesses |
7887 | * that the plane may generate whilst we perform load detection. | |
7888 | * We can not rely on the fbcon either being present (we get called | |
7889 | * during its initialisation to detect all boot displays, or it may | |
7890 | * not even exist) or that it is large enough to satisfy the | |
7891 | * requested mode. | |
7892 | */ | |
94352cf9 DV |
7893 | fb = mode_fits_in_fbdev(dev, mode); |
7894 | if (fb == NULL) { | |
d2dff872 | 7895 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7896 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7897 | old->release_fb = fb; | |
d2dff872 CW |
7898 | } else |
7899 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7900 | if (IS_ERR(fb)) { |
d2dff872 | 7901 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 7902 | goto fail; |
79e53945 | 7903 | } |
79e53945 | 7904 | |
c0c36b94 | 7905 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7906 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7907 | if (old->release_fb) |
7908 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 7909 | goto fail; |
79e53945 | 7910 | } |
7173188d | 7911 | |
79e53945 | 7912 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7913 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7914 | return true; |
412b61d8 VS |
7915 | |
7916 | fail: | |
7917 | intel_crtc->new_enabled = crtc->enabled; | |
7918 | if (intel_crtc->new_enabled) | |
7919 | intel_crtc->new_config = &intel_crtc->config; | |
7920 | else | |
7921 | intel_crtc->new_config = NULL; | |
7922 | mutex_unlock(&crtc->mutex); | |
7923 | return false; | |
79e53945 JB |
7924 | } |
7925 | ||
d2434ab7 | 7926 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7927 | struct intel_load_detect_pipe *old) |
79e53945 | 7928 | { |
d2434ab7 DV |
7929 | struct intel_encoder *intel_encoder = |
7930 | intel_attached_encoder(connector); | |
4ef69c7a | 7931 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7932 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 7933 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7934 | |
d2dff872 CW |
7935 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7936 | connector->base.id, drm_get_connector_name(connector), | |
7937 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7938 | ||
8261b191 | 7939 | if (old->load_detect_temp) { |
fc303101 DV |
7940 | to_intel_connector(connector)->new_encoder = NULL; |
7941 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
7942 | intel_crtc->new_enabled = false; |
7943 | intel_crtc->new_config = NULL; | |
fc303101 | 7944 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 7945 | |
36206361 DV |
7946 | if (old->release_fb) { |
7947 | drm_framebuffer_unregister_private(old->release_fb); | |
7948 | drm_framebuffer_unreference(old->release_fb); | |
7949 | } | |
d2dff872 | 7950 | |
67c96400 | 7951 | mutex_unlock(&crtc->mutex); |
0622a53c | 7952 | return; |
79e53945 JB |
7953 | } |
7954 | ||
c751ce4f | 7955 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7956 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7957 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7958 | |
7959 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7960 | } |
7961 | ||
da4a1efa VS |
7962 | static int i9xx_pll_refclk(struct drm_device *dev, |
7963 | const struct intel_crtc_config *pipe_config) | |
7964 | { | |
7965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7966 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7967 | ||
7968 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 7969 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
7970 | else if (HAS_PCH_SPLIT(dev)) |
7971 | return 120000; | |
7972 | else if (!IS_GEN2(dev)) | |
7973 | return 96000; | |
7974 | else | |
7975 | return 48000; | |
7976 | } | |
7977 | ||
79e53945 | 7978 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7979 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7980 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7981 | { |
f1f644dc | 7982 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7983 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7984 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7985 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7986 | u32 fp; |
7987 | intel_clock_t clock; | |
da4a1efa | 7988 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7989 | |
7990 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7991 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7992 | else |
293623f7 | 7993 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7994 | |
7995 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7996 | if (IS_PINEVIEW(dev)) { |
7997 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7998 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7999 | } else { |
8000 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8001 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8002 | } | |
8003 | ||
a6c45cf0 | 8004 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8005 | if (IS_PINEVIEW(dev)) |
8006 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8007 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8008 | else |
8009 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8010 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8011 | ||
8012 | switch (dpll & DPLL_MODE_MASK) { | |
8013 | case DPLLB_MODE_DAC_SERIAL: | |
8014 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8015 | 5 : 10; | |
8016 | break; | |
8017 | case DPLLB_MODE_LVDS: | |
8018 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8019 | 7 : 14; | |
8020 | break; | |
8021 | default: | |
28c97730 | 8022 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8023 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8024 | return; |
79e53945 JB |
8025 | } |
8026 | ||
ac58c3f0 | 8027 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8028 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8029 | else |
da4a1efa | 8030 | i9xx_clock(refclk, &clock); |
79e53945 | 8031 | } else { |
0fb58223 | 8032 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8033 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8034 | |
8035 | if (is_lvds) { | |
8036 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8037 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8038 | |
8039 | if (lvds & LVDS_CLKB_POWER_UP) | |
8040 | clock.p2 = 7; | |
8041 | else | |
8042 | clock.p2 = 14; | |
79e53945 JB |
8043 | } else { |
8044 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8045 | clock.p1 = 2; | |
8046 | else { | |
8047 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8048 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8049 | } | |
8050 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8051 | clock.p2 = 4; | |
8052 | else | |
8053 | clock.p2 = 2; | |
79e53945 | 8054 | } |
da4a1efa VS |
8055 | |
8056 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8057 | } |
8058 | ||
18442d08 VS |
8059 | /* |
8060 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8061 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8062 | * encoder's get_config() function. |
8063 | */ | |
8064 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8065 | } |
8066 | ||
6878da05 VS |
8067 | int intel_dotclock_calculate(int link_freq, |
8068 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8069 | { |
f1f644dc JB |
8070 | /* |
8071 | * The calculation for the data clock is: | |
1041a02f | 8072 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8073 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8074 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8075 | * |
8076 | * and the link clock is simpler: | |
1041a02f | 8077 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8078 | */ |
8079 | ||
6878da05 VS |
8080 | if (!m_n->link_n) |
8081 | return 0; | |
f1f644dc | 8082 | |
6878da05 VS |
8083 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8084 | } | |
f1f644dc | 8085 | |
18442d08 VS |
8086 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8087 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8088 | { |
8089 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8090 | |
18442d08 VS |
8091 | /* read out port_clock from the DPLL */ |
8092 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8093 | |
f1f644dc | 8094 | /* |
18442d08 | 8095 | * This value does not include pixel_multiplier. |
241bfc38 | 8096 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8097 | * agree once we know their relationship in the encoder's |
8098 | * get_config() function. | |
79e53945 | 8099 | */ |
241bfc38 | 8100 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8101 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8102 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8103 | } |
8104 | ||
8105 | /** Returns the currently programmed mode of the given pipe. */ | |
8106 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8107 | struct drm_crtc *crtc) | |
8108 | { | |
548f245b | 8109 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8111 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8112 | struct drm_display_mode *mode; |
f1f644dc | 8113 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8114 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8115 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8116 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8117 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8118 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8119 | |
8120 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8121 | if (!mode) | |
8122 | return NULL; | |
8123 | ||
f1f644dc JB |
8124 | /* |
8125 | * Construct a pipe_config sufficient for getting the clock info | |
8126 | * back out of crtc_clock_get. | |
8127 | * | |
8128 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8129 | * to use a real value here instead. | |
8130 | */ | |
293623f7 | 8131 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8132 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8133 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8134 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8135 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8136 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8137 | ||
773ae034 | 8138 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8139 | mode->hdisplay = (htot & 0xffff) + 1; |
8140 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8141 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8142 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8143 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8144 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8145 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8146 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8147 | ||
8148 | drm_mode_set_name(mode); | |
79e53945 JB |
8149 | |
8150 | return mode; | |
8151 | } | |
8152 | ||
3dec0095 | 8153 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8154 | { |
8155 | struct drm_device *dev = crtc->dev; | |
8156 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8158 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8159 | int dpll_reg = DPLL(pipe); |
8160 | int dpll; | |
652c393a | 8161 | |
bad720ff | 8162 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8163 | return; |
8164 | ||
8165 | if (!dev_priv->lvds_downclock_avail) | |
8166 | return; | |
8167 | ||
dbdc6479 | 8168 | dpll = I915_READ(dpll_reg); |
652c393a | 8169 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8170 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8171 | |
8ac5a6d5 | 8172 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8173 | |
8174 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8175 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8176 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8177 | |
652c393a JB |
8178 | dpll = I915_READ(dpll_reg); |
8179 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8180 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8181 | } |
652c393a JB |
8182 | } |
8183 | ||
8184 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8185 | { | |
8186 | struct drm_device *dev = crtc->dev; | |
8187 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8189 | |
bad720ff | 8190 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8191 | return; |
8192 | ||
8193 | if (!dev_priv->lvds_downclock_avail) | |
8194 | return; | |
8195 | ||
8196 | /* | |
8197 | * Since this is called by a timer, we should never get here in | |
8198 | * the manual case. | |
8199 | */ | |
8200 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8201 | int pipe = intel_crtc->pipe; |
8202 | int dpll_reg = DPLL(pipe); | |
8203 | int dpll; | |
f6e5b160 | 8204 | |
44d98a61 | 8205 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8206 | |
8ac5a6d5 | 8207 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8208 | |
dc257cf1 | 8209 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8210 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8211 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8212 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8213 | dpll = I915_READ(dpll_reg); |
8214 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8215 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8216 | } |
8217 | ||
8218 | } | |
8219 | ||
f047e395 CW |
8220 | void intel_mark_busy(struct drm_device *dev) |
8221 | { | |
c67a470b PZ |
8222 | struct drm_i915_private *dev_priv = dev->dev_private; |
8223 | ||
f62a0076 CW |
8224 | if (dev_priv->mm.busy) |
8225 | return; | |
8226 | ||
86c4ec0d | 8227 | hsw_disable_package_c8(dev_priv); |
c67a470b | 8228 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8229 | dev_priv->mm.busy = true; |
f047e395 CW |
8230 | } |
8231 | ||
8232 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8233 | { |
c67a470b | 8234 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8235 | struct drm_crtc *crtc; |
652c393a | 8236 | |
f62a0076 CW |
8237 | if (!dev_priv->mm.busy) |
8238 | return; | |
8239 | ||
8240 | dev_priv->mm.busy = false; | |
8241 | ||
d330a953 | 8242 | if (!i915.powersave) |
bb4cdd53 | 8243 | goto out; |
652c393a | 8244 | |
652c393a | 8245 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8246 | if (!crtc->fb) |
8247 | continue; | |
8248 | ||
725a5b54 | 8249 | intel_decrease_pllclock(crtc); |
652c393a | 8250 | } |
b29c19b6 | 8251 | |
3d13ef2e | 8252 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8253 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8254 | |
8255 | out: | |
86c4ec0d | 8256 | hsw_enable_package_c8(dev_priv); |
652c393a JB |
8257 | } |
8258 | ||
c65355bb CW |
8259 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8260 | struct intel_ring_buffer *ring) | |
652c393a | 8261 | { |
f047e395 CW |
8262 | struct drm_device *dev = obj->base.dev; |
8263 | struct drm_crtc *crtc; | |
652c393a | 8264 | |
d330a953 | 8265 | if (!i915.powersave) |
acb87dfb CW |
8266 | return; |
8267 | ||
652c393a JB |
8268 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8269 | if (!crtc->fb) | |
8270 | continue; | |
8271 | ||
c65355bb CW |
8272 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8273 | continue; | |
8274 | ||
8275 | intel_increase_pllclock(crtc); | |
8276 | if (ring && intel_fbc_enabled(dev)) | |
8277 | ring->fbc_dirty = true; | |
652c393a JB |
8278 | } |
8279 | } | |
8280 | ||
79e53945 JB |
8281 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8282 | { | |
8283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8284 | struct drm_device *dev = crtc->dev; |
8285 | struct intel_unpin_work *work; | |
8286 | unsigned long flags; | |
8287 | ||
8288 | spin_lock_irqsave(&dev->event_lock, flags); | |
8289 | work = intel_crtc->unpin_work; | |
8290 | intel_crtc->unpin_work = NULL; | |
8291 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8292 | ||
8293 | if (work) { | |
8294 | cancel_work_sync(&work->work); | |
8295 | kfree(work); | |
8296 | } | |
79e53945 | 8297 | |
40ccc72b MK |
8298 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8299 | ||
79e53945 | 8300 | drm_crtc_cleanup(crtc); |
67e77c5a | 8301 | |
79e53945 JB |
8302 | kfree(intel_crtc); |
8303 | } | |
8304 | ||
6b95a207 KH |
8305 | static void intel_unpin_work_fn(struct work_struct *__work) |
8306 | { | |
8307 | struct intel_unpin_work *work = | |
8308 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8309 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8310 | |
b4a98e57 | 8311 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8312 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8313 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8314 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8315 | |
b4a98e57 CW |
8316 | intel_update_fbc(dev); |
8317 | mutex_unlock(&dev->struct_mutex); | |
8318 | ||
8319 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8320 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8321 | ||
6b95a207 KH |
8322 | kfree(work); |
8323 | } | |
8324 | ||
1afe3e9d | 8325 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8326 | struct drm_crtc *crtc) |
6b95a207 KH |
8327 | { |
8328 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8330 | struct intel_unpin_work *work; | |
6b95a207 KH |
8331 | unsigned long flags; |
8332 | ||
8333 | /* Ignore early vblank irqs */ | |
8334 | if (intel_crtc == NULL) | |
8335 | return; | |
8336 | ||
8337 | spin_lock_irqsave(&dev->event_lock, flags); | |
8338 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8339 | |
8340 | /* Ensure we don't miss a work->pending update ... */ | |
8341 | smp_rmb(); | |
8342 | ||
8343 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8344 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8345 | return; | |
8346 | } | |
8347 | ||
e7d841ca CW |
8348 | /* and that the unpin work is consistent wrt ->pending. */ |
8349 | smp_rmb(); | |
8350 | ||
6b95a207 | 8351 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8352 | |
45a066eb RC |
8353 | if (work->event) |
8354 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8355 | |
0af7e4df MK |
8356 | drm_vblank_put(dev, intel_crtc->pipe); |
8357 | ||
6b95a207 KH |
8358 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8359 | ||
2c10d571 | 8360 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8361 | |
8362 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8363 | |
8364 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8365 | } |
8366 | ||
1afe3e9d JB |
8367 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8368 | { | |
8369 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8370 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8371 | ||
49b14a5c | 8372 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8373 | } |
8374 | ||
8375 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8376 | { | |
8377 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8378 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8379 | ||
49b14a5c | 8380 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8381 | } |
8382 | ||
6b95a207 KH |
8383 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8384 | { | |
8385 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8386 | struct intel_crtc *intel_crtc = | |
8387 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8388 | unsigned long flags; | |
8389 | ||
e7d841ca CW |
8390 | /* NB: An MMIO update of the plane base pointer will also |
8391 | * generate a page-flip completion irq, i.e. every modeset | |
8392 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8393 | */ | |
6b95a207 | 8394 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8395 | if (intel_crtc->unpin_work) |
8396 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8397 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8398 | } | |
8399 | ||
e7d841ca CW |
8400 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8401 | { | |
8402 | /* Ensure that the work item is consistent when activating it ... */ | |
8403 | smp_wmb(); | |
8404 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8405 | /* and that it is marked active as soon as the irq could fire. */ | |
8406 | smp_wmb(); | |
8407 | } | |
8408 | ||
8c9f3aaf JB |
8409 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8410 | struct drm_crtc *crtc, | |
8411 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8412 | struct drm_i915_gem_object *obj, |
8413 | uint32_t flags) | |
8c9f3aaf JB |
8414 | { |
8415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8416 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8417 | u32 flip_mask; |
6d90c952 | 8418 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8419 | int ret; |
8420 | ||
6d90c952 | 8421 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8422 | if (ret) |
83d4092b | 8423 | goto err; |
8c9f3aaf | 8424 | |
6d90c952 | 8425 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8426 | if (ret) |
83d4092b | 8427 | goto err_unpin; |
8c9f3aaf JB |
8428 | |
8429 | /* Can't queue multiple flips, so wait for the previous | |
8430 | * one to finish before executing the next. | |
8431 | */ | |
8432 | if (intel_crtc->plane) | |
8433 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8434 | else | |
8435 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8436 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8437 | intel_ring_emit(ring, MI_NOOP); | |
8438 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8439 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8440 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8441 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8442 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8443 | |
8444 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8445 | __intel_ring_advance(ring); |
83d4092b CW |
8446 | return 0; |
8447 | ||
8448 | err_unpin: | |
8449 | intel_unpin_fb_obj(obj); | |
8450 | err: | |
8c9f3aaf JB |
8451 | return ret; |
8452 | } | |
8453 | ||
8454 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8455 | struct drm_crtc *crtc, | |
8456 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8457 | struct drm_i915_gem_object *obj, |
8458 | uint32_t flags) | |
8c9f3aaf JB |
8459 | { |
8460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8461 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8462 | u32 flip_mask; |
6d90c952 | 8463 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8464 | int ret; |
8465 | ||
6d90c952 | 8466 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8467 | if (ret) |
83d4092b | 8468 | goto err; |
8c9f3aaf | 8469 | |
6d90c952 | 8470 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8471 | if (ret) |
83d4092b | 8472 | goto err_unpin; |
8c9f3aaf JB |
8473 | |
8474 | if (intel_crtc->plane) | |
8475 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8476 | else | |
8477 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8478 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8479 | intel_ring_emit(ring, MI_NOOP); | |
8480 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8481 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8482 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8483 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8484 | intel_ring_emit(ring, MI_NOOP); |
8485 | ||
e7d841ca | 8486 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8487 | __intel_ring_advance(ring); |
83d4092b CW |
8488 | return 0; |
8489 | ||
8490 | err_unpin: | |
8491 | intel_unpin_fb_obj(obj); | |
8492 | err: | |
8c9f3aaf JB |
8493 | return ret; |
8494 | } | |
8495 | ||
8496 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8497 | struct drm_crtc *crtc, | |
8498 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8499 | struct drm_i915_gem_object *obj, |
8500 | uint32_t flags) | |
8c9f3aaf JB |
8501 | { |
8502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8504 | uint32_t pf, pipesrc; | |
6d90c952 | 8505 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8506 | int ret; |
8507 | ||
6d90c952 | 8508 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8509 | if (ret) |
83d4092b | 8510 | goto err; |
8c9f3aaf | 8511 | |
6d90c952 | 8512 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8513 | if (ret) |
83d4092b | 8514 | goto err_unpin; |
8c9f3aaf JB |
8515 | |
8516 | /* i965+ uses the linear or tiled offsets from the | |
8517 | * Display Registers (which do not change across a page-flip) | |
8518 | * so we need only reprogram the base address. | |
8519 | */ | |
6d90c952 DV |
8520 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8521 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8522 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8523 | intel_ring_emit(ring, |
f343c5f6 | 8524 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8525 | obj->tiling_mode); |
8c9f3aaf JB |
8526 | |
8527 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8528 | * untested on non-native modes, so ignore it for now. | |
8529 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8530 | */ | |
8531 | pf = 0; | |
8532 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8533 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8534 | |
8535 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8536 | __intel_ring_advance(ring); |
83d4092b CW |
8537 | return 0; |
8538 | ||
8539 | err_unpin: | |
8540 | intel_unpin_fb_obj(obj); | |
8541 | err: | |
8c9f3aaf JB |
8542 | return ret; |
8543 | } | |
8544 | ||
8545 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8546 | struct drm_crtc *crtc, | |
8547 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8548 | struct drm_i915_gem_object *obj, |
8549 | uint32_t flags) | |
8c9f3aaf JB |
8550 | { |
8551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8552 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8553 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8554 | uint32_t pf, pipesrc; |
8555 | int ret; | |
8556 | ||
6d90c952 | 8557 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8558 | if (ret) |
83d4092b | 8559 | goto err; |
8c9f3aaf | 8560 | |
6d90c952 | 8561 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8562 | if (ret) |
83d4092b | 8563 | goto err_unpin; |
8c9f3aaf | 8564 | |
6d90c952 DV |
8565 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8566 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8567 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8568 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8569 | |
dc257cf1 DV |
8570 | /* Contrary to the suggestions in the documentation, |
8571 | * "Enable Panel Fitter" does not seem to be required when page | |
8572 | * flipping with a non-native mode, and worse causes a normal | |
8573 | * modeset to fail. | |
8574 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8575 | */ | |
8576 | pf = 0; | |
8c9f3aaf | 8577 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8578 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8579 | |
8580 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8581 | __intel_ring_advance(ring); |
83d4092b CW |
8582 | return 0; |
8583 | ||
8584 | err_unpin: | |
8585 | intel_unpin_fb_obj(obj); | |
8586 | err: | |
8c9f3aaf JB |
8587 | return ret; |
8588 | } | |
8589 | ||
7c9017e5 JB |
8590 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8591 | struct drm_crtc *crtc, | |
8592 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8593 | struct drm_i915_gem_object *obj, |
8594 | uint32_t flags) | |
7c9017e5 JB |
8595 | { |
8596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8597 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8598 | struct intel_ring_buffer *ring; |
cb05d8de | 8599 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8600 | int len, ret; |
8601 | ||
8602 | ring = obj->ring; | |
1c5fd085 | 8603 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8604 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8605 | |
8606 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8607 | if (ret) | |
83d4092b | 8608 | goto err; |
7c9017e5 | 8609 | |
cb05d8de DV |
8610 | switch(intel_crtc->plane) { |
8611 | case PLANE_A: | |
8612 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8613 | break; | |
8614 | case PLANE_B: | |
8615 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8616 | break; | |
8617 | case PLANE_C: | |
8618 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8619 | break; | |
8620 | default: | |
8621 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8622 | ret = -ENODEV; | |
ab3951eb | 8623 | goto err_unpin; |
cb05d8de DV |
8624 | } |
8625 | ||
ffe74d75 CW |
8626 | len = 4; |
8627 | if (ring->id == RCS) | |
8628 | len += 6; | |
8629 | ||
8630 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8631 | if (ret) |
83d4092b | 8632 | goto err_unpin; |
7c9017e5 | 8633 | |
ffe74d75 CW |
8634 | /* Unmask the flip-done completion message. Note that the bspec says that |
8635 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8636 | * more than one flip event at any time (or ensure that one flip message | |
8637 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8638 | * Experimentation says that BCS works despite DERRMR masking all | |
8639 | * flip-done completion events and that unmasking all planes at once | |
8640 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8641 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8642 | */ | |
8643 | if (ring->id == RCS) { | |
8644 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8645 | intel_ring_emit(ring, DERRMR); | |
8646 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8647 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8648 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
22613c96 VS |
8649 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8650 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
8651 | intel_ring_emit(ring, DERRMR); |
8652 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8653 | } | |
8654 | ||
cb05d8de | 8655 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8656 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8657 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8658 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8659 | |
8660 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8661 | __intel_ring_advance(ring); |
83d4092b CW |
8662 | return 0; |
8663 | ||
8664 | err_unpin: | |
8665 | intel_unpin_fb_obj(obj); | |
8666 | err: | |
7c9017e5 JB |
8667 | return ret; |
8668 | } | |
8669 | ||
8c9f3aaf JB |
8670 | static int intel_default_queue_flip(struct drm_device *dev, |
8671 | struct drm_crtc *crtc, | |
8672 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8673 | struct drm_i915_gem_object *obj, |
8674 | uint32_t flags) | |
8c9f3aaf JB |
8675 | { |
8676 | return -ENODEV; | |
8677 | } | |
8678 | ||
6b95a207 KH |
8679 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8680 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8681 | struct drm_pending_vblank_event *event, |
8682 | uint32_t page_flip_flags) | |
6b95a207 KH |
8683 | { |
8684 | struct drm_device *dev = crtc->dev; | |
8685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8686 | struct drm_framebuffer *old_fb = crtc->fb; |
8687 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8688 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8689 | struct intel_unpin_work *work; | |
8c9f3aaf | 8690 | unsigned long flags; |
52e68630 | 8691 | int ret; |
6b95a207 | 8692 | |
e6a595d2 VS |
8693 | /* Can't change pixel format via MI display flips. */ |
8694 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8695 | return -EINVAL; | |
8696 | ||
8697 | /* | |
8698 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8699 | * Note that pitch changes could also affect these register. | |
8700 | */ | |
8701 | if (INTEL_INFO(dev)->gen > 3 && | |
8702 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8703 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8704 | return -EINVAL; | |
8705 | ||
f900db47 CW |
8706 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
8707 | goto out_hang; | |
8708 | ||
b14c5679 | 8709 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8710 | if (work == NULL) |
8711 | return -ENOMEM; | |
8712 | ||
6b95a207 | 8713 | work->event = event; |
b4a98e57 | 8714 | work->crtc = crtc; |
4a35f83b | 8715 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8716 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8717 | ||
7317c75e JB |
8718 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8719 | if (ret) | |
8720 | goto free_work; | |
8721 | ||
6b95a207 KH |
8722 | /* We borrow the event spin lock for protecting unpin_work */ |
8723 | spin_lock_irqsave(&dev->event_lock, flags); | |
8724 | if (intel_crtc->unpin_work) { | |
8725 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8726 | kfree(work); | |
7317c75e | 8727 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8728 | |
8729 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8730 | return -EBUSY; |
8731 | } | |
8732 | intel_crtc->unpin_work = work; | |
8733 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8734 | ||
b4a98e57 CW |
8735 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8736 | flush_workqueue(dev_priv->wq); | |
8737 | ||
79158103 CW |
8738 | ret = i915_mutex_lock_interruptible(dev); |
8739 | if (ret) | |
8740 | goto cleanup; | |
6b95a207 | 8741 | |
75dfca80 | 8742 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8743 | drm_gem_object_reference(&work->old_fb_obj->base); |
8744 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8745 | |
8746 | crtc->fb = fb; | |
96b099fd | 8747 | |
e1f99ce6 | 8748 | work->pending_flip_obj = obj; |
e1f99ce6 | 8749 | |
4e5359cd SF |
8750 | work->enable_stall_check = true; |
8751 | ||
b4a98e57 | 8752 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8753 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8754 | |
ed8d1975 | 8755 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8756 | if (ret) |
8757 | goto cleanup_pending; | |
6b95a207 | 8758 | |
7782de3b | 8759 | intel_disable_fbc(dev); |
c65355bb | 8760 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8761 | mutex_unlock(&dev->struct_mutex); |
8762 | ||
e5510fac JB |
8763 | trace_i915_flip_request(intel_crtc->plane, obj); |
8764 | ||
6b95a207 | 8765 | return 0; |
96b099fd | 8766 | |
8c9f3aaf | 8767 | cleanup_pending: |
b4a98e57 | 8768 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8769 | crtc->fb = old_fb; |
05394f39 CW |
8770 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8771 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8772 | mutex_unlock(&dev->struct_mutex); |
8773 | ||
79158103 | 8774 | cleanup: |
96b099fd CW |
8775 | spin_lock_irqsave(&dev->event_lock, flags); |
8776 | intel_crtc->unpin_work = NULL; | |
8777 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8778 | ||
7317c75e JB |
8779 | drm_vblank_put(dev, intel_crtc->pipe); |
8780 | free_work: | |
96b099fd CW |
8781 | kfree(work); |
8782 | ||
f900db47 CW |
8783 | if (ret == -EIO) { |
8784 | out_hang: | |
8785 | intel_crtc_wait_for_pending_flips(crtc); | |
8786 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
8787 | if (ret == 0 && event) | |
8788 | drm_send_vblank_event(dev, intel_crtc->pipe, event); | |
8789 | } | |
96b099fd | 8790 | return ret; |
6b95a207 KH |
8791 | } |
8792 | ||
f6e5b160 | 8793 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8794 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8795 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8796 | }; |
8797 | ||
9a935856 DV |
8798 | /** |
8799 | * intel_modeset_update_staged_output_state | |
8800 | * | |
8801 | * Updates the staged output configuration state, e.g. after we've read out the | |
8802 | * current hw state. | |
8803 | */ | |
8804 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8805 | { |
7668851f | 8806 | struct intel_crtc *crtc; |
9a935856 DV |
8807 | struct intel_encoder *encoder; |
8808 | struct intel_connector *connector; | |
f6e5b160 | 8809 | |
9a935856 DV |
8810 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8811 | base.head) { | |
8812 | connector->new_encoder = | |
8813 | to_intel_encoder(connector->base.encoder); | |
8814 | } | |
f6e5b160 | 8815 | |
9a935856 DV |
8816 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8817 | base.head) { | |
8818 | encoder->new_crtc = | |
8819 | to_intel_crtc(encoder->base.crtc); | |
8820 | } | |
7668851f VS |
8821 | |
8822 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8823 | base.head) { | |
8824 | crtc->new_enabled = crtc->base.enabled; | |
7bd0a8e7 VS |
8825 | |
8826 | if (crtc->new_enabled) | |
8827 | crtc->new_config = &crtc->config; | |
8828 | else | |
8829 | crtc->new_config = NULL; | |
7668851f | 8830 | } |
f6e5b160 CW |
8831 | } |
8832 | ||
9a935856 DV |
8833 | /** |
8834 | * intel_modeset_commit_output_state | |
8835 | * | |
8836 | * This function copies the stage display pipe configuration to the real one. | |
8837 | */ | |
8838 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8839 | { | |
7668851f | 8840 | struct intel_crtc *crtc; |
9a935856 DV |
8841 | struct intel_encoder *encoder; |
8842 | struct intel_connector *connector; | |
f6e5b160 | 8843 | |
9a935856 DV |
8844 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8845 | base.head) { | |
8846 | connector->base.encoder = &connector->new_encoder->base; | |
8847 | } | |
f6e5b160 | 8848 | |
9a935856 DV |
8849 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8850 | base.head) { | |
8851 | encoder->base.crtc = &encoder->new_crtc->base; | |
8852 | } | |
7668851f VS |
8853 | |
8854 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8855 | base.head) { | |
8856 | crtc->base.enabled = crtc->new_enabled; | |
8857 | } | |
9a935856 DV |
8858 | } |
8859 | ||
050f7aeb DV |
8860 | static void |
8861 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8862 | struct intel_crtc_config *pipe_config) | |
8863 | { | |
8864 | int bpp = pipe_config->pipe_bpp; | |
8865 | ||
8866 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8867 | connector->base.base.id, | |
8868 | drm_get_connector_name(&connector->base)); | |
8869 | ||
8870 | /* Don't use an invalid EDID bpc value */ | |
8871 | if (connector->base.display_info.bpc && | |
8872 | connector->base.display_info.bpc * 3 < bpp) { | |
8873 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8874 | bpp, connector->base.display_info.bpc*3); | |
8875 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8876 | } | |
8877 | ||
8878 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8879 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8880 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8881 | bpp); | |
8882 | pipe_config->pipe_bpp = 24; | |
8883 | } | |
8884 | } | |
8885 | ||
4e53c2e0 | 8886 | static int |
050f7aeb DV |
8887 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8888 | struct drm_framebuffer *fb, | |
8889 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8890 | { |
050f7aeb DV |
8891 | struct drm_device *dev = crtc->base.dev; |
8892 | struct intel_connector *connector; | |
4e53c2e0 DV |
8893 | int bpp; |
8894 | ||
d42264b1 DV |
8895 | switch (fb->pixel_format) { |
8896 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8897 | bpp = 8*3; /* since we go through a colormap */ |
8898 | break; | |
d42264b1 DV |
8899 | case DRM_FORMAT_XRGB1555: |
8900 | case DRM_FORMAT_ARGB1555: | |
8901 | /* checked in intel_framebuffer_init already */ | |
8902 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8903 | return -EINVAL; | |
8904 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8905 | bpp = 6*3; /* min is 18bpp */ |
8906 | break; | |
d42264b1 DV |
8907 | case DRM_FORMAT_XBGR8888: |
8908 | case DRM_FORMAT_ABGR8888: | |
8909 | /* checked in intel_framebuffer_init already */ | |
8910 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8911 | return -EINVAL; | |
8912 | case DRM_FORMAT_XRGB8888: | |
8913 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8914 | bpp = 8*3; |
8915 | break; | |
d42264b1 DV |
8916 | case DRM_FORMAT_XRGB2101010: |
8917 | case DRM_FORMAT_ARGB2101010: | |
8918 | case DRM_FORMAT_XBGR2101010: | |
8919 | case DRM_FORMAT_ABGR2101010: | |
8920 | /* checked in intel_framebuffer_init already */ | |
8921 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8922 | return -EINVAL; |
4e53c2e0 DV |
8923 | bpp = 10*3; |
8924 | break; | |
baba133a | 8925 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8926 | default: |
8927 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8928 | return -EINVAL; | |
8929 | } | |
8930 | ||
4e53c2e0 DV |
8931 | pipe_config->pipe_bpp = bpp; |
8932 | ||
8933 | /* Clamp display bpp to EDID value */ | |
8934 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8935 | base.head) { |
1b829e05 DV |
8936 | if (!connector->new_encoder || |
8937 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8938 | continue; |
8939 | ||
050f7aeb | 8940 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8941 | } |
8942 | ||
8943 | return bpp; | |
8944 | } | |
8945 | ||
644db711 DV |
8946 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8947 | { | |
8948 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8949 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8950 | mode->crtc_clock, |
644db711 DV |
8951 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8952 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8953 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8954 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8955 | } | |
8956 | ||
c0b03411 DV |
8957 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8958 | struct intel_crtc_config *pipe_config, | |
8959 | const char *context) | |
8960 | { | |
8961 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8962 | context, pipe_name(crtc->pipe)); | |
8963 | ||
8964 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8965 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8966 | pipe_config->pipe_bpp, pipe_config->dither); | |
8967 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8968 | pipe_config->has_pch_encoder, | |
8969 | pipe_config->fdi_lanes, | |
8970 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8971 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8972 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8973 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8974 | pipe_config->has_dp_encoder, | |
8975 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8976 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8977 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8978 | DRM_DEBUG_KMS("requested mode:\n"); |
8979 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8980 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8981 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8982 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8983 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8984 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8985 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8986 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8987 | pipe_config->gmch_pfit.control, | |
8988 | pipe_config->gmch_pfit.pgm_ratios, | |
8989 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8990 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8991 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8992 | pipe_config->pch_pfit.size, |
8993 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8994 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8995 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8996 | } |
8997 | ||
accfc0c5 DV |
8998 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8999 | { | |
9000 | int num_encoders = 0; | |
9001 | bool uncloneable_encoders = false; | |
9002 | struct intel_encoder *encoder; | |
9003 | ||
9004 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
9005 | base.head) { | |
9006 | if (&encoder->new_crtc->base != crtc) | |
9007 | continue; | |
9008 | ||
9009 | num_encoders++; | |
9010 | if (!encoder->cloneable) | |
9011 | uncloneable_encoders = true; | |
9012 | } | |
9013 | ||
9014 | return !(num_encoders > 1 && uncloneable_encoders); | |
9015 | } | |
9016 | ||
b8cecdf5 DV |
9017 | static struct intel_crtc_config * |
9018 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9019 | struct drm_framebuffer *fb, |
b8cecdf5 | 9020 | struct drm_display_mode *mode) |
ee7b9f93 | 9021 | { |
7758a113 | 9022 | struct drm_device *dev = crtc->dev; |
7758a113 | 9023 | struct intel_encoder *encoder; |
b8cecdf5 | 9024 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9025 | int plane_bpp, ret = -EINVAL; |
9026 | bool retry = true; | |
ee7b9f93 | 9027 | |
accfc0c5 DV |
9028 | if (!check_encoder_cloning(crtc)) { |
9029 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
9030 | return ERR_PTR(-EINVAL); | |
9031 | } | |
9032 | ||
b8cecdf5 DV |
9033 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9034 | if (!pipe_config) | |
7758a113 DV |
9035 | return ERR_PTR(-ENOMEM); |
9036 | ||
b8cecdf5 DV |
9037 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9038 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9039 | |
e143a21c DV |
9040 | pipe_config->cpu_transcoder = |
9041 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9042 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9043 | |
2960bc9c ID |
9044 | /* |
9045 | * Sanitize sync polarity flags based on requested ones. If neither | |
9046 | * positive or negative polarity is requested, treat this as meaning | |
9047 | * negative polarity. | |
9048 | */ | |
9049 | if (!(pipe_config->adjusted_mode.flags & | |
9050 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9051 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9052 | ||
9053 | if (!(pipe_config->adjusted_mode.flags & | |
9054 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9055 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9056 | ||
050f7aeb DV |
9057 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9058 | * plane pixel format and any sink constraints into account. Returns the | |
9059 | * source plane bpp so that dithering can be selected on mismatches | |
9060 | * after encoders and crtc also have had their say. */ | |
9061 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9062 | fb, pipe_config); | |
4e53c2e0 DV |
9063 | if (plane_bpp < 0) |
9064 | goto fail; | |
9065 | ||
e41a56be VS |
9066 | /* |
9067 | * Determine the real pipe dimensions. Note that stereo modes can | |
9068 | * increase the actual pipe size due to the frame doubling and | |
9069 | * insertion of additional space for blanks between the frame. This | |
9070 | * is stored in the crtc timings. We use the requested mode to do this | |
9071 | * computation to clearly distinguish it from the adjusted mode, which | |
9072 | * can be changed by the connectors in the below retry loop. | |
9073 | */ | |
9074 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9075 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9076 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9077 | ||
e29c22c0 | 9078 | encoder_retry: |
ef1b460d | 9079 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9080 | pipe_config->port_clock = 0; |
ef1b460d | 9081 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9082 | |
135c81b8 | 9083 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9084 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9085 | |
7758a113 DV |
9086 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9087 | * adjust it according to limitations or connector properties, and also | |
9088 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9089 | */ |
7758a113 DV |
9090 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9091 | base.head) { | |
47f1c6c9 | 9092 | |
7758a113 DV |
9093 | if (&encoder->new_crtc->base != crtc) |
9094 | continue; | |
7ae89233 | 9095 | |
efea6e8e DV |
9096 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9097 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9098 | goto fail; |
9099 | } | |
ee7b9f93 | 9100 | } |
47f1c6c9 | 9101 | |
ff9a6750 DV |
9102 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9103 | * done afterwards in case the encoder adjusts the mode. */ | |
9104 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9105 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9106 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9107 | |
a43f6e0f | 9108 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9109 | if (ret < 0) { |
7758a113 DV |
9110 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9111 | goto fail; | |
ee7b9f93 | 9112 | } |
e29c22c0 DV |
9113 | |
9114 | if (ret == RETRY) { | |
9115 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9116 | ret = -EINVAL; | |
9117 | goto fail; | |
9118 | } | |
9119 | ||
9120 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9121 | retry = false; | |
9122 | goto encoder_retry; | |
9123 | } | |
9124 | ||
4e53c2e0 DV |
9125 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9126 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9127 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9128 | ||
b8cecdf5 | 9129 | return pipe_config; |
7758a113 | 9130 | fail: |
b8cecdf5 | 9131 | kfree(pipe_config); |
e29c22c0 | 9132 | return ERR_PTR(ret); |
ee7b9f93 | 9133 | } |
47f1c6c9 | 9134 | |
e2e1ed41 DV |
9135 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9136 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9137 | static void | |
9138 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9139 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9140 | { |
9141 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9142 | struct drm_device *dev = crtc->dev; |
9143 | struct intel_encoder *encoder; | |
9144 | struct intel_connector *connector; | |
9145 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9146 | |
e2e1ed41 | 9147 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9148 | |
e2e1ed41 DV |
9149 | /* Check which crtcs have changed outputs connected to them, these need |
9150 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9151 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9152 | * bit set at most. */ | |
9153 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9154 | base.head) { | |
9155 | if (connector->base.encoder == &connector->new_encoder->base) | |
9156 | continue; | |
79e53945 | 9157 | |
e2e1ed41 DV |
9158 | if (connector->base.encoder) { |
9159 | tmp_crtc = connector->base.encoder->crtc; | |
9160 | ||
9161 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9162 | } | |
9163 | ||
9164 | if (connector->new_encoder) | |
9165 | *prepare_pipes |= | |
9166 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9167 | } |
9168 | ||
e2e1ed41 DV |
9169 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9170 | base.head) { | |
9171 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9172 | continue; | |
9173 | ||
9174 | if (encoder->base.crtc) { | |
9175 | tmp_crtc = encoder->base.crtc; | |
9176 | ||
9177 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9178 | } | |
9179 | ||
9180 | if (encoder->new_crtc) | |
9181 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9182 | } |
9183 | ||
7668851f | 9184 | /* Check for pipes that will be enabled/disabled ... */ |
e2e1ed41 DV |
9185 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9186 | base.head) { | |
7668851f | 9187 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9188 | continue; |
7e7d76c3 | 9189 | |
7668851f | 9190 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9191 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9192 | else |
9193 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9194 | } |
9195 | ||
e2e1ed41 DV |
9196 | |
9197 | /* set_mode is also used to update properties on life display pipes. */ | |
9198 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9199 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9200 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9201 | ||
b6c5164d DV |
9202 | /* |
9203 | * For simplicity do a full modeset on any pipe where the output routing | |
9204 | * changed. We could be more clever, but that would require us to be | |
9205 | * more careful with calling the relevant encoder->mode_set functions. | |
9206 | */ | |
e2e1ed41 DV |
9207 | if (*prepare_pipes) |
9208 | *modeset_pipes = *prepare_pipes; | |
9209 | ||
9210 | /* ... and mask these out. */ | |
9211 | *modeset_pipes &= ~(*disable_pipes); | |
9212 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9213 | |
9214 | /* | |
9215 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9216 | * obies this rule, but the modeset restore mode of | |
9217 | * intel_modeset_setup_hw_state does not. | |
9218 | */ | |
9219 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9220 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9221 | |
9222 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9223 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9224 | } |
79e53945 | 9225 | |
ea9d758d | 9226 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9227 | { |
ea9d758d | 9228 | struct drm_encoder *encoder; |
f6e5b160 | 9229 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9230 | |
ea9d758d DV |
9231 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9232 | if (encoder->crtc == crtc) | |
9233 | return true; | |
9234 | ||
9235 | return false; | |
9236 | } | |
9237 | ||
9238 | static void | |
9239 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9240 | { | |
9241 | struct intel_encoder *intel_encoder; | |
9242 | struct intel_crtc *intel_crtc; | |
9243 | struct drm_connector *connector; | |
9244 | ||
9245 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9246 | base.head) { | |
9247 | if (!intel_encoder->base.crtc) | |
9248 | continue; | |
9249 | ||
9250 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9251 | ||
9252 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9253 | intel_encoder->connectors_active = false; | |
9254 | } | |
9255 | ||
9256 | intel_modeset_commit_output_state(dev); | |
9257 | ||
7668851f | 9258 | /* Double check state. */ |
ea9d758d DV |
9259 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9260 | base.head) { | |
7668851f | 9261 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9262 | WARN_ON(intel_crtc->new_config && |
9263 | intel_crtc->new_config != &intel_crtc->config); | |
9264 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9265 | } |
9266 | ||
9267 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9268 | if (!connector->encoder || !connector->encoder->crtc) | |
9269 | continue; | |
9270 | ||
9271 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9272 | ||
9273 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9274 | struct drm_property *dpms_property = |
9275 | dev->mode_config.dpms_property; | |
9276 | ||
ea9d758d | 9277 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9278 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9279 | dpms_property, |
9280 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9281 | |
9282 | intel_encoder = to_intel_encoder(connector->encoder); | |
9283 | intel_encoder->connectors_active = true; | |
9284 | } | |
9285 | } | |
9286 | ||
9287 | } | |
9288 | ||
3bd26263 | 9289 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9290 | { |
3bd26263 | 9291 | int diff; |
f1f644dc JB |
9292 | |
9293 | if (clock1 == clock2) | |
9294 | return true; | |
9295 | ||
9296 | if (!clock1 || !clock2) | |
9297 | return false; | |
9298 | ||
9299 | diff = abs(clock1 - clock2); | |
9300 | ||
9301 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9302 | return true; | |
9303 | ||
9304 | return false; | |
9305 | } | |
9306 | ||
25c5b266 DV |
9307 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9308 | list_for_each_entry((intel_crtc), \ | |
9309 | &(dev)->mode_config.crtc_list, \ | |
9310 | base.head) \ | |
0973f18f | 9311 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9312 | |
0e8ffe1b | 9313 | static bool |
2fa2fe9a DV |
9314 | intel_pipe_config_compare(struct drm_device *dev, |
9315 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9316 | struct intel_crtc_config *pipe_config) |
9317 | { | |
66e985c0 DV |
9318 | #define PIPE_CONF_CHECK_X(name) \ |
9319 | if (current_config->name != pipe_config->name) { \ | |
9320 | DRM_ERROR("mismatch in " #name " " \ | |
9321 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9322 | current_config->name, \ | |
9323 | pipe_config->name); \ | |
9324 | return false; \ | |
9325 | } | |
9326 | ||
08a24034 DV |
9327 | #define PIPE_CONF_CHECK_I(name) \ |
9328 | if (current_config->name != pipe_config->name) { \ | |
9329 | DRM_ERROR("mismatch in " #name " " \ | |
9330 | "(expected %i, found %i)\n", \ | |
9331 | current_config->name, \ | |
9332 | pipe_config->name); \ | |
9333 | return false; \ | |
88adfff1 DV |
9334 | } |
9335 | ||
1bd1bd80 DV |
9336 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9337 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9338 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9339 | "(expected %i, found %i)\n", \ |
9340 | current_config->name & (mask), \ | |
9341 | pipe_config->name & (mask)); \ | |
9342 | return false; \ | |
9343 | } | |
9344 | ||
5e550656 VS |
9345 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9346 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9347 | DRM_ERROR("mismatch in " #name " " \ | |
9348 | "(expected %i, found %i)\n", \ | |
9349 | current_config->name, \ | |
9350 | pipe_config->name); \ | |
9351 | return false; \ | |
9352 | } | |
9353 | ||
bb760063 DV |
9354 | #define PIPE_CONF_QUIRK(quirk) \ |
9355 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9356 | ||
eccb140b DV |
9357 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9358 | ||
08a24034 DV |
9359 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9360 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9361 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9362 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9363 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9364 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9365 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9366 | |
eb14cb74 VS |
9367 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9368 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9369 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9370 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9371 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9372 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9373 | ||
1bd1bd80 DV |
9374 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9375 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9376 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9377 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9378 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9379 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9380 | ||
9381 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9382 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9383 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9384 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9385 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9386 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9387 | ||
c93f54cf | 9388 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9389 | |
1bd1bd80 DV |
9390 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9391 | DRM_MODE_FLAG_INTERLACE); | |
9392 | ||
bb760063 DV |
9393 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9394 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9395 | DRM_MODE_FLAG_PHSYNC); | |
9396 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9397 | DRM_MODE_FLAG_NHSYNC); | |
9398 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9399 | DRM_MODE_FLAG_PVSYNC); | |
9400 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9401 | DRM_MODE_FLAG_NVSYNC); | |
9402 | } | |
045ac3b5 | 9403 | |
37327abd VS |
9404 | PIPE_CONF_CHECK_I(pipe_src_w); |
9405 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9406 | |
2fa2fe9a DV |
9407 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9408 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9409 | if (INTEL_INFO(dev)->gen < 4) | |
9410 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9411 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9412 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9413 | if (current_config->pch_pfit.enabled) { | |
9414 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9415 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9416 | } | |
2fa2fe9a | 9417 | |
e59150dc JB |
9418 | /* BDW+ don't expose a synchronous way to read the state */ |
9419 | if (IS_HASWELL(dev)) | |
9420 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9421 | |
282740f7 VS |
9422 | PIPE_CONF_CHECK_I(double_wide); |
9423 | ||
c0d43d62 | 9424 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9425 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9426 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9427 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9428 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9429 | |
42571aef VS |
9430 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9431 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9432 | ||
a9a7e98a JB |
9433 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9434 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 9435 | |
66e985c0 | 9436 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9437 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9438 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9439 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9440 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9441 | |
0e8ffe1b DV |
9442 | return true; |
9443 | } | |
9444 | ||
91d1b4bd DV |
9445 | static void |
9446 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9447 | { |
8af6cf88 DV |
9448 | struct intel_connector *connector; |
9449 | ||
9450 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9451 | base.head) { | |
9452 | /* This also checks the encoder/connector hw state with the | |
9453 | * ->get_hw_state callbacks. */ | |
9454 | intel_connector_check_state(connector); | |
9455 | ||
9456 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9457 | "connector's staged encoder doesn't match current encoder\n"); | |
9458 | } | |
91d1b4bd DV |
9459 | } |
9460 | ||
9461 | static void | |
9462 | check_encoder_state(struct drm_device *dev) | |
9463 | { | |
9464 | struct intel_encoder *encoder; | |
9465 | struct intel_connector *connector; | |
8af6cf88 DV |
9466 | |
9467 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9468 | base.head) { | |
9469 | bool enabled = false; | |
9470 | bool active = false; | |
9471 | enum pipe pipe, tracked_pipe; | |
9472 | ||
9473 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9474 | encoder->base.base.id, | |
9475 | drm_get_encoder_name(&encoder->base)); | |
9476 | ||
9477 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9478 | "encoder's stage crtc doesn't match current crtc\n"); | |
9479 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9480 | "encoder's active_connectors set, but no crtc\n"); | |
9481 | ||
9482 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9483 | base.head) { | |
9484 | if (connector->base.encoder != &encoder->base) | |
9485 | continue; | |
9486 | enabled = true; | |
9487 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9488 | active = true; | |
9489 | } | |
9490 | WARN(!!encoder->base.crtc != enabled, | |
9491 | "encoder's enabled state mismatch " | |
9492 | "(expected %i, found %i)\n", | |
9493 | !!encoder->base.crtc, enabled); | |
9494 | WARN(active && !encoder->base.crtc, | |
9495 | "active encoder with no crtc\n"); | |
9496 | ||
9497 | WARN(encoder->connectors_active != active, | |
9498 | "encoder's computed active state doesn't match tracked active state " | |
9499 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9500 | ||
9501 | active = encoder->get_hw_state(encoder, &pipe); | |
9502 | WARN(active != encoder->connectors_active, | |
9503 | "encoder's hw state doesn't match sw tracking " | |
9504 | "(expected %i, found %i)\n", | |
9505 | encoder->connectors_active, active); | |
9506 | ||
9507 | if (!encoder->base.crtc) | |
9508 | continue; | |
9509 | ||
9510 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9511 | WARN(active && pipe != tracked_pipe, | |
9512 | "active encoder's pipe doesn't match" | |
9513 | "(expected %i, found %i)\n", | |
9514 | tracked_pipe, pipe); | |
9515 | ||
9516 | } | |
91d1b4bd DV |
9517 | } |
9518 | ||
9519 | static void | |
9520 | check_crtc_state(struct drm_device *dev) | |
9521 | { | |
9522 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9523 | struct intel_crtc *crtc; | |
9524 | struct intel_encoder *encoder; | |
9525 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9526 | |
9527 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9528 | base.head) { | |
9529 | bool enabled = false; | |
9530 | bool active = false; | |
9531 | ||
045ac3b5 JB |
9532 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9533 | ||
8af6cf88 DV |
9534 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9535 | crtc->base.base.id); | |
9536 | ||
9537 | WARN(crtc->active && !crtc->base.enabled, | |
9538 | "active crtc, but not enabled in sw tracking\n"); | |
9539 | ||
9540 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9541 | base.head) { | |
9542 | if (encoder->base.crtc != &crtc->base) | |
9543 | continue; | |
9544 | enabled = true; | |
9545 | if (encoder->connectors_active) | |
9546 | active = true; | |
9547 | } | |
6c49f241 | 9548 | |
8af6cf88 DV |
9549 | WARN(active != crtc->active, |
9550 | "crtc's computed active state doesn't match tracked active state " | |
9551 | "(expected %i, found %i)\n", active, crtc->active); | |
9552 | WARN(enabled != crtc->base.enabled, | |
9553 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9554 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9555 | ||
0e8ffe1b DV |
9556 | active = dev_priv->display.get_pipe_config(crtc, |
9557 | &pipe_config); | |
d62cf62a DV |
9558 | |
9559 | /* hw state is inconsistent with the pipe A quirk */ | |
9560 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9561 | active = crtc->active; | |
9562 | ||
6c49f241 DV |
9563 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9564 | base.head) { | |
3eaba51c | 9565 | enum pipe pipe; |
6c49f241 DV |
9566 | if (encoder->base.crtc != &crtc->base) |
9567 | continue; | |
1d37b689 | 9568 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
9569 | encoder->get_config(encoder, &pipe_config); |
9570 | } | |
9571 | ||
0e8ffe1b DV |
9572 | WARN(crtc->active != active, |
9573 | "crtc active state doesn't match with hw state " | |
9574 | "(expected %i, found %i)\n", crtc->active, active); | |
9575 | ||
c0b03411 DV |
9576 | if (active && |
9577 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9578 | WARN(1, "pipe state doesn't match!\n"); | |
9579 | intel_dump_pipe_config(crtc, &pipe_config, | |
9580 | "[hw state]"); | |
9581 | intel_dump_pipe_config(crtc, &crtc->config, | |
9582 | "[sw state]"); | |
9583 | } | |
8af6cf88 DV |
9584 | } |
9585 | } | |
9586 | ||
91d1b4bd DV |
9587 | static void |
9588 | check_shared_dpll_state(struct drm_device *dev) | |
9589 | { | |
9590 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9591 | struct intel_crtc *crtc; | |
9592 | struct intel_dpll_hw_state dpll_hw_state; | |
9593 | int i; | |
5358901f DV |
9594 | |
9595 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9596 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9597 | int enabled_crtcs = 0, active_crtcs = 0; | |
9598 | bool active; | |
9599 | ||
9600 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9601 | ||
9602 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9603 | ||
9604 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9605 | ||
9606 | WARN(pll->active > pll->refcount, | |
9607 | "more active pll users than references: %i vs %i\n", | |
9608 | pll->active, pll->refcount); | |
9609 | WARN(pll->active && !pll->on, | |
9610 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9611 | WARN(pll->on && !pll->active, |
9612 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9613 | WARN(pll->on != active, |
9614 | "pll on state mismatch (expected %i, found %i)\n", | |
9615 | pll->on, active); | |
9616 | ||
9617 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9618 | base.head) { | |
9619 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9620 | enabled_crtcs++; | |
9621 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9622 | active_crtcs++; | |
9623 | } | |
9624 | WARN(pll->active != active_crtcs, | |
9625 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9626 | pll->active, active_crtcs); | |
9627 | WARN(pll->refcount != enabled_crtcs, | |
9628 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9629 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9630 | |
9631 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9632 | sizeof(dpll_hw_state)), | |
9633 | "pll hw state mismatch\n"); | |
5358901f | 9634 | } |
8af6cf88 DV |
9635 | } |
9636 | ||
91d1b4bd DV |
9637 | void |
9638 | intel_modeset_check_state(struct drm_device *dev) | |
9639 | { | |
9640 | check_connector_state(dev); | |
9641 | check_encoder_state(dev); | |
9642 | check_crtc_state(dev); | |
9643 | check_shared_dpll_state(dev); | |
9644 | } | |
9645 | ||
18442d08 VS |
9646 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9647 | int dotclock) | |
9648 | { | |
9649 | /* | |
9650 | * FDI already provided one idea for the dotclock. | |
9651 | * Yell if the encoder disagrees. | |
9652 | */ | |
241bfc38 | 9653 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9654 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9655 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9656 | } |
9657 | ||
f30da187 DV |
9658 | static int __intel_set_mode(struct drm_crtc *crtc, |
9659 | struct drm_display_mode *mode, | |
9660 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9661 | { |
9662 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9663 | drm_i915_private_t *dev_priv = dev->dev_private; |
4b4b9238 | 9664 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 9665 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
9666 | struct intel_crtc *intel_crtc; |
9667 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9668 | int ret = 0; |
a6778b3c | 9669 | |
4b4b9238 | 9670 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9671 | if (!saved_mode) |
9672 | return -ENOMEM; | |
a6778b3c | 9673 | |
e2e1ed41 | 9674 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9675 | &prepare_pipes, &disable_pipes); |
9676 | ||
3ac18232 | 9677 | *saved_mode = crtc->mode; |
a6778b3c | 9678 | |
25c5b266 DV |
9679 | /* Hack: Because we don't (yet) support global modeset on multiple |
9680 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9681 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9682 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9683 | * changing their mode at the same time. */ | |
25c5b266 | 9684 | if (modeset_pipes) { |
4e53c2e0 | 9685 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9686 | if (IS_ERR(pipe_config)) { |
9687 | ret = PTR_ERR(pipe_config); | |
9688 | pipe_config = NULL; | |
9689 | ||
3ac18232 | 9690 | goto out; |
25c5b266 | 9691 | } |
c0b03411 DV |
9692 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9693 | "[modeset]"); | |
50741abc | 9694 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 9695 | } |
a6778b3c | 9696 | |
30a970c6 JB |
9697 | /* |
9698 | * See if the config requires any additional preparation, e.g. | |
9699 | * to adjust global state with pipes off. We need to do this | |
9700 | * here so we can get the modeset_pipe updated config for the new | |
9701 | * mode set on this crtc. For other crtcs we need to use the | |
9702 | * adjusted_mode bits in the crtc directly. | |
9703 | */ | |
c164f833 | 9704 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 9705 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 9706 | |
c164f833 VS |
9707 | /* may have added more to prepare_pipes than we should */ |
9708 | prepare_pipes &= ~disable_pipes; | |
9709 | } | |
9710 | ||
460da916 DV |
9711 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9712 | intel_crtc_disable(&intel_crtc->base); | |
9713 | ||
ea9d758d DV |
9714 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9715 | if (intel_crtc->base.enabled) | |
9716 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9717 | } | |
a6778b3c | 9718 | |
6c4c86f5 DV |
9719 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9720 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9721 | */ |
b8cecdf5 | 9722 | if (modeset_pipes) { |
25c5b266 | 9723 | crtc->mode = *mode; |
b8cecdf5 DV |
9724 | /* mode_set/enable/disable functions rely on a correct pipe |
9725 | * config. */ | |
9726 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 9727 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
9728 | |
9729 | /* | |
9730 | * Calculate and store various constants which | |
9731 | * are later needed by vblank and swap-completion | |
9732 | * timestamping. They are derived from true hwmode. | |
9733 | */ | |
9734 | drm_calc_timestamping_constants(crtc, | |
9735 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 9736 | } |
7758a113 | 9737 | |
ea9d758d DV |
9738 | /* Only after disabling all output pipelines that will be changed can we |
9739 | * update the the output configuration. */ | |
9740 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9741 | |
47fab737 DV |
9742 | if (dev_priv->display.modeset_global_resources) |
9743 | dev_priv->display.modeset_global_resources(dev); | |
9744 | ||
a6778b3c DV |
9745 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9746 | * on the DPLL. | |
f6e5b160 | 9747 | */ |
25c5b266 | 9748 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9749 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9750 | x, y, fb); |
9751 | if (ret) | |
9752 | goto done; | |
a6778b3c DV |
9753 | } |
9754 | ||
9755 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9756 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9757 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9758 | |
a6778b3c DV |
9759 | /* FIXME: add subpixel order */ |
9760 | done: | |
4b4b9238 | 9761 | if (ret && crtc->enabled) |
3ac18232 | 9762 | crtc->mode = *saved_mode; |
a6778b3c | 9763 | |
3ac18232 | 9764 | out: |
b8cecdf5 | 9765 | kfree(pipe_config); |
3ac18232 | 9766 | kfree(saved_mode); |
a6778b3c | 9767 | return ret; |
f6e5b160 CW |
9768 | } |
9769 | ||
e7457a9a DL |
9770 | static int intel_set_mode(struct drm_crtc *crtc, |
9771 | struct drm_display_mode *mode, | |
9772 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9773 | { |
9774 | int ret; | |
9775 | ||
9776 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9777 | ||
9778 | if (ret == 0) | |
9779 | intel_modeset_check_state(crtc->dev); | |
9780 | ||
9781 | return ret; | |
9782 | } | |
9783 | ||
c0c36b94 CW |
9784 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9785 | { | |
9786 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9787 | } | |
9788 | ||
25c5b266 DV |
9789 | #undef for_each_intel_crtc_masked |
9790 | ||
d9e55608 DV |
9791 | static void intel_set_config_free(struct intel_set_config *config) |
9792 | { | |
9793 | if (!config) | |
9794 | return; | |
9795 | ||
1aa4b628 DV |
9796 | kfree(config->save_connector_encoders); |
9797 | kfree(config->save_encoder_crtcs); | |
7668851f | 9798 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
9799 | kfree(config); |
9800 | } | |
9801 | ||
85f9eb71 DV |
9802 | static int intel_set_config_save_state(struct drm_device *dev, |
9803 | struct intel_set_config *config) | |
9804 | { | |
7668851f | 9805 | struct drm_crtc *crtc; |
85f9eb71 DV |
9806 | struct drm_encoder *encoder; |
9807 | struct drm_connector *connector; | |
9808 | int count; | |
9809 | ||
7668851f VS |
9810 | config->save_crtc_enabled = |
9811 | kcalloc(dev->mode_config.num_crtc, | |
9812 | sizeof(bool), GFP_KERNEL); | |
9813 | if (!config->save_crtc_enabled) | |
9814 | return -ENOMEM; | |
9815 | ||
1aa4b628 DV |
9816 | config->save_encoder_crtcs = |
9817 | kcalloc(dev->mode_config.num_encoder, | |
9818 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9819 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9820 | return -ENOMEM; |
9821 | ||
1aa4b628 DV |
9822 | config->save_connector_encoders = |
9823 | kcalloc(dev->mode_config.num_connector, | |
9824 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9825 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9826 | return -ENOMEM; |
9827 | ||
9828 | /* Copy data. Note that driver private data is not affected. | |
9829 | * Should anything bad happen only the expected state is | |
9830 | * restored, not the drivers personal bookkeeping. | |
9831 | */ | |
7668851f VS |
9832 | count = 0; |
9833 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9834 | config->save_crtc_enabled[count++] = crtc->enabled; | |
9835 | } | |
9836 | ||
85f9eb71 DV |
9837 | count = 0; |
9838 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9839 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9840 | } |
9841 | ||
9842 | count = 0; | |
9843 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9844 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9845 | } |
9846 | ||
9847 | return 0; | |
9848 | } | |
9849 | ||
9850 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9851 | struct intel_set_config *config) | |
9852 | { | |
7668851f | 9853 | struct intel_crtc *crtc; |
9a935856 DV |
9854 | struct intel_encoder *encoder; |
9855 | struct intel_connector *connector; | |
85f9eb71 DV |
9856 | int count; |
9857 | ||
7668851f VS |
9858 | count = 0; |
9859 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9860 | crtc->new_enabled = config->save_crtc_enabled[count++]; | |
7bd0a8e7 VS |
9861 | |
9862 | if (crtc->new_enabled) | |
9863 | crtc->new_config = &crtc->config; | |
9864 | else | |
9865 | crtc->new_config = NULL; | |
7668851f VS |
9866 | } |
9867 | ||
85f9eb71 | 9868 | count = 0; |
9a935856 DV |
9869 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9870 | encoder->new_crtc = | |
9871 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9872 | } |
9873 | ||
9874 | count = 0; | |
9a935856 DV |
9875 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9876 | connector->new_encoder = | |
9877 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9878 | } |
9879 | } | |
9880 | ||
e3de42b6 | 9881 | static bool |
2e57f47d | 9882 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9883 | { |
9884 | int i; | |
9885 | ||
2e57f47d CW |
9886 | if (set->num_connectors == 0) |
9887 | return false; | |
9888 | ||
9889 | if (WARN_ON(set->connectors == NULL)) | |
9890 | return false; | |
9891 | ||
9892 | for (i = 0; i < set->num_connectors; i++) | |
9893 | if (set->connectors[i]->encoder && | |
9894 | set->connectors[i]->encoder->crtc == set->crtc && | |
9895 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9896 | return true; |
9897 | ||
9898 | return false; | |
9899 | } | |
9900 | ||
5e2b584e DV |
9901 | static void |
9902 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9903 | struct intel_set_config *config) | |
9904 | { | |
9905 | ||
9906 | /* We should be able to check here if the fb has the same properties | |
9907 | * and then just flip_or_move it */ | |
2e57f47d CW |
9908 | if (is_crtc_connector_off(set)) { |
9909 | config->mode_changed = true; | |
e3de42b6 | 9910 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9911 | /* If we have no fb then treat it as a full mode set */ |
9912 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9913 | struct intel_crtc *intel_crtc = |
9914 | to_intel_crtc(set->crtc); | |
9915 | ||
d330a953 | 9916 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
9917 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
9918 | config->fb_changed = true; | |
9919 | } else { | |
9920 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9921 | config->mode_changed = true; | |
9922 | } | |
5e2b584e DV |
9923 | } else if (set->fb == NULL) { |
9924 | config->mode_changed = true; | |
72f4901e DV |
9925 | } else if (set->fb->pixel_format != |
9926 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9927 | config->mode_changed = true; |
e3de42b6 | 9928 | } else { |
5e2b584e | 9929 | config->fb_changed = true; |
e3de42b6 | 9930 | } |
5e2b584e DV |
9931 | } |
9932 | ||
835c5873 | 9933 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9934 | config->fb_changed = true; |
9935 | ||
9936 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9937 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9938 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9939 | drm_mode_debug_printmodeline(set->mode); | |
9940 | config->mode_changed = true; | |
9941 | } | |
a1d95703 CW |
9942 | |
9943 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9944 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9945 | } |
9946 | ||
2e431051 | 9947 | static int |
9a935856 DV |
9948 | intel_modeset_stage_output_state(struct drm_device *dev, |
9949 | struct drm_mode_set *set, | |
9950 | struct intel_set_config *config) | |
50f56119 | 9951 | { |
9a935856 DV |
9952 | struct intel_connector *connector; |
9953 | struct intel_encoder *encoder; | |
7668851f | 9954 | struct intel_crtc *crtc; |
f3f08572 | 9955 | int ro; |
50f56119 | 9956 | |
9abdda74 | 9957 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9958 | * of connectors. For paranoia, double-check this. */ |
9959 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9960 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9961 | ||
9a935856 DV |
9962 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9963 | base.head) { | |
9964 | /* Otherwise traverse passed in connector list and get encoders | |
9965 | * for them. */ | |
50f56119 | 9966 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9967 | if (set->connectors[ro] == &connector->base) { |
9968 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9969 | break; |
9970 | } | |
9971 | } | |
9972 | ||
9a935856 DV |
9973 | /* If we disable the crtc, disable all its connectors. Also, if |
9974 | * the connector is on the changing crtc but not on the new | |
9975 | * connector list, disable it. */ | |
9976 | if ((!set->fb || ro == set->num_connectors) && | |
9977 | connector->base.encoder && | |
9978 | connector->base.encoder->crtc == set->crtc) { | |
9979 | connector->new_encoder = NULL; | |
9980 | ||
9981 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9982 | connector->base.base.id, | |
9983 | drm_get_connector_name(&connector->base)); | |
9984 | } | |
9985 | ||
9986 | ||
9987 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9988 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9989 | config->mode_changed = true; |
50f56119 DV |
9990 | } |
9991 | } | |
9a935856 | 9992 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9993 | |
9a935856 | 9994 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9995 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9996 | base.head) { | |
7668851f VS |
9997 | struct drm_crtc *new_crtc; |
9998 | ||
9a935856 | 9999 | if (!connector->new_encoder) |
50f56119 DV |
10000 | continue; |
10001 | ||
9a935856 | 10002 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
10003 | |
10004 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 10005 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
10006 | new_crtc = set->crtc; |
10007 | } | |
10008 | ||
10009 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
10010 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10011 | new_crtc)) { | |
5e2b584e | 10012 | return -EINVAL; |
50f56119 | 10013 | } |
9a935856 DV |
10014 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10015 | ||
10016 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10017 | connector->base.base.id, | |
10018 | drm_get_connector_name(&connector->base), | |
10019 | new_crtc->base.id); | |
10020 | } | |
10021 | ||
10022 | /* Check for any encoders that needs to be disabled. */ | |
10023 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10024 | base.head) { | |
5a65f358 | 10025 | int num_connectors = 0; |
9a935856 DV |
10026 | list_for_each_entry(connector, |
10027 | &dev->mode_config.connector_list, | |
10028 | base.head) { | |
10029 | if (connector->new_encoder == encoder) { | |
10030 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10031 | num_connectors++; |
9a935856 DV |
10032 | } |
10033 | } | |
5a65f358 PZ |
10034 | |
10035 | if (num_connectors == 0) | |
10036 | encoder->new_crtc = NULL; | |
10037 | else if (num_connectors > 1) | |
10038 | return -EINVAL; | |
10039 | ||
9a935856 DV |
10040 | /* Only now check for crtc changes so we don't miss encoders |
10041 | * that will be disabled. */ | |
10042 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10043 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10044 | config->mode_changed = true; |
50f56119 DV |
10045 | } |
10046 | } | |
9a935856 | 10047 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10048 | |
7668851f VS |
10049 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10050 | base.head) { | |
10051 | crtc->new_enabled = false; | |
10052 | ||
10053 | list_for_each_entry(encoder, | |
10054 | &dev->mode_config.encoder_list, | |
10055 | base.head) { | |
10056 | if (encoder->new_crtc == crtc) { | |
10057 | crtc->new_enabled = true; | |
10058 | break; | |
10059 | } | |
10060 | } | |
10061 | ||
10062 | if (crtc->new_enabled != crtc->base.enabled) { | |
10063 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10064 | crtc->new_enabled ? "en" : "dis"); | |
10065 | config->mode_changed = true; | |
10066 | } | |
7bd0a8e7 VS |
10067 | |
10068 | if (crtc->new_enabled) | |
10069 | crtc->new_config = &crtc->config; | |
10070 | else | |
10071 | crtc->new_config = NULL; | |
7668851f VS |
10072 | } |
10073 | ||
2e431051 DV |
10074 | return 0; |
10075 | } | |
10076 | ||
7d00a1f5 VS |
10077 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10078 | { | |
10079 | struct drm_device *dev = crtc->base.dev; | |
10080 | struct intel_encoder *encoder; | |
10081 | struct intel_connector *connector; | |
10082 | ||
10083 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10084 | pipe_name(crtc->pipe)); | |
10085 | ||
10086 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10087 | if (connector->new_encoder && | |
10088 | connector->new_encoder->new_crtc == crtc) | |
10089 | connector->new_encoder = NULL; | |
10090 | } | |
10091 | ||
10092 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10093 | if (encoder->new_crtc == crtc) | |
10094 | encoder->new_crtc = NULL; | |
10095 | } | |
10096 | ||
10097 | crtc->new_enabled = false; | |
7bd0a8e7 | 10098 | crtc->new_config = NULL; |
7d00a1f5 VS |
10099 | } |
10100 | ||
2e431051 DV |
10101 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10102 | { | |
10103 | struct drm_device *dev; | |
2e431051 DV |
10104 | struct drm_mode_set save_set; |
10105 | struct intel_set_config *config; | |
10106 | int ret; | |
2e431051 | 10107 | |
8d3e375e DV |
10108 | BUG_ON(!set); |
10109 | BUG_ON(!set->crtc); | |
10110 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10111 | |
7e53f3a4 DV |
10112 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10113 | BUG_ON(!set->mode && set->fb); | |
10114 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10115 | |
2e431051 DV |
10116 | if (set->fb) { |
10117 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10118 | set->crtc->base.id, set->fb->base.id, | |
10119 | (int)set->num_connectors, set->x, set->y); | |
10120 | } else { | |
10121 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10122 | } |
10123 | ||
10124 | dev = set->crtc->dev; | |
10125 | ||
10126 | ret = -ENOMEM; | |
10127 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10128 | if (!config) | |
10129 | goto out_config; | |
10130 | ||
10131 | ret = intel_set_config_save_state(dev, config); | |
10132 | if (ret) | |
10133 | goto out_config; | |
10134 | ||
10135 | save_set.crtc = set->crtc; | |
10136 | save_set.mode = &set->crtc->mode; | |
10137 | save_set.x = set->crtc->x; | |
10138 | save_set.y = set->crtc->y; | |
10139 | save_set.fb = set->crtc->fb; | |
10140 | ||
10141 | /* Compute whether we need a full modeset, only an fb base update or no | |
10142 | * change at all. In the future we might also check whether only the | |
10143 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10144 | * such cases. */ | |
10145 | intel_set_config_compute_mode_changes(set, config); | |
10146 | ||
9a935856 | 10147 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10148 | if (ret) |
10149 | goto fail; | |
10150 | ||
5e2b584e | 10151 | if (config->mode_changed) { |
c0c36b94 CW |
10152 | ret = intel_set_mode(set->crtc, set->mode, |
10153 | set->x, set->y, set->fb); | |
5e2b584e | 10154 | } else if (config->fb_changed) { |
4878cae2 VS |
10155 | intel_crtc_wait_for_pending_flips(set->crtc); |
10156 | ||
4f660f49 | 10157 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10158 | set->x, set->y, set->fb); |
7ca51a3a JB |
10159 | /* |
10160 | * In the fastboot case this may be our only check of the | |
10161 | * state after boot. It would be better to only do it on | |
10162 | * the first update, but we don't have a nice way of doing that | |
10163 | * (and really, set_config isn't used much for high freq page | |
10164 | * flipping, so increasing its cost here shouldn't be a big | |
10165 | * deal). | |
10166 | */ | |
d330a953 | 10167 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10168 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10169 | } |
10170 | ||
2d05eae1 | 10171 | if (ret) { |
bf67dfeb DV |
10172 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10173 | set->crtc->base.id, ret); | |
50f56119 | 10174 | fail: |
2d05eae1 | 10175 | intel_set_config_restore_state(dev, config); |
50f56119 | 10176 | |
7d00a1f5 VS |
10177 | /* |
10178 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10179 | * force the pipe off to avoid oopsing in the modeset code | |
10180 | * due to fb==NULL. This should only happen during boot since | |
10181 | * we don't yet reconstruct the FB from the hardware state. | |
10182 | */ | |
10183 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10184 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10185 | ||
2d05eae1 CW |
10186 | /* Try to restore the config */ |
10187 | if (config->mode_changed && | |
10188 | intel_set_mode(save_set.crtc, save_set.mode, | |
10189 | save_set.x, save_set.y, save_set.fb)) | |
10190 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10191 | } | |
50f56119 | 10192 | |
d9e55608 DV |
10193 | out_config: |
10194 | intel_set_config_free(config); | |
50f56119 DV |
10195 | return ret; |
10196 | } | |
f6e5b160 CW |
10197 | |
10198 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10199 | .cursor_set = intel_crtc_cursor_set, |
10200 | .cursor_move = intel_crtc_cursor_move, | |
10201 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10202 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10203 | .destroy = intel_crtc_destroy, |
10204 | .page_flip = intel_crtc_page_flip, | |
10205 | }; | |
10206 | ||
79f689aa PZ |
10207 | static void intel_cpu_pll_init(struct drm_device *dev) |
10208 | { | |
affa9354 | 10209 | if (HAS_DDI(dev)) |
79f689aa PZ |
10210 | intel_ddi_pll_init(dev); |
10211 | } | |
10212 | ||
5358901f DV |
10213 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10214 | struct intel_shared_dpll *pll, | |
10215 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10216 | { |
5358901f | 10217 | uint32_t val; |
ee7b9f93 | 10218 | |
5358901f | 10219 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10220 | hw_state->dpll = val; |
10221 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10222 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10223 | |
10224 | return val & DPLL_VCO_ENABLE; | |
10225 | } | |
10226 | ||
15bdd4cf DV |
10227 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10228 | struct intel_shared_dpll *pll) | |
10229 | { | |
10230 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10231 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10232 | } | |
10233 | ||
e7b903d2 DV |
10234 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10235 | struct intel_shared_dpll *pll) | |
10236 | { | |
e7b903d2 | 10237 | /* PCH refclock must be enabled first */ |
89eff4be | 10238 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10239 | |
15bdd4cf DV |
10240 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10241 | ||
10242 | /* Wait for the clocks to stabilize. */ | |
10243 | POSTING_READ(PCH_DPLL(pll->id)); | |
10244 | udelay(150); | |
10245 | ||
10246 | /* The pixel multiplier can only be updated once the | |
10247 | * DPLL is enabled and the clocks are stable. | |
10248 | * | |
10249 | * So write it again. | |
10250 | */ | |
10251 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10252 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10253 | udelay(200); |
10254 | } | |
10255 | ||
10256 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10257 | struct intel_shared_dpll *pll) | |
10258 | { | |
10259 | struct drm_device *dev = dev_priv->dev; | |
10260 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10261 | |
10262 | /* Make sure no transcoder isn't still depending on us. */ | |
10263 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10264 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10265 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10266 | } |
10267 | ||
15bdd4cf DV |
10268 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10269 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10270 | udelay(200); |
10271 | } | |
10272 | ||
46edb027 DV |
10273 | static char *ibx_pch_dpll_names[] = { |
10274 | "PCH DPLL A", | |
10275 | "PCH DPLL B", | |
10276 | }; | |
10277 | ||
7c74ade1 | 10278 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10279 | { |
e7b903d2 | 10280 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10281 | int i; |
10282 | ||
7c74ade1 | 10283 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10284 | |
e72f9fbf | 10285 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10286 | dev_priv->shared_dplls[i].id = i; |
10287 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10288 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10289 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10290 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10291 | dev_priv->shared_dplls[i].get_hw_state = |
10292 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10293 | } |
10294 | } | |
10295 | ||
7c74ade1 DV |
10296 | static void intel_shared_dpll_init(struct drm_device *dev) |
10297 | { | |
e7b903d2 | 10298 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10299 | |
10300 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10301 | ibx_pch_dpll_init(dev); | |
10302 | else | |
10303 | dev_priv->num_shared_dpll = 0; | |
10304 | ||
10305 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10306 | } |
10307 | ||
b358d0a6 | 10308 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10309 | { |
22fd0fab | 10310 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10311 | struct intel_crtc *intel_crtc; |
10312 | int i; | |
10313 | ||
955382f3 | 10314 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10315 | if (intel_crtc == NULL) |
10316 | return; | |
10317 | ||
10318 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10319 | ||
10320 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10321 | for (i = 0; i < 256; i++) { |
10322 | intel_crtc->lut_r[i] = i; | |
10323 | intel_crtc->lut_g[i] = i; | |
10324 | intel_crtc->lut_b[i] = i; | |
10325 | } | |
10326 | ||
1f1c2e24 VS |
10327 | /* |
10328 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10329 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10330 | */ | |
80824003 JB |
10331 | intel_crtc->pipe = pipe; |
10332 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10333 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10334 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10335 | intel_crtc->plane = !pipe; |
80824003 JB |
10336 | } |
10337 | ||
22fd0fab JB |
10338 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10339 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10340 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10341 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10342 | ||
79e53945 | 10343 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10344 | } |
10345 | ||
752aa88a JB |
10346 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10347 | { | |
10348 | struct drm_encoder *encoder = connector->base.encoder; | |
10349 | ||
10350 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10351 | ||
10352 | if (!encoder) | |
10353 | return INVALID_PIPE; | |
10354 | ||
10355 | return to_intel_crtc(encoder->crtc)->pipe; | |
10356 | } | |
10357 | ||
08d7b3d1 | 10358 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10359 | struct drm_file *file) |
08d7b3d1 | 10360 | { |
08d7b3d1 | 10361 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10362 | struct drm_mode_object *drmmode_obj; |
10363 | struct intel_crtc *crtc; | |
08d7b3d1 | 10364 | |
1cff8f6b DV |
10365 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10366 | return -ENODEV; | |
08d7b3d1 | 10367 | |
c05422d5 DV |
10368 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10369 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10370 | |
c05422d5 | 10371 | if (!drmmode_obj) { |
08d7b3d1 | 10372 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10373 | return -ENOENT; |
08d7b3d1 CW |
10374 | } |
10375 | ||
c05422d5 DV |
10376 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10377 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10378 | |
c05422d5 | 10379 | return 0; |
08d7b3d1 CW |
10380 | } |
10381 | ||
66a9278e | 10382 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10383 | { |
66a9278e DV |
10384 | struct drm_device *dev = encoder->base.dev; |
10385 | struct intel_encoder *source_encoder; | |
79e53945 | 10386 | int index_mask = 0; |
79e53945 JB |
10387 | int entry = 0; |
10388 | ||
66a9278e DV |
10389 | list_for_each_entry(source_encoder, |
10390 | &dev->mode_config.encoder_list, base.head) { | |
10391 | ||
10392 | if (encoder == source_encoder) | |
79e53945 | 10393 | index_mask |= (1 << entry); |
66a9278e DV |
10394 | |
10395 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10396 | if (encoder->cloneable && source_encoder->cloneable) | |
10397 | index_mask |= (1 << entry); | |
10398 | ||
79e53945 JB |
10399 | entry++; |
10400 | } | |
4ef69c7a | 10401 | |
79e53945 JB |
10402 | return index_mask; |
10403 | } | |
10404 | ||
4d302442 CW |
10405 | static bool has_edp_a(struct drm_device *dev) |
10406 | { | |
10407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10408 | ||
10409 | if (!IS_MOBILE(dev)) | |
10410 | return false; | |
10411 | ||
10412 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10413 | return false; | |
10414 | ||
e3589908 | 10415 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
10416 | return false; |
10417 | ||
10418 | return true; | |
10419 | } | |
10420 | ||
ba0fbca4 DL |
10421 | const char *intel_output_name(int output) |
10422 | { | |
10423 | static const char *names[] = { | |
10424 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
10425 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
10426 | [INTEL_OUTPUT_DVO] = "DVO", | |
10427 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
10428 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
10429 | [INTEL_OUTPUT_TVOUT] = "TV", | |
10430 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
10431 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
10432 | [INTEL_OUTPUT_EDP] = "eDP", | |
10433 | [INTEL_OUTPUT_DSI] = "DSI", | |
10434 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
10435 | }; | |
10436 | ||
10437 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
10438 | return "Invalid"; | |
10439 | ||
10440 | return names[output]; | |
10441 | } | |
10442 | ||
79e53945 JB |
10443 | static void intel_setup_outputs(struct drm_device *dev) |
10444 | { | |
725e30ad | 10445 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10446 | struct intel_encoder *encoder; |
cb0953d7 | 10447 | bool dpd_is_edp = false; |
79e53945 | 10448 | |
c9093354 | 10449 | intel_lvds_init(dev); |
79e53945 | 10450 | |
c40c0f5b | 10451 | if (!IS_ULT(dev)) |
79935fca | 10452 | intel_crt_init(dev); |
cb0953d7 | 10453 | |
affa9354 | 10454 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10455 | int found; |
10456 | ||
10457 | /* Haswell uses DDI functions to detect digital outputs */ | |
10458 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10459 | /* DDI A only supports eDP */ | |
10460 | if (found) | |
10461 | intel_ddi_init(dev, PORT_A); | |
10462 | ||
10463 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10464 | * register */ | |
10465 | found = I915_READ(SFUSE_STRAP); | |
10466 | ||
10467 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10468 | intel_ddi_init(dev, PORT_B); | |
10469 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10470 | intel_ddi_init(dev, PORT_C); | |
10471 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10472 | intel_ddi_init(dev, PORT_D); | |
10473 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10474 | int found; |
5d8a7752 | 10475 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
10476 | |
10477 | if (has_edp_a(dev)) | |
10478 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10479 | |
dc0fa718 | 10480 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10481 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10482 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10483 | if (!found) |
e2debe91 | 10484 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10485 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10486 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10487 | } |
10488 | ||
dc0fa718 | 10489 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10490 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10491 | |
dc0fa718 | 10492 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10493 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10494 | |
5eb08b69 | 10495 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10496 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10497 | |
270b3042 | 10498 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10499 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10500 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10501 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10502 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10503 | PORT_B); | |
10504 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10505 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10506 | } | |
10507 | ||
6f6005a5 JB |
10508 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10509 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10510 | PORT_C); | |
10511 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 10512 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 10513 | } |
19c03924 | 10514 | |
3cfca973 | 10515 | intel_dsi_init(dev); |
103a196f | 10516 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10517 | bool found = false; |
7d57382e | 10518 | |
e2debe91 | 10519 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10520 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10521 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10522 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10523 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10524 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10525 | } |
27185ae1 | 10526 | |
e7281eab | 10527 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10528 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10529 | } |
13520b05 KH |
10530 | |
10531 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10532 | |
e2debe91 | 10533 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10534 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10535 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10536 | } |
27185ae1 | 10537 | |
e2debe91 | 10538 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10539 | |
b01f2c3a JB |
10540 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10541 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10542 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10543 | } |
e7281eab | 10544 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10545 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10546 | } |
27185ae1 | 10547 | |
b01f2c3a | 10548 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10549 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10550 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10551 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10552 | intel_dvo_init(dev); |
10553 | ||
103a196f | 10554 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10555 | intel_tv_init(dev); |
10556 | ||
4ef69c7a CW |
10557 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10558 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10559 | encoder->base.possible_clones = | |
66a9278e | 10560 | intel_encoder_clones(encoder); |
79e53945 | 10561 | } |
47356eb6 | 10562 | |
dde86e2d | 10563 | intel_init_pch_refclk(dev); |
270b3042 DV |
10564 | |
10565 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10566 | } |
10567 | ||
10568 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
10569 | { | |
10570 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10571 | |
ef2d633e DV |
10572 | drm_framebuffer_cleanup(fb); |
10573 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
10574 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
10575 | kfree(intel_fb); |
10576 | } | |
10577 | ||
10578 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10579 | struct drm_file *file, |
79e53945 JB |
10580 | unsigned int *handle) |
10581 | { | |
10582 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10583 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10584 | |
05394f39 | 10585 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10586 | } |
10587 | ||
10588 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10589 | .destroy = intel_user_framebuffer_destroy, | |
10590 | .create_handle = intel_user_framebuffer_create_handle, | |
10591 | }; | |
10592 | ||
b5ea642a DV |
10593 | static int intel_framebuffer_init(struct drm_device *dev, |
10594 | struct intel_framebuffer *intel_fb, | |
10595 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10596 | struct drm_i915_gem_object *obj) | |
79e53945 | 10597 | { |
a57ce0b2 | 10598 | int aligned_height; |
a35cdaa0 | 10599 | int pitch_limit; |
79e53945 JB |
10600 | int ret; |
10601 | ||
dd4916c5 DV |
10602 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10603 | ||
c16ed4be CW |
10604 | if (obj->tiling_mode == I915_TILING_Y) { |
10605 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10606 | return -EINVAL; |
c16ed4be | 10607 | } |
57cd6508 | 10608 | |
c16ed4be CW |
10609 | if (mode_cmd->pitches[0] & 63) { |
10610 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10611 | mode_cmd->pitches[0]); | |
57cd6508 | 10612 | return -EINVAL; |
c16ed4be | 10613 | } |
57cd6508 | 10614 | |
a35cdaa0 CW |
10615 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10616 | pitch_limit = 32*1024; | |
10617 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10618 | if (obj->tiling_mode) | |
10619 | pitch_limit = 16*1024; | |
10620 | else | |
10621 | pitch_limit = 32*1024; | |
10622 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10623 | if (obj->tiling_mode) | |
10624 | pitch_limit = 8*1024; | |
10625 | else | |
10626 | pitch_limit = 16*1024; | |
10627 | } else | |
10628 | /* XXX DSPC is limited to 4k tiled */ | |
10629 | pitch_limit = 8*1024; | |
10630 | ||
10631 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10632 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10633 | obj->tiling_mode ? "tiled" : "linear", | |
10634 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10635 | return -EINVAL; |
c16ed4be | 10636 | } |
5d7bd705 VS |
10637 | |
10638 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10639 | mode_cmd->pitches[0] != obj->stride) { |
10640 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10641 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10642 | return -EINVAL; |
c16ed4be | 10643 | } |
5d7bd705 | 10644 | |
57779d06 | 10645 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10646 | switch (mode_cmd->pixel_format) { |
57779d06 | 10647 | case DRM_FORMAT_C8: |
04b3924d VS |
10648 | case DRM_FORMAT_RGB565: |
10649 | case DRM_FORMAT_XRGB8888: | |
10650 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10651 | break; |
10652 | case DRM_FORMAT_XRGB1555: | |
10653 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10654 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10655 | DRM_DEBUG("unsupported pixel format: %s\n", |
10656 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10657 | return -EINVAL; |
c16ed4be | 10658 | } |
57779d06 VS |
10659 | break; |
10660 | case DRM_FORMAT_XBGR8888: | |
10661 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10662 | case DRM_FORMAT_XRGB2101010: |
10663 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10664 | case DRM_FORMAT_XBGR2101010: |
10665 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10666 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10667 | DRM_DEBUG("unsupported pixel format: %s\n", |
10668 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10669 | return -EINVAL; |
c16ed4be | 10670 | } |
b5626747 | 10671 | break; |
04b3924d VS |
10672 | case DRM_FORMAT_YUYV: |
10673 | case DRM_FORMAT_UYVY: | |
10674 | case DRM_FORMAT_YVYU: | |
10675 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10676 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10677 | DRM_DEBUG("unsupported pixel format: %s\n", |
10678 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10679 | return -EINVAL; |
c16ed4be | 10680 | } |
57cd6508 CW |
10681 | break; |
10682 | default: | |
4ee62c76 VS |
10683 | DRM_DEBUG("unsupported pixel format: %s\n", |
10684 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10685 | return -EINVAL; |
10686 | } | |
10687 | ||
90f9a336 VS |
10688 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10689 | if (mode_cmd->offsets[0] != 0) | |
10690 | return -EINVAL; | |
10691 | ||
a57ce0b2 JB |
10692 | aligned_height = intel_align_height(dev, mode_cmd->height, |
10693 | obj->tiling_mode); | |
53155c0a DV |
10694 | /* FIXME drm helper for size checks (especially planar formats)? */ |
10695 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10696 | return -EINVAL; | |
10697 | ||
c7d73f6a DV |
10698 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10699 | intel_fb->obj = obj; | |
80075d49 | 10700 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10701 | |
79e53945 JB |
10702 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10703 | if (ret) { | |
10704 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10705 | return ret; | |
10706 | } | |
10707 | ||
79e53945 JB |
10708 | return 0; |
10709 | } | |
10710 | ||
79e53945 JB |
10711 | static struct drm_framebuffer * |
10712 | intel_user_framebuffer_create(struct drm_device *dev, | |
10713 | struct drm_file *filp, | |
308e5bcb | 10714 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10715 | { |
05394f39 | 10716 | struct drm_i915_gem_object *obj; |
79e53945 | 10717 | |
308e5bcb JB |
10718 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10719 | mode_cmd->handles[0])); | |
c8725226 | 10720 | if (&obj->base == NULL) |
cce13ff7 | 10721 | return ERR_PTR(-ENOENT); |
79e53945 | 10722 | |
d2dff872 | 10723 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10724 | } |
10725 | ||
4520f53a | 10726 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10727 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10728 | { |
10729 | } | |
10730 | #endif | |
10731 | ||
79e53945 | 10732 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10733 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10734 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10735 | }; |
10736 | ||
e70236a8 JB |
10737 | /* Set up chip specific display functions */ |
10738 | static void intel_init_display(struct drm_device *dev) | |
10739 | { | |
10740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10741 | ||
ee9300bb DV |
10742 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10743 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10744 | else if (IS_VALLEYVIEW(dev)) | |
10745 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10746 | else if (IS_PINEVIEW(dev)) | |
10747 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10748 | else | |
10749 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10750 | ||
affa9354 | 10751 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10752 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10753 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10754 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10755 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10756 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10757 | dev_priv->display.update_plane = ironlake_update_plane; |
10758 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10759 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10760 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10761 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10762 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10763 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10764 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10765 | } else if (IS_VALLEYVIEW(dev)) { |
10766 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10767 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10768 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10769 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10770 | dev_priv->display.off = i9xx_crtc_off; | |
10771 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10772 | } else { |
0e8ffe1b | 10773 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10774 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10775 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10776 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10777 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10778 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10779 | } |
e70236a8 | 10780 | |
e70236a8 | 10781 | /* Returns the core display clock speed */ |
25eb05fc JB |
10782 | if (IS_VALLEYVIEW(dev)) |
10783 | dev_priv->display.get_display_clock_speed = | |
10784 | valleyview_get_display_clock_speed; | |
10785 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10786 | dev_priv->display.get_display_clock_speed = |
10787 | i945_get_display_clock_speed; | |
10788 | else if (IS_I915G(dev)) | |
10789 | dev_priv->display.get_display_clock_speed = | |
10790 | i915_get_display_clock_speed; | |
257a7ffc | 10791 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10792 | dev_priv->display.get_display_clock_speed = |
10793 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10794 | else if (IS_PINEVIEW(dev)) |
10795 | dev_priv->display.get_display_clock_speed = | |
10796 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10797 | else if (IS_I915GM(dev)) |
10798 | dev_priv->display.get_display_clock_speed = | |
10799 | i915gm_get_display_clock_speed; | |
10800 | else if (IS_I865G(dev)) | |
10801 | dev_priv->display.get_display_clock_speed = | |
10802 | i865_get_display_clock_speed; | |
f0f8a9ce | 10803 | else if (IS_I85X(dev)) |
e70236a8 JB |
10804 | dev_priv->display.get_display_clock_speed = |
10805 | i855_get_display_clock_speed; | |
10806 | else /* 852, 830 */ | |
10807 | dev_priv->display.get_display_clock_speed = | |
10808 | i830_get_display_clock_speed; | |
10809 | ||
7f8a8569 | 10810 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10811 | if (IS_GEN5(dev)) { |
674cf967 | 10812 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10813 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10814 | } else if (IS_GEN6(dev)) { |
674cf967 | 10815 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10816 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10817 | } else if (IS_IVYBRIDGE(dev)) { |
10818 | /* FIXME: detect B0+ stepping and use auto training */ | |
10819 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10820 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10821 | dev_priv->display.modeset_global_resources = |
10822 | ivb_modeset_global_resources; | |
4e0bbc31 | 10823 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 10824 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 10825 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10826 | dev_priv->display.modeset_global_resources = |
10827 | haswell_modeset_global_resources; | |
a0e63c22 | 10828 | } |
6067aaea | 10829 | } else if (IS_G4X(dev)) { |
e0dac65e | 10830 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
10831 | } else if (IS_VALLEYVIEW(dev)) { |
10832 | dev_priv->display.modeset_global_resources = | |
10833 | valleyview_modeset_global_resources; | |
9ca2fe73 | 10834 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 10835 | } |
8c9f3aaf JB |
10836 | |
10837 | /* Default just returns -ENODEV to indicate unsupported */ | |
10838 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10839 | ||
10840 | switch (INTEL_INFO(dev)->gen) { | |
10841 | case 2: | |
10842 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10843 | break; | |
10844 | ||
10845 | case 3: | |
10846 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10847 | break; | |
10848 | ||
10849 | case 4: | |
10850 | case 5: | |
10851 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10852 | break; | |
10853 | ||
10854 | case 6: | |
10855 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10856 | break; | |
7c9017e5 | 10857 | case 7: |
4e0bbc31 | 10858 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
10859 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
10860 | break; | |
8c9f3aaf | 10861 | } |
7bd688cd JN |
10862 | |
10863 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
10864 | } |
10865 | ||
b690e96c JB |
10866 | /* |
10867 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10868 | * resume, or other times. This quirk makes sure that's the case for | |
10869 | * affected systems. | |
10870 | */ | |
0206e353 | 10871 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10872 | { |
10873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10874 | ||
10875 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10876 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10877 | } |
10878 | ||
435793df KP |
10879 | /* |
10880 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10881 | */ | |
10882 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10883 | { | |
10884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10885 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10886 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10887 | } |
10888 | ||
4dca20ef | 10889 | /* |
5a15ab5b CE |
10890 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10891 | * brightness value | |
4dca20ef CE |
10892 | */ |
10893 | static void quirk_invert_brightness(struct drm_device *dev) | |
10894 | { | |
10895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10896 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10897 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10898 | } |
10899 | ||
b690e96c JB |
10900 | struct intel_quirk { |
10901 | int device; | |
10902 | int subsystem_vendor; | |
10903 | int subsystem_device; | |
10904 | void (*hook)(struct drm_device *dev); | |
10905 | }; | |
10906 | ||
5f85f176 EE |
10907 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10908 | struct intel_dmi_quirk { | |
10909 | void (*hook)(struct drm_device *dev); | |
10910 | const struct dmi_system_id (*dmi_id_list)[]; | |
10911 | }; | |
10912 | ||
10913 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10914 | { | |
10915 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10916 | return 1; | |
10917 | } | |
10918 | ||
10919 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10920 | { | |
10921 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10922 | { | |
10923 | .callback = intel_dmi_reverse_brightness, | |
10924 | .ident = "NCR Corporation", | |
10925 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10926 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10927 | }, | |
10928 | }, | |
10929 | { } /* terminating entry */ | |
10930 | }, | |
10931 | .hook = quirk_invert_brightness, | |
10932 | }, | |
10933 | }; | |
10934 | ||
c43b5634 | 10935 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10936 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10937 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10938 | |
b690e96c JB |
10939 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10940 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10941 | ||
b690e96c JB |
10942 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10943 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10944 | ||
a4945f95 | 10945 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 10946 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10947 | |
10948 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10949 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10950 | |
10951 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10952 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10953 | |
be505f64 AH |
10954 | /* Acer Aspire 5734Z must invert backlight brightness */ |
10955 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
10956 | ||
10957 | /* Acer/eMachines G725 */ | |
10958 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
10959 | ||
10960 | /* Acer/eMachines e725 */ | |
10961 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
10962 | ||
10963 | /* Acer/Packard Bell NCL20 */ | |
10964 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
10965 | ||
10966 | /* Acer Aspire 4736Z */ | |
10967 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
10968 | |
10969 | /* Acer Aspire 5336 */ | |
10970 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
10971 | }; |
10972 | ||
10973 | static void intel_init_quirks(struct drm_device *dev) | |
10974 | { | |
10975 | struct pci_dev *d = dev->pdev; | |
10976 | int i; | |
10977 | ||
10978 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10979 | struct intel_quirk *q = &intel_quirks[i]; | |
10980 | ||
10981 | if (d->device == q->device && | |
10982 | (d->subsystem_vendor == q->subsystem_vendor || | |
10983 | q->subsystem_vendor == PCI_ANY_ID) && | |
10984 | (d->subsystem_device == q->subsystem_device || | |
10985 | q->subsystem_device == PCI_ANY_ID)) | |
10986 | q->hook(dev); | |
10987 | } | |
5f85f176 EE |
10988 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10989 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10990 | intel_dmi_quirks[i].hook(dev); | |
10991 | } | |
b690e96c JB |
10992 | } |
10993 | ||
9cce37f4 JB |
10994 | /* Disable the VGA plane that we never use */ |
10995 | static void i915_disable_vga(struct drm_device *dev) | |
10996 | { | |
10997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10998 | u8 sr1; | |
766aa1c4 | 10999 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 11000 | |
2b37c616 | 11001 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 11002 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 11003 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
11004 | sr1 = inb(VGA_SR_DATA); |
11005 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
11006 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
11007 | udelay(300); | |
11008 | ||
11009 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
11010 | POSTING_READ(vga_reg); | |
11011 | } | |
11012 | ||
f817586c DV |
11013 | void intel_modeset_init_hw(struct drm_device *dev) |
11014 | { | |
a8f78b58 ED |
11015 | intel_prepare_ddi(dev); |
11016 | ||
f817586c DV |
11017 | intel_init_clock_gating(dev); |
11018 | ||
5382f5f3 | 11019 | intel_reset_dpio(dev); |
40e9cf64 | 11020 | |
79f5b2c7 | 11021 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 11022 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 11023 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
11024 | } |
11025 | ||
7d708ee4 ID |
11026 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11027 | { | |
11028 | intel_suspend_hw(dev); | |
11029 | } | |
11030 | ||
79e53945 JB |
11031 | void intel_modeset_init(struct drm_device *dev) |
11032 | { | |
652c393a | 11033 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 11034 | int sprite, ret; |
8cc87b75 | 11035 | enum pipe pipe; |
79e53945 JB |
11036 | |
11037 | drm_mode_config_init(dev); | |
11038 | ||
11039 | dev->mode_config.min_width = 0; | |
11040 | dev->mode_config.min_height = 0; | |
11041 | ||
019d96cb DA |
11042 | dev->mode_config.preferred_depth = 24; |
11043 | dev->mode_config.prefer_shadow = 1; | |
11044 | ||
e6ecefaa | 11045 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11046 | |
b690e96c JB |
11047 | intel_init_quirks(dev); |
11048 | ||
1fa61106 ED |
11049 | intel_init_pm(dev); |
11050 | ||
e3c74757 BW |
11051 | if (INTEL_INFO(dev)->num_pipes == 0) |
11052 | return; | |
11053 | ||
e70236a8 JB |
11054 | intel_init_display(dev); |
11055 | ||
a6c45cf0 CW |
11056 | if (IS_GEN2(dev)) { |
11057 | dev->mode_config.max_width = 2048; | |
11058 | dev->mode_config.max_height = 2048; | |
11059 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11060 | dev->mode_config.max_width = 4096; |
11061 | dev->mode_config.max_height = 4096; | |
79e53945 | 11062 | } else { |
a6c45cf0 CW |
11063 | dev->mode_config.max_width = 8192; |
11064 | dev->mode_config.max_height = 8192; | |
79e53945 | 11065 | } |
5d4545ae | 11066 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11067 | |
28c97730 | 11068 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11069 | INTEL_INFO(dev)->num_pipes, |
11070 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11071 | |
8cc87b75 DL |
11072 | for_each_pipe(pipe) { |
11073 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
11074 | for_each_sprite(pipe, sprite) { |
11075 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 11076 | if (ret) |
06da8da2 | 11077 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 11078 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 11079 | } |
79e53945 JB |
11080 | } |
11081 | ||
f42bb70d | 11082 | intel_init_dpio(dev); |
5382f5f3 | 11083 | intel_reset_dpio(dev); |
f42bb70d | 11084 | |
79f689aa | 11085 | intel_cpu_pll_init(dev); |
e72f9fbf | 11086 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11087 | |
9cce37f4 JB |
11088 | /* Just disable it once at startup */ |
11089 | i915_disable_vga(dev); | |
79e53945 | 11090 | intel_setup_outputs(dev); |
11be49eb CW |
11091 | |
11092 | /* Just in case the BIOS is doing something questionable. */ | |
11093 | intel_disable_fbc(dev); | |
fa9fa083 | 11094 | |
8b687df4 | 11095 | mutex_lock(&dev->mode_config.mutex); |
fa9fa083 | 11096 | intel_modeset_setup_hw_state(dev, false); |
8b687df4 | 11097 | mutex_unlock(&dev->mode_config.mutex); |
2c7111db CW |
11098 | } |
11099 | ||
24929352 DV |
11100 | static void |
11101 | intel_connector_break_all_links(struct intel_connector *connector) | |
11102 | { | |
11103 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11104 | connector->base.encoder = NULL; | |
11105 | connector->encoder->connectors_active = false; | |
11106 | connector->encoder->base.crtc = NULL; | |
11107 | } | |
11108 | ||
7fad798e DV |
11109 | static void intel_enable_pipe_a(struct drm_device *dev) |
11110 | { | |
11111 | struct intel_connector *connector; | |
11112 | struct drm_connector *crt = NULL; | |
11113 | struct intel_load_detect_pipe load_detect_temp; | |
11114 | ||
11115 | /* We can't just switch on the pipe A, we need to set things up with a | |
11116 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11117 | * by enabling the load detect pipe once. */ | |
11118 | list_for_each_entry(connector, | |
11119 | &dev->mode_config.connector_list, | |
11120 | base.head) { | |
11121 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11122 | crt = &connector->base; | |
11123 | break; | |
11124 | } | |
11125 | } | |
11126 | ||
11127 | if (!crt) | |
11128 | return; | |
11129 | ||
11130 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11131 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11132 | ||
652c393a | 11133 | |
7fad798e DV |
11134 | } |
11135 | ||
fa555837 DV |
11136 | static bool |
11137 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11138 | { | |
7eb552ae BW |
11139 | struct drm_device *dev = crtc->base.dev; |
11140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11141 | u32 reg, val; |
11142 | ||
7eb552ae | 11143 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11144 | return true; |
11145 | ||
11146 | reg = DSPCNTR(!crtc->plane); | |
11147 | val = I915_READ(reg); | |
11148 | ||
11149 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11150 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11151 | return false; | |
11152 | ||
11153 | return true; | |
11154 | } | |
11155 | ||
24929352 DV |
11156 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11157 | { | |
11158 | struct drm_device *dev = crtc->base.dev; | |
11159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11160 | u32 reg; |
24929352 | 11161 | |
24929352 | 11162 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11163 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11164 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11165 | ||
11166 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
11167 | * disable the crtc (and hence change the state) if it is wrong. Note |
11168 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11169 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11170 | struct intel_connector *connector; |
11171 | bool plane; | |
11172 | ||
24929352 DV |
11173 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11174 | crtc->base.base.id); | |
11175 | ||
11176 | /* Pipe has the wrong plane attached and the plane is active. | |
11177 | * Temporarily change the plane mapping and disable everything | |
11178 | * ... */ | |
11179 | plane = crtc->plane; | |
11180 | crtc->plane = !plane; | |
11181 | dev_priv->display.crtc_disable(&crtc->base); | |
11182 | crtc->plane = plane; | |
11183 | ||
11184 | /* ... and break all links. */ | |
11185 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11186 | base.head) { | |
11187 | if (connector->encoder->base.crtc != &crtc->base) | |
11188 | continue; | |
11189 | ||
11190 | intel_connector_break_all_links(connector); | |
11191 | } | |
11192 | ||
11193 | WARN_ON(crtc->active); | |
11194 | crtc->base.enabled = false; | |
11195 | } | |
24929352 | 11196 | |
7fad798e DV |
11197 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11198 | crtc->pipe == PIPE_A && !crtc->active) { | |
11199 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11200 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11201 | * call below we restore the pipe to the right state, but leave | |
11202 | * the required bits on. */ | |
11203 | intel_enable_pipe_a(dev); | |
11204 | } | |
11205 | ||
24929352 DV |
11206 | /* Adjust the state of the output pipe according to whether we |
11207 | * have active connectors/encoders. */ | |
11208 | intel_crtc_update_dpms(&crtc->base); | |
11209 | ||
11210 | if (crtc->active != crtc->base.enabled) { | |
11211 | struct intel_encoder *encoder; | |
11212 | ||
11213 | /* This can happen either due to bugs in the get_hw_state | |
11214 | * functions or because the pipe is force-enabled due to the | |
11215 | * pipe A quirk. */ | |
11216 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11217 | crtc->base.base.id, | |
11218 | crtc->base.enabled ? "enabled" : "disabled", | |
11219 | crtc->active ? "enabled" : "disabled"); | |
11220 | ||
11221 | crtc->base.enabled = crtc->active; | |
11222 | ||
11223 | /* Because we only establish the connector -> encoder -> | |
11224 | * crtc links if something is active, this means the | |
11225 | * crtc is now deactivated. Break the links. connector | |
11226 | * -> encoder links are only establish when things are | |
11227 | * actually up, hence no need to break them. */ | |
11228 | WARN_ON(crtc->active); | |
11229 | ||
11230 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11231 | WARN_ON(encoder->connectors_active); | |
11232 | encoder->base.crtc = NULL; | |
11233 | } | |
11234 | } | |
11235 | } | |
11236 | ||
11237 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11238 | { | |
11239 | struct intel_connector *connector; | |
11240 | struct drm_device *dev = encoder->base.dev; | |
11241 | ||
11242 | /* We need to check both for a crtc link (meaning that the | |
11243 | * encoder is active and trying to read from a pipe) and the | |
11244 | * pipe itself being active. */ | |
11245 | bool has_active_crtc = encoder->base.crtc && | |
11246 | to_intel_crtc(encoder->base.crtc)->active; | |
11247 | ||
11248 | if (encoder->connectors_active && !has_active_crtc) { | |
11249 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11250 | encoder->base.base.id, | |
11251 | drm_get_encoder_name(&encoder->base)); | |
11252 | ||
11253 | /* Connector is active, but has no active pipe. This is | |
11254 | * fallout from our resume register restoring. Disable | |
11255 | * the encoder manually again. */ | |
11256 | if (encoder->base.crtc) { | |
11257 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11258 | encoder->base.base.id, | |
11259 | drm_get_encoder_name(&encoder->base)); | |
11260 | encoder->disable(encoder); | |
11261 | } | |
11262 | ||
11263 | /* Inconsistent output/port/pipe state happens presumably due to | |
11264 | * a bug in one of the get_hw_state functions. Or someplace else | |
11265 | * in our code, like the register restore mess on resume. Clamp | |
11266 | * things to off as a safer default. */ | |
11267 | list_for_each_entry(connector, | |
11268 | &dev->mode_config.connector_list, | |
11269 | base.head) { | |
11270 | if (connector->encoder != encoder) | |
11271 | continue; | |
11272 | ||
11273 | intel_connector_break_all_links(connector); | |
11274 | } | |
11275 | } | |
11276 | /* Enabled encoders without active connectors will be fixed in | |
11277 | * the crtc fixup. */ | |
11278 | } | |
11279 | ||
04098753 | 11280 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
11281 | { |
11282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11283 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11284 | |
04098753 ID |
11285 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
11286 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
11287 | i915_disable_vga(dev); | |
11288 | } | |
11289 | } | |
11290 | ||
11291 | void i915_redisable_vga(struct drm_device *dev) | |
11292 | { | |
11293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11294 | ||
8dc8a27c PZ |
11295 | /* This function can be called both from intel_modeset_setup_hw_state or |
11296 | * at a very early point in our resume sequence, where the power well | |
11297 | * structures are not yet restored. Since this function is at a very | |
11298 | * paranoid "someone might have enabled VGA while we were not looking" | |
11299 | * level, just check if the power well is enabled instead of trying to | |
11300 | * follow the "don't touch the power well if we don't need it" policy | |
11301 | * the rest of the driver uses. */ | |
04098753 | 11302 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
11303 | return; |
11304 | ||
04098753 | 11305 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
11306 | } |
11307 | ||
30e984df | 11308 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11309 | { |
11310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11311 | enum pipe pipe; | |
24929352 DV |
11312 | struct intel_crtc *crtc; |
11313 | struct intel_encoder *encoder; | |
11314 | struct intel_connector *connector; | |
5358901f | 11315 | int i; |
24929352 | 11316 | |
0e8ffe1b DV |
11317 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11318 | base.head) { | |
88adfff1 | 11319 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11320 | |
0e8ffe1b DV |
11321 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11322 | &crtc->config); | |
24929352 DV |
11323 | |
11324 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11325 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11326 | |
11327 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11328 | crtc->base.base.id, | |
11329 | crtc->active ? "enabled" : "disabled"); | |
11330 | } | |
11331 | ||
5358901f | 11332 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11333 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11334 | intel_ddi_setup_hw_pll_state(dev); |
11335 | ||
5358901f DV |
11336 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11337 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11338 | ||
11339 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11340 | pll->active = 0; | |
11341 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11342 | base.head) { | |
11343 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11344 | pll->active++; | |
11345 | } | |
11346 | pll->refcount = pll->active; | |
11347 | ||
35c95375 DV |
11348 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11349 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11350 | } |
11351 | ||
24929352 DV |
11352 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11353 | base.head) { | |
11354 | pipe = 0; | |
11355 | ||
11356 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11357 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11358 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11359 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11360 | } else { |
11361 | encoder->base.crtc = NULL; | |
11362 | } | |
11363 | ||
11364 | encoder->connectors_active = false; | |
6f2bcceb | 11365 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11366 | encoder->base.base.id, |
11367 | drm_get_encoder_name(&encoder->base), | |
11368 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11369 | pipe_name(pipe)); |
24929352 DV |
11370 | } |
11371 | ||
11372 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11373 | base.head) { | |
11374 | if (connector->get_hw_state(connector)) { | |
11375 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11376 | connector->encoder->connectors_active = true; | |
11377 | connector->base.encoder = &connector->encoder->base; | |
11378 | } else { | |
11379 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11380 | connector->base.encoder = NULL; | |
11381 | } | |
11382 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11383 | connector->base.base.id, | |
11384 | drm_get_connector_name(&connector->base), | |
11385 | connector->base.encoder ? "enabled" : "disabled"); | |
11386 | } | |
30e984df DV |
11387 | } |
11388 | ||
11389 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11390 | * and i915 state tracking structures. */ | |
11391 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11392 | bool force_restore) | |
11393 | { | |
11394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11395 | enum pipe pipe; | |
30e984df DV |
11396 | struct intel_crtc *crtc; |
11397 | struct intel_encoder *encoder; | |
35c95375 | 11398 | int i; |
30e984df DV |
11399 | |
11400 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11401 | |
babea61d JB |
11402 | /* |
11403 | * Now that we have the config, copy it to each CRTC struct | |
11404 | * Note that this could go away if we move to using crtc_config | |
11405 | * checking everywhere. | |
11406 | */ | |
11407 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11408 | base.head) { | |
d330a953 | 11409 | if (crtc->active && i915.fastboot) { |
f6a83288 | 11410 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
11411 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
11412 | crtc->base.base.id); | |
11413 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11414 | } | |
11415 | } | |
11416 | ||
24929352 DV |
11417 | /* HW state is read out, now we need to sanitize this mess. */ |
11418 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11419 | base.head) { | |
11420 | intel_sanitize_encoder(encoder); | |
11421 | } | |
11422 | ||
11423 | for_each_pipe(pipe) { | |
11424 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11425 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11426 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11427 | } |
9a935856 | 11428 | |
35c95375 DV |
11429 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11430 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11431 | ||
11432 | if (!pll->on || pll->active) | |
11433 | continue; | |
11434 | ||
11435 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11436 | ||
11437 | pll->disable(dev_priv, pll); | |
11438 | pll->on = false; | |
11439 | } | |
11440 | ||
96f90c54 | 11441 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
11442 | ilk_wm_get_hw_state(dev); |
11443 | ||
45e2b5f6 | 11444 | if (force_restore) { |
7d0bc1ea VS |
11445 | i915_redisable_vga(dev); |
11446 | ||
f30da187 DV |
11447 | /* |
11448 | * We need to use raw interfaces for restoring state to avoid | |
11449 | * checking (bogus) intermediate states. | |
11450 | */ | |
45e2b5f6 | 11451 | for_each_pipe(pipe) { |
b5644d05 JB |
11452 | struct drm_crtc *crtc = |
11453 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11454 | |
11455 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11456 | crtc->fb); | |
45e2b5f6 DV |
11457 | } |
11458 | } else { | |
11459 | intel_modeset_update_staged_output_state(dev); | |
11460 | } | |
8af6cf88 DV |
11461 | |
11462 | intel_modeset_check_state(dev); | |
2c7111db CW |
11463 | } |
11464 | ||
11465 | void intel_modeset_gem_init(struct drm_device *dev) | |
11466 | { | |
1833b134 | 11467 | intel_modeset_init_hw(dev); |
02e792fb DV |
11468 | |
11469 | intel_setup_overlay(dev); | |
79e53945 JB |
11470 | } |
11471 | ||
4932e2c3 ID |
11472 | void intel_connector_unregister(struct intel_connector *intel_connector) |
11473 | { | |
11474 | struct drm_connector *connector = &intel_connector->base; | |
11475 | ||
11476 | intel_panel_destroy_backlight(connector); | |
11477 | drm_sysfs_connector_remove(connector); | |
11478 | } | |
11479 | ||
79e53945 JB |
11480 | void intel_modeset_cleanup(struct drm_device *dev) |
11481 | { | |
652c393a JB |
11482 | struct drm_i915_private *dev_priv = dev->dev_private; |
11483 | struct drm_crtc *crtc; | |
d9255d57 | 11484 | struct drm_connector *connector; |
652c393a | 11485 | |
fd0c0642 DV |
11486 | /* |
11487 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11488 | * Too much stuff here (turning of rps, connectors, ...) would | |
11489 | * experience fancy races otherwise. | |
11490 | */ | |
11491 | drm_irq_uninstall(dev); | |
11492 | cancel_work_sync(&dev_priv->hotplug_work); | |
11493 | /* | |
11494 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11495 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11496 | */ | |
f87ea761 | 11497 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11498 | |
652c393a JB |
11499 | mutex_lock(&dev->struct_mutex); |
11500 | ||
723bfd70 JB |
11501 | intel_unregister_dsm_handler(); |
11502 | ||
652c393a JB |
11503 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11504 | /* Skip inactive CRTCs */ | |
11505 | if (!crtc->fb) | |
11506 | continue; | |
11507 | ||
3dec0095 | 11508 | intel_increase_pllclock(crtc); |
652c393a JB |
11509 | } |
11510 | ||
973d04f9 | 11511 | intel_disable_fbc(dev); |
e70236a8 | 11512 | |
8090c6b9 | 11513 | intel_disable_gt_powersave(dev); |
0cdab21f | 11514 | |
930ebb46 DV |
11515 | ironlake_teardown_rc6(dev); |
11516 | ||
69341a5e KH |
11517 | mutex_unlock(&dev->struct_mutex); |
11518 | ||
1630fe75 CW |
11519 | /* flush any delayed tasks or pending work */ |
11520 | flush_scheduled_work(); | |
11521 | ||
db31af1d JN |
11522 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11523 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
11524 | struct intel_connector *intel_connector; |
11525 | ||
11526 | intel_connector = to_intel_connector(connector); | |
11527 | intel_connector->unregister(intel_connector); | |
db31af1d | 11528 | } |
d9255d57 | 11529 | |
79e53945 | 11530 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11531 | |
11532 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11533 | } |
11534 | ||
f1c79df3 ZW |
11535 | /* |
11536 | * Return which encoder is currently attached for connector. | |
11537 | */ | |
df0e9248 | 11538 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11539 | { |
df0e9248 CW |
11540 | return &intel_attached_encoder(connector)->base; |
11541 | } | |
f1c79df3 | 11542 | |
df0e9248 CW |
11543 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11544 | struct intel_encoder *encoder) | |
11545 | { | |
11546 | connector->encoder = encoder; | |
11547 | drm_mode_connector_attach_encoder(&connector->base, | |
11548 | &encoder->base); | |
79e53945 | 11549 | } |
28d52043 DA |
11550 | |
11551 | /* | |
11552 | * set vga decode state - true == enable VGA decode | |
11553 | */ | |
11554 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11555 | { | |
11556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 11557 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
11558 | u16 gmch_ctrl; |
11559 | ||
75fa041d CW |
11560 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
11561 | DRM_ERROR("failed to read control word\n"); | |
11562 | return -EIO; | |
11563 | } | |
11564 | ||
c0cc8a55 CW |
11565 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
11566 | return 0; | |
11567 | ||
28d52043 DA |
11568 | if (state) |
11569 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11570 | else | |
11571 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
11572 | |
11573 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
11574 | DRM_ERROR("failed to write control word\n"); | |
11575 | return -EIO; | |
11576 | } | |
11577 | ||
28d52043 DA |
11578 | return 0; |
11579 | } | |
c4a1d9e4 | 11580 | |
c4a1d9e4 | 11581 | struct intel_display_error_state { |
ff57f1b0 PZ |
11582 | |
11583 | u32 power_well_driver; | |
11584 | ||
63b66e5b CW |
11585 | int num_transcoders; |
11586 | ||
c4a1d9e4 CW |
11587 | struct intel_cursor_error_state { |
11588 | u32 control; | |
11589 | u32 position; | |
11590 | u32 base; | |
11591 | u32 size; | |
52331309 | 11592 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11593 | |
11594 | struct intel_pipe_error_state { | |
ddf9c536 | 11595 | bool power_domain_on; |
c4a1d9e4 | 11596 | u32 source; |
52331309 | 11597 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11598 | |
11599 | struct intel_plane_error_state { | |
11600 | u32 control; | |
11601 | u32 stride; | |
11602 | u32 size; | |
11603 | u32 pos; | |
11604 | u32 addr; | |
11605 | u32 surface; | |
11606 | u32 tile_offset; | |
52331309 | 11607 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11608 | |
11609 | struct intel_transcoder_error_state { | |
ddf9c536 | 11610 | bool power_domain_on; |
63b66e5b CW |
11611 | enum transcoder cpu_transcoder; |
11612 | ||
11613 | u32 conf; | |
11614 | ||
11615 | u32 htotal; | |
11616 | u32 hblank; | |
11617 | u32 hsync; | |
11618 | u32 vtotal; | |
11619 | u32 vblank; | |
11620 | u32 vsync; | |
11621 | } transcoder[4]; | |
c4a1d9e4 CW |
11622 | }; |
11623 | ||
11624 | struct intel_display_error_state * | |
11625 | intel_display_capture_error_state(struct drm_device *dev) | |
11626 | { | |
0206e353 | 11627 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11628 | struct intel_display_error_state *error; |
63b66e5b CW |
11629 | int transcoders[] = { |
11630 | TRANSCODER_A, | |
11631 | TRANSCODER_B, | |
11632 | TRANSCODER_C, | |
11633 | TRANSCODER_EDP, | |
11634 | }; | |
c4a1d9e4 CW |
11635 | int i; |
11636 | ||
63b66e5b CW |
11637 | if (INTEL_INFO(dev)->num_pipes == 0) |
11638 | return NULL; | |
11639 | ||
9d1cb914 | 11640 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11641 | if (error == NULL) |
11642 | return NULL; | |
11643 | ||
190be112 | 11644 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
11645 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11646 | ||
52331309 | 11647 | for_each_pipe(i) { |
ddf9c536 | 11648 | error->pipe[i].power_domain_on = |
da7e29bd ID |
11649 | intel_display_power_enabled_sw(dev_priv, |
11650 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 11651 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
11652 | continue; |
11653 | ||
a18c4c3d PZ |
11654 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11655 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11656 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11657 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11658 | } else { | |
11659 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11660 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11661 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11662 | } | |
c4a1d9e4 CW |
11663 | |
11664 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11665 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11666 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11667 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11668 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11669 | } | |
ca291363 PZ |
11670 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11671 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11672 | if (INTEL_INFO(dev)->gen >= 4) { |
11673 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11674 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11675 | } | |
11676 | ||
c4a1d9e4 | 11677 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11678 | } |
11679 | ||
11680 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11681 | if (HAS_DDI(dev_priv->dev)) | |
11682 | error->num_transcoders++; /* Account for eDP. */ | |
11683 | ||
11684 | for (i = 0; i < error->num_transcoders; i++) { | |
11685 | enum transcoder cpu_transcoder = transcoders[i]; | |
11686 | ||
ddf9c536 | 11687 | error->transcoder[i].power_domain_on = |
da7e29bd | 11688 | intel_display_power_enabled_sw(dev_priv, |
38cc1daf | 11689 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 11690 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
11691 | continue; |
11692 | ||
63b66e5b CW |
11693 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11694 | ||
11695 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11696 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11697 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11698 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11699 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11700 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11701 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11702 | } |
11703 | ||
11704 | return error; | |
11705 | } | |
11706 | ||
edc3d884 MK |
11707 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11708 | ||
c4a1d9e4 | 11709 | void |
edc3d884 | 11710 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11711 | struct drm_device *dev, |
11712 | struct intel_display_error_state *error) | |
11713 | { | |
11714 | int i; | |
11715 | ||
63b66e5b CW |
11716 | if (!error) |
11717 | return; | |
11718 | ||
edc3d884 | 11719 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 11720 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 11721 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11722 | error->power_well_driver); |
52331309 | 11723 | for_each_pipe(i) { |
edc3d884 | 11724 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
11725 | err_printf(m, " Power: %s\n", |
11726 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 11727 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11728 | |
11729 | err_printf(m, "Plane [%d]:\n", i); | |
11730 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11731 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11732 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11733 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11734 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11735 | } |
4b71a570 | 11736 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11737 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11738 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11739 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11740 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11741 | } |
11742 | ||
edc3d884 MK |
11743 | err_printf(m, "Cursor [%d]:\n", i); |
11744 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11745 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11746 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11747 | } |
63b66e5b CW |
11748 | |
11749 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11750 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 11751 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
11752 | err_printf(m, " Power: %s\n", |
11753 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
11754 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11755 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11756 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11757 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11758 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11759 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11760 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11761 | } | |
c4a1d9e4 | 11762 | } |