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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
c37efb99 | 40 | #include "i915_gem_dmabuf.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
eb1bfe80 JB |
100 | static int intel_framebuffer_init(struct drm_device *dev, |
101 | struct intel_framebuffer *ifb, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd, | |
103 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
104 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
105 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 106 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 107 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
108 | struct intel_link_m_n *m_n, |
109 | struct intel_link_m_n *m2_n2); | |
29407aab | 110 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 111 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 112 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 113 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 114 | const struct intel_crtc_state *pipe_config); |
d288f65f | 115 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 116 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
117 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
118 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
119 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 127 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 128 | |
d4906093 | 129 | struct intel_limit { |
4c5def93 ACO |
130 | struct { |
131 | int min, max; | |
132 | } dot, vco, n, m, m1, m2, p, p1; | |
133 | ||
134 | struct { | |
135 | int dot_limit; | |
136 | int p2_slow, p2_fast; | |
137 | } p2; | |
d4906093 | 138 | }; |
79e53945 | 139 | |
bfa7df01 VS |
140 | /* returns HPLL frequency in kHz */ |
141 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
142 | { | |
143 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
144 | ||
145 | /* Obtain SKU information */ | |
146 | mutex_lock(&dev_priv->sb_lock); | |
147 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
148 | CCK_FUSE_HPLL_FREQ_MASK; | |
149 | mutex_unlock(&dev_priv->sb_lock); | |
150 | ||
151 | return vco_freq[hpll_freq] * 1000; | |
152 | } | |
153 | ||
c30fec65 VS |
154 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
155 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
156 | { |
157 | u32 val; | |
158 | int divider; | |
159 | ||
bfa7df01 VS |
160 | mutex_lock(&dev_priv->sb_lock); |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
c30fec65 VS |
170 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
171 | } | |
172 | ||
173 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
174 | const char *name, u32 reg) | |
175 | { | |
176 | if (dev_priv->hpll_freq == 0) | |
177 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
178 | ||
179 | return vlv_get_cck_clock(dev_priv, name, reg, | |
180 | dev_priv->hpll_freq); | |
bfa7df01 VS |
181 | } |
182 | ||
e7dc33f3 VS |
183 | static int |
184 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 185 | { |
e7dc33f3 VS |
186 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
187 | } | |
d2acd215 | 188 | |
e7dc33f3 VS |
189 | static int |
190 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
191 | { | |
19ab4ed3 | 192 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
193 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
194 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
195 | } |
196 | ||
e7dc33f3 VS |
197 | static int |
198 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 199 | { |
79e50a4f JN |
200 | uint32_t clkcfg; |
201 | ||
e7dc33f3 | 202 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
203 | clkcfg = I915_READ(CLKCFG); |
204 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
205 | case CLKCFG_FSB_400: | |
e7dc33f3 | 206 | return 100000; |
79e50a4f | 207 | case CLKCFG_FSB_533: |
e7dc33f3 | 208 | return 133333; |
79e50a4f | 209 | case CLKCFG_FSB_667: |
e7dc33f3 | 210 | return 166667; |
79e50a4f | 211 | case CLKCFG_FSB_800: |
e7dc33f3 | 212 | return 200000; |
79e50a4f | 213 | case CLKCFG_FSB_1067: |
e7dc33f3 | 214 | return 266667; |
79e50a4f | 215 | case CLKCFG_FSB_1333: |
e7dc33f3 | 216 | return 333333; |
79e50a4f JN |
217 | /* these two are just a guess; one of them might be right */ |
218 | case CLKCFG_FSB_1600: | |
219 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 220 | return 400000; |
79e50a4f | 221 | default: |
e7dc33f3 | 222 | return 133333; |
79e50a4f JN |
223 | } |
224 | } | |
225 | ||
19ab4ed3 | 226 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
227 | { |
228 | if (HAS_PCH_SPLIT(dev_priv)) | |
229 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
230 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
231 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
232 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
233 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
234 | else | |
235 | return; /* no rawclk on other platforms, or no need to know it */ | |
236 | ||
237 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
238 | } | |
239 | ||
bfa7df01 VS |
240 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
241 | { | |
666a4537 | 242 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
243 | return; |
244 | ||
245 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
246 | CCK_CZ_CLOCK_CONTROL); | |
247 | ||
248 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
249 | } | |
250 | ||
021357ac | 251 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
252 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
253 | const struct intel_crtc_state *pipe_config) | |
021357ac | 254 | { |
21a727b3 VS |
255 | if (HAS_DDI(dev_priv)) |
256 | return pipe_config->port_clock; /* SPLL */ | |
257 | else if (IS_GEN5(dev_priv)) | |
258 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 259 | else |
21a727b3 | 260 | return 270000; |
021357ac CW |
261 | } |
262 | ||
1b6f4958 | 263 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 264 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 265 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 266 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
267 | .m = { .min = 96, .max = 140 }, |
268 | .m1 = { .min = 18, .max = 26 }, | |
269 | .m2 = { .min = 6, .max = 16 }, | |
270 | .p = { .min = 4, .max = 128 }, | |
271 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 165000, |
273 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
274 | }; |
275 | ||
1b6f4958 | 276 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 277 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 278 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 279 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
280 | .m = { .min = 96, .max = 140 }, |
281 | .m1 = { .min = 18, .max = 26 }, | |
282 | .m2 = { .min = 6, .max = 16 }, | |
283 | .p = { .min = 4, .max = 128 }, | |
284 | .p1 = { .min = 2, .max = 33 }, | |
285 | .p2 = { .dot_limit = 165000, | |
286 | .p2_slow = 4, .p2_fast = 4 }, | |
287 | }; | |
288 | ||
1b6f4958 | 289 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 290 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 291 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 292 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
293 | .m = { .min = 96, .max = 140 }, |
294 | .m1 = { .min = 18, .max = 26 }, | |
295 | .m2 = { .min = 6, .max = 16 }, | |
296 | .p = { .min = 4, .max = 128 }, | |
297 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 165000, |
299 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 300 | }; |
273e27ca | 301 | |
1b6f4958 | 302 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
303 | .dot = { .min = 20000, .max = 400000 }, |
304 | .vco = { .min = 1400000, .max = 2800000 }, | |
305 | .n = { .min = 1, .max = 6 }, | |
306 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
307 | .m1 = { .min = 8, .max = 18 }, |
308 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
309 | .p = { .min = 5, .max = 80 }, |
310 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
311 | .p2 = { .dot_limit = 200000, |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
1b6f4958 | 315 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
316 | .dot = { .min = 20000, .max = 400000 }, |
317 | .vco = { .min = 1400000, .max = 2800000 }, | |
318 | .n = { .min = 1, .max = 6 }, | |
319 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
320 | .m1 = { .min = 8, .max = 18 }, |
321 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
322 | .p = { .min = 7, .max = 98 }, |
323 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
324 | .p2 = { .dot_limit = 112000, |
325 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
326 | }; |
327 | ||
273e27ca | 328 | |
1b6f4958 | 329 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 270000 }, |
331 | .vco = { .min = 1750000, .max = 3500000}, | |
332 | .n = { .min = 1, .max = 4 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 10, .max = 30 }, | |
337 | .p1 = { .min = 1, .max = 3}, | |
338 | .p2 = { .dot_limit = 270000, | |
339 | .p2_slow = 10, | |
340 | .p2_fast = 10 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
1b6f4958 | 344 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
345 | .dot = { .min = 22000, .max = 400000 }, |
346 | .vco = { .min = 1750000, .max = 3500000}, | |
347 | .n = { .min = 1, .max = 4 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 16, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 5, .max = 80 }, | |
352 | .p1 = { .min = 1, .max = 8}, | |
353 | .p2 = { .dot_limit = 165000, | |
354 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
355 | }; |
356 | ||
1b6f4958 | 357 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
358 | .dot = { .min = 20000, .max = 115000 }, |
359 | .vco = { .min = 1750000, .max = 3500000 }, | |
360 | .n = { .min = 1, .max = 3 }, | |
361 | .m = { .min = 104, .max = 138 }, | |
362 | .m1 = { .min = 17, .max = 23 }, | |
363 | .m2 = { .min = 5, .max = 11 }, | |
364 | .p = { .min = 28, .max = 112 }, | |
365 | .p1 = { .min = 2, .max = 8 }, | |
366 | .p2 = { .dot_limit = 0, | |
367 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 368 | }, |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
372 | .dot = { .min = 80000, .max = 224000 }, |
373 | .vco = { .min = 1750000, .max = 3500000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 104, .max = 138 }, | |
376 | .m1 = { .min = 17, .max = 23 }, | |
377 | .m2 = { .min = 5, .max = 11 }, | |
378 | .p = { .min = 14, .max = 42 }, | |
379 | .p1 = { .min = 2, .max = 6 }, | |
380 | .p2 = { .dot_limit = 0, | |
381 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 382 | }, |
e4b36699 KP |
383 | }; |
384 | ||
1b6f4958 | 385 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
386 | .dot = { .min = 20000, .max = 400000}, |
387 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 388 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
389 | .n = { .min = 3, .max = 6 }, |
390 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 391 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
392 | .m1 = { .min = 0, .max = 0 }, |
393 | .m2 = { .min = 0, .max = 254 }, | |
394 | .p = { .min = 5, .max = 80 }, | |
395 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
396 | .p2 = { .dot_limit = 200000, |
397 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
398 | }; |
399 | ||
1b6f4958 | 400 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
401 | .dot = { .min = 20000, .max = 400000 }, |
402 | .vco = { .min = 1700000, .max = 3500000 }, | |
403 | .n = { .min = 3, .max = 6 }, | |
404 | .m = { .min = 2, .max = 256 }, | |
405 | .m1 = { .min = 0, .max = 0 }, | |
406 | .m2 = { .min = 0, .max = 254 }, | |
407 | .p = { .min = 7, .max = 112 }, | |
408 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
409 | .p2 = { .dot_limit = 112000, |
410 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
411 | }; |
412 | ||
273e27ca EA |
413 | /* Ironlake / Sandybridge |
414 | * | |
415 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
416 | * the range value for them is (actual_value - 2). | |
417 | */ | |
1b6f4958 | 418 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
419 | .dot = { .min = 25000, .max = 350000 }, |
420 | .vco = { .min = 1760000, .max = 3510000 }, | |
421 | .n = { .min = 1, .max = 5 }, | |
422 | .m = { .min = 79, .max = 127 }, | |
423 | .m1 = { .min = 12, .max = 22 }, | |
424 | .m2 = { .min = 5, .max = 9 }, | |
425 | .p = { .min = 5, .max = 80 }, | |
426 | .p1 = { .min = 1, .max = 8 }, | |
427 | .p2 = { .dot_limit = 225000, | |
428 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
429 | }; |
430 | ||
1b6f4958 | 431 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 3 }, | |
435 | .m = { .min = 79, .max = 118 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
439 | .p1 = { .min = 2, .max = 8 }, | |
440 | .p2 = { .dot_limit = 225000, | |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
1b6f4958 | 444 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 127 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 56 }, | |
452 | .p1 = { .min = 2, .max = 8 }, | |
453 | .p2 = { .dot_limit = 225000, | |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
455 | }; |
456 | ||
273e27ca | 457 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 458 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
459 | .dot = { .min = 25000, .max = 350000 }, |
460 | .vco = { .min = 1760000, .max = 3510000 }, | |
461 | .n = { .min = 1, .max = 2 }, | |
462 | .m = { .min = 79, .max = 126 }, | |
463 | .m1 = { .min = 12, .max = 22 }, | |
464 | .m2 = { .min = 5, .max = 9 }, | |
465 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 466 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
467 | .p2 = { .dot_limit = 225000, |
468 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
469 | }; |
470 | ||
1b6f4958 | 471 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
472 | .dot = { .min = 25000, .max = 350000 }, |
473 | .vco = { .min = 1760000, .max = 3510000 }, | |
474 | .n = { .min = 1, .max = 3 }, | |
475 | .m = { .min = 79, .max = 126 }, | |
476 | .m1 = { .min = 12, .max = 22 }, | |
477 | .m2 = { .min = 5, .max = 9 }, | |
478 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 479 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
480 | .p2 = { .dot_limit = 225000, |
481 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
482 | }; |
483 | ||
1b6f4958 | 484 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
485 | /* |
486 | * These are the data rate limits (measured in fast clocks) | |
487 | * since those are the strictest limits we have. The fast | |
488 | * clock and actual rate limits are more relaxed, so checking | |
489 | * them would make no difference. | |
490 | */ | |
491 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 492 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 493 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
494 | .m1 = { .min = 2, .max = 3 }, |
495 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 496 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 497 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
498 | }; |
499 | ||
1b6f4958 | 500 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
501 | /* |
502 | * These are the data rate limits (measured in fast clocks) | |
503 | * since those are the strictest limits we have. The fast | |
504 | * clock and actual rate limits are more relaxed, so checking | |
505 | * them would make no difference. | |
506 | */ | |
507 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 508 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
509 | .n = { .min = 1, .max = 1 }, |
510 | .m1 = { .min = 2, .max = 2 }, | |
511 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
514 | }; | |
515 | ||
1b6f4958 | 516 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
517 | /* FIXME: find real dot limits */ |
518 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 519 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
520 | .n = { .min = 1, .max = 1 }, |
521 | .m1 = { .min = 2, .max = 2 }, | |
522 | /* FIXME: find real m2 limits */ | |
523 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
524 | .p1 = { .min = 2, .max = 4 }, | |
525 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
526 | }; | |
527 | ||
cdba954e ACO |
528 | static bool |
529 | needs_modeset(struct drm_crtc_state *state) | |
530 | { | |
fc596660 | 531 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
532 | } |
533 | ||
dccbea3b ID |
534 | /* |
535 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
536 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
537 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
538 | * The helpers' return value is the rate of the clock that is fed to the | |
539 | * display engine's pipe which can be the above fast dot clock rate or a | |
540 | * divided-down version of it. | |
541 | */ | |
f2b115e6 | 542 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 543 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 544 | { |
2177832f SL |
545 | clock->m = clock->m2 + 2; |
546 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 547 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 548 | return 0; |
fb03ac01 VS |
549 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
550 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
551 | |
552 | return clock->dot; | |
2177832f SL |
553 | } |
554 | ||
7429e9d4 DV |
555 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
556 | { | |
557 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
558 | } | |
559 | ||
9e2c8475 | 560 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 561 | { |
7429e9d4 | 562 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 563 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 564 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 565 | return 0; |
fb03ac01 VS |
566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
568 | |
569 | return clock->dot; | |
79e53945 JB |
570 | } |
571 | ||
9e2c8475 | 572 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
573 | { |
574 | clock->m = clock->m1 * clock->m2; | |
575 | clock->p = clock->p1 * clock->p2; | |
576 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 577 | return 0; |
589eca67 ID |
578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
580 | |
581 | return clock->dot / 5; | |
589eca67 ID |
582 | } |
583 | ||
9e2c8475 | 584 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
585 | { |
586 | clock->m = clock->m1 * clock->m2; | |
587 | clock->p = clock->p1 * clock->p2; | |
588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 589 | return 0; |
ef9348c8 CML |
590 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
591 | clock->n << 22); | |
592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
593 | |
594 | return clock->dot / 5; | |
ef9348c8 CML |
595 | } |
596 | ||
7c04d1d9 | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
598 | /** |
599 | * Returns whether the given set of divisors are valid for a given refclk with | |
600 | * the given connectors. | |
601 | */ | |
602 | ||
1b894b59 | 603 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 604 | const struct intel_limit *limit, |
9e2c8475 | 605 | const struct dpll *clock) |
79e53945 | 606 | { |
f01b7962 VS |
607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
608 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 612 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 614 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 615 | |
666a4537 WB |
616 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
617 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
666a4537 | 621 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
623 | INTELPllInvalid("p out of range\n"); | |
624 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
625 | INTELPllInvalid("m out of range\n"); | |
626 | } | |
627 | ||
79e53945 | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 629 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
631 | * connector, etc., rather than just a single range. | |
632 | */ | |
633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 634 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
635 | |
636 | return true; | |
637 | } | |
638 | ||
3b1429d9 | 639 | static int |
1b6f4958 | 640 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
641 | const struct intel_crtc_state *crtc_state, |
642 | int target) | |
79e53945 | 643 | { |
3b1429d9 | 644 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 645 | |
2d84d2b3 | 646 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 647 | /* |
a210b028 DV |
648 | * For LVDS just rely on its current settings for dual-channel. |
649 | * We haven't figured out how to reliably set up different | |
650 | * single/dual channel state, if we even can. | |
79e53945 | 651 | */ |
1974cad0 | 652 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 653 | return limit->p2.p2_fast; |
79e53945 | 654 | else |
3b1429d9 | 655 | return limit->p2.p2_slow; |
79e53945 JB |
656 | } else { |
657 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 658 | return limit->p2.p2_slow; |
79e53945 | 659 | else |
3b1429d9 | 660 | return limit->p2.p2_fast; |
79e53945 | 661 | } |
3b1429d9 VS |
662 | } |
663 | ||
70e8aa21 ACO |
664 | /* |
665 | * Returns a set of divisors for the desired target clock with the given | |
666 | * refclk, or FALSE. The returned values represent the clock equation: | |
667 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
668 | * | |
669 | * Target and reference clocks are specified in kHz. | |
670 | * | |
671 | * If match_clock is provided, then best_clock P divider must match the P | |
672 | * divider from @match_clock used for LVDS downclocking. | |
673 | */ | |
3b1429d9 | 674 | static bool |
1b6f4958 | 675 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 676 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
677 | int target, int refclk, struct dpll *match_clock, |
678 | struct dpll *best_clock) | |
3b1429d9 VS |
679 | { |
680 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 681 | struct dpll clock; |
3b1429d9 | 682 | int err = target; |
79e53945 | 683 | |
0206e353 | 684 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 685 | |
3b1429d9 VS |
686 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
687 | ||
42158660 ZY |
688 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
689 | clock.m1++) { | |
690 | for (clock.m2 = limit->m2.min; | |
691 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 692 | if (clock.m2 >= clock.m1) |
42158660 ZY |
693 | break; |
694 | for (clock.n = limit->n.min; | |
695 | clock.n <= limit->n.max; clock.n++) { | |
696 | for (clock.p1 = limit->p1.min; | |
697 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
698 | int this_err; |
699 | ||
dccbea3b | 700 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
701 | if (!intel_PLL_is_valid(dev, limit, |
702 | &clock)) | |
703 | continue; | |
704 | if (match_clock && | |
705 | clock.p != match_clock->p) | |
706 | continue; | |
707 | ||
708 | this_err = abs(clock.dot - target); | |
709 | if (this_err < err) { | |
710 | *best_clock = clock; | |
711 | err = this_err; | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | return (err != target); | |
719 | } | |
720 | ||
70e8aa21 ACO |
721 | /* |
722 | * Returns a set of divisors for the desired target clock with the given | |
723 | * refclk, or FALSE. The returned values represent the clock equation: | |
724 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
725 | * | |
726 | * Target and reference clocks are specified in kHz. | |
727 | * | |
728 | * If match_clock is provided, then best_clock P divider must match the P | |
729 | * divider from @match_clock used for LVDS downclocking. | |
730 | */ | |
ac58c3f0 | 731 | static bool |
1b6f4958 | 732 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 733 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
734 | int target, int refclk, struct dpll *match_clock, |
735 | struct dpll *best_clock) | |
79e53945 | 736 | { |
3b1429d9 | 737 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 738 | struct dpll clock; |
79e53945 JB |
739 | int err = target; |
740 | ||
0206e353 | 741 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 742 | |
3b1429d9 VS |
743 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
744 | ||
42158660 ZY |
745 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
746 | clock.m1++) { | |
747 | for (clock.m2 = limit->m2.min; | |
748 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
749 | for (clock.n = limit->n.min; |
750 | clock.n <= limit->n.max; clock.n++) { | |
751 | for (clock.p1 = limit->p1.min; | |
752 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
753 | int this_err; |
754 | ||
dccbea3b | 755 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
756 | if (!intel_PLL_is_valid(dev, limit, |
757 | &clock)) | |
79e53945 | 758 | continue; |
cec2f356 SP |
759 | if (match_clock && |
760 | clock.p != match_clock->p) | |
761 | continue; | |
79e53945 JB |
762 | |
763 | this_err = abs(clock.dot - target); | |
764 | if (this_err < err) { | |
765 | *best_clock = clock; | |
766 | err = this_err; | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | } | |
772 | ||
773 | return (err != target); | |
774 | } | |
775 | ||
997c030c ACO |
776 | /* |
777 | * Returns a set of divisors for the desired target clock with the given | |
778 | * refclk, or FALSE. The returned values represent the clock equation: | |
779 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
780 | * |
781 | * Target and reference clocks are specified in kHz. | |
782 | * | |
783 | * If match_clock is provided, then best_clock P divider must match the P | |
784 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 785 | */ |
d4906093 | 786 | static bool |
1b6f4958 | 787 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 788 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
789 | int target, int refclk, struct dpll *match_clock, |
790 | struct dpll *best_clock) | |
d4906093 | 791 | { |
3b1429d9 | 792 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 793 | struct dpll clock; |
d4906093 | 794 | int max_n; |
3b1429d9 | 795 | bool found = false; |
6ba770dc AJ |
796 | /* approximately equals target * 0.00585 */ |
797 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
798 | |
799 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
800 | |
801 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
802 | ||
d4906093 | 803 | max_n = limit->n.max; |
f77f13e2 | 804 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 805 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 806 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
807 | for (clock.m1 = limit->m1.max; |
808 | clock.m1 >= limit->m1.min; clock.m1--) { | |
809 | for (clock.m2 = limit->m2.max; | |
810 | clock.m2 >= limit->m2.min; clock.m2--) { | |
811 | for (clock.p1 = limit->p1.max; | |
812 | clock.p1 >= limit->p1.min; clock.p1--) { | |
813 | int this_err; | |
814 | ||
dccbea3b | 815 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
816 | if (!intel_PLL_is_valid(dev, limit, |
817 | &clock)) | |
d4906093 | 818 | continue; |
1b894b59 CW |
819 | |
820 | this_err = abs(clock.dot - target); | |
d4906093 ML |
821 | if (this_err < err_most) { |
822 | *best_clock = clock; | |
823 | err_most = this_err; | |
824 | max_n = clock.n; | |
825 | found = true; | |
826 | } | |
827 | } | |
828 | } | |
829 | } | |
830 | } | |
2c07245f ZW |
831 | return found; |
832 | } | |
833 | ||
d5dd62bd ID |
834 | /* |
835 | * Check if the calculated PLL configuration is more optimal compared to the | |
836 | * best configuration and error found so far. Return the calculated error. | |
837 | */ | |
838 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
839 | const struct dpll *calculated_clock, |
840 | const struct dpll *best_clock, | |
d5dd62bd ID |
841 | unsigned int best_error_ppm, |
842 | unsigned int *error_ppm) | |
843 | { | |
9ca3ba01 ID |
844 | /* |
845 | * For CHV ignore the error and consider only the P value. | |
846 | * Prefer a bigger P value based on HW requirements. | |
847 | */ | |
848 | if (IS_CHERRYVIEW(dev)) { | |
849 | *error_ppm = 0; | |
850 | ||
851 | return calculated_clock->p > best_clock->p; | |
852 | } | |
853 | ||
24be4e46 ID |
854 | if (WARN_ON_ONCE(!target_freq)) |
855 | return false; | |
856 | ||
d5dd62bd ID |
857 | *error_ppm = div_u64(1000000ULL * |
858 | abs(target_freq - calculated_clock->dot), | |
859 | target_freq); | |
860 | /* | |
861 | * Prefer a better P value over a better (smaller) error if the error | |
862 | * is small. Ensure this preference for future configurations too by | |
863 | * setting the error to 0. | |
864 | */ | |
865 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
866 | *error_ppm = 0; | |
867 | ||
868 | return true; | |
869 | } | |
870 | ||
871 | return *error_ppm + 10 < best_error_ppm; | |
872 | } | |
873 | ||
65b3d6a9 ACO |
874 | /* |
875 | * Returns a set of divisors for the desired target clock with the given | |
876 | * refclk, or FALSE. The returned values represent the clock equation: | |
877 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
878 | */ | |
a0c4da24 | 879 | static bool |
1b6f4958 | 880 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 881 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
882 | int target, int refclk, struct dpll *match_clock, |
883 | struct dpll *best_clock) | |
a0c4da24 | 884 | { |
a93e255f | 885 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 886 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 887 | struct dpll clock; |
69e4f900 | 888 | unsigned int bestppm = 1000000; |
27e639bf VS |
889 | /* min update 19.2 MHz */ |
890 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 891 | bool found = false; |
a0c4da24 | 892 | |
6b4bf1c4 VS |
893 | target *= 5; /* fast clock */ |
894 | ||
895 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
896 | |
897 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 898 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 899 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 900 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 901 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 902 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 903 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 904 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 905 | unsigned int ppm; |
69e4f900 | 906 | |
6b4bf1c4 VS |
907 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
908 | refclk * clock.m1); | |
909 | ||
dccbea3b | 910 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 911 | |
f01b7962 VS |
912 | if (!intel_PLL_is_valid(dev, limit, |
913 | &clock)) | |
43b0ac53 VS |
914 | continue; |
915 | ||
d5dd62bd ID |
916 | if (!vlv_PLL_is_optimal(dev, target, |
917 | &clock, | |
918 | best_clock, | |
919 | bestppm, &ppm)) | |
920 | continue; | |
6b4bf1c4 | 921 | |
d5dd62bd ID |
922 | *best_clock = clock; |
923 | bestppm = ppm; | |
924 | found = true; | |
a0c4da24 JB |
925 | } |
926 | } | |
927 | } | |
928 | } | |
a0c4da24 | 929 | |
49e497ef | 930 | return found; |
a0c4da24 | 931 | } |
a4fc5ed6 | 932 | |
65b3d6a9 ACO |
933 | /* |
934 | * Returns a set of divisors for the desired target clock with the given | |
935 | * refclk, or FALSE. The returned values represent the clock equation: | |
936 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
937 | */ | |
ef9348c8 | 938 | static bool |
1b6f4958 | 939 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 940 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
941 | int target, int refclk, struct dpll *match_clock, |
942 | struct dpll *best_clock) | |
ef9348c8 | 943 | { |
a93e255f | 944 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 945 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 946 | unsigned int best_error_ppm; |
9e2c8475 | 947 | struct dpll clock; |
ef9348c8 CML |
948 | uint64_t m2; |
949 | int found = false; | |
950 | ||
951 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 952 | best_error_ppm = 1000000; |
ef9348c8 CML |
953 | |
954 | /* | |
955 | * Based on hardware doc, the n always set to 1, and m1 always | |
956 | * set to 2. If requires to support 200Mhz refclk, we need to | |
957 | * revisit this because n may not 1 anymore. | |
958 | */ | |
959 | clock.n = 1, clock.m1 = 2; | |
960 | target *= 5; /* fast clock */ | |
961 | ||
962 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
963 | for (clock.p2 = limit->p2.p2_fast; | |
964 | clock.p2 >= limit->p2.p2_slow; | |
965 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 966 | unsigned int error_ppm; |
ef9348c8 CML |
967 | |
968 | clock.p = clock.p1 * clock.p2; | |
969 | ||
970 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
971 | clock.n) << 22, refclk * clock.m1); | |
972 | ||
973 | if (m2 > INT_MAX/clock.m1) | |
974 | continue; | |
975 | ||
976 | clock.m2 = m2; | |
977 | ||
dccbea3b | 978 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
979 | |
980 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
981 | continue; | |
982 | ||
9ca3ba01 ID |
983 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
984 | best_error_ppm, &error_ppm)) | |
985 | continue; | |
986 | ||
987 | *best_clock = clock; | |
988 | best_error_ppm = error_ppm; | |
989 | found = true; | |
ef9348c8 CML |
990 | } |
991 | } | |
992 | ||
993 | return found; | |
994 | } | |
995 | ||
5ab7b0b7 | 996 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 997 | struct dpll *best_clock) |
5ab7b0b7 | 998 | { |
65b3d6a9 | 999 | int refclk = 100000; |
1b6f4958 | 1000 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1001 | |
65b3d6a9 | 1002 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1003 | target_clock, refclk, NULL, best_clock); |
1004 | } | |
1005 | ||
20ddf665 VS |
1006 | bool intel_crtc_active(struct drm_crtc *crtc) |
1007 | { | |
1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1009 | ||
1010 | /* Be paranoid as we can arrive here with only partial | |
1011 | * state retrieved from the hardware during setup. | |
1012 | * | |
241bfc38 | 1013 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1014 | * as Haswell has gained clock readout/fastboot support. |
1015 | * | |
66e514c1 | 1016 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1017 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1018 | * |
1019 | * FIXME: The intel_crtc->active here should be switched to | |
1020 | * crtc->state->active once we have proper CRTC states wired up | |
1021 | * for atomic. | |
20ddf665 | 1022 | */ |
c3d1f436 | 1023 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1024 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1025 | } |
1026 | ||
a5c961d1 PZ |
1027 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1028 | enum pipe pipe) | |
1029 | { | |
1030 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1032 | ||
6e3c9717 | 1033 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1034 | } |
1035 | ||
fbf49ea2 VS |
1036 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1037 | { | |
fac5e23e | 1038 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1039 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1040 | u32 line1, line2; |
1041 | u32 line_mask; | |
1042 | ||
1043 | if (IS_GEN2(dev)) | |
1044 | line_mask = DSL_LINEMASK_GEN2; | |
1045 | else | |
1046 | line_mask = DSL_LINEMASK_GEN3; | |
1047 | ||
1048 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1049 | msleep(5); |
fbf49ea2 VS |
1050 | line2 = I915_READ(reg) & line_mask; |
1051 | ||
1052 | return line1 == line2; | |
1053 | } | |
1054 | ||
ab7ad7f6 KP |
1055 | /* |
1056 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1057 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1058 | * |
1059 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1060 | * spinning on the vblank interrupt status bit, since we won't actually | |
1061 | * see an interrupt when the pipe is disabled. | |
1062 | * | |
ab7ad7f6 KP |
1063 | * On Gen4 and above: |
1064 | * wait for the pipe register state bit to turn off | |
1065 | * | |
1066 | * Otherwise: | |
1067 | * wait for the display line value to settle (it usually | |
1068 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1069 | * |
9d0498a2 | 1070 | */ |
575f7ab7 | 1071 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1072 | { |
575f7ab7 | 1073 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1074 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1075 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1076 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1077 | |
1078 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1079 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1080 | |
1081 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1082 | if (intel_wait_for_register(dev_priv, |
1083 | reg, I965_PIPECONF_ACTIVE, 0, | |
1084 | 100)) | |
284637d9 | 1085 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1086 | } else { |
ab7ad7f6 | 1087 | /* Wait for the display line to settle */ |
fbf49ea2 | 1088 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1089 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1090 | } |
79e53945 JB |
1091 | } |
1092 | ||
b24e7179 | 1093 | /* Only for pre-ILK configs */ |
55607e8a DV |
1094 | void assert_pll(struct drm_i915_private *dev_priv, |
1095 | enum pipe pipe, bool state) | |
b24e7179 | 1096 | { |
b24e7179 JB |
1097 | u32 val; |
1098 | bool cur_state; | |
1099 | ||
649636ef | 1100 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1101 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1102 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1103 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1104 | onoff(state), onoff(cur_state)); |
b24e7179 | 1105 | } |
b24e7179 | 1106 | |
23538ef1 | 1107 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1108 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1109 | { |
1110 | u32 val; | |
1111 | bool cur_state; | |
1112 | ||
a580516d | 1113 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1114 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1115 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1116 | |
1117 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1119 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
23538ef1 | 1121 | } |
23538ef1 | 1122 | |
040484af JB |
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe, bool state) | |
1125 | { | |
040484af | 1126 | bool cur_state; |
ad80a810 PZ |
1127 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1128 | pipe); | |
040484af | 1129 | |
2d1fe073 | 1130 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1131 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1132 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1133 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1134 | } else { |
649636ef | 1135 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1136 | cur_state = !!(val & FDI_TX_ENABLE); |
1137 | } | |
e2c719b7 | 1138 | I915_STATE_WARN(cur_state != state, |
040484af | 1139 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1140 | onoff(state), onoff(cur_state)); |
040484af JB |
1141 | } |
1142 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1143 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe, bool state) | |
1147 | { | |
040484af JB |
1148 | u32 val; |
1149 | bool cur_state; | |
1150 | ||
649636ef | 1151 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1152 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
040484af | 1154 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1155 | onoff(state), onoff(cur_state)); |
040484af JB |
1156 | } |
1157 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1158 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1159 | ||
1160 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1161 | enum pipe pipe) | |
1162 | { | |
040484af JB |
1163 | u32 val; |
1164 | ||
1165 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1166 | if (IS_GEN5(dev_priv)) |
040484af JB |
1167 | return; |
1168 | ||
bf507ef7 | 1169 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1170 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1171 | return; |
1172 | ||
649636ef | 1173 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1174 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1175 | } |
1176 | ||
55607e8a DV |
1177 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1178 | enum pipe pipe, bool state) | |
040484af | 1179 | { |
040484af | 1180 | u32 val; |
55607e8a | 1181 | bool cur_state; |
040484af | 1182 | |
649636ef | 1183 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1184 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1186 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1187 | onoff(state), onoff(cur_state)); |
040484af JB |
1188 | } |
1189 | ||
b680c37a DV |
1190 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1191 | enum pipe pipe) | |
ea0760cf | 1192 | { |
91c8a326 | 1193 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 | 1194 | i915_reg_t pp_reg; |
ea0760cf JB |
1195 | u32 val; |
1196 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1197 | bool locked = true; |
ea0760cf | 1198 | |
bedd4dba JN |
1199 | if (WARN_ON(HAS_DDI(dev))) |
1200 | return; | |
1201 | ||
1202 | if (HAS_PCH_SPLIT(dev)) { | |
1203 | u32 port_sel; | |
1204 | ||
44cb734c ID |
1205 | pp_reg = PP_CONTROL(0); |
1206 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1207 | |
1208 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1209 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1210 | panel_pipe = PIPE_B; | |
1211 | /* XXX: else fix for eDP */ | |
666a4537 | 1212 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba | 1213 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1214 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1215 | panel_pipe = pipe; |
ea0760cf | 1216 | } else { |
44cb734c | 1217 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1218 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1219 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1220 | } |
1221 | ||
1222 | val = I915_READ(pp_reg); | |
1223 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1224 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1225 | locked = false; |
1226 | ||
e2c719b7 | 1227 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1228 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1229 | pipe_name(pipe)); |
ea0760cf JB |
1230 | } |
1231 | ||
93ce0ba6 JN |
1232 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe, bool state) | |
1234 | { | |
91c8a326 | 1235 | struct drm_device *dev = &dev_priv->drm; |
93ce0ba6 JN |
1236 | bool cur_state; |
1237 | ||
d9d82081 | 1238 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1239 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1240 | else |
5efb3e28 | 1241 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1242 | |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1244 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1246 | } |
1247 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1248 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1249 | ||
b840d907 JB |
1250 | void assert_pipe(struct drm_i915_private *dev_priv, |
1251 | enum pipe pipe, bool state) | |
b24e7179 | 1252 | { |
63d7bbe9 | 1253 | bool cur_state; |
702e7a56 PZ |
1254 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1255 | pipe); | |
4feed0eb | 1256 | enum intel_display_power_domain power_domain; |
b24e7179 | 1257 | |
b6b5d049 VS |
1258 | /* if we need the pipe quirk it must be always on */ |
1259 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1260 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1261 | state = true; |
1262 | ||
4feed0eb ID |
1263 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1264 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1265 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1266 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1267 | |
1268 | intel_display_power_put(dev_priv, power_domain); | |
1269 | } else { | |
1270 | cur_state = false; | |
69310161 PZ |
1271 | } |
1272 | ||
e2c719b7 | 1273 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1274 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1275 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1276 | } |
1277 | ||
931872fc CW |
1278 | static void assert_plane(struct drm_i915_private *dev_priv, |
1279 | enum plane plane, bool state) | |
b24e7179 | 1280 | { |
b24e7179 | 1281 | u32 val; |
931872fc | 1282 | bool cur_state; |
b24e7179 | 1283 | |
649636ef | 1284 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1285 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1286 | I915_STATE_WARN(cur_state != state, |
931872fc | 1287 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1288 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1289 | } |
1290 | ||
931872fc CW |
1291 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1292 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1293 | ||
b24e7179 JB |
1294 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
1296 | { | |
91c8a326 | 1297 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1298 | int i; |
b24e7179 | 1299 | |
653e1026 VS |
1300 | /* Primary planes are fixed to pipes on gen4+ */ |
1301 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1302 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1303 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1304 | "plane %c assertion failure, should be disabled but not\n", |
1305 | plane_name(pipe)); | |
19ec1358 | 1306 | return; |
28c05794 | 1307 | } |
19ec1358 | 1308 | |
b24e7179 | 1309 | /* Need to check both planes against the pipe */ |
055e393f | 1310 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1311 | u32 val = I915_READ(DSPCNTR(i)); |
1312 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1313 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1314 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1315 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1316 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1317 | } |
1318 | } | |
1319 | ||
19332d7a JB |
1320 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1321 | enum pipe pipe) | |
1322 | { | |
91c8a326 | 1323 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1324 | int sprite; |
19332d7a | 1325 | |
7feb8b88 | 1326 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1327 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1328 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1329 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1330 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1331 | sprite, pipe_name(pipe)); | |
1332 | } | |
666a4537 | 1333 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1334 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1335 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1336 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1337 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1338 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1339 | } |
1340 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1341 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1342 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1343 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1344 | plane_name(pipe), pipe_name(pipe)); |
1345 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1346 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1347 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1348 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1349 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1350 | } |
1351 | } | |
1352 | ||
08c71e5e VS |
1353 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1354 | { | |
e2c719b7 | 1355 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1356 | drm_crtc_vblank_put(crtc); |
1357 | } | |
1358 | ||
7abd4b35 ACO |
1359 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1360 | enum pipe pipe) | |
92f2584a | 1361 | { |
92f2584a JB |
1362 | u32 val; |
1363 | bool enabled; | |
1364 | ||
649636ef | 1365 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1366 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1367 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1368 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1369 | pipe_name(pipe)); | |
92f2584a JB |
1370 | } |
1371 | ||
4e634389 KP |
1372 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1373 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1374 | { |
1375 | if ((val & DP_PORT_EN) == 0) | |
1376 | return false; | |
1377 | ||
2d1fe073 | 1378 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1379 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1380 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1381 | return false; | |
2d1fe073 | 1382 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1383 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1384 | return false; | |
f0575e92 KP |
1385 | } else { |
1386 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1387 | return false; | |
1388 | } | |
1389 | return true; | |
1390 | } | |
1391 | ||
1519b995 KP |
1392 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1393 | enum pipe pipe, u32 val) | |
1394 | { | |
dc0fa718 | 1395 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1396 | return false; |
1397 | ||
2d1fe073 | 1398 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1399 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1400 | return false; |
2d1fe073 | 1401 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1402 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1403 | return false; | |
1519b995 | 1404 | } else { |
dc0fa718 | 1405 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1406 | return false; |
1407 | } | |
1408 | return true; | |
1409 | } | |
1410 | ||
1411 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1412 | enum pipe pipe, u32 val) | |
1413 | { | |
1414 | if ((val & LVDS_PORT_EN) == 0) | |
1415 | return false; | |
1416 | ||
2d1fe073 | 1417 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1418 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1419 | return false; | |
1420 | } else { | |
1421 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1422 | return false; | |
1423 | } | |
1424 | return true; | |
1425 | } | |
1426 | ||
1427 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1428 | enum pipe pipe, u32 val) | |
1429 | { | |
1430 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1431 | return false; | |
2d1fe073 | 1432 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1433 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1434 | return false; | |
1435 | } else { | |
1436 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1437 | return false; | |
1438 | } | |
1439 | return true; | |
1440 | } | |
1441 | ||
291906f1 | 1442 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1443 | enum pipe pipe, i915_reg_t reg, |
1444 | u32 port_sel) | |
291906f1 | 1445 | { |
47a05eca | 1446 | u32 val = I915_READ(reg); |
e2c719b7 | 1447 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1448 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1449 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1450 | |
2d1fe073 | 1451 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1452 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1453 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1454 | } |
1455 | ||
1456 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1457 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1458 | { |
47a05eca | 1459 | u32 val = I915_READ(reg); |
e2c719b7 | 1460 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1461 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1462 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1463 | |
2d1fe073 | 1464 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1465 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1466 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1467 | } |
1468 | ||
1469 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1470 | enum pipe pipe) | |
1471 | { | |
291906f1 | 1472 | u32 val; |
291906f1 | 1473 | |
f0575e92 KP |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1476 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1477 | |
649636ef | 1478 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1479 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1480 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1481 | pipe_name(pipe)); |
291906f1 | 1482 | |
649636ef | 1483 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1484 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1485 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1486 | pipe_name(pipe)); |
291906f1 | 1487 | |
e2debe91 PZ |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1491 | } |
1492 | ||
cd2d34d9 VS |
1493 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1494 | const struct intel_crtc_state *pipe_config) | |
1495 | { | |
1496 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1497 | enum pipe pipe = crtc->pipe; | |
1498 | ||
1499 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1500 | POSTING_READ(DPLL(pipe)); | |
1501 | udelay(150); | |
1502 | ||
2c30b43b CW |
1503 | if (intel_wait_for_register(dev_priv, |
1504 | DPLL(pipe), | |
1505 | DPLL_LOCK_VLV, | |
1506 | DPLL_LOCK_VLV, | |
1507 | 1)) | |
cd2d34d9 VS |
1508 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1509 | } | |
1510 | ||
d288f65f | 1511 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1512 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1513 | { |
cd2d34d9 | 1514 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1515 | enum pipe pipe = crtc->pipe; |
87442f73 | 1516 | |
8bd3f301 | 1517 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1518 | |
87442f73 | 1519 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1520 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1521 | |
cd2d34d9 VS |
1522 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1523 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1524 | |
8bd3f301 VS |
1525 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1526 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1527 | } |
1528 | ||
cd2d34d9 VS |
1529 | |
1530 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1531 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1532 | { |
cd2d34d9 | 1533 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1534 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1535 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1536 | u32 tmp; |
1537 | ||
a580516d | 1538 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1539 | |
1540 | /* Enable back the 10bit clock to display controller */ | |
1541 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1542 | tmp |= DPIO_DCLKP_EN; | |
1543 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1544 | ||
54433e91 VS |
1545 | mutex_unlock(&dev_priv->sb_lock); |
1546 | ||
9d556c99 CML |
1547 | /* |
1548 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1549 | */ | |
1550 | udelay(1); | |
1551 | ||
1552 | /* Enable PLL */ | |
d288f65f | 1553 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1554 | |
1555 | /* Check PLL is locked */ | |
6b18826a CW |
1556 | if (intel_wait_for_register(dev_priv, |
1557 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1558 | 1)) | |
9d556c99 | 1559 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1560 | } |
1561 | ||
1562 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1563 | const struct intel_crtc_state *pipe_config) | |
1564 | { | |
1565 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1566 | enum pipe pipe = crtc->pipe; | |
1567 | ||
1568 | assert_pipe_disabled(dev_priv, pipe); | |
1569 | ||
1570 | /* PLL is protected by panel, make sure we can write it */ | |
1571 | assert_panel_unlocked(dev_priv, pipe); | |
1572 | ||
1573 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1574 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1575 | |
c231775c VS |
1576 | if (pipe != PIPE_A) { |
1577 | /* | |
1578 | * WaPixelRepeatModeFixForC0:chv | |
1579 | * | |
1580 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1581 | * the value from DPLLBMD to either pipe B or C. | |
1582 | */ | |
1583 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1584 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1585 | I915_WRITE(CBR4_VLV, 0); | |
1586 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1587 | ||
1588 | /* | |
1589 | * DPLLB VGA mode also seems to cause problems. | |
1590 | * We should always have it disabled. | |
1591 | */ | |
1592 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1593 | } else { | |
1594 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1595 | POSTING_READ(DPLL_MD(pipe)); | |
1596 | } | |
9d556c99 CML |
1597 | } |
1598 | ||
1c4e0274 VS |
1599 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1600 | { | |
1601 | struct intel_crtc *crtc; | |
1602 | int count = 0; | |
1603 | ||
2d84d2b3 | 1604 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1605 | count += crtc->base.state->active && |
2d84d2b3 VS |
1606 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1607 | } | |
1c4e0274 VS |
1608 | |
1609 | return count; | |
1610 | } | |
1611 | ||
66e3d5c0 | 1612 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1613 | { |
66e3d5c0 | 1614 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1615 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1616 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1617 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1618 | |
66e3d5c0 | 1619 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1620 | |
63d7bbe9 | 1621 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1622 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1623 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1624 | |
1c4e0274 VS |
1625 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1626 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1627 | /* | |
1628 | * It appears to be important that we don't enable this | |
1629 | * for the current pipe before otherwise configuring the | |
1630 | * PLL. No idea how this should be handled if multiple | |
1631 | * DVO outputs are enabled simultaneosly. | |
1632 | */ | |
1633 | dpll |= DPLL_DVO_2X_MODE; | |
1634 | I915_WRITE(DPLL(!crtc->pipe), | |
1635 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1636 | } | |
66e3d5c0 | 1637 | |
c2b63374 VS |
1638 | /* |
1639 | * Apparently we need to have VGA mode enabled prior to changing | |
1640 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1641 | * dividers, even though the register value does change. | |
1642 | */ | |
1643 | I915_WRITE(reg, 0); | |
1644 | ||
8e7a65aa VS |
1645 | I915_WRITE(reg, dpll); |
1646 | ||
66e3d5c0 DV |
1647 | /* Wait for the clocks to stabilize. */ |
1648 | POSTING_READ(reg); | |
1649 | udelay(150); | |
1650 | ||
1651 | if (INTEL_INFO(dev)->gen >= 4) { | |
1652 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1653 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1654 | } else { |
1655 | /* The pixel multiplier can only be updated once the | |
1656 | * DPLL is enabled and the clocks are stable. | |
1657 | * | |
1658 | * So write it again. | |
1659 | */ | |
1660 | I915_WRITE(reg, dpll); | |
1661 | } | |
63d7bbe9 JB |
1662 | |
1663 | /* We do this three times for luck */ | |
66e3d5c0 | 1664 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1665 | POSTING_READ(reg); |
1666 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1667 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1668 | POSTING_READ(reg); |
1669 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1670 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1671 | POSTING_READ(reg); |
1672 | udelay(150); /* wait for warmup */ | |
1673 | } | |
1674 | ||
1675 | /** | |
50b44a44 | 1676 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1677 | * @dev_priv: i915 private structure |
1678 | * @pipe: pipe PLL to disable | |
1679 | * | |
1680 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1681 | * | |
1682 | * Note! This is for pre-ILK only. | |
1683 | */ | |
1c4e0274 | 1684 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1685 | { |
1c4e0274 | 1686 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1687 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1688 | enum pipe pipe = crtc->pipe; |
1689 | ||
1690 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1691 | if (IS_I830(dev) && | |
2d84d2b3 | 1692 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1693 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1694 | I915_WRITE(DPLL(PIPE_B), |
1695 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1696 | I915_WRITE(DPLL(PIPE_A), | |
1697 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1698 | } | |
1699 | ||
b6b5d049 VS |
1700 | /* Don't disable pipe or pipe PLLs if needed */ |
1701 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1702 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1703 | return; |
1704 | ||
1705 | /* Make sure the pipe isn't still relying on us */ | |
1706 | assert_pipe_disabled(dev_priv, pipe); | |
1707 | ||
b8afb911 | 1708 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1709 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1710 | } |
1711 | ||
f6071166 JB |
1712 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1713 | { | |
b8afb911 | 1714 | u32 val; |
f6071166 JB |
1715 | |
1716 | /* Make sure the pipe isn't still relying on us */ | |
1717 | assert_pipe_disabled(dev_priv, pipe); | |
1718 | ||
03ed5cbf VS |
1719 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1720 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1721 | if (pipe != PIPE_A) | |
1722 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1723 | ||
f6071166 JB |
1724 | I915_WRITE(DPLL(pipe), val); |
1725 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1726 | } |
1727 | ||
1728 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1729 | { | |
d752048d | 1730 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1731 | u32 val; |
1732 | ||
a11b0703 VS |
1733 | /* Make sure the pipe isn't still relying on us */ |
1734 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1735 | |
60bfe44f VS |
1736 | val = DPLL_SSC_REF_CLK_CHV | |
1737 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1738 | if (pipe != PIPE_A) |
1739 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1740 | |
a11b0703 VS |
1741 | I915_WRITE(DPLL(pipe), val); |
1742 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1743 | |
a580516d | 1744 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1745 | |
1746 | /* Disable 10bit clock to display controller */ | |
1747 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1748 | val &= ~DPIO_DCLKP_EN; | |
1749 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1750 | ||
a580516d | 1751 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1752 | } |
1753 | ||
e4607fcf | 1754 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1755 | struct intel_digital_port *dport, |
1756 | unsigned int expected_mask) | |
89b667f8 JB |
1757 | { |
1758 | u32 port_mask; | |
f0f59a00 | 1759 | i915_reg_t dpll_reg; |
89b667f8 | 1760 | |
e4607fcf CML |
1761 | switch (dport->port) { |
1762 | case PORT_B: | |
89b667f8 | 1763 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1764 | dpll_reg = DPLL(0); |
e4607fcf CML |
1765 | break; |
1766 | case PORT_C: | |
89b667f8 | 1767 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1768 | dpll_reg = DPLL(0); |
9b6de0a1 | 1769 | expected_mask <<= 4; |
00fc31b7 CML |
1770 | break; |
1771 | case PORT_D: | |
1772 | port_mask = DPLL_PORTD_READY_MASK; | |
1773 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1774 | break; |
1775 | default: | |
1776 | BUG(); | |
1777 | } | |
89b667f8 | 1778 | |
370004d3 CW |
1779 | if (intel_wait_for_register(dev_priv, |
1780 | dpll_reg, port_mask, expected_mask, | |
1781 | 1000)) | |
9b6de0a1 VS |
1782 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1783 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1784 | } |
1785 | ||
b8a4f404 PZ |
1786 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1787 | enum pipe pipe) | |
040484af | 1788 | { |
91c8a326 | 1789 | struct drm_device *dev = &dev_priv->drm; |
7c26e5c6 | 1790 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1792 | i915_reg_t reg; |
1793 | uint32_t val, pipeconf_val; | |
040484af | 1794 | |
040484af | 1795 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1796 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1797 | |
1798 | /* FDI must be feeding us bits for PCH ports */ | |
1799 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1800 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1801 | ||
23670b32 DV |
1802 | if (HAS_PCH_CPT(dev)) { |
1803 | /* Workaround: Set the timing override bit before enabling the | |
1804 | * pch transcoder. */ | |
1805 | reg = TRANS_CHICKEN2(pipe); | |
1806 | val = I915_READ(reg); | |
1807 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1808 | I915_WRITE(reg, val); | |
59c859d6 | 1809 | } |
23670b32 | 1810 | |
ab9412ba | 1811 | reg = PCH_TRANSCONF(pipe); |
040484af | 1812 | val = I915_READ(reg); |
5f7f726d | 1813 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1814 | |
2d1fe073 | 1815 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1816 | /* |
c5de7c6f VS |
1817 | * Make the BPC in transcoder be consistent with |
1818 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1819 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1820 | */ |
dfd07d72 | 1821 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1822 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1823 | val |= PIPECONF_8BPC; |
1824 | else | |
1825 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1826 | } |
5f7f726d PZ |
1827 | |
1828 | val &= ~TRANS_INTERLACE_MASK; | |
1829 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1830 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1831 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1832 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1833 | else | |
1834 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1835 | else |
1836 | val |= TRANS_PROGRESSIVE; | |
1837 | ||
040484af | 1838 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1839 | if (intel_wait_for_register(dev_priv, |
1840 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1841 | 100)) | |
4bb6f1f3 | 1842 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1843 | } |
1844 | ||
8fb033d7 | 1845 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1846 | enum transcoder cpu_transcoder) |
040484af | 1847 | { |
8fb033d7 | 1848 | u32 val, pipeconf_val; |
8fb033d7 | 1849 | |
8fb033d7 | 1850 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1851 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1852 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1853 | |
223a6fdf | 1854 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1858 | |
25f3ef11 | 1859 | val = TRANS_ENABLE; |
937bb610 | 1860 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1861 | |
9a76b1c6 PZ |
1862 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1863 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1864 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1865 | else |
1866 | val |= TRANS_PROGRESSIVE; | |
1867 | ||
ab9412ba | 1868 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, | |
1871 | TRANS_STATE_ENABLE, | |
1872 | TRANS_STATE_ENABLE, | |
1873 | 100)) | |
937bb610 | 1874 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1875 | } |
1876 | ||
b8a4f404 PZ |
1877 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1878 | enum pipe pipe) | |
040484af | 1879 | { |
91c8a326 | 1880 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 VS |
1881 | i915_reg_t reg; |
1882 | uint32_t val; | |
040484af JB |
1883 | |
1884 | /* FDI relies on the transcoder */ | |
1885 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1886 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1887 | ||
291906f1 JB |
1888 | /* Ports must be off as well */ |
1889 | assert_pch_ports_disabled(dev_priv, pipe); | |
1890 | ||
ab9412ba | 1891 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1892 | val = I915_READ(reg); |
1893 | val &= ~TRANS_ENABLE; | |
1894 | I915_WRITE(reg, val); | |
1895 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1896 | if (intel_wait_for_register(dev_priv, |
1897 | reg, TRANS_STATE_ENABLE, 0, | |
1898 | 50)) | |
4bb6f1f3 | 1899 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1900 | |
c465613b | 1901 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1902 | /* Workaround: Clear the timing override chicken bit again. */ |
1903 | reg = TRANS_CHICKEN2(pipe); | |
1904 | val = I915_READ(reg); | |
1905 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1906 | I915_WRITE(reg, val); | |
1907 | } | |
040484af JB |
1908 | } |
1909 | ||
ab4d966c | 1910 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1911 | { |
8fb033d7 PZ |
1912 | u32 val; |
1913 | ||
ab9412ba | 1914 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1915 | val &= ~TRANS_ENABLE; |
ab9412ba | 1916 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1917 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1918 | if (intel_wait_for_register(dev_priv, |
1919 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1920 | 50)) | |
8a52fd9f | 1921 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1922 | |
1923 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1924 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1925 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1926 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1927 | } |
1928 | ||
b24e7179 | 1929 | /** |
309cfea8 | 1930 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1931 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1932 | * |
0372264a | 1933 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1934 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1935 | */ |
e1fdc473 | 1936 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1937 | { |
0372264a | 1938 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1939 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1940 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1941 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1942 | enum pipe pch_transcoder; |
f0f59a00 | 1943 | i915_reg_t reg; |
b24e7179 JB |
1944 | u32 val; |
1945 | ||
9e2ee2dd VS |
1946 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1947 | ||
58c6eaa2 | 1948 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1949 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1950 | assert_sprites_disabled(dev_priv, pipe); |
1951 | ||
2d1fe073 | 1952 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1953 | pch_transcoder = TRANSCODER_A; |
1954 | else | |
1955 | pch_transcoder = pipe; | |
1956 | ||
b24e7179 JB |
1957 | /* |
1958 | * A pipe without a PLL won't actually be able to drive bits from | |
1959 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1960 | * need the check. | |
1961 | */ | |
09fa8bb9 | 1962 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1963 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1964 | assert_dsi_pll_enabled(dev_priv); |
1965 | else | |
1966 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1967 | } else { |
6e3c9717 | 1968 | if (crtc->config->has_pch_encoder) { |
040484af | 1969 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1970 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1971 | assert_fdi_tx_pll_enabled(dev_priv, |
1972 | (enum pipe) cpu_transcoder); | |
040484af JB |
1973 | } |
1974 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1975 | } | |
b24e7179 | 1976 | |
702e7a56 | 1977 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1978 | val = I915_READ(reg); |
7ad25d48 | 1979 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1980 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1981 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1982 | return; |
7ad25d48 | 1983 | } |
00d70b15 CW |
1984 | |
1985 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1986 | POSTING_READ(reg); |
b7792d8b VS |
1987 | |
1988 | /* | |
1989 | * Until the pipe starts DSL will read as 0, which would cause | |
1990 | * an apparent vblank timestamp jump, which messes up also the | |
1991 | * frame count when it's derived from the timestamps. So let's | |
1992 | * wait for the pipe to start properly before we call | |
1993 | * drm_crtc_vblank_on() | |
1994 | */ | |
1995 | if (dev->max_vblank_count == 0 && | |
1996 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1997 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1998 | } |
1999 | ||
2000 | /** | |
309cfea8 | 2001 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2002 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2003 | * |
575f7ab7 VS |
2004 | * Disable the pipe of @crtc, making sure that various hardware |
2005 | * specific requirements are met, if applicable, e.g. plane | |
2006 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2007 | * |
2008 | * Will wait until the pipe has shut down before returning. | |
2009 | */ | |
575f7ab7 | 2010 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2011 | { |
fac5e23e | 2012 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2013 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2014 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2015 | i915_reg_t reg; |
b24e7179 JB |
2016 | u32 val; |
2017 | ||
9e2ee2dd VS |
2018 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2019 | ||
b24e7179 JB |
2020 | /* |
2021 | * Make sure planes won't keep trying to pump pixels to us, | |
2022 | * or we might hang the display. | |
2023 | */ | |
2024 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2025 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2026 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2027 | |
702e7a56 | 2028 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2029 | val = I915_READ(reg); |
00d70b15 CW |
2030 | if ((val & PIPECONF_ENABLE) == 0) |
2031 | return; | |
2032 | ||
67adc644 VS |
2033 | /* |
2034 | * Double wide has implications for planes | |
2035 | * so best keep it disabled when not needed. | |
2036 | */ | |
6e3c9717 | 2037 | if (crtc->config->double_wide) |
67adc644 VS |
2038 | val &= ~PIPECONF_DOUBLE_WIDE; |
2039 | ||
2040 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2041 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2042 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2043 | val &= ~PIPECONF_ENABLE; |
2044 | ||
2045 | I915_WRITE(reg, val); | |
2046 | if ((val & PIPECONF_ENABLE) == 0) | |
2047 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2048 | } |
2049 | ||
832be82f VS |
2050 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2051 | { | |
2052 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2053 | } | |
2054 | ||
27ba3910 VS |
2055 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2056 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2057 | { |
2058 | switch (fb_modifier) { | |
2059 | case DRM_FORMAT_MOD_NONE: | |
2060 | return cpp; | |
2061 | case I915_FORMAT_MOD_X_TILED: | |
2062 | if (IS_GEN2(dev_priv)) | |
2063 | return 128; | |
2064 | else | |
2065 | return 512; | |
2066 | case I915_FORMAT_MOD_Y_TILED: | |
2067 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2068 | return 128; | |
2069 | else | |
2070 | return 512; | |
2071 | case I915_FORMAT_MOD_Yf_TILED: | |
2072 | switch (cpp) { | |
2073 | case 1: | |
2074 | return 64; | |
2075 | case 2: | |
2076 | case 4: | |
2077 | return 128; | |
2078 | case 8: | |
2079 | case 16: | |
2080 | return 256; | |
2081 | default: | |
2082 | MISSING_CASE(cpp); | |
2083 | return cpp; | |
2084 | } | |
2085 | break; | |
2086 | default: | |
2087 | MISSING_CASE(fb_modifier); | |
2088 | return cpp; | |
2089 | } | |
2090 | } | |
2091 | ||
832be82f VS |
2092 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2093 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2094 | { |
832be82f VS |
2095 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2096 | return 1; | |
2097 | else | |
2098 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2099 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2100 | } |
2101 | ||
8d0deca8 VS |
2102 | /* Return the tile dimensions in pixel units */ |
2103 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2104 | unsigned int *tile_width, | |
2105 | unsigned int *tile_height, | |
2106 | uint64_t fb_modifier, | |
2107 | unsigned int cpp) | |
2108 | { | |
2109 | unsigned int tile_width_bytes = | |
2110 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2111 | ||
2112 | *tile_width = tile_width_bytes / cpp; | |
2113 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2114 | } | |
2115 | ||
6761dd31 TU |
2116 | unsigned int |
2117 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2118 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2119 | { |
832be82f VS |
2120 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2121 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2122 | ||
2123 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2124 | } |
2125 | ||
1663b9d6 VS |
2126 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2127 | { | |
2128 | unsigned int size = 0; | |
2129 | int i; | |
2130 | ||
2131 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2132 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2133 | ||
2134 | return size; | |
2135 | } | |
2136 | ||
75c82a53 | 2137 | static void |
3465c580 VS |
2138 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2139 | const struct drm_framebuffer *fb, | |
2140 | unsigned int rotation) | |
f64b98cd | 2141 | { |
2d7a215f VS |
2142 | if (intel_rotation_90_or_270(rotation)) { |
2143 | *view = i915_ggtt_view_rotated; | |
2144 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2145 | } else { | |
2146 | *view = i915_ggtt_view_normal; | |
2147 | } | |
2148 | } | |
50470bb0 | 2149 | |
603525d7 | 2150 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2151 | { |
2152 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2153 | return 256 * 1024; | |
985b8bb4 | 2154 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2155 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2156 | return 128 * 1024; |
2157 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2158 | return 4 * 1024; | |
2159 | else | |
44c5905e | 2160 | return 0; |
4e9a86b6 VS |
2161 | } |
2162 | ||
603525d7 VS |
2163 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2164 | uint64_t fb_modifier) | |
2165 | { | |
2166 | switch (fb_modifier) { | |
2167 | case DRM_FORMAT_MOD_NONE: | |
2168 | return intel_linear_alignment(dev_priv); | |
2169 | case I915_FORMAT_MOD_X_TILED: | |
2170 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2171 | return 256 * 1024; | |
2172 | return 0; | |
2173 | case I915_FORMAT_MOD_Y_TILED: | |
2174 | case I915_FORMAT_MOD_Yf_TILED: | |
2175 | return 1 * 1024 * 1024; | |
2176 | default: | |
2177 | MISSING_CASE(fb_modifier); | |
2178 | return 0; | |
2179 | } | |
2180 | } | |
2181 | ||
058d88c4 CW |
2182 | struct i915_vma * |
2183 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2184 | { |
850c4cdc | 2185 | struct drm_device *dev = fb->dev; |
fac5e23e | 2186 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2187 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2188 | struct i915_ggtt_view view; |
058d88c4 | 2189 | struct i915_vma *vma; |
6b95a207 | 2190 | u32 alignment; |
6b95a207 | 2191 | |
ebcdd39e MR |
2192 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2193 | ||
603525d7 | 2194 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2195 | |
3465c580 | 2196 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2197 | |
693db184 CW |
2198 | /* Note that the w/a also requires 64 PTE of padding following the |
2199 | * bo. We currently fill all unused PTE with the shadow page and so | |
2200 | * we should always have valid PTE following the scanout preventing | |
2201 | * the VT-d warning. | |
2202 | */ | |
48f112fe | 2203 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2204 | alignment = 256 * 1024; |
2205 | ||
d6dd6843 PZ |
2206 | /* |
2207 | * Global gtt pte registers are special registers which actually forward | |
2208 | * writes to a chunk of system memory. Which means that there is no risk | |
2209 | * that the register values disappear as soon as we call | |
2210 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2211 | * pin/unpin/fence and not more. | |
2212 | */ | |
2213 | intel_runtime_pm_get(dev_priv); | |
2214 | ||
058d88c4 | 2215 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2216 | if (IS_ERR(vma)) |
2217 | goto err; | |
6b95a207 | 2218 | |
05a20d09 | 2219 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2220 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2221 | * fence, whereas 965+ only requires a fence if using | |
2222 | * framebuffer compression. For simplicity, we always, when | |
2223 | * possible, install a fence as the cost is not that onerous. | |
2224 | * | |
2225 | * If we fail to fence the tiled scanout, then either the | |
2226 | * modeset will reject the change (which is highly unlikely as | |
2227 | * the affected systems, all but one, do not have unmappable | |
2228 | * space) or we will not be able to enable full powersaving | |
2229 | * techniques (also likely not to apply due to various limits | |
2230 | * FBC and the like impose on the size of the buffer, which | |
2231 | * presumably we violated anyway with this unmappable buffer). | |
2232 | * Anyway, it is presumably better to stumble onwards with | |
2233 | * something and try to run the system in a "less than optimal" | |
2234 | * mode that matches the user configuration. | |
2235 | */ | |
2236 | if (i915_vma_get_fence(vma) == 0) | |
2237 | i915_vma_pin_fence(vma); | |
9807216f | 2238 | } |
6b95a207 | 2239 | |
49ef5294 | 2240 | err: |
d6dd6843 | 2241 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2242 | return vma; |
6b95a207 KH |
2243 | } |
2244 | ||
fb4b8ce1 | 2245 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2246 | { |
82bc3b2d | 2247 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2248 | struct i915_ggtt_view view; |
058d88c4 | 2249 | struct i915_vma *vma; |
82bc3b2d | 2250 | |
ebcdd39e MR |
2251 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2252 | ||
3465c580 | 2253 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
05a20d09 | 2254 | vma = i915_gem_object_to_ggtt(obj, &view); |
f64b98cd | 2255 | |
49ef5294 | 2256 | i915_vma_unpin_fence(vma); |
058d88c4 | 2257 | i915_gem_object_unpin_from_display_plane(vma); |
1690e1eb CW |
2258 | } |
2259 | ||
ef78ec94 VS |
2260 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2261 | unsigned int rotation) | |
2262 | { | |
2263 | if (intel_rotation_90_or_270(rotation)) | |
2264 | return to_intel_framebuffer(fb)->rotated[plane].pitch; | |
2265 | else | |
2266 | return fb->pitches[plane]; | |
2267 | } | |
2268 | ||
6687c906 VS |
2269 | /* |
2270 | * Convert the x/y offsets into a linear offset. | |
2271 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2272 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2273 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2274 | */ | |
2275 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2276 | const struct intel_plane_state *state, |
2277 | int plane) | |
6687c906 | 2278 | { |
2949056c | 2279 | const struct drm_framebuffer *fb = state->base.fb; |
6687c906 VS |
2280 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
2281 | unsigned int pitch = fb->pitches[plane]; | |
2282 | ||
2283 | return y * pitch + x * cpp; | |
2284 | } | |
2285 | ||
2286 | /* | |
2287 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2288 | * specified plane src x/y offsets. The resulting x/y offsets | |
2289 | * specify the start of scanout from the beginning of the gtt mapping. | |
2290 | */ | |
2291 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2292 | const struct intel_plane_state *state, |
2293 | int plane) | |
6687c906 VS |
2294 | |
2295 | { | |
2949056c VS |
2296 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2297 | unsigned int rotation = state->base.rotation; | |
6687c906 VS |
2298 | |
2299 | if (intel_rotation_90_or_270(rotation)) { | |
2300 | *x += intel_fb->rotated[plane].x; | |
2301 | *y += intel_fb->rotated[plane].y; | |
2302 | } else { | |
2303 | *x += intel_fb->normal[plane].x; | |
2304 | *y += intel_fb->normal[plane].y; | |
2305 | } | |
2306 | } | |
2307 | ||
29cf9491 | 2308 | /* |
29cf9491 VS |
2309 | * Input tile dimensions and pitch must already be |
2310 | * rotated to match x and y, and in pixel units. | |
2311 | */ | |
66a2d927 VS |
2312 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2313 | unsigned int tile_width, | |
2314 | unsigned int tile_height, | |
2315 | unsigned int tile_size, | |
2316 | unsigned int pitch_tiles, | |
2317 | u32 old_offset, | |
2318 | u32 new_offset) | |
29cf9491 | 2319 | { |
b9b24038 | 2320 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2321 | unsigned int tiles; |
2322 | ||
2323 | WARN_ON(old_offset & (tile_size - 1)); | |
2324 | WARN_ON(new_offset & (tile_size - 1)); | |
2325 | WARN_ON(new_offset > old_offset); | |
2326 | ||
2327 | tiles = (old_offset - new_offset) / tile_size; | |
2328 | ||
2329 | *y += tiles / pitch_tiles * tile_height; | |
2330 | *x += tiles % pitch_tiles * tile_width; | |
2331 | ||
b9b24038 VS |
2332 | /* minimize x in case it got needlessly big */ |
2333 | *y += *x / pitch_pixels * tile_height; | |
2334 | *x %= pitch_pixels; | |
2335 | ||
29cf9491 VS |
2336 | return new_offset; |
2337 | } | |
2338 | ||
66a2d927 VS |
2339 | /* |
2340 | * Adjust the tile offset by moving the difference into | |
2341 | * the x/y offsets. | |
2342 | */ | |
2343 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2344 | const struct intel_plane_state *state, int plane, | |
2345 | u32 old_offset, u32 new_offset) | |
2346 | { | |
2347 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2348 | const struct drm_framebuffer *fb = state->base.fb; | |
2349 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2350 | unsigned int rotation = state->base.rotation; | |
2351 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2352 | ||
2353 | WARN_ON(new_offset > old_offset); | |
2354 | ||
2355 | if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) { | |
2356 | unsigned int tile_size, tile_width, tile_height; | |
2357 | unsigned int pitch_tiles; | |
2358 | ||
2359 | tile_size = intel_tile_size(dev_priv); | |
2360 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2361 | fb->modifier[plane], cpp); | |
2362 | ||
2363 | if (intel_rotation_90_or_270(rotation)) { | |
2364 | pitch_tiles = pitch / tile_height; | |
2365 | swap(tile_width, tile_height); | |
2366 | } else { | |
2367 | pitch_tiles = pitch / (tile_width * cpp); | |
2368 | } | |
2369 | ||
2370 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2371 | tile_size, pitch_tiles, | |
2372 | old_offset, new_offset); | |
2373 | } else { | |
2374 | old_offset += *y * pitch + *x * cpp; | |
2375 | ||
2376 | *y = (old_offset - new_offset) / pitch; | |
2377 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2378 | } | |
2379 | ||
2380 | return new_offset; | |
2381 | } | |
2382 | ||
8d0deca8 VS |
2383 | /* |
2384 | * Computes the linear offset to the base tile and adjusts | |
2385 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2386 | * | |
2387 | * In the 90/270 rotated case, x and y are assumed | |
2388 | * to be already rotated to match the rotated GTT view, and | |
2389 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2390 | * |
2391 | * This function is used when computing the derived information | |
2392 | * under intel_framebuffer, so using any of that information | |
2393 | * here is not allowed. Anything under drm_framebuffer can be | |
2394 | * used. This is why the user has to pass in the pitch since it | |
2395 | * is specified in the rotated orientation. | |
8d0deca8 | 2396 | */ |
6687c906 VS |
2397 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2398 | int *x, int *y, | |
2399 | const struct drm_framebuffer *fb, int plane, | |
2400 | unsigned int pitch, | |
2401 | unsigned int rotation, | |
2402 | u32 alignment) | |
c2c75131 | 2403 | { |
4f2d9934 VS |
2404 | uint64_t fb_modifier = fb->modifier[plane]; |
2405 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
6687c906 | 2406 | u32 offset, offset_aligned; |
29cf9491 | 2407 | |
29cf9491 VS |
2408 | if (alignment) |
2409 | alignment--; | |
2410 | ||
b5c65338 | 2411 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2412 | unsigned int tile_size, tile_width, tile_height; |
2413 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2414 | |
d843310d | 2415 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2416 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2417 | fb_modifier, cpp); | |
2418 | ||
2419 | if (intel_rotation_90_or_270(rotation)) { | |
2420 | pitch_tiles = pitch / tile_height; | |
2421 | swap(tile_width, tile_height); | |
2422 | } else { | |
2423 | pitch_tiles = pitch / (tile_width * cpp); | |
2424 | } | |
d843310d VS |
2425 | |
2426 | tile_rows = *y / tile_height; | |
2427 | *y %= tile_height; | |
c2c75131 | 2428 | |
8d0deca8 VS |
2429 | tiles = *x / tile_width; |
2430 | *x %= tile_width; | |
bc752862 | 2431 | |
29cf9491 VS |
2432 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2433 | offset_aligned = offset & ~alignment; | |
bc752862 | 2434 | |
66a2d927 VS |
2435 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2436 | tile_size, pitch_tiles, | |
2437 | offset, offset_aligned); | |
29cf9491 | 2438 | } else { |
bc752862 | 2439 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2440 | offset_aligned = offset & ~alignment; |
2441 | ||
4e9a86b6 VS |
2442 | *y = (offset & alignment) / pitch; |
2443 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2444 | } |
29cf9491 VS |
2445 | |
2446 | return offset_aligned; | |
c2c75131 DV |
2447 | } |
2448 | ||
6687c906 | 2449 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2450 | const struct intel_plane_state *state, |
2451 | int plane) | |
6687c906 | 2452 | { |
2949056c VS |
2453 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2454 | const struct drm_framebuffer *fb = state->base.fb; | |
2455 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2456 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2457 | u32 alignment; |
2458 | ||
2459 | /* AUX_DIST needs only 4K alignment */ | |
2460 | if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) | |
2461 | alignment = 4096; | |
2462 | else | |
2463 | alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]); | |
6687c906 VS |
2464 | |
2465 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2466 | rotation, alignment); | |
2467 | } | |
2468 | ||
2469 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2470 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2471 | const struct drm_framebuffer *fb, int plane) | |
2472 | { | |
2473 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2474 | unsigned int pitch = fb->pitches[plane]; | |
2475 | u32 linear_offset = fb->offsets[plane]; | |
2476 | ||
2477 | *y = linear_offset / pitch; | |
2478 | *x = linear_offset % pitch / cpp; | |
2479 | } | |
2480 | ||
72618ebf VS |
2481 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2482 | { | |
2483 | switch (fb_modifier) { | |
2484 | case I915_FORMAT_MOD_X_TILED: | |
2485 | return I915_TILING_X; | |
2486 | case I915_FORMAT_MOD_Y_TILED: | |
2487 | return I915_TILING_Y; | |
2488 | default: | |
2489 | return I915_TILING_NONE; | |
2490 | } | |
2491 | } | |
2492 | ||
6687c906 VS |
2493 | static int |
2494 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2495 | struct drm_framebuffer *fb) | |
2496 | { | |
2497 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2498 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2499 | u32 gtt_offset_rotated = 0; | |
2500 | unsigned int max_size = 0; | |
2501 | uint32_t format = fb->pixel_format; | |
2502 | int i, num_planes = drm_format_num_planes(format); | |
2503 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2504 | ||
2505 | for (i = 0; i < num_planes; i++) { | |
2506 | unsigned int width, height; | |
2507 | unsigned int cpp, size; | |
2508 | u32 offset; | |
2509 | int x, y; | |
2510 | ||
2511 | cpp = drm_format_plane_cpp(format, i); | |
2512 | width = drm_format_plane_width(fb->width, format, i); | |
2513 | height = drm_format_plane_height(fb->height, format, i); | |
2514 | ||
2515 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2516 | ||
60d5f2a4 VS |
2517 | /* |
2518 | * The fence (if used) is aligned to the start of the object | |
2519 | * so having the framebuffer wrap around across the edge of the | |
2520 | * fenced region doesn't really work. We have no API to configure | |
2521 | * the fence start offset within the object (nor could we probably | |
2522 | * on gen2/3). So it's just easier if we just require that the | |
2523 | * fb layout agrees with the fence layout. We already check that the | |
2524 | * fb stride matches the fence stride elsewhere. | |
2525 | */ | |
2526 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2527 | (x + width) * cpp > fb->pitches[i]) { | |
2528 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2529 | i, fb->offsets[i]); | |
2530 | return -EINVAL; | |
2531 | } | |
2532 | ||
6687c906 VS |
2533 | /* |
2534 | * First pixel of the framebuffer from | |
2535 | * the start of the normal gtt mapping. | |
2536 | */ | |
2537 | intel_fb->normal[i].x = x; | |
2538 | intel_fb->normal[i].y = y; | |
2539 | ||
2540 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2541 | fb, 0, fb->pitches[i], | |
cc926387 | 2542 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2543 | offset /= tile_size; |
2544 | ||
2545 | if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) { | |
2546 | unsigned int tile_width, tile_height; | |
2547 | unsigned int pitch_tiles; | |
2548 | struct drm_rect r; | |
2549 | ||
2550 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2551 | fb->modifier[i], cpp); | |
2552 | ||
2553 | rot_info->plane[i].offset = offset; | |
2554 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2555 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2556 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2557 | ||
2558 | intel_fb->rotated[i].pitch = | |
2559 | rot_info->plane[i].height * tile_height; | |
2560 | ||
2561 | /* how many tiles does this plane need */ | |
2562 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2563 | /* | |
2564 | * If the plane isn't horizontally tile aligned, | |
2565 | * we need one more tile. | |
2566 | */ | |
2567 | if (x != 0) | |
2568 | size++; | |
2569 | ||
2570 | /* rotate the x/y offsets to match the GTT view */ | |
2571 | r.x1 = x; | |
2572 | r.y1 = y; | |
2573 | r.x2 = x + width; | |
2574 | r.y2 = y + height; | |
2575 | drm_rect_rotate(&r, | |
2576 | rot_info->plane[i].width * tile_width, | |
2577 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2578 | DRM_ROTATE_270); |
6687c906 VS |
2579 | x = r.x1; |
2580 | y = r.y1; | |
2581 | ||
2582 | /* rotate the tile dimensions to match the GTT view */ | |
2583 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2584 | swap(tile_width, tile_height); | |
2585 | ||
2586 | /* | |
2587 | * We only keep the x/y offsets, so push all of the | |
2588 | * gtt offset into the x/y offsets. | |
2589 | */ | |
66a2d927 VS |
2590 | _intel_adjust_tile_offset(&x, &y, tile_size, |
2591 | tile_width, tile_height, pitch_tiles, | |
2592 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2593 | |
2594 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2595 | ||
2596 | /* | |
2597 | * First pixel of the framebuffer from | |
2598 | * the start of the rotated gtt mapping. | |
2599 | */ | |
2600 | intel_fb->rotated[i].x = x; | |
2601 | intel_fb->rotated[i].y = y; | |
2602 | } else { | |
2603 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2604 | x * cpp, tile_size); | |
2605 | } | |
2606 | ||
2607 | /* how many tiles in total needed in the bo */ | |
2608 | max_size = max(max_size, offset + size); | |
2609 | } | |
2610 | ||
2611 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2612 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2613 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2614 | return -EINVAL; | |
2615 | } | |
2616 | ||
2617 | return 0; | |
2618 | } | |
2619 | ||
b35d63fa | 2620 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2621 | { |
2622 | switch (format) { | |
2623 | case DISPPLANE_8BPP: | |
2624 | return DRM_FORMAT_C8; | |
2625 | case DISPPLANE_BGRX555: | |
2626 | return DRM_FORMAT_XRGB1555; | |
2627 | case DISPPLANE_BGRX565: | |
2628 | return DRM_FORMAT_RGB565; | |
2629 | default: | |
2630 | case DISPPLANE_BGRX888: | |
2631 | return DRM_FORMAT_XRGB8888; | |
2632 | case DISPPLANE_RGBX888: | |
2633 | return DRM_FORMAT_XBGR8888; | |
2634 | case DISPPLANE_BGRX101010: | |
2635 | return DRM_FORMAT_XRGB2101010; | |
2636 | case DISPPLANE_RGBX101010: | |
2637 | return DRM_FORMAT_XBGR2101010; | |
2638 | } | |
2639 | } | |
2640 | ||
bc8d7dff DL |
2641 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2642 | { | |
2643 | switch (format) { | |
2644 | case PLANE_CTL_FORMAT_RGB_565: | |
2645 | return DRM_FORMAT_RGB565; | |
2646 | default: | |
2647 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2648 | if (rgb_order) { | |
2649 | if (alpha) | |
2650 | return DRM_FORMAT_ABGR8888; | |
2651 | else | |
2652 | return DRM_FORMAT_XBGR8888; | |
2653 | } else { | |
2654 | if (alpha) | |
2655 | return DRM_FORMAT_ARGB8888; | |
2656 | else | |
2657 | return DRM_FORMAT_XRGB8888; | |
2658 | } | |
2659 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2660 | if (rgb_order) | |
2661 | return DRM_FORMAT_XBGR2101010; | |
2662 | else | |
2663 | return DRM_FORMAT_XRGB2101010; | |
2664 | } | |
2665 | } | |
2666 | ||
5724dbd1 | 2667 | static bool |
f6936e29 DV |
2668 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2669 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2670 | { |
2671 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2672 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2673 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2674 | struct drm_i915_gem_object *obj = NULL; |
2675 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2676 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2677 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2678 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2679 | PAGE_SIZE); | |
2680 | ||
2681 | size_aligned -= base_aligned; | |
46f297fb | 2682 | |
ff2652ea CW |
2683 | if (plane_config->size == 0) |
2684 | return false; | |
2685 | ||
3badb49f PZ |
2686 | /* If the FB is too big, just don't use it since fbdev is not very |
2687 | * important and we should probably use that space with FBC or other | |
2688 | * features. */ | |
72e96d64 | 2689 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2690 | return false; |
2691 | ||
12c83d99 TU |
2692 | mutex_lock(&dev->struct_mutex); |
2693 | ||
f37b5c2b DV |
2694 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2695 | base_aligned, | |
2696 | base_aligned, | |
2697 | size_aligned); | |
12c83d99 TU |
2698 | if (!obj) { |
2699 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2700 | return false; |
12c83d99 | 2701 | } |
46f297fb | 2702 | |
3e510a8e CW |
2703 | if (plane_config->tiling == I915_TILING_X) |
2704 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2705 | |
6bf129df DL |
2706 | mode_cmd.pixel_format = fb->pixel_format; |
2707 | mode_cmd.width = fb->width; | |
2708 | mode_cmd.height = fb->height; | |
2709 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2710 | mode_cmd.modifier[0] = fb->modifier[0]; |
2711 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2712 | |
6bf129df | 2713 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2714 | &mode_cmd, obj)) { |
46f297fb JB |
2715 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2716 | goto out_unref_obj; | |
2717 | } | |
12c83d99 | 2718 | |
46f297fb | 2719 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2720 | |
f6936e29 | 2721 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2722 | return true; |
46f297fb JB |
2723 | |
2724 | out_unref_obj: | |
f8c417cd | 2725 | i915_gem_object_put(obj); |
46f297fb | 2726 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2727 | return false; |
2728 | } | |
2729 | ||
5a21b665 DV |
2730 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2731 | static void | |
2732 | update_state_fb(struct drm_plane *plane) | |
2733 | { | |
2734 | if (plane->fb == plane->state->fb) | |
2735 | return; | |
2736 | ||
2737 | if (plane->state->fb) | |
2738 | drm_framebuffer_unreference(plane->state->fb); | |
2739 | plane->state->fb = plane->fb; | |
2740 | if (plane->state->fb) | |
2741 | drm_framebuffer_reference(plane->state->fb); | |
2742 | } | |
2743 | ||
5724dbd1 | 2744 | static void |
f6936e29 DV |
2745 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2746 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2747 | { |
2748 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2749 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2750 | struct drm_crtc *c; |
2751 | struct intel_crtc *i; | |
2ff8fde1 | 2752 | struct drm_i915_gem_object *obj; |
88595ac9 | 2753 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2754 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2755 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2756 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2757 | struct intel_plane_state *intel_state = |
2758 | to_intel_plane_state(plane_state); | |
88595ac9 | 2759 | struct drm_framebuffer *fb; |
484b41dd | 2760 | |
2d14030b | 2761 | if (!plane_config->fb) |
484b41dd JB |
2762 | return; |
2763 | ||
f6936e29 | 2764 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2765 | fb = &plane_config->fb->base; |
2766 | goto valid_fb; | |
f55548b5 | 2767 | } |
484b41dd | 2768 | |
2d14030b | 2769 | kfree(plane_config->fb); |
484b41dd JB |
2770 | |
2771 | /* | |
2772 | * Failed to alloc the obj, check to see if we should share | |
2773 | * an fb with another CRTC instead | |
2774 | */ | |
70e1e0ec | 2775 | for_each_crtc(dev, c) { |
484b41dd JB |
2776 | i = to_intel_crtc(c); |
2777 | ||
2778 | if (c == &intel_crtc->base) | |
2779 | continue; | |
2780 | ||
2ff8fde1 MR |
2781 | if (!i->active) |
2782 | continue; | |
2783 | ||
88595ac9 DV |
2784 | fb = c->primary->fb; |
2785 | if (!fb) | |
484b41dd JB |
2786 | continue; |
2787 | ||
88595ac9 | 2788 | obj = intel_fb_obj(fb); |
058d88c4 | 2789 | if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) { |
88595ac9 DV |
2790 | drm_framebuffer_reference(fb); |
2791 | goto valid_fb; | |
484b41dd JB |
2792 | } |
2793 | } | |
88595ac9 | 2794 | |
200757f5 MR |
2795 | /* |
2796 | * We've failed to reconstruct the BIOS FB. Current display state | |
2797 | * indicates that the primary plane is visible, but has a NULL FB, | |
2798 | * which will lead to problems later if we don't fix it up. The | |
2799 | * simplest solution is to just disable the primary plane now and | |
2800 | * pretend the BIOS never had it enabled. | |
2801 | */ | |
936e71e3 | 2802 | to_intel_plane_state(plane_state)->base.visible = false; |
200757f5 | 2803 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
2622a081 | 2804 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2805 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2806 | ||
88595ac9 DV |
2807 | return; |
2808 | ||
2809 | valid_fb: | |
f44e2659 VS |
2810 | plane_state->src_x = 0; |
2811 | plane_state->src_y = 0; | |
be5651f2 ML |
2812 | plane_state->src_w = fb->width << 16; |
2813 | plane_state->src_h = fb->height << 16; | |
2814 | ||
f44e2659 VS |
2815 | plane_state->crtc_x = 0; |
2816 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2817 | plane_state->crtc_w = fb->width; |
2818 | plane_state->crtc_h = fb->height; | |
2819 | ||
936e71e3 VS |
2820 | intel_state->base.src.x1 = plane_state->src_x; |
2821 | intel_state->base.src.y1 = plane_state->src_y; | |
2822 | intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w; | |
2823 | intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h; | |
2824 | intel_state->base.dst.x1 = plane_state->crtc_x; | |
2825 | intel_state->base.dst.y1 = plane_state->crtc_y; | |
2826 | intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2827 | intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
0a8d8a86 | 2828 | |
88595ac9 | 2829 | obj = intel_fb_obj(fb); |
3e510a8e | 2830 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2831 | dev_priv->preserve_bios_swizzle = true; |
2832 | ||
be5651f2 ML |
2833 | drm_framebuffer_reference(fb); |
2834 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2835 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2836 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2837 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2838 | &obj->frontbuffer_bits); | |
46f297fb JB |
2839 | } |
2840 | ||
b63a16f6 VS |
2841 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2842 | unsigned int rotation) | |
2843 | { | |
2844 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2845 | ||
2846 | switch (fb->modifier[plane]) { | |
2847 | case DRM_FORMAT_MOD_NONE: | |
2848 | case I915_FORMAT_MOD_X_TILED: | |
2849 | switch (cpp) { | |
2850 | case 8: | |
2851 | return 4096; | |
2852 | case 4: | |
2853 | case 2: | |
2854 | case 1: | |
2855 | return 8192; | |
2856 | default: | |
2857 | MISSING_CASE(cpp); | |
2858 | break; | |
2859 | } | |
2860 | break; | |
2861 | case I915_FORMAT_MOD_Y_TILED: | |
2862 | case I915_FORMAT_MOD_Yf_TILED: | |
2863 | switch (cpp) { | |
2864 | case 8: | |
2865 | return 2048; | |
2866 | case 4: | |
2867 | return 4096; | |
2868 | case 2: | |
2869 | case 1: | |
2870 | return 8192; | |
2871 | default: | |
2872 | MISSING_CASE(cpp); | |
2873 | break; | |
2874 | } | |
2875 | break; | |
2876 | default: | |
2877 | MISSING_CASE(fb->modifier[plane]); | |
2878 | } | |
2879 | ||
2880 | return 2048; | |
2881 | } | |
2882 | ||
2883 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2884 | { | |
2885 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2886 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2887 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2888 | int x = plane_state->base.src.x1 >> 16; |
2889 | int y = plane_state->base.src.y1 >> 16; | |
2890 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2891 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2892 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2893 | int max_height = 4096; | |
8d970654 | 2894 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2895 | |
2896 | if (w > max_width || h > max_height) { | |
2897 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2898 | w, h, max_width, max_height); | |
2899 | return -EINVAL; | |
2900 | } | |
2901 | ||
2902 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2903 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2904 | ||
2905 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); | |
2906 | ||
8d970654 VS |
2907 | /* |
2908 | * AUX surface offset is specified as the distance from the | |
2909 | * main surface offset, and it must be non-negative. Make | |
2910 | * sure that is what we will get. | |
2911 | */ | |
2912 | if (offset > aux_offset) | |
2913 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2914 | offset, aux_offset & ~(alignment - 1)); | |
2915 | ||
b63a16f6 VS |
2916 | /* |
2917 | * When using an X-tiled surface, the plane blows up | |
2918 | * if the x offset + width exceed the stride. | |
2919 | * | |
2920 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2921 | */ | |
2922 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) { | |
2923 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2924 | ||
2925 | while ((x + w) * cpp > fb->pitches[0]) { | |
2926 | if (offset == 0) { | |
2927 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2928 | return -EINVAL; | |
2929 | } | |
2930 | ||
2931 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2932 | offset, offset - alignment); | |
2933 | } | |
2934 | } | |
2935 | ||
2936 | plane_state->main.offset = offset; | |
2937 | plane_state->main.x = x; | |
2938 | plane_state->main.y = y; | |
2939 | ||
2940 | return 0; | |
2941 | } | |
2942 | ||
8d970654 VS |
2943 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2944 | { | |
2945 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2946 | unsigned int rotation = plane_state->base.rotation; | |
2947 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2948 | int max_height = 4096; | |
cc926387 DV |
2949 | int x = plane_state->base.src.x1 >> 17; |
2950 | int y = plane_state->base.src.y1 >> 17; | |
2951 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2952 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2953 | u32 offset; |
2954 | ||
2955 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2956 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2957 | ||
2958 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2959 | if (w > max_width || h > max_height) { | |
2960 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2961 | w, h, max_width, max_height); | |
2962 | return -EINVAL; | |
2963 | } | |
2964 | ||
2965 | plane_state->aux.offset = offset; | |
2966 | plane_state->aux.x = x; | |
2967 | plane_state->aux.y = y; | |
2968 | ||
2969 | return 0; | |
2970 | } | |
2971 | ||
b63a16f6 VS |
2972 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2973 | { | |
2974 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2975 | unsigned int rotation = plane_state->base.rotation; | |
2976 | int ret; | |
2977 | ||
2978 | /* Rotate src coordinates to match rotated GTT view */ | |
2979 | if (intel_rotation_90_or_270(rotation)) | |
cc926387 DV |
2980 | drm_rect_rotate(&plane_state->base.src, |
2981 | fb->width, fb->height, DRM_ROTATE_270); | |
b63a16f6 | 2982 | |
8d970654 VS |
2983 | /* |
2984 | * Handle the AUX surface first since | |
2985 | * the main surface setup depends on it. | |
2986 | */ | |
2987 | if (fb->pixel_format == DRM_FORMAT_NV12) { | |
2988 | ret = skl_check_nv12_aux_surface(plane_state); | |
2989 | if (ret) | |
2990 | return ret; | |
2991 | } else { | |
2992 | plane_state->aux.offset = ~0xfff; | |
2993 | plane_state->aux.x = 0; | |
2994 | plane_state->aux.y = 0; | |
2995 | } | |
2996 | ||
b63a16f6 VS |
2997 | ret = skl_check_main_surface(plane_state); |
2998 | if (ret) | |
2999 | return ret; | |
3000 | ||
3001 | return 0; | |
3002 | } | |
3003 | ||
a8d201af ML |
3004 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
3005 | const struct intel_crtc_state *crtc_state, | |
3006 | const struct intel_plane_state *plane_state) | |
81255565 | 3007 | { |
a8d201af | 3008 | struct drm_device *dev = primary->dev; |
fac5e23e | 3009 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3011 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3012 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 3013 | int plane = intel_crtc->plane; |
54ea9da8 | 3014 | u32 linear_offset; |
81255565 | 3015 | u32 dspcntr; |
f0f59a00 | 3016 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 3017 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3018 | int x = plane_state->base.src.x1 >> 16; |
3019 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3020 | |
f45651ba VS |
3021 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
3022 | ||
fdd508a6 | 3023 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
3024 | |
3025 | if (INTEL_INFO(dev)->gen < 4) { | |
3026 | if (intel_crtc->pipe == PIPE_B) | |
3027 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3028 | ||
3029 | /* pipesrc and dspsize control the size that is scaled from, | |
3030 | * which should always be the user's requested size. | |
3031 | */ | |
3032 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
3033 | ((crtc_state->pipe_src_h - 1) << 16) | |
3034 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 3035 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
3036 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
3037 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
3038 | ((crtc_state->pipe_src_h - 1) << 16) | |
3039 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
3040 | I915_WRITE(PRIMPOS(plane), 0); |
3041 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3042 | } |
81255565 | 3043 | |
57779d06 VS |
3044 | switch (fb->pixel_format) { |
3045 | case DRM_FORMAT_C8: | |
81255565 JB |
3046 | dspcntr |= DISPPLANE_8BPP; |
3047 | break; | |
57779d06 | 3048 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3049 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3050 | break; |
57779d06 VS |
3051 | case DRM_FORMAT_RGB565: |
3052 | dspcntr |= DISPPLANE_BGRX565; | |
3053 | break; | |
3054 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3055 | dspcntr |= DISPPLANE_BGRX888; |
3056 | break; | |
3057 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3058 | dspcntr |= DISPPLANE_RGBX888; |
3059 | break; | |
3060 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3061 | dspcntr |= DISPPLANE_BGRX101010; |
3062 | break; | |
3063 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3064 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3065 | break; |
3066 | default: | |
baba133a | 3067 | BUG(); |
81255565 | 3068 | } |
57779d06 | 3069 | |
72618ebf VS |
3070 | if (INTEL_GEN(dev_priv) >= 4 && |
3071 | fb->modifier[0] == I915_FORMAT_MOD_X_TILED) | |
f45651ba | 3072 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3073 | |
de1aa629 VS |
3074 | if (IS_G4X(dev)) |
3075 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
3076 | ||
2949056c | 3077 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3078 | |
6687c906 | 3079 | if (INTEL_INFO(dev)->gen >= 4) |
c2c75131 | 3080 | intel_crtc->dspaddr_offset = |
2949056c | 3081 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3082 | |
31ad61e4 | 3083 | if (rotation == DRM_ROTATE_180) { |
48404c1e SJ |
3084 | dspcntr |= DISPPLANE_ROTATE_180; |
3085 | ||
a8d201af ML |
3086 | x += (crtc_state->pipe_src_w - 1); |
3087 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
3088 | } |
3089 | ||
2949056c | 3090 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 VS |
3091 | |
3092 | if (INTEL_INFO(dev)->gen < 4) | |
3093 | intel_crtc->dspaddr_offset = linear_offset; | |
3094 | ||
2db3366b PZ |
3095 | intel_crtc->adjusted_x = x; |
3096 | intel_crtc->adjusted_y = y; | |
3097 | ||
48404c1e SJ |
3098 | I915_WRITE(reg, dspcntr); |
3099 | ||
01f2c773 | 3100 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 3101 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d | 3102 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3103 | intel_fb_gtt_offset(fb, rotation) + |
3104 | intel_crtc->dspaddr_offset); | |
5eddb70b | 3105 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3106 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 3107 | } else |
058d88c4 | 3108 | I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset); |
5eddb70b | 3109 | POSTING_READ(reg); |
17638cd6 JB |
3110 | } |
3111 | ||
a8d201af ML |
3112 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3113 | struct drm_crtc *crtc) | |
17638cd6 JB |
3114 | { |
3115 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3116 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3118 | int plane = intel_crtc->plane; |
f45651ba | 3119 | |
a8d201af ML |
3120 | I915_WRITE(DSPCNTR(plane), 0); |
3121 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3122 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3123 | else |
3124 | I915_WRITE(DSPADDR(plane), 0); | |
3125 | POSTING_READ(DSPCNTR(plane)); | |
3126 | } | |
c9ba6fad | 3127 | |
a8d201af ML |
3128 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3129 | const struct intel_crtc_state *crtc_state, | |
3130 | const struct intel_plane_state *plane_state) | |
3131 | { | |
3132 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3133 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3135 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3136 | int plane = intel_crtc->plane; |
54ea9da8 | 3137 | u32 linear_offset; |
a8d201af ML |
3138 | u32 dspcntr; |
3139 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3140 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3141 | int x = plane_state->base.src.x1 >> 16; |
3142 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3143 | |
f45651ba | 3144 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3145 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
3146 | |
3147 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
3148 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 3149 | |
57779d06 VS |
3150 | switch (fb->pixel_format) { |
3151 | case DRM_FORMAT_C8: | |
17638cd6 JB |
3152 | dspcntr |= DISPPLANE_8BPP; |
3153 | break; | |
57779d06 VS |
3154 | case DRM_FORMAT_RGB565: |
3155 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3156 | break; |
57779d06 | 3157 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3158 | dspcntr |= DISPPLANE_BGRX888; |
3159 | break; | |
3160 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3161 | dspcntr |= DISPPLANE_RGBX888; |
3162 | break; | |
3163 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3164 | dspcntr |= DISPPLANE_BGRX101010; |
3165 | break; | |
3166 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3167 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3168 | break; |
3169 | default: | |
baba133a | 3170 | BUG(); |
17638cd6 JB |
3171 | } |
3172 | ||
72618ebf | 3173 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3174 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3175 | |
f45651ba | 3176 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 3177 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3178 | |
2949056c | 3179 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3180 | |
c2c75131 | 3181 | intel_crtc->dspaddr_offset = |
2949056c | 3182 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3183 | |
31ad61e4 | 3184 | if (rotation == DRM_ROTATE_180) { |
48404c1e SJ |
3185 | dspcntr |= DISPPLANE_ROTATE_180; |
3186 | ||
3187 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
3188 | x += (crtc_state->pipe_src_w - 1); |
3189 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
3190 | } |
3191 | } | |
3192 | ||
2949056c | 3193 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3194 | |
2db3366b PZ |
3195 | intel_crtc->adjusted_x = x; |
3196 | intel_crtc->adjusted_y = y; | |
3197 | ||
48404c1e | 3198 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3199 | |
01f2c773 | 3200 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3201 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3202 | intel_fb_gtt_offset(fb, rotation) + |
3203 | intel_crtc->dspaddr_offset); | |
b3dc685e | 3204 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
3205 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3206 | } else { | |
3207 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3208 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3209 | } | |
17638cd6 | 3210 | POSTING_READ(reg); |
17638cd6 JB |
3211 | } |
3212 | ||
7b49f948 VS |
3213 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3214 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3215 | { |
7b49f948 | 3216 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3217 | return 64; |
7b49f948 VS |
3218 | } else { |
3219 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3220 | ||
27ba3910 | 3221 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3222 | } |
3223 | } | |
3224 | ||
6687c906 VS |
3225 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
3226 | unsigned int rotation) | |
121920fa | 3227 | { |
6687c906 | 3228 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 3229 | struct i915_ggtt_view view; |
058d88c4 | 3230 | struct i915_vma *vma; |
121920fa | 3231 | |
6687c906 | 3232 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 3233 | |
058d88c4 CW |
3234 | vma = i915_gem_object_to_ggtt(obj, &view); |
3235 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
3236 | view.type)) | |
3237 | return -1; | |
3238 | ||
bde13ebd | 3239 | return i915_ggtt_offset(vma); |
121920fa TU |
3240 | } |
3241 | ||
e435d6e5 ML |
3242 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3243 | { | |
3244 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3245 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3246 | |
3247 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3248 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3249 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3250 | } |
3251 | ||
a1b2278e CK |
3252 | /* |
3253 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3254 | */ | |
0583236e | 3255 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3256 | { |
a1b2278e CK |
3257 | struct intel_crtc_scaler_state *scaler_state; |
3258 | int i; | |
3259 | ||
a1b2278e CK |
3260 | scaler_state = &intel_crtc->config->scaler_state; |
3261 | ||
3262 | /* loop through and disable scalers that aren't in use */ | |
3263 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3264 | if (!scaler_state->scalers[i].in_use) |
3265 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3266 | } |
3267 | } | |
3268 | ||
d2196774 VS |
3269 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3270 | unsigned int rotation) | |
3271 | { | |
3272 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3273 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3274 | ||
3275 | /* | |
3276 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3277 | * linear buffers or in number of tiles for tiled buffers. | |
3278 | */ | |
3279 | if (intel_rotation_90_or_270(rotation)) { | |
3280 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
3281 | ||
3282 | stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
3283 | } else { | |
3284 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
3285 | fb->pixel_format); | |
3286 | } | |
3287 | ||
3288 | return stride; | |
3289 | } | |
3290 | ||
6156a456 | 3291 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3292 | { |
6156a456 | 3293 | switch (pixel_format) { |
d161cf7a | 3294 | case DRM_FORMAT_C8: |
c34ce3d1 | 3295 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3296 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3297 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3298 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3299 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3300 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3301 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3302 | /* |
3303 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3304 | * to be already pre-multiplied. We need to add a knob (or a different | |
3305 | * DRM_FORMAT) for user-space to configure that. | |
3306 | */ | |
f75fb42a | 3307 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3308 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3309 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3310 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3311 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3312 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3313 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3314 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3315 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3316 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3317 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3318 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3319 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3320 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3321 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3322 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3323 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3324 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3325 | default: |
4249eeef | 3326 | MISSING_CASE(pixel_format); |
70d21f0e | 3327 | } |
8cfcba41 | 3328 | |
c34ce3d1 | 3329 | return 0; |
6156a456 | 3330 | } |
70d21f0e | 3331 | |
6156a456 CK |
3332 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3333 | { | |
6156a456 | 3334 | switch (fb_modifier) { |
30af77c4 | 3335 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3336 | break; |
30af77c4 | 3337 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3338 | return PLANE_CTL_TILED_X; |
b321803d | 3339 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3340 | return PLANE_CTL_TILED_Y; |
b321803d | 3341 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3342 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3343 | default: |
6156a456 | 3344 | MISSING_CASE(fb_modifier); |
70d21f0e | 3345 | } |
8cfcba41 | 3346 | |
c34ce3d1 | 3347 | return 0; |
6156a456 | 3348 | } |
70d21f0e | 3349 | |
6156a456 CK |
3350 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3351 | { | |
3b7a5119 | 3352 | switch (rotation) { |
31ad61e4 | 3353 | case DRM_ROTATE_0: |
6156a456 | 3354 | break; |
1e8df167 SJ |
3355 | /* |
3356 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3357 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3358 | */ | |
31ad61e4 | 3359 | case DRM_ROTATE_90: |
1e8df167 | 3360 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3361 | case DRM_ROTATE_180: |
c34ce3d1 | 3362 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3363 | case DRM_ROTATE_270: |
1e8df167 | 3364 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3365 | default: |
3366 | MISSING_CASE(rotation); | |
3367 | } | |
3368 | ||
c34ce3d1 | 3369 | return 0; |
6156a456 CK |
3370 | } |
3371 | ||
a8d201af ML |
3372 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3373 | const struct intel_crtc_state *crtc_state, | |
3374 | const struct intel_plane_state *plane_state) | |
6156a456 | 3375 | { |
a8d201af | 3376 | struct drm_device *dev = plane->dev; |
fac5e23e | 3377 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3379 | struct drm_framebuffer *fb = plane_state->base.fb; | |
6156a456 | 3380 | int pipe = intel_crtc->pipe; |
d2196774 | 3381 | u32 plane_ctl; |
a8d201af | 3382 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3383 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3384 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3385 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3386 | int src_x = plane_state->main.x; |
3387 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3388 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3389 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3390 | int dst_x = plane_state->base.dst.x1; | |
3391 | int dst_y = plane_state->base.dst.y1; | |
3392 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3393 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3394 | |
6156a456 CK |
3395 | plane_ctl = PLANE_CTL_ENABLE | |
3396 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3397 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3398 | ||
3399 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3400 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3401 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3402 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3403 | ||
6687c906 VS |
3404 | /* Sizes are 0 based */ |
3405 | src_w--; | |
3406 | src_h--; | |
3407 | dst_w--; | |
3408 | dst_h--; | |
3409 | ||
3410 | intel_crtc->adjusted_x = src_x; | |
3411 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3412 | |
70d21f0e | 3413 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
6687c906 | 3414 | I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); |
ef78ec94 | 3415 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
6687c906 | 3416 | I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); |
6156a456 CK |
3417 | |
3418 | if (scaler_id >= 0) { | |
3419 | uint32_t ps_ctrl = 0; | |
3420 | ||
3421 | WARN_ON(!dst_w || !dst_h); | |
3422 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3423 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3424 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3425 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3426 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3427 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3428 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3429 | } else { | |
3430 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3431 | } | |
3432 | ||
6687c906 VS |
3433 | I915_WRITE(PLANE_SURF(pipe, 0), |
3434 | intel_fb_gtt_offset(fb, rotation) + surf_addr); | |
70d21f0e DL |
3435 | |
3436 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3437 | } | |
3438 | ||
a8d201af ML |
3439 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3440 | struct drm_crtc *crtc) | |
17638cd6 JB |
3441 | { |
3442 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3443 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af | 3444 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3445 | |
a8d201af ML |
3446 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3447 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3448 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3449 | } | |
29b9bde6 | 3450 | |
a8d201af ML |
3451 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3452 | static int | |
3453 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3454 | int x, int y, enum mode_set_atomic state) | |
3455 | { | |
3456 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3457 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3458 | ||
3459 | return -ENODEV; | |
81255565 JB |
3460 | } |
3461 | ||
5a21b665 DV |
3462 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3463 | { | |
3464 | struct intel_crtc *crtc; | |
3465 | ||
91c8a326 | 3466 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3467 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3468 | } | |
3469 | ||
7514747d VS |
3470 | static void intel_update_primary_planes(struct drm_device *dev) |
3471 | { | |
7514747d | 3472 | struct drm_crtc *crtc; |
96a02917 | 3473 | |
70e1e0ec | 3474 | for_each_crtc(dev, crtc) { |
11c22da6 | 3475 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3476 | struct intel_plane_state *plane_state = |
3477 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3478 | |
936e71e3 | 3479 | if (plane_state->base.visible) |
a8d201af ML |
3480 | plane->update_plane(&plane->base, |
3481 | to_intel_crtc_state(crtc->state), | |
3482 | plane_state); | |
73974893 ML |
3483 | } |
3484 | } | |
3485 | ||
3486 | static int | |
3487 | __intel_display_resume(struct drm_device *dev, | |
3488 | struct drm_atomic_state *state) | |
3489 | { | |
3490 | struct drm_crtc_state *crtc_state; | |
3491 | struct drm_crtc *crtc; | |
3492 | int i, ret; | |
11c22da6 | 3493 | |
73974893 ML |
3494 | intel_modeset_setup_hw_state(dev); |
3495 | i915_redisable_vga(dev); | |
3496 | ||
3497 | if (!state) | |
3498 | return 0; | |
3499 | ||
3500 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3501 | /* | |
3502 | * Force recalculation even if we restore | |
3503 | * current state. With fast modeset this may not result | |
3504 | * in a modeset when the state is compatible. | |
3505 | */ | |
3506 | crtc_state->mode_changed = true; | |
96a02917 | 3507 | } |
73974893 ML |
3508 | |
3509 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3510 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3511 | ||
3512 | ret = drm_atomic_commit(state); | |
3513 | ||
3514 | WARN_ON(ret == -EDEADLK); | |
3515 | return ret; | |
96a02917 VS |
3516 | } |
3517 | ||
4ac2ba2f VS |
3518 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3519 | { | |
ae98104b VS |
3520 | return intel_has_gpu_reset(dev_priv) && |
3521 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3522 | } |
3523 | ||
c033666a | 3524 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3525 | { |
73974893 ML |
3526 | struct drm_device *dev = &dev_priv->drm; |
3527 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3528 | struct drm_atomic_state *state; | |
3529 | int ret; | |
3530 | ||
73974893 ML |
3531 | /* |
3532 | * Need mode_config.mutex so that we don't | |
3533 | * trample ongoing ->detect() and whatnot. | |
3534 | */ | |
3535 | mutex_lock(&dev->mode_config.mutex); | |
3536 | drm_modeset_acquire_init(ctx, 0); | |
3537 | while (1) { | |
3538 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3539 | if (ret != -EDEADLK) | |
3540 | break; | |
3541 | ||
3542 | drm_modeset_backoff(ctx); | |
3543 | } | |
3544 | ||
3545 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3546 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3547 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3548 | return; |
3549 | ||
f98ce92f VS |
3550 | /* |
3551 | * Disabling the crtcs gracefully seems nicer. Also the | |
3552 | * g33 docs say we should at least disable all the planes. | |
3553 | */ | |
73974893 ML |
3554 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3555 | if (IS_ERR(state)) { | |
3556 | ret = PTR_ERR(state); | |
3557 | state = NULL; | |
3558 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3559 | goto err; | |
3560 | } | |
3561 | ||
3562 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3563 | if (ret) { | |
3564 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3565 | goto err; | |
3566 | } | |
3567 | ||
3568 | dev_priv->modeset_restore_state = state; | |
3569 | state->acquire_ctx = ctx; | |
3570 | return; | |
3571 | ||
3572 | err: | |
3573 | drm_atomic_state_free(state); | |
7514747d VS |
3574 | } |
3575 | ||
c033666a | 3576 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3577 | { |
73974893 ML |
3578 | struct drm_device *dev = &dev_priv->drm; |
3579 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3580 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3581 | int ret; | |
3582 | ||
5a21b665 DV |
3583 | /* |
3584 | * Flips in the rings will be nuked by the reset, | |
3585 | * so complete all pending flips so that user space | |
3586 | * will get its events and not get stuck. | |
3587 | */ | |
3588 | intel_complete_page_flips(dev_priv); | |
3589 | ||
73974893 ML |
3590 | dev_priv->modeset_restore_state = NULL; |
3591 | ||
7514747d | 3592 | /* reset doesn't touch the display */ |
4ac2ba2f | 3593 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3594 | if (!state) { |
3595 | /* | |
3596 | * Flips in the rings have been nuked by the reset, | |
3597 | * so update the base address of all primary | |
3598 | * planes to the the last fb to make sure we're | |
3599 | * showing the correct fb after a reset. | |
3600 | * | |
3601 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3602 | * CS-based flips (which might get lost in gpu resets) any more. | |
3603 | */ | |
3604 | intel_update_primary_planes(dev); | |
3605 | } else { | |
3606 | ret = __intel_display_resume(dev, state); | |
3607 | if (ret) | |
3608 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3609 | } | |
73974893 ML |
3610 | } else { |
3611 | /* | |
3612 | * The display has been reset as well, | |
3613 | * so need a full re-initialization. | |
3614 | */ | |
3615 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3616 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3617 | |
73974893 | 3618 | intel_modeset_init_hw(dev); |
7514747d | 3619 | |
73974893 ML |
3620 | spin_lock_irq(&dev_priv->irq_lock); |
3621 | if (dev_priv->display.hpd_irq_setup) | |
3622 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3623 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3624 | |
73974893 ML |
3625 | ret = __intel_display_resume(dev, state); |
3626 | if (ret) | |
3627 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3628 | |
73974893 ML |
3629 | intel_hpd_init(dev_priv); |
3630 | } | |
7514747d | 3631 | |
73974893 ML |
3632 | drm_modeset_drop_locks(ctx); |
3633 | drm_modeset_acquire_fini(ctx); | |
3634 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3635 | } |
3636 | ||
7d5e3799 CW |
3637 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3638 | { | |
5a21b665 DV |
3639 | struct drm_device *dev = crtc->dev; |
3640 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3641 | unsigned reset_counter; | |
3642 | bool pending; | |
3643 | ||
3644 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3645 | if (intel_crtc->reset_counter != reset_counter) | |
3646 | return false; | |
3647 | ||
3648 | spin_lock_irq(&dev->event_lock); | |
3649 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3650 | spin_unlock_irq(&dev->event_lock); | |
3651 | ||
3652 | return pending; | |
7d5e3799 CW |
3653 | } |
3654 | ||
bfd16b2a ML |
3655 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3656 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3657 | { |
3658 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3659 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3660 | struct intel_crtc_state *pipe_config = |
3661 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3662 | |
bfd16b2a ML |
3663 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3664 | crtc->base.mode = crtc->base.state->mode; | |
3665 | ||
3666 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3667 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3668 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3669 | |
3670 | /* | |
3671 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3672 | * that in compute_mode_changes we check the native mode (not the pfit | |
3673 | * mode) to see if we can flip rather than do a full mode set. In the | |
3674 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3675 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3676 | * sized surface. | |
e30e8f75 GP |
3677 | */ |
3678 | ||
e30e8f75 | 3679 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3680 | ((pipe_config->pipe_src_w - 1) << 16) | |
3681 | (pipe_config->pipe_src_h - 1)); | |
3682 | ||
3683 | /* on skylake this is done by detaching scalers */ | |
3684 | if (INTEL_INFO(dev)->gen >= 9) { | |
3685 | skl_detach_scalers(crtc); | |
3686 | ||
3687 | if (pipe_config->pch_pfit.enabled) | |
3688 | skylake_pfit_enable(crtc); | |
3689 | } else if (HAS_PCH_SPLIT(dev)) { | |
3690 | if (pipe_config->pch_pfit.enabled) | |
3691 | ironlake_pfit_enable(crtc); | |
3692 | else if (old_crtc_state->pch_pfit.enabled) | |
3693 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3694 | } |
e30e8f75 GP |
3695 | } |
3696 | ||
5e84e1a4 ZW |
3697 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3698 | { | |
3699 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3700 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3701 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3702 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3703 | i915_reg_t reg; |
3704 | u32 temp; | |
5e84e1a4 ZW |
3705 | |
3706 | /* enable normal train */ | |
3707 | reg = FDI_TX_CTL(pipe); | |
3708 | temp = I915_READ(reg); | |
61e499bf | 3709 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3710 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3711 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3712 | } else { |
3713 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3714 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3715 | } |
5e84e1a4 ZW |
3716 | I915_WRITE(reg, temp); |
3717 | ||
3718 | reg = FDI_RX_CTL(pipe); | |
3719 | temp = I915_READ(reg); | |
3720 | if (HAS_PCH_CPT(dev)) { | |
3721 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3722 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3723 | } else { | |
3724 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3725 | temp |= FDI_LINK_TRAIN_NONE; | |
3726 | } | |
3727 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3728 | ||
3729 | /* wait one idle pattern time */ | |
3730 | POSTING_READ(reg); | |
3731 | udelay(1000); | |
357555c0 JB |
3732 | |
3733 | /* IVB wants error correction enabled */ | |
3734 | if (IS_IVYBRIDGE(dev)) | |
3735 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3736 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3737 | } |
3738 | ||
8db9d77b ZW |
3739 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3740 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3741 | { | |
3742 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3743 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3745 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3746 | i915_reg_t reg; |
3747 | u32 temp, tries; | |
8db9d77b | 3748 | |
1c8562f6 | 3749 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3750 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3751 | |
e1a44743 AJ |
3752 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3753 | for train result */ | |
5eddb70b CW |
3754 | reg = FDI_RX_IMR(pipe); |
3755 | temp = I915_READ(reg); | |
e1a44743 AJ |
3756 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3757 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3758 | I915_WRITE(reg, temp); |
3759 | I915_READ(reg); | |
e1a44743 AJ |
3760 | udelay(150); |
3761 | ||
8db9d77b | 3762 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3763 | reg = FDI_TX_CTL(pipe); |
3764 | temp = I915_READ(reg); | |
627eb5a3 | 3765 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3766 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3767 | temp &= ~FDI_LINK_TRAIN_NONE; |
3768 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3769 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3770 | |
5eddb70b CW |
3771 | reg = FDI_RX_CTL(pipe); |
3772 | temp = I915_READ(reg); | |
8db9d77b ZW |
3773 | temp &= ~FDI_LINK_TRAIN_NONE; |
3774 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3775 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3776 | ||
3777 | POSTING_READ(reg); | |
8db9d77b ZW |
3778 | udelay(150); |
3779 | ||
5b2adf89 | 3780 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3781 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3782 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3783 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3784 | |
5eddb70b | 3785 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3786 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3787 | temp = I915_READ(reg); |
8db9d77b ZW |
3788 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3789 | ||
3790 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3791 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3792 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3793 | break; |
3794 | } | |
8db9d77b | 3795 | } |
e1a44743 | 3796 | if (tries == 5) |
5eddb70b | 3797 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3798 | |
3799 | /* Train 2 */ | |
5eddb70b CW |
3800 | reg = FDI_TX_CTL(pipe); |
3801 | temp = I915_READ(reg); | |
8db9d77b ZW |
3802 | temp &= ~FDI_LINK_TRAIN_NONE; |
3803 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3804 | I915_WRITE(reg, temp); |
8db9d77b | 3805 | |
5eddb70b CW |
3806 | reg = FDI_RX_CTL(pipe); |
3807 | temp = I915_READ(reg); | |
8db9d77b ZW |
3808 | temp &= ~FDI_LINK_TRAIN_NONE; |
3809 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3810 | I915_WRITE(reg, temp); |
8db9d77b | 3811 | |
5eddb70b CW |
3812 | POSTING_READ(reg); |
3813 | udelay(150); | |
8db9d77b | 3814 | |
5eddb70b | 3815 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3816 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3817 | temp = I915_READ(reg); |
8db9d77b ZW |
3818 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3819 | ||
3820 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3821 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3822 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3823 | break; | |
3824 | } | |
8db9d77b | 3825 | } |
e1a44743 | 3826 | if (tries == 5) |
5eddb70b | 3827 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3828 | |
3829 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3830 | |
8db9d77b ZW |
3831 | } |
3832 | ||
0206e353 | 3833 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3834 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3835 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3836 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3837 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3838 | }; | |
3839 | ||
3840 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3841 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3842 | { | |
3843 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3844 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3845 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3846 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3847 | i915_reg_t reg; |
3848 | u32 temp, i, retry; | |
8db9d77b | 3849 | |
e1a44743 AJ |
3850 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3851 | for train result */ | |
5eddb70b CW |
3852 | reg = FDI_RX_IMR(pipe); |
3853 | temp = I915_READ(reg); | |
e1a44743 AJ |
3854 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3855 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3856 | I915_WRITE(reg, temp); |
3857 | ||
3858 | POSTING_READ(reg); | |
e1a44743 AJ |
3859 | udelay(150); |
3860 | ||
8db9d77b | 3861 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3862 | reg = FDI_TX_CTL(pipe); |
3863 | temp = I915_READ(reg); | |
627eb5a3 | 3864 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3865 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3866 | temp &= ~FDI_LINK_TRAIN_NONE; |
3867 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3868 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3869 | /* SNB-B */ | |
3870 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3871 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3872 | |
d74cf324 DV |
3873 | I915_WRITE(FDI_RX_MISC(pipe), |
3874 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3875 | ||
5eddb70b CW |
3876 | reg = FDI_RX_CTL(pipe); |
3877 | temp = I915_READ(reg); | |
8db9d77b ZW |
3878 | if (HAS_PCH_CPT(dev)) { |
3879 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3880 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3881 | } else { | |
3882 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3883 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3884 | } | |
5eddb70b CW |
3885 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3886 | ||
3887 | POSTING_READ(reg); | |
8db9d77b ZW |
3888 | udelay(150); |
3889 | ||
0206e353 | 3890 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3891 | reg = FDI_TX_CTL(pipe); |
3892 | temp = I915_READ(reg); | |
8db9d77b ZW |
3893 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3894 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3895 | I915_WRITE(reg, temp); |
3896 | ||
3897 | POSTING_READ(reg); | |
8db9d77b ZW |
3898 | udelay(500); |
3899 | ||
fa37d39e SP |
3900 | for (retry = 0; retry < 5; retry++) { |
3901 | reg = FDI_RX_IIR(pipe); | |
3902 | temp = I915_READ(reg); | |
3903 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3904 | if (temp & FDI_RX_BIT_LOCK) { | |
3905 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3906 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3907 | break; | |
3908 | } | |
3909 | udelay(50); | |
8db9d77b | 3910 | } |
fa37d39e SP |
3911 | if (retry < 5) |
3912 | break; | |
8db9d77b ZW |
3913 | } |
3914 | if (i == 4) | |
5eddb70b | 3915 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3916 | |
3917 | /* Train 2 */ | |
5eddb70b CW |
3918 | reg = FDI_TX_CTL(pipe); |
3919 | temp = I915_READ(reg); | |
8db9d77b ZW |
3920 | temp &= ~FDI_LINK_TRAIN_NONE; |
3921 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3922 | if (IS_GEN6(dev)) { | |
3923 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3924 | /* SNB-B */ | |
3925 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3926 | } | |
5eddb70b | 3927 | I915_WRITE(reg, temp); |
8db9d77b | 3928 | |
5eddb70b CW |
3929 | reg = FDI_RX_CTL(pipe); |
3930 | temp = I915_READ(reg); | |
8db9d77b ZW |
3931 | if (HAS_PCH_CPT(dev)) { |
3932 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3933 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3934 | } else { | |
3935 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3936 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3937 | } | |
5eddb70b CW |
3938 | I915_WRITE(reg, temp); |
3939 | ||
3940 | POSTING_READ(reg); | |
8db9d77b ZW |
3941 | udelay(150); |
3942 | ||
0206e353 | 3943 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3944 | reg = FDI_TX_CTL(pipe); |
3945 | temp = I915_READ(reg); | |
8db9d77b ZW |
3946 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3947 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3948 | I915_WRITE(reg, temp); |
3949 | ||
3950 | POSTING_READ(reg); | |
8db9d77b ZW |
3951 | udelay(500); |
3952 | ||
fa37d39e SP |
3953 | for (retry = 0; retry < 5; retry++) { |
3954 | reg = FDI_RX_IIR(pipe); | |
3955 | temp = I915_READ(reg); | |
3956 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3957 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3958 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3959 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3960 | break; | |
3961 | } | |
3962 | udelay(50); | |
8db9d77b | 3963 | } |
fa37d39e SP |
3964 | if (retry < 5) |
3965 | break; | |
8db9d77b ZW |
3966 | } |
3967 | if (i == 4) | |
5eddb70b | 3968 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3969 | |
3970 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3971 | } | |
3972 | ||
357555c0 JB |
3973 | /* Manual link training for Ivy Bridge A0 parts */ |
3974 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3975 | { | |
3976 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3977 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3979 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3980 | i915_reg_t reg; |
3981 | u32 temp, i, j; | |
357555c0 JB |
3982 | |
3983 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3984 | for train result */ | |
3985 | reg = FDI_RX_IMR(pipe); | |
3986 | temp = I915_READ(reg); | |
3987 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3988 | temp &= ~FDI_RX_BIT_LOCK; | |
3989 | I915_WRITE(reg, temp); | |
3990 | ||
3991 | POSTING_READ(reg); | |
3992 | udelay(150); | |
3993 | ||
01a415fd DV |
3994 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3995 | I915_READ(FDI_RX_IIR(pipe))); | |
3996 | ||
139ccd3f JB |
3997 | /* Try each vswing and preemphasis setting twice before moving on */ |
3998 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3999 | /* disable first in case we need to retry */ | |
4000 | reg = FDI_TX_CTL(pipe); | |
4001 | temp = I915_READ(reg); | |
4002 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4003 | temp &= ~FDI_TX_ENABLE; | |
4004 | I915_WRITE(reg, temp); | |
357555c0 | 4005 | |
139ccd3f JB |
4006 | reg = FDI_RX_CTL(pipe); |
4007 | temp = I915_READ(reg); | |
4008 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4009 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4010 | temp &= ~FDI_RX_ENABLE; | |
4011 | I915_WRITE(reg, temp); | |
357555c0 | 4012 | |
139ccd3f | 4013 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4014 | reg = FDI_TX_CTL(pipe); |
4015 | temp = I915_READ(reg); | |
139ccd3f | 4016 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 4017 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 4018 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4019 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4020 | temp |= snb_b_fdi_train_param[j/2]; |
4021 | temp |= FDI_COMPOSITE_SYNC; | |
4022 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4023 | |
139ccd3f JB |
4024 | I915_WRITE(FDI_RX_MISC(pipe), |
4025 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4026 | |
139ccd3f | 4027 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4028 | temp = I915_READ(reg); |
139ccd3f JB |
4029 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4030 | temp |= FDI_COMPOSITE_SYNC; | |
4031 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4032 | |
139ccd3f JB |
4033 | POSTING_READ(reg); |
4034 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4035 | |
139ccd3f JB |
4036 | for (i = 0; i < 4; i++) { |
4037 | reg = FDI_RX_IIR(pipe); | |
4038 | temp = I915_READ(reg); | |
4039 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4040 | |
139ccd3f JB |
4041 | if (temp & FDI_RX_BIT_LOCK || |
4042 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4043 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4044 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4045 | i); | |
4046 | break; | |
4047 | } | |
4048 | udelay(1); /* should be 0.5us */ | |
4049 | } | |
4050 | if (i == 4) { | |
4051 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4052 | continue; | |
4053 | } | |
357555c0 | 4054 | |
139ccd3f | 4055 | /* Train 2 */ |
357555c0 JB |
4056 | reg = FDI_TX_CTL(pipe); |
4057 | temp = I915_READ(reg); | |
139ccd3f JB |
4058 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4059 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4060 | I915_WRITE(reg, temp); | |
4061 | ||
4062 | reg = FDI_RX_CTL(pipe); | |
4063 | temp = I915_READ(reg); | |
4064 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4065 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4066 | I915_WRITE(reg, temp); |
4067 | ||
4068 | POSTING_READ(reg); | |
139ccd3f | 4069 | udelay(2); /* should be 1.5us */ |
357555c0 | 4070 | |
139ccd3f JB |
4071 | for (i = 0; i < 4; i++) { |
4072 | reg = FDI_RX_IIR(pipe); | |
4073 | temp = I915_READ(reg); | |
4074 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4075 | |
139ccd3f JB |
4076 | if (temp & FDI_RX_SYMBOL_LOCK || |
4077 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4078 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4079 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4080 | i); | |
4081 | goto train_done; | |
4082 | } | |
4083 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4084 | } |
139ccd3f JB |
4085 | if (i == 4) |
4086 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4087 | } |
357555c0 | 4088 | |
139ccd3f | 4089 | train_done: |
357555c0 JB |
4090 | DRM_DEBUG_KMS("FDI train done.\n"); |
4091 | } | |
4092 | ||
88cefb6c | 4093 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4094 | { |
88cefb6c | 4095 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4096 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4097 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4098 | i915_reg_t reg; |
4099 | u32 temp; | |
c64e311e | 4100 | |
c98e9dcf | 4101 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4102 | reg = FDI_RX_CTL(pipe); |
4103 | temp = I915_READ(reg); | |
627eb5a3 | 4104 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4105 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4106 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4107 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4108 | ||
4109 | POSTING_READ(reg); | |
c98e9dcf JB |
4110 | udelay(200); |
4111 | ||
4112 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4113 | temp = I915_READ(reg); |
4114 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4115 | ||
4116 | POSTING_READ(reg); | |
c98e9dcf JB |
4117 | udelay(200); |
4118 | ||
20749730 PZ |
4119 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4120 | reg = FDI_TX_CTL(pipe); | |
4121 | temp = I915_READ(reg); | |
4122 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4123 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4124 | |
20749730 PZ |
4125 | POSTING_READ(reg); |
4126 | udelay(100); | |
6be4a607 | 4127 | } |
0e23b99d JB |
4128 | } |
4129 | ||
88cefb6c DV |
4130 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4131 | { | |
4132 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4133 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4134 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4135 | i915_reg_t reg; |
4136 | u32 temp; | |
88cefb6c DV |
4137 | |
4138 | /* Switch from PCDclk to Rawclk */ | |
4139 | reg = FDI_RX_CTL(pipe); | |
4140 | temp = I915_READ(reg); | |
4141 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4142 | ||
4143 | /* Disable CPU FDI TX PLL */ | |
4144 | reg = FDI_TX_CTL(pipe); | |
4145 | temp = I915_READ(reg); | |
4146 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4147 | ||
4148 | POSTING_READ(reg); | |
4149 | udelay(100); | |
4150 | ||
4151 | reg = FDI_RX_CTL(pipe); | |
4152 | temp = I915_READ(reg); | |
4153 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4154 | ||
4155 | /* Wait for the clocks to turn off. */ | |
4156 | POSTING_READ(reg); | |
4157 | udelay(100); | |
4158 | } | |
4159 | ||
0fc932b8 JB |
4160 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4161 | { | |
4162 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4163 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4164 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4165 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4166 | i915_reg_t reg; |
4167 | u32 temp; | |
0fc932b8 JB |
4168 | |
4169 | /* disable CPU FDI tx and PCH FDI rx */ | |
4170 | reg = FDI_TX_CTL(pipe); | |
4171 | temp = I915_READ(reg); | |
4172 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4173 | POSTING_READ(reg); | |
4174 | ||
4175 | reg = FDI_RX_CTL(pipe); | |
4176 | temp = I915_READ(reg); | |
4177 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4178 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4179 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4180 | ||
4181 | POSTING_READ(reg); | |
4182 | udelay(100); | |
4183 | ||
4184 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 4185 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 4186 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4187 | |
4188 | /* still set train pattern 1 */ | |
4189 | reg = FDI_TX_CTL(pipe); | |
4190 | temp = I915_READ(reg); | |
4191 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4192 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4193 | I915_WRITE(reg, temp); | |
4194 | ||
4195 | reg = FDI_RX_CTL(pipe); | |
4196 | temp = I915_READ(reg); | |
4197 | if (HAS_PCH_CPT(dev)) { | |
4198 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4199 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4200 | } else { | |
4201 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4202 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4203 | } | |
4204 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4205 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4206 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4207 | I915_WRITE(reg, temp); |
4208 | ||
4209 | POSTING_READ(reg); | |
4210 | udelay(100); | |
4211 | } | |
4212 | ||
5dce5b93 CW |
4213 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
4214 | { | |
4215 | struct intel_crtc *crtc; | |
4216 | ||
4217 | /* Note that we don't need to be called with mode_config.lock here | |
4218 | * as our list of CRTC objects is static for the lifetime of the | |
4219 | * device and so cannot disappear as we iterate. Similarly, we can | |
4220 | * happily treat the predicates as racy, atomic checks as userspace | |
4221 | * cannot claim and pin a new fb without at least acquring the | |
4222 | * struct_mutex and so serialising with us. | |
4223 | */ | |
d3fcc808 | 4224 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
4225 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4226 | continue; | |
4227 | ||
5a21b665 | 4228 | if (crtc->flip_work) |
5dce5b93 CW |
4229 | intel_wait_for_vblank(dev, crtc->pipe); |
4230 | ||
4231 | return true; | |
4232 | } | |
4233 | ||
4234 | return false; | |
4235 | } | |
4236 | ||
5a21b665 | 4237 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4238 | { |
4239 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4240 | struct intel_flip_work *work = intel_crtc->flip_work; |
4241 | ||
4242 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4243 | |
4244 | if (work->event) | |
560ce1dc | 4245 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4246 | |
4247 | drm_crtc_vblank_put(&intel_crtc->base); | |
4248 | ||
5a21b665 | 4249 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4250 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4251 | |
4252 | trace_i915_flip_complete(intel_crtc->plane, | |
4253 | work->pending_flip_obj); | |
d6bbafa1 CW |
4254 | } |
4255 | ||
5008e874 | 4256 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4257 | { |
0f91128d | 4258 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4259 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4260 | long ret; |
e6c3a2a6 | 4261 | |
2c10d571 | 4262 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4263 | |
4264 | ret = wait_event_interruptible_timeout( | |
4265 | dev_priv->pending_flip_queue, | |
4266 | !intel_crtc_has_pending_flip(crtc), | |
4267 | 60*HZ); | |
4268 | ||
4269 | if (ret < 0) | |
4270 | return ret; | |
4271 | ||
5a21b665 DV |
4272 | if (ret == 0) { |
4273 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4274 | struct intel_flip_work *work; | |
4275 | ||
4276 | spin_lock_irq(&dev->event_lock); | |
4277 | work = intel_crtc->flip_work; | |
4278 | if (work && !is_mmio_work(work)) { | |
4279 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4280 | page_flip_completed(intel_crtc); | |
4281 | } | |
4282 | spin_unlock_irq(&dev->event_lock); | |
4283 | } | |
5bb61643 | 4284 | |
5008e874 | 4285 | return 0; |
e6c3a2a6 CW |
4286 | } |
4287 | ||
060f02d8 VS |
4288 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
4289 | { | |
4290 | u32 temp; | |
4291 | ||
4292 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4293 | ||
4294 | mutex_lock(&dev_priv->sb_lock); | |
4295 | ||
4296 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4297 | temp |= SBI_SSCCTL_DISABLE; | |
4298 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4299 | ||
4300 | mutex_unlock(&dev_priv->sb_lock); | |
4301 | } | |
4302 | ||
e615efe4 ED |
4303 | /* Program iCLKIP clock to the desired frequency */ |
4304 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4305 | { | |
64b46a06 | 4306 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4307 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4308 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4309 | u32 temp; | |
4310 | ||
060f02d8 | 4311 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4312 | |
64b46a06 VS |
4313 | /* The iCLK virtual clock root frequency is in MHz, |
4314 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4315 | * divisors, it is necessary to divide one by another, so we | |
4316 | * convert the virtual clock precision to KHz here for higher | |
4317 | * precision. | |
4318 | */ | |
4319 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4320 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4321 | u32 iclk_pi_range = 64; | |
64b46a06 | 4322 | u32 desired_divisor; |
e615efe4 | 4323 | |
64b46a06 VS |
4324 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4325 | clock << auxdiv); | |
4326 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4327 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4328 | |
64b46a06 VS |
4329 | /* |
4330 | * Near 20MHz is a corner case which is | |
4331 | * out of range for the 7-bit divisor | |
4332 | */ | |
4333 | if (divsel <= 0x7f) | |
4334 | break; | |
e615efe4 ED |
4335 | } |
4336 | ||
4337 | /* This should not happen with any sane values */ | |
4338 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4339 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4340 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4341 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4342 | ||
4343 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4344 | clock, |
e615efe4 ED |
4345 | auxdiv, |
4346 | divsel, | |
4347 | phasedir, | |
4348 | phaseinc); | |
4349 | ||
060f02d8 VS |
4350 | mutex_lock(&dev_priv->sb_lock); |
4351 | ||
e615efe4 | 4352 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4353 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4354 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4355 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4356 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4357 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4358 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4359 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4360 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4361 | |
4362 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4363 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4364 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4365 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4366 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4367 | |
4368 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4369 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4370 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4371 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4372 | |
060f02d8 VS |
4373 | mutex_unlock(&dev_priv->sb_lock); |
4374 | ||
e615efe4 ED |
4375 | /* Wait for initialization time */ |
4376 | udelay(24); | |
4377 | ||
4378 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4379 | } | |
4380 | ||
8802e5b6 VS |
4381 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4382 | { | |
4383 | u32 divsel, phaseinc, auxdiv; | |
4384 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4385 | u32 iclk_pi_range = 64; | |
4386 | u32 desired_divisor; | |
4387 | u32 temp; | |
4388 | ||
4389 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4390 | return 0; | |
4391 | ||
4392 | mutex_lock(&dev_priv->sb_lock); | |
4393 | ||
4394 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4395 | if (temp & SBI_SSCCTL_DISABLE) { | |
4396 | mutex_unlock(&dev_priv->sb_lock); | |
4397 | return 0; | |
4398 | } | |
4399 | ||
4400 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4401 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4402 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4403 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4404 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4405 | ||
4406 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4407 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4408 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4409 | ||
4410 | mutex_unlock(&dev_priv->sb_lock); | |
4411 | ||
4412 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4413 | ||
4414 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4415 | desired_divisor << auxdiv); | |
4416 | } | |
4417 | ||
275f01b2 DV |
4418 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4419 | enum pipe pch_transcoder) | |
4420 | { | |
4421 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4422 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4423 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4424 | |
4425 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4426 | I915_READ(HTOTAL(cpu_transcoder))); | |
4427 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4428 | I915_READ(HBLANK(cpu_transcoder))); | |
4429 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4430 | I915_READ(HSYNC(cpu_transcoder))); | |
4431 | ||
4432 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4433 | I915_READ(VTOTAL(cpu_transcoder))); | |
4434 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4435 | I915_READ(VBLANK(cpu_transcoder))); | |
4436 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4437 | I915_READ(VSYNC(cpu_transcoder))); | |
4438 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4439 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4440 | } | |
4441 | ||
003632d9 | 4442 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4443 | { |
fac5e23e | 4444 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4445 | uint32_t temp; |
4446 | ||
4447 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4448 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4449 | return; |
4450 | ||
4451 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4452 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4453 | ||
003632d9 ACO |
4454 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4455 | if (enable) | |
4456 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4457 | ||
4458 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4459 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4460 | POSTING_READ(SOUTH_CHICKEN1); | |
4461 | } | |
4462 | ||
4463 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4464 | { | |
4465 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4466 | |
4467 | switch (intel_crtc->pipe) { | |
4468 | case PIPE_A: | |
4469 | break; | |
4470 | case PIPE_B: | |
6e3c9717 | 4471 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4472 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4473 | else |
003632d9 | 4474 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4475 | |
4476 | break; | |
4477 | case PIPE_C: | |
003632d9 | 4478 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4479 | |
4480 | break; | |
4481 | default: | |
4482 | BUG(); | |
4483 | } | |
4484 | } | |
4485 | ||
c48b5305 VS |
4486 | /* Return which DP Port should be selected for Transcoder DP control */ |
4487 | static enum port | |
4488 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4489 | { | |
4490 | struct drm_device *dev = crtc->dev; | |
4491 | struct intel_encoder *encoder; | |
4492 | ||
4493 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4494 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4495 | encoder->type == INTEL_OUTPUT_EDP) |
4496 | return enc_to_dig_port(&encoder->base)->port; | |
4497 | } | |
4498 | ||
4499 | return -1; | |
4500 | } | |
4501 | ||
f67a559d JB |
4502 | /* |
4503 | * Enable PCH resources required for PCH ports: | |
4504 | * - PCH PLLs | |
4505 | * - FDI training & RX/TX | |
4506 | * - update transcoder timings | |
4507 | * - DP transcoding bits | |
4508 | * - transcoder | |
4509 | */ | |
4510 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4511 | { |
4512 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4513 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4515 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4516 | u32 temp; |
2c07245f | 4517 | |
ab9412ba | 4518 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4519 | |
1fbc0d78 DV |
4520 | if (IS_IVYBRIDGE(dev)) |
4521 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4522 | ||
cd986abb DV |
4523 | /* Write the TU size bits before fdi link training, so that error |
4524 | * detection works. */ | |
4525 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4526 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4527 | ||
c98e9dcf | 4528 | /* For PCH output, training FDI link */ |
674cf967 | 4529 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4530 | |
3ad8a208 DV |
4531 | /* We need to program the right clock selection before writing the pixel |
4532 | * mutliplier into the DPLL. */ | |
303b81e0 | 4533 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4534 | u32 sel; |
4b645f14 | 4535 | |
c98e9dcf | 4536 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4537 | temp |= TRANS_DPLL_ENABLE(pipe); |
4538 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4539 | if (intel_crtc->config->shared_dpll == |
4540 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4541 | temp |= sel; |
4542 | else | |
4543 | temp &= ~sel; | |
c98e9dcf | 4544 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4545 | } |
5eddb70b | 4546 | |
3ad8a208 DV |
4547 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4548 | * transcoder, and we actually should do this to not upset any PCH | |
4549 | * transcoder that already use the clock when we share it. | |
4550 | * | |
4551 | * Note that enable_shared_dpll tries to do the right thing, but | |
4552 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4553 | * the right LVDS enable sequence. */ | |
85b3894f | 4554 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4555 | |
d9b6cb56 JB |
4556 | /* set transcoder timing, panel must allow it */ |
4557 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4558 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4559 | |
303b81e0 | 4560 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4561 | |
c98e9dcf | 4562 | /* For PCH DP, enable TRANS_DP_CTL */ |
37a5650b | 4563 | if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) { |
9c4edaee VS |
4564 | const struct drm_display_mode *adjusted_mode = |
4565 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4566 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4567 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4568 | temp = I915_READ(reg); |
4569 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4570 | TRANS_DP_SYNC_MASK | |
4571 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4572 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4573 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4574 | |
9c4edaee | 4575 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4576 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4577 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4578 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4579 | |
4580 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4581 | case PORT_B: |
5eddb70b | 4582 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4583 | break; |
c48b5305 | 4584 | case PORT_C: |
5eddb70b | 4585 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4586 | break; |
c48b5305 | 4587 | case PORT_D: |
5eddb70b | 4588 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4589 | break; |
4590 | default: | |
e95d41e1 | 4591 | BUG(); |
32f9d658 | 4592 | } |
2c07245f | 4593 | |
5eddb70b | 4594 | I915_WRITE(reg, temp); |
6be4a607 | 4595 | } |
b52eb4dc | 4596 | |
b8a4f404 | 4597 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4598 | } |
4599 | ||
1507e5bd PZ |
4600 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4601 | { | |
4602 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4603 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4605 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4606 | |
ab9412ba | 4607 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4608 | |
8c52b5e8 | 4609 | lpt_program_iclkip(crtc); |
1507e5bd | 4610 | |
0540e488 | 4611 | /* Set transcoder timing. */ |
275f01b2 | 4612 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4613 | |
937bb610 | 4614 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4615 | } |
4616 | ||
a1520318 | 4617 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4618 | { |
fac5e23e | 4619 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4620 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4621 | u32 temp; |
4622 | ||
4623 | temp = I915_READ(dslreg); | |
4624 | udelay(500); | |
4625 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4626 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4627 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4628 | } |
4629 | } | |
4630 | ||
86adf9d7 ML |
4631 | static int |
4632 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4633 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4634 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4635 | { |
86adf9d7 ML |
4636 | struct intel_crtc_scaler_state *scaler_state = |
4637 | &crtc_state->scaler_state; | |
4638 | struct intel_crtc *intel_crtc = | |
4639 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4640 | int need_scaling; |
6156a456 CK |
4641 | |
4642 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4643 | (src_h != dst_w || src_w != dst_h): | |
4644 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4645 | |
4646 | /* | |
4647 | * if plane is being disabled or scaler is no more required or force detach | |
4648 | * - free scaler binded to this plane/crtc | |
4649 | * - in order to do this, update crtc->scaler_usage | |
4650 | * | |
4651 | * Here scaler state in crtc_state is set free so that | |
4652 | * scaler can be assigned to other user. Actual register | |
4653 | * update to free the scaler is done in plane/panel-fit programming. | |
4654 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4655 | */ | |
86adf9d7 | 4656 | if (force_detach || !need_scaling) { |
a1b2278e | 4657 | if (*scaler_id >= 0) { |
86adf9d7 | 4658 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4659 | scaler_state->scalers[*scaler_id].in_use = 0; |
4660 | ||
86adf9d7 ML |
4661 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4662 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4663 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4664 | scaler_state->scaler_users); |
4665 | *scaler_id = -1; | |
4666 | } | |
4667 | return 0; | |
4668 | } | |
4669 | ||
4670 | /* range checks */ | |
4671 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4672 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4673 | ||
4674 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4675 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4676 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4677 | "size is out of scaler range\n", |
86adf9d7 | 4678 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4679 | return -EINVAL; |
4680 | } | |
4681 | ||
86adf9d7 ML |
4682 | /* mark this plane as a scaler user in crtc_state */ |
4683 | scaler_state->scaler_users |= (1 << scaler_user); | |
4684 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4685 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4686 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4687 | scaler_state->scaler_users); | |
4688 | ||
4689 | return 0; | |
4690 | } | |
4691 | ||
4692 | /** | |
4693 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4694 | * | |
4695 | * @state: crtc's scaler state | |
86adf9d7 ML |
4696 | * |
4697 | * Return | |
4698 | * 0 - scaler_usage updated successfully | |
4699 | * error - requested scaling cannot be supported or other error condition | |
4700 | */ | |
e435d6e5 | 4701 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4702 | { |
4703 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4704 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4705 | |
78108b7c VS |
4706 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4707 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4708 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4709 | |
e435d6e5 | 4710 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4711 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4712 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4713 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4714 | } |
4715 | ||
4716 | /** | |
4717 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4718 | * | |
4719 | * @state: crtc's scaler state | |
86adf9d7 ML |
4720 | * @plane_state: atomic plane state to update |
4721 | * | |
4722 | * Return | |
4723 | * 0 - scaler_usage updated successfully | |
4724 | * error - requested scaling cannot be supported or other error condition | |
4725 | */ | |
da20eabd ML |
4726 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4727 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4728 | { |
4729 | ||
4730 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4731 | struct intel_plane *intel_plane = |
4732 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4733 | struct drm_framebuffer *fb = plane_state->base.fb; |
4734 | int ret; | |
4735 | ||
936e71e3 | 4736 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4737 | |
72660ce0 VS |
4738 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4739 | intel_plane->base.base.id, intel_plane->base.name, | |
4740 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4741 | |
4742 | ret = skl_update_scaler(crtc_state, force_detach, | |
4743 | drm_plane_index(&intel_plane->base), | |
4744 | &plane_state->scaler_id, | |
4745 | plane_state->base.rotation, | |
936e71e3 VS |
4746 | drm_rect_width(&plane_state->base.src) >> 16, |
4747 | drm_rect_height(&plane_state->base.src) >> 16, | |
4748 | drm_rect_width(&plane_state->base.dst), | |
4749 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4750 | |
4751 | if (ret || plane_state->scaler_id < 0) | |
4752 | return ret; | |
4753 | ||
a1b2278e | 4754 | /* check colorkey */ |
818ed961 | 4755 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4756 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4757 | intel_plane->base.base.id, | |
4758 | intel_plane->base.name); | |
a1b2278e CK |
4759 | return -EINVAL; |
4760 | } | |
4761 | ||
4762 | /* Check src format */ | |
86adf9d7 ML |
4763 | switch (fb->pixel_format) { |
4764 | case DRM_FORMAT_RGB565: | |
4765 | case DRM_FORMAT_XBGR8888: | |
4766 | case DRM_FORMAT_XRGB8888: | |
4767 | case DRM_FORMAT_ABGR8888: | |
4768 | case DRM_FORMAT_ARGB8888: | |
4769 | case DRM_FORMAT_XRGB2101010: | |
4770 | case DRM_FORMAT_XBGR2101010: | |
4771 | case DRM_FORMAT_YUYV: | |
4772 | case DRM_FORMAT_YVYU: | |
4773 | case DRM_FORMAT_UYVY: | |
4774 | case DRM_FORMAT_VYUY: | |
4775 | break; | |
4776 | default: | |
72660ce0 VS |
4777 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4778 | intel_plane->base.base.id, intel_plane->base.name, | |
4779 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4780 | return -EINVAL; |
a1b2278e CK |
4781 | } |
4782 | ||
a1b2278e CK |
4783 | return 0; |
4784 | } | |
4785 | ||
e435d6e5 ML |
4786 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4787 | { | |
4788 | int i; | |
4789 | ||
4790 | for (i = 0; i < crtc->num_scalers; i++) | |
4791 | skl_detach_scaler(crtc, i); | |
4792 | } | |
4793 | ||
4794 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4795 | { |
4796 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4797 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4798 | int pipe = crtc->pipe; |
a1b2278e CK |
4799 | struct intel_crtc_scaler_state *scaler_state = |
4800 | &crtc->config->scaler_state; | |
4801 | ||
4802 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4803 | ||
6e3c9717 | 4804 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4805 | int id; |
4806 | ||
4807 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4808 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4809 | return; | |
4810 | } | |
4811 | ||
4812 | id = scaler_state->scaler_id; | |
4813 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4814 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4815 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4816 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4817 | ||
4818 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4819 | } |
4820 | } | |
4821 | ||
b074cec8 JB |
4822 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4823 | { | |
4824 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4825 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4826 | int pipe = crtc->pipe; |
4827 | ||
6e3c9717 | 4828 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4829 | /* Force use of hard-coded filter coefficients |
4830 | * as some pre-programmed values are broken, | |
4831 | * e.g. x201. | |
4832 | */ | |
4833 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4834 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4835 | PF_PIPE_SEL_IVB(pipe)); | |
4836 | else | |
4837 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4838 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4839 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4840 | } |
4841 | } | |
4842 | ||
20bc8673 | 4843 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4844 | { |
cea165c3 | 4845 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4846 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4847 | |
6e3c9717 | 4848 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4849 | return; |
4850 | ||
307e4498 ML |
4851 | /* |
4852 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4853 | * This function is called from post_plane_update, which is run after | |
4854 | * a vblank wait. | |
4855 | */ | |
cea165c3 | 4856 | |
d77e4531 | 4857 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4858 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4859 | mutex_lock(&dev_priv->rps.hw_lock); |
4860 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4861 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4862 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4863 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4864 | * mailbox." Moreover, the mailbox may return a bogus state, |
4865 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4866 | */ |
4867 | } else { | |
4868 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4869 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4870 | * is essentially intel_wait_for_vblank. If we don't have this | |
4871 | * and don't wait for vblanks until the end of crtc_enable, then | |
4872 | * the HW state readout code will complain that the expected | |
4873 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4874 | if (intel_wait_for_register(dev_priv, |
4875 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4876 | 50)) | |
2a114cc1 BW |
4877 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4878 | } | |
d77e4531 PZ |
4879 | } |
4880 | ||
20bc8673 | 4881 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4882 | { |
4883 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4884 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4885 | |
6e3c9717 | 4886 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4887 | return; |
4888 | ||
4889 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4890 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4891 | mutex_lock(&dev_priv->rps.hw_lock); |
4892 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4893 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4894 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4895 | if (intel_wait_for_register(dev_priv, |
4896 | IPS_CTL, IPS_ENABLE, 0, | |
4897 | 42)) | |
23d0b130 | 4898 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4899 | } else { |
2a114cc1 | 4900 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4901 | POSTING_READ(IPS_CTL); |
4902 | } | |
d77e4531 PZ |
4903 | |
4904 | /* We need to wait for a vblank before we can disable the plane. */ | |
4905 | intel_wait_for_vblank(dev, crtc->pipe); | |
4906 | } | |
4907 | ||
7cac945f | 4908 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4909 | { |
7cac945f | 4910 | if (intel_crtc->overlay) { |
d3eedb1a | 4911 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4912 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4913 | |
4914 | mutex_lock(&dev->struct_mutex); | |
4915 | dev_priv->mm.interruptible = false; | |
4916 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4917 | dev_priv->mm.interruptible = true; | |
4918 | mutex_unlock(&dev->struct_mutex); | |
4919 | } | |
4920 | ||
4921 | /* Let userspace switch the overlay on again. In most cases userspace | |
4922 | * has to recompute where to put it anyway. | |
4923 | */ | |
4924 | } | |
4925 | ||
87d4300a ML |
4926 | /** |
4927 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4928 | * @crtc: the CRTC whose primary plane was just enabled | |
4929 | * | |
4930 | * Performs potentially sleeping operations that must be done after the primary | |
4931 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4932 | * called due to an explicit primary plane update, or due to an implicit | |
4933 | * re-enable that is caused when a sprite plane is updated to no longer | |
4934 | * completely hide the primary plane. | |
4935 | */ | |
4936 | static void | |
4937 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4938 | { |
4939 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4940 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4942 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4943 | |
87d4300a ML |
4944 | /* |
4945 | * FIXME IPS should be fine as long as one plane is | |
4946 | * enabled, but in practice it seems to have problems | |
4947 | * when going from primary only to sprite only and vice | |
4948 | * versa. | |
4949 | */ | |
a5c4d7bc VS |
4950 | hsw_enable_ips(intel_crtc); |
4951 | ||
f99d7069 | 4952 | /* |
87d4300a ML |
4953 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4954 | * So don't enable underrun reporting before at least some planes | |
4955 | * are enabled. | |
4956 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4957 | * but leave the pipe running. | |
f99d7069 | 4958 | */ |
87d4300a ML |
4959 | if (IS_GEN2(dev)) |
4960 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4961 | ||
aca7b684 VS |
4962 | /* Underruns don't always raise interrupts, so check manually. */ |
4963 | intel_check_cpu_fifo_underruns(dev_priv); | |
4964 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4965 | } |
4966 | ||
2622a081 | 4967 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4968 | static void |
4969 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4970 | { |
4971 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4972 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4974 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4975 | |
87d4300a ML |
4976 | /* |
4977 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4978 | * So diasble underrun reporting before all the planes get disabled. | |
4979 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4980 | * but leave the pipe running. | |
4981 | */ | |
4982 | if (IS_GEN2(dev)) | |
4983 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4984 | |
2622a081 VS |
4985 | /* |
4986 | * FIXME IPS should be fine as long as one plane is | |
4987 | * enabled, but in practice it seems to have problems | |
4988 | * when going from primary only to sprite only and vice | |
4989 | * versa. | |
4990 | */ | |
4991 | hsw_disable_ips(intel_crtc); | |
4992 | } | |
4993 | ||
4994 | /* FIXME get rid of this and use pre_plane_update */ | |
4995 | static void | |
4996 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4997 | { | |
4998 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4999 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5000 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5001 | int pipe = intel_crtc->pipe; | |
5002 | ||
5003 | intel_pre_disable_primary(crtc); | |
5004 | ||
87d4300a ML |
5005 | /* |
5006 | * Vblank time updates from the shadow to live plane control register | |
5007 | * are blocked if the memory self-refresh mode is active at that | |
5008 | * moment. So to make sure the plane gets truly disabled, disable | |
5009 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5010 | * will be checked/applied by the HW only at the next frame start | |
5011 | * event which is after the vblank start event, so we need to have a | |
5012 | * wait-for-vblank between disabling the plane and the pipe. | |
5013 | */ | |
262cd2e1 | 5014 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 5015 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
5016 | dev_priv->wm.vlv.cxsr = false; |
5017 | intel_wait_for_vblank(dev, pipe); | |
5018 | } | |
87d4300a ML |
5019 | } |
5020 | ||
5a21b665 DV |
5021 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5022 | { | |
5023 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5024 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5025 | struct intel_crtc_state *pipe_config = | |
5026 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5027 | struct drm_plane *primary = crtc->base.primary; |
5028 | struct drm_plane_state *old_pri_state = | |
5029 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5030 | ||
5748b6a1 | 5031 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
5032 | |
5033 | crtc->wm.cxsr_allowed = true; | |
5034 | ||
5035 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
5036 | intel_update_watermarks(&crtc->base); | |
5037 | ||
5038 | if (old_pri_state) { | |
5039 | struct intel_plane_state *primary_state = | |
5040 | to_intel_plane_state(primary->state); | |
5041 | struct intel_plane_state *old_primary_state = | |
5042 | to_intel_plane_state(old_pri_state); | |
5043 | ||
5044 | intel_fbc_post_update(crtc); | |
5045 | ||
936e71e3 | 5046 | if (primary_state->base.visible && |
5a21b665 | 5047 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5048 | !old_primary_state->base.visible)) |
5a21b665 DV |
5049 | intel_post_enable_primary(&crtc->base); |
5050 | } | |
5051 | } | |
5052 | ||
5c74cd73 | 5053 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5054 | { |
5c74cd73 | 5055 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5056 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5057 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5058 | struct intel_crtc_state *pipe_config = |
5059 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5060 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5061 | struct drm_plane *primary = crtc->base.primary; | |
5062 | struct drm_plane_state *old_pri_state = | |
5063 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5064 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 5065 | |
5c74cd73 ML |
5066 | if (old_pri_state) { |
5067 | struct intel_plane_state *primary_state = | |
5068 | to_intel_plane_state(primary->state); | |
5069 | struct intel_plane_state *old_primary_state = | |
5070 | to_intel_plane_state(old_pri_state); | |
5071 | ||
faf68d92 | 5072 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5073 | |
936e71e3 VS |
5074 | if (old_primary_state->base.visible && |
5075 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5076 | intel_pre_disable_primary(&crtc->base); |
5077 | } | |
852eb00d | 5078 | |
a4015f9a | 5079 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
852eb00d | 5080 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 5081 | |
2622a081 VS |
5082 | /* |
5083 | * Vblank time updates from the shadow to live plane control register | |
5084 | * are blocked if the memory self-refresh mode is active at that | |
5085 | * moment. So to make sure the plane gets truly disabled, disable | |
5086 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5087 | * will be checked/applied by the HW only at the next frame start | |
5088 | * event which is after the vblank start event, so we need to have a | |
5089 | * wait-for-vblank between disabling the plane and the pipe. | |
5090 | */ | |
5091 | if (old_crtc_state->base.active) { | |
2dfd178d | 5092 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
5093 | dev_priv->wm.vlv.cxsr = false; |
5094 | intel_wait_for_vblank(dev, crtc->pipe); | |
5095 | } | |
852eb00d | 5096 | } |
92826fcd | 5097 | |
ed4a6a7c MR |
5098 | /* |
5099 | * IVB workaround: must disable low power watermarks for at least | |
5100 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5101 | * when scaling is disabled. | |
5102 | * | |
5103 | * WaCxSRDisabledForSpriteScaling:ivb | |
5104 | */ | |
5105 | if (pipe_config->disable_lp_wm) { | |
5106 | ilk_disable_lp_wm(dev); | |
5107 | intel_wait_for_vblank(dev, crtc->pipe); | |
5108 | } | |
5109 | ||
5110 | /* | |
5111 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5112 | * watermark programming here. | |
5113 | */ | |
5114 | if (needs_modeset(&pipe_config->base)) | |
5115 | return; | |
5116 | ||
5117 | /* | |
5118 | * For platforms that support atomic watermarks, program the | |
5119 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5120 | * will be the intermediate values that are safe for both pre- and | |
5121 | * post- vblank; when vblank happens, the 'active' values will be set | |
5122 | * to the final 'target' values and we'll do this again to get the | |
5123 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5124 | * will be the final target values which will get automatically latched | |
5125 | * at vblank time; no further programming will be necessary. | |
5126 | * | |
5127 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5128 | * we'll continue to update watermarks the old way, if flags tell | |
5129 | * us to. | |
5130 | */ | |
5131 | if (dev_priv->display.initial_watermarks != NULL) | |
5132 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 5133 | else if (pipe_config->update_wm_pre) |
92826fcd | 5134 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
5135 | } |
5136 | ||
d032ffa0 | 5137 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5138 | { |
5139 | struct drm_device *dev = crtc->dev; | |
5140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5141 | struct drm_plane *p; |
87d4300a ML |
5142 | int pipe = intel_crtc->pipe; |
5143 | ||
7cac945f | 5144 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5145 | |
d032ffa0 ML |
5146 | drm_for_each_plane_mask(p, dev, plane_mask) |
5147 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5148 | |
f99d7069 DV |
5149 | /* |
5150 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5151 | * to compute the mask of flip planes precisely. For the time being | |
5152 | * consider this a flip to a NULL plane. | |
5153 | */ | |
5748b6a1 | 5154 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5155 | } |
5156 | ||
f67a559d JB |
5157 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
5158 | { | |
5159 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5160 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d | 5161 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5162 | struct intel_encoder *encoder; |
f67a559d | 5163 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
5164 | struct intel_crtc_state *pipe_config = |
5165 | to_intel_crtc_state(crtc->state); | |
f67a559d | 5166 | |
53d9f4e9 | 5167 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5168 | return; |
5169 | ||
b2c0593a VS |
5170 | /* |
5171 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5172 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5173 | * | |
5174 | * On ILK we get an occasional spurious CPU pipe underruns | |
5175 | * between eDP port A enable and vdd enable. Also PCH port | |
5176 | * enable seems to result in the occasional CPU pipe underrun. | |
5177 | * | |
5178 | * Spurious PCH underruns also occur during PCH enabling. | |
5179 | */ | |
5180 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5181 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5182 | if (intel_crtc->config->has_pch_encoder) |
5183 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5184 | ||
6e3c9717 | 5185 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5186 | intel_prepare_shared_dpll(intel_crtc); |
5187 | ||
37a5650b | 5188 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5189 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5190 | |
5191 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5192 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5193 | |
6e3c9717 | 5194 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5195 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5196 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5197 | } |
5198 | ||
5199 | ironlake_set_pipeconf(crtc); | |
5200 | ||
f67a559d | 5201 | intel_crtc->active = true; |
8664281b | 5202 | |
f6736a1a | 5203 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
5204 | if (encoder->pre_enable) |
5205 | encoder->pre_enable(encoder); | |
f67a559d | 5206 | |
6e3c9717 | 5207 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5208 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5209 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5210 | * enabling. */ | |
88cefb6c | 5211 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5212 | } else { |
5213 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5214 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5215 | } | |
f67a559d | 5216 | |
b074cec8 | 5217 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5218 | |
9c54c0dd JB |
5219 | /* |
5220 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5221 | * clocks enabled | |
5222 | */ | |
b95c5321 | 5223 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5224 | |
1d5bf5d9 ID |
5225 | if (dev_priv->display.initial_watermarks != NULL) |
5226 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 5227 | intel_enable_pipe(intel_crtc); |
f67a559d | 5228 | |
6e3c9717 | 5229 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5230 | ironlake_pch_enable(crtc); |
c98e9dcf | 5231 | |
f9b61ff6 DV |
5232 | assert_vblank_disabled(crtc); |
5233 | drm_crtc_vblank_on(crtc); | |
5234 | ||
fa5c73b1 DV |
5235 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5236 | encoder->enable(encoder); | |
61b77ddd DV |
5237 | |
5238 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 5239 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5240 | |
5241 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5242 | if (intel_crtc->config->has_pch_encoder) | |
5243 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 5244 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5245 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5246 | } |
5247 | ||
42db64ef PZ |
5248 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5249 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5250 | { | |
f5adf94e | 5251 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5252 | } |
5253 | ||
4f771f10 PZ |
5254 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
5255 | { | |
5256 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5257 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 PZ |
5258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5259 | struct intel_encoder *encoder; | |
99d736a2 | 5260 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5261 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
5262 | struct intel_crtc_state *pipe_config = |
5263 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 5264 | |
53d9f4e9 | 5265 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5266 | return; |
5267 | ||
81b088ca VS |
5268 | if (intel_crtc->config->has_pch_encoder) |
5269 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5270 | false); | |
5271 | ||
95a7a2ae ID |
5272 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5273 | if (encoder->pre_pll_enable) | |
5274 | encoder->pre_pll_enable(encoder); | |
5275 | ||
8106ddbd | 5276 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5277 | intel_enable_shared_dpll(intel_crtc); |
5278 | ||
37a5650b | 5279 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5280 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5281 | |
d7edc4e5 | 5282 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5283 | intel_set_pipe_timings(intel_crtc); |
5284 | ||
bc58be60 | 5285 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5286 | |
4d1de975 JN |
5287 | if (cpu_transcoder != TRANSCODER_EDP && |
5288 | !transcoder_is_dsi(cpu_transcoder)) { | |
5289 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5290 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5291 | } |
5292 | ||
6e3c9717 | 5293 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5294 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5295 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5296 | } |
5297 | ||
d7edc4e5 | 5298 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5299 | haswell_set_pipeconf(crtc); |
5300 | ||
391bf048 | 5301 | haswell_set_pipemisc(crtc); |
229fca97 | 5302 | |
b95c5321 | 5303 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5304 | |
4f771f10 | 5305 | intel_crtc->active = true; |
8664281b | 5306 | |
6b698516 DV |
5307 | if (intel_crtc->config->has_pch_encoder) |
5308 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5309 | else | |
5310 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5311 | ||
7d4aefd0 | 5312 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5313 | if (encoder->pre_enable) |
5314 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5315 | } |
4f771f10 | 5316 | |
d2d65408 | 5317 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5318 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5319 | |
d7edc4e5 | 5320 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5321 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5322 | |
1c132b44 | 5323 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5324 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5325 | else |
1c132b44 | 5326 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5327 | |
5328 | /* | |
5329 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5330 | * clocks enabled | |
5331 | */ | |
b95c5321 | 5332 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5333 | |
1f544388 | 5334 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5335 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5336 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5337 | |
1d5bf5d9 ID |
5338 | if (dev_priv->display.initial_watermarks != NULL) |
5339 | dev_priv->display.initial_watermarks(pipe_config); | |
5340 | else | |
5341 | intel_update_watermarks(crtc); | |
4d1de975 JN |
5342 | |
5343 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5344 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5345 | intel_enable_pipe(intel_crtc); |
42db64ef | 5346 | |
6e3c9717 | 5347 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5348 | lpt_pch_enable(crtc); |
4f771f10 | 5349 | |
a65347ba | 5350 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5351 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5352 | ||
f9b61ff6 DV |
5353 | assert_vblank_disabled(crtc); |
5354 | drm_crtc_vblank_on(crtc); | |
5355 | ||
8807e55b | 5356 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5357 | encoder->enable(encoder); |
8807e55b JN |
5358 | intel_opregion_notify_encoder(encoder, true); |
5359 | } | |
4f771f10 | 5360 | |
6b698516 DV |
5361 | if (intel_crtc->config->has_pch_encoder) { |
5362 | intel_wait_for_vblank(dev, pipe); | |
5363 | intel_wait_for_vblank(dev, pipe); | |
5364 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5365 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5366 | true); | |
6b698516 | 5367 | } |
d2d65408 | 5368 | |
e4916946 PZ |
5369 | /* If we change the relative order between pipe/planes enabling, we need |
5370 | * to change the workaround. */ | |
99d736a2 ML |
5371 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5372 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5373 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5374 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5375 | } | |
4f771f10 PZ |
5376 | } |
5377 | ||
bfd16b2a | 5378 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5379 | { |
5380 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5381 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5382 | int pipe = crtc->pipe; |
5383 | ||
5384 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5385 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5386 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5387 | I915_WRITE(PF_CTL(pipe), 0); |
5388 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5389 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5390 | } | |
5391 | } | |
5392 | ||
6be4a607 JB |
5393 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5394 | { | |
5395 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5396 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 | 5397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5398 | struct intel_encoder *encoder; |
6be4a607 | 5399 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5400 | |
b2c0593a VS |
5401 | /* |
5402 | * Sometimes spurious CPU pipe underruns happen when the | |
5403 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5404 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5405 | */ | |
5406 | if (intel_crtc->config->has_pch_encoder) { | |
5407 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5408 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5409 | } |
37ca8d4c | 5410 | |
ea9d758d DV |
5411 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5412 | encoder->disable(encoder); | |
5413 | ||
f9b61ff6 DV |
5414 | drm_crtc_vblank_off(crtc); |
5415 | assert_vblank_disabled(crtc); | |
5416 | ||
575f7ab7 | 5417 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5418 | |
bfd16b2a | 5419 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5420 | |
b2c0593a | 5421 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5422 | ironlake_fdi_disable(crtc); |
5423 | ||
bf49ec8c DV |
5424 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5425 | if (encoder->post_disable) | |
5426 | encoder->post_disable(encoder); | |
2c07245f | 5427 | |
6e3c9717 | 5428 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5429 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5430 | |
d925c59a | 5431 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5432 | i915_reg_t reg; |
5433 | u32 temp; | |
5434 | ||
d925c59a DV |
5435 | /* disable TRANS_DP_CTL */ |
5436 | reg = TRANS_DP_CTL(pipe); | |
5437 | temp = I915_READ(reg); | |
5438 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5439 | TRANS_DP_PORT_SEL_MASK); | |
5440 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5441 | I915_WRITE(reg, temp); | |
5442 | ||
5443 | /* disable DPLL_SEL */ | |
5444 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5445 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5446 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5447 | } |
e3421a18 | 5448 | |
d925c59a DV |
5449 | ironlake_fdi_pll_disable(intel_crtc); |
5450 | } | |
81b088ca | 5451 | |
b2c0593a | 5452 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5453 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5454 | } |
1b3c7a47 | 5455 | |
4f771f10 | 5456 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5457 | { |
4f771f10 | 5458 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5459 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5461 | struct intel_encoder *encoder; |
6e3c9717 | 5462 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5463 | |
d2d65408 VS |
5464 | if (intel_crtc->config->has_pch_encoder) |
5465 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5466 | false); | |
5467 | ||
8807e55b JN |
5468 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5469 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5470 | encoder->disable(encoder); |
8807e55b | 5471 | } |
4f771f10 | 5472 | |
f9b61ff6 DV |
5473 | drm_crtc_vblank_off(crtc); |
5474 | assert_vblank_disabled(crtc); | |
5475 | ||
4d1de975 | 5476 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5477 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5478 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5479 | |
6e3c9717 | 5480 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5481 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5482 | ||
d7edc4e5 | 5483 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5484 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5485 | |
1c132b44 | 5486 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5487 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5488 | else |
bfd16b2a | 5489 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5490 | |
d7edc4e5 | 5491 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5492 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5493 | |
97b040aa ID |
5494 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5495 | if (encoder->post_disable) | |
5496 | encoder->post_disable(encoder); | |
81b088ca | 5497 | |
92966a37 VS |
5498 | if (intel_crtc->config->has_pch_encoder) { |
5499 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5500 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5501 | intel_ddi_fdi_disable(crtc); |
5502 | ||
81b088ca VS |
5503 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5504 | true); | |
92966a37 | 5505 | } |
4f771f10 PZ |
5506 | } |
5507 | ||
2dd24552 JB |
5508 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5509 | { | |
5510 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5511 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5512 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5513 | |
681a8504 | 5514 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5515 | return; |
5516 | ||
2dd24552 | 5517 | /* |
c0b03411 DV |
5518 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5519 | * according to register description and PRM. | |
2dd24552 | 5520 | */ |
c0b03411 DV |
5521 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5522 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5523 | |
b074cec8 JB |
5524 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5525 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5526 | |
5527 | /* Border color in case we don't scale up to the full screen. Black by | |
5528 | * default, change to something else for debugging. */ | |
5529 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5530 | } |
5531 | ||
d05410f9 DA |
5532 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5533 | { | |
5534 | switch (port) { | |
5535 | case PORT_A: | |
6331a704 | 5536 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5537 | case PORT_B: |
6331a704 | 5538 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5539 | case PORT_C: |
6331a704 | 5540 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5541 | case PORT_D: |
6331a704 | 5542 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5543 | case PORT_E: |
6331a704 | 5544 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5545 | default: |
b9fec167 | 5546 | MISSING_CASE(port); |
d05410f9 DA |
5547 | return POWER_DOMAIN_PORT_OTHER; |
5548 | } | |
5549 | } | |
5550 | ||
25f78f58 VS |
5551 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5552 | { | |
5553 | switch (port) { | |
5554 | case PORT_A: | |
5555 | return POWER_DOMAIN_AUX_A; | |
5556 | case PORT_B: | |
5557 | return POWER_DOMAIN_AUX_B; | |
5558 | case PORT_C: | |
5559 | return POWER_DOMAIN_AUX_C; | |
5560 | case PORT_D: | |
5561 | return POWER_DOMAIN_AUX_D; | |
5562 | case PORT_E: | |
5563 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5564 | return POWER_DOMAIN_AUX_D; | |
5565 | default: | |
b9fec167 | 5566 | MISSING_CASE(port); |
25f78f58 VS |
5567 | return POWER_DOMAIN_AUX_A; |
5568 | } | |
5569 | } | |
5570 | ||
319be8ae ID |
5571 | enum intel_display_power_domain |
5572 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5573 | { | |
5574 | struct drm_device *dev = intel_encoder->base.dev; | |
5575 | struct intel_digital_port *intel_dig_port; | |
5576 | ||
5577 | switch (intel_encoder->type) { | |
5578 | case INTEL_OUTPUT_UNKNOWN: | |
5579 | /* Only DDI platforms should ever use this output type */ | |
5580 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
cca0502b | 5581 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5582 | case INTEL_OUTPUT_HDMI: |
5583 | case INTEL_OUTPUT_EDP: | |
5584 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5585 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5586 | case INTEL_OUTPUT_DP_MST: |
5587 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5588 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5589 | case INTEL_OUTPUT_ANALOG: |
5590 | return POWER_DOMAIN_PORT_CRT; | |
5591 | case INTEL_OUTPUT_DSI: | |
5592 | return POWER_DOMAIN_PORT_DSI; | |
5593 | default: | |
5594 | return POWER_DOMAIN_PORT_OTHER; | |
5595 | } | |
5596 | } | |
5597 | ||
25f78f58 VS |
5598 | enum intel_display_power_domain |
5599 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5600 | { | |
5601 | struct drm_device *dev = intel_encoder->base.dev; | |
5602 | struct intel_digital_port *intel_dig_port; | |
5603 | ||
5604 | switch (intel_encoder->type) { | |
5605 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5606 | case INTEL_OUTPUT_HDMI: |
5607 | /* | |
5608 | * Only DDI platforms should ever use these output types. | |
5609 | * We can get here after the HDMI detect code has already set | |
5610 | * the type of the shared encoder. Since we can't be sure | |
5611 | * what's the status of the given connectors, play safe and | |
5612 | * run the DP detection too. | |
5613 | */ | |
25f78f58 | 5614 | WARN_ON_ONCE(!HAS_DDI(dev)); |
cca0502b | 5615 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5616 | case INTEL_OUTPUT_EDP: |
5617 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5618 | return port_to_aux_power_domain(intel_dig_port->port); | |
5619 | case INTEL_OUTPUT_DP_MST: | |
5620 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5621 | return port_to_aux_power_domain(intel_dig_port->port); | |
5622 | default: | |
b9fec167 | 5623 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5624 | return POWER_DOMAIN_AUX_A; |
5625 | } | |
5626 | } | |
5627 | ||
74bff5f9 ML |
5628 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5629 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5630 | { |
319be8ae | 5631 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5632 | struct drm_encoder *encoder; |
319be8ae ID |
5633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5634 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5635 | unsigned long mask; |
74bff5f9 | 5636 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5637 | |
74bff5f9 | 5638 | if (!crtc_state->base.active) |
292b990e ML |
5639 | return 0; |
5640 | ||
77d22dca ID |
5641 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5642 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5643 | if (crtc_state->pch_pfit.enabled || |
5644 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5645 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5646 | ||
74bff5f9 ML |
5647 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5648 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5649 | ||
319be8ae | 5650 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5651 | } |
319be8ae | 5652 | |
15e7ec29 ML |
5653 | if (crtc_state->shared_dpll) |
5654 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5655 | ||
77d22dca ID |
5656 | return mask; |
5657 | } | |
5658 | ||
74bff5f9 ML |
5659 | static unsigned long |
5660 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5661 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5662 | { |
fac5e23e | 5663 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5665 | enum intel_display_power_domain domain; | |
5a21b665 | 5666 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5667 | |
292b990e | 5668 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5669 | intel_crtc->enabled_power_domains = new_domains = |
5670 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5671 | |
5a21b665 | 5672 | domains = new_domains & ~old_domains; |
292b990e ML |
5673 | |
5674 | for_each_power_domain(domain, domains) | |
5675 | intel_display_power_get(dev_priv, domain); | |
5676 | ||
5a21b665 | 5677 | return old_domains & ~new_domains; |
292b990e ML |
5678 | } |
5679 | ||
5680 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5681 | unsigned long domains) | |
5682 | { | |
5683 | enum intel_display_power_domain domain; | |
5684 | ||
5685 | for_each_power_domain(domain, domains) | |
5686 | intel_display_power_put(dev_priv, domain); | |
5687 | } | |
77d22dca | 5688 | |
adafdc6f MK |
5689 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5690 | { | |
5691 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5692 | ||
5693 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5694 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5695 | return max_cdclk_freq; | |
5696 | else if (IS_CHERRYVIEW(dev_priv)) | |
5697 | return max_cdclk_freq*95/100; | |
5698 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5699 | return 2*max_cdclk_freq*90/100; | |
5700 | else | |
5701 | return max_cdclk_freq*90/100; | |
5702 | } | |
5703 | ||
b2045352 VS |
5704 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5705 | ||
560a7ae4 DL |
5706 | static void intel_update_max_cdclk(struct drm_device *dev) |
5707 | { | |
fac5e23e | 5708 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 | 5709 | |
ef11bdb3 | 5710 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5711 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5712 | int max_cdclk, vco; |
5713 | ||
5714 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5715 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5716 | |
b2045352 VS |
5717 | /* |
5718 | * Use the lower (vco 8640) cdclk values as a | |
5719 | * first guess. skl_calc_cdclk() will correct it | |
5720 | * if the preferred vco is 8100 instead. | |
5721 | */ | |
560a7ae4 | 5722 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5723 | max_cdclk = 617143; |
560a7ae4 | 5724 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5725 | max_cdclk = 540000; |
560a7ae4 | 5726 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5727 | max_cdclk = 432000; |
560a7ae4 | 5728 | else |
487ed2e4 | 5729 | max_cdclk = 308571; |
b2045352 VS |
5730 | |
5731 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5732 | } else if (IS_BROXTON(dev)) { |
5733 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5734 | } else if (IS_BROADWELL(dev)) { |
5735 | /* | |
5736 | * FIXME with extra cooling we can allow | |
5737 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5738 | * How can we know if extra cooling is | |
5739 | * available? PCI ID, VTB, something else? | |
5740 | */ | |
5741 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5742 | dev_priv->max_cdclk_freq = 450000; | |
5743 | else if (IS_BDW_ULX(dev)) | |
5744 | dev_priv->max_cdclk_freq = 450000; | |
5745 | else if (IS_BDW_ULT(dev)) | |
5746 | dev_priv->max_cdclk_freq = 540000; | |
5747 | else | |
5748 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5749 | } else if (IS_CHERRYVIEW(dev)) { |
5750 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5751 | } else if (IS_VALLEYVIEW(dev)) { |
5752 | dev_priv->max_cdclk_freq = 400000; | |
5753 | } else { | |
5754 | /* otherwise assume cdclk is fixed */ | |
5755 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5756 | } | |
5757 | ||
adafdc6f MK |
5758 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5759 | ||
560a7ae4 DL |
5760 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5761 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5762 | |
5763 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5764 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5765 | } |
5766 | ||
5767 | static void intel_update_cdclk(struct drm_device *dev) | |
5768 | { | |
fac5e23e | 5769 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 DL |
5770 | |
5771 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5772 | |
83d7c81f | 5773 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5774 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5775 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5776 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5777 | else |
5778 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5779 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5780 | |
5781 | /* | |
b5d99ff9 VS |
5782 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5783 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5784 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5785 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5786 | */ |
b5d99ff9 | 5787 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5788 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5789 | } |
5790 | ||
92891e45 VS |
5791 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5792 | static int skl_cdclk_decimal(int cdclk) | |
5793 | { | |
5794 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5795 | } | |
5796 | ||
5f199dfa VS |
5797 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5798 | { | |
5799 | int ratio; | |
5800 | ||
5801 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5802 | return 0; | |
5803 | ||
5804 | switch (cdclk) { | |
5805 | default: | |
5806 | MISSING_CASE(cdclk); | |
5807 | case 144000: | |
5808 | case 288000: | |
5809 | case 384000: | |
5810 | case 576000: | |
5811 | ratio = 60; | |
5812 | break; | |
5813 | case 624000: | |
5814 | ratio = 65; | |
5815 | break; | |
5816 | } | |
5817 | ||
5818 | return dev_priv->cdclk_pll.ref * ratio; | |
5819 | } | |
5820 | ||
2b73001e VS |
5821 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5822 | { | |
5823 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5824 | ||
5825 | /* Timeout 200us */ | |
95cac283 CW |
5826 | if (intel_wait_for_register(dev_priv, |
5827 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5828 | 1)) | |
2b73001e | 5829 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5830 | |
5831 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5832 | } |
5833 | ||
5f199dfa | 5834 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5835 | { |
5f199dfa | 5836 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5837 | u32 val; |
5838 | ||
5839 | val = I915_READ(BXT_DE_PLL_CTL); | |
5840 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5841 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5842 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5843 | ||
5844 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5845 | ||
5846 | /* Timeout 200us */ | |
e084e1b9 CW |
5847 | if (intel_wait_for_register(dev_priv, |
5848 | BXT_DE_PLL_ENABLE, | |
5849 | BXT_DE_PLL_LOCK, | |
5850 | BXT_DE_PLL_LOCK, | |
5851 | 1)) | |
2b73001e | 5852 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5853 | |
5f199dfa | 5854 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5855 | } |
5856 | ||
324513c0 | 5857 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5858 | { |
5f199dfa VS |
5859 | u32 val, divider; |
5860 | int vco, ret; | |
f8437dd1 | 5861 | |
5f199dfa VS |
5862 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5863 | ||
5864 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5865 | ||
5866 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5867 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5868 | case 8: | |
f8437dd1 | 5869 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5870 | break; |
5f199dfa | 5871 | case 4: |
f8437dd1 | 5872 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5873 | break; |
5f199dfa | 5874 | case 3: |
f8437dd1 | 5875 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5876 | break; |
5f199dfa | 5877 | case 2: |
f8437dd1 | 5878 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5879 | break; |
5880 | default: | |
5f199dfa VS |
5881 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5882 | WARN_ON(vco != 0); | |
f8437dd1 | 5883 | |
5f199dfa VS |
5884 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5885 | break; | |
f8437dd1 VK |
5886 | } |
5887 | ||
f8437dd1 | 5888 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5889 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5890 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5891 | 0x80000000); | |
5892 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5893 | ||
5894 | if (ret) { | |
5895 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5896 | ret, cdclk); |
f8437dd1 VK |
5897 | return; |
5898 | } | |
5899 | ||
5f199dfa VS |
5900 | if (dev_priv->cdclk_pll.vco != 0 && |
5901 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5902 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5903 | |
5f199dfa VS |
5904 | if (dev_priv->cdclk_pll.vco != vco) |
5905 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5906 | |
5f199dfa VS |
5907 | val = divider | skl_cdclk_decimal(cdclk); |
5908 | /* | |
5909 | * FIXME if only the cd2x divider needs changing, it could be done | |
5910 | * without shutting off the pipe (if only one pipe is active). | |
5911 | */ | |
5912 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5913 | /* | |
5914 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5915 | * enable otherwise. | |
5916 | */ | |
5917 | if (cdclk >= 500000) | |
5918 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5919 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5920 | |
5921 | mutex_lock(&dev_priv->rps.hw_lock); | |
5922 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5923 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5924 | mutex_unlock(&dev_priv->rps.hw_lock); |
5925 | ||
5926 | if (ret) { | |
5927 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5928 | ret, cdclk); |
f8437dd1 VK |
5929 | return; |
5930 | } | |
5931 | ||
91c8a326 | 5932 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 VK |
5933 | } |
5934 | ||
d66a2194 | 5935 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5936 | { |
d66a2194 ID |
5937 | u32 cdctl, expected; |
5938 | ||
91c8a326 | 5939 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 | 5940 | |
d66a2194 ID |
5941 | if (dev_priv->cdclk_pll.vco == 0 || |
5942 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
5943 | goto sanitize; | |
5944 | ||
5945 | /* DPLL okay; verify the cdclock | |
5946 | * | |
5947 | * Some BIOS versions leave an incorrect decimal frequency value and | |
5948 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
5949 | * so sanitize this register. | |
5950 | */ | |
5951 | cdctl = I915_READ(CDCLK_CTL); | |
5952 | /* | |
5953 | * Let's ignore the pipe field, since BIOS could have configured the | |
5954 | * dividers both synching to an active pipe, or asynchronously | |
5955 | * (PIPE_NONE). | |
5956 | */ | |
5957 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
5958 | ||
5959 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
5960 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5961 | /* | |
5962 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5963 | * enable otherwise. | |
5964 | */ | |
5965 | if (dev_priv->cdclk_freq >= 500000) | |
5966 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5967 | ||
5968 | if (cdctl == expected) | |
5969 | /* All well; nothing to sanitize */ | |
5970 | return; | |
5971 | ||
5972 | sanitize: | |
5973 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
5974 | ||
5975 | /* force cdclk programming */ | |
5976 | dev_priv->cdclk_freq = 0; | |
5977 | ||
5978 | /* force full PLL disable + enable */ | |
5979 | dev_priv->cdclk_pll.vco = -1; | |
5980 | } | |
5981 | ||
324513c0 | 5982 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
5983 | { |
5984 | bxt_sanitize_cdclk(dev_priv); | |
5985 | ||
5986 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 5987 | return; |
c2e001ef | 5988 | |
f8437dd1 VK |
5989 | /* |
5990 | * FIXME: | |
5991 | * - The initial CDCLK needs to be read from VBT. | |
5992 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5993 | */ |
324513c0 | 5994 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
5995 | } |
5996 | ||
324513c0 | 5997 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5998 | { |
324513c0 | 5999 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
6000 | } |
6001 | ||
a8ca4934 VS |
6002 | static int skl_calc_cdclk(int max_pixclk, int vco) |
6003 | { | |
63911d72 | 6004 | if (vco == 8640000) { |
a8ca4934 | 6005 | if (max_pixclk > 540000) |
487ed2e4 | 6006 | return 617143; |
a8ca4934 VS |
6007 | else if (max_pixclk > 432000) |
6008 | return 540000; | |
487ed2e4 | 6009 | else if (max_pixclk > 308571) |
a8ca4934 VS |
6010 | return 432000; |
6011 | else | |
487ed2e4 | 6012 | return 308571; |
a8ca4934 | 6013 | } else { |
a8ca4934 VS |
6014 | if (max_pixclk > 540000) |
6015 | return 675000; | |
6016 | else if (max_pixclk > 450000) | |
6017 | return 540000; | |
6018 | else if (max_pixclk > 337500) | |
6019 | return 450000; | |
6020 | else | |
6021 | return 337500; | |
6022 | } | |
6023 | } | |
6024 | ||
ea61791e VS |
6025 | static void |
6026 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 6027 | { |
ea61791e | 6028 | u32 val; |
5d96d8af | 6029 | |
709e05c3 | 6030 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 6031 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 6032 | |
ea61791e | 6033 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 6034 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 6035 | return; |
5d96d8af | 6036 | |
1c3f7700 ID |
6037 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
6038 | return; | |
9f7eb31a | 6039 | |
ea61791e VS |
6040 | val = I915_READ(DPLL_CTRL1); |
6041 | ||
1c3f7700 ID |
6042 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
6043 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6044 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
6045 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
6046 | return; | |
9f7eb31a | 6047 | |
ea61791e VS |
6048 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
6049 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
6050 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
6051 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
6052 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 6053 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
6054 | break; |
6055 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
6056 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 6057 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
6058 | break; |
6059 | default: | |
6060 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
6061 | break; |
6062 | } | |
5d96d8af DL |
6063 | } |
6064 | ||
b2045352 VS |
6065 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
6066 | { | |
6067 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
6068 | ||
6069 | dev_priv->skl_preferred_vco_freq = vco; | |
6070 | ||
6071 | if (changed) | |
91c8a326 | 6072 | intel_update_max_cdclk(&dev_priv->drm); |
b2045352 VS |
6073 | } |
6074 | ||
5d96d8af | 6075 | static void |
3861fc60 | 6076 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 6077 | { |
a8ca4934 | 6078 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
6079 | u32 val; |
6080 | ||
63911d72 | 6081 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 6082 | |
5d96d8af | 6083 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 6084 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
6085 | I915_WRITE(CDCLK_CTL, val); |
6086 | POSTING_READ(CDCLK_CTL); | |
6087 | ||
6088 | /* | |
6089 | * We always enable DPLL0 with the lowest link rate possible, but still | |
6090 | * taking into account the VCO required to operate the eDP panel at the | |
6091 | * desired frequency. The usual DP link rates operate with a VCO of | |
6092 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
6093 | * The modeset code is responsible for the selection of the exact link | |
6094 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 6095 | * works with vco. |
5d96d8af DL |
6096 | */ |
6097 | val = I915_READ(DPLL_CTRL1); | |
6098 | ||
6099 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6100 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
6101 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 6102 | if (vco == 8640000) |
5d96d8af DL |
6103 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
6104 | SKL_DPLL0); | |
6105 | else | |
6106 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
6107 | SKL_DPLL0); | |
6108 | ||
6109 | I915_WRITE(DPLL_CTRL1, val); | |
6110 | POSTING_READ(DPLL_CTRL1); | |
6111 | ||
6112 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
6113 | ||
e24ca054 CW |
6114 | if (intel_wait_for_register(dev_priv, |
6115 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
6116 | 5)) | |
5d96d8af | 6117 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 6118 | |
63911d72 | 6119 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
6120 | |
6121 | /* We'll want to keep using the current vco from now on. */ | |
6122 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
6123 | } |
6124 | ||
430e05de VS |
6125 | static void |
6126 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
6127 | { | |
6128 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
6129 | if (intel_wait_for_register(dev_priv, |
6130 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
6131 | 1)) | |
430e05de | 6132 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 6133 | |
63911d72 | 6134 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
6135 | } |
6136 | ||
5d96d8af DL |
6137 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
6138 | { | |
6139 | int ret; | |
6140 | u32 val; | |
6141 | ||
6142 | /* inform PCU we want to change CDCLK */ | |
6143 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
6144 | mutex_lock(&dev_priv->rps.hw_lock); | |
6145 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
6146 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6147 | ||
6148 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
6149 | } | |
6150 | ||
6151 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
6152 | { | |
848496e5 | 6153 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
6154 | } |
6155 | ||
1cd593e0 | 6156 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 6157 | { |
91c8a326 | 6158 | struct drm_device *dev = &dev_priv->drm; |
5d96d8af DL |
6159 | u32 freq_select, pcu_ack; |
6160 | ||
1cd593e0 VS |
6161 | WARN_ON((cdclk == 24000) != (vco == 0)); |
6162 | ||
63911d72 | 6163 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
6164 | |
6165 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
6166 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
6167 | return; | |
6168 | } | |
6169 | ||
6170 | /* set CDCLK_CTL */ | |
9ef56154 | 6171 | switch (cdclk) { |
5d96d8af DL |
6172 | case 450000: |
6173 | case 432000: | |
6174 | freq_select = CDCLK_FREQ_450_432; | |
6175 | pcu_ack = 1; | |
6176 | break; | |
6177 | case 540000: | |
6178 | freq_select = CDCLK_FREQ_540; | |
6179 | pcu_ack = 2; | |
6180 | break; | |
487ed2e4 | 6181 | case 308571: |
5d96d8af DL |
6182 | case 337500: |
6183 | default: | |
6184 | freq_select = CDCLK_FREQ_337_308; | |
6185 | pcu_ack = 0; | |
6186 | break; | |
487ed2e4 | 6187 | case 617143: |
5d96d8af DL |
6188 | case 675000: |
6189 | freq_select = CDCLK_FREQ_675_617; | |
6190 | pcu_ack = 3; | |
6191 | break; | |
6192 | } | |
6193 | ||
63911d72 VS |
6194 | if (dev_priv->cdclk_pll.vco != 0 && |
6195 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
6196 | skl_dpll0_disable(dev_priv); |
6197 | ||
63911d72 | 6198 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
6199 | skl_dpll0_enable(dev_priv, vco); |
6200 | ||
9ef56154 | 6201 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
6202 | POSTING_READ(CDCLK_CTL); |
6203 | ||
6204 | /* inform PCU of the change */ | |
6205 | mutex_lock(&dev_priv->rps.hw_lock); | |
6206 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
6207 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
6208 | |
6209 | intel_update_cdclk(dev); | |
5d96d8af DL |
6210 | } |
6211 | ||
9f7eb31a VS |
6212 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
6213 | ||
5d96d8af DL |
6214 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
6215 | { | |
709e05c3 | 6216 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
6217 | } |
6218 | ||
6219 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
6220 | { | |
9f7eb31a VS |
6221 | int cdclk, vco; |
6222 | ||
6223 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 6224 | |
63911d72 | 6225 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
6226 | /* |
6227 | * Use the current vco as our initial | |
6228 | * guess as to what the preferred vco is. | |
6229 | */ | |
6230 | if (dev_priv->skl_preferred_vco_freq == 0) | |
6231 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 6232 | dev_priv->cdclk_pll.vco); |
70c2c184 | 6233 | return; |
1cd593e0 | 6234 | } |
5d96d8af | 6235 | |
70c2c184 VS |
6236 | vco = dev_priv->skl_preferred_vco_freq; |
6237 | if (vco == 0) | |
63911d72 | 6238 | vco = 8100000; |
70c2c184 | 6239 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6240 | |
70c2c184 | 6241 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6242 | } |
6243 | ||
9f7eb31a | 6244 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6245 | { |
09492498 | 6246 | uint32_t cdctl, expected; |
c73666f3 | 6247 | |
f1b391a5 SK |
6248 | /* |
6249 | * check if the pre-os intialized the display | |
6250 | * There is SWF18 scratchpad register defined which is set by the | |
6251 | * pre-os which can be used by the OS drivers to check the status | |
6252 | */ | |
6253 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6254 | goto sanitize; | |
6255 | ||
91c8a326 | 6256 | intel_update_cdclk(&dev_priv->drm); |
c73666f3 | 6257 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6258 | if (dev_priv->cdclk_pll.vco == 0 || |
6259 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6260 | goto sanitize; |
6261 | ||
6262 | /* DPLL okay; verify the cdclock | |
6263 | * | |
6264 | * Noticed in some instances that the freq selection is correct but | |
6265 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6266 | * enable display. Verify the same as well. | |
6267 | */ | |
09492498 VS |
6268 | cdctl = I915_READ(CDCLK_CTL); |
6269 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6270 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6271 | if (cdctl == expected) | |
c73666f3 | 6272 | /* All well; nothing to sanitize */ |
9f7eb31a | 6273 | return; |
c89e39f3 | 6274 | |
9f7eb31a VS |
6275 | sanitize: |
6276 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6277 | |
9f7eb31a VS |
6278 | /* force cdclk programming */ |
6279 | dev_priv->cdclk_freq = 0; | |
6280 | /* force full PLL disable + enable */ | |
63911d72 | 6281 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6282 | } |
6283 | ||
30a970c6 JB |
6284 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6285 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6286 | { | |
fac5e23e | 6287 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6288 | u32 val, cmd; |
6289 | ||
164dfd28 VK |
6290 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6291 | != dev_priv->cdclk_freq); | |
d60c4473 | 6292 | |
dfcab17e | 6293 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6294 | cmd = 2; |
dfcab17e | 6295 | else if (cdclk == 266667) |
30a970c6 JB |
6296 | cmd = 1; |
6297 | else | |
6298 | cmd = 0; | |
6299 | ||
6300 | mutex_lock(&dev_priv->rps.hw_lock); | |
6301 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6302 | val &= ~DSPFREQGUAR_MASK; | |
6303 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6304 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6305 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6306 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6307 | 50)) { | |
6308 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6309 | } | |
6310 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6311 | ||
54433e91 VS |
6312 | mutex_lock(&dev_priv->sb_lock); |
6313 | ||
dfcab17e | 6314 | if (cdclk == 400000) { |
6bcda4f0 | 6315 | u32 divider; |
30a970c6 | 6316 | |
6bcda4f0 | 6317 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6318 | |
30a970c6 JB |
6319 | /* adjust cdclk divider */ |
6320 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6321 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6322 | val |= divider; |
6323 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6324 | |
6325 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6326 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6327 | 50)) |
6328 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6329 | } |
6330 | ||
30a970c6 JB |
6331 | /* adjust self-refresh exit latency value */ |
6332 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6333 | val &= ~0x7f; | |
6334 | ||
6335 | /* | |
6336 | * For high bandwidth configs, we set a higher latency in the bunit | |
6337 | * so that the core display fetch happens in time to avoid underruns. | |
6338 | */ | |
dfcab17e | 6339 | if (cdclk == 400000) |
30a970c6 JB |
6340 | val |= 4500 / 250; /* 4.5 usec */ |
6341 | else | |
6342 | val |= 3000 / 250; /* 3.0 usec */ | |
6343 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6344 | |
a580516d | 6345 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6346 | |
b6283055 | 6347 | intel_update_cdclk(dev); |
30a970c6 JB |
6348 | } |
6349 | ||
383c5a6a VS |
6350 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6351 | { | |
fac5e23e | 6352 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6353 | u32 val, cmd; |
6354 | ||
164dfd28 VK |
6355 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6356 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
6357 | |
6358 | switch (cdclk) { | |
383c5a6a VS |
6359 | case 333333: |
6360 | case 320000: | |
383c5a6a | 6361 | case 266667: |
383c5a6a | 6362 | case 200000: |
383c5a6a VS |
6363 | break; |
6364 | default: | |
5f77eeb0 | 6365 | MISSING_CASE(cdclk); |
383c5a6a VS |
6366 | return; |
6367 | } | |
6368 | ||
9d0d3fda VS |
6369 | /* |
6370 | * Specs are full of misinformation, but testing on actual | |
6371 | * hardware has shown that we just need to write the desired | |
6372 | * CCK divider into the Punit register. | |
6373 | */ | |
6374 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6375 | ||
383c5a6a VS |
6376 | mutex_lock(&dev_priv->rps.hw_lock); |
6377 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6378 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6379 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6380 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6381 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6382 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6383 | 50)) { | |
6384 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6385 | } | |
6386 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6387 | ||
b6283055 | 6388 | intel_update_cdclk(dev); |
383c5a6a VS |
6389 | } |
6390 | ||
30a970c6 JB |
6391 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6392 | int max_pixclk) | |
6393 | { | |
6bcda4f0 | 6394 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6395 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6396 | |
30a970c6 JB |
6397 | /* |
6398 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6399 | * 200MHz | |
6400 | * 267MHz | |
29dc7ef3 | 6401 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6402 | * 400MHz (VLV only) |
6403 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6404 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6405 | * |
6406 | * We seem to get an unstable or solid color picture at 200MHz. | |
6407 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6408 | * are off. | |
30a970c6 | 6409 | */ |
6cca3195 VS |
6410 | if (!IS_CHERRYVIEW(dev_priv) && |
6411 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6412 | return 400000; |
6cca3195 | 6413 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6414 | return freq_320; |
e37c67a1 | 6415 | else if (max_pixclk > 0) |
dfcab17e | 6416 | return 266667; |
e37c67a1 VS |
6417 | else |
6418 | return 200000; | |
30a970c6 JB |
6419 | } |
6420 | ||
324513c0 | 6421 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6422 | { |
760e1477 | 6423 | if (max_pixclk > 576000) |
f8437dd1 | 6424 | return 624000; |
760e1477 | 6425 | else if (max_pixclk > 384000) |
f8437dd1 | 6426 | return 576000; |
760e1477 | 6427 | else if (max_pixclk > 288000) |
f8437dd1 | 6428 | return 384000; |
760e1477 | 6429 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6430 | return 288000; |
6431 | else | |
6432 | return 144000; | |
6433 | } | |
6434 | ||
e8788cbc | 6435 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6436 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6437 | struct drm_atomic_state *state) | |
30a970c6 | 6438 | { |
565602d7 | 6439 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6440 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6441 | struct drm_crtc *crtc; |
6442 | struct drm_crtc_state *crtc_state; | |
6443 | unsigned max_pixclk = 0, i; | |
6444 | enum pipe pipe; | |
30a970c6 | 6445 | |
565602d7 ML |
6446 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6447 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6448 | |
565602d7 ML |
6449 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6450 | int pixclk = 0; | |
6451 | ||
6452 | if (crtc_state->enable) | |
6453 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6454 | |
565602d7 | 6455 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6456 | } |
6457 | ||
565602d7 ML |
6458 | for_each_pipe(dev_priv, pipe) |
6459 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6460 | ||
30a970c6 JB |
6461 | return max_pixclk; |
6462 | } | |
6463 | ||
27c329ed | 6464 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6465 | { |
27c329ed | 6466 | struct drm_device *dev = state->dev; |
fac5e23e | 6467 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6468 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6469 | struct intel_atomic_state *intel_state = |
6470 | to_intel_atomic_state(state); | |
30a970c6 | 6471 | |
1a617b77 | 6472 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6473 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6474 | |
1a617b77 ML |
6475 | if (!intel_state->active_crtcs) |
6476 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6477 | ||
27c329ed ML |
6478 | return 0; |
6479 | } | |
304603f4 | 6480 | |
324513c0 | 6481 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6482 | { |
4e5ca60f | 6483 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6484 | struct intel_atomic_state *intel_state = |
6485 | to_intel_atomic_state(state); | |
85a96e7a | 6486 | |
1a617b77 | 6487 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6488 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6489 | |
1a617b77 | 6490 | if (!intel_state->active_crtcs) |
324513c0 | 6491 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6492 | |
27c329ed | 6493 | return 0; |
30a970c6 JB |
6494 | } |
6495 | ||
1e69cd74 VS |
6496 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6497 | { | |
6498 | unsigned int credits, default_credits; | |
6499 | ||
6500 | if (IS_CHERRYVIEW(dev_priv)) | |
6501 | default_credits = PFI_CREDIT(12); | |
6502 | else | |
6503 | default_credits = PFI_CREDIT(8); | |
6504 | ||
bfa7df01 | 6505 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6506 | /* CHV suggested value is 31 or 63 */ |
6507 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6508 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6509 | else |
6510 | credits = PFI_CREDIT(15); | |
6511 | } else { | |
6512 | credits = default_credits; | |
6513 | } | |
6514 | ||
6515 | /* | |
6516 | * WA - write default credits before re-programming | |
6517 | * FIXME: should we also set the resend bit here? | |
6518 | */ | |
6519 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6520 | default_credits); | |
6521 | ||
6522 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6523 | credits | PFI_CREDIT_RESEND); | |
6524 | ||
6525 | /* | |
6526 | * FIXME is this guaranteed to clear | |
6527 | * immediately or should we poll for it? | |
6528 | */ | |
6529 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6530 | } | |
6531 | ||
27c329ed | 6532 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6533 | { |
a821fc46 | 6534 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6535 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6536 | struct intel_atomic_state *old_intel_state = |
6537 | to_intel_atomic_state(old_state); | |
6538 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6539 | |
27c329ed ML |
6540 | /* |
6541 | * FIXME: We can end up here with all power domains off, yet | |
6542 | * with a CDCLK frequency other than the minimum. To account | |
6543 | * for this take the PIPE-A power domain, which covers the HW | |
6544 | * blocks needed for the following programming. This can be | |
6545 | * removed once it's guaranteed that we get here either with | |
6546 | * the minimum CDCLK set, or the required power domains | |
6547 | * enabled. | |
6548 | */ | |
6549 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6550 | |
27c329ed ML |
6551 | if (IS_CHERRYVIEW(dev)) |
6552 | cherryview_set_cdclk(dev, req_cdclk); | |
6553 | else | |
6554 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6555 | |
27c329ed | 6556 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6557 | |
27c329ed | 6558 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6559 | } |
6560 | ||
89b667f8 JB |
6561 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6562 | { | |
6563 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6564 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6565 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6566 | struct intel_encoder *encoder; | |
b95c5321 ML |
6567 | struct intel_crtc_state *pipe_config = |
6568 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6569 | int pipe = intel_crtc->pipe; |
89b667f8 | 6570 | |
53d9f4e9 | 6571 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6572 | return; |
6573 | ||
37a5650b | 6574 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6575 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6576 | |
6577 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6578 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6579 | |
c14b0485 | 6580 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
fac5e23e | 6581 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6582 | |
6583 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6584 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6585 | } | |
6586 | ||
5b18e57c DV |
6587 | i9xx_set_pipeconf(intel_crtc); |
6588 | ||
89b667f8 | 6589 | intel_crtc->active = true; |
89b667f8 | 6590 | |
a72e4c9f | 6591 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6592 | |
89b667f8 JB |
6593 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6594 | if (encoder->pre_pll_enable) | |
6595 | encoder->pre_pll_enable(encoder); | |
6596 | ||
cd2d34d9 VS |
6597 | if (IS_CHERRYVIEW(dev)) { |
6598 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6599 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6600 | } else { | |
6601 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6602 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6603 | } |
89b667f8 JB |
6604 | |
6605 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6606 | if (encoder->pre_enable) | |
6607 | encoder->pre_enable(encoder); | |
6608 | ||
2dd24552 JB |
6609 | i9xx_pfit_enable(intel_crtc); |
6610 | ||
b95c5321 | 6611 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6612 | |
caed361d | 6613 | intel_update_watermarks(crtc); |
e1fdc473 | 6614 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6615 | |
4b3a9526 VS |
6616 | assert_vblank_disabled(crtc); |
6617 | drm_crtc_vblank_on(crtc); | |
6618 | ||
f9b61ff6 DV |
6619 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6620 | encoder->enable(encoder); | |
89b667f8 JB |
6621 | } |
6622 | ||
f13c2ef3 DV |
6623 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6624 | { | |
6625 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6626 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6627 | |
6e3c9717 ACO |
6628 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6629 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6630 | } |
6631 | ||
0b8765c6 | 6632 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6633 | { |
6634 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6635 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6637 | struct intel_encoder *encoder; |
b95c5321 ML |
6638 | struct intel_crtc_state *pipe_config = |
6639 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6640 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6641 | |
53d9f4e9 | 6642 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6643 | return; |
6644 | ||
f13c2ef3 DV |
6645 | i9xx_set_pll_dividers(intel_crtc); |
6646 | ||
37a5650b | 6647 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6648 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6649 | |
6650 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6651 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6652 | |
5b18e57c DV |
6653 | i9xx_set_pipeconf(intel_crtc); |
6654 | ||
f7abfe8b | 6655 | intel_crtc->active = true; |
6b383a7f | 6656 | |
4a3436e8 | 6657 | if (!IS_GEN2(dev)) |
a72e4c9f | 6658 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6659 | |
9d6d9f19 MK |
6660 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6661 | if (encoder->pre_enable) | |
6662 | encoder->pre_enable(encoder); | |
6663 | ||
f6736a1a DV |
6664 | i9xx_enable_pll(intel_crtc); |
6665 | ||
2dd24552 JB |
6666 | i9xx_pfit_enable(intel_crtc); |
6667 | ||
b95c5321 | 6668 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6669 | |
f37fcc2a | 6670 | intel_update_watermarks(crtc); |
e1fdc473 | 6671 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6672 | |
4b3a9526 VS |
6673 | assert_vblank_disabled(crtc); |
6674 | drm_crtc_vblank_on(crtc); | |
6675 | ||
f9b61ff6 DV |
6676 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6677 | encoder->enable(encoder); | |
0b8765c6 | 6678 | } |
79e53945 | 6679 | |
87476d63 DV |
6680 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6681 | { | |
6682 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6683 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6684 | |
6e3c9717 | 6685 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6686 | return; |
87476d63 | 6687 | |
328d8e82 | 6688 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6689 | |
328d8e82 DV |
6690 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6691 | I915_READ(PFIT_CONTROL)); | |
6692 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6693 | } |
6694 | ||
0b8765c6 JB |
6695 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6696 | { | |
6697 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 6698 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 | 6699 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6700 | struct intel_encoder *encoder; |
0b8765c6 | 6701 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6702 | |
6304cd91 VS |
6703 | /* |
6704 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6705 | * wait for planes to fully turn off before disabling the pipe. | |
6706 | */ | |
90e83e53 ACO |
6707 | if (IS_GEN2(dev)) |
6708 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6709 | |
4b3a9526 VS |
6710 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6711 | encoder->disable(encoder); | |
6712 | ||
f9b61ff6 DV |
6713 | drm_crtc_vblank_off(crtc); |
6714 | assert_vblank_disabled(crtc); | |
6715 | ||
575f7ab7 | 6716 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6717 | |
87476d63 | 6718 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6719 | |
89b667f8 JB |
6720 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6721 | if (encoder->post_disable) | |
6722 | encoder->post_disable(encoder); | |
6723 | ||
d7edc4e5 | 6724 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6725 | if (IS_CHERRYVIEW(dev)) |
6726 | chv_disable_pll(dev_priv, pipe); | |
6727 | else if (IS_VALLEYVIEW(dev)) | |
6728 | vlv_disable_pll(dev_priv, pipe); | |
6729 | else | |
1c4e0274 | 6730 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6731 | } |
0b8765c6 | 6732 | |
d6db995f VS |
6733 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6734 | if (encoder->post_pll_disable) | |
6735 | encoder->post_pll_disable(encoder); | |
6736 | ||
4a3436e8 | 6737 | if (!IS_GEN2(dev)) |
a72e4c9f | 6738 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6739 | } |
6740 | ||
b17d48e2 ML |
6741 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6742 | { | |
842e0307 | 6743 | struct intel_encoder *encoder; |
b17d48e2 ML |
6744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6745 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6746 | enum intel_display_power_domain domain; | |
6747 | unsigned long domains; | |
6748 | ||
6749 | if (!intel_crtc->active) | |
6750 | return; | |
6751 | ||
936e71e3 | 6752 | if (to_intel_plane_state(crtc->primary->state)->base.visible) { |
5a21b665 | 6753 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6754 | |
2622a081 | 6755 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6756 | |
6757 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
936e71e3 | 6758 | to_intel_plane_state(crtc->primary->state)->base.visible = false; |
a539205a ML |
6759 | } |
6760 | ||
b17d48e2 | 6761 | dev_priv->display.crtc_disable(crtc); |
842e0307 | 6762 | |
78108b7c VS |
6763 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6764 | crtc->base.id, crtc->name); | |
842e0307 ML |
6765 | |
6766 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6767 | crtc->state->active = false; | |
37d9078b | 6768 | intel_crtc->active = false; |
842e0307 ML |
6769 | crtc->enabled = false; |
6770 | crtc->state->connector_mask = 0; | |
6771 | crtc->state->encoder_mask = 0; | |
6772 | ||
6773 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6774 | encoder->base.crtc = NULL; | |
6775 | ||
58f9c0bc | 6776 | intel_fbc_disable(intel_crtc); |
37d9078b | 6777 | intel_update_watermarks(crtc); |
1f7457b1 | 6778 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6779 | |
6780 | domains = intel_crtc->enabled_power_domains; | |
6781 | for_each_power_domain(domain, domains) | |
6782 | intel_display_power_put(dev_priv, domain); | |
6783 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6784 | |
6785 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6786 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6787 | } |
6788 | ||
6b72d486 ML |
6789 | /* |
6790 | * turn all crtc's off, but do not adjust state | |
6791 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6792 | */ | |
70e0bd74 | 6793 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6794 | { |
e2c8b870 | 6795 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6796 | struct drm_atomic_state *state; |
e2c8b870 | 6797 | int ret; |
70e0bd74 | 6798 | |
e2c8b870 ML |
6799 | state = drm_atomic_helper_suspend(dev); |
6800 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6801 | if (ret) |
6802 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6803 | else |
6804 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6805 | return ret; |
ee7b9f93 JB |
6806 | } |
6807 | ||
ea5b213a | 6808 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6809 | { |
4ef69c7a | 6810 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6811 | |
ea5b213a CW |
6812 | drm_encoder_cleanup(encoder); |
6813 | kfree(intel_encoder); | |
7e7d76c3 JB |
6814 | } |
6815 | ||
0a91ca29 DV |
6816 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6817 | * internal consistency). */ | |
5a21b665 | 6818 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6819 | { |
5a21b665 | 6820 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6821 | |
6822 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6823 | connector->base.base.id, | |
6824 | connector->base.name); | |
6825 | ||
0a91ca29 | 6826 | if (connector->get_hw_state(connector)) { |
e85376cb | 6827 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6828 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6829 | |
35dd3c64 ML |
6830 | I915_STATE_WARN(!crtc, |
6831 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6832 | |
35dd3c64 ML |
6833 | if (!crtc) |
6834 | return; | |
6835 | ||
6836 | I915_STATE_WARN(!crtc->state->active, | |
6837 | "connector is active, but attached crtc isn't\n"); | |
6838 | ||
e85376cb | 6839 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6840 | return; |
6841 | ||
e85376cb | 6842 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6843 | "atomic encoder doesn't match attached encoder\n"); |
6844 | ||
e85376cb | 6845 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6846 | "attached encoder crtc differs from connector crtc\n"); |
6847 | } else { | |
4d688a2a ML |
6848 | I915_STATE_WARN(crtc && crtc->state->active, |
6849 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6850 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6851 | "best encoder set without crtc!\n"); |
0a91ca29 | 6852 | } |
79e53945 JB |
6853 | } |
6854 | ||
08d9bc92 ACO |
6855 | int intel_connector_init(struct intel_connector *connector) |
6856 | { | |
5350a031 | 6857 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6858 | |
5350a031 | 6859 | if (!connector->base.state) |
08d9bc92 ACO |
6860 | return -ENOMEM; |
6861 | ||
08d9bc92 ACO |
6862 | return 0; |
6863 | } | |
6864 | ||
6865 | struct intel_connector *intel_connector_alloc(void) | |
6866 | { | |
6867 | struct intel_connector *connector; | |
6868 | ||
6869 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6870 | if (!connector) | |
6871 | return NULL; | |
6872 | ||
6873 | if (intel_connector_init(connector) < 0) { | |
6874 | kfree(connector); | |
6875 | return NULL; | |
6876 | } | |
6877 | ||
6878 | return connector; | |
6879 | } | |
6880 | ||
f0947c37 DV |
6881 | /* Simple connector->get_hw_state implementation for encoders that support only |
6882 | * one connector and no cloning and hence the encoder state determines the state | |
6883 | * of the connector. */ | |
6884 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6885 | { |
24929352 | 6886 | enum pipe pipe = 0; |
f0947c37 | 6887 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6888 | |
f0947c37 | 6889 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6890 | } |
6891 | ||
6d293983 | 6892 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6893 | { |
6d293983 ACO |
6894 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6895 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6896 | |
6897 | return 0; | |
6898 | } | |
6899 | ||
6d293983 | 6900 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6901 | struct intel_crtc_state *pipe_config) |
1857e1da | 6902 | { |
6d293983 ACO |
6903 | struct drm_atomic_state *state = pipe_config->base.state; |
6904 | struct intel_crtc *other_crtc; | |
6905 | struct intel_crtc_state *other_crtc_state; | |
6906 | ||
1857e1da DV |
6907 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6908 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6909 | if (pipe_config->fdi_lanes > 4) { | |
6910 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6911 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6912 | return -EINVAL; |
1857e1da DV |
6913 | } |
6914 | ||
bafb6553 | 6915 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6916 | if (pipe_config->fdi_lanes > 2) { |
6917 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6918 | pipe_config->fdi_lanes); | |
6d293983 | 6919 | return -EINVAL; |
1857e1da | 6920 | } else { |
6d293983 | 6921 | return 0; |
1857e1da DV |
6922 | } |
6923 | } | |
6924 | ||
6925 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6926 | return 0; |
1857e1da DV |
6927 | |
6928 | /* Ivybridge 3 pipe is really complicated */ | |
6929 | switch (pipe) { | |
6930 | case PIPE_A: | |
6d293983 | 6931 | return 0; |
1857e1da | 6932 | case PIPE_B: |
6d293983 ACO |
6933 | if (pipe_config->fdi_lanes <= 2) |
6934 | return 0; | |
6935 | ||
6936 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6937 | other_crtc_state = | |
6938 | intel_atomic_get_crtc_state(state, other_crtc); | |
6939 | if (IS_ERR(other_crtc_state)) | |
6940 | return PTR_ERR(other_crtc_state); | |
6941 | ||
6942 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6943 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6944 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6945 | return -EINVAL; |
1857e1da | 6946 | } |
6d293983 | 6947 | return 0; |
1857e1da | 6948 | case PIPE_C: |
251cc67c VS |
6949 | if (pipe_config->fdi_lanes > 2) { |
6950 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6951 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6952 | return -EINVAL; |
251cc67c | 6953 | } |
6d293983 ACO |
6954 | |
6955 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6956 | other_crtc_state = | |
6957 | intel_atomic_get_crtc_state(state, other_crtc); | |
6958 | if (IS_ERR(other_crtc_state)) | |
6959 | return PTR_ERR(other_crtc_state); | |
6960 | ||
6961 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6962 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6963 | return -EINVAL; |
1857e1da | 6964 | } |
6d293983 | 6965 | return 0; |
1857e1da DV |
6966 | default: |
6967 | BUG(); | |
6968 | } | |
6969 | } | |
6970 | ||
e29c22c0 DV |
6971 | #define RETRY 1 |
6972 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6973 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6974 | { |
1857e1da | 6975 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6976 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6977 | int lane, link_bw, fdi_dotclock, ret; |
6978 | bool needs_recompute = false; | |
877d48d5 | 6979 | |
e29c22c0 | 6980 | retry: |
877d48d5 DV |
6981 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6982 | * each output octet as 10 bits. The actual frequency | |
6983 | * is stored as a divider into a 100MHz clock, and the | |
6984 | * mode pixel clock is stored in units of 1KHz. | |
6985 | * Hence the bw of each lane in terms of the mode signal | |
6986 | * is: | |
6987 | */ | |
21a727b3 | 6988 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6989 | |
241bfc38 | 6990 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6991 | |
2bd89a07 | 6992 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6993 | pipe_config->pipe_bpp); |
6994 | ||
6995 | pipe_config->fdi_lanes = lane; | |
6996 | ||
2bd89a07 | 6997 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6998 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6999 | |
e3b247da | 7000 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 7001 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
7002 | pipe_config->pipe_bpp -= 2*3; |
7003 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
7004 | pipe_config->pipe_bpp); | |
7005 | needs_recompute = true; | |
7006 | pipe_config->bw_constrained = true; | |
7007 | ||
7008 | goto retry; | |
7009 | } | |
7010 | ||
7011 | if (needs_recompute) | |
7012 | return RETRY; | |
7013 | ||
6d293983 | 7014 | return ret; |
877d48d5 DV |
7015 | } |
7016 | ||
8cfb3407 VS |
7017 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
7018 | struct intel_crtc_state *pipe_config) | |
7019 | { | |
7020 | if (pipe_config->pipe_bpp > 24) | |
7021 | return false; | |
7022 | ||
7023 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 7024 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
7025 | return true; |
7026 | ||
7027 | /* | |
b432e5cf VS |
7028 | * We compare against max which means we must take |
7029 | * the increased cdclk requirement into account when | |
7030 | * calculating the new cdclk. | |
7031 | * | |
7032 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
7033 | */ |
7034 | return ilk_pipe_pixel_rate(pipe_config) <= | |
7035 | dev_priv->max_cdclk_freq * 95 / 100; | |
7036 | } | |
7037 | ||
42db64ef | 7038 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 7039 | struct intel_crtc_state *pipe_config) |
42db64ef | 7040 | { |
8cfb3407 | 7041 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7042 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 7043 | |
d330a953 | 7044 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
7045 | hsw_crtc_supports_ips(crtc) && |
7046 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
7047 | } |
7048 | ||
39acb4aa VS |
7049 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
7050 | { | |
7051 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7052 | ||
7053 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
7054 | return INTEL_INFO(dev_priv)->gen < 4 && | |
7055 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
7056 | } | |
7057 | ||
a43f6e0f | 7058 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 7059 | struct intel_crtc_state *pipe_config) |
79e53945 | 7060 | { |
a43f6e0f | 7061 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7062 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 7063 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 7064 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 7065 | |
cf532bb2 | 7066 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 7067 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
7068 | |
7069 | /* | |
39acb4aa | 7070 | * Enable double wide mode when the dot clock |
cf532bb2 | 7071 | * is > 90% of the (display) core speed. |
cf532bb2 | 7072 | */ |
39acb4aa VS |
7073 | if (intel_crtc_supports_double_wide(crtc) && |
7074 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 7075 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 7076 | pipe_config->double_wide = true; |
ad3a4479 | 7077 | } |
f3261156 | 7078 | } |
ad3a4479 | 7079 | |
f3261156 VS |
7080 | if (adjusted_mode->crtc_clock > clock_limit) { |
7081 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
7082 | adjusted_mode->crtc_clock, clock_limit, | |
7083 | yesno(pipe_config->double_wide)); | |
7084 | return -EINVAL; | |
2c07245f | 7085 | } |
89749350 | 7086 | |
1d1d0e27 VS |
7087 | /* |
7088 | * Pipe horizontal size must be even in: | |
7089 | * - DVO ganged mode | |
7090 | * - LVDS dual channel mode | |
7091 | * - Double wide pipe | |
7092 | */ | |
2d84d2b3 | 7093 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
7094 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
7095 | pipe_config->pipe_src_w &= ~1; | |
7096 | ||
8693a824 DL |
7097 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
7098 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
7099 | */ |
7100 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 7101 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 7102 | return -EINVAL; |
44f46b42 | 7103 | |
f5adf94e | 7104 | if (HAS_IPS(dev)) |
a43f6e0f DV |
7105 | hsw_compute_ips_config(crtc, pipe_config); |
7106 | ||
877d48d5 | 7107 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 7108 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 7109 | |
cf5a15be | 7110 | return 0; |
79e53945 JB |
7111 | } |
7112 | ||
1652d19e VS |
7113 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
7114 | { | |
7115 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 7116 | uint32_t cdctl; |
1652d19e | 7117 | |
ea61791e | 7118 | skl_dpll0_update(dev_priv); |
1652d19e | 7119 | |
63911d72 | 7120 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 7121 | return dev_priv->cdclk_pll.ref; |
1652d19e | 7122 | |
ea61791e | 7123 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 7124 | |
63911d72 | 7125 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
7126 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7127 | case CDCLK_FREQ_450_432: | |
7128 | return 432000; | |
7129 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 7130 | return 308571; |
ea61791e VS |
7131 | case CDCLK_FREQ_540: |
7132 | return 540000; | |
1652d19e | 7133 | case CDCLK_FREQ_675_617: |
487ed2e4 | 7134 | return 617143; |
1652d19e | 7135 | default: |
ea61791e | 7136 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7137 | } |
7138 | } else { | |
1652d19e VS |
7139 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7140 | case CDCLK_FREQ_450_432: | |
7141 | return 450000; | |
7142 | case CDCLK_FREQ_337_308: | |
7143 | return 337500; | |
ea61791e VS |
7144 | case CDCLK_FREQ_540: |
7145 | return 540000; | |
1652d19e VS |
7146 | case CDCLK_FREQ_675_617: |
7147 | return 675000; | |
7148 | default: | |
ea61791e | 7149 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7150 | } |
7151 | } | |
7152 | ||
709e05c3 | 7153 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
7154 | } |
7155 | ||
83d7c81f VS |
7156 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
7157 | { | |
7158 | u32 val; | |
7159 | ||
7160 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 7161 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
7162 | |
7163 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 7164 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 7165 | return; |
83d7c81f | 7166 | |
1c3f7700 ID |
7167 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
7168 | return; | |
83d7c81f VS |
7169 | |
7170 | val = I915_READ(BXT_DE_PLL_CTL); | |
7171 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
7172 | dev_priv->cdclk_pll.ref; | |
7173 | } | |
7174 | ||
acd3f3d3 BP |
7175 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
7176 | { | |
7177 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
7178 | u32 divider; |
7179 | int div, vco; | |
acd3f3d3 | 7180 | |
83d7c81f VS |
7181 | bxt_de_pll_update(dev_priv); |
7182 | ||
f5986242 VS |
7183 | vco = dev_priv->cdclk_pll.vco; |
7184 | if (vco == 0) | |
7185 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 7186 | |
f5986242 | 7187 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 7188 | |
f5986242 | 7189 | switch (divider) { |
acd3f3d3 | 7190 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
7191 | div = 2; |
7192 | break; | |
acd3f3d3 | 7193 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
7194 | div = 3; |
7195 | break; | |
acd3f3d3 | 7196 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
7197 | div = 4; |
7198 | break; | |
acd3f3d3 | 7199 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
7200 | div = 8; |
7201 | break; | |
7202 | default: | |
7203 | MISSING_CASE(divider); | |
7204 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
7205 | } |
7206 | ||
f5986242 | 7207 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
7208 | } |
7209 | ||
1652d19e VS |
7210 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
7211 | { | |
fac5e23e | 7212 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
7213 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7214 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7215 | ||
7216 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7217 | return 800000; | |
7218 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7219 | return 450000; | |
7220 | else if (freq == LCPLL_CLK_FREQ_450) | |
7221 | return 450000; | |
7222 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
7223 | return 540000; | |
7224 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
7225 | return 337500; | |
7226 | else | |
7227 | return 675000; | |
7228 | } | |
7229 | ||
7230 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
7231 | { | |
fac5e23e | 7232 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
7233 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7234 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7235 | ||
7236 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7237 | return 800000; | |
7238 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7239 | return 450000; | |
7240 | else if (freq == LCPLL_CLK_FREQ_450) | |
7241 | return 450000; | |
7242 | else if (IS_HSW_ULT(dev)) | |
7243 | return 337500; | |
7244 | else | |
7245 | return 540000; | |
79e53945 JB |
7246 | } |
7247 | ||
25eb05fc JB |
7248 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
7249 | { | |
bfa7df01 VS |
7250 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
7251 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
7252 | } |
7253 | ||
b37a6434 VS |
7254 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
7255 | { | |
7256 | return 450000; | |
7257 | } | |
7258 | ||
e70236a8 JB |
7259 | static int i945_get_display_clock_speed(struct drm_device *dev) |
7260 | { | |
7261 | return 400000; | |
7262 | } | |
79e53945 | 7263 | |
e70236a8 | 7264 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 7265 | { |
e907f170 | 7266 | return 333333; |
e70236a8 | 7267 | } |
79e53945 | 7268 | |
e70236a8 JB |
7269 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
7270 | { | |
7271 | return 200000; | |
7272 | } | |
79e53945 | 7273 | |
257a7ffc DV |
7274 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
7275 | { | |
7276 | u16 gcfgc = 0; | |
7277 | ||
7278 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
7279 | ||
7280 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7281 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7282 | return 266667; |
257a7ffc | 7283 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7284 | return 333333; |
257a7ffc | 7285 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7286 | return 444444; |
257a7ffc DV |
7287 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7288 | return 200000; | |
7289 | default: | |
7290 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7291 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7292 | return 133333; |
257a7ffc | 7293 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7294 | return 166667; |
257a7ffc DV |
7295 | } |
7296 | } | |
7297 | ||
e70236a8 JB |
7298 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
7299 | { | |
7300 | u16 gcfgc = 0; | |
79e53945 | 7301 | |
e70236a8 JB |
7302 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
7303 | ||
7304 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7305 | return 133333; |
e70236a8 JB |
7306 | else { |
7307 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7308 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7309 | return 333333; |
e70236a8 JB |
7310 | default: |
7311 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7312 | return 190000; | |
79e53945 | 7313 | } |
e70236a8 JB |
7314 | } |
7315 | } | |
7316 | ||
7317 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
7318 | { | |
e907f170 | 7319 | return 266667; |
e70236a8 JB |
7320 | } |
7321 | ||
1b1d2716 | 7322 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
7323 | { |
7324 | u16 hpllcc = 0; | |
1b1d2716 | 7325 | |
65cd2b3f VS |
7326 | /* |
7327 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7328 | * encoding is different :( | |
7329 | * FIXME is this the right way to detect 852GM/852GMV? | |
7330 | */ | |
7331 | if (dev->pdev->revision == 0x1) | |
7332 | return 133333; | |
7333 | ||
1b1d2716 VS |
7334 | pci_bus_read_config_word(dev->pdev->bus, |
7335 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
7336 | ||
e70236a8 JB |
7337 | /* Assume that the hardware is in the high speed state. This |
7338 | * should be the default. | |
7339 | */ | |
7340 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7341 | case GC_CLOCK_133_200: | |
1b1d2716 | 7342 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7343 | case GC_CLOCK_100_200: |
7344 | return 200000; | |
7345 | case GC_CLOCK_166_250: | |
7346 | return 250000; | |
7347 | case GC_CLOCK_100_133: | |
e907f170 | 7348 | return 133333; |
1b1d2716 VS |
7349 | case GC_CLOCK_133_266: |
7350 | case GC_CLOCK_133_266_2: | |
7351 | case GC_CLOCK_166_266: | |
7352 | return 266667; | |
e70236a8 | 7353 | } |
79e53945 | 7354 | |
e70236a8 JB |
7355 | /* Shouldn't happen */ |
7356 | return 0; | |
7357 | } | |
79e53945 | 7358 | |
e70236a8 JB |
7359 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7360 | { | |
e907f170 | 7361 | return 133333; |
79e53945 JB |
7362 | } |
7363 | ||
34edce2f VS |
7364 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7365 | { | |
fac5e23e | 7366 | struct drm_i915_private *dev_priv = to_i915(dev); |
34edce2f VS |
7367 | static const unsigned int blb_vco[8] = { |
7368 | [0] = 3200000, | |
7369 | [1] = 4000000, | |
7370 | [2] = 5333333, | |
7371 | [3] = 4800000, | |
7372 | [4] = 6400000, | |
7373 | }; | |
7374 | static const unsigned int pnv_vco[8] = { | |
7375 | [0] = 3200000, | |
7376 | [1] = 4000000, | |
7377 | [2] = 5333333, | |
7378 | [3] = 4800000, | |
7379 | [4] = 2666667, | |
7380 | }; | |
7381 | static const unsigned int cl_vco[8] = { | |
7382 | [0] = 3200000, | |
7383 | [1] = 4000000, | |
7384 | [2] = 5333333, | |
7385 | [3] = 6400000, | |
7386 | [4] = 3333333, | |
7387 | [5] = 3566667, | |
7388 | [6] = 4266667, | |
7389 | }; | |
7390 | static const unsigned int elk_vco[8] = { | |
7391 | [0] = 3200000, | |
7392 | [1] = 4000000, | |
7393 | [2] = 5333333, | |
7394 | [3] = 4800000, | |
7395 | }; | |
7396 | static const unsigned int ctg_vco[8] = { | |
7397 | [0] = 3200000, | |
7398 | [1] = 4000000, | |
7399 | [2] = 5333333, | |
7400 | [3] = 6400000, | |
7401 | [4] = 2666667, | |
7402 | [5] = 4266667, | |
7403 | }; | |
7404 | const unsigned int *vco_table; | |
7405 | unsigned int vco; | |
7406 | uint8_t tmp = 0; | |
7407 | ||
7408 | /* FIXME other chipsets? */ | |
7409 | if (IS_GM45(dev)) | |
7410 | vco_table = ctg_vco; | |
7411 | else if (IS_G4X(dev)) | |
7412 | vco_table = elk_vco; | |
7413 | else if (IS_CRESTLINE(dev)) | |
7414 | vco_table = cl_vco; | |
7415 | else if (IS_PINEVIEW(dev)) | |
7416 | vco_table = pnv_vco; | |
7417 | else if (IS_G33(dev)) | |
7418 | vco_table = blb_vco; | |
7419 | else | |
7420 | return 0; | |
7421 | ||
7422 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7423 | ||
7424 | vco = vco_table[tmp & 0x7]; | |
7425 | if (vco == 0) | |
7426 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7427 | else | |
7428 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7429 | ||
7430 | return vco; | |
7431 | } | |
7432 | ||
7433 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7434 | { | |
7435 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7436 | uint16_t tmp = 0; | |
7437 | ||
7438 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7439 | ||
7440 | cdclk_sel = (tmp >> 12) & 0x1; | |
7441 | ||
7442 | switch (vco) { | |
7443 | case 2666667: | |
7444 | case 4000000: | |
7445 | case 5333333: | |
7446 | return cdclk_sel ? 333333 : 222222; | |
7447 | case 3200000: | |
7448 | return cdclk_sel ? 320000 : 228571; | |
7449 | default: | |
7450 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7451 | return 222222; | |
7452 | } | |
7453 | } | |
7454 | ||
7455 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7456 | { | |
7457 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7458 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7459 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7460 | const uint8_t *div_table; | |
7461 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7462 | uint16_t tmp = 0; | |
7463 | ||
7464 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7465 | ||
7466 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7467 | ||
7468 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7469 | goto fail; | |
7470 | ||
7471 | switch (vco) { | |
7472 | case 3200000: | |
7473 | div_table = div_3200; | |
7474 | break; | |
7475 | case 4000000: | |
7476 | div_table = div_4000; | |
7477 | break; | |
7478 | case 5333333: | |
7479 | div_table = div_5333; | |
7480 | break; | |
7481 | default: | |
7482 | goto fail; | |
7483 | } | |
7484 | ||
7485 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7486 | ||
caf4e252 | 7487 | fail: |
34edce2f VS |
7488 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7489 | return 200000; | |
7490 | } | |
7491 | ||
7492 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7493 | { | |
7494 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7495 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7496 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7497 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7498 | const uint8_t *div_table; | |
7499 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7500 | uint16_t tmp = 0; | |
7501 | ||
7502 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7503 | ||
7504 | cdclk_sel = (tmp >> 4) & 0x7; | |
7505 | ||
7506 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7507 | goto fail; | |
7508 | ||
7509 | switch (vco) { | |
7510 | case 3200000: | |
7511 | div_table = div_3200; | |
7512 | break; | |
7513 | case 4000000: | |
7514 | div_table = div_4000; | |
7515 | break; | |
7516 | case 4800000: | |
7517 | div_table = div_4800; | |
7518 | break; | |
7519 | case 5333333: | |
7520 | div_table = div_5333; | |
7521 | break; | |
7522 | default: | |
7523 | goto fail; | |
7524 | } | |
7525 | ||
7526 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7527 | ||
caf4e252 | 7528 | fail: |
34edce2f VS |
7529 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7530 | return 190476; | |
7531 | } | |
7532 | ||
2c07245f | 7533 | static void |
a65851af | 7534 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7535 | { |
a65851af VS |
7536 | while (*num > DATA_LINK_M_N_MASK || |
7537 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7538 | *num >>= 1; |
7539 | *den >>= 1; | |
7540 | } | |
7541 | } | |
7542 | ||
a65851af VS |
7543 | static void compute_m_n(unsigned int m, unsigned int n, |
7544 | uint32_t *ret_m, uint32_t *ret_n) | |
7545 | { | |
7546 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7547 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7548 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7549 | } | |
7550 | ||
e69d0bc1 DV |
7551 | void |
7552 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7553 | int pixel_clock, int link_clock, | |
7554 | struct intel_link_m_n *m_n) | |
2c07245f | 7555 | { |
e69d0bc1 | 7556 | m_n->tu = 64; |
a65851af VS |
7557 | |
7558 | compute_m_n(bits_per_pixel * pixel_clock, | |
7559 | link_clock * nlanes * 8, | |
7560 | &m_n->gmch_m, &m_n->gmch_n); | |
7561 | ||
7562 | compute_m_n(pixel_clock, link_clock, | |
7563 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7564 | } |
7565 | ||
a7615030 CW |
7566 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7567 | { | |
d330a953 JN |
7568 | if (i915.panel_use_ssc >= 0) |
7569 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7570 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7571 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7572 | } |
7573 | ||
7429e9d4 | 7574 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7575 | { |
7df00d7a | 7576 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7577 | } |
f47709a9 | 7578 | |
7429e9d4 DV |
7579 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7580 | { | |
7581 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7582 | } |
7583 | ||
f47709a9 | 7584 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7585 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7586 | struct dpll *reduced_clock) |
a7516a05 | 7587 | { |
f47709a9 | 7588 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7589 | u32 fp, fp2 = 0; |
7590 | ||
7591 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7592 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7593 | if (reduced_clock) |
7429e9d4 | 7594 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7595 | } else { |
190f68c5 | 7596 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7597 | if (reduced_clock) |
7429e9d4 | 7598 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7599 | } |
7600 | ||
190f68c5 | 7601 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7602 | |
f47709a9 | 7603 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7604 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7605 | reduced_clock) { |
190f68c5 | 7606 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7607 | crtc->lowfreq_avail = true; |
a7516a05 | 7608 | } else { |
190f68c5 | 7609 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7610 | } |
7611 | } | |
7612 | ||
5e69f97f CML |
7613 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7614 | pipe) | |
89b667f8 JB |
7615 | { |
7616 | u32 reg_val; | |
7617 | ||
7618 | /* | |
7619 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7620 | * and set it to a reasonable value instead. | |
7621 | */ | |
ab3c759a | 7622 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7623 | reg_val &= 0xffffff00; |
7624 | reg_val |= 0x00000030; | |
ab3c759a | 7625 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7626 | |
ab3c759a | 7627 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7628 | reg_val &= 0x8cffffff; |
7629 | reg_val = 0x8c000000; | |
ab3c759a | 7630 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7631 | |
ab3c759a | 7632 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7633 | reg_val &= 0xffffff00; |
ab3c759a | 7634 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7635 | |
ab3c759a | 7636 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7637 | reg_val &= 0x00ffffff; |
7638 | reg_val |= 0xb0000000; | |
ab3c759a | 7639 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7640 | } |
7641 | ||
b551842d DV |
7642 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7643 | struct intel_link_m_n *m_n) | |
7644 | { | |
7645 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7646 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7647 | int pipe = crtc->pipe; |
7648 | ||
e3b95f1e DV |
7649 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7650 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7651 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7652 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7653 | } |
7654 | ||
7655 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7656 | struct intel_link_m_n *m_n, |
7657 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7658 | { |
7659 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7660 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7661 | int pipe = crtc->pipe; |
6e3c9717 | 7662 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7663 | |
7664 | if (INTEL_INFO(dev)->gen >= 5) { | |
7665 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7666 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7667 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7668 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7669 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7670 | * for gen < 8) and if DRRS is supported (to make sure the | |
7671 | * registers are not unnecessarily accessed). | |
7672 | */ | |
44395bfe | 7673 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7674 | crtc->config->has_drrs) { |
f769cd24 VK |
7675 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7676 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7677 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7678 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7679 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7680 | } | |
b551842d | 7681 | } else { |
e3b95f1e DV |
7682 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7683 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7684 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7685 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7686 | } |
7687 | } | |
7688 | ||
fe3cd48d | 7689 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7690 | { |
fe3cd48d R |
7691 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7692 | ||
7693 | if (m_n == M1_N1) { | |
7694 | dp_m_n = &crtc->config->dp_m_n; | |
7695 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7696 | } else if (m_n == M2_N2) { | |
7697 | ||
7698 | /* | |
7699 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7700 | * needs to be programmed into M1_N1. | |
7701 | */ | |
7702 | dp_m_n = &crtc->config->dp_m2_n2; | |
7703 | } else { | |
7704 | DRM_ERROR("Unsupported divider value\n"); | |
7705 | return; | |
7706 | } | |
7707 | ||
6e3c9717 ACO |
7708 | if (crtc->config->has_pch_encoder) |
7709 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7710 | else |
fe3cd48d | 7711 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7712 | } |
7713 | ||
251ac862 DV |
7714 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7715 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7716 | { |
03ed5cbf | 7717 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7718 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7719 | if (crtc->pipe != PIPE_A) |
7720 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7721 | |
cd2d34d9 | 7722 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7723 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7724 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7725 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7726 | ||
03ed5cbf VS |
7727 | pipe_config->dpll_hw_state.dpll_md = |
7728 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7729 | } | |
bdd4b6a6 | 7730 | |
03ed5cbf VS |
7731 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7732 | struct intel_crtc_state *pipe_config) | |
7733 | { | |
7734 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7735 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7736 | if (crtc->pipe != PIPE_A) |
7737 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7738 | ||
cd2d34d9 | 7739 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7740 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7741 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7742 | ||
03ed5cbf VS |
7743 | pipe_config->dpll_hw_state.dpll_md = |
7744 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7745 | } |
7746 | ||
d288f65f | 7747 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7748 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7749 | { |
f47709a9 | 7750 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7751 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7752 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7753 | u32 mdiv; |
a0c4da24 | 7754 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7755 | u32 coreclk, reg_val; |
a0c4da24 | 7756 | |
cd2d34d9 VS |
7757 | /* Enable Refclk */ |
7758 | I915_WRITE(DPLL(pipe), | |
7759 | pipe_config->dpll_hw_state.dpll & | |
7760 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7761 | ||
7762 | /* No need to actually set up the DPLL with DSI */ | |
7763 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7764 | return; | |
7765 | ||
a580516d | 7766 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7767 | |
d288f65f VS |
7768 | bestn = pipe_config->dpll.n; |
7769 | bestm1 = pipe_config->dpll.m1; | |
7770 | bestm2 = pipe_config->dpll.m2; | |
7771 | bestp1 = pipe_config->dpll.p1; | |
7772 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7773 | |
89b667f8 JB |
7774 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7775 | ||
7776 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7777 | if (pipe == PIPE_B) |
5e69f97f | 7778 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7779 | |
7780 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7781 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7782 | |
7783 | /* Disable target IRef on PLL */ | |
ab3c759a | 7784 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7785 | reg_val &= 0x00ffffff; |
ab3c759a | 7786 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7787 | |
7788 | /* Disable fast lock */ | |
ab3c759a | 7789 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7790 | |
7791 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7792 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7793 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7794 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7795 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7796 | |
7797 | /* | |
7798 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7799 | * but we don't support that). | |
7800 | * Note: don't use the DAC post divider as it seems unstable. | |
7801 | */ | |
7802 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7803 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7804 | |
a0c4da24 | 7805 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7806 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7807 | |
89b667f8 | 7808 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7809 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7810 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7811 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7812 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7813 | 0x009f0003); |
89b667f8 | 7814 | else |
ab3c759a | 7815 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7816 | 0x00d0000f); |
7817 | ||
37a5650b | 7818 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7819 | /* Use SSC source */ |
bdd4b6a6 | 7820 | if (pipe == PIPE_A) |
ab3c759a | 7821 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7822 | 0x0df40000); |
7823 | else | |
ab3c759a | 7824 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7825 | 0x0df70000); |
7826 | } else { /* HDMI or VGA */ | |
7827 | /* Use bend source */ | |
bdd4b6a6 | 7828 | if (pipe == PIPE_A) |
ab3c759a | 7829 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7830 | 0x0df70000); |
7831 | else | |
ab3c759a | 7832 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7833 | 0x0df40000); |
7834 | } | |
a0c4da24 | 7835 | |
ab3c759a | 7836 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7837 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7838 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7839 | coreclk |= 0x01000000; |
ab3c759a | 7840 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7841 | |
ab3c759a | 7842 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7843 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7844 | } |
7845 | ||
d288f65f | 7846 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7847 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7848 | { |
7849 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7850 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7851 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7852 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7853 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7854 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7855 | u32 dpio_val; |
9cbe40c1 | 7856 | int vco; |
9d556c99 | 7857 | |
cd2d34d9 VS |
7858 | /* Enable Refclk and SSC */ |
7859 | I915_WRITE(DPLL(pipe), | |
7860 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7861 | ||
7862 | /* No need to actually set up the DPLL with DSI */ | |
7863 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7864 | return; | |
7865 | ||
d288f65f VS |
7866 | bestn = pipe_config->dpll.n; |
7867 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7868 | bestm1 = pipe_config->dpll.m1; | |
7869 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7870 | bestp1 = pipe_config->dpll.p1; | |
7871 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7872 | vco = pipe_config->dpll.vco; |
a945ce7e | 7873 | dpio_val = 0; |
9cbe40c1 | 7874 | loopfilter = 0; |
9d556c99 | 7875 | |
a580516d | 7876 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7877 | |
9d556c99 CML |
7878 | /* p1 and p2 divider */ |
7879 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7880 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7881 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7882 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7883 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7884 | ||
7885 | /* Feedback post-divider - m2 */ | |
7886 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7887 | ||
7888 | /* Feedback refclk divider - n and m1 */ | |
7889 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7890 | DPIO_CHV_M1_DIV_BY_2 | | |
7891 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7892 | ||
7893 | /* M2 fraction division */ | |
25a25dfc | 7894 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7895 | |
7896 | /* M2 fraction division enable */ | |
a945ce7e VP |
7897 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7898 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7899 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7900 | if (bestm2_frac) | |
7901 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7902 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7903 | |
de3a0fde VP |
7904 | /* Program digital lock detect threshold */ |
7905 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7906 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7907 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7908 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7909 | if (!bestm2_frac) | |
7910 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7911 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7912 | ||
9d556c99 | 7913 | /* Loop filter */ |
9cbe40c1 VP |
7914 | if (vco == 5400000) { |
7915 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7916 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7917 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7918 | tribuf_calcntr = 0x9; | |
7919 | } else if (vco <= 6200000) { | |
7920 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7921 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7922 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7923 | tribuf_calcntr = 0x9; | |
7924 | } else if (vco <= 6480000) { | |
7925 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7926 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7927 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7928 | tribuf_calcntr = 0x8; | |
7929 | } else { | |
7930 | /* Not supported. Apply the same limits as in the max case */ | |
7931 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7932 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7933 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7934 | tribuf_calcntr = 0; | |
7935 | } | |
9d556c99 CML |
7936 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7937 | ||
968040b2 | 7938 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7939 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7940 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7941 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7942 | ||
9d556c99 CML |
7943 | /* AFC Recal */ |
7944 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7945 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7946 | DPIO_AFC_RECAL); | |
7947 | ||
a580516d | 7948 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7949 | } |
7950 | ||
d288f65f VS |
7951 | /** |
7952 | * vlv_force_pll_on - forcibly enable just the PLL | |
7953 | * @dev_priv: i915 private structure | |
7954 | * @pipe: pipe PLL to enable | |
7955 | * @dpll: PLL configuration | |
7956 | * | |
7957 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7958 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7959 | * be enabled. | |
7960 | */ | |
3f36b937 TU |
7961 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7962 | const struct dpll *dpll) | |
d288f65f VS |
7963 | { |
7964 | struct intel_crtc *crtc = | |
7965 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7966 | struct intel_crtc_state *pipe_config; |
7967 | ||
7968 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7969 | if (!pipe_config) | |
7970 | return -ENOMEM; | |
7971 | ||
7972 | pipe_config->base.crtc = &crtc->base; | |
7973 | pipe_config->pixel_multiplier = 1; | |
7974 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7975 | |
7976 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7977 | chv_compute_dpll(crtc, pipe_config); |
7978 | chv_prepare_pll(crtc, pipe_config); | |
7979 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7980 | } else { |
3f36b937 TU |
7981 | vlv_compute_dpll(crtc, pipe_config); |
7982 | vlv_prepare_pll(crtc, pipe_config); | |
7983 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7984 | } |
3f36b937 TU |
7985 | |
7986 | kfree(pipe_config); | |
7987 | ||
7988 | return 0; | |
d288f65f VS |
7989 | } |
7990 | ||
7991 | /** | |
7992 | * vlv_force_pll_off - forcibly disable just the PLL | |
7993 | * @dev_priv: i915 private structure | |
7994 | * @pipe: pipe PLL to disable | |
7995 | * | |
7996 | * Disable the PLL for @pipe. To be used in cases where we need | |
7997 | * the PLL enabled even when @pipe is not going to be enabled. | |
7998 | */ | |
7999 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
8000 | { | |
8001 | if (IS_CHERRYVIEW(dev)) | |
8002 | chv_disable_pll(to_i915(dev), pipe); | |
8003 | else | |
8004 | vlv_disable_pll(to_i915(dev), pipe); | |
8005 | } | |
8006 | ||
251ac862 DV |
8007 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8008 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8009 | struct dpll *reduced_clock) |
eb1cbe48 | 8010 | { |
f47709a9 | 8011 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8012 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8013 | u32 dpll; |
190f68c5 | 8014 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8015 | |
190f68c5 | 8016 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8017 | |
eb1cbe48 DV |
8018 | dpll = DPLL_VGA_MODE_DIS; |
8019 | ||
2d84d2b3 | 8020 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8021 | dpll |= DPLLB_MODE_LVDS; |
8022 | else | |
8023 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8024 | |
ef1b460d | 8025 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 8026 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8027 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8028 | } |
198a037f | 8029 | |
3d6e9ee0 VS |
8030 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8031 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8032 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8033 | |
37a5650b | 8034 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8035 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8036 | |
8037 | /* compute bitmask from p1 value */ | |
8038 | if (IS_PINEVIEW(dev)) | |
8039 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
8040 | else { | |
8041 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8042 | if (IS_G4X(dev) && reduced_clock) | |
8043 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
8044 | } | |
8045 | switch (clock->p2) { | |
8046 | case 5: | |
8047 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8048 | break; | |
8049 | case 7: | |
8050 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8051 | break; | |
8052 | case 10: | |
8053 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8054 | break; | |
8055 | case 14: | |
8056 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8057 | break; | |
8058 | } | |
8059 | if (INTEL_INFO(dev)->gen >= 4) | |
8060 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
8061 | ||
190f68c5 | 8062 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8063 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8064 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8065 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8066 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8067 | else | |
8068 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8069 | ||
8070 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8071 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8072 | |
eb1cbe48 | 8073 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 8074 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8075 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8076 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8077 | } |
8078 | } | |
8079 | ||
251ac862 DV |
8080 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8081 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8082 | struct dpll *reduced_clock) |
eb1cbe48 | 8083 | { |
f47709a9 | 8084 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8085 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8086 | u32 dpll; |
190f68c5 | 8087 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8088 | |
190f68c5 | 8089 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8090 | |
eb1cbe48 DV |
8091 | dpll = DPLL_VGA_MODE_DIS; |
8092 | ||
2d84d2b3 | 8093 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8094 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8095 | } else { | |
8096 | if (clock->p1 == 2) | |
8097 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8098 | else | |
8099 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8100 | if (clock->p2 == 4) | |
8101 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8102 | } | |
8103 | ||
2d84d2b3 | 8104 | if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
8105 | dpll |= DPLL_DVO_2X_MODE; |
8106 | ||
2d84d2b3 | 8107 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8108 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8109 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8110 | else | |
8111 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8112 | ||
8113 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8114 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8115 | } |
8116 | ||
8a654f3b | 8117 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
8118 | { |
8119 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8120 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 8121 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8122 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 8123 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
8124 | uint32_t crtc_vtotal, crtc_vblank_end; |
8125 | int vsyncshift = 0; | |
4d8a62ea DV |
8126 | |
8127 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8128 | * the hw state checker will get angry at the mismatch. */ | |
8129 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8130 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8131 | |
609aeaca | 8132 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8133 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8134 | crtc_vtotal -= 1; |
8135 | crtc_vblank_end -= 1; | |
609aeaca | 8136 | |
2d84d2b3 | 8137 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8138 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8139 | else | |
8140 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8141 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8142 | if (vsyncshift < 0) |
8143 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8144 | } |
8145 | ||
8146 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 8147 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 8148 | |
fe2b8f9d | 8149 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
8150 | (adjusted_mode->crtc_hdisplay - 1) | |
8151 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 8152 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
8153 | (adjusted_mode->crtc_hblank_start - 1) | |
8154 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 8155 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
8156 | (adjusted_mode->crtc_hsync_start - 1) | |
8157 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8158 | ||
fe2b8f9d | 8159 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 8160 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 8161 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 8162 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 8163 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 8164 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 8165 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
8166 | (adjusted_mode->crtc_vsync_start - 1) | |
8167 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
8168 | ||
b5e508d4 PZ |
8169 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8170 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8171 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8172 | * bits. */ | |
8173 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
8174 | (pipe == PIPE_B || pipe == PIPE_C)) | |
8175 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
8176 | ||
bc58be60 JN |
8177 | } |
8178 | ||
8179 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
8180 | { | |
8181 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8182 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
8183 | enum pipe pipe = intel_crtc->pipe; |
8184 | ||
b0e77b9c PZ |
8185 | /* pipesrc controls the size that is scaled from, which should |
8186 | * always be the user's requested size. | |
8187 | */ | |
8188 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
8189 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
8190 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
8191 | } |
8192 | ||
1bd1bd80 | 8193 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 8194 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
8195 | { |
8196 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8197 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
8198 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
8199 | uint32_t tmp; | |
8200 | ||
8201 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8202 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
8203 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8204 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
8205 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
8206 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8207 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
8208 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
8209 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8210 | |
8211 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8212 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
8213 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8214 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
8215 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
8216 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8217 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
8218 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8219 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8220 | |
8221 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
8222 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8223 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
8224 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8225 | } |
bc58be60 JN |
8226 | } |
8227 | ||
8228 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8229 | struct intel_crtc_state *pipe_config) | |
8230 | { | |
8231 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8232 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8233 | u32 tmp; |
1bd1bd80 DV |
8234 | |
8235 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
8236 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8237 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8238 | ||
2d112de7 ACO |
8239 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8240 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8241 | } |
8242 | ||
f6a83288 | 8243 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8244 | struct intel_crtc_state *pipe_config) |
babea61d | 8245 | { |
2d112de7 ACO |
8246 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8247 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8248 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8249 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8250 | |
2d112de7 ACO |
8251 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8252 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8253 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8254 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8255 | |
2d112de7 | 8256 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8257 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8258 | |
2d112de7 ACO |
8259 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8260 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8261 | |
8262 | mode->hsync = drm_mode_hsync(mode); | |
8263 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8264 | drm_mode_set_name(mode); | |
babea61d JB |
8265 | } |
8266 | ||
84b046f3 DV |
8267 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8268 | { | |
8269 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8270 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
8271 | uint32_t pipeconf; |
8272 | ||
9f11a9e4 | 8273 | pipeconf = 0; |
84b046f3 | 8274 | |
b6b5d049 VS |
8275 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8276 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8277 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8278 | |
6e3c9717 | 8279 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8280 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8281 | |
ff9ce46e | 8282 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 8283 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 8284 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8285 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8286 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8287 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8288 | |
6e3c9717 | 8289 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8290 | case 18: |
8291 | pipeconf |= PIPECONF_6BPC; | |
8292 | break; | |
8293 | case 24: | |
8294 | pipeconf |= PIPECONF_8BPC; | |
8295 | break; | |
8296 | case 30: | |
8297 | pipeconf |= PIPECONF_10BPC; | |
8298 | break; | |
8299 | default: | |
8300 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8301 | BUG(); | |
84b046f3 DV |
8302 | } |
8303 | } | |
8304 | ||
8305 | if (HAS_PIPE_CXSR(dev)) { | |
8306 | if (intel_crtc->lowfreq_avail) { | |
8307 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8308 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8309 | } else { | |
8310 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8311 | } |
8312 | } | |
8313 | ||
6e3c9717 | 8314 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 8315 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 8316 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8317 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8318 | else | |
8319 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8320 | } else | |
84b046f3 DV |
8321 | pipeconf |= PIPECONF_PROGRESSIVE; |
8322 | ||
666a4537 WB |
8323 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8324 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 8325 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8326 | |
84b046f3 DV |
8327 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8328 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8329 | } | |
8330 | ||
81c97f52 ACO |
8331 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8332 | struct intel_crtc_state *crtc_state) | |
8333 | { | |
8334 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8335 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8336 | const struct intel_limit *limit; |
81c97f52 ACO |
8337 | int refclk = 48000; |
8338 | ||
8339 | memset(&crtc_state->dpll_hw_state, 0, | |
8340 | sizeof(crtc_state->dpll_hw_state)); | |
8341 | ||
2d84d2b3 | 8342 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8343 | if (intel_panel_use_ssc(dev_priv)) { |
8344 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8345 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8346 | } | |
8347 | ||
8348 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8349 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8350 | limit = &intel_limits_i8xx_dvo; |
8351 | } else { | |
8352 | limit = &intel_limits_i8xx_dac; | |
8353 | } | |
8354 | ||
8355 | if (!crtc_state->clock_set && | |
8356 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8357 | refclk, NULL, &crtc_state->dpll)) { | |
8358 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8359 | return -EINVAL; | |
8360 | } | |
8361 | ||
8362 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8363 | ||
8364 | return 0; | |
8365 | } | |
8366 | ||
19ec6693 ACO |
8367 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8368 | struct intel_crtc_state *crtc_state) | |
8369 | { | |
8370 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8371 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8372 | const struct intel_limit *limit; |
19ec6693 ACO |
8373 | int refclk = 96000; |
8374 | ||
8375 | memset(&crtc_state->dpll_hw_state, 0, | |
8376 | sizeof(crtc_state->dpll_hw_state)); | |
8377 | ||
2d84d2b3 | 8378 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8379 | if (intel_panel_use_ssc(dev_priv)) { |
8380 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8381 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8382 | } | |
8383 | ||
8384 | if (intel_is_dual_link_lvds(dev)) | |
8385 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8386 | else | |
8387 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8388 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8389 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8390 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8391 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8392 | limit = &intel_limits_g4x_sdvo; |
8393 | } else { | |
8394 | /* The option is for other outputs */ | |
8395 | limit = &intel_limits_i9xx_sdvo; | |
8396 | } | |
8397 | ||
8398 | if (!crtc_state->clock_set && | |
8399 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8400 | refclk, NULL, &crtc_state->dpll)) { | |
8401 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8402 | return -EINVAL; | |
8403 | } | |
8404 | ||
8405 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8406 | ||
8407 | return 0; | |
8408 | } | |
8409 | ||
70e8aa21 ACO |
8410 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8411 | struct intel_crtc_state *crtc_state) | |
8412 | { | |
8413 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8414 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8415 | const struct intel_limit *limit; |
70e8aa21 ACO |
8416 | int refclk = 96000; |
8417 | ||
8418 | memset(&crtc_state->dpll_hw_state, 0, | |
8419 | sizeof(crtc_state->dpll_hw_state)); | |
8420 | ||
2d84d2b3 | 8421 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8422 | if (intel_panel_use_ssc(dev_priv)) { |
8423 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8424 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8425 | } | |
8426 | ||
8427 | limit = &intel_limits_pineview_lvds; | |
8428 | } else { | |
8429 | limit = &intel_limits_pineview_sdvo; | |
8430 | } | |
8431 | ||
8432 | if (!crtc_state->clock_set && | |
8433 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8434 | refclk, NULL, &crtc_state->dpll)) { | |
8435 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8436 | return -EINVAL; | |
8437 | } | |
8438 | ||
8439 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8440 | ||
8441 | return 0; | |
8442 | } | |
8443 | ||
190f68c5 ACO |
8444 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8445 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8446 | { |
c7653199 | 8447 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8448 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8449 | const struct intel_limit *limit; |
81c97f52 | 8450 | int refclk = 96000; |
79e53945 | 8451 | |
dd3cd74a ACO |
8452 | memset(&crtc_state->dpll_hw_state, 0, |
8453 | sizeof(crtc_state->dpll_hw_state)); | |
8454 | ||
2d84d2b3 | 8455 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8456 | if (intel_panel_use_ssc(dev_priv)) { |
8457 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8458 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8459 | } | |
43565a06 | 8460 | |
70e8aa21 ACO |
8461 | limit = &intel_limits_i9xx_lvds; |
8462 | } else { | |
8463 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8464 | } |
79e53945 | 8465 | |
70e8aa21 ACO |
8466 | if (!crtc_state->clock_set && |
8467 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8468 | refclk, NULL, &crtc_state->dpll)) { | |
8469 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8470 | return -EINVAL; | |
f47709a9 | 8471 | } |
7026d4ac | 8472 | |
81c97f52 | 8473 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8474 | |
c8f7a0db | 8475 | return 0; |
f564048e EA |
8476 | } |
8477 | ||
65b3d6a9 ACO |
8478 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8479 | struct intel_crtc_state *crtc_state) | |
8480 | { | |
8481 | int refclk = 100000; | |
1b6f4958 | 8482 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8483 | |
8484 | memset(&crtc_state->dpll_hw_state, 0, | |
8485 | sizeof(crtc_state->dpll_hw_state)); | |
8486 | ||
65b3d6a9 ACO |
8487 | if (!crtc_state->clock_set && |
8488 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8489 | refclk, NULL, &crtc_state->dpll)) { | |
8490 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8491 | return -EINVAL; | |
8492 | } | |
8493 | ||
8494 | chv_compute_dpll(crtc, crtc_state); | |
8495 | ||
8496 | return 0; | |
8497 | } | |
8498 | ||
8499 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8500 | struct intel_crtc_state *crtc_state) | |
8501 | { | |
8502 | int refclk = 100000; | |
1b6f4958 | 8503 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8504 | |
8505 | memset(&crtc_state->dpll_hw_state, 0, | |
8506 | sizeof(crtc_state->dpll_hw_state)); | |
8507 | ||
65b3d6a9 ACO |
8508 | if (!crtc_state->clock_set && |
8509 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8510 | refclk, NULL, &crtc_state->dpll)) { | |
8511 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8512 | return -EINVAL; | |
8513 | } | |
8514 | ||
8515 | vlv_compute_dpll(crtc, crtc_state); | |
8516 | ||
8517 | return 0; | |
8518 | } | |
8519 | ||
2fa2fe9a | 8520 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8521 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8522 | { |
8523 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8524 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8525 | uint32_t tmp; |
8526 | ||
dc9e7dec VS |
8527 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8528 | return; | |
8529 | ||
2fa2fe9a | 8530 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8531 | if (!(tmp & PFIT_ENABLE)) |
8532 | return; | |
2fa2fe9a | 8533 | |
06922821 | 8534 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8535 | if (INTEL_INFO(dev)->gen < 4) { |
8536 | if (crtc->pipe != PIPE_B) | |
8537 | return; | |
2fa2fe9a DV |
8538 | } else { |
8539 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8540 | return; | |
8541 | } | |
8542 | ||
06922821 | 8543 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8544 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8545 | } |
8546 | ||
acbec814 | 8547 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8548 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8549 | { |
8550 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8551 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8552 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8553 | struct dpll clock; |
acbec814 | 8554 | u32 mdiv; |
662c6ecb | 8555 | int refclk = 100000; |
acbec814 | 8556 | |
b521973b VS |
8557 | /* In case of DSI, DPLL will not be used */ |
8558 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8559 | return; |
8560 | ||
a580516d | 8561 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8562 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8563 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8564 | |
8565 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8566 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8567 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8568 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8569 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8570 | ||
dccbea3b | 8571 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8572 | } |
8573 | ||
5724dbd1 DL |
8574 | static void |
8575 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8576 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8577 | { |
8578 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8579 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8580 | u32 val, base, offset; |
8581 | int pipe = crtc->pipe, plane = crtc->plane; | |
8582 | int fourcc, pixel_format; | |
6761dd31 | 8583 | unsigned int aligned_height; |
b113d5ee | 8584 | struct drm_framebuffer *fb; |
1b842c89 | 8585 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8586 | |
42a7b088 DL |
8587 | val = I915_READ(DSPCNTR(plane)); |
8588 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8589 | return; | |
8590 | ||
d9806c9f | 8591 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8592 | if (!intel_fb) { |
1ad292b5 JB |
8593 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8594 | return; | |
8595 | } | |
8596 | ||
1b842c89 DL |
8597 | fb = &intel_fb->base; |
8598 | ||
18c5247e DV |
8599 | if (INTEL_INFO(dev)->gen >= 4) { |
8600 | if (val & DISPPLANE_TILED) { | |
49af449b | 8601 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8602 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8603 | } | |
8604 | } | |
1ad292b5 JB |
8605 | |
8606 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8607 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8608 | fb->pixel_format = fourcc; |
8609 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8610 | |
8611 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8612 | if (plane_config->tiling) |
1ad292b5 JB |
8613 | offset = I915_READ(DSPTILEOFF(plane)); |
8614 | else | |
8615 | offset = I915_READ(DSPLINOFF(plane)); | |
8616 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8617 | } else { | |
8618 | base = I915_READ(DSPADDR(plane)); | |
8619 | } | |
8620 | plane_config->base = base; | |
8621 | ||
8622 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8623 | fb->width = ((val >> 16) & 0xfff) + 1; |
8624 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8625 | |
8626 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8627 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8628 | |
b113d5ee | 8629 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8630 | fb->pixel_format, |
8631 | fb->modifier[0]); | |
1ad292b5 | 8632 | |
f37b5c2b | 8633 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8634 | |
2844a921 DL |
8635 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8636 | pipe_name(pipe), plane, fb->width, fb->height, | |
8637 | fb->bits_per_pixel, base, fb->pitches[0], | |
8638 | plane_config->size); | |
1ad292b5 | 8639 | |
2d14030b | 8640 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8641 | } |
8642 | ||
70b23a98 | 8643 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8644 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8645 | { |
8646 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8647 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8648 | int pipe = pipe_config->cpu_transcoder; |
8649 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8650 | struct dpll clock; |
0d7b6b11 | 8651 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8652 | int refclk = 100000; |
8653 | ||
b521973b VS |
8654 | /* In case of DSI, DPLL will not be used */ |
8655 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8656 | return; | |
8657 | ||
a580516d | 8658 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8659 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8660 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8661 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8662 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8663 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8664 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8665 | |
8666 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8667 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8668 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8669 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8670 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8671 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8672 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8673 | ||
dccbea3b | 8674 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8675 | } |
8676 | ||
0e8ffe1b | 8677 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8678 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8679 | { |
8680 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8681 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8682 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8683 | uint32_t tmp; |
1729050e | 8684 | bool ret; |
0e8ffe1b | 8685 | |
1729050e ID |
8686 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8687 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8688 | return false; |
8689 | ||
e143a21c | 8690 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8691 | pipe_config->shared_dpll = NULL; |
eccb140b | 8692 | |
1729050e ID |
8693 | ret = false; |
8694 | ||
0e8ffe1b DV |
8695 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8696 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8697 | goto out; |
0e8ffe1b | 8698 | |
666a4537 | 8699 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8700 | switch (tmp & PIPECONF_BPC_MASK) { |
8701 | case PIPECONF_6BPC: | |
8702 | pipe_config->pipe_bpp = 18; | |
8703 | break; | |
8704 | case PIPECONF_8BPC: | |
8705 | pipe_config->pipe_bpp = 24; | |
8706 | break; | |
8707 | case PIPECONF_10BPC: | |
8708 | pipe_config->pipe_bpp = 30; | |
8709 | break; | |
8710 | default: | |
8711 | break; | |
8712 | } | |
8713 | } | |
8714 | ||
666a4537 WB |
8715 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8716 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8717 | pipe_config->limited_color_range = true; |
8718 | ||
282740f7 VS |
8719 | if (INTEL_INFO(dev)->gen < 4) |
8720 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8721 | ||
1bd1bd80 | 8722 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8723 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8724 | |
2fa2fe9a DV |
8725 | i9xx_get_pfit_config(crtc, pipe_config); |
8726 | ||
6c49f241 | 8727 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8728 | /* No way to read it out on pipes B and C */ |
8729 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8730 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8731 | else | |
8732 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8733 | pipe_config->pixel_multiplier = |
8734 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8735 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8736 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8737 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8738 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8739 | pipe_config->pixel_multiplier = | |
8740 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8741 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8742 | } else { | |
8743 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8744 | * port and will be fixed up in the encoder->get_config | |
8745 | * function. */ | |
8746 | pipe_config->pixel_multiplier = 1; | |
8747 | } | |
8bcc2795 | 8748 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8749 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8750 | /* |
8751 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8752 | * on 830. Filter it out here so that we don't | |
8753 | * report errors due to that. | |
8754 | */ | |
8755 | if (IS_I830(dev)) | |
8756 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8757 | ||
8bcc2795 DV |
8758 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8759 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8760 | } else { |
8761 | /* Mask out read-only status bits. */ | |
8762 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8763 | DPLL_PORTC_READY_MASK | | |
8764 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8765 | } |
6c49f241 | 8766 | |
70b23a98 VS |
8767 | if (IS_CHERRYVIEW(dev)) |
8768 | chv_crtc_clock_get(crtc, pipe_config); | |
8769 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8770 | vlv_crtc_clock_get(crtc, pipe_config); |
8771 | else | |
8772 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8773 | |
0f64614d VS |
8774 | /* |
8775 | * Normally the dotclock is filled in by the encoder .get_config() | |
8776 | * but in case the pipe is enabled w/o any ports we need a sane | |
8777 | * default. | |
8778 | */ | |
8779 | pipe_config->base.adjusted_mode.crtc_clock = | |
8780 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8781 | ||
1729050e ID |
8782 | ret = true; |
8783 | ||
8784 | out: | |
8785 | intel_display_power_put(dev_priv, power_domain); | |
8786 | ||
8787 | return ret; | |
0e8ffe1b DV |
8788 | } |
8789 | ||
dde86e2d | 8790 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8791 | { |
fac5e23e | 8792 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8793 | struct intel_encoder *encoder; |
1c1a24d2 | 8794 | int i; |
74cfd7ac | 8795 | u32 val, final; |
13d83a67 | 8796 | bool has_lvds = false; |
199e5d79 | 8797 | bool has_cpu_edp = false; |
199e5d79 | 8798 | bool has_panel = false; |
99eb6a01 KP |
8799 | bool has_ck505 = false; |
8800 | bool can_ssc = false; | |
1c1a24d2 | 8801 | bool using_ssc_source = false; |
13d83a67 JB |
8802 | |
8803 | /* We need to take the global config into account */ | |
b2784e15 | 8804 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8805 | switch (encoder->type) { |
8806 | case INTEL_OUTPUT_LVDS: | |
8807 | has_panel = true; | |
8808 | has_lvds = true; | |
8809 | break; | |
8810 | case INTEL_OUTPUT_EDP: | |
8811 | has_panel = true; | |
2de6905f | 8812 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8813 | has_cpu_edp = true; |
8814 | break; | |
6847d71b PZ |
8815 | default: |
8816 | break; | |
13d83a67 JB |
8817 | } |
8818 | } | |
8819 | ||
99eb6a01 | 8820 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8821 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8822 | can_ssc = has_ck505; |
8823 | } else { | |
8824 | has_ck505 = false; | |
8825 | can_ssc = true; | |
8826 | } | |
8827 | ||
1c1a24d2 L |
8828 | /* Check if any DPLLs are using the SSC source */ |
8829 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8830 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8831 | ||
8832 | if (!(temp & DPLL_VCO_ENABLE)) | |
8833 | continue; | |
8834 | ||
8835 | if ((temp & PLL_REF_INPUT_MASK) == | |
8836 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8837 | using_ssc_source = true; | |
8838 | break; | |
8839 | } | |
8840 | } | |
8841 | ||
8842 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8843 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8844 | |
8845 | /* Ironlake: try to setup display ref clock before DPLL | |
8846 | * enabling. This is only under driver's control after | |
8847 | * PCH B stepping, previous chipset stepping should be | |
8848 | * ignoring this setting. | |
8849 | */ | |
74cfd7ac CW |
8850 | val = I915_READ(PCH_DREF_CONTROL); |
8851 | ||
8852 | /* As we must carefully and slowly disable/enable each source in turn, | |
8853 | * compute the final state we want first and check if we need to | |
8854 | * make any changes at all. | |
8855 | */ | |
8856 | final = val; | |
8857 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8858 | if (has_ck505) | |
8859 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8860 | else | |
8861 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8862 | ||
8c07eb68 | 8863 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8864 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8865 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8866 | |
8867 | if (has_panel) { | |
8868 | final |= DREF_SSC_SOURCE_ENABLE; | |
8869 | ||
8870 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8871 | final |= DREF_SSC1_ENABLE; | |
8872 | ||
8873 | if (has_cpu_edp) { | |
8874 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8875 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8876 | else | |
8877 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8878 | } else | |
8879 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8880 | } else if (using_ssc_source) { |
8881 | final |= DREF_SSC_SOURCE_ENABLE; | |
8882 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8883 | } |
8884 | ||
8885 | if (final == val) | |
8886 | return; | |
8887 | ||
13d83a67 | 8888 | /* Always enable nonspread source */ |
74cfd7ac | 8889 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8890 | |
99eb6a01 | 8891 | if (has_ck505) |
74cfd7ac | 8892 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8893 | else |
74cfd7ac | 8894 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8895 | |
199e5d79 | 8896 | if (has_panel) { |
74cfd7ac CW |
8897 | val &= ~DREF_SSC_SOURCE_MASK; |
8898 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8899 | |
199e5d79 | 8900 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8901 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8902 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8903 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8904 | } else |
74cfd7ac | 8905 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8906 | |
8907 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8908 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8909 | POSTING_READ(PCH_DREF_CONTROL); |
8910 | udelay(200); | |
8911 | ||
74cfd7ac | 8912 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8913 | |
8914 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8915 | if (has_cpu_edp) { |
99eb6a01 | 8916 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8917 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8918 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8919 | } else |
74cfd7ac | 8920 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8921 | } else |
74cfd7ac | 8922 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8923 | |
74cfd7ac | 8924 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8925 | POSTING_READ(PCH_DREF_CONTROL); |
8926 | udelay(200); | |
8927 | } else { | |
1c1a24d2 | 8928 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 8929 | |
74cfd7ac | 8930 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8931 | |
8932 | /* Turn off CPU output */ | |
74cfd7ac | 8933 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8934 | |
74cfd7ac | 8935 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8936 | POSTING_READ(PCH_DREF_CONTROL); |
8937 | udelay(200); | |
8938 | ||
1c1a24d2 L |
8939 | if (!using_ssc_source) { |
8940 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 8941 | |
1c1a24d2 L |
8942 | /* Turn off the SSC source */ |
8943 | val &= ~DREF_SSC_SOURCE_MASK; | |
8944 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 8945 | |
1c1a24d2 L |
8946 | /* Turn off SSC1 */ |
8947 | val &= ~DREF_SSC1_ENABLE; | |
8948 | ||
8949 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8950 | POSTING_READ(PCH_DREF_CONTROL); | |
8951 | udelay(200); | |
8952 | } | |
13d83a67 | 8953 | } |
74cfd7ac CW |
8954 | |
8955 | BUG_ON(val != final); | |
13d83a67 JB |
8956 | } |
8957 | ||
f31f2d55 | 8958 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8959 | { |
f31f2d55 | 8960 | uint32_t tmp; |
dde86e2d | 8961 | |
0ff066a9 PZ |
8962 | tmp = I915_READ(SOUTH_CHICKEN2); |
8963 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8964 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8965 | |
cf3598c2 ID |
8966 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
8967 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 8968 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 8969 | |
0ff066a9 PZ |
8970 | tmp = I915_READ(SOUTH_CHICKEN2); |
8971 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8972 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8973 | |
cf3598c2 ID |
8974 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
8975 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 8976 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
8977 | } |
8978 | ||
8979 | /* WaMPhyProgramming:hsw */ | |
8980 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8981 | { | |
8982 | uint32_t tmp; | |
dde86e2d PZ |
8983 | |
8984 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8985 | tmp &= ~(0xFF << 24); | |
8986 | tmp |= (0x12 << 24); | |
8987 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8988 | ||
dde86e2d PZ |
8989 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8990 | tmp |= (1 << 11); | |
8991 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8992 | ||
8993 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8994 | tmp |= (1 << 11); | |
8995 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8996 | ||
dde86e2d PZ |
8997 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8998 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8999 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9000 | ||
9001 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9002 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9003 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9004 | ||
0ff066a9 PZ |
9005 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9006 | tmp &= ~(7 << 13); | |
9007 | tmp |= (5 << 13); | |
9008 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9009 | |
0ff066a9 PZ |
9010 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9011 | tmp &= ~(7 << 13); | |
9012 | tmp |= (5 << 13); | |
9013 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9014 | |
9015 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9016 | tmp &= ~0xFF; | |
9017 | tmp |= 0x1C; | |
9018 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9019 | ||
9020 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9021 | tmp &= ~0xFF; | |
9022 | tmp |= 0x1C; | |
9023 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9024 | ||
9025 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9026 | tmp &= ~(0xFF << 16); | |
9027 | tmp |= (0x1C << 16); | |
9028 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9029 | ||
9030 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9031 | tmp &= ~(0xFF << 16); | |
9032 | tmp |= (0x1C << 16); | |
9033 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9034 | ||
0ff066a9 PZ |
9035 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9036 | tmp |= (1 << 27); | |
9037 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9038 | |
0ff066a9 PZ |
9039 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9040 | tmp |= (1 << 27); | |
9041 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9042 | |
0ff066a9 PZ |
9043 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9044 | tmp &= ~(0xF << 28); | |
9045 | tmp |= (4 << 28); | |
9046 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9047 | |
0ff066a9 PZ |
9048 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9049 | tmp &= ~(0xF << 28); | |
9050 | tmp |= (4 << 28); | |
9051 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9052 | } |
9053 | ||
2fa86a1f PZ |
9054 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9055 | * Programming" based on the parameters passed: | |
9056 | * - Sequence to enable CLKOUT_DP | |
9057 | * - Sequence to enable CLKOUT_DP without spread | |
9058 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9059 | */ | |
9060 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
9061 | bool with_fdi) | |
f31f2d55 | 9062 | { |
fac5e23e | 9063 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
9064 | uint32_t reg, tmp; |
9065 | ||
9066 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
9067 | with_spread = true; | |
c2699524 | 9068 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 9069 | with_fdi = false; |
f31f2d55 | 9070 | |
a580516d | 9071 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9072 | |
9073 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9074 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9075 | tmp |= SBI_SSCCTL_PATHALT; | |
9076 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9077 | ||
9078 | udelay(24); | |
9079 | ||
2fa86a1f PZ |
9080 | if (with_spread) { |
9081 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9082 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9083 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9084 | |
2fa86a1f PZ |
9085 | if (with_fdi) { |
9086 | lpt_reset_fdi_mphy(dev_priv); | |
9087 | lpt_program_fdi_mphy(dev_priv); | |
9088 | } | |
9089 | } | |
dde86e2d | 9090 | |
c2699524 | 9091 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9092 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9093 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9094 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9095 | |
a580516d | 9096 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9097 | } |
9098 | ||
47701c3b PZ |
9099 | /* Sequence to disable CLKOUT_DP */ |
9100 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
9101 | { | |
fac5e23e | 9102 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
9103 | uint32_t reg, tmp; |
9104 | ||
a580516d | 9105 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9106 | |
c2699524 | 9107 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9108 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9109 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9110 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
9111 | ||
9112 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9113 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
9114 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
9115 | tmp |= SBI_SSCCTL_PATHALT; | |
9116 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9117 | udelay(32); | |
9118 | } | |
9119 | tmp |= SBI_SSCCTL_DISABLE; | |
9120 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9121 | } | |
9122 | ||
a580516d | 9123 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
9124 | } |
9125 | ||
f7be2c21 VS |
9126 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
9127 | ||
9128 | static const uint16_t sscdivintphase[] = { | |
9129 | [BEND_IDX( 50)] = 0x3B23, | |
9130 | [BEND_IDX( 45)] = 0x3B23, | |
9131 | [BEND_IDX( 40)] = 0x3C23, | |
9132 | [BEND_IDX( 35)] = 0x3C23, | |
9133 | [BEND_IDX( 30)] = 0x3D23, | |
9134 | [BEND_IDX( 25)] = 0x3D23, | |
9135 | [BEND_IDX( 20)] = 0x3E23, | |
9136 | [BEND_IDX( 15)] = 0x3E23, | |
9137 | [BEND_IDX( 10)] = 0x3F23, | |
9138 | [BEND_IDX( 5)] = 0x3F23, | |
9139 | [BEND_IDX( 0)] = 0x0025, | |
9140 | [BEND_IDX( -5)] = 0x0025, | |
9141 | [BEND_IDX(-10)] = 0x0125, | |
9142 | [BEND_IDX(-15)] = 0x0125, | |
9143 | [BEND_IDX(-20)] = 0x0225, | |
9144 | [BEND_IDX(-25)] = 0x0225, | |
9145 | [BEND_IDX(-30)] = 0x0325, | |
9146 | [BEND_IDX(-35)] = 0x0325, | |
9147 | [BEND_IDX(-40)] = 0x0425, | |
9148 | [BEND_IDX(-45)] = 0x0425, | |
9149 | [BEND_IDX(-50)] = 0x0525, | |
9150 | }; | |
9151 | ||
9152 | /* | |
9153 | * Bend CLKOUT_DP | |
9154 | * steps -50 to 50 inclusive, in steps of 5 | |
9155 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
9156 | * change in clock period = -(steps / 10) * 5.787 ps | |
9157 | */ | |
9158 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
9159 | { | |
9160 | uint32_t tmp; | |
9161 | int idx = BEND_IDX(steps); | |
9162 | ||
9163 | if (WARN_ON(steps % 5 != 0)) | |
9164 | return; | |
9165 | ||
9166 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
9167 | return; | |
9168 | ||
9169 | mutex_lock(&dev_priv->sb_lock); | |
9170 | ||
9171 | if (steps % 10 != 0) | |
9172 | tmp = 0xAAAAAAAB; | |
9173 | else | |
9174 | tmp = 0x00000000; | |
9175 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
9176 | ||
9177 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
9178 | tmp &= 0xffff0000; | |
9179 | tmp |= sscdivintphase[idx]; | |
9180 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
9181 | ||
9182 | mutex_unlock(&dev_priv->sb_lock); | |
9183 | } | |
9184 | ||
9185 | #undef BEND_IDX | |
9186 | ||
bf8fa3d3 PZ |
9187 | static void lpt_init_pch_refclk(struct drm_device *dev) |
9188 | { | |
bf8fa3d3 PZ |
9189 | struct intel_encoder *encoder; |
9190 | bool has_vga = false; | |
9191 | ||
b2784e15 | 9192 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
9193 | switch (encoder->type) { |
9194 | case INTEL_OUTPUT_ANALOG: | |
9195 | has_vga = true; | |
9196 | break; | |
6847d71b PZ |
9197 | default: |
9198 | break; | |
bf8fa3d3 PZ |
9199 | } |
9200 | } | |
9201 | ||
f7be2c21 VS |
9202 | if (has_vga) { |
9203 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 9204 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 9205 | } else { |
47701c3b | 9206 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 9207 | } |
bf8fa3d3 PZ |
9208 | } |
9209 | ||
dde86e2d PZ |
9210 | /* |
9211 | * Initialize reference clocks when the driver loads | |
9212 | */ | |
9213 | void intel_init_pch_refclk(struct drm_device *dev) | |
9214 | { | |
9215 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
9216 | ironlake_init_pch_refclk(dev); | |
9217 | else if (HAS_PCH_LPT(dev)) | |
9218 | lpt_init_pch_refclk(dev); | |
9219 | } | |
9220 | ||
6ff93609 | 9221 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 9222 | { |
fac5e23e | 9223 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
9224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9225 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
9226 | uint32_t val; |
9227 | ||
78114071 | 9228 | val = 0; |
c8203565 | 9229 | |
6e3c9717 | 9230 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 9231 | case 18: |
dfd07d72 | 9232 | val |= PIPECONF_6BPC; |
c8203565 PZ |
9233 | break; |
9234 | case 24: | |
dfd07d72 | 9235 | val |= PIPECONF_8BPC; |
c8203565 PZ |
9236 | break; |
9237 | case 30: | |
dfd07d72 | 9238 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9239 | break; |
9240 | case 36: | |
dfd07d72 | 9241 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9242 | break; |
9243 | default: | |
cc769b62 PZ |
9244 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9245 | BUG(); | |
c8203565 PZ |
9246 | } |
9247 | ||
6e3c9717 | 9248 | if (intel_crtc->config->dither) |
c8203565 PZ |
9249 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9250 | ||
6e3c9717 | 9251 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9252 | val |= PIPECONF_INTERLACED_ILK; |
9253 | else | |
9254 | val |= PIPECONF_PROGRESSIVE; | |
9255 | ||
6e3c9717 | 9256 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9257 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9258 | |
c8203565 PZ |
9259 | I915_WRITE(PIPECONF(pipe), val); |
9260 | POSTING_READ(PIPECONF(pipe)); | |
9261 | } | |
9262 | ||
6ff93609 | 9263 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9264 | { |
fac5e23e | 9265 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9267 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9268 | u32 val = 0; |
ee2b0b38 | 9269 | |
391bf048 | 9270 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9271 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9272 | ||
6e3c9717 | 9273 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9274 | val |= PIPECONF_INTERLACED_ILK; |
9275 | else | |
9276 | val |= PIPECONF_PROGRESSIVE; | |
9277 | ||
702e7a56 PZ |
9278 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9279 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9280 | } |
9281 | ||
391bf048 JN |
9282 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9283 | { | |
fac5e23e | 9284 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9286 | |
391bf048 JN |
9287 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9288 | u32 val = 0; | |
756f85cf | 9289 | |
6e3c9717 | 9290 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9291 | case 18: |
9292 | val |= PIPEMISC_DITHER_6_BPC; | |
9293 | break; | |
9294 | case 24: | |
9295 | val |= PIPEMISC_DITHER_8_BPC; | |
9296 | break; | |
9297 | case 30: | |
9298 | val |= PIPEMISC_DITHER_10_BPC; | |
9299 | break; | |
9300 | case 36: | |
9301 | val |= PIPEMISC_DITHER_12_BPC; | |
9302 | break; | |
9303 | default: | |
9304 | /* Case prevented by pipe_config_set_bpp. */ | |
9305 | BUG(); | |
9306 | } | |
9307 | ||
6e3c9717 | 9308 | if (intel_crtc->config->dither) |
756f85cf PZ |
9309 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9310 | ||
391bf048 | 9311 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9312 | } |
ee2b0b38 PZ |
9313 | } |
9314 | ||
d4b1931c PZ |
9315 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9316 | { | |
9317 | /* | |
9318 | * Account for spread spectrum to avoid | |
9319 | * oversubscribing the link. Max center spread | |
9320 | * is 2.5%; use 5% for safety's sake. | |
9321 | */ | |
9322 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9323 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9324 | } |
9325 | ||
7429e9d4 | 9326 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9327 | { |
7429e9d4 | 9328 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9329 | } |
9330 | ||
b75ca6f6 ACO |
9331 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9332 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9333 | struct dpll *reduced_clock) |
79e53945 | 9334 | { |
de13a2e3 | 9335 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9336 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9337 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9338 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9339 | int factor; |
79e53945 | 9340 | |
c1858123 | 9341 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9342 | factor = 21; |
3d6e9ee0 | 9343 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9344 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9345 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 9346 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9347 | factor = 25; |
190f68c5 | 9348 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9349 | factor = 20; |
c1858123 | 9350 | |
b75ca6f6 ACO |
9351 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9352 | ||
190f68c5 | 9353 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9354 | fp |= FP_CB_TUNE; |
9355 | ||
9356 | if (reduced_clock) { | |
9357 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9358 | |
b75ca6f6 ACO |
9359 | if (reduced_clock->m < factor * reduced_clock->n) |
9360 | fp2 |= FP_CB_TUNE; | |
9361 | } else { | |
9362 | fp2 = fp; | |
9363 | } | |
9a7c7890 | 9364 | |
5eddb70b | 9365 | dpll = 0; |
2c07245f | 9366 | |
3d6e9ee0 | 9367 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9368 | dpll |= DPLLB_MODE_LVDS; |
9369 | else | |
9370 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9371 | |
190f68c5 | 9372 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9373 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9374 | |
3d6e9ee0 VS |
9375 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9376 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9377 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9378 | |
37a5650b | 9379 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9380 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9381 | |
a07d6787 | 9382 | /* compute bitmask from p1 value */ |
190f68c5 | 9383 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9384 | /* also FPA1 */ |
190f68c5 | 9385 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9386 | |
190f68c5 | 9387 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9388 | case 5: |
9389 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9390 | break; | |
9391 | case 7: | |
9392 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9393 | break; | |
9394 | case 10: | |
9395 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9396 | break; | |
9397 | case 14: | |
9398 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9399 | break; | |
79e53945 JB |
9400 | } |
9401 | ||
3d6e9ee0 VS |
9402 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9403 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9404 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9405 | else |
9406 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9407 | ||
b75ca6f6 ACO |
9408 | dpll |= DPLL_VCO_ENABLE; |
9409 | ||
9410 | crtc_state->dpll_hw_state.dpll = dpll; | |
9411 | crtc_state->dpll_hw_state.fp0 = fp; | |
9412 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9413 | } |
9414 | ||
190f68c5 ACO |
9415 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9416 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9417 | { |
997c030c | 9418 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9419 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9420 | struct dpll reduced_clock; |
7ed9f894 | 9421 | bool has_reduced_clock = false; |
e2b78267 | 9422 | struct intel_shared_dpll *pll; |
1b6f4958 | 9423 | const struct intel_limit *limit; |
997c030c | 9424 | int refclk = 120000; |
de13a2e3 | 9425 | |
dd3cd74a ACO |
9426 | memset(&crtc_state->dpll_hw_state, 0, |
9427 | sizeof(crtc_state->dpll_hw_state)); | |
9428 | ||
ded220e2 ACO |
9429 | crtc->lowfreq_avail = false; |
9430 | ||
9431 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9432 | if (!crtc_state->has_pch_encoder) | |
9433 | return 0; | |
79e53945 | 9434 | |
2d84d2b3 | 9435 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9436 | if (intel_panel_use_ssc(dev_priv)) { |
9437 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9438 | dev_priv->vbt.lvds_ssc_freq); | |
9439 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9440 | } | |
9441 | ||
9442 | if (intel_is_dual_link_lvds(dev)) { | |
9443 | if (refclk == 100000) | |
9444 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9445 | else | |
9446 | limit = &intel_limits_ironlake_dual_lvds; | |
9447 | } else { | |
9448 | if (refclk == 100000) | |
9449 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9450 | else | |
9451 | limit = &intel_limits_ironlake_single_lvds; | |
9452 | } | |
9453 | } else { | |
9454 | limit = &intel_limits_ironlake_dac; | |
9455 | } | |
9456 | ||
364ee29d | 9457 | if (!crtc_state->clock_set && |
997c030c ACO |
9458 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9459 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9460 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9461 | return -EINVAL; | |
f47709a9 | 9462 | } |
79e53945 | 9463 | |
b75ca6f6 ACO |
9464 | ironlake_compute_dpll(crtc, crtc_state, |
9465 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9466 | |
ded220e2 ACO |
9467 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9468 | if (pll == NULL) { | |
9469 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9470 | pipe_name(crtc->pipe)); | |
9471 | return -EINVAL; | |
3fb37703 | 9472 | } |
79e53945 | 9473 | |
2d84d2b3 | 9474 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9475 | has_reduced_clock) |
c7653199 | 9476 | crtc->lowfreq_avail = true; |
e2b78267 | 9477 | |
c8f7a0db | 9478 | return 0; |
79e53945 JB |
9479 | } |
9480 | ||
eb14cb74 VS |
9481 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9482 | struct intel_link_m_n *m_n) | |
9483 | { | |
9484 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9485 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9486 | enum pipe pipe = crtc->pipe; |
9487 | ||
9488 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9489 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9490 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9491 | & ~TU_SIZE_MASK; | |
9492 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9493 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9494 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9495 | } | |
9496 | ||
9497 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9498 | enum transcoder transcoder, | |
b95af8be VK |
9499 | struct intel_link_m_n *m_n, |
9500 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9501 | { |
9502 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9503 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9504 | enum pipe pipe = crtc->pipe; |
72419203 | 9505 | |
eb14cb74 VS |
9506 | if (INTEL_INFO(dev)->gen >= 5) { |
9507 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9508 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9509 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9510 | & ~TU_SIZE_MASK; | |
9511 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9512 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9513 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9514 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9515 | * gen < 8) and if DRRS is supported (to make sure the | |
9516 | * registers are not unnecessarily read). | |
9517 | */ | |
9518 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9519 | crtc->config->has_drrs) { |
b95af8be VK |
9520 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9521 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9522 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9523 | & ~TU_SIZE_MASK; | |
9524 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9525 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9526 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9527 | } | |
eb14cb74 VS |
9528 | } else { |
9529 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9530 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9531 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9532 | & ~TU_SIZE_MASK; | |
9533 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9534 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9535 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9536 | } | |
9537 | } | |
9538 | ||
9539 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9540 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9541 | { |
681a8504 | 9542 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9543 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9544 | else | |
9545 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9546 | &pipe_config->dp_m_n, |
9547 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9548 | } |
72419203 | 9549 | |
eb14cb74 | 9550 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9551 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9552 | { |
9553 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9554 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9555 | } |
9556 | ||
bd2e244f | 9557 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9558 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9559 | { |
9560 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9561 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9562 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9563 | uint32_t ps_ctrl = 0; | |
9564 | int id = -1; | |
9565 | int i; | |
bd2e244f | 9566 | |
a1b2278e CK |
9567 | /* find scaler attached to this pipe */ |
9568 | for (i = 0; i < crtc->num_scalers; i++) { | |
9569 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9570 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9571 | id = i; | |
9572 | pipe_config->pch_pfit.enabled = true; | |
9573 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9574 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9575 | break; | |
9576 | } | |
9577 | } | |
bd2e244f | 9578 | |
a1b2278e CK |
9579 | scaler_state->scaler_id = id; |
9580 | if (id >= 0) { | |
9581 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9582 | } else { | |
9583 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9584 | } |
9585 | } | |
9586 | ||
5724dbd1 DL |
9587 | static void |
9588 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9589 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9590 | { |
9591 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9592 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9593 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9594 | int pipe = crtc->pipe; |
9595 | int fourcc, pixel_format; | |
6761dd31 | 9596 | unsigned int aligned_height; |
bc8d7dff | 9597 | struct drm_framebuffer *fb; |
1b842c89 | 9598 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9599 | |
d9806c9f | 9600 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9601 | if (!intel_fb) { |
bc8d7dff DL |
9602 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9603 | return; | |
9604 | } | |
9605 | ||
1b842c89 DL |
9606 | fb = &intel_fb->base; |
9607 | ||
bc8d7dff | 9608 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9609 | if (!(val & PLANE_CTL_ENABLE)) |
9610 | goto error; | |
9611 | ||
bc8d7dff DL |
9612 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9613 | fourcc = skl_format_to_fourcc(pixel_format, | |
9614 | val & PLANE_CTL_ORDER_RGBX, | |
9615 | val & PLANE_CTL_ALPHA_MASK); | |
9616 | fb->pixel_format = fourcc; | |
9617 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9618 | ||
40f46283 DL |
9619 | tiling = val & PLANE_CTL_TILED_MASK; |
9620 | switch (tiling) { | |
9621 | case PLANE_CTL_TILED_LINEAR: | |
9622 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9623 | break; | |
9624 | case PLANE_CTL_TILED_X: | |
9625 | plane_config->tiling = I915_TILING_X; | |
9626 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9627 | break; | |
9628 | case PLANE_CTL_TILED_Y: | |
9629 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9630 | break; | |
9631 | case PLANE_CTL_TILED_YF: | |
9632 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9633 | break; | |
9634 | default: | |
9635 | MISSING_CASE(tiling); | |
9636 | goto error; | |
9637 | } | |
9638 | ||
bc8d7dff DL |
9639 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9640 | plane_config->base = base; | |
9641 | ||
9642 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9643 | ||
9644 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9645 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9646 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9647 | ||
9648 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9649 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9650 | fb->pixel_format); |
bc8d7dff DL |
9651 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9652 | ||
9653 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9654 | fb->pixel_format, |
9655 | fb->modifier[0]); | |
bc8d7dff | 9656 | |
f37b5c2b | 9657 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9658 | |
9659 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9660 | pipe_name(pipe), fb->width, fb->height, | |
9661 | fb->bits_per_pixel, base, fb->pitches[0], | |
9662 | plane_config->size); | |
9663 | ||
2d14030b | 9664 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9665 | return; |
9666 | ||
9667 | error: | |
9668 | kfree(fb); | |
9669 | } | |
9670 | ||
2fa2fe9a | 9671 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9672 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9673 | { |
9674 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9675 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9676 | uint32_t tmp; |
9677 | ||
9678 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9679 | ||
9680 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9681 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9682 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9683 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9684 | |
9685 | /* We currently do not free assignements of panel fitters on | |
9686 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9687 | * differentiates them) so just WARN about this case for now. */ | |
9688 | if (IS_GEN7(dev)) { | |
9689 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9690 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9691 | } | |
2fa2fe9a | 9692 | } |
79e53945 JB |
9693 | } |
9694 | ||
5724dbd1 DL |
9695 | static void |
9696 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9697 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9698 | { |
9699 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9700 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9701 | u32 val, base, offset; |
aeee5a49 | 9702 | int pipe = crtc->pipe; |
4c6baa59 | 9703 | int fourcc, pixel_format; |
6761dd31 | 9704 | unsigned int aligned_height; |
b113d5ee | 9705 | struct drm_framebuffer *fb; |
1b842c89 | 9706 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9707 | |
42a7b088 DL |
9708 | val = I915_READ(DSPCNTR(pipe)); |
9709 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9710 | return; | |
9711 | ||
d9806c9f | 9712 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9713 | if (!intel_fb) { |
4c6baa59 JB |
9714 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9715 | return; | |
9716 | } | |
9717 | ||
1b842c89 DL |
9718 | fb = &intel_fb->base; |
9719 | ||
18c5247e DV |
9720 | if (INTEL_INFO(dev)->gen >= 4) { |
9721 | if (val & DISPPLANE_TILED) { | |
49af449b | 9722 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9723 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9724 | } | |
9725 | } | |
4c6baa59 JB |
9726 | |
9727 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9728 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9729 | fb->pixel_format = fourcc; |
9730 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9731 | |
aeee5a49 | 9732 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9733 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9734 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9735 | } else { |
49af449b | 9736 | if (plane_config->tiling) |
aeee5a49 | 9737 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9738 | else |
aeee5a49 | 9739 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9740 | } |
9741 | plane_config->base = base; | |
9742 | ||
9743 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9744 | fb->width = ((val >> 16) & 0xfff) + 1; |
9745 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9746 | |
9747 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9748 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9749 | |
b113d5ee | 9750 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9751 | fb->pixel_format, |
9752 | fb->modifier[0]); | |
4c6baa59 | 9753 | |
f37b5c2b | 9754 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9755 | |
2844a921 DL |
9756 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9757 | pipe_name(pipe), fb->width, fb->height, | |
9758 | fb->bits_per_pixel, base, fb->pitches[0], | |
9759 | plane_config->size); | |
b113d5ee | 9760 | |
2d14030b | 9761 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9762 | } |
9763 | ||
0e8ffe1b | 9764 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9765 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9766 | { |
9767 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9768 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9769 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9770 | uint32_t tmp; |
1729050e | 9771 | bool ret; |
0e8ffe1b | 9772 | |
1729050e ID |
9773 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9774 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9775 | return false; |
9776 | ||
e143a21c | 9777 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9778 | pipe_config->shared_dpll = NULL; |
eccb140b | 9779 | |
1729050e | 9780 | ret = false; |
0e8ffe1b DV |
9781 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9782 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9783 | goto out; |
0e8ffe1b | 9784 | |
42571aef VS |
9785 | switch (tmp & PIPECONF_BPC_MASK) { |
9786 | case PIPECONF_6BPC: | |
9787 | pipe_config->pipe_bpp = 18; | |
9788 | break; | |
9789 | case PIPECONF_8BPC: | |
9790 | pipe_config->pipe_bpp = 24; | |
9791 | break; | |
9792 | case PIPECONF_10BPC: | |
9793 | pipe_config->pipe_bpp = 30; | |
9794 | break; | |
9795 | case PIPECONF_12BPC: | |
9796 | pipe_config->pipe_bpp = 36; | |
9797 | break; | |
9798 | default: | |
9799 | break; | |
9800 | } | |
9801 | ||
b5a9fa09 DV |
9802 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9803 | pipe_config->limited_color_range = true; | |
9804 | ||
ab9412ba | 9805 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9806 | struct intel_shared_dpll *pll; |
8106ddbd | 9807 | enum intel_dpll_id pll_id; |
66e985c0 | 9808 | |
88adfff1 DV |
9809 | pipe_config->has_pch_encoder = true; |
9810 | ||
627eb5a3 DV |
9811 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9812 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9813 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9814 | |
9815 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9816 | |
2d1fe073 | 9817 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9818 | /* |
9819 | * The pipe->pch transcoder and pch transcoder->pll | |
9820 | * mapping is fixed. | |
9821 | */ | |
8106ddbd | 9822 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9823 | } else { |
9824 | tmp = I915_READ(PCH_DPLL_SEL); | |
9825 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9826 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9827 | else |
8106ddbd | 9828 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9829 | } |
66e985c0 | 9830 | |
8106ddbd ACO |
9831 | pipe_config->shared_dpll = |
9832 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9833 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9834 | |
2edd6443 ACO |
9835 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9836 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9837 | |
9838 | tmp = pipe_config->dpll_hw_state.dpll; | |
9839 | pipe_config->pixel_multiplier = | |
9840 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9841 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9842 | |
9843 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9844 | } else { |
9845 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9846 | } |
9847 | ||
1bd1bd80 | 9848 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9849 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9850 | |
2fa2fe9a DV |
9851 | ironlake_get_pfit_config(crtc, pipe_config); |
9852 | ||
1729050e ID |
9853 | ret = true; |
9854 | ||
9855 | out: | |
9856 | intel_display_power_put(dev_priv, power_domain); | |
9857 | ||
9858 | return ret; | |
0e8ffe1b DV |
9859 | } |
9860 | ||
be256dc7 PZ |
9861 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9862 | { | |
91c8a326 | 9863 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 9864 | struct intel_crtc *crtc; |
be256dc7 | 9865 | |
d3fcc808 | 9866 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9867 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9868 | pipe_name(crtc->pipe)); |
9869 | ||
e2c719b7 RC |
9870 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9871 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9872 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9873 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 9874 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 9875 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 9876 | "CPU PWM1 enabled\n"); |
c5107b87 | 9877 | if (IS_HASWELL(dev)) |
e2c719b7 | 9878 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9879 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9880 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9881 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9882 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9883 | "Utility pin enabled\n"); |
e2c719b7 | 9884 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9885 | |
9926ada1 PZ |
9886 | /* |
9887 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9888 | * interrupts remain enabled. We used to check for that, but since it's | |
9889 | * gen-specific and since we only disable LCPLL after we fully disable | |
9890 | * the interrupts, the check below should be enough. | |
9891 | */ | |
e2c719b7 | 9892 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9893 | } |
9894 | ||
9ccd5aeb PZ |
9895 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9896 | { | |
91c8a326 | 9897 | struct drm_device *dev = &dev_priv->drm; |
9ccd5aeb PZ |
9898 | |
9899 | if (IS_HASWELL(dev)) | |
9900 | return I915_READ(D_COMP_HSW); | |
9901 | else | |
9902 | return I915_READ(D_COMP_BDW); | |
9903 | } | |
9904 | ||
3c4c9b81 PZ |
9905 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9906 | { | |
91c8a326 | 9907 | struct drm_device *dev = &dev_priv->drm; |
3c4c9b81 PZ |
9908 | |
9909 | if (IS_HASWELL(dev)) { | |
9910 | mutex_lock(&dev_priv->rps.hw_lock); | |
9911 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9912 | val)) | |
f475dadf | 9913 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9914 | mutex_unlock(&dev_priv->rps.hw_lock); |
9915 | } else { | |
9ccd5aeb PZ |
9916 | I915_WRITE(D_COMP_BDW, val); |
9917 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9918 | } |
be256dc7 PZ |
9919 | } |
9920 | ||
9921 | /* | |
9922 | * This function implements pieces of two sequences from BSpec: | |
9923 | * - Sequence for display software to disable LCPLL | |
9924 | * - Sequence for display software to allow package C8+ | |
9925 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9926 | * register. Callers should take care of disabling all the display engine | |
9927 | * functions, doing the mode unset, fixing interrupts, etc. | |
9928 | */ | |
6ff58d53 PZ |
9929 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9930 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9931 | { |
9932 | uint32_t val; | |
9933 | ||
9934 | assert_can_disable_lcpll(dev_priv); | |
9935 | ||
9936 | val = I915_READ(LCPLL_CTL); | |
9937 | ||
9938 | if (switch_to_fclk) { | |
9939 | val |= LCPLL_CD_SOURCE_FCLK; | |
9940 | I915_WRITE(LCPLL_CTL, val); | |
9941 | ||
f53dd63f ID |
9942 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9943 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
9944 | DRM_ERROR("Switching to FCLK failed\n"); |
9945 | ||
9946 | val = I915_READ(LCPLL_CTL); | |
9947 | } | |
9948 | ||
9949 | val |= LCPLL_PLL_DISABLE; | |
9950 | I915_WRITE(LCPLL_CTL, val); | |
9951 | POSTING_READ(LCPLL_CTL); | |
9952 | ||
24d8441d | 9953 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
9954 | DRM_ERROR("LCPLL still locked\n"); |
9955 | ||
9ccd5aeb | 9956 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9957 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9958 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9959 | ndelay(100); |
9960 | ||
9ccd5aeb PZ |
9961 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9962 | 1)) | |
be256dc7 PZ |
9963 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9964 | ||
9965 | if (allow_power_down) { | |
9966 | val = I915_READ(LCPLL_CTL); | |
9967 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9968 | I915_WRITE(LCPLL_CTL, val); | |
9969 | POSTING_READ(LCPLL_CTL); | |
9970 | } | |
9971 | } | |
9972 | ||
9973 | /* | |
9974 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9975 | * source. | |
9976 | */ | |
6ff58d53 | 9977 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9978 | { |
9979 | uint32_t val; | |
9980 | ||
9981 | val = I915_READ(LCPLL_CTL); | |
9982 | ||
9983 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9984 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9985 | return; | |
9986 | ||
a8a8bd54 PZ |
9987 | /* |
9988 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9989 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9990 | */ |
59bad947 | 9991 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9992 | |
be256dc7 PZ |
9993 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9994 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9995 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9996 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9997 | } |
9998 | ||
9ccd5aeb | 9999 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
10000 | val |= D_COMP_COMP_FORCE; |
10001 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 10002 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10003 | |
10004 | val = I915_READ(LCPLL_CTL); | |
10005 | val &= ~LCPLL_PLL_DISABLE; | |
10006 | I915_WRITE(LCPLL_CTL, val); | |
10007 | ||
93220c08 CW |
10008 | if (intel_wait_for_register(dev_priv, |
10009 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
10010 | 5)) | |
be256dc7 PZ |
10011 | DRM_ERROR("LCPLL not locked yet\n"); |
10012 | ||
10013 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
10014 | val = I915_READ(LCPLL_CTL); | |
10015 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10016 | I915_WRITE(LCPLL_CTL, val); | |
10017 | ||
f53dd63f ID |
10018 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10019 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
10020 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10021 | } | |
215733fa | 10022 | |
59bad947 | 10023 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
91c8a326 | 10024 | intel_update_cdclk(&dev_priv->drm); |
be256dc7 PZ |
10025 | } |
10026 | ||
765dab67 PZ |
10027 | /* |
10028 | * Package states C8 and deeper are really deep PC states that can only be | |
10029 | * reached when all the devices on the system allow it, so even if the graphics | |
10030 | * device allows PC8+, it doesn't mean the system will actually get to these | |
10031 | * states. Our driver only allows PC8+ when going into runtime PM. | |
10032 | * | |
10033 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
10034 | * well is disabled and most interrupts are disabled, and these are also | |
10035 | * requirements for runtime PM. When these conditions are met, we manually do | |
10036 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
10037 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
10038 | * hang the machine. | |
10039 | * | |
10040 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
10041 | * the state of some registers, so when we come back from PC8+ we need to | |
10042 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
10043 | * need to take care of the registers kept by RC6. Notice that this happens even | |
10044 | * if we don't put the device in PCI D3 state (which is what currently happens | |
10045 | * because of the runtime PM support). | |
10046 | * | |
10047 | * For more, read "Display Sequences for Package C8" on the hardware | |
10048 | * documentation. | |
10049 | */ | |
a14cb6fc | 10050 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10051 | { |
91c8a326 | 10052 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
10053 | uint32_t val; |
10054 | ||
c67a470b PZ |
10055 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
10056 | ||
c2699524 | 10057 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
10058 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10059 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
10060 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10061 | } | |
10062 | ||
10063 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
10064 | hsw_disable_lcpll(dev_priv, true, true); |
10065 | } | |
10066 | ||
a14cb6fc | 10067 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10068 | { |
91c8a326 | 10069 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
10070 | uint32_t val; |
10071 | ||
c67a470b PZ |
10072 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
10073 | ||
10074 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
10075 | lpt_init_pch_refclk(dev); |
10076 | ||
c2699524 | 10077 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
10078 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10079 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
10080 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10081 | } | |
c67a470b PZ |
10082 | } |
10083 | ||
324513c0 | 10084 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 10085 | { |
a821fc46 | 10086 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10087 | struct intel_atomic_state *old_intel_state = |
10088 | to_intel_atomic_state(old_state); | |
10089 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 10090 | |
324513c0 | 10091 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
10092 | } |
10093 | ||
b432e5cf | 10094 | /* compute the max rate for new configuration */ |
27c329ed | 10095 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 10096 | { |
565602d7 | 10097 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 10098 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
10099 | struct drm_crtc *crtc; |
10100 | struct drm_crtc_state *cstate; | |
27c329ed | 10101 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
10102 | unsigned max_pixel_rate = 0, i; |
10103 | enum pipe pipe; | |
b432e5cf | 10104 | |
565602d7 ML |
10105 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
10106 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 10107 | |
565602d7 ML |
10108 | for_each_crtc_in_state(state, crtc, cstate, i) { |
10109 | int pixel_rate; | |
27c329ed | 10110 | |
565602d7 ML |
10111 | crtc_state = to_intel_crtc_state(cstate); |
10112 | if (!crtc_state->base.enable) { | |
10113 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 10114 | continue; |
565602d7 | 10115 | } |
b432e5cf | 10116 | |
27c329ed | 10117 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
10118 | |
10119 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 10120 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
10121 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
10122 | ||
565602d7 | 10123 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
10124 | } |
10125 | ||
565602d7 ML |
10126 | for_each_pipe(dev_priv, pipe) |
10127 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
10128 | ||
b432e5cf VS |
10129 | return max_pixel_rate; |
10130 | } | |
10131 | ||
10132 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
10133 | { | |
fac5e23e | 10134 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
10135 | uint32_t val, data; |
10136 | int ret; | |
10137 | ||
10138 | if (WARN((I915_READ(LCPLL_CTL) & | |
10139 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
10140 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
10141 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
10142 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
10143 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
10144 | return; | |
10145 | ||
10146 | mutex_lock(&dev_priv->rps.hw_lock); | |
10147 | ret = sandybridge_pcode_write(dev_priv, | |
10148 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
10149 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10150 | if (ret) { | |
10151 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
10152 | return; | |
10153 | } | |
10154 | ||
10155 | val = I915_READ(LCPLL_CTL); | |
10156 | val |= LCPLL_CD_SOURCE_FCLK; | |
10157 | I915_WRITE(LCPLL_CTL, val); | |
10158 | ||
5ba00178 TU |
10159 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10160 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
10161 | DRM_ERROR("Switching to FCLK failed\n"); |
10162 | ||
10163 | val = I915_READ(LCPLL_CTL); | |
10164 | val &= ~LCPLL_CLK_FREQ_MASK; | |
10165 | ||
10166 | switch (cdclk) { | |
10167 | case 450000: | |
10168 | val |= LCPLL_CLK_FREQ_450; | |
10169 | data = 0; | |
10170 | break; | |
10171 | case 540000: | |
10172 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
10173 | data = 1; | |
10174 | break; | |
10175 | case 337500: | |
10176 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
10177 | data = 2; | |
10178 | break; | |
10179 | case 675000: | |
10180 | val |= LCPLL_CLK_FREQ_675_BDW; | |
10181 | data = 3; | |
10182 | break; | |
10183 | default: | |
10184 | WARN(1, "invalid cdclk frequency\n"); | |
10185 | return; | |
10186 | } | |
10187 | ||
10188 | I915_WRITE(LCPLL_CTL, val); | |
10189 | ||
10190 | val = I915_READ(LCPLL_CTL); | |
10191 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10192 | I915_WRITE(LCPLL_CTL, val); | |
10193 | ||
5ba00178 TU |
10194 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10195 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
10196 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10197 | ||
10198 | mutex_lock(&dev_priv->rps.hw_lock); | |
10199 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
10200 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10201 | ||
7f1052a8 VS |
10202 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
10203 | ||
b432e5cf VS |
10204 | intel_update_cdclk(dev); |
10205 | ||
10206 | WARN(cdclk != dev_priv->cdclk_freq, | |
10207 | "cdclk requested %d kHz but got %d kHz\n", | |
10208 | cdclk, dev_priv->cdclk_freq); | |
10209 | } | |
10210 | ||
587c7914 VS |
10211 | static int broadwell_calc_cdclk(int max_pixclk) |
10212 | { | |
10213 | if (max_pixclk > 540000) | |
10214 | return 675000; | |
10215 | else if (max_pixclk > 450000) | |
10216 | return 540000; | |
10217 | else if (max_pixclk > 337500) | |
10218 | return 450000; | |
10219 | else | |
10220 | return 337500; | |
10221 | } | |
10222 | ||
27c329ed | 10223 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 10224 | { |
27c329ed | 10225 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 10226 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 10227 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
10228 | int cdclk; |
10229 | ||
10230 | /* | |
10231 | * FIXME should also account for plane ratio | |
10232 | * once 64bpp pixel formats are supported. | |
10233 | */ | |
587c7914 | 10234 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 10235 | |
b432e5cf | 10236 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
10237 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
10238 | cdclk, dev_priv->max_cdclk_freq); | |
10239 | return -EINVAL; | |
b432e5cf VS |
10240 | } |
10241 | ||
1a617b77 ML |
10242 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10243 | if (!intel_state->active_crtcs) | |
587c7914 | 10244 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10245 | |
10246 | return 0; | |
10247 | } | |
10248 | ||
27c329ed | 10249 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10250 | { |
27c329ed | 10251 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10252 | struct intel_atomic_state *old_intel_state = |
10253 | to_intel_atomic_state(old_state); | |
10254 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10255 | |
27c329ed | 10256 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10257 | } |
10258 | ||
c89e39f3 CT |
10259 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10260 | { | |
10261 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10262 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10263 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10264 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10265 | int cdclk; |
10266 | ||
10267 | /* | |
10268 | * FIXME should also account for plane ratio | |
10269 | * once 64bpp pixel formats are supported. | |
10270 | */ | |
a8ca4934 | 10271 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10272 | |
10273 | /* | |
10274 | * FIXME move the cdclk caclulation to | |
10275 | * compute_config() so we can fail gracegully. | |
10276 | */ | |
10277 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10278 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10279 | cdclk, dev_priv->max_cdclk_freq); | |
10280 | cdclk = dev_priv->max_cdclk_freq; | |
10281 | } | |
10282 | ||
10283 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10284 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10285 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10286 | |
10287 | return 0; | |
10288 | } | |
10289 | ||
10290 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10291 | { | |
1cd593e0 VS |
10292 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10293 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10294 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10295 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10296 | |
1cd593e0 | 10297 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10298 | } |
10299 | ||
190f68c5 ACO |
10300 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10301 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10302 | { |
d7edc4e5 | 10303 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10304 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10305 | return -EINVAL; | |
10306 | } | |
716c2e55 | 10307 | |
c7653199 | 10308 | crtc->lowfreq_avail = false; |
644cef34 | 10309 | |
c8f7a0db | 10310 | return 0; |
79e53945 JB |
10311 | } |
10312 | ||
3760b59c S |
10313 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10314 | enum port port, | |
10315 | struct intel_crtc_state *pipe_config) | |
10316 | { | |
8106ddbd ACO |
10317 | enum intel_dpll_id id; |
10318 | ||
3760b59c S |
10319 | switch (port) { |
10320 | case PORT_A: | |
10321 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 10322 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10323 | break; |
10324 | case PORT_B: | |
10325 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 10326 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10327 | break; |
10328 | case PORT_C: | |
10329 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 10330 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10331 | break; |
10332 | default: | |
10333 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10334 | return; |
3760b59c | 10335 | } |
8106ddbd ACO |
10336 | |
10337 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10338 | } |
10339 | ||
96b7dfb7 S |
10340 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10341 | enum port port, | |
5cec258b | 10342 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10343 | { |
8106ddbd | 10344 | enum intel_dpll_id id; |
a3c988ea | 10345 | u32 temp; |
96b7dfb7 S |
10346 | |
10347 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
10348 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
10349 | ||
10350 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 10351 | case SKL_DPLL0: |
a3c988ea ACO |
10352 | id = DPLL_ID_SKL_DPLL0; |
10353 | break; | |
96b7dfb7 | 10354 | case SKL_DPLL1: |
8106ddbd | 10355 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
10356 | break; |
10357 | case SKL_DPLL2: | |
8106ddbd | 10358 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
10359 | break; |
10360 | case SKL_DPLL3: | |
8106ddbd | 10361 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 10362 | break; |
8106ddbd ACO |
10363 | default: |
10364 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10365 | return; | |
96b7dfb7 | 10366 | } |
8106ddbd ACO |
10367 | |
10368 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10369 | } |
10370 | ||
7d2c8175 DL |
10371 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10372 | enum port port, | |
5cec258b | 10373 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10374 | { |
8106ddbd ACO |
10375 | enum intel_dpll_id id; |
10376 | ||
7d2c8175 DL |
10377 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
10378 | ||
10379 | switch (pipe_config->ddi_pll_sel) { | |
10380 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 10381 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10382 | break; |
10383 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10384 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10385 | break; |
00490c22 | 10386 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10387 | id = DPLL_ID_SPLL; |
79bd23da | 10388 | break; |
9d16da65 ACO |
10389 | case PORT_CLK_SEL_LCPLL_810: |
10390 | id = DPLL_ID_LCPLL_810; | |
10391 | break; | |
10392 | case PORT_CLK_SEL_LCPLL_1350: | |
10393 | id = DPLL_ID_LCPLL_1350; | |
10394 | break; | |
10395 | case PORT_CLK_SEL_LCPLL_2700: | |
10396 | id = DPLL_ID_LCPLL_2700; | |
10397 | break; | |
8106ddbd ACO |
10398 | default: |
10399 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10400 | /* fall through */ | |
10401 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10402 | return; |
7d2c8175 | 10403 | } |
8106ddbd ACO |
10404 | |
10405 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10406 | } |
10407 | ||
cf30429e JN |
10408 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10409 | struct intel_crtc_state *pipe_config, | |
10410 | unsigned long *power_domain_mask) | |
10411 | { | |
10412 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10413 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10414 | enum intel_display_power_domain power_domain; |
10415 | u32 tmp; | |
10416 | ||
d9a7bc67 ID |
10417 | /* |
10418 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10419 | * transcoder handled below. | |
10420 | */ | |
cf30429e JN |
10421 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10422 | ||
10423 | /* | |
10424 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10425 | * consistency and less surprising code; it's in always on power). | |
10426 | */ | |
10427 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10428 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10429 | enum pipe trans_edp_pipe; | |
10430 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10431 | default: | |
10432 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10433 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10434 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10435 | trans_edp_pipe = PIPE_A; | |
10436 | break; | |
10437 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10438 | trans_edp_pipe = PIPE_B; | |
10439 | break; | |
10440 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10441 | trans_edp_pipe = PIPE_C; | |
10442 | break; | |
10443 | } | |
10444 | ||
10445 | if (trans_edp_pipe == crtc->pipe) | |
10446 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10447 | } | |
10448 | ||
10449 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10450 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10451 | return false; | |
10452 | *power_domain_mask |= BIT(power_domain); | |
10453 | ||
10454 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10455 | ||
10456 | return tmp & PIPECONF_ENABLE; | |
10457 | } | |
10458 | ||
4d1de975 JN |
10459 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10460 | struct intel_crtc_state *pipe_config, | |
10461 | unsigned long *power_domain_mask) | |
10462 | { | |
10463 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10464 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10465 | enum intel_display_power_domain power_domain; |
10466 | enum port port; | |
10467 | enum transcoder cpu_transcoder; | |
10468 | u32 tmp; | |
10469 | ||
4d1de975 JN |
10470 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10471 | if (port == PORT_A) | |
10472 | cpu_transcoder = TRANSCODER_DSI_A; | |
10473 | else | |
10474 | cpu_transcoder = TRANSCODER_DSI_C; | |
10475 | ||
10476 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10477 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10478 | continue; | |
10479 | *power_domain_mask |= BIT(power_domain); | |
10480 | ||
db18b6a6 ID |
10481 | /* |
10482 | * The PLL needs to be enabled with a valid divider | |
10483 | * configuration, otherwise accessing DSI registers will hang | |
10484 | * the machine. See BSpec North Display Engine | |
10485 | * registers/MIPI[BXT]. We can break out here early, since we | |
10486 | * need the same DSI PLL to be enabled for both DSI ports. | |
10487 | */ | |
10488 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10489 | break; | |
10490 | ||
4d1de975 JN |
10491 | /* XXX: this works for video mode only */ |
10492 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10493 | if (!(tmp & DPI_ENABLE)) | |
10494 | continue; | |
10495 | ||
10496 | tmp = I915_READ(MIPI_CTRL(port)); | |
10497 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10498 | continue; | |
10499 | ||
10500 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10501 | break; |
10502 | } | |
10503 | ||
d7edc4e5 | 10504 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10505 | } |
10506 | ||
26804afd | 10507 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10508 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10509 | { |
10510 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10511 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10512 | struct intel_shared_dpll *pll; |
26804afd DV |
10513 | enum port port; |
10514 | uint32_t tmp; | |
10515 | ||
10516 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10517 | ||
10518 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10519 | ||
ef11bdb3 | 10520 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10521 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10522 | else if (IS_BROXTON(dev)) |
10523 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10524 | else |
10525 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10526 | |
8106ddbd ACO |
10527 | pll = pipe_config->shared_dpll; |
10528 | if (pll) { | |
2edd6443 ACO |
10529 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10530 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10531 | } |
10532 | ||
26804afd DV |
10533 | /* |
10534 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10535 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10536 | * the PCH transcoder is on. | |
10537 | */ | |
ca370455 DL |
10538 | if (INTEL_INFO(dev)->gen < 9 && |
10539 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10540 | pipe_config->has_pch_encoder = true; |
10541 | ||
10542 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10543 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10544 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10545 | ||
10546 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10547 | } | |
10548 | } | |
10549 | ||
0e8ffe1b | 10550 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10551 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10552 | { |
10553 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10554 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10555 | enum intel_display_power_domain power_domain; |
10556 | unsigned long power_domain_mask; | |
cf30429e | 10557 | bool active; |
0e8ffe1b | 10558 | |
1729050e ID |
10559 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10560 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10561 | return false; |
1729050e ID |
10562 | power_domain_mask = BIT(power_domain); |
10563 | ||
8106ddbd | 10564 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10565 | |
cf30429e | 10566 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10567 | |
d7edc4e5 VS |
10568 | if (IS_BROXTON(dev_priv) && |
10569 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10570 | WARN_ON(active); | |
10571 | active = true; | |
4d1de975 JN |
10572 | } |
10573 | ||
cf30429e | 10574 | if (!active) |
1729050e | 10575 | goto out; |
0e8ffe1b | 10576 | |
d7edc4e5 | 10577 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10578 | haswell_get_ddi_port_state(crtc, pipe_config); |
10579 | intel_get_pipe_timings(crtc, pipe_config); | |
10580 | } | |
627eb5a3 | 10581 | |
bc58be60 | 10582 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10583 | |
05dc698c LL |
10584 | pipe_config->gamma_mode = |
10585 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10586 | ||
a1b2278e CK |
10587 | if (INTEL_INFO(dev)->gen >= 9) { |
10588 | skl_init_scalers(dev, crtc, pipe_config); | |
10589 | } | |
10590 | ||
af99ceda CK |
10591 | if (INTEL_INFO(dev)->gen >= 9) { |
10592 | pipe_config->scaler_state.scaler_id = -1; | |
10593 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10594 | } | |
10595 | ||
1729050e ID |
10596 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10597 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10598 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10599 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10600 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10601 | else |
1c132b44 | 10602 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10603 | } |
88adfff1 | 10604 | |
e59150dc JB |
10605 | if (IS_HASWELL(dev)) |
10606 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10607 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10608 | |
4d1de975 JN |
10609 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10610 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10611 | pipe_config->pixel_multiplier = |
10612 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10613 | } else { | |
10614 | pipe_config->pixel_multiplier = 1; | |
10615 | } | |
6c49f241 | 10616 | |
1729050e ID |
10617 | out: |
10618 | for_each_power_domain(power_domain, power_domain_mask) | |
10619 | intel_display_power_put(dev_priv, power_domain); | |
10620 | ||
cf30429e | 10621 | return active; |
0e8ffe1b DV |
10622 | } |
10623 | ||
55a08b3f ML |
10624 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10625 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10626 | { |
10627 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10628 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10630 | uint32_t cntl = 0, size = 0; |
560b85bb | 10631 | |
936e71e3 | 10632 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
10633 | unsigned int width = plane_state->base.crtc_w; |
10634 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10635 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10636 | ||
10637 | switch (stride) { | |
10638 | default: | |
10639 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10640 | width, stride); | |
10641 | stride = 256; | |
10642 | /* fallthrough */ | |
10643 | case 256: | |
10644 | case 512: | |
10645 | case 1024: | |
10646 | case 2048: | |
10647 | break; | |
4b0e333e CW |
10648 | } |
10649 | ||
dc41c154 VS |
10650 | cntl |= CURSOR_ENABLE | |
10651 | CURSOR_GAMMA_ENABLE | | |
10652 | CURSOR_FORMAT_ARGB | | |
10653 | CURSOR_STRIDE(stride); | |
10654 | ||
10655 | size = (height << 12) | width; | |
4b0e333e | 10656 | } |
560b85bb | 10657 | |
dc41c154 VS |
10658 | if (intel_crtc->cursor_cntl != 0 && |
10659 | (intel_crtc->cursor_base != base || | |
10660 | intel_crtc->cursor_size != size || | |
10661 | intel_crtc->cursor_cntl != cntl)) { | |
10662 | /* On these chipsets we can only modify the base/size/stride | |
10663 | * whilst the cursor is disabled. | |
10664 | */ | |
0b87c24e VS |
10665 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10666 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10667 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10668 | } |
560b85bb | 10669 | |
99d1f387 | 10670 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10671 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10672 | intel_crtc->cursor_base = base; |
10673 | } | |
4726e0b0 | 10674 | |
dc41c154 VS |
10675 | if (intel_crtc->cursor_size != size) { |
10676 | I915_WRITE(CURSIZE, size); | |
10677 | intel_crtc->cursor_size = size; | |
4b0e333e | 10678 | } |
560b85bb | 10679 | |
4b0e333e | 10680 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10681 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10682 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10683 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10684 | } |
560b85bb CW |
10685 | } |
10686 | ||
55a08b3f ML |
10687 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10688 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10689 | { |
10690 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10691 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10693 | int pipe = intel_crtc->pipe; | |
663f3122 | 10694 | uint32_t cntl = 0; |
4b0e333e | 10695 | |
936e71e3 | 10696 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 10697 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10698 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10699 | case 64: |
10700 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10701 | break; | |
10702 | case 128: | |
10703 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10704 | break; | |
10705 | case 256: | |
10706 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10707 | break; | |
10708 | default: | |
55a08b3f | 10709 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10710 | return; |
65a21cd6 | 10711 | } |
4b0e333e | 10712 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10713 | |
fc6f93bc | 10714 | if (HAS_DDI(dev)) |
47bf17a7 | 10715 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10716 | |
31ad61e4 | 10717 | if (plane_state->base.rotation == DRM_ROTATE_180) |
55a08b3f ML |
10718 | cntl |= CURSOR_ROTATE_180; |
10719 | } | |
4398ad45 | 10720 | |
4b0e333e CW |
10721 | if (intel_crtc->cursor_cntl != cntl) { |
10722 | I915_WRITE(CURCNTR(pipe), cntl); | |
10723 | POSTING_READ(CURCNTR(pipe)); | |
10724 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10725 | } |
4b0e333e | 10726 | |
65a21cd6 | 10727 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10728 | I915_WRITE(CURBASE(pipe), base); |
10729 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10730 | |
10731 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10732 | } |
10733 | ||
cda4b7d3 | 10734 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10735 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10736 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10737 | { |
10738 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10739 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10741 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10742 | u32 base = intel_crtc->cursor_addr; |
10743 | u32 pos = 0; | |
cda4b7d3 | 10744 | |
55a08b3f ML |
10745 | if (plane_state) { |
10746 | int x = plane_state->base.crtc_x; | |
10747 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10748 | |
55a08b3f ML |
10749 | if (x < 0) { |
10750 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10751 | x = -x; | |
10752 | } | |
10753 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10754 | |
55a08b3f ML |
10755 | if (y < 0) { |
10756 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10757 | y = -y; | |
10758 | } | |
10759 | pos |= y << CURSOR_Y_SHIFT; | |
10760 | ||
10761 | /* ILK+ do this automagically */ | |
10762 | if (HAS_GMCH_DISPLAY(dev) && | |
31ad61e4 | 10763 | plane_state->base.rotation == DRM_ROTATE_180) { |
55a08b3f ML |
10764 | base += (plane_state->base.crtc_h * |
10765 | plane_state->base.crtc_w - 1) * 4; | |
10766 | } | |
cda4b7d3 | 10767 | } |
cda4b7d3 | 10768 | |
5efb3e28 VS |
10769 | I915_WRITE(CURPOS(pipe), pos); |
10770 | ||
8ac54669 | 10771 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10772 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10773 | else |
55a08b3f | 10774 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10775 | } |
10776 | ||
dc41c154 VS |
10777 | static bool cursor_size_ok(struct drm_device *dev, |
10778 | uint32_t width, uint32_t height) | |
10779 | { | |
10780 | if (width == 0 || height == 0) | |
10781 | return false; | |
10782 | ||
10783 | /* | |
10784 | * 845g/865g are special in that they are only limited by | |
10785 | * the width of their cursors, the height is arbitrary up to | |
10786 | * the precision of the register. Everything else requires | |
10787 | * square cursors, limited to a few power-of-two sizes. | |
10788 | */ | |
10789 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10790 | if ((width & 63) != 0) | |
10791 | return false; | |
10792 | ||
10793 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10794 | return false; | |
10795 | ||
10796 | if (height > 1023) | |
10797 | return false; | |
10798 | } else { | |
10799 | switch (width | height) { | |
10800 | case 256: | |
10801 | case 128: | |
10802 | if (IS_GEN2(dev)) | |
10803 | return false; | |
10804 | case 64: | |
10805 | break; | |
10806 | default: | |
10807 | return false; | |
10808 | } | |
10809 | } | |
10810 | ||
10811 | return true; | |
10812 | } | |
10813 | ||
79e53945 JB |
10814 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10815 | static struct drm_display_mode load_detect_mode = { | |
10816 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10817 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10818 | }; | |
10819 | ||
a8bb6818 DV |
10820 | struct drm_framebuffer * |
10821 | __intel_framebuffer_create(struct drm_device *dev, | |
10822 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10823 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10824 | { |
10825 | struct intel_framebuffer *intel_fb; | |
10826 | int ret; | |
10827 | ||
10828 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10829 | if (!intel_fb) |
d2dff872 | 10830 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10831 | |
10832 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10833 | if (ret) |
10834 | goto err; | |
d2dff872 CW |
10835 | |
10836 | return &intel_fb->base; | |
dcb1394e | 10837 | |
dd4916c5 | 10838 | err: |
dd4916c5 | 10839 | kfree(intel_fb); |
dd4916c5 | 10840 | return ERR_PTR(ret); |
d2dff872 CW |
10841 | } |
10842 | ||
b5ea642a | 10843 | static struct drm_framebuffer * |
a8bb6818 DV |
10844 | intel_framebuffer_create(struct drm_device *dev, |
10845 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10846 | struct drm_i915_gem_object *obj) | |
10847 | { | |
10848 | struct drm_framebuffer *fb; | |
10849 | int ret; | |
10850 | ||
10851 | ret = i915_mutex_lock_interruptible(dev); | |
10852 | if (ret) | |
10853 | return ERR_PTR(ret); | |
10854 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10855 | mutex_unlock(&dev->struct_mutex); | |
10856 | ||
10857 | return fb; | |
10858 | } | |
10859 | ||
d2dff872 CW |
10860 | static u32 |
10861 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10862 | { | |
10863 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10864 | return ALIGN(pitch, 64); | |
10865 | } | |
10866 | ||
10867 | static u32 | |
10868 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10869 | { | |
10870 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10871 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10872 | } |
10873 | ||
10874 | static struct drm_framebuffer * | |
10875 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10876 | struct drm_display_mode *mode, | |
10877 | int depth, int bpp) | |
10878 | { | |
dcb1394e | 10879 | struct drm_framebuffer *fb; |
d2dff872 | 10880 | struct drm_i915_gem_object *obj; |
0fed39bd | 10881 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10882 | |
d37cd8a8 | 10883 | obj = i915_gem_object_create(dev, |
d2dff872 | 10884 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10885 | if (IS_ERR(obj)) |
10886 | return ERR_CAST(obj); | |
d2dff872 CW |
10887 | |
10888 | mode_cmd.width = mode->hdisplay; | |
10889 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10890 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10891 | bpp); | |
5ca0c34a | 10892 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10893 | |
dcb1394e LW |
10894 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10895 | if (IS_ERR(fb)) | |
34911fd3 | 10896 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
10897 | |
10898 | return fb; | |
d2dff872 CW |
10899 | } |
10900 | ||
10901 | static struct drm_framebuffer * | |
10902 | mode_fits_in_fbdev(struct drm_device *dev, | |
10903 | struct drm_display_mode *mode) | |
10904 | { | |
0695726e | 10905 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 10906 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
10907 | struct drm_i915_gem_object *obj; |
10908 | struct drm_framebuffer *fb; | |
10909 | ||
4c0e5528 | 10910 | if (!dev_priv->fbdev) |
d2dff872 CW |
10911 | return NULL; |
10912 | ||
4c0e5528 | 10913 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10914 | return NULL; |
10915 | ||
4c0e5528 DV |
10916 | obj = dev_priv->fbdev->fb->obj; |
10917 | BUG_ON(!obj); | |
10918 | ||
8bcd4553 | 10919 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10920 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10921 | fb->bits_per_pixel)) | |
d2dff872 CW |
10922 | return NULL; |
10923 | ||
01f2c773 | 10924 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10925 | return NULL; |
10926 | ||
edde3617 | 10927 | drm_framebuffer_reference(fb); |
d2dff872 | 10928 | return fb; |
4520f53a DV |
10929 | #else |
10930 | return NULL; | |
10931 | #endif | |
d2dff872 CW |
10932 | } |
10933 | ||
d3a40d1b ACO |
10934 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10935 | struct drm_crtc *crtc, | |
10936 | struct drm_display_mode *mode, | |
10937 | struct drm_framebuffer *fb, | |
10938 | int x, int y) | |
10939 | { | |
10940 | struct drm_plane_state *plane_state; | |
10941 | int hdisplay, vdisplay; | |
10942 | int ret; | |
10943 | ||
10944 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10945 | if (IS_ERR(plane_state)) | |
10946 | return PTR_ERR(plane_state); | |
10947 | ||
10948 | if (mode) | |
10949 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10950 | else | |
10951 | hdisplay = vdisplay = 0; | |
10952 | ||
10953 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10954 | if (ret) | |
10955 | return ret; | |
10956 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10957 | plane_state->crtc_x = 0; | |
10958 | plane_state->crtc_y = 0; | |
10959 | plane_state->crtc_w = hdisplay; | |
10960 | plane_state->crtc_h = vdisplay; | |
10961 | plane_state->src_x = x << 16; | |
10962 | plane_state->src_y = y << 16; | |
10963 | plane_state->src_w = hdisplay << 16; | |
10964 | plane_state->src_h = vdisplay << 16; | |
10965 | ||
10966 | return 0; | |
10967 | } | |
10968 | ||
d2434ab7 | 10969 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10970 | struct drm_display_mode *mode, |
51fd371b RC |
10971 | struct intel_load_detect_pipe *old, |
10972 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10973 | { |
10974 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10975 | struct intel_encoder *intel_encoder = |
10976 | intel_attached_encoder(connector); | |
79e53945 | 10977 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10978 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10979 | struct drm_crtc *crtc = NULL; |
10980 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10981 | struct drm_framebuffer *fb; |
51fd371b | 10982 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10983 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10984 | struct drm_connector_state *connector_state; |
4be07317 | 10985 | struct intel_crtc_state *crtc_state; |
51fd371b | 10986 | int ret, i = -1; |
79e53945 | 10987 | |
d2dff872 | 10988 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10989 | connector->base.id, connector->name, |
8e329a03 | 10990 | encoder->base.id, encoder->name); |
d2dff872 | 10991 | |
edde3617 ML |
10992 | old->restore_state = NULL; |
10993 | ||
51fd371b RC |
10994 | retry: |
10995 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10996 | if (ret) | |
ad3c558f | 10997 | goto fail; |
6e9f798d | 10998 | |
79e53945 JB |
10999 | /* |
11000 | * Algorithm gets a little messy: | |
7a5e4805 | 11001 | * |
79e53945 JB |
11002 | * - if the connector already has an assigned crtc, use it (but make |
11003 | * sure it's on first) | |
7a5e4805 | 11004 | * |
79e53945 JB |
11005 | * - try to find the first unused crtc that can drive this connector, |
11006 | * and use that if we find one | |
79e53945 JB |
11007 | */ |
11008 | ||
11009 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
11010 | if (connector->state->crtc) { |
11011 | crtc = connector->state->crtc; | |
8261b191 | 11012 | |
51fd371b | 11013 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 11014 | if (ret) |
ad3c558f | 11015 | goto fail; |
8261b191 CW |
11016 | |
11017 | /* Make sure the crtc and connector are running */ | |
edde3617 | 11018 | goto found; |
79e53945 JB |
11019 | } |
11020 | ||
11021 | /* Find an unused one (if possible) */ | |
70e1e0ec | 11022 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
11023 | i++; |
11024 | if (!(encoder->possible_crtcs & (1 << i))) | |
11025 | continue; | |
edde3617 ML |
11026 | |
11027 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
11028 | if (ret) | |
11029 | goto fail; | |
11030 | ||
11031 | if (possible_crtc->state->enable) { | |
11032 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 11033 | continue; |
edde3617 | 11034 | } |
a459249c VS |
11035 | |
11036 | crtc = possible_crtc; | |
11037 | break; | |
79e53945 JB |
11038 | } |
11039 | ||
11040 | /* | |
11041 | * If we didn't find an unused CRTC, don't use any. | |
11042 | */ | |
11043 | if (!crtc) { | |
7173188d | 11044 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 11045 | goto fail; |
79e53945 JB |
11046 | } |
11047 | ||
edde3617 ML |
11048 | found: |
11049 | intel_crtc = to_intel_crtc(crtc); | |
11050 | ||
4d02e2de DV |
11051 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
11052 | if (ret) | |
ad3c558f | 11053 | goto fail; |
79e53945 | 11054 | |
83a57153 | 11055 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
11056 | restore_state = drm_atomic_state_alloc(dev); |
11057 | if (!state || !restore_state) { | |
11058 | ret = -ENOMEM; | |
11059 | goto fail; | |
11060 | } | |
83a57153 ACO |
11061 | |
11062 | state->acquire_ctx = ctx; | |
edde3617 | 11063 | restore_state->acquire_ctx = ctx; |
83a57153 | 11064 | |
944b0c76 ACO |
11065 | connector_state = drm_atomic_get_connector_state(state, connector); |
11066 | if (IS_ERR(connector_state)) { | |
11067 | ret = PTR_ERR(connector_state); | |
11068 | goto fail; | |
11069 | } | |
11070 | ||
edde3617 ML |
11071 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
11072 | if (ret) | |
11073 | goto fail; | |
944b0c76 | 11074 | |
4be07317 ACO |
11075 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
11076 | if (IS_ERR(crtc_state)) { | |
11077 | ret = PTR_ERR(crtc_state); | |
11078 | goto fail; | |
11079 | } | |
11080 | ||
49d6fa21 | 11081 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 11082 | |
6492711d CW |
11083 | if (!mode) |
11084 | mode = &load_detect_mode; | |
79e53945 | 11085 | |
d2dff872 CW |
11086 | /* We need a framebuffer large enough to accommodate all accesses |
11087 | * that the plane may generate whilst we perform load detection. | |
11088 | * We can not rely on the fbcon either being present (we get called | |
11089 | * during its initialisation to detect all boot displays, or it may | |
11090 | * not even exist) or that it is large enough to satisfy the | |
11091 | * requested mode. | |
11092 | */ | |
94352cf9 DV |
11093 | fb = mode_fits_in_fbdev(dev, mode); |
11094 | if (fb == NULL) { | |
d2dff872 | 11095 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 11096 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
11097 | } else |
11098 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 11099 | if (IS_ERR(fb)) { |
d2dff872 | 11100 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 11101 | goto fail; |
79e53945 | 11102 | } |
79e53945 | 11103 | |
d3a40d1b ACO |
11104 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
11105 | if (ret) | |
11106 | goto fail; | |
11107 | ||
edde3617 ML |
11108 | drm_framebuffer_unreference(fb); |
11109 | ||
11110 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
11111 | if (ret) | |
11112 | goto fail; | |
11113 | ||
11114 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
11115 | if (!ret) | |
11116 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
11117 | if (!ret) | |
11118 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
11119 | if (ret) { | |
11120 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
11121 | goto fail; | |
11122 | } | |
8c7b5ccb | 11123 | |
3ba86073 ML |
11124 | ret = drm_atomic_commit(state); |
11125 | if (ret) { | |
6492711d | 11126 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 11127 | goto fail; |
79e53945 | 11128 | } |
edde3617 ML |
11129 | |
11130 | old->restore_state = restore_state; | |
7173188d | 11131 | |
79e53945 | 11132 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 11133 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 11134 | return true; |
412b61d8 | 11135 | |
ad3c558f | 11136 | fail: |
e5d958ef | 11137 | drm_atomic_state_free(state); |
edde3617 ML |
11138 | drm_atomic_state_free(restore_state); |
11139 | restore_state = state = NULL; | |
83a57153 | 11140 | |
51fd371b RC |
11141 | if (ret == -EDEADLK) { |
11142 | drm_modeset_backoff(ctx); | |
11143 | goto retry; | |
11144 | } | |
11145 | ||
412b61d8 | 11146 | return false; |
79e53945 JB |
11147 | } |
11148 | ||
d2434ab7 | 11149 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
11150 | struct intel_load_detect_pipe *old, |
11151 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 11152 | { |
d2434ab7 DV |
11153 | struct intel_encoder *intel_encoder = |
11154 | intel_attached_encoder(connector); | |
4ef69c7a | 11155 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 11156 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 11157 | int ret; |
79e53945 | 11158 | |
d2dff872 | 11159 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11160 | connector->base.id, connector->name, |
8e329a03 | 11161 | encoder->base.id, encoder->name); |
d2dff872 | 11162 | |
edde3617 | 11163 | if (!state) |
0622a53c | 11164 | return; |
79e53945 | 11165 | |
edde3617 ML |
11166 | ret = drm_atomic_commit(state); |
11167 | if (ret) { | |
11168 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
11169 | drm_atomic_state_free(state); | |
11170 | } | |
79e53945 JB |
11171 | } |
11172 | ||
da4a1efa | 11173 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 11174 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 11175 | { |
fac5e23e | 11176 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
11177 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
11178 | ||
11179 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 11180 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
11181 | else if (HAS_PCH_SPLIT(dev)) |
11182 | return 120000; | |
11183 | else if (!IS_GEN2(dev)) | |
11184 | return 96000; | |
11185 | else | |
11186 | return 48000; | |
11187 | } | |
11188 | ||
79e53945 | 11189 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 11190 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 11191 | struct intel_crtc_state *pipe_config) |
79e53945 | 11192 | { |
f1f644dc | 11193 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 11194 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 11195 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 11196 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 11197 | u32 fp; |
9e2c8475 | 11198 | struct dpll clock; |
dccbea3b | 11199 | int port_clock; |
da4a1efa | 11200 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
11201 | |
11202 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 11203 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 11204 | else |
293623f7 | 11205 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
11206 | |
11207 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
11208 | if (IS_PINEVIEW(dev)) { |
11209 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
11210 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
11211 | } else { |
11212 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
11213 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
11214 | } | |
11215 | ||
a6c45cf0 | 11216 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
11217 | if (IS_PINEVIEW(dev)) |
11218 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
11219 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
11220 | else |
11221 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
11222 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
11223 | ||
11224 | switch (dpll & DPLL_MODE_MASK) { | |
11225 | case DPLLB_MODE_DAC_SERIAL: | |
11226 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
11227 | 5 : 10; | |
11228 | break; | |
11229 | case DPLLB_MODE_LVDS: | |
11230 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
11231 | 7 : 14; | |
11232 | break; | |
11233 | default: | |
28c97730 | 11234 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 11235 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 11236 | return; |
79e53945 JB |
11237 | } |
11238 | ||
ac58c3f0 | 11239 | if (IS_PINEVIEW(dev)) |
dccbea3b | 11240 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11241 | else |
dccbea3b | 11242 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11243 | } else { |
0fb58223 | 11244 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11245 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11246 | |
11247 | if (is_lvds) { | |
11248 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11249 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11250 | |
11251 | if (lvds & LVDS_CLKB_POWER_UP) | |
11252 | clock.p2 = 7; | |
11253 | else | |
11254 | clock.p2 = 14; | |
79e53945 JB |
11255 | } else { |
11256 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11257 | clock.p1 = 2; | |
11258 | else { | |
11259 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11260 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11261 | } | |
11262 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11263 | clock.p2 = 4; | |
11264 | else | |
11265 | clock.p2 = 2; | |
79e53945 | 11266 | } |
da4a1efa | 11267 | |
dccbea3b | 11268 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11269 | } |
11270 | ||
18442d08 VS |
11271 | /* |
11272 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11273 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11274 | * encoder's get_config() function. |
11275 | */ | |
dccbea3b | 11276 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11277 | } |
11278 | ||
6878da05 VS |
11279 | int intel_dotclock_calculate(int link_freq, |
11280 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11281 | { |
f1f644dc JB |
11282 | /* |
11283 | * The calculation for the data clock is: | |
1041a02f | 11284 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11285 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11286 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11287 | * |
11288 | * and the link clock is simpler: | |
1041a02f | 11289 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11290 | */ |
11291 | ||
6878da05 VS |
11292 | if (!m_n->link_n) |
11293 | return 0; | |
f1f644dc | 11294 | |
6878da05 VS |
11295 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11296 | } | |
f1f644dc | 11297 | |
18442d08 | 11298 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11299 | struct intel_crtc_state *pipe_config) |
6878da05 | 11300 | { |
e3b247da | 11301 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11302 | |
18442d08 VS |
11303 | /* read out port_clock from the DPLL */ |
11304 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11305 | |
f1f644dc | 11306 | /* |
e3b247da VS |
11307 | * In case there is an active pipe without active ports, |
11308 | * we may need some idea for the dotclock anyway. | |
11309 | * Calculate one based on the FDI configuration. | |
79e53945 | 11310 | */ |
2d112de7 | 11311 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11312 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11313 | &pipe_config->fdi_m_n); |
79e53945 JB |
11314 | } |
11315 | ||
11316 | /** Returns the currently programmed mode of the given pipe. */ | |
11317 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11318 | struct drm_crtc *crtc) | |
11319 | { | |
fac5e23e | 11320 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11321 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11322 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11323 | struct drm_display_mode *mode; |
3f36b937 | 11324 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11325 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11326 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11327 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11328 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11329 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11330 | |
11331 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11332 | if (!mode) | |
11333 | return NULL; | |
11334 | ||
3f36b937 TU |
11335 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11336 | if (!pipe_config) { | |
11337 | kfree(mode); | |
11338 | return NULL; | |
11339 | } | |
11340 | ||
f1f644dc JB |
11341 | /* |
11342 | * Construct a pipe_config sufficient for getting the clock info | |
11343 | * back out of crtc_clock_get. | |
11344 | * | |
11345 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11346 | * to use a real value here instead. | |
11347 | */ | |
3f36b937 TU |
11348 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11349 | pipe_config->pixel_multiplier = 1; | |
11350 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11351 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11352 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11353 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11354 | ||
11355 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11356 | mode->hdisplay = (htot & 0xffff) + 1; |
11357 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11358 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11359 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11360 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11361 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11362 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11363 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11364 | ||
11365 | drm_mode_set_name(mode); | |
79e53945 | 11366 | |
3f36b937 TU |
11367 | kfree(pipe_config); |
11368 | ||
79e53945 JB |
11369 | return mode; |
11370 | } | |
11371 | ||
11372 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11373 | { | |
11374 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11375 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11376 | struct intel_flip_work *work; |
67e77c5a | 11377 | |
5e2d7afc | 11378 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11379 | work = intel_crtc->flip_work; |
11380 | intel_crtc->flip_work = NULL; | |
11381 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11382 | |
5a21b665 | 11383 | if (work) { |
51cbaf01 ML |
11384 | cancel_work_sync(&work->mmio_work); |
11385 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11386 | kfree(work); |
67e77c5a | 11387 | } |
79e53945 JB |
11388 | |
11389 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11390 | |
79e53945 JB |
11391 | kfree(intel_crtc); |
11392 | } | |
11393 | ||
6b95a207 KH |
11394 | static void intel_unpin_work_fn(struct work_struct *__work) |
11395 | { | |
51cbaf01 ML |
11396 | struct intel_flip_work *work = |
11397 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11398 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11399 | struct drm_device *dev = crtc->base.dev; | |
11400 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11401 | |
5a21b665 DV |
11402 | if (is_mmio_work(work)) |
11403 | flush_work(&work->mmio_work); | |
03f476e1 | 11404 | |
5a21b665 DV |
11405 | mutex_lock(&dev->struct_mutex); |
11406 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11407 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11408 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11409 | |
e8a261ea CW |
11410 | i915_gem_request_put(work->flip_queued_req); |
11411 | ||
5748b6a1 CW |
11412 | intel_frontbuffer_flip_complete(to_i915(dev), |
11413 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11414 | intel_fbc_post_update(crtc); |
11415 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11416 | |
5a21b665 DV |
11417 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11418 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11419 | |
5a21b665 DV |
11420 | kfree(work); |
11421 | } | |
d9e86c0e | 11422 | |
5a21b665 DV |
11423 | /* Is 'a' after or equal to 'b'? */ |
11424 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11425 | { | |
11426 | return !((a - b) & 0x80000000); | |
11427 | } | |
143f73b3 | 11428 | |
5a21b665 DV |
11429 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11430 | struct intel_flip_work *work) | |
11431 | { | |
11432 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11433 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 11434 | unsigned reset_counter; |
143f73b3 | 11435 | |
5a21b665 DV |
11436 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
11437 | if (crtc->reset_counter != reset_counter) | |
11438 | return true; | |
143f73b3 | 11439 | |
5a21b665 DV |
11440 | /* |
11441 | * The relevant registers doen't exist on pre-ctg. | |
11442 | * As the flip done interrupt doesn't trigger for mmio | |
11443 | * flips on gmch platforms, a flip count check isn't | |
11444 | * really needed there. But since ctg has the registers, | |
11445 | * include it in the check anyway. | |
11446 | */ | |
11447 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11448 | return true; | |
b4a98e57 | 11449 | |
5a21b665 DV |
11450 | /* |
11451 | * BDW signals flip done immediately if the plane | |
11452 | * is disabled, even if the plane enable is already | |
11453 | * armed to occur at the next vblank :( | |
11454 | */ | |
f99d7069 | 11455 | |
5a21b665 DV |
11456 | /* |
11457 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11458 | * used the same base address. In that case the mmio flip might | |
11459 | * have completed, but the CS hasn't even executed the flip yet. | |
11460 | * | |
11461 | * A flip count check isn't enough as the CS might have updated | |
11462 | * the base address just after start of vblank, but before we | |
11463 | * managed to process the interrupt. This means we'd complete the | |
11464 | * CS flip too soon. | |
11465 | * | |
11466 | * Combining both checks should get us a good enough result. It may | |
11467 | * still happen that the CS flip has been executed, but has not | |
11468 | * yet actually completed. But in case the base address is the same | |
11469 | * anyway, we don't really care. | |
11470 | */ | |
11471 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11472 | crtc->flip_work->gtt_offset && | |
11473 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11474 | crtc->flip_work->flip_count); | |
11475 | } | |
b4a98e57 | 11476 | |
5a21b665 DV |
11477 | static bool |
11478 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11479 | struct intel_flip_work *work) | |
11480 | { | |
11481 | /* | |
11482 | * MMIO work completes when vblank is different from | |
11483 | * flip_queued_vblank. | |
11484 | * | |
11485 | * Reset counter value doesn't matter, this is handled by | |
11486 | * i915_wait_request finishing early, so no need to handle | |
11487 | * reset here. | |
11488 | */ | |
11489 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11490 | } |
11491 | ||
51cbaf01 ML |
11492 | |
11493 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11494 | struct intel_flip_work *work) | |
11495 | { | |
11496 | if (!atomic_read(&work->pending)) | |
11497 | return false; | |
11498 | ||
11499 | smp_rmb(); | |
11500 | ||
5a21b665 DV |
11501 | if (is_mmio_work(work)) |
11502 | return __pageflip_finished_mmio(crtc, work); | |
11503 | else | |
11504 | return __pageflip_finished_cs(crtc, work); | |
11505 | } | |
11506 | ||
11507 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11508 | { | |
91c8a326 | 11509 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11510 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11511 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11512 | struct intel_flip_work *work; | |
11513 | unsigned long flags; | |
11514 | ||
11515 | /* Ignore early vblank irqs */ | |
11516 | if (!crtc) | |
11517 | return; | |
11518 | ||
51cbaf01 | 11519 | /* |
5a21b665 DV |
11520 | * This is called both by irq handlers and the reset code (to complete |
11521 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11522 | */ |
5a21b665 DV |
11523 | spin_lock_irqsave(&dev->event_lock, flags); |
11524 | work = intel_crtc->flip_work; | |
11525 | ||
11526 | if (work != NULL && | |
11527 | !is_mmio_work(work) && | |
11528 | pageflip_finished(intel_crtc, work)) | |
11529 | page_flip_completed(intel_crtc); | |
11530 | ||
11531 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11532 | } |
11533 | ||
51cbaf01 | 11534 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11535 | { |
91c8a326 | 11536 | struct drm_device *dev = &dev_priv->drm; |
5251f04e ML |
11537 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11539 | struct intel_flip_work *work; |
6b95a207 KH |
11540 | unsigned long flags; |
11541 | ||
5251f04e ML |
11542 | /* Ignore early vblank irqs */ |
11543 | if (!crtc) | |
11544 | return; | |
f326038a DV |
11545 | |
11546 | /* | |
11547 | * This is called both by irq handlers and the reset code (to complete | |
11548 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11549 | */ |
6b95a207 | 11550 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11551 | work = intel_crtc->flip_work; |
5251f04e | 11552 | |
5a21b665 DV |
11553 | if (work != NULL && |
11554 | is_mmio_work(work) && | |
11555 | pageflip_finished(intel_crtc, work)) | |
11556 | page_flip_completed(intel_crtc); | |
5251f04e | 11557 | |
6b95a207 KH |
11558 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11559 | } | |
11560 | ||
5a21b665 DV |
11561 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11562 | struct intel_flip_work *work) | |
84c33a64 | 11563 | { |
5a21b665 | 11564 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11565 | |
5a21b665 DV |
11566 | /* Ensure that the work item is consistent when activating it ... */ |
11567 | smp_mb__before_atomic(); | |
11568 | atomic_set(&work->pending, 1); | |
11569 | } | |
a6747b73 | 11570 | |
5a21b665 DV |
11571 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11572 | struct drm_crtc *crtc, | |
11573 | struct drm_framebuffer *fb, | |
11574 | struct drm_i915_gem_object *obj, | |
11575 | struct drm_i915_gem_request *req, | |
11576 | uint32_t flags) | |
11577 | { | |
7e37f889 | 11578 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11580 | u32 flip_mask; | |
11581 | int ret; | |
143f73b3 | 11582 | |
5a21b665 DV |
11583 | ret = intel_ring_begin(req, 6); |
11584 | if (ret) | |
11585 | return ret; | |
143f73b3 | 11586 | |
5a21b665 DV |
11587 | /* Can't queue multiple flips, so wait for the previous |
11588 | * one to finish before executing the next. | |
11589 | */ | |
11590 | if (intel_crtc->plane) | |
11591 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11592 | else | |
11593 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11594 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11595 | intel_ring_emit(ring, MI_NOOP); | |
11596 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11597 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11598 | intel_ring_emit(ring, fb->pitches[0]); |
11599 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11600 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11601 | |
5a21b665 DV |
11602 | return 0; |
11603 | } | |
84c33a64 | 11604 | |
5a21b665 DV |
11605 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11606 | struct drm_crtc *crtc, | |
11607 | struct drm_framebuffer *fb, | |
11608 | struct drm_i915_gem_object *obj, | |
11609 | struct drm_i915_gem_request *req, | |
11610 | uint32_t flags) | |
11611 | { | |
7e37f889 | 11612 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11614 | u32 flip_mask; | |
11615 | int ret; | |
d55dbd06 | 11616 | |
5a21b665 DV |
11617 | ret = intel_ring_begin(req, 6); |
11618 | if (ret) | |
11619 | return ret; | |
d55dbd06 | 11620 | |
5a21b665 DV |
11621 | if (intel_crtc->plane) |
11622 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11623 | else | |
11624 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11625 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11626 | intel_ring_emit(ring, MI_NOOP); | |
11627 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11628 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11629 | intel_ring_emit(ring, fb->pitches[0]); |
11630 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11631 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11632 | |
5a21b665 DV |
11633 | return 0; |
11634 | } | |
84c33a64 | 11635 | |
5a21b665 DV |
11636 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11637 | struct drm_crtc *crtc, | |
11638 | struct drm_framebuffer *fb, | |
11639 | struct drm_i915_gem_object *obj, | |
11640 | struct drm_i915_gem_request *req, | |
11641 | uint32_t flags) | |
11642 | { | |
7e37f889 | 11643 | struct intel_ring *ring = req->ring; |
fac5e23e | 11644 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11646 | uint32_t pf, pipesrc; | |
11647 | int ret; | |
143f73b3 | 11648 | |
5a21b665 DV |
11649 | ret = intel_ring_begin(req, 4); |
11650 | if (ret) | |
11651 | return ret; | |
143f73b3 | 11652 | |
5a21b665 DV |
11653 | /* i965+ uses the linear or tiled offsets from the |
11654 | * Display Registers (which do not change across a page-flip) | |
11655 | * so we need only reprogram the base address. | |
11656 | */ | |
b5321f30 | 11657 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11658 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11659 | intel_ring_emit(ring, fb->pitches[0]); |
11660 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
72618ebf | 11661 | intel_fb_modifier_to_tiling(fb->modifier[0])); |
5a21b665 DV |
11662 | |
11663 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11664 | * untested on non-native modes, so ignore it for now. | |
11665 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11666 | */ | |
11667 | pf = 0; | |
11668 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11669 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11670 | |
5a21b665 | 11671 | return 0; |
8c9f3aaf JB |
11672 | } |
11673 | ||
5a21b665 DV |
11674 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11675 | struct drm_crtc *crtc, | |
11676 | struct drm_framebuffer *fb, | |
11677 | struct drm_i915_gem_object *obj, | |
11678 | struct drm_i915_gem_request *req, | |
11679 | uint32_t flags) | |
da20eabd | 11680 | { |
7e37f889 | 11681 | struct intel_ring *ring = req->ring; |
fac5e23e | 11682 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11684 | uint32_t pf, pipesrc; | |
11685 | int ret; | |
d21fbe87 | 11686 | |
5a21b665 DV |
11687 | ret = intel_ring_begin(req, 4); |
11688 | if (ret) | |
11689 | return ret; | |
92826fcd | 11690 | |
b5321f30 | 11691 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11692 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
72618ebf VS |
11693 | intel_ring_emit(ring, fb->pitches[0] | |
11694 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 | 11695 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11696 | |
5a21b665 DV |
11697 | /* Contrary to the suggestions in the documentation, |
11698 | * "Enable Panel Fitter" does not seem to be required when page | |
11699 | * flipping with a non-native mode, and worse causes a normal | |
11700 | * modeset to fail. | |
11701 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11702 | */ | |
11703 | pf = 0; | |
11704 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11705 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11706 | |
5a21b665 | 11707 | return 0; |
7809e5ae MR |
11708 | } |
11709 | ||
5a21b665 DV |
11710 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11711 | struct drm_crtc *crtc, | |
11712 | struct drm_framebuffer *fb, | |
11713 | struct drm_i915_gem_object *obj, | |
11714 | struct drm_i915_gem_request *req, | |
11715 | uint32_t flags) | |
d21fbe87 | 11716 | { |
7e37f889 | 11717 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11718 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11719 | uint32_t plane_bit = 0; | |
11720 | int len, ret; | |
d21fbe87 | 11721 | |
5a21b665 DV |
11722 | switch (intel_crtc->plane) { |
11723 | case PLANE_A: | |
11724 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11725 | break; | |
11726 | case PLANE_B: | |
11727 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11728 | break; | |
11729 | case PLANE_C: | |
11730 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11731 | break; | |
11732 | default: | |
11733 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11734 | return -ENODEV; | |
11735 | } | |
11736 | ||
11737 | len = 4; | |
b5321f30 | 11738 | if (req->engine->id == RCS) { |
5a21b665 DV |
11739 | len += 6; |
11740 | /* | |
11741 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11742 | * 48bits addresses, and we need a NOOP for the batch size to | |
11743 | * stay even. | |
11744 | */ | |
11745 | if (IS_GEN8(dev)) | |
11746 | len += 2; | |
11747 | } | |
11748 | ||
11749 | /* | |
11750 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11751 | * "The full packet must be contained within the same cache line." | |
11752 | * | |
11753 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11754 | * cacheline, if we ever start emitting more commands before | |
11755 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11756 | * then do the cacheline alignment, and finally emit the | |
11757 | * MI_DISPLAY_FLIP. | |
11758 | */ | |
11759 | ret = intel_ring_cacheline_align(req); | |
11760 | if (ret) | |
11761 | return ret; | |
11762 | ||
11763 | ret = intel_ring_begin(req, len); | |
11764 | if (ret) | |
11765 | return ret; | |
11766 | ||
11767 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11768 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11769 | * more than one flip event at any time (or ensure that one flip message | |
11770 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11771 | * Experimentation says that BCS works despite DERRMR masking all | |
11772 | * flip-done completion events and that unmasking all planes at once | |
11773 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11774 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11775 | */ | |
b5321f30 CW |
11776 | if (req->engine->id == RCS) { |
11777 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11778 | intel_ring_emit_reg(ring, DERRMR); | |
11779 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11780 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11781 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11782 | if (IS_GEN8(dev)) | |
b5321f30 | 11783 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11784 | MI_SRM_LRM_GLOBAL_GTT); |
11785 | else | |
b5321f30 | 11786 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11787 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 | 11788 | intel_ring_emit_reg(ring, DERRMR); |
bde13ebd CW |
11789 | intel_ring_emit(ring, |
11790 | i915_ggtt_offset(req->engine->scratch) + 256); | |
5a21b665 | 11791 | if (IS_GEN8(dev)) { |
b5321f30 CW |
11792 | intel_ring_emit(ring, 0); |
11793 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11794 | } |
11795 | } | |
11796 | ||
b5321f30 | 11797 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
72618ebf VS |
11798 | intel_ring_emit(ring, fb->pitches[0] | |
11799 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 CW |
11800 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11801 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11802 | |
11803 | return 0; | |
11804 | } | |
11805 | ||
11806 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11807 | struct drm_i915_gem_object *obj) | |
11808 | { | |
c37efb99 CW |
11809 | struct reservation_object *resv; |
11810 | ||
5a21b665 DV |
11811 | /* |
11812 | * This is not being used for older platforms, because | |
11813 | * non-availability of flip done interrupt forces us to use | |
11814 | * CS flips. Older platforms derive flip done using some clever | |
11815 | * tricks involving the flip_pending status bits and vblank irqs. | |
11816 | * So using MMIO flips there would disrupt this mechanism. | |
11817 | */ | |
11818 | ||
11819 | if (engine == NULL) | |
11820 | return true; | |
11821 | ||
11822 | if (INTEL_GEN(engine->i915) < 5) | |
11823 | return false; | |
11824 | ||
11825 | if (i915.use_mmio_flip < 0) | |
11826 | return false; | |
11827 | else if (i915.use_mmio_flip > 0) | |
11828 | return true; | |
11829 | else if (i915.enable_execlists) | |
11830 | return true; | |
c37efb99 CW |
11831 | |
11832 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
11833 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) | |
5a21b665 | 11834 | return true; |
c37efb99 | 11835 | |
d72d908b CW |
11836 | return engine != i915_gem_active_get_engine(&obj->last_write, |
11837 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11838 | } |
11839 | ||
11840 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11841 | unsigned int rotation, | |
11842 | struct intel_flip_work *work) | |
11843 | { | |
11844 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11845 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11846 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11847 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 11848 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
11849 | |
11850 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11851 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11852 | switch (fb->modifier[0]) { | |
11853 | case DRM_FORMAT_MOD_NONE: | |
11854 | break; | |
11855 | case I915_FORMAT_MOD_X_TILED: | |
11856 | ctl |= PLANE_CTL_TILED_X; | |
11857 | break; | |
11858 | case I915_FORMAT_MOD_Y_TILED: | |
11859 | ctl |= PLANE_CTL_TILED_Y; | |
11860 | break; | |
11861 | case I915_FORMAT_MOD_Yf_TILED: | |
11862 | ctl |= PLANE_CTL_TILED_YF; | |
11863 | break; | |
11864 | default: | |
11865 | MISSING_CASE(fb->modifier[0]); | |
11866 | } | |
11867 | ||
5a21b665 DV |
11868 | /* |
11869 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11870 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11871 | */ | |
11872 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11873 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11874 | ||
11875 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11876 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11877 | } | |
11878 | ||
11879 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11880 | struct intel_flip_work *work) | |
11881 | { | |
11882 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11883 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 11884 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
11885 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
11886 | u32 dspcntr; | |
11887 | ||
11888 | dspcntr = I915_READ(reg); | |
11889 | ||
72618ebf | 11890 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
11891 | dspcntr |= DISPPLANE_TILED; |
11892 | else | |
11893 | dspcntr &= ~DISPPLANE_TILED; | |
11894 | ||
11895 | I915_WRITE(reg, dspcntr); | |
11896 | ||
11897 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11898 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11899 | } | |
11900 | ||
11901 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
11902 | { | |
11903 | struct intel_flip_work *work = | |
11904 | container_of(w, struct intel_flip_work, mmio_work); | |
11905 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
11906 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
11907 | struct intel_framebuffer *intel_fb = | |
11908 | to_intel_framebuffer(crtc->base.primary->fb); | |
11909 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
c37efb99 | 11910 | struct reservation_object *resv; |
5a21b665 DV |
11911 | |
11912 | if (work->flip_queued_req) | |
776f3236 CW |
11913 | WARN_ON(i915_wait_request(work->flip_queued_req, |
11914 | false, NULL, | |
11915 | NO_WAITBOOST)); | |
5a21b665 DV |
11916 | |
11917 | /* For framebuffer backed by dmabuf, wait for fence */ | |
c37efb99 CW |
11918 | resv = i915_gem_object_get_dmabuf_resv(obj); |
11919 | if (resv) | |
11920 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, | |
5a21b665 DV |
11921 | MAX_SCHEDULE_TIMEOUT) < 0); |
11922 | ||
11923 | intel_pipe_update_start(crtc); | |
11924 | ||
11925 | if (INTEL_GEN(dev_priv) >= 9) | |
11926 | skl_do_mmio_flip(crtc, work->rotation, work); | |
11927 | else | |
11928 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11929 | ilk_do_mmio_flip(crtc, work); | |
11930 | ||
11931 | intel_pipe_update_end(crtc, work); | |
11932 | } | |
11933 | ||
11934 | static int intel_default_queue_flip(struct drm_device *dev, | |
11935 | struct drm_crtc *crtc, | |
11936 | struct drm_framebuffer *fb, | |
11937 | struct drm_i915_gem_object *obj, | |
11938 | struct drm_i915_gem_request *req, | |
11939 | uint32_t flags) | |
11940 | { | |
11941 | return -ENODEV; | |
11942 | } | |
11943 | ||
11944 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
11945 | struct intel_crtc *intel_crtc, | |
11946 | struct intel_flip_work *work) | |
11947 | { | |
11948 | u32 addr, vblank; | |
11949 | ||
11950 | if (!atomic_read(&work->pending)) | |
11951 | return false; | |
11952 | ||
11953 | smp_rmb(); | |
11954 | ||
11955 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
11956 | if (work->flip_ready_vblank == 0) { | |
11957 | if (work->flip_queued_req && | |
f69a02c9 | 11958 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
11959 | return false; |
11960 | ||
11961 | work->flip_ready_vblank = vblank; | |
11962 | } | |
11963 | ||
11964 | if (vblank - work->flip_ready_vblank < 3) | |
11965 | return false; | |
11966 | ||
11967 | /* Potential stall - if we see that the flip has happened, | |
11968 | * assume a missed interrupt. */ | |
11969 | if (INTEL_GEN(dev_priv) >= 4) | |
11970 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11971 | else | |
11972 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11973 | ||
11974 | /* There is a potential issue here with a false positive after a flip | |
11975 | * to the same address. We could address this by checking for a | |
11976 | * non-incrementing frame counter. | |
11977 | */ | |
11978 | return addr == work->gtt_offset; | |
11979 | } | |
11980 | ||
11981 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
11982 | { | |
91c8a326 | 11983 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11984 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11986 | struct intel_flip_work *work; | |
11987 | ||
11988 | WARN_ON(!in_interrupt()); | |
11989 | ||
11990 | if (crtc == NULL) | |
11991 | return; | |
11992 | ||
11993 | spin_lock(&dev->event_lock); | |
11994 | work = intel_crtc->flip_work; | |
11995 | ||
11996 | if (work != NULL && !is_mmio_work(work) && | |
11997 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
11998 | WARN_ONCE(1, | |
11999 | "Kicking stuck page flip: queued at %d, now %d\n", | |
12000 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
12001 | page_flip_completed(intel_crtc); | |
12002 | work = NULL; | |
12003 | } | |
12004 | ||
12005 | if (work != NULL && !is_mmio_work(work) && | |
12006 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
12007 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
12008 | spin_unlock(&dev->event_lock); | |
12009 | } | |
12010 | ||
12011 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
12012 | struct drm_framebuffer *fb, | |
12013 | struct drm_pending_vblank_event *event, | |
12014 | uint32_t page_flip_flags) | |
12015 | { | |
12016 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 12017 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12018 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
12019 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12021 | struct drm_plane *primary = crtc->primary; | |
12022 | enum pipe pipe = intel_crtc->pipe; | |
12023 | struct intel_flip_work *work; | |
12024 | struct intel_engine_cs *engine; | |
12025 | bool mmio_flip; | |
8e637178 | 12026 | struct drm_i915_gem_request *request; |
058d88c4 | 12027 | struct i915_vma *vma; |
5a21b665 DV |
12028 | int ret; |
12029 | ||
12030 | /* | |
12031 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
12032 | * check to be safe. In the future we may enable pageflipping from | |
12033 | * a disabled primary plane. | |
12034 | */ | |
12035 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
12036 | return -EBUSY; | |
12037 | ||
12038 | /* Can't change pixel format via MI display flips. */ | |
12039 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
12040 | return -EINVAL; | |
12041 | ||
12042 | /* | |
12043 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
12044 | * Note that pitch changes could also affect these register. | |
12045 | */ | |
12046 | if (INTEL_INFO(dev)->gen > 3 && | |
12047 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
12048 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
12049 | return -EINVAL; | |
12050 | ||
12051 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
12052 | goto out_hang; | |
12053 | ||
12054 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
12055 | if (work == NULL) | |
12056 | return -ENOMEM; | |
12057 | ||
12058 | work->event = event; | |
12059 | work->crtc = crtc; | |
12060 | work->old_fb = old_fb; | |
12061 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
12062 | ||
12063 | ret = drm_crtc_vblank_get(crtc); | |
12064 | if (ret) | |
12065 | goto free_work; | |
12066 | ||
12067 | /* We borrow the event spin lock for protecting flip_work */ | |
12068 | spin_lock_irq(&dev->event_lock); | |
12069 | if (intel_crtc->flip_work) { | |
12070 | /* Before declaring the flip queue wedged, check if | |
12071 | * the hardware completed the operation behind our backs. | |
12072 | */ | |
12073 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
12074 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
12075 | page_flip_completed(intel_crtc); | |
12076 | } else { | |
12077 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
12078 | spin_unlock_irq(&dev->event_lock); | |
12079 | ||
12080 | drm_crtc_vblank_put(crtc); | |
12081 | kfree(work); | |
12082 | return -EBUSY; | |
12083 | } | |
12084 | } | |
12085 | intel_crtc->flip_work = work; | |
12086 | spin_unlock_irq(&dev->event_lock); | |
12087 | ||
12088 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
12089 | flush_workqueue(dev_priv->wq); | |
12090 | ||
12091 | /* Reference the objects for the scheduled work. */ | |
12092 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
12093 | |
12094 | crtc->primary->fb = fb; | |
12095 | update_state_fb(crtc->primary); | |
faf68d92 ML |
12096 | |
12097 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
12098 | to_intel_plane_state(primary->state)); | |
5a21b665 | 12099 | |
25dc556a | 12100 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
12101 | |
12102 | ret = i915_mutex_lock_interruptible(dev); | |
12103 | if (ret) | |
12104 | goto cleanup; | |
12105 | ||
12106 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
12107 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
12108 | ret = -EIO; | |
12109 | goto cleanup; | |
12110 | } | |
12111 | ||
12112 | atomic_inc(&intel_crtc->unpin_work_count); | |
12113 | ||
12114 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
12115 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
12116 | ||
12117 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
12118 | engine = &dev_priv->engine[BCS]; | |
72618ebf | 12119 | if (fb->modifier[0] != old_fb->modifier[0]) |
5a21b665 DV |
12120 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
12121 | engine = NULL; | |
12122 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
12123 | engine = &dev_priv->engine[BCS]; | |
12124 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
d72d908b CW |
12125 | engine = i915_gem_active_get_engine(&obj->last_write, |
12126 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
12127 | if (engine == NULL || engine->id != RCS) |
12128 | engine = &dev_priv->engine[BCS]; | |
12129 | } else { | |
12130 | engine = &dev_priv->engine[RCS]; | |
12131 | } | |
12132 | ||
12133 | mmio_flip = use_mmio_flip(engine, obj); | |
12134 | ||
058d88c4 CW |
12135 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
12136 | if (IS_ERR(vma)) { | |
12137 | ret = PTR_ERR(vma); | |
5a21b665 | 12138 | goto cleanup_pending; |
058d88c4 | 12139 | } |
5a21b665 | 12140 | |
6687c906 | 12141 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
12142 | work->gtt_offset += intel_crtc->dspaddr_offset; |
12143 | work->rotation = crtc->primary->state->rotation; | |
12144 | ||
12145 | if (mmio_flip) { | |
12146 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
12147 | ||
d72d908b CW |
12148 | work->flip_queued_req = i915_gem_active_get(&obj->last_write, |
12149 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
12150 | schedule_work(&work->mmio_work); |
12151 | } else { | |
8e637178 CW |
12152 | request = i915_gem_request_alloc(engine, engine->last_context); |
12153 | if (IS_ERR(request)) { | |
12154 | ret = PTR_ERR(request); | |
12155 | goto cleanup_unpin; | |
12156 | } | |
12157 | ||
12158 | ret = i915_gem_object_sync(obj, request); | |
12159 | if (ret) | |
12160 | goto cleanup_request; | |
12161 | ||
5a21b665 DV |
12162 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
12163 | page_flip_flags); | |
12164 | if (ret) | |
8e637178 | 12165 | goto cleanup_request; |
5a21b665 DV |
12166 | |
12167 | intel_mark_page_flip_active(intel_crtc, work); | |
12168 | ||
8e637178 | 12169 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
12170 | i915_add_request_no_flush(request); |
12171 | } | |
12172 | ||
12173 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
12174 | to_intel_plane(primary)->frontbuffer_bit); | |
12175 | mutex_unlock(&dev->struct_mutex); | |
12176 | ||
5748b6a1 | 12177 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
12178 | to_intel_plane(primary)->frontbuffer_bit); |
12179 | ||
12180 | trace_i915_flip_request(intel_crtc->plane, obj); | |
12181 | ||
12182 | return 0; | |
12183 | ||
8e637178 CW |
12184 | cleanup_request: |
12185 | i915_add_request_no_flush(request); | |
5a21b665 DV |
12186 | cleanup_unpin: |
12187 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
12188 | cleanup_pending: | |
5a21b665 DV |
12189 | atomic_dec(&intel_crtc->unpin_work_count); |
12190 | mutex_unlock(&dev->struct_mutex); | |
12191 | cleanup: | |
12192 | crtc->primary->fb = old_fb; | |
12193 | update_state_fb(crtc->primary); | |
12194 | ||
34911fd3 | 12195 | i915_gem_object_put_unlocked(obj); |
5a21b665 DV |
12196 | drm_framebuffer_unreference(work->old_fb); |
12197 | ||
12198 | spin_lock_irq(&dev->event_lock); | |
12199 | intel_crtc->flip_work = NULL; | |
12200 | spin_unlock_irq(&dev->event_lock); | |
12201 | ||
12202 | drm_crtc_vblank_put(crtc); | |
12203 | free_work: | |
12204 | kfree(work); | |
12205 | ||
12206 | if (ret == -EIO) { | |
12207 | struct drm_atomic_state *state; | |
12208 | struct drm_plane_state *plane_state; | |
12209 | ||
12210 | out_hang: | |
12211 | state = drm_atomic_state_alloc(dev); | |
12212 | if (!state) | |
12213 | return -ENOMEM; | |
12214 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
12215 | ||
12216 | retry: | |
12217 | plane_state = drm_atomic_get_plane_state(state, primary); | |
12218 | ret = PTR_ERR_OR_ZERO(plane_state); | |
12219 | if (!ret) { | |
12220 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
12221 | ||
12222 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
12223 | if (!ret) | |
12224 | ret = drm_atomic_commit(state); | |
12225 | } | |
12226 | ||
12227 | if (ret == -EDEADLK) { | |
12228 | drm_modeset_backoff(state->acquire_ctx); | |
12229 | drm_atomic_state_clear(state); | |
12230 | goto retry; | |
12231 | } | |
12232 | ||
12233 | if (ret) | |
12234 | drm_atomic_state_free(state); | |
12235 | ||
12236 | if (ret == 0 && event) { | |
12237 | spin_lock_irq(&dev->event_lock); | |
12238 | drm_crtc_send_vblank_event(crtc, event); | |
12239 | spin_unlock_irq(&dev->event_lock); | |
12240 | } | |
12241 | } | |
12242 | return ret; | |
12243 | } | |
12244 | ||
12245 | ||
12246 | /** | |
12247 | * intel_wm_need_update - Check whether watermarks need updating | |
12248 | * @plane: drm plane | |
12249 | * @state: new plane state | |
12250 | * | |
12251 | * Check current plane state versus the new one to determine whether | |
12252 | * watermarks need to be recalculated. | |
12253 | * | |
12254 | * Returns true or false. | |
12255 | */ | |
12256 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12257 | struct drm_plane_state *state) | |
12258 | { | |
12259 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12260 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12261 | ||
12262 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 12263 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
12264 | return true; |
12265 | ||
12266 | if (!cur->base.fb || !new->base.fb) | |
12267 | return false; | |
12268 | ||
12269 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
12270 | cur->base.rotation != new->base.rotation || | |
936e71e3 VS |
12271 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
12272 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
12273 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
12274 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
12275 | return true; |
12276 | ||
12277 | return false; | |
12278 | } | |
12279 | ||
12280 | static bool needs_scaling(struct intel_plane_state *state) | |
12281 | { | |
936e71e3 VS |
12282 | int src_w = drm_rect_width(&state->base.src) >> 16; |
12283 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
12284 | int dst_w = drm_rect_width(&state->base.dst); | |
12285 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
12286 | |
12287 | return (src_w != dst_w || src_h != dst_h); | |
12288 | } | |
d21fbe87 | 12289 | |
da20eabd ML |
12290 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12291 | struct drm_plane_state *plane_state) | |
12292 | { | |
ab1d3a0e | 12293 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12294 | struct drm_crtc *crtc = crtc_state->crtc; |
12295 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12296 | struct drm_plane *plane = plane_state->plane; | |
12297 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12298 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12299 | struct intel_plane_state *old_plane_state = |
12300 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12301 | bool mode_changed = needs_modeset(crtc_state); |
12302 | bool was_crtc_enabled = crtc->state->active; | |
12303 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12304 | bool turn_off, turn_on, visible, was_visible; |
12305 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12306 | int ret; |
da20eabd | 12307 | |
84114990 | 12308 | if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12309 | ret = skl_update_scaler_plane( |
12310 | to_intel_crtc_state(crtc_state), | |
12311 | to_intel_plane_state(plane_state)); | |
12312 | if (ret) | |
12313 | return ret; | |
12314 | } | |
12315 | ||
936e71e3 VS |
12316 | was_visible = old_plane_state->base.visible; |
12317 | visible = to_intel_plane_state(plane_state)->base.visible; | |
da20eabd ML |
12318 | |
12319 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12320 | was_visible = false; | |
12321 | ||
35c08f43 ML |
12322 | /* |
12323 | * Visibility is calculated as if the crtc was on, but | |
12324 | * after scaler setup everything depends on it being off | |
12325 | * when the crtc isn't active. | |
f818ffea VS |
12326 | * |
12327 | * FIXME this is wrong for watermarks. Watermarks should also | |
12328 | * be computed as if the pipe would be active. Perhaps move | |
12329 | * per-plane wm computation to the .check_plane() hook, and | |
12330 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12331 | */ |
12332 | if (!is_crtc_enabled) | |
936e71e3 | 12333 | to_intel_plane_state(plane_state)->base.visible = visible = false; |
da20eabd ML |
12334 | |
12335 | if (!was_visible && !visible) | |
12336 | return 0; | |
12337 | ||
e8861675 ML |
12338 | if (fb != old_plane_state->base.fb) |
12339 | pipe_config->fb_changed = true; | |
12340 | ||
da20eabd ML |
12341 | turn_off = was_visible && (!visible || mode_changed); |
12342 | turn_on = visible && (!was_visible || mode_changed); | |
12343 | ||
72660ce0 | 12344 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12345 | intel_crtc->base.base.id, |
12346 | intel_crtc->base.name, | |
72660ce0 VS |
12347 | plane->base.id, plane->name, |
12348 | fb ? fb->base.id : -1); | |
da20eabd | 12349 | |
72660ce0 VS |
12350 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12351 | plane->base.id, plane->name, | |
12352 | was_visible, visible, | |
da20eabd ML |
12353 | turn_off, turn_on, mode_changed); |
12354 | ||
caed361d VS |
12355 | if (turn_on) { |
12356 | pipe_config->update_wm_pre = true; | |
12357 | ||
12358 | /* must disable cxsr around plane enable/disable */ | |
12359 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12360 | pipe_config->disable_cxsr = true; | |
12361 | } else if (turn_off) { | |
12362 | pipe_config->update_wm_post = true; | |
92826fcd | 12363 | |
852eb00d | 12364 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12365 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12366 | pipe_config->disable_cxsr = true; |
852eb00d | 12367 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12368 | /* FIXME bollocks */ |
12369 | pipe_config->update_wm_pre = true; | |
12370 | pipe_config->update_wm_post = true; | |
852eb00d | 12371 | } |
da20eabd | 12372 | |
ed4a6a7c | 12373 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
12374 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
12375 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
12376 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12377 | ||
8be6ca85 | 12378 | if (visible || was_visible) |
cd202f69 | 12379 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12380 | |
31ae71fc ML |
12381 | /* |
12382 | * WaCxSRDisabledForSpriteScaling:ivb | |
12383 | * | |
12384 | * cstate->update_wm was already set above, so this flag will | |
12385 | * take effect when we commit and program watermarks. | |
12386 | */ | |
12387 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
12388 | needs_scaling(to_intel_plane_state(plane_state)) && | |
12389 | !needs_scaling(old_plane_state)) | |
12390 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12391 | |
da20eabd ML |
12392 | return 0; |
12393 | } | |
12394 | ||
6d3a1ce7 ML |
12395 | static bool encoders_cloneable(const struct intel_encoder *a, |
12396 | const struct intel_encoder *b) | |
12397 | { | |
12398 | /* masks could be asymmetric, so check both ways */ | |
12399 | return a == b || (a->cloneable & (1 << b->type) && | |
12400 | b->cloneable & (1 << a->type)); | |
12401 | } | |
12402 | ||
12403 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12404 | struct intel_crtc *crtc, | |
12405 | struct intel_encoder *encoder) | |
12406 | { | |
12407 | struct intel_encoder *source_encoder; | |
12408 | struct drm_connector *connector; | |
12409 | struct drm_connector_state *connector_state; | |
12410 | int i; | |
12411 | ||
12412 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12413 | if (connector_state->crtc != &crtc->base) | |
12414 | continue; | |
12415 | ||
12416 | source_encoder = | |
12417 | to_intel_encoder(connector_state->best_encoder); | |
12418 | if (!encoders_cloneable(encoder, source_encoder)) | |
12419 | return false; | |
12420 | } | |
12421 | ||
12422 | return true; | |
12423 | } | |
12424 | ||
6d3a1ce7 ML |
12425 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12426 | struct drm_crtc_state *crtc_state) | |
12427 | { | |
cf5a15be | 12428 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12429 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12430 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12431 | struct intel_crtc_state *pipe_config = |
12432 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12433 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12434 | int ret; |
6d3a1ce7 ML |
12435 | bool mode_changed = needs_modeset(crtc_state); |
12436 | ||
852eb00d | 12437 | if (mode_changed && !crtc_state->active) |
caed361d | 12438 | pipe_config->update_wm_post = true; |
eddfcbcd | 12439 | |
ad421372 ML |
12440 | if (mode_changed && crtc_state->enable && |
12441 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12442 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12443 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12444 | pipe_config); | |
12445 | if (ret) | |
12446 | return ret; | |
12447 | } | |
12448 | ||
82cf435b LL |
12449 | if (crtc_state->color_mgmt_changed) { |
12450 | ret = intel_color_check(crtc, crtc_state); | |
12451 | if (ret) | |
12452 | return ret; | |
e7852a4b LL |
12453 | |
12454 | /* | |
12455 | * Changing color management on Intel hardware is | |
12456 | * handled as part of planes update. | |
12457 | */ | |
12458 | crtc_state->planes_changed = true; | |
82cf435b LL |
12459 | } |
12460 | ||
e435d6e5 | 12461 | ret = 0; |
86c8bbbe | 12462 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12463 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12464 | if (ret) { |
12465 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12466 | return ret; | |
12467 | } | |
12468 | } | |
12469 | ||
12470 | if (dev_priv->display.compute_intermediate_wm && | |
12471 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12472 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12473 | return 0; | |
12474 | ||
12475 | /* | |
12476 | * Calculate 'intermediate' watermarks that satisfy both the | |
12477 | * old state and the new state. We can program these | |
12478 | * immediately. | |
12479 | */ | |
12480 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12481 | intel_crtc, | |
12482 | pipe_config); | |
12483 | if (ret) { | |
12484 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12485 | return ret; |
ed4a6a7c | 12486 | } |
e3d5457c VS |
12487 | } else if (dev_priv->display.compute_intermediate_wm) { |
12488 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12489 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12490 | } |
12491 | ||
e435d6e5 ML |
12492 | if (INTEL_INFO(dev)->gen >= 9) { |
12493 | if (mode_changed) | |
12494 | ret = skl_update_scaler_crtc(pipe_config); | |
12495 | ||
12496 | if (!ret) | |
12497 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12498 | pipe_config); | |
12499 | } | |
12500 | ||
12501 | return ret; | |
6d3a1ce7 ML |
12502 | } |
12503 | ||
65b38e0d | 12504 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12505 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12506 | .atomic_begin = intel_begin_crtc_commit, |
12507 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12508 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12509 | }; |
12510 | ||
d29b2f9d ACO |
12511 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12512 | { | |
12513 | struct intel_connector *connector; | |
12514 | ||
12515 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12516 | if (connector->base.state->crtc) |
12517 | drm_connector_unreference(&connector->base); | |
12518 | ||
d29b2f9d ACO |
12519 | if (connector->base.encoder) { |
12520 | connector->base.state->best_encoder = | |
12521 | connector->base.encoder; | |
12522 | connector->base.state->crtc = | |
12523 | connector->base.encoder->crtc; | |
8863dc7f DV |
12524 | |
12525 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12526 | } else { |
12527 | connector->base.state->best_encoder = NULL; | |
12528 | connector->base.state->crtc = NULL; | |
12529 | } | |
12530 | } | |
12531 | } | |
12532 | ||
050f7aeb | 12533 | static void |
eba905b2 | 12534 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12535 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12536 | { |
12537 | int bpp = pipe_config->pipe_bpp; | |
12538 | ||
12539 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12540 | connector->base.base.id, | |
c23cc417 | 12541 | connector->base.name); |
050f7aeb DV |
12542 | |
12543 | /* Don't use an invalid EDID bpc value */ | |
12544 | if (connector->base.display_info.bpc && | |
12545 | connector->base.display_info.bpc * 3 < bpp) { | |
12546 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12547 | bpp, connector->base.display_info.bpc*3); | |
12548 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12549 | } | |
12550 | ||
196f954e MK |
12551 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
12552 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
12553 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
12554 | bpp); | |
12555 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
12556 | } |
12557 | } | |
12558 | ||
4e53c2e0 | 12559 | static int |
050f7aeb | 12560 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12561 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12562 | { |
050f7aeb | 12563 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12564 | struct drm_atomic_state *state; |
da3ced29 ACO |
12565 | struct drm_connector *connector; |
12566 | struct drm_connector_state *connector_state; | |
1486017f | 12567 | int bpp, i; |
4e53c2e0 | 12568 | |
666a4537 | 12569 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12570 | bpp = 10*3; |
d328c9d7 DV |
12571 | else if (INTEL_INFO(dev)->gen >= 5) |
12572 | bpp = 12*3; | |
12573 | else | |
12574 | bpp = 8*3; | |
12575 | ||
4e53c2e0 | 12576 | |
4e53c2e0 DV |
12577 | pipe_config->pipe_bpp = bpp; |
12578 | ||
1486017f ACO |
12579 | state = pipe_config->base.state; |
12580 | ||
4e53c2e0 | 12581 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12582 | for_each_connector_in_state(state, connector, connector_state, i) { |
12583 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12584 | continue; |
12585 | ||
da3ced29 ACO |
12586 | connected_sink_compute_bpp(to_intel_connector(connector), |
12587 | pipe_config); | |
4e53c2e0 DV |
12588 | } |
12589 | ||
12590 | return bpp; | |
12591 | } | |
12592 | ||
644db711 DV |
12593 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12594 | { | |
12595 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12596 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12597 | mode->crtc_clock, |
644db711 DV |
12598 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12599 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12600 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12601 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12602 | } | |
12603 | ||
c0b03411 | 12604 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12605 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12606 | const char *context) |
12607 | { | |
6a60cd87 CK |
12608 | struct drm_device *dev = crtc->base.dev; |
12609 | struct drm_plane *plane; | |
12610 | struct intel_plane *intel_plane; | |
12611 | struct intel_plane_state *state; | |
12612 | struct drm_framebuffer *fb; | |
12613 | ||
78108b7c VS |
12614 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12615 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12616 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12617 | |
da205630 | 12618 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12619 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12620 | pipe_config->pipe_bpp, pipe_config->dither); | |
12621 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12622 | pipe_config->has_pch_encoder, | |
12623 | pipe_config->fdi_lanes, | |
12624 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12625 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12626 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12627 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12628 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12629 | pipe_config->lane_count, |
eb14cb74 VS |
12630 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12631 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12632 | pipe_config->dp_m_n.tu); | |
b95af8be | 12633 | |
90a6b7b0 | 12634 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12635 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12636 | pipe_config->lane_count, |
b95af8be VK |
12637 | pipe_config->dp_m2_n2.gmch_m, |
12638 | pipe_config->dp_m2_n2.gmch_n, | |
12639 | pipe_config->dp_m2_n2.link_m, | |
12640 | pipe_config->dp_m2_n2.link_n, | |
12641 | pipe_config->dp_m2_n2.tu); | |
12642 | ||
55072d19 DV |
12643 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12644 | pipe_config->has_audio, | |
12645 | pipe_config->has_infoframe); | |
12646 | ||
c0b03411 | 12647 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12648 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12649 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12650 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12651 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12652 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12653 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12654 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12655 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12656 | crtc->num_scalers, | |
12657 | pipe_config->scaler_state.scaler_users, | |
12658 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12659 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12660 | pipe_config->gmch_pfit.control, | |
12661 | pipe_config->gmch_pfit.pgm_ratios, | |
12662 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12663 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12664 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12665 | pipe_config->pch_pfit.size, |
12666 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12667 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12668 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12669 | |
415ff0f6 | 12670 | if (IS_BROXTON(dev)) { |
05712c15 | 12671 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12672 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12673 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12674 | pipe_config->ddi_pll_sel, |
12675 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12676 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12677 | pipe_config->dpll_hw_state.pll0, |
12678 | pipe_config->dpll_hw_state.pll1, | |
12679 | pipe_config->dpll_hw_state.pll2, | |
12680 | pipe_config->dpll_hw_state.pll3, | |
12681 | pipe_config->dpll_hw_state.pll6, | |
12682 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12683 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12684 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12685 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12686 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12687 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12688 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12689 | pipe_config->ddi_pll_sel, | |
12690 | pipe_config->dpll_hw_state.ctrl1, | |
12691 | pipe_config->dpll_hw_state.cfgcr1, | |
12692 | pipe_config->dpll_hw_state.cfgcr2); | |
12693 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12694 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12695 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12696 | pipe_config->dpll_hw_state.wrpll, |
12697 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12698 | } else { |
12699 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12700 | "fp0: 0x%x, fp1: 0x%x\n", | |
12701 | pipe_config->dpll_hw_state.dpll, | |
12702 | pipe_config->dpll_hw_state.dpll_md, | |
12703 | pipe_config->dpll_hw_state.fp0, | |
12704 | pipe_config->dpll_hw_state.fp1); | |
12705 | } | |
12706 | ||
6a60cd87 CK |
12707 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12708 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12709 | intel_plane = to_intel_plane(plane); | |
12710 | if (intel_plane->pipe != crtc->pipe) | |
12711 | continue; | |
12712 | ||
12713 | state = to_intel_plane_state(plane->state); | |
12714 | fb = state->base.fb; | |
12715 | if (!fb) { | |
1d577e02 VS |
12716 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12717 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12718 | continue; |
12719 | } | |
12720 | ||
1d577e02 VS |
12721 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12722 | plane->base.id, plane->name); | |
12723 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
12724 | fb->base.id, fb->width, fb->height, | |
12725 | drm_get_format_name(fb->pixel_format)); | |
12726 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12727 | state->scaler_id, | |
936e71e3 VS |
12728 | state->base.src.x1 >> 16, |
12729 | state->base.src.y1 >> 16, | |
12730 | drm_rect_width(&state->base.src) >> 16, | |
12731 | drm_rect_height(&state->base.src) >> 16, | |
12732 | state->base.dst.x1, state->base.dst.y1, | |
12733 | drm_rect_width(&state->base.dst), | |
12734 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 12735 | } |
c0b03411 DV |
12736 | } |
12737 | ||
5448a00d | 12738 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12739 | { |
5448a00d | 12740 | struct drm_device *dev = state->dev; |
da3ced29 | 12741 | struct drm_connector *connector; |
00f0b378 | 12742 | unsigned int used_ports = 0; |
477321e0 | 12743 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12744 | |
12745 | /* | |
12746 | * Walk the connector list instead of the encoder | |
12747 | * list to detect the problem on ddi platforms | |
12748 | * where there's just one encoder per digital port. | |
12749 | */ | |
0bff4858 VS |
12750 | drm_for_each_connector(connector, dev) { |
12751 | struct drm_connector_state *connector_state; | |
12752 | struct intel_encoder *encoder; | |
12753 | ||
12754 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12755 | if (!connector_state) | |
12756 | connector_state = connector->state; | |
12757 | ||
5448a00d | 12758 | if (!connector_state->best_encoder) |
00f0b378 VS |
12759 | continue; |
12760 | ||
5448a00d ACO |
12761 | encoder = to_intel_encoder(connector_state->best_encoder); |
12762 | ||
12763 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12764 | |
12765 | switch (encoder->type) { | |
12766 | unsigned int port_mask; | |
12767 | case INTEL_OUTPUT_UNKNOWN: | |
12768 | if (WARN_ON(!HAS_DDI(dev))) | |
12769 | break; | |
cca0502b | 12770 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12771 | case INTEL_OUTPUT_HDMI: |
12772 | case INTEL_OUTPUT_EDP: | |
12773 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12774 | ||
12775 | /* the same port mustn't appear more than once */ | |
12776 | if (used_ports & port_mask) | |
12777 | return false; | |
12778 | ||
12779 | used_ports |= port_mask; | |
477321e0 VS |
12780 | break; |
12781 | case INTEL_OUTPUT_DP_MST: | |
12782 | used_mst_ports |= | |
12783 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12784 | break; | |
00f0b378 VS |
12785 | default: |
12786 | break; | |
12787 | } | |
12788 | } | |
12789 | ||
477321e0 VS |
12790 | /* can't mix MST and SST/HDMI on the same port */ |
12791 | if (used_ports & used_mst_ports) | |
12792 | return false; | |
12793 | ||
00f0b378 VS |
12794 | return true; |
12795 | } | |
12796 | ||
83a57153 ACO |
12797 | static void |
12798 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12799 | { | |
12800 | struct drm_crtc_state tmp_state; | |
663a3640 | 12801 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12802 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12803 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12804 | uint32_t ddi_pll_sel; |
c4e2d043 | 12805 | bool force_thru; |
83a57153 | 12806 | |
7546a384 ACO |
12807 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12808 | * kzalloc'd. Code that depends on any field being zero should be | |
12809 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12810 | * only fields that are know to not cause problems are preserved. */ | |
12811 | ||
83a57153 | 12812 | tmp_state = crtc_state->base; |
663a3640 | 12813 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12814 | shared_dpll = crtc_state->shared_dpll; |
12815 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12816 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12817 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12818 | |
83a57153 | 12819 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12820 | |
83a57153 | 12821 | crtc_state->base = tmp_state; |
663a3640 | 12822 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12823 | crtc_state->shared_dpll = shared_dpll; |
12824 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12825 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12826 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12827 | } |
12828 | ||
548ee15b | 12829 | static int |
b8cecdf5 | 12830 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12831 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12832 | { |
b359283a | 12833 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12834 | struct intel_encoder *encoder; |
da3ced29 | 12835 | struct drm_connector *connector; |
0b901879 | 12836 | struct drm_connector_state *connector_state; |
d328c9d7 | 12837 | int base_bpp, ret = -EINVAL; |
0b901879 | 12838 | int i; |
e29c22c0 | 12839 | bool retry = true; |
ee7b9f93 | 12840 | |
83a57153 | 12841 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12842 | |
e143a21c DV |
12843 | pipe_config->cpu_transcoder = |
12844 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12845 | |
2960bc9c ID |
12846 | /* |
12847 | * Sanitize sync polarity flags based on requested ones. If neither | |
12848 | * positive or negative polarity is requested, treat this as meaning | |
12849 | * negative polarity. | |
12850 | */ | |
2d112de7 | 12851 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12852 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12853 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12854 | |
2d112de7 | 12855 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12856 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12857 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12858 | |
d328c9d7 DV |
12859 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12860 | pipe_config); | |
12861 | if (base_bpp < 0) | |
4e53c2e0 DV |
12862 | goto fail; |
12863 | ||
e41a56be VS |
12864 | /* |
12865 | * Determine the real pipe dimensions. Note that stereo modes can | |
12866 | * increase the actual pipe size due to the frame doubling and | |
12867 | * insertion of additional space for blanks between the frame. This | |
12868 | * is stored in the crtc timings. We use the requested mode to do this | |
12869 | * computation to clearly distinguish it from the adjusted mode, which | |
12870 | * can be changed by the connectors in the below retry loop. | |
12871 | */ | |
2d112de7 | 12872 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12873 | &pipe_config->pipe_src_w, |
12874 | &pipe_config->pipe_src_h); | |
e41a56be | 12875 | |
253c84c8 VS |
12876 | for_each_connector_in_state(state, connector, connector_state, i) { |
12877 | if (connector_state->crtc != crtc) | |
12878 | continue; | |
12879 | ||
12880 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12881 | ||
e25148d0 VS |
12882 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
12883 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12884 | goto fail; | |
12885 | } | |
12886 | ||
253c84c8 VS |
12887 | /* |
12888 | * Determine output_types before calling the .compute_config() | |
12889 | * hooks so that the hooks can use this information safely. | |
12890 | */ | |
12891 | pipe_config->output_types |= 1 << encoder->type; | |
12892 | } | |
12893 | ||
e29c22c0 | 12894 | encoder_retry: |
ef1b460d | 12895 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12896 | pipe_config->port_clock = 0; |
ef1b460d | 12897 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12898 | |
135c81b8 | 12899 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12900 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12901 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12902 | |
7758a113 DV |
12903 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12904 | * adjust it according to limitations or connector properties, and also | |
12905 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12906 | */ |
da3ced29 | 12907 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12908 | if (connector_state->crtc != crtc) |
7758a113 | 12909 | continue; |
7ae89233 | 12910 | |
0b901879 ACO |
12911 | encoder = to_intel_encoder(connector_state->best_encoder); |
12912 | ||
efea6e8e DV |
12913 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12914 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12915 | goto fail; |
12916 | } | |
ee7b9f93 | 12917 | } |
47f1c6c9 | 12918 | |
ff9a6750 DV |
12919 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12920 | * done afterwards in case the encoder adjusts the mode. */ | |
12921 | if (!pipe_config->port_clock) | |
2d112de7 | 12922 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12923 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12924 | |
a43f6e0f | 12925 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12926 | if (ret < 0) { |
7758a113 DV |
12927 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12928 | goto fail; | |
ee7b9f93 | 12929 | } |
e29c22c0 DV |
12930 | |
12931 | if (ret == RETRY) { | |
12932 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12933 | ret = -EINVAL; | |
12934 | goto fail; | |
12935 | } | |
12936 | ||
12937 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12938 | retry = false; | |
12939 | goto encoder_retry; | |
12940 | } | |
12941 | ||
e8fa4270 DV |
12942 | /* Dithering seems to not pass-through bits correctly when it should, so |
12943 | * only enable it on 6bpc panels. */ | |
12944 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12945 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12946 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12947 | |
7758a113 | 12948 | fail: |
548ee15b | 12949 | return ret; |
ee7b9f93 | 12950 | } |
47f1c6c9 | 12951 | |
ea9d758d | 12952 | static void |
4740b0f2 | 12953 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12954 | { |
0a9ab303 ACO |
12955 | struct drm_crtc *crtc; |
12956 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12957 | int i; |
ea9d758d | 12958 | |
7668851f | 12959 | /* Double check state. */ |
8a75d157 | 12960 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12961 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12962 | |
12963 | /* Update hwmode for vblank functions */ | |
12964 | if (crtc->state->active) | |
12965 | crtc->hwmode = crtc->state->adjusted_mode; | |
12966 | else | |
12967 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12968 | |
12969 | /* | |
12970 | * Update legacy state to satisfy fbc code. This can | |
12971 | * be removed when fbc uses the atomic state. | |
12972 | */ | |
12973 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12974 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12975 | ||
12976 | crtc->primary->fb = plane_state->fb; | |
12977 | crtc->x = plane_state->src_x >> 16; | |
12978 | crtc->y = plane_state->src_y >> 16; | |
12979 | } | |
ea9d758d | 12980 | } |
ea9d758d DV |
12981 | } |
12982 | ||
3bd26263 | 12983 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12984 | { |
3bd26263 | 12985 | int diff; |
f1f644dc JB |
12986 | |
12987 | if (clock1 == clock2) | |
12988 | return true; | |
12989 | ||
12990 | if (!clock1 || !clock2) | |
12991 | return false; | |
12992 | ||
12993 | diff = abs(clock1 - clock2); | |
12994 | ||
12995 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12996 | return true; | |
12997 | ||
12998 | return false; | |
12999 | } | |
13000 | ||
25c5b266 DV |
13001 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
13002 | list_for_each_entry((intel_crtc), \ | |
13003 | &(dev)->mode_config.crtc_list, \ | |
13004 | base.head) \ | |
95150bdf | 13005 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 13006 | |
cfb23ed6 ML |
13007 | static bool |
13008 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13009 | unsigned int m2, unsigned int n2, | |
13010 | bool exact) | |
13011 | { | |
13012 | if (m == m2 && n == n2) | |
13013 | return true; | |
13014 | ||
13015 | if (exact || !m || !n || !m2 || !n2) | |
13016 | return false; | |
13017 | ||
13018 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13019 | ||
31d10b57 ML |
13020 | if (n > n2) { |
13021 | while (n > n2) { | |
cfb23ed6 ML |
13022 | m2 <<= 1; |
13023 | n2 <<= 1; | |
13024 | } | |
31d10b57 ML |
13025 | } else if (n < n2) { |
13026 | while (n < n2) { | |
cfb23ed6 ML |
13027 | m <<= 1; |
13028 | n <<= 1; | |
13029 | } | |
13030 | } | |
13031 | ||
31d10b57 ML |
13032 | if (n != n2) |
13033 | return false; | |
13034 | ||
13035 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13036 | } |
13037 | ||
13038 | static bool | |
13039 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
13040 | struct intel_link_m_n *m2_n2, | |
13041 | bool adjust) | |
13042 | { | |
13043 | if (m_n->tu == m2_n2->tu && | |
13044 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13045 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
13046 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13047 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
13048 | if (adjust) | |
13049 | *m2_n2 = *m_n; | |
13050 | ||
13051 | return true; | |
13052 | } | |
13053 | ||
13054 | return false; | |
13055 | } | |
13056 | ||
0e8ffe1b | 13057 | static bool |
2fa2fe9a | 13058 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 13059 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
13060 | struct intel_crtc_state *pipe_config, |
13061 | bool adjust) | |
0e8ffe1b | 13062 | { |
cfb23ed6 ML |
13063 | bool ret = true; |
13064 | ||
13065 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
13066 | do { \ | |
13067 | if (!adjust) \ | |
13068 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
13069 | else \ | |
13070 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
13071 | } while (0) | |
13072 | ||
66e985c0 DV |
13073 | #define PIPE_CONF_CHECK_X(name) \ |
13074 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13075 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
13076 | "(expected 0x%08x, found 0x%08x)\n", \ |
13077 | current_config->name, \ | |
13078 | pipe_config->name); \ | |
cfb23ed6 | 13079 | ret = false; \ |
66e985c0 DV |
13080 | } |
13081 | ||
08a24034 DV |
13082 | #define PIPE_CONF_CHECK_I(name) \ |
13083 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13084 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
13085 | "(expected %i, found %i)\n", \ |
13086 | current_config->name, \ | |
13087 | pipe_config->name); \ | |
cfb23ed6 ML |
13088 | ret = false; \ |
13089 | } | |
13090 | ||
8106ddbd ACO |
13091 | #define PIPE_CONF_CHECK_P(name) \ |
13092 | if (current_config->name != pipe_config->name) { \ | |
13093 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13094 | "(expected %p, found %p)\n", \ | |
13095 | current_config->name, \ | |
13096 | pipe_config->name); \ | |
13097 | ret = false; \ | |
13098 | } | |
13099 | ||
cfb23ed6 ML |
13100 | #define PIPE_CONF_CHECK_M_N(name) \ |
13101 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13102 | &pipe_config->name,\ | |
13103 | adjust)) { \ | |
13104 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13105 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13106 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13107 | current_config->name.tu, \ | |
13108 | current_config->name.gmch_m, \ | |
13109 | current_config->name.gmch_n, \ | |
13110 | current_config->name.link_m, \ | |
13111 | current_config->name.link_n, \ | |
13112 | pipe_config->name.tu, \ | |
13113 | pipe_config->name.gmch_m, \ | |
13114 | pipe_config->name.gmch_n, \ | |
13115 | pipe_config->name.link_m, \ | |
13116 | pipe_config->name.link_n); \ | |
13117 | ret = false; \ | |
13118 | } | |
13119 | ||
55c561a7 DV |
13120 | /* This is required for BDW+ where there is only one set of registers for |
13121 | * switching between high and low RR. | |
13122 | * This macro can be used whenever a comparison has to be made between one | |
13123 | * hw state and multiple sw state variables. | |
13124 | */ | |
cfb23ed6 ML |
13125 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
13126 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13127 | &pipe_config->name, adjust) && \ | |
13128 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
13129 | &pipe_config->name, adjust)) { \ | |
13130 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13131 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13132 | "or tu %i gmch %i/%i link %i/%i, " \ | |
13133 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13134 | current_config->name.tu, \ | |
13135 | current_config->name.gmch_m, \ | |
13136 | current_config->name.gmch_n, \ | |
13137 | current_config->name.link_m, \ | |
13138 | current_config->name.link_n, \ | |
13139 | current_config->alt_name.tu, \ | |
13140 | current_config->alt_name.gmch_m, \ | |
13141 | current_config->alt_name.gmch_n, \ | |
13142 | current_config->alt_name.link_m, \ | |
13143 | current_config->alt_name.link_n, \ | |
13144 | pipe_config->name.tu, \ | |
13145 | pipe_config->name.gmch_m, \ | |
13146 | pipe_config->name.gmch_n, \ | |
13147 | pipe_config->name.link_m, \ | |
13148 | pipe_config->name.link_n); \ | |
13149 | ret = false; \ | |
88adfff1 DV |
13150 | } |
13151 | ||
1bd1bd80 DV |
13152 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
13153 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 13154 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
13155 | "(expected %i, found %i)\n", \ |
13156 | current_config->name & (mask), \ | |
13157 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 13158 | ret = false; \ |
1bd1bd80 DV |
13159 | } |
13160 | ||
5e550656 VS |
13161 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
13162 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 13163 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
13164 | "(expected %i, found %i)\n", \ |
13165 | current_config->name, \ | |
13166 | pipe_config->name); \ | |
cfb23ed6 | 13167 | ret = false; \ |
5e550656 VS |
13168 | } |
13169 | ||
bb760063 DV |
13170 | #define PIPE_CONF_QUIRK(quirk) \ |
13171 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
13172 | ||
eccb140b DV |
13173 | PIPE_CONF_CHECK_I(cpu_transcoder); |
13174 | ||
08a24034 DV |
13175 | PIPE_CONF_CHECK_I(has_pch_encoder); |
13176 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 13177 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 13178 | |
90a6b7b0 | 13179 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 13180 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
13181 | |
13182 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
13183 | PIPE_CONF_CHECK_M_N(dp_m_n); |
13184 | ||
cfb23ed6 ML |
13185 | if (current_config->has_drrs) |
13186 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
13187 | } else | |
13188 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 13189 | |
253c84c8 | 13190 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 13191 | |
2d112de7 ACO |
13192 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
13193 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
13194 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
13195 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
13196 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
13197 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 13198 | |
2d112de7 ACO |
13199 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
13200 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
13201 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
13202 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
13203 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
13204 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 13205 | |
c93f54cf | 13206 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 13207 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 13208 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 13209 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 13210 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 13211 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 13212 | |
9ed109a7 DV |
13213 | PIPE_CONF_CHECK_I(has_audio); |
13214 | ||
2d112de7 | 13215 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
13216 | DRM_MODE_FLAG_INTERLACE); |
13217 | ||
bb760063 | 13218 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13219 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13220 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13221 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13222 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13223 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13224 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13225 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13226 | DRM_MODE_FLAG_NVSYNC); |
13227 | } | |
045ac3b5 | 13228 | |
333b8ca8 | 13229 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
13230 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
13231 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 13232 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13233 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13234 | |
bfd16b2a ML |
13235 | if (!adjust) { |
13236 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13237 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13238 | ||
13239 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13240 | if (current_config->pch_pfit.enabled) { | |
13241 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13242 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13243 | } | |
2fa2fe9a | 13244 | |
7aefe2b5 ML |
13245 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13246 | } | |
a1b2278e | 13247 | |
e59150dc JB |
13248 | /* BDW+ don't expose a synchronous way to read the state */ |
13249 | if (IS_HASWELL(dev)) | |
13250 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 13251 | |
282740f7 VS |
13252 | PIPE_CONF_CHECK_I(double_wide); |
13253 | ||
26804afd DV |
13254 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
13255 | ||
8106ddbd | 13256 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13257 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13258 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13259 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13260 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13261 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13262 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13263 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13264 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13265 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13266 | |
47eacbab VS |
13267 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13268 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13269 | ||
42571aef VS |
13270 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
13271 | PIPE_CONF_CHECK_I(pipe_bpp); | |
13272 | ||
2d112de7 | 13273 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13274 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13275 | |
66e985c0 | 13276 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13277 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13278 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13279 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13280 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13281 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 13282 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 13283 | |
cfb23ed6 | 13284 | return ret; |
0e8ffe1b DV |
13285 | } |
13286 | ||
e3b247da VS |
13287 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13288 | const struct intel_crtc_state *pipe_config) | |
13289 | { | |
13290 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13291 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13292 | &pipe_config->fdi_m_n); |
13293 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13294 | ||
13295 | /* | |
13296 | * FDI already provided one idea for the dotclock. | |
13297 | * Yell if the encoder disagrees. | |
13298 | */ | |
13299 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13300 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13301 | fdi_dotclock, dotclock); | |
13302 | } | |
13303 | } | |
13304 | ||
c0ead703 ML |
13305 | static void verify_wm_state(struct drm_crtc *crtc, |
13306 | struct drm_crtc_state *new_state) | |
08db6652 | 13307 | { |
e7c84544 | 13308 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13309 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 13310 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
e7c84544 ML |
13311 | struct skl_ddb_entry *hw_entry, *sw_entry; |
13312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13313 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
13314 | int plane; |
13315 | ||
e7c84544 | 13316 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
13317 | return; |
13318 | ||
13319 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
13320 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13321 | ||
e7c84544 ML |
13322 | /* planes */ |
13323 | for_each_plane(dev_priv, pipe, plane) { | |
13324 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
13325 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 13326 | |
e7c84544 | 13327 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
13328 | continue; |
13329 | ||
e7c84544 ML |
13330 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
13331 | "(expected (%u,%u), found (%u,%u))\n", | |
13332 | pipe_name(pipe), plane + 1, | |
13333 | sw_entry->start, sw_entry->end, | |
13334 | hw_entry->start, hw_entry->end); | |
13335 | } | |
08db6652 | 13336 | |
e7c84544 ML |
13337 | /* cursor */ |
13338 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13339 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 13340 | |
e7c84544 | 13341 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
13342 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
13343 | "(expected (%u,%u), found (%u,%u))\n", | |
13344 | pipe_name(pipe), | |
13345 | sw_entry->start, sw_entry->end, | |
13346 | hw_entry->start, hw_entry->end); | |
13347 | } | |
13348 | } | |
13349 | ||
91d1b4bd | 13350 | static void |
c0ead703 | 13351 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 13352 | { |
35dd3c64 | 13353 | struct drm_connector *connector; |
8af6cf88 | 13354 | |
e7c84544 | 13355 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
13356 | struct drm_encoder *encoder = connector->encoder; |
13357 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13358 | |
e7c84544 ML |
13359 | if (state->crtc != crtc) |
13360 | continue; | |
13361 | ||
5a21b665 | 13362 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13363 | |
ad3c558f | 13364 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13365 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13366 | } |
91d1b4bd DV |
13367 | } |
13368 | ||
13369 | static void | |
c0ead703 | 13370 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13371 | { |
13372 | struct intel_encoder *encoder; | |
13373 | struct intel_connector *connector; | |
8af6cf88 | 13374 | |
b2784e15 | 13375 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13376 | bool enabled = false; |
4d20cd86 | 13377 | enum pipe pipe; |
8af6cf88 DV |
13378 | |
13379 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13380 | encoder->base.base.id, | |
8e329a03 | 13381 | encoder->base.name); |
8af6cf88 | 13382 | |
3a3371ff | 13383 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13384 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13385 | continue; |
13386 | enabled = true; | |
ad3c558f ML |
13387 | |
13388 | I915_STATE_WARN(connector->base.state->crtc != | |
13389 | encoder->base.crtc, | |
13390 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13391 | } |
0e32b39c | 13392 | |
e2c719b7 | 13393 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13394 | "encoder's enabled state mismatch " |
13395 | "(expected %i, found %i)\n", | |
13396 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13397 | |
13398 | if (!encoder->base.crtc) { | |
4d20cd86 | 13399 | bool active; |
7c60d198 | 13400 | |
4d20cd86 ML |
13401 | active = encoder->get_hw_state(encoder, &pipe); |
13402 | I915_STATE_WARN(active, | |
13403 | "encoder detached but still enabled on pipe %c.\n", | |
13404 | pipe_name(pipe)); | |
7c60d198 | 13405 | } |
8af6cf88 | 13406 | } |
91d1b4bd DV |
13407 | } |
13408 | ||
13409 | static void | |
c0ead703 ML |
13410 | verify_crtc_state(struct drm_crtc *crtc, |
13411 | struct drm_crtc_state *old_crtc_state, | |
13412 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13413 | { |
e7c84544 | 13414 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13415 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13416 | struct intel_encoder *encoder; |
e7c84544 ML |
13417 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13418 | struct intel_crtc_state *pipe_config, *sw_config; | |
13419 | struct drm_atomic_state *old_state; | |
13420 | bool active; | |
045ac3b5 | 13421 | |
e7c84544 | 13422 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13423 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13424 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13425 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13426 | pipe_config->base.crtc = crtc; | |
13427 | pipe_config->base.state = old_state; | |
8af6cf88 | 13428 | |
78108b7c | 13429 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13430 | |
e7c84544 | 13431 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13432 | |
e7c84544 ML |
13433 | /* hw state is inconsistent with the pipe quirk */ |
13434 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13435 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13436 | active = new_crtc_state->active; | |
6c49f241 | 13437 | |
e7c84544 ML |
13438 | I915_STATE_WARN(new_crtc_state->active != active, |
13439 | "crtc active state doesn't match with hw state " | |
13440 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13441 | |
e7c84544 ML |
13442 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13443 | "transitional active state does not match atomic hw state " | |
13444 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13445 | |
e7c84544 ML |
13446 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13447 | enum pipe pipe; | |
4d20cd86 | 13448 | |
e7c84544 ML |
13449 | active = encoder->get_hw_state(encoder, &pipe); |
13450 | I915_STATE_WARN(active != new_crtc_state->active, | |
13451 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13452 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13453 | |
e7c84544 ML |
13454 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13455 | "Encoder connected to wrong pipe %c\n", | |
13456 | pipe_name(pipe)); | |
4d20cd86 | 13457 | |
253c84c8 VS |
13458 | if (active) { |
13459 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13460 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13461 | } |
e7c84544 | 13462 | } |
53d9f4e9 | 13463 | |
e7c84544 ML |
13464 | if (!new_crtc_state->active) |
13465 | return; | |
cfb23ed6 | 13466 | |
e7c84544 | 13467 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13468 | |
e7c84544 ML |
13469 | sw_config = to_intel_crtc_state(crtc->state); |
13470 | if (!intel_pipe_config_compare(dev, sw_config, | |
13471 | pipe_config, false)) { | |
13472 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13473 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13474 | "[hw state]"); | |
13475 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13476 | "[sw state]"); | |
8af6cf88 DV |
13477 | } |
13478 | } | |
13479 | ||
91d1b4bd | 13480 | static void |
c0ead703 ML |
13481 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13482 | struct intel_shared_dpll *pll, | |
13483 | struct drm_crtc *crtc, | |
13484 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13485 | { |
91d1b4bd | 13486 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13487 | unsigned crtc_mask; |
13488 | bool active; | |
5358901f | 13489 | |
e7c84544 | 13490 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13491 | |
e7c84544 | 13492 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13493 | |
e7c84544 | 13494 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13495 | |
e7c84544 ML |
13496 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13497 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13498 | "pll in active use but not on in sw tracking\n"); | |
13499 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13500 | "pll is on but not used by any active crtc\n"); | |
13501 | I915_STATE_WARN(pll->on != active, | |
13502 | "pll on state mismatch (expected %i, found %i)\n", | |
13503 | pll->on, active); | |
13504 | } | |
5358901f | 13505 | |
e7c84544 | 13506 | if (!crtc) { |
2dd66ebd | 13507 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13508 | "more active pll users than references: %x vs %x\n", |
13509 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13510 | |
e7c84544 ML |
13511 | return; |
13512 | } | |
13513 | ||
13514 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13515 | ||
13516 | if (new_state->active) | |
13517 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13518 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13519 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13520 | else | |
13521 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13522 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13523 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13524 | |
e7c84544 ML |
13525 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13526 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13527 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13528 | |
e7c84544 ML |
13529 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13530 | &dpll_hw_state, | |
13531 | sizeof(dpll_hw_state)), | |
13532 | "pll hw state mismatch\n"); | |
13533 | } | |
13534 | ||
13535 | static void | |
c0ead703 ML |
13536 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13537 | struct drm_crtc_state *old_crtc_state, | |
13538 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13539 | { |
fac5e23e | 13540 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13541 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13542 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13543 | ||
13544 | if (new_state->shared_dpll) | |
c0ead703 | 13545 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13546 | |
13547 | if (old_state->shared_dpll && | |
13548 | old_state->shared_dpll != new_state->shared_dpll) { | |
13549 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13550 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13551 | ||
13552 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13553 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13554 | pipe_name(drm_crtc_index(crtc))); | |
13555 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13556 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13557 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13558 | } |
8af6cf88 DV |
13559 | } |
13560 | ||
e7c84544 | 13561 | static void |
c0ead703 | 13562 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13563 | struct drm_crtc_state *old_state, |
13564 | struct drm_crtc_state *new_state) | |
13565 | { | |
5a21b665 DV |
13566 | if (!needs_modeset(new_state) && |
13567 | !to_intel_crtc_state(new_state)->update_pipe) | |
13568 | return; | |
13569 | ||
c0ead703 | 13570 | verify_wm_state(crtc, new_state); |
5a21b665 | 13571 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13572 | verify_crtc_state(crtc, old_state, new_state); |
13573 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13574 | } |
13575 | ||
13576 | static void | |
c0ead703 | 13577 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13578 | { |
fac5e23e | 13579 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13580 | int i; |
13581 | ||
13582 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13583 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13584 | } |
13585 | ||
13586 | static void | |
c0ead703 | 13587 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13588 | { |
c0ead703 ML |
13589 | verify_encoder_state(dev); |
13590 | verify_connector_state(dev, NULL); | |
13591 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13592 | } |
13593 | ||
80715b2f VS |
13594 | static void update_scanline_offset(struct intel_crtc *crtc) |
13595 | { | |
13596 | struct drm_device *dev = crtc->base.dev; | |
13597 | ||
13598 | /* | |
13599 | * The scanline counter increments at the leading edge of hsync. | |
13600 | * | |
13601 | * On most platforms it starts counting from vtotal-1 on the | |
13602 | * first active line. That means the scanline counter value is | |
13603 | * always one less than what we would expect. Ie. just after | |
13604 | * start of vblank, which also occurs at start of hsync (on the | |
13605 | * last active line), the scanline counter will read vblank_start-1. | |
13606 | * | |
13607 | * On gen2 the scanline counter starts counting from 1 instead | |
13608 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13609 | * to keep the value positive), instead of adding one. | |
13610 | * | |
13611 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13612 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13613 | * there's an extra 1 line difference. So we need to add two instead of | |
13614 | * one to the value. | |
13615 | */ | |
13616 | if (IS_GEN2(dev)) { | |
124abe07 | 13617 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13618 | int vtotal; |
13619 | ||
124abe07 VS |
13620 | vtotal = adjusted_mode->crtc_vtotal; |
13621 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13622 | vtotal /= 2; |
13623 | ||
13624 | crtc->scanline_offset = vtotal - 1; | |
13625 | } else if (HAS_DDI(dev) && | |
2d84d2b3 | 13626 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13627 | crtc->scanline_offset = 2; |
13628 | } else | |
13629 | crtc->scanline_offset = 1; | |
13630 | } | |
13631 | ||
ad421372 | 13632 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13633 | { |
225da59b | 13634 | struct drm_device *dev = state->dev; |
ed6739ef | 13635 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13636 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13637 | struct drm_crtc *crtc; |
13638 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13639 | int i; |
ed6739ef ACO |
13640 | |
13641 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13642 | return; |
ed6739ef | 13643 | |
0a9ab303 | 13644 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13646 | struct intel_shared_dpll *old_dpll = |
13647 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13648 | |
fb1a38a9 | 13649 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13650 | continue; |
13651 | ||
8106ddbd | 13652 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13653 | |
8106ddbd | 13654 | if (!old_dpll) |
fb1a38a9 | 13655 | continue; |
0a9ab303 | 13656 | |
ad421372 ML |
13657 | if (!shared_dpll) |
13658 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13659 | |
8106ddbd | 13660 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13661 | } |
ed6739ef ACO |
13662 | } |
13663 | ||
99d736a2 ML |
13664 | /* |
13665 | * This implements the workaround described in the "notes" section of the mode | |
13666 | * set sequence documentation. When going from no pipes or single pipe to | |
13667 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13668 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13669 | */ | |
13670 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13671 | { | |
13672 | struct drm_crtc_state *crtc_state; | |
13673 | struct intel_crtc *intel_crtc; | |
13674 | struct drm_crtc *crtc; | |
13675 | struct intel_crtc_state *first_crtc_state = NULL; | |
13676 | struct intel_crtc_state *other_crtc_state = NULL; | |
13677 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13678 | int i; | |
13679 | ||
13680 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13681 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13682 | intel_crtc = to_intel_crtc(crtc); | |
13683 | ||
13684 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13685 | continue; | |
13686 | ||
13687 | if (first_crtc_state) { | |
13688 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13689 | break; | |
13690 | } else { | |
13691 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13692 | first_pipe = intel_crtc->pipe; | |
13693 | } | |
13694 | } | |
13695 | ||
13696 | /* No workaround needed? */ | |
13697 | if (!first_crtc_state) | |
13698 | return 0; | |
13699 | ||
13700 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13701 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13702 | struct intel_crtc_state *pipe_config; | |
13703 | ||
13704 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13705 | if (IS_ERR(pipe_config)) | |
13706 | return PTR_ERR(pipe_config); | |
13707 | ||
13708 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13709 | ||
13710 | if (!pipe_config->base.active || | |
13711 | needs_modeset(&pipe_config->base)) | |
13712 | continue; | |
13713 | ||
13714 | /* 2 or more enabled crtcs means no need for w/a */ | |
13715 | if (enabled_pipe != INVALID_PIPE) | |
13716 | return 0; | |
13717 | ||
13718 | enabled_pipe = intel_crtc->pipe; | |
13719 | } | |
13720 | ||
13721 | if (enabled_pipe != INVALID_PIPE) | |
13722 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13723 | else if (other_crtc_state) | |
13724 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13725 | ||
13726 | return 0; | |
13727 | } | |
13728 | ||
27c329ed ML |
13729 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13730 | { | |
13731 | struct drm_crtc *crtc; | |
13732 | struct drm_crtc_state *crtc_state; | |
13733 | int ret = 0; | |
13734 | ||
13735 | /* add all active pipes to the state */ | |
13736 | for_each_crtc(state->dev, crtc) { | |
13737 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13738 | if (IS_ERR(crtc_state)) | |
13739 | return PTR_ERR(crtc_state); | |
13740 | ||
13741 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13742 | continue; | |
13743 | ||
13744 | crtc_state->mode_changed = true; | |
13745 | ||
13746 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13747 | if (ret) | |
13748 | break; | |
13749 | ||
13750 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13751 | if (ret) | |
13752 | break; | |
13753 | } | |
13754 | ||
13755 | return ret; | |
13756 | } | |
13757 | ||
c347a676 | 13758 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13759 | { |
565602d7 | 13760 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13761 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13762 | struct drm_crtc *crtc; |
13763 | struct drm_crtc_state *crtc_state; | |
13764 | int ret = 0, i; | |
054518dd | 13765 | |
b359283a ML |
13766 | if (!check_digital_port_conflicts(state)) { |
13767 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13768 | return -EINVAL; | |
13769 | } | |
13770 | ||
565602d7 ML |
13771 | intel_state->modeset = true; |
13772 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13773 | ||
13774 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13775 | if (crtc_state->active) | |
13776 | intel_state->active_crtcs |= 1 << i; | |
13777 | else | |
13778 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13779 | |
13780 | if (crtc_state->active != crtc->state->active) | |
13781 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13782 | } |
13783 | ||
054518dd ACO |
13784 | /* |
13785 | * See if the config requires any additional preparation, e.g. | |
13786 | * to adjust global state with pipes off. We need to do this | |
13787 | * here so we can get the modeset_pipe updated config for the new | |
13788 | * mode set on this crtc. For other crtcs we need to use the | |
13789 | * adjusted_mode bits in the crtc directly. | |
13790 | */ | |
27c329ed | 13791 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13792 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13793 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13794 | if (!intel_state->cdclk_pll_vco) |
13795 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13796 | |
27c329ed | 13797 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13798 | if (ret < 0) |
13799 | return ret; | |
27c329ed | 13800 | |
c89e39f3 | 13801 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13802 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
13803 | ret = intel_modeset_all_pipes(state); |
13804 | ||
13805 | if (ret < 0) | |
054518dd | 13806 | return ret; |
e8788cbc ML |
13807 | |
13808 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13809 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13810 | } else |
1a617b77 | 13811 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13812 | |
ad421372 | 13813 | intel_modeset_clear_plls(state); |
054518dd | 13814 | |
565602d7 | 13815 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13816 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13817 | |
ad421372 | 13818 | return 0; |
c347a676 ACO |
13819 | } |
13820 | ||
aa363136 MR |
13821 | /* |
13822 | * Handle calculation of various watermark data at the end of the atomic check | |
13823 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13824 | * handlers to ensure that all derived state has been updated. | |
13825 | */ | |
55994c2c | 13826 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13827 | { |
13828 | struct drm_device *dev = state->dev; | |
98d39494 | 13829 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13830 | |
13831 | /* Is there platform-specific watermark information to calculate? */ | |
13832 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13833 | return dev_priv->display.compute_global_watermarks(state); |
13834 | ||
13835 | return 0; | |
aa363136 MR |
13836 | } |
13837 | ||
74c090b1 ML |
13838 | /** |
13839 | * intel_atomic_check - validate state object | |
13840 | * @dev: drm device | |
13841 | * @state: state to validate | |
13842 | */ | |
13843 | static int intel_atomic_check(struct drm_device *dev, | |
13844 | struct drm_atomic_state *state) | |
c347a676 | 13845 | { |
dd8b3bdb | 13846 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13847 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13848 | struct drm_crtc *crtc; |
13849 | struct drm_crtc_state *crtc_state; | |
13850 | int ret, i; | |
61333b60 | 13851 | bool any_ms = false; |
c347a676 | 13852 | |
74c090b1 | 13853 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13854 | if (ret) |
13855 | return ret; | |
13856 | ||
c347a676 | 13857 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13858 | struct intel_crtc_state *pipe_config = |
13859 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13860 | |
13861 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13862 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13863 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13864 | |
af4a879e | 13865 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13866 | continue; |
13867 | ||
af4a879e DV |
13868 | if (!crtc_state->enable) { |
13869 | any_ms = true; | |
cfb23ed6 | 13870 | continue; |
af4a879e | 13871 | } |
cfb23ed6 | 13872 | |
26495481 DV |
13873 | /* FIXME: For only active_changed we shouldn't need to do any |
13874 | * state recomputation at all. */ | |
13875 | ||
1ed51de9 DV |
13876 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13877 | if (ret) | |
13878 | return ret; | |
b359283a | 13879 | |
cfb23ed6 | 13880 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13881 | if (ret) { |
13882 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13883 | pipe_config, "[failed]"); | |
c347a676 | 13884 | return ret; |
25aa1c39 | 13885 | } |
c347a676 | 13886 | |
73831236 | 13887 | if (i915.fastboot && |
dd8b3bdb | 13888 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13889 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13890 | pipe_config, true)) { |
26495481 | 13891 | crtc_state->mode_changed = false; |
bfd16b2a | 13892 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13893 | } |
13894 | ||
af4a879e | 13895 | if (needs_modeset(crtc_state)) |
26495481 | 13896 | any_ms = true; |
cfb23ed6 | 13897 | |
af4a879e DV |
13898 | ret = drm_atomic_add_affected_planes(state, crtc); |
13899 | if (ret) | |
13900 | return ret; | |
61333b60 | 13901 | |
26495481 DV |
13902 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13903 | needs_modeset(crtc_state) ? | |
13904 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13905 | } |
13906 | ||
61333b60 ML |
13907 | if (any_ms) { |
13908 | ret = intel_modeset_checks(state); | |
13909 | ||
13910 | if (ret) | |
13911 | return ret; | |
27c329ed | 13912 | } else |
dd8b3bdb | 13913 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13914 | |
dd8b3bdb | 13915 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13916 | if (ret) |
13917 | return ret; | |
13918 | ||
f51be2e0 | 13919 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13920 | return calc_watermark_data(state); |
054518dd ACO |
13921 | } |
13922 | ||
5008e874 ML |
13923 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13924 | struct drm_atomic_state *state, | |
81072bfd | 13925 | bool nonblock) |
5008e874 | 13926 | { |
fac5e23e | 13927 | struct drm_i915_private *dev_priv = to_i915(dev); |
7580d774 | 13928 | struct drm_plane_state *plane_state; |
5008e874 | 13929 | struct drm_crtc_state *crtc_state; |
7580d774 | 13930 | struct drm_plane *plane; |
5008e874 ML |
13931 | struct drm_crtc *crtc; |
13932 | int i, ret; | |
13933 | ||
5a21b665 DV |
13934 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13935 | if (state->legacy_cursor_update) | |
a6747b73 ML |
13936 | continue; |
13937 | ||
5a21b665 DV |
13938 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13939 | if (ret) | |
13940 | return ret; | |
5008e874 | 13941 | |
5a21b665 DV |
13942 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
13943 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
13944 | } |
13945 | ||
f935675f ML |
13946 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13947 | if (ret) | |
13948 | return ret; | |
13949 | ||
5008e874 | 13950 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13951 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13952 | |
21daaeee | 13953 | if (!ret && !nonblock) { |
7580d774 ML |
13954 | for_each_plane_in_state(state, plane, plane_state, i) { |
13955 | struct intel_plane_state *intel_plane_state = | |
13956 | to_intel_plane_state(plane_state); | |
13957 | ||
13958 | if (!intel_plane_state->wait_req) | |
13959 | continue; | |
13960 | ||
776f3236 CW |
13961 | ret = i915_wait_request(intel_plane_state->wait_req, |
13962 | true, NULL, NULL); | |
f7e5838b | 13963 | if (ret) { |
f4457ae7 CW |
13964 | /* Any hang should be swallowed by the wait */ |
13965 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13966 | mutex_lock(&dev->struct_mutex); |
13967 | drm_atomic_helper_cleanup_planes(dev, state); | |
13968 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13969 | break; |
f7e5838b | 13970 | } |
7580d774 | 13971 | } |
7580d774 | 13972 | } |
5008e874 ML |
13973 | |
13974 | return ret; | |
13975 | } | |
13976 | ||
a2991414 ML |
13977 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
13978 | { | |
13979 | struct drm_device *dev = crtc->base.dev; | |
13980 | ||
13981 | if (!dev->max_vblank_count) | |
13982 | return drm_accurate_vblank_count(&crtc->base); | |
13983 | ||
13984 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
13985 | } | |
13986 | ||
5a21b665 DV |
13987 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13988 | struct drm_i915_private *dev_priv, | |
13989 | unsigned crtc_mask) | |
e8861675 | 13990 | { |
5a21b665 DV |
13991 | unsigned last_vblank_count[I915_MAX_PIPES]; |
13992 | enum pipe pipe; | |
13993 | int ret; | |
e8861675 | 13994 | |
5a21b665 DV |
13995 | if (!crtc_mask) |
13996 | return; | |
e8861675 | 13997 | |
5a21b665 DV |
13998 | for_each_pipe(dev_priv, pipe) { |
13999 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 14000 | |
5a21b665 | 14001 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
14002 | continue; |
14003 | ||
5a21b665 DV |
14004 | ret = drm_crtc_vblank_get(crtc); |
14005 | if (WARN_ON(ret != 0)) { | |
14006 | crtc_mask &= ~(1 << pipe); | |
14007 | continue; | |
e8861675 ML |
14008 | } |
14009 | ||
5a21b665 | 14010 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
14011 | } |
14012 | ||
5a21b665 DV |
14013 | for_each_pipe(dev_priv, pipe) { |
14014 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
14015 | long lret; | |
e8861675 | 14016 | |
5a21b665 DV |
14017 | if (!((1 << pipe) & crtc_mask)) |
14018 | continue; | |
d55dbd06 | 14019 | |
5a21b665 DV |
14020 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
14021 | last_vblank_count[pipe] != | |
14022 | drm_crtc_vblank_count(crtc), | |
14023 | msecs_to_jiffies(50)); | |
d55dbd06 | 14024 | |
5a21b665 | 14025 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 14026 | |
5a21b665 | 14027 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
14028 | } |
14029 | } | |
14030 | ||
5a21b665 | 14031 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 14032 | { |
5a21b665 DV |
14033 | /* fb updated, need to unpin old fb */ |
14034 | if (crtc_state->fb_changed) | |
14035 | return true; | |
a6747b73 | 14036 | |
5a21b665 DV |
14037 | /* wm changes, need vblank before final wm's */ |
14038 | if (crtc_state->update_wm_post) | |
14039 | return true; | |
a6747b73 | 14040 | |
5a21b665 DV |
14041 | /* |
14042 | * cxsr is re-enabled after vblank. | |
14043 | * This is already handled by crtc_state->update_wm_post, | |
14044 | * but added for clarity. | |
14045 | */ | |
14046 | if (crtc_state->disable_cxsr) | |
14047 | return true; | |
a6747b73 | 14048 | |
5a21b665 | 14049 | return false; |
e8861675 ML |
14050 | } |
14051 | ||
94f05024 | 14052 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 14053 | { |
94f05024 | 14054 | struct drm_device *dev = state->dev; |
565602d7 | 14055 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14056 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 14057 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 14058 | struct drm_crtc *crtc; |
5a21b665 | 14059 | struct intel_crtc_state *intel_cstate; |
94f05024 DV |
14060 | struct drm_plane *plane; |
14061 | struct drm_plane_state *plane_state; | |
5a21b665 DV |
14062 | bool hw_check = intel_state->modeset; |
14063 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
14064 | unsigned crtc_vblank_mask = 0; | |
94f05024 | 14065 | int i, ret; |
a6778b3c | 14066 | |
94f05024 DV |
14067 | for_each_plane_in_state(state, plane, plane_state, i) { |
14068 | struct intel_plane_state *intel_plane_state = | |
14069 | to_intel_plane_state(plane_state); | |
ea0000f0 | 14070 | |
94f05024 DV |
14071 | if (!intel_plane_state->wait_req) |
14072 | continue; | |
d4afb8cc | 14073 | |
776f3236 CW |
14074 | ret = i915_wait_request(intel_plane_state->wait_req, |
14075 | true, NULL, NULL); | |
94f05024 DV |
14076 | /* EIO should be eaten, and we can't get interrupted in the |
14077 | * worker, and blocking commits have waited already. */ | |
14078 | WARN_ON(ret); | |
14079 | } | |
1c5e19f8 | 14080 | |
ea0000f0 DV |
14081 | drm_atomic_helper_wait_for_dependencies(state); |
14082 | ||
565602d7 ML |
14083 | if (intel_state->modeset) { |
14084 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
14085 | sizeof(intel_state->min_pixclk)); | |
14086 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 14087 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
14088 | |
14089 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
14090 | } |
14091 | ||
29ceb0e6 | 14092 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
14093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14094 | ||
5a21b665 DV |
14095 | if (needs_modeset(crtc->state) || |
14096 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
14097 | hw_check = true; | |
14098 | ||
14099 | put_domains[to_intel_crtc(crtc)->pipe] = | |
14100 | modeset_get_crtc_power_domains(crtc, | |
14101 | to_intel_crtc_state(crtc->state)); | |
14102 | } | |
14103 | ||
61333b60 ML |
14104 | if (!needs_modeset(crtc->state)) |
14105 | continue; | |
14106 | ||
29ceb0e6 | 14107 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 14108 | |
29ceb0e6 VS |
14109 | if (old_crtc_state->active) { |
14110 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 14111 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 14112 | intel_crtc->active = false; |
58f9c0bc | 14113 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 14114 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
14115 | |
14116 | /* | |
14117 | * Underruns don't always raise | |
14118 | * interrupts, so check manually. | |
14119 | */ | |
14120 | intel_check_cpu_fifo_underruns(dev_priv); | |
14121 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
14122 | |
14123 | if (!crtc->state->active) | |
14124 | intel_update_watermarks(crtc); | |
a539205a | 14125 | } |
b8cecdf5 | 14126 | } |
7758a113 | 14127 | |
ea9d758d DV |
14128 | /* Only after disabling all output pipelines that will be changed can we |
14129 | * update the the output configuration. */ | |
4740b0f2 | 14130 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 14131 | |
565602d7 | 14132 | if (intel_state->modeset) { |
4740b0f2 | 14133 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
14134 | |
14135 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 14136 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14137 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 14138 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 14139 | |
c0ead703 | 14140 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 14141 | } |
47fab737 | 14142 | |
a6778b3c | 14143 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 14144 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
14145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14146 | bool modeset = needs_modeset(crtc->state); | |
5a21b665 DV |
14147 | struct intel_crtc_state *pipe_config = |
14148 | to_intel_crtc_state(crtc->state); | |
9f836f90 | 14149 | |
f6ac4b2a | 14150 | if (modeset && crtc->state->active) { |
a539205a ML |
14151 | update_scanline_offset(to_intel_crtc(crtc)); |
14152 | dev_priv->display.crtc_enable(crtc); | |
14153 | } | |
80715b2f | 14154 | |
1f7528c4 DV |
14155 | /* Complete events for now disable pipes here. */ |
14156 | if (modeset && !crtc->state->active && crtc->state->event) { | |
14157 | spin_lock_irq(&dev->event_lock); | |
14158 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
14159 | spin_unlock_irq(&dev->event_lock); | |
14160 | ||
14161 | crtc->state->event = NULL; | |
14162 | } | |
14163 | ||
f6ac4b2a | 14164 | if (!modeset) |
29ceb0e6 | 14165 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 14166 | |
5a21b665 DV |
14167 | if (crtc->state->active && |
14168 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
faf68d92 | 14169 | intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); |
5a21b665 | 14170 | |
1f7528c4 | 14171 | if (crtc->state->active) |
5a21b665 | 14172 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
f6d1973d | 14173 | |
5a21b665 DV |
14174 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
14175 | crtc_vblank_mask |= 1 << i; | |
177246a8 MR |
14176 | } |
14177 | ||
94f05024 DV |
14178 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
14179 | * already, but still need the state for the delayed optimization. To | |
14180 | * fix this: | |
14181 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
14182 | * - schedule that vblank worker _before_ calling hw_done | |
14183 | * - at the start of commit_tail, cancel it _synchrously | |
14184 | * - switch over to the vblank wait helper in the core after that since | |
14185 | * we don't need out special handling any more. | |
14186 | */ | |
5a21b665 DV |
14187 | if (!state->legacy_cursor_update) |
14188 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
14189 | ||
14190 | /* | |
14191 | * Now that the vblank has passed, we can go ahead and program the | |
14192 | * optimal watermarks on platforms that need two-step watermark | |
14193 | * programming. | |
14194 | * | |
14195 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
14196 | */ | |
14197 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14198 | intel_cstate = to_intel_crtc_state(crtc->state); | |
14199 | ||
14200 | if (dev_priv->display.optimize_watermarks) | |
14201 | dev_priv->display.optimize_watermarks(intel_cstate); | |
14202 | } | |
14203 | ||
14204 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14205 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14206 | ||
14207 | if (put_domains[i]) | |
14208 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
14209 | ||
14210 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
14211 | } | |
14212 | ||
94f05024 DV |
14213 | drm_atomic_helper_commit_hw_done(state); |
14214 | ||
5a21b665 DV |
14215 | if (intel_state->modeset) |
14216 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14217 | ||
14218 | mutex_lock(&dev->struct_mutex); | |
14219 | drm_atomic_helper_cleanup_planes(dev, state); | |
14220 | mutex_unlock(&dev->struct_mutex); | |
14221 | ||
ea0000f0 DV |
14222 | drm_atomic_helper_commit_cleanup_done(state); |
14223 | ||
ee165b1a | 14224 | drm_atomic_state_free(state); |
f30da187 | 14225 | |
75714940 MK |
14226 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14227 | * of triggering bugs in unclaimed access. After we finish | |
14228 | * modesetting, see if an error has been flagged, and if so | |
14229 | * enable debugging for the next modeset - and hope we catch | |
14230 | * the culprit. | |
14231 | * | |
14232 | * XXX note that we assume display power is on at this point. | |
14233 | * This might hold true now but we need to add pm helper to check | |
14234 | * unclaimed only when the hardware is on, as atomic commits | |
14235 | * can happen also when the device is completely off. | |
14236 | */ | |
14237 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14238 | } |
14239 | ||
14240 | static void intel_atomic_commit_work(struct work_struct *work) | |
14241 | { | |
14242 | struct drm_atomic_state *state = container_of(work, | |
14243 | struct drm_atomic_state, | |
14244 | commit_work); | |
14245 | intel_atomic_commit_tail(state); | |
14246 | } | |
14247 | ||
6c9c1b38 DV |
14248 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14249 | { | |
14250 | struct drm_plane_state *old_plane_state; | |
14251 | struct drm_plane *plane; | |
6c9c1b38 DV |
14252 | int i; |
14253 | ||
faf5bf0a CW |
14254 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14255 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14256 | intel_fb_obj(plane->state->fb), | |
14257 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14258 | } |
14259 | ||
94f05024 DV |
14260 | /** |
14261 | * intel_atomic_commit - commit validated state object | |
14262 | * @dev: DRM device | |
14263 | * @state: the top-level driver state object | |
14264 | * @nonblock: nonblocking commit | |
14265 | * | |
14266 | * This function commits a top-level state object that has been validated | |
14267 | * with drm_atomic_helper_check(). | |
14268 | * | |
14269 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
14270 | * nonblocking commits are only safe for pure plane updates. Everything else | |
14271 | * should work though. | |
14272 | * | |
14273 | * RETURNS | |
14274 | * Zero for success or -errno. | |
14275 | */ | |
14276 | static int intel_atomic_commit(struct drm_device *dev, | |
14277 | struct drm_atomic_state *state, | |
14278 | bool nonblock) | |
14279 | { | |
14280 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14281 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14282 | int ret = 0; |
14283 | ||
14284 | if (intel_state->modeset && nonblock) { | |
14285 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
14286 | return -EINVAL; | |
14287 | } | |
14288 | ||
14289 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
14290 | if (ret) | |
14291 | return ret; | |
14292 | ||
14293 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); | |
14294 | ||
14295 | ret = intel_atomic_prepare_commit(dev, state, nonblock); | |
14296 | if (ret) { | |
14297 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
14298 | return ret; | |
14299 | } | |
14300 | ||
14301 | drm_atomic_helper_swap_state(state, true); | |
14302 | dev_priv->wm.distrust_bios_wm = false; | |
14303 | dev_priv->wm.skl_results = intel_state->wm_results; | |
14304 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 14305 | intel_atomic_track_fbs(state); |
94f05024 DV |
14306 | |
14307 | if (nonblock) | |
14308 | queue_work(system_unbound_wq, &state->commit_work); | |
14309 | else | |
14310 | intel_atomic_commit_tail(state); | |
75714940 | 14311 | |
74c090b1 | 14312 | return 0; |
7f27126e JB |
14313 | } |
14314 | ||
c0c36b94 CW |
14315 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14316 | { | |
83a57153 ACO |
14317 | struct drm_device *dev = crtc->dev; |
14318 | struct drm_atomic_state *state; | |
e694eb02 | 14319 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14320 | int ret; |
83a57153 ACO |
14321 | |
14322 | state = drm_atomic_state_alloc(dev); | |
14323 | if (!state) { | |
78108b7c VS |
14324 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14325 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14326 | return; |
14327 | } | |
14328 | ||
e694eb02 | 14329 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14330 | |
e694eb02 ML |
14331 | retry: |
14332 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14333 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14334 | if (!ret) { | |
14335 | if (!crtc_state->active) | |
14336 | goto out; | |
83a57153 | 14337 | |
e694eb02 | 14338 | crtc_state->mode_changed = true; |
74c090b1 | 14339 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14340 | } |
14341 | ||
e694eb02 ML |
14342 | if (ret == -EDEADLK) { |
14343 | drm_atomic_state_clear(state); | |
14344 | drm_modeset_backoff(state->acquire_ctx); | |
14345 | goto retry; | |
4ed9fb37 | 14346 | } |
4be07317 | 14347 | |
2bfb4627 | 14348 | if (ret) |
e694eb02 | 14349 | out: |
2bfb4627 | 14350 | drm_atomic_state_free(state); |
c0c36b94 CW |
14351 | } |
14352 | ||
25c5b266 DV |
14353 | #undef for_each_intel_crtc_masked |
14354 | ||
a8784875 BP |
14355 | /* |
14356 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14357 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14358 | */ | |
14359 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14360 | u16 *red, u16 *green, u16 *blue, | |
14361 | uint32_t size) | |
14362 | { | |
14363 | struct drm_device *dev = crtc->dev; | |
14364 | struct drm_mode_config *config = &dev->mode_config; | |
14365 | struct drm_crtc_state *state; | |
14366 | int ret; | |
14367 | ||
14368 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14369 | if (ret) | |
14370 | return ret; | |
14371 | ||
14372 | /* | |
14373 | * Make sure we update the legacy properties so this works when | |
14374 | * atomic is not enabled. | |
14375 | */ | |
14376 | ||
14377 | state = crtc->state; | |
14378 | ||
14379 | drm_object_property_set_value(&crtc->base, | |
14380 | config->degamma_lut_property, | |
14381 | (state->degamma_lut) ? | |
14382 | state->degamma_lut->base.id : 0); | |
14383 | ||
14384 | drm_object_property_set_value(&crtc->base, | |
14385 | config->ctm_property, | |
14386 | (state->ctm) ? | |
14387 | state->ctm->base.id : 0); | |
14388 | ||
14389 | drm_object_property_set_value(&crtc->base, | |
14390 | config->gamma_lut_property, | |
14391 | (state->gamma_lut) ? | |
14392 | state->gamma_lut->base.id : 0); | |
14393 | ||
14394 | return 0; | |
14395 | } | |
14396 | ||
f6e5b160 | 14397 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14398 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14399 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14400 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14401 | .destroy = intel_crtc_destroy, |
527b6abe | 14402 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14403 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14404 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14405 | }; |
14406 | ||
6beb8c23 MR |
14407 | /** |
14408 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14409 | * @plane: drm plane to prepare for | |
14410 | * @fb: framebuffer to prepare for presentation | |
14411 | * | |
14412 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14413 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14414 | * bits. Some older platforms need special physical address handling for | |
14415 | * cursor planes. | |
14416 | * | |
f935675f ML |
14417 | * Must be called with struct_mutex held. |
14418 | * | |
6beb8c23 MR |
14419 | * Returns 0 on success, negative error code on failure. |
14420 | */ | |
14421 | int | |
14422 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 14423 | const struct drm_plane_state *new_state) |
465c120c MR |
14424 | { |
14425 | struct drm_device *dev = plane->dev; | |
844f9111 | 14426 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14427 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14428 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c37efb99 | 14429 | struct reservation_object *resv; |
6beb8c23 | 14430 | int ret = 0; |
465c120c | 14431 | |
1ee49399 | 14432 | if (!obj && !old_obj) |
465c120c MR |
14433 | return 0; |
14434 | ||
5008e874 ML |
14435 | if (old_obj) { |
14436 | struct drm_crtc_state *crtc_state = | |
14437 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14438 | ||
14439 | /* Big Hammer, we also need to ensure that any pending | |
14440 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14441 | * current scanout is retired before unpinning the old | |
14442 | * framebuffer. Note that we rely on userspace rendering | |
14443 | * into the buffer attached to the pipe they are waiting | |
14444 | * on. If not, userspace generates a GPU hang with IPEHR | |
14445 | * point to the MI_WAIT_FOR_EVENT. | |
14446 | * | |
14447 | * This should only fail upon a hung GPU, in which case we | |
14448 | * can safely continue. | |
14449 | */ | |
14450 | if (needs_modeset(crtc_state)) | |
14451 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
14452 | if (ret) { |
14453 | /* GPU hangs should have been swallowed by the wait */ | |
14454 | WARN_ON(ret == -EIO); | |
f935675f | 14455 | return ret; |
f4457ae7 | 14456 | } |
5008e874 ML |
14457 | } |
14458 | ||
c37efb99 CW |
14459 | if (!obj) |
14460 | return 0; | |
14461 | ||
5a21b665 | 14462 | /* For framebuffer backed by dmabuf, wait for fence */ |
c37efb99 CW |
14463 | resv = i915_gem_object_get_dmabuf_resv(obj); |
14464 | if (resv) { | |
5a21b665 DV |
14465 | long lret; |
14466 | ||
c37efb99 | 14467 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
5a21b665 DV |
14468 | MAX_SCHEDULE_TIMEOUT); |
14469 | if (lret == -ERESTARTSYS) | |
14470 | return lret; | |
14471 | ||
14472 | WARN(lret < 0, "waiting returns %li\n", lret); | |
14473 | } | |
14474 | ||
c37efb99 | 14475 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 MR |
14476 | INTEL_INFO(dev)->cursor_needs_physical) { |
14477 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14478 | ret = i915_gem_object_attach_phys(obj, align); | |
14479 | if (ret) | |
14480 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14481 | } else { | |
058d88c4 CW |
14482 | struct i915_vma *vma; |
14483 | ||
14484 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
14485 | if (IS_ERR(vma)) | |
14486 | ret = PTR_ERR(vma); | |
6beb8c23 | 14487 | } |
465c120c | 14488 | |
c37efb99 | 14489 | if (ret == 0) { |
27c01aae | 14490 | to_intel_plane_state(new_state)->wait_req = |
d72d908b CW |
14491 | i915_gem_active_get(&obj->last_write, |
14492 | &obj->base.dev->struct_mutex); | |
7580d774 | 14493 | } |
fdd508a6 | 14494 | |
6beb8c23 MR |
14495 | return ret; |
14496 | } | |
14497 | ||
38f3ce3a MR |
14498 | /** |
14499 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14500 | * @plane: drm plane to clean up for | |
14501 | * @fb: old framebuffer that was on plane | |
14502 | * | |
14503 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14504 | * |
14505 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14506 | */ |
14507 | void | |
14508 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14509 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14510 | { |
14511 | struct drm_device *dev = plane->dev; | |
7580d774 | 14512 | struct intel_plane_state *old_intel_state; |
84978257 | 14513 | struct intel_plane_state *intel_state = to_intel_plane_state(plane->state); |
1ee49399 ML |
14514 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14515 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14516 | |
7580d774 ML |
14517 | old_intel_state = to_intel_plane_state(old_state); |
14518 | ||
1ee49399 | 14519 | if (!obj && !old_obj) |
38f3ce3a MR |
14520 | return; |
14521 | ||
1ee49399 ML |
14522 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14523 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14524 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 | 14525 | |
84978257 | 14526 | i915_gem_request_assign(&intel_state->wait_req, NULL); |
7580d774 | 14527 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
465c120c MR |
14528 | } |
14529 | ||
6156a456 CK |
14530 | int |
14531 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14532 | { | |
14533 | int max_scale; | |
6156a456 CK |
14534 | int crtc_clock, cdclk; |
14535 | ||
bf8a0af0 | 14536 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14537 | return DRM_PLANE_HELPER_NO_SCALING; |
14538 | ||
6156a456 | 14539 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14540 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14541 | |
54bf1ce6 | 14542 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14543 | return DRM_PLANE_HELPER_NO_SCALING; |
14544 | ||
14545 | /* | |
14546 | * skl max scale is lower of: | |
14547 | * close to 3 but not 3, -1 is for that purpose | |
14548 | * or | |
14549 | * cdclk/crtc_clock | |
14550 | */ | |
14551 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14552 | ||
14553 | return max_scale; | |
14554 | } | |
14555 | ||
465c120c | 14556 | static int |
3c692a41 | 14557 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14558 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14559 | struct intel_plane_state *state) |
14560 | { | |
b63a16f6 | 14561 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 14562 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 14563 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14564 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14565 | bool can_position = false; | |
b63a16f6 | 14566 | int ret; |
465c120c | 14567 | |
b63a16f6 | 14568 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
14569 | /* use scaler when colorkey is not required */ |
14570 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14571 | min_scale = 1; | |
14572 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14573 | } | |
d8106366 | 14574 | can_position = true; |
6156a456 | 14575 | } |
d8106366 | 14576 | |
cc926387 DV |
14577 | ret = drm_plane_helper_check_state(&state->base, |
14578 | &state->clip, | |
14579 | min_scale, max_scale, | |
14580 | can_position, true); | |
b63a16f6 VS |
14581 | if (ret) |
14582 | return ret; | |
14583 | ||
cc926387 | 14584 | if (!state->base.fb) |
b63a16f6 VS |
14585 | return 0; |
14586 | ||
14587 | if (INTEL_GEN(dev_priv) >= 9) { | |
14588 | ret = skl_check_plane_surface(state); | |
14589 | if (ret) | |
14590 | return ret; | |
14591 | } | |
14592 | ||
14593 | return 0; | |
14af293f GP |
14594 | } |
14595 | ||
5a21b665 DV |
14596 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14597 | struct drm_crtc_state *old_crtc_state) | |
14598 | { | |
14599 | struct drm_device *dev = crtc->dev; | |
14600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14601 | struct intel_crtc_state *old_intel_state = | |
14602 | to_intel_crtc_state(old_crtc_state); | |
14603 | bool modeset = needs_modeset(crtc->state); | |
14604 | ||
14605 | /* Perform vblank evasion around commit operation */ | |
14606 | intel_pipe_update_start(intel_crtc); | |
14607 | ||
14608 | if (modeset) | |
14609 | return; | |
14610 | ||
14611 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14612 | intel_color_set_csc(crtc->state); | |
14613 | intel_color_load_luts(crtc->state); | |
14614 | } | |
14615 | ||
14616 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14617 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14618 | else if (INTEL_INFO(dev)->gen >= 9) | |
14619 | skl_detach_scalers(intel_crtc); | |
14620 | } | |
14621 | ||
14622 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14623 | struct drm_crtc_state *old_crtc_state) | |
14624 | { | |
14625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14626 | ||
14627 | intel_pipe_update_end(intel_crtc, NULL); | |
14628 | } | |
14629 | ||
cf4c7c12 | 14630 | /** |
4a3b8769 MR |
14631 | * intel_plane_destroy - destroy a plane |
14632 | * @plane: plane to destroy | |
cf4c7c12 | 14633 | * |
4a3b8769 MR |
14634 | * Common destruction function for all types of planes (primary, cursor, |
14635 | * sprite). | |
cf4c7c12 | 14636 | */ |
4a3b8769 | 14637 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14638 | { |
69ae561f VS |
14639 | if (!plane) |
14640 | return; | |
14641 | ||
465c120c | 14642 | drm_plane_cleanup(plane); |
69ae561f | 14643 | kfree(to_intel_plane(plane)); |
465c120c MR |
14644 | } |
14645 | ||
65a3fea0 | 14646 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14647 | .update_plane = drm_atomic_helper_update_plane, |
14648 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14649 | .destroy = intel_plane_destroy, |
c196e1d6 | 14650 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14651 | .atomic_get_property = intel_plane_atomic_get_property, |
14652 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14653 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14654 | .atomic_destroy_state = intel_plane_destroy_state, | |
14655 | ||
465c120c MR |
14656 | }; |
14657 | ||
14658 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14659 | int pipe) | |
14660 | { | |
fca0ce2a VS |
14661 | struct intel_plane *primary = NULL; |
14662 | struct intel_plane_state *state = NULL; | |
465c120c | 14663 | const uint32_t *intel_primary_formats; |
45e3743a | 14664 | unsigned int num_formats; |
fca0ce2a | 14665 | int ret; |
465c120c MR |
14666 | |
14667 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14668 | if (!primary) |
14669 | goto fail; | |
465c120c | 14670 | |
8e7d688b | 14671 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14672 | if (!state) |
14673 | goto fail; | |
8e7d688b | 14674 | primary->base.state = &state->base; |
ea2c67bb | 14675 | |
465c120c MR |
14676 | primary->can_scale = false; |
14677 | primary->max_downscale = 1; | |
6156a456 CK |
14678 | if (INTEL_INFO(dev)->gen >= 9) { |
14679 | primary->can_scale = true; | |
af99ceda | 14680 | state->scaler_id = -1; |
6156a456 | 14681 | } |
465c120c MR |
14682 | primary->pipe = pipe; |
14683 | primary->plane = pipe; | |
a9ff8714 | 14684 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14685 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14686 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14687 | primary->plane = !pipe; | |
14688 | ||
6c0fd451 DL |
14689 | if (INTEL_INFO(dev)->gen >= 9) { |
14690 | intel_primary_formats = skl_primary_formats; | |
14691 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14692 | |
14693 | primary->update_plane = skylake_update_primary_plane; | |
14694 | primary->disable_plane = skylake_disable_primary_plane; | |
14695 | } else if (HAS_PCH_SPLIT(dev)) { | |
14696 | intel_primary_formats = i965_primary_formats; | |
14697 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14698 | ||
14699 | primary->update_plane = ironlake_update_primary_plane; | |
14700 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14701 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14702 | intel_primary_formats = i965_primary_formats; |
14703 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14704 | |
14705 | primary->update_plane = i9xx_update_primary_plane; | |
14706 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14707 | } else { |
14708 | intel_primary_formats = i8xx_primary_formats; | |
14709 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14710 | |
14711 | primary->update_plane = i9xx_update_primary_plane; | |
14712 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14713 | } |
14714 | ||
38573dc1 VS |
14715 | if (INTEL_INFO(dev)->gen >= 9) |
14716 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14717 | &intel_plane_funcs, | |
14718 | intel_primary_formats, num_formats, | |
14719 | DRM_PLANE_TYPE_PRIMARY, | |
14720 | "plane 1%c", pipe_name(pipe)); | |
14721 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
14722 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14723 | &intel_plane_funcs, | |
14724 | intel_primary_formats, num_formats, | |
14725 | DRM_PLANE_TYPE_PRIMARY, | |
14726 | "primary %c", pipe_name(pipe)); | |
14727 | else | |
14728 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14729 | &intel_plane_funcs, | |
14730 | intel_primary_formats, num_formats, | |
14731 | DRM_PLANE_TYPE_PRIMARY, | |
14732 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
14733 | if (ret) |
14734 | goto fail; | |
48404c1e | 14735 | |
3b7a5119 SJ |
14736 | if (INTEL_INFO(dev)->gen >= 4) |
14737 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14738 | |
ea2c67bb MR |
14739 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14740 | ||
465c120c | 14741 | return &primary->base; |
fca0ce2a VS |
14742 | |
14743 | fail: | |
14744 | kfree(state); | |
14745 | kfree(primary); | |
14746 | ||
14747 | return NULL; | |
465c120c MR |
14748 | } |
14749 | ||
3b7a5119 SJ |
14750 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14751 | { | |
14752 | if (!dev->mode_config.rotation_property) { | |
31ad61e4 JL |
14753 | unsigned long flags = DRM_ROTATE_0 | |
14754 | DRM_ROTATE_180; | |
3b7a5119 SJ |
14755 | |
14756 | if (INTEL_INFO(dev)->gen >= 9) | |
31ad61e4 | 14757 | flags |= DRM_ROTATE_90 | DRM_ROTATE_270; |
3b7a5119 SJ |
14758 | |
14759 | dev->mode_config.rotation_property = | |
14760 | drm_mode_create_rotation_property(dev, flags); | |
14761 | } | |
14762 | if (dev->mode_config.rotation_property) | |
14763 | drm_object_attach_property(&plane->base.base, | |
14764 | dev->mode_config.rotation_property, | |
14765 | plane->base.state->rotation); | |
14766 | } | |
14767 | ||
3d7d6510 | 14768 | static int |
852e787c | 14769 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14770 | struct intel_crtc_state *crtc_state, |
852e787c | 14771 | struct intel_plane_state *state) |
3d7d6510 | 14772 | { |
2b875c22 | 14773 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14774 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14775 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14776 | unsigned stride; |
14777 | int ret; | |
3d7d6510 | 14778 | |
f8856a44 VS |
14779 | ret = drm_plane_helper_check_state(&state->base, |
14780 | &state->clip, | |
14781 | DRM_PLANE_HELPER_NO_SCALING, | |
14782 | DRM_PLANE_HELPER_NO_SCALING, | |
14783 | true, true); | |
757f9a3e GP |
14784 | if (ret) |
14785 | return ret; | |
14786 | ||
757f9a3e GP |
14787 | /* if we want to turn off the cursor ignore width and height */ |
14788 | if (!obj) | |
da20eabd | 14789 | return 0; |
757f9a3e | 14790 | |
757f9a3e | 14791 | /* Check for which cursor types we support */ |
061e4b8d | 14792 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14793 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14794 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14795 | return -EINVAL; |
14796 | } | |
14797 | ||
ea2c67bb MR |
14798 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14799 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14800 | DRM_DEBUG_KMS("buffer is too small\n"); |
14801 | return -ENOMEM; | |
14802 | } | |
14803 | ||
3a656b54 | 14804 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14805 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14806 | return -EINVAL; |
32b7eeec MR |
14807 | } |
14808 | ||
b29ec92c VS |
14809 | /* |
14810 | * There's something wrong with the cursor on CHV pipe C. | |
14811 | * If it straddles the left edge of the screen then | |
14812 | * moving it away from the edge or disabling it often | |
14813 | * results in a pipe underrun, and often that can lead to | |
14814 | * dead pipe (constant underrun reported, and it scans | |
14815 | * out just a solid color). To recover from that, the | |
14816 | * display power well must be turned off and on again. | |
14817 | * Refuse the put the cursor into that compromised position. | |
14818 | */ | |
14819 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
936e71e3 | 14820 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
14821 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
14822 | return -EINVAL; | |
14823 | } | |
14824 | ||
da20eabd | 14825 | return 0; |
852e787c | 14826 | } |
3d7d6510 | 14827 | |
a8ad0d8e ML |
14828 | static void |
14829 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14830 | struct drm_crtc *crtc) |
a8ad0d8e | 14831 | { |
f2858021 ML |
14832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14833 | ||
14834 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14835 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14836 | } |
14837 | ||
f4a2cf29 | 14838 | static void |
55a08b3f ML |
14839 | intel_update_cursor_plane(struct drm_plane *plane, |
14840 | const struct intel_crtc_state *crtc_state, | |
14841 | const struct intel_plane_state *state) | |
852e787c | 14842 | { |
55a08b3f ML |
14843 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14844 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14845 | struct drm_device *dev = plane->dev; |
2b875c22 | 14846 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14847 | uint32_t addr; |
852e787c | 14848 | |
f4a2cf29 | 14849 | if (!obj) |
a912f12f | 14850 | addr = 0; |
f4a2cf29 | 14851 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
058d88c4 | 14852 | addr = i915_gem_object_ggtt_offset(obj, NULL); |
f4a2cf29 | 14853 | else |
a912f12f | 14854 | addr = obj->phys_handle->busaddr; |
852e787c | 14855 | |
a912f12f | 14856 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14857 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14858 | } |
14859 | ||
3d7d6510 MR |
14860 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14861 | int pipe) | |
14862 | { | |
fca0ce2a VS |
14863 | struct intel_plane *cursor = NULL; |
14864 | struct intel_plane_state *state = NULL; | |
14865 | int ret; | |
3d7d6510 MR |
14866 | |
14867 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14868 | if (!cursor) |
14869 | goto fail; | |
3d7d6510 | 14870 | |
8e7d688b | 14871 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14872 | if (!state) |
14873 | goto fail; | |
8e7d688b | 14874 | cursor->base.state = &state->base; |
ea2c67bb | 14875 | |
3d7d6510 MR |
14876 | cursor->can_scale = false; |
14877 | cursor->max_downscale = 1; | |
14878 | cursor->pipe = pipe; | |
14879 | cursor->plane = pipe; | |
a9ff8714 | 14880 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14881 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14882 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14883 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14884 | |
fca0ce2a VS |
14885 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14886 | &intel_plane_funcs, | |
14887 | intel_cursor_formats, | |
14888 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
14889 | DRM_PLANE_TYPE_CURSOR, |
14890 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
14891 | if (ret) |
14892 | goto fail; | |
4398ad45 VS |
14893 | |
14894 | if (INTEL_INFO(dev)->gen >= 4) { | |
14895 | if (!dev->mode_config.rotation_property) | |
14896 | dev->mode_config.rotation_property = | |
14897 | drm_mode_create_rotation_property(dev, | |
31ad61e4 JL |
14898 | DRM_ROTATE_0 | |
14899 | DRM_ROTATE_180); | |
4398ad45 VS |
14900 | if (dev->mode_config.rotation_property) |
14901 | drm_object_attach_property(&cursor->base.base, | |
14902 | dev->mode_config.rotation_property, | |
8e7d688b | 14903 | state->base.rotation); |
4398ad45 VS |
14904 | } |
14905 | ||
af99ceda CK |
14906 | if (INTEL_INFO(dev)->gen >=9) |
14907 | state->scaler_id = -1; | |
14908 | ||
ea2c67bb MR |
14909 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14910 | ||
3d7d6510 | 14911 | return &cursor->base; |
fca0ce2a VS |
14912 | |
14913 | fail: | |
14914 | kfree(state); | |
14915 | kfree(cursor); | |
14916 | ||
14917 | return NULL; | |
3d7d6510 MR |
14918 | } |
14919 | ||
549e2bfb CK |
14920 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14921 | struct intel_crtc_state *crtc_state) | |
14922 | { | |
14923 | int i; | |
14924 | struct intel_scaler *intel_scaler; | |
14925 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14926 | ||
14927 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14928 | intel_scaler = &scaler_state->scalers[i]; | |
14929 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14930 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14931 | } | |
14932 | ||
14933 | scaler_state->scaler_id = -1; | |
14934 | } | |
14935 | ||
b358d0a6 | 14936 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14937 | { |
fac5e23e | 14938 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 14939 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14940 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14941 | struct drm_plane *primary = NULL; |
14942 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14943 | int ret; |
79e53945 | 14944 | |
955382f3 | 14945 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14946 | if (intel_crtc == NULL) |
14947 | return; | |
14948 | ||
f5de6e07 ACO |
14949 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14950 | if (!crtc_state) | |
14951 | goto fail; | |
550acefd ACO |
14952 | intel_crtc->config = crtc_state; |
14953 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14954 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14955 | |
549e2bfb CK |
14956 | /* initialize shared scalers */ |
14957 | if (INTEL_INFO(dev)->gen >= 9) { | |
14958 | if (pipe == PIPE_C) | |
14959 | intel_crtc->num_scalers = 1; | |
14960 | else | |
14961 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14962 | ||
14963 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14964 | } | |
14965 | ||
465c120c | 14966 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14967 | if (!primary) |
14968 | goto fail; | |
14969 | ||
14970 | cursor = intel_cursor_plane_create(dev, pipe); | |
14971 | if (!cursor) | |
14972 | goto fail; | |
14973 | ||
465c120c | 14974 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
4d5d72b7 VS |
14975 | cursor, &intel_crtc_funcs, |
14976 | "pipe %c", pipe_name(pipe)); | |
3d7d6510 MR |
14977 | if (ret) |
14978 | goto fail; | |
79e53945 | 14979 | |
1f1c2e24 VS |
14980 | /* |
14981 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14982 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14983 | */ |
80824003 JB |
14984 | intel_crtc->pipe = pipe; |
14985 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14986 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14987 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14988 | intel_crtc->plane = !pipe; |
80824003 JB |
14989 | } |
14990 | ||
4b0e333e CW |
14991 | intel_crtc->cursor_base = ~0; |
14992 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14993 | intel_crtc->cursor_size = ~0; |
8d7849db | 14994 | |
852eb00d VS |
14995 | intel_crtc->wm.cxsr_allowed = true; |
14996 | ||
22fd0fab JB |
14997 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14998 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14999 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
15000 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
15001 | ||
79e53945 | 15002 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 15003 | |
8563b1e8 LL |
15004 | intel_color_init(&intel_crtc->base); |
15005 | ||
87b6b101 | 15006 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
15007 | return; |
15008 | ||
15009 | fail: | |
69ae561f VS |
15010 | intel_plane_destroy(primary); |
15011 | intel_plane_destroy(cursor); | |
f5de6e07 | 15012 | kfree(crtc_state); |
3d7d6510 | 15013 | kfree(intel_crtc); |
79e53945 JB |
15014 | } |
15015 | ||
752aa88a JB |
15016 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
15017 | { | |
15018 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 15019 | struct drm_device *dev = connector->base.dev; |
752aa88a | 15020 | |
51fd371b | 15021 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 15022 | |
d3babd3f | 15023 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
15024 | return INVALID_PIPE; |
15025 | ||
15026 | return to_intel_crtc(encoder->crtc)->pipe; | |
15027 | } | |
15028 | ||
08d7b3d1 | 15029 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 15030 | struct drm_file *file) |
08d7b3d1 | 15031 | { |
08d7b3d1 | 15032 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 15033 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 15034 | struct intel_crtc *crtc; |
08d7b3d1 | 15035 | |
7707e653 | 15036 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 15037 | if (!drmmode_crtc) |
3f2c2057 | 15038 | return -ENOENT; |
08d7b3d1 | 15039 | |
7707e653 | 15040 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 15041 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 15042 | |
c05422d5 | 15043 | return 0; |
08d7b3d1 CW |
15044 | } |
15045 | ||
66a9278e | 15046 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 15047 | { |
66a9278e DV |
15048 | struct drm_device *dev = encoder->base.dev; |
15049 | struct intel_encoder *source_encoder; | |
79e53945 | 15050 | int index_mask = 0; |
79e53945 JB |
15051 | int entry = 0; |
15052 | ||
b2784e15 | 15053 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 15054 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
15055 | index_mask |= (1 << entry); |
15056 | ||
79e53945 JB |
15057 | entry++; |
15058 | } | |
4ef69c7a | 15059 | |
79e53945 JB |
15060 | return index_mask; |
15061 | } | |
15062 | ||
4d302442 CW |
15063 | static bool has_edp_a(struct drm_device *dev) |
15064 | { | |
fac5e23e | 15065 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d302442 CW |
15066 | |
15067 | if (!IS_MOBILE(dev)) | |
15068 | return false; | |
15069 | ||
15070 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
15071 | return false; | |
15072 | ||
e3589908 | 15073 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
15074 | return false; |
15075 | ||
15076 | return true; | |
15077 | } | |
15078 | ||
84b4e042 JB |
15079 | static bool intel_crt_present(struct drm_device *dev) |
15080 | { | |
fac5e23e | 15081 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 15082 | |
884497ed DL |
15083 | if (INTEL_INFO(dev)->gen >= 9) |
15084 | return false; | |
15085 | ||
cf404ce4 | 15086 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
15087 | return false; |
15088 | ||
15089 | if (IS_CHERRYVIEW(dev)) | |
15090 | return false; | |
15091 | ||
65e472e4 VS |
15092 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
15093 | return false; | |
15094 | ||
70ac54d0 VS |
15095 | /* DDI E can't be used if DDI A requires 4 lanes */ |
15096 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
15097 | return false; | |
15098 | ||
e4abb733 | 15099 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
15100 | return false; |
15101 | ||
15102 | return true; | |
15103 | } | |
15104 | ||
8090ba8c ID |
15105 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
15106 | { | |
15107 | int pps_num; | |
15108 | int pps_idx; | |
15109 | ||
15110 | if (HAS_DDI(dev_priv)) | |
15111 | return; | |
15112 | /* | |
15113 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
15114 | * everywhere where registers can be write protected. | |
15115 | */ | |
15116 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15117 | pps_num = 2; | |
15118 | else | |
15119 | pps_num = 1; | |
15120 | ||
15121 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
15122 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
15123 | ||
15124 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
15125 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
15126 | } | |
15127 | } | |
15128 | ||
44cb734c ID |
15129 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
15130 | { | |
15131 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) | |
15132 | dev_priv->pps_mmio_base = PCH_PPS_BASE; | |
15133 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15134 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
15135 | else | |
15136 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
15137 | |
15138 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
15139 | } |
15140 | ||
79e53945 JB |
15141 | static void intel_setup_outputs(struct drm_device *dev) |
15142 | { | |
fac5e23e | 15143 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 15144 | struct intel_encoder *encoder; |
cb0953d7 | 15145 | bool dpd_is_edp = false; |
79e53945 | 15146 | |
44cb734c ID |
15147 | intel_pps_init(dev_priv); |
15148 | ||
97a824e1 ID |
15149 | /* |
15150 | * intel_edp_init_connector() depends on this completing first, to | |
15151 | * prevent the registeration of both eDP and LVDS and the incorrect | |
15152 | * sharing of the PPS. | |
15153 | */ | |
c9093354 | 15154 | intel_lvds_init(dev); |
79e53945 | 15155 | |
84b4e042 | 15156 | if (intel_crt_present(dev)) |
79935fca | 15157 | intel_crt_init(dev); |
cb0953d7 | 15158 | |
c776eb2e VK |
15159 | if (IS_BROXTON(dev)) { |
15160 | /* | |
15161 | * FIXME: Broxton doesn't support port detection via the | |
15162 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
15163 | * detect the ports. | |
15164 | */ | |
15165 | intel_ddi_init(dev, PORT_A); | |
15166 | intel_ddi_init(dev, PORT_B); | |
15167 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
15168 | |
15169 | intel_dsi_init(dev); | |
c776eb2e | 15170 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
15171 | int found; |
15172 | ||
de31facd JB |
15173 | /* |
15174 | * Haswell uses DDI functions to detect digital outputs. | |
15175 | * On SKL pre-D0 the strap isn't connected, so we assume | |
15176 | * it's there. | |
15177 | */ | |
77179400 | 15178 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 15179 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 15180 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
15181 | intel_ddi_init(dev, PORT_A); |
15182 | ||
15183 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
15184 | * register */ | |
15185 | found = I915_READ(SFUSE_STRAP); | |
15186 | ||
15187 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
15188 | intel_ddi_init(dev, PORT_B); | |
15189 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
15190 | intel_ddi_init(dev, PORT_C); | |
15191 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
15192 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
15193 | /* |
15194 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
15195 | */ | |
ef11bdb3 | 15196 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
15197 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
15198 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
15199 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
15200 | intel_ddi_init(dev, PORT_E); | |
15201 | ||
0e72a5b5 | 15202 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 15203 | int found; |
5d8a7752 | 15204 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
15205 | |
15206 | if (has_edp_a(dev)) | |
15207 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 15208 | |
dc0fa718 | 15209 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 15210 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 15211 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 15212 | if (!found) |
e2debe91 | 15213 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 15214 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 15215 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
15216 | } |
15217 | ||
dc0fa718 | 15218 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 15219 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 15220 | |
dc0fa718 | 15221 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 15222 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 15223 | |
5eb08b69 | 15224 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 15225 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 15226 | |
270b3042 | 15227 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 15228 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 15229 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
22f35042 | 15230 | bool has_edp, has_port; |
457c52d8 | 15231 | |
e17ac6db VS |
15232 | /* |
15233 | * The DP_DETECTED bit is the latched state of the DDC | |
15234 | * SDA pin at boot. However since eDP doesn't require DDC | |
15235 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15236 | * eDP ports may have been muxed to an alternate function. | |
15237 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15238 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15239 | * detect eDP ports. | |
22f35042 VS |
15240 | * |
15241 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15242 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15243 | * and VBT for the presence of the port. Additionally we can't | |
15244 | * trust the port type the VBT declares as we've seen at least | |
15245 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15246 | */ |
457c52d8 | 15247 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
15248 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15249 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 15250 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 15251 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15252 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 15253 | |
457c52d8 | 15254 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
15255 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15256 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 15257 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 15258 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15259 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 15260 | |
9418c1f1 | 15261 | if (IS_CHERRYVIEW(dev)) { |
22f35042 VS |
15262 | /* |
15263 | * eDP not supported on port D, | |
15264 | * so no need to worry about it | |
15265 | */ | |
15266 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15267 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 15268 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
15269 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
15270 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
15271 | } |
15272 | ||
3cfca973 | 15273 | intel_dsi_init(dev); |
09da55dc | 15274 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 15275 | bool found = false; |
7d57382e | 15276 | |
e2debe91 | 15277 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15278 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 15279 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 15280 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 15281 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 15282 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15283 | } |
27185ae1 | 15284 | |
3fec3d2f | 15285 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 15286 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 15287 | } |
13520b05 KH |
15288 | |
15289 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15290 | |
e2debe91 | 15291 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15292 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 15293 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15294 | } |
27185ae1 | 15295 | |
e2debe91 | 15296 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15297 | |
3fec3d2f | 15298 | if (IS_G4X(dev)) { |
b01f2c3a | 15299 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 15300 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15301 | } |
3fec3d2f | 15302 | if (IS_G4X(dev)) |
ab9d7c30 | 15303 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 15304 | } |
27185ae1 | 15305 | |
3fec3d2f | 15306 | if (IS_G4X(dev) && |
e7281eab | 15307 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 15308 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 15309 | } else if (IS_GEN2(dev)) |
79e53945 JB |
15310 | intel_dvo_init(dev); |
15311 | ||
103a196f | 15312 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
15313 | intel_tv_init(dev); |
15314 | ||
0bc12bcb | 15315 | intel_psr_init(dev); |
7c8f8a70 | 15316 | |
b2784e15 | 15317 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
15318 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15319 | encoder->base.possible_clones = | |
66a9278e | 15320 | intel_encoder_clones(encoder); |
79e53945 | 15321 | } |
47356eb6 | 15322 | |
dde86e2d | 15323 | intel_init_pch_refclk(dev); |
270b3042 DV |
15324 | |
15325 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
15326 | } |
15327 | ||
15328 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15329 | { | |
60a5ca01 | 15330 | struct drm_device *dev = fb->dev; |
79e53945 | 15331 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15332 | |
ef2d633e | 15333 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15334 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15335 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15336 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15337 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15338 | kfree(intel_fb); |
15339 | } | |
15340 | ||
15341 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15342 | struct drm_file *file, |
79e53945 JB |
15343 | unsigned int *handle) |
15344 | { | |
15345 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15346 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15347 | |
cc917ab4 CW |
15348 | if (obj->userptr.mm) { |
15349 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15350 | return -EINVAL; | |
15351 | } | |
15352 | ||
05394f39 | 15353 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15354 | } |
15355 | ||
86c98588 RV |
15356 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15357 | struct drm_file *file, | |
15358 | unsigned flags, unsigned color, | |
15359 | struct drm_clip_rect *clips, | |
15360 | unsigned num_clips) | |
15361 | { | |
15362 | struct drm_device *dev = fb->dev; | |
15363 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15364 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15365 | ||
15366 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 15367 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15368 | mutex_unlock(&dev->struct_mutex); |
15369 | ||
15370 | return 0; | |
15371 | } | |
15372 | ||
79e53945 JB |
15373 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15374 | .destroy = intel_user_framebuffer_destroy, | |
15375 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15376 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15377 | }; |
15378 | ||
b321803d DL |
15379 | static |
15380 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
15381 | uint32_t pixel_format) | |
15382 | { | |
15383 | u32 gen = INTEL_INFO(dev)->gen; | |
15384 | ||
15385 | if (gen >= 9) { | |
ac484963 VS |
15386 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15387 | ||
b321803d DL |
15388 | /* "The stride in bytes must not exceed the of the size of 8K |
15389 | * pixels and 32K bytes." | |
15390 | */ | |
ac484963 | 15391 | return min(8192 * cpp, 32768); |
666a4537 | 15392 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
15393 | return 32*1024; |
15394 | } else if (gen >= 4) { | |
15395 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15396 | return 16*1024; | |
15397 | else | |
15398 | return 32*1024; | |
15399 | } else if (gen >= 3) { | |
15400 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15401 | return 8*1024; | |
15402 | else | |
15403 | return 16*1024; | |
15404 | } else { | |
15405 | /* XXX DSPC is limited to 4k tiled */ | |
15406 | return 8*1024; | |
15407 | } | |
15408 | } | |
15409 | ||
b5ea642a DV |
15410 | static int intel_framebuffer_init(struct drm_device *dev, |
15411 | struct intel_framebuffer *intel_fb, | |
15412 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15413 | struct drm_i915_gem_object *obj) | |
79e53945 | 15414 | { |
7b49f948 | 15415 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2ff7370 | 15416 | unsigned int tiling = i915_gem_object_get_tiling(obj); |
79e53945 | 15417 | int ret; |
b321803d | 15418 | u32 pitch_limit, stride_alignment; |
79e53945 | 15419 | |
dd4916c5 DV |
15420 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15421 | ||
2a80eada | 15422 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
15423 | /* |
15424 | * If there's a fence, enforce that | |
15425 | * the fb modifier and tiling mode match. | |
15426 | */ | |
15427 | if (tiling != I915_TILING_NONE && | |
15428 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada DV |
15429 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
15430 | return -EINVAL; | |
15431 | } | |
15432 | } else { | |
c2ff7370 | 15433 | if (tiling == I915_TILING_X) { |
2a80eada | 15434 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 15435 | } else if (tiling == I915_TILING_Y) { |
2a80eada DV |
15436 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15437 | return -EINVAL; | |
15438 | } | |
15439 | } | |
15440 | ||
9a8f0a12 TU |
15441 | /* Passed in modifier sanity checking. */ |
15442 | switch (mode_cmd->modifier[0]) { | |
15443 | case I915_FORMAT_MOD_Y_TILED: | |
15444 | case I915_FORMAT_MOD_Yf_TILED: | |
15445 | if (INTEL_INFO(dev)->gen < 9) { | |
15446 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
15447 | mode_cmd->modifier[0]); | |
15448 | return -EINVAL; | |
15449 | } | |
15450 | case DRM_FORMAT_MOD_NONE: | |
15451 | case I915_FORMAT_MOD_X_TILED: | |
15452 | break; | |
15453 | default: | |
c0f40428 JB |
15454 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15455 | mode_cmd->modifier[0]); | |
57cd6508 | 15456 | return -EINVAL; |
c16ed4be | 15457 | } |
57cd6508 | 15458 | |
c2ff7370 VS |
15459 | /* |
15460 | * gen2/3 display engine uses the fence if present, | |
15461 | * so the tiling mode must match the fb modifier exactly. | |
15462 | */ | |
15463 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
15464 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
15465 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
15466 | return -EINVAL; | |
15467 | } | |
15468 | ||
7b49f948 VS |
15469 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15470 | mode_cmd->modifier[0], | |
b321803d DL |
15471 | mode_cmd->pixel_format); |
15472 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15473 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15474 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15475 | return -EINVAL; |
c16ed4be | 15476 | } |
57cd6508 | 15477 | |
b321803d DL |
15478 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
15479 | mode_cmd->pixel_format); | |
a35cdaa0 | 15480 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15481 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15482 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15483 | "tiled" : "linear", |
a35cdaa0 | 15484 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15485 | return -EINVAL; |
c16ed4be | 15486 | } |
5d7bd705 | 15487 | |
c2ff7370 VS |
15488 | /* |
15489 | * If there's a fence, enforce that | |
15490 | * the fb pitch and fence stride match. | |
15491 | */ | |
15492 | if (tiling != I915_TILING_NONE && | |
3e510a8e | 15493 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15494 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15495 | mode_cmd->pitches[0], |
15496 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15497 | return -EINVAL; |
c16ed4be | 15498 | } |
5d7bd705 | 15499 | |
57779d06 | 15500 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15501 | switch (mode_cmd->pixel_format) { |
57779d06 | 15502 | case DRM_FORMAT_C8: |
04b3924d VS |
15503 | case DRM_FORMAT_RGB565: |
15504 | case DRM_FORMAT_XRGB8888: | |
15505 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15506 | break; |
15507 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15508 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
15509 | DRM_DEBUG("unsupported pixel format: %s\n", |
15510 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15511 | return -EINVAL; |
c16ed4be | 15512 | } |
57779d06 | 15513 | break; |
57779d06 | 15514 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
15515 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
15516 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
15517 | DRM_DEBUG("unsupported pixel format: %s\n", |
15518 | drm_get_format_name(mode_cmd->pixel_format)); | |
15519 | return -EINVAL; | |
15520 | } | |
15521 | break; | |
15522 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15523 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15524 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15525 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15526 | DRM_DEBUG("unsupported pixel format: %s\n", |
15527 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15528 | return -EINVAL; |
c16ed4be | 15529 | } |
b5626747 | 15530 | break; |
7531208b | 15531 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15532 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15533 | DRM_DEBUG("unsupported pixel format: %s\n", |
15534 | drm_get_format_name(mode_cmd->pixel_format)); | |
15535 | return -EINVAL; | |
15536 | } | |
15537 | break; | |
04b3924d VS |
15538 | case DRM_FORMAT_YUYV: |
15539 | case DRM_FORMAT_UYVY: | |
15540 | case DRM_FORMAT_YVYU: | |
15541 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15542 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15543 | DRM_DEBUG("unsupported pixel format: %s\n", |
15544 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15545 | return -EINVAL; |
c16ed4be | 15546 | } |
57cd6508 CW |
15547 | break; |
15548 | default: | |
4ee62c76 VS |
15549 | DRM_DEBUG("unsupported pixel format: %s\n", |
15550 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15551 | return -EINVAL; |
15552 | } | |
15553 | ||
90f9a336 VS |
15554 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15555 | if (mode_cmd->offsets[0] != 0) | |
15556 | return -EINVAL; | |
15557 | ||
c7d73f6a DV |
15558 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15559 | intel_fb->obj = obj; | |
15560 | ||
6687c906 VS |
15561 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15562 | if (ret) | |
15563 | return ret; | |
2d7a215f | 15564 | |
79e53945 JB |
15565 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15566 | if (ret) { | |
15567 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15568 | return ret; | |
15569 | } | |
15570 | ||
0b05e1e0 VS |
15571 | intel_fb->obj->framebuffer_references++; |
15572 | ||
79e53945 JB |
15573 | return 0; |
15574 | } | |
15575 | ||
79e53945 JB |
15576 | static struct drm_framebuffer * |
15577 | intel_user_framebuffer_create(struct drm_device *dev, | |
15578 | struct drm_file *filp, | |
1eb83451 | 15579 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15580 | { |
dcb1394e | 15581 | struct drm_framebuffer *fb; |
05394f39 | 15582 | struct drm_i915_gem_object *obj; |
76dc3769 | 15583 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15584 | |
03ac0642 CW |
15585 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15586 | if (!obj) | |
cce13ff7 | 15587 | return ERR_PTR(-ENOENT); |
79e53945 | 15588 | |
92907cbb | 15589 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15590 | if (IS_ERR(fb)) |
34911fd3 | 15591 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
15592 | |
15593 | return fb; | |
79e53945 JB |
15594 | } |
15595 | ||
0695726e | 15596 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15597 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15598 | { |
15599 | } | |
15600 | #endif | |
15601 | ||
79e53945 | 15602 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15603 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15604 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15605 | .atomic_check = intel_atomic_check, |
15606 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15607 | .atomic_state_alloc = intel_atomic_state_alloc, |
15608 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15609 | }; |
15610 | ||
88212941 ID |
15611 | /** |
15612 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15613 | * @dev_priv: device private | |
15614 | */ | |
15615 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15616 | { |
88212941 | 15617 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15618 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15619 | dev_priv->display.get_initial_plane_config = |
15620 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15621 | dev_priv->display.crtc_compute_clock = |
15622 | haswell_crtc_compute_clock; | |
15623 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15624 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15625 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15626 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15627 | dev_priv->display.get_initial_plane_config = |
15628 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15629 | dev_priv->display.crtc_compute_clock = |
15630 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15631 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15632 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15633 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15634 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15635 | dev_priv->display.get_initial_plane_config = |
15636 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15637 | dev_priv->display.crtc_compute_clock = |
15638 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15639 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15640 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15641 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15642 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15643 | dev_priv->display.get_initial_plane_config = |
15644 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15645 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15646 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15647 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15648 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15649 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15650 | dev_priv->display.get_initial_plane_config = | |
15651 | i9xx_get_initial_plane_config; | |
15652 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15653 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15654 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15655 | } else if (IS_G4X(dev_priv)) { |
15656 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15657 | dev_priv->display.get_initial_plane_config = | |
15658 | i9xx_get_initial_plane_config; | |
15659 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15660 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15661 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15662 | } else if (IS_PINEVIEW(dev_priv)) { |
15663 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15664 | dev_priv->display.get_initial_plane_config = | |
15665 | i9xx_get_initial_plane_config; | |
15666 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15667 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15668 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15669 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15670 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15671 | dev_priv->display.get_initial_plane_config = |
15672 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15673 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15674 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15675 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
15676 | } else { |
15677 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15678 | dev_priv->display.get_initial_plane_config = | |
15679 | i9xx_get_initial_plane_config; | |
15680 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
15681 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15682 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15683 | } |
e70236a8 | 15684 | |
e70236a8 | 15685 | /* Returns the core display clock speed */ |
88212941 | 15686 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
15687 | dev_priv->display.get_display_clock_speed = |
15688 | skylake_get_display_clock_speed; | |
88212941 | 15689 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
15690 | dev_priv->display.get_display_clock_speed = |
15691 | broxton_get_display_clock_speed; | |
88212941 | 15692 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
15693 | dev_priv->display.get_display_clock_speed = |
15694 | broadwell_get_display_clock_speed; | |
88212941 | 15695 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
15696 | dev_priv->display.get_display_clock_speed = |
15697 | haswell_get_display_clock_speed; | |
88212941 | 15698 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
15699 | dev_priv->display.get_display_clock_speed = |
15700 | valleyview_get_display_clock_speed; | |
88212941 | 15701 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
15702 | dev_priv->display.get_display_clock_speed = |
15703 | ilk_get_display_clock_speed; | |
88212941 ID |
15704 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
15705 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
15706 | dev_priv->display.get_display_clock_speed = |
15707 | i945_get_display_clock_speed; | |
88212941 | 15708 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
15709 | dev_priv->display.get_display_clock_speed = |
15710 | gm45_get_display_clock_speed; | |
88212941 | 15711 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
15712 | dev_priv->display.get_display_clock_speed = |
15713 | i965gm_get_display_clock_speed; | |
88212941 | 15714 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
15715 | dev_priv->display.get_display_clock_speed = |
15716 | pnv_get_display_clock_speed; | |
88212941 | 15717 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
15718 | dev_priv->display.get_display_clock_speed = |
15719 | g33_get_display_clock_speed; | |
88212941 | 15720 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
15721 | dev_priv->display.get_display_clock_speed = |
15722 | i915_get_display_clock_speed; | |
88212941 | 15723 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
15724 | dev_priv->display.get_display_clock_speed = |
15725 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15726 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15727 | dev_priv->display.get_display_clock_speed = |
15728 | i915gm_get_display_clock_speed; | |
88212941 | 15729 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15730 | dev_priv->display.get_display_clock_speed = |
15731 | i865_get_display_clock_speed; | |
88212941 | 15732 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15733 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15734 | i85x_get_display_clock_speed; |
623e01e5 | 15735 | else { /* 830 */ |
88212941 | 15736 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15737 | dev_priv->display.get_display_clock_speed = |
15738 | i830_get_display_clock_speed; | |
623e01e5 | 15739 | } |
e70236a8 | 15740 | |
88212941 | 15741 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15742 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15743 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15744 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15745 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15746 | /* FIXME: detect B0+ stepping and use auto training */ |
15747 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15748 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15749 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15750 | } |
15751 | ||
15752 | if (IS_BROADWELL(dev_priv)) { | |
15753 | dev_priv->display.modeset_commit_cdclk = | |
15754 | broadwell_modeset_commit_cdclk; | |
15755 | dev_priv->display.modeset_calc_cdclk = | |
15756 | broadwell_modeset_calc_cdclk; | |
88212941 | 15757 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15758 | dev_priv->display.modeset_commit_cdclk = |
15759 | valleyview_modeset_commit_cdclk; | |
15760 | dev_priv->display.modeset_calc_cdclk = | |
15761 | valleyview_modeset_calc_cdclk; | |
88212941 | 15762 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 15763 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 15764 | bxt_modeset_commit_cdclk; |
27c329ed | 15765 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 15766 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
15767 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
15768 | dev_priv->display.modeset_commit_cdclk = | |
15769 | skl_modeset_commit_cdclk; | |
15770 | dev_priv->display.modeset_calc_cdclk = | |
15771 | skl_modeset_calc_cdclk; | |
e70236a8 | 15772 | } |
5a21b665 DV |
15773 | |
15774 | switch (INTEL_INFO(dev_priv)->gen) { | |
15775 | case 2: | |
15776 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15777 | break; | |
15778 | ||
15779 | case 3: | |
15780 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15781 | break; | |
15782 | ||
15783 | case 4: | |
15784 | case 5: | |
15785 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15786 | break; | |
15787 | ||
15788 | case 6: | |
15789 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15790 | break; | |
15791 | case 7: | |
15792 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15793 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15794 | break; | |
15795 | case 9: | |
15796 | /* Drop through - unsupported since execlist only. */ | |
15797 | default: | |
15798 | /* Default just returns -ENODEV to indicate unsupported */ | |
15799 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15800 | } | |
e70236a8 JB |
15801 | } |
15802 | ||
b690e96c JB |
15803 | /* |
15804 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15805 | * resume, or other times. This quirk makes sure that's the case for | |
15806 | * affected systems. | |
15807 | */ | |
0206e353 | 15808 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 15809 | { |
fac5e23e | 15810 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
15811 | |
15812 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15813 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15814 | } |
15815 | ||
b6b5d049 VS |
15816 | static void quirk_pipeb_force(struct drm_device *dev) |
15817 | { | |
fac5e23e | 15818 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
15819 | |
15820 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15821 | DRM_INFO("applying pipe b force quirk\n"); | |
15822 | } | |
15823 | ||
435793df KP |
15824 | /* |
15825 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15826 | */ | |
15827 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15828 | { | |
fac5e23e | 15829 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 15830 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 15831 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15832 | } |
15833 | ||
4dca20ef | 15834 | /* |
5a15ab5b CE |
15835 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15836 | * brightness value | |
4dca20ef CE |
15837 | */ |
15838 | static void quirk_invert_brightness(struct drm_device *dev) | |
15839 | { | |
fac5e23e | 15840 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 15841 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 15842 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15843 | } |
15844 | ||
9c72cc6f SD |
15845 | /* Some VBT's incorrectly indicate no backlight is present */ |
15846 | static void quirk_backlight_present(struct drm_device *dev) | |
15847 | { | |
fac5e23e | 15848 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
15849 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
15850 | DRM_INFO("applying backlight present quirk\n"); | |
15851 | } | |
15852 | ||
b690e96c JB |
15853 | struct intel_quirk { |
15854 | int device; | |
15855 | int subsystem_vendor; | |
15856 | int subsystem_device; | |
15857 | void (*hook)(struct drm_device *dev); | |
15858 | }; | |
15859 | ||
5f85f176 EE |
15860 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15861 | struct intel_dmi_quirk { | |
15862 | void (*hook)(struct drm_device *dev); | |
15863 | const struct dmi_system_id (*dmi_id_list)[]; | |
15864 | }; | |
15865 | ||
15866 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15867 | { | |
15868 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15869 | return 1; | |
15870 | } | |
15871 | ||
15872 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15873 | { | |
15874 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15875 | { | |
15876 | .callback = intel_dmi_reverse_brightness, | |
15877 | .ident = "NCR Corporation", | |
15878 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15879 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15880 | }, | |
15881 | }, | |
15882 | { } /* terminating entry */ | |
15883 | }, | |
15884 | .hook = quirk_invert_brightness, | |
15885 | }, | |
15886 | }; | |
15887 | ||
c43b5634 | 15888 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15889 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15890 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15891 | ||
b690e96c JB |
15892 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15893 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15894 | ||
5f080c0f VS |
15895 | /* 830 needs to leave pipe A & dpll A up */ |
15896 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15897 | ||
b6b5d049 VS |
15898 | /* 830 needs to leave pipe B & dpll B up */ |
15899 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15900 | ||
435793df KP |
15901 | /* Lenovo U160 cannot use SSC on LVDS */ |
15902 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15903 | |
15904 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15905 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15906 | |
be505f64 AH |
15907 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15908 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15909 | ||
15910 | /* Acer/eMachines G725 */ | |
15911 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15912 | ||
15913 | /* Acer/eMachines e725 */ | |
15914 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15915 | ||
15916 | /* Acer/Packard Bell NCL20 */ | |
15917 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15918 | ||
15919 | /* Acer Aspire 4736Z */ | |
15920 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15921 | |
15922 | /* Acer Aspire 5336 */ | |
15923 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15924 | |
15925 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15926 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15927 | |
dfb3d47b SD |
15928 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15929 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15930 | ||
b2a9601c | 15931 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15932 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15933 | ||
1b9448b0 JN |
15934 | /* Apple Macbook 4,1 */ |
15935 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15936 | ||
d4967d8c SD |
15937 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15938 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15939 | |
15940 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15941 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15942 | |
15943 | /* Dell Chromebook 11 */ | |
15944 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15945 | |
15946 | /* Dell Chromebook 11 (2015 version) */ | |
15947 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15948 | }; |
15949 | ||
15950 | static void intel_init_quirks(struct drm_device *dev) | |
15951 | { | |
15952 | struct pci_dev *d = dev->pdev; | |
15953 | int i; | |
15954 | ||
15955 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15956 | struct intel_quirk *q = &intel_quirks[i]; | |
15957 | ||
15958 | if (d->device == q->device && | |
15959 | (d->subsystem_vendor == q->subsystem_vendor || | |
15960 | q->subsystem_vendor == PCI_ANY_ID) && | |
15961 | (d->subsystem_device == q->subsystem_device || | |
15962 | q->subsystem_device == PCI_ANY_ID)) | |
15963 | q->hook(dev); | |
15964 | } | |
5f85f176 EE |
15965 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15966 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15967 | intel_dmi_quirks[i].hook(dev); | |
15968 | } | |
b690e96c JB |
15969 | } |
15970 | ||
9cce37f4 JB |
15971 | /* Disable the VGA plane that we never use */ |
15972 | static void i915_disable_vga(struct drm_device *dev) | |
15973 | { | |
fac5e23e | 15974 | struct drm_i915_private *dev_priv = to_i915(dev); |
9cce37f4 | 15975 | u8 sr1; |
f0f59a00 | 15976 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15977 | |
2b37c616 | 15978 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15979 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15980 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15981 | sr1 = inb(VGA_SR_DATA); |
15982 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15983 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15984 | udelay(300); | |
15985 | ||
01f5a626 | 15986 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15987 | POSTING_READ(vga_reg); |
15988 | } | |
15989 | ||
f817586c DV |
15990 | void intel_modeset_init_hw(struct drm_device *dev) |
15991 | { | |
fac5e23e | 15992 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 15993 | |
b6283055 | 15994 | intel_update_cdclk(dev); |
1a617b77 ML |
15995 | |
15996 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15997 | ||
f817586c | 15998 | intel_init_clock_gating(dev); |
f817586c DV |
15999 | } |
16000 | ||
d93c0372 MR |
16001 | /* |
16002 | * Calculate what we think the watermarks should be for the state we've read | |
16003 | * out of the hardware and then immediately program those watermarks so that | |
16004 | * we ensure the hardware settings match our internal state. | |
16005 | * | |
16006 | * We can calculate what we think WM's should be by creating a duplicate of the | |
16007 | * current state (which was constructed during hardware readout) and running it | |
16008 | * through the atomic check code to calculate new watermark values in the | |
16009 | * state object. | |
16010 | */ | |
16011 | static void sanitize_watermarks(struct drm_device *dev) | |
16012 | { | |
16013 | struct drm_i915_private *dev_priv = to_i915(dev); | |
16014 | struct drm_atomic_state *state; | |
16015 | struct drm_crtc *crtc; | |
16016 | struct drm_crtc_state *cstate; | |
16017 | struct drm_modeset_acquire_ctx ctx; | |
16018 | int ret; | |
16019 | int i; | |
16020 | ||
16021 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 16022 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
16023 | return; |
16024 | ||
16025 | /* | |
16026 | * We need to hold connection_mutex before calling duplicate_state so | |
16027 | * that the connector loop is protected. | |
16028 | */ | |
16029 | drm_modeset_acquire_init(&ctx, 0); | |
16030 | retry: | |
0cd1262d | 16031 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
16032 | if (ret == -EDEADLK) { |
16033 | drm_modeset_backoff(&ctx); | |
16034 | goto retry; | |
16035 | } else if (WARN_ON(ret)) { | |
0cd1262d | 16036 | goto fail; |
d93c0372 MR |
16037 | } |
16038 | ||
16039 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
16040 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 16041 | goto fail; |
d93c0372 | 16042 | |
ed4a6a7c MR |
16043 | /* |
16044 | * Hardware readout is the only time we don't want to calculate | |
16045 | * intermediate watermarks (since we don't trust the current | |
16046 | * watermarks). | |
16047 | */ | |
16048 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
16049 | ||
d93c0372 MR |
16050 | ret = intel_atomic_check(dev, state); |
16051 | if (ret) { | |
16052 | /* | |
16053 | * If we fail here, it means that the hardware appears to be | |
16054 | * programmed in a way that shouldn't be possible, given our | |
16055 | * understanding of watermark requirements. This might mean a | |
16056 | * mistake in the hardware readout code or a mistake in the | |
16057 | * watermark calculations for a given platform. Raise a WARN | |
16058 | * so that this is noticeable. | |
16059 | * | |
16060 | * If this actually happens, we'll have to just leave the | |
16061 | * BIOS-programmed watermarks untouched and hope for the best. | |
16062 | */ | |
16063 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 16064 | goto fail; |
d93c0372 MR |
16065 | } |
16066 | ||
16067 | /* Write calculated watermark values back */ | |
d93c0372 MR |
16068 | for_each_crtc_in_state(state, crtc, cstate, i) { |
16069 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
16070 | ||
ed4a6a7c MR |
16071 | cs->wm.need_postvbl_update = true; |
16072 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
16073 | } |
16074 | ||
16075 | drm_atomic_state_free(state); | |
0cd1262d | 16076 | fail: |
d93c0372 MR |
16077 | drm_modeset_drop_locks(&ctx); |
16078 | drm_modeset_acquire_fini(&ctx); | |
16079 | } | |
16080 | ||
79e53945 JB |
16081 | void intel_modeset_init(struct drm_device *dev) |
16082 | { | |
72e96d64 JL |
16083 | struct drm_i915_private *dev_priv = to_i915(dev); |
16084 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 16085 | int sprite, ret; |
8cc87b75 | 16086 | enum pipe pipe; |
46f297fb | 16087 | struct intel_crtc *crtc; |
79e53945 JB |
16088 | |
16089 | drm_mode_config_init(dev); | |
16090 | ||
16091 | dev->mode_config.min_width = 0; | |
16092 | dev->mode_config.min_height = 0; | |
16093 | ||
019d96cb DA |
16094 | dev->mode_config.preferred_depth = 24; |
16095 | dev->mode_config.prefer_shadow = 1; | |
16096 | ||
25bab385 TU |
16097 | dev->mode_config.allow_fb_modifiers = true; |
16098 | ||
e6ecefaa | 16099 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 16100 | |
b690e96c JB |
16101 | intel_init_quirks(dev); |
16102 | ||
1fa61106 ED |
16103 | intel_init_pm(dev); |
16104 | ||
e3c74757 BW |
16105 | if (INTEL_INFO(dev)->num_pipes == 0) |
16106 | return; | |
16107 | ||
69f92f67 LW |
16108 | /* |
16109 | * There may be no VBT; and if the BIOS enabled SSC we can | |
16110 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
16111 | * BIOS isn't using it, don't assume it will work even if the VBT | |
16112 | * indicates as much. | |
16113 | */ | |
16114 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
16115 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
16116 | DREF_SSC1_ENABLE); | |
16117 | ||
16118 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
16119 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
16120 | bios_lvds_use_ssc ? "en" : "dis", | |
16121 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
16122 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
16123 | } | |
16124 | } | |
16125 | ||
a6c45cf0 CW |
16126 | if (IS_GEN2(dev)) { |
16127 | dev->mode_config.max_width = 2048; | |
16128 | dev->mode_config.max_height = 2048; | |
16129 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
16130 | dev->mode_config.max_width = 4096; |
16131 | dev->mode_config.max_height = 4096; | |
79e53945 | 16132 | } else { |
a6c45cf0 CW |
16133 | dev->mode_config.max_width = 8192; |
16134 | dev->mode_config.max_height = 8192; | |
79e53945 | 16135 | } |
068be561 | 16136 | |
dc41c154 VS |
16137 | if (IS_845G(dev) || IS_I865G(dev)) { |
16138 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
16139 | dev->mode_config.cursor_height = 1023; | |
16140 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
16141 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
16142 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
16143 | } else { | |
16144 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
16145 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
16146 | } | |
16147 | ||
72e96d64 | 16148 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 16149 | |
28c97730 | 16150 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
16151 | INTEL_INFO(dev)->num_pipes, |
16152 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 16153 | |
055e393f | 16154 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 16155 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 16156 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 16157 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 16158 | if (ret) |
06da8da2 | 16159 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 16160 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 16161 | } |
79e53945 JB |
16162 | } |
16163 | ||
bfa7df01 VS |
16164 | intel_update_czclk(dev_priv); |
16165 | intel_update_cdclk(dev); | |
16166 | ||
e72f9fbf | 16167 | intel_shared_dpll_init(dev); |
ee7b9f93 | 16168 | |
b2045352 VS |
16169 | if (dev_priv->max_cdclk_freq == 0) |
16170 | intel_update_max_cdclk(dev); | |
16171 | ||
9cce37f4 JB |
16172 | /* Just disable it once at startup */ |
16173 | i915_disable_vga(dev); | |
79e53945 | 16174 | intel_setup_outputs(dev); |
11be49eb | 16175 | |
6e9f798d | 16176 | drm_modeset_lock_all(dev); |
043e9bda | 16177 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 16178 | drm_modeset_unlock_all(dev); |
46f297fb | 16179 | |
d3fcc808 | 16180 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
16181 | struct intel_initial_plane_config plane_config = {}; |
16182 | ||
46f297fb JB |
16183 | if (!crtc->active) |
16184 | continue; | |
16185 | ||
46f297fb | 16186 | /* |
46f297fb JB |
16187 | * Note that reserving the BIOS fb up front prevents us |
16188 | * from stuffing other stolen allocations like the ring | |
16189 | * on top. This prevents some ugliness at boot time, and | |
16190 | * can even allow for smooth boot transitions if the BIOS | |
16191 | * fb is large enough for the active pipe configuration. | |
16192 | */ | |
eeebeac5 ML |
16193 | dev_priv->display.get_initial_plane_config(crtc, |
16194 | &plane_config); | |
16195 | ||
16196 | /* | |
16197 | * If the fb is shared between multiple heads, we'll | |
16198 | * just get the first one. | |
16199 | */ | |
16200 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 16201 | } |
d93c0372 MR |
16202 | |
16203 | /* | |
16204 | * Make sure hardware watermarks really match the state we read out. | |
16205 | * Note that we need to do this after reconstructing the BIOS fb's | |
16206 | * since the watermark calculation done here will use pstate->fb. | |
16207 | */ | |
16208 | sanitize_watermarks(dev); | |
2c7111db CW |
16209 | } |
16210 | ||
7fad798e DV |
16211 | static void intel_enable_pipe_a(struct drm_device *dev) |
16212 | { | |
16213 | struct intel_connector *connector; | |
16214 | struct drm_connector *crt = NULL; | |
16215 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 16216 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
16217 | |
16218 | /* We can't just switch on the pipe A, we need to set things up with a | |
16219 | * proper mode and output configuration. As a gross hack, enable pipe A | |
16220 | * by enabling the load detect pipe once. */ | |
3a3371ff | 16221 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
16222 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
16223 | crt = &connector->base; | |
16224 | break; | |
16225 | } | |
16226 | } | |
16227 | ||
16228 | if (!crt) | |
16229 | return; | |
16230 | ||
208bf9fd | 16231 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 16232 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
16233 | } |
16234 | ||
fa555837 DV |
16235 | static bool |
16236 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
16237 | { | |
7eb552ae | 16238 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 16239 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 16240 | u32 val; |
fa555837 | 16241 | |
7eb552ae | 16242 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
16243 | return true; |
16244 | ||
649636ef | 16245 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
16246 | |
16247 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16248 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16249 | return false; | |
16250 | ||
16251 | return true; | |
16252 | } | |
16253 | ||
02e93c35 VS |
16254 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16255 | { | |
16256 | struct drm_device *dev = crtc->base.dev; | |
16257 | struct intel_encoder *encoder; | |
16258 | ||
16259 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16260 | return true; | |
16261 | ||
16262 | return false; | |
16263 | } | |
16264 | ||
dd756198 VS |
16265 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
16266 | { | |
16267 | struct drm_device *dev = encoder->base.dev; | |
16268 | struct intel_connector *connector; | |
16269 | ||
16270 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16271 | return true; | |
16272 | ||
16273 | return false; | |
16274 | } | |
16275 | ||
a168f5b3 VS |
16276 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16277 | enum transcoder pch_transcoder) | |
16278 | { | |
16279 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16280 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16281 | } | |
16282 | ||
24929352 DV |
16283 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16284 | { | |
16285 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16286 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16287 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16288 | |
24929352 | 16289 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16290 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16291 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16292 | ||
16293 | I915_WRITE(reg, | |
16294 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16295 | } | |
24929352 | 16296 | |
d3eaf884 | 16297 | /* restore vblank interrupts to correct state */ |
9625604c | 16298 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16299 | if (crtc->active) { |
f9cd7b88 VS |
16300 | struct intel_plane *plane; |
16301 | ||
9625604c | 16302 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16303 | |
16304 | /* Disable everything but the primary plane */ | |
16305 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16306 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16307 | continue; | |
16308 | ||
16309 | plane->disable_plane(&plane->base, &crtc->base); | |
16310 | } | |
9625604c | 16311 | } |
d3eaf884 | 16312 | |
24929352 | 16313 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16314 | * disable the crtc (and hence change the state) if it is wrong. Note |
16315 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
16316 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
16317 | bool plane; |
16318 | ||
78108b7c VS |
16319 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16320 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16321 | |
16322 | /* Pipe has the wrong plane attached and the plane is active. | |
16323 | * Temporarily change the plane mapping and disable everything | |
16324 | * ... */ | |
16325 | plane = crtc->plane; | |
936e71e3 | 16326 | to_intel_plane_state(crtc->base.primary->state)->base.visible = true; |
24929352 | 16327 | crtc->plane = !plane; |
b17d48e2 | 16328 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16329 | crtc->plane = plane; |
24929352 | 16330 | } |
24929352 | 16331 | |
7fad798e DV |
16332 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16333 | crtc->pipe == PIPE_A && !crtc->active) { | |
16334 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16335 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16336 | * call below we restore the pipe to the right state, but leave | |
16337 | * the required bits on. */ | |
16338 | intel_enable_pipe_a(dev); | |
16339 | } | |
16340 | ||
24929352 DV |
16341 | /* Adjust the state of the output pipe according to whether we |
16342 | * have active connectors/encoders. */ | |
842e0307 | 16343 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16344 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16345 | |
a3ed6aad | 16346 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
16347 | /* |
16348 | * We start out with underrun reporting disabled to avoid races. | |
16349 | * For correct bookkeeping mark this on active crtcs. | |
16350 | * | |
c5ab3bc0 DV |
16351 | * Also on gmch platforms we dont have any hardware bits to |
16352 | * disable the underrun reporting. Which means we need to start | |
16353 | * out with underrun reporting disabled also on inactive pipes, | |
16354 | * since otherwise we'll complain about the garbage we read when | |
16355 | * e.g. coming up after runtime pm. | |
16356 | * | |
4cc31489 DV |
16357 | * No protection against concurrent access is required - at |
16358 | * worst a fifo underrun happens which also sets this to false. | |
16359 | */ | |
16360 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16361 | /* |
16362 | * We track the PCH trancoder underrun reporting state | |
16363 | * within the crtc. With crtc for pipe A housing the underrun | |
16364 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16365 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16366 | * and marking underrun reporting as disabled for the non-existing | |
16367 | * PCH transcoders B and C would prevent enabling the south | |
16368 | * error interrupt (see cpt_can_enable_serr_int()). | |
16369 | */ | |
16370 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16371 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16372 | } |
24929352 DV |
16373 | } |
16374 | ||
16375 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16376 | { | |
16377 | struct intel_connector *connector; | |
16378 | struct drm_device *dev = encoder->base.dev; | |
16379 | ||
16380 | /* We need to check both for a crtc link (meaning that the | |
16381 | * encoder is active and trying to read from a pipe) and the | |
16382 | * pipe itself being active. */ | |
16383 | bool has_active_crtc = encoder->base.crtc && | |
16384 | to_intel_crtc(encoder->base.crtc)->active; | |
16385 | ||
dd756198 | 16386 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
16387 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16388 | encoder->base.base.id, | |
8e329a03 | 16389 | encoder->base.name); |
24929352 DV |
16390 | |
16391 | /* Connector is active, but has no active pipe. This is | |
16392 | * fallout from our resume register restoring. Disable | |
16393 | * the encoder manually again. */ | |
16394 | if (encoder->base.crtc) { | |
16395 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
16396 | encoder->base.base.id, | |
8e329a03 | 16397 | encoder->base.name); |
24929352 | 16398 | encoder->disable(encoder); |
a62d1497 VS |
16399 | if (encoder->post_disable) |
16400 | encoder->post_disable(encoder); | |
24929352 | 16401 | } |
7f1950fb | 16402 | encoder->base.crtc = NULL; |
24929352 DV |
16403 | |
16404 | /* Inconsistent output/port/pipe state happens presumably due to | |
16405 | * a bug in one of the get_hw_state functions. Or someplace else | |
16406 | * in our code, like the register restore mess on resume. Clamp | |
16407 | * things to off as a safer default. */ | |
3a3371ff | 16408 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16409 | if (connector->encoder != encoder) |
16410 | continue; | |
7f1950fb EE |
16411 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
16412 | connector->base.encoder = NULL; | |
24929352 DV |
16413 | } |
16414 | } | |
16415 | /* Enabled encoders without active connectors will be fixed in | |
16416 | * the crtc fixup. */ | |
16417 | } | |
16418 | ||
04098753 | 16419 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 16420 | { |
fac5e23e | 16421 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 16422 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 16423 | |
04098753 ID |
16424 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16425 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
16426 | i915_disable_vga(dev); | |
16427 | } | |
16428 | } | |
16429 | ||
16430 | void i915_redisable_vga(struct drm_device *dev) | |
16431 | { | |
fac5e23e | 16432 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 16433 | |
8dc8a27c PZ |
16434 | /* This function can be called both from intel_modeset_setup_hw_state or |
16435 | * at a very early point in our resume sequence, where the power well | |
16436 | * structures are not yet restored. Since this function is at a very | |
16437 | * paranoid "someone might have enabled VGA while we were not looking" | |
16438 | * level, just check if the power well is enabled instead of trying to | |
16439 | * follow the "don't touch the power well if we don't need it" policy | |
16440 | * the rest of the driver uses. */ | |
6392f847 | 16441 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16442 | return; |
16443 | ||
04098753 | 16444 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
16445 | |
16446 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16447 | } |
16448 | ||
f9cd7b88 | 16449 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16450 | { |
f9cd7b88 | 16451 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16452 | |
f9cd7b88 | 16453 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16454 | } |
16455 | ||
f9cd7b88 VS |
16456 | /* FIXME read out full plane state for all planes */ |
16457 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16458 | { |
b26d3ea3 | 16459 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16460 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16461 | to_intel_plane_state(primary->state); |
d032ffa0 | 16462 | |
936e71e3 | 16463 | plane_state->base.visible = crtc->active && |
b26d3ea3 ML |
16464 | primary_get_hw_state(to_intel_plane(primary)); |
16465 | ||
936e71e3 | 16466 | if (plane_state->base.visible) |
b26d3ea3 | 16467 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
98ec7739 VS |
16468 | } |
16469 | ||
30e984df | 16470 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16471 | { |
fac5e23e | 16472 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16473 | enum pipe pipe; |
24929352 DV |
16474 | struct intel_crtc *crtc; |
16475 | struct intel_encoder *encoder; | |
16476 | struct intel_connector *connector; | |
5358901f | 16477 | int i; |
24929352 | 16478 | |
565602d7 ML |
16479 | dev_priv->active_crtcs = 0; |
16480 | ||
d3fcc808 | 16481 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16482 | struct intel_crtc_state *crtc_state = crtc->config; |
16483 | int pixclk = 0; | |
3b117c8f | 16484 | |
ec2dc6a0 | 16485 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16486 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16487 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16488 | |
565602d7 ML |
16489 | crtc_state->base.active = crtc_state->base.enable = |
16490 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16491 | ||
16492 | crtc->base.enabled = crtc_state->base.enable; | |
16493 | crtc->active = crtc_state->base.active; | |
16494 | ||
16495 | if (crtc_state->base.active) { | |
16496 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16497 | ||
c89e39f3 | 16498 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16499 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16500 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16501 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16502 | else | |
16503 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16504 | |
16505 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16506 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16507 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16508 | } |
16509 | ||
16510 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16511 | |
f9cd7b88 | 16512 | readout_plane_state(crtc); |
24929352 | 16513 | |
78108b7c VS |
16514 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16515 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
16516 | crtc->active ? "enabled" : "disabled"); |
16517 | } | |
16518 | ||
5358901f DV |
16519 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16520 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16521 | ||
2edd6443 ACO |
16522 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16523 | &pll->config.hw_state); | |
3e369b76 | 16524 | pll->config.crtc_mask = 0; |
d3fcc808 | 16525 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16526 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16527 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16528 | } |
2dd66ebd | 16529 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16530 | |
1e6f2ddc | 16531 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16532 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16533 | } |
16534 | ||
b2784e15 | 16535 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16536 | pipe = 0; |
16537 | ||
16538 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16539 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16540 | encoder->base.crtc = &crtc->base; | |
253c84c8 | 16541 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16542 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16543 | } else { |
16544 | encoder->base.crtc = NULL; | |
16545 | } | |
16546 | ||
6f2bcceb | 16547 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16548 | encoder->base.base.id, |
8e329a03 | 16549 | encoder->base.name, |
24929352 | 16550 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16551 | pipe_name(pipe)); |
24929352 DV |
16552 | } |
16553 | ||
3a3371ff | 16554 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16555 | if (connector->get_hw_state(connector)) { |
16556 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16557 | |
16558 | encoder = connector->encoder; | |
16559 | connector->base.encoder = &encoder->base; | |
16560 | ||
16561 | if (encoder->base.crtc && | |
16562 | encoder->base.crtc->state->active) { | |
16563 | /* | |
16564 | * This has to be done during hardware readout | |
16565 | * because anything calling .crtc_disable may | |
16566 | * rely on the connector_mask being accurate. | |
16567 | */ | |
16568 | encoder->base.crtc->state->connector_mask |= | |
16569 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16570 | encoder->base.crtc->state->encoder_mask |= |
16571 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16572 | } |
16573 | ||
24929352 DV |
16574 | } else { |
16575 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16576 | connector->base.encoder = NULL; | |
16577 | } | |
16578 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16579 | connector->base.base.id, | |
c23cc417 | 16580 | connector->base.name, |
24929352 DV |
16581 | connector->base.encoder ? "enabled" : "disabled"); |
16582 | } | |
7f4c6284 VS |
16583 | |
16584 | for_each_intel_crtc(dev, crtc) { | |
16585 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16586 | ||
16587 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16588 | if (crtc->base.state->active) { | |
16589 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16590 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16591 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16592 | ||
16593 | /* | |
16594 | * The initial mode needs to be set in order to keep | |
16595 | * the atomic core happy. It wants a valid mode if the | |
16596 | * crtc's enabled, so we do the above call. | |
16597 | * | |
16598 | * At this point some state updated by the connectors | |
16599 | * in their ->detect() callback has not run yet, so | |
16600 | * no recalculation can be done yet. | |
16601 | * | |
16602 | * Even if we could do a recalculation and modeset | |
16603 | * right now it would cause a double modeset if | |
16604 | * fbdev or userspace chooses a different initial mode. | |
16605 | * | |
16606 | * If that happens, someone indicated they wanted a | |
16607 | * mode change, which means it's safe to do a full | |
16608 | * recalculation. | |
16609 | */ | |
16610 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16611 | |
16612 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16613 | update_scanline_offset(crtc); | |
7f4c6284 | 16614 | } |
e3b247da VS |
16615 | |
16616 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16617 | } |
30e984df DV |
16618 | } |
16619 | ||
043e9bda ML |
16620 | /* Scan out the current hw modeset state, |
16621 | * and sanitizes it to the current state | |
16622 | */ | |
16623 | static void | |
16624 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16625 | { |
fac5e23e | 16626 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16627 | enum pipe pipe; |
30e984df DV |
16628 | struct intel_crtc *crtc; |
16629 | struct intel_encoder *encoder; | |
35c95375 | 16630 | int i; |
30e984df DV |
16631 | |
16632 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16633 | |
16634 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16635 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16636 | intel_sanitize_encoder(encoder); |
16637 | } | |
16638 | ||
055e393f | 16639 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16640 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16641 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16642 | intel_dump_pipe_config(crtc, crtc->config, |
16643 | "[setup_hw_state]"); | |
24929352 | 16644 | } |
9a935856 | 16645 | |
d29b2f9d ACO |
16646 | intel_modeset_update_connector_atomic_state(dev); |
16647 | ||
35c95375 DV |
16648 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16649 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16650 | ||
2dd66ebd | 16651 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16652 | continue; |
16653 | ||
16654 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16655 | ||
2edd6443 | 16656 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16657 | pll->on = false; |
16658 | } | |
16659 | ||
666a4537 | 16660 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16661 | vlv_wm_get_hw_state(dev); |
16662 | else if (IS_GEN9(dev)) | |
3078999f PB |
16663 | skl_wm_get_hw_state(dev); |
16664 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16665 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16666 | |
16667 | for_each_intel_crtc(dev, crtc) { | |
16668 | unsigned long put_domains; | |
16669 | ||
74bff5f9 | 16670 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16671 | if (WARN_ON(put_domains)) |
16672 | modeset_put_power_domains(dev_priv, put_domains); | |
16673 | } | |
16674 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16675 | |
16676 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16677 | } |
7d0bc1ea | 16678 | |
043e9bda ML |
16679 | void intel_display_resume(struct drm_device *dev) |
16680 | { | |
e2c8b870 ML |
16681 | struct drm_i915_private *dev_priv = to_i915(dev); |
16682 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16683 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16684 | int ret; |
f30da187 | 16685 | |
e2c8b870 | 16686 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
16687 | if (state) |
16688 | state->acquire_ctx = &ctx; | |
043e9bda | 16689 | |
ea49c9ac ML |
16690 | /* |
16691 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16692 | * won't be taken. Unfortunately some probed state like | |
16693 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16694 | * it here for now. | |
16695 | */ | |
16696 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16697 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16698 | |
73974893 ML |
16699 | while (1) { |
16700 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
16701 | if (ret != -EDEADLK) | |
16702 | break; | |
043e9bda | 16703 | |
e2c8b870 | 16704 | drm_modeset_backoff(&ctx); |
e2c8b870 | 16705 | } |
043e9bda | 16706 | |
73974893 ML |
16707 | if (!ret) |
16708 | ret = __intel_display_resume(dev, state); | |
16709 | ||
e2c8b870 ML |
16710 | drm_modeset_drop_locks(&ctx); |
16711 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16712 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16713 | |
e2c8b870 ML |
16714 | if (ret) { |
16715 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16716 | drm_atomic_state_free(state); | |
16717 | } | |
2c7111db CW |
16718 | } |
16719 | ||
16720 | void intel_modeset_gem_init(struct drm_device *dev) | |
16721 | { | |
dc97997a | 16722 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 16723 | struct drm_crtc *c; |
2ff8fde1 | 16724 | struct drm_i915_gem_object *obj; |
484b41dd | 16725 | |
dc97997a | 16726 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16727 | |
1833b134 | 16728 | intel_modeset_init_hw(dev); |
02e792fb | 16729 | |
1ee8da6d | 16730 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16731 | |
16732 | /* | |
16733 | * Make sure any fbs we allocated at startup are properly | |
16734 | * pinned & fenced. When we do the allocation it's too early | |
16735 | * for this. | |
16736 | */ | |
70e1e0ec | 16737 | for_each_crtc(dev, c) { |
058d88c4 CW |
16738 | struct i915_vma *vma; |
16739 | ||
2ff8fde1 MR |
16740 | obj = intel_fb_obj(c->primary->fb); |
16741 | if (obj == NULL) | |
484b41dd JB |
16742 | continue; |
16743 | ||
e0d6149b | 16744 | mutex_lock(&dev->struct_mutex); |
058d88c4 | 16745 | vma = intel_pin_and_fence_fb_obj(c->primary->fb, |
3465c580 | 16746 | c->primary->state->rotation); |
e0d6149b | 16747 | mutex_unlock(&dev->struct_mutex); |
058d88c4 | 16748 | if (IS_ERR(vma)) { |
484b41dd JB |
16749 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16750 | to_intel_crtc(c)->pipe); | |
66e514c1 | 16751 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 16752 | c->primary->fb = NULL; |
36750f28 | 16753 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 16754 | update_state_fb(c->primary); |
36750f28 | 16755 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16756 | } |
16757 | } | |
1ebaa0b9 CW |
16758 | } |
16759 | ||
16760 | int intel_connector_register(struct drm_connector *connector) | |
16761 | { | |
16762 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
16763 | int ret; | |
16764 | ||
16765 | ret = intel_backlight_device_register(intel_connector); | |
16766 | if (ret) | |
16767 | goto err; | |
16768 | ||
16769 | return 0; | |
0962c3c9 | 16770 | |
1ebaa0b9 CW |
16771 | err: |
16772 | return ret; | |
79e53945 JB |
16773 | } |
16774 | ||
c191eca1 | 16775 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 16776 | { |
e63d87c0 | 16777 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 16778 | |
e63d87c0 | 16779 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 16780 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
16781 | } |
16782 | ||
79e53945 JB |
16783 | void intel_modeset_cleanup(struct drm_device *dev) |
16784 | { | |
fac5e23e | 16785 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 16786 | |
dc97997a | 16787 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16788 | |
fd0c0642 DV |
16789 | /* |
16790 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16791 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16792 | * experience fancy races otherwise. |
16793 | */ | |
2aeb7d3a | 16794 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16795 | |
fd0c0642 DV |
16796 | /* |
16797 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16798 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16799 | */ | |
f87ea761 | 16800 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16801 | |
723bfd70 JB |
16802 | intel_unregister_dsm_handler(); |
16803 | ||
c937ab3e | 16804 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16805 | |
1630fe75 CW |
16806 | /* flush any delayed tasks or pending work */ |
16807 | flush_scheduled_work(); | |
16808 | ||
79e53945 | 16809 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16810 | |
1ee8da6d | 16811 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16812 | |
dc97997a | 16813 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16814 | |
16815 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16816 | } |
16817 | ||
df0e9248 CW |
16818 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16819 | struct intel_encoder *encoder) | |
16820 | { | |
16821 | connector->encoder = encoder; | |
16822 | drm_mode_connector_attach_encoder(&connector->base, | |
16823 | &encoder->base); | |
79e53945 | 16824 | } |
28d52043 DA |
16825 | |
16826 | /* | |
16827 | * set vga decode state - true == enable VGA decode | |
16828 | */ | |
16829 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16830 | { | |
fac5e23e | 16831 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 16832 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16833 | u16 gmch_ctrl; |
16834 | ||
75fa041d CW |
16835 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16836 | DRM_ERROR("failed to read control word\n"); | |
16837 | return -EIO; | |
16838 | } | |
16839 | ||
c0cc8a55 CW |
16840 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16841 | return 0; | |
16842 | ||
28d52043 DA |
16843 | if (state) |
16844 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16845 | else | |
16846 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16847 | |
16848 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16849 | DRM_ERROR("failed to write control word\n"); | |
16850 | return -EIO; | |
16851 | } | |
16852 | ||
28d52043 DA |
16853 | return 0; |
16854 | } | |
c4a1d9e4 | 16855 | |
c4a1d9e4 | 16856 | struct intel_display_error_state { |
ff57f1b0 PZ |
16857 | |
16858 | u32 power_well_driver; | |
16859 | ||
63b66e5b CW |
16860 | int num_transcoders; |
16861 | ||
c4a1d9e4 CW |
16862 | struct intel_cursor_error_state { |
16863 | u32 control; | |
16864 | u32 position; | |
16865 | u32 base; | |
16866 | u32 size; | |
52331309 | 16867 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16868 | |
16869 | struct intel_pipe_error_state { | |
ddf9c536 | 16870 | bool power_domain_on; |
c4a1d9e4 | 16871 | u32 source; |
f301b1e1 | 16872 | u32 stat; |
52331309 | 16873 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16874 | |
16875 | struct intel_plane_error_state { | |
16876 | u32 control; | |
16877 | u32 stride; | |
16878 | u32 size; | |
16879 | u32 pos; | |
16880 | u32 addr; | |
16881 | u32 surface; | |
16882 | u32 tile_offset; | |
52331309 | 16883 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16884 | |
16885 | struct intel_transcoder_error_state { | |
ddf9c536 | 16886 | bool power_domain_on; |
63b66e5b CW |
16887 | enum transcoder cpu_transcoder; |
16888 | ||
16889 | u32 conf; | |
16890 | ||
16891 | u32 htotal; | |
16892 | u32 hblank; | |
16893 | u32 hsync; | |
16894 | u32 vtotal; | |
16895 | u32 vblank; | |
16896 | u32 vsync; | |
16897 | } transcoder[4]; | |
c4a1d9e4 CW |
16898 | }; |
16899 | ||
16900 | struct intel_display_error_state * | |
c033666a | 16901 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16902 | { |
c4a1d9e4 | 16903 | struct intel_display_error_state *error; |
63b66e5b CW |
16904 | int transcoders[] = { |
16905 | TRANSCODER_A, | |
16906 | TRANSCODER_B, | |
16907 | TRANSCODER_C, | |
16908 | TRANSCODER_EDP, | |
16909 | }; | |
c4a1d9e4 CW |
16910 | int i; |
16911 | ||
c033666a | 16912 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16913 | return NULL; |
16914 | ||
9d1cb914 | 16915 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16916 | if (error == NULL) |
16917 | return NULL; | |
16918 | ||
c033666a | 16919 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16920 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16921 | ||
055e393f | 16922 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16923 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16924 | __intel_display_power_is_enabled(dev_priv, |
16925 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16926 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16927 | continue; |
16928 | ||
5efb3e28 VS |
16929 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16930 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16931 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16932 | |
16933 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16934 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16935 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16936 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16937 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16938 | } | |
c033666a | 16939 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16940 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16941 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16942 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16943 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16944 | } | |
16945 | ||
c4a1d9e4 | 16946 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16947 | |
c033666a | 16948 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16949 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16950 | } |
16951 | ||
4d1de975 | 16952 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16953 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16954 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16955 | error->num_transcoders++; /* Account for eDP. */ |
16956 | ||
16957 | for (i = 0; i < error->num_transcoders; i++) { | |
16958 | enum transcoder cpu_transcoder = transcoders[i]; | |
16959 | ||
ddf9c536 | 16960 | error->transcoder[i].power_domain_on = |
f458ebbc | 16961 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16962 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16963 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16964 | continue; |
16965 | ||
63b66e5b CW |
16966 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16967 | ||
16968 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16969 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16970 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16971 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16972 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16973 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16974 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16975 | } |
16976 | ||
16977 | return error; | |
16978 | } | |
16979 | ||
edc3d884 MK |
16980 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16981 | ||
c4a1d9e4 | 16982 | void |
edc3d884 | 16983 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16984 | struct drm_device *dev, |
16985 | struct intel_display_error_state *error) | |
16986 | { | |
fac5e23e | 16987 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
16988 | int i; |
16989 | ||
63b66e5b CW |
16990 | if (!error) |
16991 | return; | |
16992 | ||
edc3d884 | 16993 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16994 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16995 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16996 | error->power_well_driver); |
055e393f | 16997 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16998 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16999 | err_printf(m, " Power: %s\n", |
87ad3212 | 17000 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 17001 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 17002 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
17003 | |
17004 | err_printf(m, "Plane [%d]:\n", i); | |
17005 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
17006 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 17007 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
17008 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
17009 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 17010 | } |
4b71a570 | 17011 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 17012 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 17013 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
17014 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
17015 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
17016 | } |
17017 | ||
edc3d884 MK |
17018 | err_printf(m, "Cursor [%d]:\n", i); |
17019 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
17020 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
17021 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 17022 | } |
63b66e5b CW |
17023 | |
17024 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 17025 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 17026 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 17027 | err_printf(m, " Power: %s\n", |
87ad3212 | 17028 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
17029 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
17030 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
17031 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
17032 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
17033 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
17034 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
17035 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
17036 | } | |
c4a1d9e4 | 17037 | } |