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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
c37efb99 | 39 | #include "i915_gem_dmabuf.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
118 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 125 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 126 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 127 | |
d4906093 | 128 | struct intel_limit { |
4c5def93 ACO |
129 | struct { |
130 | int min, max; | |
131 | } dot, vco, n, m, m1, m2, p, p1; | |
132 | ||
133 | struct { | |
134 | int dot_limit; | |
135 | int p2_slow, p2_fast; | |
136 | } p2; | |
d4906093 | 137 | }; |
79e53945 | 138 | |
bfa7df01 VS |
139 | /* returns HPLL frequency in kHz */ |
140 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
141 | { | |
142 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
143 | ||
144 | /* Obtain SKU information */ | |
145 | mutex_lock(&dev_priv->sb_lock); | |
146 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
147 | CCK_FUSE_HPLL_FREQ_MASK; | |
148 | mutex_unlock(&dev_priv->sb_lock); | |
149 | ||
150 | return vco_freq[hpll_freq] * 1000; | |
151 | } | |
152 | ||
c30fec65 VS |
153 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
154 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
155 | { |
156 | u32 val; | |
157 | int divider; | |
158 | ||
bfa7df01 VS |
159 | mutex_lock(&dev_priv->sb_lock); |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
c30fec65 VS |
169 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
170 | } | |
171 | ||
172 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
173 | const char *name, u32 reg) | |
174 | { | |
175 | if (dev_priv->hpll_freq == 0) | |
176 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
177 | ||
178 | return vlv_get_cck_clock(dev_priv, name, reg, | |
179 | dev_priv->hpll_freq); | |
bfa7df01 VS |
180 | } |
181 | ||
e7dc33f3 VS |
182 | static int |
183 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 184 | { |
e7dc33f3 VS |
185 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
186 | } | |
d2acd215 | 187 | |
e7dc33f3 VS |
188 | static int |
189 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
190 | { | |
19ab4ed3 | 191 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
192 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
193 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
194 | } |
195 | ||
e7dc33f3 VS |
196 | static int |
197 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 198 | { |
79e50a4f JN |
199 | uint32_t clkcfg; |
200 | ||
e7dc33f3 | 201 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
202 | clkcfg = I915_READ(CLKCFG); |
203 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
204 | case CLKCFG_FSB_400: | |
e7dc33f3 | 205 | return 100000; |
79e50a4f | 206 | case CLKCFG_FSB_533: |
e7dc33f3 | 207 | return 133333; |
79e50a4f | 208 | case CLKCFG_FSB_667: |
e7dc33f3 | 209 | return 166667; |
79e50a4f | 210 | case CLKCFG_FSB_800: |
e7dc33f3 | 211 | return 200000; |
79e50a4f | 212 | case CLKCFG_FSB_1067: |
e7dc33f3 | 213 | return 266667; |
79e50a4f | 214 | case CLKCFG_FSB_1333: |
e7dc33f3 | 215 | return 333333; |
79e50a4f JN |
216 | /* these two are just a guess; one of them might be right */ |
217 | case CLKCFG_FSB_1600: | |
218 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 219 | return 400000; |
79e50a4f | 220 | default: |
e7dc33f3 | 221 | return 133333; |
79e50a4f JN |
222 | } |
223 | } | |
224 | ||
19ab4ed3 | 225 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
226 | { |
227 | if (HAS_PCH_SPLIT(dev_priv)) | |
228 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
229 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
230 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
231 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
232 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
233 | else | |
234 | return; /* no rawclk on other platforms, or no need to know it */ | |
235 | ||
236 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
237 | } | |
238 | ||
bfa7df01 VS |
239 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
240 | { | |
666a4537 | 241 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
242 | return; |
243 | ||
244 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
245 | CCK_CZ_CLOCK_CONTROL); | |
246 | ||
247 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
248 | } | |
249 | ||
021357ac | 250 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
251 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
252 | const struct intel_crtc_state *pipe_config) | |
021357ac | 253 | { |
21a727b3 VS |
254 | if (HAS_DDI(dev_priv)) |
255 | return pipe_config->port_clock; /* SPLL */ | |
256 | else if (IS_GEN5(dev_priv)) | |
257 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 258 | else |
21a727b3 | 259 | return 270000; |
021357ac CW |
260 | } |
261 | ||
1b6f4958 | 262 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
273 | }; |
274 | ||
1b6f4958 | 275 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 276 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 277 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 278 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
279 | .m = { .min = 96, .max = 140 }, |
280 | .m1 = { .min = 18, .max = 26 }, | |
281 | .m2 = { .min = 6, .max = 16 }, | |
282 | .p = { .min = 4, .max = 128 }, | |
283 | .p1 = { .min = 2, .max = 33 }, | |
284 | .p2 = { .dot_limit = 165000, | |
285 | .p2_slow = 4, .p2_fast = 4 }, | |
286 | }; | |
287 | ||
1b6f4958 | 288 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 289 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 290 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 291 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
292 | .m = { .min = 96, .max = 140 }, |
293 | .m1 = { .min = 18, .max = 26 }, | |
294 | .m2 = { .min = 6, .max = 16 }, | |
295 | .p = { .min = 4, .max = 128 }, | |
296 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 165000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 299 | }; |
273e27ca | 300 | |
1b6f4958 | 301 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
302 | .dot = { .min = 20000, .max = 400000 }, |
303 | .vco = { .min = 1400000, .max = 2800000 }, | |
304 | .n = { .min = 1, .max = 6 }, | |
305 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
306 | .m1 = { .min = 8, .max = 18 }, |
307 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
308 | .p = { .min = 5, .max = 80 }, |
309 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
310 | .p2 = { .dot_limit = 200000, |
311 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
312 | }; |
313 | ||
1b6f4958 | 314 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
315 | .dot = { .min = 20000, .max = 400000 }, |
316 | .vco = { .min = 1400000, .max = 2800000 }, | |
317 | .n = { .min = 1, .max = 6 }, | |
318 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
319 | .m1 = { .min = 8, .max = 18 }, |
320 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
321 | .p = { .min = 7, .max = 98 }, |
322 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
323 | .p2 = { .dot_limit = 112000, |
324 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
325 | }; |
326 | ||
273e27ca | 327 | |
1b6f4958 | 328 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 270000 }, |
330 | .vco = { .min = 1750000, .max = 3500000}, | |
331 | .n = { .min = 1, .max = 4 }, | |
332 | .m = { .min = 104, .max = 138 }, | |
333 | .m1 = { .min = 17, .max = 23 }, | |
334 | .m2 = { .min = 5, .max = 11 }, | |
335 | .p = { .min = 10, .max = 30 }, | |
336 | .p1 = { .min = 1, .max = 3}, | |
337 | .p2 = { .dot_limit = 270000, | |
338 | .p2_slow = 10, | |
339 | .p2_fast = 10 | |
044c7c41 | 340 | }, |
e4b36699 KP |
341 | }; |
342 | ||
1b6f4958 | 343 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
344 | .dot = { .min = 22000, .max = 400000 }, |
345 | .vco = { .min = 1750000, .max = 3500000}, | |
346 | .n = { .min = 1, .max = 4 }, | |
347 | .m = { .min = 104, .max = 138 }, | |
348 | .m1 = { .min = 16, .max = 23 }, | |
349 | .m2 = { .min = 5, .max = 11 }, | |
350 | .p = { .min = 5, .max = 80 }, | |
351 | .p1 = { .min = 1, .max = 8}, | |
352 | .p2 = { .dot_limit = 165000, | |
353 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
354 | }; |
355 | ||
1b6f4958 | 356 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
357 | .dot = { .min = 20000, .max = 115000 }, |
358 | .vco = { .min = 1750000, .max = 3500000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 104, .max = 138 }, | |
361 | .m1 = { .min = 17, .max = 23 }, | |
362 | .m2 = { .min = 5, .max = 11 }, | |
363 | .p = { .min = 28, .max = 112 }, | |
364 | .p1 = { .min = 2, .max = 8 }, | |
365 | .p2 = { .dot_limit = 0, | |
366 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 367 | }, |
e4b36699 KP |
368 | }; |
369 | ||
1b6f4958 | 370 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
371 | .dot = { .min = 80000, .max = 224000 }, |
372 | .vco = { .min = 1750000, .max = 3500000 }, | |
373 | .n = { .min = 1, .max = 3 }, | |
374 | .m = { .min = 104, .max = 138 }, | |
375 | .m1 = { .min = 17, .max = 23 }, | |
376 | .m2 = { .min = 5, .max = 11 }, | |
377 | .p = { .min = 14, .max = 42 }, | |
378 | .p1 = { .min = 2, .max = 6 }, | |
379 | .p2 = { .dot_limit = 0, | |
380 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 381 | }, |
e4b36699 KP |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
385 | .dot = { .min = 20000, .max = 400000}, |
386 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 387 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
388 | .n = { .min = 3, .max = 6 }, |
389 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 390 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
391 | .m1 = { .min = 0, .max = 0 }, |
392 | .m2 = { .min = 0, .max = 254 }, | |
393 | .p = { .min = 5, .max = 80 }, | |
394 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
395 | .p2 = { .dot_limit = 200000, |
396 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
397 | }; |
398 | ||
1b6f4958 | 399 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
400 | .dot = { .min = 20000, .max = 400000 }, |
401 | .vco = { .min = 1700000, .max = 3500000 }, | |
402 | .n = { .min = 3, .max = 6 }, | |
403 | .m = { .min = 2, .max = 256 }, | |
404 | .m1 = { .min = 0, .max = 0 }, | |
405 | .m2 = { .min = 0, .max = 254 }, | |
406 | .p = { .min = 7, .max = 112 }, | |
407 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
408 | .p2 = { .dot_limit = 112000, |
409 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
410 | }; |
411 | ||
273e27ca EA |
412 | /* Ironlake / Sandybridge |
413 | * | |
414 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
415 | * the range value for them is (actual_value - 2). | |
416 | */ | |
1b6f4958 | 417 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 5 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 5, .max = 80 }, | |
425 | .p1 = { .min = 1, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
428 | }; |
429 | ||
1b6f4958 | 430 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
431 | .dot = { .min = 25000, .max = 350000 }, |
432 | .vco = { .min = 1760000, .max = 3510000 }, | |
433 | .n = { .min = 1, .max = 3 }, | |
434 | .m = { .min = 79, .max = 118 }, | |
435 | .m1 = { .min = 12, .max = 22 }, | |
436 | .m2 = { .min = 5, .max = 9 }, | |
437 | .p = { .min = 28, .max = 112 }, | |
438 | .p1 = { .min = 2, .max = 8 }, | |
439 | .p2 = { .dot_limit = 225000, | |
440 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
441 | }; |
442 | ||
1b6f4958 | 443 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
444 | .dot = { .min = 25000, .max = 350000 }, |
445 | .vco = { .min = 1760000, .max = 3510000 }, | |
446 | .n = { .min = 1, .max = 3 }, | |
447 | .m = { .min = 79, .max = 127 }, | |
448 | .m1 = { .min = 12, .max = 22 }, | |
449 | .m2 = { .min = 5, .max = 9 }, | |
450 | .p = { .min = 14, .max = 56 }, | |
451 | .p1 = { .min = 2, .max = 8 }, | |
452 | .p2 = { .dot_limit = 225000, | |
453 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
454 | }; |
455 | ||
273e27ca | 456 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 457 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
458 | .dot = { .min = 25000, .max = 350000 }, |
459 | .vco = { .min = 1760000, .max = 3510000 }, | |
460 | .n = { .min = 1, .max = 2 }, | |
461 | .m = { .min = 79, .max = 126 }, | |
462 | .m1 = { .min = 12, .max = 22 }, | |
463 | .m2 = { .min = 5, .max = 9 }, | |
464 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 465 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
466 | .p2 = { .dot_limit = 225000, |
467 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
468 | }; |
469 | ||
1b6f4958 | 470 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
471 | .dot = { .min = 25000, .max = 350000 }, |
472 | .vco = { .min = 1760000, .max = 3510000 }, | |
473 | .n = { .min = 1, .max = 3 }, | |
474 | .m = { .min = 79, .max = 126 }, | |
475 | .m1 = { .min = 12, .max = 22 }, | |
476 | .m2 = { .min = 5, .max = 9 }, | |
477 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 478 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
479 | .p2 = { .dot_limit = 225000, |
480 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
481 | }; |
482 | ||
1b6f4958 | 483 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
484 | /* |
485 | * These are the data rate limits (measured in fast clocks) | |
486 | * since those are the strictest limits we have. The fast | |
487 | * clock and actual rate limits are more relaxed, so checking | |
488 | * them would make no difference. | |
489 | */ | |
490 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 491 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 492 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
493 | .m1 = { .min = 2, .max = 3 }, |
494 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 495 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 496 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
497 | }; |
498 | ||
1b6f4958 | 499 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
500 | /* |
501 | * These are the data rate limits (measured in fast clocks) | |
502 | * since those are the strictest limits we have. The fast | |
503 | * clock and actual rate limits are more relaxed, so checking | |
504 | * them would make no difference. | |
505 | */ | |
506 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 507 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
508 | .n = { .min = 1, .max = 1 }, |
509 | .m1 = { .min = 2, .max = 2 }, | |
510 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
511 | .p1 = { .min = 2, .max = 4 }, | |
512 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
513 | }; | |
514 | ||
1b6f4958 | 515 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
516 | /* FIXME: find real dot limits */ |
517 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 518 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
519 | .n = { .min = 1, .max = 1 }, |
520 | .m1 = { .min = 2, .max = 2 }, | |
521 | /* FIXME: find real m2 limits */ | |
522 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
523 | .p1 = { .min = 2, .max = 4 }, | |
524 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
525 | }; | |
526 | ||
cdba954e ACO |
527 | static bool |
528 | needs_modeset(struct drm_crtc_state *state) | |
529 | { | |
fc596660 | 530 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
531 | } |
532 | ||
dccbea3b ID |
533 | /* |
534 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
535 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
536 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
537 | * The helpers' return value is the rate of the clock that is fed to the | |
538 | * display engine's pipe which can be the above fast dot clock rate or a | |
539 | * divided-down version of it. | |
540 | */ | |
f2b115e6 | 541 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 542 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 543 | { |
2177832f SL |
544 | clock->m = clock->m2 + 2; |
545 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 546 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 547 | return 0; |
fb03ac01 VS |
548 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
549 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
550 | |
551 | return clock->dot; | |
2177832f SL |
552 | } |
553 | ||
7429e9d4 DV |
554 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
555 | { | |
556 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
557 | } | |
558 | ||
9e2c8475 | 559 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 560 | { |
7429e9d4 | 561 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 562 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 563 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 564 | return 0; |
fb03ac01 VS |
565 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
566 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
567 | |
568 | return clock->dot; | |
79e53945 JB |
569 | } |
570 | ||
9e2c8475 | 571 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
572 | { |
573 | clock->m = clock->m1 * clock->m2; | |
574 | clock->p = clock->p1 * clock->p2; | |
575 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 576 | return 0; |
589eca67 ID |
577 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
578 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
579 | |
580 | return clock->dot / 5; | |
589eca67 ID |
581 | } |
582 | ||
9e2c8475 | 583 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
584 | { |
585 | clock->m = clock->m1 * clock->m2; | |
586 | clock->p = clock->p1 * clock->p2; | |
587 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 588 | return 0; |
ef9348c8 CML |
589 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
590 | clock->n << 22); | |
591 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
592 | |
593 | return clock->dot / 5; | |
ef9348c8 CML |
594 | } |
595 | ||
7c04d1d9 | 596 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
597 | /** |
598 | * Returns whether the given set of divisors are valid for a given refclk with | |
599 | * the given connectors. | |
600 | */ | |
601 | ||
1b894b59 | 602 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 603 | const struct intel_limit *limit, |
9e2c8475 | 604 | const struct dpll *clock) |
79e53945 | 605 | { |
f01b7962 VS |
606 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
607 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 608 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 609 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 610 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 611 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 612 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 613 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 614 | |
666a4537 WB |
615 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
616 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
617 | if (clock->m1 <= clock->m2) |
618 | INTELPllInvalid("m1 <= m2\n"); | |
619 | ||
666a4537 | 620 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
621 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
622 | INTELPllInvalid("p out of range\n"); | |
623 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
624 | INTELPllInvalid("m out of range\n"); | |
625 | } | |
626 | ||
79e53945 | 627 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 628 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
629 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
630 | * connector, etc., rather than just a single range. | |
631 | */ | |
632 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 633 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
634 | |
635 | return true; | |
636 | } | |
637 | ||
3b1429d9 | 638 | static int |
1b6f4958 | 639 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
640 | const struct intel_crtc_state *crtc_state, |
641 | int target) | |
79e53945 | 642 | { |
3b1429d9 | 643 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 644 | |
2d84d2b3 | 645 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 646 | /* |
a210b028 DV |
647 | * For LVDS just rely on its current settings for dual-channel. |
648 | * We haven't figured out how to reliably set up different | |
649 | * single/dual channel state, if we even can. | |
79e53945 | 650 | */ |
1974cad0 | 651 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 652 | return limit->p2.p2_fast; |
79e53945 | 653 | else |
3b1429d9 | 654 | return limit->p2.p2_slow; |
79e53945 JB |
655 | } else { |
656 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 657 | return limit->p2.p2_slow; |
79e53945 | 658 | else |
3b1429d9 | 659 | return limit->p2.p2_fast; |
79e53945 | 660 | } |
3b1429d9 VS |
661 | } |
662 | ||
70e8aa21 ACO |
663 | /* |
664 | * Returns a set of divisors for the desired target clock with the given | |
665 | * refclk, or FALSE. The returned values represent the clock equation: | |
666 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
667 | * | |
668 | * Target and reference clocks are specified in kHz. | |
669 | * | |
670 | * If match_clock is provided, then best_clock P divider must match the P | |
671 | * divider from @match_clock used for LVDS downclocking. | |
672 | */ | |
3b1429d9 | 673 | static bool |
1b6f4958 | 674 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 675 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
676 | int target, int refclk, struct dpll *match_clock, |
677 | struct dpll *best_clock) | |
3b1429d9 VS |
678 | { |
679 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 680 | struct dpll clock; |
3b1429d9 | 681 | int err = target; |
79e53945 | 682 | |
0206e353 | 683 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 684 | |
3b1429d9 VS |
685 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
686 | ||
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 691 | if (clock.m2 >= clock.m1) |
42158660 ZY |
692 | break; |
693 | for (clock.n = limit->n.min; | |
694 | clock.n <= limit->n.max; clock.n++) { | |
695 | for (clock.p1 = limit->p1.min; | |
696 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
697 | int this_err; |
698 | ||
dccbea3b | 699 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
700 | if (!intel_PLL_is_valid(dev, limit, |
701 | &clock)) | |
702 | continue; | |
703 | if (match_clock && | |
704 | clock.p != match_clock->p) | |
705 | continue; | |
706 | ||
707 | this_err = abs(clock.dot - target); | |
708 | if (this_err < err) { | |
709 | *best_clock = clock; | |
710 | err = this_err; | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | ||
717 | return (err != target); | |
718 | } | |
719 | ||
70e8aa21 ACO |
720 | /* |
721 | * Returns a set of divisors for the desired target clock with the given | |
722 | * refclk, or FALSE. The returned values represent the clock equation: | |
723 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
724 | * | |
725 | * Target and reference clocks are specified in kHz. | |
726 | * | |
727 | * If match_clock is provided, then best_clock P divider must match the P | |
728 | * divider from @match_clock used for LVDS downclocking. | |
729 | */ | |
ac58c3f0 | 730 | static bool |
1b6f4958 | 731 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 732 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
733 | int target, int refclk, struct dpll *match_clock, |
734 | struct dpll *best_clock) | |
79e53945 | 735 | { |
3b1429d9 | 736 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 737 | struct dpll clock; |
79e53945 JB |
738 | int err = target; |
739 | ||
0206e353 | 740 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 741 | |
3b1429d9 VS |
742 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
743 | ||
42158660 ZY |
744 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
745 | clock.m1++) { | |
746 | for (clock.m2 = limit->m2.min; | |
747 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
748 | for (clock.n = limit->n.min; |
749 | clock.n <= limit->n.max; clock.n++) { | |
750 | for (clock.p1 = limit->p1.min; | |
751 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
752 | int this_err; |
753 | ||
dccbea3b | 754 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
755 | if (!intel_PLL_is_valid(dev, limit, |
756 | &clock)) | |
79e53945 | 757 | continue; |
cec2f356 SP |
758 | if (match_clock && |
759 | clock.p != match_clock->p) | |
760 | continue; | |
79e53945 JB |
761 | |
762 | this_err = abs(clock.dot - target); | |
763 | if (this_err < err) { | |
764 | *best_clock = clock; | |
765 | err = this_err; | |
766 | } | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | ||
772 | return (err != target); | |
773 | } | |
774 | ||
997c030c ACO |
775 | /* |
776 | * Returns a set of divisors for the desired target clock with the given | |
777 | * refclk, or FALSE. The returned values represent the clock equation: | |
778 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
779 | * |
780 | * Target and reference clocks are specified in kHz. | |
781 | * | |
782 | * If match_clock is provided, then best_clock P divider must match the P | |
783 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 784 | */ |
d4906093 | 785 | static bool |
1b6f4958 | 786 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 787 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
788 | int target, int refclk, struct dpll *match_clock, |
789 | struct dpll *best_clock) | |
d4906093 | 790 | { |
3b1429d9 | 791 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 792 | struct dpll clock; |
d4906093 | 793 | int max_n; |
3b1429d9 | 794 | bool found = false; |
6ba770dc AJ |
795 | /* approximately equals target * 0.00585 */ |
796 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
797 | |
798 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
799 | |
800 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
801 | ||
d4906093 | 802 | max_n = limit->n.max; |
f77f13e2 | 803 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 804 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 805 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
806 | for (clock.m1 = limit->m1.max; |
807 | clock.m1 >= limit->m1.min; clock.m1--) { | |
808 | for (clock.m2 = limit->m2.max; | |
809 | clock.m2 >= limit->m2.min; clock.m2--) { | |
810 | for (clock.p1 = limit->p1.max; | |
811 | clock.p1 >= limit->p1.min; clock.p1--) { | |
812 | int this_err; | |
813 | ||
dccbea3b | 814 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
815 | if (!intel_PLL_is_valid(dev, limit, |
816 | &clock)) | |
d4906093 | 817 | continue; |
1b894b59 CW |
818 | |
819 | this_err = abs(clock.dot - target); | |
d4906093 ML |
820 | if (this_err < err_most) { |
821 | *best_clock = clock; | |
822 | err_most = this_err; | |
823 | max_n = clock.n; | |
824 | found = true; | |
825 | } | |
826 | } | |
827 | } | |
828 | } | |
829 | } | |
2c07245f ZW |
830 | return found; |
831 | } | |
832 | ||
d5dd62bd ID |
833 | /* |
834 | * Check if the calculated PLL configuration is more optimal compared to the | |
835 | * best configuration and error found so far. Return the calculated error. | |
836 | */ | |
837 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
838 | const struct dpll *calculated_clock, |
839 | const struct dpll *best_clock, | |
d5dd62bd ID |
840 | unsigned int best_error_ppm, |
841 | unsigned int *error_ppm) | |
842 | { | |
9ca3ba01 ID |
843 | /* |
844 | * For CHV ignore the error and consider only the P value. | |
845 | * Prefer a bigger P value based on HW requirements. | |
846 | */ | |
847 | if (IS_CHERRYVIEW(dev)) { | |
848 | *error_ppm = 0; | |
849 | ||
850 | return calculated_clock->p > best_clock->p; | |
851 | } | |
852 | ||
24be4e46 ID |
853 | if (WARN_ON_ONCE(!target_freq)) |
854 | return false; | |
855 | ||
d5dd62bd ID |
856 | *error_ppm = div_u64(1000000ULL * |
857 | abs(target_freq - calculated_clock->dot), | |
858 | target_freq); | |
859 | /* | |
860 | * Prefer a better P value over a better (smaller) error if the error | |
861 | * is small. Ensure this preference for future configurations too by | |
862 | * setting the error to 0. | |
863 | */ | |
864 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
865 | *error_ppm = 0; | |
866 | ||
867 | return true; | |
868 | } | |
869 | ||
870 | return *error_ppm + 10 < best_error_ppm; | |
871 | } | |
872 | ||
65b3d6a9 ACO |
873 | /* |
874 | * Returns a set of divisors for the desired target clock with the given | |
875 | * refclk, or FALSE. The returned values represent the clock equation: | |
876 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
877 | */ | |
a0c4da24 | 878 | static bool |
1b6f4958 | 879 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 880 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
881 | int target, int refclk, struct dpll *match_clock, |
882 | struct dpll *best_clock) | |
a0c4da24 | 883 | { |
a93e255f | 884 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 885 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 886 | struct dpll clock; |
69e4f900 | 887 | unsigned int bestppm = 1000000; |
27e639bf VS |
888 | /* min update 19.2 MHz */ |
889 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 890 | bool found = false; |
a0c4da24 | 891 | |
6b4bf1c4 VS |
892 | target *= 5; /* fast clock */ |
893 | ||
894 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
895 | |
896 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 897 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 898 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 899 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 900 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 901 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 902 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 903 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 904 | unsigned int ppm; |
69e4f900 | 905 | |
6b4bf1c4 VS |
906 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
907 | refclk * clock.m1); | |
908 | ||
dccbea3b | 909 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 910 | |
f01b7962 VS |
911 | if (!intel_PLL_is_valid(dev, limit, |
912 | &clock)) | |
43b0ac53 VS |
913 | continue; |
914 | ||
d5dd62bd ID |
915 | if (!vlv_PLL_is_optimal(dev, target, |
916 | &clock, | |
917 | best_clock, | |
918 | bestppm, &ppm)) | |
919 | continue; | |
6b4bf1c4 | 920 | |
d5dd62bd ID |
921 | *best_clock = clock; |
922 | bestppm = ppm; | |
923 | found = true; | |
a0c4da24 JB |
924 | } |
925 | } | |
926 | } | |
927 | } | |
a0c4da24 | 928 | |
49e497ef | 929 | return found; |
a0c4da24 | 930 | } |
a4fc5ed6 | 931 | |
65b3d6a9 ACO |
932 | /* |
933 | * Returns a set of divisors for the desired target clock with the given | |
934 | * refclk, or FALSE. The returned values represent the clock equation: | |
935 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
936 | */ | |
ef9348c8 | 937 | static bool |
1b6f4958 | 938 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 939 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
940 | int target, int refclk, struct dpll *match_clock, |
941 | struct dpll *best_clock) | |
ef9348c8 | 942 | { |
a93e255f | 943 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 944 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 945 | unsigned int best_error_ppm; |
9e2c8475 | 946 | struct dpll clock; |
ef9348c8 CML |
947 | uint64_t m2; |
948 | int found = false; | |
949 | ||
950 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 951 | best_error_ppm = 1000000; |
ef9348c8 CML |
952 | |
953 | /* | |
954 | * Based on hardware doc, the n always set to 1, and m1 always | |
955 | * set to 2. If requires to support 200Mhz refclk, we need to | |
956 | * revisit this because n may not 1 anymore. | |
957 | */ | |
958 | clock.n = 1, clock.m1 = 2; | |
959 | target *= 5; /* fast clock */ | |
960 | ||
961 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
962 | for (clock.p2 = limit->p2.p2_fast; | |
963 | clock.p2 >= limit->p2.p2_slow; | |
964 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 965 | unsigned int error_ppm; |
ef9348c8 CML |
966 | |
967 | clock.p = clock.p1 * clock.p2; | |
968 | ||
969 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
970 | clock.n) << 22, refclk * clock.m1); | |
971 | ||
972 | if (m2 > INT_MAX/clock.m1) | |
973 | continue; | |
974 | ||
975 | clock.m2 = m2; | |
976 | ||
dccbea3b | 977 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
978 | |
979 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
980 | continue; | |
981 | ||
9ca3ba01 ID |
982 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
983 | best_error_ppm, &error_ppm)) | |
984 | continue; | |
985 | ||
986 | *best_clock = clock; | |
987 | best_error_ppm = error_ppm; | |
988 | found = true; | |
ef9348c8 CML |
989 | } |
990 | } | |
991 | ||
992 | return found; | |
993 | } | |
994 | ||
5ab7b0b7 | 995 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 996 | struct dpll *best_clock) |
5ab7b0b7 | 997 | { |
65b3d6a9 | 998 | int refclk = 100000; |
1b6f4958 | 999 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1000 | |
65b3d6a9 | 1001 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1002 | target_clock, refclk, NULL, best_clock); |
1003 | } | |
1004 | ||
20ddf665 VS |
1005 | bool intel_crtc_active(struct drm_crtc *crtc) |
1006 | { | |
1007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1008 | ||
1009 | /* Be paranoid as we can arrive here with only partial | |
1010 | * state retrieved from the hardware during setup. | |
1011 | * | |
241bfc38 | 1012 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1013 | * as Haswell has gained clock readout/fastboot support. |
1014 | * | |
66e514c1 | 1015 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1016 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1017 | * |
1018 | * FIXME: The intel_crtc->active here should be switched to | |
1019 | * crtc->state->active once we have proper CRTC states wired up | |
1020 | * for atomic. | |
20ddf665 | 1021 | */ |
c3d1f436 | 1022 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1023 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1024 | } |
1025 | ||
a5c961d1 PZ |
1026 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1027 | enum pipe pipe) | |
1028 | { | |
1029 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1031 | ||
6e3c9717 | 1032 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1033 | } |
1034 | ||
fbf49ea2 VS |
1035 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1036 | { | |
fac5e23e | 1037 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1038 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1039 | u32 line1, line2; |
1040 | u32 line_mask; | |
1041 | ||
1042 | if (IS_GEN2(dev)) | |
1043 | line_mask = DSL_LINEMASK_GEN2; | |
1044 | else | |
1045 | line_mask = DSL_LINEMASK_GEN3; | |
1046 | ||
1047 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1048 | msleep(5); |
fbf49ea2 VS |
1049 | line2 = I915_READ(reg) & line_mask; |
1050 | ||
1051 | return line1 == line2; | |
1052 | } | |
1053 | ||
ab7ad7f6 KP |
1054 | /* |
1055 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1056 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1057 | * |
1058 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1059 | * spinning on the vblank interrupt status bit, since we won't actually | |
1060 | * see an interrupt when the pipe is disabled. | |
1061 | * | |
ab7ad7f6 KP |
1062 | * On Gen4 and above: |
1063 | * wait for the pipe register state bit to turn off | |
1064 | * | |
1065 | * Otherwise: | |
1066 | * wait for the display line value to settle (it usually | |
1067 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1068 | * |
9d0498a2 | 1069 | */ |
575f7ab7 | 1070 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1071 | { |
575f7ab7 | 1072 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1073 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1074 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1075 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1076 | |
1077 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1078 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1079 | |
1080 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1081 | if (intel_wait_for_register(dev_priv, |
1082 | reg, I965_PIPECONF_ACTIVE, 0, | |
1083 | 100)) | |
284637d9 | 1084 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1085 | } else { |
ab7ad7f6 | 1086 | /* Wait for the display line to settle */ |
fbf49ea2 | 1087 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1088 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1089 | } |
79e53945 JB |
1090 | } |
1091 | ||
b24e7179 | 1092 | /* Only for pre-ILK configs */ |
55607e8a DV |
1093 | void assert_pll(struct drm_i915_private *dev_priv, |
1094 | enum pipe pipe, bool state) | |
b24e7179 | 1095 | { |
b24e7179 JB |
1096 | u32 val; |
1097 | bool cur_state; | |
1098 | ||
649636ef | 1099 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1100 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1101 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1102 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1103 | onoff(state), onoff(cur_state)); |
b24e7179 | 1104 | } |
b24e7179 | 1105 | |
23538ef1 | 1106 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1107 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1108 | { |
1109 | u32 val; | |
1110 | bool cur_state; | |
1111 | ||
a580516d | 1112 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1113 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1114 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1115 | |
1116 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1117 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1118 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1119 | onoff(state), onoff(cur_state)); |
23538ef1 | 1120 | } |
23538ef1 | 1121 | |
040484af JB |
1122 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1123 | enum pipe pipe, bool state) | |
1124 | { | |
040484af | 1125 | bool cur_state; |
ad80a810 PZ |
1126 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1127 | pipe); | |
040484af | 1128 | |
2d1fe073 | 1129 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1130 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1131 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1132 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1133 | } else { |
649636ef | 1134 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1135 | cur_state = !!(val & FDI_TX_ENABLE); |
1136 | } | |
e2c719b7 | 1137 | I915_STATE_WARN(cur_state != state, |
040484af | 1138 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1139 | onoff(state), onoff(cur_state)); |
040484af JB |
1140 | } |
1141 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1142 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1143 | ||
1144 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1145 | enum pipe pipe, bool state) | |
1146 | { | |
040484af JB |
1147 | u32 val; |
1148 | bool cur_state; | |
1149 | ||
649636ef | 1150 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1151 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1152 | I915_STATE_WARN(cur_state != state, |
040484af | 1153 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1154 | onoff(state), onoff(cur_state)); |
040484af JB |
1155 | } |
1156 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1157 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1158 | ||
1159 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1160 | enum pipe pipe) | |
1161 | { | |
040484af JB |
1162 | u32 val; |
1163 | ||
1164 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1165 | if (IS_GEN5(dev_priv)) |
040484af JB |
1166 | return; |
1167 | ||
bf507ef7 | 1168 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1169 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1170 | return; |
1171 | ||
649636ef | 1172 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1173 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1174 | } |
1175 | ||
55607e8a DV |
1176 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1177 | enum pipe pipe, bool state) | |
040484af | 1178 | { |
040484af | 1179 | u32 val; |
55607e8a | 1180 | bool cur_state; |
040484af | 1181 | |
649636ef | 1182 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1183 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1184 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1185 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1186 | onoff(state), onoff(cur_state)); |
040484af JB |
1187 | } |
1188 | ||
b680c37a DV |
1189 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1190 | enum pipe pipe) | |
ea0760cf | 1191 | { |
91c8a326 | 1192 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 | 1193 | i915_reg_t pp_reg; |
ea0760cf JB |
1194 | u32 val; |
1195 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1196 | bool locked = true; |
ea0760cf | 1197 | |
bedd4dba JN |
1198 | if (WARN_ON(HAS_DDI(dev))) |
1199 | return; | |
1200 | ||
1201 | if (HAS_PCH_SPLIT(dev)) { | |
1202 | u32 port_sel; | |
1203 | ||
ea0760cf | 1204 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1205 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1206 | ||
1207 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1208 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1209 | panel_pipe = PIPE_B; | |
1210 | /* XXX: else fix for eDP */ | |
666a4537 | 1211 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1212 | /* presumably write lock depends on pipe, not port select */ |
1213 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1214 | panel_pipe = pipe; | |
ea0760cf JB |
1215 | } else { |
1216 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1217 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1218 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1219 | } |
1220 | ||
1221 | val = I915_READ(pp_reg); | |
1222 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1223 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1224 | locked = false; |
1225 | ||
e2c719b7 | 1226 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1227 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1228 | pipe_name(pipe)); |
ea0760cf JB |
1229 | } |
1230 | ||
93ce0ba6 JN |
1231 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe, bool state) | |
1233 | { | |
91c8a326 | 1234 | struct drm_device *dev = &dev_priv->drm; |
93ce0ba6 JN |
1235 | bool cur_state; |
1236 | ||
d9d82081 | 1237 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1238 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1239 | else |
5efb3e28 | 1240 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1241 | |
e2c719b7 | 1242 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1243 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1244 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1245 | } |
1246 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1247 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1248 | ||
b840d907 JB |
1249 | void assert_pipe(struct drm_i915_private *dev_priv, |
1250 | enum pipe pipe, bool state) | |
b24e7179 | 1251 | { |
63d7bbe9 | 1252 | bool cur_state; |
702e7a56 PZ |
1253 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1254 | pipe); | |
4feed0eb | 1255 | enum intel_display_power_domain power_domain; |
b24e7179 | 1256 | |
b6b5d049 VS |
1257 | /* if we need the pipe quirk it must be always on */ |
1258 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1259 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1260 | state = true; |
1261 | ||
4feed0eb ID |
1262 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1263 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1264 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1265 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1266 | |
1267 | intel_display_power_put(dev_priv, power_domain); | |
1268 | } else { | |
1269 | cur_state = false; | |
69310161 PZ |
1270 | } |
1271 | ||
e2c719b7 | 1272 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1273 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1274 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1275 | } |
1276 | ||
931872fc CW |
1277 | static void assert_plane(struct drm_i915_private *dev_priv, |
1278 | enum plane plane, bool state) | |
b24e7179 | 1279 | { |
b24e7179 | 1280 | u32 val; |
931872fc | 1281 | bool cur_state; |
b24e7179 | 1282 | |
649636ef | 1283 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1284 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1285 | I915_STATE_WARN(cur_state != state, |
931872fc | 1286 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1287 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1288 | } |
1289 | ||
931872fc CW |
1290 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1291 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1292 | ||
b24e7179 JB |
1293 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1294 | enum pipe pipe) | |
1295 | { | |
91c8a326 | 1296 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1297 | int i; |
b24e7179 | 1298 | |
653e1026 VS |
1299 | /* Primary planes are fixed to pipes on gen4+ */ |
1300 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1301 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1302 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1303 | "plane %c assertion failure, should be disabled but not\n", |
1304 | plane_name(pipe)); | |
19ec1358 | 1305 | return; |
28c05794 | 1306 | } |
19ec1358 | 1307 | |
b24e7179 | 1308 | /* Need to check both planes against the pipe */ |
055e393f | 1309 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1310 | u32 val = I915_READ(DSPCNTR(i)); |
1311 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1312 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1313 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1314 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1315 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1316 | } |
1317 | } | |
1318 | ||
19332d7a JB |
1319 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1320 | enum pipe pipe) | |
1321 | { | |
91c8a326 | 1322 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1323 | int sprite; |
19332d7a | 1324 | |
7feb8b88 | 1325 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1326 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1327 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1328 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1329 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1330 | sprite, pipe_name(pipe)); | |
1331 | } | |
666a4537 | 1332 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1333 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1334 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1335 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1336 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1337 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1338 | } |
1339 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1340 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1341 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1342 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1343 | plane_name(pipe), pipe_name(pipe)); |
1344 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1345 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1346 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1347 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1348 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1349 | } |
1350 | } | |
1351 | ||
08c71e5e VS |
1352 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1353 | { | |
e2c719b7 | 1354 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1355 | drm_crtc_vblank_put(crtc); |
1356 | } | |
1357 | ||
7abd4b35 ACO |
1358 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1359 | enum pipe pipe) | |
92f2584a | 1360 | { |
92f2584a JB |
1361 | u32 val; |
1362 | bool enabled; | |
1363 | ||
649636ef | 1364 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1365 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1366 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1367 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1368 | pipe_name(pipe)); | |
92f2584a JB |
1369 | } |
1370 | ||
4e634389 KP |
1371 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1372 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1373 | { |
1374 | if ((val & DP_PORT_EN) == 0) | |
1375 | return false; | |
1376 | ||
2d1fe073 | 1377 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1378 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1379 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1380 | return false; | |
2d1fe073 | 1381 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1382 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1383 | return false; | |
f0575e92 KP |
1384 | } else { |
1385 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1386 | return false; | |
1387 | } | |
1388 | return true; | |
1389 | } | |
1390 | ||
1519b995 KP |
1391 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1392 | enum pipe pipe, u32 val) | |
1393 | { | |
dc0fa718 | 1394 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1395 | return false; |
1396 | ||
2d1fe073 | 1397 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1398 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1399 | return false; |
2d1fe073 | 1400 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1401 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1402 | return false; | |
1519b995 | 1403 | } else { |
dc0fa718 | 1404 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1405 | return false; |
1406 | } | |
1407 | return true; | |
1408 | } | |
1409 | ||
1410 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1411 | enum pipe pipe, u32 val) | |
1412 | { | |
1413 | if ((val & LVDS_PORT_EN) == 0) | |
1414 | return false; | |
1415 | ||
2d1fe073 | 1416 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1417 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1418 | return false; | |
1419 | } else { | |
1420 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1421 | return false; | |
1422 | } | |
1423 | return true; | |
1424 | } | |
1425 | ||
1426 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1427 | enum pipe pipe, u32 val) | |
1428 | { | |
1429 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1430 | return false; | |
2d1fe073 | 1431 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1432 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1433 | return false; | |
1434 | } else { | |
1435 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1436 | return false; | |
1437 | } | |
1438 | return true; | |
1439 | } | |
1440 | ||
291906f1 | 1441 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1442 | enum pipe pipe, i915_reg_t reg, |
1443 | u32 port_sel) | |
291906f1 | 1444 | { |
47a05eca | 1445 | u32 val = I915_READ(reg); |
e2c719b7 | 1446 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1447 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1448 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1449 | |
2d1fe073 | 1450 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1451 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1452 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1453 | } |
1454 | ||
1455 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1456 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1457 | { |
47a05eca | 1458 | u32 val = I915_READ(reg); |
e2c719b7 | 1459 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1460 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1461 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1462 | |
2d1fe073 | 1463 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1464 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1465 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1466 | } |
1467 | ||
1468 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1469 | enum pipe pipe) | |
1470 | { | |
291906f1 | 1471 | u32 val; |
291906f1 | 1472 | |
f0575e92 KP |
1473 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1476 | |
649636ef | 1477 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1478 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 | 1481 | |
649636ef | 1482 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1483 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1484 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1485 | pipe_name(pipe)); |
291906f1 | 1486 | |
e2debe91 PZ |
1487 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1490 | } |
1491 | ||
cd2d34d9 VS |
1492 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1493 | const struct intel_crtc_state *pipe_config) | |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1496 | enum pipe pipe = crtc->pipe; | |
1497 | ||
1498 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1499 | POSTING_READ(DPLL(pipe)); | |
1500 | udelay(150); | |
1501 | ||
2c30b43b CW |
1502 | if (intel_wait_for_register(dev_priv, |
1503 | DPLL(pipe), | |
1504 | DPLL_LOCK_VLV, | |
1505 | DPLL_LOCK_VLV, | |
1506 | 1)) | |
cd2d34d9 VS |
1507 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1508 | } | |
1509 | ||
d288f65f | 1510 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1511 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1512 | { |
cd2d34d9 | 1513 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1514 | enum pipe pipe = crtc->pipe; |
87442f73 | 1515 | |
8bd3f301 | 1516 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1517 | |
87442f73 | 1518 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1519 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1520 | |
cd2d34d9 VS |
1521 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1522 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1523 | |
8bd3f301 VS |
1524 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1525 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1526 | } |
1527 | ||
cd2d34d9 VS |
1528 | |
1529 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1530 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1531 | { |
cd2d34d9 | 1532 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1533 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1534 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1535 | u32 tmp; |
1536 | ||
a580516d | 1537 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1538 | |
1539 | /* Enable back the 10bit clock to display controller */ | |
1540 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1541 | tmp |= DPIO_DCLKP_EN; | |
1542 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1543 | ||
54433e91 VS |
1544 | mutex_unlock(&dev_priv->sb_lock); |
1545 | ||
9d556c99 CML |
1546 | /* |
1547 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1548 | */ | |
1549 | udelay(1); | |
1550 | ||
1551 | /* Enable PLL */ | |
d288f65f | 1552 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1553 | |
1554 | /* Check PLL is locked */ | |
6b18826a CW |
1555 | if (intel_wait_for_register(dev_priv, |
1556 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1557 | 1)) | |
9d556c99 | 1558 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1559 | } |
1560 | ||
1561 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1562 | const struct intel_crtc_state *pipe_config) | |
1563 | { | |
1564 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1565 | enum pipe pipe = crtc->pipe; | |
1566 | ||
1567 | assert_pipe_disabled(dev_priv, pipe); | |
1568 | ||
1569 | /* PLL is protected by panel, make sure we can write it */ | |
1570 | assert_panel_unlocked(dev_priv, pipe); | |
1571 | ||
1572 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1573 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1574 | |
c231775c VS |
1575 | if (pipe != PIPE_A) { |
1576 | /* | |
1577 | * WaPixelRepeatModeFixForC0:chv | |
1578 | * | |
1579 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1580 | * the value from DPLLBMD to either pipe B or C. | |
1581 | */ | |
1582 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1583 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1584 | I915_WRITE(CBR4_VLV, 0); | |
1585 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1586 | ||
1587 | /* | |
1588 | * DPLLB VGA mode also seems to cause problems. | |
1589 | * We should always have it disabled. | |
1590 | */ | |
1591 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1592 | } else { | |
1593 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1594 | POSTING_READ(DPLL_MD(pipe)); | |
1595 | } | |
9d556c99 CML |
1596 | } |
1597 | ||
1c4e0274 VS |
1598 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1599 | { | |
1600 | struct intel_crtc *crtc; | |
1601 | int count = 0; | |
1602 | ||
2d84d2b3 | 1603 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1604 | count += crtc->base.state->active && |
2d84d2b3 VS |
1605 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1606 | } | |
1c4e0274 VS |
1607 | |
1608 | return count; | |
1609 | } | |
1610 | ||
66e3d5c0 | 1611 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1612 | { |
66e3d5c0 | 1613 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1614 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1615 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1616 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1617 | |
66e3d5c0 | 1618 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1619 | |
63d7bbe9 | 1620 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1621 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1622 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1623 | |
1c4e0274 VS |
1624 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1625 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1626 | /* | |
1627 | * It appears to be important that we don't enable this | |
1628 | * for the current pipe before otherwise configuring the | |
1629 | * PLL. No idea how this should be handled if multiple | |
1630 | * DVO outputs are enabled simultaneosly. | |
1631 | */ | |
1632 | dpll |= DPLL_DVO_2X_MODE; | |
1633 | I915_WRITE(DPLL(!crtc->pipe), | |
1634 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1635 | } | |
66e3d5c0 | 1636 | |
c2b63374 VS |
1637 | /* |
1638 | * Apparently we need to have VGA mode enabled prior to changing | |
1639 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1640 | * dividers, even though the register value does change. | |
1641 | */ | |
1642 | I915_WRITE(reg, 0); | |
1643 | ||
8e7a65aa VS |
1644 | I915_WRITE(reg, dpll); |
1645 | ||
66e3d5c0 DV |
1646 | /* Wait for the clocks to stabilize. */ |
1647 | POSTING_READ(reg); | |
1648 | udelay(150); | |
1649 | ||
1650 | if (INTEL_INFO(dev)->gen >= 4) { | |
1651 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1652 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1653 | } else { |
1654 | /* The pixel multiplier can only be updated once the | |
1655 | * DPLL is enabled and the clocks are stable. | |
1656 | * | |
1657 | * So write it again. | |
1658 | */ | |
1659 | I915_WRITE(reg, dpll); | |
1660 | } | |
63d7bbe9 JB |
1661 | |
1662 | /* We do this three times for luck */ | |
66e3d5c0 | 1663 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1664 | POSTING_READ(reg); |
1665 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1666 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1667 | POSTING_READ(reg); |
1668 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1669 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1670 | POSTING_READ(reg); |
1671 | udelay(150); /* wait for warmup */ | |
1672 | } | |
1673 | ||
1674 | /** | |
50b44a44 | 1675 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1676 | * @dev_priv: i915 private structure |
1677 | * @pipe: pipe PLL to disable | |
1678 | * | |
1679 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1680 | * | |
1681 | * Note! This is for pre-ILK only. | |
1682 | */ | |
1c4e0274 | 1683 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1684 | { |
1c4e0274 | 1685 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1686 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1687 | enum pipe pipe = crtc->pipe; |
1688 | ||
1689 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1690 | if (IS_I830(dev) && | |
2d84d2b3 | 1691 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1692 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1693 | I915_WRITE(DPLL(PIPE_B), |
1694 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1695 | I915_WRITE(DPLL(PIPE_A), | |
1696 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1697 | } | |
1698 | ||
b6b5d049 VS |
1699 | /* Don't disable pipe or pipe PLLs if needed */ |
1700 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1701 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1702 | return; |
1703 | ||
1704 | /* Make sure the pipe isn't still relying on us */ | |
1705 | assert_pipe_disabled(dev_priv, pipe); | |
1706 | ||
b8afb911 | 1707 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1708 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1709 | } |
1710 | ||
f6071166 JB |
1711 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1712 | { | |
b8afb911 | 1713 | u32 val; |
f6071166 JB |
1714 | |
1715 | /* Make sure the pipe isn't still relying on us */ | |
1716 | assert_pipe_disabled(dev_priv, pipe); | |
1717 | ||
03ed5cbf VS |
1718 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1719 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1720 | if (pipe != PIPE_A) | |
1721 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1722 | ||
f6071166 JB |
1723 | I915_WRITE(DPLL(pipe), val); |
1724 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1725 | } |
1726 | ||
1727 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1728 | { | |
d752048d | 1729 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1730 | u32 val; |
1731 | ||
a11b0703 VS |
1732 | /* Make sure the pipe isn't still relying on us */ |
1733 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1734 | |
60bfe44f VS |
1735 | val = DPLL_SSC_REF_CLK_CHV | |
1736 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1737 | if (pipe != PIPE_A) |
1738 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1739 | |
a11b0703 VS |
1740 | I915_WRITE(DPLL(pipe), val); |
1741 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1742 | |
a580516d | 1743 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1744 | |
1745 | /* Disable 10bit clock to display controller */ | |
1746 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1747 | val &= ~DPIO_DCLKP_EN; | |
1748 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1749 | ||
a580516d | 1750 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1751 | } |
1752 | ||
e4607fcf | 1753 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1754 | struct intel_digital_port *dport, |
1755 | unsigned int expected_mask) | |
89b667f8 JB |
1756 | { |
1757 | u32 port_mask; | |
f0f59a00 | 1758 | i915_reg_t dpll_reg; |
89b667f8 | 1759 | |
e4607fcf CML |
1760 | switch (dport->port) { |
1761 | case PORT_B: | |
89b667f8 | 1762 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1763 | dpll_reg = DPLL(0); |
e4607fcf CML |
1764 | break; |
1765 | case PORT_C: | |
89b667f8 | 1766 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1767 | dpll_reg = DPLL(0); |
9b6de0a1 | 1768 | expected_mask <<= 4; |
00fc31b7 CML |
1769 | break; |
1770 | case PORT_D: | |
1771 | port_mask = DPLL_PORTD_READY_MASK; | |
1772 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1773 | break; |
1774 | default: | |
1775 | BUG(); | |
1776 | } | |
89b667f8 | 1777 | |
370004d3 CW |
1778 | if (intel_wait_for_register(dev_priv, |
1779 | dpll_reg, port_mask, expected_mask, | |
1780 | 1000)) | |
9b6de0a1 VS |
1781 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1782 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1783 | } |
1784 | ||
b8a4f404 PZ |
1785 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1786 | enum pipe pipe) | |
040484af | 1787 | { |
91c8a326 | 1788 | struct drm_device *dev = &dev_priv->drm; |
7c26e5c6 | 1789 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1791 | i915_reg_t reg; |
1792 | uint32_t val, pipeconf_val; | |
040484af | 1793 | |
040484af | 1794 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1795 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1796 | |
1797 | /* FDI must be feeding us bits for PCH ports */ | |
1798 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1799 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1800 | ||
23670b32 DV |
1801 | if (HAS_PCH_CPT(dev)) { |
1802 | /* Workaround: Set the timing override bit before enabling the | |
1803 | * pch transcoder. */ | |
1804 | reg = TRANS_CHICKEN2(pipe); | |
1805 | val = I915_READ(reg); | |
1806 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1807 | I915_WRITE(reg, val); | |
59c859d6 | 1808 | } |
23670b32 | 1809 | |
ab9412ba | 1810 | reg = PCH_TRANSCONF(pipe); |
040484af | 1811 | val = I915_READ(reg); |
5f7f726d | 1812 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1813 | |
2d1fe073 | 1814 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1815 | /* |
c5de7c6f VS |
1816 | * Make the BPC in transcoder be consistent with |
1817 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1818 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1819 | */ |
dfd07d72 | 1820 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1821 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1822 | val |= PIPECONF_8BPC; |
1823 | else | |
1824 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1825 | } |
5f7f726d PZ |
1826 | |
1827 | val &= ~TRANS_INTERLACE_MASK; | |
1828 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1829 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1830 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1831 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1832 | else | |
1833 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1834 | else |
1835 | val |= TRANS_PROGRESSIVE; | |
1836 | ||
040484af | 1837 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1838 | if (intel_wait_for_register(dev_priv, |
1839 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1840 | 100)) | |
4bb6f1f3 | 1841 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1842 | } |
1843 | ||
8fb033d7 | 1844 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1845 | enum transcoder cpu_transcoder) |
040484af | 1846 | { |
8fb033d7 | 1847 | u32 val, pipeconf_val; |
8fb033d7 | 1848 | |
8fb033d7 | 1849 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1850 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1851 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1852 | |
223a6fdf | 1853 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1854 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1855 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1856 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1857 | |
25f3ef11 | 1858 | val = TRANS_ENABLE; |
937bb610 | 1859 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1860 | |
9a76b1c6 PZ |
1861 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1862 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1863 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1864 | else |
1865 | val |= TRANS_PROGRESSIVE; | |
1866 | ||
ab9412ba | 1867 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1868 | if (intel_wait_for_register(dev_priv, |
1869 | LPT_TRANSCONF, | |
1870 | TRANS_STATE_ENABLE, | |
1871 | TRANS_STATE_ENABLE, | |
1872 | 100)) | |
937bb610 | 1873 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1874 | } |
1875 | ||
b8a4f404 PZ |
1876 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1877 | enum pipe pipe) | |
040484af | 1878 | { |
91c8a326 | 1879 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 VS |
1880 | i915_reg_t reg; |
1881 | uint32_t val; | |
040484af JB |
1882 | |
1883 | /* FDI relies on the transcoder */ | |
1884 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1885 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1886 | ||
291906f1 JB |
1887 | /* Ports must be off as well */ |
1888 | assert_pch_ports_disabled(dev_priv, pipe); | |
1889 | ||
ab9412ba | 1890 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1891 | val = I915_READ(reg); |
1892 | val &= ~TRANS_ENABLE; | |
1893 | I915_WRITE(reg, val); | |
1894 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1895 | if (intel_wait_for_register(dev_priv, |
1896 | reg, TRANS_STATE_ENABLE, 0, | |
1897 | 50)) | |
4bb6f1f3 | 1898 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1899 | |
c465613b | 1900 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1901 | /* Workaround: Clear the timing override chicken bit again. */ |
1902 | reg = TRANS_CHICKEN2(pipe); | |
1903 | val = I915_READ(reg); | |
1904 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1905 | I915_WRITE(reg, val); | |
1906 | } | |
040484af JB |
1907 | } |
1908 | ||
ab4d966c | 1909 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1910 | { |
8fb033d7 PZ |
1911 | u32 val; |
1912 | ||
ab9412ba | 1913 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1914 | val &= ~TRANS_ENABLE; |
ab9412ba | 1915 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1916 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1917 | if (intel_wait_for_register(dev_priv, |
1918 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1919 | 50)) | |
8a52fd9f | 1920 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1921 | |
1922 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1923 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1924 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1925 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1926 | } |
1927 | ||
b24e7179 | 1928 | /** |
309cfea8 | 1929 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1930 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1931 | * |
0372264a | 1932 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1933 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1934 | */ |
e1fdc473 | 1935 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1936 | { |
0372264a | 1937 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1938 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1939 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1940 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1941 | enum pipe pch_transcoder; |
f0f59a00 | 1942 | i915_reg_t reg; |
b24e7179 JB |
1943 | u32 val; |
1944 | ||
9e2ee2dd VS |
1945 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1946 | ||
58c6eaa2 | 1947 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1948 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1949 | assert_sprites_disabled(dev_priv, pipe); |
1950 | ||
2d1fe073 | 1951 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1952 | pch_transcoder = TRANSCODER_A; |
1953 | else | |
1954 | pch_transcoder = pipe; | |
1955 | ||
b24e7179 JB |
1956 | /* |
1957 | * A pipe without a PLL won't actually be able to drive bits from | |
1958 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1959 | * need the check. | |
1960 | */ | |
2d1fe073 | 1961 | if (HAS_GMCH_DISPLAY(dev_priv)) |
a65347ba | 1962 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
1963 | assert_dsi_pll_enabled(dev_priv); |
1964 | else | |
1965 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1966 | else { |
6e3c9717 | 1967 | if (crtc->config->has_pch_encoder) { |
040484af | 1968 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1969 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1970 | assert_fdi_tx_pll_enabled(dev_priv, |
1971 | (enum pipe) cpu_transcoder); | |
040484af JB |
1972 | } |
1973 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1974 | } | |
b24e7179 | 1975 | |
702e7a56 | 1976 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1977 | val = I915_READ(reg); |
7ad25d48 | 1978 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1979 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1980 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1981 | return; |
7ad25d48 | 1982 | } |
00d70b15 CW |
1983 | |
1984 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1985 | POSTING_READ(reg); |
b7792d8b VS |
1986 | |
1987 | /* | |
1988 | * Until the pipe starts DSL will read as 0, which would cause | |
1989 | * an apparent vblank timestamp jump, which messes up also the | |
1990 | * frame count when it's derived from the timestamps. So let's | |
1991 | * wait for the pipe to start properly before we call | |
1992 | * drm_crtc_vblank_on() | |
1993 | */ | |
1994 | if (dev->max_vblank_count == 0 && | |
1995 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1996 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1997 | } |
1998 | ||
1999 | /** | |
309cfea8 | 2000 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2001 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2002 | * |
575f7ab7 VS |
2003 | * Disable the pipe of @crtc, making sure that various hardware |
2004 | * specific requirements are met, if applicable, e.g. plane | |
2005 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2006 | * |
2007 | * Will wait until the pipe has shut down before returning. | |
2008 | */ | |
575f7ab7 | 2009 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2010 | { |
fac5e23e | 2011 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2012 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2013 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2014 | i915_reg_t reg; |
b24e7179 JB |
2015 | u32 val; |
2016 | ||
9e2ee2dd VS |
2017 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2018 | ||
b24e7179 JB |
2019 | /* |
2020 | * Make sure planes won't keep trying to pump pixels to us, | |
2021 | * or we might hang the display. | |
2022 | */ | |
2023 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2024 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2025 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2026 | |
702e7a56 | 2027 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2028 | val = I915_READ(reg); |
00d70b15 CW |
2029 | if ((val & PIPECONF_ENABLE) == 0) |
2030 | return; | |
2031 | ||
67adc644 VS |
2032 | /* |
2033 | * Double wide has implications for planes | |
2034 | * so best keep it disabled when not needed. | |
2035 | */ | |
6e3c9717 | 2036 | if (crtc->config->double_wide) |
67adc644 VS |
2037 | val &= ~PIPECONF_DOUBLE_WIDE; |
2038 | ||
2039 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2040 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2041 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2042 | val &= ~PIPECONF_ENABLE; |
2043 | ||
2044 | I915_WRITE(reg, val); | |
2045 | if ((val & PIPECONF_ENABLE) == 0) | |
2046 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2047 | } |
2048 | ||
693db184 CW |
2049 | static bool need_vtd_wa(struct drm_device *dev) |
2050 | { | |
2051 | #ifdef CONFIG_INTEL_IOMMU | |
2052 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2053 | return true; | |
2054 | #endif | |
2055 | return false; | |
2056 | } | |
2057 | ||
832be82f VS |
2058 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2059 | { | |
2060 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2061 | } | |
2062 | ||
27ba3910 VS |
2063 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2064 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2065 | { |
2066 | switch (fb_modifier) { | |
2067 | case DRM_FORMAT_MOD_NONE: | |
2068 | return cpp; | |
2069 | case I915_FORMAT_MOD_X_TILED: | |
2070 | if (IS_GEN2(dev_priv)) | |
2071 | return 128; | |
2072 | else | |
2073 | return 512; | |
2074 | case I915_FORMAT_MOD_Y_TILED: | |
2075 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2076 | return 128; | |
2077 | else | |
2078 | return 512; | |
2079 | case I915_FORMAT_MOD_Yf_TILED: | |
2080 | switch (cpp) { | |
2081 | case 1: | |
2082 | return 64; | |
2083 | case 2: | |
2084 | case 4: | |
2085 | return 128; | |
2086 | case 8: | |
2087 | case 16: | |
2088 | return 256; | |
2089 | default: | |
2090 | MISSING_CASE(cpp); | |
2091 | return cpp; | |
2092 | } | |
2093 | break; | |
2094 | default: | |
2095 | MISSING_CASE(fb_modifier); | |
2096 | return cpp; | |
2097 | } | |
2098 | } | |
2099 | ||
832be82f VS |
2100 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2101 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2102 | { |
832be82f VS |
2103 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2104 | return 1; | |
2105 | else | |
2106 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2107 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2108 | } |
2109 | ||
8d0deca8 VS |
2110 | /* Return the tile dimensions in pixel units */ |
2111 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2112 | unsigned int *tile_width, | |
2113 | unsigned int *tile_height, | |
2114 | uint64_t fb_modifier, | |
2115 | unsigned int cpp) | |
2116 | { | |
2117 | unsigned int tile_width_bytes = | |
2118 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2119 | ||
2120 | *tile_width = tile_width_bytes / cpp; | |
2121 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2122 | } | |
2123 | ||
6761dd31 TU |
2124 | unsigned int |
2125 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2126 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2127 | { |
832be82f VS |
2128 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2129 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2130 | ||
2131 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2132 | } |
2133 | ||
1663b9d6 VS |
2134 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2135 | { | |
2136 | unsigned int size = 0; | |
2137 | int i; | |
2138 | ||
2139 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2140 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2141 | ||
2142 | return size; | |
2143 | } | |
2144 | ||
75c82a53 | 2145 | static void |
3465c580 VS |
2146 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2147 | const struct drm_framebuffer *fb, | |
2148 | unsigned int rotation) | |
f64b98cd | 2149 | { |
2d7a215f VS |
2150 | if (intel_rotation_90_or_270(rotation)) { |
2151 | *view = i915_ggtt_view_rotated; | |
2152 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2153 | } else { | |
2154 | *view = i915_ggtt_view_normal; | |
2155 | } | |
2156 | } | |
50470bb0 | 2157 | |
2d7a215f VS |
2158 | static void |
2159 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2160 | struct drm_framebuffer *fb) | |
2161 | { | |
2162 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2163 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2164 | |
d9b3288e VS |
2165 | tile_size = intel_tile_size(dev_priv); |
2166 | ||
2167 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2168 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2169 | fb->modifier[0], cpp); | |
d9b3288e | 2170 | |
1663b9d6 VS |
2171 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2172 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2173 | |
89e3e142 | 2174 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2175 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2176 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2177 | fb->modifier[1], cpp); | |
d9b3288e | 2178 | |
2d7a215f | 2179 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2180 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2181 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2182 | } |
f64b98cd TU |
2183 | } |
2184 | ||
603525d7 | 2185 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2186 | { |
2187 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2188 | return 256 * 1024; | |
985b8bb4 | 2189 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2190 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2191 | return 128 * 1024; |
2192 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2193 | return 4 * 1024; | |
2194 | else | |
44c5905e | 2195 | return 0; |
4e9a86b6 VS |
2196 | } |
2197 | ||
603525d7 VS |
2198 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2199 | uint64_t fb_modifier) | |
2200 | { | |
2201 | switch (fb_modifier) { | |
2202 | case DRM_FORMAT_MOD_NONE: | |
2203 | return intel_linear_alignment(dev_priv); | |
2204 | case I915_FORMAT_MOD_X_TILED: | |
2205 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2206 | return 256 * 1024; | |
2207 | return 0; | |
2208 | case I915_FORMAT_MOD_Y_TILED: | |
2209 | case I915_FORMAT_MOD_Yf_TILED: | |
2210 | return 1 * 1024 * 1024; | |
2211 | default: | |
2212 | MISSING_CASE(fb_modifier); | |
2213 | return 0; | |
2214 | } | |
2215 | } | |
2216 | ||
127bd2ac | 2217 | int |
3465c580 VS |
2218 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2219 | unsigned int rotation) | |
6b95a207 | 2220 | { |
850c4cdc | 2221 | struct drm_device *dev = fb->dev; |
fac5e23e | 2222 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2223 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2224 | struct i915_ggtt_view view; |
6b95a207 KH |
2225 | u32 alignment; |
2226 | int ret; | |
2227 | ||
ebcdd39e MR |
2228 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2229 | ||
603525d7 | 2230 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2231 | |
3465c580 | 2232 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2233 | |
693db184 CW |
2234 | /* Note that the w/a also requires 64 PTE of padding following the |
2235 | * bo. We currently fill all unused PTE with the shadow page and so | |
2236 | * we should always have valid PTE following the scanout preventing | |
2237 | * the VT-d warning. | |
2238 | */ | |
2239 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2240 | alignment = 256 * 1024; | |
2241 | ||
d6dd6843 PZ |
2242 | /* |
2243 | * Global gtt pte registers are special registers which actually forward | |
2244 | * writes to a chunk of system memory. Which means that there is no risk | |
2245 | * that the register values disappear as soon as we call | |
2246 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2247 | * pin/unpin/fence and not more. | |
2248 | */ | |
2249 | intel_runtime_pm_get(dev_priv); | |
2250 | ||
7580d774 ML |
2251 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2252 | &view); | |
48b956c5 | 2253 | if (ret) |
b26a6b35 | 2254 | goto err_pm; |
6b95a207 KH |
2255 | |
2256 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2257 | * fence, whereas 965+ only requires a fence if using | |
2258 | * framebuffer compression. For simplicity, we always install | |
2259 | * a fence as the cost is not that onerous. | |
2260 | */ | |
9807216f VK |
2261 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2262 | ret = i915_gem_object_get_fence(obj); | |
2263 | if (ret == -EDEADLK) { | |
2264 | /* | |
2265 | * -EDEADLK means there are no free fences | |
2266 | * no pending flips. | |
2267 | * | |
2268 | * This is propagated to atomic, but it uses | |
2269 | * -EDEADLK to force a locking recovery, so | |
2270 | * change the returned error to -EBUSY. | |
2271 | */ | |
2272 | ret = -EBUSY; | |
2273 | goto err_unpin; | |
2274 | } else if (ret) | |
2275 | goto err_unpin; | |
1690e1eb | 2276 | |
9807216f VK |
2277 | i915_gem_object_pin_fence(obj); |
2278 | } | |
6b95a207 | 2279 | |
d6dd6843 | 2280 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2281 | return 0; |
48b956c5 CW |
2282 | |
2283 | err_unpin: | |
f64b98cd | 2284 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2285 | err_pm: |
d6dd6843 | 2286 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2287 | return ret; |
6b95a207 KH |
2288 | } |
2289 | ||
fb4b8ce1 | 2290 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2291 | { |
82bc3b2d | 2292 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2293 | struct i915_ggtt_view view; |
82bc3b2d | 2294 | |
ebcdd39e MR |
2295 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2296 | ||
3465c580 | 2297 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2298 | |
9807216f VK |
2299 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2300 | i915_gem_object_unpin_fence(obj); | |
2301 | ||
f64b98cd | 2302 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2303 | } |
2304 | ||
29cf9491 VS |
2305 | /* |
2306 | * Adjust the tile offset by moving the difference into | |
2307 | * the x/y offsets. | |
2308 | * | |
2309 | * Input tile dimensions and pitch must already be | |
2310 | * rotated to match x and y, and in pixel units. | |
2311 | */ | |
2312 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2313 | unsigned int tile_width, | |
2314 | unsigned int tile_height, | |
2315 | unsigned int tile_size, | |
2316 | unsigned int pitch_tiles, | |
2317 | u32 old_offset, | |
2318 | u32 new_offset) | |
2319 | { | |
2320 | unsigned int tiles; | |
2321 | ||
2322 | WARN_ON(old_offset & (tile_size - 1)); | |
2323 | WARN_ON(new_offset & (tile_size - 1)); | |
2324 | WARN_ON(new_offset > old_offset); | |
2325 | ||
2326 | tiles = (old_offset - new_offset) / tile_size; | |
2327 | ||
2328 | *y += tiles / pitch_tiles * tile_height; | |
2329 | *x += tiles % pitch_tiles * tile_width; | |
2330 | ||
2331 | return new_offset; | |
2332 | } | |
2333 | ||
8d0deca8 VS |
2334 | /* |
2335 | * Computes the linear offset to the base tile and adjusts | |
2336 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2337 | * | |
2338 | * In the 90/270 rotated case, x and y are assumed | |
2339 | * to be already rotated to match the rotated GTT view, and | |
2340 | * pitch is the tile_height aligned framebuffer height. | |
2341 | */ | |
4f2d9934 VS |
2342 | u32 intel_compute_tile_offset(int *x, int *y, |
2343 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2344 | unsigned int pitch, |
2345 | unsigned int rotation) | |
c2c75131 | 2346 | { |
4f2d9934 VS |
2347 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2348 | uint64_t fb_modifier = fb->modifier[plane]; | |
2349 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2350 | u32 offset, offset_aligned, alignment; |
2351 | ||
2352 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2353 | if (alignment) | |
2354 | alignment--; | |
2355 | ||
b5c65338 | 2356 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2357 | unsigned int tile_size, tile_width, tile_height; |
2358 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2359 | |
d843310d | 2360 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2361 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2362 | fb_modifier, cpp); | |
2363 | ||
2364 | if (intel_rotation_90_or_270(rotation)) { | |
2365 | pitch_tiles = pitch / tile_height; | |
2366 | swap(tile_width, tile_height); | |
2367 | } else { | |
2368 | pitch_tiles = pitch / (tile_width * cpp); | |
2369 | } | |
d843310d VS |
2370 | |
2371 | tile_rows = *y / tile_height; | |
2372 | *y %= tile_height; | |
c2c75131 | 2373 | |
8d0deca8 VS |
2374 | tiles = *x / tile_width; |
2375 | *x %= tile_width; | |
bc752862 | 2376 | |
29cf9491 VS |
2377 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2378 | offset_aligned = offset & ~alignment; | |
bc752862 | 2379 | |
29cf9491 VS |
2380 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2381 | tile_size, pitch_tiles, | |
2382 | offset, offset_aligned); | |
2383 | } else { | |
bc752862 | 2384 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2385 | offset_aligned = offset & ~alignment; |
2386 | ||
4e9a86b6 VS |
2387 | *y = (offset & alignment) / pitch; |
2388 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2389 | } |
29cf9491 VS |
2390 | |
2391 | return offset_aligned; | |
c2c75131 DV |
2392 | } |
2393 | ||
b35d63fa | 2394 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2395 | { |
2396 | switch (format) { | |
2397 | case DISPPLANE_8BPP: | |
2398 | return DRM_FORMAT_C8; | |
2399 | case DISPPLANE_BGRX555: | |
2400 | return DRM_FORMAT_XRGB1555; | |
2401 | case DISPPLANE_BGRX565: | |
2402 | return DRM_FORMAT_RGB565; | |
2403 | default: | |
2404 | case DISPPLANE_BGRX888: | |
2405 | return DRM_FORMAT_XRGB8888; | |
2406 | case DISPPLANE_RGBX888: | |
2407 | return DRM_FORMAT_XBGR8888; | |
2408 | case DISPPLANE_BGRX101010: | |
2409 | return DRM_FORMAT_XRGB2101010; | |
2410 | case DISPPLANE_RGBX101010: | |
2411 | return DRM_FORMAT_XBGR2101010; | |
2412 | } | |
2413 | } | |
2414 | ||
bc8d7dff DL |
2415 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2416 | { | |
2417 | switch (format) { | |
2418 | case PLANE_CTL_FORMAT_RGB_565: | |
2419 | return DRM_FORMAT_RGB565; | |
2420 | default: | |
2421 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2422 | if (rgb_order) { | |
2423 | if (alpha) | |
2424 | return DRM_FORMAT_ABGR8888; | |
2425 | else | |
2426 | return DRM_FORMAT_XBGR8888; | |
2427 | } else { | |
2428 | if (alpha) | |
2429 | return DRM_FORMAT_ARGB8888; | |
2430 | else | |
2431 | return DRM_FORMAT_XRGB8888; | |
2432 | } | |
2433 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2434 | if (rgb_order) | |
2435 | return DRM_FORMAT_XBGR2101010; | |
2436 | else | |
2437 | return DRM_FORMAT_XRGB2101010; | |
2438 | } | |
2439 | } | |
2440 | ||
5724dbd1 | 2441 | static bool |
f6936e29 DV |
2442 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2443 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2444 | { |
2445 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2446 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2447 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2448 | struct drm_i915_gem_object *obj = NULL; |
2449 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2450 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2451 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2452 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2453 | PAGE_SIZE); | |
2454 | ||
2455 | size_aligned -= base_aligned; | |
46f297fb | 2456 | |
ff2652ea CW |
2457 | if (plane_config->size == 0) |
2458 | return false; | |
2459 | ||
3badb49f PZ |
2460 | /* If the FB is too big, just don't use it since fbdev is not very |
2461 | * important and we should probably use that space with FBC or other | |
2462 | * features. */ | |
72e96d64 | 2463 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2464 | return false; |
2465 | ||
12c83d99 TU |
2466 | mutex_lock(&dev->struct_mutex); |
2467 | ||
f37b5c2b DV |
2468 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2469 | base_aligned, | |
2470 | base_aligned, | |
2471 | size_aligned); | |
12c83d99 TU |
2472 | if (!obj) { |
2473 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2474 | return false; |
12c83d99 | 2475 | } |
46f297fb | 2476 | |
49af449b DL |
2477 | obj->tiling_mode = plane_config->tiling; |
2478 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2479 | obj->stride = fb->pitches[0]; |
46f297fb | 2480 | |
6bf129df DL |
2481 | mode_cmd.pixel_format = fb->pixel_format; |
2482 | mode_cmd.width = fb->width; | |
2483 | mode_cmd.height = fb->height; | |
2484 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2485 | mode_cmd.modifier[0] = fb->modifier[0]; |
2486 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2487 | |
6bf129df | 2488 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2489 | &mode_cmd, obj)) { |
46f297fb JB |
2490 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2491 | goto out_unref_obj; | |
2492 | } | |
12c83d99 | 2493 | |
46f297fb | 2494 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2495 | |
f6936e29 | 2496 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2497 | return true; |
46f297fb JB |
2498 | |
2499 | out_unref_obj: | |
2500 | drm_gem_object_unreference(&obj->base); | |
2501 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2502 | return false; |
2503 | } | |
2504 | ||
5a21b665 DV |
2505 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2506 | static void | |
2507 | update_state_fb(struct drm_plane *plane) | |
2508 | { | |
2509 | if (plane->fb == plane->state->fb) | |
2510 | return; | |
2511 | ||
2512 | if (plane->state->fb) | |
2513 | drm_framebuffer_unreference(plane->state->fb); | |
2514 | plane->state->fb = plane->fb; | |
2515 | if (plane->state->fb) | |
2516 | drm_framebuffer_reference(plane->state->fb); | |
2517 | } | |
2518 | ||
5724dbd1 | 2519 | static void |
f6936e29 DV |
2520 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2521 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2522 | { |
2523 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2524 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2525 | struct drm_crtc *c; |
2526 | struct intel_crtc *i; | |
2ff8fde1 | 2527 | struct drm_i915_gem_object *obj; |
88595ac9 | 2528 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2529 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2530 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2531 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2532 | struct intel_plane_state *intel_state = |
2533 | to_intel_plane_state(plane_state); | |
88595ac9 | 2534 | struct drm_framebuffer *fb; |
484b41dd | 2535 | |
2d14030b | 2536 | if (!plane_config->fb) |
484b41dd JB |
2537 | return; |
2538 | ||
f6936e29 | 2539 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2540 | fb = &plane_config->fb->base; |
2541 | goto valid_fb; | |
f55548b5 | 2542 | } |
484b41dd | 2543 | |
2d14030b | 2544 | kfree(plane_config->fb); |
484b41dd JB |
2545 | |
2546 | /* | |
2547 | * Failed to alloc the obj, check to see if we should share | |
2548 | * an fb with another CRTC instead | |
2549 | */ | |
70e1e0ec | 2550 | for_each_crtc(dev, c) { |
484b41dd JB |
2551 | i = to_intel_crtc(c); |
2552 | ||
2553 | if (c == &intel_crtc->base) | |
2554 | continue; | |
2555 | ||
2ff8fde1 MR |
2556 | if (!i->active) |
2557 | continue; | |
2558 | ||
88595ac9 DV |
2559 | fb = c->primary->fb; |
2560 | if (!fb) | |
484b41dd JB |
2561 | continue; |
2562 | ||
88595ac9 | 2563 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2564 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2565 | drm_framebuffer_reference(fb); |
2566 | goto valid_fb; | |
484b41dd JB |
2567 | } |
2568 | } | |
88595ac9 | 2569 | |
200757f5 MR |
2570 | /* |
2571 | * We've failed to reconstruct the BIOS FB. Current display state | |
2572 | * indicates that the primary plane is visible, but has a NULL FB, | |
2573 | * which will lead to problems later if we don't fix it up. The | |
2574 | * simplest solution is to just disable the primary plane now and | |
2575 | * pretend the BIOS never had it enabled. | |
2576 | */ | |
2577 | to_intel_plane_state(plane_state)->visible = false; | |
2578 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2579 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2580 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2581 | ||
88595ac9 DV |
2582 | return; |
2583 | ||
2584 | valid_fb: | |
f44e2659 VS |
2585 | plane_state->src_x = 0; |
2586 | plane_state->src_y = 0; | |
be5651f2 ML |
2587 | plane_state->src_w = fb->width << 16; |
2588 | plane_state->src_h = fb->height << 16; | |
2589 | ||
f44e2659 VS |
2590 | plane_state->crtc_x = 0; |
2591 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2592 | plane_state->crtc_w = fb->width; |
2593 | plane_state->crtc_h = fb->height; | |
2594 | ||
0a8d8a86 MR |
2595 | intel_state->src.x1 = plane_state->src_x; |
2596 | intel_state->src.y1 = plane_state->src_y; | |
2597 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2598 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2599 | intel_state->dst.x1 = plane_state->crtc_x; | |
2600 | intel_state->dst.y1 = plane_state->crtc_y; | |
2601 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2602 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2603 | ||
88595ac9 DV |
2604 | obj = intel_fb_obj(fb); |
2605 | if (obj->tiling_mode != I915_TILING_NONE) | |
2606 | dev_priv->preserve_bios_swizzle = true; | |
2607 | ||
be5651f2 ML |
2608 | drm_framebuffer_reference(fb); |
2609 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2610 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2611 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2612 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2613 | } |
2614 | ||
a8d201af ML |
2615 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2616 | const struct intel_crtc_state *crtc_state, | |
2617 | const struct intel_plane_state *plane_state) | |
81255565 | 2618 | { |
a8d201af | 2619 | struct drm_device *dev = primary->dev; |
fac5e23e | 2620 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2622 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2623 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2624 | int plane = intel_crtc->plane; |
54ea9da8 | 2625 | u32 linear_offset; |
81255565 | 2626 | u32 dspcntr; |
f0f59a00 | 2627 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2628 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2629 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2630 | int x = plane_state->src.x1 >> 16; |
2631 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2632 | |
f45651ba VS |
2633 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2634 | ||
fdd508a6 | 2635 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2636 | |
2637 | if (INTEL_INFO(dev)->gen < 4) { | |
2638 | if (intel_crtc->pipe == PIPE_B) | |
2639 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2640 | ||
2641 | /* pipesrc and dspsize control the size that is scaled from, | |
2642 | * which should always be the user's requested size. | |
2643 | */ | |
2644 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2645 | ((crtc_state->pipe_src_h - 1) << 16) | |
2646 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2647 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2648 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2649 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2650 | ((crtc_state->pipe_src_h - 1) << 16) | |
2651 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2652 | I915_WRITE(PRIMPOS(plane), 0); |
2653 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2654 | } |
81255565 | 2655 | |
57779d06 VS |
2656 | switch (fb->pixel_format) { |
2657 | case DRM_FORMAT_C8: | |
81255565 JB |
2658 | dspcntr |= DISPPLANE_8BPP; |
2659 | break; | |
57779d06 | 2660 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2661 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2662 | break; |
57779d06 VS |
2663 | case DRM_FORMAT_RGB565: |
2664 | dspcntr |= DISPPLANE_BGRX565; | |
2665 | break; | |
2666 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2667 | dspcntr |= DISPPLANE_BGRX888; |
2668 | break; | |
2669 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2670 | dspcntr |= DISPPLANE_RGBX888; |
2671 | break; | |
2672 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2673 | dspcntr |= DISPPLANE_BGRX101010; |
2674 | break; | |
2675 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2676 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2677 | break; |
2678 | default: | |
baba133a | 2679 | BUG(); |
81255565 | 2680 | } |
57779d06 | 2681 | |
f45651ba VS |
2682 | if (INTEL_INFO(dev)->gen >= 4 && |
2683 | obj->tiling_mode != I915_TILING_NONE) | |
2684 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2685 | |
de1aa629 VS |
2686 | if (IS_G4X(dev)) |
2687 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2688 | ||
ac484963 | 2689 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2690 | |
c2c75131 DV |
2691 | if (INTEL_INFO(dev)->gen >= 4) { |
2692 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2693 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2694 | fb->pitches[0], rotation); |
c2c75131 DV |
2695 | linear_offset -= intel_crtc->dspaddr_offset; |
2696 | } else { | |
e506a0c6 | 2697 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2698 | } |
e506a0c6 | 2699 | |
8d0deca8 | 2700 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2701 | dspcntr |= DISPPLANE_ROTATE_180; |
2702 | ||
a8d201af ML |
2703 | x += (crtc_state->pipe_src_w - 1); |
2704 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2705 | |
2706 | /* Finding the last pixel of the last line of the display | |
2707 | data and adding to linear_offset*/ | |
2708 | linear_offset += | |
a8d201af | 2709 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2710 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2711 | } |
2712 | ||
2db3366b PZ |
2713 | intel_crtc->adjusted_x = x; |
2714 | intel_crtc->adjusted_y = y; | |
2715 | ||
48404c1e SJ |
2716 | I915_WRITE(reg, dspcntr); |
2717 | ||
01f2c773 | 2718 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2719 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2720 | I915_WRITE(DSPSURF(plane), |
2721 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2722 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2723 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2724 | } else |
f343c5f6 | 2725 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2726 | POSTING_READ(reg); |
17638cd6 JB |
2727 | } |
2728 | ||
a8d201af ML |
2729 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2730 | struct drm_crtc *crtc) | |
17638cd6 JB |
2731 | { |
2732 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 2733 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 2734 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 2735 | int plane = intel_crtc->plane; |
f45651ba | 2736 | |
a8d201af ML |
2737 | I915_WRITE(DSPCNTR(plane), 0); |
2738 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2739 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2740 | else |
2741 | I915_WRITE(DSPADDR(plane), 0); | |
2742 | POSTING_READ(DSPCNTR(plane)); | |
2743 | } | |
c9ba6fad | 2744 | |
a8d201af ML |
2745 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2746 | const struct intel_crtc_state *crtc_state, | |
2747 | const struct intel_plane_state *plane_state) | |
2748 | { | |
2749 | struct drm_device *dev = primary->dev; | |
fac5e23e | 2750 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2751 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2752 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2753 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2754 | int plane = intel_crtc->plane; | |
54ea9da8 | 2755 | u32 linear_offset; |
a8d201af ML |
2756 | u32 dspcntr; |
2757 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2758 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2759 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2760 | int x = plane_state->src.x1 >> 16; |
2761 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2762 | |
f45651ba | 2763 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2764 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2765 | |
2766 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2767 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2768 | |
57779d06 VS |
2769 | switch (fb->pixel_format) { |
2770 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2771 | dspcntr |= DISPPLANE_8BPP; |
2772 | break; | |
57779d06 VS |
2773 | case DRM_FORMAT_RGB565: |
2774 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2775 | break; |
57779d06 | 2776 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2777 | dspcntr |= DISPPLANE_BGRX888; |
2778 | break; | |
2779 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2780 | dspcntr |= DISPPLANE_RGBX888; |
2781 | break; | |
2782 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2783 | dspcntr |= DISPPLANE_BGRX101010; |
2784 | break; | |
2785 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2786 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2787 | break; |
2788 | default: | |
baba133a | 2789 | BUG(); |
17638cd6 JB |
2790 | } |
2791 | ||
2792 | if (obj->tiling_mode != I915_TILING_NONE) | |
2793 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2794 | |
f45651ba | 2795 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2796 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2797 | |
ac484963 | 2798 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2799 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2800 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2801 | fb->pitches[0], rotation); |
c2c75131 | 2802 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2803 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2804 | dspcntr |= DISPPLANE_ROTATE_180; |
2805 | ||
2806 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2807 | x += (crtc_state->pipe_src_w - 1); |
2808 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2809 | |
2810 | /* Finding the last pixel of the last line of the display | |
2811 | data and adding to linear_offset*/ | |
2812 | linear_offset += | |
a8d201af | 2813 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2814 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2815 | } |
2816 | } | |
2817 | ||
2db3366b PZ |
2818 | intel_crtc->adjusted_x = x; |
2819 | intel_crtc->adjusted_y = y; | |
2820 | ||
48404c1e | 2821 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2822 | |
01f2c773 | 2823 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2824 | I915_WRITE(DSPSURF(plane), |
2825 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2826 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2827 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2828 | } else { | |
2829 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2830 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2831 | } | |
17638cd6 | 2832 | POSTING_READ(reg); |
17638cd6 JB |
2833 | } |
2834 | ||
7b49f948 VS |
2835 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2836 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2837 | { |
7b49f948 | 2838 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2839 | return 64; |
7b49f948 VS |
2840 | } else { |
2841 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2842 | ||
27ba3910 | 2843 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2844 | } |
2845 | } | |
2846 | ||
44eb0cb9 MK |
2847 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2848 | struct drm_i915_gem_object *obj, | |
2849 | unsigned int plane) | |
121920fa | 2850 | { |
ce7f1728 | 2851 | struct i915_ggtt_view view; |
dedf278c | 2852 | struct i915_vma *vma; |
44eb0cb9 | 2853 | u64 offset; |
121920fa | 2854 | |
e7941294 | 2855 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2856 | intel_plane->base.state->rotation); |
121920fa | 2857 | |
ce7f1728 | 2858 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2859 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2860 | view.type)) |
dedf278c TU |
2861 | return -1; |
2862 | ||
44eb0cb9 | 2863 | offset = vma->node.start; |
dedf278c TU |
2864 | |
2865 | if (plane == 1) { | |
7723f47d | 2866 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2867 | PAGE_SIZE; |
2868 | } | |
2869 | ||
44eb0cb9 MK |
2870 | WARN_ON(upper_32_bits(offset)); |
2871 | ||
2872 | return lower_32_bits(offset); | |
121920fa TU |
2873 | } |
2874 | ||
e435d6e5 ML |
2875 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2876 | { | |
2877 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2878 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
2879 | |
2880 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2881 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2882 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2883 | } |
2884 | ||
a1b2278e CK |
2885 | /* |
2886 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2887 | */ | |
0583236e | 2888 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2889 | { |
a1b2278e CK |
2890 | struct intel_crtc_scaler_state *scaler_state; |
2891 | int i; | |
2892 | ||
a1b2278e CK |
2893 | scaler_state = &intel_crtc->config->scaler_state; |
2894 | ||
2895 | /* loop through and disable scalers that aren't in use */ | |
2896 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2897 | if (!scaler_state->scalers[i].in_use) |
2898 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2899 | } |
2900 | } | |
2901 | ||
6156a456 | 2902 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2903 | { |
6156a456 | 2904 | switch (pixel_format) { |
d161cf7a | 2905 | case DRM_FORMAT_C8: |
c34ce3d1 | 2906 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2907 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2908 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2909 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2910 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2911 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2912 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2913 | /* |
2914 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2915 | * to be already pre-multiplied. We need to add a knob (or a different | |
2916 | * DRM_FORMAT) for user-space to configure that. | |
2917 | */ | |
f75fb42a | 2918 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2919 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2920 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2921 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2922 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2923 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2924 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2925 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2926 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2927 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2928 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2929 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2930 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2931 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2932 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2933 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2934 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2935 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2936 | default: |
4249eeef | 2937 | MISSING_CASE(pixel_format); |
70d21f0e | 2938 | } |
8cfcba41 | 2939 | |
c34ce3d1 | 2940 | return 0; |
6156a456 | 2941 | } |
70d21f0e | 2942 | |
6156a456 CK |
2943 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2944 | { | |
6156a456 | 2945 | switch (fb_modifier) { |
30af77c4 | 2946 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2947 | break; |
30af77c4 | 2948 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2949 | return PLANE_CTL_TILED_X; |
b321803d | 2950 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2951 | return PLANE_CTL_TILED_Y; |
b321803d | 2952 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2953 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2954 | default: |
6156a456 | 2955 | MISSING_CASE(fb_modifier); |
70d21f0e | 2956 | } |
8cfcba41 | 2957 | |
c34ce3d1 | 2958 | return 0; |
6156a456 | 2959 | } |
70d21f0e | 2960 | |
6156a456 CK |
2961 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2962 | { | |
3b7a5119 | 2963 | switch (rotation) { |
6156a456 CK |
2964 | case BIT(DRM_ROTATE_0): |
2965 | break; | |
1e8df167 SJ |
2966 | /* |
2967 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2968 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2969 | */ | |
3b7a5119 | 2970 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2971 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2972 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2973 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2974 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2975 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2976 | default: |
2977 | MISSING_CASE(rotation); | |
2978 | } | |
2979 | ||
c34ce3d1 | 2980 | return 0; |
6156a456 CK |
2981 | } |
2982 | ||
a8d201af ML |
2983 | static void skylake_update_primary_plane(struct drm_plane *plane, |
2984 | const struct intel_crtc_state *crtc_state, | |
2985 | const struct intel_plane_state *plane_state) | |
6156a456 | 2986 | { |
a8d201af | 2987 | struct drm_device *dev = plane->dev; |
fac5e23e | 2988 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2989 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2990 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2991 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
2992 | int pipe = intel_crtc->pipe; |
2993 | u32 plane_ctl, stride_div, stride; | |
2994 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 2995 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 2996 | int x_offset, y_offset; |
44eb0cb9 | 2997 | u32 surf_addr; |
a8d201af ML |
2998 | int scaler_id = plane_state->scaler_id; |
2999 | int src_x = plane_state->src.x1 >> 16; | |
3000 | int src_y = plane_state->src.y1 >> 16; | |
3001 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3002 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3003 | int dst_x = plane_state->dst.x1; | |
3004 | int dst_y = plane_state->dst.y1; | |
3005 | int dst_w = drm_rect_width(&plane_state->dst); | |
3006 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3007 | |
6156a456 CK |
3008 | plane_ctl = PLANE_CTL_ENABLE | |
3009 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3010 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3011 | ||
3012 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3013 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3014 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3015 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3016 | ||
7b49f948 | 3017 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3018 | fb->pixel_format); |
dedf278c | 3019 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3020 | |
a42e5a23 PZ |
3021 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3022 | ||
3b7a5119 | 3023 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3024 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3025 | ||
3b7a5119 | 3026 | /* stride = Surface height in tiles */ |
832be82f | 3027 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3028 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3029 | x_offset = stride * tile_height - src_y - src_h; |
3030 | y_offset = src_x; | |
6156a456 | 3031 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3032 | } else { |
3033 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3034 | x_offset = src_x; |
3035 | y_offset = src_y; | |
6156a456 | 3036 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3037 | } |
3038 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3039 | |
2db3366b PZ |
3040 | intel_crtc->adjusted_x = x_offset; |
3041 | intel_crtc->adjusted_y = y_offset; | |
3042 | ||
70d21f0e | 3043 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3044 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3045 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3046 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3047 | |
3048 | if (scaler_id >= 0) { | |
3049 | uint32_t ps_ctrl = 0; | |
3050 | ||
3051 | WARN_ON(!dst_w || !dst_h); | |
3052 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3053 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3054 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3055 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3056 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3057 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3058 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3059 | } else { | |
3060 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3061 | } | |
3062 | ||
121920fa | 3063 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3064 | |
3065 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3066 | } | |
3067 | ||
a8d201af ML |
3068 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3069 | struct drm_crtc *crtc) | |
17638cd6 JB |
3070 | { |
3071 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3072 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af | 3073 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3074 | |
a8d201af ML |
3075 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3076 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3077 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3078 | } | |
29b9bde6 | 3079 | |
a8d201af ML |
3080 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3081 | static int | |
3082 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3083 | int x, int y, enum mode_set_atomic state) | |
3084 | { | |
3085 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3086 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3087 | ||
3088 | return -ENODEV; | |
81255565 JB |
3089 | } |
3090 | ||
5a21b665 DV |
3091 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3092 | { | |
3093 | struct intel_crtc *crtc; | |
3094 | ||
91c8a326 | 3095 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3096 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3097 | } | |
3098 | ||
7514747d VS |
3099 | static void intel_update_primary_planes(struct drm_device *dev) |
3100 | { | |
7514747d | 3101 | struct drm_crtc *crtc; |
96a02917 | 3102 | |
70e1e0ec | 3103 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3104 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3105 | struct intel_plane_state *plane_state; | |
96a02917 | 3106 | |
11c22da6 | 3107 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3108 | plane_state = to_intel_plane_state(plane->base.state); |
3109 | ||
a8d201af ML |
3110 | if (plane_state->visible) |
3111 | plane->update_plane(&plane->base, | |
3112 | to_intel_crtc_state(crtc->state), | |
3113 | plane_state); | |
11c22da6 ML |
3114 | |
3115 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3116 | } |
3117 | } | |
3118 | ||
c033666a | 3119 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d VS |
3120 | { |
3121 | /* no reset support for gen2 */ | |
c033666a | 3122 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3123 | return; |
3124 | ||
3125 | /* reset doesn't touch the display */ | |
c033666a | 3126 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
7514747d VS |
3127 | return; |
3128 | ||
91c8a326 | 3129 | drm_modeset_lock_all(&dev_priv->drm); |
f98ce92f VS |
3130 | /* |
3131 | * Disabling the crtcs gracefully seems nicer. Also the | |
3132 | * g33 docs say we should at least disable all the planes. | |
3133 | */ | |
91c8a326 | 3134 | intel_display_suspend(&dev_priv->drm); |
7514747d VS |
3135 | } |
3136 | ||
c033666a | 3137 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3138 | { |
5a21b665 DV |
3139 | /* |
3140 | * Flips in the rings will be nuked by the reset, | |
3141 | * so complete all pending flips so that user space | |
3142 | * will get its events and not get stuck. | |
3143 | */ | |
3144 | intel_complete_page_flips(dev_priv); | |
3145 | ||
7514747d | 3146 | /* no reset support for gen2 */ |
c033666a | 3147 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3148 | return; |
3149 | ||
3150 | /* reset doesn't touch the display */ | |
c033666a | 3151 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
7514747d VS |
3152 | /* |
3153 | * Flips in the rings have been nuked by the reset, | |
3154 | * so update the base address of all primary | |
3155 | * planes to the the last fb to make sure we're | |
3156 | * showing the correct fb after a reset. | |
11c22da6 ML |
3157 | * |
3158 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3159 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d | 3160 | */ |
91c8a326 | 3161 | intel_update_primary_planes(&dev_priv->drm); |
7514747d VS |
3162 | return; |
3163 | } | |
3164 | ||
3165 | /* | |
3166 | * The display has been reset as well, | |
3167 | * so need a full re-initialization. | |
3168 | */ | |
3169 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3170 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3171 | ||
91c8a326 | 3172 | intel_modeset_init_hw(&dev_priv->drm); |
7514747d VS |
3173 | |
3174 | spin_lock_irq(&dev_priv->irq_lock); | |
3175 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 3176 | dev_priv->display.hpd_irq_setup(dev_priv); |
7514747d VS |
3177 | spin_unlock_irq(&dev_priv->irq_lock); |
3178 | ||
91c8a326 | 3179 | intel_display_resume(&dev_priv->drm); |
7514747d VS |
3180 | |
3181 | intel_hpd_init(dev_priv); | |
3182 | ||
91c8a326 | 3183 | drm_modeset_unlock_all(&dev_priv->drm); |
7514747d VS |
3184 | } |
3185 | ||
7d5e3799 CW |
3186 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3187 | { | |
5a21b665 DV |
3188 | struct drm_device *dev = crtc->dev; |
3189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3190 | unsigned reset_counter; | |
3191 | bool pending; | |
3192 | ||
3193 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3194 | if (intel_crtc->reset_counter != reset_counter) | |
3195 | return false; | |
3196 | ||
3197 | spin_lock_irq(&dev->event_lock); | |
3198 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3199 | spin_unlock_irq(&dev->event_lock); | |
3200 | ||
3201 | return pending; | |
7d5e3799 CW |
3202 | } |
3203 | ||
bfd16b2a ML |
3204 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3205 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3206 | { |
3207 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3208 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3209 | struct intel_crtc_state *pipe_config = |
3210 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3211 | |
bfd16b2a ML |
3212 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3213 | crtc->base.mode = crtc->base.state->mode; | |
3214 | ||
3215 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3216 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3217 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3218 | |
3219 | /* | |
3220 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3221 | * that in compute_mode_changes we check the native mode (not the pfit | |
3222 | * mode) to see if we can flip rather than do a full mode set. In the | |
3223 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3224 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3225 | * sized surface. | |
e30e8f75 GP |
3226 | */ |
3227 | ||
e30e8f75 | 3228 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3229 | ((pipe_config->pipe_src_w - 1) << 16) | |
3230 | (pipe_config->pipe_src_h - 1)); | |
3231 | ||
3232 | /* on skylake this is done by detaching scalers */ | |
3233 | if (INTEL_INFO(dev)->gen >= 9) { | |
3234 | skl_detach_scalers(crtc); | |
3235 | ||
3236 | if (pipe_config->pch_pfit.enabled) | |
3237 | skylake_pfit_enable(crtc); | |
3238 | } else if (HAS_PCH_SPLIT(dev)) { | |
3239 | if (pipe_config->pch_pfit.enabled) | |
3240 | ironlake_pfit_enable(crtc); | |
3241 | else if (old_crtc_state->pch_pfit.enabled) | |
3242 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3243 | } |
e30e8f75 GP |
3244 | } |
3245 | ||
5e84e1a4 ZW |
3246 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3247 | { | |
3248 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3249 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3250 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3251 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3252 | i915_reg_t reg; |
3253 | u32 temp; | |
5e84e1a4 ZW |
3254 | |
3255 | /* enable normal train */ | |
3256 | reg = FDI_TX_CTL(pipe); | |
3257 | temp = I915_READ(reg); | |
61e499bf | 3258 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3259 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3260 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3261 | } else { |
3262 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3263 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3264 | } |
5e84e1a4 ZW |
3265 | I915_WRITE(reg, temp); |
3266 | ||
3267 | reg = FDI_RX_CTL(pipe); | |
3268 | temp = I915_READ(reg); | |
3269 | if (HAS_PCH_CPT(dev)) { | |
3270 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3271 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3272 | } else { | |
3273 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3274 | temp |= FDI_LINK_TRAIN_NONE; | |
3275 | } | |
3276 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3277 | ||
3278 | /* wait one idle pattern time */ | |
3279 | POSTING_READ(reg); | |
3280 | udelay(1000); | |
357555c0 JB |
3281 | |
3282 | /* IVB wants error correction enabled */ | |
3283 | if (IS_IVYBRIDGE(dev)) | |
3284 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3285 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3286 | } |
3287 | ||
8db9d77b ZW |
3288 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3289 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3290 | { | |
3291 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3292 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3294 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3295 | i915_reg_t reg; |
3296 | u32 temp, tries; | |
8db9d77b | 3297 | |
1c8562f6 | 3298 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3299 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3300 | |
e1a44743 AJ |
3301 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3302 | for train result */ | |
5eddb70b CW |
3303 | reg = FDI_RX_IMR(pipe); |
3304 | temp = I915_READ(reg); | |
e1a44743 AJ |
3305 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3306 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3307 | I915_WRITE(reg, temp); |
3308 | I915_READ(reg); | |
e1a44743 AJ |
3309 | udelay(150); |
3310 | ||
8db9d77b | 3311 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3312 | reg = FDI_TX_CTL(pipe); |
3313 | temp = I915_READ(reg); | |
627eb5a3 | 3314 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3315 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3316 | temp &= ~FDI_LINK_TRAIN_NONE; |
3317 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3318 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3319 | |
5eddb70b CW |
3320 | reg = FDI_RX_CTL(pipe); |
3321 | temp = I915_READ(reg); | |
8db9d77b ZW |
3322 | temp &= ~FDI_LINK_TRAIN_NONE; |
3323 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3324 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3325 | ||
3326 | POSTING_READ(reg); | |
8db9d77b ZW |
3327 | udelay(150); |
3328 | ||
5b2adf89 | 3329 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3330 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3331 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3332 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3333 | |
5eddb70b | 3334 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3335 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3336 | temp = I915_READ(reg); |
8db9d77b ZW |
3337 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3338 | ||
3339 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3340 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3341 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3342 | break; |
3343 | } | |
8db9d77b | 3344 | } |
e1a44743 | 3345 | if (tries == 5) |
5eddb70b | 3346 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3347 | |
3348 | /* Train 2 */ | |
5eddb70b CW |
3349 | reg = FDI_TX_CTL(pipe); |
3350 | temp = I915_READ(reg); | |
8db9d77b ZW |
3351 | temp &= ~FDI_LINK_TRAIN_NONE; |
3352 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3353 | I915_WRITE(reg, temp); |
8db9d77b | 3354 | |
5eddb70b CW |
3355 | reg = FDI_RX_CTL(pipe); |
3356 | temp = I915_READ(reg); | |
8db9d77b ZW |
3357 | temp &= ~FDI_LINK_TRAIN_NONE; |
3358 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3359 | I915_WRITE(reg, temp); |
8db9d77b | 3360 | |
5eddb70b CW |
3361 | POSTING_READ(reg); |
3362 | udelay(150); | |
8db9d77b | 3363 | |
5eddb70b | 3364 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3365 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3366 | temp = I915_READ(reg); |
8db9d77b ZW |
3367 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3368 | ||
3369 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3370 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3371 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3372 | break; | |
3373 | } | |
8db9d77b | 3374 | } |
e1a44743 | 3375 | if (tries == 5) |
5eddb70b | 3376 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3377 | |
3378 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3379 | |
8db9d77b ZW |
3380 | } |
3381 | ||
0206e353 | 3382 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3383 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3384 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3385 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3386 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3387 | }; | |
3388 | ||
3389 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3390 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3391 | { | |
3392 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3393 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3395 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3396 | i915_reg_t reg; |
3397 | u32 temp, i, retry; | |
8db9d77b | 3398 | |
e1a44743 AJ |
3399 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3400 | for train result */ | |
5eddb70b CW |
3401 | reg = FDI_RX_IMR(pipe); |
3402 | temp = I915_READ(reg); | |
e1a44743 AJ |
3403 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3404 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3405 | I915_WRITE(reg, temp); |
3406 | ||
3407 | POSTING_READ(reg); | |
e1a44743 AJ |
3408 | udelay(150); |
3409 | ||
8db9d77b | 3410 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3411 | reg = FDI_TX_CTL(pipe); |
3412 | temp = I915_READ(reg); | |
627eb5a3 | 3413 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3414 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3415 | temp &= ~FDI_LINK_TRAIN_NONE; |
3416 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3417 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3418 | /* SNB-B */ | |
3419 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3420 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3421 | |
d74cf324 DV |
3422 | I915_WRITE(FDI_RX_MISC(pipe), |
3423 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3424 | ||
5eddb70b CW |
3425 | reg = FDI_RX_CTL(pipe); |
3426 | temp = I915_READ(reg); | |
8db9d77b ZW |
3427 | if (HAS_PCH_CPT(dev)) { |
3428 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3429 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3430 | } else { | |
3431 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3432 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3433 | } | |
5eddb70b CW |
3434 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3435 | ||
3436 | POSTING_READ(reg); | |
8db9d77b ZW |
3437 | udelay(150); |
3438 | ||
0206e353 | 3439 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3440 | reg = FDI_TX_CTL(pipe); |
3441 | temp = I915_READ(reg); | |
8db9d77b ZW |
3442 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3443 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3444 | I915_WRITE(reg, temp); |
3445 | ||
3446 | POSTING_READ(reg); | |
8db9d77b ZW |
3447 | udelay(500); |
3448 | ||
fa37d39e SP |
3449 | for (retry = 0; retry < 5; retry++) { |
3450 | reg = FDI_RX_IIR(pipe); | |
3451 | temp = I915_READ(reg); | |
3452 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3453 | if (temp & FDI_RX_BIT_LOCK) { | |
3454 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3455 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3456 | break; | |
3457 | } | |
3458 | udelay(50); | |
8db9d77b | 3459 | } |
fa37d39e SP |
3460 | if (retry < 5) |
3461 | break; | |
8db9d77b ZW |
3462 | } |
3463 | if (i == 4) | |
5eddb70b | 3464 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3465 | |
3466 | /* Train 2 */ | |
5eddb70b CW |
3467 | reg = FDI_TX_CTL(pipe); |
3468 | temp = I915_READ(reg); | |
8db9d77b ZW |
3469 | temp &= ~FDI_LINK_TRAIN_NONE; |
3470 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3471 | if (IS_GEN6(dev)) { | |
3472 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3473 | /* SNB-B */ | |
3474 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3475 | } | |
5eddb70b | 3476 | I915_WRITE(reg, temp); |
8db9d77b | 3477 | |
5eddb70b CW |
3478 | reg = FDI_RX_CTL(pipe); |
3479 | temp = I915_READ(reg); | |
8db9d77b ZW |
3480 | if (HAS_PCH_CPT(dev)) { |
3481 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3482 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3483 | } else { | |
3484 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3485 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3486 | } | |
5eddb70b CW |
3487 | I915_WRITE(reg, temp); |
3488 | ||
3489 | POSTING_READ(reg); | |
8db9d77b ZW |
3490 | udelay(150); |
3491 | ||
0206e353 | 3492 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3493 | reg = FDI_TX_CTL(pipe); |
3494 | temp = I915_READ(reg); | |
8db9d77b ZW |
3495 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3496 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3497 | I915_WRITE(reg, temp); |
3498 | ||
3499 | POSTING_READ(reg); | |
8db9d77b ZW |
3500 | udelay(500); |
3501 | ||
fa37d39e SP |
3502 | for (retry = 0; retry < 5; retry++) { |
3503 | reg = FDI_RX_IIR(pipe); | |
3504 | temp = I915_READ(reg); | |
3505 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3506 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3507 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3508 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3509 | break; | |
3510 | } | |
3511 | udelay(50); | |
8db9d77b | 3512 | } |
fa37d39e SP |
3513 | if (retry < 5) |
3514 | break; | |
8db9d77b ZW |
3515 | } |
3516 | if (i == 4) | |
5eddb70b | 3517 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3518 | |
3519 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3520 | } | |
3521 | ||
357555c0 JB |
3522 | /* Manual link training for Ivy Bridge A0 parts */ |
3523 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3524 | { | |
3525 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3526 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3527 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3528 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3529 | i915_reg_t reg; |
3530 | u32 temp, i, j; | |
357555c0 JB |
3531 | |
3532 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3533 | for train result */ | |
3534 | reg = FDI_RX_IMR(pipe); | |
3535 | temp = I915_READ(reg); | |
3536 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3537 | temp &= ~FDI_RX_BIT_LOCK; | |
3538 | I915_WRITE(reg, temp); | |
3539 | ||
3540 | POSTING_READ(reg); | |
3541 | udelay(150); | |
3542 | ||
01a415fd DV |
3543 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3544 | I915_READ(FDI_RX_IIR(pipe))); | |
3545 | ||
139ccd3f JB |
3546 | /* Try each vswing and preemphasis setting twice before moving on */ |
3547 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3548 | /* disable first in case we need to retry */ | |
3549 | reg = FDI_TX_CTL(pipe); | |
3550 | temp = I915_READ(reg); | |
3551 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3552 | temp &= ~FDI_TX_ENABLE; | |
3553 | I915_WRITE(reg, temp); | |
357555c0 | 3554 | |
139ccd3f JB |
3555 | reg = FDI_RX_CTL(pipe); |
3556 | temp = I915_READ(reg); | |
3557 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3558 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3559 | temp &= ~FDI_RX_ENABLE; | |
3560 | I915_WRITE(reg, temp); | |
357555c0 | 3561 | |
139ccd3f | 3562 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3563 | reg = FDI_TX_CTL(pipe); |
3564 | temp = I915_READ(reg); | |
139ccd3f | 3565 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3566 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3567 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3568 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3569 | temp |= snb_b_fdi_train_param[j/2]; |
3570 | temp |= FDI_COMPOSITE_SYNC; | |
3571 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3572 | |
139ccd3f JB |
3573 | I915_WRITE(FDI_RX_MISC(pipe), |
3574 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3575 | |
139ccd3f | 3576 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3577 | temp = I915_READ(reg); |
139ccd3f JB |
3578 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3579 | temp |= FDI_COMPOSITE_SYNC; | |
3580 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3581 | |
139ccd3f JB |
3582 | POSTING_READ(reg); |
3583 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3584 | |
139ccd3f JB |
3585 | for (i = 0; i < 4; i++) { |
3586 | reg = FDI_RX_IIR(pipe); | |
3587 | temp = I915_READ(reg); | |
3588 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3589 | |
139ccd3f JB |
3590 | if (temp & FDI_RX_BIT_LOCK || |
3591 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3592 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3593 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3594 | i); | |
3595 | break; | |
3596 | } | |
3597 | udelay(1); /* should be 0.5us */ | |
3598 | } | |
3599 | if (i == 4) { | |
3600 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3601 | continue; | |
3602 | } | |
357555c0 | 3603 | |
139ccd3f | 3604 | /* Train 2 */ |
357555c0 JB |
3605 | reg = FDI_TX_CTL(pipe); |
3606 | temp = I915_READ(reg); | |
139ccd3f JB |
3607 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3608 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3609 | I915_WRITE(reg, temp); | |
3610 | ||
3611 | reg = FDI_RX_CTL(pipe); | |
3612 | temp = I915_READ(reg); | |
3613 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3614 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3615 | I915_WRITE(reg, temp); |
3616 | ||
3617 | POSTING_READ(reg); | |
139ccd3f | 3618 | udelay(2); /* should be 1.5us */ |
357555c0 | 3619 | |
139ccd3f JB |
3620 | for (i = 0; i < 4; i++) { |
3621 | reg = FDI_RX_IIR(pipe); | |
3622 | temp = I915_READ(reg); | |
3623 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3624 | |
139ccd3f JB |
3625 | if (temp & FDI_RX_SYMBOL_LOCK || |
3626 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3627 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3628 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3629 | i); | |
3630 | goto train_done; | |
3631 | } | |
3632 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3633 | } |
139ccd3f JB |
3634 | if (i == 4) |
3635 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3636 | } |
357555c0 | 3637 | |
139ccd3f | 3638 | train_done: |
357555c0 JB |
3639 | DRM_DEBUG_KMS("FDI train done.\n"); |
3640 | } | |
3641 | ||
88cefb6c | 3642 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3643 | { |
88cefb6c | 3644 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 3645 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 3646 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3647 | i915_reg_t reg; |
3648 | u32 temp; | |
c64e311e | 3649 | |
c98e9dcf | 3650 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3651 | reg = FDI_RX_CTL(pipe); |
3652 | temp = I915_READ(reg); | |
627eb5a3 | 3653 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3654 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3655 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3656 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3657 | ||
3658 | POSTING_READ(reg); | |
c98e9dcf JB |
3659 | udelay(200); |
3660 | ||
3661 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3662 | temp = I915_READ(reg); |
3663 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3664 | ||
3665 | POSTING_READ(reg); | |
c98e9dcf JB |
3666 | udelay(200); |
3667 | ||
20749730 PZ |
3668 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3669 | reg = FDI_TX_CTL(pipe); | |
3670 | temp = I915_READ(reg); | |
3671 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3672 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3673 | |
20749730 PZ |
3674 | POSTING_READ(reg); |
3675 | udelay(100); | |
6be4a607 | 3676 | } |
0e23b99d JB |
3677 | } |
3678 | ||
88cefb6c DV |
3679 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3680 | { | |
3681 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3682 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 3683 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3684 | i915_reg_t reg; |
3685 | u32 temp; | |
88cefb6c DV |
3686 | |
3687 | /* Switch from PCDclk to Rawclk */ | |
3688 | reg = FDI_RX_CTL(pipe); | |
3689 | temp = I915_READ(reg); | |
3690 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3691 | ||
3692 | /* Disable CPU FDI TX PLL */ | |
3693 | reg = FDI_TX_CTL(pipe); | |
3694 | temp = I915_READ(reg); | |
3695 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3696 | ||
3697 | POSTING_READ(reg); | |
3698 | udelay(100); | |
3699 | ||
3700 | reg = FDI_RX_CTL(pipe); | |
3701 | temp = I915_READ(reg); | |
3702 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3703 | ||
3704 | /* Wait for the clocks to turn off. */ | |
3705 | POSTING_READ(reg); | |
3706 | udelay(100); | |
3707 | } | |
3708 | ||
0fc932b8 JB |
3709 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3710 | { | |
3711 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3712 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
3713 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3714 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3715 | i915_reg_t reg; |
3716 | u32 temp; | |
0fc932b8 JB |
3717 | |
3718 | /* disable CPU FDI tx and PCH FDI rx */ | |
3719 | reg = FDI_TX_CTL(pipe); | |
3720 | temp = I915_READ(reg); | |
3721 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3722 | POSTING_READ(reg); | |
3723 | ||
3724 | reg = FDI_RX_CTL(pipe); | |
3725 | temp = I915_READ(reg); | |
3726 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3727 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3728 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3729 | ||
3730 | POSTING_READ(reg); | |
3731 | udelay(100); | |
3732 | ||
3733 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3734 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3735 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3736 | |
3737 | /* still set train pattern 1 */ | |
3738 | reg = FDI_TX_CTL(pipe); | |
3739 | temp = I915_READ(reg); | |
3740 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3741 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3742 | I915_WRITE(reg, temp); | |
3743 | ||
3744 | reg = FDI_RX_CTL(pipe); | |
3745 | temp = I915_READ(reg); | |
3746 | if (HAS_PCH_CPT(dev)) { | |
3747 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3748 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3749 | } else { | |
3750 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3751 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3752 | } | |
3753 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3754 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3755 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3756 | I915_WRITE(reg, temp); |
3757 | ||
3758 | POSTING_READ(reg); | |
3759 | udelay(100); | |
3760 | } | |
3761 | ||
5dce5b93 CW |
3762 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3763 | { | |
3764 | struct intel_crtc *crtc; | |
3765 | ||
3766 | /* Note that we don't need to be called with mode_config.lock here | |
3767 | * as our list of CRTC objects is static for the lifetime of the | |
3768 | * device and so cannot disappear as we iterate. Similarly, we can | |
3769 | * happily treat the predicates as racy, atomic checks as userspace | |
3770 | * cannot claim and pin a new fb without at least acquring the | |
3771 | * struct_mutex and so serialising with us. | |
3772 | */ | |
d3fcc808 | 3773 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3774 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3775 | continue; | |
3776 | ||
5a21b665 | 3777 | if (crtc->flip_work) |
5dce5b93 CW |
3778 | intel_wait_for_vblank(dev, crtc->pipe); |
3779 | ||
3780 | return true; | |
3781 | } | |
3782 | ||
3783 | return false; | |
3784 | } | |
3785 | ||
5a21b665 | 3786 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
3787 | { |
3788 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
3789 | struct intel_flip_work *work = intel_crtc->flip_work; |
3790 | ||
3791 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
3792 | |
3793 | if (work->event) | |
560ce1dc | 3794 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
3795 | |
3796 | drm_crtc_vblank_put(&intel_crtc->base); | |
3797 | ||
5a21b665 | 3798 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 3799 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
3800 | |
3801 | trace_i915_flip_complete(intel_crtc->plane, | |
3802 | work->pending_flip_obj); | |
d6bbafa1 CW |
3803 | } |
3804 | ||
5008e874 | 3805 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3806 | { |
0f91128d | 3807 | struct drm_device *dev = crtc->dev; |
fac5e23e | 3808 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 3809 | long ret; |
e6c3a2a6 | 3810 | |
2c10d571 | 3811 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3812 | |
3813 | ret = wait_event_interruptible_timeout( | |
3814 | dev_priv->pending_flip_queue, | |
3815 | !intel_crtc_has_pending_flip(crtc), | |
3816 | 60*HZ); | |
3817 | ||
3818 | if (ret < 0) | |
3819 | return ret; | |
3820 | ||
5a21b665 DV |
3821 | if (ret == 0) { |
3822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3823 | struct intel_flip_work *work; | |
3824 | ||
3825 | spin_lock_irq(&dev->event_lock); | |
3826 | work = intel_crtc->flip_work; | |
3827 | if (work && !is_mmio_work(work)) { | |
3828 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3829 | page_flip_completed(intel_crtc); | |
3830 | } | |
3831 | spin_unlock_irq(&dev->event_lock); | |
3832 | } | |
5bb61643 | 3833 | |
5008e874 | 3834 | return 0; |
e6c3a2a6 CW |
3835 | } |
3836 | ||
060f02d8 VS |
3837 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3838 | { | |
3839 | u32 temp; | |
3840 | ||
3841 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3842 | ||
3843 | mutex_lock(&dev_priv->sb_lock); | |
3844 | ||
3845 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3846 | temp |= SBI_SSCCTL_DISABLE; | |
3847 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3848 | ||
3849 | mutex_unlock(&dev_priv->sb_lock); | |
3850 | } | |
3851 | ||
e615efe4 ED |
3852 | /* Program iCLKIP clock to the desired frequency */ |
3853 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3854 | { | |
64b46a06 | 3855 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3856 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3857 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3858 | u32 temp; | |
3859 | ||
060f02d8 | 3860 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3861 | |
64b46a06 VS |
3862 | /* The iCLK virtual clock root frequency is in MHz, |
3863 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3864 | * divisors, it is necessary to divide one by another, so we | |
3865 | * convert the virtual clock precision to KHz here for higher | |
3866 | * precision. | |
3867 | */ | |
3868 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3869 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3870 | u32 iclk_pi_range = 64; | |
64b46a06 | 3871 | u32 desired_divisor; |
e615efe4 | 3872 | |
64b46a06 VS |
3873 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3874 | clock << auxdiv); | |
3875 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3876 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3877 | |
64b46a06 VS |
3878 | /* |
3879 | * Near 20MHz is a corner case which is | |
3880 | * out of range for the 7-bit divisor | |
3881 | */ | |
3882 | if (divsel <= 0x7f) | |
3883 | break; | |
e615efe4 ED |
3884 | } |
3885 | ||
3886 | /* This should not happen with any sane values */ | |
3887 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3888 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3889 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3890 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3891 | ||
3892 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3893 | clock, |
e615efe4 ED |
3894 | auxdiv, |
3895 | divsel, | |
3896 | phasedir, | |
3897 | phaseinc); | |
3898 | ||
060f02d8 VS |
3899 | mutex_lock(&dev_priv->sb_lock); |
3900 | ||
e615efe4 | 3901 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3902 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3903 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3904 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3905 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3906 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3907 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3908 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3909 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3910 | |
3911 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3912 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3913 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3914 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3915 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3916 | |
3917 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3918 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3919 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3920 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3921 | |
060f02d8 VS |
3922 | mutex_unlock(&dev_priv->sb_lock); |
3923 | ||
e615efe4 ED |
3924 | /* Wait for initialization time */ |
3925 | udelay(24); | |
3926 | ||
3927 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3928 | } | |
3929 | ||
8802e5b6 VS |
3930 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3931 | { | |
3932 | u32 divsel, phaseinc, auxdiv; | |
3933 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3934 | u32 iclk_pi_range = 64; | |
3935 | u32 desired_divisor; | |
3936 | u32 temp; | |
3937 | ||
3938 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3939 | return 0; | |
3940 | ||
3941 | mutex_lock(&dev_priv->sb_lock); | |
3942 | ||
3943 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3944 | if (temp & SBI_SSCCTL_DISABLE) { | |
3945 | mutex_unlock(&dev_priv->sb_lock); | |
3946 | return 0; | |
3947 | } | |
3948 | ||
3949 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3950 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3951 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3952 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3953 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3954 | ||
3955 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3956 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3957 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3958 | ||
3959 | mutex_unlock(&dev_priv->sb_lock); | |
3960 | ||
3961 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3962 | ||
3963 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3964 | desired_divisor << auxdiv); | |
3965 | } | |
3966 | ||
275f01b2 DV |
3967 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3968 | enum pipe pch_transcoder) | |
3969 | { | |
3970 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3971 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 3972 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3973 | |
3974 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3975 | I915_READ(HTOTAL(cpu_transcoder))); | |
3976 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3977 | I915_READ(HBLANK(cpu_transcoder))); | |
3978 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3979 | I915_READ(HSYNC(cpu_transcoder))); | |
3980 | ||
3981 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3982 | I915_READ(VTOTAL(cpu_transcoder))); | |
3983 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3984 | I915_READ(VBLANK(cpu_transcoder))); | |
3985 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3986 | I915_READ(VSYNC(cpu_transcoder))); | |
3987 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3988 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3989 | } | |
3990 | ||
003632d9 | 3991 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 3992 | { |
fac5e23e | 3993 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
3994 | uint32_t temp; |
3995 | ||
3996 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3997 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3998 | return; |
3999 | ||
4000 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4001 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4002 | ||
003632d9 ACO |
4003 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4004 | if (enable) | |
4005 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4006 | ||
4007 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4008 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4009 | POSTING_READ(SOUTH_CHICKEN1); | |
4010 | } | |
4011 | ||
4012 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4013 | { | |
4014 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4015 | |
4016 | switch (intel_crtc->pipe) { | |
4017 | case PIPE_A: | |
4018 | break; | |
4019 | case PIPE_B: | |
6e3c9717 | 4020 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4021 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4022 | else |
003632d9 | 4023 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4024 | |
4025 | break; | |
4026 | case PIPE_C: | |
003632d9 | 4027 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4028 | |
4029 | break; | |
4030 | default: | |
4031 | BUG(); | |
4032 | } | |
4033 | } | |
4034 | ||
c48b5305 VS |
4035 | /* Return which DP Port should be selected for Transcoder DP control */ |
4036 | static enum port | |
4037 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4038 | { | |
4039 | struct drm_device *dev = crtc->dev; | |
4040 | struct intel_encoder *encoder; | |
4041 | ||
4042 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4043 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4044 | encoder->type == INTEL_OUTPUT_EDP) |
4045 | return enc_to_dig_port(&encoder->base)->port; | |
4046 | } | |
4047 | ||
4048 | return -1; | |
4049 | } | |
4050 | ||
f67a559d JB |
4051 | /* |
4052 | * Enable PCH resources required for PCH ports: | |
4053 | * - PCH PLLs | |
4054 | * - FDI training & RX/TX | |
4055 | * - update transcoder timings | |
4056 | * - DP transcoding bits | |
4057 | * - transcoder | |
4058 | */ | |
4059 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4060 | { |
4061 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4062 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4064 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4065 | u32 temp; |
2c07245f | 4066 | |
ab9412ba | 4067 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4068 | |
1fbc0d78 DV |
4069 | if (IS_IVYBRIDGE(dev)) |
4070 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4071 | ||
cd986abb DV |
4072 | /* Write the TU size bits before fdi link training, so that error |
4073 | * detection works. */ | |
4074 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4075 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4076 | ||
c98e9dcf | 4077 | /* For PCH output, training FDI link */ |
674cf967 | 4078 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4079 | |
3ad8a208 DV |
4080 | /* We need to program the right clock selection before writing the pixel |
4081 | * mutliplier into the DPLL. */ | |
303b81e0 | 4082 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4083 | u32 sel; |
4b645f14 | 4084 | |
c98e9dcf | 4085 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4086 | temp |= TRANS_DPLL_ENABLE(pipe); |
4087 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4088 | if (intel_crtc->config->shared_dpll == |
4089 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4090 | temp |= sel; |
4091 | else | |
4092 | temp &= ~sel; | |
c98e9dcf | 4093 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4094 | } |
5eddb70b | 4095 | |
3ad8a208 DV |
4096 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4097 | * transcoder, and we actually should do this to not upset any PCH | |
4098 | * transcoder that already use the clock when we share it. | |
4099 | * | |
4100 | * Note that enable_shared_dpll tries to do the right thing, but | |
4101 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4102 | * the right LVDS enable sequence. */ | |
85b3894f | 4103 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4104 | |
d9b6cb56 JB |
4105 | /* set transcoder timing, panel must allow it */ |
4106 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4107 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4108 | |
303b81e0 | 4109 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4110 | |
c98e9dcf | 4111 | /* For PCH DP, enable TRANS_DP_CTL */ |
37a5650b | 4112 | if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) { |
9c4edaee VS |
4113 | const struct drm_display_mode *adjusted_mode = |
4114 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4115 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4116 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4117 | temp = I915_READ(reg); |
4118 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4119 | TRANS_DP_SYNC_MASK | |
4120 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4121 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4122 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4123 | |
9c4edaee | 4124 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4125 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4126 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4127 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4128 | |
4129 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4130 | case PORT_B: |
5eddb70b | 4131 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4132 | break; |
c48b5305 | 4133 | case PORT_C: |
5eddb70b | 4134 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4135 | break; |
c48b5305 | 4136 | case PORT_D: |
5eddb70b | 4137 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4138 | break; |
4139 | default: | |
e95d41e1 | 4140 | BUG(); |
32f9d658 | 4141 | } |
2c07245f | 4142 | |
5eddb70b | 4143 | I915_WRITE(reg, temp); |
6be4a607 | 4144 | } |
b52eb4dc | 4145 | |
b8a4f404 | 4146 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4147 | } |
4148 | ||
1507e5bd PZ |
4149 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4150 | { | |
4151 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4152 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4154 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4155 | |
ab9412ba | 4156 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4157 | |
8c52b5e8 | 4158 | lpt_program_iclkip(crtc); |
1507e5bd | 4159 | |
0540e488 | 4160 | /* Set transcoder timing. */ |
275f01b2 | 4161 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4162 | |
937bb610 | 4163 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4164 | } |
4165 | ||
a1520318 | 4166 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4167 | { |
fac5e23e | 4168 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4169 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4170 | u32 temp; |
4171 | ||
4172 | temp = I915_READ(dslreg); | |
4173 | udelay(500); | |
4174 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4175 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4176 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4177 | } |
4178 | } | |
4179 | ||
86adf9d7 ML |
4180 | static int |
4181 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4182 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4183 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4184 | { |
86adf9d7 ML |
4185 | struct intel_crtc_scaler_state *scaler_state = |
4186 | &crtc_state->scaler_state; | |
4187 | struct intel_crtc *intel_crtc = | |
4188 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4189 | int need_scaling; |
6156a456 CK |
4190 | |
4191 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4192 | (src_h != dst_w || src_w != dst_h): | |
4193 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4194 | |
4195 | /* | |
4196 | * if plane is being disabled or scaler is no more required or force detach | |
4197 | * - free scaler binded to this plane/crtc | |
4198 | * - in order to do this, update crtc->scaler_usage | |
4199 | * | |
4200 | * Here scaler state in crtc_state is set free so that | |
4201 | * scaler can be assigned to other user. Actual register | |
4202 | * update to free the scaler is done in plane/panel-fit programming. | |
4203 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4204 | */ | |
86adf9d7 | 4205 | if (force_detach || !need_scaling) { |
a1b2278e | 4206 | if (*scaler_id >= 0) { |
86adf9d7 | 4207 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4208 | scaler_state->scalers[*scaler_id].in_use = 0; |
4209 | ||
86adf9d7 ML |
4210 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4211 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4212 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4213 | scaler_state->scaler_users); |
4214 | *scaler_id = -1; | |
4215 | } | |
4216 | return 0; | |
4217 | } | |
4218 | ||
4219 | /* range checks */ | |
4220 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4221 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4222 | ||
4223 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4224 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4225 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4226 | "size is out of scaler range\n", |
86adf9d7 | 4227 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4228 | return -EINVAL; |
4229 | } | |
4230 | ||
86adf9d7 ML |
4231 | /* mark this plane as a scaler user in crtc_state */ |
4232 | scaler_state->scaler_users |= (1 << scaler_user); | |
4233 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4234 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4235 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4236 | scaler_state->scaler_users); | |
4237 | ||
4238 | return 0; | |
4239 | } | |
4240 | ||
4241 | /** | |
4242 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4243 | * | |
4244 | * @state: crtc's scaler state | |
86adf9d7 ML |
4245 | * |
4246 | * Return | |
4247 | * 0 - scaler_usage updated successfully | |
4248 | * error - requested scaling cannot be supported or other error condition | |
4249 | */ | |
e435d6e5 | 4250 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4251 | { |
4252 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4253 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4254 | |
78108b7c VS |
4255 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4256 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4257 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4258 | |
e435d6e5 | 4259 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4260 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4261 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4262 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4263 | } |
4264 | ||
4265 | /** | |
4266 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4267 | * | |
4268 | * @state: crtc's scaler state | |
86adf9d7 ML |
4269 | * @plane_state: atomic plane state to update |
4270 | * | |
4271 | * Return | |
4272 | * 0 - scaler_usage updated successfully | |
4273 | * error - requested scaling cannot be supported or other error condition | |
4274 | */ | |
da20eabd ML |
4275 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4276 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4277 | { |
4278 | ||
4279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4280 | struct intel_plane *intel_plane = |
4281 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4282 | struct drm_framebuffer *fb = plane_state->base.fb; |
4283 | int ret; | |
4284 | ||
4285 | bool force_detach = !fb || !plane_state->visible; | |
4286 | ||
72660ce0 VS |
4287 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4288 | intel_plane->base.base.id, intel_plane->base.name, | |
4289 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4290 | |
4291 | ret = skl_update_scaler(crtc_state, force_detach, | |
4292 | drm_plane_index(&intel_plane->base), | |
4293 | &plane_state->scaler_id, | |
4294 | plane_state->base.rotation, | |
4295 | drm_rect_width(&plane_state->src) >> 16, | |
4296 | drm_rect_height(&plane_state->src) >> 16, | |
4297 | drm_rect_width(&plane_state->dst), | |
4298 | drm_rect_height(&plane_state->dst)); | |
4299 | ||
4300 | if (ret || plane_state->scaler_id < 0) | |
4301 | return ret; | |
4302 | ||
a1b2278e | 4303 | /* check colorkey */ |
818ed961 | 4304 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4305 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4306 | intel_plane->base.base.id, | |
4307 | intel_plane->base.name); | |
a1b2278e CK |
4308 | return -EINVAL; |
4309 | } | |
4310 | ||
4311 | /* Check src format */ | |
86adf9d7 ML |
4312 | switch (fb->pixel_format) { |
4313 | case DRM_FORMAT_RGB565: | |
4314 | case DRM_FORMAT_XBGR8888: | |
4315 | case DRM_FORMAT_XRGB8888: | |
4316 | case DRM_FORMAT_ABGR8888: | |
4317 | case DRM_FORMAT_ARGB8888: | |
4318 | case DRM_FORMAT_XRGB2101010: | |
4319 | case DRM_FORMAT_XBGR2101010: | |
4320 | case DRM_FORMAT_YUYV: | |
4321 | case DRM_FORMAT_YVYU: | |
4322 | case DRM_FORMAT_UYVY: | |
4323 | case DRM_FORMAT_VYUY: | |
4324 | break; | |
4325 | default: | |
72660ce0 VS |
4326 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4327 | intel_plane->base.base.id, intel_plane->base.name, | |
4328 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4329 | return -EINVAL; |
a1b2278e CK |
4330 | } |
4331 | ||
a1b2278e CK |
4332 | return 0; |
4333 | } | |
4334 | ||
e435d6e5 ML |
4335 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4336 | { | |
4337 | int i; | |
4338 | ||
4339 | for (i = 0; i < crtc->num_scalers; i++) | |
4340 | skl_detach_scaler(crtc, i); | |
4341 | } | |
4342 | ||
4343 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4344 | { |
4345 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4346 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4347 | int pipe = crtc->pipe; |
a1b2278e CK |
4348 | struct intel_crtc_scaler_state *scaler_state = |
4349 | &crtc->config->scaler_state; | |
4350 | ||
4351 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4352 | ||
6e3c9717 | 4353 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4354 | int id; |
4355 | ||
4356 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4357 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4358 | return; | |
4359 | } | |
4360 | ||
4361 | id = scaler_state->scaler_id; | |
4362 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4363 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4364 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4365 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4366 | ||
4367 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4368 | } |
4369 | } | |
4370 | ||
b074cec8 JB |
4371 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4372 | { | |
4373 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4374 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4375 | int pipe = crtc->pipe; |
4376 | ||
6e3c9717 | 4377 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4378 | /* Force use of hard-coded filter coefficients |
4379 | * as some pre-programmed values are broken, | |
4380 | * e.g. x201. | |
4381 | */ | |
4382 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4383 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4384 | PF_PIPE_SEL_IVB(pipe)); | |
4385 | else | |
4386 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4387 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4388 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4389 | } |
4390 | } | |
4391 | ||
20bc8673 | 4392 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4393 | { |
cea165c3 | 4394 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4395 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4396 | |
6e3c9717 | 4397 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4398 | return; |
4399 | ||
307e4498 ML |
4400 | /* |
4401 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4402 | * This function is called from post_plane_update, which is run after | |
4403 | * a vblank wait. | |
4404 | */ | |
cea165c3 | 4405 | |
d77e4531 | 4406 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4407 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4408 | mutex_lock(&dev_priv->rps.hw_lock); |
4409 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4410 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4411 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4412 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4413 | * mailbox." Moreover, the mailbox may return a bogus state, |
4414 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4415 | */ |
4416 | } else { | |
4417 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4418 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4419 | * is essentially intel_wait_for_vblank. If we don't have this | |
4420 | * and don't wait for vblanks until the end of crtc_enable, then | |
4421 | * the HW state readout code will complain that the expected | |
4422 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4423 | if (intel_wait_for_register(dev_priv, |
4424 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4425 | 50)) | |
2a114cc1 BW |
4426 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4427 | } | |
d77e4531 PZ |
4428 | } |
4429 | ||
20bc8673 | 4430 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4431 | { |
4432 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4433 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4434 | |
6e3c9717 | 4435 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4436 | return; |
4437 | ||
4438 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4439 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4440 | mutex_lock(&dev_priv->rps.hw_lock); |
4441 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4442 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4443 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4444 | if (intel_wait_for_register(dev_priv, |
4445 | IPS_CTL, IPS_ENABLE, 0, | |
4446 | 42)) | |
23d0b130 | 4447 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4448 | } else { |
2a114cc1 | 4449 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4450 | POSTING_READ(IPS_CTL); |
4451 | } | |
d77e4531 PZ |
4452 | |
4453 | /* We need to wait for a vblank before we can disable the plane. */ | |
4454 | intel_wait_for_vblank(dev, crtc->pipe); | |
4455 | } | |
4456 | ||
7cac945f | 4457 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4458 | { |
7cac945f | 4459 | if (intel_crtc->overlay) { |
d3eedb1a | 4460 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4461 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4462 | |
4463 | mutex_lock(&dev->struct_mutex); | |
4464 | dev_priv->mm.interruptible = false; | |
4465 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4466 | dev_priv->mm.interruptible = true; | |
4467 | mutex_unlock(&dev->struct_mutex); | |
4468 | } | |
4469 | ||
4470 | /* Let userspace switch the overlay on again. In most cases userspace | |
4471 | * has to recompute where to put it anyway. | |
4472 | */ | |
4473 | } | |
4474 | ||
87d4300a ML |
4475 | /** |
4476 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4477 | * @crtc: the CRTC whose primary plane was just enabled | |
4478 | * | |
4479 | * Performs potentially sleeping operations that must be done after the primary | |
4480 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4481 | * called due to an explicit primary plane update, or due to an implicit | |
4482 | * re-enable that is caused when a sprite plane is updated to no longer | |
4483 | * completely hide the primary plane. | |
4484 | */ | |
4485 | static void | |
4486 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4487 | { |
4488 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4489 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4491 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4492 | |
87d4300a ML |
4493 | /* |
4494 | * FIXME IPS should be fine as long as one plane is | |
4495 | * enabled, but in practice it seems to have problems | |
4496 | * when going from primary only to sprite only and vice | |
4497 | * versa. | |
4498 | */ | |
a5c4d7bc VS |
4499 | hsw_enable_ips(intel_crtc); |
4500 | ||
f99d7069 | 4501 | /* |
87d4300a ML |
4502 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4503 | * So don't enable underrun reporting before at least some planes | |
4504 | * are enabled. | |
4505 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4506 | * but leave the pipe running. | |
f99d7069 | 4507 | */ |
87d4300a ML |
4508 | if (IS_GEN2(dev)) |
4509 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4510 | ||
aca7b684 VS |
4511 | /* Underruns don't always raise interrupts, so check manually. */ |
4512 | intel_check_cpu_fifo_underruns(dev_priv); | |
4513 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4514 | } |
4515 | ||
2622a081 | 4516 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4517 | static void |
4518 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4519 | { |
4520 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4521 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4522 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4523 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4524 | |
87d4300a ML |
4525 | /* |
4526 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4527 | * So diasble underrun reporting before all the planes get disabled. | |
4528 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4529 | * but leave the pipe running. | |
4530 | */ | |
4531 | if (IS_GEN2(dev)) | |
4532 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4533 | |
2622a081 VS |
4534 | /* |
4535 | * FIXME IPS should be fine as long as one plane is | |
4536 | * enabled, but in practice it seems to have problems | |
4537 | * when going from primary only to sprite only and vice | |
4538 | * versa. | |
4539 | */ | |
4540 | hsw_disable_ips(intel_crtc); | |
4541 | } | |
4542 | ||
4543 | /* FIXME get rid of this and use pre_plane_update */ | |
4544 | static void | |
4545 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4546 | { | |
4547 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4548 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4549 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4550 | int pipe = intel_crtc->pipe; | |
4551 | ||
4552 | intel_pre_disable_primary(crtc); | |
4553 | ||
87d4300a ML |
4554 | /* |
4555 | * Vblank time updates from the shadow to live plane control register | |
4556 | * are blocked if the memory self-refresh mode is active at that | |
4557 | * moment. So to make sure the plane gets truly disabled, disable | |
4558 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4559 | * will be checked/applied by the HW only at the next frame start | |
4560 | * event which is after the vblank start event, so we need to have a | |
4561 | * wait-for-vblank between disabling the plane and the pipe. | |
4562 | */ | |
262cd2e1 | 4563 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4564 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4565 | dev_priv->wm.vlv.cxsr = false; |
4566 | intel_wait_for_vblank(dev, pipe); | |
4567 | } | |
87d4300a ML |
4568 | } |
4569 | ||
5a21b665 DV |
4570 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4571 | { | |
4572 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4573 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4574 | struct intel_crtc_state *pipe_config = | |
4575 | to_intel_crtc_state(crtc->base.state); | |
4576 | struct drm_device *dev = crtc->base.dev; | |
4577 | struct drm_plane *primary = crtc->base.primary; | |
4578 | struct drm_plane_state *old_pri_state = | |
4579 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4580 | ||
4581 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); | |
4582 | ||
4583 | crtc->wm.cxsr_allowed = true; | |
4584 | ||
4585 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
4586 | intel_update_watermarks(&crtc->base); | |
4587 | ||
4588 | if (old_pri_state) { | |
4589 | struct intel_plane_state *primary_state = | |
4590 | to_intel_plane_state(primary->state); | |
4591 | struct intel_plane_state *old_primary_state = | |
4592 | to_intel_plane_state(old_pri_state); | |
4593 | ||
4594 | intel_fbc_post_update(crtc); | |
4595 | ||
4596 | if (primary_state->visible && | |
4597 | (needs_modeset(&pipe_config->base) || | |
4598 | !old_primary_state->visible)) | |
4599 | intel_post_enable_primary(&crtc->base); | |
4600 | } | |
4601 | } | |
4602 | ||
5c74cd73 | 4603 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4604 | { |
5c74cd73 | 4605 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4606 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4607 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
4608 | struct intel_crtc_state *pipe_config = |
4609 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4610 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4611 | struct drm_plane *primary = crtc->base.primary; | |
4612 | struct drm_plane_state *old_pri_state = | |
4613 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4614 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4615 | |
5c74cd73 ML |
4616 | if (old_pri_state) { |
4617 | struct intel_plane_state *primary_state = | |
4618 | to_intel_plane_state(primary->state); | |
4619 | struct intel_plane_state *old_primary_state = | |
4620 | to_intel_plane_state(old_pri_state); | |
4621 | ||
faf68d92 | 4622 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4623 | |
5c74cd73 ML |
4624 | if (old_primary_state->visible && |
4625 | (modeset || !primary_state->visible)) | |
4626 | intel_pre_disable_primary(&crtc->base); | |
4627 | } | |
852eb00d | 4628 | |
a4015f9a | 4629 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
852eb00d | 4630 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4631 | |
2622a081 VS |
4632 | /* |
4633 | * Vblank time updates from the shadow to live plane control register | |
4634 | * are blocked if the memory self-refresh mode is active at that | |
4635 | * moment. So to make sure the plane gets truly disabled, disable | |
4636 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4637 | * will be checked/applied by the HW only at the next frame start | |
4638 | * event which is after the vblank start event, so we need to have a | |
4639 | * wait-for-vblank between disabling the plane and the pipe. | |
4640 | */ | |
4641 | if (old_crtc_state->base.active) { | |
2dfd178d | 4642 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4643 | dev_priv->wm.vlv.cxsr = false; |
4644 | intel_wait_for_vblank(dev, crtc->pipe); | |
4645 | } | |
852eb00d | 4646 | } |
92826fcd | 4647 | |
ed4a6a7c MR |
4648 | /* |
4649 | * IVB workaround: must disable low power watermarks for at least | |
4650 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4651 | * when scaling is disabled. | |
4652 | * | |
4653 | * WaCxSRDisabledForSpriteScaling:ivb | |
4654 | */ | |
4655 | if (pipe_config->disable_lp_wm) { | |
4656 | ilk_disable_lp_wm(dev); | |
4657 | intel_wait_for_vblank(dev, crtc->pipe); | |
4658 | } | |
4659 | ||
4660 | /* | |
4661 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4662 | * watermark programming here. | |
4663 | */ | |
4664 | if (needs_modeset(&pipe_config->base)) | |
4665 | return; | |
4666 | ||
4667 | /* | |
4668 | * For platforms that support atomic watermarks, program the | |
4669 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4670 | * will be the intermediate values that are safe for both pre- and | |
4671 | * post- vblank; when vblank happens, the 'active' values will be set | |
4672 | * to the final 'target' values and we'll do this again to get the | |
4673 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4674 | * will be the final target values which will get automatically latched | |
4675 | * at vblank time; no further programming will be necessary. | |
4676 | * | |
4677 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4678 | * we'll continue to update watermarks the old way, if flags tell | |
4679 | * us to. | |
4680 | */ | |
4681 | if (dev_priv->display.initial_watermarks != NULL) | |
4682 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4683 | else if (pipe_config->update_wm_pre) |
92826fcd | 4684 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4685 | } |
4686 | ||
d032ffa0 | 4687 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4688 | { |
4689 | struct drm_device *dev = crtc->dev; | |
4690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4691 | struct drm_plane *p; |
87d4300a ML |
4692 | int pipe = intel_crtc->pipe; |
4693 | ||
7cac945f | 4694 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4695 | |
d032ffa0 ML |
4696 | drm_for_each_plane_mask(p, dev, plane_mask) |
4697 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4698 | |
f99d7069 DV |
4699 | /* |
4700 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4701 | * to compute the mask of flip planes precisely. For the time being | |
4702 | * consider this a flip to a NULL plane. | |
4703 | */ | |
4704 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4705 | } |
4706 | ||
f67a559d JB |
4707 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4708 | { | |
4709 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4710 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d | 4711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4712 | struct intel_encoder *encoder; |
f67a559d | 4713 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4714 | struct intel_crtc_state *pipe_config = |
4715 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4716 | |
53d9f4e9 | 4717 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4718 | return; |
4719 | ||
b2c0593a VS |
4720 | /* |
4721 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4722 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4723 | * | |
4724 | * On ILK we get an occasional spurious CPU pipe underruns | |
4725 | * between eDP port A enable and vdd enable. Also PCH port | |
4726 | * enable seems to result in the occasional CPU pipe underrun. | |
4727 | * | |
4728 | * Spurious PCH underruns also occur during PCH enabling. | |
4729 | */ | |
4730 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4731 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4732 | if (intel_crtc->config->has_pch_encoder) |
4733 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4734 | ||
6e3c9717 | 4735 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4736 | intel_prepare_shared_dpll(intel_crtc); |
4737 | ||
37a5650b | 4738 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4739 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4740 | |
4741 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4742 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4743 | |
6e3c9717 | 4744 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4745 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4746 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4747 | } |
4748 | ||
4749 | ironlake_set_pipeconf(crtc); | |
4750 | ||
f67a559d | 4751 | intel_crtc->active = true; |
8664281b | 4752 | |
f6736a1a | 4753 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4754 | if (encoder->pre_enable) |
4755 | encoder->pre_enable(encoder); | |
f67a559d | 4756 | |
6e3c9717 | 4757 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4758 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4759 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4760 | * enabling. */ | |
88cefb6c | 4761 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4762 | } else { |
4763 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4764 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4765 | } | |
f67a559d | 4766 | |
b074cec8 | 4767 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4768 | |
9c54c0dd JB |
4769 | /* |
4770 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4771 | * clocks enabled | |
4772 | */ | |
b95c5321 | 4773 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4774 | |
1d5bf5d9 ID |
4775 | if (dev_priv->display.initial_watermarks != NULL) |
4776 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4777 | intel_enable_pipe(intel_crtc); |
f67a559d | 4778 | |
6e3c9717 | 4779 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4780 | ironlake_pch_enable(crtc); |
c98e9dcf | 4781 | |
f9b61ff6 DV |
4782 | assert_vblank_disabled(crtc); |
4783 | drm_crtc_vblank_on(crtc); | |
4784 | ||
fa5c73b1 DV |
4785 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4786 | encoder->enable(encoder); | |
61b77ddd DV |
4787 | |
4788 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4789 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4790 | |
4791 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4792 | if (intel_crtc->config->has_pch_encoder) | |
4793 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4794 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4795 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4796 | } |
4797 | ||
42db64ef PZ |
4798 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4799 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4800 | { | |
f5adf94e | 4801 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4802 | } |
4803 | ||
4f771f10 PZ |
4804 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4805 | { | |
4806 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4807 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 PZ |
4808 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4809 | struct intel_encoder *encoder; | |
99d736a2 | 4810 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4811 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4812 | struct intel_crtc_state *pipe_config = |
4813 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4814 | |
53d9f4e9 | 4815 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4816 | return; |
4817 | ||
81b088ca VS |
4818 | if (intel_crtc->config->has_pch_encoder) |
4819 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4820 | false); | |
4821 | ||
95a7a2ae ID |
4822 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4823 | if (encoder->pre_pll_enable) | |
4824 | encoder->pre_pll_enable(encoder); | |
4825 | ||
8106ddbd | 4826 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4827 | intel_enable_shared_dpll(intel_crtc); |
4828 | ||
37a5650b | 4829 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4830 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4831 | |
4d1de975 JN |
4832 | if (!intel_crtc->config->has_dsi_encoder) |
4833 | intel_set_pipe_timings(intel_crtc); | |
4834 | ||
bc58be60 | 4835 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4836 | |
4d1de975 JN |
4837 | if (cpu_transcoder != TRANSCODER_EDP && |
4838 | !transcoder_is_dsi(cpu_transcoder)) { | |
4839 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4840 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4841 | } |
4842 | ||
6e3c9717 | 4843 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4844 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4845 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4846 | } |
4847 | ||
4d1de975 JN |
4848 | if (!intel_crtc->config->has_dsi_encoder) |
4849 | haswell_set_pipeconf(crtc); | |
4850 | ||
391bf048 | 4851 | haswell_set_pipemisc(crtc); |
229fca97 | 4852 | |
b95c5321 | 4853 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4854 | |
4f771f10 | 4855 | intel_crtc->active = true; |
8664281b | 4856 | |
6b698516 DV |
4857 | if (intel_crtc->config->has_pch_encoder) |
4858 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4859 | else | |
4860 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4861 | ||
7d4aefd0 | 4862 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4863 | if (encoder->pre_enable) |
4864 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4865 | } |
4f771f10 | 4866 | |
d2d65408 | 4867 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4868 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4869 | |
a65347ba | 4870 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4871 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4872 | |
1c132b44 | 4873 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4874 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4875 | else |
1c132b44 | 4876 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4877 | |
4878 | /* | |
4879 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4880 | * clocks enabled | |
4881 | */ | |
b95c5321 | 4882 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4883 | |
1f544388 | 4884 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4885 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4886 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4887 | |
1d5bf5d9 ID |
4888 | if (dev_priv->display.initial_watermarks != NULL) |
4889 | dev_priv->display.initial_watermarks(pipe_config); | |
4890 | else | |
4891 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4892 | |
4893 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4894 | if (!intel_crtc->config->has_dsi_encoder) | |
4895 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4896 | |
6e3c9717 | 4897 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4898 | lpt_pch_enable(crtc); |
4f771f10 | 4899 | |
a65347ba | 4900 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4901 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4902 | ||
f9b61ff6 DV |
4903 | assert_vblank_disabled(crtc); |
4904 | drm_crtc_vblank_on(crtc); | |
4905 | ||
8807e55b | 4906 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4907 | encoder->enable(encoder); |
8807e55b JN |
4908 | intel_opregion_notify_encoder(encoder, true); |
4909 | } | |
4f771f10 | 4910 | |
6b698516 DV |
4911 | if (intel_crtc->config->has_pch_encoder) { |
4912 | intel_wait_for_vblank(dev, pipe); | |
4913 | intel_wait_for_vblank(dev, pipe); | |
4914 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4915 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4916 | true); | |
6b698516 | 4917 | } |
d2d65408 | 4918 | |
e4916946 PZ |
4919 | /* If we change the relative order between pipe/planes enabling, we need |
4920 | * to change the workaround. */ | |
99d736a2 ML |
4921 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4922 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4923 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4924 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4925 | } | |
4f771f10 PZ |
4926 | } |
4927 | ||
bfd16b2a | 4928 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4929 | { |
4930 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4931 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
4932 | int pipe = crtc->pipe; |
4933 | ||
4934 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4935 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4936 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4937 | I915_WRITE(PF_CTL(pipe), 0); |
4938 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4939 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4940 | } | |
4941 | } | |
4942 | ||
6be4a607 JB |
4943 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4944 | { | |
4945 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4946 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 | 4947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4948 | struct intel_encoder *encoder; |
6be4a607 | 4949 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4950 | |
b2c0593a VS |
4951 | /* |
4952 | * Sometimes spurious CPU pipe underruns happen when the | |
4953 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4954 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4955 | */ | |
4956 | if (intel_crtc->config->has_pch_encoder) { | |
4957 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 4958 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 4959 | } |
37ca8d4c | 4960 | |
ea9d758d DV |
4961 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4962 | encoder->disable(encoder); | |
4963 | ||
f9b61ff6 DV |
4964 | drm_crtc_vblank_off(crtc); |
4965 | assert_vblank_disabled(crtc); | |
4966 | ||
575f7ab7 | 4967 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4968 | |
bfd16b2a | 4969 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4970 | |
b2c0593a | 4971 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
4972 | ironlake_fdi_disable(crtc); |
4973 | ||
bf49ec8c DV |
4974 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4975 | if (encoder->post_disable) | |
4976 | encoder->post_disable(encoder); | |
2c07245f | 4977 | |
6e3c9717 | 4978 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4979 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4980 | |
d925c59a | 4981 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
4982 | i915_reg_t reg; |
4983 | u32 temp; | |
4984 | ||
d925c59a DV |
4985 | /* disable TRANS_DP_CTL */ |
4986 | reg = TRANS_DP_CTL(pipe); | |
4987 | temp = I915_READ(reg); | |
4988 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4989 | TRANS_DP_PORT_SEL_MASK); | |
4990 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4991 | I915_WRITE(reg, temp); | |
4992 | ||
4993 | /* disable DPLL_SEL */ | |
4994 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4995 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4996 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4997 | } |
e3421a18 | 4998 | |
d925c59a DV |
4999 | ironlake_fdi_pll_disable(intel_crtc); |
5000 | } | |
81b088ca | 5001 | |
b2c0593a | 5002 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5003 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5004 | } |
1b3c7a47 | 5005 | |
4f771f10 | 5006 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5007 | { |
4f771f10 | 5008 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5009 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5011 | struct intel_encoder *encoder; |
6e3c9717 | 5012 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5013 | |
d2d65408 VS |
5014 | if (intel_crtc->config->has_pch_encoder) |
5015 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5016 | false); | |
5017 | ||
8807e55b JN |
5018 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5019 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5020 | encoder->disable(encoder); |
8807e55b | 5021 | } |
4f771f10 | 5022 | |
f9b61ff6 DV |
5023 | drm_crtc_vblank_off(crtc); |
5024 | assert_vblank_disabled(crtc); | |
5025 | ||
4d1de975 JN |
5026 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5027 | if (!intel_crtc->config->has_dsi_encoder) | |
5028 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5029 | |
6e3c9717 | 5030 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5031 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5032 | ||
a65347ba | 5033 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5034 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5035 | |
1c132b44 | 5036 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5037 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5038 | else |
bfd16b2a | 5039 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5040 | |
a65347ba | 5041 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5042 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5043 | |
97b040aa ID |
5044 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5045 | if (encoder->post_disable) | |
5046 | encoder->post_disable(encoder); | |
81b088ca | 5047 | |
92966a37 VS |
5048 | if (intel_crtc->config->has_pch_encoder) { |
5049 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5050 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5051 | intel_ddi_fdi_disable(crtc); |
5052 | ||
81b088ca VS |
5053 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5054 | true); | |
92966a37 | 5055 | } |
4f771f10 PZ |
5056 | } |
5057 | ||
2dd24552 JB |
5058 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5059 | { | |
5060 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5061 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5062 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5063 | |
681a8504 | 5064 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5065 | return; |
5066 | ||
2dd24552 | 5067 | /* |
c0b03411 DV |
5068 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5069 | * according to register description and PRM. | |
2dd24552 | 5070 | */ |
c0b03411 DV |
5071 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5072 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5073 | |
b074cec8 JB |
5074 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5075 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5076 | |
5077 | /* Border color in case we don't scale up to the full screen. Black by | |
5078 | * default, change to something else for debugging. */ | |
5079 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5080 | } |
5081 | ||
d05410f9 DA |
5082 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5083 | { | |
5084 | switch (port) { | |
5085 | case PORT_A: | |
6331a704 | 5086 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5087 | case PORT_B: |
6331a704 | 5088 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5089 | case PORT_C: |
6331a704 | 5090 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5091 | case PORT_D: |
6331a704 | 5092 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5093 | case PORT_E: |
6331a704 | 5094 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5095 | default: |
b9fec167 | 5096 | MISSING_CASE(port); |
d05410f9 DA |
5097 | return POWER_DOMAIN_PORT_OTHER; |
5098 | } | |
5099 | } | |
5100 | ||
25f78f58 VS |
5101 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5102 | { | |
5103 | switch (port) { | |
5104 | case PORT_A: | |
5105 | return POWER_DOMAIN_AUX_A; | |
5106 | case PORT_B: | |
5107 | return POWER_DOMAIN_AUX_B; | |
5108 | case PORT_C: | |
5109 | return POWER_DOMAIN_AUX_C; | |
5110 | case PORT_D: | |
5111 | return POWER_DOMAIN_AUX_D; | |
5112 | case PORT_E: | |
5113 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5114 | return POWER_DOMAIN_AUX_D; | |
5115 | default: | |
b9fec167 | 5116 | MISSING_CASE(port); |
25f78f58 VS |
5117 | return POWER_DOMAIN_AUX_A; |
5118 | } | |
5119 | } | |
5120 | ||
319be8ae ID |
5121 | enum intel_display_power_domain |
5122 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5123 | { | |
5124 | struct drm_device *dev = intel_encoder->base.dev; | |
5125 | struct intel_digital_port *intel_dig_port; | |
5126 | ||
5127 | switch (intel_encoder->type) { | |
5128 | case INTEL_OUTPUT_UNKNOWN: | |
5129 | /* Only DDI platforms should ever use this output type */ | |
5130 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
cca0502b | 5131 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5132 | case INTEL_OUTPUT_HDMI: |
5133 | case INTEL_OUTPUT_EDP: | |
5134 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5135 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5136 | case INTEL_OUTPUT_DP_MST: |
5137 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5138 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5139 | case INTEL_OUTPUT_ANALOG: |
5140 | return POWER_DOMAIN_PORT_CRT; | |
5141 | case INTEL_OUTPUT_DSI: | |
5142 | return POWER_DOMAIN_PORT_DSI; | |
5143 | default: | |
5144 | return POWER_DOMAIN_PORT_OTHER; | |
5145 | } | |
5146 | } | |
5147 | ||
25f78f58 VS |
5148 | enum intel_display_power_domain |
5149 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5150 | { | |
5151 | struct drm_device *dev = intel_encoder->base.dev; | |
5152 | struct intel_digital_port *intel_dig_port; | |
5153 | ||
5154 | switch (intel_encoder->type) { | |
5155 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5156 | case INTEL_OUTPUT_HDMI: |
5157 | /* | |
5158 | * Only DDI platforms should ever use these output types. | |
5159 | * We can get here after the HDMI detect code has already set | |
5160 | * the type of the shared encoder. Since we can't be sure | |
5161 | * what's the status of the given connectors, play safe and | |
5162 | * run the DP detection too. | |
5163 | */ | |
25f78f58 | 5164 | WARN_ON_ONCE(!HAS_DDI(dev)); |
cca0502b | 5165 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5166 | case INTEL_OUTPUT_EDP: |
5167 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5168 | return port_to_aux_power_domain(intel_dig_port->port); | |
5169 | case INTEL_OUTPUT_DP_MST: | |
5170 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5171 | return port_to_aux_power_domain(intel_dig_port->port); | |
5172 | default: | |
b9fec167 | 5173 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5174 | return POWER_DOMAIN_AUX_A; |
5175 | } | |
5176 | } | |
5177 | ||
74bff5f9 ML |
5178 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5179 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5180 | { |
319be8ae | 5181 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5182 | struct drm_encoder *encoder; |
319be8ae ID |
5183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5184 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5185 | unsigned long mask; |
74bff5f9 | 5186 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5187 | |
74bff5f9 | 5188 | if (!crtc_state->base.active) |
292b990e ML |
5189 | return 0; |
5190 | ||
77d22dca ID |
5191 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5192 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5193 | if (crtc_state->pch_pfit.enabled || |
5194 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5195 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5196 | ||
74bff5f9 ML |
5197 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5198 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5199 | ||
319be8ae | 5200 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5201 | } |
319be8ae | 5202 | |
15e7ec29 ML |
5203 | if (crtc_state->shared_dpll) |
5204 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5205 | ||
77d22dca ID |
5206 | return mask; |
5207 | } | |
5208 | ||
74bff5f9 ML |
5209 | static unsigned long |
5210 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5211 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5212 | { |
fac5e23e | 5213 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5215 | enum intel_display_power_domain domain; | |
5a21b665 | 5216 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5217 | |
292b990e | 5218 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5219 | intel_crtc->enabled_power_domains = new_domains = |
5220 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5221 | |
5a21b665 | 5222 | domains = new_domains & ~old_domains; |
292b990e ML |
5223 | |
5224 | for_each_power_domain(domain, domains) | |
5225 | intel_display_power_get(dev_priv, domain); | |
5226 | ||
5a21b665 | 5227 | return old_domains & ~new_domains; |
292b990e ML |
5228 | } |
5229 | ||
5230 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5231 | unsigned long domains) | |
5232 | { | |
5233 | enum intel_display_power_domain domain; | |
5234 | ||
5235 | for_each_power_domain(domain, domains) | |
5236 | intel_display_power_put(dev_priv, domain); | |
5237 | } | |
77d22dca | 5238 | |
adafdc6f MK |
5239 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5240 | { | |
5241 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5242 | ||
5243 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5244 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5245 | return max_cdclk_freq; | |
5246 | else if (IS_CHERRYVIEW(dev_priv)) | |
5247 | return max_cdclk_freq*95/100; | |
5248 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5249 | return 2*max_cdclk_freq*90/100; | |
5250 | else | |
5251 | return max_cdclk_freq*90/100; | |
5252 | } | |
5253 | ||
b2045352 VS |
5254 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5255 | ||
560a7ae4 DL |
5256 | static void intel_update_max_cdclk(struct drm_device *dev) |
5257 | { | |
fac5e23e | 5258 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 | 5259 | |
ef11bdb3 | 5260 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5261 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5262 | int max_cdclk, vco; |
5263 | ||
5264 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5265 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5266 | |
b2045352 VS |
5267 | /* |
5268 | * Use the lower (vco 8640) cdclk values as a | |
5269 | * first guess. skl_calc_cdclk() will correct it | |
5270 | * if the preferred vco is 8100 instead. | |
5271 | */ | |
560a7ae4 | 5272 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5273 | max_cdclk = 617143; |
560a7ae4 | 5274 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5275 | max_cdclk = 540000; |
560a7ae4 | 5276 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5277 | max_cdclk = 432000; |
560a7ae4 | 5278 | else |
487ed2e4 | 5279 | max_cdclk = 308571; |
b2045352 VS |
5280 | |
5281 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5282 | } else if (IS_BROXTON(dev)) { |
5283 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5284 | } else if (IS_BROADWELL(dev)) { |
5285 | /* | |
5286 | * FIXME with extra cooling we can allow | |
5287 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5288 | * How can we know if extra cooling is | |
5289 | * available? PCI ID, VTB, something else? | |
5290 | */ | |
5291 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5292 | dev_priv->max_cdclk_freq = 450000; | |
5293 | else if (IS_BDW_ULX(dev)) | |
5294 | dev_priv->max_cdclk_freq = 450000; | |
5295 | else if (IS_BDW_ULT(dev)) | |
5296 | dev_priv->max_cdclk_freq = 540000; | |
5297 | else | |
5298 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5299 | } else if (IS_CHERRYVIEW(dev)) { |
5300 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5301 | } else if (IS_VALLEYVIEW(dev)) { |
5302 | dev_priv->max_cdclk_freq = 400000; | |
5303 | } else { | |
5304 | /* otherwise assume cdclk is fixed */ | |
5305 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5306 | } | |
5307 | ||
adafdc6f MK |
5308 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5309 | ||
560a7ae4 DL |
5310 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5311 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5312 | |
5313 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5314 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5315 | } |
5316 | ||
5317 | static void intel_update_cdclk(struct drm_device *dev) | |
5318 | { | |
fac5e23e | 5319 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 DL |
5320 | |
5321 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5322 | |
83d7c81f | 5323 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5324 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5325 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5326 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5327 | else |
5328 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5329 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5330 | |
5331 | /* | |
b5d99ff9 VS |
5332 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5333 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5334 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5335 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5336 | */ |
b5d99ff9 | 5337 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5338 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5339 | } |
5340 | ||
92891e45 VS |
5341 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5342 | static int skl_cdclk_decimal(int cdclk) | |
5343 | { | |
5344 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5345 | } | |
5346 | ||
5f199dfa VS |
5347 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5348 | { | |
5349 | int ratio; | |
5350 | ||
5351 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5352 | return 0; | |
5353 | ||
5354 | switch (cdclk) { | |
5355 | default: | |
5356 | MISSING_CASE(cdclk); | |
5357 | case 144000: | |
5358 | case 288000: | |
5359 | case 384000: | |
5360 | case 576000: | |
5361 | ratio = 60; | |
5362 | break; | |
5363 | case 624000: | |
5364 | ratio = 65; | |
5365 | break; | |
5366 | } | |
5367 | ||
5368 | return dev_priv->cdclk_pll.ref * ratio; | |
5369 | } | |
5370 | ||
2b73001e VS |
5371 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5372 | { | |
5373 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5374 | ||
5375 | /* Timeout 200us */ | |
95cac283 CW |
5376 | if (intel_wait_for_register(dev_priv, |
5377 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5378 | 1)) | |
2b73001e | 5379 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5380 | |
5381 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5382 | } |
5383 | ||
5f199dfa | 5384 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5385 | { |
5f199dfa | 5386 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5387 | u32 val; |
5388 | ||
5389 | val = I915_READ(BXT_DE_PLL_CTL); | |
5390 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5391 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5392 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5393 | ||
5394 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5395 | ||
5396 | /* Timeout 200us */ | |
e084e1b9 CW |
5397 | if (intel_wait_for_register(dev_priv, |
5398 | BXT_DE_PLL_ENABLE, | |
5399 | BXT_DE_PLL_LOCK, | |
5400 | BXT_DE_PLL_LOCK, | |
5401 | 1)) | |
2b73001e | 5402 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5403 | |
5f199dfa | 5404 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5405 | } |
5406 | ||
324513c0 | 5407 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5408 | { |
5f199dfa VS |
5409 | u32 val, divider; |
5410 | int vco, ret; | |
f8437dd1 | 5411 | |
5f199dfa VS |
5412 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5413 | ||
5414 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5415 | ||
5416 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5417 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5418 | case 8: | |
f8437dd1 | 5419 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5420 | break; |
5f199dfa | 5421 | case 4: |
f8437dd1 | 5422 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5423 | break; |
5f199dfa | 5424 | case 3: |
f8437dd1 | 5425 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5426 | break; |
5f199dfa | 5427 | case 2: |
f8437dd1 | 5428 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5429 | break; |
5430 | default: | |
5f199dfa VS |
5431 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5432 | WARN_ON(vco != 0); | |
f8437dd1 | 5433 | |
5f199dfa VS |
5434 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5435 | break; | |
f8437dd1 VK |
5436 | } |
5437 | ||
f8437dd1 | 5438 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5439 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5440 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5441 | 0x80000000); | |
5442 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5443 | ||
5444 | if (ret) { | |
5445 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5446 | ret, cdclk); |
f8437dd1 VK |
5447 | return; |
5448 | } | |
5449 | ||
5f199dfa VS |
5450 | if (dev_priv->cdclk_pll.vco != 0 && |
5451 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5452 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5453 | |
5f199dfa VS |
5454 | if (dev_priv->cdclk_pll.vco != vco) |
5455 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5456 | |
5f199dfa VS |
5457 | val = divider | skl_cdclk_decimal(cdclk); |
5458 | /* | |
5459 | * FIXME if only the cd2x divider needs changing, it could be done | |
5460 | * without shutting off the pipe (if only one pipe is active). | |
5461 | */ | |
5462 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5463 | /* | |
5464 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5465 | * enable otherwise. | |
5466 | */ | |
5467 | if (cdclk >= 500000) | |
5468 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5469 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5470 | |
5471 | mutex_lock(&dev_priv->rps.hw_lock); | |
5472 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5473 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5474 | mutex_unlock(&dev_priv->rps.hw_lock); |
5475 | ||
5476 | if (ret) { | |
5477 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5478 | ret, cdclk); |
f8437dd1 VK |
5479 | return; |
5480 | } | |
5481 | ||
91c8a326 | 5482 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 VK |
5483 | } |
5484 | ||
d66a2194 | 5485 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5486 | { |
d66a2194 ID |
5487 | u32 cdctl, expected; |
5488 | ||
91c8a326 | 5489 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 | 5490 | |
d66a2194 ID |
5491 | if (dev_priv->cdclk_pll.vco == 0 || |
5492 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
5493 | goto sanitize; | |
5494 | ||
5495 | /* DPLL okay; verify the cdclock | |
5496 | * | |
5497 | * Some BIOS versions leave an incorrect decimal frequency value and | |
5498 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
5499 | * so sanitize this register. | |
5500 | */ | |
5501 | cdctl = I915_READ(CDCLK_CTL); | |
5502 | /* | |
5503 | * Let's ignore the pipe field, since BIOS could have configured the | |
5504 | * dividers both synching to an active pipe, or asynchronously | |
5505 | * (PIPE_NONE). | |
5506 | */ | |
5507 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
5508 | ||
5509 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
5510 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5511 | /* | |
5512 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5513 | * enable otherwise. | |
5514 | */ | |
5515 | if (dev_priv->cdclk_freq >= 500000) | |
5516 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5517 | ||
5518 | if (cdctl == expected) | |
5519 | /* All well; nothing to sanitize */ | |
5520 | return; | |
5521 | ||
5522 | sanitize: | |
5523 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
5524 | ||
5525 | /* force cdclk programming */ | |
5526 | dev_priv->cdclk_freq = 0; | |
5527 | ||
5528 | /* force full PLL disable + enable */ | |
5529 | dev_priv->cdclk_pll.vco = -1; | |
5530 | } | |
5531 | ||
324513c0 | 5532 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
5533 | { |
5534 | bxt_sanitize_cdclk(dev_priv); | |
5535 | ||
5536 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 5537 | return; |
c2e001ef | 5538 | |
f8437dd1 VK |
5539 | /* |
5540 | * FIXME: | |
5541 | * - The initial CDCLK needs to be read from VBT. | |
5542 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5543 | */ |
324513c0 | 5544 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
5545 | } |
5546 | ||
324513c0 | 5547 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5548 | { |
324513c0 | 5549 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
5550 | } |
5551 | ||
a8ca4934 VS |
5552 | static int skl_calc_cdclk(int max_pixclk, int vco) |
5553 | { | |
63911d72 | 5554 | if (vco == 8640000) { |
a8ca4934 | 5555 | if (max_pixclk > 540000) |
487ed2e4 | 5556 | return 617143; |
a8ca4934 VS |
5557 | else if (max_pixclk > 432000) |
5558 | return 540000; | |
487ed2e4 | 5559 | else if (max_pixclk > 308571) |
a8ca4934 VS |
5560 | return 432000; |
5561 | else | |
487ed2e4 | 5562 | return 308571; |
a8ca4934 | 5563 | } else { |
a8ca4934 VS |
5564 | if (max_pixclk > 540000) |
5565 | return 675000; | |
5566 | else if (max_pixclk > 450000) | |
5567 | return 540000; | |
5568 | else if (max_pixclk > 337500) | |
5569 | return 450000; | |
5570 | else | |
5571 | return 337500; | |
5572 | } | |
5573 | } | |
5574 | ||
ea61791e VS |
5575 | static void |
5576 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 5577 | { |
ea61791e | 5578 | u32 val; |
5d96d8af | 5579 | |
709e05c3 | 5580 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 5581 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 5582 | |
ea61791e | 5583 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 5584 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 5585 | return; |
5d96d8af | 5586 | |
1c3f7700 ID |
5587 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
5588 | return; | |
9f7eb31a | 5589 | |
ea61791e VS |
5590 | val = I915_READ(DPLL_CTRL1); |
5591 | ||
1c3f7700 ID |
5592 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
5593 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5594 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5595 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
5596 | return; | |
9f7eb31a | 5597 | |
ea61791e VS |
5598 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
5599 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
5600 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
5601 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
5602 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 5603 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
5604 | break; |
5605 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
5606 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 5607 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
5608 | break; |
5609 | default: | |
5610 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
5611 | break; |
5612 | } | |
5d96d8af DL |
5613 | } |
5614 | ||
b2045352 VS |
5615 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
5616 | { | |
5617 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
5618 | ||
5619 | dev_priv->skl_preferred_vco_freq = vco; | |
5620 | ||
5621 | if (changed) | |
91c8a326 | 5622 | intel_update_max_cdclk(&dev_priv->drm); |
b2045352 VS |
5623 | } |
5624 | ||
5d96d8af | 5625 | static void |
3861fc60 | 5626 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5627 | { |
a8ca4934 | 5628 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
5629 | u32 val; |
5630 | ||
63911d72 | 5631 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 5632 | |
5d96d8af | 5633 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 5634 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5635 | I915_WRITE(CDCLK_CTL, val); |
5636 | POSTING_READ(CDCLK_CTL); | |
5637 | ||
5638 | /* | |
5639 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5640 | * taking into account the VCO required to operate the eDP panel at the | |
5641 | * desired frequency. The usual DP link rates operate with a VCO of | |
5642 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5643 | * The modeset code is responsible for the selection of the exact link | |
5644 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 5645 | * works with vco. |
5d96d8af DL |
5646 | */ |
5647 | val = I915_READ(DPLL_CTRL1); | |
5648 | ||
5649 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5650 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5651 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 5652 | if (vco == 8640000) |
5d96d8af DL |
5653 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5654 | SKL_DPLL0); | |
5655 | else | |
5656 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5657 | SKL_DPLL0); | |
5658 | ||
5659 | I915_WRITE(DPLL_CTRL1, val); | |
5660 | POSTING_READ(DPLL_CTRL1); | |
5661 | ||
5662 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5663 | ||
e24ca054 CW |
5664 | if (intel_wait_for_register(dev_priv, |
5665 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
5666 | 5)) | |
5d96d8af | 5667 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 5668 | |
63911d72 | 5669 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
5670 | |
5671 | /* We'll want to keep using the current vco from now on. */ | |
5672 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
5673 | } |
5674 | ||
430e05de VS |
5675 | static void |
5676 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5677 | { | |
5678 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
5679 | if (intel_wait_for_register(dev_priv, |
5680 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
5681 | 1)) | |
430e05de | 5682 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 5683 | |
63911d72 | 5684 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
5685 | } |
5686 | ||
5d96d8af DL |
5687 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5688 | { | |
5689 | int ret; | |
5690 | u32 val; | |
5691 | ||
5692 | /* inform PCU we want to change CDCLK */ | |
5693 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5694 | mutex_lock(&dev_priv->rps.hw_lock); | |
5695 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5696 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5697 | ||
5698 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5699 | } | |
5700 | ||
5701 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5702 | { | |
5703 | unsigned int i; | |
5704 | ||
5705 | for (i = 0; i < 15; i++) { | |
5706 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5707 | return true; | |
5708 | udelay(10); | |
5709 | } | |
5710 | ||
5711 | return false; | |
5712 | } | |
5713 | ||
1cd593e0 | 5714 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 5715 | { |
91c8a326 | 5716 | struct drm_device *dev = &dev_priv->drm; |
5d96d8af DL |
5717 | u32 freq_select, pcu_ack; |
5718 | ||
1cd593e0 VS |
5719 | WARN_ON((cdclk == 24000) != (vco == 0)); |
5720 | ||
63911d72 | 5721 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
5722 | |
5723 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5724 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5725 | return; | |
5726 | } | |
5727 | ||
5728 | /* set CDCLK_CTL */ | |
9ef56154 | 5729 | switch (cdclk) { |
5d96d8af DL |
5730 | case 450000: |
5731 | case 432000: | |
5732 | freq_select = CDCLK_FREQ_450_432; | |
5733 | pcu_ack = 1; | |
5734 | break; | |
5735 | case 540000: | |
5736 | freq_select = CDCLK_FREQ_540; | |
5737 | pcu_ack = 2; | |
5738 | break; | |
487ed2e4 | 5739 | case 308571: |
5d96d8af DL |
5740 | case 337500: |
5741 | default: | |
5742 | freq_select = CDCLK_FREQ_337_308; | |
5743 | pcu_ack = 0; | |
5744 | break; | |
487ed2e4 | 5745 | case 617143: |
5d96d8af DL |
5746 | case 675000: |
5747 | freq_select = CDCLK_FREQ_675_617; | |
5748 | pcu_ack = 3; | |
5749 | break; | |
5750 | } | |
5751 | ||
63911d72 VS |
5752 | if (dev_priv->cdclk_pll.vco != 0 && |
5753 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
5754 | skl_dpll0_disable(dev_priv); |
5755 | ||
63911d72 | 5756 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
5757 | skl_dpll0_enable(dev_priv, vco); |
5758 | ||
9ef56154 | 5759 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5760 | POSTING_READ(CDCLK_CTL); |
5761 | ||
5762 | /* inform PCU of the change */ | |
5763 | mutex_lock(&dev_priv->rps.hw_lock); | |
5764 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5765 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5766 | |
5767 | intel_update_cdclk(dev); | |
5d96d8af DL |
5768 | } |
5769 | ||
9f7eb31a VS |
5770 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5771 | ||
5d96d8af DL |
5772 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
5773 | { | |
709e05c3 | 5774 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
5775 | } |
5776 | ||
5777 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5778 | { | |
9f7eb31a VS |
5779 | int cdclk, vco; |
5780 | ||
5781 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 5782 | |
63911d72 | 5783 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
5784 | /* |
5785 | * Use the current vco as our initial | |
5786 | * guess as to what the preferred vco is. | |
5787 | */ | |
5788 | if (dev_priv->skl_preferred_vco_freq == 0) | |
5789 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 5790 | dev_priv->cdclk_pll.vco); |
70c2c184 | 5791 | return; |
1cd593e0 | 5792 | } |
5d96d8af | 5793 | |
70c2c184 VS |
5794 | vco = dev_priv->skl_preferred_vco_freq; |
5795 | if (vco == 0) | |
63911d72 | 5796 | vco = 8100000; |
70c2c184 | 5797 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 5798 | |
70c2c184 | 5799 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
5800 | } |
5801 | ||
9f7eb31a | 5802 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 5803 | { |
09492498 | 5804 | uint32_t cdctl, expected; |
c73666f3 | 5805 | |
f1b391a5 SK |
5806 | /* |
5807 | * check if the pre-os intialized the display | |
5808 | * There is SWF18 scratchpad register defined which is set by the | |
5809 | * pre-os which can be used by the OS drivers to check the status | |
5810 | */ | |
5811 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5812 | goto sanitize; | |
5813 | ||
91c8a326 | 5814 | intel_update_cdclk(&dev_priv->drm); |
c73666f3 | 5815 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
5816 | if (dev_priv->cdclk_pll.vco == 0 || |
5817 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
5818 | goto sanitize; |
5819 | ||
5820 | /* DPLL okay; verify the cdclock | |
5821 | * | |
5822 | * Noticed in some instances that the freq selection is correct but | |
5823 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5824 | * enable display. Verify the same as well. | |
5825 | */ | |
09492498 VS |
5826 | cdctl = I915_READ(CDCLK_CTL); |
5827 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
5828 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5829 | if (cdctl == expected) | |
c73666f3 | 5830 | /* All well; nothing to sanitize */ |
9f7eb31a | 5831 | return; |
c89e39f3 | 5832 | |
9f7eb31a VS |
5833 | sanitize: |
5834 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 5835 | |
9f7eb31a VS |
5836 | /* force cdclk programming */ |
5837 | dev_priv->cdclk_freq = 0; | |
5838 | /* force full PLL disable + enable */ | |
63911d72 | 5839 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
5840 | } |
5841 | ||
30a970c6 JB |
5842 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5843 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5844 | { | |
fac5e23e | 5845 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
5846 | u32 val, cmd; |
5847 | ||
164dfd28 VK |
5848 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5849 | != dev_priv->cdclk_freq); | |
d60c4473 | 5850 | |
dfcab17e | 5851 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5852 | cmd = 2; |
dfcab17e | 5853 | else if (cdclk == 266667) |
30a970c6 JB |
5854 | cmd = 1; |
5855 | else | |
5856 | cmd = 0; | |
5857 | ||
5858 | mutex_lock(&dev_priv->rps.hw_lock); | |
5859 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5860 | val &= ~DSPFREQGUAR_MASK; | |
5861 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5862 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5863 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5864 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5865 | 50)) { | |
5866 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5867 | } | |
5868 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5869 | ||
54433e91 VS |
5870 | mutex_lock(&dev_priv->sb_lock); |
5871 | ||
dfcab17e | 5872 | if (cdclk == 400000) { |
6bcda4f0 | 5873 | u32 divider; |
30a970c6 | 5874 | |
6bcda4f0 | 5875 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5876 | |
30a970c6 JB |
5877 | /* adjust cdclk divider */ |
5878 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5879 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5880 | val |= divider; |
5881 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5882 | |
5883 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5884 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5885 | 50)) |
5886 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5887 | } |
5888 | ||
30a970c6 JB |
5889 | /* adjust self-refresh exit latency value */ |
5890 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5891 | val &= ~0x7f; | |
5892 | ||
5893 | /* | |
5894 | * For high bandwidth configs, we set a higher latency in the bunit | |
5895 | * so that the core display fetch happens in time to avoid underruns. | |
5896 | */ | |
dfcab17e | 5897 | if (cdclk == 400000) |
30a970c6 JB |
5898 | val |= 4500 / 250; /* 4.5 usec */ |
5899 | else | |
5900 | val |= 3000 / 250; /* 3.0 usec */ | |
5901 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5902 | |
a580516d | 5903 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5904 | |
b6283055 | 5905 | intel_update_cdclk(dev); |
30a970c6 JB |
5906 | } |
5907 | ||
383c5a6a VS |
5908 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5909 | { | |
fac5e23e | 5910 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
5911 | u32 val, cmd; |
5912 | ||
164dfd28 VK |
5913 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5914 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5915 | |
5916 | switch (cdclk) { | |
383c5a6a VS |
5917 | case 333333: |
5918 | case 320000: | |
383c5a6a | 5919 | case 266667: |
383c5a6a | 5920 | case 200000: |
383c5a6a VS |
5921 | break; |
5922 | default: | |
5f77eeb0 | 5923 | MISSING_CASE(cdclk); |
383c5a6a VS |
5924 | return; |
5925 | } | |
5926 | ||
9d0d3fda VS |
5927 | /* |
5928 | * Specs are full of misinformation, but testing on actual | |
5929 | * hardware has shown that we just need to write the desired | |
5930 | * CCK divider into the Punit register. | |
5931 | */ | |
5932 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5933 | ||
383c5a6a VS |
5934 | mutex_lock(&dev_priv->rps.hw_lock); |
5935 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5936 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5937 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5938 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5939 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5940 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5941 | 50)) { | |
5942 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5943 | } | |
5944 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5945 | ||
b6283055 | 5946 | intel_update_cdclk(dev); |
383c5a6a VS |
5947 | } |
5948 | ||
30a970c6 JB |
5949 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5950 | int max_pixclk) | |
5951 | { | |
6bcda4f0 | 5952 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5953 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5954 | |
30a970c6 JB |
5955 | /* |
5956 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5957 | * 200MHz | |
5958 | * 267MHz | |
29dc7ef3 | 5959 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5960 | * 400MHz (VLV only) |
5961 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5962 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5963 | * |
5964 | * We seem to get an unstable or solid color picture at 200MHz. | |
5965 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5966 | * are off. | |
30a970c6 | 5967 | */ |
6cca3195 VS |
5968 | if (!IS_CHERRYVIEW(dev_priv) && |
5969 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5970 | return 400000; |
6cca3195 | 5971 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5972 | return freq_320; |
e37c67a1 | 5973 | else if (max_pixclk > 0) |
dfcab17e | 5974 | return 266667; |
e37c67a1 VS |
5975 | else |
5976 | return 200000; | |
30a970c6 JB |
5977 | } |
5978 | ||
324513c0 | 5979 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 5980 | { |
760e1477 | 5981 | if (max_pixclk > 576000) |
f8437dd1 | 5982 | return 624000; |
760e1477 | 5983 | else if (max_pixclk > 384000) |
f8437dd1 | 5984 | return 576000; |
760e1477 | 5985 | else if (max_pixclk > 288000) |
f8437dd1 | 5986 | return 384000; |
760e1477 | 5987 | else if (max_pixclk > 144000) |
f8437dd1 VK |
5988 | return 288000; |
5989 | else | |
5990 | return 144000; | |
5991 | } | |
5992 | ||
e8788cbc | 5993 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5994 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5995 | struct drm_atomic_state *state) | |
30a970c6 | 5996 | { |
565602d7 | 5997 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 5998 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
5999 | struct drm_crtc *crtc; |
6000 | struct drm_crtc_state *crtc_state; | |
6001 | unsigned max_pixclk = 0, i; | |
6002 | enum pipe pipe; | |
30a970c6 | 6003 | |
565602d7 ML |
6004 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6005 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6006 | |
565602d7 ML |
6007 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6008 | int pixclk = 0; | |
6009 | ||
6010 | if (crtc_state->enable) | |
6011 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6012 | |
565602d7 | 6013 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6014 | } |
6015 | ||
565602d7 ML |
6016 | for_each_pipe(dev_priv, pipe) |
6017 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6018 | ||
30a970c6 JB |
6019 | return max_pixclk; |
6020 | } | |
6021 | ||
27c329ed | 6022 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6023 | { |
27c329ed | 6024 | struct drm_device *dev = state->dev; |
fac5e23e | 6025 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6026 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6027 | struct intel_atomic_state *intel_state = |
6028 | to_intel_atomic_state(state); | |
30a970c6 | 6029 | |
1a617b77 | 6030 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6031 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6032 | |
1a617b77 ML |
6033 | if (!intel_state->active_crtcs) |
6034 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6035 | ||
27c329ed ML |
6036 | return 0; |
6037 | } | |
304603f4 | 6038 | |
324513c0 | 6039 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6040 | { |
4e5ca60f | 6041 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6042 | struct intel_atomic_state *intel_state = |
6043 | to_intel_atomic_state(state); | |
85a96e7a | 6044 | |
1a617b77 | 6045 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6046 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6047 | |
1a617b77 | 6048 | if (!intel_state->active_crtcs) |
324513c0 | 6049 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6050 | |
27c329ed | 6051 | return 0; |
30a970c6 JB |
6052 | } |
6053 | ||
1e69cd74 VS |
6054 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6055 | { | |
6056 | unsigned int credits, default_credits; | |
6057 | ||
6058 | if (IS_CHERRYVIEW(dev_priv)) | |
6059 | default_credits = PFI_CREDIT(12); | |
6060 | else | |
6061 | default_credits = PFI_CREDIT(8); | |
6062 | ||
bfa7df01 | 6063 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6064 | /* CHV suggested value is 31 or 63 */ |
6065 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6066 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6067 | else |
6068 | credits = PFI_CREDIT(15); | |
6069 | } else { | |
6070 | credits = default_credits; | |
6071 | } | |
6072 | ||
6073 | /* | |
6074 | * WA - write default credits before re-programming | |
6075 | * FIXME: should we also set the resend bit here? | |
6076 | */ | |
6077 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6078 | default_credits); | |
6079 | ||
6080 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6081 | credits | PFI_CREDIT_RESEND); | |
6082 | ||
6083 | /* | |
6084 | * FIXME is this guaranteed to clear | |
6085 | * immediately or should we poll for it? | |
6086 | */ | |
6087 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6088 | } | |
6089 | ||
27c329ed | 6090 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6091 | { |
a821fc46 | 6092 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6093 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6094 | struct intel_atomic_state *old_intel_state = |
6095 | to_intel_atomic_state(old_state); | |
6096 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6097 | |
27c329ed ML |
6098 | /* |
6099 | * FIXME: We can end up here with all power domains off, yet | |
6100 | * with a CDCLK frequency other than the minimum. To account | |
6101 | * for this take the PIPE-A power domain, which covers the HW | |
6102 | * blocks needed for the following programming. This can be | |
6103 | * removed once it's guaranteed that we get here either with | |
6104 | * the minimum CDCLK set, or the required power domains | |
6105 | * enabled. | |
6106 | */ | |
6107 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6108 | |
27c329ed ML |
6109 | if (IS_CHERRYVIEW(dev)) |
6110 | cherryview_set_cdclk(dev, req_cdclk); | |
6111 | else | |
6112 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6113 | |
27c329ed | 6114 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6115 | |
27c329ed | 6116 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6117 | } |
6118 | ||
89b667f8 JB |
6119 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6120 | { | |
6121 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6122 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6123 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6124 | struct intel_encoder *encoder; | |
b95c5321 ML |
6125 | struct intel_crtc_state *pipe_config = |
6126 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6127 | int pipe = intel_crtc->pipe; |
89b667f8 | 6128 | |
53d9f4e9 | 6129 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6130 | return; |
6131 | ||
37a5650b | 6132 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6133 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6134 | |
6135 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6136 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6137 | |
c14b0485 | 6138 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
fac5e23e | 6139 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6140 | |
6141 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6142 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6143 | } | |
6144 | ||
5b18e57c DV |
6145 | i9xx_set_pipeconf(intel_crtc); |
6146 | ||
89b667f8 | 6147 | intel_crtc->active = true; |
89b667f8 | 6148 | |
a72e4c9f | 6149 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6150 | |
89b667f8 JB |
6151 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6152 | if (encoder->pre_pll_enable) | |
6153 | encoder->pre_pll_enable(encoder); | |
6154 | ||
cd2d34d9 VS |
6155 | if (IS_CHERRYVIEW(dev)) { |
6156 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6157 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6158 | } else { | |
6159 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6160 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6161 | } |
89b667f8 JB |
6162 | |
6163 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6164 | if (encoder->pre_enable) | |
6165 | encoder->pre_enable(encoder); | |
6166 | ||
2dd24552 JB |
6167 | i9xx_pfit_enable(intel_crtc); |
6168 | ||
b95c5321 | 6169 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6170 | |
caed361d | 6171 | intel_update_watermarks(crtc); |
e1fdc473 | 6172 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6173 | |
4b3a9526 VS |
6174 | assert_vblank_disabled(crtc); |
6175 | drm_crtc_vblank_on(crtc); | |
6176 | ||
f9b61ff6 DV |
6177 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6178 | encoder->enable(encoder); | |
89b667f8 JB |
6179 | } |
6180 | ||
f13c2ef3 DV |
6181 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6182 | { | |
6183 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6184 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6185 | |
6e3c9717 ACO |
6186 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6187 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6188 | } |
6189 | ||
0b8765c6 | 6190 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6191 | { |
6192 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6193 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6194 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6195 | struct intel_encoder *encoder; |
b95c5321 ML |
6196 | struct intel_crtc_state *pipe_config = |
6197 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6198 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6199 | |
53d9f4e9 | 6200 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6201 | return; |
6202 | ||
f13c2ef3 DV |
6203 | i9xx_set_pll_dividers(intel_crtc); |
6204 | ||
37a5650b | 6205 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6206 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6207 | |
6208 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6209 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6210 | |
5b18e57c DV |
6211 | i9xx_set_pipeconf(intel_crtc); |
6212 | ||
f7abfe8b | 6213 | intel_crtc->active = true; |
6b383a7f | 6214 | |
4a3436e8 | 6215 | if (!IS_GEN2(dev)) |
a72e4c9f | 6216 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6217 | |
9d6d9f19 MK |
6218 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6219 | if (encoder->pre_enable) | |
6220 | encoder->pre_enable(encoder); | |
6221 | ||
f6736a1a DV |
6222 | i9xx_enable_pll(intel_crtc); |
6223 | ||
2dd24552 JB |
6224 | i9xx_pfit_enable(intel_crtc); |
6225 | ||
b95c5321 | 6226 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6227 | |
f37fcc2a | 6228 | intel_update_watermarks(crtc); |
e1fdc473 | 6229 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6230 | |
4b3a9526 VS |
6231 | assert_vblank_disabled(crtc); |
6232 | drm_crtc_vblank_on(crtc); | |
6233 | ||
f9b61ff6 DV |
6234 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6235 | encoder->enable(encoder); | |
0b8765c6 | 6236 | } |
79e53945 | 6237 | |
87476d63 DV |
6238 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6239 | { | |
6240 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6241 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6242 | |
6e3c9717 | 6243 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6244 | return; |
87476d63 | 6245 | |
328d8e82 | 6246 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6247 | |
328d8e82 DV |
6248 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6249 | I915_READ(PFIT_CONTROL)); | |
6250 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6251 | } |
6252 | ||
0b8765c6 JB |
6253 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6254 | { | |
6255 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 6256 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 | 6257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6258 | struct intel_encoder *encoder; |
0b8765c6 | 6259 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6260 | |
6304cd91 VS |
6261 | /* |
6262 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6263 | * wait for planes to fully turn off before disabling the pipe. | |
6264 | */ | |
90e83e53 ACO |
6265 | if (IS_GEN2(dev)) |
6266 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6267 | |
4b3a9526 VS |
6268 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6269 | encoder->disable(encoder); | |
6270 | ||
f9b61ff6 DV |
6271 | drm_crtc_vblank_off(crtc); |
6272 | assert_vblank_disabled(crtc); | |
6273 | ||
575f7ab7 | 6274 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6275 | |
87476d63 | 6276 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6277 | |
89b667f8 JB |
6278 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6279 | if (encoder->post_disable) | |
6280 | encoder->post_disable(encoder); | |
6281 | ||
a65347ba | 6282 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6283 | if (IS_CHERRYVIEW(dev)) |
6284 | chv_disable_pll(dev_priv, pipe); | |
6285 | else if (IS_VALLEYVIEW(dev)) | |
6286 | vlv_disable_pll(dev_priv, pipe); | |
6287 | else | |
1c4e0274 | 6288 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6289 | } |
0b8765c6 | 6290 | |
d6db995f VS |
6291 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6292 | if (encoder->post_pll_disable) | |
6293 | encoder->post_pll_disable(encoder); | |
6294 | ||
4a3436e8 | 6295 | if (!IS_GEN2(dev)) |
a72e4c9f | 6296 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6297 | } |
6298 | ||
b17d48e2 ML |
6299 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6300 | { | |
842e0307 | 6301 | struct intel_encoder *encoder; |
b17d48e2 ML |
6302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6303 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6304 | enum intel_display_power_domain domain; | |
6305 | unsigned long domains; | |
6306 | ||
6307 | if (!intel_crtc->active) | |
6308 | return; | |
6309 | ||
a539205a | 6310 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
5a21b665 | 6311 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6312 | |
2622a081 | 6313 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6314 | |
6315 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6316 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6317 | } |
6318 | ||
b17d48e2 | 6319 | dev_priv->display.crtc_disable(crtc); |
842e0307 | 6320 | |
78108b7c VS |
6321 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6322 | crtc->base.id, crtc->name); | |
842e0307 ML |
6323 | |
6324 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6325 | crtc->state->active = false; | |
37d9078b | 6326 | intel_crtc->active = false; |
842e0307 ML |
6327 | crtc->enabled = false; |
6328 | crtc->state->connector_mask = 0; | |
6329 | crtc->state->encoder_mask = 0; | |
6330 | ||
6331 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6332 | encoder->base.crtc = NULL; | |
6333 | ||
58f9c0bc | 6334 | intel_fbc_disable(intel_crtc); |
37d9078b | 6335 | intel_update_watermarks(crtc); |
1f7457b1 | 6336 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6337 | |
6338 | domains = intel_crtc->enabled_power_domains; | |
6339 | for_each_power_domain(domain, domains) | |
6340 | intel_display_power_put(dev_priv, domain); | |
6341 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6342 | |
6343 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6344 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6345 | } |
6346 | ||
6b72d486 ML |
6347 | /* |
6348 | * turn all crtc's off, but do not adjust state | |
6349 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6350 | */ | |
70e0bd74 | 6351 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6352 | { |
e2c8b870 | 6353 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6354 | struct drm_atomic_state *state; |
e2c8b870 | 6355 | int ret; |
70e0bd74 | 6356 | |
e2c8b870 ML |
6357 | state = drm_atomic_helper_suspend(dev); |
6358 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6359 | if (ret) |
6360 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6361 | else |
6362 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6363 | return ret; |
ee7b9f93 JB |
6364 | } |
6365 | ||
ea5b213a | 6366 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6367 | { |
4ef69c7a | 6368 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6369 | |
ea5b213a CW |
6370 | drm_encoder_cleanup(encoder); |
6371 | kfree(intel_encoder); | |
7e7d76c3 JB |
6372 | } |
6373 | ||
0a91ca29 DV |
6374 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6375 | * internal consistency). */ | |
5a21b665 | 6376 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6377 | { |
5a21b665 | 6378 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6379 | |
6380 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6381 | connector->base.base.id, | |
6382 | connector->base.name); | |
6383 | ||
0a91ca29 | 6384 | if (connector->get_hw_state(connector)) { |
e85376cb | 6385 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6386 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6387 | |
35dd3c64 ML |
6388 | I915_STATE_WARN(!crtc, |
6389 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6390 | |
35dd3c64 ML |
6391 | if (!crtc) |
6392 | return; | |
6393 | ||
6394 | I915_STATE_WARN(!crtc->state->active, | |
6395 | "connector is active, but attached crtc isn't\n"); | |
6396 | ||
e85376cb | 6397 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6398 | return; |
6399 | ||
e85376cb | 6400 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6401 | "atomic encoder doesn't match attached encoder\n"); |
6402 | ||
e85376cb | 6403 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6404 | "attached encoder crtc differs from connector crtc\n"); |
6405 | } else { | |
4d688a2a ML |
6406 | I915_STATE_WARN(crtc && crtc->state->active, |
6407 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6408 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6409 | "best encoder set without crtc!\n"); |
0a91ca29 | 6410 | } |
79e53945 JB |
6411 | } |
6412 | ||
08d9bc92 ACO |
6413 | int intel_connector_init(struct intel_connector *connector) |
6414 | { | |
5350a031 | 6415 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6416 | |
5350a031 | 6417 | if (!connector->base.state) |
08d9bc92 ACO |
6418 | return -ENOMEM; |
6419 | ||
08d9bc92 ACO |
6420 | return 0; |
6421 | } | |
6422 | ||
6423 | struct intel_connector *intel_connector_alloc(void) | |
6424 | { | |
6425 | struct intel_connector *connector; | |
6426 | ||
6427 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6428 | if (!connector) | |
6429 | return NULL; | |
6430 | ||
6431 | if (intel_connector_init(connector) < 0) { | |
6432 | kfree(connector); | |
6433 | return NULL; | |
6434 | } | |
6435 | ||
6436 | return connector; | |
6437 | } | |
6438 | ||
f0947c37 DV |
6439 | /* Simple connector->get_hw_state implementation for encoders that support only |
6440 | * one connector and no cloning and hence the encoder state determines the state | |
6441 | * of the connector. */ | |
6442 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6443 | { |
24929352 | 6444 | enum pipe pipe = 0; |
f0947c37 | 6445 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6446 | |
f0947c37 | 6447 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6448 | } |
6449 | ||
6d293983 | 6450 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6451 | { |
6d293983 ACO |
6452 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6453 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6454 | |
6455 | return 0; | |
6456 | } | |
6457 | ||
6d293983 | 6458 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6459 | struct intel_crtc_state *pipe_config) |
1857e1da | 6460 | { |
6d293983 ACO |
6461 | struct drm_atomic_state *state = pipe_config->base.state; |
6462 | struct intel_crtc *other_crtc; | |
6463 | struct intel_crtc_state *other_crtc_state; | |
6464 | ||
1857e1da DV |
6465 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6466 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6467 | if (pipe_config->fdi_lanes > 4) { | |
6468 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6469 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6470 | return -EINVAL; |
1857e1da DV |
6471 | } |
6472 | ||
bafb6553 | 6473 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6474 | if (pipe_config->fdi_lanes > 2) { |
6475 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6476 | pipe_config->fdi_lanes); | |
6d293983 | 6477 | return -EINVAL; |
1857e1da | 6478 | } else { |
6d293983 | 6479 | return 0; |
1857e1da DV |
6480 | } |
6481 | } | |
6482 | ||
6483 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6484 | return 0; |
1857e1da DV |
6485 | |
6486 | /* Ivybridge 3 pipe is really complicated */ | |
6487 | switch (pipe) { | |
6488 | case PIPE_A: | |
6d293983 | 6489 | return 0; |
1857e1da | 6490 | case PIPE_B: |
6d293983 ACO |
6491 | if (pipe_config->fdi_lanes <= 2) |
6492 | return 0; | |
6493 | ||
6494 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6495 | other_crtc_state = | |
6496 | intel_atomic_get_crtc_state(state, other_crtc); | |
6497 | if (IS_ERR(other_crtc_state)) | |
6498 | return PTR_ERR(other_crtc_state); | |
6499 | ||
6500 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6501 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6502 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6503 | return -EINVAL; |
1857e1da | 6504 | } |
6d293983 | 6505 | return 0; |
1857e1da | 6506 | case PIPE_C: |
251cc67c VS |
6507 | if (pipe_config->fdi_lanes > 2) { |
6508 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6509 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6510 | return -EINVAL; |
251cc67c | 6511 | } |
6d293983 ACO |
6512 | |
6513 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6514 | other_crtc_state = | |
6515 | intel_atomic_get_crtc_state(state, other_crtc); | |
6516 | if (IS_ERR(other_crtc_state)) | |
6517 | return PTR_ERR(other_crtc_state); | |
6518 | ||
6519 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6520 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6521 | return -EINVAL; |
1857e1da | 6522 | } |
6d293983 | 6523 | return 0; |
1857e1da DV |
6524 | default: |
6525 | BUG(); | |
6526 | } | |
6527 | } | |
6528 | ||
e29c22c0 DV |
6529 | #define RETRY 1 |
6530 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6531 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6532 | { |
1857e1da | 6533 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6534 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6535 | int lane, link_bw, fdi_dotclock, ret; |
6536 | bool needs_recompute = false; | |
877d48d5 | 6537 | |
e29c22c0 | 6538 | retry: |
877d48d5 DV |
6539 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6540 | * each output octet as 10 bits. The actual frequency | |
6541 | * is stored as a divider into a 100MHz clock, and the | |
6542 | * mode pixel clock is stored in units of 1KHz. | |
6543 | * Hence the bw of each lane in terms of the mode signal | |
6544 | * is: | |
6545 | */ | |
21a727b3 | 6546 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6547 | |
241bfc38 | 6548 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6549 | |
2bd89a07 | 6550 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6551 | pipe_config->pipe_bpp); |
6552 | ||
6553 | pipe_config->fdi_lanes = lane; | |
6554 | ||
2bd89a07 | 6555 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6556 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6557 | |
e3b247da | 6558 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6559 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6560 | pipe_config->pipe_bpp -= 2*3; |
6561 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6562 | pipe_config->pipe_bpp); | |
6563 | needs_recompute = true; | |
6564 | pipe_config->bw_constrained = true; | |
6565 | ||
6566 | goto retry; | |
6567 | } | |
6568 | ||
6569 | if (needs_recompute) | |
6570 | return RETRY; | |
6571 | ||
6d293983 | 6572 | return ret; |
877d48d5 DV |
6573 | } |
6574 | ||
8cfb3407 VS |
6575 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6576 | struct intel_crtc_state *pipe_config) | |
6577 | { | |
6578 | if (pipe_config->pipe_bpp > 24) | |
6579 | return false; | |
6580 | ||
6581 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6582 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6583 | return true; |
6584 | ||
6585 | /* | |
b432e5cf VS |
6586 | * We compare against max which means we must take |
6587 | * the increased cdclk requirement into account when | |
6588 | * calculating the new cdclk. | |
6589 | * | |
6590 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6591 | */ |
6592 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6593 | dev_priv->max_cdclk_freq * 95 / 100; | |
6594 | } | |
6595 | ||
42db64ef | 6596 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6597 | struct intel_crtc_state *pipe_config) |
42db64ef | 6598 | { |
8cfb3407 | 6599 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6600 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 6601 | |
d330a953 | 6602 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6603 | hsw_crtc_supports_ips(crtc) && |
6604 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6605 | } |
6606 | ||
39acb4aa VS |
6607 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6608 | { | |
6609 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6610 | ||
6611 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6612 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6613 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6614 | } | |
6615 | ||
a43f6e0f | 6616 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6617 | struct intel_crtc_state *pipe_config) |
79e53945 | 6618 | { |
a43f6e0f | 6619 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6620 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 6621 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 6622 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 6623 | |
cf532bb2 | 6624 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 6625 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6626 | |
6627 | /* | |
39acb4aa | 6628 | * Enable double wide mode when the dot clock |
cf532bb2 | 6629 | * is > 90% of the (display) core speed. |
cf532bb2 | 6630 | */ |
39acb4aa VS |
6631 | if (intel_crtc_supports_double_wide(crtc) && |
6632 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 6633 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 6634 | pipe_config->double_wide = true; |
ad3a4479 | 6635 | } |
f3261156 | 6636 | } |
ad3a4479 | 6637 | |
f3261156 VS |
6638 | if (adjusted_mode->crtc_clock > clock_limit) { |
6639 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6640 | adjusted_mode->crtc_clock, clock_limit, | |
6641 | yesno(pipe_config->double_wide)); | |
6642 | return -EINVAL; | |
2c07245f | 6643 | } |
89749350 | 6644 | |
1d1d0e27 VS |
6645 | /* |
6646 | * Pipe horizontal size must be even in: | |
6647 | * - DVO ganged mode | |
6648 | * - LVDS dual channel mode | |
6649 | * - Double wide pipe | |
6650 | */ | |
2d84d2b3 | 6651 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6652 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6653 | pipe_config->pipe_src_w &= ~1; | |
6654 | ||
8693a824 DL |
6655 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6656 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6657 | */ |
6658 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6659 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6660 | return -EINVAL; |
44f46b42 | 6661 | |
f5adf94e | 6662 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6663 | hsw_compute_ips_config(crtc, pipe_config); |
6664 | ||
877d48d5 | 6665 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6666 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6667 | |
cf5a15be | 6668 | return 0; |
79e53945 JB |
6669 | } |
6670 | ||
1652d19e VS |
6671 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6672 | { | |
6673 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 6674 | uint32_t cdctl; |
1652d19e | 6675 | |
ea61791e | 6676 | skl_dpll0_update(dev_priv); |
1652d19e | 6677 | |
63911d72 | 6678 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 6679 | return dev_priv->cdclk_pll.ref; |
1652d19e | 6680 | |
ea61791e | 6681 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 6682 | |
63911d72 | 6683 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
6684 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6685 | case CDCLK_FREQ_450_432: | |
6686 | return 432000; | |
6687 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 6688 | return 308571; |
ea61791e VS |
6689 | case CDCLK_FREQ_540: |
6690 | return 540000; | |
1652d19e | 6691 | case CDCLK_FREQ_675_617: |
487ed2e4 | 6692 | return 617143; |
1652d19e | 6693 | default: |
ea61791e | 6694 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6695 | } |
6696 | } else { | |
1652d19e VS |
6697 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6698 | case CDCLK_FREQ_450_432: | |
6699 | return 450000; | |
6700 | case CDCLK_FREQ_337_308: | |
6701 | return 337500; | |
ea61791e VS |
6702 | case CDCLK_FREQ_540: |
6703 | return 540000; | |
1652d19e VS |
6704 | case CDCLK_FREQ_675_617: |
6705 | return 675000; | |
6706 | default: | |
ea61791e | 6707 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6708 | } |
6709 | } | |
6710 | ||
709e05c3 | 6711 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
6712 | } |
6713 | ||
83d7c81f VS |
6714 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
6715 | { | |
6716 | u32 val; | |
6717 | ||
6718 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 6719 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
6720 | |
6721 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 6722 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 6723 | return; |
83d7c81f | 6724 | |
1c3f7700 ID |
6725 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
6726 | return; | |
83d7c81f VS |
6727 | |
6728 | val = I915_READ(BXT_DE_PLL_CTL); | |
6729 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
6730 | dev_priv->cdclk_pll.ref; | |
6731 | } | |
6732 | ||
acd3f3d3 BP |
6733 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6734 | { | |
6735 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
6736 | u32 divider; |
6737 | int div, vco; | |
acd3f3d3 | 6738 | |
83d7c81f VS |
6739 | bxt_de_pll_update(dev_priv); |
6740 | ||
f5986242 VS |
6741 | vco = dev_priv->cdclk_pll.vco; |
6742 | if (vco == 0) | |
6743 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 6744 | |
f5986242 | 6745 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 6746 | |
f5986242 | 6747 | switch (divider) { |
acd3f3d3 | 6748 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
6749 | div = 2; |
6750 | break; | |
acd3f3d3 | 6751 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
6752 | div = 3; |
6753 | break; | |
acd3f3d3 | 6754 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
6755 | div = 4; |
6756 | break; | |
acd3f3d3 | 6757 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
6758 | div = 8; |
6759 | break; | |
6760 | default: | |
6761 | MISSING_CASE(divider); | |
6762 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
6763 | } |
6764 | ||
f5986242 | 6765 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
6766 | } |
6767 | ||
1652d19e VS |
6768 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6769 | { | |
fac5e23e | 6770 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6771 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6772 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6773 | ||
6774 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6775 | return 800000; | |
6776 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6777 | return 450000; | |
6778 | else if (freq == LCPLL_CLK_FREQ_450) | |
6779 | return 450000; | |
6780 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6781 | return 540000; | |
6782 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6783 | return 337500; | |
6784 | else | |
6785 | return 675000; | |
6786 | } | |
6787 | ||
6788 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6789 | { | |
fac5e23e | 6790 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6791 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6792 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6793 | ||
6794 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6795 | return 800000; | |
6796 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6797 | return 450000; | |
6798 | else if (freq == LCPLL_CLK_FREQ_450) | |
6799 | return 450000; | |
6800 | else if (IS_HSW_ULT(dev)) | |
6801 | return 337500; | |
6802 | else | |
6803 | return 540000; | |
79e53945 JB |
6804 | } |
6805 | ||
25eb05fc JB |
6806 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6807 | { | |
bfa7df01 VS |
6808 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6809 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6810 | } |
6811 | ||
b37a6434 VS |
6812 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6813 | { | |
6814 | return 450000; | |
6815 | } | |
6816 | ||
e70236a8 JB |
6817 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6818 | { | |
6819 | return 400000; | |
6820 | } | |
79e53945 | 6821 | |
e70236a8 | 6822 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6823 | { |
e907f170 | 6824 | return 333333; |
e70236a8 | 6825 | } |
79e53945 | 6826 | |
e70236a8 JB |
6827 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6828 | { | |
6829 | return 200000; | |
6830 | } | |
79e53945 | 6831 | |
257a7ffc DV |
6832 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6833 | { | |
6834 | u16 gcfgc = 0; | |
6835 | ||
6836 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6837 | ||
6838 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6839 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6840 | return 266667; |
257a7ffc | 6841 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6842 | return 333333; |
257a7ffc | 6843 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6844 | return 444444; |
257a7ffc DV |
6845 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6846 | return 200000; | |
6847 | default: | |
6848 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6849 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6850 | return 133333; |
257a7ffc | 6851 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6852 | return 166667; |
257a7ffc DV |
6853 | } |
6854 | } | |
6855 | ||
e70236a8 JB |
6856 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6857 | { | |
6858 | u16 gcfgc = 0; | |
79e53945 | 6859 | |
e70236a8 JB |
6860 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6861 | ||
6862 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6863 | return 133333; |
e70236a8 JB |
6864 | else { |
6865 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6866 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6867 | return 333333; |
e70236a8 JB |
6868 | default: |
6869 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6870 | return 190000; | |
79e53945 | 6871 | } |
e70236a8 JB |
6872 | } |
6873 | } | |
6874 | ||
6875 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6876 | { | |
e907f170 | 6877 | return 266667; |
e70236a8 JB |
6878 | } |
6879 | ||
1b1d2716 | 6880 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6881 | { |
6882 | u16 hpllcc = 0; | |
1b1d2716 | 6883 | |
65cd2b3f VS |
6884 | /* |
6885 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6886 | * encoding is different :( | |
6887 | * FIXME is this the right way to detect 852GM/852GMV? | |
6888 | */ | |
6889 | if (dev->pdev->revision == 0x1) | |
6890 | return 133333; | |
6891 | ||
1b1d2716 VS |
6892 | pci_bus_read_config_word(dev->pdev->bus, |
6893 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6894 | ||
e70236a8 JB |
6895 | /* Assume that the hardware is in the high speed state. This |
6896 | * should be the default. | |
6897 | */ | |
6898 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6899 | case GC_CLOCK_133_200: | |
1b1d2716 | 6900 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6901 | case GC_CLOCK_100_200: |
6902 | return 200000; | |
6903 | case GC_CLOCK_166_250: | |
6904 | return 250000; | |
6905 | case GC_CLOCK_100_133: | |
e907f170 | 6906 | return 133333; |
1b1d2716 VS |
6907 | case GC_CLOCK_133_266: |
6908 | case GC_CLOCK_133_266_2: | |
6909 | case GC_CLOCK_166_266: | |
6910 | return 266667; | |
e70236a8 | 6911 | } |
79e53945 | 6912 | |
e70236a8 JB |
6913 | /* Shouldn't happen */ |
6914 | return 0; | |
6915 | } | |
79e53945 | 6916 | |
e70236a8 JB |
6917 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6918 | { | |
e907f170 | 6919 | return 133333; |
79e53945 JB |
6920 | } |
6921 | ||
34edce2f VS |
6922 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6923 | { | |
fac5e23e | 6924 | struct drm_i915_private *dev_priv = to_i915(dev); |
34edce2f VS |
6925 | static const unsigned int blb_vco[8] = { |
6926 | [0] = 3200000, | |
6927 | [1] = 4000000, | |
6928 | [2] = 5333333, | |
6929 | [3] = 4800000, | |
6930 | [4] = 6400000, | |
6931 | }; | |
6932 | static const unsigned int pnv_vco[8] = { | |
6933 | [0] = 3200000, | |
6934 | [1] = 4000000, | |
6935 | [2] = 5333333, | |
6936 | [3] = 4800000, | |
6937 | [4] = 2666667, | |
6938 | }; | |
6939 | static const unsigned int cl_vco[8] = { | |
6940 | [0] = 3200000, | |
6941 | [1] = 4000000, | |
6942 | [2] = 5333333, | |
6943 | [3] = 6400000, | |
6944 | [4] = 3333333, | |
6945 | [5] = 3566667, | |
6946 | [6] = 4266667, | |
6947 | }; | |
6948 | static const unsigned int elk_vco[8] = { | |
6949 | [0] = 3200000, | |
6950 | [1] = 4000000, | |
6951 | [2] = 5333333, | |
6952 | [3] = 4800000, | |
6953 | }; | |
6954 | static const unsigned int ctg_vco[8] = { | |
6955 | [0] = 3200000, | |
6956 | [1] = 4000000, | |
6957 | [2] = 5333333, | |
6958 | [3] = 6400000, | |
6959 | [4] = 2666667, | |
6960 | [5] = 4266667, | |
6961 | }; | |
6962 | const unsigned int *vco_table; | |
6963 | unsigned int vco; | |
6964 | uint8_t tmp = 0; | |
6965 | ||
6966 | /* FIXME other chipsets? */ | |
6967 | if (IS_GM45(dev)) | |
6968 | vco_table = ctg_vco; | |
6969 | else if (IS_G4X(dev)) | |
6970 | vco_table = elk_vco; | |
6971 | else if (IS_CRESTLINE(dev)) | |
6972 | vco_table = cl_vco; | |
6973 | else if (IS_PINEVIEW(dev)) | |
6974 | vco_table = pnv_vco; | |
6975 | else if (IS_G33(dev)) | |
6976 | vco_table = blb_vco; | |
6977 | else | |
6978 | return 0; | |
6979 | ||
6980 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6981 | ||
6982 | vco = vco_table[tmp & 0x7]; | |
6983 | if (vco == 0) | |
6984 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6985 | else | |
6986 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6987 | ||
6988 | return vco; | |
6989 | } | |
6990 | ||
6991 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6992 | { | |
6993 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6994 | uint16_t tmp = 0; | |
6995 | ||
6996 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6997 | ||
6998 | cdclk_sel = (tmp >> 12) & 0x1; | |
6999 | ||
7000 | switch (vco) { | |
7001 | case 2666667: | |
7002 | case 4000000: | |
7003 | case 5333333: | |
7004 | return cdclk_sel ? 333333 : 222222; | |
7005 | case 3200000: | |
7006 | return cdclk_sel ? 320000 : 228571; | |
7007 | default: | |
7008 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7009 | return 222222; | |
7010 | } | |
7011 | } | |
7012 | ||
7013 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7014 | { | |
7015 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7016 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7017 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7018 | const uint8_t *div_table; | |
7019 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7020 | uint16_t tmp = 0; | |
7021 | ||
7022 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7023 | ||
7024 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7025 | ||
7026 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7027 | goto fail; | |
7028 | ||
7029 | switch (vco) { | |
7030 | case 3200000: | |
7031 | div_table = div_3200; | |
7032 | break; | |
7033 | case 4000000: | |
7034 | div_table = div_4000; | |
7035 | break; | |
7036 | case 5333333: | |
7037 | div_table = div_5333; | |
7038 | break; | |
7039 | default: | |
7040 | goto fail; | |
7041 | } | |
7042 | ||
7043 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7044 | ||
caf4e252 | 7045 | fail: |
34edce2f VS |
7046 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7047 | return 200000; | |
7048 | } | |
7049 | ||
7050 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7051 | { | |
7052 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7053 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7054 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7055 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7056 | const uint8_t *div_table; | |
7057 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7058 | uint16_t tmp = 0; | |
7059 | ||
7060 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7061 | ||
7062 | cdclk_sel = (tmp >> 4) & 0x7; | |
7063 | ||
7064 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7065 | goto fail; | |
7066 | ||
7067 | switch (vco) { | |
7068 | case 3200000: | |
7069 | div_table = div_3200; | |
7070 | break; | |
7071 | case 4000000: | |
7072 | div_table = div_4000; | |
7073 | break; | |
7074 | case 4800000: | |
7075 | div_table = div_4800; | |
7076 | break; | |
7077 | case 5333333: | |
7078 | div_table = div_5333; | |
7079 | break; | |
7080 | default: | |
7081 | goto fail; | |
7082 | } | |
7083 | ||
7084 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7085 | ||
caf4e252 | 7086 | fail: |
34edce2f VS |
7087 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7088 | return 190476; | |
7089 | } | |
7090 | ||
2c07245f | 7091 | static void |
a65851af | 7092 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7093 | { |
a65851af VS |
7094 | while (*num > DATA_LINK_M_N_MASK || |
7095 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7096 | *num >>= 1; |
7097 | *den >>= 1; | |
7098 | } | |
7099 | } | |
7100 | ||
a65851af VS |
7101 | static void compute_m_n(unsigned int m, unsigned int n, |
7102 | uint32_t *ret_m, uint32_t *ret_n) | |
7103 | { | |
7104 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7105 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7106 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7107 | } | |
7108 | ||
e69d0bc1 DV |
7109 | void |
7110 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7111 | int pixel_clock, int link_clock, | |
7112 | struct intel_link_m_n *m_n) | |
2c07245f | 7113 | { |
e69d0bc1 | 7114 | m_n->tu = 64; |
a65851af VS |
7115 | |
7116 | compute_m_n(bits_per_pixel * pixel_clock, | |
7117 | link_clock * nlanes * 8, | |
7118 | &m_n->gmch_m, &m_n->gmch_n); | |
7119 | ||
7120 | compute_m_n(pixel_clock, link_clock, | |
7121 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7122 | } |
7123 | ||
a7615030 CW |
7124 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7125 | { | |
d330a953 JN |
7126 | if (i915.panel_use_ssc >= 0) |
7127 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7128 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7129 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7130 | } |
7131 | ||
7429e9d4 | 7132 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7133 | { |
7df00d7a | 7134 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7135 | } |
f47709a9 | 7136 | |
7429e9d4 DV |
7137 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7138 | { | |
7139 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7140 | } |
7141 | ||
f47709a9 | 7142 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7143 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7144 | struct dpll *reduced_clock) |
a7516a05 | 7145 | { |
f47709a9 | 7146 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7147 | u32 fp, fp2 = 0; |
7148 | ||
7149 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7150 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7151 | if (reduced_clock) |
7429e9d4 | 7152 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7153 | } else { |
190f68c5 | 7154 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7155 | if (reduced_clock) |
7429e9d4 | 7156 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7157 | } |
7158 | ||
190f68c5 | 7159 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7160 | |
f47709a9 | 7161 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7162 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7163 | reduced_clock) { |
190f68c5 | 7164 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7165 | crtc->lowfreq_avail = true; |
a7516a05 | 7166 | } else { |
190f68c5 | 7167 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7168 | } |
7169 | } | |
7170 | ||
5e69f97f CML |
7171 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7172 | pipe) | |
89b667f8 JB |
7173 | { |
7174 | u32 reg_val; | |
7175 | ||
7176 | /* | |
7177 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7178 | * and set it to a reasonable value instead. | |
7179 | */ | |
ab3c759a | 7180 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7181 | reg_val &= 0xffffff00; |
7182 | reg_val |= 0x00000030; | |
ab3c759a | 7183 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7184 | |
ab3c759a | 7185 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7186 | reg_val &= 0x8cffffff; |
7187 | reg_val = 0x8c000000; | |
ab3c759a | 7188 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7189 | |
ab3c759a | 7190 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7191 | reg_val &= 0xffffff00; |
ab3c759a | 7192 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7193 | |
ab3c759a | 7194 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7195 | reg_val &= 0x00ffffff; |
7196 | reg_val |= 0xb0000000; | |
ab3c759a | 7197 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7198 | } |
7199 | ||
b551842d DV |
7200 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7201 | struct intel_link_m_n *m_n) | |
7202 | { | |
7203 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7204 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7205 | int pipe = crtc->pipe; |
7206 | ||
e3b95f1e DV |
7207 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7208 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7209 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7210 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7211 | } |
7212 | ||
7213 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7214 | struct intel_link_m_n *m_n, |
7215 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7216 | { |
7217 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7218 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7219 | int pipe = crtc->pipe; |
6e3c9717 | 7220 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7221 | |
7222 | if (INTEL_INFO(dev)->gen >= 5) { | |
7223 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7224 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7225 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7226 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7227 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7228 | * for gen < 8) and if DRRS is supported (to make sure the | |
7229 | * registers are not unnecessarily accessed). | |
7230 | */ | |
44395bfe | 7231 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7232 | crtc->config->has_drrs) { |
f769cd24 VK |
7233 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7234 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7235 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7236 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7237 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7238 | } | |
b551842d | 7239 | } else { |
e3b95f1e DV |
7240 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7241 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7242 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7243 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7244 | } |
7245 | } | |
7246 | ||
fe3cd48d | 7247 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7248 | { |
fe3cd48d R |
7249 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7250 | ||
7251 | if (m_n == M1_N1) { | |
7252 | dp_m_n = &crtc->config->dp_m_n; | |
7253 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7254 | } else if (m_n == M2_N2) { | |
7255 | ||
7256 | /* | |
7257 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7258 | * needs to be programmed into M1_N1. | |
7259 | */ | |
7260 | dp_m_n = &crtc->config->dp_m2_n2; | |
7261 | } else { | |
7262 | DRM_ERROR("Unsupported divider value\n"); | |
7263 | return; | |
7264 | } | |
7265 | ||
6e3c9717 ACO |
7266 | if (crtc->config->has_pch_encoder) |
7267 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7268 | else |
fe3cd48d | 7269 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7270 | } |
7271 | ||
251ac862 DV |
7272 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7273 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7274 | { |
03ed5cbf | 7275 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7276 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7277 | if (crtc->pipe != PIPE_A) |
7278 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7279 | |
cd2d34d9 | 7280 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7281 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7282 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7283 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7284 | ||
03ed5cbf VS |
7285 | pipe_config->dpll_hw_state.dpll_md = |
7286 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7287 | } | |
bdd4b6a6 | 7288 | |
03ed5cbf VS |
7289 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7290 | struct intel_crtc_state *pipe_config) | |
7291 | { | |
7292 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7293 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7294 | if (crtc->pipe != PIPE_A) |
7295 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7296 | ||
cd2d34d9 | 7297 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7298 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7299 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7300 | ||
03ed5cbf VS |
7301 | pipe_config->dpll_hw_state.dpll_md = |
7302 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7303 | } |
7304 | ||
d288f65f | 7305 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7306 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7307 | { |
f47709a9 | 7308 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7309 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7310 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7311 | u32 mdiv; |
a0c4da24 | 7312 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7313 | u32 coreclk, reg_val; |
a0c4da24 | 7314 | |
cd2d34d9 VS |
7315 | /* Enable Refclk */ |
7316 | I915_WRITE(DPLL(pipe), | |
7317 | pipe_config->dpll_hw_state.dpll & | |
7318 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7319 | ||
7320 | /* No need to actually set up the DPLL with DSI */ | |
7321 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7322 | return; | |
7323 | ||
a580516d | 7324 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7325 | |
d288f65f VS |
7326 | bestn = pipe_config->dpll.n; |
7327 | bestm1 = pipe_config->dpll.m1; | |
7328 | bestm2 = pipe_config->dpll.m2; | |
7329 | bestp1 = pipe_config->dpll.p1; | |
7330 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7331 | |
89b667f8 JB |
7332 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7333 | ||
7334 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7335 | if (pipe == PIPE_B) |
5e69f97f | 7336 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7337 | |
7338 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7339 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7340 | |
7341 | /* Disable target IRef on PLL */ | |
ab3c759a | 7342 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7343 | reg_val &= 0x00ffffff; |
ab3c759a | 7344 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7345 | |
7346 | /* Disable fast lock */ | |
ab3c759a | 7347 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7348 | |
7349 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7350 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7351 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7352 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7353 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7354 | |
7355 | /* | |
7356 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7357 | * but we don't support that). | |
7358 | * Note: don't use the DAC post divider as it seems unstable. | |
7359 | */ | |
7360 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7361 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7362 | |
a0c4da24 | 7363 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7364 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7365 | |
89b667f8 | 7366 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7367 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7368 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7369 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7370 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7371 | 0x009f0003); |
89b667f8 | 7372 | else |
ab3c759a | 7373 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7374 | 0x00d0000f); |
7375 | ||
37a5650b | 7376 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7377 | /* Use SSC source */ |
bdd4b6a6 | 7378 | if (pipe == PIPE_A) |
ab3c759a | 7379 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7380 | 0x0df40000); |
7381 | else | |
ab3c759a | 7382 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7383 | 0x0df70000); |
7384 | } else { /* HDMI or VGA */ | |
7385 | /* Use bend source */ | |
bdd4b6a6 | 7386 | if (pipe == PIPE_A) |
ab3c759a | 7387 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7388 | 0x0df70000); |
7389 | else | |
ab3c759a | 7390 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7391 | 0x0df40000); |
7392 | } | |
a0c4da24 | 7393 | |
ab3c759a | 7394 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7395 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7396 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7397 | coreclk |= 0x01000000; |
ab3c759a | 7398 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7399 | |
ab3c759a | 7400 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7401 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7402 | } |
7403 | ||
d288f65f | 7404 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7405 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7406 | { |
7407 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7408 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7409 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7410 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7411 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7412 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7413 | u32 dpio_val; |
9cbe40c1 | 7414 | int vco; |
9d556c99 | 7415 | |
cd2d34d9 VS |
7416 | /* Enable Refclk and SSC */ |
7417 | I915_WRITE(DPLL(pipe), | |
7418 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7419 | ||
7420 | /* No need to actually set up the DPLL with DSI */ | |
7421 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7422 | return; | |
7423 | ||
d288f65f VS |
7424 | bestn = pipe_config->dpll.n; |
7425 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7426 | bestm1 = pipe_config->dpll.m1; | |
7427 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7428 | bestp1 = pipe_config->dpll.p1; | |
7429 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7430 | vco = pipe_config->dpll.vco; |
a945ce7e | 7431 | dpio_val = 0; |
9cbe40c1 | 7432 | loopfilter = 0; |
9d556c99 | 7433 | |
a580516d | 7434 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7435 | |
9d556c99 CML |
7436 | /* p1 and p2 divider */ |
7437 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7438 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7439 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7440 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7441 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7442 | ||
7443 | /* Feedback post-divider - m2 */ | |
7444 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7445 | ||
7446 | /* Feedback refclk divider - n and m1 */ | |
7447 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7448 | DPIO_CHV_M1_DIV_BY_2 | | |
7449 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7450 | ||
7451 | /* M2 fraction division */ | |
25a25dfc | 7452 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7453 | |
7454 | /* M2 fraction division enable */ | |
a945ce7e VP |
7455 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7456 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7457 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7458 | if (bestm2_frac) | |
7459 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7460 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7461 | |
de3a0fde VP |
7462 | /* Program digital lock detect threshold */ |
7463 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7464 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7465 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7466 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7467 | if (!bestm2_frac) | |
7468 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7469 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7470 | ||
9d556c99 | 7471 | /* Loop filter */ |
9cbe40c1 VP |
7472 | if (vco == 5400000) { |
7473 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7474 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7475 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7476 | tribuf_calcntr = 0x9; | |
7477 | } else if (vco <= 6200000) { | |
7478 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7479 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7480 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7481 | tribuf_calcntr = 0x9; | |
7482 | } else if (vco <= 6480000) { | |
7483 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7484 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7485 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7486 | tribuf_calcntr = 0x8; | |
7487 | } else { | |
7488 | /* Not supported. Apply the same limits as in the max case */ | |
7489 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7490 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7491 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7492 | tribuf_calcntr = 0; | |
7493 | } | |
9d556c99 CML |
7494 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7495 | ||
968040b2 | 7496 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7497 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7498 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7499 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7500 | ||
9d556c99 CML |
7501 | /* AFC Recal */ |
7502 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7503 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7504 | DPIO_AFC_RECAL); | |
7505 | ||
a580516d | 7506 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7507 | } |
7508 | ||
d288f65f VS |
7509 | /** |
7510 | * vlv_force_pll_on - forcibly enable just the PLL | |
7511 | * @dev_priv: i915 private structure | |
7512 | * @pipe: pipe PLL to enable | |
7513 | * @dpll: PLL configuration | |
7514 | * | |
7515 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7516 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7517 | * be enabled. | |
7518 | */ | |
3f36b937 TU |
7519 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7520 | const struct dpll *dpll) | |
d288f65f VS |
7521 | { |
7522 | struct intel_crtc *crtc = | |
7523 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7524 | struct intel_crtc_state *pipe_config; |
7525 | ||
7526 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7527 | if (!pipe_config) | |
7528 | return -ENOMEM; | |
7529 | ||
7530 | pipe_config->base.crtc = &crtc->base; | |
7531 | pipe_config->pixel_multiplier = 1; | |
7532 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7533 | |
7534 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7535 | chv_compute_dpll(crtc, pipe_config); |
7536 | chv_prepare_pll(crtc, pipe_config); | |
7537 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7538 | } else { |
3f36b937 TU |
7539 | vlv_compute_dpll(crtc, pipe_config); |
7540 | vlv_prepare_pll(crtc, pipe_config); | |
7541 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7542 | } |
3f36b937 TU |
7543 | |
7544 | kfree(pipe_config); | |
7545 | ||
7546 | return 0; | |
d288f65f VS |
7547 | } |
7548 | ||
7549 | /** | |
7550 | * vlv_force_pll_off - forcibly disable just the PLL | |
7551 | * @dev_priv: i915 private structure | |
7552 | * @pipe: pipe PLL to disable | |
7553 | * | |
7554 | * Disable the PLL for @pipe. To be used in cases where we need | |
7555 | * the PLL enabled even when @pipe is not going to be enabled. | |
7556 | */ | |
7557 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7558 | { | |
7559 | if (IS_CHERRYVIEW(dev)) | |
7560 | chv_disable_pll(to_i915(dev), pipe); | |
7561 | else | |
7562 | vlv_disable_pll(to_i915(dev), pipe); | |
7563 | } | |
7564 | ||
251ac862 DV |
7565 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7566 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7567 | struct dpll *reduced_clock) |
eb1cbe48 | 7568 | { |
f47709a9 | 7569 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7570 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7571 | u32 dpll; |
190f68c5 | 7572 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7573 | |
190f68c5 | 7574 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7575 | |
eb1cbe48 DV |
7576 | dpll = DPLL_VGA_MODE_DIS; |
7577 | ||
2d84d2b3 | 7578 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7579 | dpll |= DPLLB_MODE_LVDS; |
7580 | else | |
7581 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7582 | |
ef1b460d | 7583 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7584 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7585 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7586 | } |
198a037f | 7587 | |
3d6e9ee0 VS |
7588 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7589 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 7590 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7591 | |
37a5650b | 7592 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 7593 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7594 | |
7595 | /* compute bitmask from p1 value */ | |
7596 | if (IS_PINEVIEW(dev)) | |
7597 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7598 | else { | |
7599 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7600 | if (IS_G4X(dev) && reduced_clock) | |
7601 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7602 | } | |
7603 | switch (clock->p2) { | |
7604 | case 5: | |
7605 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7606 | break; | |
7607 | case 7: | |
7608 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7609 | break; | |
7610 | case 10: | |
7611 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7612 | break; | |
7613 | case 14: | |
7614 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7615 | break; | |
7616 | } | |
7617 | if (INTEL_INFO(dev)->gen >= 4) | |
7618 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7619 | ||
190f68c5 | 7620 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7621 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 7622 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7623 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7624 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7625 | else | |
7626 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7627 | ||
7628 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7629 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7630 | |
eb1cbe48 | 7631 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7632 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7633 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7634 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7635 | } |
7636 | } | |
7637 | ||
251ac862 DV |
7638 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7639 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7640 | struct dpll *reduced_clock) |
eb1cbe48 | 7641 | { |
f47709a9 | 7642 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7643 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7644 | u32 dpll; |
190f68c5 | 7645 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7646 | |
190f68c5 | 7647 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7648 | |
eb1cbe48 DV |
7649 | dpll = DPLL_VGA_MODE_DIS; |
7650 | ||
2d84d2b3 | 7651 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7652 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7653 | } else { | |
7654 | if (clock->p1 == 2) | |
7655 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7656 | else | |
7657 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7658 | if (clock->p2 == 4) | |
7659 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7660 | } | |
7661 | ||
2d84d2b3 | 7662 | if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7663 | dpll |= DPLL_DVO_2X_MODE; |
7664 | ||
2d84d2b3 | 7665 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7666 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7667 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7668 | else | |
7669 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7670 | ||
7671 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7672 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7673 | } |
7674 | ||
8a654f3b | 7675 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7676 | { |
7677 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7678 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 7679 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7680 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7681 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7682 | uint32_t crtc_vtotal, crtc_vblank_end; |
7683 | int vsyncshift = 0; | |
4d8a62ea DV |
7684 | |
7685 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7686 | * the hw state checker will get angry at the mismatch. */ | |
7687 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7688 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7689 | |
609aeaca | 7690 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7691 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7692 | crtc_vtotal -= 1; |
7693 | crtc_vblank_end -= 1; | |
609aeaca | 7694 | |
2d84d2b3 | 7695 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7696 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7697 | else | |
7698 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7699 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7700 | if (vsyncshift < 0) |
7701 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7702 | } |
7703 | ||
7704 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7705 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7706 | |
fe2b8f9d | 7707 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7708 | (adjusted_mode->crtc_hdisplay - 1) | |
7709 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7710 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7711 | (adjusted_mode->crtc_hblank_start - 1) | |
7712 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7713 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7714 | (adjusted_mode->crtc_hsync_start - 1) | |
7715 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7716 | ||
fe2b8f9d | 7717 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7718 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7719 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7720 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7721 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7722 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7723 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7724 | (adjusted_mode->crtc_vsync_start - 1) | |
7725 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7726 | ||
b5e508d4 PZ |
7727 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7728 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7729 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7730 | * bits. */ | |
7731 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7732 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7733 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7734 | ||
bc58be60 JN |
7735 | } |
7736 | ||
7737 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7738 | { | |
7739 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7740 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7741 | enum pipe pipe = intel_crtc->pipe; |
7742 | ||
b0e77b9c PZ |
7743 | /* pipesrc controls the size that is scaled from, which should |
7744 | * always be the user's requested size. | |
7745 | */ | |
7746 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7747 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7748 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7749 | } |
7750 | ||
1bd1bd80 | 7751 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7752 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7753 | { |
7754 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7755 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7756 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7757 | uint32_t tmp; | |
7758 | ||
7759 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7760 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7761 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7762 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7763 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7764 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7765 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7766 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7767 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7768 | |
7769 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7770 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7771 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7772 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7773 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7774 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7775 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7776 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7777 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7778 | |
7779 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7780 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7781 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7782 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7783 | } |
bc58be60 JN |
7784 | } |
7785 | ||
7786 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7787 | struct intel_crtc_state *pipe_config) | |
7788 | { | |
7789 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7790 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7791 | u32 tmp; |
1bd1bd80 DV |
7792 | |
7793 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7794 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7795 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7796 | ||
2d112de7 ACO |
7797 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7798 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7799 | } |
7800 | ||
f6a83288 | 7801 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7802 | struct intel_crtc_state *pipe_config) |
babea61d | 7803 | { |
2d112de7 ACO |
7804 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7805 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7806 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7807 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7808 | |
2d112de7 ACO |
7809 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7810 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7811 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7812 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7813 | |
2d112de7 | 7814 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7815 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7816 | |
2d112de7 ACO |
7817 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7818 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7819 | |
7820 | mode->hsync = drm_mode_hsync(mode); | |
7821 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7822 | drm_mode_set_name(mode); | |
babea61d JB |
7823 | } |
7824 | ||
84b046f3 DV |
7825 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7826 | { | |
7827 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7828 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
7829 | uint32_t pipeconf; |
7830 | ||
9f11a9e4 | 7831 | pipeconf = 0; |
84b046f3 | 7832 | |
b6b5d049 VS |
7833 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7834 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7835 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7836 | |
6e3c9717 | 7837 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7838 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7839 | |
ff9ce46e | 7840 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7841 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7842 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7843 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7844 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7845 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7846 | |
6e3c9717 | 7847 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7848 | case 18: |
7849 | pipeconf |= PIPECONF_6BPC; | |
7850 | break; | |
7851 | case 24: | |
7852 | pipeconf |= PIPECONF_8BPC; | |
7853 | break; | |
7854 | case 30: | |
7855 | pipeconf |= PIPECONF_10BPC; | |
7856 | break; | |
7857 | default: | |
7858 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7859 | BUG(); | |
84b046f3 DV |
7860 | } |
7861 | } | |
7862 | ||
7863 | if (HAS_PIPE_CXSR(dev)) { | |
7864 | if (intel_crtc->lowfreq_avail) { | |
7865 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7866 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7867 | } else { | |
7868 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7869 | } |
7870 | } | |
7871 | ||
6e3c9717 | 7872 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7873 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 7874 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7875 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7876 | else | |
7877 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7878 | } else | |
84b046f3 DV |
7879 | pipeconf |= PIPECONF_PROGRESSIVE; |
7880 | ||
666a4537 WB |
7881 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7882 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7883 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7884 | |
84b046f3 DV |
7885 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7886 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7887 | } | |
7888 | ||
81c97f52 ACO |
7889 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7890 | struct intel_crtc_state *crtc_state) | |
7891 | { | |
7892 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7893 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7894 | const struct intel_limit *limit; |
81c97f52 ACO |
7895 | int refclk = 48000; |
7896 | ||
7897 | memset(&crtc_state->dpll_hw_state, 0, | |
7898 | sizeof(crtc_state->dpll_hw_state)); | |
7899 | ||
2d84d2b3 | 7900 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7901 | if (intel_panel_use_ssc(dev_priv)) { |
7902 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7903 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7904 | } | |
7905 | ||
7906 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7907 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7908 | limit = &intel_limits_i8xx_dvo; |
7909 | } else { | |
7910 | limit = &intel_limits_i8xx_dac; | |
7911 | } | |
7912 | ||
7913 | if (!crtc_state->clock_set && | |
7914 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7915 | refclk, NULL, &crtc_state->dpll)) { | |
7916 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7917 | return -EINVAL; | |
7918 | } | |
7919 | ||
7920 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7921 | ||
7922 | return 0; | |
7923 | } | |
7924 | ||
19ec6693 ACO |
7925 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7926 | struct intel_crtc_state *crtc_state) | |
7927 | { | |
7928 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7929 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7930 | const struct intel_limit *limit; |
19ec6693 ACO |
7931 | int refclk = 96000; |
7932 | ||
7933 | memset(&crtc_state->dpll_hw_state, 0, | |
7934 | sizeof(crtc_state->dpll_hw_state)); | |
7935 | ||
2d84d2b3 | 7936 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7937 | if (intel_panel_use_ssc(dev_priv)) { |
7938 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7939 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7940 | } | |
7941 | ||
7942 | if (intel_is_dual_link_lvds(dev)) | |
7943 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7944 | else | |
7945 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7946 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7947 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7948 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7949 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7950 | limit = &intel_limits_g4x_sdvo; |
7951 | } else { | |
7952 | /* The option is for other outputs */ | |
7953 | limit = &intel_limits_i9xx_sdvo; | |
7954 | } | |
7955 | ||
7956 | if (!crtc_state->clock_set && | |
7957 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7958 | refclk, NULL, &crtc_state->dpll)) { | |
7959 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7960 | return -EINVAL; | |
7961 | } | |
7962 | ||
7963 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7964 | ||
7965 | return 0; | |
7966 | } | |
7967 | ||
70e8aa21 ACO |
7968 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7969 | struct intel_crtc_state *crtc_state) | |
7970 | { | |
7971 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7972 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7973 | const struct intel_limit *limit; |
70e8aa21 ACO |
7974 | int refclk = 96000; |
7975 | ||
7976 | memset(&crtc_state->dpll_hw_state, 0, | |
7977 | sizeof(crtc_state->dpll_hw_state)); | |
7978 | ||
2d84d2b3 | 7979 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7980 | if (intel_panel_use_ssc(dev_priv)) { |
7981 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7982 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7983 | } | |
7984 | ||
7985 | limit = &intel_limits_pineview_lvds; | |
7986 | } else { | |
7987 | limit = &intel_limits_pineview_sdvo; | |
7988 | } | |
7989 | ||
7990 | if (!crtc_state->clock_set && | |
7991 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7992 | refclk, NULL, &crtc_state->dpll)) { | |
7993 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7994 | return -EINVAL; | |
7995 | } | |
7996 | ||
7997 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7998 | ||
7999 | return 0; | |
8000 | } | |
8001 | ||
190f68c5 ACO |
8002 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8003 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8004 | { |
c7653199 | 8005 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8006 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8007 | const struct intel_limit *limit; |
81c97f52 | 8008 | int refclk = 96000; |
79e53945 | 8009 | |
dd3cd74a ACO |
8010 | memset(&crtc_state->dpll_hw_state, 0, |
8011 | sizeof(crtc_state->dpll_hw_state)); | |
8012 | ||
2d84d2b3 | 8013 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8014 | if (intel_panel_use_ssc(dev_priv)) { |
8015 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8016 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8017 | } | |
43565a06 | 8018 | |
70e8aa21 ACO |
8019 | limit = &intel_limits_i9xx_lvds; |
8020 | } else { | |
8021 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8022 | } |
79e53945 | 8023 | |
70e8aa21 ACO |
8024 | if (!crtc_state->clock_set && |
8025 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8026 | refclk, NULL, &crtc_state->dpll)) { | |
8027 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8028 | return -EINVAL; | |
f47709a9 | 8029 | } |
7026d4ac | 8030 | |
81c97f52 | 8031 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8032 | |
c8f7a0db | 8033 | return 0; |
f564048e EA |
8034 | } |
8035 | ||
65b3d6a9 ACO |
8036 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8037 | struct intel_crtc_state *crtc_state) | |
8038 | { | |
8039 | int refclk = 100000; | |
1b6f4958 | 8040 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8041 | |
8042 | memset(&crtc_state->dpll_hw_state, 0, | |
8043 | sizeof(crtc_state->dpll_hw_state)); | |
8044 | ||
65b3d6a9 ACO |
8045 | if (!crtc_state->clock_set && |
8046 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8047 | refclk, NULL, &crtc_state->dpll)) { | |
8048 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8049 | return -EINVAL; | |
8050 | } | |
8051 | ||
8052 | chv_compute_dpll(crtc, crtc_state); | |
8053 | ||
8054 | return 0; | |
8055 | } | |
8056 | ||
8057 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8058 | struct intel_crtc_state *crtc_state) | |
8059 | { | |
8060 | int refclk = 100000; | |
1b6f4958 | 8061 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8062 | |
8063 | memset(&crtc_state->dpll_hw_state, 0, | |
8064 | sizeof(crtc_state->dpll_hw_state)); | |
8065 | ||
65b3d6a9 ACO |
8066 | if (!crtc_state->clock_set && |
8067 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8068 | refclk, NULL, &crtc_state->dpll)) { | |
8069 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8070 | return -EINVAL; | |
8071 | } | |
8072 | ||
8073 | vlv_compute_dpll(crtc, crtc_state); | |
8074 | ||
8075 | return 0; | |
8076 | } | |
8077 | ||
2fa2fe9a | 8078 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8079 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8080 | { |
8081 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8082 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8083 | uint32_t tmp; |
8084 | ||
dc9e7dec VS |
8085 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8086 | return; | |
8087 | ||
2fa2fe9a | 8088 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8089 | if (!(tmp & PFIT_ENABLE)) |
8090 | return; | |
2fa2fe9a | 8091 | |
06922821 | 8092 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8093 | if (INTEL_INFO(dev)->gen < 4) { |
8094 | if (crtc->pipe != PIPE_B) | |
8095 | return; | |
2fa2fe9a DV |
8096 | } else { |
8097 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8098 | return; | |
8099 | } | |
8100 | ||
06922821 | 8101 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8102 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8103 | } |
8104 | ||
acbec814 | 8105 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8106 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8107 | { |
8108 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8109 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8110 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8111 | struct dpll clock; |
acbec814 | 8112 | u32 mdiv; |
662c6ecb | 8113 | int refclk = 100000; |
acbec814 | 8114 | |
b521973b VS |
8115 | /* In case of DSI, DPLL will not be used */ |
8116 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8117 | return; |
8118 | ||
a580516d | 8119 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8120 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8121 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8122 | |
8123 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8124 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8125 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8126 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8127 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8128 | ||
dccbea3b | 8129 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8130 | } |
8131 | ||
5724dbd1 DL |
8132 | static void |
8133 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8134 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8135 | { |
8136 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8137 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8138 | u32 val, base, offset; |
8139 | int pipe = crtc->pipe, plane = crtc->plane; | |
8140 | int fourcc, pixel_format; | |
6761dd31 | 8141 | unsigned int aligned_height; |
b113d5ee | 8142 | struct drm_framebuffer *fb; |
1b842c89 | 8143 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8144 | |
42a7b088 DL |
8145 | val = I915_READ(DSPCNTR(plane)); |
8146 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8147 | return; | |
8148 | ||
d9806c9f | 8149 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8150 | if (!intel_fb) { |
1ad292b5 JB |
8151 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8152 | return; | |
8153 | } | |
8154 | ||
1b842c89 DL |
8155 | fb = &intel_fb->base; |
8156 | ||
18c5247e DV |
8157 | if (INTEL_INFO(dev)->gen >= 4) { |
8158 | if (val & DISPPLANE_TILED) { | |
49af449b | 8159 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8160 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8161 | } | |
8162 | } | |
1ad292b5 JB |
8163 | |
8164 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8165 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8166 | fb->pixel_format = fourcc; |
8167 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8168 | |
8169 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8170 | if (plane_config->tiling) |
1ad292b5 JB |
8171 | offset = I915_READ(DSPTILEOFF(plane)); |
8172 | else | |
8173 | offset = I915_READ(DSPLINOFF(plane)); | |
8174 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8175 | } else { | |
8176 | base = I915_READ(DSPADDR(plane)); | |
8177 | } | |
8178 | plane_config->base = base; | |
8179 | ||
8180 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8181 | fb->width = ((val >> 16) & 0xfff) + 1; |
8182 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8183 | |
8184 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8185 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8186 | |
b113d5ee | 8187 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8188 | fb->pixel_format, |
8189 | fb->modifier[0]); | |
1ad292b5 | 8190 | |
f37b5c2b | 8191 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8192 | |
2844a921 DL |
8193 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8194 | pipe_name(pipe), plane, fb->width, fb->height, | |
8195 | fb->bits_per_pixel, base, fb->pitches[0], | |
8196 | plane_config->size); | |
1ad292b5 | 8197 | |
2d14030b | 8198 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8199 | } |
8200 | ||
70b23a98 | 8201 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8202 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8203 | { |
8204 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8205 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8206 | int pipe = pipe_config->cpu_transcoder; |
8207 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8208 | struct dpll clock; |
0d7b6b11 | 8209 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8210 | int refclk = 100000; |
8211 | ||
b521973b VS |
8212 | /* In case of DSI, DPLL will not be used */ |
8213 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8214 | return; | |
8215 | ||
a580516d | 8216 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8217 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8218 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8219 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8220 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8221 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8222 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8223 | |
8224 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8225 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8226 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8227 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8228 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8229 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8230 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8231 | ||
dccbea3b | 8232 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8233 | } |
8234 | ||
0e8ffe1b | 8235 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8236 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8237 | { |
8238 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8239 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8240 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8241 | uint32_t tmp; |
1729050e | 8242 | bool ret; |
0e8ffe1b | 8243 | |
1729050e ID |
8244 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8245 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8246 | return false; |
8247 | ||
e143a21c | 8248 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8249 | pipe_config->shared_dpll = NULL; |
eccb140b | 8250 | |
1729050e ID |
8251 | ret = false; |
8252 | ||
0e8ffe1b DV |
8253 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8254 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8255 | goto out; |
0e8ffe1b | 8256 | |
666a4537 | 8257 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8258 | switch (tmp & PIPECONF_BPC_MASK) { |
8259 | case PIPECONF_6BPC: | |
8260 | pipe_config->pipe_bpp = 18; | |
8261 | break; | |
8262 | case PIPECONF_8BPC: | |
8263 | pipe_config->pipe_bpp = 24; | |
8264 | break; | |
8265 | case PIPECONF_10BPC: | |
8266 | pipe_config->pipe_bpp = 30; | |
8267 | break; | |
8268 | default: | |
8269 | break; | |
8270 | } | |
8271 | } | |
8272 | ||
666a4537 WB |
8273 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8274 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8275 | pipe_config->limited_color_range = true; |
8276 | ||
282740f7 VS |
8277 | if (INTEL_INFO(dev)->gen < 4) |
8278 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8279 | ||
1bd1bd80 | 8280 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8281 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8282 | |
2fa2fe9a DV |
8283 | i9xx_get_pfit_config(crtc, pipe_config); |
8284 | ||
6c49f241 | 8285 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8286 | /* No way to read it out on pipes B and C */ |
8287 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8288 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8289 | else | |
8290 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8291 | pipe_config->pixel_multiplier = |
8292 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8293 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8294 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8295 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8296 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8297 | pipe_config->pixel_multiplier = | |
8298 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8299 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8300 | } else { | |
8301 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8302 | * port and will be fixed up in the encoder->get_config | |
8303 | * function. */ | |
8304 | pipe_config->pixel_multiplier = 1; | |
8305 | } | |
8bcc2795 | 8306 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8307 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8308 | /* |
8309 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8310 | * on 830. Filter it out here so that we don't | |
8311 | * report errors due to that. | |
8312 | */ | |
8313 | if (IS_I830(dev)) | |
8314 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8315 | ||
8bcc2795 DV |
8316 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8317 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8318 | } else { |
8319 | /* Mask out read-only status bits. */ | |
8320 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8321 | DPLL_PORTC_READY_MASK | | |
8322 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8323 | } |
6c49f241 | 8324 | |
70b23a98 VS |
8325 | if (IS_CHERRYVIEW(dev)) |
8326 | chv_crtc_clock_get(crtc, pipe_config); | |
8327 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8328 | vlv_crtc_clock_get(crtc, pipe_config); |
8329 | else | |
8330 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8331 | |
0f64614d VS |
8332 | /* |
8333 | * Normally the dotclock is filled in by the encoder .get_config() | |
8334 | * but in case the pipe is enabled w/o any ports we need a sane | |
8335 | * default. | |
8336 | */ | |
8337 | pipe_config->base.adjusted_mode.crtc_clock = | |
8338 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8339 | ||
1729050e ID |
8340 | ret = true; |
8341 | ||
8342 | out: | |
8343 | intel_display_power_put(dev_priv, power_domain); | |
8344 | ||
8345 | return ret; | |
0e8ffe1b DV |
8346 | } |
8347 | ||
dde86e2d | 8348 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8349 | { |
fac5e23e | 8350 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8351 | struct intel_encoder *encoder; |
1c1a24d2 | 8352 | int i; |
74cfd7ac | 8353 | u32 val, final; |
13d83a67 | 8354 | bool has_lvds = false; |
199e5d79 | 8355 | bool has_cpu_edp = false; |
199e5d79 | 8356 | bool has_panel = false; |
99eb6a01 KP |
8357 | bool has_ck505 = false; |
8358 | bool can_ssc = false; | |
1c1a24d2 | 8359 | bool using_ssc_source = false; |
13d83a67 JB |
8360 | |
8361 | /* We need to take the global config into account */ | |
b2784e15 | 8362 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8363 | switch (encoder->type) { |
8364 | case INTEL_OUTPUT_LVDS: | |
8365 | has_panel = true; | |
8366 | has_lvds = true; | |
8367 | break; | |
8368 | case INTEL_OUTPUT_EDP: | |
8369 | has_panel = true; | |
2de6905f | 8370 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8371 | has_cpu_edp = true; |
8372 | break; | |
6847d71b PZ |
8373 | default: |
8374 | break; | |
13d83a67 JB |
8375 | } |
8376 | } | |
8377 | ||
99eb6a01 | 8378 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8379 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8380 | can_ssc = has_ck505; |
8381 | } else { | |
8382 | has_ck505 = false; | |
8383 | can_ssc = true; | |
8384 | } | |
8385 | ||
1c1a24d2 L |
8386 | /* Check if any DPLLs are using the SSC source */ |
8387 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8388 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8389 | ||
8390 | if (!(temp & DPLL_VCO_ENABLE)) | |
8391 | continue; | |
8392 | ||
8393 | if ((temp & PLL_REF_INPUT_MASK) == | |
8394 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8395 | using_ssc_source = true; | |
8396 | break; | |
8397 | } | |
8398 | } | |
8399 | ||
8400 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8401 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8402 | |
8403 | /* Ironlake: try to setup display ref clock before DPLL | |
8404 | * enabling. This is only under driver's control after | |
8405 | * PCH B stepping, previous chipset stepping should be | |
8406 | * ignoring this setting. | |
8407 | */ | |
74cfd7ac CW |
8408 | val = I915_READ(PCH_DREF_CONTROL); |
8409 | ||
8410 | /* As we must carefully and slowly disable/enable each source in turn, | |
8411 | * compute the final state we want first and check if we need to | |
8412 | * make any changes at all. | |
8413 | */ | |
8414 | final = val; | |
8415 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8416 | if (has_ck505) | |
8417 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8418 | else | |
8419 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8420 | ||
8c07eb68 | 8421 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8422 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8423 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8424 | |
8425 | if (has_panel) { | |
8426 | final |= DREF_SSC_SOURCE_ENABLE; | |
8427 | ||
8428 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8429 | final |= DREF_SSC1_ENABLE; | |
8430 | ||
8431 | if (has_cpu_edp) { | |
8432 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8433 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8434 | else | |
8435 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8436 | } else | |
8437 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8438 | } else if (using_ssc_source) { |
8439 | final |= DREF_SSC_SOURCE_ENABLE; | |
8440 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8441 | } |
8442 | ||
8443 | if (final == val) | |
8444 | return; | |
8445 | ||
13d83a67 | 8446 | /* Always enable nonspread source */ |
74cfd7ac | 8447 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8448 | |
99eb6a01 | 8449 | if (has_ck505) |
74cfd7ac | 8450 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8451 | else |
74cfd7ac | 8452 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8453 | |
199e5d79 | 8454 | if (has_panel) { |
74cfd7ac CW |
8455 | val &= ~DREF_SSC_SOURCE_MASK; |
8456 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8457 | |
199e5d79 | 8458 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8459 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8460 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8461 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8462 | } else |
74cfd7ac | 8463 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8464 | |
8465 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8466 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8467 | POSTING_READ(PCH_DREF_CONTROL); |
8468 | udelay(200); | |
8469 | ||
74cfd7ac | 8470 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8471 | |
8472 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8473 | if (has_cpu_edp) { |
99eb6a01 | 8474 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8475 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8476 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8477 | } else |
74cfd7ac | 8478 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8479 | } else |
74cfd7ac | 8480 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8481 | |
74cfd7ac | 8482 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8483 | POSTING_READ(PCH_DREF_CONTROL); |
8484 | udelay(200); | |
8485 | } else { | |
1c1a24d2 | 8486 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 8487 | |
74cfd7ac | 8488 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8489 | |
8490 | /* Turn off CPU output */ | |
74cfd7ac | 8491 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8492 | |
74cfd7ac | 8493 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8494 | POSTING_READ(PCH_DREF_CONTROL); |
8495 | udelay(200); | |
8496 | ||
1c1a24d2 L |
8497 | if (!using_ssc_source) { |
8498 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 8499 | |
1c1a24d2 L |
8500 | /* Turn off the SSC source */ |
8501 | val &= ~DREF_SSC_SOURCE_MASK; | |
8502 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 8503 | |
1c1a24d2 L |
8504 | /* Turn off SSC1 */ |
8505 | val &= ~DREF_SSC1_ENABLE; | |
8506 | ||
8507 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8508 | POSTING_READ(PCH_DREF_CONTROL); | |
8509 | udelay(200); | |
8510 | } | |
13d83a67 | 8511 | } |
74cfd7ac CW |
8512 | |
8513 | BUG_ON(val != final); | |
13d83a67 JB |
8514 | } |
8515 | ||
f31f2d55 | 8516 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8517 | { |
f31f2d55 | 8518 | uint32_t tmp; |
dde86e2d | 8519 | |
0ff066a9 PZ |
8520 | tmp = I915_READ(SOUTH_CHICKEN2); |
8521 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8522 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8523 | |
cf3598c2 ID |
8524 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
8525 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 8526 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 8527 | |
0ff066a9 PZ |
8528 | tmp = I915_READ(SOUTH_CHICKEN2); |
8529 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8530 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8531 | |
cf3598c2 ID |
8532 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
8533 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 8534 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
8535 | } |
8536 | ||
8537 | /* WaMPhyProgramming:hsw */ | |
8538 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8539 | { | |
8540 | uint32_t tmp; | |
dde86e2d PZ |
8541 | |
8542 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8543 | tmp &= ~(0xFF << 24); | |
8544 | tmp |= (0x12 << 24); | |
8545 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8546 | ||
dde86e2d PZ |
8547 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8548 | tmp |= (1 << 11); | |
8549 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8550 | ||
8551 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8552 | tmp |= (1 << 11); | |
8553 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8554 | ||
dde86e2d PZ |
8555 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8556 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8557 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8558 | ||
8559 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8560 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8561 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8562 | ||
0ff066a9 PZ |
8563 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8564 | tmp &= ~(7 << 13); | |
8565 | tmp |= (5 << 13); | |
8566 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8567 | |
0ff066a9 PZ |
8568 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8569 | tmp &= ~(7 << 13); | |
8570 | tmp |= (5 << 13); | |
8571 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8572 | |
8573 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8574 | tmp &= ~0xFF; | |
8575 | tmp |= 0x1C; | |
8576 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8577 | ||
8578 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8579 | tmp &= ~0xFF; | |
8580 | tmp |= 0x1C; | |
8581 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8582 | ||
8583 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8584 | tmp &= ~(0xFF << 16); | |
8585 | tmp |= (0x1C << 16); | |
8586 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8587 | ||
8588 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8589 | tmp &= ~(0xFF << 16); | |
8590 | tmp |= (0x1C << 16); | |
8591 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8592 | ||
0ff066a9 PZ |
8593 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8594 | tmp |= (1 << 27); | |
8595 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8596 | |
0ff066a9 PZ |
8597 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8598 | tmp |= (1 << 27); | |
8599 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8600 | |
0ff066a9 PZ |
8601 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8602 | tmp &= ~(0xF << 28); | |
8603 | tmp |= (4 << 28); | |
8604 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8605 | |
0ff066a9 PZ |
8606 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8607 | tmp &= ~(0xF << 28); | |
8608 | tmp |= (4 << 28); | |
8609 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8610 | } |
8611 | ||
2fa86a1f PZ |
8612 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8613 | * Programming" based on the parameters passed: | |
8614 | * - Sequence to enable CLKOUT_DP | |
8615 | * - Sequence to enable CLKOUT_DP without spread | |
8616 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8617 | */ | |
8618 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8619 | bool with_fdi) | |
f31f2d55 | 8620 | { |
fac5e23e | 8621 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
8622 | uint32_t reg, tmp; |
8623 | ||
8624 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8625 | with_spread = true; | |
c2699524 | 8626 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8627 | with_fdi = false; |
f31f2d55 | 8628 | |
a580516d | 8629 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8630 | |
8631 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8632 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8633 | tmp |= SBI_SSCCTL_PATHALT; | |
8634 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8635 | ||
8636 | udelay(24); | |
8637 | ||
2fa86a1f PZ |
8638 | if (with_spread) { |
8639 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8640 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8641 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8642 | |
2fa86a1f PZ |
8643 | if (with_fdi) { |
8644 | lpt_reset_fdi_mphy(dev_priv); | |
8645 | lpt_program_fdi_mphy(dev_priv); | |
8646 | } | |
8647 | } | |
dde86e2d | 8648 | |
c2699524 | 8649 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8650 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8651 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8652 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8653 | |
a580516d | 8654 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8655 | } |
8656 | ||
47701c3b PZ |
8657 | /* Sequence to disable CLKOUT_DP */ |
8658 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8659 | { | |
fac5e23e | 8660 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
8661 | uint32_t reg, tmp; |
8662 | ||
a580516d | 8663 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8664 | |
c2699524 | 8665 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8666 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8667 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8668 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8669 | ||
8670 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8671 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8672 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8673 | tmp |= SBI_SSCCTL_PATHALT; | |
8674 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8675 | udelay(32); | |
8676 | } | |
8677 | tmp |= SBI_SSCCTL_DISABLE; | |
8678 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8679 | } | |
8680 | ||
a580516d | 8681 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8682 | } |
8683 | ||
f7be2c21 VS |
8684 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8685 | ||
8686 | static const uint16_t sscdivintphase[] = { | |
8687 | [BEND_IDX( 50)] = 0x3B23, | |
8688 | [BEND_IDX( 45)] = 0x3B23, | |
8689 | [BEND_IDX( 40)] = 0x3C23, | |
8690 | [BEND_IDX( 35)] = 0x3C23, | |
8691 | [BEND_IDX( 30)] = 0x3D23, | |
8692 | [BEND_IDX( 25)] = 0x3D23, | |
8693 | [BEND_IDX( 20)] = 0x3E23, | |
8694 | [BEND_IDX( 15)] = 0x3E23, | |
8695 | [BEND_IDX( 10)] = 0x3F23, | |
8696 | [BEND_IDX( 5)] = 0x3F23, | |
8697 | [BEND_IDX( 0)] = 0x0025, | |
8698 | [BEND_IDX( -5)] = 0x0025, | |
8699 | [BEND_IDX(-10)] = 0x0125, | |
8700 | [BEND_IDX(-15)] = 0x0125, | |
8701 | [BEND_IDX(-20)] = 0x0225, | |
8702 | [BEND_IDX(-25)] = 0x0225, | |
8703 | [BEND_IDX(-30)] = 0x0325, | |
8704 | [BEND_IDX(-35)] = 0x0325, | |
8705 | [BEND_IDX(-40)] = 0x0425, | |
8706 | [BEND_IDX(-45)] = 0x0425, | |
8707 | [BEND_IDX(-50)] = 0x0525, | |
8708 | }; | |
8709 | ||
8710 | /* | |
8711 | * Bend CLKOUT_DP | |
8712 | * steps -50 to 50 inclusive, in steps of 5 | |
8713 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8714 | * change in clock period = -(steps / 10) * 5.787 ps | |
8715 | */ | |
8716 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8717 | { | |
8718 | uint32_t tmp; | |
8719 | int idx = BEND_IDX(steps); | |
8720 | ||
8721 | if (WARN_ON(steps % 5 != 0)) | |
8722 | return; | |
8723 | ||
8724 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8725 | return; | |
8726 | ||
8727 | mutex_lock(&dev_priv->sb_lock); | |
8728 | ||
8729 | if (steps % 10 != 0) | |
8730 | tmp = 0xAAAAAAAB; | |
8731 | else | |
8732 | tmp = 0x00000000; | |
8733 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8734 | ||
8735 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8736 | tmp &= 0xffff0000; | |
8737 | tmp |= sscdivintphase[idx]; | |
8738 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8739 | ||
8740 | mutex_unlock(&dev_priv->sb_lock); | |
8741 | } | |
8742 | ||
8743 | #undef BEND_IDX | |
8744 | ||
bf8fa3d3 PZ |
8745 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8746 | { | |
bf8fa3d3 PZ |
8747 | struct intel_encoder *encoder; |
8748 | bool has_vga = false; | |
8749 | ||
b2784e15 | 8750 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8751 | switch (encoder->type) { |
8752 | case INTEL_OUTPUT_ANALOG: | |
8753 | has_vga = true; | |
8754 | break; | |
6847d71b PZ |
8755 | default: |
8756 | break; | |
bf8fa3d3 PZ |
8757 | } |
8758 | } | |
8759 | ||
f7be2c21 VS |
8760 | if (has_vga) { |
8761 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8762 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8763 | } else { |
47701c3b | 8764 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8765 | } |
bf8fa3d3 PZ |
8766 | } |
8767 | ||
dde86e2d PZ |
8768 | /* |
8769 | * Initialize reference clocks when the driver loads | |
8770 | */ | |
8771 | void intel_init_pch_refclk(struct drm_device *dev) | |
8772 | { | |
8773 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8774 | ironlake_init_pch_refclk(dev); | |
8775 | else if (HAS_PCH_LPT(dev)) | |
8776 | lpt_init_pch_refclk(dev); | |
8777 | } | |
8778 | ||
6ff93609 | 8779 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8780 | { |
fac5e23e | 8781 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8782 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8783 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8784 | uint32_t val; |
8785 | ||
78114071 | 8786 | val = 0; |
c8203565 | 8787 | |
6e3c9717 | 8788 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8789 | case 18: |
dfd07d72 | 8790 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8791 | break; |
8792 | case 24: | |
dfd07d72 | 8793 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8794 | break; |
8795 | case 30: | |
dfd07d72 | 8796 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8797 | break; |
8798 | case 36: | |
dfd07d72 | 8799 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8800 | break; |
8801 | default: | |
cc769b62 PZ |
8802 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8803 | BUG(); | |
c8203565 PZ |
8804 | } |
8805 | ||
6e3c9717 | 8806 | if (intel_crtc->config->dither) |
c8203565 PZ |
8807 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8808 | ||
6e3c9717 | 8809 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8810 | val |= PIPECONF_INTERLACED_ILK; |
8811 | else | |
8812 | val |= PIPECONF_PROGRESSIVE; | |
8813 | ||
6e3c9717 | 8814 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8815 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8816 | |
c8203565 PZ |
8817 | I915_WRITE(PIPECONF(pipe), val); |
8818 | POSTING_READ(PIPECONF(pipe)); | |
8819 | } | |
8820 | ||
6ff93609 | 8821 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8822 | { |
fac5e23e | 8823 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8825 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8826 | u32 val = 0; |
ee2b0b38 | 8827 | |
391bf048 | 8828 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8829 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8830 | ||
6e3c9717 | 8831 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8832 | val |= PIPECONF_INTERLACED_ILK; |
8833 | else | |
8834 | val |= PIPECONF_PROGRESSIVE; | |
8835 | ||
702e7a56 PZ |
8836 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8837 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8838 | } |
8839 | ||
391bf048 JN |
8840 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8841 | { | |
fac5e23e | 8842 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8843 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8844 | |
391bf048 JN |
8845 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8846 | u32 val = 0; | |
756f85cf | 8847 | |
6e3c9717 | 8848 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8849 | case 18: |
8850 | val |= PIPEMISC_DITHER_6_BPC; | |
8851 | break; | |
8852 | case 24: | |
8853 | val |= PIPEMISC_DITHER_8_BPC; | |
8854 | break; | |
8855 | case 30: | |
8856 | val |= PIPEMISC_DITHER_10_BPC; | |
8857 | break; | |
8858 | case 36: | |
8859 | val |= PIPEMISC_DITHER_12_BPC; | |
8860 | break; | |
8861 | default: | |
8862 | /* Case prevented by pipe_config_set_bpp. */ | |
8863 | BUG(); | |
8864 | } | |
8865 | ||
6e3c9717 | 8866 | if (intel_crtc->config->dither) |
756f85cf PZ |
8867 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8868 | ||
391bf048 | 8869 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8870 | } |
ee2b0b38 PZ |
8871 | } |
8872 | ||
d4b1931c PZ |
8873 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8874 | { | |
8875 | /* | |
8876 | * Account for spread spectrum to avoid | |
8877 | * oversubscribing the link. Max center spread | |
8878 | * is 2.5%; use 5% for safety's sake. | |
8879 | */ | |
8880 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8881 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8882 | } |
8883 | ||
7429e9d4 | 8884 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8885 | { |
7429e9d4 | 8886 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8887 | } |
8888 | ||
b75ca6f6 ACO |
8889 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8890 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8891 | struct dpll *reduced_clock) |
79e53945 | 8892 | { |
de13a2e3 | 8893 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8894 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8895 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8896 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8897 | int factor; |
79e53945 | 8898 | |
c1858123 | 8899 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8900 | factor = 21; |
3d6e9ee0 | 8901 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8902 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8903 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8904 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8905 | factor = 25; |
190f68c5 | 8906 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8907 | factor = 20; |
c1858123 | 8908 | |
b75ca6f6 ACO |
8909 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8910 | ||
190f68c5 | 8911 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8912 | fp |= FP_CB_TUNE; |
8913 | ||
8914 | if (reduced_clock) { | |
8915 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8916 | |
b75ca6f6 ACO |
8917 | if (reduced_clock->m < factor * reduced_clock->n) |
8918 | fp2 |= FP_CB_TUNE; | |
8919 | } else { | |
8920 | fp2 = fp; | |
8921 | } | |
9a7c7890 | 8922 | |
5eddb70b | 8923 | dpll = 0; |
2c07245f | 8924 | |
3d6e9ee0 | 8925 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8926 | dpll |= DPLLB_MODE_LVDS; |
8927 | else | |
8928 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8929 | |
190f68c5 | 8930 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8931 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8932 | |
3d6e9ee0 VS |
8933 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8934 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8935 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8936 | |
37a5650b | 8937 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8938 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8939 | |
a07d6787 | 8940 | /* compute bitmask from p1 value */ |
190f68c5 | 8941 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8942 | /* also FPA1 */ |
190f68c5 | 8943 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8944 | |
190f68c5 | 8945 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8946 | case 5: |
8947 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8948 | break; | |
8949 | case 7: | |
8950 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8951 | break; | |
8952 | case 10: | |
8953 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8954 | break; | |
8955 | case 14: | |
8956 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8957 | break; | |
79e53945 JB |
8958 | } |
8959 | ||
3d6e9ee0 VS |
8960 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8961 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8962 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8963 | else |
8964 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8965 | ||
b75ca6f6 ACO |
8966 | dpll |= DPLL_VCO_ENABLE; |
8967 | ||
8968 | crtc_state->dpll_hw_state.dpll = dpll; | |
8969 | crtc_state->dpll_hw_state.fp0 = fp; | |
8970 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8971 | } |
8972 | ||
190f68c5 ACO |
8973 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8974 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8975 | { |
997c030c | 8976 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8977 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 8978 | struct dpll reduced_clock; |
7ed9f894 | 8979 | bool has_reduced_clock = false; |
e2b78267 | 8980 | struct intel_shared_dpll *pll; |
1b6f4958 | 8981 | const struct intel_limit *limit; |
997c030c | 8982 | int refclk = 120000; |
de13a2e3 | 8983 | |
dd3cd74a ACO |
8984 | memset(&crtc_state->dpll_hw_state, 0, |
8985 | sizeof(crtc_state->dpll_hw_state)); | |
8986 | ||
ded220e2 ACO |
8987 | crtc->lowfreq_avail = false; |
8988 | ||
8989 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8990 | if (!crtc_state->has_pch_encoder) | |
8991 | return 0; | |
79e53945 | 8992 | |
2d84d2b3 | 8993 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8994 | if (intel_panel_use_ssc(dev_priv)) { |
8995 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8996 | dev_priv->vbt.lvds_ssc_freq); | |
8997 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8998 | } | |
8999 | ||
9000 | if (intel_is_dual_link_lvds(dev)) { | |
9001 | if (refclk == 100000) | |
9002 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9003 | else | |
9004 | limit = &intel_limits_ironlake_dual_lvds; | |
9005 | } else { | |
9006 | if (refclk == 100000) | |
9007 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9008 | else | |
9009 | limit = &intel_limits_ironlake_single_lvds; | |
9010 | } | |
9011 | } else { | |
9012 | limit = &intel_limits_ironlake_dac; | |
9013 | } | |
9014 | ||
364ee29d | 9015 | if (!crtc_state->clock_set && |
997c030c ACO |
9016 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9017 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9018 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9019 | return -EINVAL; | |
f47709a9 | 9020 | } |
79e53945 | 9021 | |
b75ca6f6 ACO |
9022 | ironlake_compute_dpll(crtc, crtc_state, |
9023 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9024 | |
ded220e2 ACO |
9025 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9026 | if (pll == NULL) { | |
9027 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9028 | pipe_name(crtc->pipe)); | |
9029 | return -EINVAL; | |
3fb37703 | 9030 | } |
79e53945 | 9031 | |
2d84d2b3 | 9032 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9033 | has_reduced_clock) |
c7653199 | 9034 | crtc->lowfreq_avail = true; |
e2b78267 | 9035 | |
c8f7a0db | 9036 | return 0; |
79e53945 JB |
9037 | } |
9038 | ||
eb14cb74 VS |
9039 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9040 | struct intel_link_m_n *m_n) | |
9041 | { | |
9042 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9043 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9044 | enum pipe pipe = crtc->pipe; |
9045 | ||
9046 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9047 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9048 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9049 | & ~TU_SIZE_MASK; | |
9050 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9051 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9052 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9053 | } | |
9054 | ||
9055 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9056 | enum transcoder transcoder, | |
b95af8be VK |
9057 | struct intel_link_m_n *m_n, |
9058 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9059 | { |
9060 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9061 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9062 | enum pipe pipe = crtc->pipe; |
72419203 | 9063 | |
eb14cb74 VS |
9064 | if (INTEL_INFO(dev)->gen >= 5) { |
9065 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9066 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9067 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9068 | & ~TU_SIZE_MASK; | |
9069 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9070 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9071 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9072 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9073 | * gen < 8) and if DRRS is supported (to make sure the | |
9074 | * registers are not unnecessarily read). | |
9075 | */ | |
9076 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9077 | crtc->config->has_drrs) { |
b95af8be VK |
9078 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9079 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9080 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9081 | & ~TU_SIZE_MASK; | |
9082 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9083 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9084 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9085 | } | |
eb14cb74 VS |
9086 | } else { |
9087 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9088 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9089 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9090 | & ~TU_SIZE_MASK; | |
9091 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9092 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9093 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9094 | } | |
9095 | } | |
9096 | ||
9097 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9098 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9099 | { |
681a8504 | 9100 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9101 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9102 | else | |
9103 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9104 | &pipe_config->dp_m_n, |
9105 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9106 | } |
72419203 | 9107 | |
eb14cb74 | 9108 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9109 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9110 | { |
9111 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9112 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9113 | } |
9114 | ||
bd2e244f | 9115 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9116 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9117 | { |
9118 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9119 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9120 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9121 | uint32_t ps_ctrl = 0; | |
9122 | int id = -1; | |
9123 | int i; | |
bd2e244f | 9124 | |
a1b2278e CK |
9125 | /* find scaler attached to this pipe */ |
9126 | for (i = 0; i < crtc->num_scalers; i++) { | |
9127 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9128 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9129 | id = i; | |
9130 | pipe_config->pch_pfit.enabled = true; | |
9131 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9132 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9133 | break; | |
9134 | } | |
9135 | } | |
bd2e244f | 9136 | |
a1b2278e CK |
9137 | scaler_state->scaler_id = id; |
9138 | if (id >= 0) { | |
9139 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9140 | } else { | |
9141 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9142 | } |
9143 | } | |
9144 | ||
5724dbd1 DL |
9145 | static void |
9146 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9147 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9148 | { |
9149 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9150 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9151 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9152 | int pipe = crtc->pipe; |
9153 | int fourcc, pixel_format; | |
6761dd31 | 9154 | unsigned int aligned_height; |
bc8d7dff | 9155 | struct drm_framebuffer *fb; |
1b842c89 | 9156 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9157 | |
d9806c9f | 9158 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9159 | if (!intel_fb) { |
bc8d7dff DL |
9160 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9161 | return; | |
9162 | } | |
9163 | ||
1b842c89 DL |
9164 | fb = &intel_fb->base; |
9165 | ||
bc8d7dff | 9166 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9167 | if (!(val & PLANE_CTL_ENABLE)) |
9168 | goto error; | |
9169 | ||
bc8d7dff DL |
9170 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9171 | fourcc = skl_format_to_fourcc(pixel_format, | |
9172 | val & PLANE_CTL_ORDER_RGBX, | |
9173 | val & PLANE_CTL_ALPHA_MASK); | |
9174 | fb->pixel_format = fourcc; | |
9175 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9176 | ||
40f46283 DL |
9177 | tiling = val & PLANE_CTL_TILED_MASK; |
9178 | switch (tiling) { | |
9179 | case PLANE_CTL_TILED_LINEAR: | |
9180 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9181 | break; | |
9182 | case PLANE_CTL_TILED_X: | |
9183 | plane_config->tiling = I915_TILING_X; | |
9184 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9185 | break; | |
9186 | case PLANE_CTL_TILED_Y: | |
9187 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9188 | break; | |
9189 | case PLANE_CTL_TILED_YF: | |
9190 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9191 | break; | |
9192 | default: | |
9193 | MISSING_CASE(tiling); | |
9194 | goto error; | |
9195 | } | |
9196 | ||
bc8d7dff DL |
9197 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9198 | plane_config->base = base; | |
9199 | ||
9200 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9201 | ||
9202 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9203 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9204 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9205 | ||
9206 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9207 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9208 | fb->pixel_format); |
bc8d7dff DL |
9209 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9210 | ||
9211 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9212 | fb->pixel_format, |
9213 | fb->modifier[0]); | |
bc8d7dff | 9214 | |
f37b5c2b | 9215 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9216 | |
9217 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9218 | pipe_name(pipe), fb->width, fb->height, | |
9219 | fb->bits_per_pixel, base, fb->pitches[0], | |
9220 | plane_config->size); | |
9221 | ||
2d14030b | 9222 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9223 | return; |
9224 | ||
9225 | error: | |
9226 | kfree(fb); | |
9227 | } | |
9228 | ||
2fa2fe9a | 9229 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9230 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9231 | { |
9232 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9233 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9234 | uint32_t tmp; |
9235 | ||
9236 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9237 | ||
9238 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9239 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9240 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9241 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9242 | |
9243 | /* We currently do not free assignements of panel fitters on | |
9244 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9245 | * differentiates them) so just WARN about this case for now. */ | |
9246 | if (IS_GEN7(dev)) { | |
9247 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9248 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9249 | } | |
2fa2fe9a | 9250 | } |
79e53945 JB |
9251 | } |
9252 | ||
5724dbd1 DL |
9253 | static void |
9254 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9255 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9256 | { |
9257 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9258 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9259 | u32 val, base, offset; |
aeee5a49 | 9260 | int pipe = crtc->pipe; |
4c6baa59 | 9261 | int fourcc, pixel_format; |
6761dd31 | 9262 | unsigned int aligned_height; |
b113d5ee | 9263 | struct drm_framebuffer *fb; |
1b842c89 | 9264 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9265 | |
42a7b088 DL |
9266 | val = I915_READ(DSPCNTR(pipe)); |
9267 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9268 | return; | |
9269 | ||
d9806c9f | 9270 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9271 | if (!intel_fb) { |
4c6baa59 JB |
9272 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9273 | return; | |
9274 | } | |
9275 | ||
1b842c89 DL |
9276 | fb = &intel_fb->base; |
9277 | ||
18c5247e DV |
9278 | if (INTEL_INFO(dev)->gen >= 4) { |
9279 | if (val & DISPPLANE_TILED) { | |
49af449b | 9280 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9281 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9282 | } | |
9283 | } | |
4c6baa59 JB |
9284 | |
9285 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9286 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9287 | fb->pixel_format = fourcc; |
9288 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9289 | |
aeee5a49 | 9290 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9291 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9292 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9293 | } else { |
49af449b | 9294 | if (plane_config->tiling) |
aeee5a49 | 9295 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9296 | else |
aeee5a49 | 9297 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9298 | } |
9299 | plane_config->base = base; | |
9300 | ||
9301 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9302 | fb->width = ((val >> 16) & 0xfff) + 1; |
9303 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9304 | |
9305 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9306 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9307 | |
b113d5ee | 9308 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9309 | fb->pixel_format, |
9310 | fb->modifier[0]); | |
4c6baa59 | 9311 | |
f37b5c2b | 9312 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9313 | |
2844a921 DL |
9314 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9315 | pipe_name(pipe), fb->width, fb->height, | |
9316 | fb->bits_per_pixel, base, fb->pitches[0], | |
9317 | plane_config->size); | |
b113d5ee | 9318 | |
2d14030b | 9319 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9320 | } |
9321 | ||
0e8ffe1b | 9322 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9323 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9324 | { |
9325 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9326 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9327 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9328 | uint32_t tmp; |
1729050e | 9329 | bool ret; |
0e8ffe1b | 9330 | |
1729050e ID |
9331 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9332 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9333 | return false; |
9334 | ||
e143a21c | 9335 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9336 | pipe_config->shared_dpll = NULL; |
eccb140b | 9337 | |
1729050e | 9338 | ret = false; |
0e8ffe1b DV |
9339 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9340 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9341 | goto out; |
0e8ffe1b | 9342 | |
42571aef VS |
9343 | switch (tmp & PIPECONF_BPC_MASK) { |
9344 | case PIPECONF_6BPC: | |
9345 | pipe_config->pipe_bpp = 18; | |
9346 | break; | |
9347 | case PIPECONF_8BPC: | |
9348 | pipe_config->pipe_bpp = 24; | |
9349 | break; | |
9350 | case PIPECONF_10BPC: | |
9351 | pipe_config->pipe_bpp = 30; | |
9352 | break; | |
9353 | case PIPECONF_12BPC: | |
9354 | pipe_config->pipe_bpp = 36; | |
9355 | break; | |
9356 | default: | |
9357 | break; | |
9358 | } | |
9359 | ||
b5a9fa09 DV |
9360 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9361 | pipe_config->limited_color_range = true; | |
9362 | ||
ab9412ba | 9363 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9364 | struct intel_shared_dpll *pll; |
8106ddbd | 9365 | enum intel_dpll_id pll_id; |
66e985c0 | 9366 | |
88adfff1 DV |
9367 | pipe_config->has_pch_encoder = true; |
9368 | ||
627eb5a3 DV |
9369 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9370 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9371 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9372 | |
9373 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9374 | |
2d1fe073 | 9375 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9376 | /* |
9377 | * The pipe->pch transcoder and pch transcoder->pll | |
9378 | * mapping is fixed. | |
9379 | */ | |
8106ddbd | 9380 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9381 | } else { |
9382 | tmp = I915_READ(PCH_DPLL_SEL); | |
9383 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9384 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9385 | else |
8106ddbd | 9386 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9387 | } |
66e985c0 | 9388 | |
8106ddbd ACO |
9389 | pipe_config->shared_dpll = |
9390 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9391 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9392 | |
2edd6443 ACO |
9393 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9394 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9395 | |
9396 | tmp = pipe_config->dpll_hw_state.dpll; | |
9397 | pipe_config->pixel_multiplier = | |
9398 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9399 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9400 | |
9401 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9402 | } else { |
9403 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9404 | } |
9405 | ||
1bd1bd80 | 9406 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9407 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9408 | |
2fa2fe9a DV |
9409 | ironlake_get_pfit_config(crtc, pipe_config); |
9410 | ||
1729050e ID |
9411 | ret = true; |
9412 | ||
9413 | out: | |
9414 | intel_display_power_put(dev_priv, power_domain); | |
9415 | ||
9416 | return ret; | |
0e8ffe1b DV |
9417 | } |
9418 | ||
be256dc7 PZ |
9419 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9420 | { | |
91c8a326 | 9421 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 9422 | struct intel_crtc *crtc; |
be256dc7 | 9423 | |
d3fcc808 | 9424 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9425 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9426 | pipe_name(crtc->pipe)); |
9427 | ||
e2c719b7 RC |
9428 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9429 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9430 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9431 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9432 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9433 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9434 | "CPU PWM1 enabled\n"); |
c5107b87 | 9435 | if (IS_HASWELL(dev)) |
e2c719b7 | 9436 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9437 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9438 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9439 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9440 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9441 | "Utility pin enabled\n"); |
e2c719b7 | 9442 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9443 | |
9926ada1 PZ |
9444 | /* |
9445 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9446 | * interrupts remain enabled. We used to check for that, but since it's | |
9447 | * gen-specific and since we only disable LCPLL after we fully disable | |
9448 | * the interrupts, the check below should be enough. | |
9449 | */ | |
e2c719b7 | 9450 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9451 | } |
9452 | ||
9ccd5aeb PZ |
9453 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9454 | { | |
91c8a326 | 9455 | struct drm_device *dev = &dev_priv->drm; |
9ccd5aeb PZ |
9456 | |
9457 | if (IS_HASWELL(dev)) | |
9458 | return I915_READ(D_COMP_HSW); | |
9459 | else | |
9460 | return I915_READ(D_COMP_BDW); | |
9461 | } | |
9462 | ||
3c4c9b81 PZ |
9463 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9464 | { | |
91c8a326 | 9465 | struct drm_device *dev = &dev_priv->drm; |
3c4c9b81 PZ |
9466 | |
9467 | if (IS_HASWELL(dev)) { | |
9468 | mutex_lock(&dev_priv->rps.hw_lock); | |
9469 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9470 | val)) | |
f475dadf | 9471 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9472 | mutex_unlock(&dev_priv->rps.hw_lock); |
9473 | } else { | |
9ccd5aeb PZ |
9474 | I915_WRITE(D_COMP_BDW, val); |
9475 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9476 | } |
be256dc7 PZ |
9477 | } |
9478 | ||
9479 | /* | |
9480 | * This function implements pieces of two sequences from BSpec: | |
9481 | * - Sequence for display software to disable LCPLL | |
9482 | * - Sequence for display software to allow package C8+ | |
9483 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9484 | * register. Callers should take care of disabling all the display engine | |
9485 | * functions, doing the mode unset, fixing interrupts, etc. | |
9486 | */ | |
6ff58d53 PZ |
9487 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9488 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9489 | { |
9490 | uint32_t val; | |
9491 | ||
9492 | assert_can_disable_lcpll(dev_priv); | |
9493 | ||
9494 | val = I915_READ(LCPLL_CTL); | |
9495 | ||
9496 | if (switch_to_fclk) { | |
9497 | val |= LCPLL_CD_SOURCE_FCLK; | |
9498 | I915_WRITE(LCPLL_CTL, val); | |
9499 | ||
f53dd63f ID |
9500 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9501 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
9502 | DRM_ERROR("Switching to FCLK failed\n"); |
9503 | ||
9504 | val = I915_READ(LCPLL_CTL); | |
9505 | } | |
9506 | ||
9507 | val |= LCPLL_PLL_DISABLE; | |
9508 | I915_WRITE(LCPLL_CTL, val); | |
9509 | POSTING_READ(LCPLL_CTL); | |
9510 | ||
24d8441d | 9511 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
9512 | DRM_ERROR("LCPLL still locked\n"); |
9513 | ||
9ccd5aeb | 9514 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9515 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9516 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9517 | ndelay(100); |
9518 | ||
9ccd5aeb PZ |
9519 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9520 | 1)) | |
be256dc7 PZ |
9521 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9522 | ||
9523 | if (allow_power_down) { | |
9524 | val = I915_READ(LCPLL_CTL); | |
9525 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9526 | I915_WRITE(LCPLL_CTL, val); | |
9527 | POSTING_READ(LCPLL_CTL); | |
9528 | } | |
9529 | } | |
9530 | ||
9531 | /* | |
9532 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9533 | * source. | |
9534 | */ | |
6ff58d53 | 9535 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9536 | { |
9537 | uint32_t val; | |
9538 | ||
9539 | val = I915_READ(LCPLL_CTL); | |
9540 | ||
9541 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9542 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9543 | return; | |
9544 | ||
a8a8bd54 PZ |
9545 | /* |
9546 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9547 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9548 | */ |
59bad947 | 9549 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9550 | |
be256dc7 PZ |
9551 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9552 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9553 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9554 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9555 | } |
9556 | ||
9ccd5aeb | 9557 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9558 | val |= D_COMP_COMP_FORCE; |
9559 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9560 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9561 | |
9562 | val = I915_READ(LCPLL_CTL); | |
9563 | val &= ~LCPLL_PLL_DISABLE; | |
9564 | I915_WRITE(LCPLL_CTL, val); | |
9565 | ||
93220c08 CW |
9566 | if (intel_wait_for_register(dev_priv, |
9567 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
9568 | 5)) | |
be256dc7 PZ |
9569 | DRM_ERROR("LCPLL not locked yet\n"); |
9570 | ||
9571 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9572 | val = I915_READ(LCPLL_CTL); | |
9573 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9574 | I915_WRITE(LCPLL_CTL, val); | |
9575 | ||
f53dd63f ID |
9576 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9577 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
9578 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9579 | } | |
215733fa | 9580 | |
59bad947 | 9581 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
91c8a326 | 9582 | intel_update_cdclk(&dev_priv->drm); |
be256dc7 PZ |
9583 | } |
9584 | ||
765dab67 PZ |
9585 | /* |
9586 | * Package states C8 and deeper are really deep PC states that can only be | |
9587 | * reached when all the devices on the system allow it, so even if the graphics | |
9588 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9589 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9590 | * | |
9591 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9592 | * well is disabled and most interrupts are disabled, and these are also | |
9593 | * requirements for runtime PM. When these conditions are met, we manually do | |
9594 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9595 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9596 | * hang the machine. | |
9597 | * | |
9598 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9599 | * the state of some registers, so when we come back from PC8+ we need to | |
9600 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9601 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9602 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9603 | * because of the runtime PM support). | |
9604 | * | |
9605 | * For more, read "Display Sequences for Package C8" on the hardware | |
9606 | * documentation. | |
9607 | */ | |
a14cb6fc | 9608 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9609 | { |
91c8a326 | 9610 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9611 | uint32_t val; |
9612 | ||
c67a470b PZ |
9613 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9614 | ||
c2699524 | 9615 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9616 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9617 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9618 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9619 | } | |
9620 | ||
9621 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9622 | hsw_disable_lcpll(dev_priv, true, true); |
9623 | } | |
9624 | ||
a14cb6fc | 9625 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9626 | { |
91c8a326 | 9627 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9628 | uint32_t val; |
9629 | ||
c67a470b PZ |
9630 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9631 | ||
9632 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9633 | lpt_init_pch_refclk(dev); |
9634 | ||
c2699524 | 9635 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9636 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9637 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9638 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9639 | } | |
c67a470b PZ |
9640 | } |
9641 | ||
324513c0 | 9642 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9643 | { |
a821fc46 | 9644 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9645 | struct intel_atomic_state *old_intel_state = |
9646 | to_intel_atomic_state(old_state); | |
9647 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9648 | |
324513c0 | 9649 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9650 | } |
9651 | ||
b432e5cf | 9652 | /* compute the max rate for new configuration */ |
27c329ed | 9653 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9654 | { |
565602d7 | 9655 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 9656 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
9657 | struct drm_crtc *crtc; |
9658 | struct drm_crtc_state *cstate; | |
27c329ed | 9659 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9660 | unsigned max_pixel_rate = 0, i; |
9661 | enum pipe pipe; | |
b432e5cf | 9662 | |
565602d7 ML |
9663 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9664 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9665 | |
565602d7 ML |
9666 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9667 | int pixel_rate; | |
27c329ed | 9668 | |
565602d7 ML |
9669 | crtc_state = to_intel_crtc_state(cstate); |
9670 | if (!crtc_state->base.enable) { | |
9671 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9672 | continue; |
565602d7 | 9673 | } |
b432e5cf | 9674 | |
27c329ed | 9675 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9676 | |
9677 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9678 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9679 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9680 | ||
565602d7 | 9681 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9682 | } |
9683 | ||
565602d7 ML |
9684 | for_each_pipe(dev_priv, pipe) |
9685 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9686 | ||
b432e5cf VS |
9687 | return max_pixel_rate; |
9688 | } | |
9689 | ||
9690 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9691 | { | |
fac5e23e | 9692 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
9693 | uint32_t val, data; |
9694 | int ret; | |
9695 | ||
9696 | if (WARN((I915_READ(LCPLL_CTL) & | |
9697 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9698 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9699 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9700 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9701 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9702 | return; | |
9703 | ||
9704 | mutex_lock(&dev_priv->rps.hw_lock); | |
9705 | ret = sandybridge_pcode_write(dev_priv, | |
9706 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9707 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9708 | if (ret) { | |
9709 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9710 | return; | |
9711 | } | |
9712 | ||
9713 | val = I915_READ(LCPLL_CTL); | |
9714 | val |= LCPLL_CD_SOURCE_FCLK; | |
9715 | I915_WRITE(LCPLL_CTL, val); | |
9716 | ||
5ba00178 TU |
9717 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9718 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9719 | DRM_ERROR("Switching to FCLK failed\n"); |
9720 | ||
9721 | val = I915_READ(LCPLL_CTL); | |
9722 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9723 | ||
9724 | switch (cdclk) { | |
9725 | case 450000: | |
9726 | val |= LCPLL_CLK_FREQ_450; | |
9727 | data = 0; | |
9728 | break; | |
9729 | case 540000: | |
9730 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9731 | data = 1; | |
9732 | break; | |
9733 | case 337500: | |
9734 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9735 | data = 2; | |
9736 | break; | |
9737 | case 675000: | |
9738 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9739 | data = 3; | |
9740 | break; | |
9741 | default: | |
9742 | WARN(1, "invalid cdclk frequency\n"); | |
9743 | return; | |
9744 | } | |
9745 | ||
9746 | I915_WRITE(LCPLL_CTL, val); | |
9747 | ||
9748 | val = I915_READ(LCPLL_CTL); | |
9749 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9750 | I915_WRITE(LCPLL_CTL, val); | |
9751 | ||
5ba00178 TU |
9752 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9753 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9754 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9755 | ||
9756 | mutex_lock(&dev_priv->rps.hw_lock); | |
9757 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9758 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9759 | ||
7f1052a8 VS |
9760 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9761 | ||
b432e5cf VS |
9762 | intel_update_cdclk(dev); |
9763 | ||
9764 | WARN(cdclk != dev_priv->cdclk_freq, | |
9765 | "cdclk requested %d kHz but got %d kHz\n", | |
9766 | cdclk, dev_priv->cdclk_freq); | |
9767 | } | |
9768 | ||
587c7914 VS |
9769 | static int broadwell_calc_cdclk(int max_pixclk) |
9770 | { | |
9771 | if (max_pixclk > 540000) | |
9772 | return 675000; | |
9773 | else if (max_pixclk > 450000) | |
9774 | return 540000; | |
9775 | else if (max_pixclk > 337500) | |
9776 | return 450000; | |
9777 | else | |
9778 | return 337500; | |
9779 | } | |
9780 | ||
27c329ed | 9781 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9782 | { |
27c329ed | 9783 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9784 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9785 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9786 | int cdclk; |
9787 | ||
9788 | /* | |
9789 | * FIXME should also account for plane ratio | |
9790 | * once 64bpp pixel formats are supported. | |
9791 | */ | |
587c7914 | 9792 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9793 | |
b432e5cf | 9794 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9795 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9796 | cdclk, dev_priv->max_cdclk_freq); | |
9797 | return -EINVAL; | |
b432e5cf VS |
9798 | } |
9799 | ||
1a617b77 ML |
9800 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9801 | if (!intel_state->active_crtcs) | |
587c7914 | 9802 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
9803 | |
9804 | return 0; | |
9805 | } | |
9806 | ||
27c329ed | 9807 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9808 | { |
27c329ed | 9809 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9810 | struct intel_atomic_state *old_intel_state = |
9811 | to_intel_atomic_state(old_state); | |
9812 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9813 | |
27c329ed | 9814 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9815 | } |
9816 | ||
c89e39f3 CT |
9817 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
9818 | { | |
9819 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
9820 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9821 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 9822 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
9823 | int cdclk; |
9824 | ||
9825 | /* | |
9826 | * FIXME should also account for plane ratio | |
9827 | * once 64bpp pixel formats are supported. | |
9828 | */ | |
a8ca4934 | 9829 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
9830 | |
9831 | /* | |
9832 | * FIXME move the cdclk caclulation to | |
9833 | * compute_config() so we can fail gracegully. | |
9834 | */ | |
9835 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9836 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9837 | cdclk, dev_priv->max_cdclk_freq); | |
9838 | cdclk = dev_priv->max_cdclk_freq; | |
9839 | } | |
9840 | ||
9841 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
9842 | if (!intel_state->active_crtcs) | |
a8ca4934 | 9843 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
9844 | |
9845 | return 0; | |
9846 | } | |
9847 | ||
9848 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
9849 | { | |
1cd593e0 VS |
9850 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
9851 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
9852 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
9853 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 9854 | |
1cd593e0 | 9855 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
9856 | } |
9857 | ||
190f68c5 ACO |
9858 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9859 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9860 | { |
af3997b5 MK |
9861 | struct intel_encoder *intel_encoder = |
9862 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9863 | ||
9864 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9865 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9866 | return -EINVAL; | |
9867 | } | |
716c2e55 | 9868 | |
c7653199 | 9869 | crtc->lowfreq_avail = false; |
644cef34 | 9870 | |
c8f7a0db | 9871 | return 0; |
79e53945 JB |
9872 | } |
9873 | ||
3760b59c S |
9874 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9875 | enum port port, | |
9876 | struct intel_crtc_state *pipe_config) | |
9877 | { | |
8106ddbd ACO |
9878 | enum intel_dpll_id id; |
9879 | ||
3760b59c S |
9880 | switch (port) { |
9881 | case PORT_A: | |
9882 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9883 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9884 | break; |
9885 | case PORT_B: | |
9886 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9887 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9888 | break; |
9889 | case PORT_C: | |
9890 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9891 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9892 | break; |
9893 | default: | |
9894 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9895 | return; |
3760b59c | 9896 | } |
8106ddbd ACO |
9897 | |
9898 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9899 | } |
9900 | ||
96b7dfb7 S |
9901 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9902 | enum port port, | |
5cec258b | 9903 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9904 | { |
8106ddbd | 9905 | enum intel_dpll_id id; |
a3c988ea | 9906 | u32 temp; |
96b7dfb7 S |
9907 | |
9908 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9909 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9910 | ||
9911 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9912 | case SKL_DPLL0: |
a3c988ea ACO |
9913 | id = DPLL_ID_SKL_DPLL0; |
9914 | break; | |
96b7dfb7 | 9915 | case SKL_DPLL1: |
8106ddbd | 9916 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9917 | break; |
9918 | case SKL_DPLL2: | |
8106ddbd | 9919 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9920 | break; |
9921 | case SKL_DPLL3: | |
8106ddbd | 9922 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9923 | break; |
8106ddbd ACO |
9924 | default: |
9925 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9926 | return; | |
96b7dfb7 | 9927 | } |
8106ddbd ACO |
9928 | |
9929 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9930 | } |
9931 | ||
7d2c8175 DL |
9932 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9933 | enum port port, | |
5cec258b | 9934 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9935 | { |
8106ddbd ACO |
9936 | enum intel_dpll_id id; |
9937 | ||
7d2c8175 DL |
9938 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9939 | ||
9940 | switch (pipe_config->ddi_pll_sel) { | |
9941 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9942 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9943 | break; |
9944 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9945 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9946 | break; |
00490c22 | 9947 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9948 | id = DPLL_ID_SPLL; |
79bd23da | 9949 | break; |
9d16da65 ACO |
9950 | case PORT_CLK_SEL_LCPLL_810: |
9951 | id = DPLL_ID_LCPLL_810; | |
9952 | break; | |
9953 | case PORT_CLK_SEL_LCPLL_1350: | |
9954 | id = DPLL_ID_LCPLL_1350; | |
9955 | break; | |
9956 | case PORT_CLK_SEL_LCPLL_2700: | |
9957 | id = DPLL_ID_LCPLL_2700; | |
9958 | break; | |
8106ddbd ACO |
9959 | default: |
9960 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9961 | /* fall through */ | |
9962 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9963 | return; |
7d2c8175 | 9964 | } |
8106ddbd ACO |
9965 | |
9966 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9967 | } |
9968 | ||
cf30429e JN |
9969 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9970 | struct intel_crtc_state *pipe_config, | |
9971 | unsigned long *power_domain_mask) | |
9972 | { | |
9973 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9974 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
9975 | enum intel_display_power_domain power_domain; |
9976 | u32 tmp; | |
9977 | ||
d9a7bc67 ID |
9978 | /* |
9979 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9980 | * transcoder handled below. | |
9981 | */ | |
cf30429e JN |
9982 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9983 | ||
9984 | /* | |
9985 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9986 | * consistency and less surprising code; it's in always on power). | |
9987 | */ | |
9988 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9989 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9990 | enum pipe trans_edp_pipe; | |
9991 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9992 | default: | |
9993 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9994 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9995 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9996 | trans_edp_pipe = PIPE_A; | |
9997 | break; | |
9998 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9999 | trans_edp_pipe = PIPE_B; | |
10000 | break; | |
10001 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10002 | trans_edp_pipe = PIPE_C; | |
10003 | break; | |
10004 | } | |
10005 | ||
10006 | if (trans_edp_pipe == crtc->pipe) | |
10007 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10008 | } | |
10009 | ||
10010 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10011 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10012 | return false; | |
10013 | *power_domain_mask |= BIT(power_domain); | |
10014 | ||
10015 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10016 | ||
10017 | return tmp & PIPECONF_ENABLE; | |
10018 | } | |
10019 | ||
4d1de975 JN |
10020 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10021 | struct intel_crtc_state *pipe_config, | |
10022 | unsigned long *power_domain_mask) | |
10023 | { | |
10024 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10025 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10026 | enum intel_display_power_domain power_domain; |
10027 | enum port port; | |
10028 | enum transcoder cpu_transcoder; | |
10029 | u32 tmp; | |
10030 | ||
10031 | pipe_config->has_dsi_encoder = false; | |
10032 | ||
10033 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
10034 | if (port == PORT_A) | |
10035 | cpu_transcoder = TRANSCODER_DSI_A; | |
10036 | else | |
10037 | cpu_transcoder = TRANSCODER_DSI_C; | |
10038 | ||
10039 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10040 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10041 | continue; | |
10042 | *power_domain_mask |= BIT(power_domain); | |
10043 | ||
db18b6a6 ID |
10044 | /* |
10045 | * The PLL needs to be enabled with a valid divider | |
10046 | * configuration, otherwise accessing DSI registers will hang | |
10047 | * the machine. See BSpec North Display Engine | |
10048 | * registers/MIPI[BXT]. We can break out here early, since we | |
10049 | * need the same DSI PLL to be enabled for both DSI ports. | |
10050 | */ | |
10051 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10052 | break; | |
10053 | ||
4d1de975 JN |
10054 | /* XXX: this works for video mode only */ |
10055 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10056 | if (!(tmp & DPI_ENABLE)) | |
10057 | continue; | |
10058 | ||
10059 | tmp = I915_READ(MIPI_CTRL(port)); | |
10060 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10061 | continue; | |
10062 | ||
10063 | pipe_config->cpu_transcoder = cpu_transcoder; | |
10064 | pipe_config->has_dsi_encoder = true; | |
10065 | break; | |
10066 | } | |
10067 | ||
10068 | return pipe_config->has_dsi_encoder; | |
10069 | } | |
10070 | ||
26804afd | 10071 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10072 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10073 | { |
10074 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10075 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10076 | struct intel_shared_dpll *pll; |
26804afd DV |
10077 | enum port port; |
10078 | uint32_t tmp; | |
10079 | ||
10080 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10081 | ||
10082 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10083 | ||
ef11bdb3 | 10084 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10085 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10086 | else if (IS_BROXTON(dev)) |
10087 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10088 | else |
10089 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10090 | |
8106ddbd ACO |
10091 | pll = pipe_config->shared_dpll; |
10092 | if (pll) { | |
2edd6443 ACO |
10093 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10094 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10095 | } |
10096 | ||
26804afd DV |
10097 | /* |
10098 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10099 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10100 | * the PCH transcoder is on. | |
10101 | */ | |
ca370455 DL |
10102 | if (INTEL_INFO(dev)->gen < 9 && |
10103 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10104 | pipe_config->has_pch_encoder = true; |
10105 | ||
10106 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10107 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10108 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10109 | ||
10110 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10111 | } | |
10112 | } | |
10113 | ||
0e8ffe1b | 10114 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10115 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10116 | { |
10117 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10118 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10119 | enum intel_display_power_domain power_domain; |
10120 | unsigned long power_domain_mask; | |
cf30429e | 10121 | bool active; |
0e8ffe1b | 10122 | |
1729050e ID |
10123 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10124 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10125 | return false; |
1729050e ID |
10126 | power_domain_mask = BIT(power_domain); |
10127 | ||
8106ddbd | 10128 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10129 | |
cf30429e | 10130 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10131 | |
4d1de975 JN |
10132 | if (IS_BROXTON(dev_priv)) { |
10133 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
10134 | &power_domain_mask); | |
10135 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
10136 | if (pipe_config->has_dsi_encoder) | |
10137 | active = true; | |
10138 | } | |
10139 | ||
cf30429e | 10140 | if (!active) |
1729050e | 10141 | goto out; |
0e8ffe1b | 10142 | |
4d1de975 JN |
10143 | if (!pipe_config->has_dsi_encoder) { |
10144 | haswell_get_ddi_port_state(crtc, pipe_config); | |
10145 | intel_get_pipe_timings(crtc, pipe_config); | |
10146 | } | |
627eb5a3 | 10147 | |
bc58be60 | 10148 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10149 | |
05dc698c LL |
10150 | pipe_config->gamma_mode = |
10151 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10152 | ||
a1b2278e CK |
10153 | if (INTEL_INFO(dev)->gen >= 9) { |
10154 | skl_init_scalers(dev, crtc, pipe_config); | |
10155 | } | |
10156 | ||
af99ceda CK |
10157 | if (INTEL_INFO(dev)->gen >= 9) { |
10158 | pipe_config->scaler_state.scaler_id = -1; | |
10159 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10160 | } | |
10161 | ||
1729050e ID |
10162 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10163 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10164 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10165 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10166 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10167 | else |
1c132b44 | 10168 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10169 | } |
88adfff1 | 10170 | |
e59150dc JB |
10171 | if (IS_HASWELL(dev)) |
10172 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10173 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10174 | |
4d1de975 JN |
10175 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10176 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10177 | pipe_config->pixel_multiplier = |
10178 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10179 | } else { | |
10180 | pipe_config->pixel_multiplier = 1; | |
10181 | } | |
6c49f241 | 10182 | |
1729050e ID |
10183 | out: |
10184 | for_each_power_domain(power_domain, power_domain_mask) | |
10185 | intel_display_power_put(dev_priv, power_domain); | |
10186 | ||
cf30429e | 10187 | return active; |
0e8ffe1b DV |
10188 | } |
10189 | ||
55a08b3f ML |
10190 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10191 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10192 | { |
10193 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10194 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10196 | uint32_t cntl = 0, size = 0; |
560b85bb | 10197 | |
55a08b3f ML |
10198 | if (plane_state && plane_state->visible) { |
10199 | unsigned int width = plane_state->base.crtc_w; | |
10200 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10201 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10202 | ||
10203 | switch (stride) { | |
10204 | default: | |
10205 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10206 | width, stride); | |
10207 | stride = 256; | |
10208 | /* fallthrough */ | |
10209 | case 256: | |
10210 | case 512: | |
10211 | case 1024: | |
10212 | case 2048: | |
10213 | break; | |
4b0e333e CW |
10214 | } |
10215 | ||
dc41c154 VS |
10216 | cntl |= CURSOR_ENABLE | |
10217 | CURSOR_GAMMA_ENABLE | | |
10218 | CURSOR_FORMAT_ARGB | | |
10219 | CURSOR_STRIDE(stride); | |
10220 | ||
10221 | size = (height << 12) | width; | |
4b0e333e | 10222 | } |
560b85bb | 10223 | |
dc41c154 VS |
10224 | if (intel_crtc->cursor_cntl != 0 && |
10225 | (intel_crtc->cursor_base != base || | |
10226 | intel_crtc->cursor_size != size || | |
10227 | intel_crtc->cursor_cntl != cntl)) { | |
10228 | /* On these chipsets we can only modify the base/size/stride | |
10229 | * whilst the cursor is disabled. | |
10230 | */ | |
0b87c24e VS |
10231 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10232 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10233 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10234 | } |
560b85bb | 10235 | |
99d1f387 | 10236 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10237 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10238 | intel_crtc->cursor_base = base; |
10239 | } | |
4726e0b0 | 10240 | |
dc41c154 VS |
10241 | if (intel_crtc->cursor_size != size) { |
10242 | I915_WRITE(CURSIZE, size); | |
10243 | intel_crtc->cursor_size = size; | |
4b0e333e | 10244 | } |
560b85bb | 10245 | |
4b0e333e | 10246 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10247 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10248 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10249 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10250 | } |
560b85bb CW |
10251 | } |
10252 | ||
55a08b3f ML |
10253 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10254 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10255 | { |
10256 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10257 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10259 | int pipe = intel_crtc->pipe; | |
663f3122 | 10260 | uint32_t cntl = 0; |
4b0e333e | 10261 | |
55a08b3f | 10262 | if (plane_state && plane_state->visible) { |
4b0e333e | 10263 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10264 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10265 | case 64: |
10266 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10267 | break; | |
10268 | case 128: | |
10269 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10270 | break; | |
10271 | case 256: | |
10272 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10273 | break; | |
10274 | default: | |
55a08b3f | 10275 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10276 | return; |
65a21cd6 | 10277 | } |
4b0e333e | 10278 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10279 | |
fc6f93bc | 10280 | if (HAS_DDI(dev)) |
47bf17a7 | 10281 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10282 | |
55a08b3f ML |
10283 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10284 | cntl |= CURSOR_ROTATE_180; | |
10285 | } | |
4398ad45 | 10286 | |
4b0e333e CW |
10287 | if (intel_crtc->cursor_cntl != cntl) { |
10288 | I915_WRITE(CURCNTR(pipe), cntl); | |
10289 | POSTING_READ(CURCNTR(pipe)); | |
10290 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10291 | } |
4b0e333e | 10292 | |
65a21cd6 | 10293 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10294 | I915_WRITE(CURBASE(pipe), base); |
10295 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10296 | |
10297 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10298 | } |
10299 | ||
cda4b7d3 | 10300 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10301 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10302 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10303 | { |
10304 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10305 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10306 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10307 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10308 | u32 base = intel_crtc->cursor_addr; |
10309 | u32 pos = 0; | |
cda4b7d3 | 10310 | |
55a08b3f ML |
10311 | if (plane_state) { |
10312 | int x = plane_state->base.crtc_x; | |
10313 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10314 | |
55a08b3f ML |
10315 | if (x < 0) { |
10316 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10317 | x = -x; | |
10318 | } | |
10319 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10320 | |
55a08b3f ML |
10321 | if (y < 0) { |
10322 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10323 | y = -y; | |
10324 | } | |
10325 | pos |= y << CURSOR_Y_SHIFT; | |
10326 | ||
10327 | /* ILK+ do this automagically */ | |
10328 | if (HAS_GMCH_DISPLAY(dev) && | |
10329 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10330 | base += (plane_state->base.crtc_h * | |
10331 | plane_state->base.crtc_w - 1) * 4; | |
10332 | } | |
cda4b7d3 | 10333 | } |
cda4b7d3 | 10334 | |
5efb3e28 VS |
10335 | I915_WRITE(CURPOS(pipe), pos); |
10336 | ||
8ac54669 | 10337 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10338 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10339 | else |
55a08b3f | 10340 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10341 | } |
10342 | ||
dc41c154 VS |
10343 | static bool cursor_size_ok(struct drm_device *dev, |
10344 | uint32_t width, uint32_t height) | |
10345 | { | |
10346 | if (width == 0 || height == 0) | |
10347 | return false; | |
10348 | ||
10349 | /* | |
10350 | * 845g/865g are special in that they are only limited by | |
10351 | * the width of their cursors, the height is arbitrary up to | |
10352 | * the precision of the register. Everything else requires | |
10353 | * square cursors, limited to a few power-of-two sizes. | |
10354 | */ | |
10355 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10356 | if ((width & 63) != 0) | |
10357 | return false; | |
10358 | ||
10359 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10360 | return false; | |
10361 | ||
10362 | if (height > 1023) | |
10363 | return false; | |
10364 | } else { | |
10365 | switch (width | height) { | |
10366 | case 256: | |
10367 | case 128: | |
10368 | if (IS_GEN2(dev)) | |
10369 | return false; | |
10370 | case 64: | |
10371 | break; | |
10372 | default: | |
10373 | return false; | |
10374 | } | |
10375 | } | |
10376 | ||
10377 | return true; | |
10378 | } | |
10379 | ||
79e53945 JB |
10380 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10381 | static struct drm_display_mode load_detect_mode = { | |
10382 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10383 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10384 | }; | |
10385 | ||
a8bb6818 DV |
10386 | struct drm_framebuffer * |
10387 | __intel_framebuffer_create(struct drm_device *dev, | |
10388 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10389 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10390 | { |
10391 | struct intel_framebuffer *intel_fb; | |
10392 | int ret; | |
10393 | ||
10394 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10395 | if (!intel_fb) |
d2dff872 | 10396 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10397 | |
10398 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10399 | if (ret) |
10400 | goto err; | |
d2dff872 CW |
10401 | |
10402 | return &intel_fb->base; | |
dcb1394e | 10403 | |
dd4916c5 | 10404 | err: |
dd4916c5 | 10405 | kfree(intel_fb); |
dd4916c5 | 10406 | return ERR_PTR(ret); |
d2dff872 CW |
10407 | } |
10408 | ||
b5ea642a | 10409 | static struct drm_framebuffer * |
a8bb6818 DV |
10410 | intel_framebuffer_create(struct drm_device *dev, |
10411 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10412 | struct drm_i915_gem_object *obj) | |
10413 | { | |
10414 | struct drm_framebuffer *fb; | |
10415 | int ret; | |
10416 | ||
10417 | ret = i915_mutex_lock_interruptible(dev); | |
10418 | if (ret) | |
10419 | return ERR_PTR(ret); | |
10420 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10421 | mutex_unlock(&dev->struct_mutex); | |
10422 | ||
10423 | return fb; | |
10424 | } | |
10425 | ||
d2dff872 CW |
10426 | static u32 |
10427 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10428 | { | |
10429 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10430 | return ALIGN(pitch, 64); | |
10431 | } | |
10432 | ||
10433 | static u32 | |
10434 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10435 | { | |
10436 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10437 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10438 | } |
10439 | ||
10440 | static struct drm_framebuffer * | |
10441 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10442 | struct drm_display_mode *mode, | |
10443 | int depth, int bpp) | |
10444 | { | |
dcb1394e | 10445 | struct drm_framebuffer *fb; |
d2dff872 | 10446 | struct drm_i915_gem_object *obj; |
0fed39bd | 10447 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10448 | |
d37cd8a8 | 10449 | obj = i915_gem_object_create(dev, |
d2dff872 | 10450 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10451 | if (IS_ERR(obj)) |
10452 | return ERR_CAST(obj); | |
d2dff872 CW |
10453 | |
10454 | mode_cmd.width = mode->hdisplay; | |
10455 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10456 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10457 | bpp); | |
5ca0c34a | 10458 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10459 | |
dcb1394e LW |
10460 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10461 | if (IS_ERR(fb)) | |
10462 | drm_gem_object_unreference_unlocked(&obj->base); | |
10463 | ||
10464 | return fb; | |
d2dff872 CW |
10465 | } |
10466 | ||
10467 | static struct drm_framebuffer * | |
10468 | mode_fits_in_fbdev(struct drm_device *dev, | |
10469 | struct drm_display_mode *mode) | |
10470 | { | |
0695726e | 10471 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 10472 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
10473 | struct drm_i915_gem_object *obj; |
10474 | struct drm_framebuffer *fb; | |
10475 | ||
4c0e5528 | 10476 | if (!dev_priv->fbdev) |
d2dff872 CW |
10477 | return NULL; |
10478 | ||
4c0e5528 | 10479 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10480 | return NULL; |
10481 | ||
4c0e5528 DV |
10482 | obj = dev_priv->fbdev->fb->obj; |
10483 | BUG_ON(!obj); | |
10484 | ||
8bcd4553 | 10485 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10486 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10487 | fb->bits_per_pixel)) | |
d2dff872 CW |
10488 | return NULL; |
10489 | ||
01f2c773 | 10490 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10491 | return NULL; |
10492 | ||
edde3617 | 10493 | drm_framebuffer_reference(fb); |
d2dff872 | 10494 | return fb; |
4520f53a DV |
10495 | #else |
10496 | return NULL; | |
10497 | #endif | |
d2dff872 CW |
10498 | } |
10499 | ||
d3a40d1b ACO |
10500 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10501 | struct drm_crtc *crtc, | |
10502 | struct drm_display_mode *mode, | |
10503 | struct drm_framebuffer *fb, | |
10504 | int x, int y) | |
10505 | { | |
10506 | struct drm_plane_state *plane_state; | |
10507 | int hdisplay, vdisplay; | |
10508 | int ret; | |
10509 | ||
10510 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10511 | if (IS_ERR(plane_state)) | |
10512 | return PTR_ERR(plane_state); | |
10513 | ||
10514 | if (mode) | |
10515 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10516 | else | |
10517 | hdisplay = vdisplay = 0; | |
10518 | ||
10519 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10520 | if (ret) | |
10521 | return ret; | |
10522 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10523 | plane_state->crtc_x = 0; | |
10524 | plane_state->crtc_y = 0; | |
10525 | plane_state->crtc_w = hdisplay; | |
10526 | plane_state->crtc_h = vdisplay; | |
10527 | plane_state->src_x = x << 16; | |
10528 | plane_state->src_y = y << 16; | |
10529 | plane_state->src_w = hdisplay << 16; | |
10530 | plane_state->src_h = vdisplay << 16; | |
10531 | ||
10532 | return 0; | |
10533 | } | |
10534 | ||
d2434ab7 | 10535 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10536 | struct drm_display_mode *mode, |
51fd371b RC |
10537 | struct intel_load_detect_pipe *old, |
10538 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10539 | { |
10540 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10541 | struct intel_encoder *intel_encoder = |
10542 | intel_attached_encoder(connector); | |
79e53945 | 10543 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10544 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10545 | struct drm_crtc *crtc = NULL; |
10546 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10547 | struct drm_framebuffer *fb; |
51fd371b | 10548 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10549 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10550 | struct drm_connector_state *connector_state; |
4be07317 | 10551 | struct intel_crtc_state *crtc_state; |
51fd371b | 10552 | int ret, i = -1; |
79e53945 | 10553 | |
d2dff872 | 10554 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10555 | connector->base.id, connector->name, |
8e329a03 | 10556 | encoder->base.id, encoder->name); |
d2dff872 | 10557 | |
edde3617 ML |
10558 | old->restore_state = NULL; |
10559 | ||
51fd371b RC |
10560 | retry: |
10561 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10562 | if (ret) | |
ad3c558f | 10563 | goto fail; |
6e9f798d | 10564 | |
79e53945 JB |
10565 | /* |
10566 | * Algorithm gets a little messy: | |
7a5e4805 | 10567 | * |
79e53945 JB |
10568 | * - if the connector already has an assigned crtc, use it (but make |
10569 | * sure it's on first) | |
7a5e4805 | 10570 | * |
79e53945 JB |
10571 | * - try to find the first unused crtc that can drive this connector, |
10572 | * and use that if we find one | |
79e53945 JB |
10573 | */ |
10574 | ||
10575 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10576 | if (connector->state->crtc) { |
10577 | crtc = connector->state->crtc; | |
8261b191 | 10578 | |
51fd371b | 10579 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10580 | if (ret) |
ad3c558f | 10581 | goto fail; |
8261b191 CW |
10582 | |
10583 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10584 | goto found; |
79e53945 JB |
10585 | } |
10586 | ||
10587 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10588 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10589 | i++; |
10590 | if (!(encoder->possible_crtcs & (1 << i))) | |
10591 | continue; | |
edde3617 ML |
10592 | |
10593 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10594 | if (ret) | |
10595 | goto fail; | |
10596 | ||
10597 | if (possible_crtc->state->enable) { | |
10598 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10599 | continue; |
edde3617 | 10600 | } |
a459249c VS |
10601 | |
10602 | crtc = possible_crtc; | |
10603 | break; | |
79e53945 JB |
10604 | } |
10605 | ||
10606 | /* | |
10607 | * If we didn't find an unused CRTC, don't use any. | |
10608 | */ | |
10609 | if (!crtc) { | |
7173188d | 10610 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10611 | goto fail; |
79e53945 JB |
10612 | } |
10613 | ||
edde3617 ML |
10614 | found: |
10615 | intel_crtc = to_intel_crtc(crtc); | |
10616 | ||
4d02e2de DV |
10617 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10618 | if (ret) | |
ad3c558f | 10619 | goto fail; |
79e53945 | 10620 | |
83a57153 | 10621 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10622 | restore_state = drm_atomic_state_alloc(dev); |
10623 | if (!state || !restore_state) { | |
10624 | ret = -ENOMEM; | |
10625 | goto fail; | |
10626 | } | |
83a57153 ACO |
10627 | |
10628 | state->acquire_ctx = ctx; | |
edde3617 | 10629 | restore_state->acquire_ctx = ctx; |
83a57153 | 10630 | |
944b0c76 ACO |
10631 | connector_state = drm_atomic_get_connector_state(state, connector); |
10632 | if (IS_ERR(connector_state)) { | |
10633 | ret = PTR_ERR(connector_state); | |
10634 | goto fail; | |
10635 | } | |
10636 | ||
edde3617 ML |
10637 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10638 | if (ret) | |
10639 | goto fail; | |
944b0c76 | 10640 | |
4be07317 ACO |
10641 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10642 | if (IS_ERR(crtc_state)) { | |
10643 | ret = PTR_ERR(crtc_state); | |
10644 | goto fail; | |
10645 | } | |
10646 | ||
49d6fa21 | 10647 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10648 | |
6492711d CW |
10649 | if (!mode) |
10650 | mode = &load_detect_mode; | |
79e53945 | 10651 | |
d2dff872 CW |
10652 | /* We need a framebuffer large enough to accommodate all accesses |
10653 | * that the plane may generate whilst we perform load detection. | |
10654 | * We can not rely on the fbcon either being present (we get called | |
10655 | * during its initialisation to detect all boot displays, or it may | |
10656 | * not even exist) or that it is large enough to satisfy the | |
10657 | * requested mode. | |
10658 | */ | |
94352cf9 DV |
10659 | fb = mode_fits_in_fbdev(dev, mode); |
10660 | if (fb == NULL) { | |
d2dff872 | 10661 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10662 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10663 | } else |
10664 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10665 | if (IS_ERR(fb)) { |
d2dff872 | 10666 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10667 | goto fail; |
79e53945 | 10668 | } |
79e53945 | 10669 | |
d3a40d1b ACO |
10670 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10671 | if (ret) | |
10672 | goto fail; | |
10673 | ||
edde3617 ML |
10674 | drm_framebuffer_unreference(fb); |
10675 | ||
10676 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10677 | if (ret) | |
10678 | goto fail; | |
10679 | ||
10680 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10681 | if (!ret) | |
10682 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10683 | if (!ret) | |
10684 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10685 | if (ret) { | |
10686 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10687 | goto fail; | |
10688 | } | |
8c7b5ccb | 10689 | |
3ba86073 ML |
10690 | ret = drm_atomic_commit(state); |
10691 | if (ret) { | |
6492711d | 10692 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10693 | goto fail; |
79e53945 | 10694 | } |
edde3617 ML |
10695 | |
10696 | old->restore_state = restore_state; | |
7173188d | 10697 | |
79e53945 | 10698 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10699 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10700 | return true; |
412b61d8 | 10701 | |
ad3c558f | 10702 | fail: |
e5d958ef | 10703 | drm_atomic_state_free(state); |
edde3617 ML |
10704 | drm_atomic_state_free(restore_state); |
10705 | restore_state = state = NULL; | |
83a57153 | 10706 | |
51fd371b RC |
10707 | if (ret == -EDEADLK) { |
10708 | drm_modeset_backoff(ctx); | |
10709 | goto retry; | |
10710 | } | |
10711 | ||
412b61d8 | 10712 | return false; |
79e53945 JB |
10713 | } |
10714 | ||
d2434ab7 | 10715 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10716 | struct intel_load_detect_pipe *old, |
10717 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10718 | { |
d2434ab7 DV |
10719 | struct intel_encoder *intel_encoder = |
10720 | intel_attached_encoder(connector); | |
4ef69c7a | 10721 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10722 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10723 | int ret; |
79e53945 | 10724 | |
d2dff872 | 10725 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10726 | connector->base.id, connector->name, |
8e329a03 | 10727 | encoder->base.id, encoder->name); |
d2dff872 | 10728 | |
edde3617 | 10729 | if (!state) |
0622a53c | 10730 | return; |
79e53945 | 10731 | |
edde3617 ML |
10732 | ret = drm_atomic_commit(state); |
10733 | if (ret) { | |
10734 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10735 | drm_atomic_state_free(state); | |
10736 | } | |
79e53945 JB |
10737 | } |
10738 | ||
da4a1efa | 10739 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10740 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10741 | { |
fac5e23e | 10742 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10743 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10744 | ||
10745 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10746 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10747 | else if (HAS_PCH_SPLIT(dev)) |
10748 | return 120000; | |
10749 | else if (!IS_GEN2(dev)) | |
10750 | return 96000; | |
10751 | else | |
10752 | return 48000; | |
10753 | } | |
10754 | ||
79e53945 | 10755 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10756 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10757 | struct intel_crtc_state *pipe_config) |
79e53945 | 10758 | { |
f1f644dc | 10759 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10760 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10761 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10762 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10763 | u32 fp; |
9e2c8475 | 10764 | struct dpll clock; |
dccbea3b | 10765 | int port_clock; |
da4a1efa | 10766 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10767 | |
10768 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10769 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10770 | else |
293623f7 | 10771 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10772 | |
10773 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10774 | if (IS_PINEVIEW(dev)) { |
10775 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10776 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10777 | } else { |
10778 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10779 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10780 | } | |
10781 | ||
a6c45cf0 | 10782 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10783 | if (IS_PINEVIEW(dev)) |
10784 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10785 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10786 | else |
10787 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10788 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10789 | ||
10790 | switch (dpll & DPLL_MODE_MASK) { | |
10791 | case DPLLB_MODE_DAC_SERIAL: | |
10792 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10793 | 5 : 10; | |
10794 | break; | |
10795 | case DPLLB_MODE_LVDS: | |
10796 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10797 | 7 : 14; | |
10798 | break; | |
10799 | default: | |
28c97730 | 10800 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10801 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10802 | return; |
79e53945 JB |
10803 | } |
10804 | ||
ac58c3f0 | 10805 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10806 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10807 | else |
dccbea3b | 10808 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10809 | } else { |
0fb58223 | 10810 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10811 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10812 | |
10813 | if (is_lvds) { | |
10814 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10815 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10816 | |
10817 | if (lvds & LVDS_CLKB_POWER_UP) | |
10818 | clock.p2 = 7; | |
10819 | else | |
10820 | clock.p2 = 14; | |
79e53945 JB |
10821 | } else { |
10822 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10823 | clock.p1 = 2; | |
10824 | else { | |
10825 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10826 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10827 | } | |
10828 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10829 | clock.p2 = 4; | |
10830 | else | |
10831 | clock.p2 = 2; | |
79e53945 | 10832 | } |
da4a1efa | 10833 | |
dccbea3b | 10834 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10835 | } |
10836 | ||
18442d08 VS |
10837 | /* |
10838 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10839 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10840 | * encoder's get_config() function. |
10841 | */ | |
dccbea3b | 10842 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10843 | } |
10844 | ||
6878da05 VS |
10845 | int intel_dotclock_calculate(int link_freq, |
10846 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10847 | { |
f1f644dc JB |
10848 | /* |
10849 | * The calculation for the data clock is: | |
1041a02f | 10850 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10851 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10852 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10853 | * |
10854 | * and the link clock is simpler: | |
1041a02f | 10855 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10856 | */ |
10857 | ||
6878da05 VS |
10858 | if (!m_n->link_n) |
10859 | return 0; | |
f1f644dc | 10860 | |
6878da05 VS |
10861 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10862 | } | |
f1f644dc | 10863 | |
18442d08 | 10864 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10865 | struct intel_crtc_state *pipe_config) |
6878da05 | 10866 | { |
e3b247da | 10867 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10868 | |
18442d08 VS |
10869 | /* read out port_clock from the DPLL */ |
10870 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10871 | |
f1f644dc | 10872 | /* |
e3b247da VS |
10873 | * In case there is an active pipe without active ports, |
10874 | * we may need some idea for the dotclock anyway. | |
10875 | * Calculate one based on the FDI configuration. | |
79e53945 | 10876 | */ |
2d112de7 | 10877 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10878 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10879 | &pipe_config->fdi_m_n); |
79e53945 JB |
10880 | } |
10881 | ||
10882 | /** Returns the currently programmed mode of the given pipe. */ | |
10883 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10884 | struct drm_crtc *crtc) | |
10885 | { | |
fac5e23e | 10886 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10887 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10888 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10889 | struct drm_display_mode *mode; |
3f36b937 | 10890 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10891 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10892 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10893 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10894 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10895 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10896 | |
10897 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10898 | if (!mode) | |
10899 | return NULL; | |
10900 | ||
3f36b937 TU |
10901 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10902 | if (!pipe_config) { | |
10903 | kfree(mode); | |
10904 | return NULL; | |
10905 | } | |
10906 | ||
f1f644dc JB |
10907 | /* |
10908 | * Construct a pipe_config sufficient for getting the clock info | |
10909 | * back out of crtc_clock_get. | |
10910 | * | |
10911 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10912 | * to use a real value here instead. | |
10913 | */ | |
3f36b937 TU |
10914 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10915 | pipe_config->pixel_multiplier = 1; | |
10916 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10917 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10918 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10919 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10920 | ||
10921 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10922 | mode->hdisplay = (htot & 0xffff) + 1; |
10923 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10924 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10925 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10926 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10927 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10928 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10929 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10930 | ||
10931 | drm_mode_set_name(mode); | |
79e53945 | 10932 | |
3f36b937 TU |
10933 | kfree(pipe_config); |
10934 | ||
79e53945 JB |
10935 | return mode; |
10936 | } | |
10937 | ||
10938 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10939 | { | |
10940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 10941 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 10942 | struct intel_flip_work *work; |
67e77c5a | 10943 | |
5e2d7afc | 10944 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
10945 | work = intel_crtc->flip_work; |
10946 | intel_crtc->flip_work = NULL; | |
10947 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 10948 | |
5a21b665 | 10949 | if (work) { |
51cbaf01 ML |
10950 | cancel_work_sync(&work->mmio_work); |
10951 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 10952 | kfree(work); |
67e77c5a | 10953 | } |
79e53945 JB |
10954 | |
10955 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10956 | |
79e53945 JB |
10957 | kfree(intel_crtc); |
10958 | } | |
10959 | ||
6b95a207 KH |
10960 | static void intel_unpin_work_fn(struct work_struct *__work) |
10961 | { | |
51cbaf01 ML |
10962 | struct intel_flip_work *work = |
10963 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
10964 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10965 | struct drm_device *dev = crtc->base.dev; | |
10966 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 10967 | |
5a21b665 DV |
10968 | if (is_mmio_work(work)) |
10969 | flush_work(&work->mmio_work); | |
03f476e1 | 10970 | |
5a21b665 DV |
10971 | mutex_lock(&dev->struct_mutex); |
10972 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
10973 | drm_gem_object_unreference(&work->pending_flip_obj->base); | |
143f73b3 | 10974 | |
5a21b665 DV |
10975 | if (work->flip_queued_req) |
10976 | i915_gem_request_assign(&work->flip_queued_req, NULL); | |
10977 | mutex_unlock(&dev->struct_mutex); | |
143f73b3 | 10978 | |
5a21b665 DV |
10979 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
10980 | intel_fbc_post_update(crtc); | |
10981 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 10982 | |
5a21b665 DV |
10983 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10984 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 10985 | |
5a21b665 DV |
10986 | kfree(work); |
10987 | } | |
d9e86c0e | 10988 | |
5a21b665 DV |
10989 | /* Is 'a' after or equal to 'b'? */ |
10990 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10991 | { | |
10992 | return !((a - b) & 0x80000000); | |
10993 | } | |
143f73b3 | 10994 | |
5a21b665 DV |
10995 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
10996 | struct intel_flip_work *work) | |
10997 | { | |
10998 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10999 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 11000 | unsigned reset_counter; |
143f73b3 | 11001 | |
5a21b665 DV |
11002 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
11003 | if (crtc->reset_counter != reset_counter) | |
11004 | return true; | |
143f73b3 | 11005 | |
5a21b665 DV |
11006 | /* |
11007 | * The relevant registers doen't exist on pre-ctg. | |
11008 | * As the flip done interrupt doesn't trigger for mmio | |
11009 | * flips on gmch platforms, a flip count check isn't | |
11010 | * really needed there. But since ctg has the registers, | |
11011 | * include it in the check anyway. | |
11012 | */ | |
11013 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11014 | return true; | |
b4a98e57 | 11015 | |
5a21b665 DV |
11016 | /* |
11017 | * BDW signals flip done immediately if the plane | |
11018 | * is disabled, even if the plane enable is already | |
11019 | * armed to occur at the next vblank :( | |
11020 | */ | |
f99d7069 | 11021 | |
5a21b665 DV |
11022 | /* |
11023 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11024 | * used the same base address. In that case the mmio flip might | |
11025 | * have completed, but the CS hasn't even executed the flip yet. | |
11026 | * | |
11027 | * A flip count check isn't enough as the CS might have updated | |
11028 | * the base address just after start of vblank, but before we | |
11029 | * managed to process the interrupt. This means we'd complete the | |
11030 | * CS flip too soon. | |
11031 | * | |
11032 | * Combining both checks should get us a good enough result. It may | |
11033 | * still happen that the CS flip has been executed, but has not | |
11034 | * yet actually completed. But in case the base address is the same | |
11035 | * anyway, we don't really care. | |
11036 | */ | |
11037 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11038 | crtc->flip_work->gtt_offset && | |
11039 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11040 | crtc->flip_work->flip_count); | |
11041 | } | |
b4a98e57 | 11042 | |
5a21b665 DV |
11043 | static bool |
11044 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11045 | struct intel_flip_work *work) | |
11046 | { | |
11047 | /* | |
11048 | * MMIO work completes when vblank is different from | |
11049 | * flip_queued_vblank. | |
11050 | * | |
11051 | * Reset counter value doesn't matter, this is handled by | |
11052 | * i915_wait_request finishing early, so no need to handle | |
11053 | * reset here. | |
11054 | */ | |
11055 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11056 | } |
11057 | ||
51cbaf01 ML |
11058 | |
11059 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11060 | struct intel_flip_work *work) | |
11061 | { | |
11062 | if (!atomic_read(&work->pending)) | |
11063 | return false; | |
11064 | ||
11065 | smp_rmb(); | |
11066 | ||
5a21b665 DV |
11067 | if (is_mmio_work(work)) |
11068 | return __pageflip_finished_mmio(crtc, work); | |
11069 | else | |
11070 | return __pageflip_finished_cs(crtc, work); | |
11071 | } | |
11072 | ||
11073 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11074 | { | |
91c8a326 | 11075 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11076 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11078 | struct intel_flip_work *work; | |
11079 | unsigned long flags; | |
11080 | ||
11081 | /* Ignore early vblank irqs */ | |
11082 | if (!crtc) | |
11083 | return; | |
11084 | ||
51cbaf01 | 11085 | /* |
5a21b665 DV |
11086 | * This is called both by irq handlers and the reset code (to complete |
11087 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11088 | */ |
5a21b665 DV |
11089 | spin_lock_irqsave(&dev->event_lock, flags); |
11090 | work = intel_crtc->flip_work; | |
11091 | ||
11092 | if (work != NULL && | |
11093 | !is_mmio_work(work) && | |
11094 | pageflip_finished(intel_crtc, work)) | |
11095 | page_flip_completed(intel_crtc); | |
11096 | ||
11097 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11098 | } |
11099 | ||
51cbaf01 | 11100 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11101 | { |
91c8a326 | 11102 | struct drm_device *dev = &dev_priv->drm; |
5251f04e ML |
11103 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11104 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11105 | struct intel_flip_work *work; |
6b95a207 KH |
11106 | unsigned long flags; |
11107 | ||
5251f04e ML |
11108 | /* Ignore early vblank irqs */ |
11109 | if (!crtc) | |
11110 | return; | |
f326038a DV |
11111 | |
11112 | /* | |
11113 | * This is called both by irq handlers and the reset code (to complete | |
11114 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11115 | */ |
6b95a207 | 11116 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11117 | work = intel_crtc->flip_work; |
5251f04e | 11118 | |
5a21b665 DV |
11119 | if (work != NULL && |
11120 | is_mmio_work(work) && | |
11121 | pageflip_finished(intel_crtc, work)) | |
11122 | page_flip_completed(intel_crtc); | |
5251f04e | 11123 | |
6b95a207 KH |
11124 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11125 | } | |
11126 | ||
5a21b665 DV |
11127 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11128 | struct intel_flip_work *work) | |
84c33a64 | 11129 | { |
5a21b665 | 11130 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11131 | |
5a21b665 DV |
11132 | /* Ensure that the work item is consistent when activating it ... */ |
11133 | smp_mb__before_atomic(); | |
11134 | atomic_set(&work->pending, 1); | |
11135 | } | |
a6747b73 | 11136 | |
5a21b665 DV |
11137 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11138 | struct drm_crtc *crtc, | |
11139 | struct drm_framebuffer *fb, | |
11140 | struct drm_i915_gem_object *obj, | |
11141 | struct drm_i915_gem_request *req, | |
11142 | uint32_t flags) | |
11143 | { | |
11144 | struct intel_engine_cs *engine = req->engine; | |
11145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11146 | u32 flip_mask; | |
11147 | int ret; | |
143f73b3 | 11148 | |
5a21b665 DV |
11149 | ret = intel_ring_begin(req, 6); |
11150 | if (ret) | |
11151 | return ret; | |
143f73b3 | 11152 | |
5a21b665 DV |
11153 | /* Can't queue multiple flips, so wait for the previous |
11154 | * one to finish before executing the next. | |
11155 | */ | |
11156 | if (intel_crtc->plane) | |
11157 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11158 | else | |
11159 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11160 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11161 | intel_ring_emit(engine, MI_NOOP); | |
11162 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11163 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11164 | intel_ring_emit(engine, fb->pitches[0]); | |
11165 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11166 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
143f73b3 | 11167 | |
5a21b665 DV |
11168 | return 0; |
11169 | } | |
84c33a64 | 11170 | |
5a21b665 DV |
11171 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11172 | struct drm_crtc *crtc, | |
11173 | struct drm_framebuffer *fb, | |
11174 | struct drm_i915_gem_object *obj, | |
11175 | struct drm_i915_gem_request *req, | |
11176 | uint32_t flags) | |
11177 | { | |
11178 | struct intel_engine_cs *engine = req->engine; | |
11179 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11180 | u32 flip_mask; | |
11181 | int ret; | |
d55dbd06 | 11182 | |
5a21b665 DV |
11183 | ret = intel_ring_begin(req, 6); |
11184 | if (ret) | |
11185 | return ret; | |
d55dbd06 | 11186 | |
5a21b665 DV |
11187 | if (intel_crtc->plane) |
11188 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11189 | else | |
11190 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11191 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11192 | intel_ring_emit(engine, MI_NOOP); | |
11193 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
11194 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11195 | intel_ring_emit(engine, fb->pitches[0]); | |
11196 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11197 | intel_ring_emit(engine, MI_NOOP); | |
fd8e058a | 11198 | |
5a21b665 DV |
11199 | return 0; |
11200 | } | |
84c33a64 | 11201 | |
5a21b665 DV |
11202 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11203 | struct drm_crtc *crtc, | |
11204 | struct drm_framebuffer *fb, | |
11205 | struct drm_i915_gem_object *obj, | |
11206 | struct drm_i915_gem_request *req, | |
11207 | uint32_t flags) | |
11208 | { | |
11209 | struct intel_engine_cs *engine = req->engine; | |
fac5e23e | 11210 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11211 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11212 | uint32_t pf, pipesrc; | |
11213 | int ret; | |
143f73b3 | 11214 | |
5a21b665 DV |
11215 | ret = intel_ring_begin(req, 4); |
11216 | if (ret) | |
11217 | return ret; | |
143f73b3 | 11218 | |
5a21b665 DV |
11219 | /* i965+ uses the linear or tiled offsets from the |
11220 | * Display Registers (which do not change across a page-flip) | |
11221 | * so we need only reprogram the base address. | |
11222 | */ | |
11223 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11224 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11225 | intel_ring_emit(engine, fb->pitches[0]); | |
11226 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset | | |
11227 | obj->tiling_mode); | |
11228 | ||
11229 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11230 | * untested on non-native modes, so ignore it for now. | |
11231 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11232 | */ | |
11233 | pf = 0; | |
11234 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11235 | intel_ring_emit(engine, pf | pipesrc); | |
143f73b3 | 11236 | |
5a21b665 | 11237 | return 0; |
8c9f3aaf JB |
11238 | } |
11239 | ||
5a21b665 DV |
11240 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11241 | struct drm_crtc *crtc, | |
11242 | struct drm_framebuffer *fb, | |
11243 | struct drm_i915_gem_object *obj, | |
11244 | struct drm_i915_gem_request *req, | |
11245 | uint32_t flags) | |
da20eabd | 11246 | { |
5a21b665 | 11247 | struct intel_engine_cs *engine = req->engine; |
fac5e23e | 11248 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11250 | uint32_t pf, pipesrc; | |
11251 | int ret; | |
d21fbe87 | 11252 | |
5a21b665 DV |
11253 | ret = intel_ring_begin(req, 4); |
11254 | if (ret) | |
11255 | return ret; | |
92826fcd | 11256 | |
5a21b665 DV |
11257 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
11258 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11259 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); | |
11260 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
92826fcd | 11261 | |
5a21b665 DV |
11262 | /* Contrary to the suggestions in the documentation, |
11263 | * "Enable Panel Fitter" does not seem to be required when page | |
11264 | * flipping with a non-native mode, and worse causes a normal | |
11265 | * modeset to fail. | |
11266 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11267 | */ | |
11268 | pf = 0; | |
11269 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11270 | intel_ring_emit(engine, pf | pipesrc); | |
7809e5ae | 11271 | |
5a21b665 | 11272 | return 0; |
7809e5ae MR |
11273 | } |
11274 | ||
5a21b665 DV |
11275 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11276 | struct drm_crtc *crtc, | |
11277 | struct drm_framebuffer *fb, | |
11278 | struct drm_i915_gem_object *obj, | |
11279 | struct drm_i915_gem_request *req, | |
11280 | uint32_t flags) | |
d21fbe87 | 11281 | { |
5a21b665 DV |
11282 | struct intel_engine_cs *engine = req->engine; |
11283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11284 | uint32_t plane_bit = 0; | |
11285 | int len, ret; | |
d21fbe87 | 11286 | |
5a21b665 DV |
11287 | switch (intel_crtc->plane) { |
11288 | case PLANE_A: | |
11289 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11290 | break; | |
11291 | case PLANE_B: | |
11292 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11293 | break; | |
11294 | case PLANE_C: | |
11295 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11296 | break; | |
11297 | default: | |
11298 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11299 | return -ENODEV; | |
11300 | } | |
11301 | ||
11302 | len = 4; | |
11303 | if (engine->id == RCS) { | |
11304 | len += 6; | |
11305 | /* | |
11306 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11307 | * 48bits addresses, and we need a NOOP for the batch size to | |
11308 | * stay even. | |
11309 | */ | |
11310 | if (IS_GEN8(dev)) | |
11311 | len += 2; | |
11312 | } | |
11313 | ||
11314 | /* | |
11315 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11316 | * "The full packet must be contained within the same cache line." | |
11317 | * | |
11318 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11319 | * cacheline, if we ever start emitting more commands before | |
11320 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11321 | * then do the cacheline alignment, and finally emit the | |
11322 | * MI_DISPLAY_FLIP. | |
11323 | */ | |
11324 | ret = intel_ring_cacheline_align(req); | |
11325 | if (ret) | |
11326 | return ret; | |
11327 | ||
11328 | ret = intel_ring_begin(req, len); | |
11329 | if (ret) | |
11330 | return ret; | |
11331 | ||
11332 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11333 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11334 | * more than one flip event at any time (or ensure that one flip message | |
11335 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11336 | * Experimentation says that BCS works despite DERRMR masking all | |
11337 | * flip-done completion events and that unmasking all planes at once | |
11338 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11339 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11340 | */ | |
11341 | if (engine->id == RCS) { | |
11342 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11343 | intel_ring_emit_reg(engine, DERRMR); | |
11344 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11345 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11346 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11347 | if (IS_GEN8(dev)) | |
11348 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | | |
11349 | MI_SRM_LRM_GLOBAL_GTT); | |
11350 | else | |
11351 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | | |
11352 | MI_SRM_LRM_GLOBAL_GTT); | |
11353 | intel_ring_emit_reg(engine, DERRMR); | |
11354 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
11355 | if (IS_GEN8(dev)) { | |
11356 | intel_ring_emit(engine, 0); | |
11357 | intel_ring_emit(engine, MI_NOOP); | |
11358 | } | |
11359 | } | |
11360 | ||
11361 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); | |
11362 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11363 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11364 | intel_ring_emit(engine, (MI_NOOP)); | |
11365 | ||
11366 | return 0; | |
11367 | } | |
11368 | ||
11369 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11370 | struct drm_i915_gem_object *obj) | |
11371 | { | |
c37efb99 CW |
11372 | struct reservation_object *resv; |
11373 | ||
5a21b665 DV |
11374 | /* |
11375 | * This is not being used for older platforms, because | |
11376 | * non-availability of flip done interrupt forces us to use | |
11377 | * CS flips. Older platforms derive flip done using some clever | |
11378 | * tricks involving the flip_pending status bits and vblank irqs. | |
11379 | * So using MMIO flips there would disrupt this mechanism. | |
11380 | */ | |
11381 | ||
11382 | if (engine == NULL) | |
11383 | return true; | |
11384 | ||
11385 | if (INTEL_GEN(engine->i915) < 5) | |
11386 | return false; | |
11387 | ||
11388 | if (i915.use_mmio_flip < 0) | |
11389 | return false; | |
11390 | else if (i915.use_mmio_flip > 0) | |
11391 | return true; | |
11392 | else if (i915.enable_execlists) | |
11393 | return true; | |
c37efb99 CW |
11394 | |
11395 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
11396 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) | |
5a21b665 | 11397 | return true; |
c37efb99 CW |
11398 | |
11399 | return engine != i915_gem_request_get_engine(obj->last_write_req); | |
5a21b665 DV |
11400 | } |
11401 | ||
11402 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11403 | unsigned int rotation, | |
11404 | struct intel_flip_work *work) | |
11405 | { | |
11406 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11407 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11408 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11409 | const enum pipe pipe = intel_crtc->pipe; | |
11410 | u32 ctl, stride, tile_height; | |
11411 | ||
11412 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11413 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11414 | switch (fb->modifier[0]) { | |
11415 | case DRM_FORMAT_MOD_NONE: | |
11416 | break; | |
11417 | case I915_FORMAT_MOD_X_TILED: | |
11418 | ctl |= PLANE_CTL_TILED_X; | |
11419 | break; | |
11420 | case I915_FORMAT_MOD_Y_TILED: | |
11421 | ctl |= PLANE_CTL_TILED_Y; | |
11422 | break; | |
11423 | case I915_FORMAT_MOD_Yf_TILED: | |
11424 | ctl |= PLANE_CTL_TILED_YF; | |
11425 | break; | |
11426 | default: | |
11427 | MISSING_CASE(fb->modifier[0]); | |
11428 | } | |
11429 | ||
11430 | /* | |
11431 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11432 | * linear buffers or in number of tiles for tiled buffers. | |
11433 | */ | |
11434 | if (intel_rotation_90_or_270(rotation)) { | |
11435 | /* stride = Surface height in tiles */ | |
11436 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); | |
11437 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11438 | } else { | |
11439 | stride = fb->pitches[0] / | |
11440 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
11441 | fb->pixel_format); | |
11442 | } | |
11443 | ||
11444 | /* | |
11445 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11446 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11447 | */ | |
11448 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11449 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11450 | ||
11451 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11452 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11453 | } | |
11454 | ||
11455 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11456 | struct intel_flip_work *work) | |
11457 | { | |
11458 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11459 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11460 | struct intel_framebuffer *intel_fb = |
11461 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11462 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11463 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); | |
11464 | u32 dspcntr; | |
11465 | ||
11466 | dspcntr = I915_READ(reg); | |
11467 | ||
11468 | if (obj->tiling_mode != I915_TILING_NONE) | |
11469 | dspcntr |= DISPPLANE_TILED; | |
11470 | else | |
11471 | dspcntr &= ~DISPPLANE_TILED; | |
11472 | ||
11473 | I915_WRITE(reg, dspcntr); | |
11474 | ||
11475 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11476 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11477 | } | |
11478 | ||
11479 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
11480 | { | |
11481 | struct intel_flip_work *work = | |
11482 | container_of(w, struct intel_flip_work, mmio_work); | |
11483 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
11484 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
11485 | struct intel_framebuffer *intel_fb = | |
11486 | to_intel_framebuffer(crtc->base.primary->fb); | |
11487 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
c37efb99 | 11488 | struct reservation_object *resv; |
5a21b665 DV |
11489 | |
11490 | if (work->flip_queued_req) | |
11491 | WARN_ON(__i915_wait_request(work->flip_queued_req, | |
11492 | false, NULL, | |
11493 | &dev_priv->rps.mmioflips)); | |
11494 | ||
11495 | /* For framebuffer backed by dmabuf, wait for fence */ | |
c37efb99 CW |
11496 | resv = i915_gem_object_get_dmabuf_resv(obj); |
11497 | if (resv) | |
11498 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, | |
5a21b665 DV |
11499 | MAX_SCHEDULE_TIMEOUT) < 0); |
11500 | ||
11501 | intel_pipe_update_start(crtc); | |
11502 | ||
11503 | if (INTEL_GEN(dev_priv) >= 9) | |
11504 | skl_do_mmio_flip(crtc, work->rotation, work); | |
11505 | else | |
11506 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11507 | ilk_do_mmio_flip(crtc, work); | |
11508 | ||
11509 | intel_pipe_update_end(crtc, work); | |
11510 | } | |
11511 | ||
11512 | static int intel_default_queue_flip(struct drm_device *dev, | |
11513 | struct drm_crtc *crtc, | |
11514 | struct drm_framebuffer *fb, | |
11515 | struct drm_i915_gem_object *obj, | |
11516 | struct drm_i915_gem_request *req, | |
11517 | uint32_t flags) | |
11518 | { | |
11519 | return -ENODEV; | |
11520 | } | |
11521 | ||
11522 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
11523 | struct intel_crtc *intel_crtc, | |
11524 | struct intel_flip_work *work) | |
11525 | { | |
11526 | u32 addr, vblank; | |
11527 | ||
11528 | if (!atomic_read(&work->pending)) | |
11529 | return false; | |
11530 | ||
11531 | smp_rmb(); | |
11532 | ||
11533 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
11534 | if (work->flip_ready_vblank == 0) { | |
11535 | if (work->flip_queued_req && | |
f69a02c9 | 11536 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
11537 | return false; |
11538 | ||
11539 | work->flip_ready_vblank = vblank; | |
11540 | } | |
11541 | ||
11542 | if (vblank - work->flip_ready_vblank < 3) | |
11543 | return false; | |
11544 | ||
11545 | /* Potential stall - if we see that the flip has happened, | |
11546 | * assume a missed interrupt. */ | |
11547 | if (INTEL_GEN(dev_priv) >= 4) | |
11548 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11549 | else | |
11550 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11551 | ||
11552 | /* There is a potential issue here with a false positive after a flip | |
11553 | * to the same address. We could address this by checking for a | |
11554 | * non-incrementing frame counter. | |
11555 | */ | |
11556 | return addr == work->gtt_offset; | |
11557 | } | |
11558 | ||
11559 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
11560 | { | |
91c8a326 | 11561 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11562 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11563 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11564 | struct intel_flip_work *work; | |
11565 | ||
11566 | WARN_ON(!in_interrupt()); | |
11567 | ||
11568 | if (crtc == NULL) | |
11569 | return; | |
11570 | ||
11571 | spin_lock(&dev->event_lock); | |
11572 | work = intel_crtc->flip_work; | |
11573 | ||
11574 | if (work != NULL && !is_mmio_work(work) && | |
11575 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
11576 | WARN_ONCE(1, | |
11577 | "Kicking stuck page flip: queued at %d, now %d\n", | |
11578 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
11579 | page_flip_completed(intel_crtc); | |
11580 | work = NULL; | |
11581 | } | |
11582 | ||
11583 | if (work != NULL && !is_mmio_work(work) && | |
11584 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
11585 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
11586 | spin_unlock(&dev->event_lock); | |
11587 | } | |
11588 | ||
11589 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
11590 | struct drm_framebuffer *fb, | |
11591 | struct drm_pending_vblank_event *event, | |
11592 | uint32_t page_flip_flags) | |
11593 | { | |
11594 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 11595 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11596 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
11597 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11598 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11599 | struct drm_plane *primary = crtc->primary; | |
11600 | enum pipe pipe = intel_crtc->pipe; | |
11601 | struct intel_flip_work *work; | |
11602 | struct intel_engine_cs *engine; | |
11603 | bool mmio_flip; | |
11604 | struct drm_i915_gem_request *request = NULL; | |
11605 | int ret; | |
11606 | ||
11607 | /* | |
11608 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11609 | * check to be safe. In the future we may enable pageflipping from | |
11610 | * a disabled primary plane. | |
11611 | */ | |
11612 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11613 | return -EBUSY; | |
11614 | ||
11615 | /* Can't change pixel format via MI display flips. */ | |
11616 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
11617 | return -EINVAL; | |
11618 | ||
11619 | /* | |
11620 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11621 | * Note that pitch changes could also affect these register. | |
11622 | */ | |
11623 | if (INTEL_INFO(dev)->gen > 3 && | |
11624 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
11625 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
11626 | return -EINVAL; | |
11627 | ||
11628 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
11629 | goto out_hang; | |
11630 | ||
11631 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
11632 | if (work == NULL) | |
11633 | return -ENOMEM; | |
11634 | ||
11635 | work->event = event; | |
11636 | work->crtc = crtc; | |
11637 | work->old_fb = old_fb; | |
11638 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
11639 | ||
11640 | ret = drm_crtc_vblank_get(crtc); | |
11641 | if (ret) | |
11642 | goto free_work; | |
11643 | ||
11644 | /* We borrow the event spin lock for protecting flip_work */ | |
11645 | spin_lock_irq(&dev->event_lock); | |
11646 | if (intel_crtc->flip_work) { | |
11647 | /* Before declaring the flip queue wedged, check if | |
11648 | * the hardware completed the operation behind our backs. | |
11649 | */ | |
11650 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
11651 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11652 | page_flip_completed(intel_crtc); | |
11653 | } else { | |
11654 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
11655 | spin_unlock_irq(&dev->event_lock); | |
11656 | ||
11657 | drm_crtc_vblank_put(crtc); | |
11658 | kfree(work); | |
11659 | return -EBUSY; | |
11660 | } | |
11661 | } | |
11662 | intel_crtc->flip_work = work; | |
11663 | spin_unlock_irq(&dev->event_lock); | |
11664 | ||
11665 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
11666 | flush_workqueue(dev_priv->wq); | |
11667 | ||
11668 | /* Reference the objects for the scheduled work. */ | |
11669 | drm_framebuffer_reference(work->old_fb); | |
11670 | drm_gem_object_reference(&obj->base); | |
11671 | ||
11672 | crtc->primary->fb = fb; | |
11673 | update_state_fb(crtc->primary); | |
faf68d92 ML |
11674 | |
11675 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
11676 | to_intel_plane_state(primary->state)); | |
5a21b665 DV |
11677 | |
11678 | work->pending_flip_obj = obj; | |
11679 | ||
11680 | ret = i915_mutex_lock_interruptible(dev); | |
11681 | if (ret) | |
11682 | goto cleanup; | |
11683 | ||
11684 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
11685 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
11686 | ret = -EIO; | |
11687 | goto cleanup; | |
11688 | } | |
11689 | ||
11690 | atomic_inc(&intel_crtc->unpin_work_count); | |
11691 | ||
11692 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
11693 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
11694 | ||
11695 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
11696 | engine = &dev_priv->engine[BCS]; | |
11697 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) | |
11698 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
11699 | engine = NULL; | |
11700 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
11701 | engine = &dev_priv->engine[BCS]; | |
11702 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
11703 | engine = i915_gem_request_get_engine(obj->last_write_req); | |
11704 | if (engine == NULL || engine->id != RCS) | |
11705 | engine = &dev_priv->engine[BCS]; | |
11706 | } else { | |
11707 | engine = &dev_priv->engine[RCS]; | |
11708 | } | |
11709 | ||
11710 | mmio_flip = use_mmio_flip(engine, obj); | |
11711 | ||
11712 | /* When using CS flips, we want to emit semaphores between rings. | |
11713 | * However, when using mmio flips we will create a task to do the | |
11714 | * synchronisation, so all we want here is to pin the framebuffer | |
11715 | * into the display plane and skip any waits. | |
11716 | */ | |
11717 | if (!mmio_flip) { | |
11718 | ret = i915_gem_object_sync(obj, engine, &request); | |
11719 | if (!ret && !request) { | |
11720 | request = i915_gem_request_alloc(engine, NULL); | |
11721 | ret = PTR_ERR_OR_ZERO(request); | |
11722 | } | |
11723 | ||
11724 | if (ret) | |
11725 | goto cleanup_pending; | |
11726 | } | |
11727 | ||
11728 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
11729 | if (ret) | |
11730 | goto cleanup_pending; | |
11731 | ||
11732 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), | |
11733 | obj, 0); | |
11734 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
11735 | work->rotation = crtc->primary->state->rotation; | |
11736 | ||
11737 | if (mmio_flip) { | |
11738 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
11739 | ||
11740 | i915_gem_request_assign(&work->flip_queued_req, | |
11741 | obj->last_write_req); | |
11742 | ||
11743 | schedule_work(&work->mmio_work); | |
11744 | } else { | |
11745 | i915_gem_request_assign(&work->flip_queued_req, request); | |
11746 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
11747 | page_flip_flags); | |
11748 | if (ret) | |
11749 | goto cleanup_unpin; | |
11750 | ||
11751 | intel_mark_page_flip_active(intel_crtc, work); | |
11752 | ||
11753 | i915_add_request_no_flush(request); | |
11754 | } | |
11755 | ||
11756 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
11757 | to_intel_plane(primary)->frontbuffer_bit); | |
11758 | mutex_unlock(&dev->struct_mutex); | |
11759 | ||
11760 | intel_frontbuffer_flip_prepare(dev, | |
11761 | to_intel_plane(primary)->frontbuffer_bit); | |
11762 | ||
11763 | trace_i915_flip_request(intel_crtc->plane, obj); | |
11764 | ||
11765 | return 0; | |
11766 | ||
11767 | cleanup_unpin: | |
11768 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
11769 | cleanup_pending: | |
11770 | if (!IS_ERR_OR_NULL(request)) | |
11771 | i915_add_request_no_flush(request); | |
11772 | atomic_dec(&intel_crtc->unpin_work_count); | |
11773 | mutex_unlock(&dev->struct_mutex); | |
11774 | cleanup: | |
11775 | crtc->primary->fb = old_fb; | |
11776 | update_state_fb(crtc->primary); | |
11777 | ||
11778 | drm_gem_object_unreference_unlocked(&obj->base); | |
11779 | drm_framebuffer_unreference(work->old_fb); | |
11780 | ||
11781 | spin_lock_irq(&dev->event_lock); | |
11782 | intel_crtc->flip_work = NULL; | |
11783 | spin_unlock_irq(&dev->event_lock); | |
11784 | ||
11785 | drm_crtc_vblank_put(crtc); | |
11786 | free_work: | |
11787 | kfree(work); | |
11788 | ||
11789 | if (ret == -EIO) { | |
11790 | struct drm_atomic_state *state; | |
11791 | struct drm_plane_state *plane_state; | |
11792 | ||
11793 | out_hang: | |
11794 | state = drm_atomic_state_alloc(dev); | |
11795 | if (!state) | |
11796 | return -ENOMEM; | |
11797 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11798 | ||
11799 | retry: | |
11800 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11801 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11802 | if (!ret) { | |
11803 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11804 | ||
11805 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11806 | if (!ret) | |
11807 | ret = drm_atomic_commit(state); | |
11808 | } | |
11809 | ||
11810 | if (ret == -EDEADLK) { | |
11811 | drm_modeset_backoff(state->acquire_ctx); | |
11812 | drm_atomic_state_clear(state); | |
11813 | goto retry; | |
11814 | } | |
11815 | ||
11816 | if (ret) | |
11817 | drm_atomic_state_free(state); | |
11818 | ||
11819 | if (ret == 0 && event) { | |
11820 | spin_lock_irq(&dev->event_lock); | |
11821 | drm_crtc_send_vblank_event(crtc, event); | |
11822 | spin_unlock_irq(&dev->event_lock); | |
11823 | } | |
11824 | } | |
11825 | return ret; | |
11826 | } | |
11827 | ||
11828 | ||
11829 | /** | |
11830 | * intel_wm_need_update - Check whether watermarks need updating | |
11831 | * @plane: drm plane | |
11832 | * @state: new plane state | |
11833 | * | |
11834 | * Check current plane state versus the new one to determine whether | |
11835 | * watermarks need to be recalculated. | |
11836 | * | |
11837 | * Returns true or false. | |
11838 | */ | |
11839 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11840 | struct drm_plane_state *state) | |
11841 | { | |
11842 | struct intel_plane_state *new = to_intel_plane_state(state); | |
11843 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11844 | ||
11845 | /* Update watermarks on tiling or size changes. */ | |
11846 | if (new->visible != cur->visible) | |
11847 | return true; | |
11848 | ||
11849 | if (!cur->base.fb || !new->base.fb) | |
11850 | return false; | |
11851 | ||
11852 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11853 | cur->base.rotation != new->base.rotation || | |
11854 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
11855 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11856 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11857 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
11858 | return true; | |
11859 | ||
11860 | return false; | |
11861 | } | |
11862 | ||
11863 | static bool needs_scaling(struct intel_plane_state *state) | |
11864 | { | |
11865 | int src_w = drm_rect_width(&state->src) >> 16; | |
11866 | int src_h = drm_rect_height(&state->src) >> 16; | |
11867 | int dst_w = drm_rect_width(&state->dst); | |
11868 | int dst_h = drm_rect_height(&state->dst); | |
11869 | ||
11870 | return (src_w != dst_w || src_h != dst_h); | |
11871 | } | |
d21fbe87 | 11872 | |
da20eabd ML |
11873 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11874 | struct drm_plane_state *plane_state) | |
11875 | { | |
ab1d3a0e | 11876 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11877 | struct drm_crtc *crtc = crtc_state->crtc; |
11878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11879 | struct drm_plane *plane = plane_state->plane; | |
11880 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11881 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11882 | struct intel_plane_state *old_plane_state = |
11883 | to_intel_plane_state(plane->state); | |
da20eabd ML |
11884 | bool mode_changed = needs_modeset(crtc_state); |
11885 | bool was_crtc_enabled = crtc->state->active; | |
11886 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11887 | bool turn_off, turn_on, visible, was_visible; |
11888 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 11889 | int ret; |
da20eabd | 11890 | |
84114990 | 11891 | if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
11892 | ret = skl_update_scaler_plane( |
11893 | to_intel_crtc_state(crtc_state), | |
11894 | to_intel_plane_state(plane_state)); | |
11895 | if (ret) | |
11896 | return ret; | |
11897 | } | |
11898 | ||
da20eabd ML |
11899 | was_visible = old_plane_state->visible; |
11900 | visible = to_intel_plane_state(plane_state)->visible; | |
11901 | ||
11902 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11903 | was_visible = false; | |
11904 | ||
35c08f43 ML |
11905 | /* |
11906 | * Visibility is calculated as if the crtc was on, but | |
11907 | * after scaler setup everything depends on it being off | |
11908 | * when the crtc isn't active. | |
f818ffea VS |
11909 | * |
11910 | * FIXME this is wrong for watermarks. Watermarks should also | |
11911 | * be computed as if the pipe would be active. Perhaps move | |
11912 | * per-plane wm computation to the .check_plane() hook, and | |
11913 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
11914 | */ |
11915 | if (!is_crtc_enabled) | |
11916 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11917 | |
11918 | if (!was_visible && !visible) | |
11919 | return 0; | |
11920 | ||
e8861675 ML |
11921 | if (fb != old_plane_state->base.fb) |
11922 | pipe_config->fb_changed = true; | |
11923 | ||
da20eabd ML |
11924 | turn_off = was_visible && (!visible || mode_changed); |
11925 | turn_on = visible && (!was_visible || mode_changed); | |
11926 | ||
72660ce0 | 11927 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
11928 | intel_crtc->base.base.id, |
11929 | intel_crtc->base.name, | |
72660ce0 VS |
11930 | plane->base.id, plane->name, |
11931 | fb ? fb->base.id : -1); | |
da20eabd | 11932 | |
72660ce0 VS |
11933 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
11934 | plane->base.id, plane->name, | |
11935 | was_visible, visible, | |
da20eabd ML |
11936 | turn_off, turn_on, mode_changed); |
11937 | ||
caed361d VS |
11938 | if (turn_on) { |
11939 | pipe_config->update_wm_pre = true; | |
11940 | ||
11941 | /* must disable cxsr around plane enable/disable */ | |
11942 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11943 | pipe_config->disable_cxsr = true; | |
11944 | } else if (turn_off) { | |
11945 | pipe_config->update_wm_post = true; | |
92826fcd | 11946 | |
852eb00d | 11947 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11948 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11949 | pipe_config->disable_cxsr = true; |
852eb00d | 11950 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11951 | /* FIXME bollocks */ |
11952 | pipe_config->update_wm_pre = true; | |
11953 | pipe_config->update_wm_post = true; | |
852eb00d | 11954 | } |
da20eabd | 11955 | |
ed4a6a7c | 11956 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11957 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11958 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11959 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11960 | ||
8be6ca85 | 11961 | if (visible || was_visible) |
cd202f69 | 11962 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11963 | |
31ae71fc ML |
11964 | /* |
11965 | * WaCxSRDisabledForSpriteScaling:ivb | |
11966 | * | |
11967 | * cstate->update_wm was already set above, so this flag will | |
11968 | * take effect when we commit and program watermarks. | |
11969 | */ | |
11970 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11971 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11972 | !needs_scaling(old_plane_state)) | |
11973 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11974 | |
da20eabd ML |
11975 | return 0; |
11976 | } | |
11977 | ||
6d3a1ce7 ML |
11978 | static bool encoders_cloneable(const struct intel_encoder *a, |
11979 | const struct intel_encoder *b) | |
11980 | { | |
11981 | /* masks could be asymmetric, so check both ways */ | |
11982 | return a == b || (a->cloneable & (1 << b->type) && | |
11983 | b->cloneable & (1 << a->type)); | |
11984 | } | |
11985 | ||
11986 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11987 | struct intel_crtc *crtc, | |
11988 | struct intel_encoder *encoder) | |
11989 | { | |
11990 | struct intel_encoder *source_encoder; | |
11991 | struct drm_connector *connector; | |
11992 | struct drm_connector_state *connector_state; | |
11993 | int i; | |
11994 | ||
11995 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11996 | if (connector_state->crtc != &crtc->base) | |
11997 | continue; | |
11998 | ||
11999 | source_encoder = | |
12000 | to_intel_encoder(connector_state->best_encoder); | |
12001 | if (!encoders_cloneable(encoder, source_encoder)) | |
12002 | return false; | |
12003 | } | |
12004 | ||
12005 | return true; | |
12006 | } | |
12007 | ||
12008 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
12009 | struct intel_crtc *crtc) | |
12010 | { | |
12011 | struct intel_encoder *encoder; | |
12012 | struct drm_connector *connector; | |
12013 | struct drm_connector_state *connector_state; | |
12014 | int i; | |
12015 | ||
12016 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12017 | if (connector_state->crtc != &crtc->base) | |
12018 | continue; | |
12019 | ||
12020 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12021 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
12022 | return false; | |
12023 | } | |
12024 | ||
12025 | return true; | |
12026 | } | |
12027 | ||
12028 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
12029 | struct drm_crtc_state *crtc_state) | |
12030 | { | |
cf5a15be | 12031 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12032 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12033 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12034 | struct intel_crtc_state *pipe_config = |
12035 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12036 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12037 | int ret; |
6d3a1ce7 ML |
12038 | bool mode_changed = needs_modeset(crtc_state); |
12039 | ||
12040 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12041 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12042 | return -EINVAL; | |
12043 | } | |
12044 | ||
852eb00d | 12045 | if (mode_changed && !crtc_state->active) |
caed361d | 12046 | pipe_config->update_wm_post = true; |
eddfcbcd | 12047 | |
ad421372 ML |
12048 | if (mode_changed && crtc_state->enable && |
12049 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12050 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12051 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12052 | pipe_config); | |
12053 | if (ret) | |
12054 | return ret; | |
12055 | } | |
12056 | ||
82cf435b LL |
12057 | if (crtc_state->color_mgmt_changed) { |
12058 | ret = intel_color_check(crtc, crtc_state); | |
12059 | if (ret) | |
12060 | return ret; | |
12061 | } | |
12062 | ||
e435d6e5 | 12063 | ret = 0; |
86c8bbbe | 12064 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12065 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12066 | if (ret) { |
12067 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12068 | return ret; | |
12069 | } | |
12070 | } | |
12071 | ||
12072 | if (dev_priv->display.compute_intermediate_wm && | |
12073 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12074 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12075 | return 0; | |
12076 | ||
12077 | /* | |
12078 | * Calculate 'intermediate' watermarks that satisfy both the | |
12079 | * old state and the new state. We can program these | |
12080 | * immediately. | |
12081 | */ | |
12082 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12083 | intel_crtc, | |
12084 | pipe_config); | |
12085 | if (ret) { | |
12086 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12087 | return ret; |
ed4a6a7c | 12088 | } |
e3d5457c VS |
12089 | } else if (dev_priv->display.compute_intermediate_wm) { |
12090 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12091 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12092 | } |
12093 | ||
e435d6e5 ML |
12094 | if (INTEL_INFO(dev)->gen >= 9) { |
12095 | if (mode_changed) | |
12096 | ret = skl_update_scaler_crtc(pipe_config); | |
12097 | ||
12098 | if (!ret) | |
12099 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12100 | pipe_config); | |
12101 | } | |
12102 | ||
12103 | return ret; | |
6d3a1ce7 ML |
12104 | } |
12105 | ||
65b38e0d | 12106 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12107 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12108 | .atomic_begin = intel_begin_crtc_commit, |
12109 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12110 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12111 | }; |
12112 | ||
d29b2f9d ACO |
12113 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12114 | { | |
12115 | struct intel_connector *connector; | |
12116 | ||
12117 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12118 | if (connector->base.state->crtc) |
12119 | drm_connector_unreference(&connector->base); | |
12120 | ||
d29b2f9d ACO |
12121 | if (connector->base.encoder) { |
12122 | connector->base.state->best_encoder = | |
12123 | connector->base.encoder; | |
12124 | connector->base.state->crtc = | |
12125 | connector->base.encoder->crtc; | |
8863dc7f DV |
12126 | |
12127 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12128 | } else { |
12129 | connector->base.state->best_encoder = NULL; | |
12130 | connector->base.state->crtc = NULL; | |
12131 | } | |
12132 | } | |
12133 | } | |
12134 | ||
050f7aeb | 12135 | static void |
eba905b2 | 12136 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12137 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12138 | { |
12139 | int bpp = pipe_config->pipe_bpp; | |
12140 | ||
12141 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12142 | connector->base.base.id, | |
c23cc417 | 12143 | connector->base.name); |
050f7aeb DV |
12144 | |
12145 | /* Don't use an invalid EDID bpc value */ | |
12146 | if (connector->base.display_info.bpc && | |
12147 | connector->base.display_info.bpc * 3 < bpp) { | |
12148 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12149 | bpp, connector->base.display_info.bpc*3); | |
12150 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12151 | } | |
12152 | ||
013dd9e0 JN |
12153 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12154 | if (connector->base.display_info.bpc == 0) { | |
12155 | int type = connector->base.connector_type; | |
12156 | int clamp_bpp = 24; | |
12157 | ||
12158 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12159 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12160 | type == DRM_MODE_CONNECTOR_eDP) | |
12161 | clamp_bpp = 18; | |
12162 | ||
12163 | if (bpp > clamp_bpp) { | |
12164 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12165 | bpp, clamp_bpp); | |
12166 | pipe_config->pipe_bpp = clamp_bpp; | |
12167 | } | |
050f7aeb DV |
12168 | } |
12169 | } | |
12170 | ||
4e53c2e0 | 12171 | static int |
050f7aeb | 12172 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12173 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12174 | { |
050f7aeb | 12175 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12176 | struct drm_atomic_state *state; |
da3ced29 ACO |
12177 | struct drm_connector *connector; |
12178 | struct drm_connector_state *connector_state; | |
1486017f | 12179 | int bpp, i; |
4e53c2e0 | 12180 | |
666a4537 | 12181 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12182 | bpp = 10*3; |
d328c9d7 DV |
12183 | else if (INTEL_INFO(dev)->gen >= 5) |
12184 | bpp = 12*3; | |
12185 | else | |
12186 | bpp = 8*3; | |
12187 | ||
4e53c2e0 | 12188 | |
4e53c2e0 DV |
12189 | pipe_config->pipe_bpp = bpp; |
12190 | ||
1486017f ACO |
12191 | state = pipe_config->base.state; |
12192 | ||
4e53c2e0 | 12193 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12194 | for_each_connector_in_state(state, connector, connector_state, i) { |
12195 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12196 | continue; |
12197 | ||
da3ced29 ACO |
12198 | connected_sink_compute_bpp(to_intel_connector(connector), |
12199 | pipe_config); | |
4e53c2e0 DV |
12200 | } |
12201 | ||
12202 | return bpp; | |
12203 | } | |
12204 | ||
644db711 DV |
12205 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12206 | { | |
12207 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12208 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12209 | mode->crtc_clock, |
644db711 DV |
12210 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12211 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12212 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12213 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12214 | } | |
12215 | ||
c0b03411 | 12216 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12217 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12218 | const char *context) |
12219 | { | |
6a60cd87 CK |
12220 | struct drm_device *dev = crtc->base.dev; |
12221 | struct drm_plane *plane; | |
12222 | struct intel_plane *intel_plane; | |
12223 | struct intel_plane_state *state; | |
12224 | struct drm_framebuffer *fb; | |
12225 | ||
78108b7c VS |
12226 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12227 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12228 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12229 | |
da205630 | 12230 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12231 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12232 | pipe_config->pipe_bpp, pipe_config->dither); | |
12233 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12234 | pipe_config->has_pch_encoder, | |
12235 | pipe_config->fdi_lanes, | |
12236 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12237 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12238 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12239 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12240 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12241 | pipe_config->lane_count, |
eb14cb74 VS |
12242 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12243 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12244 | pipe_config->dp_m_n.tu); | |
b95af8be | 12245 | |
90a6b7b0 | 12246 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12247 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12248 | pipe_config->lane_count, |
b95af8be VK |
12249 | pipe_config->dp_m2_n2.gmch_m, |
12250 | pipe_config->dp_m2_n2.gmch_n, | |
12251 | pipe_config->dp_m2_n2.link_m, | |
12252 | pipe_config->dp_m2_n2.link_n, | |
12253 | pipe_config->dp_m2_n2.tu); | |
12254 | ||
55072d19 DV |
12255 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12256 | pipe_config->has_audio, | |
12257 | pipe_config->has_infoframe); | |
12258 | ||
c0b03411 | 12259 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12260 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12261 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12262 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12263 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12264 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12265 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12266 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12267 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12268 | crtc->num_scalers, | |
12269 | pipe_config->scaler_state.scaler_users, | |
12270 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12271 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12272 | pipe_config->gmch_pfit.control, | |
12273 | pipe_config->gmch_pfit.pgm_ratios, | |
12274 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12275 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12276 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12277 | pipe_config->pch_pfit.size, |
12278 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12279 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12280 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12281 | |
415ff0f6 | 12282 | if (IS_BROXTON(dev)) { |
05712c15 | 12283 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12284 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12285 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12286 | pipe_config->ddi_pll_sel, |
12287 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12288 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12289 | pipe_config->dpll_hw_state.pll0, |
12290 | pipe_config->dpll_hw_state.pll1, | |
12291 | pipe_config->dpll_hw_state.pll2, | |
12292 | pipe_config->dpll_hw_state.pll3, | |
12293 | pipe_config->dpll_hw_state.pll6, | |
12294 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12295 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12296 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12297 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12298 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12299 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12300 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12301 | pipe_config->ddi_pll_sel, | |
12302 | pipe_config->dpll_hw_state.ctrl1, | |
12303 | pipe_config->dpll_hw_state.cfgcr1, | |
12304 | pipe_config->dpll_hw_state.cfgcr2); | |
12305 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12306 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12307 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12308 | pipe_config->dpll_hw_state.wrpll, |
12309 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12310 | } else { |
12311 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12312 | "fp0: 0x%x, fp1: 0x%x\n", | |
12313 | pipe_config->dpll_hw_state.dpll, | |
12314 | pipe_config->dpll_hw_state.dpll_md, | |
12315 | pipe_config->dpll_hw_state.fp0, | |
12316 | pipe_config->dpll_hw_state.fp1); | |
12317 | } | |
12318 | ||
6a60cd87 CK |
12319 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12320 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12321 | intel_plane = to_intel_plane(plane); | |
12322 | if (intel_plane->pipe != crtc->pipe) | |
12323 | continue; | |
12324 | ||
12325 | state = to_intel_plane_state(plane->state); | |
12326 | fb = state->base.fb; | |
12327 | if (!fb) { | |
1d577e02 VS |
12328 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12329 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12330 | continue; |
12331 | } | |
12332 | ||
1d577e02 VS |
12333 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12334 | plane->base.id, plane->name); | |
12335 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
12336 | fb->base.id, fb->width, fb->height, | |
12337 | drm_get_format_name(fb->pixel_format)); | |
12338 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12339 | state->scaler_id, | |
12340 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12341 | drm_rect_width(&state->src) >> 16, | |
12342 | drm_rect_height(&state->src) >> 16, | |
12343 | state->dst.x1, state->dst.y1, | |
12344 | drm_rect_width(&state->dst), | |
12345 | drm_rect_height(&state->dst)); | |
6a60cd87 | 12346 | } |
c0b03411 DV |
12347 | } |
12348 | ||
5448a00d | 12349 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12350 | { |
5448a00d | 12351 | struct drm_device *dev = state->dev; |
da3ced29 | 12352 | struct drm_connector *connector; |
00f0b378 VS |
12353 | unsigned int used_ports = 0; |
12354 | ||
12355 | /* | |
12356 | * Walk the connector list instead of the encoder | |
12357 | * list to detect the problem on ddi platforms | |
12358 | * where there's just one encoder per digital port. | |
12359 | */ | |
0bff4858 VS |
12360 | drm_for_each_connector(connector, dev) { |
12361 | struct drm_connector_state *connector_state; | |
12362 | struct intel_encoder *encoder; | |
12363 | ||
12364 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12365 | if (!connector_state) | |
12366 | connector_state = connector->state; | |
12367 | ||
5448a00d | 12368 | if (!connector_state->best_encoder) |
00f0b378 VS |
12369 | continue; |
12370 | ||
5448a00d ACO |
12371 | encoder = to_intel_encoder(connector_state->best_encoder); |
12372 | ||
12373 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12374 | |
12375 | switch (encoder->type) { | |
12376 | unsigned int port_mask; | |
12377 | case INTEL_OUTPUT_UNKNOWN: | |
12378 | if (WARN_ON(!HAS_DDI(dev))) | |
12379 | break; | |
cca0502b | 12380 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12381 | case INTEL_OUTPUT_HDMI: |
12382 | case INTEL_OUTPUT_EDP: | |
12383 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12384 | ||
12385 | /* the same port mustn't appear more than once */ | |
12386 | if (used_ports & port_mask) | |
12387 | return false; | |
12388 | ||
12389 | used_ports |= port_mask; | |
12390 | default: | |
12391 | break; | |
12392 | } | |
12393 | } | |
12394 | ||
12395 | return true; | |
12396 | } | |
12397 | ||
83a57153 ACO |
12398 | static void |
12399 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12400 | { | |
12401 | struct drm_crtc_state tmp_state; | |
663a3640 | 12402 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12403 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12404 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12405 | uint32_t ddi_pll_sel; |
c4e2d043 | 12406 | bool force_thru; |
83a57153 | 12407 | |
7546a384 ACO |
12408 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12409 | * kzalloc'd. Code that depends on any field being zero should be | |
12410 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12411 | * only fields that are know to not cause problems are preserved. */ | |
12412 | ||
83a57153 | 12413 | tmp_state = crtc_state->base; |
663a3640 | 12414 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12415 | shared_dpll = crtc_state->shared_dpll; |
12416 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12417 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12418 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12419 | |
83a57153 | 12420 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12421 | |
83a57153 | 12422 | crtc_state->base = tmp_state; |
663a3640 | 12423 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12424 | crtc_state->shared_dpll = shared_dpll; |
12425 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12426 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12427 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12428 | } |
12429 | ||
548ee15b | 12430 | static int |
b8cecdf5 | 12431 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12432 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12433 | { |
b359283a | 12434 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12435 | struct intel_encoder *encoder; |
da3ced29 | 12436 | struct drm_connector *connector; |
0b901879 | 12437 | struct drm_connector_state *connector_state; |
d328c9d7 | 12438 | int base_bpp, ret = -EINVAL; |
0b901879 | 12439 | int i; |
e29c22c0 | 12440 | bool retry = true; |
ee7b9f93 | 12441 | |
83a57153 | 12442 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12443 | |
e143a21c DV |
12444 | pipe_config->cpu_transcoder = |
12445 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12446 | |
2960bc9c ID |
12447 | /* |
12448 | * Sanitize sync polarity flags based on requested ones. If neither | |
12449 | * positive or negative polarity is requested, treat this as meaning | |
12450 | * negative polarity. | |
12451 | */ | |
2d112de7 | 12452 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12453 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12454 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12455 | |
2d112de7 | 12456 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12457 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12458 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12459 | |
d328c9d7 DV |
12460 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12461 | pipe_config); | |
12462 | if (base_bpp < 0) | |
4e53c2e0 DV |
12463 | goto fail; |
12464 | ||
e41a56be VS |
12465 | /* |
12466 | * Determine the real pipe dimensions. Note that stereo modes can | |
12467 | * increase the actual pipe size due to the frame doubling and | |
12468 | * insertion of additional space for blanks between the frame. This | |
12469 | * is stored in the crtc timings. We use the requested mode to do this | |
12470 | * computation to clearly distinguish it from the adjusted mode, which | |
12471 | * can be changed by the connectors in the below retry loop. | |
12472 | */ | |
2d112de7 | 12473 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12474 | &pipe_config->pipe_src_w, |
12475 | &pipe_config->pipe_src_h); | |
e41a56be | 12476 | |
253c84c8 VS |
12477 | for_each_connector_in_state(state, connector, connector_state, i) { |
12478 | if (connector_state->crtc != crtc) | |
12479 | continue; | |
12480 | ||
12481 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12482 | ||
12483 | /* | |
12484 | * Determine output_types before calling the .compute_config() | |
12485 | * hooks so that the hooks can use this information safely. | |
12486 | */ | |
12487 | pipe_config->output_types |= 1 << encoder->type; | |
12488 | } | |
12489 | ||
e29c22c0 | 12490 | encoder_retry: |
ef1b460d | 12491 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12492 | pipe_config->port_clock = 0; |
ef1b460d | 12493 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12494 | |
135c81b8 | 12495 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12496 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12497 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12498 | |
7758a113 DV |
12499 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12500 | * adjust it according to limitations or connector properties, and also | |
12501 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12502 | */ |
da3ced29 | 12503 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12504 | if (connector_state->crtc != crtc) |
7758a113 | 12505 | continue; |
7ae89233 | 12506 | |
0b901879 ACO |
12507 | encoder = to_intel_encoder(connector_state->best_encoder); |
12508 | ||
efea6e8e DV |
12509 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12510 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12511 | goto fail; |
12512 | } | |
ee7b9f93 | 12513 | } |
47f1c6c9 | 12514 | |
ff9a6750 DV |
12515 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12516 | * done afterwards in case the encoder adjusts the mode. */ | |
12517 | if (!pipe_config->port_clock) | |
2d112de7 | 12518 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12519 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12520 | |
a43f6e0f | 12521 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12522 | if (ret < 0) { |
7758a113 DV |
12523 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12524 | goto fail; | |
ee7b9f93 | 12525 | } |
e29c22c0 DV |
12526 | |
12527 | if (ret == RETRY) { | |
12528 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12529 | ret = -EINVAL; | |
12530 | goto fail; | |
12531 | } | |
12532 | ||
12533 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12534 | retry = false; | |
12535 | goto encoder_retry; | |
12536 | } | |
12537 | ||
e8fa4270 DV |
12538 | /* Dithering seems to not pass-through bits correctly when it should, so |
12539 | * only enable it on 6bpc panels. */ | |
12540 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12541 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12542 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12543 | |
7758a113 | 12544 | fail: |
548ee15b | 12545 | return ret; |
ee7b9f93 | 12546 | } |
47f1c6c9 | 12547 | |
ea9d758d | 12548 | static void |
4740b0f2 | 12549 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12550 | { |
0a9ab303 ACO |
12551 | struct drm_crtc *crtc; |
12552 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12553 | int i; |
ea9d758d | 12554 | |
7668851f | 12555 | /* Double check state. */ |
8a75d157 | 12556 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12557 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12558 | |
12559 | /* Update hwmode for vblank functions */ | |
12560 | if (crtc->state->active) | |
12561 | crtc->hwmode = crtc->state->adjusted_mode; | |
12562 | else | |
12563 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12564 | |
12565 | /* | |
12566 | * Update legacy state to satisfy fbc code. This can | |
12567 | * be removed when fbc uses the atomic state. | |
12568 | */ | |
12569 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12570 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12571 | ||
12572 | crtc->primary->fb = plane_state->fb; | |
12573 | crtc->x = plane_state->src_x >> 16; | |
12574 | crtc->y = plane_state->src_y >> 16; | |
12575 | } | |
ea9d758d | 12576 | } |
ea9d758d DV |
12577 | } |
12578 | ||
3bd26263 | 12579 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12580 | { |
3bd26263 | 12581 | int diff; |
f1f644dc JB |
12582 | |
12583 | if (clock1 == clock2) | |
12584 | return true; | |
12585 | ||
12586 | if (!clock1 || !clock2) | |
12587 | return false; | |
12588 | ||
12589 | diff = abs(clock1 - clock2); | |
12590 | ||
12591 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12592 | return true; | |
12593 | ||
12594 | return false; | |
12595 | } | |
12596 | ||
25c5b266 DV |
12597 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12598 | list_for_each_entry((intel_crtc), \ | |
12599 | &(dev)->mode_config.crtc_list, \ | |
12600 | base.head) \ | |
95150bdf | 12601 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12602 | |
cfb23ed6 ML |
12603 | static bool |
12604 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12605 | unsigned int m2, unsigned int n2, | |
12606 | bool exact) | |
12607 | { | |
12608 | if (m == m2 && n == n2) | |
12609 | return true; | |
12610 | ||
12611 | if (exact || !m || !n || !m2 || !n2) | |
12612 | return false; | |
12613 | ||
12614 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12615 | ||
31d10b57 ML |
12616 | if (n > n2) { |
12617 | while (n > n2) { | |
cfb23ed6 ML |
12618 | m2 <<= 1; |
12619 | n2 <<= 1; | |
12620 | } | |
31d10b57 ML |
12621 | } else if (n < n2) { |
12622 | while (n < n2) { | |
cfb23ed6 ML |
12623 | m <<= 1; |
12624 | n <<= 1; | |
12625 | } | |
12626 | } | |
12627 | ||
31d10b57 ML |
12628 | if (n != n2) |
12629 | return false; | |
12630 | ||
12631 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12632 | } |
12633 | ||
12634 | static bool | |
12635 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12636 | struct intel_link_m_n *m2_n2, | |
12637 | bool adjust) | |
12638 | { | |
12639 | if (m_n->tu == m2_n2->tu && | |
12640 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12641 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12642 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12643 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12644 | if (adjust) | |
12645 | *m2_n2 = *m_n; | |
12646 | ||
12647 | return true; | |
12648 | } | |
12649 | ||
12650 | return false; | |
12651 | } | |
12652 | ||
0e8ffe1b | 12653 | static bool |
2fa2fe9a | 12654 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12655 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12656 | struct intel_crtc_state *pipe_config, |
12657 | bool adjust) | |
0e8ffe1b | 12658 | { |
cfb23ed6 ML |
12659 | bool ret = true; |
12660 | ||
12661 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12662 | do { \ | |
12663 | if (!adjust) \ | |
12664 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12665 | else \ | |
12666 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12667 | } while (0) | |
12668 | ||
66e985c0 DV |
12669 | #define PIPE_CONF_CHECK_X(name) \ |
12670 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12671 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12672 | "(expected 0x%08x, found 0x%08x)\n", \ |
12673 | current_config->name, \ | |
12674 | pipe_config->name); \ | |
cfb23ed6 | 12675 | ret = false; \ |
66e985c0 DV |
12676 | } |
12677 | ||
08a24034 DV |
12678 | #define PIPE_CONF_CHECK_I(name) \ |
12679 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12680 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12681 | "(expected %i, found %i)\n", \ |
12682 | current_config->name, \ | |
12683 | pipe_config->name); \ | |
cfb23ed6 ML |
12684 | ret = false; \ |
12685 | } | |
12686 | ||
8106ddbd ACO |
12687 | #define PIPE_CONF_CHECK_P(name) \ |
12688 | if (current_config->name != pipe_config->name) { \ | |
12689 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12690 | "(expected %p, found %p)\n", \ | |
12691 | current_config->name, \ | |
12692 | pipe_config->name); \ | |
12693 | ret = false; \ | |
12694 | } | |
12695 | ||
cfb23ed6 ML |
12696 | #define PIPE_CONF_CHECK_M_N(name) \ |
12697 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12698 | &pipe_config->name,\ | |
12699 | adjust)) { \ | |
12700 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12701 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12702 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12703 | current_config->name.tu, \ | |
12704 | current_config->name.gmch_m, \ | |
12705 | current_config->name.gmch_n, \ | |
12706 | current_config->name.link_m, \ | |
12707 | current_config->name.link_n, \ | |
12708 | pipe_config->name.tu, \ | |
12709 | pipe_config->name.gmch_m, \ | |
12710 | pipe_config->name.gmch_n, \ | |
12711 | pipe_config->name.link_m, \ | |
12712 | pipe_config->name.link_n); \ | |
12713 | ret = false; \ | |
12714 | } | |
12715 | ||
55c561a7 DV |
12716 | /* This is required for BDW+ where there is only one set of registers for |
12717 | * switching between high and low RR. | |
12718 | * This macro can be used whenever a comparison has to be made between one | |
12719 | * hw state and multiple sw state variables. | |
12720 | */ | |
cfb23ed6 ML |
12721 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12722 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12723 | &pipe_config->name, adjust) && \ | |
12724 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12725 | &pipe_config->name, adjust)) { \ | |
12726 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12727 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12728 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12729 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12730 | current_config->name.tu, \ | |
12731 | current_config->name.gmch_m, \ | |
12732 | current_config->name.gmch_n, \ | |
12733 | current_config->name.link_m, \ | |
12734 | current_config->name.link_n, \ | |
12735 | current_config->alt_name.tu, \ | |
12736 | current_config->alt_name.gmch_m, \ | |
12737 | current_config->alt_name.gmch_n, \ | |
12738 | current_config->alt_name.link_m, \ | |
12739 | current_config->alt_name.link_n, \ | |
12740 | pipe_config->name.tu, \ | |
12741 | pipe_config->name.gmch_m, \ | |
12742 | pipe_config->name.gmch_n, \ | |
12743 | pipe_config->name.link_m, \ | |
12744 | pipe_config->name.link_n); \ | |
12745 | ret = false; \ | |
88adfff1 DV |
12746 | } |
12747 | ||
1bd1bd80 DV |
12748 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12749 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12750 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12751 | "(expected %i, found %i)\n", \ |
12752 | current_config->name & (mask), \ | |
12753 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12754 | ret = false; \ |
1bd1bd80 DV |
12755 | } |
12756 | ||
5e550656 VS |
12757 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12758 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12759 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12760 | "(expected %i, found %i)\n", \ |
12761 | current_config->name, \ | |
12762 | pipe_config->name); \ | |
cfb23ed6 | 12763 | ret = false; \ |
5e550656 VS |
12764 | } |
12765 | ||
bb760063 DV |
12766 | #define PIPE_CONF_QUIRK(quirk) \ |
12767 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12768 | ||
eccb140b DV |
12769 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12770 | ||
08a24034 DV |
12771 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12772 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12773 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12774 | |
90a6b7b0 | 12775 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 12776 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
12777 | |
12778 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12779 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12780 | ||
cfb23ed6 ML |
12781 | if (current_config->has_drrs) |
12782 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12783 | } else | |
12784 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12785 | |
a65347ba | 12786 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
253c84c8 | 12787 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 12788 | |
2d112de7 ACO |
12789 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12790 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12791 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12792 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12793 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12794 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12795 | |
2d112de7 ACO |
12796 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12797 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12798 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12799 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12800 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12801 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12802 | |
c93f54cf | 12803 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12804 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12805 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12806 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12807 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12808 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12809 | |
9ed109a7 DV |
12810 | PIPE_CONF_CHECK_I(has_audio); |
12811 | ||
2d112de7 | 12812 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12813 | DRM_MODE_FLAG_INTERLACE); |
12814 | ||
bb760063 | 12815 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12816 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12817 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12818 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12819 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12820 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12821 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12822 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12823 | DRM_MODE_FLAG_NVSYNC); |
12824 | } | |
045ac3b5 | 12825 | |
333b8ca8 | 12826 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12827 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12828 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12829 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12830 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12831 | |
bfd16b2a ML |
12832 | if (!adjust) { |
12833 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12834 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12835 | ||
12836 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12837 | if (current_config->pch_pfit.enabled) { | |
12838 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12839 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12840 | } | |
2fa2fe9a | 12841 | |
7aefe2b5 ML |
12842 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12843 | } | |
a1b2278e | 12844 | |
e59150dc JB |
12845 | /* BDW+ don't expose a synchronous way to read the state */ |
12846 | if (IS_HASWELL(dev)) | |
12847 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12848 | |
282740f7 VS |
12849 | PIPE_CONF_CHECK_I(double_wide); |
12850 | ||
26804afd DV |
12851 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12852 | ||
8106ddbd | 12853 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12854 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12855 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12856 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12857 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12858 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12859 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12860 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12861 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12862 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12863 | |
47eacbab VS |
12864 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
12865 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12866 | ||
42571aef VS |
12867 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12868 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12869 | ||
2d112de7 | 12870 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12871 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12872 | |
66e985c0 | 12873 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12874 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12875 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12876 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12877 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12878 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12879 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12880 | |
cfb23ed6 | 12881 | return ret; |
0e8ffe1b DV |
12882 | } |
12883 | ||
e3b247da VS |
12884 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12885 | const struct intel_crtc_state *pipe_config) | |
12886 | { | |
12887 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12888 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12889 | &pipe_config->fdi_m_n); |
12890 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12891 | ||
12892 | /* | |
12893 | * FDI already provided one idea for the dotclock. | |
12894 | * Yell if the encoder disagrees. | |
12895 | */ | |
12896 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12897 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12898 | fdi_dotclock, dotclock); | |
12899 | } | |
12900 | } | |
12901 | ||
c0ead703 ML |
12902 | static void verify_wm_state(struct drm_crtc *crtc, |
12903 | struct drm_crtc_state *new_state) | |
08db6652 | 12904 | { |
e7c84544 | 12905 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12906 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 12907 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
e7c84544 ML |
12908 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12910 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12911 | int plane; |
12912 | ||
e7c84544 | 12913 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12914 | return; |
12915 | ||
12916 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12917 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12918 | ||
e7c84544 ML |
12919 | /* planes */ |
12920 | for_each_plane(dev_priv, pipe, plane) { | |
12921 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12922 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12923 | |
e7c84544 | 12924 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12925 | continue; |
12926 | ||
e7c84544 ML |
12927 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12928 | "(expected (%u,%u), found (%u,%u))\n", | |
12929 | pipe_name(pipe), plane + 1, | |
12930 | sw_entry->start, sw_entry->end, | |
12931 | hw_entry->start, hw_entry->end); | |
12932 | } | |
08db6652 | 12933 | |
e7c84544 ML |
12934 | /* cursor */ |
12935 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12936 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 12937 | |
e7c84544 | 12938 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
12939 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
12940 | "(expected (%u,%u), found (%u,%u))\n", | |
12941 | pipe_name(pipe), | |
12942 | sw_entry->start, sw_entry->end, | |
12943 | hw_entry->start, hw_entry->end); | |
12944 | } | |
12945 | } | |
12946 | ||
91d1b4bd | 12947 | static void |
c0ead703 | 12948 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 12949 | { |
35dd3c64 | 12950 | struct drm_connector *connector; |
8af6cf88 | 12951 | |
e7c84544 | 12952 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
12953 | struct drm_encoder *encoder = connector->encoder; |
12954 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12955 | |
e7c84544 ML |
12956 | if (state->crtc != crtc) |
12957 | continue; | |
12958 | ||
5a21b665 | 12959 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 12960 | |
ad3c558f | 12961 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12962 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12963 | } |
91d1b4bd DV |
12964 | } |
12965 | ||
12966 | static void | |
c0ead703 | 12967 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
12968 | { |
12969 | struct intel_encoder *encoder; | |
12970 | struct intel_connector *connector; | |
8af6cf88 | 12971 | |
b2784e15 | 12972 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12973 | bool enabled = false; |
4d20cd86 | 12974 | enum pipe pipe; |
8af6cf88 DV |
12975 | |
12976 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12977 | encoder->base.base.id, | |
8e329a03 | 12978 | encoder->base.name); |
8af6cf88 | 12979 | |
3a3371ff | 12980 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12981 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12982 | continue; |
12983 | enabled = true; | |
ad3c558f ML |
12984 | |
12985 | I915_STATE_WARN(connector->base.state->crtc != | |
12986 | encoder->base.crtc, | |
12987 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12988 | } |
0e32b39c | 12989 | |
e2c719b7 | 12990 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12991 | "encoder's enabled state mismatch " |
12992 | "(expected %i, found %i)\n", | |
12993 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12994 | |
12995 | if (!encoder->base.crtc) { | |
4d20cd86 | 12996 | bool active; |
7c60d198 | 12997 | |
4d20cd86 ML |
12998 | active = encoder->get_hw_state(encoder, &pipe); |
12999 | I915_STATE_WARN(active, | |
13000 | "encoder detached but still enabled on pipe %c.\n", | |
13001 | pipe_name(pipe)); | |
7c60d198 | 13002 | } |
8af6cf88 | 13003 | } |
91d1b4bd DV |
13004 | } |
13005 | ||
13006 | static void | |
c0ead703 ML |
13007 | verify_crtc_state(struct drm_crtc *crtc, |
13008 | struct drm_crtc_state *old_crtc_state, | |
13009 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13010 | { |
e7c84544 | 13011 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13012 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13013 | struct intel_encoder *encoder; |
e7c84544 ML |
13014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13015 | struct intel_crtc_state *pipe_config, *sw_config; | |
13016 | struct drm_atomic_state *old_state; | |
13017 | bool active; | |
045ac3b5 | 13018 | |
e7c84544 | 13019 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13020 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13021 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13022 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13023 | pipe_config->base.crtc = crtc; | |
13024 | pipe_config->base.state = old_state; | |
8af6cf88 | 13025 | |
78108b7c | 13026 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13027 | |
e7c84544 | 13028 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13029 | |
e7c84544 ML |
13030 | /* hw state is inconsistent with the pipe quirk */ |
13031 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13032 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13033 | active = new_crtc_state->active; | |
6c49f241 | 13034 | |
e7c84544 ML |
13035 | I915_STATE_WARN(new_crtc_state->active != active, |
13036 | "crtc active state doesn't match with hw state " | |
13037 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13038 | |
e7c84544 ML |
13039 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13040 | "transitional active state does not match atomic hw state " | |
13041 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13042 | |
e7c84544 ML |
13043 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13044 | enum pipe pipe; | |
4d20cd86 | 13045 | |
e7c84544 ML |
13046 | active = encoder->get_hw_state(encoder, &pipe); |
13047 | I915_STATE_WARN(active != new_crtc_state->active, | |
13048 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13049 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13050 | |
e7c84544 ML |
13051 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13052 | "Encoder connected to wrong pipe %c\n", | |
13053 | pipe_name(pipe)); | |
4d20cd86 | 13054 | |
253c84c8 VS |
13055 | if (active) { |
13056 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13057 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13058 | } |
e7c84544 | 13059 | } |
53d9f4e9 | 13060 | |
e7c84544 ML |
13061 | if (!new_crtc_state->active) |
13062 | return; | |
cfb23ed6 | 13063 | |
e7c84544 | 13064 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13065 | |
e7c84544 ML |
13066 | sw_config = to_intel_crtc_state(crtc->state); |
13067 | if (!intel_pipe_config_compare(dev, sw_config, | |
13068 | pipe_config, false)) { | |
13069 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13070 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13071 | "[hw state]"); | |
13072 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13073 | "[sw state]"); | |
8af6cf88 DV |
13074 | } |
13075 | } | |
13076 | ||
91d1b4bd | 13077 | static void |
c0ead703 ML |
13078 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13079 | struct intel_shared_dpll *pll, | |
13080 | struct drm_crtc *crtc, | |
13081 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13082 | { |
91d1b4bd | 13083 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13084 | unsigned crtc_mask; |
13085 | bool active; | |
5358901f | 13086 | |
e7c84544 | 13087 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13088 | |
e7c84544 | 13089 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13090 | |
e7c84544 | 13091 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13092 | |
e7c84544 ML |
13093 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13094 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13095 | "pll in active use but not on in sw tracking\n"); | |
13096 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13097 | "pll is on but not used by any active crtc\n"); | |
13098 | I915_STATE_WARN(pll->on != active, | |
13099 | "pll on state mismatch (expected %i, found %i)\n", | |
13100 | pll->on, active); | |
13101 | } | |
5358901f | 13102 | |
e7c84544 | 13103 | if (!crtc) { |
2dd66ebd | 13104 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13105 | "more active pll users than references: %x vs %x\n", |
13106 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13107 | |
e7c84544 ML |
13108 | return; |
13109 | } | |
13110 | ||
13111 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13112 | ||
13113 | if (new_state->active) | |
13114 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13115 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13116 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13117 | else | |
13118 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13119 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13120 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13121 | |
e7c84544 ML |
13122 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13123 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13124 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13125 | |
e7c84544 ML |
13126 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13127 | &dpll_hw_state, | |
13128 | sizeof(dpll_hw_state)), | |
13129 | "pll hw state mismatch\n"); | |
13130 | } | |
13131 | ||
13132 | static void | |
c0ead703 ML |
13133 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13134 | struct drm_crtc_state *old_crtc_state, | |
13135 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13136 | { |
fac5e23e | 13137 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13138 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13139 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13140 | ||
13141 | if (new_state->shared_dpll) | |
c0ead703 | 13142 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13143 | |
13144 | if (old_state->shared_dpll && | |
13145 | old_state->shared_dpll != new_state->shared_dpll) { | |
13146 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13147 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13148 | ||
13149 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13150 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13151 | pipe_name(drm_crtc_index(crtc))); | |
13152 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13153 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13154 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13155 | } |
8af6cf88 DV |
13156 | } |
13157 | ||
e7c84544 | 13158 | static void |
c0ead703 | 13159 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13160 | struct drm_crtc_state *old_state, |
13161 | struct drm_crtc_state *new_state) | |
13162 | { | |
5a21b665 DV |
13163 | if (!needs_modeset(new_state) && |
13164 | !to_intel_crtc_state(new_state)->update_pipe) | |
13165 | return; | |
13166 | ||
c0ead703 | 13167 | verify_wm_state(crtc, new_state); |
5a21b665 | 13168 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13169 | verify_crtc_state(crtc, old_state, new_state); |
13170 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13171 | } |
13172 | ||
13173 | static void | |
c0ead703 | 13174 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13175 | { |
fac5e23e | 13176 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13177 | int i; |
13178 | ||
13179 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13180 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13181 | } |
13182 | ||
13183 | static void | |
c0ead703 | 13184 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13185 | { |
c0ead703 ML |
13186 | verify_encoder_state(dev); |
13187 | verify_connector_state(dev, NULL); | |
13188 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13189 | } |
13190 | ||
80715b2f VS |
13191 | static void update_scanline_offset(struct intel_crtc *crtc) |
13192 | { | |
13193 | struct drm_device *dev = crtc->base.dev; | |
13194 | ||
13195 | /* | |
13196 | * The scanline counter increments at the leading edge of hsync. | |
13197 | * | |
13198 | * On most platforms it starts counting from vtotal-1 on the | |
13199 | * first active line. That means the scanline counter value is | |
13200 | * always one less than what we would expect. Ie. just after | |
13201 | * start of vblank, which also occurs at start of hsync (on the | |
13202 | * last active line), the scanline counter will read vblank_start-1. | |
13203 | * | |
13204 | * On gen2 the scanline counter starts counting from 1 instead | |
13205 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13206 | * to keep the value positive), instead of adding one. | |
13207 | * | |
13208 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13209 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13210 | * there's an extra 1 line difference. So we need to add two instead of | |
13211 | * one to the value. | |
13212 | */ | |
13213 | if (IS_GEN2(dev)) { | |
124abe07 | 13214 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13215 | int vtotal; |
13216 | ||
124abe07 VS |
13217 | vtotal = adjusted_mode->crtc_vtotal; |
13218 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13219 | vtotal /= 2; |
13220 | ||
13221 | crtc->scanline_offset = vtotal - 1; | |
13222 | } else if (HAS_DDI(dev) && | |
2d84d2b3 | 13223 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13224 | crtc->scanline_offset = 2; |
13225 | } else | |
13226 | crtc->scanline_offset = 1; | |
13227 | } | |
13228 | ||
ad421372 | 13229 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13230 | { |
225da59b | 13231 | struct drm_device *dev = state->dev; |
ed6739ef | 13232 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13233 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13234 | struct drm_crtc *crtc; |
13235 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13236 | int i; |
ed6739ef ACO |
13237 | |
13238 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13239 | return; |
ed6739ef | 13240 | |
0a9ab303 | 13241 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13243 | struct intel_shared_dpll *old_dpll = |
13244 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13245 | |
fb1a38a9 | 13246 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13247 | continue; |
13248 | ||
8106ddbd | 13249 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13250 | |
8106ddbd | 13251 | if (!old_dpll) |
fb1a38a9 | 13252 | continue; |
0a9ab303 | 13253 | |
ad421372 ML |
13254 | if (!shared_dpll) |
13255 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13256 | |
8106ddbd | 13257 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13258 | } |
ed6739ef ACO |
13259 | } |
13260 | ||
99d736a2 ML |
13261 | /* |
13262 | * This implements the workaround described in the "notes" section of the mode | |
13263 | * set sequence documentation. When going from no pipes or single pipe to | |
13264 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13265 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13266 | */ | |
13267 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13268 | { | |
13269 | struct drm_crtc_state *crtc_state; | |
13270 | struct intel_crtc *intel_crtc; | |
13271 | struct drm_crtc *crtc; | |
13272 | struct intel_crtc_state *first_crtc_state = NULL; | |
13273 | struct intel_crtc_state *other_crtc_state = NULL; | |
13274 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13275 | int i; | |
13276 | ||
13277 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13278 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13279 | intel_crtc = to_intel_crtc(crtc); | |
13280 | ||
13281 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13282 | continue; | |
13283 | ||
13284 | if (first_crtc_state) { | |
13285 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13286 | break; | |
13287 | } else { | |
13288 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13289 | first_pipe = intel_crtc->pipe; | |
13290 | } | |
13291 | } | |
13292 | ||
13293 | /* No workaround needed? */ | |
13294 | if (!first_crtc_state) | |
13295 | return 0; | |
13296 | ||
13297 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13298 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13299 | struct intel_crtc_state *pipe_config; | |
13300 | ||
13301 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13302 | if (IS_ERR(pipe_config)) | |
13303 | return PTR_ERR(pipe_config); | |
13304 | ||
13305 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13306 | ||
13307 | if (!pipe_config->base.active || | |
13308 | needs_modeset(&pipe_config->base)) | |
13309 | continue; | |
13310 | ||
13311 | /* 2 or more enabled crtcs means no need for w/a */ | |
13312 | if (enabled_pipe != INVALID_PIPE) | |
13313 | return 0; | |
13314 | ||
13315 | enabled_pipe = intel_crtc->pipe; | |
13316 | } | |
13317 | ||
13318 | if (enabled_pipe != INVALID_PIPE) | |
13319 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13320 | else if (other_crtc_state) | |
13321 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13322 | ||
13323 | return 0; | |
13324 | } | |
13325 | ||
27c329ed ML |
13326 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13327 | { | |
13328 | struct drm_crtc *crtc; | |
13329 | struct drm_crtc_state *crtc_state; | |
13330 | int ret = 0; | |
13331 | ||
13332 | /* add all active pipes to the state */ | |
13333 | for_each_crtc(state->dev, crtc) { | |
13334 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13335 | if (IS_ERR(crtc_state)) | |
13336 | return PTR_ERR(crtc_state); | |
13337 | ||
13338 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13339 | continue; | |
13340 | ||
13341 | crtc_state->mode_changed = true; | |
13342 | ||
13343 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13344 | if (ret) | |
13345 | break; | |
13346 | ||
13347 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13348 | if (ret) | |
13349 | break; | |
13350 | } | |
13351 | ||
13352 | return ret; | |
13353 | } | |
13354 | ||
c347a676 | 13355 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13356 | { |
565602d7 | 13357 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13358 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13359 | struct drm_crtc *crtc; |
13360 | struct drm_crtc_state *crtc_state; | |
13361 | int ret = 0, i; | |
054518dd | 13362 | |
b359283a ML |
13363 | if (!check_digital_port_conflicts(state)) { |
13364 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13365 | return -EINVAL; | |
13366 | } | |
13367 | ||
565602d7 ML |
13368 | intel_state->modeset = true; |
13369 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13370 | ||
13371 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13372 | if (crtc_state->active) | |
13373 | intel_state->active_crtcs |= 1 << i; | |
13374 | else | |
13375 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13376 | |
13377 | if (crtc_state->active != crtc->state->active) | |
13378 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13379 | } |
13380 | ||
054518dd ACO |
13381 | /* |
13382 | * See if the config requires any additional preparation, e.g. | |
13383 | * to adjust global state with pipes off. We need to do this | |
13384 | * here so we can get the modeset_pipe updated config for the new | |
13385 | * mode set on this crtc. For other crtcs we need to use the | |
13386 | * adjusted_mode bits in the crtc directly. | |
13387 | */ | |
27c329ed | 13388 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13389 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13390 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13391 | if (!intel_state->cdclk_pll_vco) |
13392 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13393 | |
27c329ed | 13394 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13395 | if (ret < 0) |
13396 | return ret; | |
27c329ed | 13397 | |
c89e39f3 | 13398 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13399 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
13400 | ret = intel_modeset_all_pipes(state); |
13401 | ||
13402 | if (ret < 0) | |
054518dd | 13403 | return ret; |
e8788cbc ML |
13404 | |
13405 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13406 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13407 | } else |
1a617b77 | 13408 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13409 | |
ad421372 | 13410 | intel_modeset_clear_plls(state); |
054518dd | 13411 | |
565602d7 | 13412 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13413 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13414 | |
ad421372 | 13415 | return 0; |
c347a676 ACO |
13416 | } |
13417 | ||
aa363136 MR |
13418 | /* |
13419 | * Handle calculation of various watermark data at the end of the atomic check | |
13420 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13421 | * handlers to ensure that all derived state has been updated. | |
13422 | */ | |
55994c2c | 13423 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13424 | { |
13425 | struct drm_device *dev = state->dev; | |
98d39494 | 13426 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13427 | |
13428 | /* Is there platform-specific watermark information to calculate? */ | |
13429 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13430 | return dev_priv->display.compute_global_watermarks(state); |
13431 | ||
13432 | return 0; | |
aa363136 MR |
13433 | } |
13434 | ||
74c090b1 ML |
13435 | /** |
13436 | * intel_atomic_check - validate state object | |
13437 | * @dev: drm device | |
13438 | * @state: state to validate | |
13439 | */ | |
13440 | static int intel_atomic_check(struct drm_device *dev, | |
13441 | struct drm_atomic_state *state) | |
c347a676 | 13442 | { |
dd8b3bdb | 13443 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13444 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13445 | struct drm_crtc *crtc; |
13446 | struct drm_crtc_state *crtc_state; | |
13447 | int ret, i; | |
61333b60 | 13448 | bool any_ms = false; |
c347a676 | 13449 | |
74c090b1 | 13450 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13451 | if (ret) |
13452 | return ret; | |
13453 | ||
c347a676 | 13454 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13455 | struct intel_crtc_state *pipe_config = |
13456 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13457 | |
13458 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13459 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13460 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13461 | |
af4a879e | 13462 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13463 | continue; |
13464 | ||
af4a879e DV |
13465 | if (!crtc_state->enable) { |
13466 | any_ms = true; | |
cfb23ed6 | 13467 | continue; |
af4a879e | 13468 | } |
cfb23ed6 | 13469 | |
26495481 DV |
13470 | /* FIXME: For only active_changed we shouldn't need to do any |
13471 | * state recomputation at all. */ | |
13472 | ||
1ed51de9 DV |
13473 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13474 | if (ret) | |
13475 | return ret; | |
b359283a | 13476 | |
cfb23ed6 | 13477 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13478 | if (ret) { |
13479 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13480 | pipe_config, "[failed]"); | |
c347a676 | 13481 | return ret; |
25aa1c39 | 13482 | } |
c347a676 | 13483 | |
73831236 | 13484 | if (i915.fastboot && |
dd8b3bdb | 13485 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13486 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13487 | pipe_config, true)) { |
26495481 | 13488 | crtc_state->mode_changed = false; |
bfd16b2a | 13489 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13490 | } |
13491 | ||
af4a879e | 13492 | if (needs_modeset(crtc_state)) |
26495481 | 13493 | any_ms = true; |
cfb23ed6 | 13494 | |
af4a879e DV |
13495 | ret = drm_atomic_add_affected_planes(state, crtc); |
13496 | if (ret) | |
13497 | return ret; | |
61333b60 | 13498 | |
26495481 DV |
13499 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13500 | needs_modeset(crtc_state) ? | |
13501 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13502 | } |
13503 | ||
61333b60 ML |
13504 | if (any_ms) { |
13505 | ret = intel_modeset_checks(state); | |
13506 | ||
13507 | if (ret) | |
13508 | return ret; | |
27c329ed | 13509 | } else |
dd8b3bdb | 13510 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13511 | |
dd8b3bdb | 13512 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13513 | if (ret) |
13514 | return ret; | |
13515 | ||
f51be2e0 | 13516 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13517 | return calc_watermark_data(state); |
054518dd ACO |
13518 | } |
13519 | ||
5008e874 ML |
13520 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13521 | struct drm_atomic_state *state, | |
81072bfd | 13522 | bool nonblock) |
5008e874 | 13523 | { |
fac5e23e | 13524 | struct drm_i915_private *dev_priv = to_i915(dev); |
7580d774 | 13525 | struct drm_plane_state *plane_state; |
5008e874 | 13526 | struct drm_crtc_state *crtc_state; |
7580d774 | 13527 | struct drm_plane *plane; |
5008e874 ML |
13528 | struct drm_crtc *crtc; |
13529 | int i, ret; | |
13530 | ||
5a21b665 DV |
13531 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13532 | if (state->legacy_cursor_update) | |
a6747b73 ML |
13533 | continue; |
13534 | ||
5a21b665 DV |
13535 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13536 | if (ret) | |
13537 | return ret; | |
5008e874 | 13538 | |
5a21b665 DV |
13539 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
13540 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
13541 | } |
13542 | ||
f935675f ML |
13543 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13544 | if (ret) | |
13545 | return ret; | |
13546 | ||
5008e874 | 13547 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13548 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13549 | |
21daaeee | 13550 | if (!ret && !nonblock) { |
7580d774 ML |
13551 | for_each_plane_in_state(state, plane, plane_state, i) { |
13552 | struct intel_plane_state *intel_plane_state = | |
13553 | to_intel_plane_state(plane_state); | |
13554 | ||
13555 | if (!intel_plane_state->wait_req) | |
13556 | continue; | |
13557 | ||
13558 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
299259a3 | 13559 | true, NULL, NULL); |
f7e5838b | 13560 | if (ret) { |
f4457ae7 CW |
13561 | /* Any hang should be swallowed by the wait */ |
13562 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13563 | mutex_lock(&dev->struct_mutex); |
13564 | drm_atomic_helper_cleanup_planes(dev, state); | |
13565 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13566 | break; |
f7e5838b | 13567 | } |
7580d774 | 13568 | } |
7580d774 | 13569 | } |
5008e874 ML |
13570 | |
13571 | return ret; | |
13572 | } | |
13573 | ||
a2991414 ML |
13574 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
13575 | { | |
13576 | struct drm_device *dev = crtc->base.dev; | |
13577 | ||
13578 | if (!dev->max_vblank_count) | |
13579 | return drm_accurate_vblank_count(&crtc->base); | |
13580 | ||
13581 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
13582 | } | |
13583 | ||
5a21b665 DV |
13584 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13585 | struct drm_i915_private *dev_priv, | |
13586 | unsigned crtc_mask) | |
e8861675 | 13587 | { |
5a21b665 DV |
13588 | unsigned last_vblank_count[I915_MAX_PIPES]; |
13589 | enum pipe pipe; | |
13590 | int ret; | |
e8861675 | 13591 | |
5a21b665 DV |
13592 | if (!crtc_mask) |
13593 | return; | |
e8861675 | 13594 | |
5a21b665 DV |
13595 | for_each_pipe(dev_priv, pipe) { |
13596 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 13597 | |
5a21b665 | 13598 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
13599 | continue; |
13600 | ||
5a21b665 DV |
13601 | ret = drm_crtc_vblank_get(crtc); |
13602 | if (WARN_ON(ret != 0)) { | |
13603 | crtc_mask &= ~(1 << pipe); | |
13604 | continue; | |
e8861675 ML |
13605 | } |
13606 | ||
5a21b665 | 13607 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
13608 | } |
13609 | ||
5a21b665 DV |
13610 | for_each_pipe(dev_priv, pipe) { |
13611 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13612 | long lret; | |
e8861675 | 13613 | |
5a21b665 DV |
13614 | if (!((1 << pipe) & crtc_mask)) |
13615 | continue; | |
d55dbd06 | 13616 | |
5a21b665 DV |
13617 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
13618 | last_vblank_count[pipe] != | |
13619 | drm_crtc_vblank_count(crtc), | |
13620 | msecs_to_jiffies(50)); | |
d55dbd06 | 13621 | |
5a21b665 | 13622 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 13623 | |
5a21b665 | 13624 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
13625 | } |
13626 | } | |
13627 | ||
5a21b665 | 13628 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 13629 | { |
5a21b665 DV |
13630 | /* fb updated, need to unpin old fb */ |
13631 | if (crtc_state->fb_changed) | |
13632 | return true; | |
a6747b73 | 13633 | |
5a21b665 DV |
13634 | /* wm changes, need vblank before final wm's */ |
13635 | if (crtc_state->update_wm_post) | |
13636 | return true; | |
a6747b73 | 13637 | |
5a21b665 DV |
13638 | /* |
13639 | * cxsr is re-enabled after vblank. | |
13640 | * This is already handled by crtc_state->update_wm_post, | |
13641 | * but added for clarity. | |
13642 | */ | |
13643 | if (crtc_state->disable_cxsr) | |
13644 | return true; | |
a6747b73 | 13645 | |
5a21b665 | 13646 | return false; |
e8861675 ML |
13647 | } |
13648 | ||
94f05024 | 13649 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 13650 | { |
94f05024 | 13651 | struct drm_device *dev = state->dev; |
565602d7 | 13652 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13653 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 13654 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13655 | struct drm_crtc *crtc; |
5a21b665 | 13656 | struct intel_crtc_state *intel_cstate; |
94f05024 DV |
13657 | struct drm_plane *plane; |
13658 | struct drm_plane_state *plane_state; | |
5a21b665 DV |
13659 | bool hw_check = intel_state->modeset; |
13660 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
13661 | unsigned crtc_vblank_mask = 0; | |
94f05024 | 13662 | int i, ret; |
a6778b3c | 13663 | |
94f05024 DV |
13664 | for_each_plane_in_state(state, plane, plane_state, i) { |
13665 | struct intel_plane_state *intel_plane_state = | |
13666 | to_intel_plane_state(plane_state); | |
ea0000f0 | 13667 | |
94f05024 DV |
13668 | if (!intel_plane_state->wait_req) |
13669 | continue; | |
d4afb8cc | 13670 | |
94f05024 DV |
13671 | ret = __i915_wait_request(intel_plane_state->wait_req, |
13672 | true, NULL, NULL); | |
13673 | /* EIO should be eaten, and we can't get interrupted in the | |
13674 | * worker, and blocking commits have waited already. */ | |
13675 | WARN_ON(ret); | |
13676 | } | |
1c5e19f8 | 13677 | |
ea0000f0 DV |
13678 | drm_atomic_helper_wait_for_dependencies(state); |
13679 | ||
565602d7 ML |
13680 | if (intel_state->modeset) { |
13681 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13682 | sizeof(intel_state->min_pixclk)); | |
13683 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13684 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
13685 | |
13686 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13687 | } |
13688 | ||
29ceb0e6 | 13689 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13691 | ||
5a21b665 DV |
13692 | if (needs_modeset(crtc->state) || |
13693 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13694 | hw_check = true; | |
13695 | ||
13696 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13697 | modeset_get_crtc_power_domains(crtc, | |
13698 | to_intel_crtc_state(crtc->state)); | |
13699 | } | |
13700 | ||
61333b60 ML |
13701 | if (!needs_modeset(crtc->state)) |
13702 | continue; | |
13703 | ||
29ceb0e6 | 13704 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13705 | |
29ceb0e6 VS |
13706 | if (old_crtc_state->active) { |
13707 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13708 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13709 | intel_crtc->active = false; |
58f9c0bc | 13710 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13711 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13712 | |
13713 | /* | |
13714 | * Underruns don't always raise | |
13715 | * interrupts, so check manually. | |
13716 | */ | |
13717 | intel_check_cpu_fifo_underruns(dev_priv); | |
13718 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13719 | |
13720 | if (!crtc->state->active) | |
13721 | intel_update_watermarks(crtc); | |
a539205a | 13722 | } |
b8cecdf5 | 13723 | } |
7758a113 | 13724 | |
ea9d758d DV |
13725 | /* Only after disabling all output pipelines that will be changed can we |
13726 | * update the the output configuration. */ | |
4740b0f2 | 13727 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13728 | |
565602d7 | 13729 | if (intel_state->modeset) { |
4740b0f2 | 13730 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13731 | |
13732 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 13733 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13734 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 13735 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 13736 | |
c0ead703 | 13737 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13738 | } |
47fab737 | 13739 | |
a6778b3c | 13740 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13741 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13743 | bool modeset = needs_modeset(crtc->state); | |
5a21b665 DV |
13744 | struct intel_crtc_state *pipe_config = |
13745 | to_intel_crtc_state(crtc->state); | |
9f836f90 | 13746 | |
f6ac4b2a | 13747 | if (modeset && crtc->state->active) { |
a539205a ML |
13748 | update_scanline_offset(to_intel_crtc(crtc)); |
13749 | dev_priv->display.crtc_enable(crtc); | |
13750 | } | |
80715b2f | 13751 | |
1f7528c4 DV |
13752 | /* Complete events for now disable pipes here. */ |
13753 | if (modeset && !crtc->state->active && crtc->state->event) { | |
13754 | spin_lock_irq(&dev->event_lock); | |
13755 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
13756 | spin_unlock_irq(&dev->event_lock); | |
13757 | ||
13758 | crtc->state->event = NULL; | |
13759 | } | |
13760 | ||
f6ac4b2a | 13761 | if (!modeset) |
29ceb0e6 | 13762 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13763 | |
5a21b665 DV |
13764 | if (crtc->state->active && |
13765 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
faf68d92 | 13766 | intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); |
5a21b665 | 13767 | |
1f7528c4 | 13768 | if (crtc->state->active) |
5a21b665 | 13769 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
f6d1973d | 13770 | |
5a21b665 DV |
13771 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13772 | crtc_vblank_mask |= 1 << i; | |
177246a8 MR |
13773 | } |
13774 | ||
94f05024 DV |
13775 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
13776 | * already, but still need the state for the delayed optimization. To | |
13777 | * fix this: | |
13778 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
13779 | * - schedule that vblank worker _before_ calling hw_done | |
13780 | * - at the start of commit_tail, cancel it _synchrously | |
13781 | * - switch over to the vblank wait helper in the core after that since | |
13782 | * we don't need out special handling any more. | |
13783 | */ | |
5a21b665 DV |
13784 | if (!state->legacy_cursor_update) |
13785 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13786 | ||
13787 | /* | |
13788 | * Now that the vblank has passed, we can go ahead and program the | |
13789 | * optimal watermarks on platforms that need two-step watermark | |
13790 | * programming. | |
13791 | * | |
13792 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13793 | */ | |
13794 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13795 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13796 | ||
13797 | if (dev_priv->display.optimize_watermarks) | |
13798 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13799 | } | |
13800 | ||
13801 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13802 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13803 | ||
13804 | if (put_domains[i]) | |
13805 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13806 | ||
13807 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
13808 | } | |
13809 | ||
94f05024 DV |
13810 | drm_atomic_helper_commit_hw_done(state); |
13811 | ||
5a21b665 DV |
13812 | if (intel_state->modeset) |
13813 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13814 | ||
13815 | mutex_lock(&dev->struct_mutex); | |
13816 | drm_atomic_helper_cleanup_planes(dev, state); | |
13817 | mutex_unlock(&dev->struct_mutex); | |
13818 | ||
ea0000f0 DV |
13819 | drm_atomic_helper_commit_cleanup_done(state); |
13820 | ||
ee165b1a | 13821 | drm_atomic_state_free(state); |
f30da187 | 13822 | |
75714940 MK |
13823 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13824 | * of triggering bugs in unclaimed access. After we finish | |
13825 | * modesetting, see if an error has been flagged, and if so | |
13826 | * enable debugging for the next modeset - and hope we catch | |
13827 | * the culprit. | |
13828 | * | |
13829 | * XXX note that we assume display power is on at this point. | |
13830 | * This might hold true now but we need to add pm helper to check | |
13831 | * unclaimed only when the hardware is on, as atomic commits | |
13832 | * can happen also when the device is completely off. | |
13833 | */ | |
13834 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
13835 | } |
13836 | ||
13837 | static void intel_atomic_commit_work(struct work_struct *work) | |
13838 | { | |
13839 | struct drm_atomic_state *state = container_of(work, | |
13840 | struct drm_atomic_state, | |
13841 | commit_work); | |
13842 | intel_atomic_commit_tail(state); | |
13843 | } | |
13844 | ||
6c9c1b38 DV |
13845 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
13846 | { | |
13847 | struct drm_plane_state *old_plane_state; | |
13848 | struct drm_plane *plane; | |
13849 | struct drm_i915_gem_object *obj, *old_obj; | |
13850 | struct intel_plane *intel_plane; | |
13851 | int i; | |
13852 | ||
13853 | mutex_lock(&state->dev->struct_mutex); | |
13854 | for_each_plane_in_state(state, plane, old_plane_state, i) { | |
13855 | obj = intel_fb_obj(plane->state->fb); | |
13856 | old_obj = intel_fb_obj(old_plane_state->fb); | |
13857 | intel_plane = to_intel_plane(plane); | |
13858 | ||
13859 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
13860 | } | |
13861 | mutex_unlock(&state->dev->struct_mutex); | |
13862 | } | |
13863 | ||
94f05024 DV |
13864 | /** |
13865 | * intel_atomic_commit - commit validated state object | |
13866 | * @dev: DRM device | |
13867 | * @state: the top-level driver state object | |
13868 | * @nonblock: nonblocking commit | |
13869 | * | |
13870 | * This function commits a top-level state object that has been validated | |
13871 | * with drm_atomic_helper_check(). | |
13872 | * | |
13873 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13874 | * nonblocking commits are only safe for pure plane updates. Everything else | |
13875 | * should work though. | |
13876 | * | |
13877 | * RETURNS | |
13878 | * Zero for success or -errno. | |
13879 | */ | |
13880 | static int intel_atomic_commit(struct drm_device *dev, | |
13881 | struct drm_atomic_state *state, | |
13882 | bool nonblock) | |
13883 | { | |
13884 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 13885 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
13886 | int ret = 0; |
13887 | ||
13888 | if (intel_state->modeset && nonblock) { | |
13889 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
13890 | return -EINVAL; | |
13891 | } | |
13892 | ||
13893 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
13894 | if (ret) | |
13895 | return ret; | |
13896 | ||
13897 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); | |
13898 | ||
13899 | ret = intel_atomic_prepare_commit(dev, state, nonblock); | |
13900 | if (ret) { | |
13901 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
13902 | return ret; | |
13903 | } | |
13904 | ||
13905 | drm_atomic_helper_swap_state(state, true); | |
13906 | dev_priv->wm.distrust_bios_wm = false; | |
13907 | dev_priv->wm.skl_results = intel_state->wm_results; | |
13908 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 13909 | intel_atomic_track_fbs(state); |
94f05024 DV |
13910 | |
13911 | if (nonblock) | |
13912 | queue_work(system_unbound_wq, &state->commit_work); | |
13913 | else | |
13914 | intel_atomic_commit_tail(state); | |
75714940 | 13915 | |
74c090b1 | 13916 | return 0; |
7f27126e JB |
13917 | } |
13918 | ||
c0c36b94 CW |
13919 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13920 | { | |
83a57153 ACO |
13921 | struct drm_device *dev = crtc->dev; |
13922 | struct drm_atomic_state *state; | |
e694eb02 | 13923 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13924 | int ret; |
83a57153 ACO |
13925 | |
13926 | state = drm_atomic_state_alloc(dev); | |
13927 | if (!state) { | |
78108b7c VS |
13928 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13929 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13930 | return; |
13931 | } | |
13932 | ||
e694eb02 | 13933 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13934 | |
e694eb02 ML |
13935 | retry: |
13936 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13937 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13938 | if (!ret) { | |
13939 | if (!crtc_state->active) | |
13940 | goto out; | |
83a57153 | 13941 | |
e694eb02 | 13942 | crtc_state->mode_changed = true; |
74c090b1 | 13943 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13944 | } |
13945 | ||
e694eb02 ML |
13946 | if (ret == -EDEADLK) { |
13947 | drm_atomic_state_clear(state); | |
13948 | drm_modeset_backoff(state->acquire_ctx); | |
13949 | goto retry; | |
4ed9fb37 | 13950 | } |
4be07317 | 13951 | |
2bfb4627 | 13952 | if (ret) |
e694eb02 | 13953 | out: |
2bfb4627 | 13954 | drm_atomic_state_free(state); |
c0c36b94 CW |
13955 | } |
13956 | ||
25c5b266 DV |
13957 | #undef for_each_intel_crtc_masked |
13958 | ||
f6e5b160 | 13959 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13960 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13961 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13962 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13963 | .destroy = intel_crtc_destroy, |
527b6abe | 13964 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
13965 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13966 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13967 | }; |
13968 | ||
6beb8c23 MR |
13969 | /** |
13970 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13971 | * @plane: drm plane to prepare for | |
13972 | * @fb: framebuffer to prepare for presentation | |
13973 | * | |
13974 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13975 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13976 | * bits. Some older platforms need special physical address handling for | |
13977 | * cursor planes. | |
13978 | * | |
f935675f ML |
13979 | * Must be called with struct_mutex held. |
13980 | * | |
6beb8c23 MR |
13981 | * Returns 0 on success, negative error code on failure. |
13982 | */ | |
13983 | int | |
13984 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13985 | const struct drm_plane_state *new_state) |
465c120c MR |
13986 | { |
13987 | struct drm_device *dev = plane->dev; | |
844f9111 | 13988 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13989 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13990 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c37efb99 | 13991 | struct reservation_object *resv; |
6beb8c23 | 13992 | int ret = 0; |
465c120c | 13993 | |
1ee49399 | 13994 | if (!obj && !old_obj) |
465c120c MR |
13995 | return 0; |
13996 | ||
5008e874 ML |
13997 | if (old_obj) { |
13998 | struct drm_crtc_state *crtc_state = | |
13999 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14000 | ||
14001 | /* Big Hammer, we also need to ensure that any pending | |
14002 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14003 | * current scanout is retired before unpinning the old | |
14004 | * framebuffer. Note that we rely on userspace rendering | |
14005 | * into the buffer attached to the pipe they are waiting | |
14006 | * on. If not, userspace generates a GPU hang with IPEHR | |
14007 | * point to the MI_WAIT_FOR_EVENT. | |
14008 | * | |
14009 | * This should only fail upon a hung GPU, in which case we | |
14010 | * can safely continue. | |
14011 | */ | |
14012 | if (needs_modeset(crtc_state)) | |
14013 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
14014 | if (ret) { |
14015 | /* GPU hangs should have been swallowed by the wait */ | |
14016 | WARN_ON(ret == -EIO); | |
f935675f | 14017 | return ret; |
f4457ae7 | 14018 | } |
5008e874 ML |
14019 | } |
14020 | ||
c37efb99 CW |
14021 | if (!obj) |
14022 | return 0; | |
14023 | ||
5a21b665 | 14024 | /* For framebuffer backed by dmabuf, wait for fence */ |
c37efb99 CW |
14025 | resv = i915_gem_object_get_dmabuf_resv(obj); |
14026 | if (resv) { | |
5a21b665 DV |
14027 | long lret; |
14028 | ||
c37efb99 | 14029 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
5a21b665 DV |
14030 | MAX_SCHEDULE_TIMEOUT); |
14031 | if (lret == -ERESTARTSYS) | |
14032 | return lret; | |
14033 | ||
14034 | WARN(lret < 0, "waiting returns %li\n", lret); | |
14035 | } | |
14036 | ||
c37efb99 | 14037 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 MR |
14038 | INTEL_INFO(dev)->cursor_needs_physical) { |
14039 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14040 | ret = i915_gem_object_attach_phys(obj, align); | |
14041 | if (ret) | |
14042 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14043 | } else { | |
3465c580 | 14044 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14045 | } |
465c120c | 14046 | |
c37efb99 | 14047 | if (ret == 0) { |
6c9c1b38 DV |
14048 | struct intel_plane_state *plane_state = |
14049 | to_intel_plane_state(new_state); | |
7580d774 | 14050 | |
6c9c1b38 DV |
14051 | i915_gem_request_assign(&plane_state->wait_req, |
14052 | obj->last_write_req); | |
7580d774 | 14053 | } |
fdd508a6 | 14054 | |
6beb8c23 MR |
14055 | return ret; |
14056 | } | |
14057 | ||
38f3ce3a MR |
14058 | /** |
14059 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14060 | * @plane: drm plane to clean up for | |
14061 | * @fb: old framebuffer that was on plane | |
14062 | * | |
14063 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14064 | * |
14065 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14066 | */ |
14067 | void | |
14068 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14069 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14070 | { |
14071 | struct drm_device *dev = plane->dev; | |
7580d774 | 14072 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14073 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14074 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14075 | |
7580d774 ML |
14076 | old_intel_state = to_intel_plane_state(old_state); |
14077 | ||
1ee49399 | 14078 | if (!obj && !old_obj) |
38f3ce3a MR |
14079 | return; |
14080 | ||
1ee49399 ML |
14081 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14082 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14083 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 | 14084 | |
7580d774 | 14085 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
465c120c MR |
14086 | } |
14087 | ||
6156a456 CK |
14088 | int |
14089 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14090 | { | |
14091 | int max_scale; | |
6156a456 CK |
14092 | int crtc_clock, cdclk; |
14093 | ||
bf8a0af0 | 14094 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14095 | return DRM_PLANE_HELPER_NO_SCALING; |
14096 | ||
6156a456 | 14097 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14098 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14099 | |
54bf1ce6 | 14100 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14101 | return DRM_PLANE_HELPER_NO_SCALING; |
14102 | ||
14103 | /* | |
14104 | * skl max scale is lower of: | |
14105 | * close to 3 but not 3, -1 is for that purpose | |
14106 | * or | |
14107 | * cdclk/crtc_clock | |
14108 | */ | |
14109 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14110 | ||
14111 | return max_scale; | |
14112 | } | |
14113 | ||
465c120c | 14114 | static int |
3c692a41 | 14115 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14116 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14117 | struct intel_plane_state *state) |
14118 | { | |
2b875c22 MR |
14119 | struct drm_crtc *crtc = state->base.crtc; |
14120 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14121 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14122 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14123 | bool can_position = false; | |
465c120c | 14124 | |
693bdc28 VS |
14125 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14126 | /* use scaler when colorkey is not required */ | |
14127 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14128 | min_scale = 1; | |
14129 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14130 | } | |
d8106366 | 14131 | can_position = true; |
6156a456 | 14132 | } |
d8106366 | 14133 | |
061e4b8d ML |
14134 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14135 | &state->dst, &state->clip, | |
9b8b013d | 14136 | state->base.rotation, |
da20eabd ML |
14137 | min_scale, max_scale, |
14138 | can_position, true, | |
14139 | &state->visible); | |
14af293f GP |
14140 | } |
14141 | ||
5a21b665 DV |
14142 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14143 | struct drm_crtc_state *old_crtc_state) | |
14144 | { | |
14145 | struct drm_device *dev = crtc->dev; | |
14146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14147 | struct intel_crtc_state *old_intel_state = | |
14148 | to_intel_crtc_state(old_crtc_state); | |
14149 | bool modeset = needs_modeset(crtc->state); | |
14150 | ||
14151 | /* Perform vblank evasion around commit operation */ | |
14152 | intel_pipe_update_start(intel_crtc); | |
14153 | ||
14154 | if (modeset) | |
14155 | return; | |
14156 | ||
14157 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14158 | intel_color_set_csc(crtc->state); | |
14159 | intel_color_load_luts(crtc->state); | |
14160 | } | |
14161 | ||
14162 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14163 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14164 | else if (INTEL_INFO(dev)->gen >= 9) | |
14165 | skl_detach_scalers(intel_crtc); | |
14166 | } | |
14167 | ||
14168 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14169 | struct drm_crtc_state *old_crtc_state) | |
14170 | { | |
14171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14172 | ||
14173 | intel_pipe_update_end(intel_crtc, NULL); | |
14174 | } | |
14175 | ||
cf4c7c12 | 14176 | /** |
4a3b8769 MR |
14177 | * intel_plane_destroy - destroy a plane |
14178 | * @plane: plane to destroy | |
cf4c7c12 | 14179 | * |
4a3b8769 MR |
14180 | * Common destruction function for all types of planes (primary, cursor, |
14181 | * sprite). | |
cf4c7c12 | 14182 | */ |
4a3b8769 | 14183 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14184 | { |
69ae561f VS |
14185 | if (!plane) |
14186 | return; | |
14187 | ||
465c120c | 14188 | drm_plane_cleanup(plane); |
69ae561f | 14189 | kfree(to_intel_plane(plane)); |
465c120c MR |
14190 | } |
14191 | ||
65a3fea0 | 14192 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14193 | .update_plane = drm_atomic_helper_update_plane, |
14194 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14195 | .destroy = intel_plane_destroy, |
c196e1d6 | 14196 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14197 | .atomic_get_property = intel_plane_atomic_get_property, |
14198 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14199 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14200 | .atomic_destroy_state = intel_plane_destroy_state, | |
14201 | ||
465c120c MR |
14202 | }; |
14203 | ||
14204 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14205 | int pipe) | |
14206 | { | |
fca0ce2a VS |
14207 | struct intel_plane *primary = NULL; |
14208 | struct intel_plane_state *state = NULL; | |
465c120c | 14209 | const uint32_t *intel_primary_formats; |
45e3743a | 14210 | unsigned int num_formats; |
fca0ce2a | 14211 | int ret; |
465c120c MR |
14212 | |
14213 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14214 | if (!primary) |
14215 | goto fail; | |
465c120c | 14216 | |
8e7d688b | 14217 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14218 | if (!state) |
14219 | goto fail; | |
8e7d688b | 14220 | primary->base.state = &state->base; |
ea2c67bb | 14221 | |
465c120c MR |
14222 | primary->can_scale = false; |
14223 | primary->max_downscale = 1; | |
6156a456 CK |
14224 | if (INTEL_INFO(dev)->gen >= 9) { |
14225 | primary->can_scale = true; | |
af99ceda | 14226 | state->scaler_id = -1; |
6156a456 | 14227 | } |
465c120c MR |
14228 | primary->pipe = pipe; |
14229 | primary->plane = pipe; | |
a9ff8714 | 14230 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14231 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14232 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14233 | primary->plane = !pipe; | |
14234 | ||
6c0fd451 DL |
14235 | if (INTEL_INFO(dev)->gen >= 9) { |
14236 | intel_primary_formats = skl_primary_formats; | |
14237 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14238 | |
14239 | primary->update_plane = skylake_update_primary_plane; | |
14240 | primary->disable_plane = skylake_disable_primary_plane; | |
14241 | } else if (HAS_PCH_SPLIT(dev)) { | |
14242 | intel_primary_formats = i965_primary_formats; | |
14243 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14244 | ||
14245 | primary->update_plane = ironlake_update_primary_plane; | |
14246 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14247 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14248 | intel_primary_formats = i965_primary_formats; |
14249 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14250 | |
14251 | primary->update_plane = i9xx_update_primary_plane; | |
14252 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14253 | } else { |
14254 | intel_primary_formats = i8xx_primary_formats; | |
14255 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14256 | |
14257 | primary->update_plane = i9xx_update_primary_plane; | |
14258 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14259 | } |
14260 | ||
38573dc1 VS |
14261 | if (INTEL_INFO(dev)->gen >= 9) |
14262 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14263 | &intel_plane_funcs, | |
14264 | intel_primary_formats, num_formats, | |
14265 | DRM_PLANE_TYPE_PRIMARY, | |
14266 | "plane 1%c", pipe_name(pipe)); | |
14267 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
14268 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14269 | &intel_plane_funcs, | |
14270 | intel_primary_formats, num_formats, | |
14271 | DRM_PLANE_TYPE_PRIMARY, | |
14272 | "primary %c", pipe_name(pipe)); | |
14273 | else | |
14274 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14275 | &intel_plane_funcs, | |
14276 | intel_primary_formats, num_formats, | |
14277 | DRM_PLANE_TYPE_PRIMARY, | |
14278 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
14279 | if (ret) |
14280 | goto fail; | |
48404c1e | 14281 | |
3b7a5119 SJ |
14282 | if (INTEL_INFO(dev)->gen >= 4) |
14283 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14284 | |
ea2c67bb MR |
14285 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14286 | ||
465c120c | 14287 | return &primary->base; |
fca0ce2a VS |
14288 | |
14289 | fail: | |
14290 | kfree(state); | |
14291 | kfree(primary); | |
14292 | ||
14293 | return NULL; | |
465c120c MR |
14294 | } |
14295 | ||
3b7a5119 SJ |
14296 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14297 | { | |
14298 | if (!dev->mode_config.rotation_property) { | |
14299 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14300 | BIT(DRM_ROTATE_180); | |
14301 | ||
14302 | if (INTEL_INFO(dev)->gen >= 9) | |
14303 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14304 | ||
14305 | dev->mode_config.rotation_property = | |
14306 | drm_mode_create_rotation_property(dev, flags); | |
14307 | } | |
14308 | if (dev->mode_config.rotation_property) | |
14309 | drm_object_attach_property(&plane->base.base, | |
14310 | dev->mode_config.rotation_property, | |
14311 | plane->base.state->rotation); | |
14312 | } | |
14313 | ||
3d7d6510 | 14314 | static int |
852e787c | 14315 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14316 | struct intel_crtc_state *crtc_state, |
852e787c | 14317 | struct intel_plane_state *state) |
3d7d6510 | 14318 | { |
061e4b8d | 14319 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14320 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14321 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14322 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14323 | unsigned stride; |
14324 | int ret; | |
3d7d6510 | 14325 | |
061e4b8d ML |
14326 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14327 | &state->dst, &state->clip, | |
9b8b013d | 14328 | state->base.rotation, |
3d7d6510 MR |
14329 | DRM_PLANE_HELPER_NO_SCALING, |
14330 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14331 | true, true, &state->visible); |
757f9a3e GP |
14332 | if (ret) |
14333 | return ret; | |
14334 | ||
757f9a3e GP |
14335 | /* if we want to turn off the cursor ignore width and height */ |
14336 | if (!obj) | |
da20eabd | 14337 | return 0; |
757f9a3e | 14338 | |
757f9a3e | 14339 | /* Check for which cursor types we support */ |
061e4b8d | 14340 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14341 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14342 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14343 | return -EINVAL; |
14344 | } | |
14345 | ||
ea2c67bb MR |
14346 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14347 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14348 | DRM_DEBUG_KMS("buffer is too small\n"); |
14349 | return -ENOMEM; | |
14350 | } | |
14351 | ||
3a656b54 | 14352 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14353 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14354 | return -EINVAL; |
32b7eeec MR |
14355 | } |
14356 | ||
b29ec92c VS |
14357 | /* |
14358 | * There's something wrong with the cursor on CHV pipe C. | |
14359 | * If it straddles the left edge of the screen then | |
14360 | * moving it away from the edge or disabling it often | |
14361 | * results in a pipe underrun, and often that can lead to | |
14362 | * dead pipe (constant underrun reported, and it scans | |
14363 | * out just a solid color). To recover from that, the | |
14364 | * display power well must be turned off and on again. | |
14365 | * Refuse the put the cursor into that compromised position. | |
14366 | */ | |
14367 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14368 | state->visible && state->base.crtc_x < 0) { | |
14369 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14370 | return -EINVAL; | |
14371 | } | |
14372 | ||
da20eabd | 14373 | return 0; |
852e787c | 14374 | } |
3d7d6510 | 14375 | |
a8ad0d8e ML |
14376 | static void |
14377 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14378 | struct drm_crtc *crtc) |
a8ad0d8e | 14379 | { |
f2858021 ML |
14380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14381 | ||
14382 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14383 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14384 | } |
14385 | ||
f4a2cf29 | 14386 | static void |
55a08b3f ML |
14387 | intel_update_cursor_plane(struct drm_plane *plane, |
14388 | const struct intel_crtc_state *crtc_state, | |
14389 | const struct intel_plane_state *state) | |
852e787c | 14390 | { |
55a08b3f ML |
14391 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14392 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14393 | struct drm_device *dev = plane->dev; |
2b875c22 | 14394 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14395 | uint32_t addr; |
852e787c | 14396 | |
f4a2cf29 | 14397 | if (!obj) |
a912f12f | 14398 | addr = 0; |
f4a2cf29 | 14399 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14400 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14401 | else |
a912f12f | 14402 | addr = obj->phys_handle->busaddr; |
852e787c | 14403 | |
a912f12f | 14404 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14405 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14406 | } |
14407 | ||
3d7d6510 MR |
14408 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14409 | int pipe) | |
14410 | { | |
fca0ce2a VS |
14411 | struct intel_plane *cursor = NULL; |
14412 | struct intel_plane_state *state = NULL; | |
14413 | int ret; | |
3d7d6510 MR |
14414 | |
14415 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14416 | if (!cursor) |
14417 | goto fail; | |
3d7d6510 | 14418 | |
8e7d688b | 14419 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14420 | if (!state) |
14421 | goto fail; | |
8e7d688b | 14422 | cursor->base.state = &state->base; |
ea2c67bb | 14423 | |
3d7d6510 MR |
14424 | cursor->can_scale = false; |
14425 | cursor->max_downscale = 1; | |
14426 | cursor->pipe = pipe; | |
14427 | cursor->plane = pipe; | |
a9ff8714 | 14428 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14429 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14430 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14431 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14432 | |
fca0ce2a VS |
14433 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14434 | &intel_plane_funcs, | |
14435 | intel_cursor_formats, | |
14436 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
14437 | DRM_PLANE_TYPE_CURSOR, |
14438 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
14439 | if (ret) |
14440 | goto fail; | |
4398ad45 VS |
14441 | |
14442 | if (INTEL_INFO(dev)->gen >= 4) { | |
14443 | if (!dev->mode_config.rotation_property) | |
14444 | dev->mode_config.rotation_property = | |
14445 | drm_mode_create_rotation_property(dev, | |
14446 | BIT(DRM_ROTATE_0) | | |
14447 | BIT(DRM_ROTATE_180)); | |
14448 | if (dev->mode_config.rotation_property) | |
14449 | drm_object_attach_property(&cursor->base.base, | |
14450 | dev->mode_config.rotation_property, | |
8e7d688b | 14451 | state->base.rotation); |
4398ad45 VS |
14452 | } |
14453 | ||
af99ceda CK |
14454 | if (INTEL_INFO(dev)->gen >=9) |
14455 | state->scaler_id = -1; | |
14456 | ||
ea2c67bb MR |
14457 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14458 | ||
3d7d6510 | 14459 | return &cursor->base; |
fca0ce2a VS |
14460 | |
14461 | fail: | |
14462 | kfree(state); | |
14463 | kfree(cursor); | |
14464 | ||
14465 | return NULL; | |
3d7d6510 MR |
14466 | } |
14467 | ||
549e2bfb CK |
14468 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14469 | struct intel_crtc_state *crtc_state) | |
14470 | { | |
14471 | int i; | |
14472 | struct intel_scaler *intel_scaler; | |
14473 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14474 | ||
14475 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14476 | intel_scaler = &scaler_state->scalers[i]; | |
14477 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14478 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14479 | } | |
14480 | ||
14481 | scaler_state->scaler_id = -1; | |
14482 | } | |
14483 | ||
b358d0a6 | 14484 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14485 | { |
fac5e23e | 14486 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 14487 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14488 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14489 | struct drm_plane *primary = NULL; |
14490 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14491 | int ret; |
79e53945 | 14492 | |
955382f3 | 14493 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14494 | if (intel_crtc == NULL) |
14495 | return; | |
14496 | ||
f5de6e07 ACO |
14497 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14498 | if (!crtc_state) | |
14499 | goto fail; | |
550acefd ACO |
14500 | intel_crtc->config = crtc_state; |
14501 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14502 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14503 | |
549e2bfb CK |
14504 | /* initialize shared scalers */ |
14505 | if (INTEL_INFO(dev)->gen >= 9) { | |
14506 | if (pipe == PIPE_C) | |
14507 | intel_crtc->num_scalers = 1; | |
14508 | else | |
14509 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14510 | ||
14511 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14512 | } | |
14513 | ||
465c120c | 14514 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14515 | if (!primary) |
14516 | goto fail; | |
14517 | ||
14518 | cursor = intel_cursor_plane_create(dev, pipe); | |
14519 | if (!cursor) | |
14520 | goto fail; | |
14521 | ||
465c120c | 14522 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
4d5d72b7 VS |
14523 | cursor, &intel_crtc_funcs, |
14524 | "pipe %c", pipe_name(pipe)); | |
3d7d6510 MR |
14525 | if (ret) |
14526 | goto fail; | |
79e53945 | 14527 | |
1f1c2e24 VS |
14528 | /* |
14529 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14530 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14531 | */ |
80824003 JB |
14532 | intel_crtc->pipe = pipe; |
14533 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14534 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14535 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14536 | intel_crtc->plane = !pipe; |
80824003 JB |
14537 | } |
14538 | ||
4b0e333e CW |
14539 | intel_crtc->cursor_base = ~0; |
14540 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14541 | intel_crtc->cursor_size = ~0; |
8d7849db | 14542 | |
852eb00d VS |
14543 | intel_crtc->wm.cxsr_allowed = true; |
14544 | ||
22fd0fab JB |
14545 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14546 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14547 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14548 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14549 | ||
79e53945 | 14550 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14551 | |
8563b1e8 LL |
14552 | intel_color_init(&intel_crtc->base); |
14553 | ||
87b6b101 | 14554 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14555 | return; |
14556 | ||
14557 | fail: | |
69ae561f VS |
14558 | intel_plane_destroy(primary); |
14559 | intel_plane_destroy(cursor); | |
f5de6e07 | 14560 | kfree(crtc_state); |
3d7d6510 | 14561 | kfree(intel_crtc); |
79e53945 JB |
14562 | } |
14563 | ||
752aa88a JB |
14564 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14565 | { | |
14566 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14567 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14568 | |
51fd371b | 14569 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14570 | |
d3babd3f | 14571 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14572 | return INVALID_PIPE; |
14573 | ||
14574 | return to_intel_crtc(encoder->crtc)->pipe; | |
14575 | } | |
14576 | ||
08d7b3d1 | 14577 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14578 | struct drm_file *file) |
08d7b3d1 | 14579 | { |
08d7b3d1 | 14580 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14581 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14582 | struct intel_crtc *crtc; |
08d7b3d1 | 14583 | |
7707e653 | 14584 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 14585 | if (!drmmode_crtc) |
3f2c2057 | 14586 | return -ENOENT; |
08d7b3d1 | 14587 | |
7707e653 | 14588 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14589 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14590 | |
c05422d5 | 14591 | return 0; |
08d7b3d1 CW |
14592 | } |
14593 | ||
66a9278e | 14594 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14595 | { |
66a9278e DV |
14596 | struct drm_device *dev = encoder->base.dev; |
14597 | struct intel_encoder *source_encoder; | |
79e53945 | 14598 | int index_mask = 0; |
79e53945 JB |
14599 | int entry = 0; |
14600 | ||
b2784e15 | 14601 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14602 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14603 | index_mask |= (1 << entry); |
14604 | ||
79e53945 JB |
14605 | entry++; |
14606 | } | |
4ef69c7a | 14607 | |
79e53945 JB |
14608 | return index_mask; |
14609 | } | |
14610 | ||
4d302442 CW |
14611 | static bool has_edp_a(struct drm_device *dev) |
14612 | { | |
fac5e23e | 14613 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d302442 CW |
14614 | |
14615 | if (!IS_MOBILE(dev)) | |
14616 | return false; | |
14617 | ||
14618 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14619 | return false; | |
14620 | ||
e3589908 | 14621 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14622 | return false; |
14623 | ||
14624 | return true; | |
14625 | } | |
14626 | ||
84b4e042 JB |
14627 | static bool intel_crt_present(struct drm_device *dev) |
14628 | { | |
fac5e23e | 14629 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 14630 | |
884497ed DL |
14631 | if (INTEL_INFO(dev)->gen >= 9) |
14632 | return false; | |
14633 | ||
cf404ce4 | 14634 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14635 | return false; |
14636 | ||
14637 | if (IS_CHERRYVIEW(dev)) | |
14638 | return false; | |
14639 | ||
65e472e4 VS |
14640 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14641 | return false; | |
14642 | ||
70ac54d0 VS |
14643 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14644 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14645 | return false; | |
14646 | ||
e4abb733 | 14647 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14648 | return false; |
14649 | ||
14650 | return true; | |
14651 | } | |
14652 | ||
79e53945 JB |
14653 | static void intel_setup_outputs(struct drm_device *dev) |
14654 | { | |
fac5e23e | 14655 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 14656 | struct intel_encoder *encoder; |
cb0953d7 | 14657 | bool dpd_is_edp = false; |
79e53945 | 14658 | |
97a824e1 ID |
14659 | /* |
14660 | * intel_edp_init_connector() depends on this completing first, to | |
14661 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14662 | * sharing of the PPS. | |
14663 | */ | |
c9093354 | 14664 | intel_lvds_init(dev); |
79e53945 | 14665 | |
84b4e042 | 14666 | if (intel_crt_present(dev)) |
79935fca | 14667 | intel_crt_init(dev); |
cb0953d7 | 14668 | |
c776eb2e VK |
14669 | if (IS_BROXTON(dev)) { |
14670 | /* | |
14671 | * FIXME: Broxton doesn't support port detection via the | |
14672 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14673 | * detect the ports. | |
14674 | */ | |
14675 | intel_ddi_init(dev, PORT_A); | |
14676 | intel_ddi_init(dev, PORT_B); | |
14677 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14678 | |
14679 | intel_dsi_init(dev); | |
c776eb2e | 14680 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14681 | int found; |
14682 | ||
de31facd JB |
14683 | /* |
14684 | * Haswell uses DDI functions to detect digital outputs. | |
14685 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14686 | * it's there. | |
14687 | */ | |
77179400 | 14688 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14689 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14690 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14691 | intel_ddi_init(dev, PORT_A); |
14692 | ||
14693 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14694 | * register */ | |
14695 | found = I915_READ(SFUSE_STRAP); | |
14696 | ||
14697 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14698 | intel_ddi_init(dev, PORT_B); | |
14699 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14700 | intel_ddi_init(dev, PORT_C); | |
14701 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14702 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14703 | /* |
14704 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14705 | */ | |
ef11bdb3 | 14706 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14707 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14708 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14709 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14710 | intel_ddi_init(dev, PORT_E); | |
14711 | ||
0e72a5b5 | 14712 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14713 | int found; |
5d8a7752 | 14714 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14715 | |
14716 | if (has_edp_a(dev)) | |
14717 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14718 | |
dc0fa718 | 14719 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14720 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14721 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14722 | if (!found) |
e2debe91 | 14723 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14724 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14725 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14726 | } |
14727 | ||
dc0fa718 | 14728 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14729 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14730 | |
dc0fa718 | 14731 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14732 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14733 | |
5eb08b69 | 14734 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14735 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14736 | |
270b3042 | 14737 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14738 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14739 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
22f35042 | 14740 | bool has_edp, has_port; |
457c52d8 | 14741 | |
e17ac6db VS |
14742 | /* |
14743 | * The DP_DETECTED bit is the latched state of the DDC | |
14744 | * SDA pin at boot. However since eDP doesn't require DDC | |
14745 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14746 | * eDP ports may have been muxed to an alternate function. | |
14747 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14748 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14749 | * detect eDP ports. | |
22f35042 VS |
14750 | * |
14751 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14752 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14753 | * and VBT for the presence of the port. Additionally we can't | |
14754 | * trust the port type the VBT declares as we've seen at least | |
14755 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14756 | */ |
457c52d8 | 14757 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
14758 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14759 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 14760 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 14761 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14762 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 14763 | |
457c52d8 | 14764 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
14765 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14766 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 14767 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 14768 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14769 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 14770 | |
9418c1f1 | 14771 | if (IS_CHERRYVIEW(dev)) { |
22f35042 VS |
14772 | /* |
14773 | * eDP not supported on port D, | |
14774 | * so no need to worry about it | |
14775 | */ | |
14776 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14777 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 14778 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
14779 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
14780 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
14781 | } |
14782 | ||
3cfca973 | 14783 | intel_dsi_init(dev); |
09da55dc | 14784 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14785 | bool found = false; |
7d57382e | 14786 | |
e2debe91 | 14787 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14788 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14789 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14790 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14791 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14792 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14793 | } |
27185ae1 | 14794 | |
3fec3d2f | 14795 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14796 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14797 | } |
13520b05 KH |
14798 | |
14799 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14800 | |
e2debe91 | 14801 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14802 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14803 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14804 | } |
27185ae1 | 14805 | |
e2debe91 | 14806 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14807 | |
3fec3d2f | 14808 | if (IS_G4X(dev)) { |
b01f2c3a | 14809 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14810 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14811 | } |
3fec3d2f | 14812 | if (IS_G4X(dev)) |
ab9d7c30 | 14813 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14814 | } |
27185ae1 | 14815 | |
3fec3d2f | 14816 | if (IS_G4X(dev) && |
e7281eab | 14817 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14818 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14819 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14820 | intel_dvo_init(dev); |
14821 | ||
103a196f | 14822 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14823 | intel_tv_init(dev); |
14824 | ||
0bc12bcb | 14825 | intel_psr_init(dev); |
7c8f8a70 | 14826 | |
b2784e15 | 14827 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14828 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14829 | encoder->base.possible_clones = | |
66a9278e | 14830 | intel_encoder_clones(encoder); |
79e53945 | 14831 | } |
47356eb6 | 14832 | |
dde86e2d | 14833 | intel_init_pch_refclk(dev); |
270b3042 DV |
14834 | |
14835 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14836 | } |
14837 | ||
14838 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14839 | { | |
60a5ca01 | 14840 | struct drm_device *dev = fb->dev; |
79e53945 | 14841 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14842 | |
ef2d633e | 14843 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14844 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14845 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14846 | drm_gem_object_unreference(&intel_fb->obj->base); |
14847 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14848 | kfree(intel_fb); |
14849 | } | |
14850 | ||
14851 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14852 | struct drm_file *file, |
79e53945 JB |
14853 | unsigned int *handle) |
14854 | { | |
14855 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14856 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14857 | |
cc917ab4 CW |
14858 | if (obj->userptr.mm) { |
14859 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14860 | return -EINVAL; | |
14861 | } | |
14862 | ||
05394f39 | 14863 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14864 | } |
14865 | ||
86c98588 RV |
14866 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14867 | struct drm_file *file, | |
14868 | unsigned flags, unsigned color, | |
14869 | struct drm_clip_rect *clips, | |
14870 | unsigned num_clips) | |
14871 | { | |
14872 | struct drm_device *dev = fb->dev; | |
14873 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14874 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14875 | ||
14876 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14877 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14878 | mutex_unlock(&dev->struct_mutex); |
14879 | ||
14880 | return 0; | |
14881 | } | |
14882 | ||
79e53945 JB |
14883 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14884 | .destroy = intel_user_framebuffer_destroy, | |
14885 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14886 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14887 | }; |
14888 | ||
b321803d DL |
14889 | static |
14890 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14891 | uint32_t pixel_format) | |
14892 | { | |
14893 | u32 gen = INTEL_INFO(dev)->gen; | |
14894 | ||
14895 | if (gen >= 9) { | |
ac484963 VS |
14896 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14897 | ||
b321803d DL |
14898 | /* "The stride in bytes must not exceed the of the size of 8K |
14899 | * pixels and 32K bytes." | |
14900 | */ | |
ac484963 | 14901 | return min(8192 * cpp, 32768); |
666a4537 | 14902 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14903 | return 32*1024; |
14904 | } else if (gen >= 4) { | |
14905 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14906 | return 16*1024; | |
14907 | else | |
14908 | return 32*1024; | |
14909 | } else if (gen >= 3) { | |
14910 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14911 | return 8*1024; | |
14912 | else | |
14913 | return 16*1024; | |
14914 | } else { | |
14915 | /* XXX DSPC is limited to 4k tiled */ | |
14916 | return 8*1024; | |
14917 | } | |
14918 | } | |
14919 | ||
b5ea642a DV |
14920 | static int intel_framebuffer_init(struct drm_device *dev, |
14921 | struct intel_framebuffer *intel_fb, | |
14922 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14923 | struct drm_i915_gem_object *obj) | |
79e53945 | 14924 | { |
7b49f948 | 14925 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14926 | unsigned int aligned_height; |
79e53945 | 14927 | int ret; |
b321803d | 14928 | u32 pitch_limit, stride_alignment; |
79e53945 | 14929 | |
dd4916c5 DV |
14930 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14931 | ||
2a80eada DV |
14932 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14933 | /* Enforce that fb modifier and tiling mode match, but only for | |
14934 | * X-tiled. This is needed for FBC. */ | |
14935 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14936 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14937 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14938 | return -EINVAL; | |
14939 | } | |
14940 | } else { | |
14941 | if (obj->tiling_mode == I915_TILING_X) | |
14942 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14943 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14944 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14945 | return -EINVAL; | |
14946 | } | |
14947 | } | |
14948 | ||
9a8f0a12 TU |
14949 | /* Passed in modifier sanity checking. */ |
14950 | switch (mode_cmd->modifier[0]) { | |
14951 | case I915_FORMAT_MOD_Y_TILED: | |
14952 | case I915_FORMAT_MOD_Yf_TILED: | |
14953 | if (INTEL_INFO(dev)->gen < 9) { | |
14954 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14955 | mode_cmd->modifier[0]); | |
14956 | return -EINVAL; | |
14957 | } | |
14958 | case DRM_FORMAT_MOD_NONE: | |
14959 | case I915_FORMAT_MOD_X_TILED: | |
14960 | break; | |
14961 | default: | |
c0f40428 JB |
14962 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14963 | mode_cmd->modifier[0]); | |
57cd6508 | 14964 | return -EINVAL; |
c16ed4be | 14965 | } |
57cd6508 | 14966 | |
7b49f948 VS |
14967 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14968 | mode_cmd->modifier[0], | |
b321803d DL |
14969 | mode_cmd->pixel_format); |
14970 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14971 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14972 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14973 | return -EINVAL; |
c16ed4be | 14974 | } |
57cd6508 | 14975 | |
b321803d DL |
14976 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14977 | mode_cmd->pixel_format); | |
a35cdaa0 | 14978 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14979 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14980 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14981 | "tiled" : "linear", |
a35cdaa0 | 14982 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14983 | return -EINVAL; |
c16ed4be | 14984 | } |
5d7bd705 | 14985 | |
2a80eada | 14986 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14987 | mode_cmd->pitches[0] != obj->stride) { |
14988 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14989 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14990 | return -EINVAL; |
c16ed4be | 14991 | } |
5d7bd705 | 14992 | |
57779d06 | 14993 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14994 | switch (mode_cmd->pixel_format) { |
57779d06 | 14995 | case DRM_FORMAT_C8: |
04b3924d VS |
14996 | case DRM_FORMAT_RGB565: |
14997 | case DRM_FORMAT_XRGB8888: | |
14998 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14999 | break; |
15000 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15001 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
15002 | DRM_DEBUG("unsupported pixel format: %s\n", |
15003 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15004 | return -EINVAL; |
c16ed4be | 15005 | } |
57779d06 | 15006 | break; |
57779d06 | 15007 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
15008 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
15009 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
15010 | DRM_DEBUG("unsupported pixel format: %s\n", |
15011 | drm_get_format_name(mode_cmd->pixel_format)); | |
15012 | return -EINVAL; | |
15013 | } | |
15014 | break; | |
15015 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15016 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15017 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15018 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15019 | DRM_DEBUG("unsupported pixel format: %s\n", |
15020 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15021 | return -EINVAL; |
c16ed4be | 15022 | } |
b5626747 | 15023 | break; |
7531208b | 15024 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15025 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15026 | DRM_DEBUG("unsupported pixel format: %s\n", |
15027 | drm_get_format_name(mode_cmd->pixel_format)); | |
15028 | return -EINVAL; | |
15029 | } | |
15030 | break; | |
04b3924d VS |
15031 | case DRM_FORMAT_YUYV: |
15032 | case DRM_FORMAT_UYVY: | |
15033 | case DRM_FORMAT_YVYU: | |
15034 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15035 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15036 | DRM_DEBUG("unsupported pixel format: %s\n", |
15037 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15038 | return -EINVAL; |
c16ed4be | 15039 | } |
57cd6508 CW |
15040 | break; |
15041 | default: | |
4ee62c76 VS |
15042 | DRM_DEBUG("unsupported pixel format: %s\n", |
15043 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15044 | return -EINVAL; |
15045 | } | |
15046 | ||
90f9a336 VS |
15047 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15048 | if (mode_cmd->offsets[0] != 0) | |
15049 | return -EINVAL; | |
15050 | ||
ec2c981e | 15051 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
15052 | mode_cmd->pixel_format, |
15053 | mode_cmd->modifier[0]); | |
53155c0a DV |
15054 | /* FIXME drm helper for size checks (especially planar formats)? */ |
15055 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
15056 | return -EINVAL; | |
15057 | ||
c7d73f6a DV |
15058 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15059 | intel_fb->obj = obj; | |
15060 | ||
2d7a215f VS |
15061 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
15062 | ||
79e53945 JB |
15063 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15064 | if (ret) { | |
15065 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15066 | return ret; | |
15067 | } | |
15068 | ||
0b05e1e0 VS |
15069 | intel_fb->obj->framebuffer_references++; |
15070 | ||
79e53945 JB |
15071 | return 0; |
15072 | } | |
15073 | ||
79e53945 JB |
15074 | static struct drm_framebuffer * |
15075 | intel_user_framebuffer_create(struct drm_device *dev, | |
15076 | struct drm_file *filp, | |
1eb83451 | 15077 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15078 | { |
dcb1394e | 15079 | struct drm_framebuffer *fb; |
05394f39 | 15080 | struct drm_i915_gem_object *obj; |
76dc3769 | 15081 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15082 | |
a8ad0bd8 | 15083 | obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0])); |
c8725226 | 15084 | if (&obj->base == NULL) |
cce13ff7 | 15085 | return ERR_PTR(-ENOENT); |
79e53945 | 15086 | |
92907cbb | 15087 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
15088 | if (IS_ERR(fb)) |
15089 | drm_gem_object_unreference_unlocked(&obj->base); | |
15090 | ||
15091 | return fb; | |
79e53945 JB |
15092 | } |
15093 | ||
0695726e | 15094 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15095 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15096 | { |
15097 | } | |
15098 | #endif | |
15099 | ||
79e53945 | 15100 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15101 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15102 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15103 | .atomic_check = intel_atomic_check, |
15104 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15105 | .atomic_state_alloc = intel_atomic_state_alloc, |
15106 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15107 | }; |
15108 | ||
88212941 ID |
15109 | /** |
15110 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15111 | * @dev_priv: device private | |
15112 | */ | |
15113 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15114 | { |
88212941 | 15115 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15116 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15117 | dev_priv->display.get_initial_plane_config = |
15118 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15119 | dev_priv->display.crtc_compute_clock = |
15120 | haswell_crtc_compute_clock; | |
15121 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15122 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15123 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15124 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15125 | dev_priv->display.get_initial_plane_config = |
15126 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15127 | dev_priv->display.crtc_compute_clock = |
15128 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15129 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15130 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15131 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15132 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15133 | dev_priv->display.get_initial_plane_config = |
15134 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15135 | dev_priv->display.crtc_compute_clock = |
15136 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15137 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15138 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15139 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15140 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15141 | dev_priv->display.get_initial_plane_config = |
15142 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15143 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15144 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15145 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15146 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15147 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15148 | dev_priv->display.get_initial_plane_config = | |
15149 | i9xx_get_initial_plane_config; | |
15150 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15151 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15152 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15153 | } else if (IS_G4X(dev_priv)) { |
15154 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15155 | dev_priv->display.get_initial_plane_config = | |
15156 | i9xx_get_initial_plane_config; | |
15157 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15158 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15159 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15160 | } else if (IS_PINEVIEW(dev_priv)) { |
15161 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15162 | dev_priv->display.get_initial_plane_config = | |
15163 | i9xx_get_initial_plane_config; | |
15164 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15165 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15166 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15167 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15168 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15169 | dev_priv->display.get_initial_plane_config = |
15170 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15171 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15172 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15173 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
15174 | } else { |
15175 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15176 | dev_priv->display.get_initial_plane_config = | |
15177 | i9xx_get_initial_plane_config; | |
15178 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
15179 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15180 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15181 | } |
e70236a8 | 15182 | |
e70236a8 | 15183 | /* Returns the core display clock speed */ |
88212941 | 15184 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
15185 | dev_priv->display.get_display_clock_speed = |
15186 | skylake_get_display_clock_speed; | |
88212941 | 15187 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
15188 | dev_priv->display.get_display_clock_speed = |
15189 | broxton_get_display_clock_speed; | |
88212941 | 15190 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
15191 | dev_priv->display.get_display_clock_speed = |
15192 | broadwell_get_display_clock_speed; | |
88212941 | 15193 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
15194 | dev_priv->display.get_display_clock_speed = |
15195 | haswell_get_display_clock_speed; | |
88212941 | 15196 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
15197 | dev_priv->display.get_display_clock_speed = |
15198 | valleyview_get_display_clock_speed; | |
88212941 | 15199 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
15200 | dev_priv->display.get_display_clock_speed = |
15201 | ilk_get_display_clock_speed; | |
88212941 ID |
15202 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
15203 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
15204 | dev_priv->display.get_display_clock_speed = |
15205 | i945_get_display_clock_speed; | |
88212941 | 15206 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
15207 | dev_priv->display.get_display_clock_speed = |
15208 | gm45_get_display_clock_speed; | |
88212941 | 15209 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
15210 | dev_priv->display.get_display_clock_speed = |
15211 | i965gm_get_display_clock_speed; | |
88212941 | 15212 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
15213 | dev_priv->display.get_display_clock_speed = |
15214 | pnv_get_display_clock_speed; | |
88212941 | 15215 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
15216 | dev_priv->display.get_display_clock_speed = |
15217 | g33_get_display_clock_speed; | |
88212941 | 15218 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
15219 | dev_priv->display.get_display_clock_speed = |
15220 | i915_get_display_clock_speed; | |
88212941 | 15221 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
15222 | dev_priv->display.get_display_clock_speed = |
15223 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15224 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15225 | dev_priv->display.get_display_clock_speed = |
15226 | i915gm_get_display_clock_speed; | |
88212941 | 15227 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15228 | dev_priv->display.get_display_clock_speed = |
15229 | i865_get_display_clock_speed; | |
88212941 | 15230 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15231 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15232 | i85x_get_display_clock_speed; |
623e01e5 | 15233 | else { /* 830 */ |
88212941 | 15234 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15235 | dev_priv->display.get_display_clock_speed = |
15236 | i830_get_display_clock_speed; | |
623e01e5 | 15237 | } |
e70236a8 | 15238 | |
88212941 | 15239 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15240 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15241 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15242 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15243 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15244 | /* FIXME: detect B0+ stepping and use auto training */ |
15245 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15246 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15247 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15248 | } |
15249 | ||
15250 | if (IS_BROADWELL(dev_priv)) { | |
15251 | dev_priv->display.modeset_commit_cdclk = | |
15252 | broadwell_modeset_commit_cdclk; | |
15253 | dev_priv->display.modeset_calc_cdclk = | |
15254 | broadwell_modeset_calc_cdclk; | |
88212941 | 15255 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15256 | dev_priv->display.modeset_commit_cdclk = |
15257 | valleyview_modeset_commit_cdclk; | |
15258 | dev_priv->display.modeset_calc_cdclk = | |
15259 | valleyview_modeset_calc_cdclk; | |
88212941 | 15260 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 15261 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 15262 | bxt_modeset_commit_cdclk; |
27c329ed | 15263 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 15264 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
15265 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
15266 | dev_priv->display.modeset_commit_cdclk = | |
15267 | skl_modeset_commit_cdclk; | |
15268 | dev_priv->display.modeset_calc_cdclk = | |
15269 | skl_modeset_calc_cdclk; | |
e70236a8 | 15270 | } |
5a21b665 DV |
15271 | |
15272 | switch (INTEL_INFO(dev_priv)->gen) { | |
15273 | case 2: | |
15274 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15275 | break; | |
15276 | ||
15277 | case 3: | |
15278 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15279 | break; | |
15280 | ||
15281 | case 4: | |
15282 | case 5: | |
15283 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15284 | break; | |
15285 | ||
15286 | case 6: | |
15287 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15288 | break; | |
15289 | case 7: | |
15290 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15291 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15292 | break; | |
15293 | case 9: | |
15294 | /* Drop through - unsupported since execlist only. */ | |
15295 | default: | |
15296 | /* Default just returns -ENODEV to indicate unsupported */ | |
15297 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15298 | } | |
e70236a8 JB |
15299 | } |
15300 | ||
b690e96c JB |
15301 | /* |
15302 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15303 | * resume, or other times. This quirk makes sure that's the case for | |
15304 | * affected systems. | |
15305 | */ | |
0206e353 | 15306 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 15307 | { |
fac5e23e | 15308 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
15309 | |
15310 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15311 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15312 | } |
15313 | ||
b6b5d049 VS |
15314 | static void quirk_pipeb_force(struct drm_device *dev) |
15315 | { | |
fac5e23e | 15316 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
15317 | |
15318 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15319 | DRM_INFO("applying pipe b force quirk\n"); | |
15320 | } | |
15321 | ||
435793df KP |
15322 | /* |
15323 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15324 | */ | |
15325 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15326 | { | |
fac5e23e | 15327 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 15328 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 15329 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15330 | } |
15331 | ||
4dca20ef | 15332 | /* |
5a15ab5b CE |
15333 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15334 | * brightness value | |
4dca20ef CE |
15335 | */ |
15336 | static void quirk_invert_brightness(struct drm_device *dev) | |
15337 | { | |
fac5e23e | 15338 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 15339 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 15340 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15341 | } |
15342 | ||
9c72cc6f SD |
15343 | /* Some VBT's incorrectly indicate no backlight is present */ |
15344 | static void quirk_backlight_present(struct drm_device *dev) | |
15345 | { | |
fac5e23e | 15346 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
15347 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
15348 | DRM_INFO("applying backlight present quirk\n"); | |
15349 | } | |
15350 | ||
b690e96c JB |
15351 | struct intel_quirk { |
15352 | int device; | |
15353 | int subsystem_vendor; | |
15354 | int subsystem_device; | |
15355 | void (*hook)(struct drm_device *dev); | |
15356 | }; | |
15357 | ||
5f85f176 EE |
15358 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15359 | struct intel_dmi_quirk { | |
15360 | void (*hook)(struct drm_device *dev); | |
15361 | const struct dmi_system_id (*dmi_id_list)[]; | |
15362 | }; | |
15363 | ||
15364 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15365 | { | |
15366 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15367 | return 1; | |
15368 | } | |
15369 | ||
15370 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15371 | { | |
15372 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15373 | { | |
15374 | .callback = intel_dmi_reverse_brightness, | |
15375 | .ident = "NCR Corporation", | |
15376 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15377 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15378 | }, | |
15379 | }, | |
15380 | { } /* terminating entry */ | |
15381 | }, | |
15382 | .hook = quirk_invert_brightness, | |
15383 | }, | |
15384 | }; | |
15385 | ||
c43b5634 | 15386 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15387 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15388 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15389 | ||
b690e96c JB |
15390 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15391 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15392 | ||
5f080c0f VS |
15393 | /* 830 needs to leave pipe A & dpll A up */ |
15394 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15395 | ||
b6b5d049 VS |
15396 | /* 830 needs to leave pipe B & dpll B up */ |
15397 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15398 | ||
435793df KP |
15399 | /* Lenovo U160 cannot use SSC on LVDS */ |
15400 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15401 | |
15402 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15403 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15404 | |
be505f64 AH |
15405 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15406 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15407 | ||
15408 | /* Acer/eMachines G725 */ | |
15409 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15410 | ||
15411 | /* Acer/eMachines e725 */ | |
15412 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15413 | ||
15414 | /* Acer/Packard Bell NCL20 */ | |
15415 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15416 | ||
15417 | /* Acer Aspire 4736Z */ | |
15418 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15419 | |
15420 | /* Acer Aspire 5336 */ | |
15421 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15422 | |
15423 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15424 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15425 | |
dfb3d47b SD |
15426 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15427 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15428 | ||
b2a9601c | 15429 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15430 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15431 | ||
1b9448b0 JN |
15432 | /* Apple Macbook 4,1 */ |
15433 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15434 | ||
d4967d8c SD |
15435 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15436 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15437 | |
15438 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15439 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15440 | |
15441 | /* Dell Chromebook 11 */ | |
15442 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15443 | |
15444 | /* Dell Chromebook 11 (2015 version) */ | |
15445 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15446 | }; |
15447 | ||
15448 | static void intel_init_quirks(struct drm_device *dev) | |
15449 | { | |
15450 | struct pci_dev *d = dev->pdev; | |
15451 | int i; | |
15452 | ||
15453 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15454 | struct intel_quirk *q = &intel_quirks[i]; | |
15455 | ||
15456 | if (d->device == q->device && | |
15457 | (d->subsystem_vendor == q->subsystem_vendor || | |
15458 | q->subsystem_vendor == PCI_ANY_ID) && | |
15459 | (d->subsystem_device == q->subsystem_device || | |
15460 | q->subsystem_device == PCI_ANY_ID)) | |
15461 | q->hook(dev); | |
15462 | } | |
5f85f176 EE |
15463 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15464 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15465 | intel_dmi_quirks[i].hook(dev); | |
15466 | } | |
b690e96c JB |
15467 | } |
15468 | ||
9cce37f4 JB |
15469 | /* Disable the VGA plane that we never use */ |
15470 | static void i915_disable_vga(struct drm_device *dev) | |
15471 | { | |
fac5e23e | 15472 | struct drm_i915_private *dev_priv = to_i915(dev); |
9cce37f4 | 15473 | u8 sr1; |
f0f59a00 | 15474 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15475 | |
2b37c616 | 15476 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15477 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15478 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15479 | sr1 = inb(VGA_SR_DATA); |
15480 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15481 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15482 | udelay(300); | |
15483 | ||
01f5a626 | 15484 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15485 | POSTING_READ(vga_reg); |
15486 | } | |
15487 | ||
f817586c DV |
15488 | void intel_modeset_init_hw(struct drm_device *dev) |
15489 | { | |
fac5e23e | 15490 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 15491 | |
b6283055 | 15492 | intel_update_cdclk(dev); |
1a617b77 ML |
15493 | |
15494 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15495 | ||
f817586c | 15496 | intel_init_clock_gating(dev); |
dc97997a | 15497 | intel_enable_gt_powersave(dev_priv); |
f817586c DV |
15498 | } |
15499 | ||
d93c0372 MR |
15500 | /* |
15501 | * Calculate what we think the watermarks should be for the state we've read | |
15502 | * out of the hardware and then immediately program those watermarks so that | |
15503 | * we ensure the hardware settings match our internal state. | |
15504 | * | |
15505 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15506 | * current state (which was constructed during hardware readout) and running it | |
15507 | * through the atomic check code to calculate new watermark values in the | |
15508 | * state object. | |
15509 | */ | |
15510 | static void sanitize_watermarks(struct drm_device *dev) | |
15511 | { | |
15512 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15513 | struct drm_atomic_state *state; | |
15514 | struct drm_crtc *crtc; | |
15515 | struct drm_crtc_state *cstate; | |
15516 | struct drm_modeset_acquire_ctx ctx; | |
15517 | int ret; | |
15518 | int i; | |
15519 | ||
15520 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15521 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15522 | return; |
15523 | ||
15524 | /* | |
15525 | * We need to hold connection_mutex before calling duplicate_state so | |
15526 | * that the connector loop is protected. | |
15527 | */ | |
15528 | drm_modeset_acquire_init(&ctx, 0); | |
15529 | retry: | |
0cd1262d | 15530 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15531 | if (ret == -EDEADLK) { |
15532 | drm_modeset_backoff(&ctx); | |
15533 | goto retry; | |
15534 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15535 | goto fail; |
d93c0372 MR |
15536 | } |
15537 | ||
15538 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15539 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15540 | goto fail; |
d93c0372 | 15541 | |
ed4a6a7c MR |
15542 | /* |
15543 | * Hardware readout is the only time we don't want to calculate | |
15544 | * intermediate watermarks (since we don't trust the current | |
15545 | * watermarks). | |
15546 | */ | |
15547 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15548 | ||
d93c0372 MR |
15549 | ret = intel_atomic_check(dev, state); |
15550 | if (ret) { | |
15551 | /* | |
15552 | * If we fail here, it means that the hardware appears to be | |
15553 | * programmed in a way that shouldn't be possible, given our | |
15554 | * understanding of watermark requirements. This might mean a | |
15555 | * mistake in the hardware readout code or a mistake in the | |
15556 | * watermark calculations for a given platform. Raise a WARN | |
15557 | * so that this is noticeable. | |
15558 | * | |
15559 | * If this actually happens, we'll have to just leave the | |
15560 | * BIOS-programmed watermarks untouched and hope for the best. | |
15561 | */ | |
15562 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15563 | goto fail; |
d93c0372 MR |
15564 | } |
15565 | ||
15566 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15567 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15568 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15569 | ||
ed4a6a7c MR |
15570 | cs->wm.need_postvbl_update = true; |
15571 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15572 | } |
15573 | ||
15574 | drm_atomic_state_free(state); | |
0cd1262d | 15575 | fail: |
d93c0372 MR |
15576 | drm_modeset_drop_locks(&ctx); |
15577 | drm_modeset_acquire_fini(&ctx); | |
15578 | } | |
15579 | ||
79e53945 JB |
15580 | void intel_modeset_init(struct drm_device *dev) |
15581 | { | |
72e96d64 JL |
15582 | struct drm_i915_private *dev_priv = to_i915(dev); |
15583 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15584 | int sprite, ret; |
8cc87b75 | 15585 | enum pipe pipe; |
46f297fb | 15586 | struct intel_crtc *crtc; |
79e53945 JB |
15587 | |
15588 | drm_mode_config_init(dev); | |
15589 | ||
15590 | dev->mode_config.min_width = 0; | |
15591 | dev->mode_config.min_height = 0; | |
15592 | ||
019d96cb DA |
15593 | dev->mode_config.preferred_depth = 24; |
15594 | dev->mode_config.prefer_shadow = 1; | |
15595 | ||
25bab385 TU |
15596 | dev->mode_config.allow_fb_modifiers = true; |
15597 | ||
e6ecefaa | 15598 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15599 | |
b690e96c JB |
15600 | intel_init_quirks(dev); |
15601 | ||
1fa61106 ED |
15602 | intel_init_pm(dev); |
15603 | ||
e3c74757 BW |
15604 | if (INTEL_INFO(dev)->num_pipes == 0) |
15605 | return; | |
15606 | ||
69f92f67 LW |
15607 | /* |
15608 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15609 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15610 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15611 | * indicates as much. | |
15612 | */ | |
15613 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15614 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15615 | DREF_SSC1_ENABLE); | |
15616 | ||
15617 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15618 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15619 | bios_lvds_use_ssc ? "en" : "dis", | |
15620 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15621 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15622 | } | |
15623 | } | |
15624 | ||
a6c45cf0 CW |
15625 | if (IS_GEN2(dev)) { |
15626 | dev->mode_config.max_width = 2048; | |
15627 | dev->mode_config.max_height = 2048; | |
15628 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15629 | dev->mode_config.max_width = 4096; |
15630 | dev->mode_config.max_height = 4096; | |
79e53945 | 15631 | } else { |
a6c45cf0 CW |
15632 | dev->mode_config.max_width = 8192; |
15633 | dev->mode_config.max_height = 8192; | |
79e53945 | 15634 | } |
068be561 | 15635 | |
dc41c154 VS |
15636 | if (IS_845G(dev) || IS_I865G(dev)) { |
15637 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15638 | dev->mode_config.cursor_height = 1023; | |
15639 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15640 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15641 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15642 | } else { | |
15643 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15644 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15645 | } | |
15646 | ||
72e96d64 | 15647 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15648 | |
28c97730 | 15649 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15650 | INTEL_INFO(dev)->num_pipes, |
15651 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15652 | |
055e393f | 15653 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15654 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15655 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15656 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15657 | if (ret) |
06da8da2 | 15658 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15659 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15660 | } |
79e53945 JB |
15661 | } |
15662 | ||
bfa7df01 VS |
15663 | intel_update_czclk(dev_priv); |
15664 | intel_update_cdclk(dev); | |
15665 | ||
e72f9fbf | 15666 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15667 | |
b2045352 VS |
15668 | if (dev_priv->max_cdclk_freq == 0) |
15669 | intel_update_max_cdclk(dev); | |
15670 | ||
9cce37f4 JB |
15671 | /* Just disable it once at startup */ |
15672 | i915_disable_vga(dev); | |
79e53945 | 15673 | intel_setup_outputs(dev); |
11be49eb | 15674 | |
6e9f798d | 15675 | drm_modeset_lock_all(dev); |
043e9bda | 15676 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15677 | drm_modeset_unlock_all(dev); |
46f297fb | 15678 | |
d3fcc808 | 15679 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15680 | struct intel_initial_plane_config plane_config = {}; |
15681 | ||
46f297fb JB |
15682 | if (!crtc->active) |
15683 | continue; | |
15684 | ||
46f297fb | 15685 | /* |
46f297fb JB |
15686 | * Note that reserving the BIOS fb up front prevents us |
15687 | * from stuffing other stolen allocations like the ring | |
15688 | * on top. This prevents some ugliness at boot time, and | |
15689 | * can even allow for smooth boot transitions if the BIOS | |
15690 | * fb is large enough for the active pipe configuration. | |
15691 | */ | |
eeebeac5 ML |
15692 | dev_priv->display.get_initial_plane_config(crtc, |
15693 | &plane_config); | |
15694 | ||
15695 | /* | |
15696 | * If the fb is shared between multiple heads, we'll | |
15697 | * just get the first one. | |
15698 | */ | |
15699 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15700 | } |
d93c0372 MR |
15701 | |
15702 | /* | |
15703 | * Make sure hardware watermarks really match the state we read out. | |
15704 | * Note that we need to do this after reconstructing the BIOS fb's | |
15705 | * since the watermark calculation done here will use pstate->fb. | |
15706 | */ | |
15707 | sanitize_watermarks(dev); | |
2c7111db CW |
15708 | } |
15709 | ||
7fad798e DV |
15710 | static void intel_enable_pipe_a(struct drm_device *dev) |
15711 | { | |
15712 | struct intel_connector *connector; | |
15713 | struct drm_connector *crt = NULL; | |
15714 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15715 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15716 | |
15717 | /* We can't just switch on the pipe A, we need to set things up with a | |
15718 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15719 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15720 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15721 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15722 | crt = &connector->base; | |
15723 | break; | |
15724 | } | |
15725 | } | |
15726 | ||
15727 | if (!crt) | |
15728 | return; | |
15729 | ||
208bf9fd | 15730 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15731 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15732 | } |
15733 | ||
fa555837 DV |
15734 | static bool |
15735 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15736 | { | |
7eb552ae | 15737 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 15738 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 15739 | u32 val; |
fa555837 | 15740 | |
7eb552ae | 15741 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15742 | return true; |
15743 | ||
649636ef | 15744 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15745 | |
15746 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15747 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15748 | return false; | |
15749 | ||
15750 | return true; | |
15751 | } | |
15752 | ||
02e93c35 VS |
15753 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15754 | { | |
15755 | struct drm_device *dev = crtc->base.dev; | |
15756 | struct intel_encoder *encoder; | |
15757 | ||
15758 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15759 | return true; | |
15760 | ||
15761 | return false; | |
15762 | } | |
15763 | ||
dd756198 VS |
15764 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15765 | { | |
15766 | struct drm_device *dev = encoder->base.dev; | |
15767 | struct intel_connector *connector; | |
15768 | ||
15769 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15770 | return true; | |
15771 | ||
15772 | return false; | |
15773 | } | |
15774 | ||
24929352 DV |
15775 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15776 | { | |
15777 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15778 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15779 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15780 | |
24929352 | 15781 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15782 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15783 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15784 | ||
15785 | I915_WRITE(reg, | |
15786 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15787 | } | |
24929352 | 15788 | |
d3eaf884 | 15789 | /* restore vblank interrupts to correct state */ |
9625604c | 15790 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15791 | if (crtc->active) { |
f9cd7b88 VS |
15792 | struct intel_plane *plane; |
15793 | ||
9625604c | 15794 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15795 | |
15796 | /* Disable everything but the primary plane */ | |
15797 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15798 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15799 | continue; | |
15800 | ||
15801 | plane->disable_plane(&plane->base, &crtc->base); | |
15802 | } | |
9625604c | 15803 | } |
d3eaf884 | 15804 | |
24929352 | 15805 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15806 | * disable the crtc (and hence change the state) if it is wrong. Note |
15807 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15808 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15809 | bool plane; |
15810 | ||
78108b7c VS |
15811 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15812 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15813 | |
15814 | /* Pipe has the wrong plane attached and the plane is active. | |
15815 | * Temporarily change the plane mapping and disable everything | |
15816 | * ... */ | |
15817 | plane = crtc->plane; | |
b70709a6 | 15818 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15819 | crtc->plane = !plane; |
b17d48e2 | 15820 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15821 | crtc->plane = plane; |
24929352 | 15822 | } |
24929352 | 15823 | |
7fad798e DV |
15824 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15825 | crtc->pipe == PIPE_A && !crtc->active) { | |
15826 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15827 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15828 | * call below we restore the pipe to the right state, but leave | |
15829 | * the required bits on. */ | |
15830 | intel_enable_pipe_a(dev); | |
15831 | } | |
15832 | ||
24929352 DV |
15833 | /* Adjust the state of the output pipe according to whether we |
15834 | * have active connectors/encoders. */ | |
842e0307 | 15835 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15836 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15837 | |
a3ed6aad | 15838 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15839 | /* |
15840 | * We start out with underrun reporting disabled to avoid races. | |
15841 | * For correct bookkeeping mark this on active crtcs. | |
15842 | * | |
c5ab3bc0 DV |
15843 | * Also on gmch platforms we dont have any hardware bits to |
15844 | * disable the underrun reporting. Which means we need to start | |
15845 | * out with underrun reporting disabled also on inactive pipes, | |
15846 | * since otherwise we'll complain about the garbage we read when | |
15847 | * e.g. coming up after runtime pm. | |
15848 | * | |
4cc31489 DV |
15849 | * No protection against concurrent access is required - at |
15850 | * worst a fifo underrun happens which also sets this to false. | |
15851 | */ | |
15852 | crtc->cpu_fifo_underrun_disabled = true; | |
15853 | crtc->pch_fifo_underrun_disabled = true; | |
15854 | } | |
24929352 DV |
15855 | } |
15856 | ||
15857 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15858 | { | |
15859 | struct intel_connector *connector; | |
15860 | struct drm_device *dev = encoder->base.dev; | |
15861 | ||
15862 | /* We need to check both for a crtc link (meaning that the | |
15863 | * encoder is active and trying to read from a pipe) and the | |
15864 | * pipe itself being active. */ | |
15865 | bool has_active_crtc = encoder->base.crtc && | |
15866 | to_intel_crtc(encoder->base.crtc)->active; | |
15867 | ||
dd756198 | 15868 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15869 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15870 | encoder->base.base.id, | |
8e329a03 | 15871 | encoder->base.name); |
24929352 DV |
15872 | |
15873 | /* Connector is active, but has no active pipe. This is | |
15874 | * fallout from our resume register restoring. Disable | |
15875 | * the encoder manually again. */ | |
15876 | if (encoder->base.crtc) { | |
15877 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15878 | encoder->base.base.id, | |
8e329a03 | 15879 | encoder->base.name); |
24929352 | 15880 | encoder->disable(encoder); |
a62d1497 VS |
15881 | if (encoder->post_disable) |
15882 | encoder->post_disable(encoder); | |
24929352 | 15883 | } |
7f1950fb | 15884 | encoder->base.crtc = NULL; |
24929352 DV |
15885 | |
15886 | /* Inconsistent output/port/pipe state happens presumably due to | |
15887 | * a bug in one of the get_hw_state functions. Or someplace else | |
15888 | * in our code, like the register restore mess on resume. Clamp | |
15889 | * things to off as a safer default. */ | |
3a3371ff | 15890 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15891 | if (connector->encoder != encoder) |
15892 | continue; | |
7f1950fb EE |
15893 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15894 | connector->base.encoder = NULL; | |
24929352 DV |
15895 | } |
15896 | } | |
15897 | /* Enabled encoders without active connectors will be fixed in | |
15898 | * the crtc fixup. */ | |
15899 | } | |
15900 | ||
04098753 | 15901 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 15902 | { |
fac5e23e | 15903 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 15904 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15905 | |
04098753 ID |
15906 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15907 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15908 | i915_disable_vga(dev); | |
15909 | } | |
15910 | } | |
15911 | ||
15912 | void i915_redisable_vga(struct drm_device *dev) | |
15913 | { | |
fac5e23e | 15914 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 15915 | |
8dc8a27c PZ |
15916 | /* This function can be called both from intel_modeset_setup_hw_state or |
15917 | * at a very early point in our resume sequence, where the power well | |
15918 | * structures are not yet restored. Since this function is at a very | |
15919 | * paranoid "someone might have enabled VGA while we were not looking" | |
15920 | * level, just check if the power well is enabled instead of trying to | |
15921 | * follow the "don't touch the power well if we don't need it" policy | |
15922 | * the rest of the driver uses. */ | |
6392f847 | 15923 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15924 | return; |
15925 | ||
04098753 | 15926 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15927 | |
15928 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15929 | } |
15930 | ||
f9cd7b88 | 15931 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15932 | { |
f9cd7b88 | 15933 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15934 | |
f9cd7b88 | 15935 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15936 | } |
15937 | ||
f9cd7b88 VS |
15938 | /* FIXME read out full plane state for all planes */ |
15939 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15940 | { |
b26d3ea3 | 15941 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15942 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15943 | to_intel_plane_state(primary->state); |
d032ffa0 | 15944 | |
19b8d387 | 15945 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15946 | primary_get_hw_state(to_intel_plane(primary)); |
15947 | ||
15948 | if (plane_state->visible) | |
15949 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15950 | } |
15951 | ||
30e984df | 15952 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 15953 | { |
fac5e23e | 15954 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 15955 | enum pipe pipe; |
24929352 DV |
15956 | struct intel_crtc *crtc; |
15957 | struct intel_encoder *encoder; | |
15958 | struct intel_connector *connector; | |
5358901f | 15959 | int i; |
24929352 | 15960 | |
565602d7 ML |
15961 | dev_priv->active_crtcs = 0; |
15962 | ||
d3fcc808 | 15963 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15964 | struct intel_crtc_state *crtc_state = crtc->config; |
15965 | int pixclk = 0; | |
3b117c8f | 15966 | |
ec2dc6a0 | 15967 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
15968 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15969 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15970 | |
565602d7 ML |
15971 | crtc_state->base.active = crtc_state->base.enable = |
15972 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15973 | ||
15974 | crtc->base.enabled = crtc_state->base.enable; | |
15975 | crtc->active = crtc_state->base.active; | |
15976 | ||
15977 | if (crtc_state->base.active) { | |
15978 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15979 | ||
c89e39f3 | 15980 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 15981 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 15982 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
15983 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
15984 | else | |
15985 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
15986 | |
15987 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15988 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
15989 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
15990 | } |
15991 | ||
15992 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15993 | |
f9cd7b88 | 15994 | readout_plane_state(crtc); |
24929352 | 15995 | |
78108b7c VS |
15996 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15997 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
15998 | crtc->active ? "enabled" : "disabled"); |
15999 | } | |
16000 | ||
5358901f DV |
16001 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16002 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16003 | ||
2edd6443 ACO |
16004 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16005 | &pll->config.hw_state); | |
3e369b76 | 16006 | pll->config.crtc_mask = 0; |
d3fcc808 | 16007 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16008 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16009 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16010 | } |
2dd66ebd | 16011 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16012 | |
1e6f2ddc | 16013 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16014 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16015 | } |
16016 | ||
b2784e15 | 16017 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16018 | pipe = 0; |
16019 | ||
16020 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16021 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16022 | encoder->base.crtc = &crtc->base; | |
253c84c8 | 16023 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16024 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16025 | } else { |
16026 | encoder->base.crtc = NULL; | |
16027 | } | |
16028 | ||
6f2bcceb | 16029 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16030 | encoder->base.base.id, |
8e329a03 | 16031 | encoder->base.name, |
24929352 | 16032 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16033 | pipe_name(pipe)); |
24929352 DV |
16034 | } |
16035 | ||
3a3371ff | 16036 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16037 | if (connector->get_hw_state(connector)) { |
16038 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16039 | |
16040 | encoder = connector->encoder; | |
16041 | connector->base.encoder = &encoder->base; | |
16042 | ||
16043 | if (encoder->base.crtc && | |
16044 | encoder->base.crtc->state->active) { | |
16045 | /* | |
16046 | * This has to be done during hardware readout | |
16047 | * because anything calling .crtc_disable may | |
16048 | * rely on the connector_mask being accurate. | |
16049 | */ | |
16050 | encoder->base.crtc->state->connector_mask |= | |
16051 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16052 | encoder->base.crtc->state->encoder_mask |= |
16053 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16054 | } |
16055 | ||
24929352 DV |
16056 | } else { |
16057 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16058 | connector->base.encoder = NULL; | |
16059 | } | |
16060 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16061 | connector->base.base.id, | |
c23cc417 | 16062 | connector->base.name, |
24929352 DV |
16063 | connector->base.encoder ? "enabled" : "disabled"); |
16064 | } | |
7f4c6284 VS |
16065 | |
16066 | for_each_intel_crtc(dev, crtc) { | |
16067 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16068 | ||
16069 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16070 | if (crtc->base.state->active) { | |
16071 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16072 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16073 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16074 | ||
16075 | /* | |
16076 | * The initial mode needs to be set in order to keep | |
16077 | * the atomic core happy. It wants a valid mode if the | |
16078 | * crtc's enabled, so we do the above call. | |
16079 | * | |
16080 | * At this point some state updated by the connectors | |
16081 | * in their ->detect() callback has not run yet, so | |
16082 | * no recalculation can be done yet. | |
16083 | * | |
16084 | * Even if we could do a recalculation and modeset | |
16085 | * right now it would cause a double modeset if | |
16086 | * fbdev or userspace chooses a different initial mode. | |
16087 | * | |
16088 | * If that happens, someone indicated they wanted a | |
16089 | * mode change, which means it's safe to do a full | |
16090 | * recalculation. | |
16091 | */ | |
16092 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16093 | |
16094 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16095 | update_scanline_offset(crtc); | |
7f4c6284 | 16096 | } |
e3b247da VS |
16097 | |
16098 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16099 | } |
30e984df DV |
16100 | } |
16101 | ||
043e9bda ML |
16102 | /* Scan out the current hw modeset state, |
16103 | * and sanitizes it to the current state | |
16104 | */ | |
16105 | static void | |
16106 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16107 | { |
fac5e23e | 16108 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16109 | enum pipe pipe; |
30e984df DV |
16110 | struct intel_crtc *crtc; |
16111 | struct intel_encoder *encoder; | |
35c95375 | 16112 | int i; |
30e984df DV |
16113 | |
16114 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16115 | |
16116 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16117 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16118 | intel_sanitize_encoder(encoder); |
16119 | } | |
16120 | ||
055e393f | 16121 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16122 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16123 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16124 | intel_dump_pipe_config(crtc, crtc->config, |
16125 | "[setup_hw_state]"); | |
24929352 | 16126 | } |
9a935856 | 16127 | |
d29b2f9d ACO |
16128 | intel_modeset_update_connector_atomic_state(dev); |
16129 | ||
35c95375 DV |
16130 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16131 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16132 | ||
2dd66ebd | 16133 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16134 | continue; |
16135 | ||
16136 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16137 | ||
2edd6443 | 16138 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16139 | pll->on = false; |
16140 | } | |
16141 | ||
666a4537 | 16142 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16143 | vlv_wm_get_hw_state(dev); |
16144 | else if (IS_GEN9(dev)) | |
3078999f PB |
16145 | skl_wm_get_hw_state(dev); |
16146 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16147 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16148 | |
16149 | for_each_intel_crtc(dev, crtc) { | |
16150 | unsigned long put_domains; | |
16151 | ||
74bff5f9 | 16152 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16153 | if (WARN_ON(put_domains)) |
16154 | modeset_put_power_domains(dev_priv, put_domains); | |
16155 | } | |
16156 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16157 | |
16158 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16159 | } |
7d0bc1ea | 16160 | |
043e9bda ML |
16161 | void intel_display_resume(struct drm_device *dev) |
16162 | { | |
e2c8b870 ML |
16163 | struct drm_i915_private *dev_priv = to_i915(dev); |
16164 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16165 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16166 | int ret; |
e2c8b870 | 16167 | bool setup = false; |
f30da187 | 16168 | |
e2c8b870 | 16169 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 16170 | |
ea49c9ac ML |
16171 | /* |
16172 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16173 | * won't be taken. Unfortunately some probed state like | |
16174 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16175 | * it here for now. | |
16176 | */ | |
16177 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16178 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16179 | |
e2c8b870 ML |
16180 | retry: |
16181 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 16182 | |
e2c8b870 ML |
16183 | if (ret == 0 && !setup) { |
16184 | setup = true; | |
043e9bda | 16185 | |
e2c8b870 ML |
16186 | intel_modeset_setup_hw_state(dev); |
16187 | i915_redisable_vga(dev); | |
45e2b5f6 | 16188 | } |
8af6cf88 | 16189 | |
e2c8b870 ML |
16190 | if (ret == 0 && state) { |
16191 | struct drm_crtc_state *crtc_state; | |
16192 | struct drm_crtc *crtc; | |
16193 | int i; | |
043e9bda | 16194 | |
e2c8b870 ML |
16195 | state->acquire_ctx = &ctx; |
16196 | ||
e3d5457c VS |
16197 | /* ignore any reset values/BIOS leftovers in the WM registers */ |
16198 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
16199 | ||
e2c8b870 ML |
16200 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
16201 | /* | |
16202 | * Force recalculation even if we restore | |
16203 | * current state. With fast modeset this may not result | |
16204 | * in a modeset when the state is compatible. | |
16205 | */ | |
16206 | crtc_state->mode_changed = true; | |
16207 | } | |
16208 | ||
16209 | ret = drm_atomic_commit(state); | |
043e9bda ML |
16210 | } |
16211 | ||
e2c8b870 ML |
16212 | if (ret == -EDEADLK) { |
16213 | drm_modeset_backoff(&ctx); | |
16214 | goto retry; | |
16215 | } | |
043e9bda | 16216 | |
e2c8b870 ML |
16217 | drm_modeset_drop_locks(&ctx); |
16218 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16219 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16220 | |
e2c8b870 ML |
16221 | if (ret) { |
16222 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16223 | drm_atomic_state_free(state); | |
16224 | } | |
2c7111db CW |
16225 | } |
16226 | ||
16227 | void intel_modeset_gem_init(struct drm_device *dev) | |
16228 | { | |
dc97997a | 16229 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 16230 | struct drm_crtc *c; |
2ff8fde1 | 16231 | struct drm_i915_gem_object *obj; |
e0d6149b | 16232 | int ret; |
484b41dd | 16233 | |
dc97997a | 16234 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16235 | |
1833b134 | 16236 | intel_modeset_init_hw(dev); |
02e792fb | 16237 | |
1ee8da6d | 16238 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16239 | |
16240 | /* | |
16241 | * Make sure any fbs we allocated at startup are properly | |
16242 | * pinned & fenced. When we do the allocation it's too early | |
16243 | * for this. | |
16244 | */ | |
70e1e0ec | 16245 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16246 | obj = intel_fb_obj(c->primary->fb); |
16247 | if (obj == NULL) | |
484b41dd JB |
16248 | continue; |
16249 | ||
e0d6149b | 16250 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16251 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16252 | c->primary->state->rotation); | |
e0d6149b TU |
16253 | mutex_unlock(&dev->struct_mutex); |
16254 | if (ret) { | |
484b41dd JB |
16255 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16256 | to_intel_crtc(c)->pipe); | |
66e514c1 | 16257 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 16258 | c->primary->fb = NULL; |
36750f28 | 16259 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 16260 | update_state_fb(c->primary); |
36750f28 | 16261 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16262 | } |
16263 | } | |
1ebaa0b9 CW |
16264 | } |
16265 | ||
16266 | int intel_connector_register(struct drm_connector *connector) | |
16267 | { | |
16268 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
16269 | int ret; | |
16270 | ||
16271 | ret = intel_backlight_device_register(intel_connector); | |
16272 | if (ret) | |
16273 | goto err; | |
16274 | ||
16275 | return 0; | |
0962c3c9 | 16276 | |
1ebaa0b9 CW |
16277 | err: |
16278 | return ret; | |
79e53945 JB |
16279 | } |
16280 | ||
c191eca1 | 16281 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 16282 | { |
e63d87c0 | 16283 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 16284 | |
e63d87c0 | 16285 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 16286 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
16287 | } |
16288 | ||
79e53945 JB |
16289 | void intel_modeset_cleanup(struct drm_device *dev) |
16290 | { | |
fac5e23e | 16291 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 16292 | |
dc97997a | 16293 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16294 | |
fd0c0642 DV |
16295 | /* |
16296 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16297 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16298 | * experience fancy races otherwise. |
16299 | */ | |
2aeb7d3a | 16300 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16301 | |
fd0c0642 DV |
16302 | /* |
16303 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16304 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16305 | */ | |
f87ea761 | 16306 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16307 | |
723bfd70 JB |
16308 | intel_unregister_dsm_handler(); |
16309 | ||
c937ab3e | 16310 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16311 | |
1630fe75 CW |
16312 | /* flush any delayed tasks or pending work */ |
16313 | flush_scheduled_work(); | |
16314 | ||
79e53945 | 16315 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16316 | |
1ee8da6d | 16317 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16318 | |
dc97997a | 16319 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16320 | |
16321 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16322 | } |
16323 | ||
df0e9248 CW |
16324 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16325 | struct intel_encoder *encoder) | |
16326 | { | |
16327 | connector->encoder = encoder; | |
16328 | drm_mode_connector_attach_encoder(&connector->base, | |
16329 | &encoder->base); | |
79e53945 | 16330 | } |
28d52043 DA |
16331 | |
16332 | /* | |
16333 | * set vga decode state - true == enable VGA decode | |
16334 | */ | |
16335 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16336 | { | |
fac5e23e | 16337 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 16338 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16339 | u16 gmch_ctrl; |
16340 | ||
75fa041d CW |
16341 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16342 | DRM_ERROR("failed to read control word\n"); | |
16343 | return -EIO; | |
16344 | } | |
16345 | ||
c0cc8a55 CW |
16346 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16347 | return 0; | |
16348 | ||
28d52043 DA |
16349 | if (state) |
16350 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16351 | else | |
16352 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16353 | |
16354 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16355 | DRM_ERROR("failed to write control word\n"); | |
16356 | return -EIO; | |
16357 | } | |
16358 | ||
28d52043 DA |
16359 | return 0; |
16360 | } | |
c4a1d9e4 | 16361 | |
c4a1d9e4 | 16362 | struct intel_display_error_state { |
ff57f1b0 PZ |
16363 | |
16364 | u32 power_well_driver; | |
16365 | ||
63b66e5b CW |
16366 | int num_transcoders; |
16367 | ||
c4a1d9e4 CW |
16368 | struct intel_cursor_error_state { |
16369 | u32 control; | |
16370 | u32 position; | |
16371 | u32 base; | |
16372 | u32 size; | |
52331309 | 16373 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16374 | |
16375 | struct intel_pipe_error_state { | |
ddf9c536 | 16376 | bool power_domain_on; |
c4a1d9e4 | 16377 | u32 source; |
f301b1e1 | 16378 | u32 stat; |
52331309 | 16379 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16380 | |
16381 | struct intel_plane_error_state { | |
16382 | u32 control; | |
16383 | u32 stride; | |
16384 | u32 size; | |
16385 | u32 pos; | |
16386 | u32 addr; | |
16387 | u32 surface; | |
16388 | u32 tile_offset; | |
52331309 | 16389 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16390 | |
16391 | struct intel_transcoder_error_state { | |
ddf9c536 | 16392 | bool power_domain_on; |
63b66e5b CW |
16393 | enum transcoder cpu_transcoder; |
16394 | ||
16395 | u32 conf; | |
16396 | ||
16397 | u32 htotal; | |
16398 | u32 hblank; | |
16399 | u32 hsync; | |
16400 | u32 vtotal; | |
16401 | u32 vblank; | |
16402 | u32 vsync; | |
16403 | } transcoder[4]; | |
c4a1d9e4 CW |
16404 | }; |
16405 | ||
16406 | struct intel_display_error_state * | |
c033666a | 16407 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16408 | { |
c4a1d9e4 | 16409 | struct intel_display_error_state *error; |
63b66e5b CW |
16410 | int transcoders[] = { |
16411 | TRANSCODER_A, | |
16412 | TRANSCODER_B, | |
16413 | TRANSCODER_C, | |
16414 | TRANSCODER_EDP, | |
16415 | }; | |
c4a1d9e4 CW |
16416 | int i; |
16417 | ||
c033666a | 16418 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16419 | return NULL; |
16420 | ||
9d1cb914 | 16421 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16422 | if (error == NULL) |
16423 | return NULL; | |
16424 | ||
c033666a | 16425 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16426 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16427 | ||
055e393f | 16428 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16429 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16430 | __intel_display_power_is_enabled(dev_priv, |
16431 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16432 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16433 | continue; |
16434 | ||
5efb3e28 VS |
16435 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16436 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16437 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16438 | |
16439 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16440 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16441 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16442 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16443 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16444 | } | |
c033666a | 16445 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16446 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16447 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16448 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16449 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16450 | } | |
16451 | ||
c4a1d9e4 | 16452 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16453 | |
c033666a | 16454 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16455 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16456 | } |
16457 | ||
4d1de975 | 16458 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16459 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16460 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16461 | error->num_transcoders++; /* Account for eDP. */ |
16462 | ||
16463 | for (i = 0; i < error->num_transcoders; i++) { | |
16464 | enum transcoder cpu_transcoder = transcoders[i]; | |
16465 | ||
ddf9c536 | 16466 | error->transcoder[i].power_domain_on = |
f458ebbc | 16467 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16468 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16469 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16470 | continue; |
16471 | ||
63b66e5b CW |
16472 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16473 | ||
16474 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16475 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16476 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16477 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16478 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16479 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16480 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16481 | } |
16482 | ||
16483 | return error; | |
16484 | } | |
16485 | ||
edc3d884 MK |
16486 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16487 | ||
c4a1d9e4 | 16488 | void |
edc3d884 | 16489 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16490 | struct drm_device *dev, |
16491 | struct intel_display_error_state *error) | |
16492 | { | |
fac5e23e | 16493 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
16494 | int i; |
16495 | ||
63b66e5b CW |
16496 | if (!error) |
16497 | return; | |
16498 | ||
edc3d884 | 16499 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16500 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16501 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16502 | error->power_well_driver); |
055e393f | 16503 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16504 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16505 | err_printf(m, " Power: %s\n", |
87ad3212 | 16506 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16507 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16508 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16509 | |
16510 | err_printf(m, "Plane [%d]:\n", i); | |
16511 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16512 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16513 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16514 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16515 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16516 | } |
4b71a570 | 16517 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16518 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16519 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16520 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16521 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16522 | } |
16523 | ||
edc3d884 MK |
16524 | err_printf(m, "Cursor [%d]:\n", i); |
16525 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16526 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16527 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16528 | } |
63b66e5b CW |
16529 | |
16530 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16531 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16532 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16533 | err_printf(m, " Power: %s\n", |
87ad3212 | 16534 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16535 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16536 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16537 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16538 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16539 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16540 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16541 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16542 | } | |
c4a1d9e4 | 16543 | } |