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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
c37efb99 | 40 | #include "i915_gem_dmabuf.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
eb1bfe80 JB |
100 | static int intel_framebuffer_init(struct drm_device *dev, |
101 | struct intel_framebuffer *ifb, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd, | |
103 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
104 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
105 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 106 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 107 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
108 | struct intel_link_m_n *m_n, |
109 | struct intel_link_m_n *m2_n2); | |
29407aab | 110 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 111 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 112 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 113 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 114 | const struct intel_crtc_state *pipe_config); |
d288f65f | 115 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 116 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
117 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
118 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
119 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 127 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 128 | |
d4906093 | 129 | struct intel_limit { |
4c5def93 ACO |
130 | struct { |
131 | int min, max; | |
132 | } dot, vco, n, m, m1, m2, p, p1; | |
133 | ||
134 | struct { | |
135 | int dot_limit; | |
136 | int p2_slow, p2_fast; | |
137 | } p2; | |
d4906093 | 138 | }; |
79e53945 | 139 | |
bfa7df01 VS |
140 | /* returns HPLL frequency in kHz */ |
141 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
142 | { | |
143 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
144 | ||
145 | /* Obtain SKU information */ | |
146 | mutex_lock(&dev_priv->sb_lock); | |
147 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
148 | CCK_FUSE_HPLL_FREQ_MASK; | |
149 | mutex_unlock(&dev_priv->sb_lock); | |
150 | ||
151 | return vco_freq[hpll_freq] * 1000; | |
152 | } | |
153 | ||
c30fec65 VS |
154 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
155 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
156 | { |
157 | u32 val; | |
158 | int divider; | |
159 | ||
bfa7df01 VS |
160 | mutex_lock(&dev_priv->sb_lock); |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
c30fec65 VS |
170 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
171 | } | |
172 | ||
173 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
174 | const char *name, u32 reg) | |
175 | { | |
176 | if (dev_priv->hpll_freq == 0) | |
177 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
178 | ||
179 | return vlv_get_cck_clock(dev_priv, name, reg, | |
180 | dev_priv->hpll_freq); | |
bfa7df01 VS |
181 | } |
182 | ||
e7dc33f3 VS |
183 | static int |
184 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 185 | { |
e7dc33f3 VS |
186 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
187 | } | |
d2acd215 | 188 | |
e7dc33f3 VS |
189 | static int |
190 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
191 | { | |
19ab4ed3 | 192 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
193 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
194 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
195 | } |
196 | ||
e7dc33f3 VS |
197 | static int |
198 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 199 | { |
79e50a4f JN |
200 | uint32_t clkcfg; |
201 | ||
e7dc33f3 | 202 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
203 | clkcfg = I915_READ(CLKCFG); |
204 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
205 | case CLKCFG_FSB_400: | |
e7dc33f3 | 206 | return 100000; |
79e50a4f | 207 | case CLKCFG_FSB_533: |
e7dc33f3 | 208 | return 133333; |
79e50a4f | 209 | case CLKCFG_FSB_667: |
e7dc33f3 | 210 | return 166667; |
79e50a4f | 211 | case CLKCFG_FSB_800: |
e7dc33f3 | 212 | return 200000; |
79e50a4f | 213 | case CLKCFG_FSB_1067: |
e7dc33f3 | 214 | return 266667; |
79e50a4f | 215 | case CLKCFG_FSB_1333: |
e7dc33f3 | 216 | return 333333; |
79e50a4f JN |
217 | /* these two are just a guess; one of them might be right */ |
218 | case CLKCFG_FSB_1600: | |
219 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 220 | return 400000; |
79e50a4f | 221 | default: |
e7dc33f3 | 222 | return 133333; |
79e50a4f JN |
223 | } |
224 | } | |
225 | ||
19ab4ed3 | 226 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
227 | { |
228 | if (HAS_PCH_SPLIT(dev_priv)) | |
229 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
230 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
231 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
232 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
233 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
234 | else | |
235 | return; /* no rawclk on other platforms, or no need to know it */ | |
236 | ||
237 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
238 | } | |
239 | ||
bfa7df01 VS |
240 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
241 | { | |
666a4537 | 242 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
243 | return; |
244 | ||
245 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
246 | CCK_CZ_CLOCK_CONTROL); | |
247 | ||
248 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
249 | } | |
250 | ||
021357ac | 251 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
252 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
253 | const struct intel_crtc_state *pipe_config) | |
021357ac | 254 | { |
21a727b3 VS |
255 | if (HAS_DDI(dev_priv)) |
256 | return pipe_config->port_clock; /* SPLL */ | |
257 | else if (IS_GEN5(dev_priv)) | |
258 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 259 | else |
21a727b3 | 260 | return 270000; |
021357ac CW |
261 | } |
262 | ||
1b6f4958 | 263 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 264 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 265 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 266 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
267 | .m = { .min = 96, .max = 140 }, |
268 | .m1 = { .min = 18, .max = 26 }, | |
269 | .m2 = { .min = 6, .max = 16 }, | |
270 | .p = { .min = 4, .max = 128 }, | |
271 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 165000, |
273 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
274 | }; |
275 | ||
1b6f4958 | 276 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 277 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 278 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 279 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
280 | .m = { .min = 96, .max = 140 }, |
281 | .m1 = { .min = 18, .max = 26 }, | |
282 | .m2 = { .min = 6, .max = 16 }, | |
283 | .p = { .min = 4, .max = 128 }, | |
284 | .p1 = { .min = 2, .max = 33 }, | |
285 | .p2 = { .dot_limit = 165000, | |
286 | .p2_slow = 4, .p2_fast = 4 }, | |
287 | }; | |
288 | ||
1b6f4958 | 289 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 290 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 291 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 292 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
293 | .m = { .min = 96, .max = 140 }, |
294 | .m1 = { .min = 18, .max = 26 }, | |
295 | .m2 = { .min = 6, .max = 16 }, | |
296 | .p = { .min = 4, .max = 128 }, | |
297 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 165000, |
299 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 300 | }; |
273e27ca | 301 | |
1b6f4958 | 302 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
303 | .dot = { .min = 20000, .max = 400000 }, |
304 | .vco = { .min = 1400000, .max = 2800000 }, | |
305 | .n = { .min = 1, .max = 6 }, | |
306 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
307 | .m1 = { .min = 8, .max = 18 }, |
308 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
309 | .p = { .min = 5, .max = 80 }, |
310 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
311 | .p2 = { .dot_limit = 200000, |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
1b6f4958 | 315 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
316 | .dot = { .min = 20000, .max = 400000 }, |
317 | .vco = { .min = 1400000, .max = 2800000 }, | |
318 | .n = { .min = 1, .max = 6 }, | |
319 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
320 | .m1 = { .min = 8, .max = 18 }, |
321 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
322 | .p = { .min = 7, .max = 98 }, |
323 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
324 | .p2 = { .dot_limit = 112000, |
325 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
326 | }; |
327 | ||
273e27ca | 328 | |
1b6f4958 | 329 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 270000 }, |
331 | .vco = { .min = 1750000, .max = 3500000}, | |
332 | .n = { .min = 1, .max = 4 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 10, .max = 30 }, | |
337 | .p1 = { .min = 1, .max = 3}, | |
338 | .p2 = { .dot_limit = 270000, | |
339 | .p2_slow = 10, | |
340 | .p2_fast = 10 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
1b6f4958 | 344 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
345 | .dot = { .min = 22000, .max = 400000 }, |
346 | .vco = { .min = 1750000, .max = 3500000}, | |
347 | .n = { .min = 1, .max = 4 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 16, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 5, .max = 80 }, | |
352 | .p1 = { .min = 1, .max = 8}, | |
353 | .p2 = { .dot_limit = 165000, | |
354 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
355 | }; |
356 | ||
1b6f4958 | 357 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
358 | .dot = { .min = 20000, .max = 115000 }, |
359 | .vco = { .min = 1750000, .max = 3500000 }, | |
360 | .n = { .min = 1, .max = 3 }, | |
361 | .m = { .min = 104, .max = 138 }, | |
362 | .m1 = { .min = 17, .max = 23 }, | |
363 | .m2 = { .min = 5, .max = 11 }, | |
364 | .p = { .min = 28, .max = 112 }, | |
365 | .p1 = { .min = 2, .max = 8 }, | |
366 | .p2 = { .dot_limit = 0, | |
367 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 368 | }, |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
372 | .dot = { .min = 80000, .max = 224000 }, |
373 | .vco = { .min = 1750000, .max = 3500000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 104, .max = 138 }, | |
376 | .m1 = { .min = 17, .max = 23 }, | |
377 | .m2 = { .min = 5, .max = 11 }, | |
378 | .p = { .min = 14, .max = 42 }, | |
379 | .p1 = { .min = 2, .max = 6 }, | |
380 | .p2 = { .dot_limit = 0, | |
381 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 382 | }, |
e4b36699 KP |
383 | }; |
384 | ||
1b6f4958 | 385 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
386 | .dot = { .min = 20000, .max = 400000}, |
387 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 388 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
389 | .n = { .min = 3, .max = 6 }, |
390 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 391 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
392 | .m1 = { .min = 0, .max = 0 }, |
393 | .m2 = { .min = 0, .max = 254 }, | |
394 | .p = { .min = 5, .max = 80 }, | |
395 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
396 | .p2 = { .dot_limit = 200000, |
397 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
398 | }; |
399 | ||
1b6f4958 | 400 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
401 | .dot = { .min = 20000, .max = 400000 }, |
402 | .vco = { .min = 1700000, .max = 3500000 }, | |
403 | .n = { .min = 3, .max = 6 }, | |
404 | .m = { .min = 2, .max = 256 }, | |
405 | .m1 = { .min = 0, .max = 0 }, | |
406 | .m2 = { .min = 0, .max = 254 }, | |
407 | .p = { .min = 7, .max = 112 }, | |
408 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
409 | .p2 = { .dot_limit = 112000, |
410 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
411 | }; |
412 | ||
273e27ca EA |
413 | /* Ironlake / Sandybridge |
414 | * | |
415 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
416 | * the range value for them is (actual_value - 2). | |
417 | */ | |
1b6f4958 | 418 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
419 | .dot = { .min = 25000, .max = 350000 }, |
420 | .vco = { .min = 1760000, .max = 3510000 }, | |
421 | .n = { .min = 1, .max = 5 }, | |
422 | .m = { .min = 79, .max = 127 }, | |
423 | .m1 = { .min = 12, .max = 22 }, | |
424 | .m2 = { .min = 5, .max = 9 }, | |
425 | .p = { .min = 5, .max = 80 }, | |
426 | .p1 = { .min = 1, .max = 8 }, | |
427 | .p2 = { .dot_limit = 225000, | |
428 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
429 | }; |
430 | ||
1b6f4958 | 431 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 3 }, | |
435 | .m = { .min = 79, .max = 118 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
439 | .p1 = { .min = 2, .max = 8 }, | |
440 | .p2 = { .dot_limit = 225000, | |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
1b6f4958 | 444 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 127 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 56 }, | |
452 | .p1 = { .min = 2, .max = 8 }, | |
453 | .p2 = { .dot_limit = 225000, | |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
455 | }; |
456 | ||
273e27ca | 457 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 458 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
459 | .dot = { .min = 25000, .max = 350000 }, |
460 | .vco = { .min = 1760000, .max = 3510000 }, | |
461 | .n = { .min = 1, .max = 2 }, | |
462 | .m = { .min = 79, .max = 126 }, | |
463 | .m1 = { .min = 12, .max = 22 }, | |
464 | .m2 = { .min = 5, .max = 9 }, | |
465 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 466 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
467 | .p2 = { .dot_limit = 225000, |
468 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
469 | }; |
470 | ||
1b6f4958 | 471 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
472 | .dot = { .min = 25000, .max = 350000 }, |
473 | .vco = { .min = 1760000, .max = 3510000 }, | |
474 | .n = { .min = 1, .max = 3 }, | |
475 | .m = { .min = 79, .max = 126 }, | |
476 | .m1 = { .min = 12, .max = 22 }, | |
477 | .m2 = { .min = 5, .max = 9 }, | |
478 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 479 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
480 | .p2 = { .dot_limit = 225000, |
481 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
482 | }; |
483 | ||
1b6f4958 | 484 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
485 | /* |
486 | * These are the data rate limits (measured in fast clocks) | |
487 | * since those are the strictest limits we have. The fast | |
488 | * clock and actual rate limits are more relaxed, so checking | |
489 | * them would make no difference. | |
490 | */ | |
491 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 492 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 493 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
494 | .m1 = { .min = 2, .max = 3 }, |
495 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 496 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 497 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
498 | }; |
499 | ||
1b6f4958 | 500 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
501 | /* |
502 | * These are the data rate limits (measured in fast clocks) | |
503 | * since those are the strictest limits we have. The fast | |
504 | * clock and actual rate limits are more relaxed, so checking | |
505 | * them would make no difference. | |
506 | */ | |
507 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 508 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
509 | .n = { .min = 1, .max = 1 }, |
510 | .m1 = { .min = 2, .max = 2 }, | |
511 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
514 | }; | |
515 | ||
1b6f4958 | 516 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
517 | /* FIXME: find real dot limits */ |
518 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 519 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
520 | .n = { .min = 1, .max = 1 }, |
521 | .m1 = { .min = 2, .max = 2 }, | |
522 | /* FIXME: find real m2 limits */ | |
523 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
524 | .p1 = { .min = 2, .max = 4 }, | |
525 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
526 | }; | |
527 | ||
cdba954e ACO |
528 | static bool |
529 | needs_modeset(struct drm_crtc_state *state) | |
530 | { | |
fc596660 | 531 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
532 | } |
533 | ||
dccbea3b ID |
534 | /* |
535 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
536 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
537 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
538 | * The helpers' return value is the rate of the clock that is fed to the | |
539 | * display engine's pipe which can be the above fast dot clock rate or a | |
540 | * divided-down version of it. | |
541 | */ | |
f2b115e6 | 542 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 543 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 544 | { |
2177832f SL |
545 | clock->m = clock->m2 + 2; |
546 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 547 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 548 | return 0; |
fb03ac01 VS |
549 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
550 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
551 | |
552 | return clock->dot; | |
2177832f SL |
553 | } |
554 | ||
7429e9d4 DV |
555 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
556 | { | |
557 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
558 | } | |
559 | ||
9e2c8475 | 560 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 561 | { |
7429e9d4 | 562 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 563 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 564 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 565 | return 0; |
fb03ac01 VS |
566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
568 | |
569 | return clock->dot; | |
79e53945 JB |
570 | } |
571 | ||
9e2c8475 | 572 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
573 | { |
574 | clock->m = clock->m1 * clock->m2; | |
575 | clock->p = clock->p1 * clock->p2; | |
576 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 577 | return 0; |
589eca67 ID |
578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
580 | |
581 | return clock->dot / 5; | |
589eca67 ID |
582 | } |
583 | ||
9e2c8475 | 584 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
585 | { |
586 | clock->m = clock->m1 * clock->m2; | |
587 | clock->p = clock->p1 * clock->p2; | |
588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 589 | return 0; |
ef9348c8 CML |
590 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
591 | clock->n << 22); | |
592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
593 | |
594 | return clock->dot / 5; | |
ef9348c8 CML |
595 | } |
596 | ||
7c04d1d9 | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
598 | /** |
599 | * Returns whether the given set of divisors are valid for a given refclk with | |
600 | * the given connectors. | |
601 | */ | |
602 | ||
1b894b59 | 603 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 604 | const struct intel_limit *limit, |
9e2c8475 | 605 | const struct dpll *clock) |
79e53945 | 606 | { |
f01b7962 VS |
607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
608 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 612 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 614 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 615 | |
666a4537 WB |
616 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
617 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
666a4537 | 621 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
623 | INTELPllInvalid("p out of range\n"); | |
624 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
625 | INTELPllInvalid("m out of range\n"); | |
626 | } | |
627 | ||
79e53945 | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 629 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
631 | * connector, etc., rather than just a single range. | |
632 | */ | |
633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 634 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
635 | |
636 | return true; | |
637 | } | |
638 | ||
3b1429d9 | 639 | static int |
1b6f4958 | 640 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
641 | const struct intel_crtc_state *crtc_state, |
642 | int target) | |
79e53945 | 643 | { |
3b1429d9 | 644 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 645 | |
2d84d2b3 | 646 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 647 | /* |
a210b028 DV |
648 | * For LVDS just rely on its current settings for dual-channel. |
649 | * We haven't figured out how to reliably set up different | |
650 | * single/dual channel state, if we even can. | |
79e53945 | 651 | */ |
1974cad0 | 652 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 653 | return limit->p2.p2_fast; |
79e53945 | 654 | else |
3b1429d9 | 655 | return limit->p2.p2_slow; |
79e53945 JB |
656 | } else { |
657 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 658 | return limit->p2.p2_slow; |
79e53945 | 659 | else |
3b1429d9 | 660 | return limit->p2.p2_fast; |
79e53945 | 661 | } |
3b1429d9 VS |
662 | } |
663 | ||
70e8aa21 ACO |
664 | /* |
665 | * Returns a set of divisors for the desired target clock with the given | |
666 | * refclk, or FALSE. The returned values represent the clock equation: | |
667 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
668 | * | |
669 | * Target and reference clocks are specified in kHz. | |
670 | * | |
671 | * If match_clock is provided, then best_clock P divider must match the P | |
672 | * divider from @match_clock used for LVDS downclocking. | |
673 | */ | |
3b1429d9 | 674 | static bool |
1b6f4958 | 675 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 676 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
677 | int target, int refclk, struct dpll *match_clock, |
678 | struct dpll *best_clock) | |
3b1429d9 VS |
679 | { |
680 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 681 | struct dpll clock; |
3b1429d9 | 682 | int err = target; |
79e53945 | 683 | |
0206e353 | 684 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 685 | |
3b1429d9 VS |
686 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
687 | ||
42158660 ZY |
688 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
689 | clock.m1++) { | |
690 | for (clock.m2 = limit->m2.min; | |
691 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 692 | if (clock.m2 >= clock.m1) |
42158660 ZY |
693 | break; |
694 | for (clock.n = limit->n.min; | |
695 | clock.n <= limit->n.max; clock.n++) { | |
696 | for (clock.p1 = limit->p1.min; | |
697 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
698 | int this_err; |
699 | ||
dccbea3b | 700 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
701 | if (!intel_PLL_is_valid(dev, limit, |
702 | &clock)) | |
703 | continue; | |
704 | if (match_clock && | |
705 | clock.p != match_clock->p) | |
706 | continue; | |
707 | ||
708 | this_err = abs(clock.dot - target); | |
709 | if (this_err < err) { | |
710 | *best_clock = clock; | |
711 | err = this_err; | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | return (err != target); | |
719 | } | |
720 | ||
70e8aa21 ACO |
721 | /* |
722 | * Returns a set of divisors for the desired target clock with the given | |
723 | * refclk, or FALSE. The returned values represent the clock equation: | |
724 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
725 | * | |
726 | * Target and reference clocks are specified in kHz. | |
727 | * | |
728 | * If match_clock is provided, then best_clock P divider must match the P | |
729 | * divider from @match_clock used for LVDS downclocking. | |
730 | */ | |
ac58c3f0 | 731 | static bool |
1b6f4958 | 732 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 733 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
734 | int target, int refclk, struct dpll *match_clock, |
735 | struct dpll *best_clock) | |
79e53945 | 736 | { |
3b1429d9 | 737 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 738 | struct dpll clock; |
79e53945 JB |
739 | int err = target; |
740 | ||
0206e353 | 741 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 742 | |
3b1429d9 VS |
743 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
744 | ||
42158660 ZY |
745 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
746 | clock.m1++) { | |
747 | for (clock.m2 = limit->m2.min; | |
748 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
749 | for (clock.n = limit->n.min; |
750 | clock.n <= limit->n.max; clock.n++) { | |
751 | for (clock.p1 = limit->p1.min; | |
752 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
753 | int this_err; |
754 | ||
dccbea3b | 755 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
756 | if (!intel_PLL_is_valid(dev, limit, |
757 | &clock)) | |
79e53945 | 758 | continue; |
cec2f356 SP |
759 | if (match_clock && |
760 | clock.p != match_clock->p) | |
761 | continue; | |
79e53945 JB |
762 | |
763 | this_err = abs(clock.dot - target); | |
764 | if (this_err < err) { | |
765 | *best_clock = clock; | |
766 | err = this_err; | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | } | |
772 | ||
773 | return (err != target); | |
774 | } | |
775 | ||
997c030c ACO |
776 | /* |
777 | * Returns a set of divisors for the desired target clock with the given | |
778 | * refclk, or FALSE. The returned values represent the clock equation: | |
779 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
780 | * |
781 | * Target and reference clocks are specified in kHz. | |
782 | * | |
783 | * If match_clock is provided, then best_clock P divider must match the P | |
784 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 785 | */ |
d4906093 | 786 | static bool |
1b6f4958 | 787 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 788 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
789 | int target, int refclk, struct dpll *match_clock, |
790 | struct dpll *best_clock) | |
d4906093 | 791 | { |
3b1429d9 | 792 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 793 | struct dpll clock; |
d4906093 | 794 | int max_n; |
3b1429d9 | 795 | bool found = false; |
6ba770dc AJ |
796 | /* approximately equals target * 0.00585 */ |
797 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
798 | |
799 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
800 | |
801 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
802 | ||
d4906093 | 803 | max_n = limit->n.max; |
f77f13e2 | 804 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 805 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 806 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
807 | for (clock.m1 = limit->m1.max; |
808 | clock.m1 >= limit->m1.min; clock.m1--) { | |
809 | for (clock.m2 = limit->m2.max; | |
810 | clock.m2 >= limit->m2.min; clock.m2--) { | |
811 | for (clock.p1 = limit->p1.max; | |
812 | clock.p1 >= limit->p1.min; clock.p1--) { | |
813 | int this_err; | |
814 | ||
dccbea3b | 815 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
816 | if (!intel_PLL_is_valid(dev, limit, |
817 | &clock)) | |
d4906093 | 818 | continue; |
1b894b59 CW |
819 | |
820 | this_err = abs(clock.dot - target); | |
d4906093 ML |
821 | if (this_err < err_most) { |
822 | *best_clock = clock; | |
823 | err_most = this_err; | |
824 | max_n = clock.n; | |
825 | found = true; | |
826 | } | |
827 | } | |
828 | } | |
829 | } | |
830 | } | |
2c07245f ZW |
831 | return found; |
832 | } | |
833 | ||
d5dd62bd ID |
834 | /* |
835 | * Check if the calculated PLL configuration is more optimal compared to the | |
836 | * best configuration and error found so far. Return the calculated error. | |
837 | */ | |
838 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
839 | const struct dpll *calculated_clock, |
840 | const struct dpll *best_clock, | |
d5dd62bd ID |
841 | unsigned int best_error_ppm, |
842 | unsigned int *error_ppm) | |
843 | { | |
9ca3ba01 ID |
844 | /* |
845 | * For CHV ignore the error and consider only the P value. | |
846 | * Prefer a bigger P value based on HW requirements. | |
847 | */ | |
848 | if (IS_CHERRYVIEW(dev)) { | |
849 | *error_ppm = 0; | |
850 | ||
851 | return calculated_clock->p > best_clock->p; | |
852 | } | |
853 | ||
24be4e46 ID |
854 | if (WARN_ON_ONCE(!target_freq)) |
855 | return false; | |
856 | ||
d5dd62bd ID |
857 | *error_ppm = div_u64(1000000ULL * |
858 | abs(target_freq - calculated_clock->dot), | |
859 | target_freq); | |
860 | /* | |
861 | * Prefer a better P value over a better (smaller) error if the error | |
862 | * is small. Ensure this preference for future configurations too by | |
863 | * setting the error to 0. | |
864 | */ | |
865 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
866 | *error_ppm = 0; | |
867 | ||
868 | return true; | |
869 | } | |
870 | ||
871 | return *error_ppm + 10 < best_error_ppm; | |
872 | } | |
873 | ||
65b3d6a9 ACO |
874 | /* |
875 | * Returns a set of divisors for the desired target clock with the given | |
876 | * refclk, or FALSE. The returned values represent the clock equation: | |
877 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
878 | */ | |
a0c4da24 | 879 | static bool |
1b6f4958 | 880 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 881 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
882 | int target, int refclk, struct dpll *match_clock, |
883 | struct dpll *best_clock) | |
a0c4da24 | 884 | { |
a93e255f | 885 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 886 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 887 | struct dpll clock; |
69e4f900 | 888 | unsigned int bestppm = 1000000; |
27e639bf VS |
889 | /* min update 19.2 MHz */ |
890 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 891 | bool found = false; |
a0c4da24 | 892 | |
6b4bf1c4 VS |
893 | target *= 5; /* fast clock */ |
894 | ||
895 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
896 | |
897 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 898 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 899 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 900 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 901 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 902 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 903 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 904 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 905 | unsigned int ppm; |
69e4f900 | 906 | |
6b4bf1c4 VS |
907 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
908 | refclk * clock.m1); | |
909 | ||
dccbea3b | 910 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 911 | |
f01b7962 VS |
912 | if (!intel_PLL_is_valid(dev, limit, |
913 | &clock)) | |
43b0ac53 VS |
914 | continue; |
915 | ||
d5dd62bd ID |
916 | if (!vlv_PLL_is_optimal(dev, target, |
917 | &clock, | |
918 | best_clock, | |
919 | bestppm, &ppm)) | |
920 | continue; | |
6b4bf1c4 | 921 | |
d5dd62bd ID |
922 | *best_clock = clock; |
923 | bestppm = ppm; | |
924 | found = true; | |
a0c4da24 JB |
925 | } |
926 | } | |
927 | } | |
928 | } | |
a0c4da24 | 929 | |
49e497ef | 930 | return found; |
a0c4da24 | 931 | } |
a4fc5ed6 | 932 | |
65b3d6a9 ACO |
933 | /* |
934 | * Returns a set of divisors for the desired target clock with the given | |
935 | * refclk, or FALSE. The returned values represent the clock equation: | |
936 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
937 | */ | |
ef9348c8 | 938 | static bool |
1b6f4958 | 939 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 940 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
941 | int target, int refclk, struct dpll *match_clock, |
942 | struct dpll *best_clock) | |
ef9348c8 | 943 | { |
a93e255f | 944 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 945 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 946 | unsigned int best_error_ppm; |
9e2c8475 | 947 | struct dpll clock; |
ef9348c8 CML |
948 | uint64_t m2; |
949 | int found = false; | |
950 | ||
951 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 952 | best_error_ppm = 1000000; |
ef9348c8 CML |
953 | |
954 | /* | |
955 | * Based on hardware doc, the n always set to 1, and m1 always | |
956 | * set to 2. If requires to support 200Mhz refclk, we need to | |
957 | * revisit this because n may not 1 anymore. | |
958 | */ | |
959 | clock.n = 1, clock.m1 = 2; | |
960 | target *= 5; /* fast clock */ | |
961 | ||
962 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
963 | for (clock.p2 = limit->p2.p2_fast; | |
964 | clock.p2 >= limit->p2.p2_slow; | |
965 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 966 | unsigned int error_ppm; |
ef9348c8 CML |
967 | |
968 | clock.p = clock.p1 * clock.p2; | |
969 | ||
970 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
971 | clock.n) << 22, refclk * clock.m1); | |
972 | ||
973 | if (m2 > INT_MAX/clock.m1) | |
974 | continue; | |
975 | ||
976 | clock.m2 = m2; | |
977 | ||
dccbea3b | 978 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
979 | |
980 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
981 | continue; | |
982 | ||
9ca3ba01 ID |
983 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
984 | best_error_ppm, &error_ppm)) | |
985 | continue; | |
986 | ||
987 | *best_clock = clock; | |
988 | best_error_ppm = error_ppm; | |
989 | found = true; | |
ef9348c8 CML |
990 | } |
991 | } | |
992 | ||
993 | return found; | |
994 | } | |
995 | ||
5ab7b0b7 | 996 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 997 | struct dpll *best_clock) |
5ab7b0b7 | 998 | { |
65b3d6a9 | 999 | int refclk = 100000; |
1b6f4958 | 1000 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1001 | |
65b3d6a9 | 1002 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1003 | target_clock, refclk, NULL, best_clock); |
1004 | } | |
1005 | ||
20ddf665 VS |
1006 | bool intel_crtc_active(struct drm_crtc *crtc) |
1007 | { | |
1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1009 | ||
1010 | /* Be paranoid as we can arrive here with only partial | |
1011 | * state retrieved from the hardware during setup. | |
1012 | * | |
241bfc38 | 1013 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1014 | * as Haswell has gained clock readout/fastboot support. |
1015 | * | |
66e514c1 | 1016 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1017 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1018 | * |
1019 | * FIXME: The intel_crtc->active here should be switched to | |
1020 | * crtc->state->active once we have proper CRTC states wired up | |
1021 | * for atomic. | |
20ddf665 | 1022 | */ |
c3d1f436 | 1023 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1024 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1025 | } |
1026 | ||
a5c961d1 PZ |
1027 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1028 | enum pipe pipe) | |
1029 | { | |
1030 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1032 | ||
6e3c9717 | 1033 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1034 | } |
1035 | ||
fbf49ea2 VS |
1036 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1037 | { | |
fac5e23e | 1038 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1039 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1040 | u32 line1, line2; |
1041 | u32 line_mask; | |
1042 | ||
1043 | if (IS_GEN2(dev)) | |
1044 | line_mask = DSL_LINEMASK_GEN2; | |
1045 | else | |
1046 | line_mask = DSL_LINEMASK_GEN3; | |
1047 | ||
1048 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1049 | msleep(5); |
fbf49ea2 VS |
1050 | line2 = I915_READ(reg) & line_mask; |
1051 | ||
1052 | return line1 == line2; | |
1053 | } | |
1054 | ||
ab7ad7f6 KP |
1055 | /* |
1056 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1057 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1058 | * |
1059 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1060 | * spinning on the vblank interrupt status bit, since we won't actually | |
1061 | * see an interrupt when the pipe is disabled. | |
1062 | * | |
ab7ad7f6 KP |
1063 | * On Gen4 and above: |
1064 | * wait for the pipe register state bit to turn off | |
1065 | * | |
1066 | * Otherwise: | |
1067 | * wait for the display line value to settle (it usually | |
1068 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1069 | * |
9d0498a2 | 1070 | */ |
575f7ab7 | 1071 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1072 | { |
575f7ab7 | 1073 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1074 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1075 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1076 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1077 | |
1078 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1079 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1080 | |
1081 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1082 | if (intel_wait_for_register(dev_priv, |
1083 | reg, I965_PIPECONF_ACTIVE, 0, | |
1084 | 100)) | |
284637d9 | 1085 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1086 | } else { |
ab7ad7f6 | 1087 | /* Wait for the display line to settle */ |
fbf49ea2 | 1088 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1089 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1090 | } |
79e53945 JB |
1091 | } |
1092 | ||
b24e7179 | 1093 | /* Only for pre-ILK configs */ |
55607e8a DV |
1094 | void assert_pll(struct drm_i915_private *dev_priv, |
1095 | enum pipe pipe, bool state) | |
b24e7179 | 1096 | { |
b24e7179 JB |
1097 | u32 val; |
1098 | bool cur_state; | |
1099 | ||
649636ef | 1100 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1101 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1102 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1103 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1104 | onoff(state), onoff(cur_state)); |
b24e7179 | 1105 | } |
b24e7179 | 1106 | |
23538ef1 | 1107 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1108 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1109 | { |
1110 | u32 val; | |
1111 | bool cur_state; | |
1112 | ||
a580516d | 1113 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1114 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1115 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1116 | |
1117 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1119 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
23538ef1 | 1121 | } |
23538ef1 | 1122 | |
040484af JB |
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe, bool state) | |
1125 | { | |
040484af | 1126 | bool cur_state; |
ad80a810 PZ |
1127 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1128 | pipe); | |
040484af | 1129 | |
2d1fe073 | 1130 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1131 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1132 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1133 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1134 | } else { |
649636ef | 1135 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1136 | cur_state = !!(val & FDI_TX_ENABLE); |
1137 | } | |
e2c719b7 | 1138 | I915_STATE_WARN(cur_state != state, |
040484af | 1139 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1140 | onoff(state), onoff(cur_state)); |
040484af JB |
1141 | } |
1142 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1143 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe, bool state) | |
1147 | { | |
040484af JB |
1148 | u32 val; |
1149 | bool cur_state; | |
1150 | ||
649636ef | 1151 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1152 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
040484af | 1154 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1155 | onoff(state), onoff(cur_state)); |
040484af JB |
1156 | } |
1157 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1158 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1159 | ||
1160 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1161 | enum pipe pipe) | |
1162 | { | |
040484af JB |
1163 | u32 val; |
1164 | ||
1165 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1166 | if (IS_GEN5(dev_priv)) |
040484af JB |
1167 | return; |
1168 | ||
bf507ef7 | 1169 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1170 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1171 | return; |
1172 | ||
649636ef | 1173 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1174 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1175 | } |
1176 | ||
55607e8a DV |
1177 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1178 | enum pipe pipe, bool state) | |
040484af | 1179 | { |
040484af | 1180 | u32 val; |
55607e8a | 1181 | bool cur_state; |
040484af | 1182 | |
649636ef | 1183 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1184 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1186 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1187 | onoff(state), onoff(cur_state)); |
040484af JB |
1188 | } |
1189 | ||
b680c37a DV |
1190 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1191 | enum pipe pipe) | |
ea0760cf | 1192 | { |
91c8a326 | 1193 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 | 1194 | i915_reg_t pp_reg; |
ea0760cf JB |
1195 | u32 val; |
1196 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1197 | bool locked = true; |
ea0760cf | 1198 | |
bedd4dba JN |
1199 | if (WARN_ON(HAS_DDI(dev))) |
1200 | return; | |
1201 | ||
1202 | if (HAS_PCH_SPLIT(dev)) { | |
1203 | u32 port_sel; | |
1204 | ||
44cb734c ID |
1205 | pp_reg = PP_CONTROL(0); |
1206 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1207 | |
1208 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1209 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1210 | panel_pipe = PIPE_B; | |
1211 | /* XXX: else fix for eDP */ | |
666a4537 | 1212 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba | 1213 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1214 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1215 | panel_pipe = pipe; |
ea0760cf | 1216 | } else { |
44cb734c | 1217 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1218 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1219 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1220 | } |
1221 | ||
1222 | val = I915_READ(pp_reg); | |
1223 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1224 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1225 | locked = false; |
1226 | ||
e2c719b7 | 1227 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1228 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1229 | pipe_name(pipe)); |
ea0760cf JB |
1230 | } |
1231 | ||
93ce0ba6 JN |
1232 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe, bool state) | |
1234 | { | |
91c8a326 | 1235 | struct drm_device *dev = &dev_priv->drm; |
93ce0ba6 JN |
1236 | bool cur_state; |
1237 | ||
d9d82081 | 1238 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1239 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1240 | else |
5efb3e28 | 1241 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1242 | |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1244 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1246 | } |
1247 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1248 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1249 | ||
b840d907 JB |
1250 | void assert_pipe(struct drm_i915_private *dev_priv, |
1251 | enum pipe pipe, bool state) | |
b24e7179 | 1252 | { |
63d7bbe9 | 1253 | bool cur_state; |
702e7a56 PZ |
1254 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1255 | pipe); | |
4feed0eb | 1256 | enum intel_display_power_domain power_domain; |
b24e7179 | 1257 | |
b6b5d049 VS |
1258 | /* if we need the pipe quirk it must be always on */ |
1259 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1260 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1261 | state = true; |
1262 | ||
4feed0eb ID |
1263 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1264 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1265 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1266 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1267 | |
1268 | intel_display_power_put(dev_priv, power_domain); | |
1269 | } else { | |
1270 | cur_state = false; | |
69310161 PZ |
1271 | } |
1272 | ||
e2c719b7 | 1273 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1274 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1275 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1276 | } |
1277 | ||
931872fc CW |
1278 | static void assert_plane(struct drm_i915_private *dev_priv, |
1279 | enum plane plane, bool state) | |
b24e7179 | 1280 | { |
b24e7179 | 1281 | u32 val; |
931872fc | 1282 | bool cur_state; |
b24e7179 | 1283 | |
649636ef | 1284 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1285 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1286 | I915_STATE_WARN(cur_state != state, |
931872fc | 1287 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1288 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1289 | } |
1290 | ||
931872fc CW |
1291 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1292 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1293 | ||
b24e7179 JB |
1294 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
1296 | { | |
91c8a326 | 1297 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1298 | int i; |
b24e7179 | 1299 | |
653e1026 VS |
1300 | /* Primary planes are fixed to pipes on gen4+ */ |
1301 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1302 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1303 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1304 | "plane %c assertion failure, should be disabled but not\n", |
1305 | plane_name(pipe)); | |
19ec1358 | 1306 | return; |
28c05794 | 1307 | } |
19ec1358 | 1308 | |
b24e7179 | 1309 | /* Need to check both planes against the pipe */ |
055e393f | 1310 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1311 | u32 val = I915_READ(DSPCNTR(i)); |
1312 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1313 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1314 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1315 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1316 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1317 | } |
1318 | } | |
1319 | ||
19332d7a JB |
1320 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1321 | enum pipe pipe) | |
1322 | { | |
91c8a326 | 1323 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1324 | int sprite; |
19332d7a | 1325 | |
7feb8b88 | 1326 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1327 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1328 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1329 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1330 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1331 | sprite, pipe_name(pipe)); | |
1332 | } | |
666a4537 | 1333 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1334 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1335 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1336 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1337 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1338 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1339 | } |
1340 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1341 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1342 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1343 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1344 | plane_name(pipe), pipe_name(pipe)); |
1345 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1346 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1347 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1348 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1349 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1350 | } |
1351 | } | |
1352 | ||
08c71e5e VS |
1353 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1354 | { | |
e2c719b7 | 1355 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1356 | drm_crtc_vblank_put(crtc); |
1357 | } | |
1358 | ||
7abd4b35 ACO |
1359 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1360 | enum pipe pipe) | |
92f2584a | 1361 | { |
92f2584a JB |
1362 | u32 val; |
1363 | bool enabled; | |
1364 | ||
649636ef | 1365 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1366 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1367 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1368 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1369 | pipe_name(pipe)); | |
92f2584a JB |
1370 | } |
1371 | ||
4e634389 KP |
1372 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1373 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1374 | { |
1375 | if ((val & DP_PORT_EN) == 0) | |
1376 | return false; | |
1377 | ||
2d1fe073 | 1378 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1379 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1380 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1381 | return false; | |
2d1fe073 | 1382 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1383 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1384 | return false; | |
f0575e92 KP |
1385 | } else { |
1386 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1387 | return false; | |
1388 | } | |
1389 | return true; | |
1390 | } | |
1391 | ||
1519b995 KP |
1392 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1393 | enum pipe pipe, u32 val) | |
1394 | { | |
dc0fa718 | 1395 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1396 | return false; |
1397 | ||
2d1fe073 | 1398 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1399 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1400 | return false; |
2d1fe073 | 1401 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1402 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1403 | return false; | |
1519b995 | 1404 | } else { |
dc0fa718 | 1405 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1406 | return false; |
1407 | } | |
1408 | return true; | |
1409 | } | |
1410 | ||
1411 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1412 | enum pipe pipe, u32 val) | |
1413 | { | |
1414 | if ((val & LVDS_PORT_EN) == 0) | |
1415 | return false; | |
1416 | ||
2d1fe073 | 1417 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1418 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1419 | return false; | |
1420 | } else { | |
1421 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1422 | return false; | |
1423 | } | |
1424 | return true; | |
1425 | } | |
1426 | ||
1427 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1428 | enum pipe pipe, u32 val) | |
1429 | { | |
1430 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1431 | return false; | |
2d1fe073 | 1432 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1433 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1434 | return false; | |
1435 | } else { | |
1436 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1437 | return false; | |
1438 | } | |
1439 | return true; | |
1440 | } | |
1441 | ||
291906f1 | 1442 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1443 | enum pipe pipe, i915_reg_t reg, |
1444 | u32 port_sel) | |
291906f1 | 1445 | { |
47a05eca | 1446 | u32 val = I915_READ(reg); |
e2c719b7 | 1447 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1448 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1449 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1450 | |
2d1fe073 | 1451 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1452 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1453 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1454 | } |
1455 | ||
1456 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1457 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1458 | { |
47a05eca | 1459 | u32 val = I915_READ(reg); |
e2c719b7 | 1460 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1461 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1462 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1463 | |
2d1fe073 | 1464 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1465 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1466 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1467 | } |
1468 | ||
1469 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1470 | enum pipe pipe) | |
1471 | { | |
291906f1 | 1472 | u32 val; |
291906f1 | 1473 | |
f0575e92 KP |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1476 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1477 | |
649636ef | 1478 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1479 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1480 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1481 | pipe_name(pipe)); |
291906f1 | 1482 | |
649636ef | 1483 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1484 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1485 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1486 | pipe_name(pipe)); |
291906f1 | 1487 | |
e2debe91 PZ |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1491 | } |
1492 | ||
cd2d34d9 VS |
1493 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1494 | const struct intel_crtc_state *pipe_config) | |
1495 | { | |
1496 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1497 | enum pipe pipe = crtc->pipe; | |
1498 | ||
1499 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1500 | POSTING_READ(DPLL(pipe)); | |
1501 | udelay(150); | |
1502 | ||
2c30b43b CW |
1503 | if (intel_wait_for_register(dev_priv, |
1504 | DPLL(pipe), | |
1505 | DPLL_LOCK_VLV, | |
1506 | DPLL_LOCK_VLV, | |
1507 | 1)) | |
cd2d34d9 VS |
1508 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1509 | } | |
1510 | ||
d288f65f | 1511 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1512 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1513 | { |
cd2d34d9 | 1514 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1515 | enum pipe pipe = crtc->pipe; |
87442f73 | 1516 | |
8bd3f301 | 1517 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1518 | |
87442f73 | 1519 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1520 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1521 | |
cd2d34d9 VS |
1522 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1523 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1524 | |
8bd3f301 VS |
1525 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1526 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1527 | } |
1528 | ||
cd2d34d9 VS |
1529 | |
1530 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1531 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1532 | { |
cd2d34d9 | 1533 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1534 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1535 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1536 | u32 tmp; |
1537 | ||
a580516d | 1538 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1539 | |
1540 | /* Enable back the 10bit clock to display controller */ | |
1541 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1542 | tmp |= DPIO_DCLKP_EN; | |
1543 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1544 | ||
54433e91 VS |
1545 | mutex_unlock(&dev_priv->sb_lock); |
1546 | ||
9d556c99 CML |
1547 | /* |
1548 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1549 | */ | |
1550 | udelay(1); | |
1551 | ||
1552 | /* Enable PLL */ | |
d288f65f | 1553 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1554 | |
1555 | /* Check PLL is locked */ | |
6b18826a CW |
1556 | if (intel_wait_for_register(dev_priv, |
1557 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1558 | 1)) | |
9d556c99 | 1559 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1560 | } |
1561 | ||
1562 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1563 | const struct intel_crtc_state *pipe_config) | |
1564 | { | |
1565 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1566 | enum pipe pipe = crtc->pipe; | |
1567 | ||
1568 | assert_pipe_disabled(dev_priv, pipe); | |
1569 | ||
1570 | /* PLL is protected by panel, make sure we can write it */ | |
1571 | assert_panel_unlocked(dev_priv, pipe); | |
1572 | ||
1573 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1574 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1575 | |
c231775c VS |
1576 | if (pipe != PIPE_A) { |
1577 | /* | |
1578 | * WaPixelRepeatModeFixForC0:chv | |
1579 | * | |
1580 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1581 | * the value from DPLLBMD to either pipe B or C. | |
1582 | */ | |
1583 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1584 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1585 | I915_WRITE(CBR4_VLV, 0); | |
1586 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1587 | ||
1588 | /* | |
1589 | * DPLLB VGA mode also seems to cause problems. | |
1590 | * We should always have it disabled. | |
1591 | */ | |
1592 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1593 | } else { | |
1594 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1595 | POSTING_READ(DPLL_MD(pipe)); | |
1596 | } | |
9d556c99 CML |
1597 | } |
1598 | ||
1c4e0274 VS |
1599 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1600 | { | |
1601 | struct intel_crtc *crtc; | |
1602 | int count = 0; | |
1603 | ||
2d84d2b3 | 1604 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1605 | count += crtc->base.state->active && |
2d84d2b3 VS |
1606 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1607 | } | |
1c4e0274 VS |
1608 | |
1609 | return count; | |
1610 | } | |
1611 | ||
66e3d5c0 | 1612 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1613 | { |
66e3d5c0 | 1614 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1615 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1616 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1617 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1618 | |
66e3d5c0 | 1619 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1620 | |
63d7bbe9 | 1621 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1622 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1623 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1624 | |
1c4e0274 VS |
1625 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1626 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1627 | /* | |
1628 | * It appears to be important that we don't enable this | |
1629 | * for the current pipe before otherwise configuring the | |
1630 | * PLL. No idea how this should be handled if multiple | |
1631 | * DVO outputs are enabled simultaneosly. | |
1632 | */ | |
1633 | dpll |= DPLL_DVO_2X_MODE; | |
1634 | I915_WRITE(DPLL(!crtc->pipe), | |
1635 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1636 | } | |
66e3d5c0 | 1637 | |
c2b63374 VS |
1638 | /* |
1639 | * Apparently we need to have VGA mode enabled prior to changing | |
1640 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1641 | * dividers, even though the register value does change. | |
1642 | */ | |
1643 | I915_WRITE(reg, 0); | |
1644 | ||
8e7a65aa VS |
1645 | I915_WRITE(reg, dpll); |
1646 | ||
66e3d5c0 DV |
1647 | /* Wait for the clocks to stabilize. */ |
1648 | POSTING_READ(reg); | |
1649 | udelay(150); | |
1650 | ||
1651 | if (INTEL_INFO(dev)->gen >= 4) { | |
1652 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1653 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1654 | } else { |
1655 | /* The pixel multiplier can only be updated once the | |
1656 | * DPLL is enabled and the clocks are stable. | |
1657 | * | |
1658 | * So write it again. | |
1659 | */ | |
1660 | I915_WRITE(reg, dpll); | |
1661 | } | |
63d7bbe9 JB |
1662 | |
1663 | /* We do this three times for luck */ | |
66e3d5c0 | 1664 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1665 | POSTING_READ(reg); |
1666 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1667 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1668 | POSTING_READ(reg); |
1669 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1670 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1671 | POSTING_READ(reg); |
1672 | udelay(150); /* wait for warmup */ | |
1673 | } | |
1674 | ||
1675 | /** | |
50b44a44 | 1676 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1677 | * @dev_priv: i915 private structure |
1678 | * @pipe: pipe PLL to disable | |
1679 | * | |
1680 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1681 | * | |
1682 | * Note! This is for pre-ILK only. | |
1683 | */ | |
1c4e0274 | 1684 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1685 | { |
1c4e0274 | 1686 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1687 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1688 | enum pipe pipe = crtc->pipe; |
1689 | ||
1690 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1691 | if (IS_I830(dev) && | |
2d84d2b3 | 1692 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1693 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1694 | I915_WRITE(DPLL(PIPE_B), |
1695 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1696 | I915_WRITE(DPLL(PIPE_A), | |
1697 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1698 | } | |
1699 | ||
b6b5d049 VS |
1700 | /* Don't disable pipe or pipe PLLs if needed */ |
1701 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1702 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1703 | return; |
1704 | ||
1705 | /* Make sure the pipe isn't still relying on us */ | |
1706 | assert_pipe_disabled(dev_priv, pipe); | |
1707 | ||
b8afb911 | 1708 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1709 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1710 | } |
1711 | ||
f6071166 JB |
1712 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1713 | { | |
b8afb911 | 1714 | u32 val; |
f6071166 JB |
1715 | |
1716 | /* Make sure the pipe isn't still relying on us */ | |
1717 | assert_pipe_disabled(dev_priv, pipe); | |
1718 | ||
03ed5cbf VS |
1719 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1720 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1721 | if (pipe != PIPE_A) | |
1722 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1723 | ||
f6071166 JB |
1724 | I915_WRITE(DPLL(pipe), val); |
1725 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1726 | } |
1727 | ||
1728 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1729 | { | |
d752048d | 1730 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1731 | u32 val; |
1732 | ||
a11b0703 VS |
1733 | /* Make sure the pipe isn't still relying on us */ |
1734 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1735 | |
60bfe44f VS |
1736 | val = DPLL_SSC_REF_CLK_CHV | |
1737 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1738 | if (pipe != PIPE_A) |
1739 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1740 | |
a11b0703 VS |
1741 | I915_WRITE(DPLL(pipe), val); |
1742 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1743 | |
a580516d | 1744 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1745 | |
1746 | /* Disable 10bit clock to display controller */ | |
1747 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1748 | val &= ~DPIO_DCLKP_EN; | |
1749 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1750 | ||
a580516d | 1751 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1752 | } |
1753 | ||
e4607fcf | 1754 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1755 | struct intel_digital_port *dport, |
1756 | unsigned int expected_mask) | |
89b667f8 JB |
1757 | { |
1758 | u32 port_mask; | |
f0f59a00 | 1759 | i915_reg_t dpll_reg; |
89b667f8 | 1760 | |
e4607fcf CML |
1761 | switch (dport->port) { |
1762 | case PORT_B: | |
89b667f8 | 1763 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1764 | dpll_reg = DPLL(0); |
e4607fcf CML |
1765 | break; |
1766 | case PORT_C: | |
89b667f8 | 1767 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1768 | dpll_reg = DPLL(0); |
9b6de0a1 | 1769 | expected_mask <<= 4; |
00fc31b7 CML |
1770 | break; |
1771 | case PORT_D: | |
1772 | port_mask = DPLL_PORTD_READY_MASK; | |
1773 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1774 | break; |
1775 | default: | |
1776 | BUG(); | |
1777 | } | |
89b667f8 | 1778 | |
370004d3 CW |
1779 | if (intel_wait_for_register(dev_priv, |
1780 | dpll_reg, port_mask, expected_mask, | |
1781 | 1000)) | |
9b6de0a1 VS |
1782 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1783 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1784 | } |
1785 | ||
b8a4f404 PZ |
1786 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1787 | enum pipe pipe) | |
040484af | 1788 | { |
91c8a326 | 1789 | struct drm_device *dev = &dev_priv->drm; |
7c26e5c6 | 1790 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1792 | i915_reg_t reg; |
1793 | uint32_t val, pipeconf_val; | |
040484af | 1794 | |
040484af | 1795 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1796 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1797 | |
1798 | /* FDI must be feeding us bits for PCH ports */ | |
1799 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1800 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1801 | ||
23670b32 DV |
1802 | if (HAS_PCH_CPT(dev)) { |
1803 | /* Workaround: Set the timing override bit before enabling the | |
1804 | * pch transcoder. */ | |
1805 | reg = TRANS_CHICKEN2(pipe); | |
1806 | val = I915_READ(reg); | |
1807 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1808 | I915_WRITE(reg, val); | |
59c859d6 | 1809 | } |
23670b32 | 1810 | |
ab9412ba | 1811 | reg = PCH_TRANSCONF(pipe); |
040484af | 1812 | val = I915_READ(reg); |
5f7f726d | 1813 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1814 | |
2d1fe073 | 1815 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1816 | /* |
c5de7c6f VS |
1817 | * Make the BPC in transcoder be consistent with |
1818 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1819 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1820 | */ |
dfd07d72 | 1821 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1822 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1823 | val |= PIPECONF_8BPC; |
1824 | else | |
1825 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1826 | } |
5f7f726d PZ |
1827 | |
1828 | val &= ~TRANS_INTERLACE_MASK; | |
1829 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1830 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1831 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1832 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1833 | else | |
1834 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1835 | else |
1836 | val |= TRANS_PROGRESSIVE; | |
1837 | ||
040484af | 1838 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1839 | if (intel_wait_for_register(dev_priv, |
1840 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1841 | 100)) | |
4bb6f1f3 | 1842 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1843 | } |
1844 | ||
8fb033d7 | 1845 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1846 | enum transcoder cpu_transcoder) |
040484af | 1847 | { |
8fb033d7 | 1848 | u32 val, pipeconf_val; |
8fb033d7 | 1849 | |
8fb033d7 | 1850 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1851 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1852 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1853 | |
223a6fdf | 1854 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1858 | |
25f3ef11 | 1859 | val = TRANS_ENABLE; |
937bb610 | 1860 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1861 | |
9a76b1c6 PZ |
1862 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1863 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1864 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1865 | else |
1866 | val |= TRANS_PROGRESSIVE; | |
1867 | ||
ab9412ba | 1868 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, | |
1871 | TRANS_STATE_ENABLE, | |
1872 | TRANS_STATE_ENABLE, | |
1873 | 100)) | |
937bb610 | 1874 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1875 | } |
1876 | ||
b8a4f404 PZ |
1877 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1878 | enum pipe pipe) | |
040484af | 1879 | { |
91c8a326 | 1880 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 VS |
1881 | i915_reg_t reg; |
1882 | uint32_t val; | |
040484af JB |
1883 | |
1884 | /* FDI relies on the transcoder */ | |
1885 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1886 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1887 | ||
291906f1 JB |
1888 | /* Ports must be off as well */ |
1889 | assert_pch_ports_disabled(dev_priv, pipe); | |
1890 | ||
ab9412ba | 1891 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1892 | val = I915_READ(reg); |
1893 | val &= ~TRANS_ENABLE; | |
1894 | I915_WRITE(reg, val); | |
1895 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1896 | if (intel_wait_for_register(dev_priv, |
1897 | reg, TRANS_STATE_ENABLE, 0, | |
1898 | 50)) | |
4bb6f1f3 | 1899 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1900 | |
c465613b | 1901 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1902 | /* Workaround: Clear the timing override chicken bit again. */ |
1903 | reg = TRANS_CHICKEN2(pipe); | |
1904 | val = I915_READ(reg); | |
1905 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1906 | I915_WRITE(reg, val); | |
1907 | } | |
040484af JB |
1908 | } |
1909 | ||
ab4d966c | 1910 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1911 | { |
8fb033d7 PZ |
1912 | u32 val; |
1913 | ||
ab9412ba | 1914 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1915 | val &= ~TRANS_ENABLE; |
ab9412ba | 1916 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1917 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1918 | if (intel_wait_for_register(dev_priv, |
1919 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1920 | 50)) | |
8a52fd9f | 1921 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1922 | |
1923 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1924 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1925 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1926 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1927 | } |
1928 | ||
b24e7179 | 1929 | /** |
309cfea8 | 1930 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1931 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1932 | * |
0372264a | 1933 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1934 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1935 | */ |
e1fdc473 | 1936 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1937 | { |
0372264a | 1938 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1939 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1940 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1941 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1942 | enum pipe pch_transcoder; |
f0f59a00 | 1943 | i915_reg_t reg; |
b24e7179 JB |
1944 | u32 val; |
1945 | ||
9e2ee2dd VS |
1946 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1947 | ||
58c6eaa2 | 1948 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1949 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1950 | assert_sprites_disabled(dev_priv, pipe); |
1951 | ||
2d1fe073 | 1952 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1953 | pch_transcoder = TRANSCODER_A; |
1954 | else | |
1955 | pch_transcoder = pipe; | |
1956 | ||
b24e7179 JB |
1957 | /* |
1958 | * A pipe without a PLL won't actually be able to drive bits from | |
1959 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1960 | * need the check. | |
1961 | */ | |
09fa8bb9 | 1962 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1963 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1964 | assert_dsi_pll_enabled(dev_priv); |
1965 | else | |
1966 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1967 | } else { |
6e3c9717 | 1968 | if (crtc->config->has_pch_encoder) { |
040484af | 1969 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1970 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1971 | assert_fdi_tx_pll_enabled(dev_priv, |
1972 | (enum pipe) cpu_transcoder); | |
040484af JB |
1973 | } |
1974 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1975 | } | |
b24e7179 | 1976 | |
702e7a56 | 1977 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1978 | val = I915_READ(reg); |
7ad25d48 | 1979 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1980 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1981 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1982 | return; |
7ad25d48 | 1983 | } |
00d70b15 CW |
1984 | |
1985 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1986 | POSTING_READ(reg); |
b7792d8b VS |
1987 | |
1988 | /* | |
1989 | * Until the pipe starts DSL will read as 0, which would cause | |
1990 | * an apparent vblank timestamp jump, which messes up also the | |
1991 | * frame count when it's derived from the timestamps. So let's | |
1992 | * wait for the pipe to start properly before we call | |
1993 | * drm_crtc_vblank_on() | |
1994 | */ | |
1995 | if (dev->max_vblank_count == 0 && | |
1996 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1997 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1998 | } |
1999 | ||
2000 | /** | |
309cfea8 | 2001 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2002 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2003 | * |
575f7ab7 VS |
2004 | * Disable the pipe of @crtc, making sure that various hardware |
2005 | * specific requirements are met, if applicable, e.g. plane | |
2006 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2007 | * |
2008 | * Will wait until the pipe has shut down before returning. | |
2009 | */ | |
575f7ab7 | 2010 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2011 | { |
fac5e23e | 2012 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2013 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2014 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2015 | i915_reg_t reg; |
b24e7179 JB |
2016 | u32 val; |
2017 | ||
9e2ee2dd VS |
2018 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2019 | ||
b24e7179 JB |
2020 | /* |
2021 | * Make sure planes won't keep trying to pump pixels to us, | |
2022 | * or we might hang the display. | |
2023 | */ | |
2024 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2025 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2026 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2027 | |
702e7a56 | 2028 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2029 | val = I915_READ(reg); |
00d70b15 CW |
2030 | if ((val & PIPECONF_ENABLE) == 0) |
2031 | return; | |
2032 | ||
67adc644 VS |
2033 | /* |
2034 | * Double wide has implications for planes | |
2035 | * so best keep it disabled when not needed. | |
2036 | */ | |
6e3c9717 | 2037 | if (crtc->config->double_wide) |
67adc644 VS |
2038 | val &= ~PIPECONF_DOUBLE_WIDE; |
2039 | ||
2040 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2041 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2042 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2043 | val &= ~PIPECONF_ENABLE; |
2044 | ||
2045 | I915_WRITE(reg, val); | |
2046 | if ((val & PIPECONF_ENABLE) == 0) | |
2047 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2048 | } |
2049 | ||
832be82f VS |
2050 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2051 | { | |
2052 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2053 | } | |
2054 | ||
27ba3910 VS |
2055 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2056 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2057 | { |
2058 | switch (fb_modifier) { | |
2059 | case DRM_FORMAT_MOD_NONE: | |
2060 | return cpp; | |
2061 | case I915_FORMAT_MOD_X_TILED: | |
2062 | if (IS_GEN2(dev_priv)) | |
2063 | return 128; | |
2064 | else | |
2065 | return 512; | |
2066 | case I915_FORMAT_MOD_Y_TILED: | |
2067 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2068 | return 128; | |
2069 | else | |
2070 | return 512; | |
2071 | case I915_FORMAT_MOD_Yf_TILED: | |
2072 | switch (cpp) { | |
2073 | case 1: | |
2074 | return 64; | |
2075 | case 2: | |
2076 | case 4: | |
2077 | return 128; | |
2078 | case 8: | |
2079 | case 16: | |
2080 | return 256; | |
2081 | default: | |
2082 | MISSING_CASE(cpp); | |
2083 | return cpp; | |
2084 | } | |
2085 | break; | |
2086 | default: | |
2087 | MISSING_CASE(fb_modifier); | |
2088 | return cpp; | |
2089 | } | |
2090 | } | |
2091 | ||
832be82f VS |
2092 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2093 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2094 | { |
832be82f VS |
2095 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2096 | return 1; | |
2097 | else | |
2098 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2099 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2100 | } |
2101 | ||
8d0deca8 VS |
2102 | /* Return the tile dimensions in pixel units */ |
2103 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2104 | unsigned int *tile_width, | |
2105 | unsigned int *tile_height, | |
2106 | uint64_t fb_modifier, | |
2107 | unsigned int cpp) | |
2108 | { | |
2109 | unsigned int tile_width_bytes = | |
2110 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2111 | ||
2112 | *tile_width = tile_width_bytes / cpp; | |
2113 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2114 | } | |
2115 | ||
6761dd31 TU |
2116 | unsigned int |
2117 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2118 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2119 | { |
832be82f VS |
2120 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2121 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2122 | ||
2123 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2124 | } |
2125 | ||
1663b9d6 VS |
2126 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2127 | { | |
2128 | unsigned int size = 0; | |
2129 | int i; | |
2130 | ||
2131 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2132 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2133 | ||
2134 | return size; | |
2135 | } | |
2136 | ||
75c82a53 | 2137 | static void |
3465c580 VS |
2138 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2139 | const struct drm_framebuffer *fb, | |
2140 | unsigned int rotation) | |
f64b98cd | 2141 | { |
2d7a215f VS |
2142 | if (intel_rotation_90_or_270(rotation)) { |
2143 | *view = i915_ggtt_view_rotated; | |
2144 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2145 | } else { | |
2146 | *view = i915_ggtt_view_normal; | |
2147 | } | |
2148 | } | |
50470bb0 | 2149 | |
603525d7 | 2150 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2151 | { |
2152 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2153 | return 256 * 1024; | |
985b8bb4 | 2154 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2155 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2156 | return 128 * 1024; |
2157 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2158 | return 4 * 1024; | |
2159 | else | |
44c5905e | 2160 | return 0; |
4e9a86b6 VS |
2161 | } |
2162 | ||
603525d7 VS |
2163 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2164 | uint64_t fb_modifier) | |
2165 | { | |
2166 | switch (fb_modifier) { | |
2167 | case DRM_FORMAT_MOD_NONE: | |
2168 | return intel_linear_alignment(dev_priv); | |
2169 | case I915_FORMAT_MOD_X_TILED: | |
2170 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2171 | return 256 * 1024; | |
2172 | return 0; | |
2173 | case I915_FORMAT_MOD_Y_TILED: | |
2174 | case I915_FORMAT_MOD_Yf_TILED: | |
2175 | return 1 * 1024 * 1024; | |
2176 | default: | |
2177 | MISSING_CASE(fb_modifier); | |
2178 | return 0; | |
2179 | } | |
2180 | } | |
2181 | ||
127bd2ac | 2182 | int |
3465c580 VS |
2183 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2184 | unsigned int rotation) | |
6b95a207 | 2185 | { |
850c4cdc | 2186 | struct drm_device *dev = fb->dev; |
fac5e23e | 2187 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2188 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2189 | struct i915_ggtt_view view; |
6b95a207 KH |
2190 | u32 alignment; |
2191 | int ret; | |
2192 | ||
ebcdd39e MR |
2193 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2194 | ||
603525d7 | 2195 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2196 | |
3465c580 | 2197 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2198 | |
693db184 CW |
2199 | /* Note that the w/a also requires 64 PTE of padding following the |
2200 | * bo. We currently fill all unused PTE with the shadow page and so | |
2201 | * we should always have valid PTE following the scanout preventing | |
2202 | * the VT-d warning. | |
2203 | */ | |
48f112fe | 2204 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2205 | alignment = 256 * 1024; |
2206 | ||
d6dd6843 PZ |
2207 | /* |
2208 | * Global gtt pte registers are special registers which actually forward | |
2209 | * writes to a chunk of system memory. Which means that there is no risk | |
2210 | * that the register values disappear as soon as we call | |
2211 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2212 | * pin/unpin/fence and not more. | |
2213 | */ | |
2214 | intel_runtime_pm_get(dev_priv); | |
2215 | ||
7580d774 ML |
2216 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2217 | &view); | |
48b956c5 | 2218 | if (ret) |
b26a6b35 | 2219 | goto err_pm; |
6b95a207 KH |
2220 | |
2221 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2222 | * fence, whereas 965+ only requires a fence if using | |
2223 | * framebuffer compression. For simplicity, we always install | |
2224 | * a fence as the cost is not that onerous. | |
2225 | */ | |
9807216f VK |
2226 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2227 | ret = i915_gem_object_get_fence(obj); | |
2228 | if (ret == -EDEADLK) { | |
2229 | /* | |
2230 | * -EDEADLK means there are no free fences | |
2231 | * no pending flips. | |
2232 | * | |
2233 | * This is propagated to atomic, but it uses | |
2234 | * -EDEADLK to force a locking recovery, so | |
2235 | * change the returned error to -EBUSY. | |
2236 | */ | |
2237 | ret = -EBUSY; | |
2238 | goto err_unpin; | |
2239 | } else if (ret) | |
2240 | goto err_unpin; | |
1690e1eb | 2241 | |
9807216f VK |
2242 | i915_gem_object_pin_fence(obj); |
2243 | } | |
6b95a207 | 2244 | |
d6dd6843 | 2245 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2246 | return 0; |
48b956c5 CW |
2247 | |
2248 | err_unpin: | |
f64b98cd | 2249 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2250 | err_pm: |
d6dd6843 | 2251 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2252 | return ret; |
6b95a207 KH |
2253 | } |
2254 | ||
fb4b8ce1 | 2255 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2256 | { |
82bc3b2d | 2257 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2258 | struct i915_ggtt_view view; |
82bc3b2d | 2259 | |
ebcdd39e MR |
2260 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2261 | ||
3465c580 | 2262 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2263 | |
9807216f VK |
2264 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2265 | i915_gem_object_unpin_fence(obj); | |
2266 | ||
f64b98cd | 2267 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2268 | } |
2269 | ||
ef78ec94 VS |
2270 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2271 | unsigned int rotation) | |
2272 | { | |
2273 | if (intel_rotation_90_or_270(rotation)) | |
2274 | return to_intel_framebuffer(fb)->rotated[plane].pitch; | |
2275 | else | |
2276 | return fb->pitches[plane]; | |
2277 | } | |
2278 | ||
6687c906 VS |
2279 | /* |
2280 | * Convert the x/y offsets into a linear offset. | |
2281 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2282 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2283 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2284 | */ | |
2285 | u32 intel_fb_xy_to_linear(int x, int y, | |
2286 | const struct drm_framebuffer *fb, int plane) | |
2287 | { | |
2288 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2289 | unsigned int pitch = fb->pitches[plane]; | |
2290 | ||
2291 | return y * pitch + x * cpp; | |
2292 | } | |
2293 | ||
2294 | /* | |
2295 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2296 | * specified plane src x/y offsets. The resulting x/y offsets | |
2297 | * specify the start of scanout from the beginning of the gtt mapping. | |
2298 | */ | |
2299 | void intel_add_fb_offsets(int *x, int *y, | |
2300 | const struct drm_framebuffer *fb, int plane, | |
2301 | unsigned int rotation) | |
2302 | ||
2303 | { | |
2304 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2305 | ||
2306 | if (intel_rotation_90_or_270(rotation)) { | |
2307 | *x += intel_fb->rotated[plane].x; | |
2308 | *y += intel_fb->rotated[plane].y; | |
2309 | } else { | |
2310 | *x += intel_fb->normal[plane].x; | |
2311 | *y += intel_fb->normal[plane].y; | |
2312 | } | |
2313 | } | |
2314 | ||
29cf9491 VS |
2315 | /* |
2316 | * Adjust the tile offset by moving the difference into | |
2317 | * the x/y offsets. | |
2318 | * | |
2319 | * Input tile dimensions and pitch must already be | |
2320 | * rotated to match x and y, and in pixel units. | |
2321 | */ | |
2322 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2323 | unsigned int tile_width, | |
2324 | unsigned int tile_height, | |
2325 | unsigned int tile_size, | |
2326 | unsigned int pitch_tiles, | |
2327 | u32 old_offset, | |
2328 | u32 new_offset) | |
2329 | { | |
2330 | unsigned int tiles; | |
2331 | ||
2332 | WARN_ON(old_offset & (tile_size - 1)); | |
2333 | WARN_ON(new_offset & (tile_size - 1)); | |
2334 | WARN_ON(new_offset > old_offset); | |
2335 | ||
2336 | tiles = (old_offset - new_offset) / tile_size; | |
2337 | ||
2338 | *y += tiles / pitch_tiles * tile_height; | |
2339 | *x += tiles % pitch_tiles * tile_width; | |
2340 | ||
2341 | return new_offset; | |
2342 | } | |
2343 | ||
8d0deca8 VS |
2344 | /* |
2345 | * Computes the linear offset to the base tile and adjusts | |
2346 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2347 | * | |
2348 | * In the 90/270 rotated case, x and y are assumed | |
2349 | * to be already rotated to match the rotated GTT view, and | |
2350 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2351 | * |
2352 | * This function is used when computing the derived information | |
2353 | * under intel_framebuffer, so using any of that information | |
2354 | * here is not allowed. Anything under drm_framebuffer can be | |
2355 | * used. This is why the user has to pass in the pitch since it | |
2356 | * is specified in the rotated orientation. | |
8d0deca8 | 2357 | */ |
6687c906 VS |
2358 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2359 | int *x, int *y, | |
2360 | const struct drm_framebuffer *fb, int plane, | |
2361 | unsigned int pitch, | |
2362 | unsigned int rotation, | |
2363 | u32 alignment) | |
c2c75131 | 2364 | { |
4f2d9934 VS |
2365 | uint64_t fb_modifier = fb->modifier[plane]; |
2366 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
6687c906 | 2367 | u32 offset, offset_aligned; |
29cf9491 | 2368 | |
29cf9491 VS |
2369 | if (alignment) |
2370 | alignment--; | |
2371 | ||
b5c65338 | 2372 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2373 | unsigned int tile_size, tile_width, tile_height; |
2374 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2375 | |
d843310d | 2376 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2377 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2378 | fb_modifier, cpp); | |
2379 | ||
2380 | if (intel_rotation_90_or_270(rotation)) { | |
2381 | pitch_tiles = pitch / tile_height; | |
2382 | swap(tile_width, tile_height); | |
2383 | } else { | |
2384 | pitch_tiles = pitch / (tile_width * cpp); | |
2385 | } | |
d843310d VS |
2386 | |
2387 | tile_rows = *y / tile_height; | |
2388 | *y %= tile_height; | |
c2c75131 | 2389 | |
8d0deca8 VS |
2390 | tiles = *x / tile_width; |
2391 | *x %= tile_width; | |
bc752862 | 2392 | |
29cf9491 VS |
2393 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2394 | offset_aligned = offset & ~alignment; | |
bc752862 | 2395 | |
29cf9491 VS |
2396 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2397 | tile_size, pitch_tiles, | |
2398 | offset, offset_aligned); | |
2399 | } else { | |
bc752862 | 2400 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2401 | offset_aligned = offset & ~alignment; |
2402 | ||
4e9a86b6 VS |
2403 | *y = (offset & alignment) / pitch; |
2404 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2405 | } |
29cf9491 VS |
2406 | |
2407 | return offset_aligned; | |
c2c75131 DV |
2408 | } |
2409 | ||
6687c906 VS |
2410 | u32 intel_compute_tile_offset(int *x, int *y, |
2411 | const struct drm_framebuffer *fb, int plane, | |
6687c906 VS |
2412 | unsigned int rotation) |
2413 | { | |
2414 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
2415 | u32 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]); | |
ef78ec94 | 2416 | int pitch = intel_fb_pitch(fb, plane, rotation); |
6687c906 VS |
2417 | |
2418 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2419 | rotation, alignment); | |
2420 | } | |
2421 | ||
2422 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2423 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2424 | const struct drm_framebuffer *fb, int plane) | |
2425 | { | |
2426 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2427 | unsigned int pitch = fb->pitches[plane]; | |
2428 | u32 linear_offset = fb->offsets[plane]; | |
2429 | ||
2430 | *y = linear_offset / pitch; | |
2431 | *x = linear_offset % pitch / cpp; | |
2432 | } | |
2433 | ||
2434 | static int | |
2435 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2436 | struct drm_framebuffer *fb) | |
2437 | { | |
2438 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2439 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2440 | u32 gtt_offset_rotated = 0; | |
2441 | unsigned int max_size = 0; | |
2442 | uint32_t format = fb->pixel_format; | |
2443 | int i, num_planes = drm_format_num_planes(format); | |
2444 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2445 | ||
2446 | for (i = 0; i < num_planes; i++) { | |
2447 | unsigned int width, height; | |
2448 | unsigned int cpp, size; | |
2449 | u32 offset; | |
2450 | int x, y; | |
2451 | ||
2452 | cpp = drm_format_plane_cpp(format, i); | |
2453 | width = drm_format_plane_width(fb->width, format, i); | |
2454 | height = drm_format_plane_height(fb->height, format, i); | |
2455 | ||
2456 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2457 | ||
2458 | /* | |
2459 | * First pixel of the framebuffer from | |
2460 | * the start of the normal gtt mapping. | |
2461 | */ | |
2462 | intel_fb->normal[i].x = x; | |
2463 | intel_fb->normal[i].y = y; | |
2464 | ||
2465 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2466 | fb, 0, fb->pitches[i], | |
2467 | BIT(DRM_ROTATE_0), tile_size); | |
2468 | offset /= tile_size; | |
2469 | ||
2470 | if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) { | |
2471 | unsigned int tile_width, tile_height; | |
2472 | unsigned int pitch_tiles; | |
2473 | struct drm_rect r; | |
2474 | ||
2475 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2476 | fb->modifier[i], cpp); | |
2477 | ||
2478 | rot_info->plane[i].offset = offset; | |
2479 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2480 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2481 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2482 | ||
2483 | intel_fb->rotated[i].pitch = | |
2484 | rot_info->plane[i].height * tile_height; | |
2485 | ||
2486 | /* how many tiles does this plane need */ | |
2487 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2488 | /* | |
2489 | * If the plane isn't horizontally tile aligned, | |
2490 | * we need one more tile. | |
2491 | */ | |
2492 | if (x != 0) | |
2493 | size++; | |
2494 | ||
2495 | /* rotate the x/y offsets to match the GTT view */ | |
2496 | r.x1 = x; | |
2497 | r.y1 = y; | |
2498 | r.x2 = x + width; | |
2499 | r.y2 = y + height; | |
2500 | drm_rect_rotate(&r, | |
2501 | rot_info->plane[i].width * tile_width, | |
2502 | rot_info->plane[i].height * tile_height, | |
2503 | BIT(DRM_ROTATE_270)); | |
2504 | x = r.x1; | |
2505 | y = r.y1; | |
2506 | ||
2507 | /* rotate the tile dimensions to match the GTT view */ | |
2508 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2509 | swap(tile_width, tile_height); | |
2510 | ||
2511 | /* | |
2512 | * We only keep the x/y offsets, so push all of the | |
2513 | * gtt offset into the x/y offsets. | |
2514 | */ | |
2515 | intel_adjust_tile_offset(&x, &y, tile_size, | |
2516 | tile_width, tile_height, pitch_tiles, | |
2517 | gtt_offset_rotated * tile_size, 0); | |
2518 | ||
2519 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2520 | ||
2521 | /* | |
2522 | * First pixel of the framebuffer from | |
2523 | * the start of the rotated gtt mapping. | |
2524 | */ | |
2525 | intel_fb->rotated[i].x = x; | |
2526 | intel_fb->rotated[i].y = y; | |
2527 | } else { | |
2528 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2529 | x * cpp, tile_size); | |
2530 | } | |
2531 | ||
2532 | /* how many tiles in total needed in the bo */ | |
2533 | max_size = max(max_size, offset + size); | |
2534 | } | |
2535 | ||
2536 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2537 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2538 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2539 | return -EINVAL; | |
2540 | } | |
2541 | ||
2542 | return 0; | |
2543 | } | |
2544 | ||
b35d63fa | 2545 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2546 | { |
2547 | switch (format) { | |
2548 | case DISPPLANE_8BPP: | |
2549 | return DRM_FORMAT_C8; | |
2550 | case DISPPLANE_BGRX555: | |
2551 | return DRM_FORMAT_XRGB1555; | |
2552 | case DISPPLANE_BGRX565: | |
2553 | return DRM_FORMAT_RGB565; | |
2554 | default: | |
2555 | case DISPPLANE_BGRX888: | |
2556 | return DRM_FORMAT_XRGB8888; | |
2557 | case DISPPLANE_RGBX888: | |
2558 | return DRM_FORMAT_XBGR8888; | |
2559 | case DISPPLANE_BGRX101010: | |
2560 | return DRM_FORMAT_XRGB2101010; | |
2561 | case DISPPLANE_RGBX101010: | |
2562 | return DRM_FORMAT_XBGR2101010; | |
2563 | } | |
2564 | } | |
2565 | ||
bc8d7dff DL |
2566 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2567 | { | |
2568 | switch (format) { | |
2569 | case PLANE_CTL_FORMAT_RGB_565: | |
2570 | return DRM_FORMAT_RGB565; | |
2571 | default: | |
2572 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2573 | if (rgb_order) { | |
2574 | if (alpha) | |
2575 | return DRM_FORMAT_ABGR8888; | |
2576 | else | |
2577 | return DRM_FORMAT_XBGR8888; | |
2578 | } else { | |
2579 | if (alpha) | |
2580 | return DRM_FORMAT_ARGB8888; | |
2581 | else | |
2582 | return DRM_FORMAT_XRGB8888; | |
2583 | } | |
2584 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2585 | if (rgb_order) | |
2586 | return DRM_FORMAT_XBGR2101010; | |
2587 | else | |
2588 | return DRM_FORMAT_XRGB2101010; | |
2589 | } | |
2590 | } | |
2591 | ||
5724dbd1 | 2592 | static bool |
f6936e29 DV |
2593 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2594 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2595 | { |
2596 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2597 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2598 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2599 | struct drm_i915_gem_object *obj = NULL; |
2600 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2601 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2602 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2603 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2604 | PAGE_SIZE); | |
2605 | ||
2606 | size_aligned -= base_aligned; | |
46f297fb | 2607 | |
ff2652ea CW |
2608 | if (plane_config->size == 0) |
2609 | return false; | |
2610 | ||
3badb49f PZ |
2611 | /* If the FB is too big, just don't use it since fbdev is not very |
2612 | * important and we should probably use that space with FBC or other | |
2613 | * features. */ | |
72e96d64 | 2614 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2615 | return false; |
2616 | ||
12c83d99 TU |
2617 | mutex_lock(&dev->struct_mutex); |
2618 | ||
f37b5c2b DV |
2619 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2620 | base_aligned, | |
2621 | base_aligned, | |
2622 | size_aligned); | |
12c83d99 TU |
2623 | if (!obj) { |
2624 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2625 | return false; |
12c83d99 | 2626 | } |
46f297fb | 2627 | |
3e510a8e CW |
2628 | if (plane_config->tiling == I915_TILING_X) |
2629 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2630 | |
6bf129df DL |
2631 | mode_cmd.pixel_format = fb->pixel_format; |
2632 | mode_cmd.width = fb->width; | |
2633 | mode_cmd.height = fb->height; | |
2634 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2635 | mode_cmd.modifier[0] = fb->modifier[0]; |
2636 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2637 | |
6bf129df | 2638 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2639 | &mode_cmd, obj)) { |
46f297fb JB |
2640 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2641 | goto out_unref_obj; | |
2642 | } | |
12c83d99 | 2643 | |
46f297fb | 2644 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2645 | |
f6936e29 | 2646 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2647 | return true; |
46f297fb JB |
2648 | |
2649 | out_unref_obj: | |
f8c417cd | 2650 | i915_gem_object_put(obj); |
46f297fb | 2651 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2652 | return false; |
2653 | } | |
2654 | ||
5a21b665 DV |
2655 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2656 | static void | |
2657 | update_state_fb(struct drm_plane *plane) | |
2658 | { | |
2659 | if (plane->fb == plane->state->fb) | |
2660 | return; | |
2661 | ||
2662 | if (plane->state->fb) | |
2663 | drm_framebuffer_unreference(plane->state->fb); | |
2664 | plane->state->fb = plane->fb; | |
2665 | if (plane->state->fb) | |
2666 | drm_framebuffer_reference(plane->state->fb); | |
2667 | } | |
2668 | ||
5724dbd1 | 2669 | static void |
f6936e29 DV |
2670 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2671 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2672 | { |
2673 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2674 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2675 | struct drm_crtc *c; |
2676 | struct intel_crtc *i; | |
2ff8fde1 | 2677 | struct drm_i915_gem_object *obj; |
88595ac9 | 2678 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2679 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2680 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2681 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2682 | struct intel_plane_state *intel_state = |
2683 | to_intel_plane_state(plane_state); | |
88595ac9 | 2684 | struct drm_framebuffer *fb; |
484b41dd | 2685 | |
2d14030b | 2686 | if (!plane_config->fb) |
484b41dd JB |
2687 | return; |
2688 | ||
f6936e29 | 2689 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2690 | fb = &plane_config->fb->base; |
2691 | goto valid_fb; | |
f55548b5 | 2692 | } |
484b41dd | 2693 | |
2d14030b | 2694 | kfree(plane_config->fb); |
484b41dd JB |
2695 | |
2696 | /* | |
2697 | * Failed to alloc the obj, check to see if we should share | |
2698 | * an fb with another CRTC instead | |
2699 | */ | |
70e1e0ec | 2700 | for_each_crtc(dev, c) { |
484b41dd JB |
2701 | i = to_intel_crtc(c); |
2702 | ||
2703 | if (c == &intel_crtc->base) | |
2704 | continue; | |
2705 | ||
2ff8fde1 MR |
2706 | if (!i->active) |
2707 | continue; | |
2708 | ||
88595ac9 DV |
2709 | fb = c->primary->fb; |
2710 | if (!fb) | |
484b41dd JB |
2711 | continue; |
2712 | ||
88595ac9 | 2713 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2714 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2715 | drm_framebuffer_reference(fb); |
2716 | goto valid_fb; | |
484b41dd JB |
2717 | } |
2718 | } | |
88595ac9 | 2719 | |
200757f5 MR |
2720 | /* |
2721 | * We've failed to reconstruct the BIOS FB. Current display state | |
2722 | * indicates that the primary plane is visible, but has a NULL FB, | |
2723 | * which will lead to problems later if we don't fix it up. The | |
2724 | * simplest solution is to just disable the primary plane now and | |
2725 | * pretend the BIOS never had it enabled. | |
2726 | */ | |
2727 | to_intel_plane_state(plane_state)->visible = false; | |
2728 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2729 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2730 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2731 | ||
88595ac9 DV |
2732 | return; |
2733 | ||
2734 | valid_fb: | |
f44e2659 VS |
2735 | plane_state->src_x = 0; |
2736 | plane_state->src_y = 0; | |
be5651f2 ML |
2737 | plane_state->src_w = fb->width << 16; |
2738 | plane_state->src_h = fb->height << 16; | |
2739 | ||
f44e2659 VS |
2740 | plane_state->crtc_x = 0; |
2741 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2742 | plane_state->crtc_w = fb->width; |
2743 | plane_state->crtc_h = fb->height; | |
2744 | ||
0a8d8a86 MR |
2745 | intel_state->src.x1 = plane_state->src_x; |
2746 | intel_state->src.y1 = plane_state->src_y; | |
2747 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2748 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2749 | intel_state->dst.x1 = plane_state->crtc_x; | |
2750 | intel_state->dst.y1 = plane_state->crtc_y; | |
2751 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2752 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2753 | ||
88595ac9 | 2754 | obj = intel_fb_obj(fb); |
3e510a8e | 2755 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2756 | dev_priv->preserve_bios_swizzle = true; |
2757 | ||
be5651f2 ML |
2758 | drm_framebuffer_reference(fb); |
2759 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2760 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2761 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2762 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2763 | &obj->frontbuffer_bits); | |
46f297fb JB |
2764 | } |
2765 | ||
a8d201af ML |
2766 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2767 | const struct intel_crtc_state *crtc_state, | |
2768 | const struct intel_plane_state *plane_state) | |
81255565 | 2769 | { |
a8d201af | 2770 | struct drm_device *dev = primary->dev; |
fac5e23e | 2771 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2773 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2774 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2775 | int plane = intel_crtc->plane; |
54ea9da8 | 2776 | u32 linear_offset; |
81255565 | 2777 | u32 dspcntr; |
f0f59a00 | 2778 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2779 | unsigned int rotation = plane_state->base.rotation; |
54ea9da8 VS |
2780 | int x = plane_state->src.x1 >> 16; |
2781 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2782 | |
f45651ba VS |
2783 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2784 | ||
fdd508a6 | 2785 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2786 | |
2787 | if (INTEL_INFO(dev)->gen < 4) { | |
2788 | if (intel_crtc->pipe == PIPE_B) | |
2789 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2790 | ||
2791 | /* pipesrc and dspsize control the size that is scaled from, | |
2792 | * which should always be the user's requested size. | |
2793 | */ | |
2794 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2795 | ((crtc_state->pipe_src_h - 1) << 16) | |
2796 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2797 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2798 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2799 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2800 | ((crtc_state->pipe_src_h - 1) << 16) | |
2801 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2802 | I915_WRITE(PRIMPOS(plane), 0); |
2803 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2804 | } |
81255565 | 2805 | |
57779d06 VS |
2806 | switch (fb->pixel_format) { |
2807 | case DRM_FORMAT_C8: | |
81255565 JB |
2808 | dspcntr |= DISPPLANE_8BPP; |
2809 | break; | |
57779d06 | 2810 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2811 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2812 | break; |
57779d06 VS |
2813 | case DRM_FORMAT_RGB565: |
2814 | dspcntr |= DISPPLANE_BGRX565; | |
2815 | break; | |
2816 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2817 | dspcntr |= DISPPLANE_BGRX888; |
2818 | break; | |
2819 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2820 | dspcntr |= DISPPLANE_RGBX888; |
2821 | break; | |
2822 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2823 | dspcntr |= DISPPLANE_BGRX101010; |
2824 | break; | |
2825 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2826 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2827 | break; |
2828 | default: | |
baba133a | 2829 | BUG(); |
81255565 | 2830 | } |
57779d06 | 2831 | |
3e510a8e | 2832 | if (INTEL_INFO(dev)->gen >= 4 && i915_gem_object_is_tiled(obj)) |
f45651ba | 2833 | dspcntr |= DISPPLANE_TILED; |
81255565 | 2834 | |
de1aa629 VS |
2835 | if (IS_G4X(dev)) |
2836 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2837 | ||
6687c906 | 2838 | intel_add_fb_offsets(&x, &y, fb, 0, rotation); |
81255565 | 2839 | |
6687c906 | 2840 | if (INTEL_INFO(dev)->gen >= 4) |
c2c75131 | 2841 | intel_crtc->dspaddr_offset = |
ef78ec94 | 2842 | intel_compute_tile_offset(&x, &y, fb, 0, rotation); |
e506a0c6 | 2843 | |
8d0deca8 | 2844 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2845 | dspcntr |= DISPPLANE_ROTATE_180; |
2846 | ||
a8d201af ML |
2847 | x += (crtc_state->pipe_src_w - 1); |
2848 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2849 | } |
2850 | ||
6687c906 VS |
2851 | linear_offset = intel_fb_xy_to_linear(x, y, fb, 0); |
2852 | ||
2853 | if (INTEL_INFO(dev)->gen < 4) | |
2854 | intel_crtc->dspaddr_offset = linear_offset; | |
2855 | ||
2db3366b PZ |
2856 | intel_crtc->adjusted_x = x; |
2857 | intel_crtc->adjusted_y = y; | |
2858 | ||
48404c1e SJ |
2859 | I915_WRITE(reg, dspcntr); |
2860 | ||
01f2c773 | 2861 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2862 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d | 2863 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
2864 | intel_fb_gtt_offset(fb, rotation) + |
2865 | intel_crtc->dspaddr_offset); | |
5eddb70b | 2866 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2867 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2868 | } else |
f343c5f6 | 2869 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2870 | POSTING_READ(reg); |
17638cd6 JB |
2871 | } |
2872 | ||
a8d201af ML |
2873 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2874 | struct drm_crtc *crtc) | |
17638cd6 JB |
2875 | { |
2876 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 2877 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 2878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 2879 | int plane = intel_crtc->plane; |
f45651ba | 2880 | |
a8d201af ML |
2881 | I915_WRITE(DSPCNTR(plane), 0); |
2882 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2883 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2884 | else |
2885 | I915_WRITE(DSPADDR(plane), 0); | |
2886 | POSTING_READ(DSPCNTR(plane)); | |
2887 | } | |
c9ba6fad | 2888 | |
a8d201af ML |
2889 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2890 | const struct intel_crtc_state *crtc_state, | |
2891 | const struct intel_plane_state *plane_state) | |
2892 | { | |
2893 | struct drm_device *dev = primary->dev; | |
fac5e23e | 2894 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2895 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2896 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2897 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2898 | int plane = intel_crtc->plane; | |
54ea9da8 | 2899 | u32 linear_offset; |
a8d201af ML |
2900 | u32 dspcntr; |
2901 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2902 | unsigned int rotation = plane_state->base.rotation; |
a8d201af ML |
2903 | int x = plane_state->src.x1 >> 16; |
2904 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2905 | |
f45651ba | 2906 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2907 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2908 | |
2909 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2910 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2911 | |
57779d06 VS |
2912 | switch (fb->pixel_format) { |
2913 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2914 | dspcntr |= DISPPLANE_8BPP; |
2915 | break; | |
57779d06 VS |
2916 | case DRM_FORMAT_RGB565: |
2917 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2918 | break; |
57779d06 | 2919 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2920 | dspcntr |= DISPPLANE_BGRX888; |
2921 | break; | |
2922 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2923 | dspcntr |= DISPPLANE_RGBX888; |
2924 | break; | |
2925 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2926 | dspcntr |= DISPPLANE_BGRX101010; |
2927 | break; | |
2928 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2929 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2930 | break; |
2931 | default: | |
baba133a | 2932 | BUG(); |
17638cd6 JB |
2933 | } |
2934 | ||
3e510a8e | 2935 | if (i915_gem_object_is_tiled(obj)) |
17638cd6 | 2936 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 2937 | |
f45651ba | 2938 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2939 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2940 | |
6687c906 VS |
2941 | intel_add_fb_offsets(&x, &y, fb, 0, rotation); |
2942 | ||
c2c75131 | 2943 | intel_crtc->dspaddr_offset = |
ef78ec94 | 2944 | intel_compute_tile_offset(&x, &y, fb, 0, rotation); |
6687c906 | 2945 | |
8d0deca8 | 2946 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2947 | dspcntr |= DISPPLANE_ROTATE_180; |
2948 | ||
2949 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2950 | x += (crtc_state->pipe_src_w - 1); |
2951 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2952 | } |
2953 | } | |
2954 | ||
6687c906 VS |
2955 | linear_offset = intel_fb_xy_to_linear(x, y, fb, 0); |
2956 | ||
2db3366b PZ |
2957 | intel_crtc->adjusted_x = x; |
2958 | intel_crtc->adjusted_y = y; | |
2959 | ||
48404c1e | 2960 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2961 | |
01f2c773 | 2962 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 2963 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
2964 | intel_fb_gtt_offset(fb, rotation) + |
2965 | intel_crtc->dspaddr_offset); | |
b3dc685e | 2966 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2967 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2968 | } else { | |
2969 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2970 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2971 | } | |
17638cd6 | 2972 | POSTING_READ(reg); |
17638cd6 JB |
2973 | } |
2974 | ||
7b49f948 VS |
2975 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2976 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2977 | { |
7b49f948 | 2978 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2979 | return 64; |
7b49f948 VS |
2980 | } else { |
2981 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2982 | ||
27ba3910 | 2983 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2984 | } |
2985 | } | |
2986 | ||
6687c906 VS |
2987 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
2988 | unsigned int rotation) | |
121920fa | 2989 | { |
6687c906 | 2990 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 2991 | struct i915_ggtt_view view; |
44eb0cb9 | 2992 | u64 offset; |
121920fa | 2993 | |
6687c906 | 2994 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 2995 | |
6687c906 | 2996 | offset = i915_gem_obj_ggtt_offset_view(obj, &view); |
dedf278c | 2997 | |
44eb0cb9 MK |
2998 | WARN_ON(upper_32_bits(offset)); |
2999 | ||
3000 | return lower_32_bits(offset); | |
121920fa TU |
3001 | } |
3002 | ||
e435d6e5 ML |
3003 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3004 | { | |
3005 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3006 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3007 | |
3008 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3009 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3010 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3011 | } |
3012 | ||
a1b2278e CK |
3013 | /* |
3014 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3015 | */ | |
0583236e | 3016 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3017 | { |
a1b2278e CK |
3018 | struct intel_crtc_scaler_state *scaler_state; |
3019 | int i; | |
3020 | ||
a1b2278e CK |
3021 | scaler_state = &intel_crtc->config->scaler_state; |
3022 | ||
3023 | /* loop through and disable scalers that aren't in use */ | |
3024 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3025 | if (!scaler_state->scalers[i].in_use) |
3026 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3027 | } |
3028 | } | |
3029 | ||
d2196774 VS |
3030 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3031 | unsigned int rotation) | |
3032 | { | |
3033 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3034 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3035 | ||
3036 | /* | |
3037 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3038 | * linear buffers or in number of tiles for tiled buffers. | |
3039 | */ | |
3040 | if (intel_rotation_90_or_270(rotation)) { | |
3041 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
3042 | ||
3043 | stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
3044 | } else { | |
3045 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
3046 | fb->pixel_format); | |
3047 | } | |
3048 | ||
3049 | return stride; | |
3050 | } | |
3051 | ||
6156a456 | 3052 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3053 | { |
6156a456 | 3054 | switch (pixel_format) { |
d161cf7a | 3055 | case DRM_FORMAT_C8: |
c34ce3d1 | 3056 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3057 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3058 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3059 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3060 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3061 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3062 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3063 | /* |
3064 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3065 | * to be already pre-multiplied. We need to add a knob (or a different | |
3066 | * DRM_FORMAT) for user-space to configure that. | |
3067 | */ | |
f75fb42a | 3068 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3069 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3070 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3071 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3072 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3073 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3074 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3075 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3076 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3077 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3078 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3079 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3080 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3081 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3082 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3083 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3084 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3085 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3086 | default: |
4249eeef | 3087 | MISSING_CASE(pixel_format); |
70d21f0e | 3088 | } |
8cfcba41 | 3089 | |
c34ce3d1 | 3090 | return 0; |
6156a456 | 3091 | } |
70d21f0e | 3092 | |
6156a456 CK |
3093 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3094 | { | |
6156a456 | 3095 | switch (fb_modifier) { |
30af77c4 | 3096 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3097 | break; |
30af77c4 | 3098 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3099 | return PLANE_CTL_TILED_X; |
b321803d | 3100 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3101 | return PLANE_CTL_TILED_Y; |
b321803d | 3102 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3103 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3104 | default: |
6156a456 | 3105 | MISSING_CASE(fb_modifier); |
70d21f0e | 3106 | } |
8cfcba41 | 3107 | |
c34ce3d1 | 3108 | return 0; |
6156a456 | 3109 | } |
70d21f0e | 3110 | |
6156a456 CK |
3111 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3112 | { | |
3b7a5119 | 3113 | switch (rotation) { |
6156a456 CK |
3114 | case BIT(DRM_ROTATE_0): |
3115 | break; | |
1e8df167 SJ |
3116 | /* |
3117 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3118 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3119 | */ | |
3b7a5119 | 3120 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3121 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3122 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3123 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3124 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3125 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3126 | default: |
3127 | MISSING_CASE(rotation); | |
3128 | } | |
3129 | ||
c34ce3d1 | 3130 | return 0; |
6156a456 CK |
3131 | } |
3132 | ||
a8d201af ML |
3133 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3134 | const struct intel_crtc_state *crtc_state, | |
3135 | const struct intel_plane_state *plane_state) | |
6156a456 | 3136 | { |
a8d201af | 3137 | struct drm_device *dev = plane->dev; |
fac5e23e | 3138 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3140 | struct drm_framebuffer *fb = plane_state->base.fb; | |
6156a456 | 3141 | int pipe = intel_crtc->pipe; |
d2196774 | 3142 | u32 plane_ctl; |
a8d201af | 3143 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3144 | u32 stride = skl_plane_stride(fb, 0, rotation); |
44eb0cb9 | 3145 | u32 surf_addr; |
a8d201af ML |
3146 | int scaler_id = plane_state->scaler_id; |
3147 | int src_x = plane_state->src.x1 >> 16; | |
3148 | int src_y = plane_state->src.y1 >> 16; | |
3149 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3150 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3151 | int dst_x = plane_state->dst.x1; | |
3152 | int dst_y = plane_state->dst.y1; | |
3153 | int dst_w = drm_rect_width(&plane_state->dst); | |
3154 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3155 | |
6156a456 CK |
3156 | plane_ctl = PLANE_CTL_ENABLE | |
3157 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3158 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3159 | ||
3160 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3161 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3162 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3163 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3164 | ||
3b7a5119 | 3165 | if (intel_rotation_90_or_270(rotation)) { |
6687c906 VS |
3166 | struct drm_rect r = { |
3167 | .x1 = src_x, | |
3168 | .x2 = src_x + src_w, | |
3169 | .y1 = src_y, | |
3170 | .y2 = src_y + src_h, | |
3171 | }; | |
6687c906 VS |
3172 | |
3173 | /* Rotate src coordinates to match rotated GTT view */ | |
3174 | drm_rect_rotate(&r, fb->width, fb->height, BIT(DRM_ROTATE_270)); | |
832be82f | 3175 | |
6687c906 VS |
3176 | src_x = r.x1; |
3177 | src_y = r.y1; | |
3178 | src_w = drm_rect_width(&r); | |
3179 | src_h = drm_rect_height(&r); | |
3b7a5119 | 3180 | } |
b321803d | 3181 | |
6687c906 | 3182 | intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation); |
ef78ec94 | 3183 | surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, rotation); |
6687c906 VS |
3184 | |
3185 | /* Sizes are 0 based */ | |
3186 | src_w--; | |
3187 | src_h--; | |
3188 | dst_w--; | |
3189 | dst_h--; | |
3190 | ||
3191 | intel_crtc->adjusted_x = src_x; | |
3192 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3193 | |
70d21f0e | 3194 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
6687c906 | 3195 | I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); |
ef78ec94 | 3196 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
6687c906 | 3197 | I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); |
6156a456 CK |
3198 | |
3199 | if (scaler_id >= 0) { | |
3200 | uint32_t ps_ctrl = 0; | |
3201 | ||
3202 | WARN_ON(!dst_w || !dst_h); | |
3203 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3204 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3205 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3206 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3207 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3208 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3209 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3210 | } else { | |
3211 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3212 | } | |
3213 | ||
6687c906 VS |
3214 | I915_WRITE(PLANE_SURF(pipe, 0), |
3215 | intel_fb_gtt_offset(fb, rotation) + surf_addr); | |
70d21f0e DL |
3216 | |
3217 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3218 | } | |
3219 | ||
a8d201af ML |
3220 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3221 | struct drm_crtc *crtc) | |
17638cd6 JB |
3222 | { |
3223 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3224 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af | 3225 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3226 | |
a8d201af ML |
3227 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3228 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3229 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3230 | } | |
29b9bde6 | 3231 | |
a8d201af ML |
3232 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3233 | static int | |
3234 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3235 | int x, int y, enum mode_set_atomic state) | |
3236 | { | |
3237 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3238 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3239 | ||
3240 | return -ENODEV; | |
81255565 JB |
3241 | } |
3242 | ||
5a21b665 DV |
3243 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3244 | { | |
3245 | struct intel_crtc *crtc; | |
3246 | ||
91c8a326 | 3247 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3248 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3249 | } | |
3250 | ||
7514747d VS |
3251 | static void intel_update_primary_planes(struct drm_device *dev) |
3252 | { | |
7514747d | 3253 | struct drm_crtc *crtc; |
96a02917 | 3254 | |
70e1e0ec | 3255 | for_each_crtc(dev, crtc) { |
11c22da6 | 3256 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3257 | struct intel_plane_state *plane_state = |
3258 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3259 | |
a8d201af ML |
3260 | if (plane_state->visible) |
3261 | plane->update_plane(&plane->base, | |
3262 | to_intel_crtc_state(crtc->state), | |
3263 | plane_state); | |
73974893 ML |
3264 | } |
3265 | } | |
3266 | ||
3267 | static int | |
3268 | __intel_display_resume(struct drm_device *dev, | |
3269 | struct drm_atomic_state *state) | |
3270 | { | |
3271 | struct drm_crtc_state *crtc_state; | |
3272 | struct drm_crtc *crtc; | |
3273 | int i, ret; | |
11c22da6 | 3274 | |
73974893 ML |
3275 | intel_modeset_setup_hw_state(dev); |
3276 | i915_redisable_vga(dev); | |
3277 | ||
3278 | if (!state) | |
3279 | return 0; | |
3280 | ||
3281 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3282 | /* | |
3283 | * Force recalculation even if we restore | |
3284 | * current state. With fast modeset this may not result | |
3285 | * in a modeset when the state is compatible. | |
3286 | */ | |
3287 | crtc_state->mode_changed = true; | |
96a02917 | 3288 | } |
73974893 ML |
3289 | |
3290 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3291 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3292 | ||
3293 | ret = drm_atomic_commit(state); | |
3294 | ||
3295 | WARN_ON(ret == -EDEADLK); | |
3296 | return ret; | |
96a02917 VS |
3297 | } |
3298 | ||
4ac2ba2f VS |
3299 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3300 | { | |
ae98104b VS |
3301 | return intel_has_gpu_reset(dev_priv) && |
3302 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3303 | } |
3304 | ||
c033666a | 3305 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3306 | { |
73974893 ML |
3307 | struct drm_device *dev = &dev_priv->drm; |
3308 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3309 | struct drm_atomic_state *state; | |
3310 | int ret; | |
3311 | ||
73974893 ML |
3312 | /* |
3313 | * Need mode_config.mutex so that we don't | |
3314 | * trample ongoing ->detect() and whatnot. | |
3315 | */ | |
3316 | mutex_lock(&dev->mode_config.mutex); | |
3317 | drm_modeset_acquire_init(ctx, 0); | |
3318 | while (1) { | |
3319 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3320 | if (ret != -EDEADLK) | |
3321 | break; | |
3322 | ||
3323 | drm_modeset_backoff(ctx); | |
3324 | } | |
3325 | ||
3326 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3327 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3328 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3329 | return; |
3330 | ||
f98ce92f VS |
3331 | /* |
3332 | * Disabling the crtcs gracefully seems nicer. Also the | |
3333 | * g33 docs say we should at least disable all the planes. | |
3334 | */ | |
73974893 ML |
3335 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3336 | if (IS_ERR(state)) { | |
3337 | ret = PTR_ERR(state); | |
3338 | state = NULL; | |
3339 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3340 | goto err; | |
3341 | } | |
3342 | ||
3343 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3344 | if (ret) { | |
3345 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3346 | goto err; | |
3347 | } | |
3348 | ||
3349 | dev_priv->modeset_restore_state = state; | |
3350 | state->acquire_ctx = ctx; | |
3351 | return; | |
3352 | ||
3353 | err: | |
3354 | drm_atomic_state_free(state); | |
7514747d VS |
3355 | } |
3356 | ||
c033666a | 3357 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3358 | { |
73974893 ML |
3359 | struct drm_device *dev = &dev_priv->drm; |
3360 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3361 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3362 | int ret; | |
3363 | ||
5a21b665 DV |
3364 | /* |
3365 | * Flips in the rings will be nuked by the reset, | |
3366 | * so complete all pending flips so that user space | |
3367 | * will get its events and not get stuck. | |
3368 | */ | |
3369 | intel_complete_page_flips(dev_priv); | |
3370 | ||
73974893 ML |
3371 | dev_priv->modeset_restore_state = NULL; |
3372 | ||
7514747d | 3373 | /* reset doesn't touch the display */ |
4ac2ba2f | 3374 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3375 | if (!state) { |
3376 | /* | |
3377 | * Flips in the rings have been nuked by the reset, | |
3378 | * so update the base address of all primary | |
3379 | * planes to the the last fb to make sure we're | |
3380 | * showing the correct fb after a reset. | |
3381 | * | |
3382 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3383 | * CS-based flips (which might get lost in gpu resets) any more. | |
3384 | */ | |
3385 | intel_update_primary_planes(dev); | |
3386 | } else { | |
3387 | ret = __intel_display_resume(dev, state); | |
3388 | if (ret) | |
3389 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3390 | } | |
73974893 ML |
3391 | } else { |
3392 | /* | |
3393 | * The display has been reset as well, | |
3394 | * so need a full re-initialization. | |
3395 | */ | |
3396 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3397 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3398 | |
73974893 | 3399 | intel_modeset_init_hw(dev); |
7514747d | 3400 | |
73974893 ML |
3401 | spin_lock_irq(&dev_priv->irq_lock); |
3402 | if (dev_priv->display.hpd_irq_setup) | |
3403 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3404 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3405 | |
73974893 ML |
3406 | ret = __intel_display_resume(dev, state); |
3407 | if (ret) | |
3408 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3409 | |
73974893 ML |
3410 | intel_hpd_init(dev_priv); |
3411 | } | |
7514747d | 3412 | |
73974893 ML |
3413 | drm_modeset_drop_locks(ctx); |
3414 | drm_modeset_acquire_fini(ctx); | |
3415 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3416 | } |
3417 | ||
7d5e3799 CW |
3418 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3419 | { | |
5a21b665 DV |
3420 | struct drm_device *dev = crtc->dev; |
3421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3422 | unsigned reset_counter; | |
3423 | bool pending; | |
3424 | ||
3425 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3426 | if (intel_crtc->reset_counter != reset_counter) | |
3427 | return false; | |
3428 | ||
3429 | spin_lock_irq(&dev->event_lock); | |
3430 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3431 | spin_unlock_irq(&dev->event_lock); | |
3432 | ||
3433 | return pending; | |
7d5e3799 CW |
3434 | } |
3435 | ||
bfd16b2a ML |
3436 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3437 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3438 | { |
3439 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3440 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3441 | struct intel_crtc_state *pipe_config = |
3442 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3443 | |
bfd16b2a ML |
3444 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3445 | crtc->base.mode = crtc->base.state->mode; | |
3446 | ||
3447 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3448 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3449 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3450 | |
3451 | /* | |
3452 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3453 | * that in compute_mode_changes we check the native mode (not the pfit | |
3454 | * mode) to see if we can flip rather than do a full mode set. In the | |
3455 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3456 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3457 | * sized surface. | |
e30e8f75 GP |
3458 | */ |
3459 | ||
e30e8f75 | 3460 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3461 | ((pipe_config->pipe_src_w - 1) << 16) | |
3462 | (pipe_config->pipe_src_h - 1)); | |
3463 | ||
3464 | /* on skylake this is done by detaching scalers */ | |
3465 | if (INTEL_INFO(dev)->gen >= 9) { | |
3466 | skl_detach_scalers(crtc); | |
3467 | ||
3468 | if (pipe_config->pch_pfit.enabled) | |
3469 | skylake_pfit_enable(crtc); | |
3470 | } else if (HAS_PCH_SPLIT(dev)) { | |
3471 | if (pipe_config->pch_pfit.enabled) | |
3472 | ironlake_pfit_enable(crtc); | |
3473 | else if (old_crtc_state->pch_pfit.enabled) | |
3474 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3475 | } |
e30e8f75 GP |
3476 | } |
3477 | ||
5e84e1a4 ZW |
3478 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3479 | { | |
3480 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3481 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3483 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3484 | i915_reg_t reg; |
3485 | u32 temp; | |
5e84e1a4 ZW |
3486 | |
3487 | /* enable normal train */ | |
3488 | reg = FDI_TX_CTL(pipe); | |
3489 | temp = I915_READ(reg); | |
61e499bf | 3490 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3491 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3492 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3493 | } else { |
3494 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3495 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3496 | } |
5e84e1a4 ZW |
3497 | I915_WRITE(reg, temp); |
3498 | ||
3499 | reg = FDI_RX_CTL(pipe); | |
3500 | temp = I915_READ(reg); | |
3501 | if (HAS_PCH_CPT(dev)) { | |
3502 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3503 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3504 | } else { | |
3505 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3506 | temp |= FDI_LINK_TRAIN_NONE; | |
3507 | } | |
3508 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3509 | ||
3510 | /* wait one idle pattern time */ | |
3511 | POSTING_READ(reg); | |
3512 | udelay(1000); | |
357555c0 JB |
3513 | |
3514 | /* IVB wants error correction enabled */ | |
3515 | if (IS_IVYBRIDGE(dev)) | |
3516 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3517 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3518 | } |
3519 | ||
8db9d77b ZW |
3520 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3521 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3522 | { | |
3523 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3524 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3525 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3526 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3527 | i915_reg_t reg; |
3528 | u32 temp, tries; | |
8db9d77b | 3529 | |
1c8562f6 | 3530 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3531 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3532 | |
e1a44743 AJ |
3533 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3534 | for train result */ | |
5eddb70b CW |
3535 | reg = FDI_RX_IMR(pipe); |
3536 | temp = I915_READ(reg); | |
e1a44743 AJ |
3537 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3538 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3539 | I915_WRITE(reg, temp); |
3540 | I915_READ(reg); | |
e1a44743 AJ |
3541 | udelay(150); |
3542 | ||
8db9d77b | 3543 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3544 | reg = FDI_TX_CTL(pipe); |
3545 | temp = I915_READ(reg); | |
627eb5a3 | 3546 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3547 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3548 | temp &= ~FDI_LINK_TRAIN_NONE; |
3549 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3550 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3551 | |
5eddb70b CW |
3552 | reg = FDI_RX_CTL(pipe); |
3553 | temp = I915_READ(reg); | |
8db9d77b ZW |
3554 | temp &= ~FDI_LINK_TRAIN_NONE; |
3555 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3556 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3557 | ||
3558 | POSTING_READ(reg); | |
8db9d77b ZW |
3559 | udelay(150); |
3560 | ||
5b2adf89 | 3561 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3562 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3563 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3564 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3565 | |
5eddb70b | 3566 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3567 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3568 | temp = I915_READ(reg); |
8db9d77b ZW |
3569 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3570 | ||
3571 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3572 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3573 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3574 | break; |
3575 | } | |
8db9d77b | 3576 | } |
e1a44743 | 3577 | if (tries == 5) |
5eddb70b | 3578 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3579 | |
3580 | /* Train 2 */ | |
5eddb70b CW |
3581 | reg = FDI_TX_CTL(pipe); |
3582 | temp = I915_READ(reg); | |
8db9d77b ZW |
3583 | temp &= ~FDI_LINK_TRAIN_NONE; |
3584 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3585 | I915_WRITE(reg, temp); |
8db9d77b | 3586 | |
5eddb70b CW |
3587 | reg = FDI_RX_CTL(pipe); |
3588 | temp = I915_READ(reg); | |
8db9d77b ZW |
3589 | temp &= ~FDI_LINK_TRAIN_NONE; |
3590 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3591 | I915_WRITE(reg, temp); |
8db9d77b | 3592 | |
5eddb70b CW |
3593 | POSTING_READ(reg); |
3594 | udelay(150); | |
8db9d77b | 3595 | |
5eddb70b | 3596 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3597 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3598 | temp = I915_READ(reg); |
8db9d77b ZW |
3599 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3600 | ||
3601 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3602 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3603 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3604 | break; | |
3605 | } | |
8db9d77b | 3606 | } |
e1a44743 | 3607 | if (tries == 5) |
5eddb70b | 3608 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3609 | |
3610 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3611 | |
8db9d77b ZW |
3612 | } |
3613 | ||
0206e353 | 3614 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3615 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3616 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3617 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3618 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3619 | }; | |
3620 | ||
3621 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3622 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3623 | { | |
3624 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3625 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3626 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3627 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3628 | i915_reg_t reg; |
3629 | u32 temp, i, retry; | |
8db9d77b | 3630 | |
e1a44743 AJ |
3631 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3632 | for train result */ | |
5eddb70b CW |
3633 | reg = FDI_RX_IMR(pipe); |
3634 | temp = I915_READ(reg); | |
e1a44743 AJ |
3635 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3636 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3637 | I915_WRITE(reg, temp); |
3638 | ||
3639 | POSTING_READ(reg); | |
e1a44743 AJ |
3640 | udelay(150); |
3641 | ||
8db9d77b | 3642 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3643 | reg = FDI_TX_CTL(pipe); |
3644 | temp = I915_READ(reg); | |
627eb5a3 | 3645 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3646 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3647 | temp &= ~FDI_LINK_TRAIN_NONE; |
3648 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3649 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3650 | /* SNB-B */ | |
3651 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3652 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3653 | |
d74cf324 DV |
3654 | I915_WRITE(FDI_RX_MISC(pipe), |
3655 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3656 | ||
5eddb70b CW |
3657 | reg = FDI_RX_CTL(pipe); |
3658 | temp = I915_READ(reg); | |
8db9d77b ZW |
3659 | if (HAS_PCH_CPT(dev)) { |
3660 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3661 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3662 | } else { | |
3663 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3664 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3665 | } | |
5eddb70b CW |
3666 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3667 | ||
3668 | POSTING_READ(reg); | |
8db9d77b ZW |
3669 | udelay(150); |
3670 | ||
0206e353 | 3671 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3672 | reg = FDI_TX_CTL(pipe); |
3673 | temp = I915_READ(reg); | |
8db9d77b ZW |
3674 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3675 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3676 | I915_WRITE(reg, temp); |
3677 | ||
3678 | POSTING_READ(reg); | |
8db9d77b ZW |
3679 | udelay(500); |
3680 | ||
fa37d39e SP |
3681 | for (retry = 0; retry < 5; retry++) { |
3682 | reg = FDI_RX_IIR(pipe); | |
3683 | temp = I915_READ(reg); | |
3684 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3685 | if (temp & FDI_RX_BIT_LOCK) { | |
3686 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3687 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3688 | break; | |
3689 | } | |
3690 | udelay(50); | |
8db9d77b | 3691 | } |
fa37d39e SP |
3692 | if (retry < 5) |
3693 | break; | |
8db9d77b ZW |
3694 | } |
3695 | if (i == 4) | |
5eddb70b | 3696 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3697 | |
3698 | /* Train 2 */ | |
5eddb70b CW |
3699 | reg = FDI_TX_CTL(pipe); |
3700 | temp = I915_READ(reg); | |
8db9d77b ZW |
3701 | temp &= ~FDI_LINK_TRAIN_NONE; |
3702 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3703 | if (IS_GEN6(dev)) { | |
3704 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3705 | /* SNB-B */ | |
3706 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3707 | } | |
5eddb70b | 3708 | I915_WRITE(reg, temp); |
8db9d77b | 3709 | |
5eddb70b CW |
3710 | reg = FDI_RX_CTL(pipe); |
3711 | temp = I915_READ(reg); | |
8db9d77b ZW |
3712 | if (HAS_PCH_CPT(dev)) { |
3713 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3714 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3715 | } else { | |
3716 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3717 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3718 | } | |
5eddb70b CW |
3719 | I915_WRITE(reg, temp); |
3720 | ||
3721 | POSTING_READ(reg); | |
8db9d77b ZW |
3722 | udelay(150); |
3723 | ||
0206e353 | 3724 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3725 | reg = FDI_TX_CTL(pipe); |
3726 | temp = I915_READ(reg); | |
8db9d77b ZW |
3727 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3728 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3729 | I915_WRITE(reg, temp); |
3730 | ||
3731 | POSTING_READ(reg); | |
8db9d77b ZW |
3732 | udelay(500); |
3733 | ||
fa37d39e SP |
3734 | for (retry = 0; retry < 5; retry++) { |
3735 | reg = FDI_RX_IIR(pipe); | |
3736 | temp = I915_READ(reg); | |
3737 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3738 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3739 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3740 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3741 | break; | |
3742 | } | |
3743 | udelay(50); | |
8db9d77b | 3744 | } |
fa37d39e SP |
3745 | if (retry < 5) |
3746 | break; | |
8db9d77b ZW |
3747 | } |
3748 | if (i == 4) | |
5eddb70b | 3749 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3750 | |
3751 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3752 | } | |
3753 | ||
357555c0 JB |
3754 | /* Manual link training for Ivy Bridge A0 parts */ |
3755 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3756 | { | |
3757 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3758 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3760 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3761 | i915_reg_t reg; |
3762 | u32 temp, i, j; | |
357555c0 JB |
3763 | |
3764 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3765 | for train result */ | |
3766 | reg = FDI_RX_IMR(pipe); | |
3767 | temp = I915_READ(reg); | |
3768 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3769 | temp &= ~FDI_RX_BIT_LOCK; | |
3770 | I915_WRITE(reg, temp); | |
3771 | ||
3772 | POSTING_READ(reg); | |
3773 | udelay(150); | |
3774 | ||
01a415fd DV |
3775 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3776 | I915_READ(FDI_RX_IIR(pipe))); | |
3777 | ||
139ccd3f JB |
3778 | /* Try each vswing and preemphasis setting twice before moving on */ |
3779 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3780 | /* disable first in case we need to retry */ | |
3781 | reg = FDI_TX_CTL(pipe); | |
3782 | temp = I915_READ(reg); | |
3783 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3784 | temp &= ~FDI_TX_ENABLE; | |
3785 | I915_WRITE(reg, temp); | |
357555c0 | 3786 | |
139ccd3f JB |
3787 | reg = FDI_RX_CTL(pipe); |
3788 | temp = I915_READ(reg); | |
3789 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3790 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3791 | temp &= ~FDI_RX_ENABLE; | |
3792 | I915_WRITE(reg, temp); | |
357555c0 | 3793 | |
139ccd3f | 3794 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3795 | reg = FDI_TX_CTL(pipe); |
3796 | temp = I915_READ(reg); | |
139ccd3f | 3797 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3798 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3799 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3800 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3801 | temp |= snb_b_fdi_train_param[j/2]; |
3802 | temp |= FDI_COMPOSITE_SYNC; | |
3803 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3804 | |
139ccd3f JB |
3805 | I915_WRITE(FDI_RX_MISC(pipe), |
3806 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3807 | |
139ccd3f | 3808 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3809 | temp = I915_READ(reg); |
139ccd3f JB |
3810 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3811 | temp |= FDI_COMPOSITE_SYNC; | |
3812 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3813 | |
139ccd3f JB |
3814 | POSTING_READ(reg); |
3815 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3816 | |
139ccd3f JB |
3817 | for (i = 0; i < 4; i++) { |
3818 | reg = FDI_RX_IIR(pipe); | |
3819 | temp = I915_READ(reg); | |
3820 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3821 | |
139ccd3f JB |
3822 | if (temp & FDI_RX_BIT_LOCK || |
3823 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3824 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3825 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3826 | i); | |
3827 | break; | |
3828 | } | |
3829 | udelay(1); /* should be 0.5us */ | |
3830 | } | |
3831 | if (i == 4) { | |
3832 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3833 | continue; | |
3834 | } | |
357555c0 | 3835 | |
139ccd3f | 3836 | /* Train 2 */ |
357555c0 JB |
3837 | reg = FDI_TX_CTL(pipe); |
3838 | temp = I915_READ(reg); | |
139ccd3f JB |
3839 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3840 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3841 | I915_WRITE(reg, temp); | |
3842 | ||
3843 | reg = FDI_RX_CTL(pipe); | |
3844 | temp = I915_READ(reg); | |
3845 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3846 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3847 | I915_WRITE(reg, temp); |
3848 | ||
3849 | POSTING_READ(reg); | |
139ccd3f | 3850 | udelay(2); /* should be 1.5us */ |
357555c0 | 3851 | |
139ccd3f JB |
3852 | for (i = 0; i < 4; i++) { |
3853 | reg = FDI_RX_IIR(pipe); | |
3854 | temp = I915_READ(reg); | |
3855 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3856 | |
139ccd3f JB |
3857 | if (temp & FDI_RX_SYMBOL_LOCK || |
3858 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3859 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3860 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3861 | i); | |
3862 | goto train_done; | |
3863 | } | |
3864 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3865 | } |
139ccd3f JB |
3866 | if (i == 4) |
3867 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3868 | } |
357555c0 | 3869 | |
139ccd3f | 3870 | train_done: |
357555c0 JB |
3871 | DRM_DEBUG_KMS("FDI train done.\n"); |
3872 | } | |
3873 | ||
88cefb6c | 3874 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3875 | { |
88cefb6c | 3876 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 3877 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 3878 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3879 | i915_reg_t reg; |
3880 | u32 temp; | |
c64e311e | 3881 | |
c98e9dcf | 3882 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3883 | reg = FDI_RX_CTL(pipe); |
3884 | temp = I915_READ(reg); | |
627eb5a3 | 3885 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3886 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3887 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3888 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3889 | ||
3890 | POSTING_READ(reg); | |
c98e9dcf JB |
3891 | udelay(200); |
3892 | ||
3893 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3894 | temp = I915_READ(reg); |
3895 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3896 | ||
3897 | POSTING_READ(reg); | |
c98e9dcf JB |
3898 | udelay(200); |
3899 | ||
20749730 PZ |
3900 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3901 | reg = FDI_TX_CTL(pipe); | |
3902 | temp = I915_READ(reg); | |
3903 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3904 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3905 | |
20749730 PZ |
3906 | POSTING_READ(reg); |
3907 | udelay(100); | |
6be4a607 | 3908 | } |
0e23b99d JB |
3909 | } |
3910 | ||
88cefb6c DV |
3911 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3912 | { | |
3913 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3914 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 3915 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3916 | i915_reg_t reg; |
3917 | u32 temp; | |
88cefb6c DV |
3918 | |
3919 | /* Switch from PCDclk to Rawclk */ | |
3920 | reg = FDI_RX_CTL(pipe); | |
3921 | temp = I915_READ(reg); | |
3922 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3923 | ||
3924 | /* Disable CPU FDI TX PLL */ | |
3925 | reg = FDI_TX_CTL(pipe); | |
3926 | temp = I915_READ(reg); | |
3927 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3928 | ||
3929 | POSTING_READ(reg); | |
3930 | udelay(100); | |
3931 | ||
3932 | reg = FDI_RX_CTL(pipe); | |
3933 | temp = I915_READ(reg); | |
3934 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3935 | ||
3936 | /* Wait for the clocks to turn off. */ | |
3937 | POSTING_READ(reg); | |
3938 | udelay(100); | |
3939 | } | |
3940 | ||
0fc932b8 JB |
3941 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3942 | { | |
3943 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3944 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
3945 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3946 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3947 | i915_reg_t reg; |
3948 | u32 temp; | |
0fc932b8 JB |
3949 | |
3950 | /* disable CPU FDI tx and PCH FDI rx */ | |
3951 | reg = FDI_TX_CTL(pipe); | |
3952 | temp = I915_READ(reg); | |
3953 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3954 | POSTING_READ(reg); | |
3955 | ||
3956 | reg = FDI_RX_CTL(pipe); | |
3957 | temp = I915_READ(reg); | |
3958 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3959 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3960 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3961 | ||
3962 | POSTING_READ(reg); | |
3963 | udelay(100); | |
3964 | ||
3965 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3966 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3967 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3968 | |
3969 | /* still set train pattern 1 */ | |
3970 | reg = FDI_TX_CTL(pipe); | |
3971 | temp = I915_READ(reg); | |
3972 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3973 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3974 | I915_WRITE(reg, temp); | |
3975 | ||
3976 | reg = FDI_RX_CTL(pipe); | |
3977 | temp = I915_READ(reg); | |
3978 | if (HAS_PCH_CPT(dev)) { | |
3979 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3980 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3981 | } else { | |
3982 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3983 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3984 | } | |
3985 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3986 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3987 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3988 | I915_WRITE(reg, temp); |
3989 | ||
3990 | POSTING_READ(reg); | |
3991 | udelay(100); | |
3992 | } | |
3993 | ||
5dce5b93 CW |
3994 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3995 | { | |
3996 | struct intel_crtc *crtc; | |
3997 | ||
3998 | /* Note that we don't need to be called with mode_config.lock here | |
3999 | * as our list of CRTC objects is static for the lifetime of the | |
4000 | * device and so cannot disappear as we iterate. Similarly, we can | |
4001 | * happily treat the predicates as racy, atomic checks as userspace | |
4002 | * cannot claim and pin a new fb without at least acquring the | |
4003 | * struct_mutex and so serialising with us. | |
4004 | */ | |
d3fcc808 | 4005 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
4006 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4007 | continue; | |
4008 | ||
5a21b665 | 4009 | if (crtc->flip_work) |
5dce5b93 CW |
4010 | intel_wait_for_vblank(dev, crtc->pipe); |
4011 | ||
4012 | return true; | |
4013 | } | |
4014 | ||
4015 | return false; | |
4016 | } | |
4017 | ||
5a21b665 | 4018 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4019 | { |
4020 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4021 | struct intel_flip_work *work = intel_crtc->flip_work; |
4022 | ||
4023 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4024 | |
4025 | if (work->event) | |
560ce1dc | 4026 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4027 | |
4028 | drm_crtc_vblank_put(&intel_crtc->base); | |
4029 | ||
5a21b665 | 4030 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4031 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4032 | |
4033 | trace_i915_flip_complete(intel_crtc->plane, | |
4034 | work->pending_flip_obj); | |
d6bbafa1 CW |
4035 | } |
4036 | ||
5008e874 | 4037 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4038 | { |
0f91128d | 4039 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4040 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4041 | long ret; |
e6c3a2a6 | 4042 | |
2c10d571 | 4043 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4044 | |
4045 | ret = wait_event_interruptible_timeout( | |
4046 | dev_priv->pending_flip_queue, | |
4047 | !intel_crtc_has_pending_flip(crtc), | |
4048 | 60*HZ); | |
4049 | ||
4050 | if (ret < 0) | |
4051 | return ret; | |
4052 | ||
5a21b665 DV |
4053 | if (ret == 0) { |
4054 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4055 | struct intel_flip_work *work; | |
4056 | ||
4057 | spin_lock_irq(&dev->event_lock); | |
4058 | work = intel_crtc->flip_work; | |
4059 | if (work && !is_mmio_work(work)) { | |
4060 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4061 | page_flip_completed(intel_crtc); | |
4062 | } | |
4063 | spin_unlock_irq(&dev->event_lock); | |
4064 | } | |
5bb61643 | 4065 | |
5008e874 | 4066 | return 0; |
e6c3a2a6 CW |
4067 | } |
4068 | ||
060f02d8 VS |
4069 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
4070 | { | |
4071 | u32 temp; | |
4072 | ||
4073 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4074 | ||
4075 | mutex_lock(&dev_priv->sb_lock); | |
4076 | ||
4077 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4078 | temp |= SBI_SSCCTL_DISABLE; | |
4079 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4080 | ||
4081 | mutex_unlock(&dev_priv->sb_lock); | |
4082 | } | |
4083 | ||
e615efe4 ED |
4084 | /* Program iCLKIP clock to the desired frequency */ |
4085 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4086 | { | |
64b46a06 | 4087 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4088 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4089 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4090 | u32 temp; | |
4091 | ||
060f02d8 | 4092 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4093 | |
64b46a06 VS |
4094 | /* The iCLK virtual clock root frequency is in MHz, |
4095 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4096 | * divisors, it is necessary to divide one by another, so we | |
4097 | * convert the virtual clock precision to KHz here for higher | |
4098 | * precision. | |
4099 | */ | |
4100 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4101 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4102 | u32 iclk_pi_range = 64; | |
64b46a06 | 4103 | u32 desired_divisor; |
e615efe4 | 4104 | |
64b46a06 VS |
4105 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4106 | clock << auxdiv); | |
4107 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4108 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4109 | |
64b46a06 VS |
4110 | /* |
4111 | * Near 20MHz is a corner case which is | |
4112 | * out of range for the 7-bit divisor | |
4113 | */ | |
4114 | if (divsel <= 0x7f) | |
4115 | break; | |
e615efe4 ED |
4116 | } |
4117 | ||
4118 | /* This should not happen with any sane values */ | |
4119 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4120 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4121 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4122 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4123 | ||
4124 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4125 | clock, |
e615efe4 ED |
4126 | auxdiv, |
4127 | divsel, | |
4128 | phasedir, | |
4129 | phaseinc); | |
4130 | ||
060f02d8 VS |
4131 | mutex_lock(&dev_priv->sb_lock); |
4132 | ||
e615efe4 | 4133 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4134 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4135 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4136 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4137 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4138 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4139 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4140 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4141 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4142 | |
4143 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4144 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4145 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4146 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4147 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4148 | |
4149 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4150 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4151 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4152 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4153 | |
060f02d8 VS |
4154 | mutex_unlock(&dev_priv->sb_lock); |
4155 | ||
e615efe4 ED |
4156 | /* Wait for initialization time */ |
4157 | udelay(24); | |
4158 | ||
4159 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4160 | } | |
4161 | ||
8802e5b6 VS |
4162 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4163 | { | |
4164 | u32 divsel, phaseinc, auxdiv; | |
4165 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4166 | u32 iclk_pi_range = 64; | |
4167 | u32 desired_divisor; | |
4168 | u32 temp; | |
4169 | ||
4170 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4171 | return 0; | |
4172 | ||
4173 | mutex_lock(&dev_priv->sb_lock); | |
4174 | ||
4175 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4176 | if (temp & SBI_SSCCTL_DISABLE) { | |
4177 | mutex_unlock(&dev_priv->sb_lock); | |
4178 | return 0; | |
4179 | } | |
4180 | ||
4181 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4182 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4183 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4184 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4185 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4186 | ||
4187 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4188 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4189 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4190 | ||
4191 | mutex_unlock(&dev_priv->sb_lock); | |
4192 | ||
4193 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4194 | ||
4195 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4196 | desired_divisor << auxdiv); | |
4197 | } | |
4198 | ||
275f01b2 DV |
4199 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4200 | enum pipe pch_transcoder) | |
4201 | { | |
4202 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4203 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4204 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4205 | |
4206 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4207 | I915_READ(HTOTAL(cpu_transcoder))); | |
4208 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4209 | I915_READ(HBLANK(cpu_transcoder))); | |
4210 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4211 | I915_READ(HSYNC(cpu_transcoder))); | |
4212 | ||
4213 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4214 | I915_READ(VTOTAL(cpu_transcoder))); | |
4215 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4216 | I915_READ(VBLANK(cpu_transcoder))); | |
4217 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4218 | I915_READ(VSYNC(cpu_transcoder))); | |
4219 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4220 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4221 | } | |
4222 | ||
003632d9 | 4223 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4224 | { |
fac5e23e | 4225 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4226 | uint32_t temp; |
4227 | ||
4228 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4229 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4230 | return; |
4231 | ||
4232 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4233 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4234 | ||
003632d9 ACO |
4235 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4236 | if (enable) | |
4237 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4238 | ||
4239 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4240 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4241 | POSTING_READ(SOUTH_CHICKEN1); | |
4242 | } | |
4243 | ||
4244 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4245 | { | |
4246 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4247 | |
4248 | switch (intel_crtc->pipe) { | |
4249 | case PIPE_A: | |
4250 | break; | |
4251 | case PIPE_B: | |
6e3c9717 | 4252 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4253 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4254 | else |
003632d9 | 4255 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4256 | |
4257 | break; | |
4258 | case PIPE_C: | |
003632d9 | 4259 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4260 | |
4261 | break; | |
4262 | default: | |
4263 | BUG(); | |
4264 | } | |
4265 | } | |
4266 | ||
c48b5305 VS |
4267 | /* Return which DP Port should be selected for Transcoder DP control */ |
4268 | static enum port | |
4269 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4270 | { | |
4271 | struct drm_device *dev = crtc->dev; | |
4272 | struct intel_encoder *encoder; | |
4273 | ||
4274 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4275 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4276 | encoder->type == INTEL_OUTPUT_EDP) |
4277 | return enc_to_dig_port(&encoder->base)->port; | |
4278 | } | |
4279 | ||
4280 | return -1; | |
4281 | } | |
4282 | ||
f67a559d JB |
4283 | /* |
4284 | * Enable PCH resources required for PCH ports: | |
4285 | * - PCH PLLs | |
4286 | * - FDI training & RX/TX | |
4287 | * - update transcoder timings | |
4288 | * - DP transcoding bits | |
4289 | * - transcoder | |
4290 | */ | |
4291 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4292 | { |
4293 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4294 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4295 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4296 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4297 | u32 temp; |
2c07245f | 4298 | |
ab9412ba | 4299 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4300 | |
1fbc0d78 DV |
4301 | if (IS_IVYBRIDGE(dev)) |
4302 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4303 | ||
cd986abb DV |
4304 | /* Write the TU size bits before fdi link training, so that error |
4305 | * detection works. */ | |
4306 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4307 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4308 | ||
c98e9dcf | 4309 | /* For PCH output, training FDI link */ |
674cf967 | 4310 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4311 | |
3ad8a208 DV |
4312 | /* We need to program the right clock selection before writing the pixel |
4313 | * mutliplier into the DPLL. */ | |
303b81e0 | 4314 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4315 | u32 sel; |
4b645f14 | 4316 | |
c98e9dcf | 4317 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4318 | temp |= TRANS_DPLL_ENABLE(pipe); |
4319 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4320 | if (intel_crtc->config->shared_dpll == |
4321 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4322 | temp |= sel; |
4323 | else | |
4324 | temp &= ~sel; | |
c98e9dcf | 4325 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4326 | } |
5eddb70b | 4327 | |
3ad8a208 DV |
4328 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4329 | * transcoder, and we actually should do this to not upset any PCH | |
4330 | * transcoder that already use the clock when we share it. | |
4331 | * | |
4332 | * Note that enable_shared_dpll tries to do the right thing, but | |
4333 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4334 | * the right LVDS enable sequence. */ | |
85b3894f | 4335 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4336 | |
d9b6cb56 JB |
4337 | /* set transcoder timing, panel must allow it */ |
4338 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4339 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4340 | |
303b81e0 | 4341 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4342 | |
c98e9dcf | 4343 | /* For PCH DP, enable TRANS_DP_CTL */ |
37a5650b | 4344 | if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) { |
9c4edaee VS |
4345 | const struct drm_display_mode *adjusted_mode = |
4346 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4347 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4348 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4349 | temp = I915_READ(reg); |
4350 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4351 | TRANS_DP_SYNC_MASK | |
4352 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4353 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4354 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4355 | |
9c4edaee | 4356 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4357 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4358 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4359 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4360 | |
4361 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4362 | case PORT_B: |
5eddb70b | 4363 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4364 | break; |
c48b5305 | 4365 | case PORT_C: |
5eddb70b | 4366 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4367 | break; |
c48b5305 | 4368 | case PORT_D: |
5eddb70b | 4369 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4370 | break; |
4371 | default: | |
e95d41e1 | 4372 | BUG(); |
32f9d658 | 4373 | } |
2c07245f | 4374 | |
5eddb70b | 4375 | I915_WRITE(reg, temp); |
6be4a607 | 4376 | } |
b52eb4dc | 4377 | |
b8a4f404 | 4378 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4379 | } |
4380 | ||
1507e5bd PZ |
4381 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4382 | { | |
4383 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4384 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4386 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4387 | |
ab9412ba | 4388 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4389 | |
8c52b5e8 | 4390 | lpt_program_iclkip(crtc); |
1507e5bd | 4391 | |
0540e488 | 4392 | /* Set transcoder timing. */ |
275f01b2 | 4393 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4394 | |
937bb610 | 4395 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4396 | } |
4397 | ||
a1520318 | 4398 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4399 | { |
fac5e23e | 4400 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4401 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4402 | u32 temp; |
4403 | ||
4404 | temp = I915_READ(dslreg); | |
4405 | udelay(500); | |
4406 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4407 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4408 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4409 | } |
4410 | } | |
4411 | ||
86adf9d7 ML |
4412 | static int |
4413 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4414 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4415 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4416 | { |
86adf9d7 ML |
4417 | struct intel_crtc_scaler_state *scaler_state = |
4418 | &crtc_state->scaler_state; | |
4419 | struct intel_crtc *intel_crtc = | |
4420 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4421 | int need_scaling; |
6156a456 CK |
4422 | |
4423 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4424 | (src_h != dst_w || src_w != dst_h): | |
4425 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4426 | |
4427 | /* | |
4428 | * if plane is being disabled or scaler is no more required or force detach | |
4429 | * - free scaler binded to this plane/crtc | |
4430 | * - in order to do this, update crtc->scaler_usage | |
4431 | * | |
4432 | * Here scaler state in crtc_state is set free so that | |
4433 | * scaler can be assigned to other user. Actual register | |
4434 | * update to free the scaler is done in plane/panel-fit programming. | |
4435 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4436 | */ | |
86adf9d7 | 4437 | if (force_detach || !need_scaling) { |
a1b2278e | 4438 | if (*scaler_id >= 0) { |
86adf9d7 | 4439 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4440 | scaler_state->scalers[*scaler_id].in_use = 0; |
4441 | ||
86adf9d7 ML |
4442 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4443 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4444 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4445 | scaler_state->scaler_users); |
4446 | *scaler_id = -1; | |
4447 | } | |
4448 | return 0; | |
4449 | } | |
4450 | ||
4451 | /* range checks */ | |
4452 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4453 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4454 | ||
4455 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4456 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4457 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4458 | "size is out of scaler range\n", |
86adf9d7 | 4459 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4460 | return -EINVAL; |
4461 | } | |
4462 | ||
86adf9d7 ML |
4463 | /* mark this plane as a scaler user in crtc_state */ |
4464 | scaler_state->scaler_users |= (1 << scaler_user); | |
4465 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4466 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4467 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4468 | scaler_state->scaler_users); | |
4469 | ||
4470 | return 0; | |
4471 | } | |
4472 | ||
4473 | /** | |
4474 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4475 | * | |
4476 | * @state: crtc's scaler state | |
86adf9d7 ML |
4477 | * |
4478 | * Return | |
4479 | * 0 - scaler_usage updated successfully | |
4480 | * error - requested scaling cannot be supported or other error condition | |
4481 | */ | |
e435d6e5 | 4482 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4483 | { |
4484 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4485 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4486 | |
78108b7c VS |
4487 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4488 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4489 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4490 | |
e435d6e5 | 4491 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4492 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4493 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4494 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4495 | } |
4496 | ||
4497 | /** | |
4498 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4499 | * | |
4500 | * @state: crtc's scaler state | |
86adf9d7 ML |
4501 | * @plane_state: atomic plane state to update |
4502 | * | |
4503 | * Return | |
4504 | * 0 - scaler_usage updated successfully | |
4505 | * error - requested scaling cannot be supported or other error condition | |
4506 | */ | |
da20eabd ML |
4507 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4508 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4509 | { |
4510 | ||
4511 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4512 | struct intel_plane *intel_plane = |
4513 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4514 | struct drm_framebuffer *fb = plane_state->base.fb; |
4515 | int ret; | |
4516 | ||
4517 | bool force_detach = !fb || !plane_state->visible; | |
4518 | ||
72660ce0 VS |
4519 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4520 | intel_plane->base.base.id, intel_plane->base.name, | |
4521 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4522 | |
4523 | ret = skl_update_scaler(crtc_state, force_detach, | |
4524 | drm_plane_index(&intel_plane->base), | |
4525 | &plane_state->scaler_id, | |
4526 | plane_state->base.rotation, | |
4527 | drm_rect_width(&plane_state->src) >> 16, | |
4528 | drm_rect_height(&plane_state->src) >> 16, | |
4529 | drm_rect_width(&plane_state->dst), | |
4530 | drm_rect_height(&plane_state->dst)); | |
4531 | ||
4532 | if (ret || plane_state->scaler_id < 0) | |
4533 | return ret; | |
4534 | ||
a1b2278e | 4535 | /* check colorkey */ |
818ed961 | 4536 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4537 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4538 | intel_plane->base.base.id, | |
4539 | intel_plane->base.name); | |
a1b2278e CK |
4540 | return -EINVAL; |
4541 | } | |
4542 | ||
4543 | /* Check src format */ | |
86adf9d7 ML |
4544 | switch (fb->pixel_format) { |
4545 | case DRM_FORMAT_RGB565: | |
4546 | case DRM_FORMAT_XBGR8888: | |
4547 | case DRM_FORMAT_XRGB8888: | |
4548 | case DRM_FORMAT_ABGR8888: | |
4549 | case DRM_FORMAT_ARGB8888: | |
4550 | case DRM_FORMAT_XRGB2101010: | |
4551 | case DRM_FORMAT_XBGR2101010: | |
4552 | case DRM_FORMAT_YUYV: | |
4553 | case DRM_FORMAT_YVYU: | |
4554 | case DRM_FORMAT_UYVY: | |
4555 | case DRM_FORMAT_VYUY: | |
4556 | break; | |
4557 | default: | |
72660ce0 VS |
4558 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4559 | intel_plane->base.base.id, intel_plane->base.name, | |
4560 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4561 | return -EINVAL; |
a1b2278e CK |
4562 | } |
4563 | ||
a1b2278e CK |
4564 | return 0; |
4565 | } | |
4566 | ||
e435d6e5 ML |
4567 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4568 | { | |
4569 | int i; | |
4570 | ||
4571 | for (i = 0; i < crtc->num_scalers; i++) | |
4572 | skl_detach_scaler(crtc, i); | |
4573 | } | |
4574 | ||
4575 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4576 | { |
4577 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4578 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4579 | int pipe = crtc->pipe; |
a1b2278e CK |
4580 | struct intel_crtc_scaler_state *scaler_state = |
4581 | &crtc->config->scaler_state; | |
4582 | ||
4583 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4584 | ||
6e3c9717 | 4585 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4586 | int id; |
4587 | ||
4588 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4589 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4590 | return; | |
4591 | } | |
4592 | ||
4593 | id = scaler_state->scaler_id; | |
4594 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4595 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4596 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4597 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4598 | ||
4599 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4600 | } |
4601 | } | |
4602 | ||
b074cec8 JB |
4603 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4604 | { | |
4605 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4606 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4607 | int pipe = crtc->pipe; |
4608 | ||
6e3c9717 | 4609 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4610 | /* Force use of hard-coded filter coefficients |
4611 | * as some pre-programmed values are broken, | |
4612 | * e.g. x201. | |
4613 | */ | |
4614 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4615 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4616 | PF_PIPE_SEL_IVB(pipe)); | |
4617 | else | |
4618 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4619 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4620 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4621 | } |
4622 | } | |
4623 | ||
20bc8673 | 4624 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4625 | { |
cea165c3 | 4626 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4627 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4628 | |
6e3c9717 | 4629 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4630 | return; |
4631 | ||
307e4498 ML |
4632 | /* |
4633 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4634 | * This function is called from post_plane_update, which is run after | |
4635 | * a vblank wait. | |
4636 | */ | |
cea165c3 | 4637 | |
d77e4531 | 4638 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4639 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4640 | mutex_lock(&dev_priv->rps.hw_lock); |
4641 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4642 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4643 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4644 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4645 | * mailbox." Moreover, the mailbox may return a bogus state, |
4646 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4647 | */ |
4648 | } else { | |
4649 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4650 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4651 | * is essentially intel_wait_for_vblank. If we don't have this | |
4652 | * and don't wait for vblanks until the end of crtc_enable, then | |
4653 | * the HW state readout code will complain that the expected | |
4654 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4655 | if (intel_wait_for_register(dev_priv, |
4656 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4657 | 50)) | |
2a114cc1 BW |
4658 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4659 | } | |
d77e4531 PZ |
4660 | } |
4661 | ||
20bc8673 | 4662 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4663 | { |
4664 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4665 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4666 | |
6e3c9717 | 4667 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4668 | return; |
4669 | ||
4670 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4671 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4672 | mutex_lock(&dev_priv->rps.hw_lock); |
4673 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4674 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4675 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4676 | if (intel_wait_for_register(dev_priv, |
4677 | IPS_CTL, IPS_ENABLE, 0, | |
4678 | 42)) | |
23d0b130 | 4679 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4680 | } else { |
2a114cc1 | 4681 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4682 | POSTING_READ(IPS_CTL); |
4683 | } | |
d77e4531 PZ |
4684 | |
4685 | /* We need to wait for a vblank before we can disable the plane. */ | |
4686 | intel_wait_for_vblank(dev, crtc->pipe); | |
4687 | } | |
4688 | ||
7cac945f | 4689 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4690 | { |
7cac945f | 4691 | if (intel_crtc->overlay) { |
d3eedb1a | 4692 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4693 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4694 | |
4695 | mutex_lock(&dev->struct_mutex); | |
4696 | dev_priv->mm.interruptible = false; | |
4697 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4698 | dev_priv->mm.interruptible = true; | |
4699 | mutex_unlock(&dev->struct_mutex); | |
4700 | } | |
4701 | ||
4702 | /* Let userspace switch the overlay on again. In most cases userspace | |
4703 | * has to recompute where to put it anyway. | |
4704 | */ | |
4705 | } | |
4706 | ||
87d4300a ML |
4707 | /** |
4708 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4709 | * @crtc: the CRTC whose primary plane was just enabled | |
4710 | * | |
4711 | * Performs potentially sleeping operations that must be done after the primary | |
4712 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4713 | * called due to an explicit primary plane update, or due to an implicit | |
4714 | * re-enable that is caused when a sprite plane is updated to no longer | |
4715 | * completely hide the primary plane. | |
4716 | */ | |
4717 | static void | |
4718 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4719 | { |
4720 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4721 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4723 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4724 | |
87d4300a ML |
4725 | /* |
4726 | * FIXME IPS should be fine as long as one plane is | |
4727 | * enabled, but in practice it seems to have problems | |
4728 | * when going from primary only to sprite only and vice | |
4729 | * versa. | |
4730 | */ | |
a5c4d7bc VS |
4731 | hsw_enable_ips(intel_crtc); |
4732 | ||
f99d7069 | 4733 | /* |
87d4300a ML |
4734 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4735 | * So don't enable underrun reporting before at least some planes | |
4736 | * are enabled. | |
4737 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4738 | * but leave the pipe running. | |
f99d7069 | 4739 | */ |
87d4300a ML |
4740 | if (IS_GEN2(dev)) |
4741 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4742 | ||
aca7b684 VS |
4743 | /* Underruns don't always raise interrupts, so check manually. */ |
4744 | intel_check_cpu_fifo_underruns(dev_priv); | |
4745 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4746 | } |
4747 | ||
2622a081 | 4748 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4749 | static void |
4750 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4751 | { |
4752 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4753 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4754 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4755 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4756 | |
87d4300a ML |
4757 | /* |
4758 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4759 | * So diasble underrun reporting before all the planes get disabled. | |
4760 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4761 | * but leave the pipe running. | |
4762 | */ | |
4763 | if (IS_GEN2(dev)) | |
4764 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4765 | |
2622a081 VS |
4766 | /* |
4767 | * FIXME IPS should be fine as long as one plane is | |
4768 | * enabled, but in practice it seems to have problems | |
4769 | * when going from primary only to sprite only and vice | |
4770 | * versa. | |
4771 | */ | |
4772 | hsw_disable_ips(intel_crtc); | |
4773 | } | |
4774 | ||
4775 | /* FIXME get rid of this and use pre_plane_update */ | |
4776 | static void | |
4777 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4778 | { | |
4779 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4780 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4782 | int pipe = intel_crtc->pipe; | |
4783 | ||
4784 | intel_pre_disable_primary(crtc); | |
4785 | ||
87d4300a ML |
4786 | /* |
4787 | * Vblank time updates from the shadow to live plane control register | |
4788 | * are blocked if the memory self-refresh mode is active at that | |
4789 | * moment. So to make sure the plane gets truly disabled, disable | |
4790 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4791 | * will be checked/applied by the HW only at the next frame start | |
4792 | * event which is after the vblank start event, so we need to have a | |
4793 | * wait-for-vblank between disabling the plane and the pipe. | |
4794 | */ | |
262cd2e1 | 4795 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4796 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4797 | dev_priv->wm.vlv.cxsr = false; |
4798 | intel_wait_for_vblank(dev, pipe); | |
4799 | } | |
87d4300a ML |
4800 | } |
4801 | ||
5a21b665 DV |
4802 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4803 | { | |
4804 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4805 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4806 | struct intel_crtc_state *pipe_config = | |
4807 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4808 | struct drm_plane *primary = crtc->base.primary; |
4809 | struct drm_plane_state *old_pri_state = | |
4810 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4811 | ||
5748b6a1 | 4812 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
4813 | |
4814 | crtc->wm.cxsr_allowed = true; | |
4815 | ||
4816 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
4817 | intel_update_watermarks(&crtc->base); | |
4818 | ||
4819 | if (old_pri_state) { | |
4820 | struct intel_plane_state *primary_state = | |
4821 | to_intel_plane_state(primary->state); | |
4822 | struct intel_plane_state *old_primary_state = | |
4823 | to_intel_plane_state(old_pri_state); | |
4824 | ||
4825 | intel_fbc_post_update(crtc); | |
4826 | ||
4827 | if (primary_state->visible && | |
4828 | (needs_modeset(&pipe_config->base) || | |
4829 | !old_primary_state->visible)) | |
4830 | intel_post_enable_primary(&crtc->base); | |
4831 | } | |
4832 | } | |
4833 | ||
5c74cd73 | 4834 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4835 | { |
5c74cd73 | 4836 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4837 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4838 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
4839 | struct intel_crtc_state *pipe_config = |
4840 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4841 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4842 | struct drm_plane *primary = crtc->base.primary; | |
4843 | struct drm_plane_state *old_pri_state = | |
4844 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4845 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4846 | |
5c74cd73 ML |
4847 | if (old_pri_state) { |
4848 | struct intel_plane_state *primary_state = | |
4849 | to_intel_plane_state(primary->state); | |
4850 | struct intel_plane_state *old_primary_state = | |
4851 | to_intel_plane_state(old_pri_state); | |
4852 | ||
faf68d92 | 4853 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4854 | |
5c74cd73 ML |
4855 | if (old_primary_state->visible && |
4856 | (modeset || !primary_state->visible)) | |
4857 | intel_pre_disable_primary(&crtc->base); | |
4858 | } | |
852eb00d | 4859 | |
a4015f9a | 4860 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
852eb00d | 4861 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4862 | |
2622a081 VS |
4863 | /* |
4864 | * Vblank time updates from the shadow to live plane control register | |
4865 | * are blocked if the memory self-refresh mode is active at that | |
4866 | * moment. So to make sure the plane gets truly disabled, disable | |
4867 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4868 | * will be checked/applied by the HW only at the next frame start | |
4869 | * event which is after the vblank start event, so we need to have a | |
4870 | * wait-for-vblank between disabling the plane and the pipe. | |
4871 | */ | |
4872 | if (old_crtc_state->base.active) { | |
2dfd178d | 4873 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4874 | dev_priv->wm.vlv.cxsr = false; |
4875 | intel_wait_for_vblank(dev, crtc->pipe); | |
4876 | } | |
852eb00d | 4877 | } |
92826fcd | 4878 | |
ed4a6a7c MR |
4879 | /* |
4880 | * IVB workaround: must disable low power watermarks for at least | |
4881 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4882 | * when scaling is disabled. | |
4883 | * | |
4884 | * WaCxSRDisabledForSpriteScaling:ivb | |
4885 | */ | |
4886 | if (pipe_config->disable_lp_wm) { | |
4887 | ilk_disable_lp_wm(dev); | |
4888 | intel_wait_for_vblank(dev, crtc->pipe); | |
4889 | } | |
4890 | ||
4891 | /* | |
4892 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4893 | * watermark programming here. | |
4894 | */ | |
4895 | if (needs_modeset(&pipe_config->base)) | |
4896 | return; | |
4897 | ||
4898 | /* | |
4899 | * For platforms that support atomic watermarks, program the | |
4900 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4901 | * will be the intermediate values that are safe for both pre- and | |
4902 | * post- vblank; when vblank happens, the 'active' values will be set | |
4903 | * to the final 'target' values and we'll do this again to get the | |
4904 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4905 | * will be the final target values which will get automatically latched | |
4906 | * at vblank time; no further programming will be necessary. | |
4907 | * | |
4908 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4909 | * we'll continue to update watermarks the old way, if flags tell | |
4910 | * us to. | |
4911 | */ | |
4912 | if (dev_priv->display.initial_watermarks != NULL) | |
4913 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4914 | else if (pipe_config->update_wm_pre) |
92826fcd | 4915 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4916 | } |
4917 | ||
d032ffa0 | 4918 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4919 | { |
4920 | struct drm_device *dev = crtc->dev; | |
4921 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4922 | struct drm_plane *p; |
87d4300a ML |
4923 | int pipe = intel_crtc->pipe; |
4924 | ||
7cac945f | 4925 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4926 | |
d032ffa0 ML |
4927 | drm_for_each_plane_mask(p, dev, plane_mask) |
4928 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4929 | |
f99d7069 DV |
4930 | /* |
4931 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4932 | * to compute the mask of flip planes precisely. For the time being | |
4933 | * consider this a flip to a NULL plane. | |
4934 | */ | |
5748b6a1 | 4935 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
4936 | } |
4937 | ||
f67a559d JB |
4938 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4939 | { | |
4940 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4941 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d | 4942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4943 | struct intel_encoder *encoder; |
f67a559d | 4944 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4945 | struct intel_crtc_state *pipe_config = |
4946 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4947 | |
53d9f4e9 | 4948 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4949 | return; |
4950 | ||
b2c0593a VS |
4951 | /* |
4952 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4953 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4954 | * | |
4955 | * On ILK we get an occasional spurious CPU pipe underruns | |
4956 | * between eDP port A enable and vdd enable. Also PCH port | |
4957 | * enable seems to result in the occasional CPU pipe underrun. | |
4958 | * | |
4959 | * Spurious PCH underruns also occur during PCH enabling. | |
4960 | */ | |
4961 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4962 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4963 | if (intel_crtc->config->has_pch_encoder) |
4964 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4965 | ||
6e3c9717 | 4966 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4967 | intel_prepare_shared_dpll(intel_crtc); |
4968 | ||
37a5650b | 4969 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4970 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4971 | |
4972 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4973 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4974 | |
6e3c9717 | 4975 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4976 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4977 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4978 | } |
4979 | ||
4980 | ironlake_set_pipeconf(crtc); | |
4981 | ||
f67a559d | 4982 | intel_crtc->active = true; |
8664281b | 4983 | |
f6736a1a | 4984 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4985 | if (encoder->pre_enable) |
4986 | encoder->pre_enable(encoder); | |
f67a559d | 4987 | |
6e3c9717 | 4988 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4989 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4990 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4991 | * enabling. */ | |
88cefb6c | 4992 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4993 | } else { |
4994 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4995 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4996 | } | |
f67a559d | 4997 | |
b074cec8 | 4998 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4999 | |
9c54c0dd JB |
5000 | /* |
5001 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5002 | * clocks enabled | |
5003 | */ | |
b95c5321 | 5004 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5005 | |
1d5bf5d9 ID |
5006 | if (dev_priv->display.initial_watermarks != NULL) |
5007 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 5008 | intel_enable_pipe(intel_crtc); |
f67a559d | 5009 | |
6e3c9717 | 5010 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5011 | ironlake_pch_enable(crtc); |
c98e9dcf | 5012 | |
f9b61ff6 DV |
5013 | assert_vblank_disabled(crtc); |
5014 | drm_crtc_vblank_on(crtc); | |
5015 | ||
fa5c73b1 DV |
5016 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5017 | encoder->enable(encoder); | |
61b77ddd DV |
5018 | |
5019 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 5020 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5021 | |
5022 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5023 | if (intel_crtc->config->has_pch_encoder) | |
5024 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 5025 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5026 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5027 | } |
5028 | ||
42db64ef PZ |
5029 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5030 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5031 | { | |
f5adf94e | 5032 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5033 | } |
5034 | ||
4f771f10 PZ |
5035 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
5036 | { | |
5037 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5038 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 PZ |
5039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5040 | struct intel_encoder *encoder; | |
99d736a2 | 5041 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5042 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
5043 | struct intel_crtc_state *pipe_config = |
5044 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 5045 | |
53d9f4e9 | 5046 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5047 | return; |
5048 | ||
81b088ca VS |
5049 | if (intel_crtc->config->has_pch_encoder) |
5050 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5051 | false); | |
5052 | ||
95a7a2ae ID |
5053 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5054 | if (encoder->pre_pll_enable) | |
5055 | encoder->pre_pll_enable(encoder); | |
5056 | ||
8106ddbd | 5057 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5058 | intel_enable_shared_dpll(intel_crtc); |
5059 | ||
37a5650b | 5060 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5061 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5062 | |
d7edc4e5 | 5063 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5064 | intel_set_pipe_timings(intel_crtc); |
5065 | ||
bc58be60 | 5066 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5067 | |
4d1de975 JN |
5068 | if (cpu_transcoder != TRANSCODER_EDP && |
5069 | !transcoder_is_dsi(cpu_transcoder)) { | |
5070 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5071 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5072 | } |
5073 | ||
6e3c9717 | 5074 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5075 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5076 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5077 | } |
5078 | ||
d7edc4e5 | 5079 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5080 | haswell_set_pipeconf(crtc); |
5081 | ||
391bf048 | 5082 | haswell_set_pipemisc(crtc); |
229fca97 | 5083 | |
b95c5321 | 5084 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5085 | |
4f771f10 | 5086 | intel_crtc->active = true; |
8664281b | 5087 | |
6b698516 DV |
5088 | if (intel_crtc->config->has_pch_encoder) |
5089 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5090 | else | |
5091 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5092 | ||
7d4aefd0 | 5093 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5094 | if (encoder->pre_enable) |
5095 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5096 | } |
4f771f10 | 5097 | |
d2d65408 | 5098 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5099 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5100 | |
d7edc4e5 | 5101 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5102 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5103 | |
1c132b44 | 5104 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5105 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5106 | else |
1c132b44 | 5107 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5108 | |
5109 | /* | |
5110 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5111 | * clocks enabled | |
5112 | */ | |
b95c5321 | 5113 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5114 | |
1f544388 | 5115 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5116 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5117 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5118 | |
1d5bf5d9 ID |
5119 | if (dev_priv->display.initial_watermarks != NULL) |
5120 | dev_priv->display.initial_watermarks(pipe_config); | |
5121 | else | |
5122 | intel_update_watermarks(crtc); | |
4d1de975 JN |
5123 | |
5124 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5125 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5126 | intel_enable_pipe(intel_crtc); |
42db64ef | 5127 | |
6e3c9717 | 5128 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5129 | lpt_pch_enable(crtc); |
4f771f10 | 5130 | |
a65347ba | 5131 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5132 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5133 | ||
f9b61ff6 DV |
5134 | assert_vblank_disabled(crtc); |
5135 | drm_crtc_vblank_on(crtc); | |
5136 | ||
8807e55b | 5137 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5138 | encoder->enable(encoder); |
8807e55b JN |
5139 | intel_opregion_notify_encoder(encoder, true); |
5140 | } | |
4f771f10 | 5141 | |
6b698516 DV |
5142 | if (intel_crtc->config->has_pch_encoder) { |
5143 | intel_wait_for_vblank(dev, pipe); | |
5144 | intel_wait_for_vblank(dev, pipe); | |
5145 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5146 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5147 | true); | |
6b698516 | 5148 | } |
d2d65408 | 5149 | |
e4916946 PZ |
5150 | /* If we change the relative order between pipe/planes enabling, we need |
5151 | * to change the workaround. */ | |
99d736a2 ML |
5152 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5153 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5154 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5155 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5156 | } | |
4f771f10 PZ |
5157 | } |
5158 | ||
bfd16b2a | 5159 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5160 | { |
5161 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5162 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5163 | int pipe = crtc->pipe; |
5164 | ||
5165 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5166 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5167 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5168 | I915_WRITE(PF_CTL(pipe), 0); |
5169 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5170 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5171 | } | |
5172 | } | |
5173 | ||
6be4a607 JB |
5174 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5175 | { | |
5176 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5177 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 | 5178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5179 | struct intel_encoder *encoder; |
6be4a607 | 5180 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5181 | |
b2c0593a VS |
5182 | /* |
5183 | * Sometimes spurious CPU pipe underruns happen when the | |
5184 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5185 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5186 | */ | |
5187 | if (intel_crtc->config->has_pch_encoder) { | |
5188 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5189 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5190 | } |
37ca8d4c | 5191 | |
ea9d758d DV |
5192 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5193 | encoder->disable(encoder); | |
5194 | ||
f9b61ff6 DV |
5195 | drm_crtc_vblank_off(crtc); |
5196 | assert_vblank_disabled(crtc); | |
5197 | ||
575f7ab7 | 5198 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5199 | |
bfd16b2a | 5200 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5201 | |
b2c0593a | 5202 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5203 | ironlake_fdi_disable(crtc); |
5204 | ||
bf49ec8c DV |
5205 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5206 | if (encoder->post_disable) | |
5207 | encoder->post_disable(encoder); | |
2c07245f | 5208 | |
6e3c9717 | 5209 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5210 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5211 | |
d925c59a | 5212 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5213 | i915_reg_t reg; |
5214 | u32 temp; | |
5215 | ||
d925c59a DV |
5216 | /* disable TRANS_DP_CTL */ |
5217 | reg = TRANS_DP_CTL(pipe); | |
5218 | temp = I915_READ(reg); | |
5219 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5220 | TRANS_DP_PORT_SEL_MASK); | |
5221 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5222 | I915_WRITE(reg, temp); | |
5223 | ||
5224 | /* disable DPLL_SEL */ | |
5225 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5226 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5227 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5228 | } |
e3421a18 | 5229 | |
d925c59a DV |
5230 | ironlake_fdi_pll_disable(intel_crtc); |
5231 | } | |
81b088ca | 5232 | |
b2c0593a | 5233 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5234 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5235 | } |
1b3c7a47 | 5236 | |
4f771f10 | 5237 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5238 | { |
4f771f10 | 5239 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5240 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5242 | struct intel_encoder *encoder; |
6e3c9717 | 5243 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5244 | |
d2d65408 VS |
5245 | if (intel_crtc->config->has_pch_encoder) |
5246 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5247 | false); | |
5248 | ||
8807e55b JN |
5249 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5250 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5251 | encoder->disable(encoder); |
8807e55b | 5252 | } |
4f771f10 | 5253 | |
f9b61ff6 DV |
5254 | drm_crtc_vblank_off(crtc); |
5255 | assert_vblank_disabled(crtc); | |
5256 | ||
4d1de975 | 5257 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5258 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5259 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5260 | |
6e3c9717 | 5261 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5262 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5263 | ||
d7edc4e5 | 5264 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5265 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5266 | |
1c132b44 | 5267 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5268 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5269 | else |
bfd16b2a | 5270 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5271 | |
d7edc4e5 | 5272 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5273 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5274 | |
97b040aa ID |
5275 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5276 | if (encoder->post_disable) | |
5277 | encoder->post_disable(encoder); | |
81b088ca | 5278 | |
92966a37 VS |
5279 | if (intel_crtc->config->has_pch_encoder) { |
5280 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5281 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5282 | intel_ddi_fdi_disable(crtc); |
5283 | ||
81b088ca VS |
5284 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5285 | true); | |
92966a37 | 5286 | } |
4f771f10 PZ |
5287 | } |
5288 | ||
2dd24552 JB |
5289 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5290 | { | |
5291 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5292 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5293 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5294 | |
681a8504 | 5295 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5296 | return; |
5297 | ||
2dd24552 | 5298 | /* |
c0b03411 DV |
5299 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5300 | * according to register description and PRM. | |
2dd24552 | 5301 | */ |
c0b03411 DV |
5302 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5303 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5304 | |
b074cec8 JB |
5305 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5306 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5307 | |
5308 | /* Border color in case we don't scale up to the full screen. Black by | |
5309 | * default, change to something else for debugging. */ | |
5310 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5311 | } |
5312 | ||
d05410f9 DA |
5313 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5314 | { | |
5315 | switch (port) { | |
5316 | case PORT_A: | |
6331a704 | 5317 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5318 | case PORT_B: |
6331a704 | 5319 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5320 | case PORT_C: |
6331a704 | 5321 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5322 | case PORT_D: |
6331a704 | 5323 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5324 | case PORT_E: |
6331a704 | 5325 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5326 | default: |
b9fec167 | 5327 | MISSING_CASE(port); |
d05410f9 DA |
5328 | return POWER_DOMAIN_PORT_OTHER; |
5329 | } | |
5330 | } | |
5331 | ||
25f78f58 VS |
5332 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5333 | { | |
5334 | switch (port) { | |
5335 | case PORT_A: | |
5336 | return POWER_DOMAIN_AUX_A; | |
5337 | case PORT_B: | |
5338 | return POWER_DOMAIN_AUX_B; | |
5339 | case PORT_C: | |
5340 | return POWER_DOMAIN_AUX_C; | |
5341 | case PORT_D: | |
5342 | return POWER_DOMAIN_AUX_D; | |
5343 | case PORT_E: | |
5344 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5345 | return POWER_DOMAIN_AUX_D; | |
5346 | default: | |
b9fec167 | 5347 | MISSING_CASE(port); |
25f78f58 VS |
5348 | return POWER_DOMAIN_AUX_A; |
5349 | } | |
5350 | } | |
5351 | ||
319be8ae ID |
5352 | enum intel_display_power_domain |
5353 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5354 | { | |
5355 | struct drm_device *dev = intel_encoder->base.dev; | |
5356 | struct intel_digital_port *intel_dig_port; | |
5357 | ||
5358 | switch (intel_encoder->type) { | |
5359 | case INTEL_OUTPUT_UNKNOWN: | |
5360 | /* Only DDI platforms should ever use this output type */ | |
5361 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
cca0502b | 5362 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5363 | case INTEL_OUTPUT_HDMI: |
5364 | case INTEL_OUTPUT_EDP: | |
5365 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5366 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5367 | case INTEL_OUTPUT_DP_MST: |
5368 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5369 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5370 | case INTEL_OUTPUT_ANALOG: |
5371 | return POWER_DOMAIN_PORT_CRT; | |
5372 | case INTEL_OUTPUT_DSI: | |
5373 | return POWER_DOMAIN_PORT_DSI; | |
5374 | default: | |
5375 | return POWER_DOMAIN_PORT_OTHER; | |
5376 | } | |
5377 | } | |
5378 | ||
25f78f58 VS |
5379 | enum intel_display_power_domain |
5380 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5381 | { | |
5382 | struct drm_device *dev = intel_encoder->base.dev; | |
5383 | struct intel_digital_port *intel_dig_port; | |
5384 | ||
5385 | switch (intel_encoder->type) { | |
5386 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5387 | case INTEL_OUTPUT_HDMI: |
5388 | /* | |
5389 | * Only DDI platforms should ever use these output types. | |
5390 | * We can get here after the HDMI detect code has already set | |
5391 | * the type of the shared encoder. Since we can't be sure | |
5392 | * what's the status of the given connectors, play safe and | |
5393 | * run the DP detection too. | |
5394 | */ | |
25f78f58 | 5395 | WARN_ON_ONCE(!HAS_DDI(dev)); |
cca0502b | 5396 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5397 | case INTEL_OUTPUT_EDP: |
5398 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5399 | return port_to_aux_power_domain(intel_dig_port->port); | |
5400 | case INTEL_OUTPUT_DP_MST: | |
5401 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5402 | return port_to_aux_power_domain(intel_dig_port->port); | |
5403 | default: | |
b9fec167 | 5404 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5405 | return POWER_DOMAIN_AUX_A; |
5406 | } | |
5407 | } | |
5408 | ||
74bff5f9 ML |
5409 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5410 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5411 | { |
319be8ae | 5412 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5413 | struct drm_encoder *encoder; |
319be8ae ID |
5414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5415 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5416 | unsigned long mask; |
74bff5f9 | 5417 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5418 | |
74bff5f9 | 5419 | if (!crtc_state->base.active) |
292b990e ML |
5420 | return 0; |
5421 | ||
77d22dca ID |
5422 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5423 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5424 | if (crtc_state->pch_pfit.enabled || |
5425 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5426 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5427 | ||
74bff5f9 ML |
5428 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5429 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5430 | ||
319be8ae | 5431 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5432 | } |
319be8ae | 5433 | |
15e7ec29 ML |
5434 | if (crtc_state->shared_dpll) |
5435 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5436 | ||
77d22dca ID |
5437 | return mask; |
5438 | } | |
5439 | ||
74bff5f9 ML |
5440 | static unsigned long |
5441 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5442 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5443 | { |
fac5e23e | 5444 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5446 | enum intel_display_power_domain domain; | |
5a21b665 | 5447 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5448 | |
292b990e | 5449 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5450 | intel_crtc->enabled_power_domains = new_domains = |
5451 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5452 | |
5a21b665 | 5453 | domains = new_domains & ~old_domains; |
292b990e ML |
5454 | |
5455 | for_each_power_domain(domain, domains) | |
5456 | intel_display_power_get(dev_priv, domain); | |
5457 | ||
5a21b665 | 5458 | return old_domains & ~new_domains; |
292b990e ML |
5459 | } |
5460 | ||
5461 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5462 | unsigned long domains) | |
5463 | { | |
5464 | enum intel_display_power_domain domain; | |
5465 | ||
5466 | for_each_power_domain(domain, domains) | |
5467 | intel_display_power_put(dev_priv, domain); | |
5468 | } | |
77d22dca | 5469 | |
adafdc6f MK |
5470 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5471 | { | |
5472 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5473 | ||
5474 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5475 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5476 | return max_cdclk_freq; | |
5477 | else if (IS_CHERRYVIEW(dev_priv)) | |
5478 | return max_cdclk_freq*95/100; | |
5479 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5480 | return 2*max_cdclk_freq*90/100; | |
5481 | else | |
5482 | return max_cdclk_freq*90/100; | |
5483 | } | |
5484 | ||
b2045352 VS |
5485 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5486 | ||
560a7ae4 DL |
5487 | static void intel_update_max_cdclk(struct drm_device *dev) |
5488 | { | |
fac5e23e | 5489 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 | 5490 | |
ef11bdb3 | 5491 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5492 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5493 | int max_cdclk, vco; |
5494 | ||
5495 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5496 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5497 | |
b2045352 VS |
5498 | /* |
5499 | * Use the lower (vco 8640) cdclk values as a | |
5500 | * first guess. skl_calc_cdclk() will correct it | |
5501 | * if the preferred vco is 8100 instead. | |
5502 | */ | |
560a7ae4 | 5503 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5504 | max_cdclk = 617143; |
560a7ae4 | 5505 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5506 | max_cdclk = 540000; |
560a7ae4 | 5507 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5508 | max_cdclk = 432000; |
560a7ae4 | 5509 | else |
487ed2e4 | 5510 | max_cdclk = 308571; |
b2045352 VS |
5511 | |
5512 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5513 | } else if (IS_BROXTON(dev)) { |
5514 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5515 | } else if (IS_BROADWELL(dev)) { |
5516 | /* | |
5517 | * FIXME with extra cooling we can allow | |
5518 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5519 | * How can we know if extra cooling is | |
5520 | * available? PCI ID, VTB, something else? | |
5521 | */ | |
5522 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5523 | dev_priv->max_cdclk_freq = 450000; | |
5524 | else if (IS_BDW_ULX(dev)) | |
5525 | dev_priv->max_cdclk_freq = 450000; | |
5526 | else if (IS_BDW_ULT(dev)) | |
5527 | dev_priv->max_cdclk_freq = 540000; | |
5528 | else | |
5529 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5530 | } else if (IS_CHERRYVIEW(dev)) { |
5531 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5532 | } else if (IS_VALLEYVIEW(dev)) { |
5533 | dev_priv->max_cdclk_freq = 400000; | |
5534 | } else { | |
5535 | /* otherwise assume cdclk is fixed */ | |
5536 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5537 | } | |
5538 | ||
adafdc6f MK |
5539 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5540 | ||
560a7ae4 DL |
5541 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5542 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5543 | |
5544 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5545 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5546 | } |
5547 | ||
5548 | static void intel_update_cdclk(struct drm_device *dev) | |
5549 | { | |
fac5e23e | 5550 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 DL |
5551 | |
5552 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5553 | |
83d7c81f | 5554 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5555 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5556 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5557 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5558 | else |
5559 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5560 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5561 | |
5562 | /* | |
b5d99ff9 VS |
5563 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5564 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5565 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5566 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5567 | */ |
b5d99ff9 | 5568 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5569 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5570 | } |
5571 | ||
92891e45 VS |
5572 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5573 | static int skl_cdclk_decimal(int cdclk) | |
5574 | { | |
5575 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5576 | } | |
5577 | ||
5f199dfa VS |
5578 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5579 | { | |
5580 | int ratio; | |
5581 | ||
5582 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5583 | return 0; | |
5584 | ||
5585 | switch (cdclk) { | |
5586 | default: | |
5587 | MISSING_CASE(cdclk); | |
5588 | case 144000: | |
5589 | case 288000: | |
5590 | case 384000: | |
5591 | case 576000: | |
5592 | ratio = 60; | |
5593 | break; | |
5594 | case 624000: | |
5595 | ratio = 65; | |
5596 | break; | |
5597 | } | |
5598 | ||
5599 | return dev_priv->cdclk_pll.ref * ratio; | |
5600 | } | |
5601 | ||
2b73001e VS |
5602 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5603 | { | |
5604 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5605 | ||
5606 | /* Timeout 200us */ | |
95cac283 CW |
5607 | if (intel_wait_for_register(dev_priv, |
5608 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5609 | 1)) | |
2b73001e | 5610 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5611 | |
5612 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5613 | } |
5614 | ||
5f199dfa | 5615 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5616 | { |
5f199dfa | 5617 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5618 | u32 val; |
5619 | ||
5620 | val = I915_READ(BXT_DE_PLL_CTL); | |
5621 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5622 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5623 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5624 | ||
5625 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5626 | ||
5627 | /* Timeout 200us */ | |
e084e1b9 CW |
5628 | if (intel_wait_for_register(dev_priv, |
5629 | BXT_DE_PLL_ENABLE, | |
5630 | BXT_DE_PLL_LOCK, | |
5631 | BXT_DE_PLL_LOCK, | |
5632 | 1)) | |
2b73001e | 5633 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5634 | |
5f199dfa | 5635 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5636 | } |
5637 | ||
324513c0 | 5638 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5639 | { |
5f199dfa VS |
5640 | u32 val, divider; |
5641 | int vco, ret; | |
f8437dd1 | 5642 | |
5f199dfa VS |
5643 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5644 | ||
5645 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5646 | ||
5647 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5648 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5649 | case 8: | |
f8437dd1 | 5650 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5651 | break; |
5f199dfa | 5652 | case 4: |
f8437dd1 | 5653 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5654 | break; |
5f199dfa | 5655 | case 3: |
f8437dd1 | 5656 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5657 | break; |
5f199dfa | 5658 | case 2: |
f8437dd1 | 5659 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5660 | break; |
5661 | default: | |
5f199dfa VS |
5662 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5663 | WARN_ON(vco != 0); | |
f8437dd1 | 5664 | |
5f199dfa VS |
5665 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5666 | break; | |
f8437dd1 VK |
5667 | } |
5668 | ||
f8437dd1 | 5669 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5670 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5671 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5672 | 0x80000000); | |
5673 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5674 | ||
5675 | if (ret) { | |
5676 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5677 | ret, cdclk); |
f8437dd1 VK |
5678 | return; |
5679 | } | |
5680 | ||
5f199dfa VS |
5681 | if (dev_priv->cdclk_pll.vco != 0 && |
5682 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5683 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5684 | |
5f199dfa VS |
5685 | if (dev_priv->cdclk_pll.vco != vco) |
5686 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5687 | |
5f199dfa VS |
5688 | val = divider | skl_cdclk_decimal(cdclk); |
5689 | /* | |
5690 | * FIXME if only the cd2x divider needs changing, it could be done | |
5691 | * without shutting off the pipe (if only one pipe is active). | |
5692 | */ | |
5693 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5694 | /* | |
5695 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5696 | * enable otherwise. | |
5697 | */ | |
5698 | if (cdclk >= 500000) | |
5699 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5700 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5701 | |
5702 | mutex_lock(&dev_priv->rps.hw_lock); | |
5703 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5704 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5705 | mutex_unlock(&dev_priv->rps.hw_lock); |
5706 | ||
5707 | if (ret) { | |
5708 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5709 | ret, cdclk); |
f8437dd1 VK |
5710 | return; |
5711 | } | |
5712 | ||
91c8a326 | 5713 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 VK |
5714 | } |
5715 | ||
d66a2194 | 5716 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5717 | { |
d66a2194 ID |
5718 | u32 cdctl, expected; |
5719 | ||
91c8a326 | 5720 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 | 5721 | |
d66a2194 ID |
5722 | if (dev_priv->cdclk_pll.vco == 0 || |
5723 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
5724 | goto sanitize; | |
5725 | ||
5726 | /* DPLL okay; verify the cdclock | |
5727 | * | |
5728 | * Some BIOS versions leave an incorrect decimal frequency value and | |
5729 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
5730 | * so sanitize this register. | |
5731 | */ | |
5732 | cdctl = I915_READ(CDCLK_CTL); | |
5733 | /* | |
5734 | * Let's ignore the pipe field, since BIOS could have configured the | |
5735 | * dividers both synching to an active pipe, or asynchronously | |
5736 | * (PIPE_NONE). | |
5737 | */ | |
5738 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
5739 | ||
5740 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
5741 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5742 | /* | |
5743 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5744 | * enable otherwise. | |
5745 | */ | |
5746 | if (dev_priv->cdclk_freq >= 500000) | |
5747 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5748 | ||
5749 | if (cdctl == expected) | |
5750 | /* All well; nothing to sanitize */ | |
5751 | return; | |
5752 | ||
5753 | sanitize: | |
5754 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
5755 | ||
5756 | /* force cdclk programming */ | |
5757 | dev_priv->cdclk_freq = 0; | |
5758 | ||
5759 | /* force full PLL disable + enable */ | |
5760 | dev_priv->cdclk_pll.vco = -1; | |
5761 | } | |
5762 | ||
324513c0 | 5763 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
5764 | { |
5765 | bxt_sanitize_cdclk(dev_priv); | |
5766 | ||
5767 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 5768 | return; |
c2e001ef | 5769 | |
f8437dd1 VK |
5770 | /* |
5771 | * FIXME: | |
5772 | * - The initial CDCLK needs to be read from VBT. | |
5773 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5774 | */ |
324513c0 | 5775 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
5776 | } |
5777 | ||
324513c0 | 5778 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5779 | { |
324513c0 | 5780 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
5781 | } |
5782 | ||
a8ca4934 VS |
5783 | static int skl_calc_cdclk(int max_pixclk, int vco) |
5784 | { | |
63911d72 | 5785 | if (vco == 8640000) { |
a8ca4934 | 5786 | if (max_pixclk > 540000) |
487ed2e4 | 5787 | return 617143; |
a8ca4934 VS |
5788 | else if (max_pixclk > 432000) |
5789 | return 540000; | |
487ed2e4 | 5790 | else if (max_pixclk > 308571) |
a8ca4934 VS |
5791 | return 432000; |
5792 | else | |
487ed2e4 | 5793 | return 308571; |
a8ca4934 | 5794 | } else { |
a8ca4934 VS |
5795 | if (max_pixclk > 540000) |
5796 | return 675000; | |
5797 | else if (max_pixclk > 450000) | |
5798 | return 540000; | |
5799 | else if (max_pixclk > 337500) | |
5800 | return 450000; | |
5801 | else | |
5802 | return 337500; | |
5803 | } | |
5804 | } | |
5805 | ||
ea61791e VS |
5806 | static void |
5807 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 5808 | { |
ea61791e | 5809 | u32 val; |
5d96d8af | 5810 | |
709e05c3 | 5811 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 5812 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 5813 | |
ea61791e | 5814 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 5815 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 5816 | return; |
5d96d8af | 5817 | |
1c3f7700 ID |
5818 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
5819 | return; | |
9f7eb31a | 5820 | |
ea61791e VS |
5821 | val = I915_READ(DPLL_CTRL1); |
5822 | ||
1c3f7700 ID |
5823 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
5824 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5825 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5826 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
5827 | return; | |
9f7eb31a | 5828 | |
ea61791e VS |
5829 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
5830 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
5831 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
5832 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
5833 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 5834 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
5835 | break; |
5836 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
5837 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 5838 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
5839 | break; |
5840 | default: | |
5841 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
5842 | break; |
5843 | } | |
5d96d8af DL |
5844 | } |
5845 | ||
b2045352 VS |
5846 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
5847 | { | |
5848 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
5849 | ||
5850 | dev_priv->skl_preferred_vco_freq = vco; | |
5851 | ||
5852 | if (changed) | |
91c8a326 | 5853 | intel_update_max_cdclk(&dev_priv->drm); |
b2045352 VS |
5854 | } |
5855 | ||
5d96d8af | 5856 | static void |
3861fc60 | 5857 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5858 | { |
a8ca4934 | 5859 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
5860 | u32 val; |
5861 | ||
63911d72 | 5862 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 5863 | |
5d96d8af | 5864 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 5865 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5866 | I915_WRITE(CDCLK_CTL, val); |
5867 | POSTING_READ(CDCLK_CTL); | |
5868 | ||
5869 | /* | |
5870 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5871 | * taking into account the VCO required to operate the eDP panel at the | |
5872 | * desired frequency. The usual DP link rates operate with a VCO of | |
5873 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5874 | * The modeset code is responsible for the selection of the exact link | |
5875 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 5876 | * works with vco. |
5d96d8af DL |
5877 | */ |
5878 | val = I915_READ(DPLL_CTRL1); | |
5879 | ||
5880 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5881 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5882 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 5883 | if (vco == 8640000) |
5d96d8af DL |
5884 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5885 | SKL_DPLL0); | |
5886 | else | |
5887 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5888 | SKL_DPLL0); | |
5889 | ||
5890 | I915_WRITE(DPLL_CTRL1, val); | |
5891 | POSTING_READ(DPLL_CTRL1); | |
5892 | ||
5893 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5894 | ||
e24ca054 CW |
5895 | if (intel_wait_for_register(dev_priv, |
5896 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
5897 | 5)) | |
5d96d8af | 5898 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 5899 | |
63911d72 | 5900 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
5901 | |
5902 | /* We'll want to keep using the current vco from now on. */ | |
5903 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
5904 | } |
5905 | ||
430e05de VS |
5906 | static void |
5907 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5908 | { | |
5909 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
5910 | if (intel_wait_for_register(dev_priv, |
5911 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
5912 | 1)) | |
430e05de | 5913 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 5914 | |
63911d72 | 5915 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
5916 | } |
5917 | ||
5d96d8af DL |
5918 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5919 | { | |
5920 | int ret; | |
5921 | u32 val; | |
5922 | ||
5923 | /* inform PCU we want to change CDCLK */ | |
5924 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5925 | mutex_lock(&dev_priv->rps.hw_lock); | |
5926 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5927 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5928 | ||
5929 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5930 | } | |
5931 | ||
5932 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5933 | { | |
848496e5 | 5934 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
5935 | } |
5936 | ||
1cd593e0 | 5937 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 5938 | { |
91c8a326 | 5939 | struct drm_device *dev = &dev_priv->drm; |
5d96d8af DL |
5940 | u32 freq_select, pcu_ack; |
5941 | ||
1cd593e0 VS |
5942 | WARN_ON((cdclk == 24000) != (vco == 0)); |
5943 | ||
63911d72 | 5944 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
5945 | |
5946 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5947 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5948 | return; | |
5949 | } | |
5950 | ||
5951 | /* set CDCLK_CTL */ | |
9ef56154 | 5952 | switch (cdclk) { |
5d96d8af DL |
5953 | case 450000: |
5954 | case 432000: | |
5955 | freq_select = CDCLK_FREQ_450_432; | |
5956 | pcu_ack = 1; | |
5957 | break; | |
5958 | case 540000: | |
5959 | freq_select = CDCLK_FREQ_540; | |
5960 | pcu_ack = 2; | |
5961 | break; | |
487ed2e4 | 5962 | case 308571: |
5d96d8af DL |
5963 | case 337500: |
5964 | default: | |
5965 | freq_select = CDCLK_FREQ_337_308; | |
5966 | pcu_ack = 0; | |
5967 | break; | |
487ed2e4 | 5968 | case 617143: |
5d96d8af DL |
5969 | case 675000: |
5970 | freq_select = CDCLK_FREQ_675_617; | |
5971 | pcu_ack = 3; | |
5972 | break; | |
5973 | } | |
5974 | ||
63911d72 VS |
5975 | if (dev_priv->cdclk_pll.vco != 0 && |
5976 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
5977 | skl_dpll0_disable(dev_priv); |
5978 | ||
63911d72 | 5979 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
5980 | skl_dpll0_enable(dev_priv, vco); |
5981 | ||
9ef56154 | 5982 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5983 | POSTING_READ(CDCLK_CTL); |
5984 | ||
5985 | /* inform PCU of the change */ | |
5986 | mutex_lock(&dev_priv->rps.hw_lock); | |
5987 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5988 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5989 | |
5990 | intel_update_cdclk(dev); | |
5d96d8af DL |
5991 | } |
5992 | ||
9f7eb31a VS |
5993 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5994 | ||
5d96d8af DL |
5995 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
5996 | { | |
709e05c3 | 5997 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
5998 | } |
5999 | ||
6000 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
6001 | { | |
9f7eb31a VS |
6002 | int cdclk, vco; |
6003 | ||
6004 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 6005 | |
63911d72 | 6006 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
6007 | /* |
6008 | * Use the current vco as our initial | |
6009 | * guess as to what the preferred vco is. | |
6010 | */ | |
6011 | if (dev_priv->skl_preferred_vco_freq == 0) | |
6012 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 6013 | dev_priv->cdclk_pll.vco); |
70c2c184 | 6014 | return; |
1cd593e0 | 6015 | } |
5d96d8af | 6016 | |
70c2c184 VS |
6017 | vco = dev_priv->skl_preferred_vco_freq; |
6018 | if (vco == 0) | |
63911d72 | 6019 | vco = 8100000; |
70c2c184 | 6020 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6021 | |
70c2c184 | 6022 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6023 | } |
6024 | ||
9f7eb31a | 6025 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6026 | { |
09492498 | 6027 | uint32_t cdctl, expected; |
c73666f3 | 6028 | |
f1b391a5 SK |
6029 | /* |
6030 | * check if the pre-os intialized the display | |
6031 | * There is SWF18 scratchpad register defined which is set by the | |
6032 | * pre-os which can be used by the OS drivers to check the status | |
6033 | */ | |
6034 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6035 | goto sanitize; | |
6036 | ||
91c8a326 | 6037 | intel_update_cdclk(&dev_priv->drm); |
c73666f3 | 6038 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6039 | if (dev_priv->cdclk_pll.vco == 0 || |
6040 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6041 | goto sanitize; |
6042 | ||
6043 | /* DPLL okay; verify the cdclock | |
6044 | * | |
6045 | * Noticed in some instances that the freq selection is correct but | |
6046 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6047 | * enable display. Verify the same as well. | |
6048 | */ | |
09492498 VS |
6049 | cdctl = I915_READ(CDCLK_CTL); |
6050 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6051 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6052 | if (cdctl == expected) | |
c73666f3 | 6053 | /* All well; nothing to sanitize */ |
9f7eb31a | 6054 | return; |
c89e39f3 | 6055 | |
9f7eb31a VS |
6056 | sanitize: |
6057 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6058 | |
9f7eb31a VS |
6059 | /* force cdclk programming */ |
6060 | dev_priv->cdclk_freq = 0; | |
6061 | /* force full PLL disable + enable */ | |
63911d72 | 6062 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6063 | } |
6064 | ||
30a970c6 JB |
6065 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6066 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6067 | { | |
fac5e23e | 6068 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6069 | u32 val, cmd; |
6070 | ||
164dfd28 VK |
6071 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6072 | != dev_priv->cdclk_freq); | |
d60c4473 | 6073 | |
dfcab17e | 6074 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6075 | cmd = 2; |
dfcab17e | 6076 | else if (cdclk == 266667) |
30a970c6 JB |
6077 | cmd = 1; |
6078 | else | |
6079 | cmd = 0; | |
6080 | ||
6081 | mutex_lock(&dev_priv->rps.hw_lock); | |
6082 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6083 | val &= ~DSPFREQGUAR_MASK; | |
6084 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6085 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6086 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6087 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6088 | 50)) { | |
6089 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6090 | } | |
6091 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6092 | ||
54433e91 VS |
6093 | mutex_lock(&dev_priv->sb_lock); |
6094 | ||
dfcab17e | 6095 | if (cdclk == 400000) { |
6bcda4f0 | 6096 | u32 divider; |
30a970c6 | 6097 | |
6bcda4f0 | 6098 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6099 | |
30a970c6 JB |
6100 | /* adjust cdclk divider */ |
6101 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6102 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6103 | val |= divider; |
6104 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6105 | |
6106 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6107 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6108 | 50)) |
6109 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6110 | } |
6111 | ||
30a970c6 JB |
6112 | /* adjust self-refresh exit latency value */ |
6113 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6114 | val &= ~0x7f; | |
6115 | ||
6116 | /* | |
6117 | * For high bandwidth configs, we set a higher latency in the bunit | |
6118 | * so that the core display fetch happens in time to avoid underruns. | |
6119 | */ | |
dfcab17e | 6120 | if (cdclk == 400000) |
30a970c6 JB |
6121 | val |= 4500 / 250; /* 4.5 usec */ |
6122 | else | |
6123 | val |= 3000 / 250; /* 3.0 usec */ | |
6124 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6125 | |
a580516d | 6126 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6127 | |
b6283055 | 6128 | intel_update_cdclk(dev); |
30a970c6 JB |
6129 | } |
6130 | ||
383c5a6a VS |
6131 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6132 | { | |
fac5e23e | 6133 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6134 | u32 val, cmd; |
6135 | ||
164dfd28 VK |
6136 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6137 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
6138 | |
6139 | switch (cdclk) { | |
383c5a6a VS |
6140 | case 333333: |
6141 | case 320000: | |
383c5a6a | 6142 | case 266667: |
383c5a6a | 6143 | case 200000: |
383c5a6a VS |
6144 | break; |
6145 | default: | |
5f77eeb0 | 6146 | MISSING_CASE(cdclk); |
383c5a6a VS |
6147 | return; |
6148 | } | |
6149 | ||
9d0d3fda VS |
6150 | /* |
6151 | * Specs are full of misinformation, but testing on actual | |
6152 | * hardware has shown that we just need to write the desired | |
6153 | * CCK divider into the Punit register. | |
6154 | */ | |
6155 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6156 | ||
383c5a6a VS |
6157 | mutex_lock(&dev_priv->rps.hw_lock); |
6158 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6159 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6160 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6161 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6162 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6163 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6164 | 50)) { | |
6165 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6166 | } | |
6167 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6168 | ||
b6283055 | 6169 | intel_update_cdclk(dev); |
383c5a6a VS |
6170 | } |
6171 | ||
30a970c6 JB |
6172 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6173 | int max_pixclk) | |
6174 | { | |
6bcda4f0 | 6175 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6176 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6177 | |
30a970c6 JB |
6178 | /* |
6179 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6180 | * 200MHz | |
6181 | * 267MHz | |
29dc7ef3 | 6182 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6183 | * 400MHz (VLV only) |
6184 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6185 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6186 | * |
6187 | * We seem to get an unstable or solid color picture at 200MHz. | |
6188 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6189 | * are off. | |
30a970c6 | 6190 | */ |
6cca3195 VS |
6191 | if (!IS_CHERRYVIEW(dev_priv) && |
6192 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6193 | return 400000; |
6cca3195 | 6194 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6195 | return freq_320; |
e37c67a1 | 6196 | else if (max_pixclk > 0) |
dfcab17e | 6197 | return 266667; |
e37c67a1 VS |
6198 | else |
6199 | return 200000; | |
30a970c6 JB |
6200 | } |
6201 | ||
324513c0 | 6202 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6203 | { |
760e1477 | 6204 | if (max_pixclk > 576000) |
f8437dd1 | 6205 | return 624000; |
760e1477 | 6206 | else if (max_pixclk > 384000) |
f8437dd1 | 6207 | return 576000; |
760e1477 | 6208 | else if (max_pixclk > 288000) |
f8437dd1 | 6209 | return 384000; |
760e1477 | 6210 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6211 | return 288000; |
6212 | else | |
6213 | return 144000; | |
6214 | } | |
6215 | ||
e8788cbc | 6216 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6217 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6218 | struct drm_atomic_state *state) | |
30a970c6 | 6219 | { |
565602d7 | 6220 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6221 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6222 | struct drm_crtc *crtc; |
6223 | struct drm_crtc_state *crtc_state; | |
6224 | unsigned max_pixclk = 0, i; | |
6225 | enum pipe pipe; | |
30a970c6 | 6226 | |
565602d7 ML |
6227 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6228 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6229 | |
565602d7 ML |
6230 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6231 | int pixclk = 0; | |
6232 | ||
6233 | if (crtc_state->enable) | |
6234 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6235 | |
565602d7 | 6236 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6237 | } |
6238 | ||
565602d7 ML |
6239 | for_each_pipe(dev_priv, pipe) |
6240 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6241 | ||
30a970c6 JB |
6242 | return max_pixclk; |
6243 | } | |
6244 | ||
27c329ed | 6245 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6246 | { |
27c329ed | 6247 | struct drm_device *dev = state->dev; |
fac5e23e | 6248 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6249 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6250 | struct intel_atomic_state *intel_state = |
6251 | to_intel_atomic_state(state); | |
30a970c6 | 6252 | |
1a617b77 | 6253 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6254 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6255 | |
1a617b77 ML |
6256 | if (!intel_state->active_crtcs) |
6257 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6258 | ||
27c329ed ML |
6259 | return 0; |
6260 | } | |
304603f4 | 6261 | |
324513c0 | 6262 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6263 | { |
4e5ca60f | 6264 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6265 | struct intel_atomic_state *intel_state = |
6266 | to_intel_atomic_state(state); | |
85a96e7a | 6267 | |
1a617b77 | 6268 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6269 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6270 | |
1a617b77 | 6271 | if (!intel_state->active_crtcs) |
324513c0 | 6272 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6273 | |
27c329ed | 6274 | return 0; |
30a970c6 JB |
6275 | } |
6276 | ||
1e69cd74 VS |
6277 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6278 | { | |
6279 | unsigned int credits, default_credits; | |
6280 | ||
6281 | if (IS_CHERRYVIEW(dev_priv)) | |
6282 | default_credits = PFI_CREDIT(12); | |
6283 | else | |
6284 | default_credits = PFI_CREDIT(8); | |
6285 | ||
bfa7df01 | 6286 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6287 | /* CHV suggested value is 31 or 63 */ |
6288 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6289 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6290 | else |
6291 | credits = PFI_CREDIT(15); | |
6292 | } else { | |
6293 | credits = default_credits; | |
6294 | } | |
6295 | ||
6296 | /* | |
6297 | * WA - write default credits before re-programming | |
6298 | * FIXME: should we also set the resend bit here? | |
6299 | */ | |
6300 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6301 | default_credits); | |
6302 | ||
6303 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6304 | credits | PFI_CREDIT_RESEND); | |
6305 | ||
6306 | /* | |
6307 | * FIXME is this guaranteed to clear | |
6308 | * immediately or should we poll for it? | |
6309 | */ | |
6310 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6311 | } | |
6312 | ||
27c329ed | 6313 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6314 | { |
a821fc46 | 6315 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6316 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6317 | struct intel_atomic_state *old_intel_state = |
6318 | to_intel_atomic_state(old_state); | |
6319 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6320 | |
27c329ed ML |
6321 | /* |
6322 | * FIXME: We can end up here with all power domains off, yet | |
6323 | * with a CDCLK frequency other than the minimum. To account | |
6324 | * for this take the PIPE-A power domain, which covers the HW | |
6325 | * blocks needed for the following programming. This can be | |
6326 | * removed once it's guaranteed that we get here either with | |
6327 | * the minimum CDCLK set, or the required power domains | |
6328 | * enabled. | |
6329 | */ | |
6330 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6331 | |
27c329ed ML |
6332 | if (IS_CHERRYVIEW(dev)) |
6333 | cherryview_set_cdclk(dev, req_cdclk); | |
6334 | else | |
6335 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6336 | |
27c329ed | 6337 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6338 | |
27c329ed | 6339 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6340 | } |
6341 | ||
89b667f8 JB |
6342 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6343 | { | |
6344 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6345 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6347 | struct intel_encoder *encoder; | |
b95c5321 ML |
6348 | struct intel_crtc_state *pipe_config = |
6349 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6350 | int pipe = intel_crtc->pipe; |
89b667f8 | 6351 | |
53d9f4e9 | 6352 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6353 | return; |
6354 | ||
37a5650b | 6355 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6356 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6357 | |
6358 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6359 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6360 | |
c14b0485 | 6361 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
fac5e23e | 6362 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6363 | |
6364 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6365 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6366 | } | |
6367 | ||
5b18e57c DV |
6368 | i9xx_set_pipeconf(intel_crtc); |
6369 | ||
89b667f8 | 6370 | intel_crtc->active = true; |
89b667f8 | 6371 | |
a72e4c9f | 6372 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6373 | |
89b667f8 JB |
6374 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6375 | if (encoder->pre_pll_enable) | |
6376 | encoder->pre_pll_enable(encoder); | |
6377 | ||
cd2d34d9 VS |
6378 | if (IS_CHERRYVIEW(dev)) { |
6379 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6380 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6381 | } else { | |
6382 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6383 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6384 | } |
89b667f8 JB |
6385 | |
6386 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6387 | if (encoder->pre_enable) | |
6388 | encoder->pre_enable(encoder); | |
6389 | ||
2dd24552 JB |
6390 | i9xx_pfit_enable(intel_crtc); |
6391 | ||
b95c5321 | 6392 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6393 | |
caed361d | 6394 | intel_update_watermarks(crtc); |
e1fdc473 | 6395 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6396 | |
4b3a9526 VS |
6397 | assert_vblank_disabled(crtc); |
6398 | drm_crtc_vblank_on(crtc); | |
6399 | ||
f9b61ff6 DV |
6400 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6401 | encoder->enable(encoder); | |
89b667f8 JB |
6402 | } |
6403 | ||
f13c2ef3 DV |
6404 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6405 | { | |
6406 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6407 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6408 | |
6e3c9717 ACO |
6409 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6410 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6411 | } |
6412 | ||
0b8765c6 | 6413 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6414 | { |
6415 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6416 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6417 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6418 | struct intel_encoder *encoder; |
b95c5321 ML |
6419 | struct intel_crtc_state *pipe_config = |
6420 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6421 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6422 | |
53d9f4e9 | 6423 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6424 | return; |
6425 | ||
f13c2ef3 DV |
6426 | i9xx_set_pll_dividers(intel_crtc); |
6427 | ||
37a5650b | 6428 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6429 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6430 | |
6431 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6432 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6433 | |
5b18e57c DV |
6434 | i9xx_set_pipeconf(intel_crtc); |
6435 | ||
f7abfe8b | 6436 | intel_crtc->active = true; |
6b383a7f | 6437 | |
4a3436e8 | 6438 | if (!IS_GEN2(dev)) |
a72e4c9f | 6439 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6440 | |
9d6d9f19 MK |
6441 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6442 | if (encoder->pre_enable) | |
6443 | encoder->pre_enable(encoder); | |
6444 | ||
f6736a1a DV |
6445 | i9xx_enable_pll(intel_crtc); |
6446 | ||
2dd24552 JB |
6447 | i9xx_pfit_enable(intel_crtc); |
6448 | ||
b95c5321 | 6449 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6450 | |
f37fcc2a | 6451 | intel_update_watermarks(crtc); |
e1fdc473 | 6452 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6453 | |
4b3a9526 VS |
6454 | assert_vblank_disabled(crtc); |
6455 | drm_crtc_vblank_on(crtc); | |
6456 | ||
f9b61ff6 DV |
6457 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6458 | encoder->enable(encoder); | |
0b8765c6 | 6459 | } |
79e53945 | 6460 | |
87476d63 DV |
6461 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6462 | { | |
6463 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6464 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6465 | |
6e3c9717 | 6466 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6467 | return; |
87476d63 | 6468 | |
328d8e82 | 6469 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6470 | |
328d8e82 DV |
6471 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6472 | I915_READ(PFIT_CONTROL)); | |
6473 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6474 | } |
6475 | ||
0b8765c6 JB |
6476 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6477 | { | |
6478 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 6479 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 | 6480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6481 | struct intel_encoder *encoder; |
0b8765c6 | 6482 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6483 | |
6304cd91 VS |
6484 | /* |
6485 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6486 | * wait for planes to fully turn off before disabling the pipe. | |
6487 | */ | |
90e83e53 ACO |
6488 | if (IS_GEN2(dev)) |
6489 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6490 | |
4b3a9526 VS |
6491 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6492 | encoder->disable(encoder); | |
6493 | ||
f9b61ff6 DV |
6494 | drm_crtc_vblank_off(crtc); |
6495 | assert_vblank_disabled(crtc); | |
6496 | ||
575f7ab7 | 6497 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6498 | |
87476d63 | 6499 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6500 | |
89b667f8 JB |
6501 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6502 | if (encoder->post_disable) | |
6503 | encoder->post_disable(encoder); | |
6504 | ||
d7edc4e5 | 6505 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6506 | if (IS_CHERRYVIEW(dev)) |
6507 | chv_disable_pll(dev_priv, pipe); | |
6508 | else if (IS_VALLEYVIEW(dev)) | |
6509 | vlv_disable_pll(dev_priv, pipe); | |
6510 | else | |
1c4e0274 | 6511 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6512 | } |
0b8765c6 | 6513 | |
d6db995f VS |
6514 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6515 | if (encoder->post_pll_disable) | |
6516 | encoder->post_pll_disable(encoder); | |
6517 | ||
4a3436e8 | 6518 | if (!IS_GEN2(dev)) |
a72e4c9f | 6519 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6520 | } |
6521 | ||
b17d48e2 ML |
6522 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6523 | { | |
842e0307 | 6524 | struct intel_encoder *encoder; |
b17d48e2 ML |
6525 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6526 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6527 | enum intel_display_power_domain domain; | |
6528 | unsigned long domains; | |
6529 | ||
6530 | if (!intel_crtc->active) | |
6531 | return; | |
6532 | ||
a539205a | 6533 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
5a21b665 | 6534 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6535 | |
2622a081 | 6536 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6537 | |
6538 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6539 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6540 | } |
6541 | ||
b17d48e2 | 6542 | dev_priv->display.crtc_disable(crtc); |
842e0307 | 6543 | |
78108b7c VS |
6544 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6545 | crtc->base.id, crtc->name); | |
842e0307 ML |
6546 | |
6547 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6548 | crtc->state->active = false; | |
37d9078b | 6549 | intel_crtc->active = false; |
842e0307 ML |
6550 | crtc->enabled = false; |
6551 | crtc->state->connector_mask = 0; | |
6552 | crtc->state->encoder_mask = 0; | |
6553 | ||
6554 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6555 | encoder->base.crtc = NULL; | |
6556 | ||
58f9c0bc | 6557 | intel_fbc_disable(intel_crtc); |
37d9078b | 6558 | intel_update_watermarks(crtc); |
1f7457b1 | 6559 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6560 | |
6561 | domains = intel_crtc->enabled_power_domains; | |
6562 | for_each_power_domain(domain, domains) | |
6563 | intel_display_power_put(dev_priv, domain); | |
6564 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6565 | |
6566 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6567 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6568 | } |
6569 | ||
6b72d486 ML |
6570 | /* |
6571 | * turn all crtc's off, but do not adjust state | |
6572 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6573 | */ | |
70e0bd74 | 6574 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6575 | { |
e2c8b870 | 6576 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6577 | struct drm_atomic_state *state; |
e2c8b870 | 6578 | int ret; |
70e0bd74 | 6579 | |
e2c8b870 ML |
6580 | state = drm_atomic_helper_suspend(dev); |
6581 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6582 | if (ret) |
6583 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6584 | else |
6585 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6586 | return ret; |
ee7b9f93 JB |
6587 | } |
6588 | ||
ea5b213a | 6589 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6590 | { |
4ef69c7a | 6591 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6592 | |
ea5b213a CW |
6593 | drm_encoder_cleanup(encoder); |
6594 | kfree(intel_encoder); | |
7e7d76c3 JB |
6595 | } |
6596 | ||
0a91ca29 DV |
6597 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6598 | * internal consistency). */ | |
5a21b665 | 6599 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6600 | { |
5a21b665 | 6601 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6602 | |
6603 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6604 | connector->base.base.id, | |
6605 | connector->base.name); | |
6606 | ||
0a91ca29 | 6607 | if (connector->get_hw_state(connector)) { |
e85376cb | 6608 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6609 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6610 | |
35dd3c64 ML |
6611 | I915_STATE_WARN(!crtc, |
6612 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6613 | |
35dd3c64 ML |
6614 | if (!crtc) |
6615 | return; | |
6616 | ||
6617 | I915_STATE_WARN(!crtc->state->active, | |
6618 | "connector is active, but attached crtc isn't\n"); | |
6619 | ||
e85376cb | 6620 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6621 | return; |
6622 | ||
e85376cb | 6623 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6624 | "atomic encoder doesn't match attached encoder\n"); |
6625 | ||
e85376cb | 6626 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6627 | "attached encoder crtc differs from connector crtc\n"); |
6628 | } else { | |
4d688a2a ML |
6629 | I915_STATE_WARN(crtc && crtc->state->active, |
6630 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6631 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6632 | "best encoder set without crtc!\n"); |
0a91ca29 | 6633 | } |
79e53945 JB |
6634 | } |
6635 | ||
08d9bc92 ACO |
6636 | int intel_connector_init(struct intel_connector *connector) |
6637 | { | |
5350a031 | 6638 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6639 | |
5350a031 | 6640 | if (!connector->base.state) |
08d9bc92 ACO |
6641 | return -ENOMEM; |
6642 | ||
08d9bc92 ACO |
6643 | return 0; |
6644 | } | |
6645 | ||
6646 | struct intel_connector *intel_connector_alloc(void) | |
6647 | { | |
6648 | struct intel_connector *connector; | |
6649 | ||
6650 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6651 | if (!connector) | |
6652 | return NULL; | |
6653 | ||
6654 | if (intel_connector_init(connector) < 0) { | |
6655 | kfree(connector); | |
6656 | return NULL; | |
6657 | } | |
6658 | ||
6659 | return connector; | |
6660 | } | |
6661 | ||
f0947c37 DV |
6662 | /* Simple connector->get_hw_state implementation for encoders that support only |
6663 | * one connector and no cloning and hence the encoder state determines the state | |
6664 | * of the connector. */ | |
6665 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6666 | { |
24929352 | 6667 | enum pipe pipe = 0; |
f0947c37 | 6668 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6669 | |
f0947c37 | 6670 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6671 | } |
6672 | ||
6d293983 | 6673 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6674 | { |
6d293983 ACO |
6675 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6676 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6677 | |
6678 | return 0; | |
6679 | } | |
6680 | ||
6d293983 | 6681 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6682 | struct intel_crtc_state *pipe_config) |
1857e1da | 6683 | { |
6d293983 ACO |
6684 | struct drm_atomic_state *state = pipe_config->base.state; |
6685 | struct intel_crtc *other_crtc; | |
6686 | struct intel_crtc_state *other_crtc_state; | |
6687 | ||
1857e1da DV |
6688 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6689 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6690 | if (pipe_config->fdi_lanes > 4) { | |
6691 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6692 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6693 | return -EINVAL; |
1857e1da DV |
6694 | } |
6695 | ||
bafb6553 | 6696 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6697 | if (pipe_config->fdi_lanes > 2) { |
6698 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6699 | pipe_config->fdi_lanes); | |
6d293983 | 6700 | return -EINVAL; |
1857e1da | 6701 | } else { |
6d293983 | 6702 | return 0; |
1857e1da DV |
6703 | } |
6704 | } | |
6705 | ||
6706 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6707 | return 0; |
1857e1da DV |
6708 | |
6709 | /* Ivybridge 3 pipe is really complicated */ | |
6710 | switch (pipe) { | |
6711 | case PIPE_A: | |
6d293983 | 6712 | return 0; |
1857e1da | 6713 | case PIPE_B: |
6d293983 ACO |
6714 | if (pipe_config->fdi_lanes <= 2) |
6715 | return 0; | |
6716 | ||
6717 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6718 | other_crtc_state = | |
6719 | intel_atomic_get_crtc_state(state, other_crtc); | |
6720 | if (IS_ERR(other_crtc_state)) | |
6721 | return PTR_ERR(other_crtc_state); | |
6722 | ||
6723 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6724 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6725 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6726 | return -EINVAL; |
1857e1da | 6727 | } |
6d293983 | 6728 | return 0; |
1857e1da | 6729 | case PIPE_C: |
251cc67c VS |
6730 | if (pipe_config->fdi_lanes > 2) { |
6731 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6732 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6733 | return -EINVAL; |
251cc67c | 6734 | } |
6d293983 ACO |
6735 | |
6736 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6737 | other_crtc_state = | |
6738 | intel_atomic_get_crtc_state(state, other_crtc); | |
6739 | if (IS_ERR(other_crtc_state)) | |
6740 | return PTR_ERR(other_crtc_state); | |
6741 | ||
6742 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6743 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6744 | return -EINVAL; |
1857e1da | 6745 | } |
6d293983 | 6746 | return 0; |
1857e1da DV |
6747 | default: |
6748 | BUG(); | |
6749 | } | |
6750 | } | |
6751 | ||
e29c22c0 DV |
6752 | #define RETRY 1 |
6753 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6754 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6755 | { |
1857e1da | 6756 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6757 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6758 | int lane, link_bw, fdi_dotclock, ret; |
6759 | bool needs_recompute = false; | |
877d48d5 | 6760 | |
e29c22c0 | 6761 | retry: |
877d48d5 DV |
6762 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6763 | * each output octet as 10 bits. The actual frequency | |
6764 | * is stored as a divider into a 100MHz clock, and the | |
6765 | * mode pixel clock is stored in units of 1KHz. | |
6766 | * Hence the bw of each lane in terms of the mode signal | |
6767 | * is: | |
6768 | */ | |
21a727b3 | 6769 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6770 | |
241bfc38 | 6771 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6772 | |
2bd89a07 | 6773 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6774 | pipe_config->pipe_bpp); |
6775 | ||
6776 | pipe_config->fdi_lanes = lane; | |
6777 | ||
2bd89a07 | 6778 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6779 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6780 | |
e3b247da | 6781 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6782 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6783 | pipe_config->pipe_bpp -= 2*3; |
6784 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6785 | pipe_config->pipe_bpp); | |
6786 | needs_recompute = true; | |
6787 | pipe_config->bw_constrained = true; | |
6788 | ||
6789 | goto retry; | |
6790 | } | |
6791 | ||
6792 | if (needs_recompute) | |
6793 | return RETRY; | |
6794 | ||
6d293983 | 6795 | return ret; |
877d48d5 DV |
6796 | } |
6797 | ||
8cfb3407 VS |
6798 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6799 | struct intel_crtc_state *pipe_config) | |
6800 | { | |
6801 | if (pipe_config->pipe_bpp > 24) | |
6802 | return false; | |
6803 | ||
6804 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6805 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6806 | return true; |
6807 | ||
6808 | /* | |
b432e5cf VS |
6809 | * We compare against max which means we must take |
6810 | * the increased cdclk requirement into account when | |
6811 | * calculating the new cdclk. | |
6812 | * | |
6813 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6814 | */ |
6815 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6816 | dev_priv->max_cdclk_freq * 95 / 100; | |
6817 | } | |
6818 | ||
42db64ef | 6819 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6820 | struct intel_crtc_state *pipe_config) |
42db64ef | 6821 | { |
8cfb3407 | 6822 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6823 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 6824 | |
d330a953 | 6825 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6826 | hsw_crtc_supports_ips(crtc) && |
6827 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6828 | } |
6829 | ||
39acb4aa VS |
6830 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6831 | { | |
6832 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6833 | ||
6834 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6835 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6836 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6837 | } | |
6838 | ||
a43f6e0f | 6839 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6840 | struct intel_crtc_state *pipe_config) |
79e53945 | 6841 | { |
a43f6e0f | 6842 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6843 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 6844 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 6845 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 6846 | |
cf532bb2 | 6847 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 6848 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6849 | |
6850 | /* | |
39acb4aa | 6851 | * Enable double wide mode when the dot clock |
cf532bb2 | 6852 | * is > 90% of the (display) core speed. |
cf532bb2 | 6853 | */ |
39acb4aa VS |
6854 | if (intel_crtc_supports_double_wide(crtc) && |
6855 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 6856 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 6857 | pipe_config->double_wide = true; |
ad3a4479 | 6858 | } |
f3261156 | 6859 | } |
ad3a4479 | 6860 | |
f3261156 VS |
6861 | if (adjusted_mode->crtc_clock > clock_limit) { |
6862 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6863 | adjusted_mode->crtc_clock, clock_limit, | |
6864 | yesno(pipe_config->double_wide)); | |
6865 | return -EINVAL; | |
2c07245f | 6866 | } |
89749350 | 6867 | |
1d1d0e27 VS |
6868 | /* |
6869 | * Pipe horizontal size must be even in: | |
6870 | * - DVO ganged mode | |
6871 | * - LVDS dual channel mode | |
6872 | * - Double wide pipe | |
6873 | */ | |
2d84d2b3 | 6874 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6875 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6876 | pipe_config->pipe_src_w &= ~1; | |
6877 | ||
8693a824 DL |
6878 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6879 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6880 | */ |
6881 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6882 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6883 | return -EINVAL; |
44f46b42 | 6884 | |
f5adf94e | 6885 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6886 | hsw_compute_ips_config(crtc, pipe_config); |
6887 | ||
877d48d5 | 6888 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6889 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6890 | |
cf5a15be | 6891 | return 0; |
79e53945 JB |
6892 | } |
6893 | ||
1652d19e VS |
6894 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6895 | { | |
6896 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 6897 | uint32_t cdctl; |
1652d19e | 6898 | |
ea61791e | 6899 | skl_dpll0_update(dev_priv); |
1652d19e | 6900 | |
63911d72 | 6901 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 6902 | return dev_priv->cdclk_pll.ref; |
1652d19e | 6903 | |
ea61791e | 6904 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 6905 | |
63911d72 | 6906 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
6907 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6908 | case CDCLK_FREQ_450_432: | |
6909 | return 432000; | |
6910 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 6911 | return 308571; |
ea61791e VS |
6912 | case CDCLK_FREQ_540: |
6913 | return 540000; | |
1652d19e | 6914 | case CDCLK_FREQ_675_617: |
487ed2e4 | 6915 | return 617143; |
1652d19e | 6916 | default: |
ea61791e | 6917 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6918 | } |
6919 | } else { | |
1652d19e VS |
6920 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6921 | case CDCLK_FREQ_450_432: | |
6922 | return 450000; | |
6923 | case CDCLK_FREQ_337_308: | |
6924 | return 337500; | |
ea61791e VS |
6925 | case CDCLK_FREQ_540: |
6926 | return 540000; | |
1652d19e VS |
6927 | case CDCLK_FREQ_675_617: |
6928 | return 675000; | |
6929 | default: | |
ea61791e | 6930 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6931 | } |
6932 | } | |
6933 | ||
709e05c3 | 6934 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
6935 | } |
6936 | ||
83d7c81f VS |
6937 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
6938 | { | |
6939 | u32 val; | |
6940 | ||
6941 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 6942 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
6943 | |
6944 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 6945 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 6946 | return; |
83d7c81f | 6947 | |
1c3f7700 ID |
6948 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
6949 | return; | |
83d7c81f VS |
6950 | |
6951 | val = I915_READ(BXT_DE_PLL_CTL); | |
6952 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
6953 | dev_priv->cdclk_pll.ref; | |
6954 | } | |
6955 | ||
acd3f3d3 BP |
6956 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6957 | { | |
6958 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
6959 | u32 divider; |
6960 | int div, vco; | |
acd3f3d3 | 6961 | |
83d7c81f VS |
6962 | bxt_de_pll_update(dev_priv); |
6963 | ||
f5986242 VS |
6964 | vco = dev_priv->cdclk_pll.vco; |
6965 | if (vco == 0) | |
6966 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 6967 | |
f5986242 | 6968 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 6969 | |
f5986242 | 6970 | switch (divider) { |
acd3f3d3 | 6971 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
6972 | div = 2; |
6973 | break; | |
acd3f3d3 | 6974 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
6975 | div = 3; |
6976 | break; | |
acd3f3d3 | 6977 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
6978 | div = 4; |
6979 | break; | |
acd3f3d3 | 6980 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
6981 | div = 8; |
6982 | break; | |
6983 | default: | |
6984 | MISSING_CASE(divider); | |
6985 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
6986 | } |
6987 | ||
f5986242 | 6988 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
6989 | } |
6990 | ||
1652d19e VS |
6991 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6992 | { | |
fac5e23e | 6993 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6994 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6995 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6996 | ||
6997 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6998 | return 800000; | |
6999 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7000 | return 450000; | |
7001 | else if (freq == LCPLL_CLK_FREQ_450) | |
7002 | return 450000; | |
7003 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
7004 | return 540000; | |
7005 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
7006 | return 337500; | |
7007 | else | |
7008 | return 675000; | |
7009 | } | |
7010 | ||
7011 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
7012 | { | |
fac5e23e | 7013 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
7014 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7015 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7016 | ||
7017 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7018 | return 800000; | |
7019 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7020 | return 450000; | |
7021 | else if (freq == LCPLL_CLK_FREQ_450) | |
7022 | return 450000; | |
7023 | else if (IS_HSW_ULT(dev)) | |
7024 | return 337500; | |
7025 | else | |
7026 | return 540000; | |
79e53945 JB |
7027 | } |
7028 | ||
25eb05fc JB |
7029 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
7030 | { | |
bfa7df01 VS |
7031 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
7032 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
7033 | } |
7034 | ||
b37a6434 VS |
7035 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
7036 | { | |
7037 | return 450000; | |
7038 | } | |
7039 | ||
e70236a8 JB |
7040 | static int i945_get_display_clock_speed(struct drm_device *dev) |
7041 | { | |
7042 | return 400000; | |
7043 | } | |
79e53945 | 7044 | |
e70236a8 | 7045 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 7046 | { |
e907f170 | 7047 | return 333333; |
e70236a8 | 7048 | } |
79e53945 | 7049 | |
e70236a8 JB |
7050 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
7051 | { | |
7052 | return 200000; | |
7053 | } | |
79e53945 | 7054 | |
257a7ffc DV |
7055 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
7056 | { | |
7057 | u16 gcfgc = 0; | |
7058 | ||
7059 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
7060 | ||
7061 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7062 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7063 | return 266667; |
257a7ffc | 7064 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7065 | return 333333; |
257a7ffc | 7066 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7067 | return 444444; |
257a7ffc DV |
7068 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7069 | return 200000; | |
7070 | default: | |
7071 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7072 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7073 | return 133333; |
257a7ffc | 7074 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7075 | return 166667; |
257a7ffc DV |
7076 | } |
7077 | } | |
7078 | ||
e70236a8 JB |
7079 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
7080 | { | |
7081 | u16 gcfgc = 0; | |
79e53945 | 7082 | |
e70236a8 JB |
7083 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
7084 | ||
7085 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7086 | return 133333; |
e70236a8 JB |
7087 | else { |
7088 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7089 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7090 | return 333333; |
e70236a8 JB |
7091 | default: |
7092 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7093 | return 190000; | |
79e53945 | 7094 | } |
e70236a8 JB |
7095 | } |
7096 | } | |
7097 | ||
7098 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
7099 | { | |
e907f170 | 7100 | return 266667; |
e70236a8 JB |
7101 | } |
7102 | ||
1b1d2716 | 7103 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
7104 | { |
7105 | u16 hpllcc = 0; | |
1b1d2716 | 7106 | |
65cd2b3f VS |
7107 | /* |
7108 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7109 | * encoding is different :( | |
7110 | * FIXME is this the right way to detect 852GM/852GMV? | |
7111 | */ | |
7112 | if (dev->pdev->revision == 0x1) | |
7113 | return 133333; | |
7114 | ||
1b1d2716 VS |
7115 | pci_bus_read_config_word(dev->pdev->bus, |
7116 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
7117 | ||
e70236a8 JB |
7118 | /* Assume that the hardware is in the high speed state. This |
7119 | * should be the default. | |
7120 | */ | |
7121 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7122 | case GC_CLOCK_133_200: | |
1b1d2716 | 7123 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7124 | case GC_CLOCK_100_200: |
7125 | return 200000; | |
7126 | case GC_CLOCK_166_250: | |
7127 | return 250000; | |
7128 | case GC_CLOCK_100_133: | |
e907f170 | 7129 | return 133333; |
1b1d2716 VS |
7130 | case GC_CLOCK_133_266: |
7131 | case GC_CLOCK_133_266_2: | |
7132 | case GC_CLOCK_166_266: | |
7133 | return 266667; | |
e70236a8 | 7134 | } |
79e53945 | 7135 | |
e70236a8 JB |
7136 | /* Shouldn't happen */ |
7137 | return 0; | |
7138 | } | |
79e53945 | 7139 | |
e70236a8 JB |
7140 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7141 | { | |
e907f170 | 7142 | return 133333; |
79e53945 JB |
7143 | } |
7144 | ||
34edce2f VS |
7145 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7146 | { | |
fac5e23e | 7147 | struct drm_i915_private *dev_priv = to_i915(dev); |
34edce2f VS |
7148 | static const unsigned int blb_vco[8] = { |
7149 | [0] = 3200000, | |
7150 | [1] = 4000000, | |
7151 | [2] = 5333333, | |
7152 | [3] = 4800000, | |
7153 | [4] = 6400000, | |
7154 | }; | |
7155 | static const unsigned int pnv_vco[8] = { | |
7156 | [0] = 3200000, | |
7157 | [1] = 4000000, | |
7158 | [2] = 5333333, | |
7159 | [3] = 4800000, | |
7160 | [4] = 2666667, | |
7161 | }; | |
7162 | static const unsigned int cl_vco[8] = { | |
7163 | [0] = 3200000, | |
7164 | [1] = 4000000, | |
7165 | [2] = 5333333, | |
7166 | [3] = 6400000, | |
7167 | [4] = 3333333, | |
7168 | [5] = 3566667, | |
7169 | [6] = 4266667, | |
7170 | }; | |
7171 | static const unsigned int elk_vco[8] = { | |
7172 | [0] = 3200000, | |
7173 | [1] = 4000000, | |
7174 | [2] = 5333333, | |
7175 | [3] = 4800000, | |
7176 | }; | |
7177 | static const unsigned int ctg_vco[8] = { | |
7178 | [0] = 3200000, | |
7179 | [1] = 4000000, | |
7180 | [2] = 5333333, | |
7181 | [3] = 6400000, | |
7182 | [4] = 2666667, | |
7183 | [5] = 4266667, | |
7184 | }; | |
7185 | const unsigned int *vco_table; | |
7186 | unsigned int vco; | |
7187 | uint8_t tmp = 0; | |
7188 | ||
7189 | /* FIXME other chipsets? */ | |
7190 | if (IS_GM45(dev)) | |
7191 | vco_table = ctg_vco; | |
7192 | else if (IS_G4X(dev)) | |
7193 | vco_table = elk_vco; | |
7194 | else if (IS_CRESTLINE(dev)) | |
7195 | vco_table = cl_vco; | |
7196 | else if (IS_PINEVIEW(dev)) | |
7197 | vco_table = pnv_vco; | |
7198 | else if (IS_G33(dev)) | |
7199 | vco_table = blb_vco; | |
7200 | else | |
7201 | return 0; | |
7202 | ||
7203 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7204 | ||
7205 | vco = vco_table[tmp & 0x7]; | |
7206 | if (vco == 0) | |
7207 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7208 | else | |
7209 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7210 | ||
7211 | return vco; | |
7212 | } | |
7213 | ||
7214 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7215 | { | |
7216 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7217 | uint16_t tmp = 0; | |
7218 | ||
7219 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7220 | ||
7221 | cdclk_sel = (tmp >> 12) & 0x1; | |
7222 | ||
7223 | switch (vco) { | |
7224 | case 2666667: | |
7225 | case 4000000: | |
7226 | case 5333333: | |
7227 | return cdclk_sel ? 333333 : 222222; | |
7228 | case 3200000: | |
7229 | return cdclk_sel ? 320000 : 228571; | |
7230 | default: | |
7231 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7232 | return 222222; | |
7233 | } | |
7234 | } | |
7235 | ||
7236 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7237 | { | |
7238 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7239 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7240 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7241 | const uint8_t *div_table; | |
7242 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7243 | uint16_t tmp = 0; | |
7244 | ||
7245 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7246 | ||
7247 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7248 | ||
7249 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7250 | goto fail; | |
7251 | ||
7252 | switch (vco) { | |
7253 | case 3200000: | |
7254 | div_table = div_3200; | |
7255 | break; | |
7256 | case 4000000: | |
7257 | div_table = div_4000; | |
7258 | break; | |
7259 | case 5333333: | |
7260 | div_table = div_5333; | |
7261 | break; | |
7262 | default: | |
7263 | goto fail; | |
7264 | } | |
7265 | ||
7266 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7267 | ||
caf4e252 | 7268 | fail: |
34edce2f VS |
7269 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7270 | return 200000; | |
7271 | } | |
7272 | ||
7273 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7274 | { | |
7275 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7276 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7277 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7278 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7279 | const uint8_t *div_table; | |
7280 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7281 | uint16_t tmp = 0; | |
7282 | ||
7283 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7284 | ||
7285 | cdclk_sel = (tmp >> 4) & 0x7; | |
7286 | ||
7287 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7288 | goto fail; | |
7289 | ||
7290 | switch (vco) { | |
7291 | case 3200000: | |
7292 | div_table = div_3200; | |
7293 | break; | |
7294 | case 4000000: | |
7295 | div_table = div_4000; | |
7296 | break; | |
7297 | case 4800000: | |
7298 | div_table = div_4800; | |
7299 | break; | |
7300 | case 5333333: | |
7301 | div_table = div_5333; | |
7302 | break; | |
7303 | default: | |
7304 | goto fail; | |
7305 | } | |
7306 | ||
7307 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7308 | ||
caf4e252 | 7309 | fail: |
34edce2f VS |
7310 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7311 | return 190476; | |
7312 | } | |
7313 | ||
2c07245f | 7314 | static void |
a65851af | 7315 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7316 | { |
a65851af VS |
7317 | while (*num > DATA_LINK_M_N_MASK || |
7318 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7319 | *num >>= 1; |
7320 | *den >>= 1; | |
7321 | } | |
7322 | } | |
7323 | ||
a65851af VS |
7324 | static void compute_m_n(unsigned int m, unsigned int n, |
7325 | uint32_t *ret_m, uint32_t *ret_n) | |
7326 | { | |
7327 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7328 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7329 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7330 | } | |
7331 | ||
e69d0bc1 DV |
7332 | void |
7333 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7334 | int pixel_clock, int link_clock, | |
7335 | struct intel_link_m_n *m_n) | |
2c07245f | 7336 | { |
e69d0bc1 | 7337 | m_n->tu = 64; |
a65851af VS |
7338 | |
7339 | compute_m_n(bits_per_pixel * pixel_clock, | |
7340 | link_clock * nlanes * 8, | |
7341 | &m_n->gmch_m, &m_n->gmch_n); | |
7342 | ||
7343 | compute_m_n(pixel_clock, link_clock, | |
7344 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7345 | } |
7346 | ||
a7615030 CW |
7347 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7348 | { | |
d330a953 JN |
7349 | if (i915.panel_use_ssc >= 0) |
7350 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7351 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7352 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7353 | } |
7354 | ||
7429e9d4 | 7355 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7356 | { |
7df00d7a | 7357 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7358 | } |
f47709a9 | 7359 | |
7429e9d4 DV |
7360 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7361 | { | |
7362 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7363 | } |
7364 | ||
f47709a9 | 7365 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7366 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7367 | struct dpll *reduced_clock) |
a7516a05 | 7368 | { |
f47709a9 | 7369 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7370 | u32 fp, fp2 = 0; |
7371 | ||
7372 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7373 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7374 | if (reduced_clock) |
7429e9d4 | 7375 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7376 | } else { |
190f68c5 | 7377 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7378 | if (reduced_clock) |
7429e9d4 | 7379 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7380 | } |
7381 | ||
190f68c5 | 7382 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7383 | |
f47709a9 | 7384 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7385 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7386 | reduced_clock) { |
190f68c5 | 7387 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7388 | crtc->lowfreq_avail = true; |
a7516a05 | 7389 | } else { |
190f68c5 | 7390 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7391 | } |
7392 | } | |
7393 | ||
5e69f97f CML |
7394 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7395 | pipe) | |
89b667f8 JB |
7396 | { |
7397 | u32 reg_val; | |
7398 | ||
7399 | /* | |
7400 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7401 | * and set it to a reasonable value instead. | |
7402 | */ | |
ab3c759a | 7403 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7404 | reg_val &= 0xffffff00; |
7405 | reg_val |= 0x00000030; | |
ab3c759a | 7406 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7407 | |
ab3c759a | 7408 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7409 | reg_val &= 0x8cffffff; |
7410 | reg_val = 0x8c000000; | |
ab3c759a | 7411 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7412 | |
ab3c759a | 7413 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7414 | reg_val &= 0xffffff00; |
ab3c759a | 7415 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7416 | |
ab3c759a | 7417 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7418 | reg_val &= 0x00ffffff; |
7419 | reg_val |= 0xb0000000; | |
ab3c759a | 7420 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7421 | } |
7422 | ||
b551842d DV |
7423 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7424 | struct intel_link_m_n *m_n) | |
7425 | { | |
7426 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7427 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7428 | int pipe = crtc->pipe; |
7429 | ||
e3b95f1e DV |
7430 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7431 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7432 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7433 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7434 | } |
7435 | ||
7436 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7437 | struct intel_link_m_n *m_n, |
7438 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7439 | { |
7440 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7441 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7442 | int pipe = crtc->pipe; |
6e3c9717 | 7443 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7444 | |
7445 | if (INTEL_INFO(dev)->gen >= 5) { | |
7446 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7447 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7448 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7449 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7450 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7451 | * for gen < 8) and if DRRS is supported (to make sure the | |
7452 | * registers are not unnecessarily accessed). | |
7453 | */ | |
44395bfe | 7454 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7455 | crtc->config->has_drrs) { |
f769cd24 VK |
7456 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7457 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7458 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7459 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7460 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7461 | } | |
b551842d | 7462 | } else { |
e3b95f1e DV |
7463 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7464 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7465 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7466 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7467 | } |
7468 | } | |
7469 | ||
fe3cd48d | 7470 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7471 | { |
fe3cd48d R |
7472 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7473 | ||
7474 | if (m_n == M1_N1) { | |
7475 | dp_m_n = &crtc->config->dp_m_n; | |
7476 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7477 | } else if (m_n == M2_N2) { | |
7478 | ||
7479 | /* | |
7480 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7481 | * needs to be programmed into M1_N1. | |
7482 | */ | |
7483 | dp_m_n = &crtc->config->dp_m2_n2; | |
7484 | } else { | |
7485 | DRM_ERROR("Unsupported divider value\n"); | |
7486 | return; | |
7487 | } | |
7488 | ||
6e3c9717 ACO |
7489 | if (crtc->config->has_pch_encoder) |
7490 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7491 | else |
fe3cd48d | 7492 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7493 | } |
7494 | ||
251ac862 DV |
7495 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7496 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7497 | { |
03ed5cbf | 7498 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7499 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7500 | if (crtc->pipe != PIPE_A) |
7501 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7502 | |
cd2d34d9 | 7503 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7504 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7505 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7506 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7507 | ||
03ed5cbf VS |
7508 | pipe_config->dpll_hw_state.dpll_md = |
7509 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7510 | } | |
bdd4b6a6 | 7511 | |
03ed5cbf VS |
7512 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7513 | struct intel_crtc_state *pipe_config) | |
7514 | { | |
7515 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7516 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7517 | if (crtc->pipe != PIPE_A) |
7518 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7519 | ||
cd2d34d9 | 7520 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7521 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7522 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7523 | ||
03ed5cbf VS |
7524 | pipe_config->dpll_hw_state.dpll_md = |
7525 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7526 | } |
7527 | ||
d288f65f | 7528 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7529 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7530 | { |
f47709a9 | 7531 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7532 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7533 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7534 | u32 mdiv; |
a0c4da24 | 7535 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7536 | u32 coreclk, reg_val; |
a0c4da24 | 7537 | |
cd2d34d9 VS |
7538 | /* Enable Refclk */ |
7539 | I915_WRITE(DPLL(pipe), | |
7540 | pipe_config->dpll_hw_state.dpll & | |
7541 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7542 | ||
7543 | /* No need to actually set up the DPLL with DSI */ | |
7544 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7545 | return; | |
7546 | ||
a580516d | 7547 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7548 | |
d288f65f VS |
7549 | bestn = pipe_config->dpll.n; |
7550 | bestm1 = pipe_config->dpll.m1; | |
7551 | bestm2 = pipe_config->dpll.m2; | |
7552 | bestp1 = pipe_config->dpll.p1; | |
7553 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7554 | |
89b667f8 JB |
7555 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7556 | ||
7557 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7558 | if (pipe == PIPE_B) |
5e69f97f | 7559 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7560 | |
7561 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7562 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7563 | |
7564 | /* Disable target IRef on PLL */ | |
ab3c759a | 7565 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7566 | reg_val &= 0x00ffffff; |
ab3c759a | 7567 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7568 | |
7569 | /* Disable fast lock */ | |
ab3c759a | 7570 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7571 | |
7572 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7573 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7574 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7575 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7576 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7577 | |
7578 | /* | |
7579 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7580 | * but we don't support that). | |
7581 | * Note: don't use the DAC post divider as it seems unstable. | |
7582 | */ | |
7583 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7584 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7585 | |
a0c4da24 | 7586 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7587 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7588 | |
89b667f8 | 7589 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7590 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7591 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7592 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7593 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7594 | 0x009f0003); |
89b667f8 | 7595 | else |
ab3c759a | 7596 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7597 | 0x00d0000f); |
7598 | ||
37a5650b | 7599 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7600 | /* Use SSC source */ |
bdd4b6a6 | 7601 | if (pipe == PIPE_A) |
ab3c759a | 7602 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7603 | 0x0df40000); |
7604 | else | |
ab3c759a | 7605 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7606 | 0x0df70000); |
7607 | } else { /* HDMI or VGA */ | |
7608 | /* Use bend source */ | |
bdd4b6a6 | 7609 | if (pipe == PIPE_A) |
ab3c759a | 7610 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7611 | 0x0df70000); |
7612 | else | |
ab3c759a | 7613 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7614 | 0x0df40000); |
7615 | } | |
a0c4da24 | 7616 | |
ab3c759a | 7617 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7618 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7619 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7620 | coreclk |= 0x01000000; |
ab3c759a | 7621 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7622 | |
ab3c759a | 7623 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7624 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7625 | } |
7626 | ||
d288f65f | 7627 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7628 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7629 | { |
7630 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7631 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7632 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7633 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7634 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7635 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7636 | u32 dpio_val; |
9cbe40c1 | 7637 | int vco; |
9d556c99 | 7638 | |
cd2d34d9 VS |
7639 | /* Enable Refclk and SSC */ |
7640 | I915_WRITE(DPLL(pipe), | |
7641 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7642 | ||
7643 | /* No need to actually set up the DPLL with DSI */ | |
7644 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7645 | return; | |
7646 | ||
d288f65f VS |
7647 | bestn = pipe_config->dpll.n; |
7648 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7649 | bestm1 = pipe_config->dpll.m1; | |
7650 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7651 | bestp1 = pipe_config->dpll.p1; | |
7652 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7653 | vco = pipe_config->dpll.vco; |
a945ce7e | 7654 | dpio_val = 0; |
9cbe40c1 | 7655 | loopfilter = 0; |
9d556c99 | 7656 | |
a580516d | 7657 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7658 | |
9d556c99 CML |
7659 | /* p1 and p2 divider */ |
7660 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7661 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7662 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7663 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7664 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7665 | ||
7666 | /* Feedback post-divider - m2 */ | |
7667 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7668 | ||
7669 | /* Feedback refclk divider - n and m1 */ | |
7670 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7671 | DPIO_CHV_M1_DIV_BY_2 | | |
7672 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7673 | ||
7674 | /* M2 fraction division */ | |
25a25dfc | 7675 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7676 | |
7677 | /* M2 fraction division enable */ | |
a945ce7e VP |
7678 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7679 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7680 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7681 | if (bestm2_frac) | |
7682 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7683 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7684 | |
de3a0fde VP |
7685 | /* Program digital lock detect threshold */ |
7686 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7687 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7688 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7689 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7690 | if (!bestm2_frac) | |
7691 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7692 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7693 | ||
9d556c99 | 7694 | /* Loop filter */ |
9cbe40c1 VP |
7695 | if (vco == 5400000) { |
7696 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7697 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7698 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7699 | tribuf_calcntr = 0x9; | |
7700 | } else if (vco <= 6200000) { | |
7701 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7702 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7703 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7704 | tribuf_calcntr = 0x9; | |
7705 | } else if (vco <= 6480000) { | |
7706 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7707 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7708 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7709 | tribuf_calcntr = 0x8; | |
7710 | } else { | |
7711 | /* Not supported. Apply the same limits as in the max case */ | |
7712 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7713 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7714 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7715 | tribuf_calcntr = 0; | |
7716 | } | |
9d556c99 CML |
7717 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7718 | ||
968040b2 | 7719 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7720 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7721 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7722 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7723 | ||
9d556c99 CML |
7724 | /* AFC Recal */ |
7725 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7726 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7727 | DPIO_AFC_RECAL); | |
7728 | ||
a580516d | 7729 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7730 | } |
7731 | ||
d288f65f VS |
7732 | /** |
7733 | * vlv_force_pll_on - forcibly enable just the PLL | |
7734 | * @dev_priv: i915 private structure | |
7735 | * @pipe: pipe PLL to enable | |
7736 | * @dpll: PLL configuration | |
7737 | * | |
7738 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7739 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7740 | * be enabled. | |
7741 | */ | |
3f36b937 TU |
7742 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7743 | const struct dpll *dpll) | |
d288f65f VS |
7744 | { |
7745 | struct intel_crtc *crtc = | |
7746 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7747 | struct intel_crtc_state *pipe_config; |
7748 | ||
7749 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7750 | if (!pipe_config) | |
7751 | return -ENOMEM; | |
7752 | ||
7753 | pipe_config->base.crtc = &crtc->base; | |
7754 | pipe_config->pixel_multiplier = 1; | |
7755 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7756 | |
7757 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7758 | chv_compute_dpll(crtc, pipe_config); |
7759 | chv_prepare_pll(crtc, pipe_config); | |
7760 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7761 | } else { |
3f36b937 TU |
7762 | vlv_compute_dpll(crtc, pipe_config); |
7763 | vlv_prepare_pll(crtc, pipe_config); | |
7764 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7765 | } |
3f36b937 TU |
7766 | |
7767 | kfree(pipe_config); | |
7768 | ||
7769 | return 0; | |
d288f65f VS |
7770 | } |
7771 | ||
7772 | /** | |
7773 | * vlv_force_pll_off - forcibly disable just the PLL | |
7774 | * @dev_priv: i915 private structure | |
7775 | * @pipe: pipe PLL to disable | |
7776 | * | |
7777 | * Disable the PLL for @pipe. To be used in cases where we need | |
7778 | * the PLL enabled even when @pipe is not going to be enabled. | |
7779 | */ | |
7780 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7781 | { | |
7782 | if (IS_CHERRYVIEW(dev)) | |
7783 | chv_disable_pll(to_i915(dev), pipe); | |
7784 | else | |
7785 | vlv_disable_pll(to_i915(dev), pipe); | |
7786 | } | |
7787 | ||
251ac862 DV |
7788 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7789 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7790 | struct dpll *reduced_clock) |
eb1cbe48 | 7791 | { |
f47709a9 | 7792 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7793 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7794 | u32 dpll; |
190f68c5 | 7795 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7796 | |
190f68c5 | 7797 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7798 | |
eb1cbe48 DV |
7799 | dpll = DPLL_VGA_MODE_DIS; |
7800 | ||
2d84d2b3 | 7801 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7802 | dpll |= DPLLB_MODE_LVDS; |
7803 | else | |
7804 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7805 | |
ef1b460d | 7806 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7807 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7808 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7809 | } |
198a037f | 7810 | |
3d6e9ee0 VS |
7811 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7812 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 7813 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7814 | |
37a5650b | 7815 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 7816 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7817 | |
7818 | /* compute bitmask from p1 value */ | |
7819 | if (IS_PINEVIEW(dev)) | |
7820 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7821 | else { | |
7822 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7823 | if (IS_G4X(dev) && reduced_clock) | |
7824 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7825 | } | |
7826 | switch (clock->p2) { | |
7827 | case 5: | |
7828 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7829 | break; | |
7830 | case 7: | |
7831 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7832 | break; | |
7833 | case 10: | |
7834 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7835 | break; | |
7836 | case 14: | |
7837 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7838 | break; | |
7839 | } | |
7840 | if (INTEL_INFO(dev)->gen >= 4) | |
7841 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7842 | ||
190f68c5 | 7843 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7844 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 7845 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7846 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7847 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7848 | else | |
7849 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7850 | ||
7851 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7852 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7853 | |
eb1cbe48 | 7854 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7855 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7856 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7857 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7858 | } |
7859 | } | |
7860 | ||
251ac862 DV |
7861 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7862 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7863 | struct dpll *reduced_clock) |
eb1cbe48 | 7864 | { |
f47709a9 | 7865 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7866 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7867 | u32 dpll; |
190f68c5 | 7868 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7869 | |
190f68c5 | 7870 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7871 | |
eb1cbe48 DV |
7872 | dpll = DPLL_VGA_MODE_DIS; |
7873 | ||
2d84d2b3 | 7874 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7875 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7876 | } else { | |
7877 | if (clock->p1 == 2) | |
7878 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7879 | else | |
7880 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7881 | if (clock->p2 == 4) | |
7882 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7883 | } | |
7884 | ||
2d84d2b3 | 7885 | if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7886 | dpll |= DPLL_DVO_2X_MODE; |
7887 | ||
2d84d2b3 | 7888 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7889 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7890 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7891 | else | |
7892 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7893 | ||
7894 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7895 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7896 | } |
7897 | ||
8a654f3b | 7898 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7899 | { |
7900 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7901 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 7902 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7903 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7904 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7905 | uint32_t crtc_vtotal, crtc_vblank_end; |
7906 | int vsyncshift = 0; | |
4d8a62ea DV |
7907 | |
7908 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7909 | * the hw state checker will get angry at the mismatch. */ | |
7910 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7911 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7912 | |
609aeaca | 7913 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7914 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7915 | crtc_vtotal -= 1; |
7916 | crtc_vblank_end -= 1; | |
609aeaca | 7917 | |
2d84d2b3 | 7918 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7919 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7920 | else | |
7921 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7922 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7923 | if (vsyncshift < 0) |
7924 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7925 | } |
7926 | ||
7927 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7928 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7929 | |
fe2b8f9d | 7930 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7931 | (adjusted_mode->crtc_hdisplay - 1) | |
7932 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7933 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7934 | (adjusted_mode->crtc_hblank_start - 1) | |
7935 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7936 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7937 | (adjusted_mode->crtc_hsync_start - 1) | |
7938 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7939 | ||
fe2b8f9d | 7940 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7941 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7942 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7943 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7944 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7945 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7946 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7947 | (adjusted_mode->crtc_vsync_start - 1) | |
7948 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7949 | ||
b5e508d4 PZ |
7950 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7951 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7952 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7953 | * bits. */ | |
7954 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7955 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7956 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7957 | ||
bc58be60 JN |
7958 | } |
7959 | ||
7960 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7961 | { | |
7962 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7963 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7964 | enum pipe pipe = intel_crtc->pipe; |
7965 | ||
b0e77b9c PZ |
7966 | /* pipesrc controls the size that is scaled from, which should |
7967 | * always be the user's requested size. | |
7968 | */ | |
7969 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7970 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7971 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7972 | } |
7973 | ||
1bd1bd80 | 7974 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7975 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7976 | { |
7977 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7978 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7979 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7980 | uint32_t tmp; | |
7981 | ||
7982 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7983 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7984 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7985 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7986 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7987 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7988 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7989 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7990 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7991 | |
7992 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7993 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7994 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7995 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7996 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7997 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7998 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7999 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8000 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8001 | |
8002 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
8003 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8004 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
8005 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8006 | } |
bc58be60 JN |
8007 | } |
8008 | ||
8009 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8010 | struct intel_crtc_state *pipe_config) | |
8011 | { | |
8012 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8013 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8014 | u32 tmp; |
1bd1bd80 DV |
8015 | |
8016 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
8017 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8018 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8019 | ||
2d112de7 ACO |
8020 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8021 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8022 | } |
8023 | ||
f6a83288 | 8024 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8025 | struct intel_crtc_state *pipe_config) |
babea61d | 8026 | { |
2d112de7 ACO |
8027 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8028 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8029 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8030 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8031 | |
2d112de7 ACO |
8032 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8033 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8034 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8035 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8036 | |
2d112de7 | 8037 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8038 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8039 | |
2d112de7 ACO |
8040 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8041 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8042 | |
8043 | mode->hsync = drm_mode_hsync(mode); | |
8044 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8045 | drm_mode_set_name(mode); | |
babea61d JB |
8046 | } |
8047 | ||
84b046f3 DV |
8048 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8049 | { | |
8050 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8051 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
8052 | uint32_t pipeconf; |
8053 | ||
9f11a9e4 | 8054 | pipeconf = 0; |
84b046f3 | 8055 | |
b6b5d049 VS |
8056 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8057 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8058 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8059 | |
6e3c9717 | 8060 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8061 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8062 | |
ff9ce46e | 8063 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 8064 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 8065 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8066 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8067 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8068 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8069 | |
6e3c9717 | 8070 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8071 | case 18: |
8072 | pipeconf |= PIPECONF_6BPC; | |
8073 | break; | |
8074 | case 24: | |
8075 | pipeconf |= PIPECONF_8BPC; | |
8076 | break; | |
8077 | case 30: | |
8078 | pipeconf |= PIPECONF_10BPC; | |
8079 | break; | |
8080 | default: | |
8081 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8082 | BUG(); | |
84b046f3 DV |
8083 | } |
8084 | } | |
8085 | ||
8086 | if (HAS_PIPE_CXSR(dev)) { | |
8087 | if (intel_crtc->lowfreq_avail) { | |
8088 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8089 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8090 | } else { | |
8091 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8092 | } |
8093 | } | |
8094 | ||
6e3c9717 | 8095 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 8096 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 8097 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8098 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8099 | else | |
8100 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8101 | } else | |
84b046f3 DV |
8102 | pipeconf |= PIPECONF_PROGRESSIVE; |
8103 | ||
666a4537 WB |
8104 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8105 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 8106 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8107 | |
84b046f3 DV |
8108 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8109 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8110 | } | |
8111 | ||
81c97f52 ACO |
8112 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8113 | struct intel_crtc_state *crtc_state) | |
8114 | { | |
8115 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8116 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8117 | const struct intel_limit *limit; |
81c97f52 ACO |
8118 | int refclk = 48000; |
8119 | ||
8120 | memset(&crtc_state->dpll_hw_state, 0, | |
8121 | sizeof(crtc_state->dpll_hw_state)); | |
8122 | ||
2d84d2b3 | 8123 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8124 | if (intel_panel_use_ssc(dev_priv)) { |
8125 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8126 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8127 | } | |
8128 | ||
8129 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8130 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8131 | limit = &intel_limits_i8xx_dvo; |
8132 | } else { | |
8133 | limit = &intel_limits_i8xx_dac; | |
8134 | } | |
8135 | ||
8136 | if (!crtc_state->clock_set && | |
8137 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8138 | refclk, NULL, &crtc_state->dpll)) { | |
8139 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8140 | return -EINVAL; | |
8141 | } | |
8142 | ||
8143 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8144 | ||
8145 | return 0; | |
8146 | } | |
8147 | ||
19ec6693 ACO |
8148 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8149 | struct intel_crtc_state *crtc_state) | |
8150 | { | |
8151 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8152 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8153 | const struct intel_limit *limit; |
19ec6693 ACO |
8154 | int refclk = 96000; |
8155 | ||
8156 | memset(&crtc_state->dpll_hw_state, 0, | |
8157 | sizeof(crtc_state->dpll_hw_state)); | |
8158 | ||
2d84d2b3 | 8159 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8160 | if (intel_panel_use_ssc(dev_priv)) { |
8161 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8162 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8163 | } | |
8164 | ||
8165 | if (intel_is_dual_link_lvds(dev)) | |
8166 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8167 | else | |
8168 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8169 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8170 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8171 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8172 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8173 | limit = &intel_limits_g4x_sdvo; |
8174 | } else { | |
8175 | /* The option is for other outputs */ | |
8176 | limit = &intel_limits_i9xx_sdvo; | |
8177 | } | |
8178 | ||
8179 | if (!crtc_state->clock_set && | |
8180 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8181 | refclk, NULL, &crtc_state->dpll)) { | |
8182 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8183 | return -EINVAL; | |
8184 | } | |
8185 | ||
8186 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8187 | ||
8188 | return 0; | |
8189 | } | |
8190 | ||
70e8aa21 ACO |
8191 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8192 | struct intel_crtc_state *crtc_state) | |
8193 | { | |
8194 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8195 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8196 | const struct intel_limit *limit; |
70e8aa21 ACO |
8197 | int refclk = 96000; |
8198 | ||
8199 | memset(&crtc_state->dpll_hw_state, 0, | |
8200 | sizeof(crtc_state->dpll_hw_state)); | |
8201 | ||
2d84d2b3 | 8202 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8203 | if (intel_panel_use_ssc(dev_priv)) { |
8204 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8205 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8206 | } | |
8207 | ||
8208 | limit = &intel_limits_pineview_lvds; | |
8209 | } else { | |
8210 | limit = &intel_limits_pineview_sdvo; | |
8211 | } | |
8212 | ||
8213 | if (!crtc_state->clock_set && | |
8214 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8215 | refclk, NULL, &crtc_state->dpll)) { | |
8216 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8217 | return -EINVAL; | |
8218 | } | |
8219 | ||
8220 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8221 | ||
8222 | return 0; | |
8223 | } | |
8224 | ||
190f68c5 ACO |
8225 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8226 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8227 | { |
c7653199 | 8228 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8229 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8230 | const struct intel_limit *limit; |
81c97f52 | 8231 | int refclk = 96000; |
79e53945 | 8232 | |
dd3cd74a ACO |
8233 | memset(&crtc_state->dpll_hw_state, 0, |
8234 | sizeof(crtc_state->dpll_hw_state)); | |
8235 | ||
2d84d2b3 | 8236 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8237 | if (intel_panel_use_ssc(dev_priv)) { |
8238 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8239 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8240 | } | |
43565a06 | 8241 | |
70e8aa21 ACO |
8242 | limit = &intel_limits_i9xx_lvds; |
8243 | } else { | |
8244 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8245 | } |
79e53945 | 8246 | |
70e8aa21 ACO |
8247 | if (!crtc_state->clock_set && |
8248 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8249 | refclk, NULL, &crtc_state->dpll)) { | |
8250 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8251 | return -EINVAL; | |
f47709a9 | 8252 | } |
7026d4ac | 8253 | |
81c97f52 | 8254 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8255 | |
c8f7a0db | 8256 | return 0; |
f564048e EA |
8257 | } |
8258 | ||
65b3d6a9 ACO |
8259 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8260 | struct intel_crtc_state *crtc_state) | |
8261 | { | |
8262 | int refclk = 100000; | |
1b6f4958 | 8263 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8264 | |
8265 | memset(&crtc_state->dpll_hw_state, 0, | |
8266 | sizeof(crtc_state->dpll_hw_state)); | |
8267 | ||
65b3d6a9 ACO |
8268 | if (!crtc_state->clock_set && |
8269 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8270 | refclk, NULL, &crtc_state->dpll)) { | |
8271 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8272 | return -EINVAL; | |
8273 | } | |
8274 | ||
8275 | chv_compute_dpll(crtc, crtc_state); | |
8276 | ||
8277 | return 0; | |
8278 | } | |
8279 | ||
8280 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8281 | struct intel_crtc_state *crtc_state) | |
8282 | { | |
8283 | int refclk = 100000; | |
1b6f4958 | 8284 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8285 | |
8286 | memset(&crtc_state->dpll_hw_state, 0, | |
8287 | sizeof(crtc_state->dpll_hw_state)); | |
8288 | ||
65b3d6a9 ACO |
8289 | if (!crtc_state->clock_set && |
8290 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8291 | refclk, NULL, &crtc_state->dpll)) { | |
8292 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8293 | return -EINVAL; | |
8294 | } | |
8295 | ||
8296 | vlv_compute_dpll(crtc, crtc_state); | |
8297 | ||
8298 | return 0; | |
8299 | } | |
8300 | ||
2fa2fe9a | 8301 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8302 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8303 | { |
8304 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8305 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8306 | uint32_t tmp; |
8307 | ||
dc9e7dec VS |
8308 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8309 | return; | |
8310 | ||
2fa2fe9a | 8311 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8312 | if (!(tmp & PFIT_ENABLE)) |
8313 | return; | |
2fa2fe9a | 8314 | |
06922821 | 8315 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8316 | if (INTEL_INFO(dev)->gen < 4) { |
8317 | if (crtc->pipe != PIPE_B) | |
8318 | return; | |
2fa2fe9a DV |
8319 | } else { |
8320 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8321 | return; | |
8322 | } | |
8323 | ||
06922821 | 8324 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8325 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8326 | } |
8327 | ||
acbec814 | 8328 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8329 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8330 | { |
8331 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8332 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8333 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8334 | struct dpll clock; |
acbec814 | 8335 | u32 mdiv; |
662c6ecb | 8336 | int refclk = 100000; |
acbec814 | 8337 | |
b521973b VS |
8338 | /* In case of DSI, DPLL will not be used */ |
8339 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8340 | return; |
8341 | ||
a580516d | 8342 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8343 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8344 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8345 | |
8346 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8347 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8348 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8349 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8350 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8351 | ||
dccbea3b | 8352 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8353 | } |
8354 | ||
5724dbd1 DL |
8355 | static void |
8356 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8357 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8358 | { |
8359 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8360 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8361 | u32 val, base, offset; |
8362 | int pipe = crtc->pipe, plane = crtc->plane; | |
8363 | int fourcc, pixel_format; | |
6761dd31 | 8364 | unsigned int aligned_height; |
b113d5ee | 8365 | struct drm_framebuffer *fb; |
1b842c89 | 8366 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8367 | |
42a7b088 DL |
8368 | val = I915_READ(DSPCNTR(plane)); |
8369 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8370 | return; | |
8371 | ||
d9806c9f | 8372 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8373 | if (!intel_fb) { |
1ad292b5 JB |
8374 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8375 | return; | |
8376 | } | |
8377 | ||
1b842c89 DL |
8378 | fb = &intel_fb->base; |
8379 | ||
18c5247e DV |
8380 | if (INTEL_INFO(dev)->gen >= 4) { |
8381 | if (val & DISPPLANE_TILED) { | |
49af449b | 8382 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8383 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8384 | } | |
8385 | } | |
1ad292b5 JB |
8386 | |
8387 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8388 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8389 | fb->pixel_format = fourcc; |
8390 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8391 | |
8392 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8393 | if (plane_config->tiling) |
1ad292b5 JB |
8394 | offset = I915_READ(DSPTILEOFF(plane)); |
8395 | else | |
8396 | offset = I915_READ(DSPLINOFF(plane)); | |
8397 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8398 | } else { | |
8399 | base = I915_READ(DSPADDR(plane)); | |
8400 | } | |
8401 | plane_config->base = base; | |
8402 | ||
8403 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8404 | fb->width = ((val >> 16) & 0xfff) + 1; |
8405 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8406 | |
8407 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8408 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8409 | |
b113d5ee | 8410 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8411 | fb->pixel_format, |
8412 | fb->modifier[0]); | |
1ad292b5 | 8413 | |
f37b5c2b | 8414 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8415 | |
2844a921 DL |
8416 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8417 | pipe_name(pipe), plane, fb->width, fb->height, | |
8418 | fb->bits_per_pixel, base, fb->pitches[0], | |
8419 | plane_config->size); | |
1ad292b5 | 8420 | |
2d14030b | 8421 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8422 | } |
8423 | ||
70b23a98 | 8424 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8425 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8426 | { |
8427 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8428 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8429 | int pipe = pipe_config->cpu_transcoder; |
8430 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8431 | struct dpll clock; |
0d7b6b11 | 8432 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8433 | int refclk = 100000; |
8434 | ||
b521973b VS |
8435 | /* In case of DSI, DPLL will not be used */ |
8436 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8437 | return; | |
8438 | ||
a580516d | 8439 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8440 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8441 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8442 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8443 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8444 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8445 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8446 | |
8447 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8448 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8449 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8450 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8451 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8452 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8453 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8454 | ||
dccbea3b | 8455 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8456 | } |
8457 | ||
0e8ffe1b | 8458 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8459 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8460 | { |
8461 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8462 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8463 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8464 | uint32_t tmp; |
1729050e | 8465 | bool ret; |
0e8ffe1b | 8466 | |
1729050e ID |
8467 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8468 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8469 | return false; |
8470 | ||
e143a21c | 8471 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8472 | pipe_config->shared_dpll = NULL; |
eccb140b | 8473 | |
1729050e ID |
8474 | ret = false; |
8475 | ||
0e8ffe1b DV |
8476 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8477 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8478 | goto out; |
0e8ffe1b | 8479 | |
666a4537 | 8480 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8481 | switch (tmp & PIPECONF_BPC_MASK) { |
8482 | case PIPECONF_6BPC: | |
8483 | pipe_config->pipe_bpp = 18; | |
8484 | break; | |
8485 | case PIPECONF_8BPC: | |
8486 | pipe_config->pipe_bpp = 24; | |
8487 | break; | |
8488 | case PIPECONF_10BPC: | |
8489 | pipe_config->pipe_bpp = 30; | |
8490 | break; | |
8491 | default: | |
8492 | break; | |
8493 | } | |
8494 | } | |
8495 | ||
666a4537 WB |
8496 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8497 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8498 | pipe_config->limited_color_range = true; |
8499 | ||
282740f7 VS |
8500 | if (INTEL_INFO(dev)->gen < 4) |
8501 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8502 | ||
1bd1bd80 | 8503 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8504 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8505 | |
2fa2fe9a DV |
8506 | i9xx_get_pfit_config(crtc, pipe_config); |
8507 | ||
6c49f241 | 8508 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8509 | /* No way to read it out on pipes B and C */ |
8510 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8511 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8512 | else | |
8513 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8514 | pipe_config->pixel_multiplier = |
8515 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8516 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8517 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8518 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8519 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8520 | pipe_config->pixel_multiplier = | |
8521 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8522 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8523 | } else { | |
8524 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8525 | * port and will be fixed up in the encoder->get_config | |
8526 | * function. */ | |
8527 | pipe_config->pixel_multiplier = 1; | |
8528 | } | |
8bcc2795 | 8529 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8530 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8531 | /* |
8532 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8533 | * on 830. Filter it out here so that we don't | |
8534 | * report errors due to that. | |
8535 | */ | |
8536 | if (IS_I830(dev)) | |
8537 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8538 | ||
8bcc2795 DV |
8539 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8540 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8541 | } else { |
8542 | /* Mask out read-only status bits. */ | |
8543 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8544 | DPLL_PORTC_READY_MASK | | |
8545 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8546 | } |
6c49f241 | 8547 | |
70b23a98 VS |
8548 | if (IS_CHERRYVIEW(dev)) |
8549 | chv_crtc_clock_get(crtc, pipe_config); | |
8550 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8551 | vlv_crtc_clock_get(crtc, pipe_config); |
8552 | else | |
8553 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8554 | |
0f64614d VS |
8555 | /* |
8556 | * Normally the dotclock is filled in by the encoder .get_config() | |
8557 | * but in case the pipe is enabled w/o any ports we need a sane | |
8558 | * default. | |
8559 | */ | |
8560 | pipe_config->base.adjusted_mode.crtc_clock = | |
8561 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8562 | ||
1729050e ID |
8563 | ret = true; |
8564 | ||
8565 | out: | |
8566 | intel_display_power_put(dev_priv, power_domain); | |
8567 | ||
8568 | return ret; | |
0e8ffe1b DV |
8569 | } |
8570 | ||
dde86e2d | 8571 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8572 | { |
fac5e23e | 8573 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8574 | struct intel_encoder *encoder; |
1c1a24d2 | 8575 | int i; |
74cfd7ac | 8576 | u32 val, final; |
13d83a67 | 8577 | bool has_lvds = false; |
199e5d79 | 8578 | bool has_cpu_edp = false; |
199e5d79 | 8579 | bool has_panel = false; |
99eb6a01 KP |
8580 | bool has_ck505 = false; |
8581 | bool can_ssc = false; | |
1c1a24d2 | 8582 | bool using_ssc_source = false; |
13d83a67 JB |
8583 | |
8584 | /* We need to take the global config into account */ | |
b2784e15 | 8585 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8586 | switch (encoder->type) { |
8587 | case INTEL_OUTPUT_LVDS: | |
8588 | has_panel = true; | |
8589 | has_lvds = true; | |
8590 | break; | |
8591 | case INTEL_OUTPUT_EDP: | |
8592 | has_panel = true; | |
2de6905f | 8593 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8594 | has_cpu_edp = true; |
8595 | break; | |
6847d71b PZ |
8596 | default: |
8597 | break; | |
13d83a67 JB |
8598 | } |
8599 | } | |
8600 | ||
99eb6a01 | 8601 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8602 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8603 | can_ssc = has_ck505; |
8604 | } else { | |
8605 | has_ck505 = false; | |
8606 | can_ssc = true; | |
8607 | } | |
8608 | ||
1c1a24d2 L |
8609 | /* Check if any DPLLs are using the SSC source */ |
8610 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8611 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8612 | ||
8613 | if (!(temp & DPLL_VCO_ENABLE)) | |
8614 | continue; | |
8615 | ||
8616 | if ((temp & PLL_REF_INPUT_MASK) == | |
8617 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8618 | using_ssc_source = true; | |
8619 | break; | |
8620 | } | |
8621 | } | |
8622 | ||
8623 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8624 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8625 | |
8626 | /* Ironlake: try to setup display ref clock before DPLL | |
8627 | * enabling. This is only under driver's control after | |
8628 | * PCH B stepping, previous chipset stepping should be | |
8629 | * ignoring this setting. | |
8630 | */ | |
74cfd7ac CW |
8631 | val = I915_READ(PCH_DREF_CONTROL); |
8632 | ||
8633 | /* As we must carefully and slowly disable/enable each source in turn, | |
8634 | * compute the final state we want first and check if we need to | |
8635 | * make any changes at all. | |
8636 | */ | |
8637 | final = val; | |
8638 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8639 | if (has_ck505) | |
8640 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8641 | else | |
8642 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8643 | ||
8c07eb68 | 8644 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8645 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8646 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8647 | |
8648 | if (has_panel) { | |
8649 | final |= DREF_SSC_SOURCE_ENABLE; | |
8650 | ||
8651 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8652 | final |= DREF_SSC1_ENABLE; | |
8653 | ||
8654 | if (has_cpu_edp) { | |
8655 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8656 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8657 | else | |
8658 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8659 | } else | |
8660 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8661 | } else if (using_ssc_source) { |
8662 | final |= DREF_SSC_SOURCE_ENABLE; | |
8663 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8664 | } |
8665 | ||
8666 | if (final == val) | |
8667 | return; | |
8668 | ||
13d83a67 | 8669 | /* Always enable nonspread source */ |
74cfd7ac | 8670 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8671 | |
99eb6a01 | 8672 | if (has_ck505) |
74cfd7ac | 8673 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8674 | else |
74cfd7ac | 8675 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8676 | |
199e5d79 | 8677 | if (has_panel) { |
74cfd7ac CW |
8678 | val &= ~DREF_SSC_SOURCE_MASK; |
8679 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8680 | |
199e5d79 | 8681 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8682 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8683 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8684 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8685 | } else |
74cfd7ac | 8686 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8687 | |
8688 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8689 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8690 | POSTING_READ(PCH_DREF_CONTROL); |
8691 | udelay(200); | |
8692 | ||
74cfd7ac | 8693 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8694 | |
8695 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8696 | if (has_cpu_edp) { |
99eb6a01 | 8697 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8698 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8699 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8700 | } else |
74cfd7ac | 8701 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8702 | } else |
74cfd7ac | 8703 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8704 | |
74cfd7ac | 8705 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8706 | POSTING_READ(PCH_DREF_CONTROL); |
8707 | udelay(200); | |
8708 | } else { | |
1c1a24d2 | 8709 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 8710 | |
74cfd7ac | 8711 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8712 | |
8713 | /* Turn off CPU output */ | |
74cfd7ac | 8714 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8715 | |
74cfd7ac | 8716 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8717 | POSTING_READ(PCH_DREF_CONTROL); |
8718 | udelay(200); | |
8719 | ||
1c1a24d2 L |
8720 | if (!using_ssc_source) { |
8721 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 8722 | |
1c1a24d2 L |
8723 | /* Turn off the SSC source */ |
8724 | val &= ~DREF_SSC_SOURCE_MASK; | |
8725 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 8726 | |
1c1a24d2 L |
8727 | /* Turn off SSC1 */ |
8728 | val &= ~DREF_SSC1_ENABLE; | |
8729 | ||
8730 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8731 | POSTING_READ(PCH_DREF_CONTROL); | |
8732 | udelay(200); | |
8733 | } | |
13d83a67 | 8734 | } |
74cfd7ac CW |
8735 | |
8736 | BUG_ON(val != final); | |
13d83a67 JB |
8737 | } |
8738 | ||
f31f2d55 | 8739 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8740 | { |
f31f2d55 | 8741 | uint32_t tmp; |
dde86e2d | 8742 | |
0ff066a9 PZ |
8743 | tmp = I915_READ(SOUTH_CHICKEN2); |
8744 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8745 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8746 | |
cf3598c2 ID |
8747 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
8748 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 8749 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 8750 | |
0ff066a9 PZ |
8751 | tmp = I915_READ(SOUTH_CHICKEN2); |
8752 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8753 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8754 | |
cf3598c2 ID |
8755 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
8756 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 8757 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
8758 | } |
8759 | ||
8760 | /* WaMPhyProgramming:hsw */ | |
8761 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8762 | { | |
8763 | uint32_t tmp; | |
dde86e2d PZ |
8764 | |
8765 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8766 | tmp &= ~(0xFF << 24); | |
8767 | tmp |= (0x12 << 24); | |
8768 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8769 | ||
dde86e2d PZ |
8770 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8771 | tmp |= (1 << 11); | |
8772 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8773 | ||
8774 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8775 | tmp |= (1 << 11); | |
8776 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8777 | ||
dde86e2d PZ |
8778 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8779 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8780 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8781 | ||
8782 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8783 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8784 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8785 | ||
0ff066a9 PZ |
8786 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8787 | tmp &= ~(7 << 13); | |
8788 | tmp |= (5 << 13); | |
8789 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8790 | |
0ff066a9 PZ |
8791 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8792 | tmp &= ~(7 << 13); | |
8793 | tmp |= (5 << 13); | |
8794 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8795 | |
8796 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8797 | tmp &= ~0xFF; | |
8798 | tmp |= 0x1C; | |
8799 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8800 | ||
8801 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8802 | tmp &= ~0xFF; | |
8803 | tmp |= 0x1C; | |
8804 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8805 | ||
8806 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8807 | tmp &= ~(0xFF << 16); | |
8808 | tmp |= (0x1C << 16); | |
8809 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8810 | ||
8811 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8812 | tmp &= ~(0xFF << 16); | |
8813 | tmp |= (0x1C << 16); | |
8814 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8815 | ||
0ff066a9 PZ |
8816 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8817 | tmp |= (1 << 27); | |
8818 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8819 | |
0ff066a9 PZ |
8820 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8821 | tmp |= (1 << 27); | |
8822 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8823 | |
0ff066a9 PZ |
8824 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8825 | tmp &= ~(0xF << 28); | |
8826 | tmp |= (4 << 28); | |
8827 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8828 | |
0ff066a9 PZ |
8829 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8830 | tmp &= ~(0xF << 28); | |
8831 | tmp |= (4 << 28); | |
8832 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8833 | } |
8834 | ||
2fa86a1f PZ |
8835 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8836 | * Programming" based on the parameters passed: | |
8837 | * - Sequence to enable CLKOUT_DP | |
8838 | * - Sequence to enable CLKOUT_DP without spread | |
8839 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8840 | */ | |
8841 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8842 | bool with_fdi) | |
f31f2d55 | 8843 | { |
fac5e23e | 8844 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
8845 | uint32_t reg, tmp; |
8846 | ||
8847 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8848 | with_spread = true; | |
c2699524 | 8849 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8850 | with_fdi = false; |
f31f2d55 | 8851 | |
a580516d | 8852 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8853 | |
8854 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8855 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8856 | tmp |= SBI_SSCCTL_PATHALT; | |
8857 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8858 | ||
8859 | udelay(24); | |
8860 | ||
2fa86a1f PZ |
8861 | if (with_spread) { |
8862 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8863 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8864 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8865 | |
2fa86a1f PZ |
8866 | if (with_fdi) { |
8867 | lpt_reset_fdi_mphy(dev_priv); | |
8868 | lpt_program_fdi_mphy(dev_priv); | |
8869 | } | |
8870 | } | |
dde86e2d | 8871 | |
c2699524 | 8872 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8873 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8874 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8875 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8876 | |
a580516d | 8877 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8878 | } |
8879 | ||
47701c3b PZ |
8880 | /* Sequence to disable CLKOUT_DP */ |
8881 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8882 | { | |
fac5e23e | 8883 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
8884 | uint32_t reg, tmp; |
8885 | ||
a580516d | 8886 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8887 | |
c2699524 | 8888 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8889 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8890 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8891 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8892 | ||
8893 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8894 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8895 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8896 | tmp |= SBI_SSCCTL_PATHALT; | |
8897 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8898 | udelay(32); | |
8899 | } | |
8900 | tmp |= SBI_SSCCTL_DISABLE; | |
8901 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8902 | } | |
8903 | ||
a580516d | 8904 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8905 | } |
8906 | ||
f7be2c21 VS |
8907 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8908 | ||
8909 | static const uint16_t sscdivintphase[] = { | |
8910 | [BEND_IDX( 50)] = 0x3B23, | |
8911 | [BEND_IDX( 45)] = 0x3B23, | |
8912 | [BEND_IDX( 40)] = 0x3C23, | |
8913 | [BEND_IDX( 35)] = 0x3C23, | |
8914 | [BEND_IDX( 30)] = 0x3D23, | |
8915 | [BEND_IDX( 25)] = 0x3D23, | |
8916 | [BEND_IDX( 20)] = 0x3E23, | |
8917 | [BEND_IDX( 15)] = 0x3E23, | |
8918 | [BEND_IDX( 10)] = 0x3F23, | |
8919 | [BEND_IDX( 5)] = 0x3F23, | |
8920 | [BEND_IDX( 0)] = 0x0025, | |
8921 | [BEND_IDX( -5)] = 0x0025, | |
8922 | [BEND_IDX(-10)] = 0x0125, | |
8923 | [BEND_IDX(-15)] = 0x0125, | |
8924 | [BEND_IDX(-20)] = 0x0225, | |
8925 | [BEND_IDX(-25)] = 0x0225, | |
8926 | [BEND_IDX(-30)] = 0x0325, | |
8927 | [BEND_IDX(-35)] = 0x0325, | |
8928 | [BEND_IDX(-40)] = 0x0425, | |
8929 | [BEND_IDX(-45)] = 0x0425, | |
8930 | [BEND_IDX(-50)] = 0x0525, | |
8931 | }; | |
8932 | ||
8933 | /* | |
8934 | * Bend CLKOUT_DP | |
8935 | * steps -50 to 50 inclusive, in steps of 5 | |
8936 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8937 | * change in clock period = -(steps / 10) * 5.787 ps | |
8938 | */ | |
8939 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8940 | { | |
8941 | uint32_t tmp; | |
8942 | int idx = BEND_IDX(steps); | |
8943 | ||
8944 | if (WARN_ON(steps % 5 != 0)) | |
8945 | return; | |
8946 | ||
8947 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8948 | return; | |
8949 | ||
8950 | mutex_lock(&dev_priv->sb_lock); | |
8951 | ||
8952 | if (steps % 10 != 0) | |
8953 | tmp = 0xAAAAAAAB; | |
8954 | else | |
8955 | tmp = 0x00000000; | |
8956 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8957 | ||
8958 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8959 | tmp &= 0xffff0000; | |
8960 | tmp |= sscdivintphase[idx]; | |
8961 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8962 | ||
8963 | mutex_unlock(&dev_priv->sb_lock); | |
8964 | } | |
8965 | ||
8966 | #undef BEND_IDX | |
8967 | ||
bf8fa3d3 PZ |
8968 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8969 | { | |
bf8fa3d3 PZ |
8970 | struct intel_encoder *encoder; |
8971 | bool has_vga = false; | |
8972 | ||
b2784e15 | 8973 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8974 | switch (encoder->type) { |
8975 | case INTEL_OUTPUT_ANALOG: | |
8976 | has_vga = true; | |
8977 | break; | |
6847d71b PZ |
8978 | default: |
8979 | break; | |
bf8fa3d3 PZ |
8980 | } |
8981 | } | |
8982 | ||
f7be2c21 VS |
8983 | if (has_vga) { |
8984 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8985 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8986 | } else { |
47701c3b | 8987 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8988 | } |
bf8fa3d3 PZ |
8989 | } |
8990 | ||
dde86e2d PZ |
8991 | /* |
8992 | * Initialize reference clocks when the driver loads | |
8993 | */ | |
8994 | void intel_init_pch_refclk(struct drm_device *dev) | |
8995 | { | |
8996 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8997 | ironlake_init_pch_refclk(dev); | |
8998 | else if (HAS_PCH_LPT(dev)) | |
8999 | lpt_init_pch_refclk(dev); | |
9000 | } | |
9001 | ||
6ff93609 | 9002 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 9003 | { |
fac5e23e | 9004 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
9005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9006 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
9007 | uint32_t val; |
9008 | ||
78114071 | 9009 | val = 0; |
c8203565 | 9010 | |
6e3c9717 | 9011 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 9012 | case 18: |
dfd07d72 | 9013 | val |= PIPECONF_6BPC; |
c8203565 PZ |
9014 | break; |
9015 | case 24: | |
dfd07d72 | 9016 | val |= PIPECONF_8BPC; |
c8203565 PZ |
9017 | break; |
9018 | case 30: | |
dfd07d72 | 9019 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9020 | break; |
9021 | case 36: | |
dfd07d72 | 9022 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9023 | break; |
9024 | default: | |
cc769b62 PZ |
9025 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9026 | BUG(); | |
c8203565 PZ |
9027 | } |
9028 | ||
6e3c9717 | 9029 | if (intel_crtc->config->dither) |
c8203565 PZ |
9030 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9031 | ||
6e3c9717 | 9032 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9033 | val |= PIPECONF_INTERLACED_ILK; |
9034 | else | |
9035 | val |= PIPECONF_PROGRESSIVE; | |
9036 | ||
6e3c9717 | 9037 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9038 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9039 | |
c8203565 PZ |
9040 | I915_WRITE(PIPECONF(pipe), val); |
9041 | POSTING_READ(PIPECONF(pipe)); | |
9042 | } | |
9043 | ||
6ff93609 | 9044 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9045 | { |
fac5e23e | 9046 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9048 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9049 | u32 val = 0; |
ee2b0b38 | 9050 | |
391bf048 | 9051 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9052 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9053 | ||
6e3c9717 | 9054 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9055 | val |= PIPECONF_INTERLACED_ILK; |
9056 | else | |
9057 | val |= PIPECONF_PROGRESSIVE; | |
9058 | ||
702e7a56 PZ |
9059 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9060 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9061 | } |
9062 | ||
391bf048 JN |
9063 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9064 | { | |
fac5e23e | 9065 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9066 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9067 | |
391bf048 JN |
9068 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9069 | u32 val = 0; | |
756f85cf | 9070 | |
6e3c9717 | 9071 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9072 | case 18: |
9073 | val |= PIPEMISC_DITHER_6_BPC; | |
9074 | break; | |
9075 | case 24: | |
9076 | val |= PIPEMISC_DITHER_8_BPC; | |
9077 | break; | |
9078 | case 30: | |
9079 | val |= PIPEMISC_DITHER_10_BPC; | |
9080 | break; | |
9081 | case 36: | |
9082 | val |= PIPEMISC_DITHER_12_BPC; | |
9083 | break; | |
9084 | default: | |
9085 | /* Case prevented by pipe_config_set_bpp. */ | |
9086 | BUG(); | |
9087 | } | |
9088 | ||
6e3c9717 | 9089 | if (intel_crtc->config->dither) |
756f85cf PZ |
9090 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9091 | ||
391bf048 | 9092 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9093 | } |
ee2b0b38 PZ |
9094 | } |
9095 | ||
d4b1931c PZ |
9096 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9097 | { | |
9098 | /* | |
9099 | * Account for spread spectrum to avoid | |
9100 | * oversubscribing the link. Max center spread | |
9101 | * is 2.5%; use 5% for safety's sake. | |
9102 | */ | |
9103 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9104 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9105 | } |
9106 | ||
7429e9d4 | 9107 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9108 | { |
7429e9d4 | 9109 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9110 | } |
9111 | ||
b75ca6f6 ACO |
9112 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9113 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9114 | struct dpll *reduced_clock) |
79e53945 | 9115 | { |
de13a2e3 | 9116 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9117 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9118 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9119 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9120 | int factor; |
79e53945 | 9121 | |
c1858123 | 9122 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9123 | factor = 21; |
3d6e9ee0 | 9124 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9125 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9126 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 9127 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9128 | factor = 25; |
190f68c5 | 9129 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9130 | factor = 20; |
c1858123 | 9131 | |
b75ca6f6 ACO |
9132 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9133 | ||
190f68c5 | 9134 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9135 | fp |= FP_CB_TUNE; |
9136 | ||
9137 | if (reduced_clock) { | |
9138 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9139 | |
b75ca6f6 ACO |
9140 | if (reduced_clock->m < factor * reduced_clock->n) |
9141 | fp2 |= FP_CB_TUNE; | |
9142 | } else { | |
9143 | fp2 = fp; | |
9144 | } | |
9a7c7890 | 9145 | |
5eddb70b | 9146 | dpll = 0; |
2c07245f | 9147 | |
3d6e9ee0 | 9148 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9149 | dpll |= DPLLB_MODE_LVDS; |
9150 | else | |
9151 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9152 | |
190f68c5 | 9153 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9154 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9155 | |
3d6e9ee0 VS |
9156 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9157 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9158 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9159 | |
37a5650b | 9160 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9161 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9162 | |
a07d6787 | 9163 | /* compute bitmask from p1 value */ |
190f68c5 | 9164 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9165 | /* also FPA1 */ |
190f68c5 | 9166 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9167 | |
190f68c5 | 9168 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9169 | case 5: |
9170 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9171 | break; | |
9172 | case 7: | |
9173 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9174 | break; | |
9175 | case 10: | |
9176 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9177 | break; | |
9178 | case 14: | |
9179 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9180 | break; | |
79e53945 JB |
9181 | } |
9182 | ||
3d6e9ee0 VS |
9183 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9184 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9185 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9186 | else |
9187 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9188 | ||
b75ca6f6 ACO |
9189 | dpll |= DPLL_VCO_ENABLE; |
9190 | ||
9191 | crtc_state->dpll_hw_state.dpll = dpll; | |
9192 | crtc_state->dpll_hw_state.fp0 = fp; | |
9193 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9194 | } |
9195 | ||
190f68c5 ACO |
9196 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9197 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9198 | { |
997c030c | 9199 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9200 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9201 | struct dpll reduced_clock; |
7ed9f894 | 9202 | bool has_reduced_clock = false; |
e2b78267 | 9203 | struct intel_shared_dpll *pll; |
1b6f4958 | 9204 | const struct intel_limit *limit; |
997c030c | 9205 | int refclk = 120000; |
de13a2e3 | 9206 | |
dd3cd74a ACO |
9207 | memset(&crtc_state->dpll_hw_state, 0, |
9208 | sizeof(crtc_state->dpll_hw_state)); | |
9209 | ||
ded220e2 ACO |
9210 | crtc->lowfreq_avail = false; |
9211 | ||
9212 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9213 | if (!crtc_state->has_pch_encoder) | |
9214 | return 0; | |
79e53945 | 9215 | |
2d84d2b3 | 9216 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9217 | if (intel_panel_use_ssc(dev_priv)) { |
9218 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9219 | dev_priv->vbt.lvds_ssc_freq); | |
9220 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9221 | } | |
9222 | ||
9223 | if (intel_is_dual_link_lvds(dev)) { | |
9224 | if (refclk == 100000) | |
9225 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9226 | else | |
9227 | limit = &intel_limits_ironlake_dual_lvds; | |
9228 | } else { | |
9229 | if (refclk == 100000) | |
9230 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9231 | else | |
9232 | limit = &intel_limits_ironlake_single_lvds; | |
9233 | } | |
9234 | } else { | |
9235 | limit = &intel_limits_ironlake_dac; | |
9236 | } | |
9237 | ||
364ee29d | 9238 | if (!crtc_state->clock_set && |
997c030c ACO |
9239 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9240 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9241 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9242 | return -EINVAL; | |
f47709a9 | 9243 | } |
79e53945 | 9244 | |
b75ca6f6 ACO |
9245 | ironlake_compute_dpll(crtc, crtc_state, |
9246 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9247 | |
ded220e2 ACO |
9248 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9249 | if (pll == NULL) { | |
9250 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9251 | pipe_name(crtc->pipe)); | |
9252 | return -EINVAL; | |
3fb37703 | 9253 | } |
79e53945 | 9254 | |
2d84d2b3 | 9255 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9256 | has_reduced_clock) |
c7653199 | 9257 | crtc->lowfreq_avail = true; |
e2b78267 | 9258 | |
c8f7a0db | 9259 | return 0; |
79e53945 JB |
9260 | } |
9261 | ||
eb14cb74 VS |
9262 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9263 | struct intel_link_m_n *m_n) | |
9264 | { | |
9265 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9266 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9267 | enum pipe pipe = crtc->pipe; |
9268 | ||
9269 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9270 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9271 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9272 | & ~TU_SIZE_MASK; | |
9273 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9274 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9275 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9276 | } | |
9277 | ||
9278 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9279 | enum transcoder transcoder, | |
b95af8be VK |
9280 | struct intel_link_m_n *m_n, |
9281 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9282 | { |
9283 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9284 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9285 | enum pipe pipe = crtc->pipe; |
72419203 | 9286 | |
eb14cb74 VS |
9287 | if (INTEL_INFO(dev)->gen >= 5) { |
9288 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9289 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9290 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9291 | & ~TU_SIZE_MASK; | |
9292 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9293 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9294 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9295 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9296 | * gen < 8) and if DRRS is supported (to make sure the | |
9297 | * registers are not unnecessarily read). | |
9298 | */ | |
9299 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9300 | crtc->config->has_drrs) { |
b95af8be VK |
9301 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9302 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9303 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9304 | & ~TU_SIZE_MASK; | |
9305 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9306 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9307 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9308 | } | |
eb14cb74 VS |
9309 | } else { |
9310 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9311 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9312 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9313 | & ~TU_SIZE_MASK; | |
9314 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9315 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9316 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9317 | } | |
9318 | } | |
9319 | ||
9320 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9321 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9322 | { |
681a8504 | 9323 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9324 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9325 | else | |
9326 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9327 | &pipe_config->dp_m_n, |
9328 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9329 | } |
72419203 | 9330 | |
eb14cb74 | 9331 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9332 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9333 | { |
9334 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9335 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9336 | } |
9337 | ||
bd2e244f | 9338 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9339 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9340 | { |
9341 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9342 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9343 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9344 | uint32_t ps_ctrl = 0; | |
9345 | int id = -1; | |
9346 | int i; | |
bd2e244f | 9347 | |
a1b2278e CK |
9348 | /* find scaler attached to this pipe */ |
9349 | for (i = 0; i < crtc->num_scalers; i++) { | |
9350 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9351 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9352 | id = i; | |
9353 | pipe_config->pch_pfit.enabled = true; | |
9354 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9355 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9356 | break; | |
9357 | } | |
9358 | } | |
bd2e244f | 9359 | |
a1b2278e CK |
9360 | scaler_state->scaler_id = id; |
9361 | if (id >= 0) { | |
9362 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9363 | } else { | |
9364 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9365 | } |
9366 | } | |
9367 | ||
5724dbd1 DL |
9368 | static void |
9369 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9370 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9371 | { |
9372 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9373 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9374 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9375 | int pipe = crtc->pipe; |
9376 | int fourcc, pixel_format; | |
6761dd31 | 9377 | unsigned int aligned_height; |
bc8d7dff | 9378 | struct drm_framebuffer *fb; |
1b842c89 | 9379 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9380 | |
d9806c9f | 9381 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9382 | if (!intel_fb) { |
bc8d7dff DL |
9383 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9384 | return; | |
9385 | } | |
9386 | ||
1b842c89 DL |
9387 | fb = &intel_fb->base; |
9388 | ||
bc8d7dff | 9389 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9390 | if (!(val & PLANE_CTL_ENABLE)) |
9391 | goto error; | |
9392 | ||
bc8d7dff DL |
9393 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9394 | fourcc = skl_format_to_fourcc(pixel_format, | |
9395 | val & PLANE_CTL_ORDER_RGBX, | |
9396 | val & PLANE_CTL_ALPHA_MASK); | |
9397 | fb->pixel_format = fourcc; | |
9398 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9399 | ||
40f46283 DL |
9400 | tiling = val & PLANE_CTL_TILED_MASK; |
9401 | switch (tiling) { | |
9402 | case PLANE_CTL_TILED_LINEAR: | |
9403 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9404 | break; | |
9405 | case PLANE_CTL_TILED_X: | |
9406 | plane_config->tiling = I915_TILING_X; | |
9407 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9408 | break; | |
9409 | case PLANE_CTL_TILED_Y: | |
9410 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9411 | break; | |
9412 | case PLANE_CTL_TILED_YF: | |
9413 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9414 | break; | |
9415 | default: | |
9416 | MISSING_CASE(tiling); | |
9417 | goto error; | |
9418 | } | |
9419 | ||
bc8d7dff DL |
9420 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9421 | plane_config->base = base; | |
9422 | ||
9423 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9424 | ||
9425 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9426 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9427 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9428 | ||
9429 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9430 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9431 | fb->pixel_format); |
bc8d7dff DL |
9432 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9433 | ||
9434 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9435 | fb->pixel_format, |
9436 | fb->modifier[0]); | |
bc8d7dff | 9437 | |
f37b5c2b | 9438 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9439 | |
9440 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9441 | pipe_name(pipe), fb->width, fb->height, | |
9442 | fb->bits_per_pixel, base, fb->pitches[0], | |
9443 | plane_config->size); | |
9444 | ||
2d14030b | 9445 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9446 | return; |
9447 | ||
9448 | error: | |
9449 | kfree(fb); | |
9450 | } | |
9451 | ||
2fa2fe9a | 9452 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9453 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9454 | { |
9455 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9456 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9457 | uint32_t tmp; |
9458 | ||
9459 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9460 | ||
9461 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9462 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9463 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9464 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9465 | |
9466 | /* We currently do not free assignements of panel fitters on | |
9467 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9468 | * differentiates them) so just WARN about this case for now. */ | |
9469 | if (IS_GEN7(dev)) { | |
9470 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9471 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9472 | } | |
2fa2fe9a | 9473 | } |
79e53945 JB |
9474 | } |
9475 | ||
5724dbd1 DL |
9476 | static void |
9477 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9478 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9479 | { |
9480 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9481 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9482 | u32 val, base, offset; |
aeee5a49 | 9483 | int pipe = crtc->pipe; |
4c6baa59 | 9484 | int fourcc, pixel_format; |
6761dd31 | 9485 | unsigned int aligned_height; |
b113d5ee | 9486 | struct drm_framebuffer *fb; |
1b842c89 | 9487 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9488 | |
42a7b088 DL |
9489 | val = I915_READ(DSPCNTR(pipe)); |
9490 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9491 | return; | |
9492 | ||
d9806c9f | 9493 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9494 | if (!intel_fb) { |
4c6baa59 JB |
9495 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9496 | return; | |
9497 | } | |
9498 | ||
1b842c89 DL |
9499 | fb = &intel_fb->base; |
9500 | ||
18c5247e DV |
9501 | if (INTEL_INFO(dev)->gen >= 4) { |
9502 | if (val & DISPPLANE_TILED) { | |
49af449b | 9503 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9504 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9505 | } | |
9506 | } | |
4c6baa59 JB |
9507 | |
9508 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9509 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9510 | fb->pixel_format = fourcc; |
9511 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9512 | |
aeee5a49 | 9513 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9514 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9515 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9516 | } else { |
49af449b | 9517 | if (plane_config->tiling) |
aeee5a49 | 9518 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9519 | else |
aeee5a49 | 9520 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9521 | } |
9522 | plane_config->base = base; | |
9523 | ||
9524 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9525 | fb->width = ((val >> 16) & 0xfff) + 1; |
9526 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9527 | |
9528 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9529 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9530 | |
b113d5ee | 9531 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9532 | fb->pixel_format, |
9533 | fb->modifier[0]); | |
4c6baa59 | 9534 | |
f37b5c2b | 9535 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9536 | |
2844a921 DL |
9537 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9538 | pipe_name(pipe), fb->width, fb->height, | |
9539 | fb->bits_per_pixel, base, fb->pitches[0], | |
9540 | plane_config->size); | |
b113d5ee | 9541 | |
2d14030b | 9542 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9543 | } |
9544 | ||
0e8ffe1b | 9545 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9546 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9547 | { |
9548 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9549 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9550 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9551 | uint32_t tmp; |
1729050e | 9552 | bool ret; |
0e8ffe1b | 9553 | |
1729050e ID |
9554 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9555 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9556 | return false; |
9557 | ||
e143a21c | 9558 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9559 | pipe_config->shared_dpll = NULL; |
eccb140b | 9560 | |
1729050e | 9561 | ret = false; |
0e8ffe1b DV |
9562 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9563 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9564 | goto out; |
0e8ffe1b | 9565 | |
42571aef VS |
9566 | switch (tmp & PIPECONF_BPC_MASK) { |
9567 | case PIPECONF_6BPC: | |
9568 | pipe_config->pipe_bpp = 18; | |
9569 | break; | |
9570 | case PIPECONF_8BPC: | |
9571 | pipe_config->pipe_bpp = 24; | |
9572 | break; | |
9573 | case PIPECONF_10BPC: | |
9574 | pipe_config->pipe_bpp = 30; | |
9575 | break; | |
9576 | case PIPECONF_12BPC: | |
9577 | pipe_config->pipe_bpp = 36; | |
9578 | break; | |
9579 | default: | |
9580 | break; | |
9581 | } | |
9582 | ||
b5a9fa09 DV |
9583 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9584 | pipe_config->limited_color_range = true; | |
9585 | ||
ab9412ba | 9586 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9587 | struct intel_shared_dpll *pll; |
8106ddbd | 9588 | enum intel_dpll_id pll_id; |
66e985c0 | 9589 | |
88adfff1 DV |
9590 | pipe_config->has_pch_encoder = true; |
9591 | ||
627eb5a3 DV |
9592 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9593 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9594 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9595 | |
9596 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9597 | |
2d1fe073 | 9598 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9599 | /* |
9600 | * The pipe->pch transcoder and pch transcoder->pll | |
9601 | * mapping is fixed. | |
9602 | */ | |
8106ddbd | 9603 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9604 | } else { |
9605 | tmp = I915_READ(PCH_DPLL_SEL); | |
9606 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9607 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9608 | else |
8106ddbd | 9609 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9610 | } |
66e985c0 | 9611 | |
8106ddbd ACO |
9612 | pipe_config->shared_dpll = |
9613 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9614 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9615 | |
2edd6443 ACO |
9616 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9617 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9618 | |
9619 | tmp = pipe_config->dpll_hw_state.dpll; | |
9620 | pipe_config->pixel_multiplier = | |
9621 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9622 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9623 | |
9624 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9625 | } else { |
9626 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9627 | } |
9628 | ||
1bd1bd80 | 9629 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9630 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9631 | |
2fa2fe9a DV |
9632 | ironlake_get_pfit_config(crtc, pipe_config); |
9633 | ||
1729050e ID |
9634 | ret = true; |
9635 | ||
9636 | out: | |
9637 | intel_display_power_put(dev_priv, power_domain); | |
9638 | ||
9639 | return ret; | |
0e8ffe1b DV |
9640 | } |
9641 | ||
be256dc7 PZ |
9642 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9643 | { | |
91c8a326 | 9644 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 9645 | struct intel_crtc *crtc; |
be256dc7 | 9646 | |
d3fcc808 | 9647 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9648 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9649 | pipe_name(crtc->pipe)); |
9650 | ||
e2c719b7 RC |
9651 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9652 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9653 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9654 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 9655 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 9656 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 9657 | "CPU PWM1 enabled\n"); |
c5107b87 | 9658 | if (IS_HASWELL(dev)) |
e2c719b7 | 9659 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9660 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9661 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9662 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9663 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9664 | "Utility pin enabled\n"); |
e2c719b7 | 9665 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9666 | |
9926ada1 PZ |
9667 | /* |
9668 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9669 | * interrupts remain enabled. We used to check for that, but since it's | |
9670 | * gen-specific and since we only disable LCPLL after we fully disable | |
9671 | * the interrupts, the check below should be enough. | |
9672 | */ | |
e2c719b7 | 9673 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9674 | } |
9675 | ||
9ccd5aeb PZ |
9676 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9677 | { | |
91c8a326 | 9678 | struct drm_device *dev = &dev_priv->drm; |
9ccd5aeb PZ |
9679 | |
9680 | if (IS_HASWELL(dev)) | |
9681 | return I915_READ(D_COMP_HSW); | |
9682 | else | |
9683 | return I915_READ(D_COMP_BDW); | |
9684 | } | |
9685 | ||
3c4c9b81 PZ |
9686 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9687 | { | |
91c8a326 | 9688 | struct drm_device *dev = &dev_priv->drm; |
3c4c9b81 PZ |
9689 | |
9690 | if (IS_HASWELL(dev)) { | |
9691 | mutex_lock(&dev_priv->rps.hw_lock); | |
9692 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9693 | val)) | |
f475dadf | 9694 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9695 | mutex_unlock(&dev_priv->rps.hw_lock); |
9696 | } else { | |
9ccd5aeb PZ |
9697 | I915_WRITE(D_COMP_BDW, val); |
9698 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9699 | } |
be256dc7 PZ |
9700 | } |
9701 | ||
9702 | /* | |
9703 | * This function implements pieces of two sequences from BSpec: | |
9704 | * - Sequence for display software to disable LCPLL | |
9705 | * - Sequence for display software to allow package C8+ | |
9706 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9707 | * register. Callers should take care of disabling all the display engine | |
9708 | * functions, doing the mode unset, fixing interrupts, etc. | |
9709 | */ | |
6ff58d53 PZ |
9710 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9711 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9712 | { |
9713 | uint32_t val; | |
9714 | ||
9715 | assert_can_disable_lcpll(dev_priv); | |
9716 | ||
9717 | val = I915_READ(LCPLL_CTL); | |
9718 | ||
9719 | if (switch_to_fclk) { | |
9720 | val |= LCPLL_CD_SOURCE_FCLK; | |
9721 | I915_WRITE(LCPLL_CTL, val); | |
9722 | ||
f53dd63f ID |
9723 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9724 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
9725 | DRM_ERROR("Switching to FCLK failed\n"); |
9726 | ||
9727 | val = I915_READ(LCPLL_CTL); | |
9728 | } | |
9729 | ||
9730 | val |= LCPLL_PLL_DISABLE; | |
9731 | I915_WRITE(LCPLL_CTL, val); | |
9732 | POSTING_READ(LCPLL_CTL); | |
9733 | ||
24d8441d | 9734 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
9735 | DRM_ERROR("LCPLL still locked\n"); |
9736 | ||
9ccd5aeb | 9737 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9738 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9739 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9740 | ndelay(100); |
9741 | ||
9ccd5aeb PZ |
9742 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9743 | 1)) | |
be256dc7 PZ |
9744 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9745 | ||
9746 | if (allow_power_down) { | |
9747 | val = I915_READ(LCPLL_CTL); | |
9748 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9749 | I915_WRITE(LCPLL_CTL, val); | |
9750 | POSTING_READ(LCPLL_CTL); | |
9751 | } | |
9752 | } | |
9753 | ||
9754 | /* | |
9755 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9756 | * source. | |
9757 | */ | |
6ff58d53 | 9758 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9759 | { |
9760 | uint32_t val; | |
9761 | ||
9762 | val = I915_READ(LCPLL_CTL); | |
9763 | ||
9764 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9765 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9766 | return; | |
9767 | ||
a8a8bd54 PZ |
9768 | /* |
9769 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9770 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9771 | */ |
59bad947 | 9772 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9773 | |
be256dc7 PZ |
9774 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9775 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9776 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9777 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9778 | } |
9779 | ||
9ccd5aeb | 9780 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9781 | val |= D_COMP_COMP_FORCE; |
9782 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9783 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9784 | |
9785 | val = I915_READ(LCPLL_CTL); | |
9786 | val &= ~LCPLL_PLL_DISABLE; | |
9787 | I915_WRITE(LCPLL_CTL, val); | |
9788 | ||
93220c08 CW |
9789 | if (intel_wait_for_register(dev_priv, |
9790 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
9791 | 5)) | |
be256dc7 PZ |
9792 | DRM_ERROR("LCPLL not locked yet\n"); |
9793 | ||
9794 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9795 | val = I915_READ(LCPLL_CTL); | |
9796 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9797 | I915_WRITE(LCPLL_CTL, val); | |
9798 | ||
f53dd63f ID |
9799 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9800 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
9801 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9802 | } | |
215733fa | 9803 | |
59bad947 | 9804 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
91c8a326 | 9805 | intel_update_cdclk(&dev_priv->drm); |
be256dc7 PZ |
9806 | } |
9807 | ||
765dab67 PZ |
9808 | /* |
9809 | * Package states C8 and deeper are really deep PC states that can only be | |
9810 | * reached when all the devices on the system allow it, so even if the graphics | |
9811 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9812 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9813 | * | |
9814 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9815 | * well is disabled and most interrupts are disabled, and these are also | |
9816 | * requirements for runtime PM. When these conditions are met, we manually do | |
9817 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9818 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9819 | * hang the machine. | |
9820 | * | |
9821 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9822 | * the state of some registers, so when we come back from PC8+ we need to | |
9823 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9824 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9825 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9826 | * because of the runtime PM support). | |
9827 | * | |
9828 | * For more, read "Display Sequences for Package C8" on the hardware | |
9829 | * documentation. | |
9830 | */ | |
a14cb6fc | 9831 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9832 | { |
91c8a326 | 9833 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9834 | uint32_t val; |
9835 | ||
c67a470b PZ |
9836 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9837 | ||
c2699524 | 9838 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9839 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9840 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9841 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9842 | } | |
9843 | ||
9844 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9845 | hsw_disable_lcpll(dev_priv, true, true); |
9846 | } | |
9847 | ||
a14cb6fc | 9848 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9849 | { |
91c8a326 | 9850 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9851 | uint32_t val; |
9852 | ||
c67a470b PZ |
9853 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9854 | ||
9855 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9856 | lpt_init_pch_refclk(dev); |
9857 | ||
c2699524 | 9858 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9859 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9860 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9861 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9862 | } | |
c67a470b PZ |
9863 | } |
9864 | ||
324513c0 | 9865 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9866 | { |
a821fc46 | 9867 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9868 | struct intel_atomic_state *old_intel_state = |
9869 | to_intel_atomic_state(old_state); | |
9870 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9871 | |
324513c0 | 9872 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9873 | } |
9874 | ||
b432e5cf | 9875 | /* compute the max rate for new configuration */ |
27c329ed | 9876 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9877 | { |
565602d7 | 9878 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 9879 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
9880 | struct drm_crtc *crtc; |
9881 | struct drm_crtc_state *cstate; | |
27c329ed | 9882 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9883 | unsigned max_pixel_rate = 0, i; |
9884 | enum pipe pipe; | |
b432e5cf | 9885 | |
565602d7 ML |
9886 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9887 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9888 | |
565602d7 ML |
9889 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9890 | int pixel_rate; | |
27c329ed | 9891 | |
565602d7 ML |
9892 | crtc_state = to_intel_crtc_state(cstate); |
9893 | if (!crtc_state->base.enable) { | |
9894 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9895 | continue; |
565602d7 | 9896 | } |
b432e5cf | 9897 | |
27c329ed | 9898 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9899 | |
9900 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9901 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9902 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9903 | ||
565602d7 | 9904 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9905 | } |
9906 | ||
565602d7 ML |
9907 | for_each_pipe(dev_priv, pipe) |
9908 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9909 | ||
b432e5cf VS |
9910 | return max_pixel_rate; |
9911 | } | |
9912 | ||
9913 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9914 | { | |
fac5e23e | 9915 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
9916 | uint32_t val, data; |
9917 | int ret; | |
9918 | ||
9919 | if (WARN((I915_READ(LCPLL_CTL) & | |
9920 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9921 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9922 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9923 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9924 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9925 | return; | |
9926 | ||
9927 | mutex_lock(&dev_priv->rps.hw_lock); | |
9928 | ret = sandybridge_pcode_write(dev_priv, | |
9929 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9930 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9931 | if (ret) { | |
9932 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9933 | return; | |
9934 | } | |
9935 | ||
9936 | val = I915_READ(LCPLL_CTL); | |
9937 | val |= LCPLL_CD_SOURCE_FCLK; | |
9938 | I915_WRITE(LCPLL_CTL, val); | |
9939 | ||
5ba00178 TU |
9940 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9941 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9942 | DRM_ERROR("Switching to FCLK failed\n"); |
9943 | ||
9944 | val = I915_READ(LCPLL_CTL); | |
9945 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9946 | ||
9947 | switch (cdclk) { | |
9948 | case 450000: | |
9949 | val |= LCPLL_CLK_FREQ_450; | |
9950 | data = 0; | |
9951 | break; | |
9952 | case 540000: | |
9953 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9954 | data = 1; | |
9955 | break; | |
9956 | case 337500: | |
9957 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9958 | data = 2; | |
9959 | break; | |
9960 | case 675000: | |
9961 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9962 | data = 3; | |
9963 | break; | |
9964 | default: | |
9965 | WARN(1, "invalid cdclk frequency\n"); | |
9966 | return; | |
9967 | } | |
9968 | ||
9969 | I915_WRITE(LCPLL_CTL, val); | |
9970 | ||
9971 | val = I915_READ(LCPLL_CTL); | |
9972 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9973 | I915_WRITE(LCPLL_CTL, val); | |
9974 | ||
5ba00178 TU |
9975 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9976 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9977 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9978 | ||
9979 | mutex_lock(&dev_priv->rps.hw_lock); | |
9980 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9981 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9982 | ||
7f1052a8 VS |
9983 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9984 | ||
b432e5cf VS |
9985 | intel_update_cdclk(dev); |
9986 | ||
9987 | WARN(cdclk != dev_priv->cdclk_freq, | |
9988 | "cdclk requested %d kHz but got %d kHz\n", | |
9989 | cdclk, dev_priv->cdclk_freq); | |
9990 | } | |
9991 | ||
587c7914 VS |
9992 | static int broadwell_calc_cdclk(int max_pixclk) |
9993 | { | |
9994 | if (max_pixclk > 540000) | |
9995 | return 675000; | |
9996 | else if (max_pixclk > 450000) | |
9997 | return 540000; | |
9998 | else if (max_pixclk > 337500) | |
9999 | return 450000; | |
10000 | else | |
10001 | return 337500; | |
10002 | } | |
10003 | ||
27c329ed | 10004 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 10005 | { |
27c329ed | 10006 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 10007 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 10008 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
10009 | int cdclk; |
10010 | ||
10011 | /* | |
10012 | * FIXME should also account for plane ratio | |
10013 | * once 64bpp pixel formats are supported. | |
10014 | */ | |
587c7914 | 10015 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 10016 | |
b432e5cf | 10017 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
10018 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
10019 | cdclk, dev_priv->max_cdclk_freq); | |
10020 | return -EINVAL; | |
b432e5cf VS |
10021 | } |
10022 | ||
1a617b77 ML |
10023 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10024 | if (!intel_state->active_crtcs) | |
587c7914 | 10025 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10026 | |
10027 | return 0; | |
10028 | } | |
10029 | ||
27c329ed | 10030 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10031 | { |
27c329ed | 10032 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10033 | struct intel_atomic_state *old_intel_state = |
10034 | to_intel_atomic_state(old_state); | |
10035 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10036 | |
27c329ed | 10037 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10038 | } |
10039 | ||
c89e39f3 CT |
10040 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10041 | { | |
10042 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10043 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10044 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10045 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10046 | int cdclk; |
10047 | ||
10048 | /* | |
10049 | * FIXME should also account for plane ratio | |
10050 | * once 64bpp pixel formats are supported. | |
10051 | */ | |
a8ca4934 | 10052 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10053 | |
10054 | /* | |
10055 | * FIXME move the cdclk caclulation to | |
10056 | * compute_config() so we can fail gracegully. | |
10057 | */ | |
10058 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10059 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10060 | cdclk, dev_priv->max_cdclk_freq); | |
10061 | cdclk = dev_priv->max_cdclk_freq; | |
10062 | } | |
10063 | ||
10064 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10065 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10066 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10067 | |
10068 | return 0; | |
10069 | } | |
10070 | ||
10071 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10072 | { | |
1cd593e0 VS |
10073 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10074 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10075 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10076 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10077 | |
1cd593e0 | 10078 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10079 | } |
10080 | ||
190f68c5 ACO |
10081 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10082 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10083 | { |
d7edc4e5 | 10084 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10085 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10086 | return -EINVAL; | |
10087 | } | |
716c2e55 | 10088 | |
c7653199 | 10089 | crtc->lowfreq_avail = false; |
644cef34 | 10090 | |
c8f7a0db | 10091 | return 0; |
79e53945 JB |
10092 | } |
10093 | ||
3760b59c S |
10094 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10095 | enum port port, | |
10096 | struct intel_crtc_state *pipe_config) | |
10097 | { | |
8106ddbd ACO |
10098 | enum intel_dpll_id id; |
10099 | ||
3760b59c S |
10100 | switch (port) { |
10101 | case PORT_A: | |
10102 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 10103 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10104 | break; |
10105 | case PORT_B: | |
10106 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 10107 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10108 | break; |
10109 | case PORT_C: | |
10110 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 10111 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10112 | break; |
10113 | default: | |
10114 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10115 | return; |
3760b59c | 10116 | } |
8106ddbd ACO |
10117 | |
10118 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10119 | } |
10120 | ||
96b7dfb7 S |
10121 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10122 | enum port port, | |
5cec258b | 10123 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10124 | { |
8106ddbd | 10125 | enum intel_dpll_id id; |
a3c988ea | 10126 | u32 temp; |
96b7dfb7 S |
10127 | |
10128 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
10129 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
10130 | ||
10131 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 10132 | case SKL_DPLL0: |
a3c988ea ACO |
10133 | id = DPLL_ID_SKL_DPLL0; |
10134 | break; | |
96b7dfb7 | 10135 | case SKL_DPLL1: |
8106ddbd | 10136 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
10137 | break; |
10138 | case SKL_DPLL2: | |
8106ddbd | 10139 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
10140 | break; |
10141 | case SKL_DPLL3: | |
8106ddbd | 10142 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 10143 | break; |
8106ddbd ACO |
10144 | default: |
10145 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10146 | return; | |
96b7dfb7 | 10147 | } |
8106ddbd ACO |
10148 | |
10149 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10150 | } |
10151 | ||
7d2c8175 DL |
10152 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10153 | enum port port, | |
5cec258b | 10154 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10155 | { |
8106ddbd ACO |
10156 | enum intel_dpll_id id; |
10157 | ||
7d2c8175 DL |
10158 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
10159 | ||
10160 | switch (pipe_config->ddi_pll_sel) { | |
10161 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 10162 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10163 | break; |
10164 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10165 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10166 | break; |
00490c22 | 10167 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10168 | id = DPLL_ID_SPLL; |
79bd23da | 10169 | break; |
9d16da65 ACO |
10170 | case PORT_CLK_SEL_LCPLL_810: |
10171 | id = DPLL_ID_LCPLL_810; | |
10172 | break; | |
10173 | case PORT_CLK_SEL_LCPLL_1350: | |
10174 | id = DPLL_ID_LCPLL_1350; | |
10175 | break; | |
10176 | case PORT_CLK_SEL_LCPLL_2700: | |
10177 | id = DPLL_ID_LCPLL_2700; | |
10178 | break; | |
8106ddbd ACO |
10179 | default: |
10180 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10181 | /* fall through */ | |
10182 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10183 | return; |
7d2c8175 | 10184 | } |
8106ddbd ACO |
10185 | |
10186 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10187 | } |
10188 | ||
cf30429e JN |
10189 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10190 | struct intel_crtc_state *pipe_config, | |
10191 | unsigned long *power_domain_mask) | |
10192 | { | |
10193 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10194 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10195 | enum intel_display_power_domain power_domain; |
10196 | u32 tmp; | |
10197 | ||
d9a7bc67 ID |
10198 | /* |
10199 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10200 | * transcoder handled below. | |
10201 | */ | |
cf30429e JN |
10202 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10203 | ||
10204 | /* | |
10205 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10206 | * consistency and less surprising code; it's in always on power). | |
10207 | */ | |
10208 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10209 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10210 | enum pipe trans_edp_pipe; | |
10211 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10212 | default: | |
10213 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10214 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10215 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10216 | trans_edp_pipe = PIPE_A; | |
10217 | break; | |
10218 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10219 | trans_edp_pipe = PIPE_B; | |
10220 | break; | |
10221 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10222 | trans_edp_pipe = PIPE_C; | |
10223 | break; | |
10224 | } | |
10225 | ||
10226 | if (trans_edp_pipe == crtc->pipe) | |
10227 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10228 | } | |
10229 | ||
10230 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10231 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10232 | return false; | |
10233 | *power_domain_mask |= BIT(power_domain); | |
10234 | ||
10235 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10236 | ||
10237 | return tmp & PIPECONF_ENABLE; | |
10238 | } | |
10239 | ||
4d1de975 JN |
10240 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10241 | struct intel_crtc_state *pipe_config, | |
10242 | unsigned long *power_domain_mask) | |
10243 | { | |
10244 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10245 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10246 | enum intel_display_power_domain power_domain; |
10247 | enum port port; | |
10248 | enum transcoder cpu_transcoder; | |
10249 | u32 tmp; | |
10250 | ||
4d1de975 JN |
10251 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10252 | if (port == PORT_A) | |
10253 | cpu_transcoder = TRANSCODER_DSI_A; | |
10254 | else | |
10255 | cpu_transcoder = TRANSCODER_DSI_C; | |
10256 | ||
10257 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10258 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10259 | continue; | |
10260 | *power_domain_mask |= BIT(power_domain); | |
10261 | ||
db18b6a6 ID |
10262 | /* |
10263 | * The PLL needs to be enabled with a valid divider | |
10264 | * configuration, otherwise accessing DSI registers will hang | |
10265 | * the machine. See BSpec North Display Engine | |
10266 | * registers/MIPI[BXT]. We can break out here early, since we | |
10267 | * need the same DSI PLL to be enabled for both DSI ports. | |
10268 | */ | |
10269 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10270 | break; | |
10271 | ||
4d1de975 JN |
10272 | /* XXX: this works for video mode only */ |
10273 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10274 | if (!(tmp & DPI_ENABLE)) | |
10275 | continue; | |
10276 | ||
10277 | tmp = I915_READ(MIPI_CTRL(port)); | |
10278 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10279 | continue; | |
10280 | ||
10281 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10282 | break; |
10283 | } | |
10284 | ||
d7edc4e5 | 10285 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10286 | } |
10287 | ||
26804afd | 10288 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10289 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10290 | { |
10291 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10292 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10293 | struct intel_shared_dpll *pll; |
26804afd DV |
10294 | enum port port; |
10295 | uint32_t tmp; | |
10296 | ||
10297 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10298 | ||
10299 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10300 | ||
ef11bdb3 | 10301 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10302 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10303 | else if (IS_BROXTON(dev)) |
10304 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10305 | else |
10306 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10307 | |
8106ddbd ACO |
10308 | pll = pipe_config->shared_dpll; |
10309 | if (pll) { | |
2edd6443 ACO |
10310 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10311 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10312 | } |
10313 | ||
26804afd DV |
10314 | /* |
10315 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10316 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10317 | * the PCH transcoder is on. | |
10318 | */ | |
ca370455 DL |
10319 | if (INTEL_INFO(dev)->gen < 9 && |
10320 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10321 | pipe_config->has_pch_encoder = true; |
10322 | ||
10323 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10324 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10325 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10326 | ||
10327 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10328 | } | |
10329 | } | |
10330 | ||
0e8ffe1b | 10331 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10332 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10333 | { |
10334 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10335 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10336 | enum intel_display_power_domain power_domain; |
10337 | unsigned long power_domain_mask; | |
cf30429e | 10338 | bool active; |
0e8ffe1b | 10339 | |
1729050e ID |
10340 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10341 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10342 | return false; |
1729050e ID |
10343 | power_domain_mask = BIT(power_domain); |
10344 | ||
8106ddbd | 10345 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10346 | |
cf30429e | 10347 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10348 | |
d7edc4e5 VS |
10349 | if (IS_BROXTON(dev_priv) && |
10350 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10351 | WARN_ON(active); | |
10352 | active = true; | |
4d1de975 JN |
10353 | } |
10354 | ||
cf30429e | 10355 | if (!active) |
1729050e | 10356 | goto out; |
0e8ffe1b | 10357 | |
d7edc4e5 | 10358 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10359 | haswell_get_ddi_port_state(crtc, pipe_config); |
10360 | intel_get_pipe_timings(crtc, pipe_config); | |
10361 | } | |
627eb5a3 | 10362 | |
bc58be60 | 10363 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10364 | |
05dc698c LL |
10365 | pipe_config->gamma_mode = |
10366 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10367 | ||
a1b2278e CK |
10368 | if (INTEL_INFO(dev)->gen >= 9) { |
10369 | skl_init_scalers(dev, crtc, pipe_config); | |
10370 | } | |
10371 | ||
af99ceda CK |
10372 | if (INTEL_INFO(dev)->gen >= 9) { |
10373 | pipe_config->scaler_state.scaler_id = -1; | |
10374 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10375 | } | |
10376 | ||
1729050e ID |
10377 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10378 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10379 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10380 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10381 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10382 | else |
1c132b44 | 10383 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10384 | } |
88adfff1 | 10385 | |
e59150dc JB |
10386 | if (IS_HASWELL(dev)) |
10387 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10388 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10389 | |
4d1de975 JN |
10390 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10391 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10392 | pipe_config->pixel_multiplier = |
10393 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10394 | } else { | |
10395 | pipe_config->pixel_multiplier = 1; | |
10396 | } | |
6c49f241 | 10397 | |
1729050e ID |
10398 | out: |
10399 | for_each_power_domain(power_domain, power_domain_mask) | |
10400 | intel_display_power_put(dev_priv, power_domain); | |
10401 | ||
cf30429e | 10402 | return active; |
0e8ffe1b DV |
10403 | } |
10404 | ||
55a08b3f ML |
10405 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10406 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10407 | { |
10408 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10409 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10411 | uint32_t cntl = 0, size = 0; |
560b85bb | 10412 | |
55a08b3f ML |
10413 | if (plane_state && plane_state->visible) { |
10414 | unsigned int width = plane_state->base.crtc_w; | |
10415 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10416 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10417 | ||
10418 | switch (stride) { | |
10419 | default: | |
10420 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10421 | width, stride); | |
10422 | stride = 256; | |
10423 | /* fallthrough */ | |
10424 | case 256: | |
10425 | case 512: | |
10426 | case 1024: | |
10427 | case 2048: | |
10428 | break; | |
4b0e333e CW |
10429 | } |
10430 | ||
dc41c154 VS |
10431 | cntl |= CURSOR_ENABLE | |
10432 | CURSOR_GAMMA_ENABLE | | |
10433 | CURSOR_FORMAT_ARGB | | |
10434 | CURSOR_STRIDE(stride); | |
10435 | ||
10436 | size = (height << 12) | width; | |
4b0e333e | 10437 | } |
560b85bb | 10438 | |
dc41c154 VS |
10439 | if (intel_crtc->cursor_cntl != 0 && |
10440 | (intel_crtc->cursor_base != base || | |
10441 | intel_crtc->cursor_size != size || | |
10442 | intel_crtc->cursor_cntl != cntl)) { | |
10443 | /* On these chipsets we can only modify the base/size/stride | |
10444 | * whilst the cursor is disabled. | |
10445 | */ | |
0b87c24e VS |
10446 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10447 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10448 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10449 | } |
560b85bb | 10450 | |
99d1f387 | 10451 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10452 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10453 | intel_crtc->cursor_base = base; |
10454 | } | |
4726e0b0 | 10455 | |
dc41c154 VS |
10456 | if (intel_crtc->cursor_size != size) { |
10457 | I915_WRITE(CURSIZE, size); | |
10458 | intel_crtc->cursor_size = size; | |
4b0e333e | 10459 | } |
560b85bb | 10460 | |
4b0e333e | 10461 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10462 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10463 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10464 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10465 | } |
560b85bb CW |
10466 | } |
10467 | ||
55a08b3f ML |
10468 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10469 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10470 | { |
10471 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10472 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10473 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10474 | int pipe = intel_crtc->pipe; | |
663f3122 | 10475 | uint32_t cntl = 0; |
4b0e333e | 10476 | |
55a08b3f | 10477 | if (plane_state && plane_state->visible) { |
4b0e333e | 10478 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10479 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10480 | case 64: |
10481 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10482 | break; | |
10483 | case 128: | |
10484 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10485 | break; | |
10486 | case 256: | |
10487 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10488 | break; | |
10489 | default: | |
55a08b3f | 10490 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10491 | return; |
65a21cd6 | 10492 | } |
4b0e333e | 10493 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10494 | |
fc6f93bc | 10495 | if (HAS_DDI(dev)) |
47bf17a7 | 10496 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10497 | |
55a08b3f ML |
10498 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10499 | cntl |= CURSOR_ROTATE_180; | |
10500 | } | |
4398ad45 | 10501 | |
4b0e333e CW |
10502 | if (intel_crtc->cursor_cntl != cntl) { |
10503 | I915_WRITE(CURCNTR(pipe), cntl); | |
10504 | POSTING_READ(CURCNTR(pipe)); | |
10505 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10506 | } |
4b0e333e | 10507 | |
65a21cd6 | 10508 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10509 | I915_WRITE(CURBASE(pipe), base); |
10510 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10511 | |
10512 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10513 | } |
10514 | ||
cda4b7d3 | 10515 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10516 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10517 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10518 | { |
10519 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10520 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10522 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10523 | u32 base = intel_crtc->cursor_addr; |
10524 | u32 pos = 0; | |
cda4b7d3 | 10525 | |
55a08b3f ML |
10526 | if (plane_state) { |
10527 | int x = plane_state->base.crtc_x; | |
10528 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10529 | |
55a08b3f ML |
10530 | if (x < 0) { |
10531 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10532 | x = -x; | |
10533 | } | |
10534 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10535 | |
55a08b3f ML |
10536 | if (y < 0) { |
10537 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10538 | y = -y; | |
10539 | } | |
10540 | pos |= y << CURSOR_Y_SHIFT; | |
10541 | ||
10542 | /* ILK+ do this automagically */ | |
10543 | if (HAS_GMCH_DISPLAY(dev) && | |
10544 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10545 | base += (plane_state->base.crtc_h * | |
10546 | plane_state->base.crtc_w - 1) * 4; | |
10547 | } | |
cda4b7d3 | 10548 | } |
cda4b7d3 | 10549 | |
5efb3e28 VS |
10550 | I915_WRITE(CURPOS(pipe), pos); |
10551 | ||
8ac54669 | 10552 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10553 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10554 | else |
55a08b3f | 10555 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10556 | } |
10557 | ||
dc41c154 VS |
10558 | static bool cursor_size_ok(struct drm_device *dev, |
10559 | uint32_t width, uint32_t height) | |
10560 | { | |
10561 | if (width == 0 || height == 0) | |
10562 | return false; | |
10563 | ||
10564 | /* | |
10565 | * 845g/865g are special in that they are only limited by | |
10566 | * the width of their cursors, the height is arbitrary up to | |
10567 | * the precision of the register. Everything else requires | |
10568 | * square cursors, limited to a few power-of-two sizes. | |
10569 | */ | |
10570 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10571 | if ((width & 63) != 0) | |
10572 | return false; | |
10573 | ||
10574 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10575 | return false; | |
10576 | ||
10577 | if (height > 1023) | |
10578 | return false; | |
10579 | } else { | |
10580 | switch (width | height) { | |
10581 | case 256: | |
10582 | case 128: | |
10583 | if (IS_GEN2(dev)) | |
10584 | return false; | |
10585 | case 64: | |
10586 | break; | |
10587 | default: | |
10588 | return false; | |
10589 | } | |
10590 | } | |
10591 | ||
10592 | return true; | |
10593 | } | |
10594 | ||
79e53945 JB |
10595 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10596 | static struct drm_display_mode load_detect_mode = { | |
10597 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10598 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10599 | }; | |
10600 | ||
a8bb6818 DV |
10601 | struct drm_framebuffer * |
10602 | __intel_framebuffer_create(struct drm_device *dev, | |
10603 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10604 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10605 | { |
10606 | struct intel_framebuffer *intel_fb; | |
10607 | int ret; | |
10608 | ||
10609 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10610 | if (!intel_fb) |
d2dff872 | 10611 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10612 | |
10613 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10614 | if (ret) |
10615 | goto err; | |
d2dff872 CW |
10616 | |
10617 | return &intel_fb->base; | |
dcb1394e | 10618 | |
dd4916c5 | 10619 | err: |
dd4916c5 | 10620 | kfree(intel_fb); |
dd4916c5 | 10621 | return ERR_PTR(ret); |
d2dff872 CW |
10622 | } |
10623 | ||
b5ea642a | 10624 | static struct drm_framebuffer * |
a8bb6818 DV |
10625 | intel_framebuffer_create(struct drm_device *dev, |
10626 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10627 | struct drm_i915_gem_object *obj) | |
10628 | { | |
10629 | struct drm_framebuffer *fb; | |
10630 | int ret; | |
10631 | ||
10632 | ret = i915_mutex_lock_interruptible(dev); | |
10633 | if (ret) | |
10634 | return ERR_PTR(ret); | |
10635 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10636 | mutex_unlock(&dev->struct_mutex); | |
10637 | ||
10638 | return fb; | |
10639 | } | |
10640 | ||
d2dff872 CW |
10641 | static u32 |
10642 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10643 | { | |
10644 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10645 | return ALIGN(pitch, 64); | |
10646 | } | |
10647 | ||
10648 | static u32 | |
10649 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10650 | { | |
10651 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10652 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10653 | } |
10654 | ||
10655 | static struct drm_framebuffer * | |
10656 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10657 | struct drm_display_mode *mode, | |
10658 | int depth, int bpp) | |
10659 | { | |
dcb1394e | 10660 | struct drm_framebuffer *fb; |
d2dff872 | 10661 | struct drm_i915_gem_object *obj; |
0fed39bd | 10662 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10663 | |
d37cd8a8 | 10664 | obj = i915_gem_object_create(dev, |
d2dff872 | 10665 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10666 | if (IS_ERR(obj)) |
10667 | return ERR_CAST(obj); | |
d2dff872 CW |
10668 | |
10669 | mode_cmd.width = mode->hdisplay; | |
10670 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10671 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10672 | bpp); | |
5ca0c34a | 10673 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10674 | |
dcb1394e LW |
10675 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10676 | if (IS_ERR(fb)) | |
34911fd3 | 10677 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
10678 | |
10679 | return fb; | |
d2dff872 CW |
10680 | } |
10681 | ||
10682 | static struct drm_framebuffer * | |
10683 | mode_fits_in_fbdev(struct drm_device *dev, | |
10684 | struct drm_display_mode *mode) | |
10685 | { | |
0695726e | 10686 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 10687 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
10688 | struct drm_i915_gem_object *obj; |
10689 | struct drm_framebuffer *fb; | |
10690 | ||
4c0e5528 | 10691 | if (!dev_priv->fbdev) |
d2dff872 CW |
10692 | return NULL; |
10693 | ||
4c0e5528 | 10694 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10695 | return NULL; |
10696 | ||
4c0e5528 DV |
10697 | obj = dev_priv->fbdev->fb->obj; |
10698 | BUG_ON(!obj); | |
10699 | ||
8bcd4553 | 10700 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10701 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10702 | fb->bits_per_pixel)) | |
d2dff872 CW |
10703 | return NULL; |
10704 | ||
01f2c773 | 10705 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10706 | return NULL; |
10707 | ||
edde3617 | 10708 | drm_framebuffer_reference(fb); |
d2dff872 | 10709 | return fb; |
4520f53a DV |
10710 | #else |
10711 | return NULL; | |
10712 | #endif | |
d2dff872 CW |
10713 | } |
10714 | ||
d3a40d1b ACO |
10715 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10716 | struct drm_crtc *crtc, | |
10717 | struct drm_display_mode *mode, | |
10718 | struct drm_framebuffer *fb, | |
10719 | int x, int y) | |
10720 | { | |
10721 | struct drm_plane_state *plane_state; | |
10722 | int hdisplay, vdisplay; | |
10723 | int ret; | |
10724 | ||
10725 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10726 | if (IS_ERR(plane_state)) | |
10727 | return PTR_ERR(plane_state); | |
10728 | ||
10729 | if (mode) | |
10730 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10731 | else | |
10732 | hdisplay = vdisplay = 0; | |
10733 | ||
10734 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10735 | if (ret) | |
10736 | return ret; | |
10737 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10738 | plane_state->crtc_x = 0; | |
10739 | plane_state->crtc_y = 0; | |
10740 | plane_state->crtc_w = hdisplay; | |
10741 | plane_state->crtc_h = vdisplay; | |
10742 | plane_state->src_x = x << 16; | |
10743 | plane_state->src_y = y << 16; | |
10744 | plane_state->src_w = hdisplay << 16; | |
10745 | plane_state->src_h = vdisplay << 16; | |
10746 | ||
10747 | return 0; | |
10748 | } | |
10749 | ||
d2434ab7 | 10750 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10751 | struct drm_display_mode *mode, |
51fd371b RC |
10752 | struct intel_load_detect_pipe *old, |
10753 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10754 | { |
10755 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10756 | struct intel_encoder *intel_encoder = |
10757 | intel_attached_encoder(connector); | |
79e53945 | 10758 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10759 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10760 | struct drm_crtc *crtc = NULL; |
10761 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10762 | struct drm_framebuffer *fb; |
51fd371b | 10763 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10764 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10765 | struct drm_connector_state *connector_state; |
4be07317 | 10766 | struct intel_crtc_state *crtc_state; |
51fd371b | 10767 | int ret, i = -1; |
79e53945 | 10768 | |
d2dff872 | 10769 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10770 | connector->base.id, connector->name, |
8e329a03 | 10771 | encoder->base.id, encoder->name); |
d2dff872 | 10772 | |
edde3617 ML |
10773 | old->restore_state = NULL; |
10774 | ||
51fd371b RC |
10775 | retry: |
10776 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10777 | if (ret) | |
ad3c558f | 10778 | goto fail; |
6e9f798d | 10779 | |
79e53945 JB |
10780 | /* |
10781 | * Algorithm gets a little messy: | |
7a5e4805 | 10782 | * |
79e53945 JB |
10783 | * - if the connector already has an assigned crtc, use it (but make |
10784 | * sure it's on first) | |
7a5e4805 | 10785 | * |
79e53945 JB |
10786 | * - try to find the first unused crtc that can drive this connector, |
10787 | * and use that if we find one | |
79e53945 JB |
10788 | */ |
10789 | ||
10790 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10791 | if (connector->state->crtc) { |
10792 | crtc = connector->state->crtc; | |
8261b191 | 10793 | |
51fd371b | 10794 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10795 | if (ret) |
ad3c558f | 10796 | goto fail; |
8261b191 CW |
10797 | |
10798 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10799 | goto found; |
79e53945 JB |
10800 | } |
10801 | ||
10802 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10803 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10804 | i++; |
10805 | if (!(encoder->possible_crtcs & (1 << i))) | |
10806 | continue; | |
edde3617 ML |
10807 | |
10808 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10809 | if (ret) | |
10810 | goto fail; | |
10811 | ||
10812 | if (possible_crtc->state->enable) { | |
10813 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10814 | continue; |
edde3617 | 10815 | } |
a459249c VS |
10816 | |
10817 | crtc = possible_crtc; | |
10818 | break; | |
79e53945 JB |
10819 | } |
10820 | ||
10821 | /* | |
10822 | * If we didn't find an unused CRTC, don't use any. | |
10823 | */ | |
10824 | if (!crtc) { | |
7173188d | 10825 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10826 | goto fail; |
79e53945 JB |
10827 | } |
10828 | ||
edde3617 ML |
10829 | found: |
10830 | intel_crtc = to_intel_crtc(crtc); | |
10831 | ||
4d02e2de DV |
10832 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10833 | if (ret) | |
ad3c558f | 10834 | goto fail; |
79e53945 | 10835 | |
83a57153 | 10836 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10837 | restore_state = drm_atomic_state_alloc(dev); |
10838 | if (!state || !restore_state) { | |
10839 | ret = -ENOMEM; | |
10840 | goto fail; | |
10841 | } | |
83a57153 ACO |
10842 | |
10843 | state->acquire_ctx = ctx; | |
edde3617 | 10844 | restore_state->acquire_ctx = ctx; |
83a57153 | 10845 | |
944b0c76 ACO |
10846 | connector_state = drm_atomic_get_connector_state(state, connector); |
10847 | if (IS_ERR(connector_state)) { | |
10848 | ret = PTR_ERR(connector_state); | |
10849 | goto fail; | |
10850 | } | |
10851 | ||
edde3617 ML |
10852 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10853 | if (ret) | |
10854 | goto fail; | |
944b0c76 | 10855 | |
4be07317 ACO |
10856 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10857 | if (IS_ERR(crtc_state)) { | |
10858 | ret = PTR_ERR(crtc_state); | |
10859 | goto fail; | |
10860 | } | |
10861 | ||
49d6fa21 | 10862 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10863 | |
6492711d CW |
10864 | if (!mode) |
10865 | mode = &load_detect_mode; | |
79e53945 | 10866 | |
d2dff872 CW |
10867 | /* We need a framebuffer large enough to accommodate all accesses |
10868 | * that the plane may generate whilst we perform load detection. | |
10869 | * We can not rely on the fbcon either being present (we get called | |
10870 | * during its initialisation to detect all boot displays, or it may | |
10871 | * not even exist) or that it is large enough to satisfy the | |
10872 | * requested mode. | |
10873 | */ | |
94352cf9 DV |
10874 | fb = mode_fits_in_fbdev(dev, mode); |
10875 | if (fb == NULL) { | |
d2dff872 | 10876 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10877 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10878 | } else |
10879 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10880 | if (IS_ERR(fb)) { |
d2dff872 | 10881 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10882 | goto fail; |
79e53945 | 10883 | } |
79e53945 | 10884 | |
d3a40d1b ACO |
10885 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10886 | if (ret) | |
10887 | goto fail; | |
10888 | ||
edde3617 ML |
10889 | drm_framebuffer_unreference(fb); |
10890 | ||
10891 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10892 | if (ret) | |
10893 | goto fail; | |
10894 | ||
10895 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10896 | if (!ret) | |
10897 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10898 | if (!ret) | |
10899 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10900 | if (ret) { | |
10901 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10902 | goto fail; | |
10903 | } | |
8c7b5ccb | 10904 | |
3ba86073 ML |
10905 | ret = drm_atomic_commit(state); |
10906 | if (ret) { | |
6492711d | 10907 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10908 | goto fail; |
79e53945 | 10909 | } |
edde3617 ML |
10910 | |
10911 | old->restore_state = restore_state; | |
7173188d | 10912 | |
79e53945 | 10913 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10914 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10915 | return true; |
412b61d8 | 10916 | |
ad3c558f | 10917 | fail: |
e5d958ef | 10918 | drm_atomic_state_free(state); |
edde3617 ML |
10919 | drm_atomic_state_free(restore_state); |
10920 | restore_state = state = NULL; | |
83a57153 | 10921 | |
51fd371b RC |
10922 | if (ret == -EDEADLK) { |
10923 | drm_modeset_backoff(ctx); | |
10924 | goto retry; | |
10925 | } | |
10926 | ||
412b61d8 | 10927 | return false; |
79e53945 JB |
10928 | } |
10929 | ||
d2434ab7 | 10930 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10931 | struct intel_load_detect_pipe *old, |
10932 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10933 | { |
d2434ab7 DV |
10934 | struct intel_encoder *intel_encoder = |
10935 | intel_attached_encoder(connector); | |
4ef69c7a | 10936 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10937 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10938 | int ret; |
79e53945 | 10939 | |
d2dff872 | 10940 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10941 | connector->base.id, connector->name, |
8e329a03 | 10942 | encoder->base.id, encoder->name); |
d2dff872 | 10943 | |
edde3617 | 10944 | if (!state) |
0622a53c | 10945 | return; |
79e53945 | 10946 | |
edde3617 ML |
10947 | ret = drm_atomic_commit(state); |
10948 | if (ret) { | |
10949 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10950 | drm_atomic_state_free(state); | |
10951 | } | |
79e53945 JB |
10952 | } |
10953 | ||
da4a1efa | 10954 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10955 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10956 | { |
fac5e23e | 10957 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10958 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10959 | ||
10960 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10961 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10962 | else if (HAS_PCH_SPLIT(dev)) |
10963 | return 120000; | |
10964 | else if (!IS_GEN2(dev)) | |
10965 | return 96000; | |
10966 | else | |
10967 | return 48000; | |
10968 | } | |
10969 | ||
79e53945 | 10970 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10971 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10972 | struct intel_crtc_state *pipe_config) |
79e53945 | 10973 | { |
f1f644dc | 10974 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10975 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10976 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10977 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10978 | u32 fp; |
9e2c8475 | 10979 | struct dpll clock; |
dccbea3b | 10980 | int port_clock; |
da4a1efa | 10981 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10982 | |
10983 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10984 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10985 | else |
293623f7 | 10986 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10987 | |
10988 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10989 | if (IS_PINEVIEW(dev)) { |
10990 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10991 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10992 | } else { |
10993 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10994 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10995 | } | |
10996 | ||
a6c45cf0 | 10997 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10998 | if (IS_PINEVIEW(dev)) |
10999 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
11000 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
11001 | else |
11002 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
11003 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
11004 | ||
11005 | switch (dpll & DPLL_MODE_MASK) { | |
11006 | case DPLLB_MODE_DAC_SERIAL: | |
11007 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
11008 | 5 : 10; | |
11009 | break; | |
11010 | case DPLLB_MODE_LVDS: | |
11011 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
11012 | 7 : 14; | |
11013 | break; | |
11014 | default: | |
28c97730 | 11015 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 11016 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 11017 | return; |
79e53945 JB |
11018 | } |
11019 | ||
ac58c3f0 | 11020 | if (IS_PINEVIEW(dev)) |
dccbea3b | 11021 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11022 | else |
dccbea3b | 11023 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11024 | } else { |
0fb58223 | 11025 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11026 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11027 | |
11028 | if (is_lvds) { | |
11029 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11030 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11031 | |
11032 | if (lvds & LVDS_CLKB_POWER_UP) | |
11033 | clock.p2 = 7; | |
11034 | else | |
11035 | clock.p2 = 14; | |
79e53945 JB |
11036 | } else { |
11037 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11038 | clock.p1 = 2; | |
11039 | else { | |
11040 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11041 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11042 | } | |
11043 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11044 | clock.p2 = 4; | |
11045 | else | |
11046 | clock.p2 = 2; | |
79e53945 | 11047 | } |
da4a1efa | 11048 | |
dccbea3b | 11049 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11050 | } |
11051 | ||
18442d08 VS |
11052 | /* |
11053 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11054 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11055 | * encoder's get_config() function. |
11056 | */ | |
dccbea3b | 11057 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11058 | } |
11059 | ||
6878da05 VS |
11060 | int intel_dotclock_calculate(int link_freq, |
11061 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11062 | { |
f1f644dc JB |
11063 | /* |
11064 | * The calculation for the data clock is: | |
1041a02f | 11065 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11066 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11067 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11068 | * |
11069 | * and the link clock is simpler: | |
1041a02f | 11070 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11071 | */ |
11072 | ||
6878da05 VS |
11073 | if (!m_n->link_n) |
11074 | return 0; | |
f1f644dc | 11075 | |
6878da05 VS |
11076 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11077 | } | |
f1f644dc | 11078 | |
18442d08 | 11079 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11080 | struct intel_crtc_state *pipe_config) |
6878da05 | 11081 | { |
e3b247da | 11082 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11083 | |
18442d08 VS |
11084 | /* read out port_clock from the DPLL */ |
11085 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11086 | |
f1f644dc | 11087 | /* |
e3b247da VS |
11088 | * In case there is an active pipe without active ports, |
11089 | * we may need some idea for the dotclock anyway. | |
11090 | * Calculate one based on the FDI configuration. | |
79e53945 | 11091 | */ |
2d112de7 | 11092 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11093 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11094 | &pipe_config->fdi_m_n); |
79e53945 JB |
11095 | } |
11096 | ||
11097 | /** Returns the currently programmed mode of the given pipe. */ | |
11098 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11099 | struct drm_crtc *crtc) | |
11100 | { | |
fac5e23e | 11101 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11103 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11104 | struct drm_display_mode *mode; |
3f36b937 | 11105 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11106 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11107 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11108 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11109 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11110 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11111 | |
11112 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11113 | if (!mode) | |
11114 | return NULL; | |
11115 | ||
3f36b937 TU |
11116 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11117 | if (!pipe_config) { | |
11118 | kfree(mode); | |
11119 | return NULL; | |
11120 | } | |
11121 | ||
f1f644dc JB |
11122 | /* |
11123 | * Construct a pipe_config sufficient for getting the clock info | |
11124 | * back out of crtc_clock_get. | |
11125 | * | |
11126 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11127 | * to use a real value here instead. | |
11128 | */ | |
3f36b937 TU |
11129 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11130 | pipe_config->pixel_multiplier = 1; | |
11131 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11132 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11133 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11134 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11135 | ||
11136 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11137 | mode->hdisplay = (htot & 0xffff) + 1; |
11138 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11139 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11140 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11141 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11142 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11143 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11144 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11145 | ||
11146 | drm_mode_set_name(mode); | |
79e53945 | 11147 | |
3f36b937 TU |
11148 | kfree(pipe_config); |
11149 | ||
79e53945 JB |
11150 | return mode; |
11151 | } | |
11152 | ||
11153 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11154 | { | |
11155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11156 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11157 | struct intel_flip_work *work; |
67e77c5a | 11158 | |
5e2d7afc | 11159 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11160 | work = intel_crtc->flip_work; |
11161 | intel_crtc->flip_work = NULL; | |
11162 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11163 | |
5a21b665 | 11164 | if (work) { |
51cbaf01 ML |
11165 | cancel_work_sync(&work->mmio_work); |
11166 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11167 | kfree(work); |
67e77c5a | 11168 | } |
79e53945 JB |
11169 | |
11170 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11171 | |
79e53945 JB |
11172 | kfree(intel_crtc); |
11173 | } | |
11174 | ||
6b95a207 KH |
11175 | static void intel_unpin_work_fn(struct work_struct *__work) |
11176 | { | |
51cbaf01 ML |
11177 | struct intel_flip_work *work = |
11178 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11179 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11180 | struct drm_device *dev = crtc->base.dev; | |
11181 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11182 | |
5a21b665 DV |
11183 | if (is_mmio_work(work)) |
11184 | flush_work(&work->mmio_work); | |
03f476e1 | 11185 | |
5a21b665 DV |
11186 | mutex_lock(&dev->struct_mutex); |
11187 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11188 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11189 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11190 | |
e8a261ea CW |
11191 | i915_gem_request_put(work->flip_queued_req); |
11192 | ||
5748b6a1 CW |
11193 | intel_frontbuffer_flip_complete(to_i915(dev), |
11194 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11195 | intel_fbc_post_update(crtc); |
11196 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11197 | |
5a21b665 DV |
11198 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11199 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11200 | |
5a21b665 DV |
11201 | kfree(work); |
11202 | } | |
d9e86c0e | 11203 | |
5a21b665 DV |
11204 | /* Is 'a' after or equal to 'b'? */ |
11205 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11206 | { | |
11207 | return !((a - b) & 0x80000000); | |
11208 | } | |
143f73b3 | 11209 | |
5a21b665 DV |
11210 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11211 | struct intel_flip_work *work) | |
11212 | { | |
11213 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11214 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 11215 | unsigned reset_counter; |
143f73b3 | 11216 | |
5a21b665 DV |
11217 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
11218 | if (crtc->reset_counter != reset_counter) | |
11219 | return true; | |
143f73b3 | 11220 | |
5a21b665 DV |
11221 | /* |
11222 | * The relevant registers doen't exist on pre-ctg. | |
11223 | * As the flip done interrupt doesn't trigger for mmio | |
11224 | * flips on gmch platforms, a flip count check isn't | |
11225 | * really needed there. But since ctg has the registers, | |
11226 | * include it in the check anyway. | |
11227 | */ | |
11228 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11229 | return true; | |
b4a98e57 | 11230 | |
5a21b665 DV |
11231 | /* |
11232 | * BDW signals flip done immediately if the plane | |
11233 | * is disabled, even if the plane enable is already | |
11234 | * armed to occur at the next vblank :( | |
11235 | */ | |
f99d7069 | 11236 | |
5a21b665 DV |
11237 | /* |
11238 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11239 | * used the same base address. In that case the mmio flip might | |
11240 | * have completed, but the CS hasn't even executed the flip yet. | |
11241 | * | |
11242 | * A flip count check isn't enough as the CS might have updated | |
11243 | * the base address just after start of vblank, but before we | |
11244 | * managed to process the interrupt. This means we'd complete the | |
11245 | * CS flip too soon. | |
11246 | * | |
11247 | * Combining both checks should get us a good enough result. It may | |
11248 | * still happen that the CS flip has been executed, but has not | |
11249 | * yet actually completed. But in case the base address is the same | |
11250 | * anyway, we don't really care. | |
11251 | */ | |
11252 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11253 | crtc->flip_work->gtt_offset && | |
11254 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11255 | crtc->flip_work->flip_count); | |
11256 | } | |
b4a98e57 | 11257 | |
5a21b665 DV |
11258 | static bool |
11259 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11260 | struct intel_flip_work *work) | |
11261 | { | |
11262 | /* | |
11263 | * MMIO work completes when vblank is different from | |
11264 | * flip_queued_vblank. | |
11265 | * | |
11266 | * Reset counter value doesn't matter, this is handled by | |
11267 | * i915_wait_request finishing early, so no need to handle | |
11268 | * reset here. | |
11269 | */ | |
11270 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11271 | } |
11272 | ||
51cbaf01 ML |
11273 | |
11274 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11275 | struct intel_flip_work *work) | |
11276 | { | |
11277 | if (!atomic_read(&work->pending)) | |
11278 | return false; | |
11279 | ||
11280 | smp_rmb(); | |
11281 | ||
5a21b665 DV |
11282 | if (is_mmio_work(work)) |
11283 | return __pageflip_finished_mmio(crtc, work); | |
11284 | else | |
11285 | return __pageflip_finished_cs(crtc, work); | |
11286 | } | |
11287 | ||
11288 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11289 | { | |
91c8a326 | 11290 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11291 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11293 | struct intel_flip_work *work; | |
11294 | unsigned long flags; | |
11295 | ||
11296 | /* Ignore early vblank irqs */ | |
11297 | if (!crtc) | |
11298 | return; | |
11299 | ||
51cbaf01 | 11300 | /* |
5a21b665 DV |
11301 | * This is called both by irq handlers and the reset code (to complete |
11302 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11303 | */ |
5a21b665 DV |
11304 | spin_lock_irqsave(&dev->event_lock, flags); |
11305 | work = intel_crtc->flip_work; | |
11306 | ||
11307 | if (work != NULL && | |
11308 | !is_mmio_work(work) && | |
11309 | pageflip_finished(intel_crtc, work)) | |
11310 | page_flip_completed(intel_crtc); | |
11311 | ||
11312 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11313 | } |
11314 | ||
51cbaf01 | 11315 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11316 | { |
91c8a326 | 11317 | struct drm_device *dev = &dev_priv->drm; |
5251f04e ML |
11318 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11319 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11320 | struct intel_flip_work *work; |
6b95a207 KH |
11321 | unsigned long flags; |
11322 | ||
5251f04e ML |
11323 | /* Ignore early vblank irqs */ |
11324 | if (!crtc) | |
11325 | return; | |
f326038a DV |
11326 | |
11327 | /* | |
11328 | * This is called both by irq handlers and the reset code (to complete | |
11329 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11330 | */ |
6b95a207 | 11331 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11332 | work = intel_crtc->flip_work; |
5251f04e | 11333 | |
5a21b665 DV |
11334 | if (work != NULL && |
11335 | is_mmio_work(work) && | |
11336 | pageflip_finished(intel_crtc, work)) | |
11337 | page_flip_completed(intel_crtc); | |
5251f04e | 11338 | |
6b95a207 KH |
11339 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11340 | } | |
11341 | ||
5a21b665 DV |
11342 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11343 | struct intel_flip_work *work) | |
84c33a64 | 11344 | { |
5a21b665 | 11345 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11346 | |
5a21b665 DV |
11347 | /* Ensure that the work item is consistent when activating it ... */ |
11348 | smp_mb__before_atomic(); | |
11349 | atomic_set(&work->pending, 1); | |
11350 | } | |
a6747b73 | 11351 | |
5a21b665 DV |
11352 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11353 | struct drm_crtc *crtc, | |
11354 | struct drm_framebuffer *fb, | |
11355 | struct drm_i915_gem_object *obj, | |
11356 | struct drm_i915_gem_request *req, | |
11357 | uint32_t flags) | |
11358 | { | |
7e37f889 | 11359 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11360 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11361 | u32 flip_mask; | |
11362 | int ret; | |
143f73b3 | 11363 | |
5a21b665 DV |
11364 | ret = intel_ring_begin(req, 6); |
11365 | if (ret) | |
11366 | return ret; | |
143f73b3 | 11367 | |
5a21b665 DV |
11368 | /* Can't queue multiple flips, so wait for the previous |
11369 | * one to finish before executing the next. | |
11370 | */ | |
11371 | if (intel_crtc->plane) | |
11372 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11373 | else | |
11374 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11375 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11376 | intel_ring_emit(ring, MI_NOOP); | |
11377 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11378 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11379 | intel_ring_emit(ring, fb->pitches[0]); |
11380 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11381 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11382 | |
5a21b665 DV |
11383 | return 0; |
11384 | } | |
84c33a64 | 11385 | |
5a21b665 DV |
11386 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11387 | struct drm_crtc *crtc, | |
11388 | struct drm_framebuffer *fb, | |
11389 | struct drm_i915_gem_object *obj, | |
11390 | struct drm_i915_gem_request *req, | |
11391 | uint32_t flags) | |
11392 | { | |
7e37f889 | 11393 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11395 | u32 flip_mask; | |
11396 | int ret; | |
d55dbd06 | 11397 | |
5a21b665 DV |
11398 | ret = intel_ring_begin(req, 6); |
11399 | if (ret) | |
11400 | return ret; | |
d55dbd06 | 11401 | |
5a21b665 DV |
11402 | if (intel_crtc->plane) |
11403 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11404 | else | |
11405 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11406 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11407 | intel_ring_emit(ring, MI_NOOP); | |
11408 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11409 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11410 | intel_ring_emit(ring, fb->pitches[0]); |
11411 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11412 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11413 | |
5a21b665 DV |
11414 | return 0; |
11415 | } | |
84c33a64 | 11416 | |
5a21b665 DV |
11417 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11418 | struct drm_crtc *crtc, | |
11419 | struct drm_framebuffer *fb, | |
11420 | struct drm_i915_gem_object *obj, | |
11421 | struct drm_i915_gem_request *req, | |
11422 | uint32_t flags) | |
11423 | { | |
7e37f889 | 11424 | struct intel_ring *ring = req->ring; |
fac5e23e | 11425 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11427 | uint32_t pf, pipesrc; | |
11428 | int ret; | |
143f73b3 | 11429 | |
5a21b665 DV |
11430 | ret = intel_ring_begin(req, 4); |
11431 | if (ret) | |
11432 | return ret; | |
143f73b3 | 11433 | |
5a21b665 DV |
11434 | /* i965+ uses the linear or tiled offsets from the |
11435 | * Display Registers (which do not change across a page-flip) | |
11436 | * so we need only reprogram the base address. | |
11437 | */ | |
b5321f30 | 11438 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11439 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11440 | intel_ring_emit(ring, fb->pitches[0]); |
11441 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
3e510a8e | 11442 | i915_gem_object_get_tiling(obj)); |
5a21b665 DV |
11443 | |
11444 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11445 | * untested on non-native modes, so ignore it for now. | |
11446 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11447 | */ | |
11448 | pf = 0; | |
11449 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11450 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11451 | |
5a21b665 | 11452 | return 0; |
8c9f3aaf JB |
11453 | } |
11454 | ||
5a21b665 DV |
11455 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11456 | struct drm_crtc *crtc, | |
11457 | struct drm_framebuffer *fb, | |
11458 | struct drm_i915_gem_object *obj, | |
11459 | struct drm_i915_gem_request *req, | |
11460 | uint32_t flags) | |
da20eabd | 11461 | { |
7e37f889 | 11462 | struct intel_ring *ring = req->ring; |
fac5e23e | 11463 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11464 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11465 | uint32_t pf, pipesrc; | |
11466 | int ret; | |
d21fbe87 | 11467 | |
5a21b665 DV |
11468 | ret = intel_ring_begin(req, 4); |
11469 | if (ret) | |
11470 | return ret; | |
92826fcd | 11471 | |
b5321f30 | 11472 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11473 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
3e510a8e | 11474 | intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj)); |
b5321f30 | 11475 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11476 | |
5a21b665 DV |
11477 | /* Contrary to the suggestions in the documentation, |
11478 | * "Enable Panel Fitter" does not seem to be required when page | |
11479 | * flipping with a non-native mode, and worse causes a normal | |
11480 | * modeset to fail. | |
11481 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11482 | */ | |
11483 | pf = 0; | |
11484 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11485 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11486 | |
5a21b665 | 11487 | return 0; |
7809e5ae MR |
11488 | } |
11489 | ||
5a21b665 DV |
11490 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11491 | struct drm_crtc *crtc, | |
11492 | struct drm_framebuffer *fb, | |
11493 | struct drm_i915_gem_object *obj, | |
11494 | struct drm_i915_gem_request *req, | |
11495 | uint32_t flags) | |
d21fbe87 | 11496 | { |
7e37f889 | 11497 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11499 | uint32_t plane_bit = 0; | |
11500 | int len, ret; | |
d21fbe87 | 11501 | |
5a21b665 DV |
11502 | switch (intel_crtc->plane) { |
11503 | case PLANE_A: | |
11504 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11505 | break; | |
11506 | case PLANE_B: | |
11507 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11508 | break; | |
11509 | case PLANE_C: | |
11510 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11511 | break; | |
11512 | default: | |
11513 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11514 | return -ENODEV; | |
11515 | } | |
11516 | ||
11517 | len = 4; | |
b5321f30 | 11518 | if (req->engine->id == RCS) { |
5a21b665 DV |
11519 | len += 6; |
11520 | /* | |
11521 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11522 | * 48bits addresses, and we need a NOOP for the batch size to | |
11523 | * stay even. | |
11524 | */ | |
11525 | if (IS_GEN8(dev)) | |
11526 | len += 2; | |
11527 | } | |
11528 | ||
11529 | /* | |
11530 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11531 | * "The full packet must be contained within the same cache line." | |
11532 | * | |
11533 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11534 | * cacheline, if we ever start emitting more commands before | |
11535 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11536 | * then do the cacheline alignment, and finally emit the | |
11537 | * MI_DISPLAY_FLIP. | |
11538 | */ | |
11539 | ret = intel_ring_cacheline_align(req); | |
11540 | if (ret) | |
11541 | return ret; | |
11542 | ||
11543 | ret = intel_ring_begin(req, len); | |
11544 | if (ret) | |
11545 | return ret; | |
11546 | ||
11547 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11548 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11549 | * more than one flip event at any time (or ensure that one flip message | |
11550 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11551 | * Experimentation says that BCS works despite DERRMR masking all | |
11552 | * flip-done completion events and that unmasking all planes at once | |
11553 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11554 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11555 | */ | |
b5321f30 CW |
11556 | if (req->engine->id == RCS) { |
11557 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11558 | intel_ring_emit_reg(ring, DERRMR); | |
11559 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11560 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11561 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11562 | if (IS_GEN8(dev)) | |
b5321f30 | 11563 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11564 | MI_SRM_LRM_GLOBAL_GTT); |
11565 | else | |
b5321f30 | 11566 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11567 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 CW |
11568 | intel_ring_emit_reg(ring, DERRMR); |
11569 | intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256); | |
5a21b665 | 11570 | if (IS_GEN8(dev)) { |
b5321f30 CW |
11571 | intel_ring_emit(ring, 0); |
11572 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11573 | } |
11574 | } | |
11575 | ||
b5321f30 | 11576 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
3e510a8e | 11577 | intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj)); |
b5321f30 CW |
11578 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11579 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11580 | |
11581 | return 0; | |
11582 | } | |
11583 | ||
11584 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11585 | struct drm_i915_gem_object *obj) | |
11586 | { | |
c37efb99 CW |
11587 | struct reservation_object *resv; |
11588 | ||
5a21b665 DV |
11589 | /* |
11590 | * This is not being used for older platforms, because | |
11591 | * non-availability of flip done interrupt forces us to use | |
11592 | * CS flips. Older platforms derive flip done using some clever | |
11593 | * tricks involving the flip_pending status bits and vblank irqs. | |
11594 | * So using MMIO flips there would disrupt this mechanism. | |
11595 | */ | |
11596 | ||
11597 | if (engine == NULL) | |
11598 | return true; | |
11599 | ||
11600 | if (INTEL_GEN(engine->i915) < 5) | |
11601 | return false; | |
11602 | ||
11603 | if (i915.use_mmio_flip < 0) | |
11604 | return false; | |
11605 | else if (i915.use_mmio_flip > 0) | |
11606 | return true; | |
11607 | else if (i915.enable_execlists) | |
11608 | return true; | |
c37efb99 CW |
11609 | |
11610 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
11611 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) | |
5a21b665 | 11612 | return true; |
c37efb99 | 11613 | |
d72d908b CW |
11614 | return engine != i915_gem_active_get_engine(&obj->last_write, |
11615 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11616 | } |
11617 | ||
11618 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11619 | unsigned int rotation, | |
11620 | struct intel_flip_work *work) | |
11621 | { | |
11622 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11623 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11624 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11625 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 11626 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
11627 | |
11628 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11629 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11630 | switch (fb->modifier[0]) { | |
11631 | case DRM_FORMAT_MOD_NONE: | |
11632 | break; | |
11633 | case I915_FORMAT_MOD_X_TILED: | |
11634 | ctl |= PLANE_CTL_TILED_X; | |
11635 | break; | |
11636 | case I915_FORMAT_MOD_Y_TILED: | |
11637 | ctl |= PLANE_CTL_TILED_Y; | |
11638 | break; | |
11639 | case I915_FORMAT_MOD_Yf_TILED: | |
11640 | ctl |= PLANE_CTL_TILED_YF; | |
11641 | break; | |
11642 | default: | |
11643 | MISSING_CASE(fb->modifier[0]); | |
11644 | } | |
11645 | ||
5a21b665 DV |
11646 | /* |
11647 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11648 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11649 | */ | |
11650 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11651 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11652 | ||
11653 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11654 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11655 | } | |
11656 | ||
11657 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11658 | struct intel_flip_work *work) | |
11659 | { | |
11660 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11661 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11662 | struct intel_framebuffer *intel_fb = |
11663 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11664 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11665 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); | |
11666 | u32 dspcntr; | |
11667 | ||
11668 | dspcntr = I915_READ(reg); | |
11669 | ||
3e510a8e | 11670 | if (i915_gem_object_is_tiled(obj)) |
5a21b665 DV |
11671 | dspcntr |= DISPPLANE_TILED; |
11672 | else | |
11673 | dspcntr &= ~DISPPLANE_TILED; | |
11674 | ||
11675 | I915_WRITE(reg, dspcntr); | |
11676 | ||
11677 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11678 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11679 | } | |
11680 | ||
11681 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
11682 | { | |
11683 | struct intel_flip_work *work = | |
11684 | container_of(w, struct intel_flip_work, mmio_work); | |
11685 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
11686 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
11687 | struct intel_framebuffer *intel_fb = | |
11688 | to_intel_framebuffer(crtc->base.primary->fb); | |
11689 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
c37efb99 | 11690 | struct reservation_object *resv; |
5a21b665 DV |
11691 | |
11692 | if (work->flip_queued_req) | |
776f3236 CW |
11693 | WARN_ON(i915_wait_request(work->flip_queued_req, |
11694 | false, NULL, | |
11695 | NO_WAITBOOST)); | |
5a21b665 DV |
11696 | |
11697 | /* For framebuffer backed by dmabuf, wait for fence */ | |
c37efb99 CW |
11698 | resv = i915_gem_object_get_dmabuf_resv(obj); |
11699 | if (resv) | |
11700 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, | |
5a21b665 DV |
11701 | MAX_SCHEDULE_TIMEOUT) < 0); |
11702 | ||
11703 | intel_pipe_update_start(crtc); | |
11704 | ||
11705 | if (INTEL_GEN(dev_priv) >= 9) | |
11706 | skl_do_mmio_flip(crtc, work->rotation, work); | |
11707 | else | |
11708 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11709 | ilk_do_mmio_flip(crtc, work); | |
11710 | ||
11711 | intel_pipe_update_end(crtc, work); | |
11712 | } | |
11713 | ||
11714 | static int intel_default_queue_flip(struct drm_device *dev, | |
11715 | struct drm_crtc *crtc, | |
11716 | struct drm_framebuffer *fb, | |
11717 | struct drm_i915_gem_object *obj, | |
11718 | struct drm_i915_gem_request *req, | |
11719 | uint32_t flags) | |
11720 | { | |
11721 | return -ENODEV; | |
11722 | } | |
11723 | ||
11724 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
11725 | struct intel_crtc *intel_crtc, | |
11726 | struct intel_flip_work *work) | |
11727 | { | |
11728 | u32 addr, vblank; | |
11729 | ||
11730 | if (!atomic_read(&work->pending)) | |
11731 | return false; | |
11732 | ||
11733 | smp_rmb(); | |
11734 | ||
11735 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
11736 | if (work->flip_ready_vblank == 0) { | |
11737 | if (work->flip_queued_req && | |
f69a02c9 | 11738 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
11739 | return false; |
11740 | ||
11741 | work->flip_ready_vblank = vblank; | |
11742 | } | |
11743 | ||
11744 | if (vblank - work->flip_ready_vblank < 3) | |
11745 | return false; | |
11746 | ||
11747 | /* Potential stall - if we see that the flip has happened, | |
11748 | * assume a missed interrupt. */ | |
11749 | if (INTEL_GEN(dev_priv) >= 4) | |
11750 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11751 | else | |
11752 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11753 | ||
11754 | /* There is a potential issue here with a false positive after a flip | |
11755 | * to the same address. We could address this by checking for a | |
11756 | * non-incrementing frame counter. | |
11757 | */ | |
11758 | return addr == work->gtt_offset; | |
11759 | } | |
11760 | ||
11761 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
11762 | { | |
91c8a326 | 11763 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11764 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11766 | struct intel_flip_work *work; | |
11767 | ||
11768 | WARN_ON(!in_interrupt()); | |
11769 | ||
11770 | if (crtc == NULL) | |
11771 | return; | |
11772 | ||
11773 | spin_lock(&dev->event_lock); | |
11774 | work = intel_crtc->flip_work; | |
11775 | ||
11776 | if (work != NULL && !is_mmio_work(work) && | |
11777 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
11778 | WARN_ONCE(1, | |
11779 | "Kicking stuck page flip: queued at %d, now %d\n", | |
11780 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
11781 | page_flip_completed(intel_crtc); | |
11782 | work = NULL; | |
11783 | } | |
11784 | ||
11785 | if (work != NULL && !is_mmio_work(work) && | |
11786 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
11787 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
11788 | spin_unlock(&dev->event_lock); | |
11789 | } | |
11790 | ||
11791 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
11792 | struct drm_framebuffer *fb, | |
11793 | struct drm_pending_vblank_event *event, | |
11794 | uint32_t page_flip_flags) | |
11795 | { | |
11796 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 11797 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11798 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
11799 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11800 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11801 | struct drm_plane *primary = crtc->primary; | |
11802 | enum pipe pipe = intel_crtc->pipe; | |
11803 | struct intel_flip_work *work; | |
11804 | struct intel_engine_cs *engine; | |
11805 | bool mmio_flip; | |
8e637178 | 11806 | struct drm_i915_gem_request *request; |
5a21b665 DV |
11807 | int ret; |
11808 | ||
11809 | /* | |
11810 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11811 | * check to be safe. In the future we may enable pageflipping from | |
11812 | * a disabled primary plane. | |
11813 | */ | |
11814 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11815 | return -EBUSY; | |
11816 | ||
11817 | /* Can't change pixel format via MI display flips. */ | |
11818 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
11819 | return -EINVAL; | |
11820 | ||
11821 | /* | |
11822 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11823 | * Note that pitch changes could also affect these register. | |
11824 | */ | |
11825 | if (INTEL_INFO(dev)->gen > 3 && | |
11826 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
11827 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
11828 | return -EINVAL; | |
11829 | ||
11830 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
11831 | goto out_hang; | |
11832 | ||
11833 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
11834 | if (work == NULL) | |
11835 | return -ENOMEM; | |
11836 | ||
11837 | work->event = event; | |
11838 | work->crtc = crtc; | |
11839 | work->old_fb = old_fb; | |
11840 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
11841 | ||
11842 | ret = drm_crtc_vblank_get(crtc); | |
11843 | if (ret) | |
11844 | goto free_work; | |
11845 | ||
11846 | /* We borrow the event spin lock for protecting flip_work */ | |
11847 | spin_lock_irq(&dev->event_lock); | |
11848 | if (intel_crtc->flip_work) { | |
11849 | /* Before declaring the flip queue wedged, check if | |
11850 | * the hardware completed the operation behind our backs. | |
11851 | */ | |
11852 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
11853 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11854 | page_flip_completed(intel_crtc); | |
11855 | } else { | |
11856 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
11857 | spin_unlock_irq(&dev->event_lock); | |
11858 | ||
11859 | drm_crtc_vblank_put(crtc); | |
11860 | kfree(work); | |
11861 | return -EBUSY; | |
11862 | } | |
11863 | } | |
11864 | intel_crtc->flip_work = work; | |
11865 | spin_unlock_irq(&dev->event_lock); | |
11866 | ||
11867 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
11868 | flush_workqueue(dev_priv->wq); | |
11869 | ||
11870 | /* Reference the objects for the scheduled work. */ | |
11871 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
11872 | |
11873 | crtc->primary->fb = fb; | |
11874 | update_state_fb(crtc->primary); | |
faf68d92 ML |
11875 | |
11876 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
11877 | to_intel_plane_state(primary->state)); | |
5a21b665 | 11878 | |
25dc556a | 11879 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
11880 | |
11881 | ret = i915_mutex_lock_interruptible(dev); | |
11882 | if (ret) | |
11883 | goto cleanup; | |
11884 | ||
11885 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
11886 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
11887 | ret = -EIO; | |
11888 | goto cleanup; | |
11889 | } | |
11890 | ||
11891 | atomic_inc(&intel_crtc->unpin_work_count); | |
11892 | ||
11893 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
11894 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
11895 | ||
11896 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
11897 | engine = &dev_priv->engine[BCS]; | |
3e510a8e CW |
11898 | if (i915_gem_object_get_tiling(obj) != |
11899 | i915_gem_object_get_tiling(intel_fb_obj(work->old_fb))) | |
5a21b665 DV |
11900 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11901 | engine = NULL; | |
11902 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
11903 | engine = &dev_priv->engine[BCS]; | |
11904 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
d72d908b CW |
11905 | engine = i915_gem_active_get_engine(&obj->last_write, |
11906 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11907 | if (engine == NULL || engine->id != RCS) |
11908 | engine = &dev_priv->engine[BCS]; | |
11909 | } else { | |
11910 | engine = &dev_priv->engine[RCS]; | |
11911 | } | |
11912 | ||
11913 | mmio_flip = use_mmio_flip(engine, obj); | |
11914 | ||
5a21b665 DV |
11915 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
11916 | if (ret) | |
11917 | goto cleanup_pending; | |
11918 | ||
6687c906 | 11919 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
11920 | work->gtt_offset += intel_crtc->dspaddr_offset; |
11921 | work->rotation = crtc->primary->state->rotation; | |
11922 | ||
11923 | if (mmio_flip) { | |
11924 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
11925 | ||
d72d908b CW |
11926 | work->flip_queued_req = i915_gem_active_get(&obj->last_write, |
11927 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11928 | schedule_work(&work->mmio_work); |
11929 | } else { | |
8e637178 CW |
11930 | request = i915_gem_request_alloc(engine, engine->last_context); |
11931 | if (IS_ERR(request)) { | |
11932 | ret = PTR_ERR(request); | |
11933 | goto cleanup_unpin; | |
11934 | } | |
11935 | ||
11936 | ret = i915_gem_object_sync(obj, request); | |
11937 | if (ret) | |
11938 | goto cleanup_request; | |
11939 | ||
5a21b665 DV |
11940 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
11941 | page_flip_flags); | |
11942 | if (ret) | |
8e637178 | 11943 | goto cleanup_request; |
5a21b665 DV |
11944 | |
11945 | intel_mark_page_flip_active(intel_crtc, work); | |
11946 | ||
8e637178 | 11947 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
11948 | i915_add_request_no_flush(request); |
11949 | } | |
11950 | ||
11951 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
11952 | to_intel_plane(primary)->frontbuffer_bit); | |
11953 | mutex_unlock(&dev->struct_mutex); | |
11954 | ||
5748b6a1 | 11955 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
11956 | to_intel_plane(primary)->frontbuffer_bit); |
11957 | ||
11958 | trace_i915_flip_request(intel_crtc->plane, obj); | |
11959 | ||
11960 | return 0; | |
11961 | ||
8e637178 CW |
11962 | cleanup_request: |
11963 | i915_add_request_no_flush(request); | |
5a21b665 DV |
11964 | cleanup_unpin: |
11965 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
11966 | cleanup_pending: | |
5a21b665 DV |
11967 | atomic_dec(&intel_crtc->unpin_work_count); |
11968 | mutex_unlock(&dev->struct_mutex); | |
11969 | cleanup: | |
11970 | crtc->primary->fb = old_fb; | |
11971 | update_state_fb(crtc->primary); | |
11972 | ||
34911fd3 | 11973 | i915_gem_object_put_unlocked(obj); |
5a21b665 DV |
11974 | drm_framebuffer_unreference(work->old_fb); |
11975 | ||
11976 | spin_lock_irq(&dev->event_lock); | |
11977 | intel_crtc->flip_work = NULL; | |
11978 | spin_unlock_irq(&dev->event_lock); | |
11979 | ||
11980 | drm_crtc_vblank_put(crtc); | |
11981 | free_work: | |
11982 | kfree(work); | |
11983 | ||
11984 | if (ret == -EIO) { | |
11985 | struct drm_atomic_state *state; | |
11986 | struct drm_plane_state *plane_state; | |
11987 | ||
11988 | out_hang: | |
11989 | state = drm_atomic_state_alloc(dev); | |
11990 | if (!state) | |
11991 | return -ENOMEM; | |
11992 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11993 | ||
11994 | retry: | |
11995 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11996 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11997 | if (!ret) { | |
11998 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11999 | ||
12000 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
12001 | if (!ret) | |
12002 | ret = drm_atomic_commit(state); | |
12003 | } | |
12004 | ||
12005 | if (ret == -EDEADLK) { | |
12006 | drm_modeset_backoff(state->acquire_ctx); | |
12007 | drm_atomic_state_clear(state); | |
12008 | goto retry; | |
12009 | } | |
12010 | ||
12011 | if (ret) | |
12012 | drm_atomic_state_free(state); | |
12013 | ||
12014 | if (ret == 0 && event) { | |
12015 | spin_lock_irq(&dev->event_lock); | |
12016 | drm_crtc_send_vblank_event(crtc, event); | |
12017 | spin_unlock_irq(&dev->event_lock); | |
12018 | } | |
12019 | } | |
12020 | return ret; | |
12021 | } | |
12022 | ||
12023 | ||
12024 | /** | |
12025 | * intel_wm_need_update - Check whether watermarks need updating | |
12026 | * @plane: drm plane | |
12027 | * @state: new plane state | |
12028 | * | |
12029 | * Check current plane state versus the new one to determine whether | |
12030 | * watermarks need to be recalculated. | |
12031 | * | |
12032 | * Returns true or false. | |
12033 | */ | |
12034 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12035 | struct drm_plane_state *state) | |
12036 | { | |
12037 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12038 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12039 | ||
12040 | /* Update watermarks on tiling or size changes. */ | |
12041 | if (new->visible != cur->visible) | |
12042 | return true; | |
12043 | ||
12044 | if (!cur->base.fb || !new->base.fb) | |
12045 | return false; | |
12046 | ||
12047 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
12048 | cur->base.rotation != new->base.rotation || | |
12049 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
12050 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
12051 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
12052 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
12053 | return true; | |
12054 | ||
12055 | return false; | |
12056 | } | |
12057 | ||
12058 | static bool needs_scaling(struct intel_plane_state *state) | |
12059 | { | |
12060 | int src_w = drm_rect_width(&state->src) >> 16; | |
12061 | int src_h = drm_rect_height(&state->src) >> 16; | |
12062 | int dst_w = drm_rect_width(&state->dst); | |
12063 | int dst_h = drm_rect_height(&state->dst); | |
12064 | ||
12065 | return (src_w != dst_w || src_h != dst_h); | |
12066 | } | |
d21fbe87 | 12067 | |
da20eabd ML |
12068 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12069 | struct drm_plane_state *plane_state) | |
12070 | { | |
ab1d3a0e | 12071 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12072 | struct drm_crtc *crtc = crtc_state->crtc; |
12073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12074 | struct drm_plane *plane = plane_state->plane; | |
12075 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12076 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12077 | struct intel_plane_state *old_plane_state = |
12078 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12079 | bool mode_changed = needs_modeset(crtc_state); |
12080 | bool was_crtc_enabled = crtc->state->active; | |
12081 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12082 | bool turn_off, turn_on, visible, was_visible; |
12083 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12084 | int ret; |
da20eabd | 12085 | |
84114990 | 12086 | if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12087 | ret = skl_update_scaler_plane( |
12088 | to_intel_crtc_state(crtc_state), | |
12089 | to_intel_plane_state(plane_state)); | |
12090 | if (ret) | |
12091 | return ret; | |
12092 | } | |
12093 | ||
da20eabd ML |
12094 | was_visible = old_plane_state->visible; |
12095 | visible = to_intel_plane_state(plane_state)->visible; | |
12096 | ||
12097 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12098 | was_visible = false; | |
12099 | ||
35c08f43 ML |
12100 | /* |
12101 | * Visibility is calculated as if the crtc was on, but | |
12102 | * after scaler setup everything depends on it being off | |
12103 | * when the crtc isn't active. | |
f818ffea VS |
12104 | * |
12105 | * FIXME this is wrong for watermarks. Watermarks should also | |
12106 | * be computed as if the pipe would be active. Perhaps move | |
12107 | * per-plane wm computation to the .check_plane() hook, and | |
12108 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12109 | */ |
12110 | if (!is_crtc_enabled) | |
12111 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
12112 | |
12113 | if (!was_visible && !visible) | |
12114 | return 0; | |
12115 | ||
e8861675 ML |
12116 | if (fb != old_plane_state->base.fb) |
12117 | pipe_config->fb_changed = true; | |
12118 | ||
da20eabd ML |
12119 | turn_off = was_visible && (!visible || mode_changed); |
12120 | turn_on = visible && (!was_visible || mode_changed); | |
12121 | ||
72660ce0 | 12122 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12123 | intel_crtc->base.base.id, |
12124 | intel_crtc->base.name, | |
72660ce0 VS |
12125 | plane->base.id, plane->name, |
12126 | fb ? fb->base.id : -1); | |
da20eabd | 12127 | |
72660ce0 VS |
12128 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12129 | plane->base.id, plane->name, | |
12130 | was_visible, visible, | |
da20eabd ML |
12131 | turn_off, turn_on, mode_changed); |
12132 | ||
caed361d VS |
12133 | if (turn_on) { |
12134 | pipe_config->update_wm_pre = true; | |
12135 | ||
12136 | /* must disable cxsr around plane enable/disable */ | |
12137 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12138 | pipe_config->disable_cxsr = true; | |
12139 | } else if (turn_off) { | |
12140 | pipe_config->update_wm_post = true; | |
92826fcd | 12141 | |
852eb00d | 12142 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12143 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12144 | pipe_config->disable_cxsr = true; |
852eb00d | 12145 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12146 | /* FIXME bollocks */ |
12147 | pipe_config->update_wm_pre = true; | |
12148 | pipe_config->update_wm_post = true; | |
852eb00d | 12149 | } |
da20eabd | 12150 | |
ed4a6a7c | 12151 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
12152 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
12153 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
12154 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12155 | ||
8be6ca85 | 12156 | if (visible || was_visible) |
cd202f69 | 12157 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12158 | |
31ae71fc ML |
12159 | /* |
12160 | * WaCxSRDisabledForSpriteScaling:ivb | |
12161 | * | |
12162 | * cstate->update_wm was already set above, so this flag will | |
12163 | * take effect when we commit and program watermarks. | |
12164 | */ | |
12165 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
12166 | needs_scaling(to_intel_plane_state(plane_state)) && | |
12167 | !needs_scaling(old_plane_state)) | |
12168 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12169 | |
da20eabd ML |
12170 | return 0; |
12171 | } | |
12172 | ||
6d3a1ce7 ML |
12173 | static bool encoders_cloneable(const struct intel_encoder *a, |
12174 | const struct intel_encoder *b) | |
12175 | { | |
12176 | /* masks could be asymmetric, so check both ways */ | |
12177 | return a == b || (a->cloneable & (1 << b->type) && | |
12178 | b->cloneable & (1 << a->type)); | |
12179 | } | |
12180 | ||
12181 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12182 | struct intel_crtc *crtc, | |
12183 | struct intel_encoder *encoder) | |
12184 | { | |
12185 | struct intel_encoder *source_encoder; | |
12186 | struct drm_connector *connector; | |
12187 | struct drm_connector_state *connector_state; | |
12188 | int i; | |
12189 | ||
12190 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12191 | if (connector_state->crtc != &crtc->base) | |
12192 | continue; | |
12193 | ||
12194 | source_encoder = | |
12195 | to_intel_encoder(connector_state->best_encoder); | |
12196 | if (!encoders_cloneable(encoder, source_encoder)) | |
12197 | return false; | |
12198 | } | |
12199 | ||
12200 | return true; | |
12201 | } | |
12202 | ||
6d3a1ce7 ML |
12203 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12204 | struct drm_crtc_state *crtc_state) | |
12205 | { | |
cf5a15be | 12206 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12207 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12209 | struct intel_crtc_state *pipe_config = |
12210 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12211 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12212 | int ret; |
6d3a1ce7 ML |
12213 | bool mode_changed = needs_modeset(crtc_state); |
12214 | ||
852eb00d | 12215 | if (mode_changed && !crtc_state->active) |
caed361d | 12216 | pipe_config->update_wm_post = true; |
eddfcbcd | 12217 | |
ad421372 ML |
12218 | if (mode_changed && crtc_state->enable && |
12219 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12220 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12221 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12222 | pipe_config); | |
12223 | if (ret) | |
12224 | return ret; | |
12225 | } | |
12226 | ||
82cf435b LL |
12227 | if (crtc_state->color_mgmt_changed) { |
12228 | ret = intel_color_check(crtc, crtc_state); | |
12229 | if (ret) | |
12230 | return ret; | |
e7852a4b LL |
12231 | |
12232 | /* | |
12233 | * Changing color management on Intel hardware is | |
12234 | * handled as part of planes update. | |
12235 | */ | |
12236 | crtc_state->planes_changed = true; | |
82cf435b LL |
12237 | } |
12238 | ||
e435d6e5 | 12239 | ret = 0; |
86c8bbbe | 12240 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12241 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12242 | if (ret) { |
12243 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12244 | return ret; | |
12245 | } | |
12246 | } | |
12247 | ||
12248 | if (dev_priv->display.compute_intermediate_wm && | |
12249 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12250 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12251 | return 0; | |
12252 | ||
12253 | /* | |
12254 | * Calculate 'intermediate' watermarks that satisfy both the | |
12255 | * old state and the new state. We can program these | |
12256 | * immediately. | |
12257 | */ | |
12258 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12259 | intel_crtc, | |
12260 | pipe_config); | |
12261 | if (ret) { | |
12262 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12263 | return ret; |
ed4a6a7c | 12264 | } |
e3d5457c VS |
12265 | } else if (dev_priv->display.compute_intermediate_wm) { |
12266 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12267 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12268 | } |
12269 | ||
e435d6e5 ML |
12270 | if (INTEL_INFO(dev)->gen >= 9) { |
12271 | if (mode_changed) | |
12272 | ret = skl_update_scaler_crtc(pipe_config); | |
12273 | ||
12274 | if (!ret) | |
12275 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12276 | pipe_config); | |
12277 | } | |
12278 | ||
12279 | return ret; | |
6d3a1ce7 ML |
12280 | } |
12281 | ||
65b38e0d | 12282 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12283 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12284 | .atomic_begin = intel_begin_crtc_commit, |
12285 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12286 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12287 | }; |
12288 | ||
d29b2f9d ACO |
12289 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12290 | { | |
12291 | struct intel_connector *connector; | |
12292 | ||
12293 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12294 | if (connector->base.state->crtc) |
12295 | drm_connector_unreference(&connector->base); | |
12296 | ||
d29b2f9d ACO |
12297 | if (connector->base.encoder) { |
12298 | connector->base.state->best_encoder = | |
12299 | connector->base.encoder; | |
12300 | connector->base.state->crtc = | |
12301 | connector->base.encoder->crtc; | |
8863dc7f DV |
12302 | |
12303 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12304 | } else { |
12305 | connector->base.state->best_encoder = NULL; | |
12306 | connector->base.state->crtc = NULL; | |
12307 | } | |
12308 | } | |
12309 | } | |
12310 | ||
050f7aeb | 12311 | static void |
eba905b2 | 12312 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12313 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12314 | { |
12315 | int bpp = pipe_config->pipe_bpp; | |
12316 | ||
12317 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12318 | connector->base.base.id, | |
c23cc417 | 12319 | connector->base.name); |
050f7aeb DV |
12320 | |
12321 | /* Don't use an invalid EDID bpc value */ | |
12322 | if (connector->base.display_info.bpc && | |
12323 | connector->base.display_info.bpc * 3 < bpp) { | |
12324 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12325 | bpp, connector->base.display_info.bpc*3); | |
12326 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12327 | } | |
12328 | ||
013dd9e0 JN |
12329 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12330 | if (connector->base.display_info.bpc == 0) { | |
12331 | int type = connector->base.connector_type; | |
12332 | int clamp_bpp = 24; | |
12333 | ||
12334 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12335 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12336 | type == DRM_MODE_CONNECTOR_eDP) | |
12337 | clamp_bpp = 18; | |
12338 | ||
12339 | if (bpp > clamp_bpp) { | |
12340 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12341 | bpp, clamp_bpp); | |
12342 | pipe_config->pipe_bpp = clamp_bpp; | |
12343 | } | |
050f7aeb DV |
12344 | } |
12345 | } | |
12346 | ||
4e53c2e0 | 12347 | static int |
050f7aeb | 12348 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12349 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12350 | { |
050f7aeb | 12351 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12352 | struct drm_atomic_state *state; |
da3ced29 ACO |
12353 | struct drm_connector *connector; |
12354 | struct drm_connector_state *connector_state; | |
1486017f | 12355 | int bpp, i; |
4e53c2e0 | 12356 | |
666a4537 | 12357 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12358 | bpp = 10*3; |
d328c9d7 DV |
12359 | else if (INTEL_INFO(dev)->gen >= 5) |
12360 | bpp = 12*3; | |
12361 | else | |
12362 | bpp = 8*3; | |
12363 | ||
4e53c2e0 | 12364 | |
4e53c2e0 DV |
12365 | pipe_config->pipe_bpp = bpp; |
12366 | ||
1486017f ACO |
12367 | state = pipe_config->base.state; |
12368 | ||
4e53c2e0 | 12369 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12370 | for_each_connector_in_state(state, connector, connector_state, i) { |
12371 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12372 | continue; |
12373 | ||
da3ced29 ACO |
12374 | connected_sink_compute_bpp(to_intel_connector(connector), |
12375 | pipe_config); | |
4e53c2e0 DV |
12376 | } |
12377 | ||
12378 | return bpp; | |
12379 | } | |
12380 | ||
644db711 DV |
12381 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12382 | { | |
12383 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12384 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12385 | mode->crtc_clock, |
644db711 DV |
12386 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12387 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12388 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12389 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12390 | } | |
12391 | ||
c0b03411 | 12392 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12393 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12394 | const char *context) |
12395 | { | |
6a60cd87 CK |
12396 | struct drm_device *dev = crtc->base.dev; |
12397 | struct drm_plane *plane; | |
12398 | struct intel_plane *intel_plane; | |
12399 | struct intel_plane_state *state; | |
12400 | struct drm_framebuffer *fb; | |
12401 | ||
78108b7c VS |
12402 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12403 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12404 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12405 | |
da205630 | 12406 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12407 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12408 | pipe_config->pipe_bpp, pipe_config->dither); | |
12409 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12410 | pipe_config->has_pch_encoder, | |
12411 | pipe_config->fdi_lanes, | |
12412 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12413 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12414 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12415 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12416 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12417 | pipe_config->lane_count, |
eb14cb74 VS |
12418 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12419 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12420 | pipe_config->dp_m_n.tu); | |
b95af8be | 12421 | |
90a6b7b0 | 12422 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12423 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12424 | pipe_config->lane_count, |
b95af8be VK |
12425 | pipe_config->dp_m2_n2.gmch_m, |
12426 | pipe_config->dp_m2_n2.gmch_n, | |
12427 | pipe_config->dp_m2_n2.link_m, | |
12428 | pipe_config->dp_m2_n2.link_n, | |
12429 | pipe_config->dp_m2_n2.tu); | |
12430 | ||
55072d19 DV |
12431 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12432 | pipe_config->has_audio, | |
12433 | pipe_config->has_infoframe); | |
12434 | ||
c0b03411 | 12435 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12436 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12437 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12438 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12439 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12440 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12441 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12442 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12443 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12444 | crtc->num_scalers, | |
12445 | pipe_config->scaler_state.scaler_users, | |
12446 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12447 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12448 | pipe_config->gmch_pfit.control, | |
12449 | pipe_config->gmch_pfit.pgm_ratios, | |
12450 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12451 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12452 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12453 | pipe_config->pch_pfit.size, |
12454 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12455 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12456 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12457 | |
415ff0f6 | 12458 | if (IS_BROXTON(dev)) { |
05712c15 | 12459 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12460 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12461 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12462 | pipe_config->ddi_pll_sel, |
12463 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12464 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12465 | pipe_config->dpll_hw_state.pll0, |
12466 | pipe_config->dpll_hw_state.pll1, | |
12467 | pipe_config->dpll_hw_state.pll2, | |
12468 | pipe_config->dpll_hw_state.pll3, | |
12469 | pipe_config->dpll_hw_state.pll6, | |
12470 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12471 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12472 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12473 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12474 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12475 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12476 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12477 | pipe_config->ddi_pll_sel, | |
12478 | pipe_config->dpll_hw_state.ctrl1, | |
12479 | pipe_config->dpll_hw_state.cfgcr1, | |
12480 | pipe_config->dpll_hw_state.cfgcr2); | |
12481 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12482 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12483 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12484 | pipe_config->dpll_hw_state.wrpll, |
12485 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12486 | } else { |
12487 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12488 | "fp0: 0x%x, fp1: 0x%x\n", | |
12489 | pipe_config->dpll_hw_state.dpll, | |
12490 | pipe_config->dpll_hw_state.dpll_md, | |
12491 | pipe_config->dpll_hw_state.fp0, | |
12492 | pipe_config->dpll_hw_state.fp1); | |
12493 | } | |
12494 | ||
6a60cd87 CK |
12495 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12496 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12497 | intel_plane = to_intel_plane(plane); | |
12498 | if (intel_plane->pipe != crtc->pipe) | |
12499 | continue; | |
12500 | ||
12501 | state = to_intel_plane_state(plane->state); | |
12502 | fb = state->base.fb; | |
12503 | if (!fb) { | |
1d577e02 VS |
12504 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12505 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12506 | continue; |
12507 | } | |
12508 | ||
1d577e02 VS |
12509 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12510 | plane->base.id, plane->name); | |
12511 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
12512 | fb->base.id, fb->width, fb->height, | |
12513 | drm_get_format_name(fb->pixel_format)); | |
12514 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12515 | state->scaler_id, | |
12516 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12517 | drm_rect_width(&state->src) >> 16, | |
12518 | drm_rect_height(&state->src) >> 16, | |
12519 | state->dst.x1, state->dst.y1, | |
12520 | drm_rect_width(&state->dst), | |
12521 | drm_rect_height(&state->dst)); | |
6a60cd87 | 12522 | } |
c0b03411 DV |
12523 | } |
12524 | ||
5448a00d | 12525 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12526 | { |
5448a00d | 12527 | struct drm_device *dev = state->dev; |
da3ced29 | 12528 | struct drm_connector *connector; |
00f0b378 | 12529 | unsigned int used_ports = 0; |
477321e0 | 12530 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12531 | |
12532 | /* | |
12533 | * Walk the connector list instead of the encoder | |
12534 | * list to detect the problem on ddi platforms | |
12535 | * where there's just one encoder per digital port. | |
12536 | */ | |
0bff4858 VS |
12537 | drm_for_each_connector(connector, dev) { |
12538 | struct drm_connector_state *connector_state; | |
12539 | struct intel_encoder *encoder; | |
12540 | ||
12541 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12542 | if (!connector_state) | |
12543 | connector_state = connector->state; | |
12544 | ||
5448a00d | 12545 | if (!connector_state->best_encoder) |
00f0b378 VS |
12546 | continue; |
12547 | ||
5448a00d ACO |
12548 | encoder = to_intel_encoder(connector_state->best_encoder); |
12549 | ||
12550 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12551 | |
12552 | switch (encoder->type) { | |
12553 | unsigned int port_mask; | |
12554 | case INTEL_OUTPUT_UNKNOWN: | |
12555 | if (WARN_ON(!HAS_DDI(dev))) | |
12556 | break; | |
cca0502b | 12557 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12558 | case INTEL_OUTPUT_HDMI: |
12559 | case INTEL_OUTPUT_EDP: | |
12560 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12561 | ||
12562 | /* the same port mustn't appear more than once */ | |
12563 | if (used_ports & port_mask) | |
12564 | return false; | |
12565 | ||
12566 | used_ports |= port_mask; | |
477321e0 VS |
12567 | break; |
12568 | case INTEL_OUTPUT_DP_MST: | |
12569 | used_mst_ports |= | |
12570 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12571 | break; | |
00f0b378 VS |
12572 | default: |
12573 | break; | |
12574 | } | |
12575 | } | |
12576 | ||
477321e0 VS |
12577 | /* can't mix MST and SST/HDMI on the same port */ |
12578 | if (used_ports & used_mst_ports) | |
12579 | return false; | |
12580 | ||
00f0b378 VS |
12581 | return true; |
12582 | } | |
12583 | ||
83a57153 ACO |
12584 | static void |
12585 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12586 | { | |
12587 | struct drm_crtc_state tmp_state; | |
663a3640 | 12588 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12589 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12590 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12591 | uint32_t ddi_pll_sel; |
c4e2d043 | 12592 | bool force_thru; |
83a57153 | 12593 | |
7546a384 ACO |
12594 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12595 | * kzalloc'd. Code that depends on any field being zero should be | |
12596 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12597 | * only fields that are know to not cause problems are preserved. */ | |
12598 | ||
83a57153 | 12599 | tmp_state = crtc_state->base; |
663a3640 | 12600 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12601 | shared_dpll = crtc_state->shared_dpll; |
12602 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12603 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12604 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12605 | |
83a57153 | 12606 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12607 | |
83a57153 | 12608 | crtc_state->base = tmp_state; |
663a3640 | 12609 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12610 | crtc_state->shared_dpll = shared_dpll; |
12611 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12612 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12613 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12614 | } |
12615 | ||
548ee15b | 12616 | static int |
b8cecdf5 | 12617 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12618 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12619 | { |
b359283a | 12620 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12621 | struct intel_encoder *encoder; |
da3ced29 | 12622 | struct drm_connector *connector; |
0b901879 | 12623 | struct drm_connector_state *connector_state; |
d328c9d7 | 12624 | int base_bpp, ret = -EINVAL; |
0b901879 | 12625 | int i; |
e29c22c0 | 12626 | bool retry = true; |
ee7b9f93 | 12627 | |
83a57153 | 12628 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12629 | |
e143a21c DV |
12630 | pipe_config->cpu_transcoder = |
12631 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12632 | |
2960bc9c ID |
12633 | /* |
12634 | * Sanitize sync polarity flags based on requested ones. If neither | |
12635 | * positive or negative polarity is requested, treat this as meaning | |
12636 | * negative polarity. | |
12637 | */ | |
2d112de7 | 12638 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12639 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12640 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12641 | |
2d112de7 | 12642 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12643 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12644 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12645 | |
d328c9d7 DV |
12646 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12647 | pipe_config); | |
12648 | if (base_bpp < 0) | |
4e53c2e0 DV |
12649 | goto fail; |
12650 | ||
e41a56be VS |
12651 | /* |
12652 | * Determine the real pipe dimensions. Note that stereo modes can | |
12653 | * increase the actual pipe size due to the frame doubling and | |
12654 | * insertion of additional space for blanks between the frame. This | |
12655 | * is stored in the crtc timings. We use the requested mode to do this | |
12656 | * computation to clearly distinguish it from the adjusted mode, which | |
12657 | * can be changed by the connectors in the below retry loop. | |
12658 | */ | |
2d112de7 | 12659 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12660 | &pipe_config->pipe_src_w, |
12661 | &pipe_config->pipe_src_h); | |
e41a56be | 12662 | |
253c84c8 VS |
12663 | for_each_connector_in_state(state, connector, connector_state, i) { |
12664 | if (connector_state->crtc != crtc) | |
12665 | continue; | |
12666 | ||
12667 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12668 | ||
e25148d0 VS |
12669 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
12670 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12671 | goto fail; | |
12672 | } | |
12673 | ||
253c84c8 VS |
12674 | /* |
12675 | * Determine output_types before calling the .compute_config() | |
12676 | * hooks so that the hooks can use this information safely. | |
12677 | */ | |
12678 | pipe_config->output_types |= 1 << encoder->type; | |
12679 | } | |
12680 | ||
e29c22c0 | 12681 | encoder_retry: |
ef1b460d | 12682 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12683 | pipe_config->port_clock = 0; |
ef1b460d | 12684 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12685 | |
135c81b8 | 12686 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12687 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12688 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12689 | |
7758a113 DV |
12690 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12691 | * adjust it according to limitations or connector properties, and also | |
12692 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12693 | */ |
da3ced29 | 12694 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12695 | if (connector_state->crtc != crtc) |
7758a113 | 12696 | continue; |
7ae89233 | 12697 | |
0b901879 ACO |
12698 | encoder = to_intel_encoder(connector_state->best_encoder); |
12699 | ||
efea6e8e DV |
12700 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12701 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12702 | goto fail; |
12703 | } | |
ee7b9f93 | 12704 | } |
47f1c6c9 | 12705 | |
ff9a6750 DV |
12706 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12707 | * done afterwards in case the encoder adjusts the mode. */ | |
12708 | if (!pipe_config->port_clock) | |
2d112de7 | 12709 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12710 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12711 | |
a43f6e0f | 12712 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12713 | if (ret < 0) { |
7758a113 DV |
12714 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12715 | goto fail; | |
ee7b9f93 | 12716 | } |
e29c22c0 DV |
12717 | |
12718 | if (ret == RETRY) { | |
12719 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12720 | ret = -EINVAL; | |
12721 | goto fail; | |
12722 | } | |
12723 | ||
12724 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12725 | retry = false; | |
12726 | goto encoder_retry; | |
12727 | } | |
12728 | ||
e8fa4270 DV |
12729 | /* Dithering seems to not pass-through bits correctly when it should, so |
12730 | * only enable it on 6bpc panels. */ | |
12731 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12732 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12733 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12734 | |
7758a113 | 12735 | fail: |
548ee15b | 12736 | return ret; |
ee7b9f93 | 12737 | } |
47f1c6c9 | 12738 | |
ea9d758d | 12739 | static void |
4740b0f2 | 12740 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12741 | { |
0a9ab303 ACO |
12742 | struct drm_crtc *crtc; |
12743 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12744 | int i; |
ea9d758d | 12745 | |
7668851f | 12746 | /* Double check state. */ |
8a75d157 | 12747 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12748 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12749 | |
12750 | /* Update hwmode for vblank functions */ | |
12751 | if (crtc->state->active) | |
12752 | crtc->hwmode = crtc->state->adjusted_mode; | |
12753 | else | |
12754 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12755 | |
12756 | /* | |
12757 | * Update legacy state to satisfy fbc code. This can | |
12758 | * be removed when fbc uses the atomic state. | |
12759 | */ | |
12760 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12761 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12762 | ||
12763 | crtc->primary->fb = plane_state->fb; | |
12764 | crtc->x = plane_state->src_x >> 16; | |
12765 | crtc->y = plane_state->src_y >> 16; | |
12766 | } | |
ea9d758d | 12767 | } |
ea9d758d DV |
12768 | } |
12769 | ||
3bd26263 | 12770 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12771 | { |
3bd26263 | 12772 | int diff; |
f1f644dc JB |
12773 | |
12774 | if (clock1 == clock2) | |
12775 | return true; | |
12776 | ||
12777 | if (!clock1 || !clock2) | |
12778 | return false; | |
12779 | ||
12780 | diff = abs(clock1 - clock2); | |
12781 | ||
12782 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12783 | return true; | |
12784 | ||
12785 | return false; | |
12786 | } | |
12787 | ||
25c5b266 DV |
12788 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12789 | list_for_each_entry((intel_crtc), \ | |
12790 | &(dev)->mode_config.crtc_list, \ | |
12791 | base.head) \ | |
95150bdf | 12792 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12793 | |
cfb23ed6 ML |
12794 | static bool |
12795 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12796 | unsigned int m2, unsigned int n2, | |
12797 | bool exact) | |
12798 | { | |
12799 | if (m == m2 && n == n2) | |
12800 | return true; | |
12801 | ||
12802 | if (exact || !m || !n || !m2 || !n2) | |
12803 | return false; | |
12804 | ||
12805 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12806 | ||
31d10b57 ML |
12807 | if (n > n2) { |
12808 | while (n > n2) { | |
cfb23ed6 ML |
12809 | m2 <<= 1; |
12810 | n2 <<= 1; | |
12811 | } | |
31d10b57 ML |
12812 | } else if (n < n2) { |
12813 | while (n < n2) { | |
cfb23ed6 ML |
12814 | m <<= 1; |
12815 | n <<= 1; | |
12816 | } | |
12817 | } | |
12818 | ||
31d10b57 ML |
12819 | if (n != n2) |
12820 | return false; | |
12821 | ||
12822 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12823 | } |
12824 | ||
12825 | static bool | |
12826 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12827 | struct intel_link_m_n *m2_n2, | |
12828 | bool adjust) | |
12829 | { | |
12830 | if (m_n->tu == m2_n2->tu && | |
12831 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12832 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12833 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12834 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12835 | if (adjust) | |
12836 | *m2_n2 = *m_n; | |
12837 | ||
12838 | return true; | |
12839 | } | |
12840 | ||
12841 | return false; | |
12842 | } | |
12843 | ||
0e8ffe1b | 12844 | static bool |
2fa2fe9a | 12845 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12846 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12847 | struct intel_crtc_state *pipe_config, |
12848 | bool adjust) | |
0e8ffe1b | 12849 | { |
cfb23ed6 ML |
12850 | bool ret = true; |
12851 | ||
12852 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12853 | do { \ | |
12854 | if (!adjust) \ | |
12855 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12856 | else \ | |
12857 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12858 | } while (0) | |
12859 | ||
66e985c0 DV |
12860 | #define PIPE_CONF_CHECK_X(name) \ |
12861 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12862 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12863 | "(expected 0x%08x, found 0x%08x)\n", \ |
12864 | current_config->name, \ | |
12865 | pipe_config->name); \ | |
cfb23ed6 | 12866 | ret = false; \ |
66e985c0 DV |
12867 | } |
12868 | ||
08a24034 DV |
12869 | #define PIPE_CONF_CHECK_I(name) \ |
12870 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12871 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12872 | "(expected %i, found %i)\n", \ |
12873 | current_config->name, \ | |
12874 | pipe_config->name); \ | |
cfb23ed6 ML |
12875 | ret = false; \ |
12876 | } | |
12877 | ||
8106ddbd ACO |
12878 | #define PIPE_CONF_CHECK_P(name) \ |
12879 | if (current_config->name != pipe_config->name) { \ | |
12880 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12881 | "(expected %p, found %p)\n", \ | |
12882 | current_config->name, \ | |
12883 | pipe_config->name); \ | |
12884 | ret = false; \ | |
12885 | } | |
12886 | ||
cfb23ed6 ML |
12887 | #define PIPE_CONF_CHECK_M_N(name) \ |
12888 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12889 | &pipe_config->name,\ | |
12890 | adjust)) { \ | |
12891 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12892 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12893 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12894 | current_config->name.tu, \ | |
12895 | current_config->name.gmch_m, \ | |
12896 | current_config->name.gmch_n, \ | |
12897 | current_config->name.link_m, \ | |
12898 | current_config->name.link_n, \ | |
12899 | pipe_config->name.tu, \ | |
12900 | pipe_config->name.gmch_m, \ | |
12901 | pipe_config->name.gmch_n, \ | |
12902 | pipe_config->name.link_m, \ | |
12903 | pipe_config->name.link_n); \ | |
12904 | ret = false; \ | |
12905 | } | |
12906 | ||
55c561a7 DV |
12907 | /* This is required for BDW+ where there is only one set of registers for |
12908 | * switching between high and low RR. | |
12909 | * This macro can be used whenever a comparison has to be made between one | |
12910 | * hw state and multiple sw state variables. | |
12911 | */ | |
cfb23ed6 ML |
12912 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12913 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12914 | &pipe_config->name, adjust) && \ | |
12915 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12916 | &pipe_config->name, adjust)) { \ | |
12917 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12918 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12919 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12920 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12921 | current_config->name.tu, \ | |
12922 | current_config->name.gmch_m, \ | |
12923 | current_config->name.gmch_n, \ | |
12924 | current_config->name.link_m, \ | |
12925 | current_config->name.link_n, \ | |
12926 | current_config->alt_name.tu, \ | |
12927 | current_config->alt_name.gmch_m, \ | |
12928 | current_config->alt_name.gmch_n, \ | |
12929 | current_config->alt_name.link_m, \ | |
12930 | current_config->alt_name.link_n, \ | |
12931 | pipe_config->name.tu, \ | |
12932 | pipe_config->name.gmch_m, \ | |
12933 | pipe_config->name.gmch_n, \ | |
12934 | pipe_config->name.link_m, \ | |
12935 | pipe_config->name.link_n); \ | |
12936 | ret = false; \ | |
88adfff1 DV |
12937 | } |
12938 | ||
1bd1bd80 DV |
12939 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12940 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12941 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12942 | "(expected %i, found %i)\n", \ |
12943 | current_config->name & (mask), \ | |
12944 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12945 | ret = false; \ |
1bd1bd80 DV |
12946 | } |
12947 | ||
5e550656 VS |
12948 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12949 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12950 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12951 | "(expected %i, found %i)\n", \ |
12952 | current_config->name, \ | |
12953 | pipe_config->name); \ | |
cfb23ed6 | 12954 | ret = false; \ |
5e550656 VS |
12955 | } |
12956 | ||
bb760063 DV |
12957 | #define PIPE_CONF_QUIRK(quirk) \ |
12958 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12959 | ||
eccb140b DV |
12960 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12961 | ||
08a24034 DV |
12962 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12963 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12964 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12965 | |
90a6b7b0 | 12966 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 12967 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
12968 | |
12969 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12970 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12971 | ||
cfb23ed6 ML |
12972 | if (current_config->has_drrs) |
12973 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12974 | } else | |
12975 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12976 | |
253c84c8 | 12977 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 12978 | |
2d112de7 ACO |
12979 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12980 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12981 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12982 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12983 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12984 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12985 | |
2d112de7 ACO |
12986 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12987 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12988 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12989 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12990 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12991 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12992 | |
c93f54cf | 12993 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12994 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12995 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12996 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12997 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12998 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12999 | |
9ed109a7 DV |
13000 | PIPE_CONF_CHECK_I(has_audio); |
13001 | ||
2d112de7 | 13002 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
13003 | DRM_MODE_FLAG_INTERLACE); |
13004 | ||
bb760063 | 13005 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13006 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13007 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13008 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13009 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13010 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13011 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13012 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13013 | DRM_MODE_FLAG_NVSYNC); |
13014 | } | |
045ac3b5 | 13015 | |
333b8ca8 | 13016 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
13017 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
13018 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 13019 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13020 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13021 | |
bfd16b2a ML |
13022 | if (!adjust) { |
13023 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13024 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13025 | ||
13026 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13027 | if (current_config->pch_pfit.enabled) { | |
13028 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13029 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13030 | } | |
2fa2fe9a | 13031 | |
7aefe2b5 ML |
13032 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13033 | } | |
a1b2278e | 13034 | |
e59150dc JB |
13035 | /* BDW+ don't expose a synchronous way to read the state */ |
13036 | if (IS_HASWELL(dev)) | |
13037 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 13038 | |
282740f7 VS |
13039 | PIPE_CONF_CHECK_I(double_wide); |
13040 | ||
26804afd DV |
13041 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
13042 | ||
8106ddbd | 13043 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13044 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13045 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13046 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13047 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13048 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13049 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13050 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13051 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13052 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13053 | |
47eacbab VS |
13054 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13055 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13056 | ||
42571aef VS |
13057 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
13058 | PIPE_CONF_CHECK_I(pipe_bpp); | |
13059 | ||
2d112de7 | 13060 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13061 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13062 | |
66e985c0 | 13063 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13064 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13065 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13066 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13067 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13068 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 13069 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 13070 | |
cfb23ed6 | 13071 | return ret; |
0e8ffe1b DV |
13072 | } |
13073 | ||
e3b247da VS |
13074 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13075 | const struct intel_crtc_state *pipe_config) | |
13076 | { | |
13077 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13078 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13079 | &pipe_config->fdi_m_n); |
13080 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13081 | ||
13082 | /* | |
13083 | * FDI already provided one idea for the dotclock. | |
13084 | * Yell if the encoder disagrees. | |
13085 | */ | |
13086 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13087 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13088 | fdi_dotclock, dotclock); | |
13089 | } | |
13090 | } | |
13091 | ||
c0ead703 ML |
13092 | static void verify_wm_state(struct drm_crtc *crtc, |
13093 | struct drm_crtc_state *new_state) | |
08db6652 | 13094 | { |
e7c84544 | 13095 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13096 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 13097 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
e7c84544 ML |
13098 | struct skl_ddb_entry *hw_entry, *sw_entry; |
13099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13100 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
13101 | int plane; |
13102 | ||
e7c84544 | 13103 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
13104 | return; |
13105 | ||
13106 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
13107 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13108 | ||
e7c84544 ML |
13109 | /* planes */ |
13110 | for_each_plane(dev_priv, pipe, plane) { | |
13111 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
13112 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 13113 | |
e7c84544 | 13114 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
13115 | continue; |
13116 | ||
e7c84544 ML |
13117 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
13118 | "(expected (%u,%u), found (%u,%u))\n", | |
13119 | pipe_name(pipe), plane + 1, | |
13120 | sw_entry->start, sw_entry->end, | |
13121 | hw_entry->start, hw_entry->end); | |
13122 | } | |
08db6652 | 13123 | |
e7c84544 ML |
13124 | /* cursor */ |
13125 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13126 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 13127 | |
e7c84544 | 13128 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
13129 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
13130 | "(expected (%u,%u), found (%u,%u))\n", | |
13131 | pipe_name(pipe), | |
13132 | sw_entry->start, sw_entry->end, | |
13133 | hw_entry->start, hw_entry->end); | |
13134 | } | |
13135 | } | |
13136 | ||
91d1b4bd | 13137 | static void |
c0ead703 | 13138 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 13139 | { |
35dd3c64 | 13140 | struct drm_connector *connector; |
8af6cf88 | 13141 | |
e7c84544 | 13142 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
13143 | struct drm_encoder *encoder = connector->encoder; |
13144 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13145 | |
e7c84544 ML |
13146 | if (state->crtc != crtc) |
13147 | continue; | |
13148 | ||
5a21b665 | 13149 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13150 | |
ad3c558f | 13151 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13152 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13153 | } |
91d1b4bd DV |
13154 | } |
13155 | ||
13156 | static void | |
c0ead703 | 13157 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13158 | { |
13159 | struct intel_encoder *encoder; | |
13160 | struct intel_connector *connector; | |
8af6cf88 | 13161 | |
b2784e15 | 13162 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13163 | bool enabled = false; |
4d20cd86 | 13164 | enum pipe pipe; |
8af6cf88 DV |
13165 | |
13166 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13167 | encoder->base.base.id, | |
8e329a03 | 13168 | encoder->base.name); |
8af6cf88 | 13169 | |
3a3371ff | 13170 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13171 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13172 | continue; |
13173 | enabled = true; | |
ad3c558f ML |
13174 | |
13175 | I915_STATE_WARN(connector->base.state->crtc != | |
13176 | encoder->base.crtc, | |
13177 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13178 | } |
0e32b39c | 13179 | |
e2c719b7 | 13180 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13181 | "encoder's enabled state mismatch " |
13182 | "(expected %i, found %i)\n", | |
13183 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13184 | |
13185 | if (!encoder->base.crtc) { | |
4d20cd86 | 13186 | bool active; |
7c60d198 | 13187 | |
4d20cd86 ML |
13188 | active = encoder->get_hw_state(encoder, &pipe); |
13189 | I915_STATE_WARN(active, | |
13190 | "encoder detached but still enabled on pipe %c.\n", | |
13191 | pipe_name(pipe)); | |
7c60d198 | 13192 | } |
8af6cf88 | 13193 | } |
91d1b4bd DV |
13194 | } |
13195 | ||
13196 | static void | |
c0ead703 ML |
13197 | verify_crtc_state(struct drm_crtc *crtc, |
13198 | struct drm_crtc_state *old_crtc_state, | |
13199 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13200 | { |
e7c84544 | 13201 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13202 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13203 | struct intel_encoder *encoder; |
e7c84544 ML |
13204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13205 | struct intel_crtc_state *pipe_config, *sw_config; | |
13206 | struct drm_atomic_state *old_state; | |
13207 | bool active; | |
045ac3b5 | 13208 | |
e7c84544 | 13209 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13210 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13211 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13212 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13213 | pipe_config->base.crtc = crtc; | |
13214 | pipe_config->base.state = old_state; | |
8af6cf88 | 13215 | |
78108b7c | 13216 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13217 | |
e7c84544 | 13218 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13219 | |
e7c84544 ML |
13220 | /* hw state is inconsistent with the pipe quirk */ |
13221 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13222 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13223 | active = new_crtc_state->active; | |
6c49f241 | 13224 | |
e7c84544 ML |
13225 | I915_STATE_WARN(new_crtc_state->active != active, |
13226 | "crtc active state doesn't match with hw state " | |
13227 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13228 | |
e7c84544 ML |
13229 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13230 | "transitional active state does not match atomic hw state " | |
13231 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13232 | |
e7c84544 ML |
13233 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13234 | enum pipe pipe; | |
4d20cd86 | 13235 | |
e7c84544 ML |
13236 | active = encoder->get_hw_state(encoder, &pipe); |
13237 | I915_STATE_WARN(active != new_crtc_state->active, | |
13238 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13239 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13240 | |
e7c84544 ML |
13241 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13242 | "Encoder connected to wrong pipe %c\n", | |
13243 | pipe_name(pipe)); | |
4d20cd86 | 13244 | |
253c84c8 VS |
13245 | if (active) { |
13246 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13247 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13248 | } |
e7c84544 | 13249 | } |
53d9f4e9 | 13250 | |
e7c84544 ML |
13251 | if (!new_crtc_state->active) |
13252 | return; | |
cfb23ed6 | 13253 | |
e7c84544 | 13254 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13255 | |
e7c84544 ML |
13256 | sw_config = to_intel_crtc_state(crtc->state); |
13257 | if (!intel_pipe_config_compare(dev, sw_config, | |
13258 | pipe_config, false)) { | |
13259 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13260 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13261 | "[hw state]"); | |
13262 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13263 | "[sw state]"); | |
8af6cf88 DV |
13264 | } |
13265 | } | |
13266 | ||
91d1b4bd | 13267 | static void |
c0ead703 ML |
13268 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13269 | struct intel_shared_dpll *pll, | |
13270 | struct drm_crtc *crtc, | |
13271 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13272 | { |
91d1b4bd | 13273 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13274 | unsigned crtc_mask; |
13275 | bool active; | |
5358901f | 13276 | |
e7c84544 | 13277 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13278 | |
e7c84544 | 13279 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13280 | |
e7c84544 | 13281 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13282 | |
e7c84544 ML |
13283 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13284 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13285 | "pll in active use but not on in sw tracking\n"); | |
13286 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13287 | "pll is on but not used by any active crtc\n"); | |
13288 | I915_STATE_WARN(pll->on != active, | |
13289 | "pll on state mismatch (expected %i, found %i)\n", | |
13290 | pll->on, active); | |
13291 | } | |
5358901f | 13292 | |
e7c84544 | 13293 | if (!crtc) { |
2dd66ebd | 13294 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13295 | "more active pll users than references: %x vs %x\n", |
13296 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13297 | |
e7c84544 ML |
13298 | return; |
13299 | } | |
13300 | ||
13301 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13302 | ||
13303 | if (new_state->active) | |
13304 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13305 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13306 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13307 | else | |
13308 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13309 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13310 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13311 | |
e7c84544 ML |
13312 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13313 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13314 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13315 | |
e7c84544 ML |
13316 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13317 | &dpll_hw_state, | |
13318 | sizeof(dpll_hw_state)), | |
13319 | "pll hw state mismatch\n"); | |
13320 | } | |
13321 | ||
13322 | static void | |
c0ead703 ML |
13323 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13324 | struct drm_crtc_state *old_crtc_state, | |
13325 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13326 | { |
fac5e23e | 13327 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13328 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13329 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13330 | ||
13331 | if (new_state->shared_dpll) | |
c0ead703 | 13332 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13333 | |
13334 | if (old_state->shared_dpll && | |
13335 | old_state->shared_dpll != new_state->shared_dpll) { | |
13336 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13337 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13338 | ||
13339 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13340 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13341 | pipe_name(drm_crtc_index(crtc))); | |
13342 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13343 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13344 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13345 | } |
8af6cf88 DV |
13346 | } |
13347 | ||
e7c84544 | 13348 | static void |
c0ead703 | 13349 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13350 | struct drm_crtc_state *old_state, |
13351 | struct drm_crtc_state *new_state) | |
13352 | { | |
5a21b665 DV |
13353 | if (!needs_modeset(new_state) && |
13354 | !to_intel_crtc_state(new_state)->update_pipe) | |
13355 | return; | |
13356 | ||
c0ead703 | 13357 | verify_wm_state(crtc, new_state); |
5a21b665 | 13358 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13359 | verify_crtc_state(crtc, old_state, new_state); |
13360 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13361 | } |
13362 | ||
13363 | static void | |
c0ead703 | 13364 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13365 | { |
fac5e23e | 13366 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13367 | int i; |
13368 | ||
13369 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13370 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13371 | } |
13372 | ||
13373 | static void | |
c0ead703 | 13374 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13375 | { |
c0ead703 ML |
13376 | verify_encoder_state(dev); |
13377 | verify_connector_state(dev, NULL); | |
13378 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13379 | } |
13380 | ||
80715b2f VS |
13381 | static void update_scanline_offset(struct intel_crtc *crtc) |
13382 | { | |
13383 | struct drm_device *dev = crtc->base.dev; | |
13384 | ||
13385 | /* | |
13386 | * The scanline counter increments at the leading edge of hsync. | |
13387 | * | |
13388 | * On most platforms it starts counting from vtotal-1 on the | |
13389 | * first active line. That means the scanline counter value is | |
13390 | * always one less than what we would expect. Ie. just after | |
13391 | * start of vblank, which also occurs at start of hsync (on the | |
13392 | * last active line), the scanline counter will read vblank_start-1. | |
13393 | * | |
13394 | * On gen2 the scanline counter starts counting from 1 instead | |
13395 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13396 | * to keep the value positive), instead of adding one. | |
13397 | * | |
13398 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13399 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13400 | * there's an extra 1 line difference. So we need to add two instead of | |
13401 | * one to the value. | |
13402 | */ | |
13403 | if (IS_GEN2(dev)) { | |
124abe07 | 13404 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13405 | int vtotal; |
13406 | ||
124abe07 VS |
13407 | vtotal = adjusted_mode->crtc_vtotal; |
13408 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13409 | vtotal /= 2; |
13410 | ||
13411 | crtc->scanline_offset = vtotal - 1; | |
13412 | } else if (HAS_DDI(dev) && | |
2d84d2b3 | 13413 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13414 | crtc->scanline_offset = 2; |
13415 | } else | |
13416 | crtc->scanline_offset = 1; | |
13417 | } | |
13418 | ||
ad421372 | 13419 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13420 | { |
225da59b | 13421 | struct drm_device *dev = state->dev; |
ed6739ef | 13422 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13423 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13424 | struct drm_crtc *crtc; |
13425 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13426 | int i; |
ed6739ef ACO |
13427 | |
13428 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13429 | return; |
ed6739ef | 13430 | |
0a9ab303 | 13431 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13432 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13433 | struct intel_shared_dpll *old_dpll = |
13434 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13435 | |
fb1a38a9 | 13436 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13437 | continue; |
13438 | ||
8106ddbd | 13439 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13440 | |
8106ddbd | 13441 | if (!old_dpll) |
fb1a38a9 | 13442 | continue; |
0a9ab303 | 13443 | |
ad421372 ML |
13444 | if (!shared_dpll) |
13445 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13446 | |
8106ddbd | 13447 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13448 | } |
ed6739ef ACO |
13449 | } |
13450 | ||
99d736a2 ML |
13451 | /* |
13452 | * This implements the workaround described in the "notes" section of the mode | |
13453 | * set sequence documentation. When going from no pipes or single pipe to | |
13454 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13455 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13456 | */ | |
13457 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13458 | { | |
13459 | struct drm_crtc_state *crtc_state; | |
13460 | struct intel_crtc *intel_crtc; | |
13461 | struct drm_crtc *crtc; | |
13462 | struct intel_crtc_state *first_crtc_state = NULL; | |
13463 | struct intel_crtc_state *other_crtc_state = NULL; | |
13464 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13465 | int i; | |
13466 | ||
13467 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13468 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13469 | intel_crtc = to_intel_crtc(crtc); | |
13470 | ||
13471 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13472 | continue; | |
13473 | ||
13474 | if (first_crtc_state) { | |
13475 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13476 | break; | |
13477 | } else { | |
13478 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13479 | first_pipe = intel_crtc->pipe; | |
13480 | } | |
13481 | } | |
13482 | ||
13483 | /* No workaround needed? */ | |
13484 | if (!first_crtc_state) | |
13485 | return 0; | |
13486 | ||
13487 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13488 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13489 | struct intel_crtc_state *pipe_config; | |
13490 | ||
13491 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13492 | if (IS_ERR(pipe_config)) | |
13493 | return PTR_ERR(pipe_config); | |
13494 | ||
13495 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13496 | ||
13497 | if (!pipe_config->base.active || | |
13498 | needs_modeset(&pipe_config->base)) | |
13499 | continue; | |
13500 | ||
13501 | /* 2 or more enabled crtcs means no need for w/a */ | |
13502 | if (enabled_pipe != INVALID_PIPE) | |
13503 | return 0; | |
13504 | ||
13505 | enabled_pipe = intel_crtc->pipe; | |
13506 | } | |
13507 | ||
13508 | if (enabled_pipe != INVALID_PIPE) | |
13509 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13510 | else if (other_crtc_state) | |
13511 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13512 | ||
13513 | return 0; | |
13514 | } | |
13515 | ||
27c329ed ML |
13516 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13517 | { | |
13518 | struct drm_crtc *crtc; | |
13519 | struct drm_crtc_state *crtc_state; | |
13520 | int ret = 0; | |
13521 | ||
13522 | /* add all active pipes to the state */ | |
13523 | for_each_crtc(state->dev, crtc) { | |
13524 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13525 | if (IS_ERR(crtc_state)) | |
13526 | return PTR_ERR(crtc_state); | |
13527 | ||
13528 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13529 | continue; | |
13530 | ||
13531 | crtc_state->mode_changed = true; | |
13532 | ||
13533 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13534 | if (ret) | |
13535 | break; | |
13536 | ||
13537 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13538 | if (ret) | |
13539 | break; | |
13540 | } | |
13541 | ||
13542 | return ret; | |
13543 | } | |
13544 | ||
c347a676 | 13545 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13546 | { |
565602d7 | 13547 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13548 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13549 | struct drm_crtc *crtc; |
13550 | struct drm_crtc_state *crtc_state; | |
13551 | int ret = 0, i; | |
054518dd | 13552 | |
b359283a ML |
13553 | if (!check_digital_port_conflicts(state)) { |
13554 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13555 | return -EINVAL; | |
13556 | } | |
13557 | ||
565602d7 ML |
13558 | intel_state->modeset = true; |
13559 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13560 | ||
13561 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13562 | if (crtc_state->active) | |
13563 | intel_state->active_crtcs |= 1 << i; | |
13564 | else | |
13565 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13566 | |
13567 | if (crtc_state->active != crtc->state->active) | |
13568 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13569 | } |
13570 | ||
054518dd ACO |
13571 | /* |
13572 | * See if the config requires any additional preparation, e.g. | |
13573 | * to adjust global state with pipes off. We need to do this | |
13574 | * here so we can get the modeset_pipe updated config for the new | |
13575 | * mode set on this crtc. For other crtcs we need to use the | |
13576 | * adjusted_mode bits in the crtc directly. | |
13577 | */ | |
27c329ed | 13578 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13579 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13580 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13581 | if (!intel_state->cdclk_pll_vco) |
13582 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13583 | |
27c329ed | 13584 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13585 | if (ret < 0) |
13586 | return ret; | |
27c329ed | 13587 | |
c89e39f3 | 13588 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13589 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
13590 | ret = intel_modeset_all_pipes(state); |
13591 | ||
13592 | if (ret < 0) | |
054518dd | 13593 | return ret; |
e8788cbc ML |
13594 | |
13595 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13596 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13597 | } else |
1a617b77 | 13598 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13599 | |
ad421372 | 13600 | intel_modeset_clear_plls(state); |
054518dd | 13601 | |
565602d7 | 13602 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13603 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13604 | |
ad421372 | 13605 | return 0; |
c347a676 ACO |
13606 | } |
13607 | ||
aa363136 MR |
13608 | /* |
13609 | * Handle calculation of various watermark data at the end of the atomic check | |
13610 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13611 | * handlers to ensure that all derived state has been updated. | |
13612 | */ | |
55994c2c | 13613 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13614 | { |
13615 | struct drm_device *dev = state->dev; | |
98d39494 | 13616 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13617 | |
13618 | /* Is there platform-specific watermark information to calculate? */ | |
13619 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13620 | return dev_priv->display.compute_global_watermarks(state); |
13621 | ||
13622 | return 0; | |
aa363136 MR |
13623 | } |
13624 | ||
74c090b1 ML |
13625 | /** |
13626 | * intel_atomic_check - validate state object | |
13627 | * @dev: drm device | |
13628 | * @state: state to validate | |
13629 | */ | |
13630 | static int intel_atomic_check(struct drm_device *dev, | |
13631 | struct drm_atomic_state *state) | |
c347a676 | 13632 | { |
dd8b3bdb | 13633 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13634 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13635 | struct drm_crtc *crtc; |
13636 | struct drm_crtc_state *crtc_state; | |
13637 | int ret, i; | |
61333b60 | 13638 | bool any_ms = false; |
c347a676 | 13639 | |
74c090b1 | 13640 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13641 | if (ret) |
13642 | return ret; | |
13643 | ||
c347a676 | 13644 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13645 | struct intel_crtc_state *pipe_config = |
13646 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13647 | |
13648 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13649 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13650 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13651 | |
af4a879e | 13652 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13653 | continue; |
13654 | ||
af4a879e DV |
13655 | if (!crtc_state->enable) { |
13656 | any_ms = true; | |
cfb23ed6 | 13657 | continue; |
af4a879e | 13658 | } |
cfb23ed6 | 13659 | |
26495481 DV |
13660 | /* FIXME: For only active_changed we shouldn't need to do any |
13661 | * state recomputation at all. */ | |
13662 | ||
1ed51de9 DV |
13663 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13664 | if (ret) | |
13665 | return ret; | |
b359283a | 13666 | |
cfb23ed6 | 13667 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13668 | if (ret) { |
13669 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13670 | pipe_config, "[failed]"); | |
c347a676 | 13671 | return ret; |
25aa1c39 | 13672 | } |
c347a676 | 13673 | |
73831236 | 13674 | if (i915.fastboot && |
dd8b3bdb | 13675 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13676 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13677 | pipe_config, true)) { |
26495481 | 13678 | crtc_state->mode_changed = false; |
bfd16b2a | 13679 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13680 | } |
13681 | ||
af4a879e | 13682 | if (needs_modeset(crtc_state)) |
26495481 | 13683 | any_ms = true; |
cfb23ed6 | 13684 | |
af4a879e DV |
13685 | ret = drm_atomic_add_affected_planes(state, crtc); |
13686 | if (ret) | |
13687 | return ret; | |
61333b60 | 13688 | |
26495481 DV |
13689 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13690 | needs_modeset(crtc_state) ? | |
13691 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13692 | } |
13693 | ||
61333b60 ML |
13694 | if (any_ms) { |
13695 | ret = intel_modeset_checks(state); | |
13696 | ||
13697 | if (ret) | |
13698 | return ret; | |
27c329ed | 13699 | } else |
dd8b3bdb | 13700 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13701 | |
dd8b3bdb | 13702 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13703 | if (ret) |
13704 | return ret; | |
13705 | ||
f51be2e0 | 13706 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13707 | return calc_watermark_data(state); |
054518dd ACO |
13708 | } |
13709 | ||
5008e874 ML |
13710 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13711 | struct drm_atomic_state *state, | |
81072bfd | 13712 | bool nonblock) |
5008e874 | 13713 | { |
fac5e23e | 13714 | struct drm_i915_private *dev_priv = to_i915(dev); |
7580d774 | 13715 | struct drm_plane_state *plane_state; |
5008e874 | 13716 | struct drm_crtc_state *crtc_state; |
7580d774 | 13717 | struct drm_plane *plane; |
5008e874 ML |
13718 | struct drm_crtc *crtc; |
13719 | int i, ret; | |
13720 | ||
5a21b665 DV |
13721 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13722 | if (state->legacy_cursor_update) | |
a6747b73 ML |
13723 | continue; |
13724 | ||
5a21b665 DV |
13725 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13726 | if (ret) | |
13727 | return ret; | |
5008e874 | 13728 | |
5a21b665 DV |
13729 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
13730 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
13731 | } |
13732 | ||
f935675f ML |
13733 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13734 | if (ret) | |
13735 | return ret; | |
13736 | ||
5008e874 | 13737 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13738 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13739 | |
21daaeee | 13740 | if (!ret && !nonblock) { |
7580d774 ML |
13741 | for_each_plane_in_state(state, plane, plane_state, i) { |
13742 | struct intel_plane_state *intel_plane_state = | |
13743 | to_intel_plane_state(plane_state); | |
13744 | ||
13745 | if (!intel_plane_state->wait_req) | |
13746 | continue; | |
13747 | ||
776f3236 CW |
13748 | ret = i915_wait_request(intel_plane_state->wait_req, |
13749 | true, NULL, NULL); | |
f7e5838b | 13750 | if (ret) { |
f4457ae7 CW |
13751 | /* Any hang should be swallowed by the wait */ |
13752 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13753 | mutex_lock(&dev->struct_mutex); |
13754 | drm_atomic_helper_cleanup_planes(dev, state); | |
13755 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13756 | break; |
f7e5838b | 13757 | } |
7580d774 | 13758 | } |
7580d774 | 13759 | } |
5008e874 ML |
13760 | |
13761 | return ret; | |
13762 | } | |
13763 | ||
a2991414 ML |
13764 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
13765 | { | |
13766 | struct drm_device *dev = crtc->base.dev; | |
13767 | ||
13768 | if (!dev->max_vblank_count) | |
13769 | return drm_accurate_vblank_count(&crtc->base); | |
13770 | ||
13771 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
13772 | } | |
13773 | ||
5a21b665 DV |
13774 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13775 | struct drm_i915_private *dev_priv, | |
13776 | unsigned crtc_mask) | |
e8861675 | 13777 | { |
5a21b665 DV |
13778 | unsigned last_vblank_count[I915_MAX_PIPES]; |
13779 | enum pipe pipe; | |
13780 | int ret; | |
e8861675 | 13781 | |
5a21b665 DV |
13782 | if (!crtc_mask) |
13783 | return; | |
e8861675 | 13784 | |
5a21b665 DV |
13785 | for_each_pipe(dev_priv, pipe) { |
13786 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 13787 | |
5a21b665 | 13788 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
13789 | continue; |
13790 | ||
5a21b665 DV |
13791 | ret = drm_crtc_vblank_get(crtc); |
13792 | if (WARN_ON(ret != 0)) { | |
13793 | crtc_mask &= ~(1 << pipe); | |
13794 | continue; | |
e8861675 ML |
13795 | } |
13796 | ||
5a21b665 | 13797 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
13798 | } |
13799 | ||
5a21b665 DV |
13800 | for_each_pipe(dev_priv, pipe) { |
13801 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13802 | long lret; | |
e8861675 | 13803 | |
5a21b665 DV |
13804 | if (!((1 << pipe) & crtc_mask)) |
13805 | continue; | |
d55dbd06 | 13806 | |
5a21b665 DV |
13807 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
13808 | last_vblank_count[pipe] != | |
13809 | drm_crtc_vblank_count(crtc), | |
13810 | msecs_to_jiffies(50)); | |
d55dbd06 | 13811 | |
5a21b665 | 13812 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 13813 | |
5a21b665 | 13814 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
13815 | } |
13816 | } | |
13817 | ||
5a21b665 | 13818 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 13819 | { |
5a21b665 DV |
13820 | /* fb updated, need to unpin old fb */ |
13821 | if (crtc_state->fb_changed) | |
13822 | return true; | |
a6747b73 | 13823 | |
5a21b665 DV |
13824 | /* wm changes, need vblank before final wm's */ |
13825 | if (crtc_state->update_wm_post) | |
13826 | return true; | |
a6747b73 | 13827 | |
5a21b665 DV |
13828 | /* |
13829 | * cxsr is re-enabled after vblank. | |
13830 | * This is already handled by crtc_state->update_wm_post, | |
13831 | * but added for clarity. | |
13832 | */ | |
13833 | if (crtc_state->disable_cxsr) | |
13834 | return true; | |
a6747b73 | 13835 | |
5a21b665 | 13836 | return false; |
e8861675 ML |
13837 | } |
13838 | ||
94f05024 | 13839 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 13840 | { |
94f05024 | 13841 | struct drm_device *dev = state->dev; |
565602d7 | 13842 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13843 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 13844 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13845 | struct drm_crtc *crtc; |
5a21b665 | 13846 | struct intel_crtc_state *intel_cstate; |
94f05024 DV |
13847 | struct drm_plane *plane; |
13848 | struct drm_plane_state *plane_state; | |
5a21b665 DV |
13849 | bool hw_check = intel_state->modeset; |
13850 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
13851 | unsigned crtc_vblank_mask = 0; | |
94f05024 | 13852 | int i, ret; |
a6778b3c | 13853 | |
94f05024 DV |
13854 | for_each_plane_in_state(state, plane, plane_state, i) { |
13855 | struct intel_plane_state *intel_plane_state = | |
13856 | to_intel_plane_state(plane_state); | |
ea0000f0 | 13857 | |
94f05024 DV |
13858 | if (!intel_plane_state->wait_req) |
13859 | continue; | |
d4afb8cc | 13860 | |
776f3236 CW |
13861 | ret = i915_wait_request(intel_plane_state->wait_req, |
13862 | true, NULL, NULL); | |
94f05024 DV |
13863 | /* EIO should be eaten, and we can't get interrupted in the |
13864 | * worker, and blocking commits have waited already. */ | |
13865 | WARN_ON(ret); | |
13866 | } | |
1c5e19f8 | 13867 | |
ea0000f0 DV |
13868 | drm_atomic_helper_wait_for_dependencies(state); |
13869 | ||
565602d7 ML |
13870 | if (intel_state->modeset) { |
13871 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13872 | sizeof(intel_state->min_pixclk)); | |
13873 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13874 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
13875 | |
13876 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13877 | } |
13878 | ||
29ceb0e6 | 13879 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13881 | ||
5a21b665 DV |
13882 | if (needs_modeset(crtc->state) || |
13883 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13884 | hw_check = true; | |
13885 | ||
13886 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13887 | modeset_get_crtc_power_domains(crtc, | |
13888 | to_intel_crtc_state(crtc->state)); | |
13889 | } | |
13890 | ||
61333b60 ML |
13891 | if (!needs_modeset(crtc->state)) |
13892 | continue; | |
13893 | ||
29ceb0e6 | 13894 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13895 | |
29ceb0e6 VS |
13896 | if (old_crtc_state->active) { |
13897 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13898 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13899 | intel_crtc->active = false; |
58f9c0bc | 13900 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13901 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13902 | |
13903 | /* | |
13904 | * Underruns don't always raise | |
13905 | * interrupts, so check manually. | |
13906 | */ | |
13907 | intel_check_cpu_fifo_underruns(dev_priv); | |
13908 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13909 | |
13910 | if (!crtc->state->active) | |
13911 | intel_update_watermarks(crtc); | |
a539205a | 13912 | } |
b8cecdf5 | 13913 | } |
7758a113 | 13914 | |
ea9d758d DV |
13915 | /* Only after disabling all output pipelines that will be changed can we |
13916 | * update the the output configuration. */ | |
4740b0f2 | 13917 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13918 | |
565602d7 | 13919 | if (intel_state->modeset) { |
4740b0f2 | 13920 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13921 | |
13922 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 13923 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13924 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 13925 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 13926 | |
c0ead703 | 13927 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13928 | } |
47fab737 | 13929 | |
a6778b3c | 13930 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13931 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13932 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13933 | bool modeset = needs_modeset(crtc->state); | |
5a21b665 DV |
13934 | struct intel_crtc_state *pipe_config = |
13935 | to_intel_crtc_state(crtc->state); | |
9f836f90 | 13936 | |
f6ac4b2a | 13937 | if (modeset && crtc->state->active) { |
a539205a ML |
13938 | update_scanline_offset(to_intel_crtc(crtc)); |
13939 | dev_priv->display.crtc_enable(crtc); | |
13940 | } | |
80715b2f | 13941 | |
1f7528c4 DV |
13942 | /* Complete events for now disable pipes here. */ |
13943 | if (modeset && !crtc->state->active && crtc->state->event) { | |
13944 | spin_lock_irq(&dev->event_lock); | |
13945 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
13946 | spin_unlock_irq(&dev->event_lock); | |
13947 | ||
13948 | crtc->state->event = NULL; | |
13949 | } | |
13950 | ||
f6ac4b2a | 13951 | if (!modeset) |
29ceb0e6 | 13952 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13953 | |
5a21b665 DV |
13954 | if (crtc->state->active && |
13955 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
faf68d92 | 13956 | intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); |
5a21b665 | 13957 | |
1f7528c4 | 13958 | if (crtc->state->active) |
5a21b665 | 13959 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
f6d1973d | 13960 | |
5a21b665 DV |
13961 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13962 | crtc_vblank_mask |= 1 << i; | |
177246a8 MR |
13963 | } |
13964 | ||
94f05024 DV |
13965 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
13966 | * already, but still need the state for the delayed optimization. To | |
13967 | * fix this: | |
13968 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
13969 | * - schedule that vblank worker _before_ calling hw_done | |
13970 | * - at the start of commit_tail, cancel it _synchrously | |
13971 | * - switch over to the vblank wait helper in the core after that since | |
13972 | * we don't need out special handling any more. | |
13973 | */ | |
5a21b665 DV |
13974 | if (!state->legacy_cursor_update) |
13975 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13976 | ||
13977 | /* | |
13978 | * Now that the vblank has passed, we can go ahead and program the | |
13979 | * optimal watermarks on platforms that need two-step watermark | |
13980 | * programming. | |
13981 | * | |
13982 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13983 | */ | |
13984 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13985 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13986 | ||
13987 | if (dev_priv->display.optimize_watermarks) | |
13988 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13989 | } | |
13990 | ||
13991 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13992 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13993 | ||
13994 | if (put_domains[i]) | |
13995 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13996 | ||
13997 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
13998 | } | |
13999 | ||
94f05024 DV |
14000 | drm_atomic_helper_commit_hw_done(state); |
14001 | ||
5a21b665 DV |
14002 | if (intel_state->modeset) |
14003 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14004 | ||
14005 | mutex_lock(&dev->struct_mutex); | |
14006 | drm_atomic_helper_cleanup_planes(dev, state); | |
14007 | mutex_unlock(&dev->struct_mutex); | |
14008 | ||
ea0000f0 DV |
14009 | drm_atomic_helper_commit_cleanup_done(state); |
14010 | ||
ee165b1a | 14011 | drm_atomic_state_free(state); |
f30da187 | 14012 | |
75714940 MK |
14013 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14014 | * of triggering bugs in unclaimed access. After we finish | |
14015 | * modesetting, see if an error has been flagged, and if so | |
14016 | * enable debugging for the next modeset - and hope we catch | |
14017 | * the culprit. | |
14018 | * | |
14019 | * XXX note that we assume display power is on at this point. | |
14020 | * This might hold true now but we need to add pm helper to check | |
14021 | * unclaimed only when the hardware is on, as atomic commits | |
14022 | * can happen also when the device is completely off. | |
14023 | */ | |
14024 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14025 | } |
14026 | ||
14027 | static void intel_atomic_commit_work(struct work_struct *work) | |
14028 | { | |
14029 | struct drm_atomic_state *state = container_of(work, | |
14030 | struct drm_atomic_state, | |
14031 | commit_work); | |
14032 | intel_atomic_commit_tail(state); | |
14033 | } | |
14034 | ||
6c9c1b38 DV |
14035 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14036 | { | |
14037 | struct drm_plane_state *old_plane_state; | |
14038 | struct drm_plane *plane; | |
6c9c1b38 DV |
14039 | int i; |
14040 | ||
faf5bf0a CW |
14041 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14042 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14043 | intel_fb_obj(plane->state->fb), | |
14044 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14045 | } |
14046 | ||
94f05024 DV |
14047 | /** |
14048 | * intel_atomic_commit - commit validated state object | |
14049 | * @dev: DRM device | |
14050 | * @state: the top-level driver state object | |
14051 | * @nonblock: nonblocking commit | |
14052 | * | |
14053 | * This function commits a top-level state object that has been validated | |
14054 | * with drm_atomic_helper_check(). | |
14055 | * | |
14056 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
14057 | * nonblocking commits are only safe for pure plane updates. Everything else | |
14058 | * should work though. | |
14059 | * | |
14060 | * RETURNS | |
14061 | * Zero for success or -errno. | |
14062 | */ | |
14063 | static int intel_atomic_commit(struct drm_device *dev, | |
14064 | struct drm_atomic_state *state, | |
14065 | bool nonblock) | |
14066 | { | |
14067 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14068 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14069 | int ret = 0; |
14070 | ||
14071 | if (intel_state->modeset && nonblock) { | |
14072 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
14073 | return -EINVAL; | |
14074 | } | |
14075 | ||
14076 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
14077 | if (ret) | |
14078 | return ret; | |
14079 | ||
14080 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); | |
14081 | ||
14082 | ret = intel_atomic_prepare_commit(dev, state, nonblock); | |
14083 | if (ret) { | |
14084 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
14085 | return ret; | |
14086 | } | |
14087 | ||
14088 | drm_atomic_helper_swap_state(state, true); | |
14089 | dev_priv->wm.distrust_bios_wm = false; | |
14090 | dev_priv->wm.skl_results = intel_state->wm_results; | |
14091 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 14092 | intel_atomic_track_fbs(state); |
94f05024 DV |
14093 | |
14094 | if (nonblock) | |
14095 | queue_work(system_unbound_wq, &state->commit_work); | |
14096 | else | |
14097 | intel_atomic_commit_tail(state); | |
75714940 | 14098 | |
74c090b1 | 14099 | return 0; |
7f27126e JB |
14100 | } |
14101 | ||
c0c36b94 CW |
14102 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14103 | { | |
83a57153 ACO |
14104 | struct drm_device *dev = crtc->dev; |
14105 | struct drm_atomic_state *state; | |
e694eb02 | 14106 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14107 | int ret; |
83a57153 ACO |
14108 | |
14109 | state = drm_atomic_state_alloc(dev); | |
14110 | if (!state) { | |
78108b7c VS |
14111 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14112 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14113 | return; |
14114 | } | |
14115 | ||
e694eb02 | 14116 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14117 | |
e694eb02 ML |
14118 | retry: |
14119 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14120 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14121 | if (!ret) { | |
14122 | if (!crtc_state->active) | |
14123 | goto out; | |
83a57153 | 14124 | |
e694eb02 | 14125 | crtc_state->mode_changed = true; |
74c090b1 | 14126 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14127 | } |
14128 | ||
e694eb02 ML |
14129 | if (ret == -EDEADLK) { |
14130 | drm_atomic_state_clear(state); | |
14131 | drm_modeset_backoff(state->acquire_ctx); | |
14132 | goto retry; | |
4ed9fb37 | 14133 | } |
4be07317 | 14134 | |
2bfb4627 | 14135 | if (ret) |
e694eb02 | 14136 | out: |
2bfb4627 | 14137 | drm_atomic_state_free(state); |
c0c36b94 CW |
14138 | } |
14139 | ||
25c5b266 DV |
14140 | #undef for_each_intel_crtc_masked |
14141 | ||
a8784875 BP |
14142 | /* |
14143 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14144 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14145 | */ | |
14146 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14147 | u16 *red, u16 *green, u16 *blue, | |
14148 | uint32_t size) | |
14149 | { | |
14150 | struct drm_device *dev = crtc->dev; | |
14151 | struct drm_mode_config *config = &dev->mode_config; | |
14152 | struct drm_crtc_state *state; | |
14153 | int ret; | |
14154 | ||
14155 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14156 | if (ret) | |
14157 | return ret; | |
14158 | ||
14159 | /* | |
14160 | * Make sure we update the legacy properties so this works when | |
14161 | * atomic is not enabled. | |
14162 | */ | |
14163 | ||
14164 | state = crtc->state; | |
14165 | ||
14166 | drm_object_property_set_value(&crtc->base, | |
14167 | config->degamma_lut_property, | |
14168 | (state->degamma_lut) ? | |
14169 | state->degamma_lut->base.id : 0); | |
14170 | ||
14171 | drm_object_property_set_value(&crtc->base, | |
14172 | config->ctm_property, | |
14173 | (state->ctm) ? | |
14174 | state->ctm->base.id : 0); | |
14175 | ||
14176 | drm_object_property_set_value(&crtc->base, | |
14177 | config->gamma_lut_property, | |
14178 | (state->gamma_lut) ? | |
14179 | state->gamma_lut->base.id : 0); | |
14180 | ||
14181 | return 0; | |
14182 | } | |
14183 | ||
f6e5b160 | 14184 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14185 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14186 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14187 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14188 | .destroy = intel_crtc_destroy, |
527b6abe | 14189 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14190 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14191 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14192 | }; |
14193 | ||
6beb8c23 MR |
14194 | /** |
14195 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14196 | * @plane: drm plane to prepare for | |
14197 | * @fb: framebuffer to prepare for presentation | |
14198 | * | |
14199 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14200 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14201 | * bits. Some older platforms need special physical address handling for | |
14202 | * cursor planes. | |
14203 | * | |
f935675f ML |
14204 | * Must be called with struct_mutex held. |
14205 | * | |
6beb8c23 MR |
14206 | * Returns 0 on success, negative error code on failure. |
14207 | */ | |
14208 | int | |
14209 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 14210 | const struct drm_plane_state *new_state) |
465c120c MR |
14211 | { |
14212 | struct drm_device *dev = plane->dev; | |
844f9111 | 14213 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14214 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14215 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c37efb99 | 14216 | struct reservation_object *resv; |
6beb8c23 | 14217 | int ret = 0; |
465c120c | 14218 | |
1ee49399 | 14219 | if (!obj && !old_obj) |
465c120c MR |
14220 | return 0; |
14221 | ||
5008e874 ML |
14222 | if (old_obj) { |
14223 | struct drm_crtc_state *crtc_state = | |
14224 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14225 | ||
14226 | /* Big Hammer, we also need to ensure that any pending | |
14227 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14228 | * current scanout is retired before unpinning the old | |
14229 | * framebuffer. Note that we rely on userspace rendering | |
14230 | * into the buffer attached to the pipe they are waiting | |
14231 | * on. If not, userspace generates a GPU hang with IPEHR | |
14232 | * point to the MI_WAIT_FOR_EVENT. | |
14233 | * | |
14234 | * This should only fail upon a hung GPU, in which case we | |
14235 | * can safely continue. | |
14236 | */ | |
14237 | if (needs_modeset(crtc_state)) | |
14238 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
14239 | if (ret) { |
14240 | /* GPU hangs should have been swallowed by the wait */ | |
14241 | WARN_ON(ret == -EIO); | |
f935675f | 14242 | return ret; |
f4457ae7 | 14243 | } |
5008e874 ML |
14244 | } |
14245 | ||
c37efb99 CW |
14246 | if (!obj) |
14247 | return 0; | |
14248 | ||
5a21b665 | 14249 | /* For framebuffer backed by dmabuf, wait for fence */ |
c37efb99 CW |
14250 | resv = i915_gem_object_get_dmabuf_resv(obj); |
14251 | if (resv) { | |
5a21b665 DV |
14252 | long lret; |
14253 | ||
c37efb99 | 14254 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
5a21b665 DV |
14255 | MAX_SCHEDULE_TIMEOUT); |
14256 | if (lret == -ERESTARTSYS) | |
14257 | return lret; | |
14258 | ||
14259 | WARN(lret < 0, "waiting returns %li\n", lret); | |
14260 | } | |
14261 | ||
c37efb99 | 14262 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 MR |
14263 | INTEL_INFO(dev)->cursor_needs_physical) { |
14264 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14265 | ret = i915_gem_object_attach_phys(obj, align); | |
14266 | if (ret) | |
14267 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14268 | } else { | |
3465c580 | 14269 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14270 | } |
465c120c | 14271 | |
c37efb99 | 14272 | if (ret == 0) { |
27c01aae | 14273 | to_intel_plane_state(new_state)->wait_req = |
d72d908b CW |
14274 | i915_gem_active_get(&obj->last_write, |
14275 | &obj->base.dev->struct_mutex); | |
7580d774 | 14276 | } |
fdd508a6 | 14277 | |
6beb8c23 MR |
14278 | return ret; |
14279 | } | |
14280 | ||
38f3ce3a MR |
14281 | /** |
14282 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14283 | * @plane: drm plane to clean up for | |
14284 | * @fb: old framebuffer that was on plane | |
14285 | * | |
14286 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14287 | * |
14288 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14289 | */ |
14290 | void | |
14291 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14292 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14293 | { |
14294 | struct drm_device *dev = plane->dev; | |
7580d774 | 14295 | struct intel_plane_state *old_intel_state; |
84978257 | 14296 | struct intel_plane_state *intel_state = to_intel_plane_state(plane->state); |
1ee49399 ML |
14297 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14298 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14299 | |
7580d774 ML |
14300 | old_intel_state = to_intel_plane_state(old_state); |
14301 | ||
1ee49399 | 14302 | if (!obj && !old_obj) |
38f3ce3a MR |
14303 | return; |
14304 | ||
1ee49399 ML |
14305 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14306 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14307 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 | 14308 | |
84978257 | 14309 | i915_gem_request_assign(&intel_state->wait_req, NULL); |
7580d774 | 14310 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
465c120c MR |
14311 | } |
14312 | ||
6156a456 CK |
14313 | int |
14314 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14315 | { | |
14316 | int max_scale; | |
6156a456 CK |
14317 | int crtc_clock, cdclk; |
14318 | ||
bf8a0af0 | 14319 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14320 | return DRM_PLANE_HELPER_NO_SCALING; |
14321 | ||
6156a456 | 14322 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14323 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14324 | |
54bf1ce6 | 14325 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14326 | return DRM_PLANE_HELPER_NO_SCALING; |
14327 | ||
14328 | /* | |
14329 | * skl max scale is lower of: | |
14330 | * close to 3 but not 3, -1 is for that purpose | |
14331 | * or | |
14332 | * cdclk/crtc_clock | |
14333 | */ | |
14334 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14335 | ||
14336 | return max_scale; | |
14337 | } | |
14338 | ||
465c120c | 14339 | static int |
3c692a41 | 14340 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14341 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14342 | struct intel_plane_state *state) |
14343 | { | |
2b875c22 MR |
14344 | struct drm_crtc *crtc = state->base.crtc; |
14345 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14346 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14347 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14348 | bool can_position = false; | |
465c120c | 14349 | |
693bdc28 VS |
14350 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14351 | /* use scaler when colorkey is not required */ | |
14352 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14353 | min_scale = 1; | |
14354 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14355 | } | |
d8106366 | 14356 | can_position = true; |
6156a456 | 14357 | } |
d8106366 | 14358 | |
061e4b8d ML |
14359 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14360 | &state->dst, &state->clip, | |
9b8b013d | 14361 | state->base.rotation, |
da20eabd ML |
14362 | min_scale, max_scale, |
14363 | can_position, true, | |
14364 | &state->visible); | |
14af293f GP |
14365 | } |
14366 | ||
5a21b665 DV |
14367 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14368 | struct drm_crtc_state *old_crtc_state) | |
14369 | { | |
14370 | struct drm_device *dev = crtc->dev; | |
14371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14372 | struct intel_crtc_state *old_intel_state = | |
14373 | to_intel_crtc_state(old_crtc_state); | |
14374 | bool modeset = needs_modeset(crtc->state); | |
14375 | ||
14376 | /* Perform vblank evasion around commit operation */ | |
14377 | intel_pipe_update_start(intel_crtc); | |
14378 | ||
14379 | if (modeset) | |
14380 | return; | |
14381 | ||
14382 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14383 | intel_color_set_csc(crtc->state); | |
14384 | intel_color_load_luts(crtc->state); | |
14385 | } | |
14386 | ||
14387 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14388 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14389 | else if (INTEL_INFO(dev)->gen >= 9) | |
14390 | skl_detach_scalers(intel_crtc); | |
14391 | } | |
14392 | ||
14393 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14394 | struct drm_crtc_state *old_crtc_state) | |
14395 | { | |
14396 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14397 | ||
14398 | intel_pipe_update_end(intel_crtc, NULL); | |
14399 | } | |
14400 | ||
cf4c7c12 | 14401 | /** |
4a3b8769 MR |
14402 | * intel_plane_destroy - destroy a plane |
14403 | * @plane: plane to destroy | |
cf4c7c12 | 14404 | * |
4a3b8769 MR |
14405 | * Common destruction function for all types of planes (primary, cursor, |
14406 | * sprite). | |
cf4c7c12 | 14407 | */ |
4a3b8769 | 14408 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14409 | { |
69ae561f VS |
14410 | if (!plane) |
14411 | return; | |
14412 | ||
465c120c | 14413 | drm_plane_cleanup(plane); |
69ae561f | 14414 | kfree(to_intel_plane(plane)); |
465c120c MR |
14415 | } |
14416 | ||
65a3fea0 | 14417 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14418 | .update_plane = drm_atomic_helper_update_plane, |
14419 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14420 | .destroy = intel_plane_destroy, |
c196e1d6 | 14421 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14422 | .atomic_get_property = intel_plane_atomic_get_property, |
14423 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14424 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14425 | .atomic_destroy_state = intel_plane_destroy_state, | |
14426 | ||
465c120c MR |
14427 | }; |
14428 | ||
14429 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14430 | int pipe) | |
14431 | { | |
fca0ce2a VS |
14432 | struct intel_plane *primary = NULL; |
14433 | struct intel_plane_state *state = NULL; | |
465c120c | 14434 | const uint32_t *intel_primary_formats; |
45e3743a | 14435 | unsigned int num_formats; |
fca0ce2a | 14436 | int ret; |
465c120c MR |
14437 | |
14438 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14439 | if (!primary) |
14440 | goto fail; | |
465c120c | 14441 | |
8e7d688b | 14442 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14443 | if (!state) |
14444 | goto fail; | |
8e7d688b | 14445 | primary->base.state = &state->base; |
ea2c67bb | 14446 | |
465c120c MR |
14447 | primary->can_scale = false; |
14448 | primary->max_downscale = 1; | |
6156a456 CK |
14449 | if (INTEL_INFO(dev)->gen >= 9) { |
14450 | primary->can_scale = true; | |
af99ceda | 14451 | state->scaler_id = -1; |
6156a456 | 14452 | } |
465c120c MR |
14453 | primary->pipe = pipe; |
14454 | primary->plane = pipe; | |
a9ff8714 | 14455 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14456 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14457 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14458 | primary->plane = !pipe; | |
14459 | ||
6c0fd451 DL |
14460 | if (INTEL_INFO(dev)->gen >= 9) { |
14461 | intel_primary_formats = skl_primary_formats; | |
14462 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14463 | |
14464 | primary->update_plane = skylake_update_primary_plane; | |
14465 | primary->disable_plane = skylake_disable_primary_plane; | |
14466 | } else if (HAS_PCH_SPLIT(dev)) { | |
14467 | intel_primary_formats = i965_primary_formats; | |
14468 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14469 | ||
14470 | primary->update_plane = ironlake_update_primary_plane; | |
14471 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14472 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14473 | intel_primary_formats = i965_primary_formats; |
14474 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14475 | |
14476 | primary->update_plane = i9xx_update_primary_plane; | |
14477 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14478 | } else { |
14479 | intel_primary_formats = i8xx_primary_formats; | |
14480 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14481 | |
14482 | primary->update_plane = i9xx_update_primary_plane; | |
14483 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14484 | } |
14485 | ||
38573dc1 VS |
14486 | if (INTEL_INFO(dev)->gen >= 9) |
14487 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14488 | &intel_plane_funcs, | |
14489 | intel_primary_formats, num_formats, | |
14490 | DRM_PLANE_TYPE_PRIMARY, | |
14491 | "plane 1%c", pipe_name(pipe)); | |
14492 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
14493 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14494 | &intel_plane_funcs, | |
14495 | intel_primary_formats, num_formats, | |
14496 | DRM_PLANE_TYPE_PRIMARY, | |
14497 | "primary %c", pipe_name(pipe)); | |
14498 | else | |
14499 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14500 | &intel_plane_funcs, | |
14501 | intel_primary_formats, num_formats, | |
14502 | DRM_PLANE_TYPE_PRIMARY, | |
14503 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
14504 | if (ret) |
14505 | goto fail; | |
48404c1e | 14506 | |
3b7a5119 SJ |
14507 | if (INTEL_INFO(dev)->gen >= 4) |
14508 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14509 | |
ea2c67bb MR |
14510 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14511 | ||
465c120c | 14512 | return &primary->base; |
fca0ce2a VS |
14513 | |
14514 | fail: | |
14515 | kfree(state); | |
14516 | kfree(primary); | |
14517 | ||
14518 | return NULL; | |
465c120c MR |
14519 | } |
14520 | ||
3b7a5119 SJ |
14521 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14522 | { | |
14523 | if (!dev->mode_config.rotation_property) { | |
14524 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14525 | BIT(DRM_ROTATE_180); | |
14526 | ||
14527 | if (INTEL_INFO(dev)->gen >= 9) | |
14528 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14529 | ||
14530 | dev->mode_config.rotation_property = | |
14531 | drm_mode_create_rotation_property(dev, flags); | |
14532 | } | |
14533 | if (dev->mode_config.rotation_property) | |
14534 | drm_object_attach_property(&plane->base.base, | |
14535 | dev->mode_config.rotation_property, | |
14536 | plane->base.state->rotation); | |
14537 | } | |
14538 | ||
3d7d6510 | 14539 | static int |
852e787c | 14540 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14541 | struct intel_crtc_state *crtc_state, |
852e787c | 14542 | struct intel_plane_state *state) |
3d7d6510 | 14543 | { |
061e4b8d | 14544 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14545 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14546 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14547 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14548 | unsigned stride; |
14549 | int ret; | |
3d7d6510 | 14550 | |
061e4b8d ML |
14551 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14552 | &state->dst, &state->clip, | |
9b8b013d | 14553 | state->base.rotation, |
3d7d6510 MR |
14554 | DRM_PLANE_HELPER_NO_SCALING, |
14555 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14556 | true, true, &state->visible); |
757f9a3e GP |
14557 | if (ret) |
14558 | return ret; | |
14559 | ||
757f9a3e GP |
14560 | /* if we want to turn off the cursor ignore width and height */ |
14561 | if (!obj) | |
da20eabd | 14562 | return 0; |
757f9a3e | 14563 | |
757f9a3e | 14564 | /* Check for which cursor types we support */ |
061e4b8d | 14565 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14566 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14567 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14568 | return -EINVAL; |
14569 | } | |
14570 | ||
ea2c67bb MR |
14571 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14572 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14573 | DRM_DEBUG_KMS("buffer is too small\n"); |
14574 | return -ENOMEM; | |
14575 | } | |
14576 | ||
3a656b54 | 14577 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14578 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14579 | return -EINVAL; |
32b7eeec MR |
14580 | } |
14581 | ||
b29ec92c VS |
14582 | /* |
14583 | * There's something wrong with the cursor on CHV pipe C. | |
14584 | * If it straddles the left edge of the screen then | |
14585 | * moving it away from the edge or disabling it often | |
14586 | * results in a pipe underrun, and often that can lead to | |
14587 | * dead pipe (constant underrun reported, and it scans | |
14588 | * out just a solid color). To recover from that, the | |
14589 | * display power well must be turned off and on again. | |
14590 | * Refuse the put the cursor into that compromised position. | |
14591 | */ | |
14592 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14593 | state->visible && state->base.crtc_x < 0) { | |
14594 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14595 | return -EINVAL; | |
14596 | } | |
14597 | ||
da20eabd | 14598 | return 0; |
852e787c | 14599 | } |
3d7d6510 | 14600 | |
a8ad0d8e ML |
14601 | static void |
14602 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14603 | struct drm_crtc *crtc) |
a8ad0d8e | 14604 | { |
f2858021 ML |
14605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14606 | ||
14607 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14608 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14609 | } |
14610 | ||
f4a2cf29 | 14611 | static void |
55a08b3f ML |
14612 | intel_update_cursor_plane(struct drm_plane *plane, |
14613 | const struct intel_crtc_state *crtc_state, | |
14614 | const struct intel_plane_state *state) | |
852e787c | 14615 | { |
55a08b3f ML |
14616 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14617 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14618 | struct drm_device *dev = plane->dev; |
2b875c22 | 14619 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14620 | uint32_t addr; |
852e787c | 14621 | |
f4a2cf29 | 14622 | if (!obj) |
a912f12f | 14623 | addr = 0; |
f4a2cf29 | 14624 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14625 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14626 | else |
a912f12f | 14627 | addr = obj->phys_handle->busaddr; |
852e787c | 14628 | |
a912f12f | 14629 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14630 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14631 | } |
14632 | ||
3d7d6510 MR |
14633 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14634 | int pipe) | |
14635 | { | |
fca0ce2a VS |
14636 | struct intel_plane *cursor = NULL; |
14637 | struct intel_plane_state *state = NULL; | |
14638 | int ret; | |
3d7d6510 MR |
14639 | |
14640 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14641 | if (!cursor) |
14642 | goto fail; | |
3d7d6510 | 14643 | |
8e7d688b | 14644 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14645 | if (!state) |
14646 | goto fail; | |
8e7d688b | 14647 | cursor->base.state = &state->base; |
ea2c67bb | 14648 | |
3d7d6510 MR |
14649 | cursor->can_scale = false; |
14650 | cursor->max_downscale = 1; | |
14651 | cursor->pipe = pipe; | |
14652 | cursor->plane = pipe; | |
a9ff8714 | 14653 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14654 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14655 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14656 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14657 | |
fca0ce2a VS |
14658 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14659 | &intel_plane_funcs, | |
14660 | intel_cursor_formats, | |
14661 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
14662 | DRM_PLANE_TYPE_CURSOR, |
14663 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
14664 | if (ret) |
14665 | goto fail; | |
4398ad45 VS |
14666 | |
14667 | if (INTEL_INFO(dev)->gen >= 4) { | |
14668 | if (!dev->mode_config.rotation_property) | |
14669 | dev->mode_config.rotation_property = | |
14670 | drm_mode_create_rotation_property(dev, | |
14671 | BIT(DRM_ROTATE_0) | | |
14672 | BIT(DRM_ROTATE_180)); | |
14673 | if (dev->mode_config.rotation_property) | |
14674 | drm_object_attach_property(&cursor->base.base, | |
14675 | dev->mode_config.rotation_property, | |
8e7d688b | 14676 | state->base.rotation); |
4398ad45 VS |
14677 | } |
14678 | ||
af99ceda CK |
14679 | if (INTEL_INFO(dev)->gen >=9) |
14680 | state->scaler_id = -1; | |
14681 | ||
ea2c67bb MR |
14682 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14683 | ||
3d7d6510 | 14684 | return &cursor->base; |
fca0ce2a VS |
14685 | |
14686 | fail: | |
14687 | kfree(state); | |
14688 | kfree(cursor); | |
14689 | ||
14690 | return NULL; | |
3d7d6510 MR |
14691 | } |
14692 | ||
549e2bfb CK |
14693 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14694 | struct intel_crtc_state *crtc_state) | |
14695 | { | |
14696 | int i; | |
14697 | struct intel_scaler *intel_scaler; | |
14698 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14699 | ||
14700 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14701 | intel_scaler = &scaler_state->scalers[i]; | |
14702 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14703 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14704 | } | |
14705 | ||
14706 | scaler_state->scaler_id = -1; | |
14707 | } | |
14708 | ||
b358d0a6 | 14709 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14710 | { |
fac5e23e | 14711 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 14712 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14713 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14714 | struct drm_plane *primary = NULL; |
14715 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14716 | int ret; |
79e53945 | 14717 | |
955382f3 | 14718 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14719 | if (intel_crtc == NULL) |
14720 | return; | |
14721 | ||
f5de6e07 ACO |
14722 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14723 | if (!crtc_state) | |
14724 | goto fail; | |
550acefd ACO |
14725 | intel_crtc->config = crtc_state; |
14726 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14727 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14728 | |
549e2bfb CK |
14729 | /* initialize shared scalers */ |
14730 | if (INTEL_INFO(dev)->gen >= 9) { | |
14731 | if (pipe == PIPE_C) | |
14732 | intel_crtc->num_scalers = 1; | |
14733 | else | |
14734 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14735 | ||
14736 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14737 | } | |
14738 | ||
465c120c | 14739 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14740 | if (!primary) |
14741 | goto fail; | |
14742 | ||
14743 | cursor = intel_cursor_plane_create(dev, pipe); | |
14744 | if (!cursor) | |
14745 | goto fail; | |
14746 | ||
465c120c | 14747 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
4d5d72b7 VS |
14748 | cursor, &intel_crtc_funcs, |
14749 | "pipe %c", pipe_name(pipe)); | |
3d7d6510 MR |
14750 | if (ret) |
14751 | goto fail; | |
79e53945 | 14752 | |
1f1c2e24 VS |
14753 | /* |
14754 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14755 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14756 | */ |
80824003 JB |
14757 | intel_crtc->pipe = pipe; |
14758 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14759 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14760 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14761 | intel_crtc->plane = !pipe; |
80824003 JB |
14762 | } |
14763 | ||
4b0e333e CW |
14764 | intel_crtc->cursor_base = ~0; |
14765 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14766 | intel_crtc->cursor_size = ~0; |
8d7849db | 14767 | |
852eb00d VS |
14768 | intel_crtc->wm.cxsr_allowed = true; |
14769 | ||
22fd0fab JB |
14770 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14771 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14772 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14773 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14774 | ||
79e53945 | 14775 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14776 | |
8563b1e8 LL |
14777 | intel_color_init(&intel_crtc->base); |
14778 | ||
87b6b101 | 14779 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14780 | return; |
14781 | ||
14782 | fail: | |
69ae561f VS |
14783 | intel_plane_destroy(primary); |
14784 | intel_plane_destroy(cursor); | |
f5de6e07 | 14785 | kfree(crtc_state); |
3d7d6510 | 14786 | kfree(intel_crtc); |
79e53945 JB |
14787 | } |
14788 | ||
752aa88a JB |
14789 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14790 | { | |
14791 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14792 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14793 | |
51fd371b | 14794 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14795 | |
d3babd3f | 14796 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14797 | return INVALID_PIPE; |
14798 | ||
14799 | return to_intel_crtc(encoder->crtc)->pipe; | |
14800 | } | |
14801 | ||
08d7b3d1 | 14802 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14803 | struct drm_file *file) |
08d7b3d1 | 14804 | { |
08d7b3d1 | 14805 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14806 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14807 | struct intel_crtc *crtc; |
08d7b3d1 | 14808 | |
7707e653 | 14809 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 14810 | if (!drmmode_crtc) |
3f2c2057 | 14811 | return -ENOENT; |
08d7b3d1 | 14812 | |
7707e653 | 14813 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14814 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14815 | |
c05422d5 | 14816 | return 0; |
08d7b3d1 CW |
14817 | } |
14818 | ||
66a9278e | 14819 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14820 | { |
66a9278e DV |
14821 | struct drm_device *dev = encoder->base.dev; |
14822 | struct intel_encoder *source_encoder; | |
79e53945 | 14823 | int index_mask = 0; |
79e53945 JB |
14824 | int entry = 0; |
14825 | ||
b2784e15 | 14826 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14827 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14828 | index_mask |= (1 << entry); |
14829 | ||
79e53945 JB |
14830 | entry++; |
14831 | } | |
4ef69c7a | 14832 | |
79e53945 JB |
14833 | return index_mask; |
14834 | } | |
14835 | ||
4d302442 CW |
14836 | static bool has_edp_a(struct drm_device *dev) |
14837 | { | |
fac5e23e | 14838 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d302442 CW |
14839 | |
14840 | if (!IS_MOBILE(dev)) | |
14841 | return false; | |
14842 | ||
14843 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14844 | return false; | |
14845 | ||
e3589908 | 14846 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14847 | return false; |
14848 | ||
14849 | return true; | |
14850 | } | |
14851 | ||
84b4e042 JB |
14852 | static bool intel_crt_present(struct drm_device *dev) |
14853 | { | |
fac5e23e | 14854 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 14855 | |
884497ed DL |
14856 | if (INTEL_INFO(dev)->gen >= 9) |
14857 | return false; | |
14858 | ||
cf404ce4 | 14859 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14860 | return false; |
14861 | ||
14862 | if (IS_CHERRYVIEW(dev)) | |
14863 | return false; | |
14864 | ||
65e472e4 VS |
14865 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14866 | return false; | |
14867 | ||
70ac54d0 VS |
14868 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14869 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14870 | return false; | |
14871 | ||
e4abb733 | 14872 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14873 | return false; |
14874 | ||
14875 | return true; | |
14876 | } | |
14877 | ||
8090ba8c ID |
14878 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
14879 | { | |
14880 | int pps_num; | |
14881 | int pps_idx; | |
14882 | ||
14883 | if (HAS_DDI(dev_priv)) | |
14884 | return; | |
14885 | /* | |
14886 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
14887 | * everywhere where registers can be write protected. | |
14888 | */ | |
14889 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14890 | pps_num = 2; | |
14891 | else | |
14892 | pps_num = 1; | |
14893 | ||
14894 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
14895 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
14896 | ||
14897 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
14898 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
14899 | } | |
14900 | } | |
14901 | ||
44cb734c ID |
14902 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
14903 | { | |
14904 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) | |
14905 | dev_priv->pps_mmio_base = PCH_PPS_BASE; | |
14906 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14907 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
14908 | else | |
14909 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
14910 | |
14911 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
14912 | } |
14913 | ||
79e53945 JB |
14914 | static void intel_setup_outputs(struct drm_device *dev) |
14915 | { | |
fac5e23e | 14916 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 14917 | struct intel_encoder *encoder; |
cb0953d7 | 14918 | bool dpd_is_edp = false; |
79e53945 | 14919 | |
44cb734c ID |
14920 | intel_pps_init(dev_priv); |
14921 | ||
97a824e1 ID |
14922 | /* |
14923 | * intel_edp_init_connector() depends on this completing first, to | |
14924 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14925 | * sharing of the PPS. | |
14926 | */ | |
c9093354 | 14927 | intel_lvds_init(dev); |
79e53945 | 14928 | |
84b4e042 | 14929 | if (intel_crt_present(dev)) |
79935fca | 14930 | intel_crt_init(dev); |
cb0953d7 | 14931 | |
c776eb2e VK |
14932 | if (IS_BROXTON(dev)) { |
14933 | /* | |
14934 | * FIXME: Broxton doesn't support port detection via the | |
14935 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14936 | * detect the ports. | |
14937 | */ | |
14938 | intel_ddi_init(dev, PORT_A); | |
14939 | intel_ddi_init(dev, PORT_B); | |
14940 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14941 | |
14942 | intel_dsi_init(dev); | |
c776eb2e | 14943 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14944 | int found; |
14945 | ||
de31facd JB |
14946 | /* |
14947 | * Haswell uses DDI functions to detect digital outputs. | |
14948 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14949 | * it's there. | |
14950 | */ | |
77179400 | 14951 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14952 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14953 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14954 | intel_ddi_init(dev, PORT_A); |
14955 | ||
14956 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14957 | * register */ | |
14958 | found = I915_READ(SFUSE_STRAP); | |
14959 | ||
14960 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14961 | intel_ddi_init(dev, PORT_B); | |
14962 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14963 | intel_ddi_init(dev, PORT_C); | |
14964 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14965 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14966 | /* |
14967 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14968 | */ | |
ef11bdb3 | 14969 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14970 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14971 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14972 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14973 | intel_ddi_init(dev, PORT_E); | |
14974 | ||
0e72a5b5 | 14975 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14976 | int found; |
5d8a7752 | 14977 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14978 | |
14979 | if (has_edp_a(dev)) | |
14980 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14981 | |
dc0fa718 | 14982 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14983 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14984 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14985 | if (!found) |
e2debe91 | 14986 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14987 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14988 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14989 | } |
14990 | ||
dc0fa718 | 14991 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14992 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14993 | |
dc0fa718 | 14994 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14995 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14996 | |
5eb08b69 | 14997 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14998 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14999 | |
270b3042 | 15000 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 15001 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 15002 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
22f35042 | 15003 | bool has_edp, has_port; |
457c52d8 | 15004 | |
e17ac6db VS |
15005 | /* |
15006 | * The DP_DETECTED bit is the latched state of the DDC | |
15007 | * SDA pin at boot. However since eDP doesn't require DDC | |
15008 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15009 | * eDP ports may have been muxed to an alternate function. | |
15010 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15011 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15012 | * detect eDP ports. | |
22f35042 VS |
15013 | * |
15014 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15015 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15016 | * and VBT for the presence of the port. Additionally we can't | |
15017 | * trust the port type the VBT declares as we've seen at least | |
15018 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15019 | */ |
457c52d8 | 15020 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
15021 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15022 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 15023 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 15024 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15025 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 15026 | |
457c52d8 | 15027 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
15028 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15029 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 15030 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 15031 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15032 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 15033 | |
9418c1f1 | 15034 | if (IS_CHERRYVIEW(dev)) { |
22f35042 VS |
15035 | /* |
15036 | * eDP not supported on port D, | |
15037 | * so no need to worry about it | |
15038 | */ | |
15039 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15040 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 15041 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
15042 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
15043 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
15044 | } |
15045 | ||
3cfca973 | 15046 | intel_dsi_init(dev); |
09da55dc | 15047 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 15048 | bool found = false; |
7d57382e | 15049 | |
e2debe91 | 15050 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15051 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 15052 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 15053 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 15054 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 15055 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15056 | } |
27185ae1 | 15057 | |
3fec3d2f | 15058 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 15059 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 15060 | } |
13520b05 KH |
15061 | |
15062 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15063 | |
e2debe91 | 15064 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15065 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 15066 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15067 | } |
27185ae1 | 15068 | |
e2debe91 | 15069 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15070 | |
3fec3d2f | 15071 | if (IS_G4X(dev)) { |
b01f2c3a | 15072 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 15073 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15074 | } |
3fec3d2f | 15075 | if (IS_G4X(dev)) |
ab9d7c30 | 15076 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 15077 | } |
27185ae1 | 15078 | |
3fec3d2f | 15079 | if (IS_G4X(dev) && |
e7281eab | 15080 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 15081 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 15082 | } else if (IS_GEN2(dev)) |
79e53945 JB |
15083 | intel_dvo_init(dev); |
15084 | ||
103a196f | 15085 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
15086 | intel_tv_init(dev); |
15087 | ||
0bc12bcb | 15088 | intel_psr_init(dev); |
7c8f8a70 | 15089 | |
b2784e15 | 15090 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
15091 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15092 | encoder->base.possible_clones = | |
66a9278e | 15093 | intel_encoder_clones(encoder); |
79e53945 | 15094 | } |
47356eb6 | 15095 | |
dde86e2d | 15096 | intel_init_pch_refclk(dev); |
270b3042 DV |
15097 | |
15098 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
15099 | } |
15100 | ||
15101 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15102 | { | |
60a5ca01 | 15103 | struct drm_device *dev = fb->dev; |
79e53945 | 15104 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15105 | |
ef2d633e | 15106 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15107 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15108 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15109 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15110 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15111 | kfree(intel_fb); |
15112 | } | |
15113 | ||
15114 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15115 | struct drm_file *file, |
79e53945 JB |
15116 | unsigned int *handle) |
15117 | { | |
15118 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15119 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15120 | |
cc917ab4 CW |
15121 | if (obj->userptr.mm) { |
15122 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15123 | return -EINVAL; | |
15124 | } | |
15125 | ||
05394f39 | 15126 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15127 | } |
15128 | ||
86c98588 RV |
15129 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15130 | struct drm_file *file, | |
15131 | unsigned flags, unsigned color, | |
15132 | struct drm_clip_rect *clips, | |
15133 | unsigned num_clips) | |
15134 | { | |
15135 | struct drm_device *dev = fb->dev; | |
15136 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15137 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15138 | ||
15139 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 15140 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15141 | mutex_unlock(&dev->struct_mutex); |
15142 | ||
15143 | return 0; | |
15144 | } | |
15145 | ||
79e53945 JB |
15146 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15147 | .destroy = intel_user_framebuffer_destroy, | |
15148 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15149 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15150 | }; |
15151 | ||
b321803d DL |
15152 | static |
15153 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
15154 | uint32_t pixel_format) | |
15155 | { | |
15156 | u32 gen = INTEL_INFO(dev)->gen; | |
15157 | ||
15158 | if (gen >= 9) { | |
ac484963 VS |
15159 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15160 | ||
b321803d DL |
15161 | /* "The stride in bytes must not exceed the of the size of 8K |
15162 | * pixels and 32K bytes." | |
15163 | */ | |
ac484963 | 15164 | return min(8192 * cpp, 32768); |
666a4537 | 15165 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
15166 | return 32*1024; |
15167 | } else if (gen >= 4) { | |
15168 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15169 | return 16*1024; | |
15170 | else | |
15171 | return 32*1024; | |
15172 | } else if (gen >= 3) { | |
15173 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15174 | return 8*1024; | |
15175 | else | |
15176 | return 16*1024; | |
15177 | } else { | |
15178 | /* XXX DSPC is limited to 4k tiled */ | |
15179 | return 8*1024; | |
15180 | } | |
15181 | } | |
15182 | ||
b5ea642a DV |
15183 | static int intel_framebuffer_init(struct drm_device *dev, |
15184 | struct intel_framebuffer *intel_fb, | |
15185 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15186 | struct drm_i915_gem_object *obj) | |
79e53945 | 15187 | { |
7b49f948 | 15188 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 15189 | int ret; |
b321803d | 15190 | u32 pitch_limit, stride_alignment; |
79e53945 | 15191 | |
dd4916c5 DV |
15192 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15193 | ||
2a80eada DV |
15194 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
15195 | /* Enforce that fb modifier and tiling mode match, but only for | |
15196 | * X-tiled. This is needed for FBC. */ | |
3e510a8e | 15197 | if (!!(i915_gem_object_get_tiling(obj) == I915_TILING_X) != |
2a80eada DV |
15198 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { |
15199 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
15200 | return -EINVAL; | |
15201 | } | |
15202 | } else { | |
3e510a8e | 15203 | if (i915_gem_object_get_tiling(obj) == I915_TILING_X) |
2a80eada | 15204 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
3e510a8e | 15205 | else if (i915_gem_object_get_tiling(obj) == I915_TILING_Y) { |
2a80eada DV |
15206 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15207 | return -EINVAL; | |
15208 | } | |
15209 | } | |
15210 | ||
9a8f0a12 TU |
15211 | /* Passed in modifier sanity checking. */ |
15212 | switch (mode_cmd->modifier[0]) { | |
15213 | case I915_FORMAT_MOD_Y_TILED: | |
15214 | case I915_FORMAT_MOD_Yf_TILED: | |
15215 | if (INTEL_INFO(dev)->gen < 9) { | |
15216 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
15217 | mode_cmd->modifier[0]); | |
15218 | return -EINVAL; | |
15219 | } | |
15220 | case DRM_FORMAT_MOD_NONE: | |
15221 | case I915_FORMAT_MOD_X_TILED: | |
15222 | break; | |
15223 | default: | |
c0f40428 JB |
15224 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15225 | mode_cmd->modifier[0]); | |
57cd6508 | 15226 | return -EINVAL; |
c16ed4be | 15227 | } |
57cd6508 | 15228 | |
7b49f948 VS |
15229 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15230 | mode_cmd->modifier[0], | |
b321803d DL |
15231 | mode_cmd->pixel_format); |
15232 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15233 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15234 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15235 | return -EINVAL; |
c16ed4be | 15236 | } |
57cd6508 | 15237 | |
b321803d DL |
15238 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
15239 | mode_cmd->pixel_format); | |
a35cdaa0 | 15240 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15241 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15242 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15243 | "tiled" : "linear", |
a35cdaa0 | 15244 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15245 | return -EINVAL; |
c16ed4be | 15246 | } |
5d7bd705 | 15247 | |
2a80eada | 15248 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
3e510a8e | 15249 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15250 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15251 | mode_cmd->pitches[0], |
15252 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15253 | return -EINVAL; |
c16ed4be | 15254 | } |
5d7bd705 | 15255 | |
57779d06 | 15256 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15257 | switch (mode_cmd->pixel_format) { |
57779d06 | 15258 | case DRM_FORMAT_C8: |
04b3924d VS |
15259 | case DRM_FORMAT_RGB565: |
15260 | case DRM_FORMAT_XRGB8888: | |
15261 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15262 | break; |
15263 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15264 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
15265 | DRM_DEBUG("unsupported pixel format: %s\n", |
15266 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15267 | return -EINVAL; |
c16ed4be | 15268 | } |
57779d06 | 15269 | break; |
57779d06 | 15270 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
15271 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
15272 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
15273 | DRM_DEBUG("unsupported pixel format: %s\n", |
15274 | drm_get_format_name(mode_cmd->pixel_format)); | |
15275 | return -EINVAL; | |
15276 | } | |
15277 | break; | |
15278 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15279 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15280 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15281 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15282 | DRM_DEBUG("unsupported pixel format: %s\n", |
15283 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15284 | return -EINVAL; |
c16ed4be | 15285 | } |
b5626747 | 15286 | break; |
7531208b | 15287 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15288 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15289 | DRM_DEBUG("unsupported pixel format: %s\n", |
15290 | drm_get_format_name(mode_cmd->pixel_format)); | |
15291 | return -EINVAL; | |
15292 | } | |
15293 | break; | |
04b3924d VS |
15294 | case DRM_FORMAT_YUYV: |
15295 | case DRM_FORMAT_UYVY: | |
15296 | case DRM_FORMAT_YVYU: | |
15297 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15298 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15299 | DRM_DEBUG("unsupported pixel format: %s\n", |
15300 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15301 | return -EINVAL; |
c16ed4be | 15302 | } |
57cd6508 CW |
15303 | break; |
15304 | default: | |
4ee62c76 VS |
15305 | DRM_DEBUG("unsupported pixel format: %s\n", |
15306 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15307 | return -EINVAL; |
15308 | } | |
15309 | ||
90f9a336 VS |
15310 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15311 | if (mode_cmd->offsets[0] != 0) | |
15312 | return -EINVAL; | |
15313 | ||
c7d73f6a DV |
15314 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15315 | intel_fb->obj = obj; | |
15316 | ||
6687c906 VS |
15317 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15318 | if (ret) | |
15319 | return ret; | |
2d7a215f | 15320 | |
79e53945 JB |
15321 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15322 | if (ret) { | |
15323 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15324 | return ret; | |
15325 | } | |
15326 | ||
0b05e1e0 VS |
15327 | intel_fb->obj->framebuffer_references++; |
15328 | ||
79e53945 JB |
15329 | return 0; |
15330 | } | |
15331 | ||
79e53945 JB |
15332 | static struct drm_framebuffer * |
15333 | intel_user_framebuffer_create(struct drm_device *dev, | |
15334 | struct drm_file *filp, | |
1eb83451 | 15335 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15336 | { |
dcb1394e | 15337 | struct drm_framebuffer *fb; |
05394f39 | 15338 | struct drm_i915_gem_object *obj; |
76dc3769 | 15339 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15340 | |
03ac0642 CW |
15341 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15342 | if (!obj) | |
cce13ff7 | 15343 | return ERR_PTR(-ENOENT); |
79e53945 | 15344 | |
92907cbb | 15345 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15346 | if (IS_ERR(fb)) |
34911fd3 | 15347 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
15348 | |
15349 | return fb; | |
79e53945 JB |
15350 | } |
15351 | ||
0695726e | 15352 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15353 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15354 | { |
15355 | } | |
15356 | #endif | |
15357 | ||
79e53945 | 15358 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15359 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15360 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15361 | .atomic_check = intel_atomic_check, |
15362 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15363 | .atomic_state_alloc = intel_atomic_state_alloc, |
15364 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15365 | }; |
15366 | ||
88212941 ID |
15367 | /** |
15368 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15369 | * @dev_priv: device private | |
15370 | */ | |
15371 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15372 | { |
88212941 | 15373 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15374 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15375 | dev_priv->display.get_initial_plane_config = |
15376 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15377 | dev_priv->display.crtc_compute_clock = |
15378 | haswell_crtc_compute_clock; | |
15379 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15380 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15381 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15382 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15383 | dev_priv->display.get_initial_plane_config = |
15384 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15385 | dev_priv->display.crtc_compute_clock = |
15386 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15387 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15388 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15389 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15390 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15391 | dev_priv->display.get_initial_plane_config = |
15392 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15393 | dev_priv->display.crtc_compute_clock = |
15394 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15395 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15396 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15397 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15398 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15399 | dev_priv->display.get_initial_plane_config = |
15400 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15401 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15402 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15403 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15404 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15405 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15406 | dev_priv->display.get_initial_plane_config = | |
15407 | i9xx_get_initial_plane_config; | |
15408 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15409 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15410 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15411 | } else if (IS_G4X(dev_priv)) { |
15412 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15413 | dev_priv->display.get_initial_plane_config = | |
15414 | i9xx_get_initial_plane_config; | |
15415 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15416 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15417 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15418 | } else if (IS_PINEVIEW(dev_priv)) { |
15419 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15420 | dev_priv->display.get_initial_plane_config = | |
15421 | i9xx_get_initial_plane_config; | |
15422 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15423 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15424 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15425 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15426 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15427 | dev_priv->display.get_initial_plane_config = |
15428 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15429 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15430 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15431 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
15432 | } else { |
15433 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15434 | dev_priv->display.get_initial_plane_config = | |
15435 | i9xx_get_initial_plane_config; | |
15436 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
15437 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15438 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15439 | } |
e70236a8 | 15440 | |
e70236a8 | 15441 | /* Returns the core display clock speed */ |
88212941 | 15442 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
15443 | dev_priv->display.get_display_clock_speed = |
15444 | skylake_get_display_clock_speed; | |
88212941 | 15445 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
15446 | dev_priv->display.get_display_clock_speed = |
15447 | broxton_get_display_clock_speed; | |
88212941 | 15448 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
15449 | dev_priv->display.get_display_clock_speed = |
15450 | broadwell_get_display_clock_speed; | |
88212941 | 15451 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
15452 | dev_priv->display.get_display_clock_speed = |
15453 | haswell_get_display_clock_speed; | |
88212941 | 15454 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
15455 | dev_priv->display.get_display_clock_speed = |
15456 | valleyview_get_display_clock_speed; | |
88212941 | 15457 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
15458 | dev_priv->display.get_display_clock_speed = |
15459 | ilk_get_display_clock_speed; | |
88212941 ID |
15460 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
15461 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
15462 | dev_priv->display.get_display_clock_speed = |
15463 | i945_get_display_clock_speed; | |
88212941 | 15464 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
15465 | dev_priv->display.get_display_clock_speed = |
15466 | gm45_get_display_clock_speed; | |
88212941 | 15467 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
15468 | dev_priv->display.get_display_clock_speed = |
15469 | i965gm_get_display_clock_speed; | |
88212941 | 15470 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
15471 | dev_priv->display.get_display_clock_speed = |
15472 | pnv_get_display_clock_speed; | |
88212941 | 15473 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
15474 | dev_priv->display.get_display_clock_speed = |
15475 | g33_get_display_clock_speed; | |
88212941 | 15476 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
15477 | dev_priv->display.get_display_clock_speed = |
15478 | i915_get_display_clock_speed; | |
88212941 | 15479 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
15480 | dev_priv->display.get_display_clock_speed = |
15481 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15482 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15483 | dev_priv->display.get_display_clock_speed = |
15484 | i915gm_get_display_clock_speed; | |
88212941 | 15485 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15486 | dev_priv->display.get_display_clock_speed = |
15487 | i865_get_display_clock_speed; | |
88212941 | 15488 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15489 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15490 | i85x_get_display_clock_speed; |
623e01e5 | 15491 | else { /* 830 */ |
88212941 | 15492 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15493 | dev_priv->display.get_display_clock_speed = |
15494 | i830_get_display_clock_speed; | |
623e01e5 | 15495 | } |
e70236a8 | 15496 | |
88212941 | 15497 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15498 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15499 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15500 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15501 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15502 | /* FIXME: detect B0+ stepping and use auto training */ |
15503 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15504 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15505 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15506 | } |
15507 | ||
15508 | if (IS_BROADWELL(dev_priv)) { | |
15509 | dev_priv->display.modeset_commit_cdclk = | |
15510 | broadwell_modeset_commit_cdclk; | |
15511 | dev_priv->display.modeset_calc_cdclk = | |
15512 | broadwell_modeset_calc_cdclk; | |
88212941 | 15513 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15514 | dev_priv->display.modeset_commit_cdclk = |
15515 | valleyview_modeset_commit_cdclk; | |
15516 | dev_priv->display.modeset_calc_cdclk = | |
15517 | valleyview_modeset_calc_cdclk; | |
88212941 | 15518 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 15519 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 15520 | bxt_modeset_commit_cdclk; |
27c329ed | 15521 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 15522 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
15523 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
15524 | dev_priv->display.modeset_commit_cdclk = | |
15525 | skl_modeset_commit_cdclk; | |
15526 | dev_priv->display.modeset_calc_cdclk = | |
15527 | skl_modeset_calc_cdclk; | |
e70236a8 | 15528 | } |
5a21b665 DV |
15529 | |
15530 | switch (INTEL_INFO(dev_priv)->gen) { | |
15531 | case 2: | |
15532 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15533 | break; | |
15534 | ||
15535 | case 3: | |
15536 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15537 | break; | |
15538 | ||
15539 | case 4: | |
15540 | case 5: | |
15541 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15542 | break; | |
15543 | ||
15544 | case 6: | |
15545 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15546 | break; | |
15547 | case 7: | |
15548 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15549 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15550 | break; | |
15551 | case 9: | |
15552 | /* Drop through - unsupported since execlist only. */ | |
15553 | default: | |
15554 | /* Default just returns -ENODEV to indicate unsupported */ | |
15555 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15556 | } | |
e70236a8 JB |
15557 | } |
15558 | ||
b690e96c JB |
15559 | /* |
15560 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15561 | * resume, or other times. This quirk makes sure that's the case for | |
15562 | * affected systems. | |
15563 | */ | |
0206e353 | 15564 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 15565 | { |
fac5e23e | 15566 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
15567 | |
15568 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15569 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15570 | } |
15571 | ||
b6b5d049 VS |
15572 | static void quirk_pipeb_force(struct drm_device *dev) |
15573 | { | |
fac5e23e | 15574 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
15575 | |
15576 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15577 | DRM_INFO("applying pipe b force quirk\n"); | |
15578 | } | |
15579 | ||
435793df KP |
15580 | /* |
15581 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15582 | */ | |
15583 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15584 | { | |
fac5e23e | 15585 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 15586 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 15587 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15588 | } |
15589 | ||
4dca20ef | 15590 | /* |
5a15ab5b CE |
15591 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15592 | * brightness value | |
4dca20ef CE |
15593 | */ |
15594 | static void quirk_invert_brightness(struct drm_device *dev) | |
15595 | { | |
fac5e23e | 15596 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 15597 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 15598 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15599 | } |
15600 | ||
9c72cc6f SD |
15601 | /* Some VBT's incorrectly indicate no backlight is present */ |
15602 | static void quirk_backlight_present(struct drm_device *dev) | |
15603 | { | |
fac5e23e | 15604 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
15605 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
15606 | DRM_INFO("applying backlight present quirk\n"); | |
15607 | } | |
15608 | ||
b690e96c JB |
15609 | struct intel_quirk { |
15610 | int device; | |
15611 | int subsystem_vendor; | |
15612 | int subsystem_device; | |
15613 | void (*hook)(struct drm_device *dev); | |
15614 | }; | |
15615 | ||
5f85f176 EE |
15616 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15617 | struct intel_dmi_quirk { | |
15618 | void (*hook)(struct drm_device *dev); | |
15619 | const struct dmi_system_id (*dmi_id_list)[]; | |
15620 | }; | |
15621 | ||
15622 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15623 | { | |
15624 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15625 | return 1; | |
15626 | } | |
15627 | ||
15628 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15629 | { | |
15630 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15631 | { | |
15632 | .callback = intel_dmi_reverse_brightness, | |
15633 | .ident = "NCR Corporation", | |
15634 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15635 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15636 | }, | |
15637 | }, | |
15638 | { } /* terminating entry */ | |
15639 | }, | |
15640 | .hook = quirk_invert_brightness, | |
15641 | }, | |
15642 | }; | |
15643 | ||
c43b5634 | 15644 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15645 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15646 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15647 | ||
b690e96c JB |
15648 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15649 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15650 | ||
5f080c0f VS |
15651 | /* 830 needs to leave pipe A & dpll A up */ |
15652 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15653 | ||
b6b5d049 VS |
15654 | /* 830 needs to leave pipe B & dpll B up */ |
15655 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15656 | ||
435793df KP |
15657 | /* Lenovo U160 cannot use SSC on LVDS */ |
15658 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15659 | |
15660 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15661 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15662 | |
be505f64 AH |
15663 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15664 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15665 | ||
15666 | /* Acer/eMachines G725 */ | |
15667 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15668 | ||
15669 | /* Acer/eMachines e725 */ | |
15670 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15671 | ||
15672 | /* Acer/Packard Bell NCL20 */ | |
15673 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15674 | ||
15675 | /* Acer Aspire 4736Z */ | |
15676 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15677 | |
15678 | /* Acer Aspire 5336 */ | |
15679 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15680 | |
15681 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15682 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15683 | |
dfb3d47b SD |
15684 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15685 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15686 | ||
b2a9601c | 15687 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15688 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15689 | ||
1b9448b0 JN |
15690 | /* Apple Macbook 4,1 */ |
15691 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15692 | ||
d4967d8c SD |
15693 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15694 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15695 | |
15696 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15697 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15698 | |
15699 | /* Dell Chromebook 11 */ | |
15700 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15701 | |
15702 | /* Dell Chromebook 11 (2015 version) */ | |
15703 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15704 | }; |
15705 | ||
15706 | static void intel_init_quirks(struct drm_device *dev) | |
15707 | { | |
15708 | struct pci_dev *d = dev->pdev; | |
15709 | int i; | |
15710 | ||
15711 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15712 | struct intel_quirk *q = &intel_quirks[i]; | |
15713 | ||
15714 | if (d->device == q->device && | |
15715 | (d->subsystem_vendor == q->subsystem_vendor || | |
15716 | q->subsystem_vendor == PCI_ANY_ID) && | |
15717 | (d->subsystem_device == q->subsystem_device || | |
15718 | q->subsystem_device == PCI_ANY_ID)) | |
15719 | q->hook(dev); | |
15720 | } | |
5f85f176 EE |
15721 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15722 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15723 | intel_dmi_quirks[i].hook(dev); | |
15724 | } | |
b690e96c JB |
15725 | } |
15726 | ||
9cce37f4 JB |
15727 | /* Disable the VGA plane that we never use */ |
15728 | static void i915_disable_vga(struct drm_device *dev) | |
15729 | { | |
fac5e23e | 15730 | struct drm_i915_private *dev_priv = to_i915(dev); |
9cce37f4 | 15731 | u8 sr1; |
f0f59a00 | 15732 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15733 | |
2b37c616 | 15734 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15735 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15736 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15737 | sr1 = inb(VGA_SR_DATA); |
15738 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15739 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15740 | udelay(300); | |
15741 | ||
01f5a626 | 15742 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15743 | POSTING_READ(vga_reg); |
15744 | } | |
15745 | ||
f817586c DV |
15746 | void intel_modeset_init_hw(struct drm_device *dev) |
15747 | { | |
fac5e23e | 15748 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 15749 | |
b6283055 | 15750 | intel_update_cdclk(dev); |
1a617b77 ML |
15751 | |
15752 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15753 | ||
f817586c | 15754 | intel_init_clock_gating(dev); |
f817586c DV |
15755 | } |
15756 | ||
d93c0372 MR |
15757 | /* |
15758 | * Calculate what we think the watermarks should be for the state we've read | |
15759 | * out of the hardware and then immediately program those watermarks so that | |
15760 | * we ensure the hardware settings match our internal state. | |
15761 | * | |
15762 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15763 | * current state (which was constructed during hardware readout) and running it | |
15764 | * through the atomic check code to calculate new watermark values in the | |
15765 | * state object. | |
15766 | */ | |
15767 | static void sanitize_watermarks(struct drm_device *dev) | |
15768 | { | |
15769 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15770 | struct drm_atomic_state *state; | |
15771 | struct drm_crtc *crtc; | |
15772 | struct drm_crtc_state *cstate; | |
15773 | struct drm_modeset_acquire_ctx ctx; | |
15774 | int ret; | |
15775 | int i; | |
15776 | ||
15777 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15778 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15779 | return; |
15780 | ||
15781 | /* | |
15782 | * We need to hold connection_mutex before calling duplicate_state so | |
15783 | * that the connector loop is protected. | |
15784 | */ | |
15785 | drm_modeset_acquire_init(&ctx, 0); | |
15786 | retry: | |
0cd1262d | 15787 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15788 | if (ret == -EDEADLK) { |
15789 | drm_modeset_backoff(&ctx); | |
15790 | goto retry; | |
15791 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15792 | goto fail; |
d93c0372 MR |
15793 | } |
15794 | ||
15795 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15796 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15797 | goto fail; |
d93c0372 | 15798 | |
ed4a6a7c MR |
15799 | /* |
15800 | * Hardware readout is the only time we don't want to calculate | |
15801 | * intermediate watermarks (since we don't trust the current | |
15802 | * watermarks). | |
15803 | */ | |
15804 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15805 | ||
d93c0372 MR |
15806 | ret = intel_atomic_check(dev, state); |
15807 | if (ret) { | |
15808 | /* | |
15809 | * If we fail here, it means that the hardware appears to be | |
15810 | * programmed in a way that shouldn't be possible, given our | |
15811 | * understanding of watermark requirements. This might mean a | |
15812 | * mistake in the hardware readout code or a mistake in the | |
15813 | * watermark calculations for a given platform. Raise a WARN | |
15814 | * so that this is noticeable. | |
15815 | * | |
15816 | * If this actually happens, we'll have to just leave the | |
15817 | * BIOS-programmed watermarks untouched and hope for the best. | |
15818 | */ | |
15819 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15820 | goto fail; |
d93c0372 MR |
15821 | } |
15822 | ||
15823 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15824 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15825 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15826 | ||
ed4a6a7c MR |
15827 | cs->wm.need_postvbl_update = true; |
15828 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15829 | } |
15830 | ||
15831 | drm_atomic_state_free(state); | |
0cd1262d | 15832 | fail: |
d93c0372 MR |
15833 | drm_modeset_drop_locks(&ctx); |
15834 | drm_modeset_acquire_fini(&ctx); | |
15835 | } | |
15836 | ||
79e53945 JB |
15837 | void intel_modeset_init(struct drm_device *dev) |
15838 | { | |
72e96d64 JL |
15839 | struct drm_i915_private *dev_priv = to_i915(dev); |
15840 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15841 | int sprite, ret; |
8cc87b75 | 15842 | enum pipe pipe; |
46f297fb | 15843 | struct intel_crtc *crtc; |
79e53945 JB |
15844 | |
15845 | drm_mode_config_init(dev); | |
15846 | ||
15847 | dev->mode_config.min_width = 0; | |
15848 | dev->mode_config.min_height = 0; | |
15849 | ||
019d96cb DA |
15850 | dev->mode_config.preferred_depth = 24; |
15851 | dev->mode_config.prefer_shadow = 1; | |
15852 | ||
25bab385 TU |
15853 | dev->mode_config.allow_fb_modifiers = true; |
15854 | ||
e6ecefaa | 15855 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15856 | |
b690e96c JB |
15857 | intel_init_quirks(dev); |
15858 | ||
1fa61106 ED |
15859 | intel_init_pm(dev); |
15860 | ||
e3c74757 BW |
15861 | if (INTEL_INFO(dev)->num_pipes == 0) |
15862 | return; | |
15863 | ||
69f92f67 LW |
15864 | /* |
15865 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15866 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15867 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15868 | * indicates as much. | |
15869 | */ | |
15870 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15871 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15872 | DREF_SSC1_ENABLE); | |
15873 | ||
15874 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15875 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15876 | bios_lvds_use_ssc ? "en" : "dis", | |
15877 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15878 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15879 | } | |
15880 | } | |
15881 | ||
a6c45cf0 CW |
15882 | if (IS_GEN2(dev)) { |
15883 | dev->mode_config.max_width = 2048; | |
15884 | dev->mode_config.max_height = 2048; | |
15885 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15886 | dev->mode_config.max_width = 4096; |
15887 | dev->mode_config.max_height = 4096; | |
79e53945 | 15888 | } else { |
a6c45cf0 CW |
15889 | dev->mode_config.max_width = 8192; |
15890 | dev->mode_config.max_height = 8192; | |
79e53945 | 15891 | } |
068be561 | 15892 | |
dc41c154 VS |
15893 | if (IS_845G(dev) || IS_I865G(dev)) { |
15894 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15895 | dev->mode_config.cursor_height = 1023; | |
15896 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15897 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15898 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15899 | } else { | |
15900 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15901 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15902 | } | |
15903 | ||
72e96d64 | 15904 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15905 | |
28c97730 | 15906 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15907 | INTEL_INFO(dev)->num_pipes, |
15908 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15909 | |
055e393f | 15910 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15911 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15912 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15913 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15914 | if (ret) |
06da8da2 | 15915 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15916 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15917 | } |
79e53945 JB |
15918 | } |
15919 | ||
bfa7df01 VS |
15920 | intel_update_czclk(dev_priv); |
15921 | intel_update_cdclk(dev); | |
15922 | ||
e72f9fbf | 15923 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15924 | |
b2045352 VS |
15925 | if (dev_priv->max_cdclk_freq == 0) |
15926 | intel_update_max_cdclk(dev); | |
15927 | ||
9cce37f4 JB |
15928 | /* Just disable it once at startup */ |
15929 | i915_disable_vga(dev); | |
79e53945 | 15930 | intel_setup_outputs(dev); |
11be49eb | 15931 | |
6e9f798d | 15932 | drm_modeset_lock_all(dev); |
043e9bda | 15933 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15934 | drm_modeset_unlock_all(dev); |
46f297fb | 15935 | |
d3fcc808 | 15936 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15937 | struct intel_initial_plane_config plane_config = {}; |
15938 | ||
46f297fb JB |
15939 | if (!crtc->active) |
15940 | continue; | |
15941 | ||
46f297fb | 15942 | /* |
46f297fb JB |
15943 | * Note that reserving the BIOS fb up front prevents us |
15944 | * from stuffing other stolen allocations like the ring | |
15945 | * on top. This prevents some ugliness at boot time, and | |
15946 | * can even allow for smooth boot transitions if the BIOS | |
15947 | * fb is large enough for the active pipe configuration. | |
15948 | */ | |
eeebeac5 ML |
15949 | dev_priv->display.get_initial_plane_config(crtc, |
15950 | &plane_config); | |
15951 | ||
15952 | /* | |
15953 | * If the fb is shared between multiple heads, we'll | |
15954 | * just get the first one. | |
15955 | */ | |
15956 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15957 | } |
d93c0372 MR |
15958 | |
15959 | /* | |
15960 | * Make sure hardware watermarks really match the state we read out. | |
15961 | * Note that we need to do this after reconstructing the BIOS fb's | |
15962 | * since the watermark calculation done here will use pstate->fb. | |
15963 | */ | |
15964 | sanitize_watermarks(dev); | |
2c7111db CW |
15965 | } |
15966 | ||
7fad798e DV |
15967 | static void intel_enable_pipe_a(struct drm_device *dev) |
15968 | { | |
15969 | struct intel_connector *connector; | |
15970 | struct drm_connector *crt = NULL; | |
15971 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15972 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15973 | |
15974 | /* We can't just switch on the pipe A, we need to set things up with a | |
15975 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15976 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15977 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15978 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15979 | crt = &connector->base; | |
15980 | break; | |
15981 | } | |
15982 | } | |
15983 | ||
15984 | if (!crt) | |
15985 | return; | |
15986 | ||
208bf9fd | 15987 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15988 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15989 | } |
15990 | ||
fa555837 DV |
15991 | static bool |
15992 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15993 | { | |
7eb552ae | 15994 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 15995 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 15996 | u32 val; |
fa555837 | 15997 | |
7eb552ae | 15998 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15999 | return true; |
16000 | ||
649636ef | 16001 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
16002 | |
16003 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16004 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16005 | return false; | |
16006 | ||
16007 | return true; | |
16008 | } | |
16009 | ||
02e93c35 VS |
16010 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16011 | { | |
16012 | struct drm_device *dev = crtc->base.dev; | |
16013 | struct intel_encoder *encoder; | |
16014 | ||
16015 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16016 | return true; | |
16017 | ||
16018 | return false; | |
16019 | } | |
16020 | ||
dd756198 VS |
16021 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
16022 | { | |
16023 | struct drm_device *dev = encoder->base.dev; | |
16024 | struct intel_connector *connector; | |
16025 | ||
16026 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16027 | return true; | |
16028 | ||
16029 | return false; | |
16030 | } | |
16031 | ||
a168f5b3 VS |
16032 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16033 | enum transcoder pch_transcoder) | |
16034 | { | |
16035 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16036 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16037 | } | |
16038 | ||
24929352 DV |
16039 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16040 | { | |
16041 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16042 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16043 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16044 | |
24929352 | 16045 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16046 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16047 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16048 | ||
16049 | I915_WRITE(reg, | |
16050 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16051 | } | |
24929352 | 16052 | |
d3eaf884 | 16053 | /* restore vblank interrupts to correct state */ |
9625604c | 16054 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16055 | if (crtc->active) { |
f9cd7b88 VS |
16056 | struct intel_plane *plane; |
16057 | ||
9625604c | 16058 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16059 | |
16060 | /* Disable everything but the primary plane */ | |
16061 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16062 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16063 | continue; | |
16064 | ||
16065 | plane->disable_plane(&plane->base, &crtc->base); | |
16066 | } | |
9625604c | 16067 | } |
d3eaf884 | 16068 | |
24929352 | 16069 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16070 | * disable the crtc (and hence change the state) if it is wrong. Note |
16071 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
16072 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
16073 | bool plane; |
16074 | ||
78108b7c VS |
16075 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16076 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16077 | |
16078 | /* Pipe has the wrong plane attached and the plane is active. | |
16079 | * Temporarily change the plane mapping and disable everything | |
16080 | * ... */ | |
16081 | plane = crtc->plane; | |
b70709a6 | 16082 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 16083 | crtc->plane = !plane; |
b17d48e2 | 16084 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16085 | crtc->plane = plane; |
24929352 | 16086 | } |
24929352 | 16087 | |
7fad798e DV |
16088 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16089 | crtc->pipe == PIPE_A && !crtc->active) { | |
16090 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16091 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16092 | * call below we restore the pipe to the right state, but leave | |
16093 | * the required bits on. */ | |
16094 | intel_enable_pipe_a(dev); | |
16095 | } | |
16096 | ||
24929352 DV |
16097 | /* Adjust the state of the output pipe according to whether we |
16098 | * have active connectors/encoders. */ | |
842e0307 | 16099 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16100 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16101 | |
a3ed6aad | 16102 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
16103 | /* |
16104 | * We start out with underrun reporting disabled to avoid races. | |
16105 | * For correct bookkeeping mark this on active crtcs. | |
16106 | * | |
c5ab3bc0 DV |
16107 | * Also on gmch platforms we dont have any hardware bits to |
16108 | * disable the underrun reporting. Which means we need to start | |
16109 | * out with underrun reporting disabled also on inactive pipes, | |
16110 | * since otherwise we'll complain about the garbage we read when | |
16111 | * e.g. coming up after runtime pm. | |
16112 | * | |
4cc31489 DV |
16113 | * No protection against concurrent access is required - at |
16114 | * worst a fifo underrun happens which also sets this to false. | |
16115 | */ | |
16116 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16117 | /* |
16118 | * We track the PCH trancoder underrun reporting state | |
16119 | * within the crtc. With crtc for pipe A housing the underrun | |
16120 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16121 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16122 | * and marking underrun reporting as disabled for the non-existing | |
16123 | * PCH transcoders B and C would prevent enabling the south | |
16124 | * error interrupt (see cpt_can_enable_serr_int()). | |
16125 | */ | |
16126 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16127 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16128 | } |
24929352 DV |
16129 | } |
16130 | ||
16131 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16132 | { | |
16133 | struct intel_connector *connector; | |
16134 | struct drm_device *dev = encoder->base.dev; | |
16135 | ||
16136 | /* We need to check both for a crtc link (meaning that the | |
16137 | * encoder is active and trying to read from a pipe) and the | |
16138 | * pipe itself being active. */ | |
16139 | bool has_active_crtc = encoder->base.crtc && | |
16140 | to_intel_crtc(encoder->base.crtc)->active; | |
16141 | ||
dd756198 | 16142 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
16143 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16144 | encoder->base.base.id, | |
8e329a03 | 16145 | encoder->base.name); |
24929352 DV |
16146 | |
16147 | /* Connector is active, but has no active pipe. This is | |
16148 | * fallout from our resume register restoring. Disable | |
16149 | * the encoder manually again. */ | |
16150 | if (encoder->base.crtc) { | |
16151 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
16152 | encoder->base.base.id, | |
8e329a03 | 16153 | encoder->base.name); |
24929352 | 16154 | encoder->disable(encoder); |
a62d1497 VS |
16155 | if (encoder->post_disable) |
16156 | encoder->post_disable(encoder); | |
24929352 | 16157 | } |
7f1950fb | 16158 | encoder->base.crtc = NULL; |
24929352 DV |
16159 | |
16160 | /* Inconsistent output/port/pipe state happens presumably due to | |
16161 | * a bug in one of the get_hw_state functions. Or someplace else | |
16162 | * in our code, like the register restore mess on resume. Clamp | |
16163 | * things to off as a safer default. */ | |
3a3371ff | 16164 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16165 | if (connector->encoder != encoder) |
16166 | continue; | |
7f1950fb EE |
16167 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
16168 | connector->base.encoder = NULL; | |
24929352 DV |
16169 | } |
16170 | } | |
16171 | /* Enabled encoders without active connectors will be fixed in | |
16172 | * the crtc fixup. */ | |
16173 | } | |
16174 | ||
04098753 | 16175 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 16176 | { |
fac5e23e | 16177 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 16178 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 16179 | |
04098753 ID |
16180 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16181 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
16182 | i915_disable_vga(dev); | |
16183 | } | |
16184 | } | |
16185 | ||
16186 | void i915_redisable_vga(struct drm_device *dev) | |
16187 | { | |
fac5e23e | 16188 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 16189 | |
8dc8a27c PZ |
16190 | /* This function can be called both from intel_modeset_setup_hw_state or |
16191 | * at a very early point in our resume sequence, where the power well | |
16192 | * structures are not yet restored. Since this function is at a very | |
16193 | * paranoid "someone might have enabled VGA while we were not looking" | |
16194 | * level, just check if the power well is enabled instead of trying to | |
16195 | * follow the "don't touch the power well if we don't need it" policy | |
16196 | * the rest of the driver uses. */ | |
6392f847 | 16197 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16198 | return; |
16199 | ||
04098753 | 16200 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
16201 | |
16202 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16203 | } |
16204 | ||
f9cd7b88 | 16205 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16206 | { |
f9cd7b88 | 16207 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16208 | |
f9cd7b88 | 16209 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16210 | } |
16211 | ||
f9cd7b88 VS |
16212 | /* FIXME read out full plane state for all planes */ |
16213 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16214 | { |
b26d3ea3 | 16215 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16216 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16217 | to_intel_plane_state(primary->state); |
d032ffa0 | 16218 | |
19b8d387 | 16219 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
16220 | primary_get_hw_state(to_intel_plane(primary)); |
16221 | ||
16222 | if (plane_state->visible) | |
16223 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
16224 | } |
16225 | ||
30e984df | 16226 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16227 | { |
fac5e23e | 16228 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16229 | enum pipe pipe; |
24929352 DV |
16230 | struct intel_crtc *crtc; |
16231 | struct intel_encoder *encoder; | |
16232 | struct intel_connector *connector; | |
5358901f | 16233 | int i; |
24929352 | 16234 | |
565602d7 ML |
16235 | dev_priv->active_crtcs = 0; |
16236 | ||
d3fcc808 | 16237 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16238 | struct intel_crtc_state *crtc_state = crtc->config; |
16239 | int pixclk = 0; | |
3b117c8f | 16240 | |
ec2dc6a0 | 16241 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16242 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16243 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16244 | |
565602d7 ML |
16245 | crtc_state->base.active = crtc_state->base.enable = |
16246 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16247 | ||
16248 | crtc->base.enabled = crtc_state->base.enable; | |
16249 | crtc->active = crtc_state->base.active; | |
16250 | ||
16251 | if (crtc_state->base.active) { | |
16252 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16253 | ||
c89e39f3 | 16254 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16255 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16256 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16257 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16258 | else | |
16259 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16260 | |
16261 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16262 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16263 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16264 | } |
16265 | ||
16266 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16267 | |
f9cd7b88 | 16268 | readout_plane_state(crtc); |
24929352 | 16269 | |
78108b7c VS |
16270 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16271 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
16272 | crtc->active ? "enabled" : "disabled"); |
16273 | } | |
16274 | ||
5358901f DV |
16275 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16276 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16277 | ||
2edd6443 ACO |
16278 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16279 | &pll->config.hw_state); | |
3e369b76 | 16280 | pll->config.crtc_mask = 0; |
d3fcc808 | 16281 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16282 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16283 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16284 | } |
2dd66ebd | 16285 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16286 | |
1e6f2ddc | 16287 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16288 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16289 | } |
16290 | ||
b2784e15 | 16291 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16292 | pipe = 0; |
16293 | ||
16294 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16295 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16296 | encoder->base.crtc = &crtc->base; | |
253c84c8 | 16297 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16298 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16299 | } else { |
16300 | encoder->base.crtc = NULL; | |
16301 | } | |
16302 | ||
6f2bcceb | 16303 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16304 | encoder->base.base.id, |
8e329a03 | 16305 | encoder->base.name, |
24929352 | 16306 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16307 | pipe_name(pipe)); |
24929352 DV |
16308 | } |
16309 | ||
3a3371ff | 16310 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16311 | if (connector->get_hw_state(connector)) { |
16312 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16313 | |
16314 | encoder = connector->encoder; | |
16315 | connector->base.encoder = &encoder->base; | |
16316 | ||
16317 | if (encoder->base.crtc && | |
16318 | encoder->base.crtc->state->active) { | |
16319 | /* | |
16320 | * This has to be done during hardware readout | |
16321 | * because anything calling .crtc_disable may | |
16322 | * rely on the connector_mask being accurate. | |
16323 | */ | |
16324 | encoder->base.crtc->state->connector_mask |= | |
16325 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16326 | encoder->base.crtc->state->encoder_mask |= |
16327 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16328 | } |
16329 | ||
24929352 DV |
16330 | } else { |
16331 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16332 | connector->base.encoder = NULL; | |
16333 | } | |
16334 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16335 | connector->base.base.id, | |
c23cc417 | 16336 | connector->base.name, |
24929352 DV |
16337 | connector->base.encoder ? "enabled" : "disabled"); |
16338 | } | |
7f4c6284 VS |
16339 | |
16340 | for_each_intel_crtc(dev, crtc) { | |
16341 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16342 | ||
16343 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16344 | if (crtc->base.state->active) { | |
16345 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16346 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16347 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16348 | ||
16349 | /* | |
16350 | * The initial mode needs to be set in order to keep | |
16351 | * the atomic core happy. It wants a valid mode if the | |
16352 | * crtc's enabled, so we do the above call. | |
16353 | * | |
16354 | * At this point some state updated by the connectors | |
16355 | * in their ->detect() callback has not run yet, so | |
16356 | * no recalculation can be done yet. | |
16357 | * | |
16358 | * Even if we could do a recalculation and modeset | |
16359 | * right now it would cause a double modeset if | |
16360 | * fbdev or userspace chooses a different initial mode. | |
16361 | * | |
16362 | * If that happens, someone indicated they wanted a | |
16363 | * mode change, which means it's safe to do a full | |
16364 | * recalculation. | |
16365 | */ | |
16366 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16367 | |
16368 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16369 | update_scanline_offset(crtc); | |
7f4c6284 | 16370 | } |
e3b247da VS |
16371 | |
16372 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16373 | } |
30e984df DV |
16374 | } |
16375 | ||
043e9bda ML |
16376 | /* Scan out the current hw modeset state, |
16377 | * and sanitizes it to the current state | |
16378 | */ | |
16379 | static void | |
16380 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16381 | { |
fac5e23e | 16382 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16383 | enum pipe pipe; |
30e984df DV |
16384 | struct intel_crtc *crtc; |
16385 | struct intel_encoder *encoder; | |
35c95375 | 16386 | int i; |
30e984df DV |
16387 | |
16388 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16389 | |
16390 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16391 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16392 | intel_sanitize_encoder(encoder); |
16393 | } | |
16394 | ||
055e393f | 16395 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16396 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16397 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16398 | intel_dump_pipe_config(crtc, crtc->config, |
16399 | "[setup_hw_state]"); | |
24929352 | 16400 | } |
9a935856 | 16401 | |
d29b2f9d ACO |
16402 | intel_modeset_update_connector_atomic_state(dev); |
16403 | ||
35c95375 DV |
16404 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16405 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16406 | ||
2dd66ebd | 16407 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16408 | continue; |
16409 | ||
16410 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16411 | ||
2edd6443 | 16412 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16413 | pll->on = false; |
16414 | } | |
16415 | ||
666a4537 | 16416 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16417 | vlv_wm_get_hw_state(dev); |
16418 | else if (IS_GEN9(dev)) | |
3078999f PB |
16419 | skl_wm_get_hw_state(dev); |
16420 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16421 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16422 | |
16423 | for_each_intel_crtc(dev, crtc) { | |
16424 | unsigned long put_domains; | |
16425 | ||
74bff5f9 | 16426 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16427 | if (WARN_ON(put_domains)) |
16428 | modeset_put_power_domains(dev_priv, put_domains); | |
16429 | } | |
16430 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16431 | |
16432 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16433 | } |
7d0bc1ea | 16434 | |
043e9bda ML |
16435 | void intel_display_resume(struct drm_device *dev) |
16436 | { | |
e2c8b870 ML |
16437 | struct drm_i915_private *dev_priv = to_i915(dev); |
16438 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16439 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16440 | int ret; |
f30da187 | 16441 | |
e2c8b870 | 16442 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
16443 | if (state) |
16444 | state->acquire_ctx = &ctx; | |
043e9bda | 16445 | |
ea49c9ac ML |
16446 | /* |
16447 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16448 | * won't be taken. Unfortunately some probed state like | |
16449 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16450 | * it here for now. | |
16451 | */ | |
16452 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16453 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16454 | |
73974893 ML |
16455 | while (1) { |
16456 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
16457 | if (ret != -EDEADLK) | |
16458 | break; | |
043e9bda | 16459 | |
e2c8b870 | 16460 | drm_modeset_backoff(&ctx); |
e2c8b870 | 16461 | } |
043e9bda | 16462 | |
73974893 ML |
16463 | if (!ret) |
16464 | ret = __intel_display_resume(dev, state); | |
16465 | ||
e2c8b870 ML |
16466 | drm_modeset_drop_locks(&ctx); |
16467 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16468 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16469 | |
e2c8b870 ML |
16470 | if (ret) { |
16471 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16472 | drm_atomic_state_free(state); | |
16473 | } | |
2c7111db CW |
16474 | } |
16475 | ||
16476 | void intel_modeset_gem_init(struct drm_device *dev) | |
16477 | { | |
dc97997a | 16478 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 16479 | struct drm_crtc *c; |
2ff8fde1 | 16480 | struct drm_i915_gem_object *obj; |
e0d6149b | 16481 | int ret; |
484b41dd | 16482 | |
dc97997a | 16483 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16484 | |
1833b134 | 16485 | intel_modeset_init_hw(dev); |
02e792fb | 16486 | |
1ee8da6d | 16487 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16488 | |
16489 | /* | |
16490 | * Make sure any fbs we allocated at startup are properly | |
16491 | * pinned & fenced. When we do the allocation it's too early | |
16492 | * for this. | |
16493 | */ | |
70e1e0ec | 16494 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16495 | obj = intel_fb_obj(c->primary->fb); |
16496 | if (obj == NULL) | |
484b41dd JB |
16497 | continue; |
16498 | ||
e0d6149b | 16499 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16500 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16501 | c->primary->state->rotation); | |
e0d6149b TU |
16502 | mutex_unlock(&dev->struct_mutex); |
16503 | if (ret) { | |
484b41dd JB |
16504 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16505 | to_intel_crtc(c)->pipe); | |
66e514c1 | 16506 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 16507 | c->primary->fb = NULL; |
36750f28 | 16508 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 16509 | update_state_fb(c->primary); |
36750f28 | 16510 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16511 | } |
16512 | } | |
1ebaa0b9 CW |
16513 | } |
16514 | ||
16515 | int intel_connector_register(struct drm_connector *connector) | |
16516 | { | |
16517 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
16518 | int ret; | |
16519 | ||
16520 | ret = intel_backlight_device_register(intel_connector); | |
16521 | if (ret) | |
16522 | goto err; | |
16523 | ||
16524 | return 0; | |
0962c3c9 | 16525 | |
1ebaa0b9 CW |
16526 | err: |
16527 | return ret; | |
79e53945 JB |
16528 | } |
16529 | ||
c191eca1 | 16530 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 16531 | { |
e63d87c0 | 16532 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 16533 | |
e63d87c0 | 16534 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 16535 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
16536 | } |
16537 | ||
79e53945 JB |
16538 | void intel_modeset_cleanup(struct drm_device *dev) |
16539 | { | |
fac5e23e | 16540 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 16541 | |
dc97997a | 16542 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16543 | |
fd0c0642 DV |
16544 | /* |
16545 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16546 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16547 | * experience fancy races otherwise. |
16548 | */ | |
2aeb7d3a | 16549 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16550 | |
fd0c0642 DV |
16551 | /* |
16552 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16553 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16554 | */ | |
f87ea761 | 16555 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16556 | |
723bfd70 JB |
16557 | intel_unregister_dsm_handler(); |
16558 | ||
c937ab3e | 16559 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16560 | |
1630fe75 CW |
16561 | /* flush any delayed tasks or pending work */ |
16562 | flush_scheduled_work(); | |
16563 | ||
79e53945 | 16564 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16565 | |
1ee8da6d | 16566 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16567 | |
dc97997a | 16568 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16569 | |
16570 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16571 | } |
16572 | ||
df0e9248 CW |
16573 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16574 | struct intel_encoder *encoder) | |
16575 | { | |
16576 | connector->encoder = encoder; | |
16577 | drm_mode_connector_attach_encoder(&connector->base, | |
16578 | &encoder->base); | |
79e53945 | 16579 | } |
28d52043 DA |
16580 | |
16581 | /* | |
16582 | * set vga decode state - true == enable VGA decode | |
16583 | */ | |
16584 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16585 | { | |
fac5e23e | 16586 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 16587 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16588 | u16 gmch_ctrl; |
16589 | ||
75fa041d CW |
16590 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16591 | DRM_ERROR("failed to read control word\n"); | |
16592 | return -EIO; | |
16593 | } | |
16594 | ||
c0cc8a55 CW |
16595 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16596 | return 0; | |
16597 | ||
28d52043 DA |
16598 | if (state) |
16599 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16600 | else | |
16601 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16602 | |
16603 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16604 | DRM_ERROR("failed to write control word\n"); | |
16605 | return -EIO; | |
16606 | } | |
16607 | ||
28d52043 DA |
16608 | return 0; |
16609 | } | |
c4a1d9e4 | 16610 | |
c4a1d9e4 | 16611 | struct intel_display_error_state { |
ff57f1b0 PZ |
16612 | |
16613 | u32 power_well_driver; | |
16614 | ||
63b66e5b CW |
16615 | int num_transcoders; |
16616 | ||
c4a1d9e4 CW |
16617 | struct intel_cursor_error_state { |
16618 | u32 control; | |
16619 | u32 position; | |
16620 | u32 base; | |
16621 | u32 size; | |
52331309 | 16622 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16623 | |
16624 | struct intel_pipe_error_state { | |
ddf9c536 | 16625 | bool power_domain_on; |
c4a1d9e4 | 16626 | u32 source; |
f301b1e1 | 16627 | u32 stat; |
52331309 | 16628 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16629 | |
16630 | struct intel_plane_error_state { | |
16631 | u32 control; | |
16632 | u32 stride; | |
16633 | u32 size; | |
16634 | u32 pos; | |
16635 | u32 addr; | |
16636 | u32 surface; | |
16637 | u32 tile_offset; | |
52331309 | 16638 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16639 | |
16640 | struct intel_transcoder_error_state { | |
ddf9c536 | 16641 | bool power_domain_on; |
63b66e5b CW |
16642 | enum transcoder cpu_transcoder; |
16643 | ||
16644 | u32 conf; | |
16645 | ||
16646 | u32 htotal; | |
16647 | u32 hblank; | |
16648 | u32 hsync; | |
16649 | u32 vtotal; | |
16650 | u32 vblank; | |
16651 | u32 vsync; | |
16652 | } transcoder[4]; | |
c4a1d9e4 CW |
16653 | }; |
16654 | ||
16655 | struct intel_display_error_state * | |
c033666a | 16656 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16657 | { |
c4a1d9e4 | 16658 | struct intel_display_error_state *error; |
63b66e5b CW |
16659 | int transcoders[] = { |
16660 | TRANSCODER_A, | |
16661 | TRANSCODER_B, | |
16662 | TRANSCODER_C, | |
16663 | TRANSCODER_EDP, | |
16664 | }; | |
c4a1d9e4 CW |
16665 | int i; |
16666 | ||
c033666a | 16667 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16668 | return NULL; |
16669 | ||
9d1cb914 | 16670 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16671 | if (error == NULL) |
16672 | return NULL; | |
16673 | ||
c033666a | 16674 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16675 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16676 | ||
055e393f | 16677 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16678 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16679 | __intel_display_power_is_enabled(dev_priv, |
16680 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16681 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16682 | continue; |
16683 | ||
5efb3e28 VS |
16684 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16685 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16686 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16687 | |
16688 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16689 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16690 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16691 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16692 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16693 | } | |
c033666a | 16694 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16695 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16696 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16697 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16698 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16699 | } | |
16700 | ||
c4a1d9e4 | 16701 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16702 | |
c033666a | 16703 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16704 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16705 | } |
16706 | ||
4d1de975 | 16707 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16708 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16709 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16710 | error->num_transcoders++; /* Account for eDP. */ |
16711 | ||
16712 | for (i = 0; i < error->num_transcoders; i++) { | |
16713 | enum transcoder cpu_transcoder = transcoders[i]; | |
16714 | ||
ddf9c536 | 16715 | error->transcoder[i].power_domain_on = |
f458ebbc | 16716 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16717 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16718 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16719 | continue; |
16720 | ||
63b66e5b CW |
16721 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16722 | ||
16723 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16724 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16725 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16726 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16727 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16728 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16729 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16730 | } |
16731 | ||
16732 | return error; | |
16733 | } | |
16734 | ||
edc3d884 MK |
16735 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16736 | ||
c4a1d9e4 | 16737 | void |
edc3d884 | 16738 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16739 | struct drm_device *dev, |
16740 | struct intel_display_error_state *error) | |
16741 | { | |
fac5e23e | 16742 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
16743 | int i; |
16744 | ||
63b66e5b CW |
16745 | if (!error) |
16746 | return; | |
16747 | ||
edc3d884 | 16748 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16749 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16750 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16751 | error->power_well_driver); |
055e393f | 16752 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16753 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16754 | err_printf(m, " Power: %s\n", |
87ad3212 | 16755 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16756 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16757 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16758 | |
16759 | err_printf(m, "Plane [%d]:\n", i); | |
16760 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16761 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16762 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16763 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16764 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16765 | } |
4b71a570 | 16766 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16767 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16768 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16769 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16770 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16771 | } |
16772 | ||
edc3d884 MK |
16773 | err_printf(m, "Cursor [%d]:\n", i); |
16774 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16775 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16776 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16777 | } |
63b66e5b CW |
16778 | |
16779 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16780 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16781 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16782 | err_printf(m, " Power: %s\n", |
87ad3212 | 16783 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16784 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16785 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16786 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16787 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16788 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16789 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16790 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16791 | } | |
c4a1d9e4 | 16792 | } |