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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
d2acd215 DV |
172 | int |
173 | intel_pch_rawclk(struct drm_device *dev) | |
174 | { | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | ||
177 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
178 | ||
179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
180 | } | |
181 | ||
79e50a4f JN |
182 | /* hrawclock is 1/4 the FSB frequency */ |
183 | int intel_hrawclk(struct drm_device *dev) | |
184 | { | |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
186 | uint32_t clkcfg; | |
187 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
190 | return 200; |
191 | ||
192 | clkcfg = I915_READ(CLKCFG); | |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
195 | return 100; | |
196 | case CLKCFG_FSB_533: | |
197 | return 133; | |
198 | case CLKCFG_FSB_667: | |
199 | return 166; | |
200 | case CLKCFG_FSB_800: | |
201 | return 200; | |
202 | case CLKCFG_FSB_1067: | |
203 | return 266; | |
204 | case CLKCFG_FSB_1333: | |
205 | return 333; | |
206 | /* these two are just a guess; one of them might be right */ | |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
209 | return 400; | |
210 | default: | |
211 | return 133; | |
212 | } | |
213 | } | |
214 | ||
bfa7df01 VS |
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { | |
666a4537 | 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
218 | return; |
219 | ||
220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
221 | CCK_CZ_CLOCK_CONTROL); | |
222 | ||
223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
224 | } | |
225 | ||
021357ac CW |
226 | static inline u32 /* units of 100MHz */ |
227 | intel_fdi_link_freq(struct drm_device *dev) | |
228 | { | |
8b99e68c CW |
229 | if (IS_GEN5(dev)) { |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
232 | } else | |
233 | return 27; | |
021357ac CW |
234 | } |
235 | ||
5d536e28 | 236 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 237 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 238 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 239 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
240 | .m = { .min = 96, .max = 140 }, |
241 | .m1 = { .min = 18, .max = 26 }, | |
242 | .m2 = { .min = 6, .max = 16 }, | |
243 | .p = { .min = 4, .max = 128 }, | |
244 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
245 | .p2 = { .dot_limit = 165000, |
246 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
247 | }; |
248 | ||
5d536e28 DV |
249 | static const intel_limit_t intel_limits_i8xx_dvo = { |
250 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 251 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 252 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
253 | .m = { .min = 96, .max = 140 }, |
254 | .m1 = { .min = 18, .max = 26 }, | |
255 | .m2 = { .min = 6, .max = 16 }, | |
256 | .p = { .min = 4, .max = 128 }, | |
257 | .p1 = { .min = 2, .max = 33 }, | |
258 | .p2 = { .dot_limit = 165000, | |
259 | .p2_slow = 4, .p2_fast = 4 }, | |
260 | }; | |
261 | ||
e4b36699 | 262 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 273 | }; |
273e27ca | 274 | |
e4b36699 | 275 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
276 | .dot = { .min = 20000, .max = 400000 }, |
277 | .vco = { .min = 1400000, .max = 2800000 }, | |
278 | .n = { .min = 1, .max = 6 }, | |
279 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
280 | .m1 = { .min = 8, .max = 18 }, |
281 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
282 | .p = { .min = 5, .max = 80 }, |
283 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
284 | .p2 = { .dot_limit = 200000, |
285 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
286 | }; |
287 | ||
288 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
289 | .dot = { .min = 20000, .max = 400000 }, |
290 | .vco = { .min = 1400000, .max = 2800000 }, | |
291 | .n = { .min = 1, .max = 6 }, | |
292 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
293 | .m1 = { .min = 8, .max = 18 }, |
294 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
295 | .p = { .min = 7, .max = 98 }, |
296 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 112000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
299 | }; |
300 | ||
273e27ca | 301 | |
e4b36699 | 302 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 270000 }, |
304 | .vco = { .min = 1750000, .max = 3500000}, | |
305 | .n = { .min = 1, .max = 4 }, | |
306 | .m = { .min = 104, .max = 138 }, | |
307 | .m1 = { .min = 17, .max = 23 }, | |
308 | .m2 = { .min = 5, .max = 11 }, | |
309 | .p = { .min = 10, .max = 30 }, | |
310 | .p1 = { .min = 1, .max = 3}, | |
311 | .p2 = { .dot_limit = 270000, | |
312 | .p2_slow = 10, | |
313 | .p2_fast = 10 | |
044c7c41 | 314 | }, |
e4b36699 KP |
315 | }; |
316 | ||
317 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
318 | .dot = { .min = 22000, .max = 400000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 16, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 5, .max = 80 }, | |
325 | .p1 = { .min = 1, .max = 8}, | |
326 | .p2 = { .dot_limit = 165000, | |
327 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
328 | }; |
329 | ||
330 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
331 | .dot = { .min = 20000, .max = 115000 }, |
332 | .vco = { .min = 1750000, .max = 3500000 }, | |
333 | .n = { .min = 1, .max = 3 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 28, .max = 112 }, | |
338 | .p1 = { .min = 2, .max = 8 }, | |
339 | .p2 = { .dot_limit = 0, | |
340 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
344 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
345 | .dot = { .min = 80000, .max = 224000 }, |
346 | .vco = { .min = 1750000, .max = 3500000 }, | |
347 | .n = { .min = 1, .max = 3 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 17, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 14, .max = 42 }, | |
352 | .p1 = { .min = 2, .max = 6 }, | |
353 | .p2 = { .dot_limit = 0, | |
354 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 355 | }, |
e4b36699 KP |
356 | }; |
357 | ||
f2b115e6 | 358 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
359 | .dot = { .min = 20000, .max = 400000}, |
360 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 361 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
362 | .n = { .min = 3, .max = 6 }, |
363 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 364 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
365 | .m1 = { .min = 0, .max = 0 }, |
366 | .m2 = { .min = 0, .max = 254 }, | |
367 | .p = { .min = 5, .max = 80 }, | |
368 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
369 | .p2 = { .dot_limit = 200000, |
370 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000 }, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
376 | .n = { .min = 3, .max = 6 }, | |
377 | .m = { .min = 2, .max = 256 }, | |
378 | .m1 = { .min = 0, .max = 0 }, | |
379 | .m2 = { .min = 0, .max = 254 }, | |
380 | .p = { .min = 7, .max = 112 }, | |
381 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
382 | .p2 = { .dot_limit = 112000, |
383 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
384 | }; |
385 | ||
273e27ca EA |
386 | /* Ironlake / Sandybridge |
387 | * | |
388 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
389 | * the range value for them is (actual_value - 2). | |
390 | */ | |
b91ad0ec | 391 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
392 | .dot = { .min = 25000, .max = 350000 }, |
393 | .vco = { .min = 1760000, .max = 3510000 }, | |
394 | .n = { .min = 1, .max = 5 }, | |
395 | .m = { .min = 79, .max = 127 }, | |
396 | .m1 = { .min = 12, .max = 22 }, | |
397 | .m2 = { .min = 5, .max = 9 }, | |
398 | .p = { .min = 5, .max = 80 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
400 | .p2 = { .dot_limit = 225000, | |
401 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
402 | }; |
403 | ||
b91ad0ec | 404 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
405 | .dot = { .min = 25000, .max = 350000 }, |
406 | .vco = { .min = 1760000, .max = 3510000 }, | |
407 | .n = { .min = 1, .max = 3 }, | |
408 | .m = { .min = 79, .max = 118 }, | |
409 | .m1 = { .min = 12, .max = 22 }, | |
410 | .m2 = { .min = 5, .max = 9 }, | |
411 | .p = { .min = 28, .max = 112 }, | |
412 | .p1 = { .min = 2, .max = 8 }, | |
413 | .p2 = { .dot_limit = 225000, | |
414 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
415 | }; |
416 | ||
417 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 3 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 14, .max = 56 }, | |
425 | .p1 = { .min = 2, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
428 | }; |
429 | ||
273e27ca | 430 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 431 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 2 }, | |
435 | .m = { .min = 79, .max = 126 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 439 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
440 | .p2 = { .dot_limit = 225000, |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 126 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 452 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
453 | .p2 = { .dot_limit = 225000, |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
455 | }; |
456 | ||
dc730512 | 457 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
458 | /* |
459 | * These are the data rate limits (measured in fast clocks) | |
460 | * since those are the strictest limits we have. The fast | |
461 | * clock and actual rate limits are more relaxed, so checking | |
462 | * them would make no difference. | |
463 | */ | |
464 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 465 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 466 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
467 | .m1 = { .min = 2, .max = 3 }, |
468 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 469 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 470 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
471 | }; |
472 | ||
ef9348c8 CML |
473 | static const intel_limit_t intel_limits_chv = { |
474 | /* | |
475 | * These are the data rate limits (measured in fast clocks) | |
476 | * since those are the strictest limits we have. The fast | |
477 | * clock and actual rate limits are more relaxed, so checking | |
478 | * them would make no difference. | |
479 | */ | |
480 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 481 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
482 | .n = { .min = 1, .max = 1 }, |
483 | .m1 = { .min = 2, .max = 2 }, | |
484 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
485 | .p1 = { .min = 2, .max = 4 }, | |
486 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
487 | }; | |
488 | ||
5ab7b0b7 ID |
489 | static const intel_limit_t intel_limits_bxt = { |
490 | /* FIXME: find real dot limits */ | |
491 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 492 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
493 | .n = { .min = 1, .max = 1 }, |
494 | .m1 = { .min = 2, .max = 2 }, | |
495 | /* FIXME: find real m2 limits */ | |
496 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
497 | .p1 = { .min = 2, .max = 4 }, | |
498 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
499 | }; | |
500 | ||
cdba954e ACO |
501 | static bool |
502 | needs_modeset(struct drm_crtc_state *state) | |
503 | { | |
fc596660 | 504 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
505 | } |
506 | ||
e0638cdf PZ |
507 | /** |
508 | * Returns whether any output on the specified pipe is of the specified type | |
509 | */ | |
4093561b | 510 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 511 | { |
409ee761 | 512 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
513 | struct intel_encoder *encoder; |
514 | ||
409ee761 | 515 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
516 | if (encoder->type == type) |
517 | return true; | |
518 | ||
519 | return false; | |
520 | } | |
521 | ||
d0737e1d ACO |
522 | /** |
523 | * Returns whether any output on the specified pipe will have the specified | |
524 | * type after a staged modeset is complete, i.e., the same as | |
525 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
526 | * encoder->crtc. | |
527 | */ | |
a93e255f ACO |
528 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
529 | int type) | |
d0737e1d | 530 | { |
a93e255f | 531 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 532 | struct drm_connector *connector; |
a93e255f | 533 | struct drm_connector_state *connector_state; |
d0737e1d | 534 | struct intel_encoder *encoder; |
a93e255f ACO |
535 | int i, num_connectors = 0; |
536 | ||
da3ced29 | 537 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
538 | if (connector_state->crtc != crtc_state->base.crtc) |
539 | continue; | |
540 | ||
541 | num_connectors++; | |
d0737e1d | 542 | |
a93e255f ACO |
543 | encoder = to_intel_encoder(connector_state->best_encoder); |
544 | if (encoder->type == type) | |
d0737e1d | 545 | return true; |
a93e255f ACO |
546 | } |
547 | ||
548 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
549 | |
550 | return false; | |
551 | } | |
552 | ||
a93e255f ACO |
553 | static const intel_limit_t * |
554 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 555 | { |
a93e255f | 556 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 557 | const intel_limit_t *limit; |
b91ad0ec | 558 | |
a93e255f | 559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 560 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 561 | if (refclk == 100000) |
b91ad0ec ZW |
562 | limit = &intel_limits_ironlake_dual_lvds_100m; |
563 | else | |
564 | limit = &intel_limits_ironlake_dual_lvds; | |
565 | } else { | |
1b894b59 | 566 | if (refclk == 100000) |
b91ad0ec ZW |
567 | limit = &intel_limits_ironlake_single_lvds_100m; |
568 | else | |
569 | limit = &intel_limits_ironlake_single_lvds; | |
570 | } | |
c6bb3538 | 571 | } else |
b91ad0ec | 572 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
573 | |
574 | return limit; | |
575 | } | |
576 | ||
a93e255f ACO |
577 | static const intel_limit_t * |
578 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 579 | { |
a93e255f | 580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
581 | const intel_limit_t *limit; |
582 | ||
a93e255f | 583 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 584 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 585 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 586 | else |
e4b36699 | 587 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
588 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
589 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 590 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 591 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 592 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 593 | } else /* The option is for other outputs */ |
e4b36699 | 594 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
595 | |
596 | return limit; | |
597 | } | |
598 | ||
a93e255f ACO |
599 | static const intel_limit_t * |
600 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 601 | { |
a93e255f | 602 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
603 | const intel_limit_t *limit; |
604 | ||
5ab7b0b7 ID |
605 | if (IS_BROXTON(dev)) |
606 | limit = &intel_limits_bxt; | |
607 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 608 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 609 | else if (IS_G4X(dev)) { |
a93e255f | 610 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 611 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 613 | limit = &intel_limits_pineview_lvds; |
2177832f | 614 | else |
f2b115e6 | 615 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
616 | } else if (IS_CHERRYVIEW(dev)) { |
617 | limit = &intel_limits_chv; | |
a0c4da24 | 618 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 619 | limit = &intel_limits_vlv; |
a6c45cf0 | 620 | } else if (!IS_GEN2(dev)) { |
a93e255f | 621 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
622 | limit = &intel_limits_i9xx_lvds; |
623 | else | |
624 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 625 | } else { |
a93e255f | 626 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 627 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 628 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
630 | else |
631 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
632 | } |
633 | return limit; | |
634 | } | |
635 | ||
dccbea3b ID |
636 | /* |
637 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
638 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
639 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
640 | * The helpers' return value is the rate of the clock that is fed to the | |
641 | * display engine's pipe which can be the above fast dot clock rate or a | |
642 | * divided-down version of it. | |
643 | */ | |
f2b115e6 | 644 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 645 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 646 | { |
2177832f SL |
647 | clock->m = clock->m2 + 2; |
648 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 649 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 650 | return 0; |
fb03ac01 VS |
651 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
652 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
653 | |
654 | return clock->dot; | |
2177832f SL |
655 | } |
656 | ||
7429e9d4 DV |
657 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
658 | { | |
659 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
660 | } | |
661 | ||
dccbea3b | 662 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 663 | { |
7429e9d4 | 664 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 665 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 666 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 667 | return 0; |
fb03ac01 VS |
668 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
669 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
670 | |
671 | return clock->dot; | |
79e53945 JB |
672 | } |
673 | ||
dccbea3b | 674 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
675 | { |
676 | clock->m = clock->m1 * clock->m2; | |
677 | clock->p = clock->p1 * clock->p2; | |
678 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 679 | return 0; |
589eca67 ID |
680 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
681 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
682 | |
683 | return clock->dot / 5; | |
589eca67 ID |
684 | } |
685 | ||
dccbea3b | 686 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
687 | { |
688 | clock->m = clock->m1 * clock->m2; | |
689 | clock->p = clock->p1 * clock->p2; | |
690 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 691 | return 0; |
ef9348c8 CML |
692 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
693 | clock->n << 22); | |
694 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
695 | |
696 | return clock->dot / 5; | |
ef9348c8 CML |
697 | } |
698 | ||
7c04d1d9 | 699 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
700 | /** |
701 | * Returns whether the given set of divisors are valid for a given refclk with | |
702 | * the given connectors. | |
703 | */ | |
704 | ||
1b894b59 CW |
705 | static bool intel_PLL_is_valid(struct drm_device *dev, |
706 | const intel_limit_t *limit, | |
707 | const intel_clock_t *clock) | |
79e53945 | 708 | { |
f01b7962 VS |
709 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
710 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 711 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 712 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 714 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 716 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 717 | |
666a4537 WB |
718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
719 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
720 | if (clock->m1 <= clock->m2) |
721 | INTELPllInvalid("m1 <= m2\n"); | |
722 | ||
666a4537 | 723 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
724 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
725 | INTELPllInvalid("p out of range\n"); | |
726 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
727 | INTELPllInvalid("m out of range\n"); | |
728 | } | |
729 | ||
79e53945 | 730 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 731 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
732 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
733 | * connector, etc., rather than just a single range. | |
734 | */ | |
735 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 736 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
737 | |
738 | return true; | |
739 | } | |
740 | ||
3b1429d9 VS |
741 | static int |
742 | i9xx_select_p2_div(const intel_limit_t *limit, | |
743 | const struct intel_crtc_state *crtc_state, | |
744 | int target) | |
79e53945 | 745 | { |
3b1429d9 | 746 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 747 | |
a93e255f | 748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 749 | /* |
a210b028 DV |
750 | * For LVDS just rely on its current settings for dual-channel. |
751 | * We haven't figured out how to reliably set up different | |
752 | * single/dual channel state, if we even can. | |
79e53945 | 753 | */ |
1974cad0 | 754 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 755 | return limit->p2.p2_fast; |
79e53945 | 756 | else |
3b1429d9 | 757 | return limit->p2.p2_slow; |
79e53945 JB |
758 | } else { |
759 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 760 | return limit->p2.p2_slow; |
79e53945 | 761 | else |
3b1429d9 | 762 | return limit->p2.p2_fast; |
79e53945 | 763 | } |
3b1429d9 VS |
764 | } |
765 | ||
766 | static bool | |
767 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
768 | struct intel_crtc_state *crtc_state, | |
769 | int target, int refclk, intel_clock_t *match_clock, | |
770 | intel_clock_t *best_clock) | |
771 | { | |
772 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
773 | intel_clock_t clock; | |
774 | int err = target; | |
79e53945 | 775 | |
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 784 | if (clock.m2 >= clock.m1) |
42158660 ZY |
785 | break; |
786 | for (clock.n = limit->n.min; | |
787 | clock.n <= limit->n.max; clock.n++) { | |
788 | for (clock.p1 = limit->p1.min; | |
789 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
790 | int this_err; |
791 | ||
dccbea3b | 792 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
793 | if (!intel_PLL_is_valid(dev, limit, |
794 | &clock)) | |
795 | continue; | |
796 | if (match_clock && | |
797 | clock.p != match_clock->p) | |
798 | continue; | |
799 | ||
800 | this_err = abs(clock.dot - target); | |
801 | if (this_err < err) { | |
802 | *best_clock = clock; | |
803 | err = this_err; | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
810 | return (err != target); | |
811 | } | |
812 | ||
813 | static bool | |
a93e255f ACO |
814 | pnv_find_best_dpll(const intel_limit_t *limit, |
815 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
816 | int target, int refclk, intel_clock_t *match_clock, |
817 | intel_clock_t *best_clock) | |
79e53945 | 818 | { |
3b1429d9 | 819 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 820 | intel_clock_t clock; |
79e53945 JB |
821 | int err = target; |
822 | ||
0206e353 | 823 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 824 | |
3b1429d9 VS |
825 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
826 | ||
42158660 ZY |
827 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
828 | clock.m1++) { | |
829 | for (clock.m2 = limit->m2.min; | |
830 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
831 | for (clock.n = limit->n.min; |
832 | clock.n <= limit->n.max; clock.n++) { | |
833 | for (clock.p1 = limit->p1.min; | |
834 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
835 | int this_err; |
836 | ||
dccbea3b | 837 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
838 | if (!intel_PLL_is_valid(dev, limit, |
839 | &clock)) | |
79e53945 | 840 | continue; |
cec2f356 SP |
841 | if (match_clock && |
842 | clock.p != match_clock->p) | |
843 | continue; | |
79e53945 JB |
844 | |
845 | this_err = abs(clock.dot - target); | |
846 | if (this_err < err) { | |
847 | *best_clock = clock; | |
848 | err = this_err; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | return (err != target); | |
856 | } | |
857 | ||
d4906093 | 858 | static bool |
a93e255f ACO |
859 | g4x_find_best_dpll(const intel_limit_t *limit, |
860 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
861 | int target, int refclk, intel_clock_t *match_clock, |
862 | intel_clock_t *best_clock) | |
d4906093 | 863 | { |
3b1429d9 | 864 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
865 | intel_clock_t clock; |
866 | int max_n; | |
3b1429d9 | 867 | bool found = false; |
6ba770dc AJ |
868 | /* approximately equals target * 0.00585 */ |
869 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
870 | |
871 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
872 | |
873 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
874 | ||
d4906093 | 875 | max_n = limit->n.max; |
f77f13e2 | 876 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 877 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 878 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
879 | for (clock.m1 = limit->m1.max; |
880 | clock.m1 >= limit->m1.min; clock.m1--) { | |
881 | for (clock.m2 = limit->m2.max; | |
882 | clock.m2 >= limit->m2.min; clock.m2--) { | |
883 | for (clock.p1 = limit->p1.max; | |
884 | clock.p1 >= limit->p1.min; clock.p1--) { | |
885 | int this_err; | |
886 | ||
dccbea3b | 887 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
888 | if (!intel_PLL_is_valid(dev, limit, |
889 | &clock)) | |
d4906093 | 890 | continue; |
1b894b59 CW |
891 | |
892 | this_err = abs(clock.dot - target); | |
d4906093 ML |
893 | if (this_err < err_most) { |
894 | *best_clock = clock; | |
895 | err_most = this_err; | |
896 | max_n = clock.n; | |
897 | found = true; | |
898 | } | |
899 | } | |
900 | } | |
901 | } | |
902 | } | |
2c07245f ZW |
903 | return found; |
904 | } | |
905 | ||
d5dd62bd ID |
906 | /* |
907 | * Check if the calculated PLL configuration is more optimal compared to the | |
908 | * best configuration and error found so far. Return the calculated error. | |
909 | */ | |
910 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
911 | const intel_clock_t *calculated_clock, | |
912 | const intel_clock_t *best_clock, | |
913 | unsigned int best_error_ppm, | |
914 | unsigned int *error_ppm) | |
915 | { | |
9ca3ba01 ID |
916 | /* |
917 | * For CHV ignore the error and consider only the P value. | |
918 | * Prefer a bigger P value based on HW requirements. | |
919 | */ | |
920 | if (IS_CHERRYVIEW(dev)) { | |
921 | *error_ppm = 0; | |
922 | ||
923 | return calculated_clock->p > best_clock->p; | |
924 | } | |
925 | ||
24be4e46 ID |
926 | if (WARN_ON_ONCE(!target_freq)) |
927 | return false; | |
928 | ||
d5dd62bd ID |
929 | *error_ppm = div_u64(1000000ULL * |
930 | abs(target_freq - calculated_clock->dot), | |
931 | target_freq); | |
932 | /* | |
933 | * Prefer a better P value over a better (smaller) error if the error | |
934 | * is small. Ensure this preference for future configurations too by | |
935 | * setting the error to 0. | |
936 | */ | |
937 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
938 | *error_ppm = 0; | |
939 | ||
940 | return true; | |
941 | } | |
942 | ||
943 | return *error_ppm + 10 < best_error_ppm; | |
944 | } | |
945 | ||
a0c4da24 | 946 | static bool |
a93e255f ACO |
947 | vlv_find_best_dpll(const intel_limit_t *limit, |
948 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
949 | int target, int refclk, intel_clock_t *match_clock, |
950 | intel_clock_t *best_clock) | |
a0c4da24 | 951 | { |
a93e255f | 952 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 953 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 954 | intel_clock_t clock; |
69e4f900 | 955 | unsigned int bestppm = 1000000; |
27e639bf VS |
956 | /* min update 19.2 MHz */ |
957 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 958 | bool found = false; |
a0c4da24 | 959 | |
6b4bf1c4 VS |
960 | target *= 5; /* fast clock */ |
961 | ||
962 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
963 | |
964 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 965 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 967 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 968 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 969 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 970 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 971 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 972 | unsigned int ppm; |
69e4f900 | 973 | |
6b4bf1c4 VS |
974 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
975 | refclk * clock.m1); | |
976 | ||
dccbea3b | 977 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 978 | |
f01b7962 VS |
979 | if (!intel_PLL_is_valid(dev, limit, |
980 | &clock)) | |
43b0ac53 VS |
981 | continue; |
982 | ||
d5dd62bd ID |
983 | if (!vlv_PLL_is_optimal(dev, target, |
984 | &clock, | |
985 | best_clock, | |
986 | bestppm, &ppm)) | |
987 | continue; | |
6b4bf1c4 | 988 | |
d5dd62bd ID |
989 | *best_clock = clock; |
990 | bestppm = ppm; | |
991 | found = true; | |
a0c4da24 JB |
992 | } |
993 | } | |
994 | } | |
995 | } | |
a0c4da24 | 996 | |
49e497ef | 997 | return found; |
a0c4da24 | 998 | } |
a4fc5ed6 | 999 | |
ef9348c8 | 1000 | static bool |
a93e255f ACO |
1001 | chv_find_best_dpll(const intel_limit_t *limit, |
1002 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1003 | int target, int refclk, intel_clock_t *match_clock, |
1004 | intel_clock_t *best_clock) | |
1005 | { | |
a93e255f | 1006 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1007 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1008 | unsigned int best_error_ppm; |
ef9348c8 CML |
1009 | intel_clock_t clock; |
1010 | uint64_t m2; | |
1011 | int found = false; | |
1012 | ||
1013 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1014 | best_error_ppm = 1000000; |
ef9348c8 CML |
1015 | |
1016 | /* | |
1017 | * Based on hardware doc, the n always set to 1, and m1 always | |
1018 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1019 | * revisit this because n may not 1 anymore. | |
1020 | */ | |
1021 | clock.n = 1, clock.m1 = 2; | |
1022 | target *= 5; /* fast clock */ | |
1023 | ||
1024 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1025 | for (clock.p2 = limit->p2.p2_fast; | |
1026 | clock.p2 >= limit->p2.p2_slow; | |
1027 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1028 | unsigned int error_ppm; |
ef9348c8 CML |
1029 | |
1030 | clock.p = clock.p1 * clock.p2; | |
1031 | ||
1032 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1033 | clock.n) << 22, refclk * clock.m1); | |
1034 | ||
1035 | if (m2 > INT_MAX/clock.m1) | |
1036 | continue; | |
1037 | ||
1038 | clock.m2 = m2; | |
1039 | ||
dccbea3b | 1040 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1041 | |
1042 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1043 | continue; | |
1044 | ||
9ca3ba01 ID |
1045 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1046 | best_error_ppm, &error_ppm)) | |
1047 | continue; | |
1048 | ||
1049 | *best_clock = clock; | |
1050 | best_error_ppm = error_ppm; | |
1051 | found = true; | |
ef9348c8 CML |
1052 | } |
1053 | } | |
1054 | ||
1055 | return found; | |
1056 | } | |
1057 | ||
5ab7b0b7 ID |
1058 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1059 | intel_clock_t *best_clock) | |
1060 | { | |
1061 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1062 | ||
1063 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1064 | target_clock, refclk, NULL, best_clock); | |
1065 | } | |
1066 | ||
20ddf665 VS |
1067 | bool intel_crtc_active(struct drm_crtc *crtc) |
1068 | { | |
1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1070 | ||
1071 | /* Be paranoid as we can arrive here with only partial | |
1072 | * state retrieved from the hardware during setup. | |
1073 | * | |
241bfc38 | 1074 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1075 | * as Haswell has gained clock readout/fastboot support. |
1076 | * | |
66e514c1 | 1077 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1078 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1079 | * |
1080 | * FIXME: The intel_crtc->active here should be switched to | |
1081 | * crtc->state->active once we have proper CRTC states wired up | |
1082 | * for atomic. | |
20ddf665 | 1083 | */ |
c3d1f436 | 1084 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1085 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1086 | } |
1087 | ||
a5c961d1 PZ |
1088 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe) | |
1090 | { | |
1091 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1093 | ||
6e3c9717 | 1094 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1095 | } |
1096 | ||
fbf49ea2 VS |
1097 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1098 | { | |
1099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1100 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1101 | u32 line1, line2; |
1102 | u32 line_mask; | |
1103 | ||
1104 | if (IS_GEN2(dev)) | |
1105 | line_mask = DSL_LINEMASK_GEN2; | |
1106 | else | |
1107 | line_mask = DSL_LINEMASK_GEN3; | |
1108 | ||
1109 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1110 | msleep(5); |
fbf49ea2 VS |
1111 | line2 = I915_READ(reg) & line_mask; |
1112 | ||
1113 | return line1 == line2; | |
1114 | } | |
1115 | ||
ab7ad7f6 KP |
1116 | /* |
1117 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1118 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1119 | * |
1120 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1121 | * spinning on the vblank interrupt status bit, since we won't actually | |
1122 | * see an interrupt when the pipe is disabled. | |
1123 | * | |
ab7ad7f6 KP |
1124 | * On Gen4 and above: |
1125 | * wait for the pipe register state bit to turn off | |
1126 | * | |
1127 | * Otherwise: | |
1128 | * wait for the display line value to settle (it usually | |
1129 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1130 | * |
9d0498a2 | 1131 | */ |
575f7ab7 | 1132 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1133 | { |
575f7ab7 | 1134 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1136 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1137 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1138 | |
1139 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1140 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1141 | |
1142 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1143 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1144 | 100)) | |
284637d9 | 1145 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1146 | } else { |
ab7ad7f6 | 1147 | /* Wait for the display line to settle */ |
fbf49ea2 | 1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1149 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1150 | } |
79e53945 JB |
1151 | } |
1152 | ||
b24e7179 | 1153 | /* Only for pre-ILK configs */ |
55607e8a DV |
1154 | void assert_pll(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe, bool state) | |
b24e7179 | 1156 | { |
b24e7179 JB |
1157 | u32 val; |
1158 | bool cur_state; | |
1159 | ||
649636ef | 1160 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1161 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1162 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1163 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1164 | onoff(state), onoff(cur_state)); |
b24e7179 | 1165 | } |
b24e7179 | 1166 | |
23538ef1 JN |
1167 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1168 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1169 | { | |
1170 | u32 val; | |
1171 | bool cur_state; | |
1172 | ||
a580516d | 1173 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1174 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1175 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1176 | |
1177 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1179 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1181 | } |
1182 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1183 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1184 | ||
55607e8a | 1185 | struct intel_shared_dpll * |
e2b78267 DV |
1186 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1187 | { | |
1188 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1189 | ||
6e3c9717 | 1190 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1191 | return NULL; |
1192 | ||
6e3c9717 | 1193 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1194 | } |
1195 | ||
040484af | 1196 | /* For ILK+ */ |
55607e8a DV |
1197 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1198 | struct intel_shared_dpll *pll, | |
1199 | bool state) | |
040484af | 1200 | { |
040484af | 1201 | bool cur_state; |
5358901f | 1202 | struct intel_dpll_hw_state hw_state; |
040484af | 1203 | |
87ad3212 | 1204 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1205 | return; |
ee7b9f93 | 1206 | |
5358901f | 1207 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
5358901f | 1209 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1210 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1211 | } |
040484af JB |
1212 | |
1213 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1214 | enum pipe pipe, bool state) | |
1215 | { | |
040484af | 1216 | bool cur_state; |
ad80a810 PZ |
1217 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1218 | pipe); | |
040484af | 1219 | |
affa9354 PZ |
1220 | if (HAS_DDI(dev_priv->dev)) { |
1221 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1222 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1223 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1224 | } else { |
649636ef | 1225 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1226 | cur_state = !!(val & FDI_TX_ENABLE); |
1227 | } | |
e2c719b7 | 1228 | I915_STATE_WARN(cur_state != state, |
040484af | 1229 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1230 | onoff(state), onoff(cur_state)); |
040484af JB |
1231 | } |
1232 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1233 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1234 | ||
1235 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1236 | enum pipe pipe, bool state) | |
1237 | { | |
040484af JB |
1238 | u32 val; |
1239 | bool cur_state; | |
1240 | ||
649636ef | 1241 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1242 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
040484af | 1244 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | onoff(state), onoff(cur_state)); |
040484af JB |
1246 | } |
1247 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1248 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1249 | ||
1250 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1251 | enum pipe pipe) | |
1252 | { | |
040484af JB |
1253 | u32 val; |
1254 | ||
1255 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1256 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1257 | return; |
1258 | ||
bf507ef7 | 1259 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1260 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1261 | return; |
1262 | ||
649636ef | 1263 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1264 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1265 | } |
1266 | ||
55607e8a DV |
1267 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1268 | enum pipe pipe, bool state) | |
040484af | 1269 | { |
040484af | 1270 | u32 val; |
55607e8a | 1271 | bool cur_state; |
040484af | 1272 | |
649636ef | 1273 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1274 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1275 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1276 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1277 | onoff(state), onoff(cur_state)); |
040484af JB |
1278 | } |
1279 | ||
b680c37a DV |
1280 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
ea0760cf | 1282 | { |
bedd4dba | 1283 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1284 | i915_reg_t pp_reg; |
ea0760cf JB |
1285 | u32 val; |
1286 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1287 | bool locked = true; |
ea0760cf | 1288 | |
bedd4dba JN |
1289 | if (WARN_ON(HAS_DDI(dev))) |
1290 | return; | |
1291 | ||
1292 | if (HAS_PCH_SPLIT(dev)) { | |
1293 | u32 port_sel; | |
1294 | ||
ea0760cf | 1295 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1296 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1297 | ||
1298 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1299 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1300 | panel_pipe = PIPE_B; | |
1301 | /* XXX: else fix for eDP */ | |
666a4537 | 1302 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1303 | /* presumably write lock depends on pipe, not port select */ |
1304 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1305 | panel_pipe = pipe; | |
ea0760cf JB |
1306 | } else { |
1307 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1308 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1309 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1310 | } |
1311 | ||
1312 | val = I915_READ(pp_reg); | |
1313 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1314 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1315 | locked = false; |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1318 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1319 | pipe_name(pipe)); |
ea0760cf JB |
1320 | } |
1321 | ||
93ce0ba6 JN |
1322 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, bool state) | |
1324 | { | |
1325 | struct drm_device *dev = dev_priv->dev; | |
1326 | bool cur_state; | |
1327 | ||
d9d82081 | 1328 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1329 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1330 | else |
5efb3e28 | 1331 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1332 | |
e2c719b7 | 1333 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1334 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1335 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1336 | } |
1337 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1338 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1339 | ||
b840d907 JB |
1340 | void assert_pipe(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe, bool state) | |
b24e7179 | 1342 | { |
63d7bbe9 | 1343 | bool cur_state; |
702e7a56 PZ |
1344 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1345 | pipe); | |
4feed0eb | 1346 | enum intel_display_power_domain power_domain; |
b24e7179 | 1347 | |
b6b5d049 VS |
1348 | /* if we need the pipe quirk it must be always on */ |
1349 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1350 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1351 | state = true; |
1352 | ||
4feed0eb ID |
1353 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1354 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1355 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1356 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1357 | |
1358 | intel_display_power_put(dev_priv, power_domain); | |
1359 | } else { | |
1360 | cur_state = false; | |
69310161 PZ |
1361 | } |
1362 | ||
e2c719b7 | 1363 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1364 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1365 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1366 | } |
1367 | ||
931872fc CW |
1368 | static void assert_plane(struct drm_i915_private *dev_priv, |
1369 | enum plane plane, bool state) | |
b24e7179 | 1370 | { |
b24e7179 | 1371 | u32 val; |
931872fc | 1372 | bool cur_state; |
b24e7179 | 1373 | |
649636ef | 1374 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1375 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1376 | I915_STATE_WARN(cur_state != state, |
931872fc | 1377 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1378 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1379 | } |
1380 | ||
931872fc CW |
1381 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1382 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1383 | ||
b24e7179 JB |
1384 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1385 | enum pipe pipe) | |
1386 | { | |
653e1026 | 1387 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1388 | int i; |
b24e7179 | 1389 | |
653e1026 VS |
1390 | /* Primary planes are fixed to pipes on gen4+ */ |
1391 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1392 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1393 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1394 | "plane %c assertion failure, should be disabled but not\n", |
1395 | plane_name(pipe)); | |
19ec1358 | 1396 | return; |
28c05794 | 1397 | } |
19ec1358 | 1398 | |
b24e7179 | 1399 | /* Need to check both planes against the pipe */ |
055e393f | 1400 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1401 | u32 val = I915_READ(DSPCNTR(i)); |
1402 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1403 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1404 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1405 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1406 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1407 | } |
1408 | } | |
1409 | ||
19332d7a JB |
1410 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1411 | enum pipe pipe) | |
1412 | { | |
20674eef | 1413 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1414 | int sprite; |
19332d7a | 1415 | |
7feb8b88 | 1416 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1417 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1418 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1419 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1420 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1421 | sprite, pipe_name(pipe)); | |
1422 | } | |
666a4537 | 1423 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1424 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1425 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1426 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1427 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1428 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1429 | } |
1430 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1431 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1432 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1433 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1434 | plane_name(pipe), pipe_name(pipe)); |
1435 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1436 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1437 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1438 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1439 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1440 | } |
1441 | } | |
1442 | ||
08c71e5e VS |
1443 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1444 | { | |
e2c719b7 | 1445 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1446 | drm_crtc_vblank_put(crtc); |
1447 | } | |
1448 | ||
89eff4be | 1449 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1450 | { |
1451 | u32 val; | |
1452 | bool enabled; | |
1453 | ||
e2c719b7 | 1454 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1455 | |
92f2584a JB |
1456 | val = I915_READ(PCH_DREF_CONTROL); |
1457 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1458 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1459 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1460 | } |
1461 | ||
ab9412ba DV |
1462 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1463 | enum pipe pipe) | |
92f2584a | 1464 | { |
92f2584a JB |
1465 | u32 val; |
1466 | bool enabled; | |
1467 | ||
649636ef | 1468 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1469 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1470 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1471 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1472 | pipe_name(pipe)); | |
92f2584a JB |
1473 | } |
1474 | ||
4e634389 KP |
1475 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1476 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1477 | { |
1478 | if ((val & DP_PORT_EN) == 0) | |
1479 | return false; | |
1480 | ||
1481 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1482 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1483 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1484 | return false; | |
44f37d1f CML |
1485 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1486 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1487 | return false; | |
f0575e92 KP |
1488 | } else { |
1489 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1490 | return false; | |
1491 | } | |
1492 | return true; | |
1493 | } | |
1494 | ||
1519b995 KP |
1495 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1496 | enum pipe pipe, u32 val) | |
1497 | { | |
dc0fa718 | 1498 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1499 | return false; |
1500 | ||
1501 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1502 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1503 | return false; |
44f37d1f CML |
1504 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1505 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1506 | return false; | |
1519b995 | 1507 | } else { |
dc0fa718 | 1508 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1509 | return false; |
1510 | } | |
1511 | return true; | |
1512 | } | |
1513 | ||
1514 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1515 | enum pipe pipe, u32 val) | |
1516 | { | |
1517 | if ((val & LVDS_PORT_EN) == 0) | |
1518 | return false; | |
1519 | ||
1520 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1521 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1522 | return false; | |
1523 | } else { | |
1524 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1525 | return false; | |
1526 | } | |
1527 | return true; | |
1528 | } | |
1529 | ||
1530 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1531 | enum pipe pipe, u32 val) | |
1532 | { | |
1533 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1534 | return false; | |
1535 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1536 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1537 | return false; | |
1538 | } else { | |
1539 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1540 | return false; | |
1541 | } | |
1542 | return true; | |
1543 | } | |
1544 | ||
291906f1 | 1545 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1546 | enum pipe pipe, i915_reg_t reg, |
1547 | u32 port_sel) | |
291906f1 | 1548 | { |
47a05eca | 1549 | u32 val = I915_READ(reg); |
e2c719b7 | 1550 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1551 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1552 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1553 | |
e2c719b7 | 1554 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1555 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1556 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1557 | } |
1558 | ||
1559 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1560 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1561 | { |
47a05eca | 1562 | u32 val = I915_READ(reg); |
e2c719b7 | 1563 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1564 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1565 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1566 | |
e2c719b7 | 1567 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1568 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1569 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1570 | } |
1571 | ||
1572 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1573 | enum pipe pipe) | |
1574 | { | |
291906f1 | 1575 | u32 val; |
291906f1 | 1576 | |
f0575e92 KP |
1577 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1578 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1579 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1580 | |
649636ef | 1581 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1582 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1583 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1584 | pipe_name(pipe)); |
291906f1 | 1585 | |
649636ef | 1586 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1587 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1588 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1589 | pipe_name(pipe)); |
291906f1 | 1590 | |
e2debe91 PZ |
1591 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1592 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1593 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1594 | } |
1595 | ||
d288f65f | 1596 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1597 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1598 | { |
426115cf DV |
1599 | struct drm_device *dev = crtc->base.dev; |
1600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1601 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1602 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1603 | |
426115cf | 1604 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1605 | |
87442f73 | 1606 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1607 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1608 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1609 | |
426115cf DV |
1610 | I915_WRITE(reg, dpll); |
1611 | POSTING_READ(reg); | |
1612 | udelay(150); | |
1613 | ||
1614 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1615 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1616 | ||
d288f65f | 1617 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1618 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1619 | |
1620 | /* We do this three times for luck */ | |
426115cf | 1621 | I915_WRITE(reg, dpll); |
87442f73 DV |
1622 | POSTING_READ(reg); |
1623 | udelay(150); /* wait for warmup */ | |
426115cf | 1624 | I915_WRITE(reg, dpll); |
87442f73 DV |
1625 | POSTING_READ(reg); |
1626 | udelay(150); /* wait for warmup */ | |
426115cf | 1627 | I915_WRITE(reg, dpll); |
87442f73 DV |
1628 | POSTING_READ(reg); |
1629 | udelay(150); /* wait for warmup */ | |
1630 | } | |
1631 | ||
d288f65f | 1632 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1633 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1634 | { |
1635 | struct drm_device *dev = crtc->base.dev; | |
1636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1637 | int pipe = crtc->pipe; | |
1638 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1639 | u32 tmp; |
1640 | ||
1641 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1642 | ||
a580516d | 1643 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1644 | |
1645 | /* Enable back the 10bit clock to display controller */ | |
1646 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1647 | tmp |= DPIO_DCLKP_EN; | |
1648 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1649 | ||
54433e91 VS |
1650 | mutex_unlock(&dev_priv->sb_lock); |
1651 | ||
9d556c99 CML |
1652 | /* |
1653 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1654 | */ | |
1655 | udelay(1); | |
1656 | ||
1657 | /* Enable PLL */ | |
d288f65f | 1658 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1659 | |
1660 | /* Check PLL is locked */ | |
a11b0703 | 1661 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1662 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1663 | ||
a11b0703 | 1664 | /* not sure when this should be written */ |
d288f65f | 1665 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1666 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1667 | } |
1668 | ||
1c4e0274 VS |
1669 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1670 | { | |
1671 | struct intel_crtc *crtc; | |
1672 | int count = 0; | |
1673 | ||
1674 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1675 | count += crtc->base.state->active && |
409ee761 | 1676 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1677 | |
1678 | return count; | |
1679 | } | |
1680 | ||
66e3d5c0 | 1681 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1682 | { |
66e3d5c0 DV |
1683 | struct drm_device *dev = crtc->base.dev; |
1684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1685 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1686 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1687 | |
66e3d5c0 | 1688 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1689 | |
63d7bbe9 | 1690 | /* No really, not for ILK+ */ |
3d13ef2e | 1691 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1692 | |
1693 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1694 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1695 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1696 | |
1c4e0274 VS |
1697 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1698 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1699 | /* | |
1700 | * It appears to be important that we don't enable this | |
1701 | * for the current pipe before otherwise configuring the | |
1702 | * PLL. No idea how this should be handled if multiple | |
1703 | * DVO outputs are enabled simultaneosly. | |
1704 | */ | |
1705 | dpll |= DPLL_DVO_2X_MODE; | |
1706 | I915_WRITE(DPLL(!crtc->pipe), | |
1707 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1708 | } | |
66e3d5c0 | 1709 | |
c2b63374 VS |
1710 | /* |
1711 | * Apparently we need to have VGA mode enabled prior to changing | |
1712 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1713 | * dividers, even though the register value does change. | |
1714 | */ | |
1715 | I915_WRITE(reg, 0); | |
1716 | ||
8e7a65aa VS |
1717 | I915_WRITE(reg, dpll); |
1718 | ||
66e3d5c0 DV |
1719 | /* Wait for the clocks to stabilize. */ |
1720 | POSTING_READ(reg); | |
1721 | udelay(150); | |
1722 | ||
1723 | if (INTEL_INFO(dev)->gen >= 4) { | |
1724 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1725 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1726 | } else { |
1727 | /* The pixel multiplier can only be updated once the | |
1728 | * DPLL is enabled and the clocks are stable. | |
1729 | * | |
1730 | * So write it again. | |
1731 | */ | |
1732 | I915_WRITE(reg, dpll); | |
1733 | } | |
63d7bbe9 JB |
1734 | |
1735 | /* We do this three times for luck */ | |
66e3d5c0 | 1736 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1737 | POSTING_READ(reg); |
1738 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1739 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1740 | POSTING_READ(reg); |
1741 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1742 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1743 | POSTING_READ(reg); |
1744 | udelay(150); /* wait for warmup */ | |
1745 | } | |
1746 | ||
1747 | /** | |
50b44a44 | 1748 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1749 | * @dev_priv: i915 private structure |
1750 | * @pipe: pipe PLL to disable | |
1751 | * | |
1752 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1753 | * | |
1754 | * Note! This is for pre-ILK only. | |
1755 | */ | |
1c4e0274 | 1756 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1757 | { |
1c4e0274 VS |
1758 | struct drm_device *dev = crtc->base.dev; |
1759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1760 | enum pipe pipe = crtc->pipe; | |
1761 | ||
1762 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1763 | if (IS_I830(dev) && | |
409ee761 | 1764 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1765 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1766 | I915_WRITE(DPLL(PIPE_B), |
1767 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1768 | I915_WRITE(DPLL(PIPE_A), | |
1769 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1770 | } | |
1771 | ||
b6b5d049 VS |
1772 | /* Don't disable pipe or pipe PLLs if needed */ |
1773 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1774 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1775 | return; |
1776 | ||
1777 | /* Make sure the pipe isn't still relying on us */ | |
1778 | assert_pipe_disabled(dev_priv, pipe); | |
1779 | ||
b8afb911 | 1780 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1781 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1782 | } |
1783 | ||
f6071166 JB |
1784 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1785 | { | |
b8afb911 | 1786 | u32 val; |
f6071166 JB |
1787 | |
1788 | /* Make sure the pipe isn't still relying on us */ | |
1789 | assert_pipe_disabled(dev_priv, pipe); | |
1790 | ||
e5cbfbfb ID |
1791 | /* |
1792 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1793 | * The latter is needed for VGA hotplug / manual detection. | |
1794 | */ | |
b8afb911 | 1795 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1796 | if (pipe == PIPE_B) |
60bfe44f | 1797 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1798 | I915_WRITE(DPLL(pipe), val); |
1799 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1800 | |
1801 | } | |
1802 | ||
1803 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1804 | { | |
d752048d | 1805 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1806 | u32 val; |
1807 | ||
a11b0703 VS |
1808 | /* Make sure the pipe isn't still relying on us */ |
1809 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1810 | |
a11b0703 | 1811 | /* Set PLL en = 0 */ |
60bfe44f VS |
1812 | val = DPLL_SSC_REF_CLK_CHV | |
1813 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1814 | if (pipe != PIPE_A) |
1815 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1816 | I915_WRITE(DPLL(pipe), val); | |
1817 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1818 | |
a580516d | 1819 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1820 | |
1821 | /* Disable 10bit clock to display controller */ | |
1822 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1823 | val &= ~DPIO_DCLKP_EN; | |
1824 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1825 | ||
a580516d | 1826 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1827 | } |
1828 | ||
e4607fcf | 1829 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1830 | struct intel_digital_port *dport, |
1831 | unsigned int expected_mask) | |
89b667f8 JB |
1832 | { |
1833 | u32 port_mask; | |
f0f59a00 | 1834 | i915_reg_t dpll_reg; |
89b667f8 | 1835 | |
e4607fcf CML |
1836 | switch (dport->port) { |
1837 | case PORT_B: | |
89b667f8 | 1838 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1839 | dpll_reg = DPLL(0); |
e4607fcf CML |
1840 | break; |
1841 | case PORT_C: | |
89b667f8 | 1842 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1843 | dpll_reg = DPLL(0); |
9b6de0a1 | 1844 | expected_mask <<= 4; |
00fc31b7 CML |
1845 | break; |
1846 | case PORT_D: | |
1847 | port_mask = DPLL_PORTD_READY_MASK; | |
1848 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1849 | break; |
1850 | default: | |
1851 | BUG(); | |
1852 | } | |
89b667f8 | 1853 | |
9b6de0a1 VS |
1854 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1855 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1856 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1857 | } |
1858 | ||
b14b1055 DV |
1859 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1860 | { | |
1861 | struct drm_device *dev = crtc->base.dev; | |
1862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1863 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1864 | ||
be19f0ff CW |
1865 | if (WARN_ON(pll == NULL)) |
1866 | return; | |
1867 | ||
3e369b76 | 1868 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1869 | if (pll->active == 0) { |
1870 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1871 | WARN_ON(pll->on); | |
1872 | assert_shared_dpll_disabled(dev_priv, pll); | |
1873 | ||
1874 | pll->mode_set(dev_priv, pll); | |
1875 | } | |
1876 | } | |
1877 | ||
92f2584a | 1878 | /** |
85b3894f | 1879 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1880 | * @dev_priv: i915 private structure |
1881 | * @pipe: pipe PLL to enable | |
1882 | * | |
1883 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1884 | * drives the transcoder clock. | |
1885 | */ | |
85b3894f | 1886 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1887 | { |
3d13ef2e DL |
1888 | struct drm_device *dev = crtc->base.dev; |
1889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1890 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1891 | |
87a875bb | 1892 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1893 | return; |
1894 | ||
3e369b76 | 1895 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1896 | return; |
ee7b9f93 | 1897 | |
74dd6928 | 1898 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1899 | pll->name, pll->active, pll->on, |
e2b78267 | 1900 | crtc->base.base.id); |
92f2584a | 1901 | |
cdbd2316 DV |
1902 | if (pll->active++) { |
1903 | WARN_ON(!pll->on); | |
e9d6944e | 1904 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1905 | return; |
1906 | } | |
f4a091c7 | 1907 | WARN_ON(pll->on); |
ee7b9f93 | 1908 | |
bd2bb1b9 PZ |
1909 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1910 | ||
46edb027 | 1911 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1912 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1913 | pll->on = true; |
92f2584a JB |
1914 | } |
1915 | ||
f6daaec2 | 1916 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1917 | { |
3d13ef2e DL |
1918 | struct drm_device *dev = crtc->base.dev; |
1919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1920 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1921 | |
92f2584a | 1922 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1923 | if (INTEL_INFO(dev)->gen < 5) |
1924 | return; | |
1925 | ||
eddfcbcd ML |
1926 | if (pll == NULL) |
1927 | return; | |
92f2584a | 1928 | |
eddfcbcd | 1929 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1930 | return; |
7a419866 | 1931 | |
46edb027 DV |
1932 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1933 | pll->name, pll->active, pll->on, | |
e2b78267 | 1934 | crtc->base.base.id); |
7a419866 | 1935 | |
48da64a8 | 1936 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1937 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1938 | return; |
1939 | } | |
1940 | ||
e9d6944e | 1941 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1942 | WARN_ON(!pll->on); |
cdbd2316 | 1943 | if (--pll->active) |
7a419866 | 1944 | return; |
ee7b9f93 | 1945 | |
46edb027 | 1946 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1947 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1948 | pll->on = false; |
bd2bb1b9 PZ |
1949 | |
1950 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1951 | } |
1952 | ||
b8a4f404 PZ |
1953 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1954 | enum pipe pipe) | |
040484af | 1955 | { |
23670b32 | 1956 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1957 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1959 | i915_reg_t reg; |
1960 | uint32_t val, pipeconf_val; | |
040484af JB |
1961 | |
1962 | /* PCH only available on ILK+ */ | |
55522f37 | 1963 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1964 | |
1965 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1966 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1967 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1968 | |
1969 | /* FDI must be feeding us bits for PCH ports */ | |
1970 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1971 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1972 | ||
23670b32 DV |
1973 | if (HAS_PCH_CPT(dev)) { |
1974 | /* Workaround: Set the timing override bit before enabling the | |
1975 | * pch transcoder. */ | |
1976 | reg = TRANS_CHICKEN2(pipe); | |
1977 | val = I915_READ(reg); | |
1978 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1979 | I915_WRITE(reg, val); | |
59c859d6 | 1980 | } |
23670b32 | 1981 | |
ab9412ba | 1982 | reg = PCH_TRANSCONF(pipe); |
040484af | 1983 | val = I915_READ(reg); |
5f7f726d | 1984 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1985 | |
1986 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1987 | /* | |
c5de7c6f VS |
1988 | * Make the BPC in transcoder be consistent with |
1989 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1990 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1991 | */ |
dfd07d72 | 1992 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1993 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1994 | val |= PIPECONF_8BPC; | |
1995 | else | |
1996 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1997 | } |
5f7f726d PZ |
1998 | |
1999 | val &= ~TRANS_INTERLACE_MASK; | |
2000 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2001 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2002 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2003 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2004 | else | |
2005 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2006 | else |
2007 | val |= TRANS_PROGRESSIVE; | |
2008 | ||
040484af JB |
2009 | I915_WRITE(reg, val | TRANS_ENABLE); |
2010 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2011 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2012 | } |
2013 | ||
8fb033d7 | 2014 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2015 | enum transcoder cpu_transcoder) |
040484af | 2016 | { |
8fb033d7 | 2017 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2018 | |
2019 | /* PCH only available on ILK+ */ | |
55522f37 | 2020 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2021 | |
8fb033d7 | 2022 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2023 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2024 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2025 | |
223a6fdf | 2026 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2027 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2028 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2029 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2030 | |
25f3ef11 | 2031 | val = TRANS_ENABLE; |
937bb610 | 2032 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2033 | |
9a76b1c6 PZ |
2034 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2035 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2036 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2037 | else |
2038 | val |= TRANS_PROGRESSIVE; | |
2039 | ||
ab9412ba DV |
2040 | I915_WRITE(LPT_TRANSCONF, val); |
2041 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2042 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2043 | } |
2044 | ||
b8a4f404 PZ |
2045 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2046 | enum pipe pipe) | |
040484af | 2047 | { |
23670b32 | 2048 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2049 | i915_reg_t reg; |
2050 | uint32_t val; | |
040484af JB |
2051 | |
2052 | /* FDI relies on the transcoder */ | |
2053 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2054 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2055 | ||
291906f1 JB |
2056 | /* Ports must be off as well */ |
2057 | assert_pch_ports_disabled(dev_priv, pipe); | |
2058 | ||
ab9412ba | 2059 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2060 | val = I915_READ(reg); |
2061 | val &= ~TRANS_ENABLE; | |
2062 | I915_WRITE(reg, val); | |
2063 | /* wait for PCH transcoder off, transcoder state */ | |
2064 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2065 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2066 | |
c465613b | 2067 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2068 | /* Workaround: Clear the timing override chicken bit again. */ |
2069 | reg = TRANS_CHICKEN2(pipe); | |
2070 | val = I915_READ(reg); | |
2071 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2072 | I915_WRITE(reg, val); | |
2073 | } | |
040484af JB |
2074 | } |
2075 | ||
ab4d966c | 2076 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2077 | { |
8fb033d7 PZ |
2078 | u32 val; |
2079 | ||
ab9412ba | 2080 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2081 | val &= ~TRANS_ENABLE; |
ab9412ba | 2082 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2083 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2084 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2085 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2086 | |
2087 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2088 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2089 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2090 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2091 | } |
2092 | ||
b24e7179 | 2093 | /** |
309cfea8 | 2094 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2095 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2096 | * |
0372264a | 2097 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2098 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2099 | */ |
e1fdc473 | 2100 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2101 | { |
0372264a PZ |
2102 | struct drm_device *dev = crtc->base.dev; |
2103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2104 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2105 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2106 | enum pipe pch_transcoder; |
f0f59a00 | 2107 | i915_reg_t reg; |
b24e7179 JB |
2108 | u32 val; |
2109 | ||
9e2ee2dd VS |
2110 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2111 | ||
58c6eaa2 | 2112 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2113 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2114 | assert_sprites_disabled(dev_priv, pipe); |
2115 | ||
681e5811 | 2116 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2117 | pch_transcoder = TRANSCODER_A; |
2118 | else | |
2119 | pch_transcoder = pipe; | |
2120 | ||
b24e7179 JB |
2121 | /* |
2122 | * A pipe without a PLL won't actually be able to drive bits from | |
2123 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2124 | * need the check. | |
2125 | */ | |
50360403 | 2126 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2127 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2128 | assert_dsi_pll_enabled(dev_priv); |
2129 | else | |
2130 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2131 | else { |
6e3c9717 | 2132 | if (crtc->config->has_pch_encoder) { |
040484af | 2133 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2134 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2135 | assert_fdi_tx_pll_enabled(dev_priv, |
2136 | (enum pipe) cpu_transcoder); | |
040484af JB |
2137 | } |
2138 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2139 | } | |
b24e7179 | 2140 | |
702e7a56 | 2141 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2142 | val = I915_READ(reg); |
7ad25d48 | 2143 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2144 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2145 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2146 | return; |
7ad25d48 | 2147 | } |
00d70b15 CW |
2148 | |
2149 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2150 | POSTING_READ(reg); |
b7792d8b VS |
2151 | |
2152 | /* | |
2153 | * Until the pipe starts DSL will read as 0, which would cause | |
2154 | * an apparent vblank timestamp jump, which messes up also the | |
2155 | * frame count when it's derived from the timestamps. So let's | |
2156 | * wait for the pipe to start properly before we call | |
2157 | * drm_crtc_vblank_on() | |
2158 | */ | |
2159 | if (dev->max_vblank_count == 0 && | |
2160 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2161 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2162 | } |
2163 | ||
2164 | /** | |
309cfea8 | 2165 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2166 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2167 | * |
575f7ab7 VS |
2168 | * Disable the pipe of @crtc, making sure that various hardware |
2169 | * specific requirements are met, if applicable, e.g. plane | |
2170 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2171 | * |
2172 | * Will wait until the pipe has shut down before returning. | |
2173 | */ | |
575f7ab7 | 2174 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2175 | { |
575f7ab7 | 2176 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2177 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2178 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2179 | i915_reg_t reg; |
b24e7179 JB |
2180 | u32 val; |
2181 | ||
9e2ee2dd VS |
2182 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2183 | ||
b24e7179 JB |
2184 | /* |
2185 | * Make sure planes won't keep trying to pump pixels to us, | |
2186 | * or we might hang the display. | |
2187 | */ | |
2188 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2189 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2190 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2191 | |
702e7a56 | 2192 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2193 | val = I915_READ(reg); |
00d70b15 CW |
2194 | if ((val & PIPECONF_ENABLE) == 0) |
2195 | return; | |
2196 | ||
67adc644 VS |
2197 | /* |
2198 | * Double wide has implications for planes | |
2199 | * so best keep it disabled when not needed. | |
2200 | */ | |
6e3c9717 | 2201 | if (crtc->config->double_wide) |
67adc644 VS |
2202 | val &= ~PIPECONF_DOUBLE_WIDE; |
2203 | ||
2204 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2205 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2206 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2207 | val &= ~PIPECONF_ENABLE; |
2208 | ||
2209 | I915_WRITE(reg, val); | |
2210 | if ((val & PIPECONF_ENABLE) == 0) | |
2211 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2212 | } |
2213 | ||
693db184 CW |
2214 | static bool need_vtd_wa(struct drm_device *dev) |
2215 | { | |
2216 | #ifdef CONFIG_INTEL_IOMMU | |
2217 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2218 | return true; | |
2219 | #endif | |
2220 | return false; | |
2221 | } | |
2222 | ||
832be82f VS |
2223 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2224 | { | |
2225 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2226 | } | |
2227 | ||
7b49f948 VS |
2228 | static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv, |
2229 | uint64_t fb_modifier, unsigned int cpp) | |
2230 | { | |
2231 | switch (fb_modifier) { | |
2232 | case DRM_FORMAT_MOD_NONE: | |
2233 | return cpp; | |
2234 | case I915_FORMAT_MOD_X_TILED: | |
2235 | if (IS_GEN2(dev_priv)) | |
2236 | return 128; | |
2237 | else | |
2238 | return 512; | |
2239 | case I915_FORMAT_MOD_Y_TILED: | |
2240 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2241 | return 128; | |
2242 | else | |
2243 | return 512; | |
2244 | case I915_FORMAT_MOD_Yf_TILED: | |
2245 | switch (cpp) { | |
2246 | case 1: | |
2247 | return 64; | |
2248 | case 2: | |
2249 | case 4: | |
2250 | return 128; | |
2251 | case 8: | |
2252 | case 16: | |
2253 | return 256; | |
2254 | default: | |
2255 | MISSING_CASE(cpp); | |
2256 | return cpp; | |
2257 | } | |
2258 | break; | |
2259 | default: | |
2260 | MISSING_CASE(fb_modifier); | |
2261 | return cpp; | |
2262 | } | |
2263 | } | |
2264 | ||
832be82f VS |
2265 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2266 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2267 | { |
832be82f VS |
2268 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2269 | return 1; | |
2270 | else | |
2271 | return intel_tile_size(dev_priv) / | |
2272 | intel_tile_width(dev_priv, fb_modifier, cpp); | |
6761dd31 TU |
2273 | } |
2274 | ||
2275 | unsigned int | |
2276 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2277 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2278 | { |
832be82f VS |
2279 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2280 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2281 | ||
2282 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2283 | } |
2284 | ||
75c82a53 | 2285 | static void |
f64b98cd TU |
2286 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2287 | const struct drm_plane_state *plane_state) | |
2288 | { | |
832be82f | 2289 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
7723f47d | 2290 | struct intel_rotation_info *info = &view->params.rotated; |
d9b3288e | 2291 | unsigned int tile_size, tile_width, tile_height, cpp; |
50470bb0 | 2292 | |
f64b98cd TU |
2293 | *view = i915_ggtt_view_normal; |
2294 | ||
50470bb0 | 2295 | if (!plane_state) |
75c82a53 | 2296 | return; |
50470bb0 | 2297 | |
121920fa | 2298 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2299 | return; |
50470bb0 | 2300 | |
9abc4648 | 2301 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2302 | |
2303 | info->height = fb->height; | |
2304 | info->pixel_format = fb->pixel_format; | |
2305 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2306 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2307 | info->fb_modifier = fb->modifier[0]; |
2308 | ||
d9b3288e VS |
2309 | tile_size = intel_tile_size(dev_priv); |
2310 | ||
2311 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
b16bb01f | 2312 | tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp); |
d9b3288e VS |
2313 | tile_height = tile_size / tile_width; |
2314 | ||
2315 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width); | |
84fe03f7 | 2316 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
d9b3288e | 2317 | info->size = info->width_pages * info->height_pages * tile_size; |
84fe03f7 | 2318 | |
89e3e142 | 2319 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2320 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
d9b3288e VS |
2321 | tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp); |
2322 | tile_height = tile_size / tile_width; | |
2323 | ||
2324 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width); | |
832be82f | 2325 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height); |
d9b3288e | 2326 | info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size; |
89e3e142 | 2327 | } |
f64b98cd TU |
2328 | } |
2329 | ||
603525d7 | 2330 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2331 | { |
2332 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2333 | return 256 * 1024; | |
985b8bb4 | 2334 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2335 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2336 | return 128 * 1024; |
2337 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2338 | return 4 * 1024; | |
2339 | else | |
44c5905e | 2340 | return 0; |
4e9a86b6 VS |
2341 | } |
2342 | ||
603525d7 VS |
2343 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2344 | uint64_t fb_modifier) | |
2345 | { | |
2346 | switch (fb_modifier) { | |
2347 | case DRM_FORMAT_MOD_NONE: | |
2348 | return intel_linear_alignment(dev_priv); | |
2349 | case I915_FORMAT_MOD_X_TILED: | |
2350 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2351 | return 256 * 1024; | |
2352 | return 0; | |
2353 | case I915_FORMAT_MOD_Y_TILED: | |
2354 | case I915_FORMAT_MOD_Yf_TILED: | |
2355 | return 1 * 1024 * 1024; | |
2356 | default: | |
2357 | MISSING_CASE(fb_modifier); | |
2358 | return 0; | |
2359 | } | |
2360 | } | |
2361 | ||
127bd2ac | 2362 | int |
850c4cdc TU |
2363 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2364 | struct drm_framebuffer *fb, | |
7580d774 | 2365 | const struct drm_plane_state *plane_state) |
6b95a207 | 2366 | { |
850c4cdc | 2367 | struct drm_device *dev = fb->dev; |
ce453d81 | 2368 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2369 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2370 | struct i915_ggtt_view view; |
6b95a207 KH |
2371 | u32 alignment; |
2372 | int ret; | |
2373 | ||
ebcdd39e MR |
2374 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2375 | ||
603525d7 | 2376 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2377 | |
75c82a53 | 2378 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2379 | |
693db184 CW |
2380 | /* Note that the w/a also requires 64 PTE of padding following the |
2381 | * bo. We currently fill all unused PTE with the shadow page and so | |
2382 | * we should always have valid PTE following the scanout preventing | |
2383 | * the VT-d warning. | |
2384 | */ | |
2385 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2386 | alignment = 256 * 1024; | |
2387 | ||
d6dd6843 PZ |
2388 | /* |
2389 | * Global gtt pte registers are special registers which actually forward | |
2390 | * writes to a chunk of system memory. Which means that there is no risk | |
2391 | * that the register values disappear as soon as we call | |
2392 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2393 | * pin/unpin/fence and not more. | |
2394 | */ | |
2395 | intel_runtime_pm_get(dev_priv); | |
2396 | ||
7580d774 ML |
2397 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2398 | &view); | |
48b956c5 | 2399 | if (ret) |
b26a6b35 | 2400 | goto err_pm; |
6b95a207 KH |
2401 | |
2402 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2403 | * fence, whereas 965+ only requires a fence if using | |
2404 | * framebuffer compression. For simplicity, we always install | |
2405 | * a fence as the cost is not that onerous. | |
2406 | */ | |
9807216f VK |
2407 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2408 | ret = i915_gem_object_get_fence(obj); | |
2409 | if (ret == -EDEADLK) { | |
2410 | /* | |
2411 | * -EDEADLK means there are no free fences | |
2412 | * no pending flips. | |
2413 | * | |
2414 | * This is propagated to atomic, but it uses | |
2415 | * -EDEADLK to force a locking recovery, so | |
2416 | * change the returned error to -EBUSY. | |
2417 | */ | |
2418 | ret = -EBUSY; | |
2419 | goto err_unpin; | |
2420 | } else if (ret) | |
2421 | goto err_unpin; | |
1690e1eb | 2422 | |
9807216f VK |
2423 | i915_gem_object_pin_fence(obj); |
2424 | } | |
6b95a207 | 2425 | |
d6dd6843 | 2426 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2427 | return 0; |
48b956c5 CW |
2428 | |
2429 | err_unpin: | |
f64b98cd | 2430 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2431 | err_pm: |
d6dd6843 | 2432 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2433 | return ret; |
6b95a207 KH |
2434 | } |
2435 | ||
82bc3b2d TU |
2436 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2437 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2438 | { |
82bc3b2d | 2439 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2440 | struct i915_ggtt_view view; |
82bc3b2d | 2441 | |
ebcdd39e MR |
2442 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2443 | ||
75c82a53 | 2444 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2445 | |
9807216f VK |
2446 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2447 | i915_gem_object_unpin_fence(obj); | |
2448 | ||
f64b98cd | 2449 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2450 | } |
2451 | ||
c2c75131 DV |
2452 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2453 | * is assumed to be a power-of-two. */ | |
54ea9da8 VS |
2454 | u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
2455 | int *x, int *y, | |
2456 | uint64_t fb_modifier, | |
2457 | unsigned int cpp, | |
2458 | unsigned int pitch) | |
c2c75131 | 2459 | { |
b5c65338 | 2460 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
d843310d | 2461 | unsigned int tile_size, tile_width, tile_height; |
bc752862 | 2462 | unsigned int tile_rows, tiles; |
c2c75131 | 2463 | |
d843310d VS |
2464 | tile_size = intel_tile_size(dev_priv); |
2465 | tile_width = intel_tile_width(dev_priv, fb_modifier, cpp); | |
2466 | tile_height = tile_size / tile_width; | |
2467 | ||
2468 | tile_rows = *y / tile_height; | |
2469 | *y %= tile_height; | |
c2c75131 | 2470 | |
d843310d VS |
2471 | tiles = *x / (tile_width/cpp); |
2472 | *x %= tile_width/cpp; | |
bc752862 | 2473 | |
d843310d | 2474 | return tile_rows * pitch * tile_height + tiles * tile_size; |
bc752862 | 2475 | } else { |
4e9a86b6 | 2476 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2477 | unsigned int offset; |
2478 | ||
2479 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2480 | *y = (offset & alignment) / pitch; |
2481 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2482 | return offset & ~alignment; | |
bc752862 | 2483 | } |
c2c75131 DV |
2484 | } |
2485 | ||
b35d63fa | 2486 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2487 | { |
2488 | switch (format) { | |
2489 | case DISPPLANE_8BPP: | |
2490 | return DRM_FORMAT_C8; | |
2491 | case DISPPLANE_BGRX555: | |
2492 | return DRM_FORMAT_XRGB1555; | |
2493 | case DISPPLANE_BGRX565: | |
2494 | return DRM_FORMAT_RGB565; | |
2495 | default: | |
2496 | case DISPPLANE_BGRX888: | |
2497 | return DRM_FORMAT_XRGB8888; | |
2498 | case DISPPLANE_RGBX888: | |
2499 | return DRM_FORMAT_XBGR8888; | |
2500 | case DISPPLANE_BGRX101010: | |
2501 | return DRM_FORMAT_XRGB2101010; | |
2502 | case DISPPLANE_RGBX101010: | |
2503 | return DRM_FORMAT_XBGR2101010; | |
2504 | } | |
2505 | } | |
2506 | ||
bc8d7dff DL |
2507 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2508 | { | |
2509 | switch (format) { | |
2510 | case PLANE_CTL_FORMAT_RGB_565: | |
2511 | return DRM_FORMAT_RGB565; | |
2512 | default: | |
2513 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2514 | if (rgb_order) { | |
2515 | if (alpha) | |
2516 | return DRM_FORMAT_ABGR8888; | |
2517 | else | |
2518 | return DRM_FORMAT_XBGR8888; | |
2519 | } else { | |
2520 | if (alpha) | |
2521 | return DRM_FORMAT_ARGB8888; | |
2522 | else | |
2523 | return DRM_FORMAT_XRGB8888; | |
2524 | } | |
2525 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2526 | if (rgb_order) | |
2527 | return DRM_FORMAT_XBGR2101010; | |
2528 | else | |
2529 | return DRM_FORMAT_XRGB2101010; | |
2530 | } | |
2531 | } | |
2532 | ||
5724dbd1 | 2533 | static bool |
f6936e29 DV |
2534 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2535 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2536 | { |
2537 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2538 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2539 | struct drm_i915_gem_object *obj = NULL; |
2540 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2541 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2542 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2543 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2544 | PAGE_SIZE); | |
2545 | ||
2546 | size_aligned -= base_aligned; | |
46f297fb | 2547 | |
ff2652ea CW |
2548 | if (plane_config->size == 0) |
2549 | return false; | |
2550 | ||
3badb49f PZ |
2551 | /* If the FB is too big, just don't use it since fbdev is not very |
2552 | * important and we should probably use that space with FBC or other | |
2553 | * features. */ | |
2554 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2555 | return false; | |
2556 | ||
12c83d99 TU |
2557 | mutex_lock(&dev->struct_mutex); |
2558 | ||
f37b5c2b DV |
2559 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2560 | base_aligned, | |
2561 | base_aligned, | |
2562 | size_aligned); | |
12c83d99 TU |
2563 | if (!obj) { |
2564 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2565 | return false; |
12c83d99 | 2566 | } |
46f297fb | 2567 | |
49af449b DL |
2568 | obj->tiling_mode = plane_config->tiling; |
2569 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2570 | obj->stride = fb->pitches[0]; |
46f297fb | 2571 | |
6bf129df DL |
2572 | mode_cmd.pixel_format = fb->pixel_format; |
2573 | mode_cmd.width = fb->width; | |
2574 | mode_cmd.height = fb->height; | |
2575 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2576 | mode_cmd.modifier[0] = fb->modifier[0]; |
2577 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2578 | |
6bf129df | 2579 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2580 | &mode_cmd, obj)) { |
46f297fb JB |
2581 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2582 | goto out_unref_obj; | |
2583 | } | |
12c83d99 | 2584 | |
46f297fb | 2585 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2586 | |
f6936e29 | 2587 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2588 | return true; |
46f297fb JB |
2589 | |
2590 | out_unref_obj: | |
2591 | drm_gem_object_unreference(&obj->base); | |
2592 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2593 | return false; |
2594 | } | |
2595 | ||
afd65eb4 MR |
2596 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2597 | static void | |
2598 | update_state_fb(struct drm_plane *plane) | |
2599 | { | |
2600 | if (plane->fb == plane->state->fb) | |
2601 | return; | |
2602 | ||
2603 | if (plane->state->fb) | |
2604 | drm_framebuffer_unreference(plane->state->fb); | |
2605 | plane->state->fb = plane->fb; | |
2606 | if (plane->state->fb) | |
2607 | drm_framebuffer_reference(plane->state->fb); | |
2608 | } | |
2609 | ||
5724dbd1 | 2610 | static void |
f6936e29 DV |
2611 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2612 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2613 | { |
2614 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2615 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2616 | struct drm_crtc *c; |
2617 | struct intel_crtc *i; | |
2ff8fde1 | 2618 | struct drm_i915_gem_object *obj; |
88595ac9 | 2619 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2620 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2621 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2622 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2623 | struct intel_plane_state *intel_state = |
2624 | to_intel_plane_state(plane_state); | |
88595ac9 | 2625 | struct drm_framebuffer *fb; |
484b41dd | 2626 | |
2d14030b | 2627 | if (!plane_config->fb) |
484b41dd JB |
2628 | return; |
2629 | ||
f6936e29 | 2630 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2631 | fb = &plane_config->fb->base; |
2632 | goto valid_fb; | |
f55548b5 | 2633 | } |
484b41dd | 2634 | |
2d14030b | 2635 | kfree(plane_config->fb); |
484b41dd JB |
2636 | |
2637 | /* | |
2638 | * Failed to alloc the obj, check to see if we should share | |
2639 | * an fb with another CRTC instead | |
2640 | */ | |
70e1e0ec | 2641 | for_each_crtc(dev, c) { |
484b41dd JB |
2642 | i = to_intel_crtc(c); |
2643 | ||
2644 | if (c == &intel_crtc->base) | |
2645 | continue; | |
2646 | ||
2ff8fde1 MR |
2647 | if (!i->active) |
2648 | continue; | |
2649 | ||
88595ac9 DV |
2650 | fb = c->primary->fb; |
2651 | if (!fb) | |
484b41dd JB |
2652 | continue; |
2653 | ||
88595ac9 | 2654 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2655 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2656 | drm_framebuffer_reference(fb); |
2657 | goto valid_fb; | |
484b41dd JB |
2658 | } |
2659 | } | |
88595ac9 | 2660 | |
200757f5 MR |
2661 | /* |
2662 | * We've failed to reconstruct the BIOS FB. Current display state | |
2663 | * indicates that the primary plane is visible, but has a NULL FB, | |
2664 | * which will lead to problems later if we don't fix it up. The | |
2665 | * simplest solution is to just disable the primary plane now and | |
2666 | * pretend the BIOS never had it enabled. | |
2667 | */ | |
2668 | to_intel_plane_state(plane_state)->visible = false; | |
2669 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2670 | intel_pre_disable_primary(&intel_crtc->base); | |
2671 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2672 | ||
88595ac9 DV |
2673 | return; |
2674 | ||
2675 | valid_fb: | |
f44e2659 VS |
2676 | plane_state->src_x = 0; |
2677 | plane_state->src_y = 0; | |
be5651f2 ML |
2678 | plane_state->src_w = fb->width << 16; |
2679 | plane_state->src_h = fb->height << 16; | |
2680 | ||
f44e2659 VS |
2681 | plane_state->crtc_x = 0; |
2682 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2683 | plane_state->crtc_w = fb->width; |
2684 | plane_state->crtc_h = fb->height; | |
2685 | ||
0a8d8a86 MR |
2686 | intel_state->src.x1 = plane_state->src_x; |
2687 | intel_state->src.y1 = plane_state->src_y; | |
2688 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2689 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2690 | intel_state->dst.x1 = plane_state->crtc_x; | |
2691 | intel_state->dst.y1 = plane_state->crtc_y; | |
2692 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2693 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2694 | ||
88595ac9 DV |
2695 | obj = intel_fb_obj(fb); |
2696 | if (obj->tiling_mode != I915_TILING_NONE) | |
2697 | dev_priv->preserve_bios_swizzle = true; | |
2698 | ||
be5651f2 ML |
2699 | drm_framebuffer_reference(fb); |
2700 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2701 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2702 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2703 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2704 | } |
2705 | ||
a8d201af ML |
2706 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2707 | const struct intel_crtc_state *crtc_state, | |
2708 | const struct intel_plane_state *plane_state) | |
81255565 | 2709 | { |
a8d201af | 2710 | struct drm_device *dev = primary->dev; |
81255565 | 2711 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2713 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2714 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2715 | int plane = intel_crtc->plane; |
54ea9da8 | 2716 | u32 linear_offset; |
81255565 | 2717 | u32 dspcntr; |
f0f59a00 | 2718 | i915_reg_t reg = DSPCNTR(plane); |
ac484963 | 2719 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2720 | int x = plane_state->src.x1 >> 16; |
2721 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2722 | |
f45651ba VS |
2723 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2724 | ||
fdd508a6 | 2725 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2726 | |
2727 | if (INTEL_INFO(dev)->gen < 4) { | |
2728 | if (intel_crtc->pipe == PIPE_B) | |
2729 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2730 | ||
2731 | /* pipesrc and dspsize control the size that is scaled from, | |
2732 | * which should always be the user's requested size. | |
2733 | */ | |
2734 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2735 | ((crtc_state->pipe_src_h - 1) << 16) | |
2736 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2737 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2738 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2739 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2740 | ((crtc_state->pipe_src_h - 1) << 16) | |
2741 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2742 | I915_WRITE(PRIMPOS(plane), 0); |
2743 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2744 | } |
81255565 | 2745 | |
57779d06 VS |
2746 | switch (fb->pixel_format) { |
2747 | case DRM_FORMAT_C8: | |
81255565 JB |
2748 | dspcntr |= DISPPLANE_8BPP; |
2749 | break; | |
57779d06 | 2750 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2751 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2752 | break; |
57779d06 VS |
2753 | case DRM_FORMAT_RGB565: |
2754 | dspcntr |= DISPPLANE_BGRX565; | |
2755 | break; | |
2756 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2757 | dspcntr |= DISPPLANE_BGRX888; |
2758 | break; | |
2759 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2760 | dspcntr |= DISPPLANE_RGBX888; |
2761 | break; | |
2762 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2763 | dspcntr |= DISPPLANE_BGRX101010; |
2764 | break; | |
2765 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2766 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2767 | break; |
2768 | default: | |
baba133a | 2769 | BUG(); |
81255565 | 2770 | } |
57779d06 | 2771 | |
f45651ba VS |
2772 | if (INTEL_INFO(dev)->gen >= 4 && |
2773 | obj->tiling_mode != I915_TILING_NONE) | |
2774 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2775 | |
de1aa629 VS |
2776 | if (IS_G4X(dev)) |
2777 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2778 | ||
ac484963 | 2779 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2780 | |
c2c75131 DV |
2781 | if (INTEL_INFO(dev)->gen >= 4) { |
2782 | intel_crtc->dspaddr_offset = | |
ce1e5c14 | 2783 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2784 | fb->modifier[0], cpp, |
ce1e5c14 | 2785 | fb->pitches[0]); |
c2c75131 DV |
2786 | linear_offset -= intel_crtc->dspaddr_offset; |
2787 | } else { | |
e506a0c6 | 2788 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2789 | } |
e506a0c6 | 2790 | |
a8d201af | 2791 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2792 | dspcntr |= DISPPLANE_ROTATE_180; |
2793 | ||
a8d201af ML |
2794 | x += (crtc_state->pipe_src_w - 1); |
2795 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2796 | |
2797 | /* Finding the last pixel of the last line of the display | |
2798 | data and adding to linear_offset*/ | |
2799 | linear_offset += | |
a8d201af | 2800 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2801 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2802 | } |
2803 | ||
2db3366b PZ |
2804 | intel_crtc->adjusted_x = x; |
2805 | intel_crtc->adjusted_y = y; | |
2806 | ||
48404c1e SJ |
2807 | I915_WRITE(reg, dspcntr); |
2808 | ||
01f2c773 | 2809 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2810 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2811 | I915_WRITE(DSPSURF(plane), |
2812 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2813 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2814 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2815 | } else |
f343c5f6 | 2816 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2817 | POSTING_READ(reg); |
17638cd6 JB |
2818 | } |
2819 | ||
a8d201af ML |
2820 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2821 | struct drm_crtc *crtc) | |
17638cd6 JB |
2822 | { |
2823 | struct drm_device *dev = crtc->dev; | |
2824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2826 | int plane = intel_crtc->plane; |
f45651ba | 2827 | |
a8d201af ML |
2828 | I915_WRITE(DSPCNTR(plane), 0); |
2829 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2830 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2831 | else |
2832 | I915_WRITE(DSPADDR(plane), 0); | |
2833 | POSTING_READ(DSPCNTR(plane)); | |
2834 | } | |
c9ba6fad | 2835 | |
a8d201af ML |
2836 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2837 | const struct intel_crtc_state *crtc_state, | |
2838 | const struct intel_plane_state *plane_state) | |
2839 | { | |
2840 | struct drm_device *dev = primary->dev; | |
2841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2843 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2844 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2845 | int plane = intel_crtc->plane; | |
54ea9da8 | 2846 | u32 linear_offset; |
a8d201af ML |
2847 | u32 dspcntr; |
2848 | i915_reg_t reg = DSPCNTR(plane); | |
ac484963 | 2849 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2850 | int x = plane_state->src.x1 >> 16; |
2851 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2852 | |
f45651ba | 2853 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2854 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2855 | |
2856 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2857 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2858 | |
57779d06 VS |
2859 | switch (fb->pixel_format) { |
2860 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2861 | dspcntr |= DISPPLANE_8BPP; |
2862 | break; | |
57779d06 VS |
2863 | case DRM_FORMAT_RGB565: |
2864 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2865 | break; |
57779d06 | 2866 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2867 | dspcntr |= DISPPLANE_BGRX888; |
2868 | break; | |
2869 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2870 | dspcntr |= DISPPLANE_RGBX888; |
2871 | break; | |
2872 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2873 | dspcntr |= DISPPLANE_BGRX101010; |
2874 | break; | |
2875 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2876 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2877 | break; |
2878 | default: | |
baba133a | 2879 | BUG(); |
17638cd6 JB |
2880 | } |
2881 | ||
2882 | if (obj->tiling_mode != I915_TILING_NONE) | |
2883 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2884 | |
f45651ba | 2885 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2886 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2887 | |
ac484963 | 2888 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2889 | intel_crtc->dspaddr_offset = |
ce1e5c14 | 2890 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2891 | fb->modifier[0], cpp, |
ce1e5c14 | 2892 | fb->pitches[0]); |
c2c75131 | 2893 | linear_offset -= intel_crtc->dspaddr_offset; |
a8d201af | 2894 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2895 | dspcntr |= DISPPLANE_ROTATE_180; |
2896 | ||
2897 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2898 | x += (crtc_state->pipe_src_w - 1); |
2899 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2900 | |
2901 | /* Finding the last pixel of the last line of the display | |
2902 | data and adding to linear_offset*/ | |
2903 | linear_offset += | |
a8d201af | 2904 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2905 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2906 | } |
2907 | } | |
2908 | ||
2db3366b PZ |
2909 | intel_crtc->adjusted_x = x; |
2910 | intel_crtc->adjusted_y = y; | |
2911 | ||
48404c1e | 2912 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2913 | |
01f2c773 | 2914 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2915 | I915_WRITE(DSPSURF(plane), |
2916 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2917 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2918 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2919 | } else { | |
2920 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2921 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2922 | } | |
17638cd6 | 2923 | POSTING_READ(reg); |
17638cd6 JB |
2924 | } |
2925 | ||
7b49f948 VS |
2926 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2927 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2928 | { |
7b49f948 | 2929 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2930 | return 64; |
7b49f948 VS |
2931 | } else { |
2932 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2933 | ||
2934 | return intel_tile_width(dev_priv, fb_modifier, cpp); | |
b321803d DL |
2935 | } |
2936 | } | |
2937 | ||
44eb0cb9 MK |
2938 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2939 | struct drm_i915_gem_object *obj, | |
2940 | unsigned int plane) | |
121920fa | 2941 | { |
ce7f1728 | 2942 | struct i915_ggtt_view view; |
dedf278c | 2943 | struct i915_vma *vma; |
44eb0cb9 | 2944 | u64 offset; |
121920fa | 2945 | |
e7941294 | 2946 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
ce7f1728 | 2947 | intel_plane->base.state); |
121920fa | 2948 | |
ce7f1728 | 2949 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2950 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2951 | view.type)) |
dedf278c TU |
2952 | return -1; |
2953 | ||
44eb0cb9 | 2954 | offset = vma->node.start; |
dedf278c TU |
2955 | |
2956 | if (plane == 1) { | |
7723f47d | 2957 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2958 | PAGE_SIZE; |
2959 | } | |
2960 | ||
44eb0cb9 MK |
2961 | WARN_ON(upper_32_bits(offset)); |
2962 | ||
2963 | return lower_32_bits(offset); | |
121920fa TU |
2964 | } |
2965 | ||
e435d6e5 ML |
2966 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2967 | { | |
2968 | struct drm_device *dev = intel_crtc->base.dev; | |
2969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2970 | ||
2971 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2972 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2973 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2974 | } |
2975 | ||
a1b2278e CK |
2976 | /* |
2977 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2978 | */ | |
0583236e | 2979 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2980 | { |
a1b2278e CK |
2981 | struct intel_crtc_scaler_state *scaler_state; |
2982 | int i; | |
2983 | ||
a1b2278e CK |
2984 | scaler_state = &intel_crtc->config->scaler_state; |
2985 | ||
2986 | /* loop through and disable scalers that aren't in use */ | |
2987 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2988 | if (!scaler_state->scalers[i].in_use) |
2989 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2990 | } |
2991 | } | |
2992 | ||
6156a456 | 2993 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2994 | { |
6156a456 | 2995 | switch (pixel_format) { |
d161cf7a | 2996 | case DRM_FORMAT_C8: |
c34ce3d1 | 2997 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2998 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2999 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3000 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3001 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3002 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3003 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3004 | /* |
3005 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3006 | * to be already pre-multiplied. We need to add a knob (or a different | |
3007 | * DRM_FORMAT) for user-space to configure that. | |
3008 | */ | |
f75fb42a | 3009 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3010 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3011 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3012 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3014 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3015 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3016 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3017 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3018 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3019 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3020 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3021 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3022 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3023 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3024 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3025 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3026 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3027 | default: |
4249eeef | 3028 | MISSING_CASE(pixel_format); |
70d21f0e | 3029 | } |
8cfcba41 | 3030 | |
c34ce3d1 | 3031 | return 0; |
6156a456 | 3032 | } |
70d21f0e | 3033 | |
6156a456 CK |
3034 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3035 | { | |
6156a456 | 3036 | switch (fb_modifier) { |
30af77c4 | 3037 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3038 | break; |
30af77c4 | 3039 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3040 | return PLANE_CTL_TILED_X; |
b321803d | 3041 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3042 | return PLANE_CTL_TILED_Y; |
b321803d | 3043 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3044 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3045 | default: |
6156a456 | 3046 | MISSING_CASE(fb_modifier); |
70d21f0e | 3047 | } |
8cfcba41 | 3048 | |
c34ce3d1 | 3049 | return 0; |
6156a456 | 3050 | } |
70d21f0e | 3051 | |
6156a456 CK |
3052 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3053 | { | |
3b7a5119 | 3054 | switch (rotation) { |
6156a456 CK |
3055 | case BIT(DRM_ROTATE_0): |
3056 | break; | |
1e8df167 SJ |
3057 | /* |
3058 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3059 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3060 | */ | |
3b7a5119 | 3061 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3062 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3063 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3064 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3065 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3066 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3067 | default: |
3068 | MISSING_CASE(rotation); | |
3069 | } | |
3070 | ||
c34ce3d1 | 3071 | return 0; |
6156a456 CK |
3072 | } |
3073 | ||
a8d201af ML |
3074 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3075 | const struct intel_crtc_state *crtc_state, | |
3076 | const struct intel_plane_state *plane_state) | |
6156a456 | 3077 | { |
a8d201af | 3078 | struct drm_device *dev = plane->dev; |
6156a456 | 3079 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3081 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3082 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3083 | int pipe = intel_crtc->pipe; |
3084 | u32 plane_ctl, stride_div, stride; | |
3085 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3086 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3087 | int x_offset, y_offset; |
44eb0cb9 | 3088 | u32 surf_addr; |
a8d201af ML |
3089 | int scaler_id = plane_state->scaler_id; |
3090 | int src_x = plane_state->src.x1 >> 16; | |
3091 | int src_y = plane_state->src.y1 >> 16; | |
3092 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3093 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3094 | int dst_x = plane_state->dst.x1; | |
3095 | int dst_y = plane_state->dst.y1; | |
3096 | int dst_w = drm_rect_width(&plane_state->dst); | |
3097 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3098 | |
6156a456 CK |
3099 | plane_ctl = PLANE_CTL_ENABLE | |
3100 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3101 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3102 | ||
3103 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3104 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3105 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3106 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3107 | ||
7b49f948 | 3108 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3109 | fb->pixel_format); |
dedf278c | 3110 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3111 | |
a42e5a23 PZ |
3112 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3113 | ||
3b7a5119 | 3114 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3115 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3116 | ||
3b7a5119 | 3117 | /* stride = Surface height in tiles */ |
832be82f | 3118 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3119 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3120 | x_offset = stride * tile_height - src_y - src_h; |
3121 | y_offset = src_x; | |
6156a456 | 3122 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3123 | } else { |
3124 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3125 | x_offset = src_x; |
3126 | y_offset = src_y; | |
6156a456 | 3127 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3128 | } |
3129 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3130 | |
2db3366b PZ |
3131 | intel_crtc->adjusted_x = x_offset; |
3132 | intel_crtc->adjusted_y = y_offset; | |
3133 | ||
70d21f0e | 3134 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3135 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3136 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3137 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3138 | |
3139 | if (scaler_id >= 0) { | |
3140 | uint32_t ps_ctrl = 0; | |
3141 | ||
3142 | WARN_ON(!dst_w || !dst_h); | |
3143 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3144 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3145 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3146 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3147 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3148 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3149 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3150 | } else { | |
3151 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3152 | } | |
3153 | ||
121920fa | 3154 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3155 | |
3156 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3157 | } | |
3158 | ||
a8d201af ML |
3159 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3160 | struct drm_crtc *crtc) | |
17638cd6 JB |
3161 | { |
3162 | struct drm_device *dev = crtc->dev; | |
3163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3164 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3165 | |
a8d201af ML |
3166 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3167 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3168 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3169 | } | |
29b9bde6 | 3170 | |
a8d201af ML |
3171 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3172 | static int | |
3173 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3174 | int x, int y, enum mode_set_atomic state) | |
3175 | { | |
3176 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3177 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3178 | ||
3179 | return -ENODEV; | |
81255565 JB |
3180 | } |
3181 | ||
7514747d | 3182 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3183 | { |
96a02917 VS |
3184 | struct drm_crtc *crtc; |
3185 | ||
70e1e0ec | 3186 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3188 | enum plane plane = intel_crtc->plane; | |
3189 | ||
3190 | intel_prepare_page_flip(dev, plane); | |
3191 | intel_finish_page_flip_plane(dev, plane); | |
3192 | } | |
7514747d VS |
3193 | } |
3194 | ||
3195 | static void intel_update_primary_planes(struct drm_device *dev) | |
3196 | { | |
7514747d | 3197 | struct drm_crtc *crtc; |
96a02917 | 3198 | |
70e1e0ec | 3199 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3200 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3201 | struct intel_plane_state *plane_state; | |
96a02917 | 3202 | |
11c22da6 | 3203 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3204 | plane_state = to_intel_plane_state(plane->base.state); |
3205 | ||
a8d201af ML |
3206 | if (plane_state->visible) |
3207 | plane->update_plane(&plane->base, | |
3208 | to_intel_crtc_state(crtc->state), | |
3209 | plane_state); | |
11c22da6 ML |
3210 | |
3211 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3212 | } |
3213 | } | |
3214 | ||
7514747d VS |
3215 | void intel_prepare_reset(struct drm_device *dev) |
3216 | { | |
3217 | /* no reset support for gen2 */ | |
3218 | if (IS_GEN2(dev)) | |
3219 | return; | |
3220 | ||
3221 | /* reset doesn't touch the display */ | |
3222 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3223 | return; | |
3224 | ||
3225 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3226 | /* |
3227 | * Disabling the crtcs gracefully seems nicer. Also the | |
3228 | * g33 docs say we should at least disable all the planes. | |
3229 | */ | |
6b72d486 | 3230 | intel_display_suspend(dev); |
7514747d VS |
3231 | } |
3232 | ||
3233 | void intel_finish_reset(struct drm_device *dev) | |
3234 | { | |
3235 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3236 | ||
3237 | /* | |
3238 | * Flips in the rings will be nuked by the reset, | |
3239 | * so complete all pending flips so that user space | |
3240 | * will get its events and not get stuck. | |
3241 | */ | |
3242 | intel_complete_page_flips(dev); | |
3243 | ||
3244 | /* no reset support for gen2 */ | |
3245 | if (IS_GEN2(dev)) | |
3246 | return; | |
3247 | ||
3248 | /* reset doesn't touch the display */ | |
3249 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3250 | /* | |
3251 | * Flips in the rings have been nuked by the reset, | |
3252 | * so update the base address of all primary | |
3253 | * planes to the the last fb to make sure we're | |
3254 | * showing the correct fb after a reset. | |
11c22da6 ML |
3255 | * |
3256 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3257 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3258 | */ |
3259 | intel_update_primary_planes(dev); | |
3260 | return; | |
3261 | } | |
3262 | ||
3263 | /* | |
3264 | * The display has been reset as well, | |
3265 | * so need a full re-initialization. | |
3266 | */ | |
3267 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3268 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3269 | ||
3270 | intel_modeset_init_hw(dev); | |
3271 | ||
3272 | spin_lock_irq(&dev_priv->irq_lock); | |
3273 | if (dev_priv->display.hpd_irq_setup) | |
3274 | dev_priv->display.hpd_irq_setup(dev); | |
3275 | spin_unlock_irq(&dev_priv->irq_lock); | |
3276 | ||
043e9bda | 3277 | intel_display_resume(dev); |
7514747d VS |
3278 | |
3279 | intel_hpd_init(dev_priv); | |
3280 | ||
3281 | drm_modeset_unlock_all(dev); | |
3282 | } | |
3283 | ||
7d5e3799 CW |
3284 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3285 | { | |
3286 | struct drm_device *dev = crtc->dev; | |
3287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3289 | bool pending; |
3290 | ||
3291 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3292 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3293 | return false; | |
3294 | ||
5e2d7afc | 3295 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3296 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3297 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3298 | |
3299 | return pending; | |
3300 | } | |
3301 | ||
bfd16b2a ML |
3302 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3303 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3304 | { |
3305 | struct drm_device *dev = crtc->base.dev; | |
3306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3307 | struct intel_crtc_state *pipe_config = |
3308 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3309 | |
bfd16b2a ML |
3310 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3311 | crtc->base.mode = crtc->base.state->mode; | |
3312 | ||
3313 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3314 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3315 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3316 | |
44522d85 ML |
3317 | if (HAS_DDI(dev)) |
3318 | intel_set_pipe_csc(&crtc->base); | |
3319 | ||
e30e8f75 GP |
3320 | /* |
3321 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3322 | * that in compute_mode_changes we check the native mode (not the pfit | |
3323 | * mode) to see if we can flip rather than do a full mode set. In the | |
3324 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3325 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3326 | * sized surface. | |
e30e8f75 GP |
3327 | */ |
3328 | ||
e30e8f75 | 3329 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3330 | ((pipe_config->pipe_src_w - 1) << 16) | |
3331 | (pipe_config->pipe_src_h - 1)); | |
3332 | ||
3333 | /* on skylake this is done by detaching scalers */ | |
3334 | if (INTEL_INFO(dev)->gen >= 9) { | |
3335 | skl_detach_scalers(crtc); | |
3336 | ||
3337 | if (pipe_config->pch_pfit.enabled) | |
3338 | skylake_pfit_enable(crtc); | |
3339 | } else if (HAS_PCH_SPLIT(dev)) { | |
3340 | if (pipe_config->pch_pfit.enabled) | |
3341 | ironlake_pfit_enable(crtc); | |
3342 | else if (old_crtc_state->pch_pfit.enabled) | |
3343 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3344 | } |
e30e8f75 GP |
3345 | } |
3346 | ||
5e84e1a4 ZW |
3347 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3348 | { | |
3349 | struct drm_device *dev = crtc->dev; | |
3350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3352 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3353 | i915_reg_t reg; |
3354 | u32 temp; | |
5e84e1a4 ZW |
3355 | |
3356 | /* enable normal train */ | |
3357 | reg = FDI_TX_CTL(pipe); | |
3358 | temp = I915_READ(reg); | |
61e499bf | 3359 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3360 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3361 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3362 | } else { |
3363 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3364 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3365 | } |
5e84e1a4 ZW |
3366 | I915_WRITE(reg, temp); |
3367 | ||
3368 | reg = FDI_RX_CTL(pipe); | |
3369 | temp = I915_READ(reg); | |
3370 | if (HAS_PCH_CPT(dev)) { | |
3371 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3372 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3373 | } else { | |
3374 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3375 | temp |= FDI_LINK_TRAIN_NONE; | |
3376 | } | |
3377 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3378 | ||
3379 | /* wait one idle pattern time */ | |
3380 | POSTING_READ(reg); | |
3381 | udelay(1000); | |
357555c0 JB |
3382 | |
3383 | /* IVB wants error correction enabled */ | |
3384 | if (IS_IVYBRIDGE(dev)) | |
3385 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3386 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3387 | } |
3388 | ||
8db9d77b ZW |
3389 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3390 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3391 | { | |
3392 | struct drm_device *dev = crtc->dev; | |
3393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3395 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3396 | i915_reg_t reg; |
3397 | u32 temp, tries; | |
8db9d77b | 3398 | |
1c8562f6 | 3399 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3400 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3401 | |
e1a44743 AJ |
3402 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3403 | for train result */ | |
5eddb70b CW |
3404 | reg = FDI_RX_IMR(pipe); |
3405 | temp = I915_READ(reg); | |
e1a44743 AJ |
3406 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3407 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3408 | I915_WRITE(reg, temp); |
3409 | I915_READ(reg); | |
e1a44743 AJ |
3410 | udelay(150); |
3411 | ||
8db9d77b | 3412 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3413 | reg = FDI_TX_CTL(pipe); |
3414 | temp = I915_READ(reg); | |
627eb5a3 | 3415 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3416 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3417 | temp &= ~FDI_LINK_TRAIN_NONE; |
3418 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3419 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3420 | |
5eddb70b CW |
3421 | reg = FDI_RX_CTL(pipe); |
3422 | temp = I915_READ(reg); | |
8db9d77b ZW |
3423 | temp &= ~FDI_LINK_TRAIN_NONE; |
3424 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3425 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3426 | ||
3427 | POSTING_READ(reg); | |
8db9d77b ZW |
3428 | udelay(150); |
3429 | ||
5b2adf89 | 3430 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3431 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3432 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3433 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3434 | |
5eddb70b | 3435 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3436 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3437 | temp = I915_READ(reg); |
8db9d77b ZW |
3438 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3439 | ||
3440 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3441 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3442 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3443 | break; |
3444 | } | |
8db9d77b | 3445 | } |
e1a44743 | 3446 | if (tries == 5) |
5eddb70b | 3447 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3448 | |
3449 | /* Train 2 */ | |
5eddb70b CW |
3450 | reg = FDI_TX_CTL(pipe); |
3451 | temp = I915_READ(reg); | |
8db9d77b ZW |
3452 | temp &= ~FDI_LINK_TRAIN_NONE; |
3453 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3454 | I915_WRITE(reg, temp); |
8db9d77b | 3455 | |
5eddb70b CW |
3456 | reg = FDI_RX_CTL(pipe); |
3457 | temp = I915_READ(reg); | |
8db9d77b ZW |
3458 | temp &= ~FDI_LINK_TRAIN_NONE; |
3459 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3460 | I915_WRITE(reg, temp); |
8db9d77b | 3461 | |
5eddb70b CW |
3462 | POSTING_READ(reg); |
3463 | udelay(150); | |
8db9d77b | 3464 | |
5eddb70b | 3465 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3466 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3467 | temp = I915_READ(reg); |
8db9d77b ZW |
3468 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3469 | ||
3470 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3471 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3472 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3473 | break; | |
3474 | } | |
8db9d77b | 3475 | } |
e1a44743 | 3476 | if (tries == 5) |
5eddb70b | 3477 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3478 | |
3479 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3480 | |
8db9d77b ZW |
3481 | } |
3482 | ||
0206e353 | 3483 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3484 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3485 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3486 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3487 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3488 | }; | |
3489 | ||
3490 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3491 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3492 | { | |
3493 | struct drm_device *dev = crtc->dev; | |
3494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3495 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3496 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3497 | i915_reg_t reg; |
3498 | u32 temp, i, retry; | |
8db9d77b | 3499 | |
e1a44743 AJ |
3500 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3501 | for train result */ | |
5eddb70b CW |
3502 | reg = FDI_RX_IMR(pipe); |
3503 | temp = I915_READ(reg); | |
e1a44743 AJ |
3504 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3505 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3506 | I915_WRITE(reg, temp); |
3507 | ||
3508 | POSTING_READ(reg); | |
e1a44743 AJ |
3509 | udelay(150); |
3510 | ||
8db9d77b | 3511 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3512 | reg = FDI_TX_CTL(pipe); |
3513 | temp = I915_READ(reg); | |
627eb5a3 | 3514 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3515 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3516 | temp &= ~FDI_LINK_TRAIN_NONE; |
3517 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3518 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3519 | /* SNB-B */ | |
3520 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3521 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3522 | |
d74cf324 DV |
3523 | I915_WRITE(FDI_RX_MISC(pipe), |
3524 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3525 | ||
5eddb70b CW |
3526 | reg = FDI_RX_CTL(pipe); |
3527 | temp = I915_READ(reg); | |
8db9d77b ZW |
3528 | if (HAS_PCH_CPT(dev)) { |
3529 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3530 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3531 | } else { | |
3532 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3533 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3534 | } | |
5eddb70b CW |
3535 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3536 | ||
3537 | POSTING_READ(reg); | |
8db9d77b ZW |
3538 | udelay(150); |
3539 | ||
0206e353 | 3540 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3541 | reg = FDI_TX_CTL(pipe); |
3542 | temp = I915_READ(reg); | |
8db9d77b ZW |
3543 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3544 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3545 | I915_WRITE(reg, temp); |
3546 | ||
3547 | POSTING_READ(reg); | |
8db9d77b ZW |
3548 | udelay(500); |
3549 | ||
fa37d39e SP |
3550 | for (retry = 0; retry < 5; retry++) { |
3551 | reg = FDI_RX_IIR(pipe); | |
3552 | temp = I915_READ(reg); | |
3553 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3554 | if (temp & FDI_RX_BIT_LOCK) { | |
3555 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3556 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3557 | break; | |
3558 | } | |
3559 | udelay(50); | |
8db9d77b | 3560 | } |
fa37d39e SP |
3561 | if (retry < 5) |
3562 | break; | |
8db9d77b ZW |
3563 | } |
3564 | if (i == 4) | |
5eddb70b | 3565 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3566 | |
3567 | /* Train 2 */ | |
5eddb70b CW |
3568 | reg = FDI_TX_CTL(pipe); |
3569 | temp = I915_READ(reg); | |
8db9d77b ZW |
3570 | temp &= ~FDI_LINK_TRAIN_NONE; |
3571 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3572 | if (IS_GEN6(dev)) { | |
3573 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3574 | /* SNB-B */ | |
3575 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3576 | } | |
5eddb70b | 3577 | I915_WRITE(reg, temp); |
8db9d77b | 3578 | |
5eddb70b CW |
3579 | reg = FDI_RX_CTL(pipe); |
3580 | temp = I915_READ(reg); | |
8db9d77b ZW |
3581 | if (HAS_PCH_CPT(dev)) { |
3582 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3583 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3584 | } else { | |
3585 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3586 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3587 | } | |
5eddb70b CW |
3588 | I915_WRITE(reg, temp); |
3589 | ||
3590 | POSTING_READ(reg); | |
8db9d77b ZW |
3591 | udelay(150); |
3592 | ||
0206e353 | 3593 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3594 | reg = FDI_TX_CTL(pipe); |
3595 | temp = I915_READ(reg); | |
8db9d77b ZW |
3596 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3597 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3598 | I915_WRITE(reg, temp); |
3599 | ||
3600 | POSTING_READ(reg); | |
8db9d77b ZW |
3601 | udelay(500); |
3602 | ||
fa37d39e SP |
3603 | for (retry = 0; retry < 5; retry++) { |
3604 | reg = FDI_RX_IIR(pipe); | |
3605 | temp = I915_READ(reg); | |
3606 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3607 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3608 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3609 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3610 | break; | |
3611 | } | |
3612 | udelay(50); | |
8db9d77b | 3613 | } |
fa37d39e SP |
3614 | if (retry < 5) |
3615 | break; | |
8db9d77b ZW |
3616 | } |
3617 | if (i == 4) | |
5eddb70b | 3618 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3619 | |
3620 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3621 | } | |
3622 | ||
357555c0 JB |
3623 | /* Manual link training for Ivy Bridge A0 parts */ |
3624 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3625 | { | |
3626 | struct drm_device *dev = crtc->dev; | |
3627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3629 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3630 | i915_reg_t reg; |
3631 | u32 temp, i, j; | |
357555c0 JB |
3632 | |
3633 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3634 | for train result */ | |
3635 | reg = FDI_RX_IMR(pipe); | |
3636 | temp = I915_READ(reg); | |
3637 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3638 | temp &= ~FDI_RX_BIT_LOCK; | |
3639 | I915_WRITE(reg, temp); | |
3640 | ||
3641 | POSTING_READ(reg); | |
3642 | udelay(150); | |
3643 | ||
01a415fd DV |
3644 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3645 | I915_READ(FDI_RX_IIR(pipe))); | |
3646 | ||
139ccd3f JB |
3647 | /* Try each vswing and preemphasis setting twice before moving on */ |
3648 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3649 | /* disable first in case we need to retry */ | |
3650 | reg = FDI_TX_CTL(pipe); | |
3651 | temp = I915_READ(reg); | |
3652 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3653 | temp &= ~FDI_TX_ENABLE; | |
3654 | I915_WRITE(reg, temp); | |
357555c0 | 3655 | |
139ccd3f JB |
3656 | reg = FDI_RX_CTL(pipe); |
3657 | temp = I915_READ(reg); | |
3658 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3659 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3660 | temp &= ~FDI_RX_ENABLE; | |
3661 | I915_WRITE(reg, temp); | |
357555c0 | 3662 | |
139ccd3f | 3663 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3664 | reg = FDI_TX_CTL(pipe); |
3665 | temp = I915_READ(reg); | |
139ccd3f | 3666 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3667 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3668 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3669 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3670 | temp |= snb_b_fdi_train_param[j/2]; |
3671 | temp |= FDI_COMPOSITE_SYNC; | |
3672 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3673 | |
139ccd3f JB |
3674 | I915_WRITE(FDI_RX_MISC(pipe), |
3675 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3676 | |
139ccd3f | 3677 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3678 | temp = I915_READ(reg); |
139ccd3f JB |
3679 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3680 | temp |= FDI_COMPOSITE_SYNC; | |
3681 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3682 | |
139ccd3f JB |
3683 | POSTING_READ(reg); |
3684 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3685 | |
139ccd3f JB |
3686 | for (i = 0; i < 4; i++) { |
3687 | reg = FDI_RX_IIR(pipe); | |
3688 | temp = I915_READ(reg); | |
3689 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3690 | |
139ccd3f JB |
3691 | if (temp & FDI_RX_BIT_LOCK || |
3692 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3693 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3694 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3695 | i); | |
3696 | break; | |
3697 | } | |
3698 | udelay(1); /* should be 0.5us */ | |
3699 | } | |
3700 | if (i == 4) { | |
3701 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3702 | continue; | |
3703 | } | |
357555c0 | 3704 | |
139ccd3f | 3705 | /* Train 2 */ |
357555c0 JB |
3706 | reg = FDI_TX_CTL(pipe); |
3707 | temp = I915_READ(reg); | |
139ccd3f JB |
3708 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3709 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3710 | I915_WRITE(reg, temp); | |
3711 | ||
3712 | reg = FDI_RX_CTL(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3715 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3716 | I915_WRITE(reg, temp); |
3717 | ||
3718 | POSTING_READ(reg); | |
139ccd3f | 3719 | udelay(2); /* should be 1.5us */ |
357555c0 | 3720 | |
139ccd3f JB |
3721 | for (i = 0; i < 4; i++) { |
3722 | reg = FDI_RX_IIR(pipe); | |
3723 | temp = I915_READ(reg); | |
3724 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3725 | |
139ccd3f JB |
3726 | if (temp & FDI_RX_SYMBOL_LOCK || |
3727 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3728 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3729 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3730 | i); | |
3731 | goto train_done; | |
3732 | } | |
3733 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3734 | } |
139ccd3f JB |
3735 | if (i == 4) |
3736 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3737 | } |
357555c0 | 3738 | |
139ccd3f | 3739 | train_done: |
357555c0 JB |
3740 | DRM_DEBUG_KMS("FDI train done.\n"); |
3741 | } | |
3742 | ||
88cefb6c | 3743 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3744 | { |
88cefb6c | 3745 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3746 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3747 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3748 | i915_reg_t reg; |
3749 | u32 temp; | |
c64e311e | 3750 | |
c98e9dcf | 3751 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3752 | reg = FDI_RX_CTL(pipe); |
3753 | temp = I915_READ(reg); | |
627eb5a3 | 3754 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3755 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3756 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3757 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3758 | ||
3759 | POSTING_READ(reg); | |
c98e9dcf JB |
3760 | udelay(200); |
3761 | ||
3762 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3763 | temp = I915_READ(reg); |
3764 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3765 | ||
3766 | POSTING_READ(reg); | |
c98e9dcf JB |
3767 | udelay(200); |
3768 | ||
20749730 PZ |
3769 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3770 | reg = FDI_TX_CTL(pipe); | |
3771 | temp = I915_READ(reg); | |
3772 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3773 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3774 | |
20749730 PZ |
3775 | POSTING_READ(reg); |
3776 | udelay(100); | |
6be4a607 | 3777 | } |
0e23b99d JB |
3778 | } |
3779 | ||
88cefb6c DV |
3780 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3781 | { | |
3782 | struct drm_device *dev = intel_crtc->base.dev; | |
3783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3784 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3785 | i915_reg_t reg; |
3786 | u32 temp; | |
88cefb6c DV |
3787 | |
3788 | /* Switch from PCDclk to Rawclk */ | |
3789 | reg = FDI_RX_CTL(pipe); | |
3790 | temp = I915_READ(reg); | |
3791 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3792 | ||
3793 | /* Disable CPU FDI TX PLL */ | |
3794 | reg = FDI_TX_CTL(pipe); | |
3795 | temp = I915_READ(reg); | |
3796 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3797 | ||
3798 | POSTING_READ(reg); | |
3799 | udelay(100); | |
3800 | ||
3801 | reg = FDI_RX_CTL(pipe); | |
3802 | temp = I915_READ(reg); | |
3803 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3804 | ||
3805 | /* Wait for the clocks to turn off. */ | |
3806 | POSTING_READ(reg); | |
3807 | udelay(100); | |
3808 | } | |
3809 | ||
0fc932b8 JB |
3810 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3811 | { | |
3812 | struct drm_device *dev = crtc->dev; | |
3813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3815 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3816 | i915_reg_t reg; |
3817 | u32 temp; | |
0fc932b8 JB |
3818 | |
3819 | /* disable CPU FDI tx and PCH FDI rx */ | |
3820 | reg = FDI_TX_CTL(pipe); | |
3821 | temp = I915_READ(reg); | |
3822 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3823 | POSTING_READ(reg); | |
3824 | ||
3825 | reg = FDI_RX_CTL(pipe); | |
3826 | temp = I915_READ(reg); | |
3827 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3828 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3829 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3830 | ||
3831 | POSTING_READ(reg); | |
3832 | udelay(100); | |
3833 | ||
3834 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3835 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3836 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3837 | |
3838 | /* still set train pattern 1 */ | |
3839 | reg = FDI_TX_CTL(pipe); | |
3840 | temp = I915_READ(reg); | |
3841 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3842 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3843 | I915_WRITE(reg, temp); | |
3844 | ||
3845 | reg = FDI_RX_CTL(pipe); | |
3846 | temp = I915_READ(reg); | |
3847 | if (HAS_PCH_CPT(dev)) { | |
3848 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3850 | } else { | |
3851 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3852 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3853 | } | |
3854 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3855 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3856 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3857 | I915_WRITE(reg, temp); |
3858 | ||
3859 | POSTING_READ(reg); | |
3860 | udelay(100); | |
3861 | } | |
3862 | ||
5dce5b93 CW |
3863 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3864 | { | |
3865 | struct intel_crtc *crtc; | |
3866 | ||
3867 | /* Note that we don't need to be called with mode_config.lock here | |
3868 | * as our list of CRTC objects is static for the lifetime of the | |
3869 | * device and so cannot disappear as we iterate. Similarly, we can | |
3870 | * happily treat the predicates as racy, atomic checks as userspace | |
3871 | * cannot claim and pin a new fb without at least acquring the | |
3872 | * struct_mutex and so serialising with us. | |
3873 | */ | |
d3fcc808 | 3874 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3875 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3876 | continue; | |
3877 | ||
3878 | if (crtc->unpin_work) | |
3879 | intel_wait_for_vblank(dev, crtc->pipe); | |
3880 | ||
3881 | return true; | |
3882 | } | |
3883 | ||
3884 | return false; | |
3885 | } | |
3886 | ||
d6bbafa1 CW |
3887 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3888 | { | |
3889 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3890 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3891 | ||
3892 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3893 | smp_rmb(); | |
3894 | intel_crtc->unpin_work = NULL; | |
3895 | ||
3896 | if (work->event) | |
3897 | drm_send_vblank_event(intel_crtc->base.dev, | |
3898 | intel_crtc->pipe, | |
3899 | work->event); | |
3900 | ||
3901 | drm_crtc_vblank_put(&intel_crtc->base); | |
3902 | ||
3903 | wake_up_all(&dev_priv->pending_flip_queue); | |
3904 | queue_work(dev_priv->wq, &work->work); | |
3905 | ||
3906 | trace_i915_flip_complete(intel_crtc->plane, | |
3907 | work->pending_flip_obj); | |
3908 | } | |
3909 | ||
5008e874 | 3910 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3911 | { |
0f91128d | 3912 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3913 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3914 | long ret; |
e6c3a2a6 | 3915 | |
2c10d571 | 3916 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3917 | |
3918 | ret = wait_event_interruptible_timeout( | |
3919 | dev_priv->pending_flip_queue, | |
3920 | !intel_crtc_has_pending_flip(crtc), | |
3921 | 60*HZ); | |
3922 | ||
3923 | if (ret < 0) | |
3924 | return ret; | |
3925 | ||
3926 | if (ret == 0) { | |
9c787942 | 3927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3928 | |
5e2d7afc | 3929 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3930 | if (intel_crtc->unpin_work) { |
3931 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3932 | page_flip_completed(intel_crtc); | |
3933 | } | |
5e2d7afc | 3934 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3935 | } |
5bb61643 | 3936 | |
5008e874 | 3937 | return 0; |
e6c3a2a6 CW |
3938 | } |
3939 | ||
060f02d8 VS |
3940 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3941 | { | |
3942 | u32 temp; | |
3943 | ||
3944 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3945 | ||
3946 | mutex_lock(&dev_priv->sb_lock); | |
3947 | ||
3948 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3949 | temp |= SBI_SSCCTL_DISABLE; | |
3950 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3951 | ||
3952 | mutex_unlock(&dev_priv->sb_lock); | |
3953 | } | |
3954 | ||
e615efe4 ED |
3955 | /* Program iCLKIP clock to the desired frequency */ |
3956 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3957 | { | |
3958 | struct drm_device *dev = crtc->dev; | |
3959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3960 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3961 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3962 | u32 temp; | |
3963 | ||
060f02d8 | 3964 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3965 | |
3966 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3967 | if (clock == 20000) { |
e615efe4 ED |
3968 | auxdiv = 1; |
3969 | divsel = 0x41; | |
3970 | phaseinc = 0x20; | |
3971 | } else { | |
3972 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3973 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3974 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3975 | * convert the virtual clock precision to KHz here for higher |
3976 | * precision. | |
3977 | */ | |
3978 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3979 | u32 iclk_pi_range = 64; | |
3980 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3981 | ||
a2572f5c | 3982 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3983 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3984 | pi_value = desired_divisor % iclk_pi_range; | |
3985 | ||
3986 | auxdiv = 0; | |
3987 | divsel = msb_divisor_value - 2; | |
3988 | phaseinc = pi_value; | |
3989 | } | |
3990 | ||
3991 | /* This should not happen with any sane values */ | |
3992 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3993 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3994 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3995 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3996 | ||
3997 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3998 | clock, |
e615efe4 ED |
3999 | auxdiv, |
4000 | divsel, | |
4001 | phasedir, | |
4002 | phaseinc); | |
4003 | ||
060f02d8 VS |
4004 | mutex_lock(&dev_priv->sb_lock); |
4005 | ||
e615efe4 | 4006 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4007 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4008 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4009 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4010 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4011 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4012 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4013 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4014 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4015 | |
4016 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4017 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4018 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4019 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4020 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4021 | |
4022 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4023 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4024 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4025 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4026 | |
060f02d8 VS |
4027 | mutex_unlock(&dev_priv->sb_lock); |
4028 | ||
e615efe4 ED |
4029 | /* Wait for initialization time */ |
4030 | udelay(24); | |
4031 | ||
4032 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4033 | } | |
4034 | ||
275f01b2 DV |
4035 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4036 | enum pipe pch_transcoder) | |
4037 | { | |
4038 | struct drm_device *dev = crtc->base.dev; | |
4039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4040 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4041 | |
4042 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4043 | I915_READ(HTOTAL(cpu_transcoder))); | |
4044 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4045 | I915_READ(HBLANK(cpu_transcoder))); | |
4046 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4047 | I915_READ(HSYNC(cpu_transcoder))); | |
4048 | ||
4049 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4050 | I915_READ(VTOTAL(cpu_transcoder))); | |
4051 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4052 | I915_READ(VBLANK(cpu_transcoder))); | |
4053 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4054 | I915_READ(VSYNC(cpu_transcoder))); | |
4055 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4056 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4057 | } | |
4058 | ||
003632d9 | 4059 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4060 | { |
4061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4062 | uint32_t temp; | |
4063 | ||
4064 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4065 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4066 | return; |
4067 | ||
4068 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4069 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4070 | ||
003632d9 ACO |
4071 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4072 | if (enable) | |
4073 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4074 | ||
4075 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4076 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4077 | POSTING_READ(SOUTH_CHICKEN1); | |
4078 | } | |
4079 | ||
4080 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4081 | { | |
4082 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4083 | |
4084 | switch (intel_crtc->pipe) { | |
4085 | case PIPE_A: | |
4086 | break; | |
4087 | case PIPE_B: | |
6e3c9717 | 4088 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4089 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4090 | else |
003632d9 | 4091 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4092 | |
4093 | break; | |
4094 | case PIPE_C: | |
003632d9 | 4095 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4096 | |
4097 | break; | |
4098 | default: | |
4099 | BUG(); | |
4100 | } | |
4101 | } | |
4102 | ||
c48b5305 VS |
4103 | /* Return which DP Port should be selected for Transcoder DP control */ |
4104 | static enum port | |
4105 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4106 | { | |
4107 | struct drm_device *dev = crtc->dev; | |
4108 | struct intel_encoder *encoder; | |
4109 | ||
4110 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4111 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4112 | encoder->type == INTEL_OUTPUT_EDP) | |
4113 | return enc_to_dig_port(&encoder->base)->port; | |
4114 | } | |
4115 | ||
4116 | return -1; | |
4117 | } | |
4118 | ||
f67a559d JB |
4119 | /* |
4120 | * Enable PCH resources required for PCH ports: | |
4121 | * - PCH PLLs | |
4122 | * - FDI training & RX/TX | |
4123 | * - update transcoder timings | |
4124 | * - DP transcoding bits | |
4125 | * - transcoder | |
4126 | */ | |
4127 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4128 | { |
4129 | struct drm_device *dev = crtc->dev; | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4131 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4132 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4133 | u32 temp; |
2c07245f | 4134 | |
ab9412ba | 4135 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4136 | |
1fbc0d78 DV |
4137 | if (IS_IVYBRIDGE(dev)) |
4138 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4139 | ||
cd986abb DV |
4140 | /* Write the TU size bits before fdi link training, so that error |
4141 | * detection works. */ | |
4142 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4143 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4144 | ||
3860b2ec VS |
4145 | /* |
4146 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4147 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4148 | */ | |
4149 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4150 | ||
c98e9dcf | 4151 | /* For PCH output, training FDI link */ |
674cf967 | 4152 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4153 | |
3ad8a208 DV |
4154 | /* We need to program the right clock selection before writing the pixel |
4155 | * mutliplier into the DPLL. */ | |
303b81e0 | 4156 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4157 | u32 sel; |
4b645f14 | 4158 | |
c98e9dcf | 4159 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4160 | temp |= TRANS_DPLL_ENABLE(pipe); |
4161 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4162 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4163 | temp |= sel; |
4164 | else | |
4165 | temp &= ~sel; | |
c98e9dcf | 4166 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4167 | } |
5eddb70b | 4168 | |
3ad8a208 DV |
4169 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4170 | * transcoder, and we actually should do this to not upset any PCH | |
4171 | * transcoder that already use the clock when we share it. | |
4172 | * | |
4173 | * Note that enable_shared_dpll tries to do the right thing, but | |
4174 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4175 | * the right LVDS enable sequence. */ | |
85b3894f | 4176 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4177 | |
d9b6cb56 JB |
4178 | /* set transcoder timing, panel must allow it */ |
4179 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4180 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4181 | |
303b81e0 | 4182 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4183 | |
3860b2ec VS |
4184 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4185 | ||
c98e9dcf | 4186 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4187 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4188 | const struct drm_display_mode *adjusted_mode = |
4189 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4190 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4191 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4192 | temp = I915_READ(reg); |
4193 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4194 | TRANS_DP_SYNC_MASK | |
4195 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4196 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4197 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4198 | |
9c4edaee | 4199 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4200 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4201 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4202 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4203 | |
4204 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4205 | case PORT_B: |
5eddb70b | 4206 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4207 | break; |
c48b5305 | 4208 | case PORT_C: |
5eddb70b | 4209 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4210 | break; |
c48b5305 | 4211 | case PORT_D: |
5eddb70b | 4212 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4213 | break; |
4214 | default: | |
e95d41e1 | 4215 | BUG(); |
32f9d658 | 4216 | } |
2c07245f | 4217 | |
5eddb70b | 4218 | I915_WRITE(reg, temp); |
6be4a607 | 4219 | } |
b52eb4dc | 4220 | |
b8a4f404 | 4221 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4222 | } |
4223 | ||
1507e5bd PZ |
4224 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4225 | { | |
4226 | struct drm_device *dev = crtc->dev; | |
4227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4229 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4230 | |
ab9412ba | 4231 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4232 | |
8c52b5e8 | 4233 | lpt_program_iclkip(crtc); |
1507e5bd | 4234 | |
0540e488 | 4235 | /* Set transcoder timing. */ |
275f01b2 | 4236 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4237 | |
937bb610 | 4238 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4239 | } |
4240 | ||
190f68c5 ACO |
4241 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4242 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4243 | { |
e2b78267 | 4244 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4245 | struct intel_shared_dpll *pll; |
de419ab6 | 4246 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4247 | enum intel_dpll_id i; |
00490c22 | 4248 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4249 | |
de419ab6 ML |
4250 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4251 | ||
98b6bd99 DV |
4252 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4253 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4254 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4255 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4256 | |
46edb027 DV |
4257 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4258 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4259 | |
de419ab6 | 4260 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4261 | |
98b6bd99 DV |
4262 | goto found; |
4263 | } | |
4264 | ||
bcddf610 S |
4265 | if (IS_BROXTON(dev_priv->dev)) { |
4266 | /* PLL is attached to port in bxt */ | |
4267 | struct intel_encoder *encoder; | |
4268 | struct intel_digital_port *intel_dig_port; | |
4269 | ||
4270 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4271 | if (WARN_ON(!encoder)) | |
4272 | return NULL; | |
4273 | ||
4274 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4275 | /* 1:1 mapping between ports and PLLs */ | |
4276 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4277 | pll = &dev_priv->shared_dplls[i]; | |
4278 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4279 | crtc->base.base.id, pll->name); | |
de419ab6 | 4280 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4281 | |
4282 | goto found; | |
00490c22 ML |
4283 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4284 | /* Do not consider SPLL */ | |
4285 | max = 2; | |
bcddf610 | 4286 | |
00490c22 | 4287 | for (i = 0; i < max; i++) { |
e72f9fbf | 4288 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4289 | |
4290 | /* Only want to check enabled timings first */ | |
de419ab6 | 4291 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4292 | continue; |
4293 | ||
190f68c5 | 4294 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4295 | &shared_dpll[i].hw_state, |
4296 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4297 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4298 | crtc->base.base.id, pll->name, |
de419ab6 | 4299 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4300 | pll->active); |
ee7b9f93 JB |
4301 | goto found; |
4302 | } | |
4303 | } | |
4304 | ||
4305 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4306 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4307 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4308 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4309 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4310 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4311 | goto found; |
4312 | } | |
4313 | } | |
4314 | ||
4315 | return NULL; | |
4316 | ||
4317 | found: | |
de419ab6 ML |
4318 | if (shared_dpll[i].crtc_mask == 0) |
4319 | shared_dpll[i].hw_state = | |
4320 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4321 | |
190f68c5 | 4322 | crtc_state->shared_dpll = i; |
46edb027 DV |
4323 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4324 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4325 | |
de419ab6 | 4326 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4327 | |
ee7b9f93 JB |
4328 | return pll; |
4329 | } | |
4330 | ||
de419ab6 | 4331 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4332 | { |
de419ab6 ML |
4333 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4334 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4335 | struct intel_shared_dpll *pll; |
4336 | enum intel_dpll_id i; | |
4337 | ||
de419ab6 ML |
4338 | if (!to_intel_atomic_state(state)->dpll_set) |
4339 | return; | |
8bd31e67 | 4340 | |
de419ab6 | 4341 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4342 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4343 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4344 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4345 | } |
4346 | } | |
4347 | ||
a1520318 | 4348 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4349 | { |
4350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4351 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4352 | u32 temp; |
4353 | ||
4354 | temp = I915_READ(dslreg); | |
4355 | udelay(500); | |
4356 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4357 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4358 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4359 | } |
4360 | } | |
4361 | ||
86adf9d7 ML |
4362 | static int |
4363 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4364 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4365 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4366 | { |
86adf9d7 ML |
4367 | struct intel_crtc_scaler_state *scaler_state = |
4368 | &crtc_state->scaler_state; | |
4369 | struct intel_crtc *intel_crtc = | |
4370 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4371 | int need_scaling; |
6156a456 CK |
4372 | |
4373 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4374 | (src_h != dst_w || src_w != dst_h): | |
4375 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4376 | |
4377 | /* | |
4378 | * if plane is being disabled or scaler is no more required or force detach | |
4379 | * - free scaler binded to this plane/crtc | |
4380 | * - in order to do this, update crtc->scaler_usage | |
4381 | * | |
4382 | * Here scaler state in crtc_state is set free so that | |
4383 | * scaler can be assigned to other user. Actual register | |
4384 | * update to free the scaler is done in plane/panel-fit programming. | |
4385 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4386 | */ | |
86adf9d7 | 4387 | if (force_detach || !need_scaling) { |
a1b2278e | 4388 | if (*scaler_id >= 0) { |
86adf9d7 | 4389 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4390 | scaler_state->scalers[*scaler_id].in_use = 0; |
4391 | ||
86adf9d7 ML |
4392 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4393 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4394 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4395 | scaler_state->scaler_users); |
4396 | *scaler_id = -1; | |
4397 | } | |
4398 | return 0; | |
4399 | } | |
4400 | ||
4401 | /* range checks */ | |
4402 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4403 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4404 | ||
4405 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4406 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4407 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4408 | "size is out of scaler range\n", |
86adf9d7 | 4409 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4410 | return -EINVAL; |
4411 | } | |
4412 | ||
86adf9d7 ML |
4413 | /* mark this plane as a scaler user in crtc_state */ |
4414 | scaler_state->scaler_users |= (1 << scaler_user); | |
4415 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4416 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4417 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4418 | scaler_state->scaler_users); | |
4419 | ||
4420 | return 0; | |
4421 | } | |
4422 | ||
4423 | /** | |
4424 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4425 | * | |
4426 | * @state: crtc's scaler state | |
86adf9d7 ML |
4427 | * |
4428 | * Return | |
4429 | * 0 - scaler_usage updated successfully | |
4430 | * error - requested scaling cannot be supported or other error condition | |
4431 | */ | |
e435d6e5 | 4432 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4433 | { |
4434 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4435 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4436 | |
4437 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4438 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4439 | ||
e435d6e5 | 4440 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4441 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4442 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4443 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4444 | } |
4445 | ||
4446 | /** | |
4447 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4448 | * | |
4449 | * @state: crtc's scaler state | |
86adf9d7 ML |
4450 | * @plane_state: atomic plane state to update |
4451 | * | |
4452 | * Return | |
4453 | * 0 - scaler_usage updated successfully | |
4454 | * error - requested scaling cannot be supported or other error condition | |
4455 | */ | |
da20eabd ML |
4456 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4457 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4458 | { |
4459 | ||
4460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4461 | struct intel_plane *intel_plane = |
4462 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4463 | struct drm_framebuffer *fb = plane_state->base.fb; |
4464 | int ret; | |
4465 | ||
4466 | bool force_detach = !fb || !plane_state->visible; | |
4467 | ||
4468 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4469 | intel_plane->base.base.id, intel_crtc->pipe, | |
4470 | drm_plane_index(&intel_plane->base)); | |
4471 | ||
4472 | ret = skl_update_scaler(crtc_state, force_detach, | |
4473 | drm_plane_index(&intel_plane->base), | |
4474 | &plane_state->scaler_id, | |
4475 | plane_state->base.rotation, | |
4476 | drm_rect_width(&plane_state->src) >> 16, | |
4477 | drm_rect_height(&plane_state->src) >> 16, | |
4478 | drm_rect_width(&plane_state->dst), | |
4479 | drm_rect_height(&plane_state->dst)); | |
4480 | ||
4481 | if (ret || plane_state->scaler_id < 0) | |
4482 | return ret; | |
4483 | ||
a1b2278e | 4484 | /* check colorkey */ |
818ed961 | 4485 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4486 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4487 | intel_plane->base.base.id); |
a1b2278e CK |
4488 | return -EINVAL; |
4489 | } | |
4490 | ||
4491 | /* Check src format */ | |
86adf9d7 ML |
4492 | switch (fb->pixel_format) { |
4493 | case DRM_FORMAT_RGB565: | |
4494 | case DRM_FORMAT_XBGR8888: | |
4495 | case DRM_FORMAT_XRGB8888: | |
4496 | case DRM_FORMAT_ABGR8888: | |
4497 | case DRM_FORMAT_ARGB8888: | |
4498 | case DRM_FORMAT_XRGB2101010: | |
4499 | case DRM_FORMAT_XBGR2101010: | |
4500 | case DRM_FORMAT_YUYV: | |
4501 | case DRM_FORMAT_YVYU: | |
4502 | case DRM_FORMAT_UYVY: | |
4503 | case DRM_FORMAT_VYUY: | |
4504 | break; | |
4505 | default: | |
4506 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4507 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4508 | return -EINVAL; | |
a1b2278e CK |
4509 | } |
4510 | ||
a1b2278e CK |
4511 | return 0; |
4512 | } | |
4513 | ||
e435d6e5 ML |
4514 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4515 | { | |
4516 | int i; | |
4517 | ||
4518 | for (i = 0; i < crtc->num_scalers; i++) | |
4519 | skl_detach_scaler(crtc, i); | |
4520 | } | |
4521 | ||
4522 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4523 | { |
4524 | struct drm_device *dev = crtc->base.dev; | |
4525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4526 | int pipe = crtc->pipe; | |
a1b2278e CK |
4527 | struct intel_crtc_scaler_state *scaler_state = |
4528 | &crtc->config->scaler_state; | |
4529 | ||
4530 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4531 | ||
6e3c9717 | 4532 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4533 | int id; |
4534 | ||
4535 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4536 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4537 | return; | |
4538 | } | |
4539 | ||
4540 | id = scaler_state->scaler_id; | |
4541 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4542 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4543 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4544 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4545 | ||
4546 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4547 | } |
4548 | } | |
4549 | ||
b074cec8 JB |
4550 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4551 | { | |
4552 | struct drm_device *dev = crtc->base.dev; | |
4553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4554 | int pipe = crtc->pipe; | |
4555 | ||
6e3c9717 | 4556 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4557 | /* Force use of hard-coded filter coefficients |
4558 | * as some pre-programmed values are broken, | |
4559 | * e.g. x201. | |
4560 | */ | |
4561 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4562 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4563 | PF_PIPE_SEL_IVB(pipe)); | |
4564 | else | |
4565 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4566 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4567 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4568 | } |
4569 | } | |
4570 | ||
20bc8673 | 4571 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4572 | { |
cea165c3 VS |
4573 | struct drm_device *dev = crtc->base.dev; |
4574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4575 | |
6e3c9717 | 4576 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4577 | return; |
4578 | ||
cea165c3 VS |
4579 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4580 | intel_wait_for_vblank(dev, crtc->pipe); | |
4581 | ||
d77e4531 | 4582 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4583 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4584 | mutex_lock(&dev_priv->rps.hw_lock); |
4585 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4586 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4587 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4588 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4589 | * mailbox." Moreover, the mailbox may return a bogus state, |
4590 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4591 | */ |
4592 | } else { | |
4593 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4594 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4595 | * is essentially intel_wait_for_vblank. If we don't have this | |
4596 | * and don't wait for vblanks until the end of crtc_enable, then | |
4597 | * the HW state readout code will complain that the expected | |
4598 | * IPS_CTL value is not the one we read. */ | |
4599 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4600 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4601 | } | |
d77e4531 PZ |
4602 | } |
4603 | ||
20bc8673 | 4604 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4605 | { |
4606 | struct drm_device *dev = crtc->base.dev; | |
4607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4608 | ||
6e3c9717 | 4609 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4610 | return; |
4611 | ||
4612 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4613 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4614 | mutex_lock(&dev_priv->rps.hw_lock); |
4615 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4616 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4617 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4618 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4619 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4620 | } else { |
2a114cc1 | 4621 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4622 | POSTING_READ(IPS_CTL); |
4623 | } | |
d77e4531 PZ |
4624 | |
4625 | /* We need to wait for a vblank before we can disable the plane. */ | |
4626 | intel_wait_for_vblank(dev, crtc->pipe); | |
4627 | } | |
4628 | ||
4629 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4630 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4631 | { | |
4632 | struct drm_device *dev = crtc->dev; | |
4633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4634 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4635 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4636 | int i; |
4637 | bool reenable_ips = false; | |
4638 | ||
4639 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4640 | if (!crtc->state->active) |
d77e4531 PZ |
4641 | return; |
4642 | ||
50360403 | 4643 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4644 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4645 | assert_dsi_pll_enabled(dev_priv); |
4646 | else | |
4647 | assert_pll_enabled(dev_priv, pipe); | |
4648 | } | |
4649 | ||
d77e4531 PZ |
4650 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4651 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4652 | */ | |
6e3c9717 | 4653 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4654 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4655 | GAMMA_MODE_MODE_SPLIT)) { | |
4656 | hsw_disable_ips(intel_crtc); | |
4657 | reenable_ips = true; | |
4658 | } | |
4659 | ||
4660 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4661 | i915_reg_t palreg; |
f65a9c5b VS |
4662 | |
4663 | if (HAS_GMCH_DISPLAY(dev)) | |
4664 | palreg = PALETTE(pipe, i); | |
4665 | else | |
4666 | palreg = LGC_PALETTE(pipe, i); | |
4667 | ||
4668 | I915_WRITE(palreg, | |
d77e4531 PZ |
4669 | (intel_crtc->lut_r[i] << 16) | |
4670 | (intel_crtc->lut_g[i] << 8) | | |
4671 | intel_crtc->lut_b[i]); | |
4672 | } | |
4673 | ||
4674 | if (reenable_ips) | |
4675 | hsw_enable_ips(intel_crtc); | |
4676 | } | |
4677 | ||
7cac945f | 4678 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4679 | { |
7cac945f | 4680 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4681 | struct drm_device *dev = intel_crtc->base.dev; |
4682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4683 | ||
4684 | mutex_lock(&dev->struct_mutex); | |
4685 | dev_priv->mm.interruptible = false; | |
4686 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4687 | dev_priv->mm.interruptible = true; | |
4688 | mutex_unlock(&dev->struct_mutex); | |
4689 | } | |
4690 | ||
4691 | /* Let userspace switch the overlay on again. In most cases userspace | |
4692 | * has to recompute where to put it anyway. | |
4693 | */ | |
4694 | } | |
4695 | ||
87d4300a ML |
4696 | /** |
4697 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4698 | * @crtc: the CRTC whose primary plane was just enabled | |
4699 | * | |
4700 | * Performs potentially sleeping operations that must be done after the primary | |
4701 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4702 | * called due to an explicit primary plane update, or due to an implicit | |
4703 | * re-enable that is caused when a sprite plane is updated to no longer | |
4704 | * completely hide the primary plane. | |
4705 | */ | |
4706 | static void | |
4707 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4708 | { |
4709 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4710 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4712 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4713 | |
87d4300a ML |
4714 | /* |
4715 | * FIXME IPS should be fine as long as one plane is | |
4716 | * enabled, but in practice it seems to have problems | |
4717 | * when going from primary only to sprite only and vice | |
4718 | * versa. | |
4719 | */ | |
a5c4d7bc VS |
4720 | hsw_enable_ips(intel_crtc); |
4721 | ||
f99d7069 | 4722 | /* |
87d4300a ML |
4723 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4724 | * So don't enable underrun reporting before at least some planes | |
4725 | * are enabled. | |
4726 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4727 | * but leave the pipe running. | |
f99d7069 | 4728 | */ |
87d4300a ML |
4729 | if (IS_GEN2(dev)) |
4730 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4731 | ||
aca7b684 VS |
4732 | /* Underruns don't always raise interrupts, so check manually. */ |
4733 | intel_check_cpu_fifo_underruns(dev_priv); | |
4734 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4735 | } |
4736 | ||
87d4300a ML |
4737 | /** |
4738 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4739 | * @crtc: the CRTC whose primary plane is to be disabled | |
4740 | * | |
4741 | * Performs potentially sleeping operations that must be done before the | |
4742 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4743 | * be called due to an explicit primary plane update, or due to an implicit | |
4744 | * disable that is caused when a sprite plane completely hides the primary | |
4745 | * plane. | |
4746 | */ | |
4747 | static void | |
4748 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4749 | { |
4750 | struct drm_device *dev = crtc->dev; | |
4751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4753 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4754 | |
87d4300a ML |
4755 | /* |
4756 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4757 | * So diasble underrun reporting before all the planes get disabled. | |
4758 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4759 | * but leave the pipe running. | |
4760 | */ | |
4761 | if (IS_GEN2(dev)) | |
4762 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4763 | |
87d4300a ML |
4764 | /* |
4765 | * Vblank time updates from the shadow to live plane control register | |
4766 | * are blocked if the memory self-refresh mode is active at that | |
4767 | * moment. So to make sure the plane gets truly disabled, disable | |
4768 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4769 | * will be checked/applied by the HW only at the next frame start | |
4770 | * event which is after the vblank start event, so we need to have a | |
4771 | * wait-for-vblank between disabling the plane and the pipe. | |
4772 | */ | |
262cd2e1 | 4773 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4774 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4775 | dev_priv->wm.vlv.cxsr = false; |
4776 | intel_wait_for_vblank(dev, pipe); | |
4777 | } | |
87d4300a | 4778 | |
87d4300a ML |
4779 | /* |
4780 | * FIXME IPS should be fine as long as one plane is | |
4781 | * enabled, but in practice it seems to have problems | |
4782 | * when going from primary only to sprite only and vice | |
4783 | * versa. | |
4784 | */ | |
a5c4d7bc | 4785 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4786 | } |
4787 | ||
ac21b225 ML |
4788 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4789 | { | |
4790 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4791 | struct intel_crtc_state *pipe_config = |
4792 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4793 | struct drm_device *dev = crtc->base.dev; |
ac21b225 | 4794 | |
ac21b225 ML |
4795 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
4796 | ||
ab1d3a0e | 4797 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4798 | |
b9001114 | 4799 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4800 | intel_update_watermarks(&crtc->base); |
4801 | ||
c80ac854 | 4802 | if (atomic->update_fbc) |
1eb52238 | 4803 | intel_fbc_post_update(crtc); |
ac21b225 ML |
4804 | |
4805 | if (atomic->post_enable_primary) | |
4806 | intel_post_enable_primary(&crtc->base); | |
4807 | ||
ac21b225 ML |
4808 | memset(atomic, 0, sizeof(*atomic)); |
4809 | } | |
4810 | ||
5c74cd73 | 4811 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4812 | { |
5c74cd73 | 4813 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4814 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4815 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4816 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4817 | struct intel_crtc_state *pipe_config = |
4818 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4819 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4820 | struct drm_plane *primary = crtc->base.primary; | |
4821 | struct drm_plane_state *old_pri_state = | |
4822 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4823 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4824 | |
1eb52238 PZ |
4825 | if (atomic->update_fbc) |
4826 | intel_fbc_pre_update(crtc); | |
ac21b225 | 4827 | |
5c74cd73 ML |
4828 | if (old_pri_state) { |
4829 | struct intel_plane_state *primary_state = | |
4830 | to_intel_plane_state(primary->state); | |
4831 | struct intel_plane_state *old_primary_state = | |
4832 | to_intel_plane_state(old_pri_state); | |
4833 | ||
4834 | if (old_primary_state->visible && | |
4835 | (modeset || !primary_state->visible)) | |
4836 | intel_pre_disable_primary(&crtc->base); | |
4837 | } | |
852eb00d | 4838 | |
ab1d3a0e | 4839 | if (pipe_config->disable_cxsr) { |
852eb00d | 4840 | crtc->wm.cxsr_allowed = false; |
2dfd178d ML |
4841 | |
4842 | if (old_crtc_state->base.active) | |
4843 | intel_set_memory_cxsr(dev_priv, false); | |
852eb00d | 4844 | } |
92826fcd | 4845 | |
ed4a6a7c MR |
4846 | /* |
4847 | * IVB workaround: must disable low power watermarks for at least | |
4848 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4849 | * when scaling is disabled. | |
4850 | * | |
4851 | * WaCxSRDisabledForSpriteScaling:ivb | |
4852 | */ | |
4853 | if (pipe_config->disable_lp_wm) { | |
4854 | ilk_disable_lp_wm(dev); | |
4855 | intel_wait_for_vblank(dev, crtc->pipe); | |
4856 | } | |
4857 | ||
4858 | /* | |
4859 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4860 | * watermark programming here. | |
4861 | */ | |
4862 | if (needs_modeset(&pipe_config->base)) | |
4863 | return; | |
4864 | ||
4865 | /* | |
4866 | * For platforms that support atomic watermarks, program the | |
4867 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4868 | * will be the intermediate values that are safe for both pre- and | |
4869 | * post- vblank; when vblank happens, the 'active' values will be set | |
4870 | * to the final 'target' values and we'll do this again to get the | |
4871 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4872 | * will be the final target values which will get automatically latched | |
4873 | * at vblank time; no further programming will be necessary. | |
4874 | * | |
4875 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4876 | * we'll continue to update watermarks the old way, if flags tell | |
4877 | * us to. | |
4878 | */ | |
4879 | if (dev_priv->display.initial_watermarks != NULL) | |
4880 | dev_priv->display.initial_watermarks(pipe_config); | |
4881 | else if (pipe_config->wm_changed) | |
92826fcd | 4882 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4883 | } |
4884 | ||
d032ffa0 | 4885 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4886 | { |
4887 | struct drm_device *dev = crtc->dev; | |
4888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4889 | struct drm_plane *p; |
87d4300a ML |
4890 | int pipe = intel_crtc->pipe; |
4891 | ||
7cac945f | 4892 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4893 | |
d032ffa0 ML |
4894 | drm_for_each_plane_mask(p, dev, plane_mask) |
4895 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4896 | |
f99d7069 DV |
4897 | /* |
4898 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4899 | * to compute the mask of flip planes precisely. For the time being | |
4900 | * consider this a flip to a NULL plane. | |
4901 | */ | |
4902 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4903 | } |
4904 | ||
f67a559d JB |
4905 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4906 | { | |
4907 | struct drm_device *dev = crtc->dev; | |
4908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4910 | struct intel_encoder *encoder; |
f67a559d | 4911 | int pipe = intel_crtc->pipe; |
f67a559d | 4912 | |
53d9f4e9 | 4913 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4914 | return; |
4915 | ||
81b088ca VS |
4916 | if (intel_crtc->config->has_pch_encoder) |
4917 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4918 | ||
6e3c9717 | 4919 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4920 | intel_prepare_shared_dpll(intel_crtc); |
4921 | ||
6e3c9717 | 4922 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4923 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4924 | |
4925 | intel_set_pipe_timings(intel_crtc); | |
4926 | ||
6e3c9717 | 4927 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4928 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4929 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4930 | } |
4931 | ||
4932 | ironlake_set_pipeconf(crtc); | |
4933 | ||
f67a559d | 4934 | intel_crtc->active = true; |
8664281b | 4935 | |
a72e4c9f | 4936 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4937 | |
f6736a1a | 4938 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4939 | if (encoder->pre_enable) |
4940 | encoder->pre_enable(encoder); | |
f67a559d | 4941 | |
6e3c9717 | 4942 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4943 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4944 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4945 | * enabling. */ | |
88cefb6c | 4946 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4947 | } else { |
4948 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4949 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4950 | } | |
f67a559d | 4951 | |
b074cec8 | 4952 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4953 | |
9c54c0dd JB |
4954 | /* |
4955 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4956 | * clocks enabled | |
4957 | */ | |
4958 | intel_crtc_load_lut(crtc); | |
4959 | ||
ed4a6a7c | 4960 | dev_priv->display.initial_watermarks(intel_crtc->config); |
e1fdc473 | 4961 | intel_enable_pipe(intel_crtc); |
f67a559d | 4962 | |
6e3c9717 | 4963 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4964 | ironlake_pch_enable(crtc); |
c98e9dcf | 4965 | |
f9b61ff6 DV |
4966 | assert_vblank_disabled(crtc); |
4967 | drm_crtc_vblank_on(crtc); | |
4968 | ||
fa5c73b1 DV |
4969 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4970 | encoder->enable(encoder); | |
61b77ddd DV |
4971 | |
4972 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4973 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4974 | |
4975 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4976 | if (intel_crtc->config->has_pch_encoder) | |
4977 | intel_wait_for_vblank(dev, pipe); | |
4978 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4979 | } |
4980 | ||
42db64ef PZ |
4981 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4982 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4983 | { | |
f5adf94e | 4984 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4985 | } |
4986 | ||
4f771f10 PZ |
4987 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4988 | { | |
4989 | struct drm_device *dev = crtc->dev; | |
4990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4991 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4992 | struct intel_encoder *encoder; | |
99d736a2 ML |
4993 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4994 | struct intel_crtc_state *pipe_config = | |
4995 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4996 | |
53d9f4e9 | 4997 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4998 | return; |
4999 | ||
81b088ca VS |
5000 | if (intel_crtc->config->has_pch_encoder) |
5001 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5002 | false); | |
5003 | ||
df8ad70c DV |
5004 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
5005 | intel_enable_shared_dpll(intel_crtc); | |
5006 | ||
6e3c9717 | 5007 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5008 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
5009 | |
5010 | intel_set_pipe_timings(intel_crtc); | |
5011 | ||
6e3c9717 ACO |
5012 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5013 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5014 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5015 | } |
5016 | ||
6e3c9717 | 5017 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5018 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5019 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5020 | } |
5021 | ||
5022 | haswell_set_pipeconf(crtc); | |
5023 | ||
5024 | intel_set_pipe_csc(crtc); | |
5025 | ||
4f771f10 | 5026 | intel_crtc->active = true; |
8664281b | 5027 | |
6b698516 DV |
5028 | if (intel_crtc->config->has_pch_encoder) |
5029 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5030 | else | |
5031 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5032 | ||
7d4aefd0 | 5033 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5034 | if (encoder->pre_enable) |
5035 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5036 | } |
4f771f10 | 5037 | |
d2d65408 | 5038 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5039 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5040 | |
a65347ba | 5041 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5042 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5043 | |
1c132b44 | 5044 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5045 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5046 | else |
1c132b44 | 5047 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5048 | |
5049 | /* | |
5050 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5051 | * clocks enabled | |
5052 | */ | |
5053 | intel_crtc_load_lut(crtc); | |
5054 | ||
1f544388 | 5055 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5056 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5057 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5058 | |
ed4a6a7c | 5059 | dev_priv->display.initial_watermarks(pipe_config); |
e1fdc473 | 5060 | intel_enable_pipe(intel_crtc); |
42db64ef | 5061 | |
6e3c9717 | 5062 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5063 | lpt_pch_enable(crtc); |
4f771f10 | 5064 | |
a65347ba | 5065 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5066 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5067 | ||
f9b61ff6 DV |
5068 | assert_vblank_disabled(crtc); |
5069 | drm_crtc_vblank_on(crtc); | |
5070 | ||
8807e55b | 5071 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5072 | encoder->enable(encoder); |
8807e55b JN |
5073 | intel_opregion_notify_encoder(encoder, true); |
5074 | } | |
4f771f10 | 5075 | |
6b698516 DV |
5076 | if (intel_crtc->config->has_pch_encoder) { |
5077 | intel_wait_for_vblank(dev, pipe); | |
5078 | intel_wait_for_vblank(dev, pipe); | |
5079 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5080 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5081 | true); | |
6b698516 | 5082 | } |
d2d65408 | 5083 | |
e4916946 PZ |
5084 | /* If we change the relative order between pipe/planes enabling, we need |
5085 | * to change the workaround. */ | |
99d736a2 ML |
5086 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5087 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5088 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5089 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5090 | } | |
4f771f10 PZ |
5091 | } |
5092 | ||
bfd16b2a | 5093 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5094 | { |
5095 | struct drm_device *dev = crtc->base.dev; | |
5096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5097 | int pipe = crtc->pipe; | |
5098 | ||
5099 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5100 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5101 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5102 | I915_WRITE(PF_CTL(pipe), 0); |
5103 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5104 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5105 | } | |
5106 | } | |
5107 | ||
6be4a607 JB |
5108 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5109 | { | |
5110 | struct drm_device *dev = crtc->dev; | |
5111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5112 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5113 | struct intel_encoder *encoder; |
6be4a607 | 5114 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5115 | |
37ca8d4c VS |
5116 | if (intel_crtc->config->has_pch_encoder) |
5117 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5118 | ||
ea9d758d DV |
5119 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5120 | encoder->disable(encoder); | |
5121 | ||
f9b61ff6 DV |
5122 | drm_crtc_vblank_off(crtc); |
5123 | assert_vblank_disabled(crtc); | |
5124 | ||
3860b2ec VS |
5125 | /* |
5126 | * Sometimes spurious CPU pipe underruns happen when the | |
5127 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5128 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5129 | */ | |
5130 | if (intel_crtc->config->has_pch_encoder) | |
5131 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5132 | ||
575f7ab7 | 5133 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5134 | |
bfd16b2a | 5135 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5136 | |
3860b2ec | 5137 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5138 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5139 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5140 | } | |
5a74f70a | 5141 | |
bf49ec8c DV |
5142 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5143 | if (encoder->post_disable) | |
5144 | encoder->post_disable(encoder); | |
2c07245f | 5145 | |
6e3c9717 | 5146 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5147 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5148 | |
d925c59a | 5149 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5150 | i915_reg_t reg; |
5151 | u32 temp; | |
5152 | ||
d925c59a DV |
5153 | /* disable TRANS_DP_CTL */ |
5154 | reg = TRANS_DP_CTL(pipe); | |
5155 | temp = I915_READ(reg); | |
5156 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5157 | TRANS_DP_PORT_SEL_MASK); | |
5158 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5159 | I915_WRITE(reg, temp); | |
5160 | ||
5161 | /* disable DPLL_SEL */ | |
5162 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5163 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5164 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5165 | } |
e3421a18 | 5166 | |
d925c59a DV |
5167 | ironlake_fdi_pll_disable(intel_crtc); |
5168 | } | |
81b088ca VS |
5169 | |
5170 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5171 | } |
1b3c7a47 | 5172 | |
4f771f10 | 5173 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5174 | { |
4f771f10 PZ |
5175 | struct drm_device *dev = crtc->dev; |
5176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5177 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5178 | struct intel_encoder *encoder; |
6e3c9717 | 5179 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5180 | |
d2d65408 VS |
5181 | if (intel_crtc->config->has_pch_encoder) |
5182 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5183 | false); | |
5184 | ||
8807e55b JN |
5185 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5186 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5187 | encoder->disable(encoder); |
8807e55b | 5188 | } |
4f771f10 | 5189 | |
f9b61ff6 DV |
5190 | drm_crtc_vblank_off(crtc); |
5191 | assert_vblank_disabled(crtc); | |
5192 | ||
575f7ab7 | 5193 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5194 | |
6e3c9717 | 5195 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5196 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5197 | ||
a65347ba | 5198 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5199 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5200 | |
1c132b44 | 5201 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5202 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5203 | else |
bfd16b2a | 5204 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5205 | |
a65347ba | 5206 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5207 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5208 | |
97b040aa ID |
5209 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5210 | if (encoder->post_disable) | |
5211 | encoder->post_disable(encoder); | |
81b088ca | 5212 | |
92966a37 VS |
5213 | if (intel_crtc->config->has_pch_encoder) { |
5214 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5215 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5216 | intel_ddi_fdi_disable(crtc); |
5217 | ||
81b088ca VS |
5218 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5219 | true); | |
92966a37 | 5220 | } |
4f771f10 PZ |
5221 | } |
5222 | ||
2dd24552 JB |
5223 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5224 | { | |
5225 | struct drm_device *dev = crtc->base.dev; | |
5226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5227 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5228 | |
681a8504 | 5229 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5230 | return; |
5231 | ||
2dd24552 | 5232 | /* |
c0b03411 DV |
5233 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5234 | * according to register description and PRM. | |
2dd24552 | 5235 | */ |
c0b03411 DV |
5236 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5237 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5238 | |
b074cec8 JB |
5239 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5240 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5241 | |
5242 | /* Border color in case we don't scale up to the full screen. Black by | |
5243 | * default, change to something else for debugging. */ | |
5244 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5245 | } |
5246 | ||
d05410f9 DA |
5247 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5248 | { | |
5249 | switch (port) { | |
5250 | case PORT_A: | |
6331a704 | 5251 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5252 | case PORT_B: |
6331a704 | 5253 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5254 | case PORT_C: |
6331a704 | 5255 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5256 | case PORT_D: |
6331a704 | 5257 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5258 | case PORT_E: |
6331a704 | 5259 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5260 | default: |
b9fec167 | 5261 | MISSING_CASE(port); |
d05410f9 DA |
5262 | return POWER_DOMAIN_PORT_OTHER; |
5263 | } | |
5264 | } | |
5265 | ||
25f78f58 VS |
5266 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5267 | { | |
5268 | switch (port) { | |
5269 | case PORT_A: | |
5270 | return POWER_DOMAIN_AUX_A; | |
5271 | case PORT_B: | |
5272 | return POWER_DOMAIN_AUX_B; | |
5273 | case PORT_C: | |
5274 | return POWER_DOMAIN_AUX_C; | |
5275 | case PORT_D: | |
5276 | return POWER_DOMAIN_AUX_D; | |
5277 | case PORT_E: | |
5278 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5279 | return POWER_DOMAIN_AUX_D; | |
5280 | default: | |
b9fec167 | 5281 | MISSING_CASE(port); |
25f78f58 VS |
5282 | return POWER_DOMAIN_AUX_A; |
5283 | } | |
5284 | } | |
5285 | ||
319be8ae ID |
5286 | enum intel_display_power_domain |
5287 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5288 | { | |
5289 | struct drm_device *dev = intel_encoder->base.dev; | |
5290 | struct intel_digital_port *intel_dig_port; | |
5291 | ||
5292 | switch (intel_encoder->type) { | |
5293 | case INTEL_OUTPUT_UNKNOWN: | |
5294 | /* Only DDI platforms should ever use this output type */ | |
5295 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5296 | case INTEL_OUTPUT_DISPLAYPORT: | |
5297 | case INTEL_OUTPUT_HDMI: | |
5298 | case INTEL_OUTPUT_EDP: | |
5299 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5300 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5301 | case INTEL_OUTPUT_DP_MST: |
5302 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5303 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5304 | case INTEL_OUTPUT_ANALOG: |
5305 | return POWER_DOMAIN_PORT_CRT; | |
5306 | case INTEL_OUTPUT_DSI: | |
5307 | return POWER_DOMAIN_PORT_DSI; | |
5308 | default: | |
5309 | return POWER_DOMAIN_PORT_OTHER; | |
5310 | } | |
5311 | } | |
5312 | ||
25f78f58 VS |
5313 | enum intel_display_power_domain |
5314 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5315 | { | |
5316 | struct drm_device *dev = intel_encoder->base.dev; | |
5317 | struct intel_digital_port *intel_dig_port; | |
5318 | ||
5319 | switch (intel_encoder->type) { | |
5320 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5321 | case INTEL_OUTPUT_HDMI: |
5322 | /* | |
5323 | * Only DDI platforms should ever use these output types. | |
5324 | * We can get here after the HDMI detect code has already set | |
5325 | * the type of the shared encoder. Since we can't be sure | |
5326 | * what's the status of the given connectors, play safe and | |
5327 | * run the DP detection too. | |
5328 | */ | |
25f78f58 VS |
5329 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5330 | case INTEL_OUTPUT_DISPLAYPORT: | |
5331 | case INTEL_OUTPUT_EDP: | |
5332 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5333 | return port_to_aux_power_domain(intel_dig_port->port); | |
5334 | case INTEL_OUTPUT_DP_MST: | |
5335 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5336 | return port_to_aux_power_domain(intel_dig_port->port); | |
5337 | default: | |
b9fec167 | 5338 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5339 | return POWER_DOMAIN_AUX_A; |
5340 | } | |
5341 | } | |
5342 | ||
74bff5f9 ML |
5343 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5344 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5345 | { |
319be8ae | 5346 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5347 | struct drm_encoder *encoder; |
319be8ae ID |
5348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5349 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5350 | unsigned long mask; |
74bff5f9 | 5351 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5352 | |
74bff5f9 | 5353 | if (!crtc_state->base.active) |
292b990e ML |
5354 | return 0; |
5355 | ||
77d22dca ID |
5356 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5357 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5358 | if (crtc_state->pch_pfit.enabled || |
5359 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5360 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5361 | ||
74bff5f9 ML |
5362 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5363 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5364 | ||
319be8ae | 5365 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5366 | } |
319be8ae | 5367 | |
77d22dca ID |
5368 | return mask; |
5369 | } | |
5370 | ||
74bff5f9 ML |
5371 | static unsigned long |
5372 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5373 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5374 | { |
292b990e ML |
5375 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5377 | enum intel_display_power_domain domain; | |
5378 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5379 | |
292b990e | 5380 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5381 | intel_crtc->enabled_power_domains = new_domains = |
5382 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5383 | |
292b990e ML |
5384 | domains = new_domains & ~old_domains; |
5385 | ||
5386 | for_each_power_domain(domain, domains) | |
5387 | intel_display_power_get(dev_priv, domain); | |
5388 | ||
5389 | return old_domains & ~new_domains; | |
5390 | } | |
5391 | ||
5392 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5393 | unsigned long domains) | |
5394 | { | |
5395 | enum intel_display_power_domain domain; | |
5396 | ||
5397 | for_each_power_domain(domain, domains) | |
5398 | intel_display_power_put(dev_priv, domain); | |
5399 | } | |
77d22dca | 5400 | |
adafdc6f MK |
5401 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5402 | { | |
5403 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5404 | ||
5405 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5406 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5407 | return max_cdclk_freq; | |
5408 | else if (IS_CHERRYVIEW(dev_priv)) | |
5409 | return max_cdclk_freq*95/100; | |
5410 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5411 | return 2*max_cdclk_freq*90/100; | |
5412 | else | |
5413 | return max_cdclk_freq*90/100; | |
5414 | } | |
5415 | ||
560a7ae4 DL |
5416 | static void intel_update_max_cdclk(struct drm_device *dev) |
5417 | { | |
5418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5419 | ||
ef11bdb3 | 5420 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5421 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5422 | ||
5423 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5424 | dev_priv->max_cdclk_freq = 675000; | |
5425 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5426 | dev_priv->max_cdclk_freq = 540000; | |
5427 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5428 | dev_priv->max_cdclk_freq = 450000; | |
5429 | else | |
5430 | dev_priv->max_cdclk_freq = 337500; | |
5431 | } else if (IS_BROADWELL(dev)) { | |
5432 | /* | |
5433 | * FIXME with extra cooling we can allow | |
5434 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5435 | * How can we know if extra cooling is | |
5436 | * available? PCI ID, VTB, something else? | |
5437 | */ | |
5438 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5439 | dev_priv->max_cdclk_freq = 450000; | |
5440 | else if (IS_BDW_ULX(dev)) | |
5441 | dev_priv->max_cdclk_freq = 450000; | |
5442 | else if (IS_BDW_ULT(dev)) | |
5443 | dev_priv->max_cdclk_freq = 540000; | |
5444 | else | |
5445 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5446 | } else if (IS_CHERRYVIEW(dev)) { |
5447 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5448 | } else if (IS_VALLEYVIEW(dev)) { |
5449 | dev_priv->max_cdclk_freq = 400000; | |
5450 | } else { | |
5451 | /* otherwise assume cdclk is fixed */ | |
5452 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5453 | } | |
5454 | ||
adafdc6f MK |
5455 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5456 | ||
560a7ae4 DL |
5457 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5458 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5459 | |
5460 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5461 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5462 | } |
5463 | ||
5464 | static void intel_update_cdclk(struct drm_device *dev) | |
5465 | { | |
5466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5467 | ||
5468 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5469 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5470 | dev_priv->cdclk_freq); | |
5471 | ||
5472 | /* | |
5473 | * Program the gmbus_freq based on the cdclk frequency. | |
5474 | * BSpec erroneously claims we should aim for 4MHz, but | |
5475 | * in fact 1MHz is the correct frequency. | |
5476 | */ | |
666a4537 | 5477 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5478 | /* |
5479 | * Program the gmbus_freq based on the cdclk frequency. | |
5480 | * BSpec erroneously claims we should aim for 4MHz, but | |
5481 | * in fact 1MHz is the correct frequency. | |
5482 | */ | |
5483 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5484 | } | |
5485 | ||
5486 | if (dev_priv->max_cdclk_freq == 0) | |
5487 | intel_update_max_cdclk(dev); | |
5488 | } | |
5489 | ||
70d0c574 | 5490 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5491 | { |
5492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5493 | uint32_t divider; | |
5494 | uint32_t ratio; | |
5495 | uint32_t current_freq; | |
5496 | int ret; | |
5497 | ||
5498 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5499 | switch (frequency) { | |
5500 | case 144000: | |
5501 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5502 | ratio = BXT_DE_PLL_RATIO(60); | |
5503 | break; | |
5504 | case 288000: | |
5505 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5506 | ratio = BXT_DE_PLL_RATIO(60); | |
5507 | break; | |
5508 | case 384000: | |
5509 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5510 | ratio = BXT_DE_PLL_RATIO(60); | |
5511 | break; | |
5512 | case 576000: | |
5513 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5514 | ratio = BXT_DE_PLL_RATIO(60); | |
5515 | break; | |
5516 | case 624000: | |
5517 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5518 | ratio = BXT_DE_PLL_RATIO(65); | |
5519 | break; | |
5520 | case 19200: | |
5521 | /* | |
5522 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5523 | * to suppress GCC warning. | |
5524 | */ | |
5525 | ratio = 0; | |
5526 | divider = 0; | |
5527 | break; | |
5528 | default: | |
5529 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5530 | ||
5531 | return; | |
5532 | } | |
5533 | ||
5534 | mutex_lock(&dev_priv->rps.hw_lock); | |
5535 | /* Inform power controller of upcoming frequency change */ | |
5536 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5537 | 0x80000000); | |
5538 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5539 | ||
5540 | if (ret) { | |
5541 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5542 | ret, frequency); | |
5543 | return; | |
5544 | } | |
5545 | ||
5546 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5547 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5548 | current_freq = current_freq * 500 + 1000; | |
5549 | ||
5550 | /* | |
5551 | * DE PLL has to be disabled when | |
5552 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5553 | * - before setting to 624MHz (PLL needs toggling) | |
5554 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5555 | */ | |
5556 | if (frequency == 19200 || frequency == 624000 || | |
5557 | current_freq == 624000) { | |
5558 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5559 | /* Timeout 200us */ | |
5560 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5561 | 1)) | |
5562 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5563 | } | |
5564 | ||
5565 | if (frequency != 19200) { | |
5566 | uint32_t val; | |
5567 | ||
5568 | val = I915_READ(BXT_DE_PLL_CTL); | |
5569 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5570 | val |= ratio; | |
5571 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5572 | ||
5573 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5574 | /* Timeout 200us */ | |
5575 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5576 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5577 | ||
5578 | val = I915_READ(CDCLK_CTL); | |
5579 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5580 | val |= divider; | |
5581 | /* | |
5582 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5583 | * enable otherwise. | |
5584 | */ | |
5585 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5586 | if (frequency >= 500000) | |
5587 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5588 | ||
5589 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5590 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5591 | val |= (frequency - 1000) / 500; | |
5592 | I915_WRITE(CDCLK_CTL, val); | |
5593 | } | |
5594 | ||
5595 | mutex_lock(&dev_priv->rps.hw_lock); | |
5596 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5597 | DIV_ROUND_UP(frequency, 25000)); | |
5598 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5599 | ||
5600 | if (ret) { | |
5601 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5602 | ret, frequency); | |
5603 | return; | |
5604 | } | |
5605 | ||
a47871bd | 5606 | intel_update_cdclk(dev); |
f8437dd1 VK |
5607 | } |
5608 | ||
5609 | void broxton_init_cdclk(struct drm_device *dev) | |
5610 | { | |
5611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5612 | uint32_t val; | |
5613 | ||
5614 | /* | |
5615 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5616 | * or else the reset will hang because there is no PCH to respond. | |
5617 | * Move the handshake programming to initialization sequence. | |
5618 | * Previously was left up to BIOS. | |
5619 | */ | |
5620 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5621 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5622 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5623 | ||
5624 | /* Enable PG1 for cdclk */ | |
5625 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5626 | ||
5627 | /* check if cd clock is enabled */ | |
5628 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5629 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5630 | return; | |
5631 | } | |
5632 | ||
5633 | /* | |
5634 | * FIXME: | |
5635 | * - The initial CDCLK needs to be read from VBT. | |
5636 | * Need to make this change after VBT has changes for BXT. | |
5637 | * - check if setting the max (or any) cdclk freq is really necessary | |
5638 | * here, it belongs to modeset time | |
5639 | */ | |
5640 | broxton_set_cdclk(dev, 624000); | |
5641 | ||
5642 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5643 | POSTING_READ(DBUF_CTL); |
5644 | ||
f8437dd1 VK |
5645 | udelay(10); |
5646 | ||
5647 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5648 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5649 | } | |
5650 | ||
5651 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5652 | { | |
5653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5654 | ||
5655 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5656 | POSTING_READ(DBUF_CTL); |
5657 | ||
f8437dd1 VK |
5658 | udelay(10); |
5659 | ||
5660 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5661 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5662 | ||
5663 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5664 | broxton_set_cdclk(dev, 19200); | |
5665 | ||
5666 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5667 | } | |
5668 | ||
5d96d8af DL |
5669 | static const struct skl_cdclk_entry { |
5670 | unsigned int freq; | |
5671 | unsigned int vco; | |
5672 | } skl_cdclk_frequencies[] = { | |
5673 | { .freq = 308570, .vco = 8640 }, | |
5674 | { .freq = 337500, .vco = 8100 }, | |
5675 | { .freq = 432000, .vco = 8640 }, | |
5676 | { .freq = 450000, .vco = 8100 }, | |
5677 | { .freq = 540000, .vco = 8100 }, | |
5678 | { .freq = 617140, .vco = 8640 }, | |
5679 | { .freq = 675000, .vco = 8100 }, | |
5680 | }; | |
5681 | ||
5682 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5683 | { | |
5684 | return (freq - 1000) / 500; | |
5685 | } | |
5686 | ||
5687 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5688 | { | |
5689 | unsigned int i; | |
5690 | ||
5691 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5692 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5693 | ||
5694 | if (e->freq == freq) | |
5695 | return e->vco; | |
5696 | } | |
5697 | ||
5698 | return 8100; | |
5699 | } | |
5700 | ||
5701 | static void | |
5702 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5703 | { | |
5704 | unsigned int min_freq; | |
5705 | u32 val; | |
5706 | ||
5707 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5708 | val = I915_READ(CDCLK_CTL); | |
5709 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5710 | val |= CDCLK_FREQ_337_308; | |
5711 | ||
5712 | if (required_vco == 8640) | |
5713 | min_freq = 308570; | |
5714 | else | |
5715 | min_freq = 337500; | |
5716 | ||
5717 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5718 | ||
5719 | I915_WRITE(CDCLK_CTL, val); | |
5720 | POSTING_READ(CDCLK_CTL); | |
5721 | ||
5722 | /* | |
5723 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5724 | * taking into account the VCO required to operate the eDP panel at the | |
5725 | * desired frequency. The usual DP link rates operate with a VCO of | |
5726 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5727 | * The modeset code is responsible for the selection of the exact link | |
5728 | * rate later on, with the constraint of choosing a frequency that | |
5729 | * works with required_vco. | |
5730 | */ | |
5731 | val = I915_READ(DPLL_CTRL1); | |
5732 | ||
5733 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5734 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5735 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5736 | if (required_vco == 8640) | |
5737 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5738 | SKL_DPLL0); | |
5739 | else | |
5740 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5741 | SKL_DPLL0); | |
5742 | ||
5743 | I915_WRITE(DPLL_CTRL1, val); | |
5744 | POSTING_READ(DPLL_CTRL1); | |
5745 | ||
5746 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5747 | ||
5748 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5749 | DRM_ERROR("DPLL0 not locked\n"); | |
5750 | } | |
5751 | ||
5752 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5753 | { | |
5754 | int ret; | |
5755 | u32 val; | |
5756 | ||
5757 | /* inform PCU we want to change CDCLK */ | |
5758 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5759 | mutex_lock(&dev_priv->rps.hw_lock); | |
5760 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5761 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5762 | ||
5763 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5764 | } | |
5765 | ||
5766 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5767 | { | |
5768 | unsigned int i; | |
5769 | ||
5770 | for (i = 0; i < 15; i++) { | |
5771 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5772 | return true; | |
5773 | udelay(10); | |
5774 | } | |
5775 | ||
5776 | return false; | |
5777 | } | |
5778 | ||
5779 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5780 | { | |
560a7ae4 | 5781 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5782 | u32 freq_select, pcu_ack; |
5783 | ||
5784 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5785 | ||
5786 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5787 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5788 | return; | |
5789 | } | |
5790 | ||
5791 | /* set CDCLK_CTL */ | |
5792 | switch(freq) { | |
5793 | case 450000: | |
5794 | case 432000: | |
5795 | freq_select = CDCLK_FREQ_450_432; | |
5796 | pcu_ack = 1; | |
5797 | break; | |
5798 | case 540000: | |
5799 | freq_select = CDCLK_FREQ_540; | |
5800 | pcu_ack = 2; | |
5801 | break; | |
5802 | case 308570: | |
5803 | case 337500: | |
5804 | default: | |
5805 | freq_select = CDCLK_FREQ_337_308; | |
5806 | pcu_ack = 0; | |
5807 | break; | |
5808 | case 617140: | |
5809 | case 675000: | |
5810 | freq_select = CDCLK_FREQ_675_617; | |
5811 | pcu_ack = 3; | |
5812 | break; | |
5813 | } | |
5814 | ||
5815 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5816 | POSTING_READ(CDCLK_CTL); | |
5817 | ||
5818 | /* inform PCU of the change */ | |
5819 | mutex_lock(&dev_priv->rps.hw_lock); | |
5820 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5821 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5822 | |
5823 | intel_update_cdclk(dev); | |
5d96d8af DL |
5824 | } |
5825 | ||
5826 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5827 | { | |
5828 | /* disable DBUF power */ | |
5829 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5830 | POSTING_READ(DBUF_CTL); | |
5831 | ||
5832 | udelay(10); | |
5833 | ||
5834 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5835 | DRM_ERROR("DBuf power disable timeout\n"); | |
5836 | ||
ab96c1ee ID |
5837 | /* disable DPLL0 */ |
5838 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5839 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5840 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5841 | } |
5842 | ||
5843 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5844 | { | |
5d96d8af DL |
5845 | unsigned int required_vco; |
5846 | ||
39d9b85a GW |
5847 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5848 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5849 | /* enable DPLL0 */ | |
5850 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5851 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5852 | } |
5853 | ||
5d96d8af DL |
5854 | /* set CDCLK to the frequency the BIOS chose */ |
5855 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5856 | ||
5857 | /* enable DBUF power */ | |
5858 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5859 | POSTING_READ(DBUF_CTL); | |
5860 | ||
5861 | udelay(10); | |
5862 | ||
5863 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5864 | DRM_ERROR("DBuf power enable timeout\n"); | |
5865 | } | |
5866 | ||
c73666f3 SK |
5867 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5868 | { | |
5869 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5870 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5871 | int freq = dev_priv->skl_boot_cdclk; | |
5872 | ||
f1b391a5 SK |
5873 | /* |
5874 | * check if the pre-os intialized the display | |
5875 | * There is SWF18 scratchpad register defined which is set by the | |
5876 | * pre-os which can be used by the OS drivers to check the status | |
5877 | */ | |
5878 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5879 | goto sanitize; | |
5880 | ||
c73666f3 SK |
5881 | /* Is PLL enabled and locked ? */ |
5882 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5883 | goto sanitize; | |
5884 | ||
5885 | /* DPLL okay; verify the cdclock | |
5886 | * | |
5887 | * Noticed in some instances that the freq selection is correct but | |
5888 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5889 | * enable display. Verify the same as well. | |
5890 | */ | |
5891 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5892 | /* All well; nothing to sanitize */ | |
5893 | return false; | |
5894 | sanitize: | |
5895 | /* | |
5896 | * As of now initialize with max cdclk till | |
5897 | * we get dynamic cdclk support | |
5898 | * */ | |
5899 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5900 | skl_init_cdclk(dev_priv); | |
5901 | ||
5902 | /* we did have to sanitize */ | |
5903 | return true; | |
5904 | } | |
5905 | ||
30a970c6 JB |
5906 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5907 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5908 | { | |
5909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5910 | u32 val, cmd; | |
5911 | ||
164dfd28 VK |
5912 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5913 | != dev_priv->cdclk_freq); | |
d60c4473 | 5914 | |
dfcab17e | 5915 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5916 | cmd = 2; |
dfcab17e | 5917 | else if (cdclk == 266667) |
30a970c6 JB |
5918 | cmd = 1; |
5919 | else | |
5920 | cmd = 0; | |
5921 | ||
5922 | mutex_lock(&dev_priv->rps.hw_lock); | |
5923 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5924 | val &= ~DSPFREQGUAR_MASK; | |
5925 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5926 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5927 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5928 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5929 | 50)) { | |
5930 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5931 | } | |
5932 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5933 | ||
54433e91 VS |
5934 | mutex_lock(&dev_priv->sb_lock); |
5935 | ||
dfcab17e | 5936 | if (cdclk == 400000) { |
6bcda4f0 | 5937 | u32 divider; |
30a970c6 | 5938 | |
6bcda4f0 | 5939 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5940 | |
30a970c6 JB |
5941 | /* adjust cdclk divider */ |
5942 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5943 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5944 | val |= divider; |
5945 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5946 | |
5947 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5948 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5949 | 50)) |
5950 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5951 | } |
5952 | ||
30a970c6 JB |
5953 | /* adjust self-refresh exit latency value */ |
5954 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5955 | val &= ~0x7f; | |
5956 | ||
5957 | /* | |
5958 | * For high bandwidth configs, we set a higher latency in the bunit | |
5959 | * so that the core display fetch happens in time to avoid underruns. | |
5960 | */ | |
dfcab17e | 5961 | if (cdclk == 400000) |
30a970c6 JB |
5962 | val |= 4500 / 250; /* 4.5 usec */ |
5963 | else | |
5964 | val |= 3000 / 250; /* 3.0 usec */ | |
5965 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5966 | |
a580516d | 5967 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5968 | |
b6283055 | 5969 | intel_update_cdclk(dev); |
30a970c6 JB |
5970 | } |
5971 | ||
383c5a6a VS |
5972 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5973 | { | |
5974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5975 | u32 val, cmd; | |
5976 | ||
164dfd28 VK |
5977 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5978 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5979 | |
5980 | switch (cdclk) { | |
383c5a6a VS |
5981 | case 333333: |
5982 | case 320000: | |
383c5a6a | 5983 | case 266667: |
383c5a6a | 5984 | case 200000: |
383c5a6a VS |
5985 | break; |
5986 | default: | |
5f77eeb0 | 5987 | MISSING_CASE(cdclk); |
383c5a6a VS |
5988 | return; |
5989 | } | |
5990 | ||
9d0d3fda VS |
5991 | /* |
5992 | * Specs are full of misinformation, but testing on actual | |
5993 | * hardware has shown that we just need to write the desired | |
5994 | * CCK divider into the Punit register. | |
5995 | */ | |
5996 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5997 | ||
383c5a6a VS |
5998 | mutex_lock(&dev_priv->rps.hw_lock); |
5999 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6000 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6001 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6002 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6003 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6004 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6005 | 50)) { | |
6006 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6007 | } | |
6008 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6009 | ||
b6283055 | 6010 | intel_update_cdclk(dev); |
383c5a6a VS |
6011 | } |
6012 | ||
30a970c6 JB |
6013 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6014 | int max_pixclk) | |
6015 | { | |
6bcda4f0 | 6016 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6017 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6018 | |
30a970c6 JB |
6019 | /* |
6020 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6021 | * 200MHz | |
6022 | * 267MHz | |
29dc7ef3 | 6023 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6024 | * 400MHz (VLV only) |
6025 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6026 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6027 | * |
6028 | * We seem to get an unstable or solid color picture at 200MHz. | |
6029 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6030 | * are off. | |
30a970c6 | 6031 | */ |
6cca3195 VS |
6032 | if (!IS_CHERRYVIEW(dev_priv) && |
6033 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6034 | return 400000; |
6cca3195 | 6035 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6036 | return freq_320; |
e37c67a1 | 6037 | else if (max_pixclk > 0) |
dfcab17e | 6038 | return 266667; |
e37c67a1 VS |
6039 | else |
6040 | return 200000; | |
30a970c6 JB |
6041 | } |
6042 | ||
f8437dd1 VK |
6043 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6044 | int max_pixclk) | |
6045 | { | |
6046 | /* | |
6047 | * FIXME: | |
6048 | * - remove the guardband, it's not needed on BXT | |
6049 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6050 | */ | |
6051 | if (max_pixclk > 576000*9/10) | |
6052 | return 624000; | |
6053 | else if (max_pixclk > 384000*9/10) | |
6054 | return 576000; | |
6055 | else if (max_pixclk > 288000*9/10) | |
6056 | return 384000; | |
6057 | else if (max_pixclk > 144000*9/10) | |
6058 | return 288000; | |
6059 | else | |
6060 | return 144000; | |
6061 | } | |
6062 | ||
e8788cbc | 6063 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6064 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6065 | struct drm_atomic_state *state) | |
30a970c6 | 6066 | { |
565602d7 ML |
6067 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6069 | struct drm_crtc *crtc; | |
6070 | struct drm_crtc_state *crtc_state; | |
6071 | unsigned max_pixclk = 0, i; | |
6072 | enum pipe pipe; | |
30a970c6 | 6073 | |
565602d7 ML |
6074 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6075 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6076 | |
565602d7 ML |
6077 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6078 | int pixclk = 0; | |
6079 | ||
6080 | if (crtc_state->enable) | |
6081 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6082 | |
565602d7 | 6083 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6084 | } |
6085 | ||
565602d7 ML |
6086 | for_each_pipe(dev_priv, pipe) |
6087 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6088 | ||
30a970c6 JB |
6089 | return max_pixclk; |
6090 | } | |
6091 | ||
27c329ed | 6092 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6093 | { |
27c329ed ML |
6094 | struct drm_device *dev = state->dev; |
6095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6096 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6097 | struct intel_atomic_state *intel_state = |
6098 | to_intel_atomic_state(state); | |
30a970c6 | 6099 | |
304603f4 ACO |
6100 | if (max_pixclk < 0) |
6101 | return max_pixclk; | |
30a970c6 | 6102 | |
1a617b77 | 6103 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6104 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6105 | |
1a617b77 ML |
6106 | if (!intel_state->active_crtcs) |
6107 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6108 | ||
27c329ed ML |
6109 | return 0; |
6110 | } | |
304603f4 | 6111 | |
27c329ed ML |
6112 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6113 | { | |
6114 | struct drm_device *dev = state->dev; | |
6115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6116 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6117 | struct intel_atomic_state *intel_state = |
6118 | to_intel_atomic_state(state); | |
85a96e7a | 6119 | |
27c329ed ML |
6120 | if (max_pixclk < 0) |
6121 | return max_pixclk; | |
85a96e7a | 6122 | |
1a617b77 | 6123 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6124 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6125 | |
1a617b77 ML |
6126 | if (!intel_state->active_crtcs) |
6127 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6128 | ||
27c329ed | 6129 | return 0; |
30a970c6 JB |
6130 | } |
6131 | ||
1e69cd74 VS |
6132 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6133 | { | |
6134 | unsigned int credits, default_credits; | |
6135 | ||
6136 | if (IS_CHERRYVIEW(dev_priv)) | |
6137 | default_credits = PFI_CREDIT(12); | |
6138 | else | |
6139 | default_credits = PFI_CREDIT(8); | |
6140 | ||
bfa7df01 | 6141 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6142 | /* CHV suggested value is 31 or 63 */ |
6143 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6144 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6145 | else |
6146 | credits = PFI_CREDIT(15); | |
6147 | } else { | |
6148 | credits = default_credits; | |
6149 | } | |
6150 | ||
6151 | /* | |
6152 | * WA - write default credits before re-programming | |
6153 | * FIXME: should we also set the resend bit here? | |
6154 | */ | |
6155 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6156 | default_credits); | |
6157 | ||
6158 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6159 | credits | PFI_CREDIT_RESEND); | |
6160 | ||
6161 | /* | |
6162 | * FIXME is this guaranteed to clear | |
6163 | * immediately or should we poll for it? | |
6164 | */ | |
6165 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6166 | } | |
6167 | ||
27c329ed | 6168 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6169 | { |
a821fc46 | 6170 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6171 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6172 | struct intel_atomic_state *old_intel_state = |
6173 | to_intel_atomic_state(old_state); | |
6174 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6175 | |
27c329ed ML |
6176 | /* |
6177 | * FIXME: We can end up here with all power domains off, yet | |
6178 | * with a CDCLK frequency other than the minimum. To account | |
6179 | * for this take the PIPE-A power domain, which covers the HW | |
6180 | * blocks needed for the following programming. This can be | |
6181 | * removed once it's guaranteed that we get here either with | |
6182 | * the minimum CDCLK set, or the required power domains | |
6183 | * enabled. | |
6184 | */ | |
6185 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6186 | |
27c329ed ML |
6187 | if (IS_CHERRYVIEW(dev)) |
6188 | cherryview_set_cdclk(dev, req_cdclk); | |
6189 | else | |
6190 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6191 | |
27c329ed | 6192 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6193 | |
27c329ed | 6194 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6195 | } |
6196 | ||
89b667f8 JB |
6197 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6198 | { | |
6199 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6200 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6201 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6202 | struct intel_encoder *encoder; | |
6203 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6204 | |
53d9f4e9 | 6205 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6206 | return; |
6207 | ||
6e3c9717 | 6208 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6209 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6210 | |
6211 | intel_set_pipe_timings(intel_crtc); | |
6212 | ||
c14b0485 VS |
6213 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6215 | ||
6216 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6217 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6218 | } | |
6219 | ||
5b18e57c DV |
6220 | i9xx_set_pipeconf(intel_crtc); |
6221 | ||
89b667f8 | 6222 | intel_crtc->active = true; |
89b667f8 | 6223 | |
a72e4c9f | 6224 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6225 | |
89b667f8 JB |
6226 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6227 | if (encoder->pre_pll_enable) | |
6228 | encoder->pre_pll_enable(encoder); | |
6229 | ||
a65347ba | 6230 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6231 | if (IS_CHERRYVIEW(dev)) { |
6232 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6233 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6234 | } else { |
6235 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6236 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6237 | } |
9d556c99 | 6238 | } |
89b667f8 JB |
6239 | |
6240 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6241 | if (encoder->pre_enable) | |
6242 | encoder->pre_enable(encoder); | |
6243 | ||
2dd24552 JB |
6244 | i9xx_pfit_enable(intel_crtc); |
6245 | ||
63cbb074 VS |
6246 | intel_crtc_load_lut(crtc); |
6247 | ||
e1fdc473 | 6248 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6249 | |
4b3a9526 VS |
6250 | assert_vblank_disabled(crtc); |
6251 | drm_crtc_vblank_on(crtc); | |
6252 | ||
f9b61ff6 DV |
6253 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6254 | encoder->enable(encoder); | |
89b667f8 JB |
6255 | } |
6256 | ||
f13c2ef3 DV |
6257 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6258 | { | |
6259 | struct drm_device *dev = crtc->base.dev; | |
6260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6261 | ||
6e3c9717 ACO |
6262 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6263 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6264 | } |
6265 | ||
0b8765c6 | 6266 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6267 | { |
6268 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6269 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6271 | struct intel_encoder *encoder; |
79e53945 | 6272 | int pipe = intel_crtc->pipe; |
79e53945 | 6273 | |
53d9f4e9 | 6274 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6275 | return; |
6276 | ||
f13c2ef3 DV |
6277 | i9xx_set_pll_dividers(intel_crtc); |
6278 | ||
6e3c9717 | 6279 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6280 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6281 | |
6282 | intel_set_pipe_timings(intel_crtc); | |
6283 | ||
5b18e57c DV |
6284 | i9xx_set_pipeconf(intel_crtc); |
6285 | ||
f7abfe8b | 6286 | intel_crtc->active = true; |
6b383a7f | 6287 | |
4a3436e8 | 6288 | if (!IS_GEN2(dev)) |
a72e4c9f | 6289 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6290 | |
9d6d9f19 MK |
6291 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6292 | if (encoder->pre_enable) | |
6293 | encoder->pre_enable(encoder); | |
6294 | ||
f6736a1a DV |
6295 | i9xx_enable_pll(intel_crtc); |
6296 | ||
2dd24552 JB |
6297 | i9xx_pfit_enable(intel_crtc); |
6298 | ||
63cbb074 VS |
6299 | intel_crtc_load_lut(crtc); |
6300 | ||
f37fcc2a | 6301 | intel_update_watermarks(crtc); |
e1fdc473 | 6302 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6303 | |
4b3a9526 VS |
6304 | assert_vblank_disabled(crtc); |
6305 | drm_crtc_vblank_on(crtc); | |
6306 | ||
f9b61ff6 DV |
6307 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6308 | encoder->enable(encoder); | |
0b8765c6 | 6309 | } |
79e53945 | 6310 | |
87476d63 DV |
6311 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6312 | { | |
6313 | struct drm_device *dev = crtc->base.dev; | |
6314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6315 | |
6e3c9717 | 6316 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6317 | return; |
87476d63 | 6318 | |
328d8e82 | 6319 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6320 | |
328d8e82 DV |
6321 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6322 | I915_READ(PFIT_CONTROL)); | |
6323 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6324 | } |
6325 | ||
0b8765c6 JB |
6326 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6327 | { | |
6328 | struct drm_device *dev = crtc->dev; | |
6329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6330 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6331 | struct intel_encoder *encoder; |
0b8765c6 | 6332 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6333 | |
6304cd91 VS |
6334 | /* |
6335 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6336 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6337 | * We also need to wait on all gmch platforms because of the |
6338 | * self-refresh mode constraint explained above. | |
6304cd91 | 6339 | */ |
564ed191 | 6340 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6341 | |
4b3a9526 VS |
6342 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6343 | encoder->disable(encoder); | |
6344 | ||
f9b61ff6 DV |
6345 | drm_crtc_vblank_off(crtc); |
6346 | assert_vblank_disabled(crtc); | |
6347 | ||
575f7ab7 | 6348 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6349 | |
87476d63 | 6350 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6351 | |
89b667f8 JB |
6352 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6353 | if (encoder->post_disable) | |
6354 | encoder->post_disable(encoder); | |
6355 | ||
a65347ba | 6356 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6357 | if (IS_CHERRYVIEW(dev)) |
6358 | chv_disable_pll(dev_priv, pipe); | |
6359 | else if (IS_VALLEYVIEW(dev)) | |
6360 | vlv_disable_pll(dev_priv, pipe); | |
6361 | else | |
1c4e0274 | 6362 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6363 | } |
0b8765c6 | 6364 | |
d6db995f VS |
6365 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6366 | if (encoder->post_pll_disable) | |
6367 | encoder->post_pll_disable(encoder); | |
6368 | ||
4a3436e8 | 6369 | if (!IS_GEN2(dev)) |
a72e4c9f | 6370 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6371 | } |
6372 | ||
b17d48e2 ML |
6373 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6374 | { | |
6375 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6376 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6377 | enum intel_display_power_domain domain; | |
6378 | unsigned long domains; | |
6379 | ||
6380 | if (!intel_crtc->active) | |
6381 | return; | |
6382 | ||
a539205a | 6383 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6384 | WARN_ON(intel_crtc->unpin_work); |
6385 | ||
a539205a | 6386 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6387 | |
6388 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6389 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6390 | } |
6391 | ||
b17d48e2 | 6392 | dev_priv->display.crtc_disable(crtc); |
37d9078b | 6393 | intel_crtc->active = false; |
58f9c0bc | 6394 | intel_fbc_disable(intel_crtc); |
37d9078b | 6395 | intel_update_watermarks(crtc); |
1f7457b1 | 6396 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6397 | |
6398 | domains = intel_crtc->enabled_power_domains; | |
6399 | for_each_power_domain(domain, domains) | |
6400 | intel_display_power_put(dev_priv, domain); | |
6401 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6402 | |
6403 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6404 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6405 | } |
6406 | ||
6b72d486 ML |
6407 | /* |
6408 | * turn all crtc's off, but do not adjust state | |
6409 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6410 | */ | |
70e0bd74 | 6411 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6412 | { |
e2c8b870 | 6413 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6414 | struct drm_atomic_state *state; |
e2c8b870 | 6415 | int ret; |
70e0bd74 | 6416 | |
e2c8b870 ML |
6417 | state = drm_atomic_helper_suspend(dev); |
6418 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6419 | if (ret) |
6420 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6421 | else |
6422 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6423 | return ret; |
ee7b9f93 JB |
6424 | } |
6425 | ||
ea5b213a | 6426 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6427 | { |
4ef69c7a | 6428 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6429 | |
ea5b213a CW |
6430 | drm_encoder_cleanup(encoder); |
6431 | kfree(intel_encoder); | |
7e7d76c3 JB |
6432 | } |
6433 | ||
0a91ca29 DV |
6434 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6435 | * internal consistency). */ | |
b980514c | 6436 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6437 | { |
35dd3c64 ML |
6438 | struct drm_crtc *crtc = connector->base.state->crtc; |
6439 | ||
6440 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6441 | connector->base.base.id, | |
6442 | connector->base.name); | |
6443 | ||
0a91ca29 | 6444 | if (connector->get_hw_state(connector)) { |
e85376cb | 6445 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6446 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6447 | |
35dd3c64 ML |
6448 | I915_STATE_WARN(!crtc, |
6449 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6450 | |
35dd3c64 ML |
6451 | if (!crtc) |
6452 | return; | |
6453 | ||
6454 | I915_STATE_WARN(!crtc->state->active, | |
6455 | "connector is active, but attached crtc isn't\n"); | |
6456 | ||
e85376cb | 6457 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6458 | return; |
6459 | ||
e85376cb | 6460 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6461 | "atomic encoder doesn't match attached encoder\n"); |
6462 | ||
e85376cb | 6463 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6464 | "attached encoder crtc differs from connector crtc\n"); |
6465 | } else { | |
4d688a2a ML |
6466 | I915_STATE_WARN(crtc && crtc->state->active, |
6467 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6468 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6469 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6470 | } |
79e53945 JB |
6471 | } |
6472 | ||
08d9bc92 ACO |
6473 | int intel_connector_init(struct intel_connector *connector) |
6474 | { | |
5350a031 | 6475 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6476 | |
5350a031 | 6477 | if (!connector->base.state) |
08d9bc92 ACO |
6478 | return -ENOMEM; |
6479 | ||
08d9bc92 ACO |
6480 | return 0; |
6481 | } | |
6482 | ||
6483 | struct intel_connector *intel_connector_alloc(void) | |
6484 | { | |
6485 | struct intel_connector *connector; | |
6486 | ||
6487 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6488 | if (!connector) | |
6489 | return NULL; | |
6490 | ||
6491 | if (intel_connector_init(connector) < 0) { | |
6492 | kfree(connector); | |
6493 | return NULL; | |
6494 | } | |
6495 | ||
6496 | return connector; | |
6497 | } | |
6498 | ||
f0947c37 DV |
6499 | /* Simple connector->get_hw_state implementation for encoders that support only |
6500 | * one connector and no cloning and hence the encoder state determines the state | |
6501 | * of the connector. */ | |
6502 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6503 | { |
24929352 | 6504 | enum pipe pipe = 0; |
f0947c37 | 6505 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6506 | |
f0947c37 | 6507 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6508 | } |
6509 | ||
6d293983 | 6510 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6511 | { |
6d293983 ACO |
6512 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6513 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6514 | |
6515 | return 0; | |
6516 | } | |
6517 | ||
6d293983 | 6518 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6519 | struct intel_crtc_state *pipe_config) |
1857e1da | 6520 | { |
6d293983 ACO |
6521 | struct drm_atomic_state *state = pipe_config->base.state; |
6522 | struct intel_crtc *other_crtc; | |
6523 | struct intel_crtc_state *other_crtc_state; | |
6524 | ||
1857e1da DV |
6525 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6526 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6527 | if (pipe_config->fdi_lanes > 4) { | |
6528 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6529 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6530 | return -EINVAL; |
1857e1da DV |
6531 | } |
6532 | ||
bafb6553 | 6533 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6534 | if (pipe_config->fdi_lanes > 2) { |
6535 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6536 | pipe_config->fdi_lanes); | |
6d293983 | 6537 | return -EINVAL; |
1857e1da | 6538 | } else { |
6d293983 | 6539 | return 0; |
1857e1da DV |
6540 | } |
6541 | } | |
6542 | ||
6543 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6544 | return 0; |
1857e1da DV |
6545 | |
6546 | /* Ivybridge 3 pipe is really complicated */ | |
6547 | switch (pipe) { | |
6548 | case PIPE_A: | |
6d293983 | 6549 | return 0; |
1857e1da | 6550 | case PIPE_B: |
6d293983 ACO |
6551 | if (pipe_config->fdi_lanes <= 2) |
6552 | return 0; | |
6553 | ||
6554 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6555 | other_crtc_state = | |
6556 | intel_atomic_get_crtc_state(state, other_crtc); | |
6557 | if (IS_ERR(other_crtc_state)) | |
6558 | return PTR_ERR(other_crtc_state); | |
6559 | ||
6560 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6561 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6562 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6563 | return -EINVAL; |
1857e1da | 6564 | } |
6d293983 | 6565 | return 0; |
1857e1da | 6566 | case PIPE_C: |
251cc67c VS |
6567 | if (pipe_config->fdi_lanes > 2) { |
6568 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6569 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6570 | return -EINVAL; |
251cc67c | 6571 | } |
6d293983 ACO |
6572 | |
6573 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6574 | other_crtc_state = | |
6575 | intel_atomic_get_crtc_state(state, other_crtc); | |
6576 | if (IS_ERR(other_crtc_state)) | |
6577 | return PTR_ERR(other_crtc_state); | |
6578 | ||
6579 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6580 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6581 | return -EINVAL; |
1857e1da | 6582 | } |
6d293983 | 6583 | return 0; |
1857e1da DV |
6584 | default: |
6585 | BUG(); | |
6586 | } | |
6587 | } | |
6588 | ||
e29c22c0 DV |
6589 | #define RETRY 1 |
6590 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6591 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6592 | { |
1857e1da | 6593 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6594 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6595 | int lane, link_bw, fdi_dotclock, ret; |
6596 | bool needs_recompute = false; | |
877d48d5 | 6597 | |
e29c22c0 | 6598 | retry: |
877d48d5 DV |
6599 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6600 | * each output octet as 10 bits. The actual frequency | |
6601 | * is stored as a divider into a 100MHz clock, and the | |
6602 | * mode pixel clock is stored in units of 1KHz. | |
6603 | * Hence the bw of each lane in terms of the mode signal | |
6604 | * is: | |
6605 | */ | |
6606 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6607 | ||
241bfc38 | 6608 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6609 | |
2bd89a07 | 6610 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6611 | pipe_config->pipe_bpp); |
6612 | ||
6613 | pipe_config->fdi_lanes = lane; | |
6614 | ||
2bd89a07 | 6615 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6616 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6617 | |
6d293983 ACO |
6618 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6619 | intel_crtc->pipe, pipe_config); | |
6620 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6621 | pipe_config->pipe_bpp -= 2*3; |
6622 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6623 | pipe_config->pipe_bpp); | |
6624 | needs_recompute = true; | |
6625 | pipe_config->bw_constrained = true; | |
6626 | ||
6627 | goto retry; | |
6628 | } | |
6629 | ||
6630 | if (needs_recompute) | |
6631 | return RETRY; | |
6632 | ||
6d293983 | 6633 | return ret; |
877d48d5 DV |
6634 | } |
6635 | ||
8cfb3407 VS |
6636 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6637 | struct intel_crtc_state *pipe_config) | |
6638 | { | |
6639 | if (pipe_config->pipe_bpp > 24) | |
6640 | return false; | |
6641 | ||
6642 | /* HSW can handle pixel rate up to cdclk? */ | |
6643 | if (IS_HASWELL(dev_priv->dev)) | |
6644 | return true; | |
6645 | ||
6646 | /* | |
b432e5cf VS |
6647 | * We compare against max which means we must take |
6648 | * the increased cdclk requirement into account when | |
6649 | * calculating the new cdclk. | |
6650 | * | |
6651 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6652 | */ |
6653 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6654 | dev_priv->max_cdclk_freq * 95 / 100; | |
6655 | } | |
6656 | ||
42db64ef | 6657 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6658 | struct intel_crtc_state *pipe_config) |
42db64ef | 6659 | { |
8cfb3407 VS |
6660 | struct drm_device *dev = crtc->base.dev; |
6661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6662 | ||
d330a953 | 6663 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6664 | hsw_crtc_supports_ips(crtc) && |
6665 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6666 | } |
6667 | ||
39acb4aa VS |
6668 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6669 | { | |
6670 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6671 | ||
6672 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6673 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6674 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6675 | } | |
6676 | ||
a43f6e0f | 6677 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6678 | struct intel_crtc_state *pipe_config) |
79e53945 | 6679 | { |
a43f6e0f | 6680 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6681 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6682 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6683 | |
ad3a4479 | 6684 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6685 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6686 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6687 | |
6688 | /* | |
39acb4aa | 6689 | * Enable double wide mode when the dot clock |
cf532bb2 | 6690 | * is > 90% of the (display) core speed. |
cf532bb2 | 6691 | */ |
39acb4aa VS |
6692 | if (intel_crtc_supports_double_wide(crtc) && |
6693 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6694 | clock_limit *= 2; |
cf532bb2 | 6695 | pipe_config->double_wide = true; |
ad3a4479 VS |
6696 | } |
6697 | ||
39acb4aa VS |
6698 | if (adjusted_mode->crtc_clock > clock_limit) { |
6699 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6700 | adjusted_mode->crtc_clock, clock_limit, | |
6701 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6702 | return -EINVAL; |
39acb4aa | 6703 | } |
2c07245f | 6704 | } |
89749350 | 6705 | |
1d1d0e27 VS |
6706 | /* |
6707 | * Pipe horizontal size must be even in: | |
6708 | * - DVO ganged mode | |
6709 | * - LVDS dual channel mode | |
6710 | * - Double wide pipe | |
6711 | */ | |
a93e255f | 6712 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6713 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6714 | pipe_config->pipe_src_w &= ~1; | |
6715 | ||
8693a824 DL |
6716 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6717 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6718 | */ |
6719 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6720 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6721 | return -EINVAL; |
44f46b42 | 6722 | |
f5adf94e | 6723 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6724 | hsw_compute_ips_config(crtc, pipe_config); |
6725 | ||
877d48d5 | 6726 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6727 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6728 | |
cf5a15be | 6729 | return 0; |
79e53945 JB |
6730 | } |
6731 | ||
1652d19e VS |
6732 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6733 | { | |
6734 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6735 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6736 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6737 | uint32_t linkrate; | |
6738 | ||
414355a7 | 6739 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6740 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6741 | |
6742 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6743 | return 540000; | |
6744 | ||
6745 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6746 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6747 | |
71cd8423 DL |
6748 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6749 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6750 | /* vco 8640 */ |
6751 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6752 | case CDCLK_FREQ_450_432: | |
6753 | return 432000; | |
6754 | case CDCLK_FREQ_337_308: | |
6755 | return 308570; | |
6756 | case CDCLK_FREQ_675_617: | |
6757 | return 617140; | |
6758 | default: | |
6759 | WARN(1, "Unknown cd freq selection\n"); | |
6760 | } | |
6761 | } else { | |
6762 | /* vco 8100 */ | |
6763 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6764 | case CDCLK_FREQ_450_432: | |
6765 | return 450000; | |
6766 | case CDCLK_FREQ_337_308: | |
6767 | return 337500; | |
6768 | case CDCLK_FREQ_675_617: | |
6769 | return 675000; | |
6770 | default: | |
6771 | WARN(1, "Unknown cd freq selection\n"); | |
6772 | } | |
6773 | } | |
6774 | ||
6775 | /* error case, do as if DPLL0 isn't enabled */ | |
6776 | return 24000; | |
6777 | } | |
6778 | ||
acd3f3d3 BP |
6779 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6780 | { | |
6781 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6782 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6783 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6784 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6785 | int cdclk; | |
6786 | ||
6787 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6788 | return 19200; | |
6789 | ||
6790 | cdclk = 19200 * pll_ratio / 2; | |
6791 | ||
6792 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6793 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6794 | return cdclk; /* 576MHz or 624MHz */ | |
6795 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6796 | return cdclk * 2 / 3; /* 384MHz */ | |
6797 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6798 | return cdclk / 2; /* 288MHz */ | |
6799 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6800 | return cdclk / 4; /* 144MHz */ | |
6801 | } | |
6802 | ||
6803 | /* error case, do as if DE PLL isn't enabled */ | |
6804 | return 19200; | |
6805 | } | |
6806 | ||
1652d19e VS |
6807 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6808 | { | |
6809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6810 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6811 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6812 | ||
6813 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6814 | return 800000; | |
6815 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6816 | return 450000; | |
6817 | else if (freq == LCPLL_CLK_FREQ_450) | |
6818 | return 450000; | |
6819 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6820 | return 540000; | |
6821 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6822 | return 337500; | |
6823 | else | |
6824 | return 675000; | |
6825 | } | |
6826 | ||
6827 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6828 | { | |
6829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6830 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6831 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6832 | ||
6833 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6834 | return 800000; | |
6835 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6836 | return 450000; | |
6837 | else if (freq == LCPLL_CLK_FREQ_450) | |
6838 | return 450000; | |
6839 | else if (IS_HSW_ULT(dev)) | |
6840 | return 337500; | |
6841 | else | |
6842 | return 540000; | |
79e53945 JB |
6843 | } |
6844 | ||
25eb05fc JB |
6845 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6846 | { | |
bfa7df01 VS |
6847 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6848 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6849 | } |
6850 | ||
b37a6434 VS |
6851 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6852 | { | |
6853 | return 450000; | |
6854 | } | |
6855 | ||
e70236a8 JB |
6856 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6857 | { | |
6858 | return 400000; | |
6859 | } | |
79e53945 | 6860 | |
e70236a8 | 6861 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6862 | { |
e907f170 | 6863 | return 333333; |
e70236a8 | 6864 | } |
79e53945 | 6865 | |
e70236a8 JB |
6866 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6867 | { | |
6868 | return 200000; | |
6869 | } | |
79e53945 | 6870 | |
257a7ffc DV |
6871 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6872 | { | |
6873 | u16 gcfgc = 0; | |
6874 | ||
6875 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6876 | ||
6877 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6878 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6879 | return 266667; |
257a7ffc | 6880 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6881 | return 333333; |
257a7ffc | 6882 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6883 | return 444444; |
257a7ffc DV |
6884 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6885 | return 200000; | |
6886 | default: | |
6887 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6888 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6889 | return 133333; |
257a7ffc | 6890 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6891 | return 166667; |
257a7ffc DV |
6892 | } |
6893 | } | |
6894 | ||
e70236a8 JB |
6895 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6896 | { | |
6897 | u16 gcfgc = 0; | |
79e53945 | 6898 | |
e70236a8 JB |
6899 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6900 | ||
6901 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6902 | return 133333; |
e70236a8 JB |
6903 | else { |
6904 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6905 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6906 | return 333333; |
e70236a8 JB |
6907 | default: |
6908 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6909 | return 190000; | |
79e53945 | 6910 | } |
e70236a8 JB |
6911 | } |
6912 | } | |
6913 | ||
6914 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6915 | { | |
e907f170 | 6916 | return 266667; |
e70236a8 JB |
6917 | } |
6918 | ||
1b1d2716 | 6919 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6920 | { |
6921 | u16 hpllcc = 0; | |
1b1d2716 | 6922 | |
65cd2b3f VS |
6923 | /* |
6924 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6925 | * encoding is different :( | |
6926 | * FIXME is this the right way to detect 852GM/852GMV? | |
6927 | */ | |
6928 | if (dev->pdev->revision == 0x1) | |
6929 | return 133333; | |
6930 | ||
1b1d2716 VS |
6931 | pci_bus_read_config_word(dev->pdev->bus, |
6932 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6933 | ||
e70236a8 JB |
6934 | /* Assume that the hardware is in the high speed state. This |
6935 | * should be the default. | |
6936 | */ | |
6937 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6938 | case GC_CLOCK_133_200: | |
1b1d2716 | 6939 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6940 | case GC_CLOCK_100_200: |
6941 | return 200000; | |
6942 | case GC_CLOCK_166_250: | |
6943 | return 250000; | |
6944 | case GC_CLOCK_100_133: | |
e907f170 | 6945 | return 133333; |
1b1d2716 VS |
6946 | case GC_CLOCK_133_266: |
6947 | case GC_CLOCK_133_266_2: | |
6948 | case GC_CLOCK_166_266: | |
6949 | return 266667; | |
e70236a8 | 6950 | } |
79e53945 | 6951 | |
e70236a8 JB |
6952 | /* Shouldn't happen */ |
6953 | return 0; | |
6954 | } | |
79e53945 | 6955 | |
e70236a8 JB |
6956 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6957 | { | |
e907f170 | 6958 | return 133333; |
79e53945 JB |
6959 | } |
6960 | ||
34edce2f VS |
6961 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6962 | { | |
6963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6964 | static const unsigned int blb_vco[8] = { | |
6965 | [0] = 3200000, | |
6966 | [1] = 4000000, | |
6967 | [2] = 5333333, | |
6968 | [3] = 4800000, | |
6969 | [4] = 6400000, | |
6970 | }; | |
6971 | static const unsigned int pnv_vco[8] = { | |
6972 | [0] = 3200000, | |
6973 | [1] = 4000000, | |
6974 | [2] = 5333333, | |
6975 | [3] = 4800000, | |
6976 | [4] = 2666667, | |
6977 | }; | |
6978 | static const unsigned int cl_vco[8] = { | |
6979 | [0] = 3200000, | |
6980 | [1] = 4000000, | |
6981 | [2] = 5333333, | |
6982 | [3] = 6400000, | |
6983 | [4] = 3333333, | |
6984 | [5] = 3566667, | |
6985 | [6] = 4266667, | |
6986 | }; | |
6987 | static const unsigned int elk_vco[8] = { | |
6988 | [0] = 3200000, | |
6989 | [1] = 4000000, | |
6990 | [2] = 5333333, | |
6991 | [3] = 4800000, | |
6992 | }; | |
6993 | static const unsigned int ctg_vco[8] = { | |
6994 | [0] = 3200000, | |
6995 | [1] = 4000000, | |
6996 | [2] = 5333333, | |
6997 | [3] = 6400000, | |
6998 | [4] = 2666667, | |
6999 | [5] = 4266667, | |
7000 | }; | |
7001 | const unsigned int *vco_table; | |
7002 | unsigned int vco; | |
7003 | uint8_t tmp = 0; | |
7004 | ||
7005 | /* FIXME other chipsets? */ | |
7006 | if (IS_GM45(dev)) | |
7007 | vco_table = ctg_vco; | |
7008 | else if (IS_G4X(dev)) | |
7009 | vco_table = elk_vco; | |
7010 | else if (IS_CRESTLINE(dev)) | |
7011 | vco_table = cl_vco; | |
7012 | else if (IS_PINEVIEW(dev)) | |
7013 | vco_table = pnv_vco; | |
7014 | else if (IS_G33(dev)) | |
7015 | vco_table = blb_vco; | |
7016 | else | |
7017 | return 0; | |
7018 | ||
7019 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7020 | ||
7021 | vco = vco_table[tmp & 0x7]; | |
7022 | if (vco == 0) | |
7023 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7024 | else | |
7025 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7026 | ||
7027 | return vco; | |
7028 | } | |
7029 | ||
7030 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7031 | { | |
7032 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7033 | uint16_t tmp = 0; | |
7034 | ||
7035 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7036 | ||
7037 | cdclk_sel = (tmp >> 12) & 0x1; | |
7038 | ||
7039 | switch (vco) { | |
7040 | case 2666667: | |
7041 | case 4000000: | |
7042 | case 5333333: | |
7043 | return cdclk_sel ? 333333 : 222222; | |
7044 | case 3200000: | |
7045 | return cdclk_sel ? 320000 : 228571; | |
7046 | default: | |
7047 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7048 | return 222222; | |
7049 | } | |
7050 | } | |
7051 | ||
7052 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7053 | { | |
7054 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7055 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7056 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7057 | const uint8_t *div_table; | |
7058 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7059 | uint16_t tmp = 0; | |
7060 | ||
7061 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7062 | ||
7063 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7064 | ||
7065 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7066 | goto fail; | |
7067 | ||
7068 | switch (vco) { | |
7069 | case 3200000: | |
7070 | div_table = div_3200; | |
7071 | break; | |
7072 | case 4000000: | |
7073 | div_table = div_4000; | |
7074 | break; | |
7075 | case 5333333: | |
7076 | div_table = div_5333; | |
7077 | break; | |
7078 | default: | |
7079 | goto fail; | |
7080 | } | |
7081 | ||
7082 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7083 | ||
caf4e252 | 7084 | fail: |
34edce2f VS |
7085 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7086 | return 200000; | |
7087 | } | |
7088 | ||
7089 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7090 | { | |
7091 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7092 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7093 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7094 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7095 | const uint8_t *div_table; | |
7096 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7097 | uint16_t tmp = 0; | |
7098 | ||
7099 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7100 | ||
7101 | cdclk_sel = (tmp >> 4) & 0x7; | |
7102 | ||
7103 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7104 | goto fail; | |
7105 | ||
7106 | switch (vco) { | |
7107 | case 3200000: | |
7108 | div_table = div_3200; | |
7109 | break; | |
7110 | case 4000000: | |
7111 | div_table = div_4000; | |
7112 | break; | |
7113 | case 4800000: | |
7114 | div_table = div_4800; | |
7115 | break; | |
7116 | case 5333333: | |
7117 | div_table = div_5333; | |
7118 | break; | |
7119 | default: | |
7120 | goto fail; | |
7121 | } | |
7122 | ||
7123 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7124 | ||
caf4e252 | 7125 | fail: |
34edce2f VS |
7126 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7127 | return 190476; | |
7128 | } | |
7129 | ||
2c07245f | 7130 | static void |
a65851af | 7131 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7132 | { |
a65851af VS |
7133 | while (*num > DATA_LINK_M_N_MASK || |
7134 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7135 | *num >>= 1; |
7136 | *den >>= 1; | |
7137 | } | |
7138 | } | |
7139 | ||
a65851af VS |
7140 | static void compute_m_n(unsigned int m, unsigned int n, |
7141 | uint32_t *ret_m, uint32_t *ret_n) | |
7142 | { | |
7143 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7144 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7145 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7146 | } | |
7147 | ||
e69d0bc1 DV |
7148 | void |
7149 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7150 | int pixel_clock, int link_clock, | |
7151 | struct intel_link_m_n *m_n) | |
2c07245f | 7152 | { |
e69d0bc1 | 7153 | m_n->tu = 64; |
a65851af VS |
7154 | |
7155 | compute_m_n(bits_per_pixel * pixel_clock, | |
7156 | link_clock * nlanes * 8, | |
7157 | &m_n->gmch_m, &m_n->gmch_n); | |
7158 | ||
7159 | compute_m_n(pixel_clock, link_clock, | |
7160 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7161 | } |
7162 | ||
a7615030 CW |
7163 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7164 | { | |
d330a953 JN |
7165 | if (i915.panel_use_ssc >= 0) |
7166 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7167 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7168 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7169 | } |
7170 | ||
a93e255f ACO |
7171 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7172 | int num_connectors) | |
c65d77d8 | 7173 | { |
a93e255f | 7174 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7175 | struct drm_i915_private *dev_priv = dev->dev_private; |
7176 | int refclk; | |
7177 | ||
a93e255f ACO |
7178 | WARN_ON(!crtc_state->base.state); |
7179 | ||
666a4537 | 7180 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7181 | refclk = 100000; |
a93e255f | 7182 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7183 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7184 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7185 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7186 | } else if (!IS_GEN2(dev)) { |
7187 | refclk = 96000; | |
7188 | } else { | |
7189 | refclk = 48000; | |
7190 | } | |
7191 | ||
7192 | return refclk; | |
7193 | } | |
7194 | ||
7429e9d4 | 7195 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7196 | { |
7df00d7a | 7197 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7198 | } |
f47709a9 | 7199 | |
7429e9d4 DV |
7200 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7201 | { | |
7202 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7203 | } |
7204 | ||
f47709a9 | 7205 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7206 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7207 | intel_clock_t *reduced_clock) |
7208 | { | |
f47709a9 | 7209 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7210 | u32 fp, fp2 = 0; |
7211 | ||
7212 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7213 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7214 | if (reduced_clock) |
7429e9d4 | 7215 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7216 | } else { |
190f68c5 | 7217 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7218 | if (reduced_clock) |
7429e9d4 | 7219 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7220 | } |
7221 | ||
190f68c5 | 7222 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7223 | |
f47709a9 | 7224 | crtc->lowfreq_avail = false; |
a93e255f | 7225 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7226 | reduced_clock) { |
190f68c5 | 7227 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7228 | crtc->lowfreq_avail = true; |
a7516a05 | 7229 | } else { |
190f68c5 | 7230 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7231 | } |
7232 | } | |
7233 | ||
5e69f97f CML |
7234 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7235 | pipe) | |
89b667f8 JB |
7236 | { |
7237 | u32 reg_val; | |
7238 | ||
7239 | /* | |
7240 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7241 | * and set it to a reasonable value instead. | |
7242 | */ | |
ab3c759a | 7243 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7244 | reg_val &= 0xffffff00; |
7245 | reg_val |= 0x00000030; | |
ab3c759a | 7246 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7247 | |
ab3c759a | 7248 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7249 | reg_val &= 0x8cffffff; |
7250 | reg_val = 0x8c000000; | |
ab3c759a | 7251 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7252 | |
ab3c759a | 7253 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7254 | reg_val &= 0xffffff00; |
ab3c759a | 7255 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7256 | |
ab3c759a | 7257 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7258 | reg_val &= 0x00ffffff; |
7259 | reg_val |= 0xb0000000; | |
ab3c759a | 7260 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7261 | } |
7262 | ||
b551842d DV |
7263 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7264 | struct intel_link_m_n *m_n) | |
7265 | { | |
7266 | struct drm_device *dev = crtc->base.dev; | |
7267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7268 | int pipe = crtc->pipe; | |
7269 | ||
e3b95f1e DV |
7270 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7271 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7272 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7273 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7274 | } |
7275 | ||
7276 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7277 | struct intel_link_m_n *m_n, |
7278 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7279 | { |
7280 | struct drm_device *dev = crtc->base.dev; | |
7281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7282 | int pipe = crtc->pipe; | |
6e3c9717 | 7283 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7284 | |
7285 | if (INTEL_INFO(dev)->gen >= 5) { | |
7286 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7287 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7288 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7289 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7290 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7291 | * for gen < 8) and if DRRS is supported (to make sure the | |
7292 | * registers are not unnecessarily accessed). | |
7293 | */ | |
44395bfe | 7294 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7295 | crtc->config->has_drrs) { |
f769cd24 VK |
7296 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7297 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7298 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7299 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7300 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7301 | } | |
b551842d | 7302 | } else { |
e3b95f1e DV |
7303 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7304 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7305 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7306 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7307 | } |
7308 | } | |
7309 | ||
fe3cd48d | 7310 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7311 | { |
fe3cd48d R |
7312 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7313 | ||
7314 | if (m_n == M1_N1) { | |
7315 | dp_m_n = &crtc->config->dp_m_n; | |
7316 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7317 | } else if (m_n == M2_N2) { | |
7318 | ||
7319 | /* | |
7320 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7321 | * needs to be programmed into M1_N1. | |
7322 | */ | |
7323 | dp_m_n = &crtc->config->dp_m2_n2; | |
7324 | } else { | |
7325 | DRM_ERROR("Unsupported divider value\n"); | |
7326 | return; | |
7327 | } | |
7328 | ||
6e3c9717 ACO |
7329 | if (crtc->config->has_pch_encoder) |
7330 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7331 | else |
fe3cd48d | 7332 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7333 | } |
7334 | ||
251ac862 DV |
7335 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7336 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7337 | { |
7338 | u32 dpll, dpll_md; | |
7339 | ||
7340 | /* | |
7341 | * Enable DPIO clock input. We should never disable the reference | |
7342 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7343 | * on it. | |
7344 | */ | |
60bfe44f VS |
7345 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7346 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7347 | /* We should never disable this, set it here for state tracking */ |
7348 | if (crtc->pipe == PIPE_B) | |
7349 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7350 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7351 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7352 | |
d288f65f | 7353 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7354 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7355 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7356 | } |
7357 | ||
d288f65f | 7358 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7359 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7360 | { |
f47709a9 | 7361 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7362 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7363 | int pipe = crtc->pipe; |
bdd4b6a6 | 7364 | u32 mdiv; |
a0c4da24 | 7365 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7366 | u32 coreclk, reg_val; |
a0c4da24 | 7367 | |
a580516d | 7368 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7369 | |
d288f65f VS |
7370 | bestn = pipe_config->dpll.n; |
7371 | bestm1 = pipe_config->dpll.m1; | |
7372 | bestm2 = pipe_config->dpll.m2; | |
7373 | bestp1 = pipe_config->dpll.p1; | |
7374 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7375 | |
89b667f8 JB |
7376 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7377 | ||
7378 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7379 | if (pipe == PIPE_B) |
5e69f97f | 7380 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7381 | |
7382 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7383 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7384 | |
7385 | /* Disable target IRef on PLL */ | |
ab3c759a | 7386 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7387 | reg_val &= 0x00ffffff; |
ab3c759a | 7388 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7389 | |
7390 | /* Disable fast lock */ | |
ab3c759a | 7391 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7392 | |
7393 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7394 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7395 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7396 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7397 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7398 | |
7399 | /* | |
7400 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7401 | * but we don't support that). | |
7402 | * Note: don't use the DAC post divider as it seems unstable. | |
7403 | */ | |
7404 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7405 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7406 | |
a0c4da24 | 7407 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7408 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7409 | |
89b667f8 | 7410 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7411 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7412 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7413 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7414 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7415 | 0x009f0003); |
89b667f8 | 7416 | else |
ab3c759a | 7417 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7418 | 0x00d0000f); |
7419 | ||
681a8504 | 7420 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7421 | /* Use SSC source */ |
bdd4b6a6 | 7422 | if (pipe == PIPE_A) |
ab3c759a | 7423 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7424 | 0x0df40000); |
7425 | else | |
ab3c759a | 7426 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7427 | 0x0df70000); |
7428 | } else { /* HDMI or VGA */ | |
7429 | /* Use bend source */ | |
bdd4b6a6 | 7430 | if (pipe == PIPE_A) |
ab3c759a | 7431 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7432 | 0x0df70000); |
7433 | else | |
ab3c759a | 7434 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7435 | 0x0df40000); |
7436 | } | |
a0c4da24 | 7437 | |
ab3c759a | 7438 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7439 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7440 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7441 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7442 | coreclk |= 0x01000000; |
ab3c759a | 7443 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7444 | |
ab3c759a | 7445 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7446 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7447 | } |
7448 | ||
251ac862 DV |
7449 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7450 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7451 | { |
60bfe44f VS |
7452 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7453 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7454 | DPLL_VCO_ENABLE; |
7455 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7456 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7457 | |
d288f65f VS |
7458 | pipe_config->dpll_hw_state.dpll_md = |
7459 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7460 | } |
7461 | ||
d288f65f | 7462 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7463 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7464 | { |
7465 | struct drm_device *dev = crtc->base.dev; | |
7466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7467 | int pipe = crtc->pipe; | |
f0f59a00 | 7468 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7469 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7470 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7471 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7472 | u32 dpio_val; |
9cbe40c1 | 7473 | int vco; |
9d556c99 | 7474 | |
d288f65f VS |
7475 | bestn = pipe_config->dpll.n; |
7476 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7477 | bestm1 = pipe_config->dpll.m1; | |
7478 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7479 | bestp1 = pipe_config->dpll.p1; | |
7480 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7481 | vco = pipe_config->dpll.vco; |
a945ce7e | 7482 | dpio_val = 0; |
9cbe40c1 | 7483 | loopfilter = 0; |
9d556c99 CML |
7484 | |
7485 | /* | |
7486 | * Enable Refclk and SSC | |
7487 | */ | |
a11b0703 | 7488 | I915_WRITE(dpll_reg, |
d288f65f | 7489 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7490 | |
a580516d | 7491 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7492 | |
9d556c99 CML |
7493 | /* p1 and p2 divider */ |
7494 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7495 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7496 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7497 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7498 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7499 | ||
7500 | /* Feedback post-divider - m2 */ | |
7501 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7502 | ||
7503 | /* Feedback refclk divider - n and m1 */ | |
7504 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7505 | DPIO_CHV_M1_DIV_BY_2 | | |
7506 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7507 | ||
7508 | /* M2 fraction division */ | |
25a25dfc | 7509 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7510 | |
7511 | /* M2 fraction division enable */ | |
a945ce7e VP |
7512 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7513 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7514 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7515 | if (bestm2_frac) | |
7516 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7517 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7518 | |
de3a0fde VP |
7519 | /* Program digital lock detect threshold */ |
7520 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7521 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7522 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7523 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7524 | if (!bestm2_frac) | |
7525 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7526 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7527 | ||
9d556c99 | 7528 | /* Loop filter */ |
9cbe40c1 VP |
7529 | if (vco == 5400000) { |
7530 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7531 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7532 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7533 | tribuf_calcntr = 0x9; | |
7534 | } else if (vco <= 6200000) { | |
7535 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7536 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7537 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7538 | tribuf_calcntr = 0x9; | |
7539 | } else if (vco <= 6480000) { | |
7540 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7541 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7542 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7543 | tribuf_calcntr = 0x8; | |
7544 | } else { | |
7545 | /* Not supported. Apply the same limits as in the max case */ | |
7546 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7547 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7548 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7549 | tribuf_calcntr = 0; | |
7550 | } | |
9d556c99 CML |
7551 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7552 | ||
968040b2 | 7553 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7554 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7555 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7556 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7557 | ||
9d556c99 CML |
7558 | /* AFC Recal */ |
7559 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7560 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7561 | DPIO_AFC_RECAL); | |
7562 | ||
a580516d | 7563 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7564 | } |
7565 | ||
d288f65f VS |
7566 | /** |
7567 | * vlv_force_pll_on - forcibly enable just the PLL | |
7568 | * @dev_priv: i915 private structure | |
7569 | * @pipe: pipe PLL to enable | |
7570 | * @dpll: PLL configuration | |
7571 | * | |
7572 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7573 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7574 | * be enabled. | |
7575 | */ | |
3f36b937 TU |
7576 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7577 | const struct dpll *dpll) | |
d288f65f VS |
7578 | { |
7579 | struct intel_crtc *crtc = | |
7580 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7581 | struct intel_crtc_state *pipe_config; |
7582 | ||
7583 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7584 | if (!pipe_config) | |
7585 | return -ENOMEM; | |
7586 | ||
7587 | pipe_config->base.crtc = &crtc->base; | |
7588 | pipe_config->pixel_multiplier = 1; | |
7589 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7590 | |
7591 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7592 | chv_compute_dpll(crtc, pipe_config); |
7593 | chv_prepare_pll(crtc, pipe_config); | |
7594 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7595 | } else { |
3f36b937 TU |
7596 | vlv_compute_dpll(crtc, pipe_config); |
7597 | vlv_prepare_pll(crtc, pipe_config); | |
7598 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7599 | } |
3f36b937 TU |
7600 | |
7601 | kfree(pipe_config); | |
7602 | ||
7603 | return 0; | |
d288f65f VS |
7604 | } |
7605 | ||
7606 | /** | |
7607 | * vlv_force_pll_off - forcibly disable just the PLL | |
7608 | * @dev_priv: i915 private structure | |
7609 | * @pipe: pipe PLL to disable | |
7610 | * | |
7611 | * Disable the PLL for @pipe. To be used in cases where we need | |
7612 | * the PLL enabled even when @pipe is not going to be enabled. | |
7613 | */ | |
7614 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7615 | { | |
7616 | if (IS_CHERRYVIEW(dev)) | |
7617 | chv_disable_pll(to_i915(dev), pipe); | |
7618 | else | |
7619 | vlv_disable_pll(to_i915(dev), pipe); | |
7620 | } | |
7621 | ||
251ac862 DV |
7622 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7623 | struct intel_crtc_state *crtc_state, | |
7624 | intel_clock_t *reduced_clock, | |
7625 | int num_connectors) | |
eb1cbe48 | 7626 | { |
f47709a9 | 7627 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7628 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7629 | u32 dpll; |
7630 | bool is_sdvo; | |
190f68c5 | 7631 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7632 | |
190f68c5 | 7633 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7634 | |
a93e255f ACO |
7635 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7636 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7637 | |
7638 | dpll = DPLL_VGA_MODE_DIS; | |
7639 | ||
a93e255f | 7640 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7641 | dpll |= DPLLB_MODE_LVDS; |
7642 | else | |
7643 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7644 | |
ef1b460d | 7645 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7646 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7647 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7648 | } |
198a037f DV |
7649 | |
7650 | if (is_sdvo) | |
4a33e48d | 7651 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7652 | |
190f68c5 | 7653 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7654 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7655 | |
7656 | /* compute bitmask from p1 value */ | |
7657 | if (IS_PINEVIEW(dev)) | |
7658 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7659 | else { | |
7660 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7661 | if (IS_G4X(dev) && reduced_clock) | |
7662 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7663 | } | |
7664 | switch (clock->p2) { | |
7665 | case 5: | |
7666 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7667 | break; | |
7668 | case 7: | |
7669 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7670 | break; | |
7671 | case 10: | |
7672 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7673 | break; | |
7674 | case 14: | |
7675 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7676 | break; | |
7677 | } | |
7678 | if (INTEL_INFO(dev)->gen >= 4) | |
7679 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7680 | ||
190f68c5 | 7681 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7682 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7683 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7684 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7685 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7686 | else | |
7687 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7688 | ||
7689 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7690 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7691 | |
eb1cbe48 | 7692 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7693 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7694 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7695 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7696 | } |
7697 | } | |
7698 | ||
251ac862 DV |
7699 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7700 | struct intel_crtc_state *crtc_state, | |
7701 | intel_clock_t *reduced_clock, | |
7702 | int num_connectors) | |
eb1cbe48 | 7703 | { |
f47709a9 | 7704 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7705 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7706 | u32 dpll; |
190f68c5 | 7707 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7708 | |
190f68c5 | 7709 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7710 | |
eb1cbe48 DV |
7711 | dpll = DPLL_VGA_MODE_DIS; |
7712 | ||
a93e255f | 7713 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7714 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7715 | } else { | |
7716 | if (clock->p1 == 2) | |
7717 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7718 | else | |
7719 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7720 | if (clock->p2 == 4) | |
7721 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7722 | } | |
7723 | ||
a93e255f | 7724 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7725 | dpll |= DPLL_DVO_2X_MODE; |
7726 | ||
a93e255f | 7727 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7728 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7729 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7730 | else | |
7731 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7732 | ||
7733 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7734 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7735 | } |
7736 | ||
8a654f3b | 7737 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7738 | { |
7739 | struct drm_device *dev = intel_crtc->base.dev; | |
7740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7741 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7742 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7743 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7744 | uint32_t crtc_vtotal, crtc_vblank_end; |
7745 | int vsyncshift = 0; | |
4d8a62ea DV |
7746 | |
7747 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7748 | * the hw state checker will get angry at the mismatch. */ | |
7749 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7750 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7751 | |
609aeaca | 7752 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7753 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7754 | crtc_vtotal -= 1; |
7755 | crtc_vblank_end -= 1; | |
609aeaca | 7756 | |
409ee761 | 7757 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7758 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7759 | else | |
7760 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7761 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7762 | if (vsyncshift < 0) |
7763 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7764 | } |
7765 | ||
7766 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7767 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7768 | |
fe2b8f9d | 7769 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7770 | (adjusted_mode->crtc_hdisplay - 1) | |
7771 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7772 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7773 | (adjusted_mode->crtc_hblank_start - 1) | |
7774 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7775 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7776 | (adjusted_mode->crtc_hsync_start - 1) | |
7777 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7778 | ||
fe2b8f9d | 7779 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7780 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7781 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7782 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7783 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7784 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7785 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7786 | (adjusted_mode->crtc_vsync_start - 1) | |
7787 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7788 | ||
b5e508d4 PZ |
7789 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7790 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7791 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7792 | * bits. */ | |
7793 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7794 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7795 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7796 | ||
b0e77b9c PZ |
7797 | /* pipesrc controls the size that is scaled from, which should |
7798 | * always be the user's requested size. | |
7799 | */ | |
7800 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7801 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7802 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7803 | } |
7804 | ||
1bd1bd80 | 7805 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7806 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7807 | { |
7808 | struct drm_device *dev = crtc->base.dev; | |
7809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7810 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7811 | uint32_t tmp; | |
7812 | ||
7813 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7814 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7815 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7816 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7817 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7818 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7819 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7820 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7821 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7822 | |
7823 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7824 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7825 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7826 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7827 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7828 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7829 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7830 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7831 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7832 | |
7833 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7834 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7835 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7836 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7837 | } |
7838 | ||
7839 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7840 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7841 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7842 | ||
2d112de7 ACO |
7843 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7844 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7845 | } |
7846 | ||
f6a83288 | 7847 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7848 | struct intel_crtc_state *pipe_config) |
babea61d | 7849 | { |
2d112de7 ACO |
7850 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7851 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7852 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7853 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7854 | |
2d112de7 ACO |
7855 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7856 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7857 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7858 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7859 | |
2d112de7 | 7860 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7861 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7862 | |
2d112de7 ACO |
7863 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7864 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7865 | |
7866 | mode->hsync = drm_mode_hsync(mode); | |
7867 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7868 | drm_mode_set_name(mode); | |
babea61d JB |
7869 | } |
7870 | ||
84b046f3 DV |
7871 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7872 | { | |
7873 | struct drm_device *dev = intel_crtc->base.dev; | |
7874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7875 | uint32_t pipeconf; | |
7876 | ||
9f11a9e4 | 7877 | pipeconf = 0; |
84b046f3 | 7878 | |
b6b5d049 VS |
7879 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7880 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7881 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7882 | |
6e3c9717 | 7883 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7884 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7885 | |
ff9ce46e | 7886 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7887 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7888 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7889 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7890 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7891 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7892 | |
6e3c9717 | 7893 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7894 | case 18: |
7895 | pipeconf |= PIPECONF_6BPC; | |
7896 | break; | |
7897 | case 24: | |
7898 | pipeconf |= PIPECONF_8BPC; | |
7899 | break; | |
7900 | case 30: | |
7901 | pipeconf |= PIPECONF_10BPC; | |
7902 | break; | |
7903 | default: | |
7904 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7905 | BUG(); | |
84b046f3 DV |
7906 | } |
7907 | } | |
7908 | ||
7909 | if (HAS_PIPE_CXSR(dev)) { | |
7910 | if (intel_crtc->lowfreq_avail) { | |
7911 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7912 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7913 | } else { | |
7914 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7915 | } |
7916 | } | |
7917 | ||
6e3c9717 | 7918 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7919 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7920 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7921 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7922 | else | |
7923 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7924 | } else | |
84b046f3 DV |
7925 | pipeconf |= PIPECONF_PROGRESSIVE; |
7926 | ||
666a4537 WB |
7927 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7928 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7929 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7930 | |
84b046f3 DV |
7931 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7932 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7933 | } | |
7934 | ||
190f68c5 ACO |
7935 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7936 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7937 | { |
c7653199 | 7938 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7939 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7940 | int refclk, num_connectors = 0; |
c329a4ec DV |
7941 | intel_clock_t clock; |
7942 | bool ok; | |
d4906093 | 7943 | const intel_limit_t *limit; |
55bb9992 | 7944 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7945 | struct drm_connector *connector; |
55bb9992 ACO |
7946 | struct drm_connector_state *connector_state; |
7947 | int i; | |
79e53945 | 7948 | |
dd3cd74a ACO |
7949 | memset(&crtc_state->dpll_hw_state, 0, |
7950 | sizeof(crtc_state->dpll_hw_state)); | |
7951 | ||
a65347ba JN |
7952 | if (crtc_state->has_dsi_encoder) |
7953 | return 0; | |
43565a06 | 7954 | |
a65347ba JN |
7955 | for_each_connector_in_state(state, connector, connector_state, i) { |
7956 | if (connector_state->crtc == &crtc->base) | |
7957 | num_connectors++; | |
79e53945 JB |
7958 | } |
7959 | ||
190f68c5 | 7960 | if (!crtc_state->clock_set) { |
a93e255f | 7961 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7962 | |
e9fd1c02 JN |
7963 | /* |
7964 | * Returns a set of divisors for the desired target clock with | |
7965 | * the given refclk, or FALSE. The returned values represent | |
7966 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7967 | * 2) / p1 / p2. | |
7968 | */ | |
a93e255f ACO |
7969 | limit = intel_limit(crtc_state, refclk); |
7970 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7971 | crtc_state->port_clock, |
e9fd1c02 | 7972 | refclk, NULL, &clock); |
f2335330 | 7973 | if (!ok) { |
e9fd1c02 JN |
7974 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7975 | return -EINVAL; | |
7976 | } | |
79e53945 | 7977 | |
f2335330 | 7978 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7979 | crtc_state->dpll.n = clock.n; |
7980 | crtc_state->dpll.m1 = clock.m1; | |
7981 | crtc_state->dpll.m2 = clock.m2; | |
7982 | crtc_state->dpll.p1 = clock.p1; | |
7983 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7984 | } |
7026d4ac | 7985 | |
e9fd1c02 | 7986 | if (IS_GEN2(dev)) { |
c329a4ec | 7987 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7988 | num_connectors); |
9d556c99 | 7989 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7990 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7991 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7992 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7993 | } else { |
c329a4ec | 7994 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7995 | num_connectors); |
e9fd1c02 | 7996 | } |
79e53945 | 7997 | |
c8f7a0db | 7998 | return 0; |
f564048e EA |
7999 | } |
8000 | ||
2fa2fe9a | 8001 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8002 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8003 | { |
8004 | struct drm_device *dev = crtc->base.dev; | |
8005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8006 | uint32_t tmp; | |
8007 | ||
dc9e7dec VS |
8008 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8009 | return; | |
8010 | ||
2fa2fe9a | 8011 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8012 | if (!(tmp & PFIT_ENABLE)) |
8013 | return; | |
2fa2fe9a | 8014 | |
06922821 | 8015 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8016 | if (INTEL_INFO(dev)->gen < 4) { |
8017 | if (crtc->pipe != PIPE_B) | |
8018 | return; | |
2fa2fe9a DV |
8019 | } else { |
8020 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8021 | return; | |
8022 | } | |
8023 | ||
06922821 | 8024 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8025 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8026 | if (INTEL_INFO(dev)->gen < 5) | |
8027 | pipe_config->gmch_pfit.lvds_border_bits = | |
8028 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8029 | } | |
8030 | ||
acbec814 | 8031 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8032 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8033 | { |
8034 | struct drm_device *dev = crtc->base.dev; | |
8035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8036 | int pipe = pipe_config->cpu_transcoder; | |
8037 | intel_clock_t clock; | |
8038 | u32 mdiv; | |
662c6ecb | 8039 | int refclk = 100000; |
acbec814 | 8040 | |
f573de5a SK |
8041 | /* In case of MIPI DPLL will not even be used */ |
8042 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8043 | return; | |
8044 | ||
a580516d | 8045 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8046 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8047 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8048 | |
8049 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8050 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8051 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8052 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8053 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8054 | ||
dccbea3b | 8055 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8056 | } |
8057 | ||
5724dbd1 DL |
8058 | static void |
8059 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8060 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8061 | { |
8062 | struct drm_device *dev = crtc->base.dev; | |
8063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8064 | u32 val, base, offset; | |
8065 | int pipe = crtc->pipe, plane = crtc->plane; | |
8066 | int fourcc, pixel_format; | |
6761dd31 | 8067 | unsigned int aligned_height; |
b113d5ee | 8068 | struct drm_framebuffer *fb; |
1b842c89 | 8069 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8070 | |
42a7b088 DL |
8071 | val = I915_READ(DSPCNTR(plane)); |
8072 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8073 | return; | |
8074 | ||
d9806c9f | 8075 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8076 | if (!intel_fb) { |
1ad292b5 JB |
8077 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8078 | return; | |
8079 | } | |
8080 | ||
1b842c89 DL |
8081 | fb = &intel_fb->base; |
8082 | ||
18c5247e DV |
8083 | if (INTEL_INFO(dev)->gen >= 4) { |
8084 | if (val & DISPPLANE_TILED) { | |
49af449b | 8085 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8086 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8087 | } | |
8088 | } | |
1ad292b5 JB |
8089 | |
8090 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8091 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8092 | fb->pixel_format = fourcc; |
8093 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8094 | |
8095 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8096 | if (plane_config->tiling) |
1ad292b5 JB |
8097 | offset = I915_READ(DSPTILEOFF(plane)); |
8098 | else | |
8099 | offset = I915_READ(DSPLINOFF(plane)); | |
8100 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8101 | } else { | |
8102 | base = I915_READ(DSPADDR(plane)); | |
8103 | } | |
8104 | plane_config->base = base; | |
8105 | ||
8106 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8107 | fb->width = ((val >> 16) & 0xfff) + 1; |
8108 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8109 | |
8110 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8111 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8112 | |
b113d5ee | 8113 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8114 | fb->pixel_format, |
8115 | fb->modifier[0]); | |
1ad292b5 | 8116 | |
f37b5c2b | 8117 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8118 | |
2844a921 DL |
8119 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8120 | pipe_name(pipe), plane, fb->width, fb->height, | |
8121 | fb->bits_per_pixel, base, fb->pitches[0], | |
8122 | plane_config->size); | |
1ad292b5 | 8123 | |
2d14030b | 8124 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8125 | } |
8126 | ||
70b23a98 | 8127 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8128 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8129 | { |
8130 | struct drm_device *dev = crtc->base.dev; | |
8131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8132 | int pipe = pipe_config->cpu_transcoder; | |
8133 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8134 | intel_clock_t clock; | |
0d7b6b11 | 8135 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8136 | int refclk = 100000; |
8137 | ||
a580516d | 8138 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8139 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8140 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8141 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8142 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8143 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8144 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8145 | |
8146 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8147 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8148 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8149 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8150 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8151 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8152 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8153 | ||
dccbea3b | 8154 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8155 | } |
8156 | ||
0e8ffe1b | 8157 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8158 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8159 | { |
8160 | struct drm_device *dev = crtc->base.dev; | |
8161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8162 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8163 | uint32_t tmp; |
1729050e | 8164 | bool ret; |
0e8ffe1b | 8165 | |
1729050e ID |
8166 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8167 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8168 | return false; |
8169 | ||
e143a21c | 8170 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8171 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8172 | |
1729050e ID |
8173 | ret = false; |
8174 | ||
0e8ffe1b DV |
8175 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8176 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8177 | goto out; |
0e8ffe1b | 8178 | |
666a4537 | 8179 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8180 | switch (tmp & PIPECONF_BPC_MASK) { |
8181 | case PIPECONF_6BPC: | |
8182 | pipe_config->pipe_bpp = 18; | |
8183 | break; | |
8184 | case PIPECONF_8BPC: | |
8185 | pipe_config->pipe_bpp = 24; | |
8186 | break; | |
8187 | case PIPECONF_10BPC: | |
8188 | pipe_config->pipe_bpp = 30; | |
8189 | break; | |
8190 | default: | |
8191 | break; | |
8192 | } | |
8193 | } | |
8194 | ||
666a4537 WB |
8195 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8196 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8197 | pipe_config->limited_color_range = true; |
8198 | ||
282740f7 VS |
8199 | if (INTEL_INFO(dev)->gen < 4) |
8200 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8201 | ||
1bd1bd80 DV |
8202 | intel_get_pipe_timings(crtc, pipe_config); |
8203 | ||
2fa2fe9a DV |
8204 | i9xx_get_pfit_config(crtc, pipe_config); |
8205 | ||
6c49f241 DV |
8206 | if (INTEL_INFO(dev)->gen >= 4) { |
8207 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8208 | pipe_config->pixel_multiplier = | |
8209 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8210 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8211 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8212 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8213 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8214 | pipe_config->pixel_multiplier = | |
8215 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8216 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8217 | } else { | |
8218 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8219 | * port and will be fixed up in the encoder->get_config | |
8220 | * function. */ | |
8221 | pipe_config->pixel_multiplier = 1; | |
8222 | } | |
8bcc2795 | 8223 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8224 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8225 | /* |
8226 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8227 | * on 830. Filter it out here so that we don't | |
8228 | * report errors due to that. | |
8229 | */ | |
8230 | if (IS_I830(dev)) | |
8231 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8232 | ||
8bcc2795 DV |
8233 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8234 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8235 | } else { |
8236 | /* Mask out read-only status bits. */ | |
8237 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8238 | DPLL_PORTC_READY_MASK | | |
8239 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8240 | } |
6c49f241 | 8241 | |
70b23a98 VS |
8242 | if (IS_CHERRYVIEW(dev)) |
8243 | chv_crtc_clock_get(crtc, pipe_config); | |
8244 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8245 | vlv_crtc_clock_get(crtc, pipe_config); |
8246 | else | |
8247 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8248 | |
0f64614d VS |
8249 | /* |
8250 | * Normally the dotclock is filled in by the encoder .get_config() | |
8251 | * but in case the pipe is enabled w/o any ports we need a sane | |
8252 | * default. | |
8253 | */ | |
8254 | pipe_config->base.adjusted_mode.crtc_clock = | |
8255 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8256 | ||
1729050e ID |
8257 | ret = true; |
8258 | ||
8259 | out: | |
8260 | intel_display_power_put(dev_priv, power_domain); | |
8261 | ||
8262 | return ret; | |
0e8ffe1b DV |
8263 | } |
8264 | ||
dde86e2d | 8265 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8266 | { |
8267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8268 | struct intel_encoder *encoder; |
74cfd7ac | 8269 | u32 val, final; |
13d83a67 | 8270 | bool has_lvds = false; |
199e5d79 | 8271 | bool has_cpu_edp = false; |
199e5d79 | 8272 | bool has_panel = false; |
99eb6a01 KP |
8273 | bool has_ck505 = false; |
8274 | bool can_ssc = false; | |
13d83a67 JB |
8275 | |
8276 | /* We need to take the global config into account */ | |
b2784e15 | 8277 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8278 | switch (encoder->type) { |
8279 | case INTEL_OUTPUT_LVDS: | |
8280 | has_panel = true; | |
8281 | has_lvds = true; | |
8282 | break; | |
8283 | case INTEL_OUTPUT_EDP: | |
8284 | has_panel = true; | |
2de6905f | 8285 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8286 | has_cpu_edp = true; |
8287 | break; | |
6847d71b PZ |
8288 | default: |
8289 | break; | |
13d83a67 JB |
8290 | } |
8291 | } | |
8292 | ||
99eb6a01 | 8293 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8294 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8295 | can_ssc = has_ck505; |
8296 | } else { | |
8297 | has_ck505 = false; | |
8298 | can_ssc = true; | |
8299 | } | |
8300 | ||
2de6905f ID |
8301 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8302 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8303 | |
8304 | /* Ironlake: try to setup display ref clock before DPLL | |
8305 | * enabling. This is only under driver's control after | |
8306 | * PCH B stepping, previous chipset stepping should be | |
8307 | * ignoring this setting. | |
8308 | */ | |
74cfd7ac CW |
8309 | val = I915_READ(PCH_DREF_CONTROL); |
8310 | ||
8311 | /* As we must carefully and slowly disable/enable each source in turn, | |
8312 | * compute the final state we want first and check if we need to | |
8313 | * make any changes at all. | |
8314 | */ | |
8315 | final = val; | |
8316 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8317 | if (has_ck505) | |
8318 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8319 | else | |
8320 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8321 | ||
8322 | final &= ~DREF_SSC_SOURCE_MASK; | |
8323 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8324 | final &= ~DREF_SSC1_ENABLE; | |
8325 | ||
8326 | if (has_panel) { | |
8327 | final |= DREF_SSC_SOURCE_ENABLE; | |
8328 | ||
8329 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8330 | final |= DREF_SSC1_ENABLE; | |
8331 | ||
8332 | if (has_cpu_edp) { | |
8333 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8334 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8335 | else | |
8336 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8337 | } else | |
8338 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8339 | } else { | |
8340 | final |= DREF_SSC_SOURCE_DISABLE; | |
8341 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8342 | } | |
8343 | ||
8344 | if (final == val) | |
8345 | return; | |
8346 | ||
13d83a67 | 8347 | /* Always enable nonspread source */ |
74cfd7ac | 8348 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8349 | |
99eb6a01 | 8350 | if (has_ck505) |
74cfd7ac | 8351 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8352 | else |
74cfd7ac | 8353 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8354 | |
199e5d79 | 8355 | if (has_panel) { |
74cfd7ac CW |
8356 | val &= ~DREF_SSC_SOURCE_MASK; |
8357 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8358 | |
199e5d79 | 8359 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8360 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8361 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8362 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8363 | } else |
74cfd7ac | 8364 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8365 | |
8366 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8367 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8368 | POSTING_READ(PCH_DREF_CONTROL); |
8369 | udelay(200); | |
8370 | ||
74cfd7ac | 8371 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8372 | |
8373 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8374 | if (has_cpu_edp) { |
99eb6a01 | 8375 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8376 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8377 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8378 | } else |
74cfd7ac | 8379 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8380 | } else |
74cfd7ac | 8381 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8382 | |
74cfd7ac | 8383 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8384 | POSTING_READ(PCH_DREF_CONTROL); |
8385 | udelay(200); | |
8386 | } else { | |
8387 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8388 | ||
74cfd7ac | 8389 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8390 | |
8391 | /* Turn off CPU output */ | |
74cfd7ac | 8392 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8393 | |
74cfd7ac | 8394 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8395 | POSTING_READ(PCH_DREF_CONTROL); |
8396 | udelay(200); | |
8397 | ||
8398 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8399 | val &= ~DREF_SSC_SOURCE_MASK; |
8400 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8401 | |
8402 | /* Turn off SSC1 */ | |
74cfd7ac | 8403 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8404 | |
74cfd7ac | 8405 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8406 | POSTING_READ(PCH_DREF_CONTROL); |
8407 | udelay(200); | |
8408 | } | |
74cfd7ac CW |
8409 | |
8410 | BUG_ON(val != final); | |
13d83a67 JB |
8411 | } |
8412 | ||
f31f2d55 | 8413 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8414 | { |
f31f2d55 | 8415 | uint32_t tmp; |
dde86e2d | 8416 | |
0ff066a9 PZ |
8417 | tmp = I915_READ(SOUTH_CHICKEN2); |
8418 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8419 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8420 | |
0ff066a9 PZ |
8421 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8422 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8423 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8424 | |
0ff066a9 PZ |
8425 | tmp = I915_READ(SOUTH_CHICKEN2); |
8426 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8427 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8428 | |
0ff066a9 PZ |
8429 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8430 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8431 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8432 | } |
8433 | ||
8434 | /* WaMPhyProgramming:hsw */ | |
8435 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8436 | { | |
8437 | uint32_t tmp; | |
dde86e2d PZ |
8438 | |
8439 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8440 | tmp &= ~(0xFF << 24); | |
8441 | tmp |= (0x12 << 24); | |
8442 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8443 | ||
dde86e2d PZ |
8444 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8445 | tmp |= (1 << 11); | |
8446 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8447 | ||
8448 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8449 | tmp |= (1 << 11); | |
8450 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8451 | ||
dde86e2d PZ |
8452 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8453 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8454 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8455 | ||
8456 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8457 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8458 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8459 | ||
0ff066a9 PZ |
8460 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8461 | tmp &= ~(7 << 13); | |
8462 | tmp |= (5 << 13); | |
8463 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8464 | |
0ff066a9 PZ |
8465 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8466 | tmp &= ~(7 << 13); | |
8467 | tmp |= (5 << 13); | |
8468 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8469 | |
8470 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8471 | tmp &= ~0xFF; | |
8472 | tmp |= 0x1C; | |
8473 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8474 | ||
8475 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8476 | tmp &= ~0xFF; | |
8477 | tmp |= 0x1C; | |
8478 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8479 | ||
8480 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8481 | tmp &= ~(0xFF << 16); | |
8482 | tmp |= (0x1C << 16); | |
8483 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8484 | ||
8485 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8486 | tmp &= ~(0xFF << 16); | |
8487 | tmp |= (0x1C << 16); | |
8488 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8489 | ||
0ff066a9 PZ |
8490 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8491 | tmp |= (1 << 27); | |
8492 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8493 | |
0ff066a9 PZ |
8494 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8495 | tmp |= (1 << 27); | |
8496 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8497 | |
0ff066a9 PZ |
8498 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8499 | tmp &= ~(0xF << 28); | |
8500 | tmp |= (4 << 28); | |
8501 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8502 | |
0ff066a9 PZ |
8503 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8504 | tmp &= ~(0xF << 28); | |
8505 | tmp |= (4 << 28); | |
8506 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8507 | } |
8508 | ||
2fa86a1f PZ |
8509 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8510 | * Programming" based on the parameters passed: | |
8511 | * - Sequence to enable CLKOUT_DP | |
8512 | * - Sequence to enable CLKOUT_DP without spread | |
8513 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8514 | */ | |
8515 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8516 | bool with_fdi) | |
f31f2d55 PZ |
8517 | { |
8518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8519 | uint32_t reg, tmp; |
8520 | ||
8521 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8522 | with_spread = true; | |
c2699524 | 8523 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8524 | with_fdi = false; |
f31f2d55 | 8525 | |
a580516d | 8526 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8527 | |
8528 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8529 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8530 | tmp |= SBI_SSCCTL_PATHALT; | |
8531 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8532 | ||
8533 | udelay(24); | |
8534 | ||
2fa86a1f PZ |
8535 | if (with_spread) { |
8536 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8537 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8538 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8539 | |
2fa86a1f PZ |
8540 | if (with_fdi) { |
8541 | lpt_reset_fdi_mphy(dev_priv); | |
8542 | lpt_program_fdi_mphy(dev_priv); | |
8543 | } | |
8544 | } | |
dde86e2d | 8545 | |
c2699524 | 8546 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8547 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8548 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8549 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8550 | |
a580516d | 8551 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8552 | } |
8553 | ||
47701c3b PZ |
8554 | /* Sequence to disable CLKOUT_DP */ |
8555 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8556 | { | |
8557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8558 | uint32_t reg, tmp; | |
8559 | ||
a580516d | 8560 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8561 | |
c2699524 | 8562 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8563 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8564 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8565 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8566 | ||
8567 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8568 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8569 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8570 | tmp |= SBI_SSCCTL_PATHALT; | |
8571 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8572 | udelay(32); | |
8573 | } | |
8574 | tmp |= SBI_SSCCTL_DISABLE; | |
8575 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8576 | } | |
8577 | ||
a580516d | 8578 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8579 | } |
8580 | ||
f7be2c21 VS |
8581 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8582 | ||
8583 | static const uint16_t sscdivintphase[] = { | |
8584 | [BEND_IDX( 50)] = 0x3B23, | |
8585 | [BEND_IDX( 45)] = 0x3B23, | |
8586 | [BEND_IDX( 40)] = 0x3C23, | |
8587 | [BEND_IDX( 35)] = 0x3C23, | |
8588 | [BEND_IDX( 30)] = 0x3D23, | |
8589 | [BEND_IDX( 25)] = 0x3D23, | |
8590 | [BEND_IDX( 20)] = 0x3E23, | |
8591 | [BEND_IDX( 15)] = 0x3E23, | |
8592 | [BEND_IDX( 10)] = 0x3F23, | |
8593 | [BEND_IDX( 5)] = 0x3F23, | |
8594 | [BEND_IDX( 0)] = 0x0025, | |
8595 | [BEND_IDX( -5)] = 0x0025, | |
8596 | [BEND_IDX(-10)] = 0x0125, | |
8597 | [BEND_IDX(-15)] = 0x0125, | |
8598 | [BEND_IDX(-20)] = 0x0225, | |
8599 | [BEND_IDX(-25)] = 0x0225, | |
8600 | [BEND_IDX(-30)] = 0x0325, | |
8601 | [BEND_IDX(-35)] = 0x0325, | |
8602 | [BEND_IDX(-40)] = 0x0425, | |
8603 | [BEND_IDX(-45)] = 0x0425, | |
8604 | [BEND_IDX(-50)] = 0x0525, | |
8605 | }; | |
8606 | ||
8607 | /* | |
8608 | * Bend CLKOUT_DP | |
8609 | * steps -50 to 50 inclusive, in steps of 5 | |
8610 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8611 | * change in clock period = -(steps / 10) * 5.787 ps | |
8612 | */ | |
8613 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8614 | { | |
8615 | uint32_t tmp; | |
8616 | int idx = BEND_IDX(steps); | |
8617 | ||
8618 | if (WARN_ON(steps % 5 != 0)) | |
8619 | return; | |
8620 | ||
8621 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8622 | return; | |
8623 | ||
8624 | mutex_lock(&dev_priv->sb_lock); | |
8625 | ||
8626 | if (steps % 10 != 0) | |
8627 | tmp = 0xAAAAAAAB; | |
8628 | else | |
8629 | tmp = 0x00000000; | |
8630 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8631 | ||
8632 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8633 | tmp &= 0xffff0000; | |
8634 | tmp |= sscdivintphase[idx]; | |
8635 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8636 | ||
8637 | mutex_unlock(&dev_priv->sb_lock); | |
8638 | } | |
8639 | ||
8640 | #undef BEND_IDX | |
8641 | ||
bf8fa3d3 PZ |
8642 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8643 | { | |
bf8fa3d3 PZ |
8644 | struct intel_encoder *encoder; |
8645 | bool has_vga = false; | |
8646 | ||
b2784e15 | 8647 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8648 | switch (encoder->type) { |
8649 | case INTEL_OUTPUT_ANALOG: | |
8650 | has_vga = true; | |
8651 | break; | |
6847d71b PZ |
8652 | default: |
8653 | break; | |
bf8fa3d3 PZ |
8654 | } |
8655 | } | |
8656 | ||
f7be2c21 VS |
8657 | if (has_vga) { |
8658 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8659 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8660 | } else { |
47701c3b | 8661 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8662 | } |
bf8fa3d3 PZ |
8663 | } |
8664 | ||
dde86e2d PZ |
8665 | /* |
8666 | * Initialize reference clocks when the driver loads | |
8667 | */ | |
8668 | void intel_init_pch_refclk(struct drm_device *dev) | |
8669 | { | |
8670 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8671 | ironlake_init_pch_refclk(dev); | |
8672 | else if (HAS_PCH_LPT(dev)) | |
8673 | lpt_init_pch_refclk(dev); | |
8674 | } | |
8675 | ||
55bb9992 | 8676 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8677 | { |
55bb9992 | 8678 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8679 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8680 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8681 | struct drm_connector *connector; |
55bb9992 | 8682 | struct drm_connector_state *connector_state; |
d9d444cb | 8683 | struct intel_encoder *encoder; |
55bb9992 | 8684 | int num_connectors = 0, i; |
d9d444cb JB |
8685 | bool is_lvds = false; |
8686 | ||
da3ced29 | 8687 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8688 | if (connector_state->crtc != crtc_state->base.crtc) |
8689 | continue; | |
8690 | ||
8691 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8692 | ||
d9d444cb JB |
8693 | switch (encoder->type) { |
8694 | case INTEL_OUTPUT_LVDS: | |
8695 | is_lvds = true; | |
8696 | break; | |
6847d71b PZ |
8697 | default: |
8698 | break; | |
d9d444cb JB |
8699 | } |
8700 | num_connectors++; | |
8701 | } | |
8702 | ||
8703 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8704 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8705 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8706 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8707 | } |
8708 | ||
8709 | return 120000; | |
8710 | } | |
8711 | ||
6ff93609 | 8712 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8713 | { |
c8203565 | 8714 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8716 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8717 | uint32_t val; |
8718 | ||
78114071 | 8719 | val = 0; |
c8203565 | 8720 | |
6e3c9717 | 8721 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8722 | case 18: |
dfd07d72 | 8723 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8724 | break; |
8725 | case 24: | |
dfd07d72 | 8726 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8727 | break; |
8728 | case 30: | |
dfd07d72 | 8729 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8730 | break; |
8731 | case 36: | |
dfd07d72 | 8732 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8733 | break; |
8734 | default: | |
cc769b62 PZ |
8735 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8736 | BUG(); | |
c8203565 PZ |
8737 | } |
8738 | ||
6e3c9717 | 8739 | if (intel_crtc->config->dither) |
c8203565 PZ |
8740 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8741 | ||
6e3c9717 | 8742 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8743 | val |= PIPECONF_INTERLACED_ILK; |
8744 | else | |
8745 | val |= PIPECONF_PROGRESSIVE; | |
8746 | ||
6e3c9717 | 8747 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8748 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8749 | |
c8203565 PZ |
8750 | I915_WRITE(PIPECONF(pipe), val); |
8751 | POSTING_READ(PIPECONF(pipe)); | |
8752 | } | |
8753 | ||
86d3efce VS |
8754 | /* |
8755 | * Set up the pipe CSC unit. | |
8756 | * | |
8757 | * Currently only full range RGB to limited range RGB conversion | |
8758 | * is supported, but eventually this should handle various | |
8759 | * RGB<->YCbCr scenarios as well. | |
8760 | */ | |
50f3b016 | 8761 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8762 | { |
8763 | struct drm_device *dev = crtc->dev; | |
8764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8766 | int pipe = intel_crtc->pipe; | |
8767 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8768 | ||
8769 | /* | |
8770 | * TODO: Check what kind of values actually come out of the pipe | |
8771 | * with these coeff/postoff values and adjust to get the best | |
8772 | * accuracy. Perhaps we even need to take the bpc value into | |
8773 | * consideration. | |
8774 | */ | |
8775 | ||
6e3c9717 | 8776 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8777 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8778 | ||
8779 | /* | |
8780 | * GY/GU and RY/RU should be the other way around according | |
8781 | * to BSpec, but reality doesn't agree. Just set them up in | |
8782 | * a way that results in the correct picture. | |
8783 | */ | |
8784 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8785 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8786 | ||
8787 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8788 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8789 | ||
8790 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8791 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8792 | ||
8793 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8794 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8795 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8796 | ||
8797 | if (INTEL_INFO(dev)->gen > 6) { | |
8798 | uint16_t postoff = 0; | |
8799 | ||
6e3c9717 | 8800 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8801 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8802 | |
8803 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8804 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8805 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8806 | ||
8807 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8808 | } else { | |
8809 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8810 | ||
6e3c9717 | 8811 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8812 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8813 | ||
8814 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8815 | } | |
8816 | } | |
8817 | ||
6ff93609 | 8818 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8819 | { |
756f85cf PZ |
8820 | struct drm_device *dev = crtc->dev; |
8821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8823 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8824 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8825 | uint32_t val; |
8826 | ||
3eff4faa | 8827 | val = 0; |
ee2b0b38 | 8828 | |
6e3c9717 | 8829 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8830 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8831 | ||
6e3c9717 | 8832 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8833 | val |= PIPECONF_INTERLACED_ILK; |
8834 | else | |
8835 | val |= PIPECONF_PROGRESSIVE; | |
8836 | ||
702e7a56 PZ |
8837 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8838 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8839 | |
8840 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8841 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8842 | |
3cdf122c | 8843 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8844 | val = 0; |
8845 | ||
6e3c9717 | 8846 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8847 | case 18: |
8848 | val |= PIPEMISC_DITHER_6_BPC; | |
8849 | break; | |
8850 | case 24: | |
8851 | val |= PIPEMISC_DITHER_8_BPC; | |
8852 | break; | |
8853 | case 30: | |
8854 | val |= PIPEMISC_DITHER_10_BPC; | |
8855 | break; | |
8856 | case 36: | |
8857 | val |= PIPEMISC_DITHER_12_BPC; | |
8858 | break; | |
8859 | default: | |
8860 | /* Case prevented by pipe_config_set_bpp. */ | |
8861 | BUG(); | |
8862 | } | |
8863 | ||
6e3c9717 | 8864 | if (intel_crtc->config->dither) |
756f85cf PZ |
8865 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8866 | ||
8867 | I915_WRITE(PIPEMISC(pipe), val); | |
8868 | } | |
ee2b0b38 PZ |
8869 | } |
8870 | ||
6591c6e4 | 8871 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8872 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8873 | intel_clock_t *clock, |
8874 | bool *has_reduced_clock, | |
8875 | intel_clock_t *reduced_clock) | |
8876 | { | |
8877 | struct drm_device *dev = crtc->dev; | |
8878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8879 | int refclk; |
d4906093 | 8880 | const intel_limit_t *limit; |
c329a4ec | 8881 | bool ret; |
79e53945 | 8882 | |
55bb9992 | 8883 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8884 | |
d4906093 ML |
8885 | /* |
8886 | * Returns a set of divisors for the desired target clock with the given | |
8887 | * refclk, or FALSE. The returned values represent the clock equation: | |
8888 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8889 | */ | |
a93e255f ACO |
8890 | limit = intel_limit(crtc_state, refclk); |
8891 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8892 | crtc_state->port_clock, |
ee9300bb | 8893 | refclk, NULL, clock); |
6591c6e4 PZ |
8894 | if (!ret) |
8895 | return false; | |
cda4b7d3 | 8896 | |
6591c6e4 PZ |
8897 | return true; |
8898 | } | |
8899 | ||
d4b1931c PZ |
8900 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8901 | { | |
8902 | /* | |
8903 | * Account for spread spectrum to avoid | |
8904 | * oversubscribing the link. Max center spread | |
8905 | * is 2.5%; use 5% for safety's sake. | |
8906 | */ | |
8907 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8908 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8909 | } |
8910 | ||
7429e9d4 | 8911 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8912 | { |
7429e9d4 | 8913 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8914 | } |
8915 | ||
de13a2e3 | 8916 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8917 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8918 | u32 *fp, |
9a7c7890 | 8919 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8920 | { |
de13a2e3 | 8921 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8922 | struct drm_device *dev = crtc->dev; |
8923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8924 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8925 | struct drm_connector *connector; |
55bb9992 ACO |
8926 | struct drm_connector_state *connector_state; |
8927 | struct intel_encoder *encoder; | |
de13a2e3 | 8928 | uint32_t dpll; |
55bb9992 | 8929 | int factor, num_connectors = 0, i; |
09ede541 | 8930 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8931 | |
da3ced29 | 8932 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8933 | if (connector_state->crtc != crtc_state->base.crtc) |
8934 | continue; | |
8935 | ||
8936 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8937 | ||
8938 | switch (encoder->type) { | |
79e53945 JB |
8939 | case INTEL_OUTPUT_LVDS: |
8940 | is_lvds = true; | |
8941 | break; | |
8942 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8943 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8944 | is_sdvo = true; |
79e53945 | 8945 | break; |
6847d71b PZ |
8946 | default: |
8947 | break; | |
79e53945 | 8948 | } |
43565a06 | 8949 | |
c751ce4f | 8950 | num_connectors++; |
79e53945 | 8951 | } |
79e53945 | 8952 | |
c1858123 | 8953 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8954 | factor = 21; |
8955 | if (is_lvds) { | |
8956 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8957 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8958 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8959 | factor = 25; |
190f68c5 | 8960 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8961 | factor = 20; |
c1858123 | 8962 | |
190f68c5 | 8963 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8964 | *fp |= FP_CB_TUNE; |
2c07245f | 8965 | |
9a7c7890 DV |
8966 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8967 | *fp2 |= FP_CB_TUNE; | |
8968 | ||
5eddb70b | 8969 | dpll = 0; |
2c07245f | 8970 | |
a07d6787 EA |
8971 | if (is_lvds) |
8972 | dpll |= DPLLB_MODE_LVDS; | |
8973 | else | |
8974 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8975 | |
190f68c5 | 8976 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8977 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8978 | |
8979 | if (is_sdvo) | |
4a33e48d | 8980 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8981 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8982 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8983 | |
a07d6787 | 8984 | /* compute bitmask from p1 value */ |
190f68c5 | 8985 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8986 | /* also FPA1 */ |
190f68c5 | 8987 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8988 | |
190f68c5 | 8989 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8990 | case 5: |
8991 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8992 | break; | |
8993 | case 7: | |
8994 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8995 | break; | |
8996 | case 10: | |
8997 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8998 | break; | |
8999 | case 14: | |
9000 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9001 | break; | |
79e53945 JB |
9002 | } |
9003 | ||
b4c09f3b | 9004 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9005 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9006 | else |
9007 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9008 | ||
959e16d6 | 9009 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9010 | } |
9011 | ||
190f68c5 ACO |
9012 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9013 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9014 | { |
c7653199 | 9015 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9016 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9017 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9018 | bool ok, has_reduced_clock = false; |
8b47047b | 9019 | bool is_lvds = false; |
e2b78267 | 9020 | struct intel_shared_dpll *pll; |
de13a2e3 | 9021 | |
dd3cd74a ACO |
9022 | memset(&crtc_state->dpll_hw_state, 0, |
9023 | sizeof(crtc_state->dpll_hw_state)); | |
9024 | ||
7905df29 | 9025 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9026 | |
5dc5298b PZ |
9027 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9028 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9029 | |
190f68c5 | 9030 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9031 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9032 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9033 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9034 | return -EINVAL; | |
79e53945 | 9035 | } |
f47709a9 | 9036 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9037 | if (!crtc_state->clock_set) { |
9038 | crtc_state->dpll.n = clock.n; | |
9039 | crtc_state->dpll.m1 = clock.m1; | |
9040 | crtc_state->dpll.m2 = clock.m2; | |
9041 | crtc_state->dpll.p1 = clock.p1; | |
9042 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9043 | } |
79e53945 | 9044 | |
5dc5298b | 9045 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9046 | if (crtc_state->has_pch_encoder) { |
9047 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9048 | if (has_reduced_clock) |
7429e9d4 | 9049 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9050 | |
190f68c5 | 9051 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9052 | &fp, &reduced_clock, |
9053 | has_reduced_clock ? &fp2 : NULL); | |
9054 | ||
190f68c5 ACO |
9055 | crtc_state->dpll_hw_state.dpll = dpll; |
9056 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9057 | if (has_reduced_clock) |
190f68c5 | 9058 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9059 | else |
190f68c5 | 9060 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9061 | |
190f68c5 | 9062 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9063 | if (pll == NULL) { |
84f44ce7 | 9064 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9065 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9066 | return -EINVAL; |
9067 | } | |
3fb37703 | 9068 | } |
79e53945 | 9069 | |
ab585dea | 9070 | if (is_lvds && has_reduced_clock) |
c7653199 | 9071 | crtc->lowfreq_avail = true; |
bcd644e0 | 9072 | else |
c7653199 | 9073 | crtc->lowfreq_avail = false; |
e2b78267 | 9074 | |
c8f7a0db | 9075 | return 0; |
79e53945 JB |
9076 | } |
9077 | ||
eb14cb74 VS |
9078 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9079 | struct intel_link_m_n *m_n) | |
9080 | { | |
9081 | struct drm_device *dev = crtc->base.dev; | |
9082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9083 | enum pipe pipe = crtc->pipe; | |
9084 | ||
9085 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9086 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9087 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9088 | & ~TU_SIZE_MASK; | |
9089 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9090 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9091 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9092 | } | |
9093 | ||
9094 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9095 | enum transcoder transcoder, | |
b95af8be VK |
9096 | struct intel_link_m_n *m_n, |
9097 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9098 | { |
9099 | struct drm_device *dev = crtc->base.dev; | |
9100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9101 | enum pipe pipe = crtc->pipe; |
72419203 | 9102 | |
eb14cb74 VS |
9103 | if (INTEL_INFO(dev)->gen >= 5) { |
9104 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9105 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9106 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9107 | & ~TU_SIZE_MASK; | |
9108 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9109 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9110 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9111 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9112 | * gen < 8) and if DRRS is supported (to make sure the | |
9113 | * registers are not unnecessarily read). | |
9114 | */ | |
9115 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9116 | crtc->config->has_drrs) { |
b95af8be VK |
9117 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9118 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9119 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9120 | & ~TU_SIZE_MASK; | |
9121 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9122 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9123 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9124 | } | |
eb14cb74 VS |
9125 | } else { |
9126 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9127 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9128 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9129 | & ~TU_SIZE_MASK; | |
9130 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9131 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9132 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9133 | } | |
9134 | } | |
9135 | ||
9136 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9137 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9138 | { |
681a8504 | 9139 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9140 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9141 | else | |
9142 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9143 | &pipe_config->dp_m_n, |
9144 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9145 | } |
72419203 | 9146 | |
eb14cb74 | 9147 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9148 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9149 | { |
9150 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9151 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9152 | } |
9153 | ||
bd2e244f | 9154 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9155 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9156 | { |
9157 | struct drm_device *dev = crtc->base.dev; | |
9158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9159 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9160 | uint32_t ps_ctrl = 0; | |
9161 | int id = -1; | |
9162 | int i; | |
bd2e244f | 9163 | |
a1b2278e CK |
9164 | /* find scaler attached to this pipe */ |
9165 | for (i = 0; i < crtc->num_scalers; i++) { | |
9166 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9167 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9168 | id = i; | |
9169 | pipe_config->pch_pfit.enabled = true; | |
9170 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9171 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9172 | break; | |
9173 | } | |
9174 | } | |
bd2e244f | 9175 | |
a1b2278e CK |
9176 | scaler_state->scaler_id = id; |
9177 | if (id >= 0) { | |
9178 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9179 | } else { | |
9180 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9181 | } |
9182 | } | |
9183 | ||
5724dbd1 DL |
9184 | static void |
9185 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9186 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9187 | { |
9188 | struct drm_device *dev = crtc->base.dev; | |
9189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9190 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9191 | int pipe = crtc->pipe; |
9192 | int fourcc, pixel_format; | |
6761dd31 | 9193 | unsigned int aligned_height; |
bc8d7dff | 9194 | struct drm_framebuffer *fb; |
1b842c89 | 9195 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9196 | |
d9806c9f | 9197 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9198 | if (!intel_fb) { |
bc8d7dff DL |
9199 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9200 | return; | |
9201 | } | |
9202 | ||
1b842c89 DL |
9203 | fb = &intel_fb->base; |
9204 | ||
bc8d7dff | 9205 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9206 | if (!(val & PLANE_CTL_ENABLE)) |
9207 | goto error; | |
9208 | ||
bc8d7dff DL |
9209 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9210 | fourcc = skl_format_to_fourcc(pixel_format, | |
9211 | val & PLANE_CTL_ORDER_RGBX, | |
9212 | val & PLANE_CTL_ALPHA_MASK); | |
9213 | fb->pixel_format = fourcc; | |
9214 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9215 | ||
40f46283 DL |
9216 | tiling = val & PLANE_CTL_TILED_MASK; |
9217 | switch (tiling) { | |
9218 | case PLANE_CTL_TILED_LINEAR: | |
9219 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9220 | break; | |
9221 | case PLANE_CTL_TILED_X: | |
9222 | plane_config->tiling = I915_TILING_X; | |
9223 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9224 | break; | |
9225 | case PLANE_CTL_TILED_Y: | |
9226 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9227 | break; | |
9228 | case PLANE_CTL_TILED_YF: | |
9229 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9230 | break; | |
9231 | default: | |
9232 | MISSING_CASE(tiling); | |
9233 | goto error; | |
9234 | } | |
9235 | ||
bc8d7dff DL |
9236 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9237 | plane_config->base = base; | |
9238 | ||
9239 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9240 | ||
9241 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9242 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9243 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9244 | ||
9245 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9246 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9247 | fb->pixel_format); |
bc8d7dff DL |
9248 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9249 | ||
9250 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9251 | fb->pixel_format, |
9252 | fb->modifier[0]); | |
bc8d7dff | 9253 | |
f37b5c2b | 9254 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9255 | |
9256 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9257 | pipe_name(pipe), fb->width, fb->height, | |
9258 | fb->bits_per_pixel, base, fb->pitches[0], | |
9259 | plane_config->size); | |
9260 | ||
2d14030b | 9261 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9262 | return; |
9263 | ||
9264 | error: | |
9265 | kfree(fb); | |
9266 | } | |
9267 | ||
2fa2fe9a | 9268 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9269 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9270 | { |
9271 | struct drm_device *dev = crtc->base.dev; | |
9272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9273 | uint32_t tmp; | |
9274 | ||
9275 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9276 | ||
9277 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9278 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9279 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9280 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9281 | |
9282 | /* We currently do not free assignements of panel fitters on | |
9283 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9284 | * differentiates them) so just WARN about this case for now. */ | |
9285 | if (IS_GEN7(dev)) { | |
9286 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9287 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9288 | } | |
2fa2fe9a | 9289 | } |
79e53945 JB |
9290 | } |
9291 | ||
5724dbd1 DL |
9292 | static void |
9293 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9294 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9295 | { |
9296 | struct drm_device *dev = crtc->base.dev; | |
9297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9298 | u32 val, base, offset; | |
aeee5a49 | 9299 | int pipe = crtc->pipe; |
4c6baa59 | 9300 | int fourcc, pixel_format; |
6761dd31 | 9301 | unsigned int aligned_height; |
b113d5ee | 9302 | struct drm_framebuffer *fb; |
1b842c89 | 9303 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9304 | |
42a7b088 DL |
9305 | val = I915_READ(DSPCNTR(pipe)); |
9306 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9307 | return; | |
9308 | ||
d9806c9f | 9309 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9310 | if (!intel_fb) { |
4c6baa59 JB |
9311 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9312 | return; | |
9313 | } | |
9314 | ||
1b842c89 DL |
9315 | fb = &intel_fb->base; |
9316 | ||
18c5247e DV |
9317 | if (INTEL_INFO(dev)->gen >= 4) { |
9318 | if (val & DISPPLANE_TILED) { | |
49af449b | 9319 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9320 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9321 | } | |
9322 | } | |
4c6baa59 JB |
9323 | |
9324 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9325 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9326 | fb->pixel_format = fourcc; |
9327 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9328 | |
aeee5a49 | 9329 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9330 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9331 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9332 | } else { |
49af449b | 9333 | if (plane_config->tiling) |
aeee5a49 | 9334 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9335 | else |
aeee5a49 | 9336 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9337 | } |
9338 | plane_config->base = base; | |
9339 | ||
9340 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9341 | fb->width = ((val >> 16) & 0xfff) + 1; |
9342 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9343 | |
9344 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9345 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9346 | |
b113d5ee | 9347 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9348 | fb->pixel_format, |
9349 | fb->modifier[0]); | |
4c6baa59 | 9350 | |
f37b5c2b | 9351 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9352 | |
2844a921 DL |
9353 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9354 | pipe_name(pipe), fb->width, fb->height, | |
9355 | fb->bits_per_pixel, base, fb->pitches[0], | |
9356 | plane_config->size); | |
b113d5ee | 9357 | |
2d14030b | 9358 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9359 | } |
9360 | ||
0e8ffe1b | 9361 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9362 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9363 | { |
9364 | struct drm_device *dev = crtc->base.dev; | |
9365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9366 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9367 | uint32_t tmp; |
1729050e | 9368 | bool ret; |
0e8ffe1b | 9369 | |
1729050e ID |
9370 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9371 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9372 | return false; |
9373 | ||
e143a21c | 9374 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9375 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9376 | |
1729050e | 9377 | ret = false; |
0e8ffe1b DV |
9378 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9379 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9380 | goto out; |
0e8ffe1b | 9381 | |
42571aef VS |
9382 | switch (tmp & PIPECONF_BPC_MASK) { |
9383 | case PIPECONF_6BPC: | |
9384 | pipe_config->pipe_bpp = 18; | |
9385 | break; | |
9386 | case PIPECONF_8BPC: | |
9387 | pipe_config->pipe_bpp = 24; | |
9388 | break; | |
9389 | case PIPECONF_10BPC: | |
9390 | pipe_config->pipe_bpp = 30; | |
9391 | break; | |
9392 | case PIPECONF_12BPC: | |
9393 | pipe_config->pipe_bpp = 36; | |
9394 | break; | |
9395 | default: | |
9396 | break; | |
9397 | } | |
9398 | ||
b5a9fa09 DV |
9399 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9400 | pipe_config->limited_color_range = true; | |
9401 | ||
ab9412ba | 9402 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9403 | struct intel_shared_dpll *pll; |
9404 | ||
88adfff1 DV |
9405 | pipe_config->has_pch_encoder = true; |
9406 | ||
627eb5a3 DV |
9407 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9408 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9409 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9410 | |
9411 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9412 | |
c0d43d62 | 9413 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9414 | pipe_config->shared_dpll = |
9415 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9416 | } else { |
9417 | tmp = I915_READ(PCH_DPLL_SEL); | |
9418 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9419 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9420 | else | |
9421 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9422 | } | |
66e985c0 DV |
9423 | |
9424 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9425 | ||
9426 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9427 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9428 | |
9429 | tmp = pipe_config->dpll_hw_state.dpll; | |
9430 | pipe_config->pixel_multiplier = | |
9431 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9432 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9433 | |
9434 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9435 | } else { |
9436 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9437 | } |
9438 | ||
1bd1bd80 DV |
9439 | intel_get_pipe_timings(crtc, pipe_config); |
9440 | ||
2fa2fe9a DV |
9441 | ironlake_get_pfit_config(crtc, pipe_config); |
9442 | ||
1729050e ID |
9443 | ret = true; |
9444 | ||
9445 | out: | |
9446 | intel_display_power_put(dev_priv, power_domain); | |
9447 | ||
9448 | return ret; | |
0e8ffe1b DV |
9449 | } |
9450 | ||
be256dc7 PZ |
9451 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9452 | { | |
9453 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9454 | struct intel_crtc *crtc; |
be256dc7 | 9455 | |
d3fcc808 | 9456 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9457 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9458 | pipe_name(crtc->pipe)); |
9459 | ||
e2c719b7 RC |
9460 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9461 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9462 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9463 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9464 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9465 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9466 | "CPU PWM1 enabled\n"); |
c5107b87 | 9467 | if (IS_HASWELL(dev)) |
e2c719b7 | 9468 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9469 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9470 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9471 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9472 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9473 | "Utility pin enabled\n"); |
e2c719b7 | 9474 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9475 | |
9926ada1 PZ |
9476 | /* |
9477 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9478 | * interrupts remain enabled. We used to check for that, but since it's | |
9479 | * gen-specific and since we only disable LCPLL after we fully disable | |
9480 | * the interrupts, the check below should be enough. | |
9481 | */ | |
e2c719b7 | 9482 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9483 | } |
9484 | ||
9ccd5aeb PZ |
9485 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9486 | { | |
9487 | struct drm_device *dev = dev_priv->dev; | |
9488 | ||
9489 | if (IS_HASWELL(dev)) | |
9490 | return I915_READ(D_COMP_HSW); | |
9491 | else | |
9492 | return I915_READ(D_COMP_BDW); | |
9493 | } | |
9494 | ||
3c4c9b81 PZ |
9495 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9496 | { | |
9497 | struct drm_device *dev = dev_priv->dev; | |
9498 | ||
9499 | if (IS_HASWELL(dev)) { | |
9500 | mutex_lock(&dev_priv->rps.hw_lock); | |
9501 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9502 | val)) | |
f475dadf | 9503 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9504 | mutex_unlock(&dev_priv->rps.hw_lock); |
9505 | } else { | |
9ccd5aeb PZ |
9506 | I915_WRITE(D_COMP_BDW, val); |
9507 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9508 | } |
be256dc7 PZ |
9509 | } |
9510 | ||
9511 | /* | |
9512 | * This function implements pieces of two sequences from BSpec: | |
9513 | * - Sequence for display software to disable LCPLL | |
9514 | * - Sequence for display software to allow package C8+ | |
9515 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9516 | * register. Callers should take care of disabling all the display engine | |
9517 | * functions, doing the mode unset, fixing interrupts, etc. | |
9518 | */ | |
6ff58d53 PZ |
9519 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9520 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9521 | { |
9522 | uint32_t val; | |
9523 | ||
9524 | assert_can_disable_lcpll(dev_priv); | |
9525 | ||
9526 | val = I915_READ(LCPLL_CTL); | |
9527 | ||
9528 | if (switch_to_fclk) { | |
9529 | val |= LCPLL_CD_SOURCE_FCLK; | |
9530 | I915_WRITE(LCPLL_CTL, val); | |
9531 | ||
9532 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9533 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9534 | DRM_ERROR("Switching to FCLK failed\n"); | |
9535 | ||
9536 | val = I915_READ(LCPLL_CTL); | |
9537 | } | |
9538 | ||
9539 | val |= LCPLL_PLL_DISABLE; | |
9540 | I915_WRITE(LCPLL_CTL, val); | |
9541 | POSTING_READ(LCPLL_CTL); | |
9542 | ||
9543 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9544 | DRM_ERROR("LCPLL still locked\n"); | |
9545 | ||
9ccd5aeb | 9546 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9547 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9548 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9549 | ndelay(100); |
9550 | ||
9ccd5aeb PZ |
9551 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9552 | 1)) | |
be256dc7 PZ |
9553 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9554 | ||
9555 | if (allow_power_down) { | |
9556 | val = I915_READ(LCPLL_CTL); | |
9557 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9558 | I915_WRITE(LCPLL_CTL, val); | |
9559 | POSTING_READ(LCPLL_CTL); | |
9560 | } | |
9561 | } | |
9562 | ||
9563 | /* | |
9564 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9565 | * source. | |
9566 | */ | |
6ff58d53 | 9567 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9568 | { |
9569 | uint32_t val; | |
9570 | ||
9571 | val = I915_READ(LCPLL_CTL); | |
9572 | ||
9573 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9574 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9575 | return; | |
9576 | ||
a8a8bd54 PZ |
9577 | /* |
9578 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9579 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9580 | */ |
59bad947 | 9581 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9582 | |
be256dc7 PZ |
9583 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9584 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9585 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9586 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9587 | } |
9588 | ||
9ccd5aeb | 9589 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9590 | val |= D_COMP_COMP_FORCE; |
9591 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9592 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9593 | |
9594 | val = I915_READ(LCPLL_CTL); | |
9595 | val &= ~LCPLL_PLL_DISABLE; | |
9596 | I915_WRITE(LCPLL_CTL, val); | |
9597 | ||
9598 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9599 | DRM_ERROR("LCPLL not locked yet\n"); | |
9600 | ||
9601 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9602 | val = I915_READ(LCPLL_CTL); | |
9603 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9604 | I915_WRITE(LCPLL_CTL, val); | |
9605 | ||
9606 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9607 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9608 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9609 | } | |
215733fa | 9610 | |
59bad947 | 9611 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9612 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9613 | } |
9614 | ||
765dab67 PZ |
9615 | /* |
9616 | * Package states C8 and deeper are really deep PC states that can only be | |
9617 | * reached when all the devices on the system allow it, so even if the graphics | |
9618 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9619 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9620 | * | |
9621 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9622 | * well is disabled and most interrupts are disabled, and these are also | |
9623 | * requirements for runtime PM. When these conditions are met, we manually do | |
9624 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9625 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9626 | * hang the machine. | |
9627 | * | |
9628 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9629 | * the state of some registers, so when we come back from PC8+ we need to | |
9630 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9631 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9632 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9633 | * because of the runtime PM support). | |
9634 | * | |
9635 | * For more, read "Display Sequences for Package C8" on the hardware | |
9636 | * documentation. | |
9637 | */ | |
a14cb6fc | 9638 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9639 | { |
c67a470b PZ |
9640 | struct drm_device *dev = dev_priv->dev; |
9641 | uint32_t val; | |
9642 | ||
c67a470b PZ |
9643 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9644 | ||
c2699524 | 9645 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9646 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9647 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9648 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9649 | } | |
9650 | ||
9651 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9652 | hsw_disable_lcpll(dev_priv, true, true); |
9653 | } | |
9654 | ||
a14cb6fc | 9655 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9656 | { |
9657 | struct drm_device *dev = dev_priv->dev; | |
9658 | uint32_t val; | |
9659 | ||
c67a470b PZ |
9660 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9661 | ||
9662 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9663 | lpt_init_pch_refclk(dev); |
9664 | ||
c2699524 | 9665 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9666 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9667 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9668 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9669 | } | |
c67a470b PZ |
9670 | } |
9671 | ||
27c329ed | 9672 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9673 | { |
a821fc46 | 9674 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9675 | struct intel_atomic_state *old_intel_state = |
9676 | to_intel_atomic_state(old_state); | |
9677 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9678 | |
27c329ed | 9679 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9680 | } |
9681 | ||
b432e5cf | 9682 | /* compute the max rate for new configuration */ |
27c329ed | 9683 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9684 | { |
565602d7 ML |
9685 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9686 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9687 | struct drm_crtc *crtc; | |
9688 | struct drm_crtc_state *cstate; | |
27c329ed | 9689 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9690 | unsigned max_pixel_rate = 0, i; |
9691 | enum pipe pipe; | |
b432e5cf | 9692 | |
565602d7 ML |
9693 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9694 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9695 | |
565602d7 ML |
9696 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9697 | int pixel_rate; | |
27c329ed | 9698 | |
565602d7 ML |
9699 | crtc_state = to_intel_crtc_state(cstate); |
9700 | if (!crtc_state->base.enable) { | |
9701 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9702 | continue; |
565602d7 | 9703 | } |
b432e5cf | 9704 | |
27c329ed | 9705 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9706 | |
9707 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9708 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9709 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9710 | ||
565602d7 | 9711 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9712 | } |
9713 | ||
565602d7 ML |
9714 | for_each_pipe(dev_priv, pipe) |
9715 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9716 | ||
b432e5cf VS |
9717 | return max_pixel_rate; |
9718 | } | |
9719 | ||
9720 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9721 | { | |
9722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9723 | uint32_t val, data; | |
9724 | int ret; | |
9725 | ||
9726 | if (WARN((I915_READ(LCPLL_CTL) & | |
9727 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9728 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9729 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9730 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9731 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9732 | return; | |
9733 | ||
9734 | mutex_lock(&dev_priv->rps.hw_lock); | |
9735 | ret = sandybridge_pcode_write(dev_priv, | |
9736 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9737 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9738 | if (ret) { | |
9739 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9740 | return; | |
9741 | } | |
9742 | ||
9743 | val = I915_READ(LCPLL_CTL); | |
9744 | val |= LCPLL_CD_SOURCE_FCLK; | |
9745 | I915_WRITE(LCPLL_CTL, val); | |
9746 | ||
9747 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9748 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9749 | DRM_ERROR("Switching to FCLK failed\n"); | |
9750 | ||
9751 | val = I915_READ(LCPLL_CTL); | |
9752 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9753 | ||
9754 | switch (cdclk) { | |
9755 | case 450000: | |
9756 | val |= LCPLL_CLK_FREQ_450; | |
9757 | data = 0; | |
9758 | break; | |
9759 | case 540000: | |
9760 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9761 | data = 1; | |
9762 | break; | |
9763 | case 337500: | |
9764 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9765 | data = 2; | |
9766 | break; | |
9767 | case 675000: | |
9768 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9769 | data = 3; | |
9770 | break; | |
9771 | default: | |
9772 | WARN(1, "invalid cdclk frequency\n"); | |
9773 | return; | |
9774 | } | |
9775 | ||
9776 | I915_WRITE(LCPLL_CTL, val); | |
9777 | ||
9778 | val = I915_READ(LCPLL_CTL); | |
9779 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9780 | I915_WRITE(LCPLL_CTL, val); | |
9781 | ||
9782 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9783 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9784 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9785 | ||
9786 | mutex_lock(&dev_priv->rps.hw_lock); | |
9787 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9788 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9789 | ||
9790 | intel_update_cdclk(dev); | |
9791 | ||
9792 | WARN(cdclk != dev_priv->cdclk_freq, | |
9793 | "cdclk requested %d kHz but got %d kHz\n", | |
9794 | cdclk, dev_priv->cdclk_freq); | |
9795 | } | |
9796 | ||
27c329ed | 9797 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9798 | { |
27c329ed | 9799 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9800 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9801 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9802 | int cdclk; |
9803 | ||
9804 | /* | |
9805 | * FIXME should also account for plane ratio | |
9806 | * once 64bpp pixel formats are supported. | |
9807 | */ | |
27c329ed | 9808 | if (max_pixclk > 540000) |
b432e5cf | 9809 | cdclk = 675000; |
27c329ed | 9810 | else if (max_pixclk > 450000) |
b432e5cf | 9811 | cdclk = 540000; |
27c329ed | 9812 | else if (max_pixclk > 337500) |
b432e5cf VS |
9813 | cdclk = 450000; |
9814 | else | |
9815 | cdclk = 337500; | |
9816 | ||
b432e5cf | 9817 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9818 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9819 | cdclk, dev_priv->max_cdclk_freq); | |
9820 | return -EINVAL; | |
b432e5cf VS |
9821 | } |
9822 | ||
1a617b77 ML |
9823 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9824 | if (!intel_state->active_crtcs) | |
9825 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9826 | |
9827 | return 0; | |
9828 | } | |
9829 | ||
27c329ed | 9830 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9831 | { |
27c329ed | 9832 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9833 | struct intel_atomic_state *old_intel_state = |
9834 | to_intel_atomic_state(old_state); | |
9835 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9836 | |
27c329ed | 9837 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9838 | } |
9839 | ||
190f68c5 ACO |
9840 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9841 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9842 | { |
af3997b5 MK |
9843 | struct intel_encoder *intel_encoder = |
9844 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9845 | ||
9846 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9847 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9848 | return -EINVAL; | |
9849 | } | |
716c2e55 | 9850 | |
c7653199 | 9851 | crtc->lowfreq_avail = false; |
644cef34 | 9852 | |
c8f7a0db | 9853 | return 0; |
79e53945 JB |
9854 | } |
9855 | ||
3760b59c S |
9856 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9857 | enum port port, | |
9858 | struct intel_crtc_state *pipe_config) | |
9859 | { | |
9860 | switch (port) { | |
9861 | case PORT_A: | |
9862 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9863 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9864 | break; | |
9865 | case PORT_B: | |
9866 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9867 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9868 | break; | |
9869 | case PORT_C: | |
9870 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9871 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9872 | break; | |
9873 | default: | |
9874 | DRM_ERROR("Incorrect port type\n"); | |
9875 | } | |
9876 | } | |
9877 | ||
96b7dfb7 S |
9878 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9879 | enum port port, | |
5cec258b | 9880 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9881 | { |
3148ade7 | 9882 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9883 | |
9884 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9885 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9886 | ||
9887 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9888 | case SKL_DPLL0: |
9889 | /* | |
9890 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9891 | * of the shared DPLL framework and thus needs to be read out | |
9892 | * separately | |
9893 | */ | |
9894 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9895 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9896 | break; | |
96b7dfb7 S |
9897 | case SKL_DPLL1: |
9898 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9899 | break; | |
9900 | case SKL_DPLL2: | |
9901 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9902 | break; | |
9903 | case SKL_DPLL3: | |
9904 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9905 | break; | |
96b7dfb7 S |
9906 | } |
9907 | } | |
9908 | ||
7d2c8175 DL |
9909 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9910 | enum port port, | |
5cec258b | 9911 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9912 | { |
9913 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9914 | ||
9915 | switch (pipe_config->ddi_pll_sel) { | |
9916 | case PORT_CLK_SEL_WRPLL1: | |
9917 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9918 | break; | |
9919 | case PORT_CLK_SEL_WRPLL2: | |
9920 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9921 | break; | |
00490c22 ML |
9922 | case PORT_CLK_SEL_SPLL: |
9923 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9924 | break; |
7d2c8175 DL |
9925 | } |
9926 | } | |
9927 | ||
26804afd | 9928 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9929 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9930 | { |
9931 | struct drm_device *dev = crtc->base.dev; | |
9932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9933 | struct intel_shared_dpll *pll; |
26804afd DV |
9934 | enum port port; |
9935 | uint32_t tmp; | |
9936 | ||
9937 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9938 | ||
9939 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9940 | ||
ef11bdb3 | 9941 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9942 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9943 | else if (IS_BROXTON(dev)) |
9944 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9945 | else |
9946 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9947 | |
d452c5b6 DV |
9948 | if (pipe_config->shared_dpll >= 0) { |
9949 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9950 | ||
9951 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9952 | &pipe_config->dpll_hw_state)); | |
9953 | } | |
9954 | ||
26804afd DV |
9955 | /* |
9956 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9957 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9958 | * the PCH transcoder is on. | |
9959 | */ | |
ca370455 DL |
9960 | if (INTEL_INFO(dev)->gen < 9 && |
9961 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9962 | pipe_config->has_pch_encoder = true; |
9963 | ||
9964 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9965 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9966 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9967 | ||
9968 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9969 | } | |
9970 | } | |
9971 | ||
0e8ffe1b | 9972 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9973 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9974 | { |
9975 | struct drm_device *dev = crtc->base.dev; | |
9976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9977 | enum intel_display_power_domain power_domain; |
9978 | unsigned long power_domain_mask; | |
0e8ffe1b | 9979 | uint32_t tmp; |
1729050e | 9980 | bool ret; |
0e8ffe1b | 9981 | |
1729050e ID |
9982 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9983 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9984 | return false; |
1729050e ID |
9985 | power_domain_mask = BIT(power_domain); |
9986 | ||
9987 | ret = false; | |
b5482bd0 | 9988 | |
e143a21c | 9989 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9990 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9991 | ||
eccb140b DV |
9992 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9993 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9994 | enum pipe trans_edp_pipe; | |
9995 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9996 | default: | |
9997 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9998 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9999 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10000 | trans_edp_pipe = PIPE_A; | |
10001 | break; | |
10002 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10003 | trans_edp_pipe = PIPE_B; | |
10004 | break; | |
10005 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10006 | trans_edp_pipe = PIPE_C; | |
10007 | break; | |
10008 | } | |
10009 | ||
10010 | if (trans_edp_pipe == crtc->pipe) | |
10011 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10012 | } | |
10013 | ||
1729050e ID |
10014 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
10015 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10016 | goto out; | |
10017 | power_domain_mask |= BIT(power_domain); | |
2bfce950 | 10018 | |
eccb140b | 10019 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b | 10020 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 10021 | goto out; |
0e8ffe1b | 10022 | |
26804afd | 10023 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10024 | |
1bd1bd80 DV |
10025 | intel_get_pipe_timings(crtc, pipe_config); |
10026 | ||
a1b2278e CK |
10027 | if (INTEL_INFO(dev)->gen >= 9) { |
10028 | skl_init_scalers(dev, crtc, pipe_config); | |
10029 | } | |
10030 | ||
af99ceda CK |
10031 | if (INTEL_INFO(dev)->gen >= 9) { |
10032 | pipe_config->scaler_state.scaler_id = -1; | |
10033 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10034 | } | |
10035 | ||
1729050e ID |
10036 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10037 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10038 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10039 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10040 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10041 | else |
1c132b44 | 10042 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10043 | } |
88adfff1 | 10044 | |
e59150dc JB |
10045 | if (IS_HASWELL(dev)) |
10046 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10047 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10048 | |
ebb69c95 CT |
10049 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10050 | pipe_config->pixel_multiplier = | |
10051 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10052 | } else { | |
10053 | pipe_config->pixel_multiplier = 1; | |
10054 | } | |
6c49f241 | 10055 | |
1729050e ID |
10056 | ret = true; |
10057 | ||
10058 | out: | |
10059 | for_each_power_domain(power_domain, power_domain_mask) | |
10060 | intel_display_power_put(dev_priv, power_domain); | |
10061 | ||
10062 | return ret; | |
0e8ffe1b DV |
10063 | } |
10064 | ||
55a08b3f ML |
10065 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10066 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10067 | { |
10068 | struct drm_device *dev = crtc->dev; | |
10069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10071 | uint32_t cntl = 0, size = 0; |
560b85bb | 10072 | |
55a08b3f ML |
10073 | if (plane_state && plane_state->visible) { |
10074 | unsigned int width = plane_state->base.crtc_w; | |
10075 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10076 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10077 | ||
10078 | switch (stride) { | |
10079 | default: | |
10080 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10081 | width, stride); | |
10082 | stride = 256; | |
10083 | /* fallthrough */ | |
10084 | case 256: | |
10085 | case 512: | |
10086 | case 1024: | |
10087 | case 2048: | |
10088 | break; | |
4b0e333e CW |
10089 | } |
10090 | ||
dc41c154 VS |
10091 | cntl |= CURSOR_ENABLE | |
10092 | CURSOR_GAMMA_ENABLE | | |
10093 | CURSOR_FORMAT_ARGB | | |
10094 | CURSOR_STRIDE(stride); | |
10095 | ||
10096 | size = (height << 12) | width; | |
4b0e333e | 10097 | } |
560b85bb | 10098 | |
dc41c154 VS |
10099 | if (intel_crtc->cursor_cntl != 0 && |
10100 | (intel_crtc->cursor_base != base || | |
10101 | intel_crtc->cursor_size != size || | |
10102 | intel_crtc->cursor_cntl != cntl)) { | |
10103 | /* On these chipsets we can only modify the base/size/stride | |
10104 | * whilst the cursor is disabled. | |
10105 | */ | |
0b87c24e VS |
10106 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10107 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10108 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10109 | } |
560b85bb | 10110 | |
99d1f387 | 10111 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10112 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10113 | intel_crtc->cursor_base = base; |
10114 | } | |
4726e0b0 | 10115 | |
dc41c154 VS |
10116 | if (intel_crtc->cursor_size != size) { |
10117 | I915_WRITE(CURSIZE, size); | |
10118 | intel_crtc->cursor_size = size; | |
4b0e333e | 10119 | } |
560b85bb | 10120 | |
4b0e333e | 10121 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10122 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10123 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10124 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10125 | } |
560b85bb CW |
10126 | } |
10127 | ||
55a08b3f ML |
10128 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10129 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10130 | { |
10131 | struct drm_device *dev = crtc->dev; | |
10132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10134 | int pipe = intel_crtc->pipe; | |
663f3122 | 10135 | uint32_t cntl = 0; |
4b0e333e | 10136 | |
55a08b3f | 10137 | if (plane_state && plane_state->visible) { |
4b0e333e | 10138 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10139 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10140 | case 64: |
10141 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10142 | break; | |
10143 | case 128: | |
10144 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10145 | break; | |
10146 | case 256: | |
10147 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10148 | break; | |
10149 | default: | |
55a08b3f | 10150 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10151 | return; |
65a21cd6 | 10152 | } |
4b0e333e | 10153 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10154 | |
fc6f93bc | 10155 | if (HAS_DDI(dev)) |
47bf17a7 | 10156 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10157 | |
55a08b3f ML |
10158 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10159 | cntl |= CURSOR_ROTATE_180; | |
10160 | } | |
4398ad45 | 10161 | |
4b0e333e CW |
10162 | if (intel_crtc->cursor_cntl != cntl) { |
10163 | I915_WRITE(CURCNTR(pipe), cntl); | |
10164 | POSTING_READ(CURCNTR(pipe)); | |
10165 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10166 | } |
4b0e333e | 10167 | |
65a21cd6 | 10168 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10169 | I915_WRITE(CURBASE(pipe), base); |
10170 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10171 | |
10172 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10173 | } |
10174 | ||
cda4b7d3 | 10175 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10176 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10177 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10178 | { |
10179 | struct drm_device *dev = crtc->dev; | |
10180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10181 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10182 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10183 | u32 base = intel_crtc->cursor_addr; |
10184 | u32 pos = 0; | |
cda4b7d3 | 10185 | |
55a08b3f ML |
10186 | if (plane_state) { |
10187 | int x = plane_state->base.crtc_x; | |
10188 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10189 | |
55a08b3f ML |
10190 | if (x < 0) { |
10191 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10192 | x = -x; | |
10193 | } | |
10194 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10195 | |
55a08b3f ML |
10196 | if (y < 0) { |
10197 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10198 | y = -y; | |
10199 | } | |
10200 | pos |= y << CURSOR_Y_SHIFT; | |
10201 | ||
10202 | /* ILK+ do this automagically */ | |
10203 | if (HAS_GMCH_DISPLAY(dev) && | |
10204 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10205 | base += (plane_state->base.crtc_h * | |
10206 | plane_state->base.crtc_w - 1) * 4; | |
10207 | } | |
cda4b7d3 | 10208 | } |
cda4b7d3 | 10209 | |
5efb3e28 VS |
10210 | I915_WRITE(CURPOS(pipe), pos); |
10211 | ||
8ac54669 | 10212 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10213 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10214 | else |
55a08b3f | 10215 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10216 | } |
10217 | ||
dc41c154 VS |
10218 | static bool cursor_size_ok(struct drm_device *dev, |
10219 | uint32_t width, uint32_t height) | |
10220 | { | |
10221 | if (width == 0 || height == 0) | |
10222 | return false; | |
10223 | ||
10224 | /* | |
10225 | * 845g/865g are special in that they are only limited by | |
10226 | * the width of their cursors, the height is arbitrary up to | |
10227 | * the precision of the register. Everything else requires | |
10228 | * square cursors, limited to a few power-of-two sizes. | |
10229 | */ | |
10230 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10231 | if ((width & 63) != 0) | |
10232 | return false; | |
10233 | ||
10234 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10235 | return false; | |
10236 | ||
10237 | if (height > 1023) | |
10238 | return false; | |
10239 | } else { | |
10240 | switch (width | height) { | |
10241 | case 256: | |
10242 | case 128: | |
10243 | if (IS_GEN2(dev)) | |
10244 | return false; | |
10245 | case 64: | |
10246 | break; | |
10247 | default: | |
10248 | return false; | |
10249 | } | |
10250 | } | |
10251 | ||
10252 | return true; | |
10253 | } | |
10254 | ||
79e53945 | 10255 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10256 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10257 | { |
7203425a | 10258 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10260 | |
7203425a | 10261 | for (i = start; i < end; i++) { |
79e53945 JB |
10262 | intel_crtc->lut_r[i] = red[i] >> 8; |
10263 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10264 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10265 | } | |
10266 | ||
10267 | intel_crtc_load_lut(crtc); | |
10268 | } | |
10269 | ||
79e53945 JB |
10270 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10271 | static struct drm_display_mode load_detect_mode = { | |
10272 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10273 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10274 | }; | |
10275 | ||
a8bb6818 DV |
10276 | struct drm_framebuffer * |
10277 | __intel_framebuffer_create(struct drm_device *dev, | |
10278 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10279 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10280 | { |
10281 | struct intel_framebuffer *intel_fb; | |
10282 | int ret; | |
10283 | ||
10284 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10285 | if (!intel_fb) |
d2dff872 | 10286 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10287 | |
10288 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10289 | if (ret) |
10290 | goto err; | |
d2dff872 CW |
10291 | |
10292 | return &intel_fb->base; | |
dcb1394e | 10293 | |
dd4916c5 | 10294 | err: |
dd4916c5 | 10295 | kfree(intel_fb); |
dd4916c5 | 10296 | return ERR_PTR(ret); |
d2dff872 CW |
10297 | } |
10298 | ||
b5ea642a | 10299 | static struct drm_framebuffer * |
a8bb6818 DV |
10300 | intel_framebuffer_create(struct drm_device *dev, |
10301 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10302 | struct drm_i915_gem_object *obj) | |
10303 | { | |
10304 | struct drm_framebuffer *fb; | |
10305 | int ret; | |
10306 | ||
10307 | ret = i915_mutex_lock_interruptible(dev); | |
10308 | if (ret) | |
10309 | return ERR_PTR(ret); | |
10310 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10311 | mutex_unlock(&dev->struct_mutex); | |
10312 | ||
10313 | return fb; | |
10314 | } | |
10315 | ||
d2dff872 CW |
10316 | static u32 |
10317 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10318 | { | |
10319 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10320 | return ALIGN(pitch, 64); | |
10321 | } | |
10322 | ||
10323 | static u32 | |
10324 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10325 | { | |
10326 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10327 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10328 | } |
10329 | ||
10330 | static struct drm_framebuffer * | |
10331 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10332 | struct drm_display_mode *mode, | |
10333 | int depth, int bpp) | |
10334 | { | |
dcb1394e | 10335 | struct drm_framebuffer *fb; |
d2dff872 | 10336 | struct drm_i915_gem_object *obj; |
0fed39bd | 10337 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10338 | |
10339 | obj = i915_gem_alloc_object(dev, | |
10340 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10341 | if (obj == NULL) | |
10342 | return ERR_PTR(-ENOMEM); | |
10343 | ||
10344 | mode_cmd.width = mode->hdisplay; | |
10345 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10346 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10347 | bpp); | |
5ca0c34a | 10348 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10349 | |
dcb1394e LW |
10350 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10351 | if (IS_ERR(fb)) | |
10352 | drm_gem_object_unreference_unlocked(&obj->base); | |
10353 | ||
10354 | return fb; | |
d2dff872 CW |
10355 | } |
10356 | ||
10357 | static struct drm_framebuffer * | |
10358 | mode_fits_in_fbdev(struct drm_device *dev, | |
10359 | struct drm_display_mode *mode) | |
10360 | { | |
0695726e | 10361 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10362 | struct drm_i915_private *dev_priv = dev->dev_private; |
10363 | struct drm_i915_gem_object *obj; | |
10364 | struct drm_framebuffer *fb; | |
10365 | ||
4c0e5528 | 10366 | if (!dev_priv->fbdev) |
d2dff872 CW |
10367 | return NULL; |
10368 | ||
4c0e5528 | 10369 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10370 | return NULL; |
10371 | ||
4c0e5528 DV |
10372 | obj = dev_priv->fbdev->fb->obj; |
10373 | BUG_ON(!obj); | |
10374 | ||
8bcd4553 | 10375 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10376 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10377 | fb->bits_per_pixel)) | |
d2dff872 CW |
10378 | return NULL; |
10379 | ||
01f2c773 | 10380 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10381 | return NULL; |
10382 | ||
edde3617 | 10383 | drm_framebuffer_reference(fb); |
d2dff872 | 10384 | return fb; |
4520f53a DV |
10385 | #else |
10386 | return NULL; | |
10387 | #endif | |
d2dff872 CW |
10388 | } |
10389 | ||
d3a40d1b ACO |
10390 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10391 | struct drm_crtc *crtc, | |
10392 | struct drm_display_mode *mode, | |
10393 | struct drm_framebuffer *fb, | |
10394 | int x, int y) | |
10395 | { | |
10396 | struct drm_plane_state *plane_state; | |
10397 | int hdisplay, vdisplay; | |
10398 | int ret; | |
10399 | ||
10400 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10401 | if (IS_ERR(plane_state)) | |
10402 | return PTR_ERR(plane_state); | |
10403 | ||
10404 | if (mode) | |
10405 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10406 | else | |
10407 | hdisplay = vdisplay = 0; | |
10408 | ||
10409 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10410 | if (ret) | |
10411 | return ret; | |
10412 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10413 | plane_state->crtc_x = 0; | |
10414 | plane_state->crtc_y = 0; | |
10415 | plane_state->crtc_w = hdisplay; | |
10416 | plane_state->crtc_h = vdisplay; | |
10417 | plane_state->src_x = x << 16; | |
10418 | plane_state->src_y = y << 16; | |
10419 | plane_state->src_w = hdisplay << 16; | |
10420 | plane_state->src_h = vdisplay << 16; | |
10421 | ||
10422 | return 0; | |
10423 | } | |
10424 | ||
d2434ab7 | 10425 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10426 | struct drm_display_mode *mode, |
51fd371b RC |
10427 | struct intel_load_detect_pipe *old, |
10428 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10429 | { |
10430 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10431 | struct intel_encoder *intel_encoder = |
10432 | intel_attached_encoder(connector); | |
79e53945 | 10433 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10434 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10435 | struct drm_crtc *crtc = NULL; |
10436 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10437 | struct drm_framebuffer *fb; |
51fd371b | 10438 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10439 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10440 | struct drm_connector_state *connector_state; |
4be07317 | 10441 | struct intel_crtc_state *crtc_state; |
51fd371b | 10442 | int ret, i = -1; |
79e53945 | 10443 | |
d2dff872 | 10444 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10445 | connector->base.id, connector->name, |
8e329a03 | 10446 | encoder->base.id, encoder->name); |
d2dff872 | 10447 | |
edde3617 ML |
10448 | old->restore_state = NULL; |
10449 | ||
51fd371b RC |
10450 | retry: |
10451 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10452 | if (ret) | |
ad3c558f | 10453 | goto fail; |
6e9f798d | 10454 | |
79e53945 JB |
10455 | /* |
10456 | * Algorithm gets a little messy: | |
7a5e4805 | 10457 | * |
79e53945 JB |
10458 | * - if the connector already has an assigned crtc, use it (but make |
10459 | * sure it's on first) | |
7a5e4805 | 10460 | * |
79e53945 JB |
10461 | * - try to find the first unused crtc that can drive this connector, |
10462 | * and use that if we find one | |
79e53945 JB |
10463 | */ |
10464 | ||
10465 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10466 | if (connector->state->crtc) { |
10467 | crtc = connector->state->crtc; | |
8261b191 | 10468 | |
51fd371b | 10469 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10470 | if (ret) |
ad3c558f | 10471 | goto fail; |
8261b191 CW |
10472 | |
10473 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10474 | goto found; |
79e53945 JB |
10475 | } |
10476 | ||
10477 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10478 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10479 | i++; |
10480 | if (!(encoder->possible_crtcs & (1 << i))) | |
10481 | continue; | |
edde3617 ML |
10482 | |
10483 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10484 | if (ret) | |
10485 | goto fail; | |
10486 | ||
10487 | if (possible_crtc->state->enable) { | |
10488 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10489 | continue; |
edde3617 | 10490 | } |
a459249c VS |
10491 | |
10492 | crtc = possible_crtc; | |
10493 | break; | |
79e53945 JB |
10494 | } |
10495 | ||
10496 | /* | |
10497 | * If we didn't find an unused CRTC, don't use any. | |
10498 | */ | |
10499 | if (!crtc) { | |
7173188d | 10500 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10501 | goto fail; |
79e53945 JB |
10502 | } |
10503 | ||
edde3617 ML |
10504 | found: |
10505 | intel_crtc = to_intel_crtc(crtc); | |
10506 | ||
4d02e2de DV |
10507 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10508 | if (ret) | |
ad3c558f | 10509 | goto fail; |
79e53945 | 10510 | |
83a57153 | 10511 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10512 | restore_state = drm_atomic_state_alloc(dev); |
10513 | if (!state || !restore_state) { | |
10514 | ret = -ENOMEM; | |
10515 | goto fail; | |
10516 | } | |
83a57153 ACO |
10517 | |
10518 | state->acquire_ctx = ctx; | |
edde3617 | 10519 | restore_state->acquire_ctx = ctx; |
83a57153 | 10520 | |
944b0c76 ACO |
10521 | connector_state = drm_atomic_get_connector_state(state, connector); |
10522 | if (IS_ERR(connector_state)) { | |
10523 | ret = PTR_ERR(connector_state); | |
10524 | goto fail; | |
10525 | } | |
10526 | ||
edde3617 ML |
10527 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10528 | if (ret) | |
10529 | goto fail; | |
944b0c76 | 10530 | |
4be07317 ACO |
10531 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10532 | if (IS_ERR(crtc_state)) { | |
10533 | ret = PTR_ERR(crtc_state); | |
10534 | goto fail; | |
10535 | } | |
10536 | ||
49d6fa21 | 10537 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10538 | |
6492711d CW |
10539 | if (!mode) |
10540 | mode = &load_detect_mode; | |
79e53945 | 10541 | |
d2dff872 CW |
10542 | /* We need a framebuffer large enough to accommodate all accesses |
10543 | * that the plane may generate whilst we perform load detection. | |
10544 | * We can not rely on the fbcon either being present (we get called | |
10545 | * during its initialisation to detect all boot displays, or it may | |
10546 | * not even exist) or that it is large enough to satisfy the | |
10547 | * requested mode. | |
10548 | */ | |
94352cf9 DV |
10549 | fb = mode_fits_in_fbdev(dev, mode); |
10550 | if (fb == NULL) { | |
d2dff872 | 10551 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10552 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10553 | } else |
10554 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10555 | if (IS_ERR(fb)) { |
d2dff872 | 10556 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10557 | goto fail; |
79e53945 | 10558 | } |
79e53945 | 10559 | |
d3a40d1b ACO |
10560 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10561 | if (ret) | |
10562 | goto fail; | |
10563 | ||
edde3617 ML |
10564 | drm_framebuffer_unreference(fb); |
10565 | ||
10566 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10567 | if (ret) | |
10568 | goto fail; | |
10569 | ||
10570 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10571 | if (!ret) | |
10572 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10573 | if (!ret) | |
10574 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10575 | if (ret) { | |
10576 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10577 | goto fail; | |
10578 | } | |
8c7b5ccb | 10579 | |
74c090b1 | 10580 | if (drm_atomic_commit(state)) { |
6492711d | 10581 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10582 | goto fail; |
79e53945 | 10583 | } |
edde3617 ML |
10584 | |
10585 | old->restore_state = restore_state; | |
7173188d | 10586 | |
79e53945 | 10587 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10588 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10589 | return true; |
412b61d8 | 10590 | |
ad3c558f | 10591 | fail: |
e5d958ef | 10592 | drm_atomic_state_free(state); |
edde3617 ML |
10593 | drm_atomic_state_free(restore_state); |
10594 | restore_state = state = NULL; | |
83a57153 | 10595 | |
51fd371b RC |
10596 | if (ret == -EDEADLK) { |
10597 | drm_modeset_backoff(ctx); | |
10598 | goto retry; | |
10599 | } | |
10600 | ||
412b61d8 | 10601 | return false; |
79e53945 JB |
10602 | } |
10603 | ||
d2434ab7 | 10604 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10605 | struct intel_load_detect_pipe *old, |
10606 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10607 | { |
d2434ab7 DV |
10608 | struct intel_encoder *intel_encoder = |
10609 | intel_attached_encoder(connector); | |
4ef69c7a | 10610 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10611 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10612 | int ret; |
79e53945 | 10613 | |
d2dff872 | 10614 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10615 | connector->base.id, connector->name, |
8e329a03 | 10616 | encoder->base.id, encoder->name); |
d2dff872 | 10617 | |
edde3617 | 10618 | if (!state) |
0622a53c | 10619 | return; |
79e53945 | 10620 | |
edde3617 ML |
10621 | ret = drm_atomic_commit(state); |
10622 | if (ret) { | |
10623 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10624 | drm_atomic_state_free(state); | |
10625 | } | |
79e53945 JB |
10626 | } |
10627 | ||
da4a1efa | 10628 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10629 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10630 | { |
10631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10632 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10633 | ||
10634 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10635 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10636 | else if (HAS_PCH_SPLIT(dev)) |
10637 | return 120000; | |
10638 | else if (!IS_GEN2(dev)) | |
10639 | return 96000; | |
10640 | else | |
10641 | return 48000; | |
10642 | } | |
10643 | ||
79e53945 | 10644 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10645 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10646 | struct intel_crtc_state *pipe_config) |
79e53945 | 10647 | { |
f1f644dc | 10648 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10649 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10650 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10651 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10652 | u32 fp; |
10653 | intel_clock_t clock; | |
dccbea3b | 10654 | int port_clock; |
da4a1efa | 10655 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10656 | |
10657 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10658 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10659 | else |
293623f7 | 10660 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10661 | |
10662 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10663 | if (IS_PINEVIEW(dev)) { |
10664 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10665 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10666 | } else { |
10667 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10668 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10669 | } | |
10670 | ||
a6c45cf0 | 10671 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10672 | if (IS_PINEVIEW(dev)) |
10673 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10674 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10675 | else |
10676 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10677 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10678 | ||
10679 | switch (dpll & DPLL_MODE_MASK) { | |
10680 | case DPLLB_MODE_DAC_SERIAL: | |
10681 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10682 | 5 : 10; | |
10683 | break; | |
10684 | case DPLLB_MODE_LVDS: | |
10685 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10686 | 7 : 14; | |
10687 | break; | |
10688 | default: | |
28c97730 | 10689 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10690 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10691 | return; |
79e53945 JB |
10692 | } |
10693 | ||
ac58c3f0 | 10694 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10695 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10696 | else |
dccbea3b | 10697 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10698 | } else { |
0fb58223 | 10699 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10700 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10701 | |
10702 | if (is_lvds) { | |
10703 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10704 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10705 | |
10706 | if (lvds & LVDS_CLKB_POWER_UP) | |
10707 | clock.p2 = 7; | |
10708 | else | |
10709 | clock.p2 = 14; | |
79e53945 JB |
10710 | } else { |
10711 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10712 | clock.p1 = 2; | |
10713 | else { | |
10714 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10715 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10716 | } | |
10717 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10718 | clock.p2 = 4; | |
10719 | else | |
10720 | clock.p2 = 2; | |
79e53945 | 10721 | } |
da4a1efa | 10722 | |
dccbea3b | 10723 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10724 | } |
10725 | ||
18442d08 VS |
10726 | /* |
10727 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10728 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10729 | * encoder's get_config() function. |
10730 | */ | |
dccbea3b | 10731 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10732 | } |
10733 | ||
6878da05 VS |
10734 | int intel_dotclock_calculate(int link_freq, |
10735 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10736 | { |
f1f644dc JB |
10737 | /* |
10738 | * The calculation for the data clock is: | |
1041a02f | 10739 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10740 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10741 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10742 | * |
10743 | * and the link clock is simpler: | |
1041a02f | 10744 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10745 | */ |
10746 | ||
6878da05 VS |
10747 | if (!m_n->link_n) |
10748 | return 0; | |
f1f644dc | 10749 | |
6878da05 VS |
10750 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10751 | } | |
f1f644dc | 10752 | |
18442d08 | 10753 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10754 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10755 | { |
10756 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10757 | |
18442d08 VS |
10758 | /* read out port_clock from the DPLL */ |
10759 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10760 | |
f1f644dc | 10761 | /* |
18442d08 | 10762 | * This value does not include pixel_multiplier. |
241bfc38 | 10763 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10764 | * agree once we know their relationship in the encoder's |
10765 | * get_config() function. | |
79e53945 | 10766 | */ |
2d112de7 | 10767 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10768 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10769 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10770 | } |
10771 | ||
10772 | /** Returns the currently programmed mode of the given pipe. */ | |
10773 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10774 | struct drm_crtc *crtc) | |
10775 | { | |
548f245b | 10776 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10778 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10779 | struct drm_display_mode *mode; |
3f36b937 | 10780 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10781 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10782 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10783 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10784 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10785 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10786 | |
10787 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10788 | if (!mode) | |
10789 | return NULL; | |
10790 | ||
3f36b937 TU |
10791 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10792 | if (!pipe_config) { | |
10793 | kfree(mode); | |
10794 | return NULL; | |
10795 | } | |
10796 | ||
f1f644dc JB |
10797 | /* |
10798 | * Construct a pipe_config sufficient for getting the clock info | |
10799 | * back out of crtc_clock_get. | |
10800 | * | |
10801 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10802 | * to use a real value here instead. | |
10803 | */ | |
3f36b937 TU |
10804 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10805 | pipe_config->pixel_multiplier = 1; | |
10806 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10807 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10808 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10809 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10810 | ||
10811 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10812 | mode->hdisplay = (htot & 0xffff) + 1; |
10813 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10814 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10815 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10816 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10817 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10818 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10819 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10820 | ||
10821 | drm_mode_set_name(mode); | |
79e53945 | 10822 | |
3f36b937 TU |
10823 | kfree(pipe_config); |
10824 | ||
79e53945 JB |
10825 | return mode; |
10826 | } | |
10827 | ||
f047e395 CW |
10828 | void intel_mark_busy(struct drm_device *dev) |
10829 | { | |
c67a470b PZ |
10830 | struct drm_i915_private *dev_priv = dev->dev_private; |
10831 | ||
f62a0076 CW |
10832 | if (dev_priv->mm.busy) |
10833 | return; | |
10834 | ||
43694d69 | 10835 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10836 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10837 | if (INTEL_INFO(dev)->gen >= 6) |
10838 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10839 | dev_priv->mm.busy = true; |
f047e395 CW |
10840 | } |
10841 | ||
10842 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10843 | { |
c67a470b | 10844 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10845 | |
f62a0076 CW |
10846 | if (!dev_priv->mm.busy) |
10847 | return; | |
10848 | ||
10849 | dev_priv->mm.busy = false; | |
10850 | ||
3d13ef2e | 10851 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10852 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10853 | |
43694d69 | 10854 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10855 | } |
10856 | ||
79e53945 JB |
10857 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10858 | { | |
10859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10860 | struct drm_device *dev = crtc->dev; |
10861 | struct intel_unpin_work *work; | |
67e77c5a | 10862 | |
5e2d7afc | 10863 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10864 | work = intel_crtc->unpin_work; |
10865 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10866 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10867 | |
10868 | if (work) { | |
10869 | cancel_work_sync(&work->work); | |
10870 | kfree(work); | |
10871 | } | |
79e53945 JB |
10872 | |
10873 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10874 | |
79e53945 JB |
10875 | kfree(intel_crtc); |
10876 | } | |
10877 | ||
6b95a207 KH |
10878 | static void intel_unpin_work_fn(struct work_struct *__work) |
10879 | { | |
10880 | struct intel_unpin_work *work = | |
10881 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10882 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10883 | struct drm_device *dev = crtc->base.dev; | |
10884 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10885 | |
b4a98e57 | 10886 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10887 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10888 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10889 | |
f06cc1b9 | 10890 | if (work->flip_queued_req) |
146d84f0 | 10891 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10892 | mutex_unlock(&dev->struct_mutex); |
10893 | ||
a9ff8714 | 10894 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10895 | intel_fbc_post_update(crtc); |
89ed88ba | 10896 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10897 | |
a9ff8714 VS |
10898 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10899 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10900 | |
6b95a207 KH |
10901 | kfree(work); |
10902 | } | |
10903 | ||
1afe3e9d | 10904 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10905 | struct drm_crtc *crtc) |
6b95a207 | 10906 | { |
6b95a207 KH |
10907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10908 | struct intel_unpin_work *work; | |
6b95a207 KH |
10909 | unsigned long flags; |
10910 | ||
10911 | /* Ignore early vblank irqs */ | |
10912 | if (intel_crtc == NULL) | |
10913 | return; | |
10914 | ||
f326038a DV |
10915 | /* |
10916 | * This is called both by irq handlers and the reset code (to complete | |
10917 | * lost pageflips) so needs the full irqsave spinlocks. | |
10918 | */ | |
6b95a207 KH |
10919 | spin_lock_irqsave(&dev->event_lock, flags); |
10920 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10921 | |
10922 | /* Ensure we don't miss a work->pending update ... */ | |
10923 | smp_rmb(); | |
10924 | ||
10925 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10926 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10927 | return; | |
10928 | } | |
10929 | ||
d6bbafa1 | 10930 | page_flip_completed(intel_crtc); |
0af7e4df | 10931 | |
6b95a207 | 10932 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10933 | } |
10934 | ||
1afe3e9d JB |
10935 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10936 | { | |
fbee40df | 10937 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10938 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10939 | ||
49b14a5c | 10940 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10941 | } |
10942 | ||
10943 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10944 | { | |
fbee40df | 10945 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10946 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10947 | ||
49b14a5c | 10948 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10949 | } |
10950 | ||
75f7f3ec VS |
10951 | /* Is 'a' after or equal to 'b'? */ |
10952 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10953 | { | |
10954 | return !((a - b) & 0x80000000); | |
10955 | } | |
10956 | ||
10957 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10958 | { | |
10959 | struct drm_device *dev = crtc->base.dev; | |
10960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10961 | ||
bdfa7542 VS |
10962 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10963 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10964 | return true; | |
10965 | ||
75f7f3ec VS |
10966 | /* |
10967 | * The relevant registers doen't exist on pre-ctg. | |
10968 | * As the flip done interrupt doesn't trigger for mmio | |
10969 | * flips on gmch platforms, a flip count check isn't | |
10970 | * really needed there. But since ctg has the registers, | |
10971 | * include it in the check anyway. | |
10972 | */ | |
10973 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10974 | return true; | |
10975 | ||
e8861675 ML |
10976 | /* |
10977 | * BDW signals flip done immediately if the plane | |
10978 | * is disabled, even if the plane enable is already | |
10979 | * armed to occur at the next vblank :( | |
10980 | */ | |
10981 | ||
75f7f3ec VS |
10982 | /* |
10983 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10984 | * used the same base address. In that case the mmio flip might | |
10985 | * have completed, but the CS hasn't even executed the flip yet. | |
10986 | * | |
10987 | * A flip count check isn't enough as the CS might have updated | |
10988 | * the base address just after start of vblank, but before we | |
10989 | * managed to process the interrupt. This means we'd complete the | |
10990 | * CS flip too soon. | |
10991 | * | |
10992 | * Combining both checks should get us a good enough result. It may | |
10993 | * still happen that the CS flip has been executed, but has not | |
10994 | * yet actually completed. But in case the base address is the same | |
10995 | * anyway, we don't really care. | |
10996 | */ | |
10997 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10998 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10999 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11000 | crtc->unpin_work->flip_count); |
11001 | } | |
11002 | ||
6b95a207 KH |
11003 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11004 | { | |
fbee40df | 11005 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11006 | struct intel_crtc *intel_crtc = |
11007 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11008 | unsigned long flags; | |
11009 | ||
f326038a DV |
11010 | |
11011 | /* | |
11012 | * This is called both by irq handlers and the reset code (to complete | |
11013 | * lost pageflips) so needs the full irqsave spinlocks. | |
11014 | * | |
11015 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11016 | * generate a page-flip completion irq, i.e. every modeset |
11017 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11018 | */ | |
6b95a207 | 11019 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11020 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11021 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11022 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11023 | } | |
11024 | ||
6042639c | 11025 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11026 | { |
11027 | /* Ensure that the work item is consistent when activating it ... */ | |
11028 | smp_wmb(); | |
6042639c | 11029 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11030 | /* and that it is marked active as soon as the irq could fire. */ |
11031 | smp_wmb(); | |
11032 | } | |
11033 | ||
8c9f3aaf JB |
11034 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11035 | struct drm_crtc *crtc, | |
11036 | struct drm_framebuffer *fb, | |
ed8d1975 | 11037 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11038 | struct drm_i915_gem_request *req, |
ed8d1975 | 11039 | uint32_t flags) |
8c9f3aaf | 11040 | { |
6258fbe2 | 11041 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11043 | u32 flip_mask; |
11044 | int ret; | |
11045 | ||
5fb9de1a | 11046 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11047 | if (ret) |
4fa62c89 | 11048 | return ret; |
8c9f3aaf JB |
11049 | |
11050 | /* Can't queue multiple flips, so wait for the previous | |
11051 | * one to finish before executing the next. | |
11052 | */ | |
11053 | if (intel_crtc->plane) | |
11054 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11055 | else | |
11056 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11057 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11058 | intel_ring_emit(ring, MI_NOOP); | |
11059 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11060 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11061 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11062 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11063 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11064 | |
6042639c | 11065 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11066 | return 0; |
8c9f3aaf JB |
11067 | } |
11068 | ||
11069 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11070 | struct drm_crtc *crtc, | |
11071 | struct drm_framebuffer *fb, | |
ed8d1975 | 11072 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11073 | struct drm_i915_gem_request *req, |
ed8d1975 | 11074 | uint32_t flags) |
8c9f3aaf | 11075 | { |
6258fbe2 | 11076 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11078 | u32 flip_mask; |
11079 | int ret; | |
11080 | ||
5fb9de1a | 11081 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11082 | if (ret) |
4fa62c89 | 11083 | return ret; |
8c9f3aaf JB |
11084 | |
11085 | if (intel_crtc->plane) | |
11086 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11087 | else | |
11088 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11089 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11090 | intel_ring_emit(ring, MI_NOOP); | |
11091 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11092 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11093 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11094 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11095 | intel_ring_emit(ring, MI_NOOP); |
11096 | ||
6042639c | 11097 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11098 | return 0; |
8c9f3aaf JB |
11099 | } |
11100 | ||
11101 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11102 | struct drm_crtc *crtc, | |
11103 | struct drm_framebuffer *fb, | |
ed8d1975 | 11104 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11105 | struct drm_i915_gem_request *req, |
ed8d1975 | 11106 | uint32_t flags) |
8c9f3aaf | 11107 | { |
6258fbe2 | 11108 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11109 | struct drm_i915_private *dev_priv = dev->dev_private; |
11110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11111 | uint32_t pf, pipesrc; | |
11112 | int ret; | |
11113 | ||
5fb9de1a | 11114 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11115 | if (ret) |
4fa62c89 | 11116 | return ret; |
8c9f3aaf JB |
11117 | |
11118 | /* i965+ uses the linear or tiled offsets from the | |
11119 | * Display Registers (which do not change across a page-flip) | |
11120 | * so we need only reprogram the base address. | |
11121 | */ | |
6d90c952 DV |
11122 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11123 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11124 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11125 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11126 | obj->tiling_mode); |
8c9f3aaf JB |
11127 | |
11128 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11129 | * untested on non-native modes, so ignore it for now. | |
11130 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11131 | */ | |
11132 | pf = 0; | |
11133 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11134 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11135 | |
6042639c | 11136 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11137 | return 0; |
8c9f3aaf JB |
11138 | } |
11139 | ||
11140 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11141 | struct drm_crtc *crtc, | |
11142 | struct drm_framebuffer *fb, | |
ed8d1975 | 11143 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11144 | struct drm_i915_gem_request *req, |
ed8d1975 | 11145 | uint32_t flags) |
8c9f3aaf | 11146 | { |
6258fbe2 | 11147 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11148 | struct drm_i915_private *dev_priv = dev->dev_private; |
11149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11150 | uint32_t pf, pipesrc; | |
11151 | int ret; | |
11152 | ||
5fb9de1a | 11153 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11154 | if (ret) |
4fa62c89 | 11155 | return ret; |
8c9f3aaf | 11156 | |
6d90c952 DV |
11157 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11158 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11159 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11160 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11161 | |
dc257cf1 DV |
11162 | /* Contrary to the suggestions in the documentation, |
11163 | * "Enable Panel Fitter" does not seem to be required when page | |
11164 | * flipping with a non-native mode, and worse causes a normal | |
11165 | * modeset to fail. | |
11166 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11167 | */ | |
11168 | pf = 0; | |
8c9f3aaf | 11169 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11170 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11171 | |
6042639c | 11172 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11173 | return 0; |
8c9f3aaf JB |
11174 | } |
11175 | ||
7c9017e5 JB |
11176 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11177 | struct drm_crtc *crtc, | |
11178 | struct drm_framebuffer *fb, | |
ed8d1975 | 11179 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11180 | struct drm_i915_gem_request *req, |
ed8d1975 | 11181 | uint32_t flags) |
7c9017e5 | 11182 | { |
6258fbe2 | 11183 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11185 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11186 | int len, ret; |
11187 | ||
eba905b2 | 11188 | switch (intel_crtc->plane) { |
cb05d8de DV |
11189 | case PLANE_A: |
11190 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11191 | break; | |
11192 | case PLANE_B: | |
11193 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11194 | break; | |
11195 | case PLANE_C: | |
11196 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11197 | break; | |
11198 | default: | |
11199 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11200 | return -ENODEV; |
cb05d8de DV |
11201 | } |
11202 | ||
ffe74d75 | 11203 | len = 4; |
f476828a | 11204 | if (ring->id == RCS) { |
ffe74d75 | 11205 | len += 6; |
f476828a DL |
11206 | /* |
11207 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11208 | * 48bits addresses, and we need a NOOP for the batch size to | |
11209 | * stay even. | |
11210 | */ | |
11211 | if (IS_GEN8(dev)) | |
11212 | len += 2; | |
11213 | } | |
ffe74d75 | 11214 | |
f66fab8e VS |
11215 | /* |
11216 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11217 | * "The full packet must be contained within the same cache line." | |
11218 | * | |
11219 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11220 | * cacheline, if we ever start emitting more commands before | |
11221 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11222 | * then do the cacheline alignment, and finally emit the | |
11223 | * MI_DISPLAY_FLIP. | |
11224 | */ | |
bba09b12 | 11225 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11226 | if (ret) |
4fa62c89 | 11227 | return ret; |
f66fab8e | 11228 | |
5fb9de1a | 11229 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11230 | if (ret) |
4fa62c89 | 11231 | return ret; |
7c9017e5 | 11232 | |
ffe74d75 CW |
11233 | /* Unmask the flip-done completion message. Note that the bspec says that |
11234 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11235 | * more than one flip event at any time (or ensure that one flip message | |
11236 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11237 | * Experimentation says that BCS works despite DERRMR masking all | |
11238 | * flip-done completion events and that unmasking all planes at once | |
11239 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11240 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11241 | */ | |
11242 | if (ring->id == RCS) { | |
11243 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11244 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11245 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11246 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11247 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11248 | if (IS_GEN8(dev)) |
f1afe24f | 11249 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11250 | MI_SRM_LRM_GLOBAL_GTT); |
11251 | else | |
f1afe24f | 11252 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11253 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11254 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11255 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11256 | if (IS_GEN8(dev)) { |
11257 | intel_ring_emit(ring, 0); | |
11258 | intel_ring_emit(ring, MI_NOOP); | |
11259 | } | |
ffe74d75 CW |
11260 | } |
11261 | ||
cb05d8de | 11262 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11263 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11264 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11265 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11266 | |
6042639c | 11267 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11268 | return 0; |
7c9017e5 JB |
11269 | } |
11270 | ||
84c33a64 SG |
11271 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11272 | struct drm_i915_gem_object *obj) | |
11273 | { | |
11274 | /* | |
11275 | * This is not being used for older platforms, because | |
11276 | * non-availability of flip done interrupt forces us to use | |
11277 | * CS flips. Older platforms derive flip done using some clever | |
11278 | * tricks involving the flip_pending status bits and vblank irqs. | |
11279 | * So using MMIO flips there would disrupt this mechanism. | |
11280 | */ | |
11281 | ||
8e09bf83 CW |
11282 | if (ring == NULL) |
11283 | return true; | |
11284 | ||
84c33a64 SG |
11285 | if (INTEL_INFO(ring->dev)->gen < 5) |
11286 | return false; | |
11287 | ||
11288 | if (i915.use_mmio_flip < 0) | |
11289 | return false; | |
11290 | else if (i915.use_mmio_flip > 0) | |
11291 | return true; | |
14bf993e OM |
11292 | else if (i915.enable_execlists) |
11293 | return true; | |
fd8e058a AG |
11294 | else if (obj->base.dma_buf && |
11295 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11296 | false)) | |
11297 | return true; | |
84c33a64 | 11298 | else |
b4716185 | 11299 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11300 | } |
11301 | ||
6042639c | 11302 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11303 | unsigned int rotation, |
6042639c | 11304 | struct intel_unpin_work *work) |
ff944564 DL |
11305 | { |
11306 | struct drm_device *dev = intel_crtc->base.dev; | |
11307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11308 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11309 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11310 | u32 ctl, stride, tile_height; |
ff944564 DL |
11311 | |
11312 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11313 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11314 | switch (fb->modifier[0]) { |
11315 | case DRM_FORMAT_MOD_NONE: | |
11316 | break; | |
11317 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11318 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11319 | break; |
11320 | case I915_FORMAT_MOD_Y_TILED: | |
11321 | ctl |= PLANE_CTL_TILED_Y; | |
11322 | break; | |
11323 | case I915_FORMAT_MOD_Yf_TILED: | |
11324 | ctl |= PLANE_CTL_TILED_YF; | |
11325 | break; | |
11326 | default: | |
11327 | MISSING_CASE(fb->modifier[0]); | |
11328 | } | |
ff944564 DL |
11329 | |
11330 | /* | |
11331 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11332 | * linear buffers or in number of tiles for tiled buffers. | |
11333 | */ | |
86efe24a TU |
11334 | if (intel_rotation_90_or_270(rotation)) { |
11335 | /* stride = Surface height in tiles */ | |
832be82f | 11336 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11337 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11338 | } else { | |
11339 | stride = fb->pitches[0] / | |
7b49f948 VS |
11340 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11341 | fb->pixel_format); | |
86efe24a | 11342 | } |
ff944564 DL |
11343 | |
11344 | /* | |
11345 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11346 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11347 | */ | |
11348 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11349 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11350 | ||
6042639c | 11351 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11352 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11353 | } | |
11354 | ||
6042639c CW |
11355 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11356 | struct intel_unpin_work *work) | |
84c33a64 SG |
11357 | { |
11358 | struct drm_device *dev = intel_crtc->base.dev; | |
11359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11360 | struct intel_framebuffer *intel_fb = | |
11361 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11362 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11363 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11364 | u32 dspcntr; |
84c33a64 | 11365 | |
84c33a64 SG |
11366 | dspcntr = I915_READ(reg); |
11367 | ||
c5d97472 DL |
11368 | if (obj->tiling_mode != I915_TILING_NONE) |
11369 | dspcntr |= DISPPLANE_TILED; | |
11370 | else | |
11371 | dspcntr &= ~DISPPLANE_TILED; | |
11372 | ||
84c33a64 SG |
11373 | I915_WRITE(reg, dspcntr); |
11374 | ||
6042639c | 11375 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11376 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11377 | } |
11378 | ||
11379 | /* | |
11380 | * XXX: This is the temporary way to update the plane registers until we get | |
11381 | * around to using the usual plane update functions for MMIO flips | |
11382 | */ | |
6042639c | 11383 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11384 | { |
6042639c CW |
11385 | struct intel_crtc *crtc = mmio_flip->crtc; |
11386 | struct intel_unpin_work *work; | |
11387 | ||
11388 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11389 | work = crtc->unpin_work; | |
11390 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11391 | if (work == NULL) | |
11392 | return; | |
ff944564 | 11393 | |
6042639c | 11394 | intel_mark_page_flip_active(work); |
ff944564 | 11395 | |
6042639c | 11396 | intel_pipe_update_start(crtc); |
ff944564 | 11397 | |
6042639c | 11398 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11399 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11400 | else |
11401 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11402 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11403 | |
6042639c | 11404 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11405 | } |
11406 | ||
9362c7c5 | 11407 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11408 | { |
b2cfe0ab CW |
11409 | struct intel_mmio_flip *mmio_flip = |
11410 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11411 | struct intel_framebuffer *intel_fb = |
11412 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11413 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11414 | |
6042639c | 11415 | if (mmio_flip->req) { |
eed29a5b | 11416 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11417 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11418 | false, NULL, |
11419 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11420 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11421 | } | |
84c33a64 | 11422 | |
fd8e058a AG |
11423 | /* For framebuffer backed by dmabuf, wait for fence */ |
11424 | if (obj->base.dma_buf) | |
11425 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11426 | false, false, | |
11427 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11428 | ||
6042639c | 11429 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11430 | kfree(mmio_flip); |
84c33a64 SG |
11431 | } |
11432 | ||
11433 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11434 | struct drm_crtc *crtc, | |
86efe24a | 11435 | struct drm_i915_gem_object *obj) |
84c33a64 | 11436 | { |
b2cfe0ab CW |
11437 | struct intel_mmio_flip *mmio_flip; |
11438 | ||
11439 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11440 | if (mmio_flip == NULL) | |
11441 | return -ENOMEM; | |
84c33a64 | 11442 | |
bcafc4e3 | 11443 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11444 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11445 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11446 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11447 | |
b2cfe0ab CW |
11448 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11449 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11450 | |
84c33a64 SG |
11451 | return 0; |
11452 | } | |
11453 | ||
8c9f3aaf JB |
11454 | static int intel_default_queue_flip(struct drm_device *dev, |
11455 | struct drm_crtc *crtc, | |
11456 | struct drm_framebuffer *fb, | |
ed8d1975 | 11457 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11458 | struct drm_i915_gem_request *req, |
ed8d1975 | 11459 | uint32_t flags) |
8c9f3aaf JB |
11460 | { |
11461 | return -ENODEV; | |
11462 | } | |
11463 | ||
d6bbafa1 CW |
11464 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11465 | struct drm_crtc *crtc) | |
11466 | { | |
11467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11468 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11469 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11470 | u32 addr; | |
11471 | ||
11472 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11473 | return true; | |
11474 | ||
908565c2 CW |
11475 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11476 | return false; | |
11477 | ||
d6bbafa1 CW |
11478 | if (!work->enable_stall_check) |
11479 | return false; | |
11480 | ||
11481 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11482 | if (work->flip_queued_req && |
11483 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11484 | return false; |
11485 | ||
1e3feefd | 11486 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11487 | } |
11488 | ||
1e3feefd | 11489 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11490 | return false; |
11491 | ||
11492 | /* Potential stall - if we see that the flip has happened, | |
11493 | * assume a missed interrupt. */ | |
11494 | if (INTEL_INFO(dev)->gen >= 4) | |
11495 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11496 | else | |
11497 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11498 | ||
11499 | /* There is a potential issue here with a false positive after a flip | |
11500 | * to the same address. We could address this by checking for a | |
11501 | * non-incrementing frame counter. | |
11502 | */ | |
11503 | return addr == work->gtt_offset; | |
11504 | } | |
11505 | ||
11506 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11507 | { | |
11508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11509 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11511 | struct intel_unpin_work *work; |
f326038a | 11512 | |
6c51d46f | 11513 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11514 | |
11515 | if (crtc == NULL) | |
11516 | return; | |
11517 | ||
f326038a | 11518 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11519 | work = intel_crtc->unpin_work; |
11520 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11521 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11522 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11523 | page_flip_completed(intel_crtc); |
6ad790c0 | 11524 | work = NULL; |
d6bbafa1 | 11525 | } |
6ad790c0 CW |
11526 | if (work != NULL && |
11527 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11528 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11529 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11530 | } |
11531 | ||
6b95a207 KH |
11532 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11533 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11534 | struct drm_pending_vblank_event *event, |
11535 | uint32_t page_flip_flags) | |
6b95a207 KH |
11536 | { |
11537 | struct drm_device *dev = crtc->dev; | |
11538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11539 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11540 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11541 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11542 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11543 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11544 | struct intel_unpin_work *work; |
a4872ba6 | 11545 | struct intel_engine_cs *ring; |
cf5d8a46 | 11546 | bool mmio_flip; |
91af127f | 11547 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11548 | int ret; |
6b95a207 | 11549 | |
2ff8fde1 MR |
11550 | /* |
11551 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11552 | * check to be safe. In the future we may enable pageflipping from | |
11553 | * a disabled primary plane. | |
11554 | */ | |
11555 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11556 | return -EBUSY; | |
11557 | ||
e6a595d2 | 11558 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11559 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11560 | return -EINVAL; |
11561 | ||
11562 | /* | |
11563 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11564 | * Note that pitch changes could also affect these register. | |
11565 | */ | |
11566 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11567 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11568 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11569 | return -EINVAL; |
11570 | ||
f900db47 CW |
11571 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11572 | goto out_hang; | |
11573 | ||
b14c5679 | 11574 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11575 | if (work == NULL) |
11576 | return -ENOMEM; | |
11577 | ||
6b95a207 | 11578 | work->event = event; |
b4a98e57 | 11579 | work->crtc = crtc; |
ab8d6675 | 11580 | work->old_fb = old_fb; |
6b95a207 KH |
11581 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11582 | ||
87b6b101 | 11583 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11584 | if (ret) |
11585 | goto free_work; | |
11586 | ||
6b95a207 | 11587 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11588 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11589 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11590 | /* Before declaring the flip queue wedged, check if |
11591 | * the hardware completed the operation behind our backs. | |
11592 | */ | |
11593 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11594 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11595 | page_flip_completed(intel_crtc); | |
11596 | } else { | |
11597 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11598 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11599 | |
d6bbafa1 CW |
11600 | drm_crtc_vblank_put(crtc); |
11601 | kfree(work); | |
11602 | return -EBUSY; | |
11603 | } | |
6b95a207 KH |
11604 | } |
11605 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11606 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11607 | |
b4a98e57 CW |
11608 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11609 | flush_workqueue(dev_priv->wq); | |
11610 | ||
75dfca80 | 11611 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11612 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11613 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11614 | |
f4510a27 | 11615 | crtc->primary->fb = fb; |
afd65eb4 | 11616 | update_state_fb(crtc->primary); |
e8216e50 | 11617 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11618 | |
e1f99ce6 | 11619 | work->pending_flip_obj = obj; |
e1f99ce6 | 11620 | |
89ed88ba CW |
11621 | ret = i915_mutex_lock_interruptible(dev); |
11622 | if (ret) | |
11623 | goto cleanup; | |
11624 | ||
b4a98e57 | 11625 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11626 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11627 | |
75f7f3ec | 11628 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11629 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11630 | |
666a4537 | 11631 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11632 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11633 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11634 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11635 | ring = NULL; | |
48bf5b2d | 11636 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11637 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11638 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11639 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11640 | if (ring == NULL || ring->id != RCS) |
11641 | ring = &dev_priv->ring[BCS]; | |
11642 | } else { | |
11643 | ring = &dev_priv->ring[RCS]; | |
11644 | } | |
11645 | ||
cf5d8a46 CW |
11646 | mmio_flip = use_mmio_flip(ring, obj); |
11647 | ||
11648 | /* When using CS flips, we want to emit semaphores between rings. | |
11649 | * However, when using mmio flips we will create a task to do the | |
11650 | * synchronisation, so all we want here is to pin the framebuffer | |
11651 | * into the display plane and skip any waits. | |
11652 | */ | |
7580d774 ML |
11653 | if (!mmio_flip) { |
11654 | ret = i915_gem_object_sync(obj, ring, &request); | |
11655 | if (ret) | |
11656 | goto cleanup_pending; | |
11657 | } | |
11658 | ||
82bc3b2d | 11659 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11660 | crtc->primary->state); |
8c9f3aaf JB |
11661 | if (ret) |
11662 | goto cleanup_pending; | |
6b95a207 | 11663 | |
dedf278c TU |
11664 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11665 | obj, 0); | |
11666 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11667 | |
cf5d8a46 | 11668 | if (mmio_flip) { |
86efe24a | 11669 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11670 | if (ret) |
11671 | goto cleanup_unpin; | |
11672 | ||
f06cc1b9 JH |
11673 | i915_gem_request_assign(&work->flip_queued_req, |
11674 | obj->last_write_req); | |
d6bbafa1 | 11675 | } else { |
6258fbe2 | 11676 | if (!request) { |
26827088 DG |
11677 | request = i915_gem_request_alloc(ring, NULL); |
11678 | if (IS_ERR(request)) { | |
11679 | ret = PTR_ERR(request); | |
6258fbe2 | 11680 | goto cleanup_unpin; |
26827088 | 11681 | } |
6258fbe2 JH |
11682 | } |
11683 | ||
11684 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11685 | page_flip_flags); |
11686 | if (ret) | |
11687 | goto cleanup_unpin; | |
11688 | ||
6258fbe2 | 11689 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11690 | } |
11691 | ||
91af127f | 11692 | if (request) |
75289874 | 11693 | i915_add_request_no_flush(request); |
91af127f | 11694 | |
1e3feefd | 11695 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11696 | work->enable_stall_check = true; |
4fa62c89 | 11697 | |
ab8d6675 | 11698 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11699 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11700 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11701 | |
a9ff8714 VS |
11702 | intel_frontbuffer_flip_prepare(dev, |
11703 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11704 | |
e5510fac JB |
11705 | trace_i915_flip_request(intel_crtc->plane, obj); |
11706 | ||
6b95a207 | 11707 | return 0; |
96b099fd | 11708 | |
4fa62c89 | 11709 | cleanup_unpin: |
82bc3b2d | 11710 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11711 | cleanup_pending: |
0aa498d5 | 11712 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11713 | i915_gem_request_cancel(request); |
b4a98e57 | 11714 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11715 | mutex_unlock(&dev->struct_mutex); |
11716 | cleanup: | |
f4510a27 | 11717 | crtc->primary->fb = old_fb; |
afd65eb4 | 11718 | update_state_fb(crtc->primary); |
89ed88ba CW |
11719 | |
11720 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11721 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11722 | |
5e2d7afc | 11723 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11724 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11725 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11726 | |
87b6b101 | 11727 | drm_crtc_vblank_put(crtc); |
7317c75e | 11728 | free_work: |
96b099fd CW |
11729 | kfree(work); |
11730 | ||
f900db47 | 11731 | if (ret == -EIO) { |
02e0efb5 ML |
11732 | struct drm_atomic_state *state; |
11733 | struct drm_plane_state *plane_state; | |
11734 | ||
f900db47 | 11735 | out_hang: |
02e0efb5 ML |
11736 | state = drm_atomic_state_alloc(dev); |
11737 | if (!state) | |
11738 | return -ENOMEM; | |
11739 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11740 | ||
11741 | retry: | |
11742 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11743 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11744 | if (!ret) { | |
11745 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11746 | ||
11747 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11748 | if (!ret) | |
11749 | ret = drm_atomic_commit(state); | |
11750 | } | |
11751 | ||
11752 | if (ret == -EDEADLK) { | |
11753 | drm_modeset_backoff(state->acquire_ctx); | |
11754 | drm_atomic_state_clear(state); | |
11755 | goto retry; | |
11756 | } | |
11757 | ||
11758 | if (ret) | |
11759 | drm_atomic_state_free(state); | |
11760 | ||
f0d3dad3 | 11761 | if (ret == 0 && event) { |
5e2d7afc | 11762 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11763 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11764 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11765 | } |
f900db47 | 11766 | } |
96b099fd | 11767 | return ret; |
6b95a207 KH |
11768 | } |
11769 | ||
da20eabd ML |
11770 | |
11771 | /** | |
11772 | * intel_wm_need_update - Check whether watermarks need updating | |
11773 | * @plane: drm plane | |
11774 | * @state: new plane state | |
11775 | * | |
11776 | * Check current plane state versus the new one to determine whether | |
11777 | * watermarks need to be recalculated. | |
11778 | * | |
11779 | * Returns true or false. | |
11780 | */ | |
11781 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11782 | struct drm_plane_state *state) | |
11783 | { | |
d21fbe87 MR |
11784 | struct intel_plane_state *new = to_intel_plane_state(state); |
11785 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11786 | ||
11787 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11788 | if (new->visible != cur->visible) |
11789 | return true; | |
11790 | ||
11791 | if (!cur->base.fb || !new->base.fb) | |
11792 | return false; | |
11793 | ||
11794 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11795 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11796 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11797 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11798 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11799 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11800 | return true; |
7809e5ae | 11801 | |
2791a16c | 11802 | return false; |
7809e5ae MR |
11803 | } |
11804 | ||
d21fbe87 MR |
11805 | static bool needs_scaling(struct intel_plane_state *state) |
11806 | { | |
11807 | int src_w = drm_rect_width(&state->src) >> 16; | |
11808 | int src_h = drm_rect_height(&state->src) >> 16; | |
11809 | int dst_w = drm_rect_width(&state->dst); | |
11810 | int dst_h = drm_rect_height(&state->dst); | |
11811 | ||
11812 | return (src_w != dst_w || src_h != dst_h); | |
11813 | } | |
11814 | ||
da20eabd ML |
11815 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11816 | struct drm_plane_state *plane_state) | |
11817 | { | |
ab1d3a0e | 11818 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11819 | struct drm_crtc *crtc = crtc_state->crtc; |
11820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11821 | struct drm_plane *plane = plane_state->plane; | |
11822 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11823 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11824 | struct intel_plane_state *old_plane_state = |
11825 | to_intel_plane_state(plane->state); | |
11826 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11827 | bool mode_changed = needs_modeset(crtc_state); |
11828 | bool was_crtc_enabled = crtc->state->active; | |
11829 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11830 | bool turn_off, turn_on, visible, was_visible; |
11831 | struct drm_framebuffer *fb = plane_state->fb; | |
11832 | ||
11833 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11834 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11835 | ret = skl_update_scaler_plane( | |
11836 | to_intel_crtc_state(crtc_state), | |
11837 | to_intel_plane_state(plane_state)); | |
11838 | if (ret) | |
11839 | return ret; | |
11840 | } | |
11841 | ||
da20eabd ML |
11842 | was_visible = old_plane_state->visible; |
11843 | visible = to_intel_plane_state(plane_state)->visible; | |
11844 | ||
11845 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11846 | was_visible = false; | |
11847 | ||
35c08f43 ML |
11848 | /* |
11849 | * Visibility is calculated as if the crtc was on, but | |
11850 | * after scaler setup everything depends on it being off | |
11851 | * when the crtc isn't active. | |
11852 | */ | |
11853 | if (!is_crtc_enabled) | |
11854 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11855 | |
11856 | if (!was_visible && !visible) | |
11857 | return 0; | |
11858 | ||
e8861675 ML |
11859 | if (fb != old_plane_state->base.fb) |
11860 | pipe_config->fb_changed = true; | |
11861 | ||
da20eabd ML |
11862 | turn_off = was_visible && (!visible || mode_changed); |
11863 | turn_on = visible && (!was_visible || mode_changed); | |
11864 | ||
11865 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11866 | plane->base.id, fb ? fb->base.id : -1); | |
11867 | ||
11868 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11869 | plane->base.id, was_visible, visible, | |
11870 | turn_off, turn_on, mode_changed); | |
11871 | ||
92826fcd ML |
11872 | if (turn_on || turn_off) { |
11873 | pipe_config->wm_changed = true; | |
11874 | ||
852eb00d | 11875 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11876 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11877 | pipe_config->disable_cxsr = true; |
852eb00d | 11878 | } else if (intel_wm_need_update(plane, plane_state)) { |
92826fcd | 11879 | pipe_config->wm_changed = true; |
852eb00d | 11880 | } |
da20eabd | 11881 | |
ed4a6a7c MR |
11882 | /* Pre-gen9 platforms need two-step watermark updates */ |
11883 | if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 && | |
11884 | dev_priv->display.optimize_watermarks) | |
11885 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; | |
11886 | ||
8be6ca85 | 11887 | if (visible || was_visible) |
a9ff8714 VS |
11888 | intel_crtc->atomic.fb_bits |= |
11889 | to_intel_plane(plane)->frontbuffer_bit; | |
11890 | ||
da20eabd ML |
11891 | switch (plane->type) { |
11892 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd | 11893 | intel_crtc->atomic.post_enable_primary = turn_on; |
fcf38d13 | 11894 | intel_crtc->atomic.update_fbc = true; |
da20eabd | 11895 | |
da20eabd ML |
11896 | break; |
11897 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11898 | break; |
11899 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11900 | /* |
11901 | * WaCxSRDisabledForSpriteScaling:ivb | |
11902 | * | |
11903 | * cstate->update_wm was already set above, so this flag will | |
11904 | * take effect when we commit and program watermarks. | |
11905 | */ | |
11906 | if (IS_IVYBRIDGE(dev) && | |
11907 | needs_scaling(to_intel_plane_state(plane_state)) && | |
e8861675 ML |
11908 | !needs_scaling(old_plane_state)) |
11909 | pipe_config->disable_lp_wm = true; | |
d21fbe87 MR |
11910 | |
11911 | break; | |
da20eabd ML |
11912 | } |
11913 | return 0; | |
11914 | } | |
11915 | ||
6d3a1ce7 ML |
11916 | static bool encoders_cloneable(const struct intel_encoder *a, |
11917 | const struct intel_encoder *b) | |
11918 | { | |
11919 | /* masks could be asymmetric, so check both ways */ | |
11920 | return a == b || (a->cloneable & (1 << b->type) && | |
11921 | b->cloneable & (1 << a->type)); | |
11922 | } | |
11923 | ||
11924 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11925 | struct intel_crtc *crtc, | |
11926 | struct intel_encoder *encoder) | |
11927 | { | |
11928 | struct intel_encoder *source_encoder; | |
11929 | struct drm_connector *connector; | |
11930 | struct drm_connector_state *connector_state; | |
11931 | int i; | |
11932 | ||
11933 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11934 | if (connector_state->crtc != &crtc->base) | |
11935 | continue; | |
11936 | ||
11937 | source_encoder = | |
11938 | to_intel_encoder(connector_state->best_encoder); | |
11939 | if (!encoders_cloneable(encoder, source_encoder)) | |
11940 | return false; | |
11941 | } | |
11942 | ||
11943 | return true; | |
11944 | } | |
11945 | ||
11946 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11947 | struct intel_crtc *crtc) | |
11948 | { | |
11949 | struct intel_encoder *encoder; | |
11950 | struct drm_connector *connector; | |
11951 | struct drm_connector_state *connector_state; | |
11952 | int i; | |
11953 | ||
11954 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11955 | if (connector_state->crtc != &crtc->base) | |
11956 | continue; | |
11957 | ||
11958 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11959 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11960 | return false; | |
11961 | } | |
11962 | ||
11963 | return true; | |
11964 | } | |
11965 | ||
11966 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11967 | struct drm_crtc_state *crtc_state) | |
11968 | { | |
cf5a15be | 11969 | struct drm_device *dev = crtc->dev; |
ad421372 | 11970 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11972 | struct intel_crtc_state *pipe_config = |
11973 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11974 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11975 | int ret; |
6d3a1ce7 ML |
11976 | bool mode_changed = needs_modeset(crtc_state); |
11977 | ||
11978 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11979 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11980 | return -EINVAL; | |
11981 | } | |
11982 | ||
852eb00d | 11983 | if (mode_changed && !crtc_state->active) |
92826fcd | 11984 | pipe_config->wm_changed = true; |
eddfcbcd | 11985 | |
ad421372 ML |
11986 | if (mode_changed && crtc_state->enable && |
11987 | dev_priv->display.crtc_compute_clock && | |
11988 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11989 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11990 | pipe_config); | |
11991 | if (ret) | |
11992 | return ret; | |
11993 | } | |
11994 | ||
e435d6e5 | 11995 | ret = 0; |
86c8bbbe MR |
11996 | if (dev_priv->display.compute_pipe_wm) { |
11997 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
ed4a6a7c MR |
11998 | if (ret) { |
11999 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12000 | return ret; | |
12001 | } | |
12002 | } | |
12003 | ||
12004 | if (dev_priv->display.compute_intermediate_wm && | |
12005 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12006 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12007 | return 0; | |
12008 | ||
12009 | /* | |
12010 | * Calculate 'intermediate' watermarks that satisfy both the | |
12011 | * old state and the new state. We can program these | |
12012 | * immediately. | |
12013 | */ | |
12014 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12015 | intel_crtc, | |
12016 | pipe_config); | |
12017 | if (ret) { | |
12018 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12019 | return ret; |
ed4a6a7c | 12020 | } |
86c8bbbe MR |
12021 | } |
12022 | ||
e435d6e5 ML |
12023 | if (INTEL_INFO(dev)->gen >= 9) { |
12024 | if (mode_changed) | |
12025 | ret = skl_update_scaler_crtc(pipe_config); | |
12026 | ||
12027 | if (!ret) | |
12028 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12029 | pipe_config); | |
12030 | } | |
12031 | ||
12032 | return ret; | |
6d3a1ce7 ML |
12033 | } |
12034 | ||
65b38e0d | 12035 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12036 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12037 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12038 | .atomic_begin = intel_begin_crtc_commit, |
12039 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12040 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12041 | }; |
12042 | ||
d29b2f9d ACO |
12043 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12044 | { | |
12045 | struct intel_connector *connector; | |
12046 | ||
12047 | for_each_intel_connector(dev, connector) { | |
12048 | if (connector->base.encoder) { | |
12049 | connector->base.state->best_encoder = | |
12050 | connector->base.encoder; | |
12051 | connector->base.state->crtc = | |
12052 | connector->base.encoder->crtc; | |
12053 | } else { | |
12054 | connector->base.state->best_encoder = NULL; | |
12055 | connector->base.state->crtc = NULL; | |
12056 | } | |
12057 | } | |
12058 | } | |
12059 | ||
050f7aeb | 12060 | static void |
eba905b2 | 12061 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12062 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12063 | { |
12064 | int bpp = pipe_config->pipe_bpp; | |
12065 | ||
12066 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12067 | connector->base.base.id, | |
c23cc417 | 12068 | connector->base.name); |
050f7aeb DV |
12069 | |
12070 | /* Don't use an invalid EDID bpc value */ | |
12071 | if (connector->base.display_info.bpc && | |
12072 | connector->base.display_info.bpc * 3 < bpp) { | |
12073 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12074 | bpp, connector->base.display_info.bpc*3); | |
12075 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12076 | } | |
12077 | ||
013dd9e0 JN |
12078 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12079 | if (connector->base.display_info.bpc == 0) { | |
12080 | int type = connector->base.connector_type; | |
12081 | int clamp_bpp = 24; | |
12082 | ||
12083 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12084 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12085 | type == DRM_MODE_CONNECTOR_eDP) | |
12086 | clamp_bpp = 18; | |
12087 | ||
12088 | if (bpp > clamp_bpp) { | |
12089 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12090 | bpp, clamp_bpp); | |
12091 | pipe_config->pipe_bpp = clamp_bpp; | |
12092 | } | |
050f7aeb DV |
12093 | } |
12094 | } | |
12095 | ||
4e53c2e0 | 12096 | static int |
050f7aeb | 12097 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12098 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12099 | { |
050f7aeb | 12100 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12101 | struct drm_atomic_state *state; |
da3ced29 ACO |
12102 | struct drm_connector *connector; |
12103 | struct drm_connector_state *connector_state; | |
1486017f | 12104 | int bpp, i; |
4e53c2e0 | 12105 | |
666a4537 | 12106 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12107 | bpp = 10*3; |
d328c9d7 DV |
12108 | else if (INTEL_INFO(dev)->gen >= 5) |
12109 | bpp = 12*3; | |
12110 | else | |
12111 | bpp = 8*3; | |
12112 | ||
4e53c2e0 | 12113 | |
4e53c2e0 DV |
12114 | pipe_config->pipe_bpp = bpp; |
12115 | ||
1486017f ACO |
12116 | state = pipe_config->base.state; |
12117 | ||
4e53c2e0 | 12118 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12119 | for_each_connector_in_state(state, connector, connector_state, i) { |
12120 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12121 | continue; |
12122 | ||
da3ced29 ACO |
12123 | connected_sink_compute_bpp(to_intel_connector(connector), |
12124 | pipe_config); | |
4e53c2e0 DV |
12125 | } |
12126 | ||
12127 | return bpp; | |
12128 | } | |
12129 | ||
644db711 DV |
12130 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12131 | { | |
12132 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12133 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12134 | mode->crtc_clock, |
644db711 DV |
12135 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12136 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12137 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12138 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12139 | } | |
12140 | ||
c0b03411 | 12141 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12142 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12143 | const char *context) |
12144 | { | |
6a60cd87 CK |
12145 | struct drm_device *dev = crtc->base.dev; |
12146 | struct drm_plane *plane; | |
12147 | struct intel_plane *intel_plane; | |
12148 | struct intel_plane_state *state; | |
12149 | struct drm_framebuffer *fb; | |
12150 | ||
12151 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12152 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12153 | |
12154 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12155 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12156 | pipe_config->pipe_bpp, pipe_config->dither); | |
12157 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12158 | pipe_config->has_pch_encoder, | |
12159 | pipe_config->fdi_lanes, | |
12160 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12161 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12162 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12163 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12164 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12165 | pipe_config->lane_count, |
eb14cb74 VS |
12166 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12167 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12168 | pipe_config->dp_m_n.tu); | |
b95af8be | 12169 | |
90a6b7b0 | 12170 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12171 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12172 | pipe_config->lane_count, |
b95af8be VK |
12173 | pipe_config->dp_m2_n2.gmch_m, |
12174 | pipe_config->dp_m2_n2.gmch_n, | |
12175 | pipe_config->dp_m2_n2.link_m, | |
12176 | pipe_config->dp_m2_n2.link_n, | |
12177 | pipe_config->dp_m2_n2.tu); | |
12178 | ||
55072d19 DV |
12179 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12180 | pipe_config->has_audio, | |
12181 | pipe_config->has_infoframe); | |
12182 | ||
c0b03411 | 12183 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12184 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12185 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12186 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12187 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12188 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12189 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12190 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12191 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12192 | crtc->num_scalers, | |
12193 | pipe_config->scaler_state.scaler_users, | |
12194 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12195 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12196 | pipe_config->gmch_pfit.control, | |
12197 | pipe_config->gmch_pfit.pgm_ratios, | |
12198 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12199 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12200 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12201 | pipe_config->pch_pfit.size, |
12202 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12203 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12204 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12205 | |
415ff0f6 | 12206 | if (IS_BROXTON(dev)) { |
05712c15 | 12207 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12208 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12209 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12210 | pipe_config->ddi_pll_sel, |
12211 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12212 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12213 | pipe_config->dpll_hw_state.pll0, |
12214 | pipe_config->dpll_hw_state.pll1, | |
12215 | pipe_config->dpll_hw_state.pll2, | |
12216 | pipe_config->dpll_hw_state.pll3, | |
12217 | pipe_config->dpll_hw_state.pll6, | |
12218 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12219 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12220 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12221 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12222 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12223 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12224 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12225 | pipe_config->ddi_pll_sel, | |
12226 | pipe_config->dpll_hw_state.ctrl1, | |
12227 | pipe_config->dpll_hw_state.cfgcr1, | |
12228 | pipe_config->dpll_hw_state.cfgcr2); | |
12229 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12230 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12231 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12232 | pipe_config->dpll_hw_state.wrpll, |
12233 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12234 | } else { |
12235 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12236 | "fp0: 0x%x, fp1: 0x%x\n", | |
12237 | pipe_config->dpll_hw_state.dpll, | |
12238 | pipe_config->dpll_hw_state.dpll_md, | |
12239 | pipe_config->dpll_hw_state.fp0, | |
12240 | pipe_config->dpll_hw_state.fp1); | |
12241 | } | |
12242 | ||
6a60cd87 CK |
12243 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12244 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12245 | intel_plane = to_intel_plane(plane); | |
12246 | if (intel_plane->pipe != crtc->pipe) | |
12247 | continue; | |
12248 | ||
12249 | state = to_intel_plane_state(plane->state); | |
12250 | fb = state->base.fb; | |
12251 | if (!fb) { | |
12252 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12253 | "disabled, scaler_id = %d\n", | |
12254 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12255 | plane->base.id, intel_plane->pipe, | |
12256 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12257 | drm_plane_index(plane), state->scaler_id); | |
12258 | continue; | |
12259 | } | |
12260 | ||
12261 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12262 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12263 | plane->base.id, intel_plane->pipe, | |
12264 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12265 | drm_plane_index(plane)); | |
12266 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12267 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12268 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12269 | state->scaler_id, | |
12270 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12271 | drm_rect_width(&state->src) >> 16, | |
12272 | drm_rect_height(&state->src) >> 16, | |
12273 | state->dst.x1, state->dst.y1, | |
12274 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12275 | } | |
c0b03411 DV |
12276 | } |
12277 | ||
5448a00d | 12278 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12279 | { |
5448a00d | 12280 | struct drm_device *dev = state->dev; |
da3ced29 | 12281 | struct drm_connector *connector; |
00f0b378 VS |
12282 | unsigned int used_ports = 0; |
12283 | ||
12284 | /* | |
12285 | * Walk the connector list instead of the encoder | |
12286 | * list to detect the problem on ddi platforms | |
12287 | * where there's just one encoder per digital port. | |
12288 | */ | |
0bff4858 VS |
12289 | drm_for_each_connector(connector, dev) { |
12290 | struct drm_connector_state *connector_state; | |
12291 | struct intel_encoder *encoder; | |
12292 | ||
12293 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12294 | if (!connector_state) | |
12295 | connector_state = connector->state; | |
12296 | ||
5448a00d | 12297 | if (!connector_state->best_encoder) |
00f0b378 VS |
12298 | continue; |
12299 | ||
5448a00d ACO |
12300 | encoder = to_intel_encoder(connector_state->best_encoder); |
12301 | ||
12302 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12303 | |
12304 | switch (encoder->type) { | |
12305 | unsigned int port_mask; | |
12306 | case INTEL_OUTPUT_UNKNOWN: | |
12307 | if (WARN_ON(!HAS_DDI(dev))) | |
12308 | break; | |
12309 | case INTEL_OUTPUT_DISPLAYPORT: | |
12310 | case INTEL_OUTPUT_HDMI: | |
12311 | case INTEL_OUTPUT_EDP: | |
12312 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12313 | ||
12314 | /* the same port mustn't appear more than once */ | |
12315 | if (used_ports & port_mask) | |
12316 | return false; | |
12317 | ||
12318 | used_ports |= port_mask; | |
12319 | default: | |
12320 | break; | |
12321 | } | |
12322 | } | |
12323 | ||
12324 | return true; | |
12325 | } | |
12326 | ||
83a57153 ACO |
12327 | static void |
12328 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12329 | { | |
12330 | struct drm_crtc_state tmp_state; | |
663a3640 | 12331 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12332 | struct intel_dpll_hw_state dpll_hw_state; |
12333 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12334 | uint32_t ddi_pll_sel; |
c4e2d043 | 12335 | bool force_thru; |
83a57153 | 12336 | |
7546a384 ACO |
12337 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12338 | * kzalloc'd. Code that depends on any field being zero should be | |
12339 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12340 | * only fields that are know to not cause problems are preserved. */ | |
12341 | ||
83a57153 | 12342 | tmp_state = crtc_state->base; |
663a3640 | 12343 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12344 | shared_dpll = crtc_state->shared_dpll; |
12345 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12346 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12347 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12348 | |
83a57153 | 12349 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12350 | |
83a57153 | 12351 | crtc_state->base = tmp_state; |
663a3640 | 12352 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12353 | crtc_state->shared_dpll = shared_dpll; |
12354 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12355 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12356 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12357 | } |
12358 | ||
548ee15b | 12359 | static int |
b8cecdf5 | 12360 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12361 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12362 | { |
b359283a | 12363 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12364 | struct intel_encoder *encoder; |
da3ced29 | 12365 | struct drm_connector *connector; |
0b901879 | 12366 | struct drm_connector_state *connector_state; |
d328c9d7 | 12367 | int base_bpp, ret = -EINVAL; |
0b901879 | 12368 | int i; |
e29c22c0 | 12369 | bool retry = true; |
ee7b9f93 | 12370 | |
83a57153 | 12371 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12372 | |
e143a21c DV |
12373 | pipe_config->cpu_transcoder = |
12374 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12375 | |
2960bc9c ID |
12376 | /* |
12377 | * Sanitize sync polarity flags based on requested ones. If neither | |
12378 | * positive or negative polarity is requested, treat this as meaning | |
12379 | * negative polarity. | |
12380 | */ | |
2d112de7 | 12381 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12382 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12383 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12384 | |
2d112de7 | 12385 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12386 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12387 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12388 | |
d328c9d7 DV |
12389 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12390 | pipe_config); | |
12391 | if (base_bpp < 0) | |
4e53c2e0 DV |
12392 | goto fail; |
12393 | ||
e41a56be VS |
12394 | /* |
12395 | * Determine the real pipe dimensions. Note that stereo modes can | |
12396 | * increase the actual pipe size due to the frame doubling and | |
12397 | * insertion of additional space for blanks between the frame. This | |
12398 | * is stored in the crtc timings. We use the requested mode to do this | |
12399 | * computation to clearly distinguish it from the adjusted mode, which | |
12400 | * can be changed by the connectors in the below retry loop. | |
12401 | */ | |
2d112de7 | 12402 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12403 | &pipe_config->pipe_src_w, |
12404 | &pipe_config->pipe_src_h); | |
e41a56be | 12405 | |
e29c22c0 | 12406 | encoder_retry: |
ef1b460d | 12407 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12408 | pipe_config->port_clock = 0; |
ef1b460d | 12409 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12410 | |
135c81b8 | 12411 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12412 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12413 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12414 | |
7758a113 DV |
12415 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12416 | * adjust it according to limitations or connector properties, and also | |
12417 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12418 | */ |
da3ced29 | 12419 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12420 | if (connector_state->crtc != crtc) |
7758a113 | 12421 | continue; |
7ae89233 | 12422 | |
0b901879 ACO |
12423 | encoder = to_intel_encoder(connector_state->best_encoder); |
12424 | ||
efea6e8e DV |
12425 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12426 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12427 | goto fail; |
12428 | } | |
ee7b9f93 | 12429 | } |
47f1c6c9 | 12430 | |
ff9a6750 DV |
12431 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12432 | * done afterwards in case the encoder adjusts the mode. */ | |
12433 | if (!pipe_config->port_clock) | |
2d112de7 | 12434 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12435 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12436 | |
a43f6e0f | 12437 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12438 | if (ret < 0) { |
7758a113 DV |
12439 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12440 | goto fail; | |
ee7b9f93 | 12441 | } |
e29c22c0 DV |
12442 | |
12443 | if (ret == RETRY) { | |
12444 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12445 | ret = -EINVAL; | |
12446 | goto fail; | |
12447 | } | |
12448 | ||
12449 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12450 | retry = false; | |
12451 | goto encoder_retry; | |
12452 | } | |
12453 | ||
e8fa4270 DV |
12454 | /* Dithering seems to not pass-through bits correctly when it should, so |
12455 | * only enable it on 6bpc panels. */ | |
12456 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12457 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12458 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12459 | |
7758a113 | 12460 | fail: |
548ee15b | 12461 | return ret; |
ee7b9f93 | 12462 | } |
47f1c6c9 | 12463 | |
ea9d758d | 12464 | static void |
4740b0f2 | 12465 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12466 | { |
0a9ab303 ACO |
12467 | struct drm_crtc *crtc; |
12468 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12469 | int i; |
ea9d758d | 12470 | |
7668851f | 12471 | /* Double check state. */ |
8a75d157 | 12472 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12473 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12474 | |
12475 | /* Update hwmode for vblank functions */ | |
12476 | if (crtc->state->active) | |
12477 | crtc->hwmode = crtc->state->adjusted_mode; | |
12478 | else | |
12479 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12480 | |
12481 | /* | |
12482 | * Update legacy state to satisfy fbc code. This can | |
12483 | * be removed when fbc uses the atomic state. | |
12484 | */ | |
12485 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12486 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12487 | ||
12488 | crtc->primary->fb = plane_state->fb; | |
12489 | crtc->x = plane_state->src_x >> 16; | |
12490 | crtc->y = plane_state->src_y >> 16; | |
12491 | } | |
ea9d758d | 12492 | } |
ea9d758d DV |
12493 | } |
12494 | ||
3bd26263 | 12495 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12496 | { |
3bd26263 | 12497 | int diff; |
f1f644dc JB |
12498 | |
12499 | if (clock1 == clock2) | |
12500 | return true; | |
12501 | ||
12502 | if (!clock1 || !clock2) | |
12503 | return false; | |
12504 | ||
12505 | diff = abs(clock1 - clock2); | |
12506 | ||
12507 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12508 | return true; | |
12509 | ||
12510 | return false; | |
12511 | } | |
12512 | ||
25c5b266 DV |
12513 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12514 | list_for_each_entry((intel_crtc), \ | |
12515 | &(dev)->mode_config.crtc_list, \ | |
12516 | base.head) \ | |
95150bdf | 12517 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12518 | |
cfb23ed6 ML |
12519 | static bool |
12520 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12521 | unsigned int m2, unsigned int n2, | |
12522 | bool exact) | |
12523 | { | |
12524 | if (m == m2 && n == n2) | |
12525 | return true; | |
12526 | ||
12527 | if (exact || !m || !n || !m2 || !n2) | |
12528 | return false; | |
12529 | ||
12530 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12531 | ||
31d10b57 ML |
12532 | if (n > n2) { |
12533 | while (n > n2) { | |
cfb23ed6 ML |
12534 | m2 <<= 1; |
12535 | n2 <<= 1; | |
12536 | } | |
31d10b57 ML |
12537 | } else if (n < n2) { |
12538 | while (n < n2) { | |
cfb23ed6 ML |
12539 | m <<= 1; |
12540 | n <<= 1; | |
12541 | } | |
12542 | } | |
12543 | ||
31d10b57 ML |
12544 | if (n != n2) |
12545 | return false; | |
12546 | ||
12547 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12548 | } |
12549 | ||
12550 | static bool | |
12551 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12552 | struct intel_link_m_n *m2_n2, | |
12553 | bool adjust) | |
12554 | { | |
12555 | if (m_n->tu == m2_n2->tu && | |
12556 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12557 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12558 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12559 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12560 | if (adjust) | |
12561 | *m2_n2 = *m_n; | |
12562 | ||
12563 | return true; | |
12564 | } | |
12565 | ||
12566 | return false; | |
12567 | } | |
12568 | ||
0e8ffe1b | 12569 | static bool |
2fa2fe9a | 12570 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12571 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12572 | struct intel_crtc_state *pipe_config, |
12573 | bool adjust) | |
0e8ffe1b | 12574 | { |
cfb23ed6 ML |
12575 | bool ret = true; |
12576 | ||
12577 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12578 | do { \ | |
12579 | if (!adjust) \ | |
12580 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12581 | else \ | |
12582 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12583 | } while (0) | |
12584 | ||
66e985c0 DV |
12585 | #define PIPE_CONF_CHECK_X(name) \ |
12586 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12587 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12588 | "(expected 0x%08x, found 0x%08x)\n", \ |
12589 | current_config->name, \ | |
12590 | pipe_config->name); \ | |
cfb23ed6 | 12591 | ret = false; \ |
66e985c0 DV |
12592 | } |
12593 | ||
08a24034 DV |
12594 | #define PIPE_CONF_CHECK_I(name) \ |
12595 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12596 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12597 | "(expected %i, found %i)\n", \ |
12598 | current_config->name, \ | |
12599 | pipe_config->name); \ | |
cfb23ed6 ML |
12600 | ret = false; \ |
12601 | } | |
12602 | ||
12603 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12604 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12605 | &pipe_config->name,\ | |
12606 | adjust)) { \ | |
12607 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12608 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12609 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12610 | current_config->name.tu, \ | |
12611 | current_config->name.gmch_m, \ | |
12612 | current_config->name.gmch_n, \ | |
12613 | current_config->name.link_m, \ | |
12614 | current_config->name.link_n, \ | |
12615 | pipe_config->name.tu, \ | |
12616 | pipe_config->name.gmch_m, \ | |
12617 | pipe_config->name.gmch_n, \ | |
12618 | pipe_config->name.link_m, \ | |
12619 | pipe_config->name.link_n); \ | |
12620 | ret = false; \ | |
12621 | } | |
12622 | ||
12623 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12624 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12625 | &pipe_config->name, adjust) && \ | |
12626 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12627 | &pipe_config->name, adjust)) { \ | |
12628 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12629 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12630 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12631 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12632 | current_config->name.tu, \ | |
12633 | current_config->name.gmch_m, \ | |
12634 | current_config->name.gmch_n, \ | |
12635 | current_config->name.link_m, \ | |
12636 | current_config->name.link_n, \ | |
12637 | current_config->alt_name.tu, \ | |
12638 | current_config->alt_name.gmch_m, \ | |
12639 | current_config->alt_name.gmch_n, \ | |
12640 | current_config->alt_name.link_m, \ | |
12641 | current_config->alt_name.link_n, \ | |
12642 | pipe_config->name.tu, \ | |
12643 | pipe_config->name.gmch_m, \ | |
12644 | pipe_config->name.gmch_n, \ | |
12645 | pipe_config->name.link_m, \ | |
12646 | pipe_config->name.link_n); \ | |
12647 | ret = false; \ | |
88adfff1 DV |
12648 | } |
12649 | ||
b95af8be VK |
12650 | /* This is required for BDW+ where there is only one set of registers for |
12651 | * switching between high and low RR. | |
12652 | * This macro can be used whenever a comparison has to be made between one | |
12653 | * hw state and multiple sw state variables. | |
12654 | */ | |
12655 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12656 | if ((current_config->name != pipe_config->name) && \ | |
12657 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12658 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12659 | "(expected %i or %i, found %i)\n", \ |
12660 | current_config->name, \ | |
12661 | current_config->alt_name, \ | |
12662 | pipe_config->name); \ | |
cfb23ed6 | 12663 | ret = false; \ |
b95af8be VK |
12664 | } |
12665 | ||
1bd1bd80 DV |
12666 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12667 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12668 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12669 | "(expected %i, found %i)\n", \ |
12670 | current_config->name & (mask), \ | |
12671 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12672 | ret = false; \ |
1bd1bd80 DV |
12673 | } |
12674 | ||
5e550656 VS |
12675 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12676 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12677 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12678 | "(expected %i, found %i)\n", \ |
12679 | current_config->name, \ | |
12680 | pipe_config->name); \ | |
cfb23ed6 | 12681 | ret = false; \ |
5e550656 VS |
12682 | } |
12683 | ||
bb760063 DV |
12684 | #define PIPE_CONF_QUIRK(quirk) \ |
12685 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12686 | ||
eccb140b DV |
12687 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12688 | ||
08a24034 DV |
12689 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12690 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12691 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12692 | |
eb14cb74 | 12693 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12694 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12695 | |
12696 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12697 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12698 | ||
cfb23ed6 ML |
12699 | if (current_config->has_drrs) |
12700 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12701 | } else | |
12702 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12703 | |
a65347ba JN |
12704 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12705 | ||
2d112de7 ACO |
12706 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12707 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12708 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12709 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12710 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12711 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12712 | |
2d112de7 ACO |
12713 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12714 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12715 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12716 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12717 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12718 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12719 | |
c93f54cf | 12720 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12721 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12722 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12723 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12724 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12725 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12726 | |
9ed109a7 DV |
12727 | PIPE_CONF_CHECK_I(has_audio); |
12728 | ||
2d112de7 | 12729 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12730 | DRM_MODE_FLAG_INTERLACE); |
12731 | ||
bb760063 | 12732 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12733 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12734 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12735 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12736 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12737 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12738 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12739 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12740 | DRM_MODE_FLAG_NVSYNC); |
12741 | } | |
045ac3b5 | 12742 | |
333b8ca8 | 12743 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12744 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12745 | if (INTEL_INFO(dev)->gen < 4) | |
12746 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12747 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12748 | |
bfd16b2a ML |
12749 | if (!adjust) { |
12750 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12751 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12752 | ||
12753 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12754 | if (current_config->pch_pfit.enabled) { | |
12755 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12756 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12757 | } | |
2fa2fe9a | 12758 | |
7aefe2b5 ML |
12759 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12760 | } | |
a1b2278e | 12761 | |
e59150dc JB |
12762 | /* BDW+ don't expose a synchronous way to read the state */ |
12763 | if (IS_HASWELL(dev)) | |
12764 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12765 | |
282740f7 VS |
12766 | PIPE_CONF_CHECK_I(double_wide); |
12767 | ||
26804afd DV |
12768 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12769 | ||
c0d43d62 | 12770 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12771 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12772 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12773 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12774 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12775 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12776 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12777 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12778 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12779 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12780 | |
42571aef VS |
12781 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12782 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12783 | ||
2d112de7 | 12784 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12785 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12786 | |
66e985c0 | 12787 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12788 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12789 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12790 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12791 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12792 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12793 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12794 | |
cfb23ed6 | 12795 | return ret; |
0e8ffe1b DV |
12796 | } |
12797 | ||
08db6652 DL |
12798 | static void check_wm_state(struct drm_device *dev) |
12799 | { | |
12800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12801 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12802 | struct intel_crtc *intel_crtc; | |
12803 | int plane; | |
12804 | ||
12805 | if (INTEL_INFO(dev)->gen < 9) | |
12806 | return; | |
12807 | ||
12808 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12809 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12810 | ||
12811 | for_each_intel_crtc(dev, intel_crtc) { | |
12812 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12813 | const enum pipe pipe = intel_crtc->pipe; | |
12814 | ||
12815 | if (!intel_crtc->active) | |
12816 | continue; | |
12817 | ||
12818 | /* planes */ | |
dd740780 | 12819 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12820 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12821 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12822 | ||
12823 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12824 | continue; | |
12825 | ||
12826 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12827 | "(expected (%u,%u), found (%u,%u))\n", | |
12828 | pipe_name(pipe), plane + 1, | |
12829 | sw_entry->start, sw_entry->end, | |
12830 | hw_entry->start, hw_entry->end); | |
12831 | } | |
12832 | ||
12833 | /* cursor */ | |
4969d33e MR |
12834 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12835 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12836 | |
12837 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12838 | continue; | |
12839 | ||
12840 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12841 | "(expected (%u,%u), found (%u,%u))\n", | |
12842 | pipe_name(pipe), | |
12843 | sw_entry->start, sw_entry->end, | |
12844 | hw_entry->start, hw_entry->end); | |
12845 | } | |
12846 | } | |
12847 | ||
91d1b4bd | 12848 | static void |
35dd3c64 ML |
12849 | check_connector_state(struct drm_device *dev, |
12850 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12851 | { |
35dd3c64 ML |
12852 | struct drm_connector_state *old_conn_state; |
12853 | struct drm_connector *connector; | |
12854 | int i; | |
8af6cf88 | 12855 | |
35dd3c64 ML |
12856 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12857 | struct drm_encoder *encoder = connector->encoder; | |
12858 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12859 | |
8af6cf88 DV |
12860 | /* This also checks the encoder/connector hw state with the |
12861 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12862 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12863 | |
ad3c558f | 12864 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12865 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12866 | } |
91d1b4bd DV |
12867 | } |
12868 | ||
12869 | static void | |
12870 | check_encoder_state(struct drm_device *dev) | |
12871 | { | |
12872 | struct intel_encoder *encoder; | |
12873 | struct intel_connector *connector; | |
8af6cf88 | 12874 | |
b2784e15 | 12875 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12876 | bool enabled = false; |
4d20cd86 | 12877 | enum pipe pipe; |
8af6cf88 DV |
12878 | |
12879 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12880 | encoder->base.base.id, | |
8e329a03 | 12881 | encoder->base.name); |
8af6cf88 | 12882 | |
3a3371ff | 12883 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12884 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12885 | continue; |
12886 | enabled = true; | |
ad3c558f ML |
12887 | |
12888 | I915_STATE_WARN(connector->base.state->crtc != | |
12889 | encoder->base.crtc, | |
12890 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12891 | } |
0e32b39c | 12892 | |
e2c719b7 | 12893 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12894 | "encoder's enabled state mismatch " |
12895 | "(expected %i, found %i)\n", | |
12896 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12897 | |
12898 | if (!encoder->base.crtc) { | |
4d20cd86 | 12899 | bool active; |
7c60d198 | 12900 | |
4d20cd86 ML |
12901 | active = encoder->get_hw_state(encoder, &pipe); |
12902 | I915_STATE_WARN(active, | |
12903 | "encoder detached but still enabled on pipe %c.\n", | |
12904 | pipe_name(pipe)); | |
7c60d198 | 12905 | } |
8af6cf88 | 12906 | } |
91d1b4bd DV |
12907 | } |
12908 | ||
12909 | static void | |
4d20cd86 | 12910 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12911 | { |
fbee40df | 12912 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12913 | struct intel_encoder *encoder; |
4d20cd86 ML |
12914 | struct drm_crtc_state *old_crtc_state; |
12915 | struct drm_crtc *crtc; | |
12916 | int i; | |
8af6cf88 | 12917 | |
4d20cd86 ML |
12918 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12920 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12921 | bool active; |
8af6cf88 | 12922 | |
bfd16b2a ML |
12923 | if (!needs_modeset(crtc->state) && |
12924 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12925 | continue; |
045ac3b5 | 12926 | |
4d20cd86 ML |
12927 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12928 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12929 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12930 | pipe_config->base.crtc = crtc; | |
12931 | pipe_config->base.state = old_state; | |
8af6cf88 | 12932 | |
4d20cd86 ML |
12933 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12934 | crtc->base.id); | |
8af6cf88 | 12935 | |
4d20cd86 ML |
12936 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12937 | pipe_config); | |
d62cf62a | 12938 | |
b6b5d049 | 12939 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12940 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12941 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12942 | active = crtc->state->active; | |
6c49f241 | 12943 | |
4d20cd86 | 12944 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12945 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12946 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12947 | |
4d20cd86 | 12948 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12949 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12950 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12951 | ||
12952 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12953 | enum pipe pipe; | |
12954 | ||
12955 | active = encoder->get_hw_state(encoder, &pipe); | |
12956 | I915_STATE_WARN(active != crtc->state->active, | |
12957 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12958 | encoder->base.base.id, active, crtc->state->active); | |
12959 | ||
12960 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12961 | "Encoder connected to wrong pipe %c\n", | |
12962 | pipe_name(pipe)); | |
12963 | ||
12964 | if (active) | |
12965 | encoder->get_config(encoder, pipe_config); | |
12966 | } | |
53d9f4e9 | 12967 | |
4d20cd86 | 12968 | if (!crtc->state->active) |
cfb23ed6 ML |
12969 | continue; |
12970 | ||
4d20cd86 ML |
12971 | sw_config = to_intel_crtc_state(crtc->state); |
12972 | if (!intel_pipe_config_compare(dev, sw_config, | |
12973 | pipe_config, false)) { | |
e2c719b7 | 12974 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12975 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12976 | "[hw state]"); |
4d20cd86 | 12977 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12978 | "[sw state]"); |
12979 | } | |
8af6cf88 DV |
12980 | } |
12981 | } | |
12982 | ||
91d1b4bd DV |
12983 | static void |
12984 | check_shared_dpll_state(struct drm_device *dev) | |
12985 | { | |
fbee40df | 12986 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12987 | struct intel_crtc *crtc; |
12988 | struct intel_dpll_hw_state dpll_hw_state; | |
12989 | int i; | |
5358901f DV |
12990 | |
12991 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12992 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12993 | int enabled_crtcs = 0, active_crtcs = 0; | |
12994 | bool active; | |
12995 | ||
12996 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12997 | ||
12998 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12999 | ||
13000 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
13001 | ||
e2c719b7 | 13002 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13003 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13004 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13005 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13006 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13007 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13008 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13009 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13010 | "pll on state mismatch (expected %i, found %i)\n", |
13011 | pll->on, active); | |
13012 | ||
d3fcc808 | 13013 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13014 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13015 | enabled_crtcs++; |
13016 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13017 | active_crtcs++; | |
13018 | } | |
e2c719b7 | 13019 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13020 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13021 | pll->active, active_crtcs); | |
e2c719b7 | 13022 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13023 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13024 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13025 | |
e2c719b7 | 13026 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13027 | sizeof(dpll_hw_state)), |
13028 | "pll hw state mismatch\n"); | |
5358901f | 13029 | } |
8af6cf88 DV |
13030 | } |
13031 | ||
ee165b1a ML |
13032 | static void |
13033 | intel_modeset_check_state(struct drm_device *dev, | |
13034 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13035 | { |
08db6652 | 13036 | check_wm_state(dev); |
35dd3c64 | 13037 | check_connector_state(dev, old_state); |
91d1b4bd | 13038 | check_encoder_state(dev); |
4d20cd86 | 13039 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13040 | check_shared_dpll_state(dev); |
13041 | } | |
13042 | ||
5cec258b | 13043 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13044 | int dotclock) |
13045 | { | |
13046 | /* | |
13047 | * FDI already provided one idea for the dotclock. | |
13048 | * Yell if the encoder disagrees. | |
13049 | */ | |
2d112de7 | 13050 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13051 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13052 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13053 | } |
13054 | ||
80715b2f VS |
13055 | static void update_scanline_offset(struct intel_crtc *crtc) |
13056 | { | |
13057 | struct drm_device *dev = crtc->base.dev; | |
13058 | ||
13059 | /* | |
13060 | * The scanline counter increments at the leading edge of hsync. | |
13061 | * | |
13062 | * On most platforms it starts counting from vtotal-1 on the | |
13063 | * first active line. That means the scanline counter value is | |
13064 | * always one less than what we would expect. Ie. just after | |
13065 | * start of vblank, which also occurs at start of hsync (on the | |
13066 | * last active line), the scanline counter will read vblank_start-1. | |
13067 | * | |
13068 | * On gen2 the scanline counter starts counting from 1 instead | |
13069 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13070 | * to keep the value positive), instead of adding one. | |
13071 | * | |
13072 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13073 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13074 | * there's an extra 1 line difference. So we need to add two instead of | |
13075 | * one to the value. | |
13076 | */ | |
13077 | if (IS_GEN2(dev)) { | |
124abe07 | 13078 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13079 | int vtotal; |
13080 | ||
124abe07 VS |
13081 | vtotal = adjusted_mode->crtc_vtotal; |
13082 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13083 | vtotal /= 2; |
13084 | ||
13085 | crtc->scanline_offset = vtotal - 1; | |
13086 | } else if (HAS_DDI(dev) && | |
409ee761 | 13087 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13088 | crtc->scanline_offset = 2; |
13089 | } else | |
13090 | crtc->scanline_offset = 1; | |
13091 | } | |
13092 | ||
ad421372 | 13093 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13094 | { |
225da59b | 13095 | struct drm_device *dev = state->dev; |
ed6739ef | 13096 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13097 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13098 | struct drm_crtc *crtc; |
13099 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13100 | int i; |
ed6739ef ACO |
13101 | |
13102 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13103 | return; |
ed6739ef | 13104 | |
0a9ab303 | 13105 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 ML |
13106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13107 | int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13108 | |
fb1a38a9 | 13109 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13110 | continue; |
13111 | ||
fb1a38a9 ML |
13112 | to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE; |
13113 | ||
13114 | if (old_dpll == DPLL_ID_PRIVATE) | |
13115 | continue; | |
0a9ab303 | 13116 | |
ad421372 ML |
13117 | if (!shared_dpll) |
13118 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13119 | |
fb1a38a9 | 13120 | shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
ad421372 | 13121 | } |
ed6739ef ACO |
13122 | } |
13123 | ||
99d736a2 ML |
13124 | /* |
13125 | * This implements the workaround described in the "notes" section of the mode | |
13126 | * set sequence documentation. When going from no pipes or single pipe to | |
13127 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13128 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13129 | */ | |
13130 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13131 | { | |
13132 | struct drm_crtc_state *crtc_state; | |
13133 | struct intel_crtc *intel_crtc; | |
13134 | struct drm_crtc *crtc; | |
13135 | struct intel_crtc_state *first_crtc_state = NULL; | |
13136 | struct intel_crtc_state *other_crtc_state = NULL; | |
13137 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13138 | int i; | |
13139 | ||
13140 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13141 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13142 | intel_crtc = to_intel_crtc(crtc); | |
13143 | ||
13144 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13145 | continue; | |
13146 | ||
13147 | if (first_crtc_state) { | |
13148 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13149 | break; | |
13150 | } else { | |
13151 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13152 | first_pipe = intel_crtc->pipe; | |
13153 | } | |
13154 | } | |
13155 | ||
13156 | /* No workaround needed? */ | |
13157 | if (!first_crtc_state) | |
13158 | return 0; | |
13159 | ||
13160 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13161 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13162 | struct intel_crtc_state *pipe_config; | |
13163 | ||
13164 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13165 | if (IS_ERR(pipe_config)) | |
13166 | return PTR_ERR(pipe_config); | |
13167 | ||
13168 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13169 | ||
13170 | if (!pipe_config->base.active || | |
13171 | needs_modeset(&pipe_config->base)) | |
13172 | continue; | |
13173 | ||
13174 | /* 2 or more enabled crtcs means no need for w/a */ | |
13175 | if (enabled_pipe != INVALID_PIPE) | |
13176 | return 0; | |
13177 | ||
13178 | enabled_pipe = intel_crtc->pipe; | |
13179 | } | |
13180 | ||
13181 | if (enabled_pipe != INVALID_PIPE) | |
13182 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13183 | else if (other_crtc_state) | |
13184 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13185 | ||
13186 | return 0; | |
13187 | } | |
13188 | ||
27c329ed ML |
13189 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13190 | { | |
13191 | struct drm_crtc *crtc; | |
13192 | struct drm_crtc_state *crtc_state; | |
13193 | int ret = 0; | |
13194 | ||
13195 | /* add all active pipes to the state */ | |
13196 | for_each_crtc(state->dev, crtc) { | |
13197 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13198 | if (IS_ERR(crtc_state)) | |
13199 | return PTR_ERR(crtc_state); | |
13200 | ||
13201 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13202 | continue; | |
13203 | ||
13204 | crtc_state->mode_changed = true; | |
13205 | ||
13206 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13207 | if (ret) | |
13208 | break; | |
13209 | ||
13210 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13211 | if (ret) | |
13212 | break; | |
13213 | } | |
13214 | ||
13215 | return ret; | |
13216 | } | |
13217 | ||
c347a676 | 13218 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13219 | { |
565602d7 ML |
13220 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13221 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13222 | struct drm_crtc *crtc; | |
13223 | struct drm_crtc_state *crtc_state; | |
13224 | int ret = 0, i; | |
054518dd | 13225 | |
b359283a ML |
13226 | if (!check_digital_port_conflicts(state)) { |
13227 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13228 | return -EINVAL; | |
13229 | } | |
13230 | ||
565602d7 ML |
13231 | intel_state->modeset = true; |
13232 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13233 | ||
13234 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13235 | if (crtc_state->active) | |
13236 | intel_state->active_crtcs |= 1 << i; | |
13237 | else | |
13238 | intel_state->active_crtcs &= ~(1 << i); | |
13239 | } | |
13240 | ||
054518dd ACO |
13241 | /* |
13242 | * See if the config requires any additional preparation, e.g. | |
13243 | * to adjust global state with pipes off. We need to do this | |
13244 | * here so we can get the modeset_pipe updated config for the new | |
13245 | * mode set on this crtc. For other crtcs we need to use the | |
13246 | * adjusted_mode bits in the crtc directly. | |
13247 | */ | |
27c329ed | 13248 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13249 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13250 | ||
1a617b77 | 13251 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13252 | ret = intel_modeset_all_pipes(state); |
13253 | ||
13254 | if (ret < 0) | |
054518dd | 13255 | return ret; |
e8788cbc ML |
13256 | |
13257 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13258 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13259 | } else |
1a617b77 | 13260 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13261 | |
ad421372 | 13262 | intel_modeset_clear_plls(state); |
054518dd | 13263 | |
565602d7 | 13264 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13265 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13266 | |
ad421372 | 13267 | return 0; |
c347a676 ACO |
13268 | } |
13269 | ||
aa363136 MR |
13270 | /* |
13271 | * Handle calculation of various watermark data at the end of the atomic check | |
13272 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13273 | * handlers to ensure that all derived state has been updated. | |
13274 | */ | |
13275 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13276 | { | |
13277 | struct drm_device *dev = state->dev; | |
13278 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13279 | struct drm_crtc *crtc; | |
13280 | struct drm_crtc_state *cstate; | |
13281 | struct drm_plane *plane; | |
13282 | struct drm_plane_state *pstate; | |
13283 | ||
13284 | /* | |
13285 | * Calculate watermark configuration details now that derived | |
13286 | * plane/crtc state is all properly updated. | |
13287 | */ | |
13288 | drm_for_each_crtc(crtc, dev) { | |
13289 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13290 | crtc->state; | |
13291 | ||
13292 | if (cstate->active) | |
13293 | intel_state->wm_config.num_pipes_active++; | |
13294 | } | |
13295 | drm_for_each_legacy_plane(plane, dev) { | |
13296 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13297 | plane->state; | |
13298 | ||
13299 | if (!to_intel_plane_state(pstate)->visible) | |
13300 | continue; | |
13301 | ||
13302 | intel_state->wm_config.sprites_enabled = true; | |
13303 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13304 | pstate->crtc_h != pstate->src_h >> 16) | |
13305 | intel_state->wm_config.sprites_scaled = true; | |
13306 | } | |
13307 | } | |
13308 | ||
74c090b1 ML |
13309 | /** |
13310 | * intel_atomic_check - validate state object | |
13311 | * @dev: drm device | |
13312 | * @state: state to validate | |
13313 | */ | |
13314 | static int intel_atomic_check(struct drm_device *dev, | |
13315 | struct drm_atomic_state *state) | |
c347a676 | 13316 | { |
dd8b3bdb | 13317 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13318 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13319 | struct drm_crtc *crtc; |
13320 | struct drm_crtc_state *crtc_state; | |
13321 | int ret, i; | |
61333b60 | 13322 | bool any_ms = false; |
c347a676 | 13323 | |
74c090b1 | 13324 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13325 | if (ret) |
13326 | return ret; | |
13327 | ||
c347a676 | 13328 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13329 | struct intel_crtc_state *pipe_config = |
13330 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13331 | |
ba8af3e5 ML |
13332 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13333 | sizeof(struct intel_crtc_atomic_commit)); | |
13334 | ||
1ed51de9 DV |
13335 | /* Catch I915_MODE_FLAG_INHERITED */ |
13336 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13337 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13338 | |
61333b60 ML |
13339 | if (!crtc_state->enable) { |
13340 | if (needs_modeset(crtc_state)) | |
13341 | any_ms = true; | |
c347a676 | 13342 | continue; |
61333b60 | 13343 | } |
c347a676 | 13344 | |
26495481 | 13345 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13346 | continue; |
13347 | ||
26495481 DV |
13348 | /* FIXME: For only active_changed we shouldn't need to do any |
13349 | * state recomputation at all. */ | |
13350 | ||
1ed51de9 DV |
13351 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13352 | if (ret) | |
13353 | return ret; | |
b359283a | 13354 | |
cfb23ed6 | 13355 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13356 | if (ret) |
13357 | return ret; | |
13358 | ||
73831236 | 13359 | if (i915.fastboot && |
dd8b3bdb | 13360 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13361 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13362 | pipe_config, true)) { |
26495481 | 13363 | crtc_state->mode_changed = false; |
bfd16b2a | 13364 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13365 | } |
13366 | ||
13367 | if (needs_modeset(crtc_state)) { | |
13368 | any_ms = true; | |
cfb23ed6 ML |
13369 | |
13370 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13371 | if (ret) | |
13372 | return ret; | |
13373 | } | |
61333b60 | 13374 | |
26495481 DV |
13375 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13376 | needs_modeset(crtc_state) ? | |
13377 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13378 | } |
13379 | ||
61333b60 ML |
13380 | if (any_ms) { |
13381 | ret = intel_modeset_checks(state); | |
13382 | ||
13383 | if (ret) | |
13384 | return ret; | |
27c329ed | 13385 | } else |
dd8b3bdb | 13386 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13387 | |
dd8b3bdb | 13388 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13389 | if (ret) |
13390 | return ret; | |
13391 | ||
f51be2e0 | 13392 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13393 | calc_watermark_data(state); |
13394 | ||
13395 | return 0; | |
054518dd ACO |
13396 | } |
13397 | ||
5008e874 ML |
13398 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13399 | struct drm_atomic_state *state, | |
13400 | bool async) | |
13401 | { | |
7580d774 ML |
13402 | struct drm_i915_private *dev_priv = dev->dev_private; |
13403 | struct drm_plane_state *plane_state; | |
5008e874 | 13404 | struct drm_crtc_state *crtc_state; |
7580d774 | 13405 | struct drm_plane *plane; |
5008e874 ML |
13406 | struct drm_crtc *crtc; |
13407 | int i, ret; | |
13408 | ||
13409 | if (async) { | |
13410 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13411 | return -EINVAL; | |
13412 | } | |
13413 | ||
13414 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13415 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13416 | if (ret) | |
13417 | return ret; | |
7580d774 ML |
13418 | |
13419 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13420 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13421 | } |
13422 | ||
f935675f ML |
13423 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13424 | if (ret) | |
13425 | return ret; | |
13426 | ||
5008e874 | 13427 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13428 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13429 | u32 reset_counter; | |
13430 | ||
13431 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13432 | mutex_unlock(&dev->struct_mutex); | |
13433 | ||
13434 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13435 | struct intel_plane_state *intel_plane_state = | |
13436 | to_intel_plane_state(plane_state); | |
13437 | ||
13438 | if (!intel_plane_state->wait_req) | |
13439 | continue; | |
13440 | ||
13441 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13442 | reset_counter, true, | |
13443 | NULL, NULL); | |
13444 | ||
13445 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13446 | if (ret == -EIO) | |
13447 | ret = 0; | |
13448 | ||
13449 | if (ret) | |
13450 | break; | |
13451 | } | |
13452 | ||
13453 | if (!ret) | |
13454 | return 0; | |
13455 | ||
13456 | mutex_lock(&dev->struct_mutex); | |
13457 | drm_atomic_helper_cleanup_planes(dev, state); | |
13458 | } | |
5008e874 | 13459 | |
f935675f | 13460 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13461 | return ret; |
13462 | } | |
13463 | ||
e8861675 ML |
13464 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13465 | struct drm_i915_private *dev_priv, | |
13466 | unsigned crtc_mask) | |
13467 | { | |
13468 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13469 | enum pipe pipe; | |
13470 | int ret; | |
13471 | ||
13472 | if (!crtc_mask) | |
13473 | return; | |
13474 | ||
13475 | for_each_pipe(dev_priv, pipe) { | |
13476 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13477 | ||
13478 | if (!((1 << pipe) & crtc_mask)) | |
13479 | continue; | |
13480 | ||
13481 | ret = drm_crtc_vblank_get(crtc); | |
13482 | if (WARN_ON(ret != 0)) { | |
13483 | crtc_mask &= ~(1 << pipe); | |
13484 | continue; | |
13485 | } | |
13486 | ||
13487 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13488 | } | |
13489 | ||
13490 | for_each_pipe(dev_priv, pipe) { | |
13491 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13492 | long lret; | |
13493 | ||
13494 | if (!((1 << pipe) & crtc_mask)) | |
13495 | continue; | |
13496 | ||
13497 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13498 | last_vblank_count[pipe] != | |
13499 | drm_crtc_vblank_count(crtc), | |
13500 | msecs_to_jiffies(50)); | |
13501 | ||
13502 | WARN_ON(!lret); | |
13503 | ||
13504 | drm_crtc_vblank_put(crtc); | |
13505 | } | |
13506 | } | |
13507 | ||
13508 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13509 | { | |
13510 | /* fb updated, need to unpin old fb */ | |
13511 | if (crtc_state->fb_changed) | |
13512 | return true; | |
13513 | ||
13514 | /* wm changes, need vblank before final wm's */ | |
13515 | if (crtc_state->wm_changed) | |
13516 | return true; | |
13517 | ||
13518 | /* | |
13519 | * cxsr is re-enabled after vblank. | |
13520 | * This is already handled by crtc_state->wm_changed, | |
13521 | * but added for clarity. | |
13522 | */ | |
13523 | if (crtc_state->disable_cxsr) | |
13524 | return true; | |
13525 | ||
13526 | return false; | |
13527 | } | |
13528 | ||
74c090b1 ML |
13529 | /** |
13530 | * intel_atomic_commit - commit validated state object | |
13531 | * @dev: DRM device | |
13532 | * @state: the top-level driver state object | |
13533 | * @async: asynchronous commit | |
13534 | * | |
13535 | * This function commits a top-level state object that has been validated | |
13536 | * with drm_atomic_helper_check(). | |
13537 | * | |
13538 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13539 | * we can only handle plane-related operations and do not yet support | |
13540 | * asynchronous commit. | |
13541 | * | |
13542 | * RETURNS | |
13543 | * Zero for success or -errno. | |
13544 | */ | |
13545 | static int intel_atomic_commit(struct drm_device *dev, | |
13546 | struct drm_atomic_state *state, | |
13547 | bool async) | |
a6778b3c | 13548 | { |
565602d7 | 13549 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13550 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13551 | struct drm_crtc_state *crtc_state; |
7580d774 | 13552 | struct drm_crtc *crtc; |
ed4a6a7c | 13553 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13554 | int ret = 0, i; |
13555 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13556 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13557 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13558 | |
5008e874 | 13559 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13560 | if (ret) { |
13561 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13562 | return ret; |
7580d774 | 13563 | } |
d4afb8cc | 13564 | |
1c5e19f8 | 13565 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13566 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13567 | |
565602d7 ML |
13568 | if (intel_state->modeset) { |
13569 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13570 | sizeof(intel_state->min_pixclk)); | |
13571 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13572 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13573 | |
13574 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13575 | } |
13576 | ||
0a9ab303 | 13577 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13578 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13579 | ||
33c8df89 ML |
13580 | if (needs_modeset(crtc->state) || |
13581 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13582 | hw_check = true; | |
13583 | ||
13584 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13585 | modeset_get_crtc_power_domains(crtc, | |
13586 | to_intel_crtc_state(crtc->state)); | |
13587 | } | |
13588 | ||
61333b60 ML |
13589 | if (!needs_modeset(crtc->state)) |
13590 | continue; | |
13591 | ||
5c74cd73 | 13592 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
460da916 | 13593 | |
a539205a ML |
13594 | if (crtc_state->active) { |
13595 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13596 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd | 13597 | intel_crtc->active = false; |
58f9c0bc | 13598 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13599 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13600 | |
13601 | /* | |
13602 | * Underruns don't always raise | |
13603 | * interrupts, so check manually. | |
13604 | */ | |
13605 | intel_check_cpu_fifo_underruns(dev_priv); | |
13606 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13607 | |
13608 | if (!crtc->state->active) | |
13609 | intel_update_watermarks(crtc); | |
a539205a | 13610 | } |
b8cecdf5 | 13611 | } |
7758a113 | 13612 | |
ea9d758d DV |
13613 | /* Only after disabling all output pipelines that will be changed can we |
13614 | * update the the output configuration. */ | |
4740b0f2 | 13615 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13616 | |
565602d7 | 13617 | if (intel_state->modeset) { |
4740b0f2 ML |
13618 | intel_shared_dpll_commit(state); |
13619 | ||
13620 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
33c8df89 ML |
13621 | |
13622 | if (dev_priv->display.modeset_commit_cdclk && | |
13623 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13624 | dev_priv->display.modeset_commit_cdclk(state); | |
4740b0f2 | 13625 | } |
47fab737 | 13626 | |
a6778b3c | 13627 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13628 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13630 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13631 | struct intel_crtc_state *pipe_config = |
13632 | to_intel_crtc_state(crtc->state); | |
13633 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13634 | |
f6ac4b2a | 13635 | if (modeset && crtc->state->active) { |
a539205a ML |
13636 | update_scanline_offset(to_intel_crtc(crtc)); |
13637 | dev_priv->display.crtc_enable(crtc); | |
13638 | } | |
80715b2f | 13639 | |
f6ac4b2a | 13640 | if (!modeset) |
5c74cd73 | 13641 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
f6ac4b2a | 13642 | |
49227c4a PZ |
13643 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
13644 | intel_fbc_enable(intel_crtc); | |
13645 | ||
6173ee28 ML |
13646 | if (crtc->state->active && |
13647 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13648 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a | 13649 | |
e8861675 ML |
13650 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13651 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13652 | } |
a6778b3c | 13653 | |
a6778b3c | 13654 | /* FIXME: add subpixel order */ |
83a57153 | 13655 | |
e8861675 ML |
13656 | if (!state->legacy_cursor_update) |
13657 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13658 | |
33c8df89 | 13659 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
e8861675 ML |
13660 | intel_post_plane_update(to_intel_crtc(crtc)); |
13661 | ||
33c8df89 ML |
13662 | if (put_domains[i]) |
13663 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13664 | } | |
13665 | ||
13666 | if (intel_state->modeset) | |
13667 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13668 | ||
ed4a6a7c MR |
13669 | /* |
13670 | * Now that the vblank has passed, we can go ahead and program the | |
13671 | * optimal watermarks on platforms that need two-step watermark | |
13672 | * programming. | |
13673 | * | |
13674 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13675 | */ | |
13676 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13677 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13678 | ||
13679 | if (dev_priv->display.optimize_watermarks) | |
13680 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13681 | } | |
13682 | ||
f935675f | 13683 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13684 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13685 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13686 | |
565602d7 | 13687 | if (hw_check) |
ee165b1a ML |
13688 | intel_modeset_check_state(dev, state); |
13689 | ||
13690 | drm_atomic_state_free(state); | |
f30da187 | 13691 | |
75714940 MK |
13692 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13693 | * of triggering bugs in unclaimed access. After we finish | |
13694 | * modesetting, see if an error has been flagged, and if so | |
13695 | * enable debugging for the next modeset - and hope we catch | |
13696 | * the culprit. | |
13697 | * | |
13698 | * XXX note that we assume display power is on at this point. | |
13699 | * This might hold true now but we need to add pm helper to check | |
13700 | * unclaimed only when the hardware is on, as atomic commits | |
13701 | * can happen also when the device is completely off. | |
13702 | */ | |
13703 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13704 | ||
74c090b1 | 13705 | return 0; |
7f27126e JB |
13706 | } |
13707 | ||
c0c36b94 CW |
13708 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13709 | { | |
83a57153 ACO |
13710 | struct drm_device *dev = crtc->dev; |
13711 | struct drm_atomic_state *state; | |
e694eb02 | 13712 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13713 | int ret; |
83a57153 ACO |
13714 | |
13715 | state = drm_atomic_state_alloc(dev); | |
13716 | if (!state) { | |
e694eb02 | 13717 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13718 | crtc->base.id); |
13719 | return; | |
13720 | } | |
13721 | ||
e694eb02 | 13722 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13723 | |
e694eb02 ML |
13724 | retry: |
13725 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13726 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13727 | if (!ret) { | |
13728 | if (!crtc_state->active) | |
13729 | goto out; | |
83a57153 | 13730 | |
e694eb02 | 13731 | crtc_state->mode_changed = true; |
74c090b1 | 13732 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13733 | } |
13734 | ||
e694eb02 ML |
13735 | if (ret == -EDEADLK) { |
13736 | drm_atomic_state_clear(state); | |
13737 | drm_modeset_backoff(state->acquire_ctx); | |
13738 | goto retry; | |
4ed9fb37 | 13739 | } |
4be07317 | 13740 | |
2bfb4627 | 13741 | if (ret) |
e694eb02 | 13742 | out: |
2bfb4627 | 13743 | drm_atomic_state_free(state); |
c0c36b94 CW |
13744 | } |
13745 | ||
25c5b266 DV |
13746 | #undef for_each_intel_crtc_masked |
13747 | ||
f6e5b160 | 13748 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13749 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13750 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13751 | .destroy = intel_crtc_destroy, |
13752 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13753 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13754 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13755 | }; |
13756 | ||
5358901f DV |
13757 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13758 | struct intel_shared_dpll *pll, | |
13759 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13760 | { |
5358901f | 13761 | uint32_t val; |
ee7b9f93 | 13762 | |
12fda387 | 13763 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13764 | return false; |
13765 | ||
5358901f | 13766 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13767 | hw_state->dpll = val; |
13768 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13769 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f | 13770 | |
12fda387 ID |
13771 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
13772 | ||
5358901f DV |
13773 | return val & DPLL_VCO_ENABLE; |
13774 | } | |
13775 | ||
15bdd4cf DV |
13776 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13777 | struct intel_shared_dpll *pll) | |
13778 | { | |
3e369b76 ACO |
13779 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13780 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13781 | } |
13782 | ||
e7b903d2 DV |
13783 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13784 | struct intel_shared_dpll *pll) | |
13785 | { | |
e7b903d2 | 13786 | /* PCH refclock must be enabled first */ |
89eff4be | 13787 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13788 | |
3e369b76 | 13789 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13790 | |
13791 | /* Wait for the clocks to stabilize. */ | |
13792 | POSTING_READ(PCH_DPLL(pll->id)); | |
13793 | udelay(150); | |
13794 | ||
13795 | /* The pixel multiplier can only be updated once the | |
13796 | * DPLL is enabled and the clocks are stable. | |
13797 | * | |
13798 | * So write it again. | |
13799 | */ | |
3e369b76 | 13800 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13801 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13802 | udelay(200); |
13803 | } | |
13804 | ||
13805 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13806 | struct intel_shared_dpll *pll) | |
13807 | { | |
13808 | struct drm_device *dev = dev_priv->dev; | |
13809 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13810 | |
13811 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13812 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13813 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13814 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13815 | } |
13816 | ||
15bdd4cf DV |
13817 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13818 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13819 | udelay(200); |
13820 | } | |
13821 | ||
46edb027 DV |
13822 | static char *ibx_pch_dpll_names[] = { |
13823 | "PCH DPLL A", | |
13824 | "PCH DPLL B", | |
13825 | }; | |
13826 | ||
7c74ade1 | 13827 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13828 | { |
e7b903d2 | 13829 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13830 | int i; |
13831 | ||
7c74ade1 | 13832 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13833 | |
e72f9fbf | 13834 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13835 | dev_priv->shared_dplls[i].id = i; |
13836 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13837 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13838 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13839 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13840 | dev_priv->shared_dplls[i].get_hw_state = |
13841 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13842 | } |
13843 | } | |
13844 | ||
7c74ade1 DV |
13845 | static void intel_shared_dpll_init(struct drm_device *dev) |
13846 | { | |
e7b903d2 | 13847 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13848 | |
9cd86933 DV |
13849 | if (HAS_DDI(dev)) |
13850 | intel_ddi_pll_init(dev); | |
13851 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13852 | ibx_pch_dpll_init(dev); |
13853 | else | |
13854 | dev_priv->num_shared_dpll = 0; | |
13855 | ||
13856 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13857 | } |
13858 | ||
6beb8c23 MR |
13859 | /** |
13860 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13861 | * @plane: drm plane to prepare for | |
13862 | * @fb: framebuffer to prepare for presentation | |
13863 | * | |
13864 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13865 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13866 | * bits. Some older platforms need special physical address handling for | |
13867 | * cursor planes. | |
13868 | * | |
f935675f ML |
13869 | * Must be called with struct_mutex held. |
13870 | * | |
6beb8c23 MR |
13871 | * Returns 0 on success, negative error code on failure. |
13872 | */ | |
13873 | int | |
13874 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13875 | const struct drm_plane_state *new_state) |
465c120c MR |
13876 | { |
13877 | struct drm_device *dev = plane->dev; | |
844f9111 | 13878 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13879 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13880 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13881 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13882 | int ret = 0; |
465c120c | 13883 | |
1ee49399 | 13884 | if (!obj && !old_obj) |
465c120c MR |
13885 | return 0; |
13886 | ||
5008e874 ML |
13887 | if (old_obj) { |
13888 | struct drm_crtc_state *crtc_state = | |
13889 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13890 | ||
13891 | /* Big Hammer, we also need to ensure that any pending | |
13892 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13893 | * current scanout is retired before unpinning the old | |
13894 | * framebuffer. Note that we rely on userspace rendering | |
13895 | * into the buffer attached to the pipe they are waiting | |
13896 | * on. If not, userspace generates a GPU hang with IPEHR | |
13897 | * point to the MI_WAIT_FOR_EVENT. | |
13898 | * | |
13899 | * This should only fail upon a hung GPU, in which case we | |
13900 | * can safely continue. | |
13901 | */ | |
13902 | if (needs_modeset(crtc_state)) | |
13903 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13904 | ||
13905 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13906 | if (ret && ret != -EIO) | |
f935675f | 13907 | return ret; |
5008e874 ML |
13908 | } |
13909 | ||
3c28ff22 AG |
13910 | /* For framebuffer backed by dmabuf, wait for fence */ |
13911 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13912 | long lret; |
13913 | ||
13914 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13915 | false, true, | |
13916 | MAX_SCHEDULE_TIMEOUT); | |
13917 | if (lret == -ERESTARTSYS) | |
13918 | return lret; | |
3c28ff22 | 13919 | |
bcf8be27 | 13920 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13921 | } |
13922 | ||
1ee49399 ML |
13923 | if (!obj) { |
13924 | ret = 0; | |
13925 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13926 | INTEL_INFO(dev)->cursor_needs_physical) { |
13927 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13928 | ret = i915_gem_object_attach_phys(obj, align); | |
13929 | if (ret) | |
13930 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13931 | } else { | |
7580d774 | 13932 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13933 | } |
465c120c | 13934 | |
7580d774 ML |
13935 | if (ret == 0) { |
13936 | if (obj) { | |
13937 | struct intel_plane_state *plane_state = | |
13938 | to_intel_plane_state(new_state); | |
13939 | ||
13940 | i915_gem_request_assign(&plane_state->wait_req, | |
13941 | obj->last_write_req); | |
13942 | } | |
13943 | ||
a9ff8714 | 13944 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13945 | } |
fdd508a6 | 13946 | |
6beb8c23 MR |
13947 | return ret; |
13948 | } | |
13949 | ||
38f3ce3a MR |
13950 | /** |
13951 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13952 | * @plane: drm plane to clean up for | |
13953 | * @fb: old framebuffer that was on plane | |
13954 | * | |
13955 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13956 | * |
13957 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13958 | */ |
13959 | void | |
13960 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13961 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13962 | { |
13963 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13964 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13965 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13966 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13967 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13968 | |
7580d774 ML |
13969 | old_intel_state = to_intel_plane_state(old_state); |
13970 | ||
1ee49399 | 13971 | if (!obj && !old_obj) |
38f3ce3a MR |
13972 | return; |
13973 | ||
1ee49399 ML |
13974 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13975 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13976 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13977 | |
13978 | /* prepare_fb aborted? */ | |
13979 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13980 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13981 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13982 | |
13983 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13984 | ||
465c120c MR |
13985 | } |
13986 | ||
6156a456 CK |
13987 | int |
13988 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13989 | { | |
13990 | int max_scale; | |
13991 | struct drm_device *dev; | |
13992 | struct drm_i915_private *dev_priv; | |
13993 | int crtc_clock, cdclk; | |
13994 | ||
bf8a0af0 | 13995 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13996 | return DRM_PLANE_HELPER_NO_SCALING; |
13997 | ||
13998 | dev = intel_crtc->base.dev; | |
13999 | dev_priv = dev->dev_private; | |
14000 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 14001 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14002 | |
54bf1ce6 | 14003 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14004 | return DRM_PLANE_HELPER_NO_SCALING; |
14005 | ||
14006 | /* | |
14007 | * skl max scale is lower of: | |
14008 | * close to 3 but not 3, -1 is for that purpose | |
14009 | * or | |
14010 | * cdclk/crtc_clock | |
14011 | */ | |
14012 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14013 | ||
14014 | return max_scale; | |
14015 | } | |
14016 | ||
465c120c | 14017 | static int |
3c692a41 | 14018 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14019 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14020 | struct intel_plane_state *state) |
14021 | { | |
2b875c22 MR |
14022 | struct drm_crtc *crtc = state->base.crtc; |
14023 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14024 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14025 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14026 | bool can_position = false; | |
465c120c | 14027 | |
693bdc28 VS |
14028 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14029 | /* use scaler when colorkey is not required */ | |
14030 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14031 | min_scale = 1; | |
14032 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14033 | } | |
d8106366 | 14034 | can_position = true; |
6156a456 | 14035 | } |
d8106366 | 14036 | |
061e4b8d ML |
14037 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14038 | &state->dst, &state->clip, | |
da20eabd ML |
14039 | min_scale, max_scale, |
14040 | can_position, true, | |
14041 | &state->visible); | |
14af293f GP |
14042 | } |
14043 | ||
613d2b27 ML |
14044 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14045 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 14046 | { |
32b7eeec | 14047 | struct drm_device *dev = crtc->dev; |
3c692a41 | 14048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
14049 | struct intel_crtc_state *old_intel_state = |
14050 | to_intel_crtc_state(old_crtc_state); | |
14051 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 14052 | |
c34c9ee4 | 14053 | /* Perform vblank evasion around commit operation */ |
62852622 | 14054 | intel_pipe_update_start(intel_crtc); |
0583236e | 14055 | |
bfd16b2a ML |
14056 | if (modeset) |
14057 | return; | |
14058 | ||
14059 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14060 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14061 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 14062 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
14063 | } |
14064 | ||
613d2b27 ML |
14065 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
14066 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 14067 | { |
32b7eeec | 14068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 14069 | |
62852622 | 14070 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
14071 | } |
14072 | ||
cf4c7c12 | 14073 | /** |
4a3b8769 MR |
14074 | * intel_plane_destroy - destroy a plane |
14075 | * @plane: plane to destroy | |
cf4c7c12 | 14076 | * |
4a3b8769 MR |
14077 | * Common destruction function for all types of planes (primary, cursor, |
14078 | * sprite). | |
cf4c7c12 | 14079 | */ |
4a3b8769 | 14080 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
14081 | { |
14082 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14083 | drm_plane_cleanup(plane); | |
14084 | kfree(intel_plane); | |
14085 | } | |
14086 | ||
65a3fea0 | 14087 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14088 | .update_plane = drm_atomic_helper_update_plane, |
14089 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14090 | .destroy = intel_plane_destroy, |
c196e1d6 | 14091 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14092 | .atomic_get_property = intel_plane_atomic_get_property, |
14093 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14094 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14095 | .atomic_destroy_state = intel_plane_destroy_state, | |
14096 | ||
465c120c MR |
14097 | }; |
14098 | ||
14099 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14100 | int pipe) | |
14101 | { | |
14102 | struct intel_plane *primary; | |
8e7d688b | 14103 | struct intel_plane_state *state; |
465c120c | 14104 | const uint32_t *intel_primary_formats; |
45e3743a | 14105 | unsigned int num_formats; |
465c120c MR |
14106 | |
14107 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14108 | if (primary == NULL) | |
14109 | return NULL; | |
14110 | ||
8e7d688b MR |
14111 | state = intel_create_plane_state(&primary->base); |
14112 | if (!state) { | |
ea2c67bb MR |
14113 | kfree(primary); |
14114 | return NULL; | |
14115 | } | |
8e7d688b | 14116 | primary->base.state = &state->base; |
ea2c67bb | 14117 | |
465c120c MR |
14118 | primary->can_scale = false; |
14119 | primary->max_downscale = 1; | |
6156a456 CK |
14120 | if (INTEL_INFO(dev)->gen >= 9) { |
14121 | primary->can_scale = true; | |
af99ceda | 14122 | state->scaler_id = -1; |
6156a456 | 14123 | } |
465c120c MR |
14124 | primary->pipe = pipe; |
14125 | primary->plane = pipe; | |
a9ff8714 | 14126 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14127 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14128 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14129 | primary->plane = !pipe; | |
14130 | ||
6c0fd451 DL |
14131 | if (INTEL_INFO(dev)->gen >= 9) { |
14132 | intel_primary_formats = skl_primary_formats; | |
14133 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14134 | |
14135 | primary->update_plane = skylake_update_primary_plane; | |
14136 | primary->disable_plane = skylake_disable_primary_plane; | |
14137 | } else if (HAS_PCH_SPLIT(dev)) { | |
14138 | intel_primary_formats = i965_primary_formats; | |
14139 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14140 | ||
14141 | primary->update_plane = ironlake_update_primary_plane; | |
14142 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14143 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14144 | intel_primary_formats = i965_primary_formats; |
14145 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14146 | |
14147 | primary->update_plane = i9xx_update_primary_plane; | |
14148 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14149 | } else { |
14150 | intel_primary_formats = i8xx_primary_formats; | |
14151 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14152 | |
14153 | primary->update_plane = i9xx_update_primary_plane; | |
14154 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14155 | } |
14156 | ||
14157 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14158 | &intel_plane_funcs, |
465c120c | 14159 | intel_primary_formats, num_formats, |
b0b3b795 | 14160 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14161 | |
3b7a5119 SJ |
14162 | if (INTEL_INFO(dev)->gen >= 4) |
14163 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14164 | |
ea2c67bb MR |
14165 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14166 | ||
465c120c MR |
14167 | return &primary->base; |
14168 | } | |
14169 | ||
3b7a5119 SJ |
14170 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14171 | { | |
14172 | if (!dev->mode_config.rotation_property) { | |
14173 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14174 | BIT(DRM_ROTATE_180); | |
14175 | ||
14176 | if (INTEL_INFO(dev)->gen >= 9) | |
14177 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14178 | ||
14179 | dev->mode_config.rotation_property = | |
14180 | drm_mode_create_rotation_property(dev, flags); | |
14181 | } | |
14182 | if (dev->mode_config.rotation_property) | |
14183 | drm_object_attach_property(&plane->base.base, | |
14184 | dev->mode_config.rotation_property, | |
14185 | plane->base.state->rotation); | |
14186 | } | |
14187 | ||
3d7d6510 | 14188 | static int |
852e787c | 14189 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14190 | struct intel_crtc_state *crtc_state, |
852e787c | 14191 | struct intel_plane_state *state) |
3d7d6510 | 14192 | { |
061e4b8d | 14193 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14194 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14195 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14196 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14197 | unsigned stride; |
14198 | int ret; | |
3d7d6510 | 14199 | |
061e4b8d ML |
14200 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14201 | &state->dst, &state->clip, | |
3d7d6510 MR |
14202 | DRM_PLANE_HELPER_NO_SCALING, |
14203 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14204 | true, true, &state->visible); |
757f9a3e GP |
14205 | if (ret) |
14206 | return ret; | |
14207 | ||
757f9a3e GP |
14208 | /* if we want to turn off the cursor ignore width and height */ |
14209 | if (!obj) | |
da20eabd | 14210 | return 0; |
757f9a3e | 14211 | |
757f9a3e | 14212 | /* Check for which cursor types we support */ |
061e4b8d | 14213 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14214 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14215 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14216 | return -EINVAL; |
14217 | } | |
14218 | ||
ea2c67bb MR |
14219 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14220 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14221 | DRM_DEBUG_KMS("buffer is too small\n"); |
14222 | return -ENOMEM; | |
14223 | } | |
14224 | ||
3a656b54 | 14225 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14226 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14227 | return -EINVAL; |
32b7eeec MR |
14228 | } |
14229 | ||
b29ec92c VS |
14230 | /* |
14231 | * There's something wrong with the cursor on CHV pipe C. | |
14232 | * If it straddles the left edge of the screen then | |
14233 | * moving it away from the edge or disabling it often | |
14234 | * results in a pipe underrun, and often that can lead to | |
14235 | * dead pipe (constant underrun reported, and it scans | |
14236 | * out just a solid color). To recover from that, the | |
14237 | * display power well must be turned off and on again. | |
14238 | * Refuse the put the cursor into that compromised position. | |
14239 | */ | |
14240 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14241 | state->visible && state->base.crtc_x < 0) { | |
14242 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14243 | return -EINVAL; | |
14244 | } | |
14245 | ||
da20eabd | 14246 | return 0; |
852e787c | 14247 | } |
3d7d6510 | 14248 | |
a8ad0d8e ML |
14249 | static void |
14250 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14251 | struct drm_crtc *crtc) |
a8ad0d8e | 14252 | { |
f2858021 ML |
14253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14254 | ||
14255 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14256 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14257 | } |
14258 | ||
f4a2cf29 | 14259 | static void |
55a08b3f ML |
14260 | intel_update_cursor_plane(struct drm_plane *plane, |
14261 | const struct intel_crtc_state *crtc_state, | |
14262 | const struct intel_plane_state *state) | |
852e787c | 14263 | { |
55a08b3f ML |
14264 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14266 | struct drm_device *dev = plane->dev; |
2b875c22 | 14267 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14268 | uint32_t addr; |
852e787c | 14269 | |
f4a2cf29 | 14270 | if (!obj) |
a912f12f | 14271 | addr = 0; |
f4a2cf29 | 14272 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14273 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14274 | else |
a912f12f | 14275 | addr = obj->phys_handle->busaddr; |
852e787c | 14276 | |
a912f12f | 14277 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14278 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14279 | } |
14280 | ||
3d7d6510 MR |
14281 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14282 | int pipe) | |
14283 | { | |
14284 | struct intel_plane *cursor; | |
8e7d688b | 14285 | struct intel_plane_state *state; |
3d7d6510 MR |
14286 | |
14287 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14288 | if (cursor == NULL) | |
14289 | return NULL; | |
14290 | ||
8e7d688b MR |
14291 | state = intel_create_plane_state(&cursor->base); |
14292 | if (!state) { | |
ea2c67bb MR |
14293 | kfree(cursor); |
14294 | return NULL; | |
14295 | } | |
8e7d688b | 14296 | cursor->base.state = &state->base; |
ea2c67bb | 14297 | |
3d7d6510 MR |
14298 | cursor->can_scale = false; |
14299 | cursor->max_downscale = 1; | |
14300 | cursor->pipe = pipe; | |
14301 | cursor->plane = pipe; | |
a9ff8714 | 14302 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14303 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14304 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14305 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14306 | |
14307 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14308 | &intel_plane_funcs, |
3d7d6510 MR |
14309 | intel_cursor_formats, |
14310 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14311 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14312 | |
14313 | if (INTEL_INFO(dev)->gen >= 4) { | |
14314 | if (!dev->mode_config.rotation_property) | |
14315 | dev->mode_config.rotation_property = | |
14316 | drm_mode_create_rotation_property(dev, | |
14317 | BIT(DRM_ROTATE_0) | | |
14318 | BIT(DRM_ROTATE_180)); | |
14319 | if (dev->mode_config.rotation_property) | |
14320 | drm_object_attach_property(&cursor->base.base, | |
14321 | dev->mode_config.rotation_property, | |
8e7d688b | 14322 | state->base.rotation); |
4398ad45 VS |
14323 | } |
14324 | ||
af99ceda CK |
14325 | if (INTEL_INFO(dev)->gen >=9) |
14326 | state->scaler_id = -1; | |
14327 | ||
ea2c67bb MR |
14328 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14329 | ||
3d7d6510 MR |
14330 | return &cursor->base; |
14331 | } | |
14332 | ||
549e2bfb CK |
14333 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14334 | struct intel_crtc_state *crtc_state) | |
14335 | { | |
14336 | int i; | |
14337 | struct intel_scaler *intel_scaler; | |
14338 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14339 | ||
14340 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14341 | intel_scaler = &scaler_state->scalers[i]; | |
14342 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14343 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14344 | } | |
14345 | ||
14346 | scaler_state->scaler_id = -1; | |
14347 | } | |
14348 | ||
b358d0a6 | 14349 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14350 | { |
fbee40df | 14351 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14352 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14353 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14354 | struct drm_plane *primary = NULL; |
14355 | struct drm_plane *cursor = NULL; | |
465c120c | 14356 | int i, ret; |
79e53945 | 14357 | |
955382f3 | 14358 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14359 | if (intel_crtc == NULL) |
14360 | return; | |
14361 | ||
f5de6e07 ACO |
14362 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14363 | if (!crtc_state) | |
14364 | goto fail; | |
550acefd ACO |
14365 | intel_crtc->config = crtc_state; |
14366 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14367 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14368 | |
549e2bfb CK |
14369 | /* initialize shared scalers */ |
14370 | if (INTEL_INFO(dev)->gen >= 9) { | |
14371 | if (pipe == PIPE_C) | |
14372 | intel_crtc->num_scalers = 1; | |
14373 | else | |
14374 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14375 | ||
14376 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14377 | } | |
14378 | ||
465c120c | 14379 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14380 | if (!primary) |
14381 | goto fail; | |
14382 | ||
14383 | cursor = intel_cursor_plane_create(dev, pipe); | |
14384 | if (!cursor) | |
14385 | goto fail; | |
14386 | ||
465c120c | 14387 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14388 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14389 | if (ret) |
14390 | goto fail; | |
79e53945 JB |
14391 | |
14392 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14393 | for (i = 0; i < 256; i++) { |
14394 | intel_crtc->lut_r[i] = i; | |
14395 | intel_crtc->lut_g[i] = i; | |
14396 | intel_crtc->lut_b[i] = i; | |
14397 | } | |
14398 | ||
1f1c2e24 VS |
14399 | /* |
14400 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14401 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14402 | */ |
80824003 JB |
14403 | intel_crtc->pipe = pipe; |
14404 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14405 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14406 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14407 | intel_crtc->plane = !pipe; |
80824003 JB |
14408 | } |
14409 | ||
4b0e333e CW |
14410 | intel_crtc->cursor_base = ~0; |
14411 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14412 | intel_crtc->cursor_size = ~0; |
8d7849db | 14413 | |
852eb00d VS |
14414 | intel_crtc->wm.cxsr_allowed = true; |
14415 | ||
22fd0fab JB |
14416 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14417 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14418 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14419 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14420 | ||
79e53945 | 14421 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14422 | |
14423 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14424 | return; |
14425 | ||
14426 | fail: | |
14427 | if (primary) | |
14428 | drm_plane_cleanup(primary); | |
14429 | if (cursor) | |
14430 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14431 | kfree(crtc_state); |
3d7d6510 | 14432 | kfree(intel_crtc); |
79e53945 JB |
14433 | } |
14434 | ||
752aa88a JB |
14435 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14436 | { | |
14437 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14438 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14439 | |
51fd371b | 14440 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14441 | |
d3babd3f | 14442 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14443 | return INVALID_PIPE; |
14444 | ||
14445 | return to_intel_crtc(encoder->crtc)->pipe; | |
14446 | } | |
14447 | ||
08d7b3d1 | 14448 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14449 | struct drm_file *file) |
08d7b3d1 | 14450 | { |
08d7b3d1 | 14451 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14452 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14453 | struct intel_crtc *crtc; |
08d7b3d1 | 14454 | |
7707e653 | 14455 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14456 | |
7707e653 | 14457 | if (!drmmode_crtc) { |
08d7b3d1 | 14458 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14459 | return -ENOENT; |
08d7b3d1 CW |
14460 | } |
14461 | ||
7707e653 | 14462 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14463 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14464 | |
c05422d5 | 14465 | return 0; |
08d7b3d1 CW |
14466 | } |
14467 | ||
66a9278e | 14468 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14469 | { |
66a9278e DV |
14470 | struct drm_device *dev = encoder->base.dev; |
14471 | struct intel_encoder *source_encoder; | |
79e53945 | 14472 | int index_mask = 0; |
79e53945 JB |
14473 | int entry = 0; |
14474 | ||
b2784e15 | 14475 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14476 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14477 | index_mask |= (1 << entry); |
14478 | ||
79e53945 JB |
14479 | entry++; |
14480 | } | |
4ef69c7a | 14481 | |
79e53945 JB |
14482 | return index_mask; |
14483 | } | |
14484 | ||
4d302442 CW |
14485 | static bool has_edp_a(struct drm_device *dev) |
14486 | { | |
14487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14488 | ||
14489 | if (!IS_MOBILE(dev)) | |
14490 | return false; | |
14491 | ||
14492 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14493 | return false; | |
14494 | ||
e3589908 | 14495 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14496 | return false; |
14497 | ||
14498 | return true; | |
14499 | } | |
14500 | ||
84b4e042 JB |
14501 | static bool intel_crt_present(struct drm_device *dev) |
14502 | { | |
14503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14504 | ||
884497ed DL |
14505 | if (INTEL_INFO(dev)->gen >= 9) |
14506 | return false; | |
14507 | ||
cf404ce4 | 14508 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14509 | return false; |
14510 | ||
14511 | if (IS_CHERRYVIEW(dev)) | |
14512 | return false; | |
14513 | ||
65e472e4 VS |
14514 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14515 | return false; | |
14516 | ||
70ac54d0 VS |
14517 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14518 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14519 | return false; | |
14520 | ||
e4abb733 | 14521 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14522 | return false; |
14523 | ||
14524 | return true; | |
14525 | } | |
14526 | ||
79e53945 JB |
14527 | static void intel_setup_outputs(struct drm_device *dev) |
14528 | { | |
725e30ad | 14529 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14530 | struct intel_encoder *encoder; |
cb0953d7 | 14531 | bool dpd_is_edp = false; |
79e53945 | 14532 | |
c9093354 | 14533 | intel_lvds_init(dev); |
79e53945 | 14534 | |
84b4e042 | 14535 | if (intel_crt_present(dev)) |
79935fca | 14536 | intel_crt_init(dev); |
cb0953d7 | 14537 | |
c776eb2e VK |
14538 | if (IS_BROXTON(dev)) { |
14539 | /* | |
14540 | * FIXME: Broxton doesn't support port detection via the | |
14541 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14542 | * detect the ports. | |
14543 | */ | |
14544 | intel_ddi_init(dev, PORT_A); | |
14545 | intel_ddi_init(dev, PORT_B); | |
14546 | intel_ddi_init(dev, PORT_C); | |
14547 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14548 | int found; |
14549 | ||
de31facd JB |
14550 | /* |
14551 | * Haswell uses DDI functions to detect digital outputs. | |
14552 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14553 | * it's there. | |
14554 | */ | |
77179400 | 14555 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14556 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14557 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14558 | intel_ddi_init(dev, PORT_A); |
14559 | ||
14560 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14561 | * register */ | |
14562 | found = I915_READ(SFUSE_STRAP); | |
14563 | ||
14564 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14565 | intel_ddi_init(dev, PORT_B); | |
14566 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14567 | intel_ddi_init(dev, PORT_C); | |
14568 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14569 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14570 | /* |
14571 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14572 | */ | |
ef11bdb3 | 14573 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14574 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14575 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14576 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14577 | intel_ddi_init(dev, PORT_E); | |
14578 | ||
0e72a5b5 | 14579 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14580 | int found; |
5d8a7752 | 14581 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14582 | |
14583 | if (has_edp_a(dev)) | |
14584 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14585 | |
dc0fa718 | 14586 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14587 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14588 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14589 | if (!found) |
e2debe91 | 14590 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14591 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14592 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14593 | } |
14594 | ||
dc0fa718 | 14595 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14596 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14597 | |
dc0fa718 | 14598 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14599 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14600 | |
5eb08b69 | 14601 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14602 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14603 | |
270b3042 | 14604 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14605 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14606 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14607 | /* |
14608 | * The DP_DETECTED bit is the latched state of the DDC | |
14609 | * SDA pin at boot. However since eDP doesn't require DDC | |
14610 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14611 | * eDP ports may have been muxed to an alternate function. | |
14612 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14613 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14614 | * detect eDP ports. | |
14615 | */ | |
e66eb81d | 14616 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14617 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14618 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14619 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14620 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14621 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14622 | |
e66eb81d | 14623 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14624 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14625 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14626 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14627 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14628 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14629 | |
9418c1f1 | 14630 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14631 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14632 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14633 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14634 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14635 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14636 | } |
14637 | ||
3cfca973 | 14638 | intel_dsi_init(dev); |
09da55dc | 14639 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14640 | bool found = false; |
7d57382e | 14641 | |
e2debe91 | 14642 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14643 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14644 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14645 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14646 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14647 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14648 | } |
27185ae1 | 14649 | |
3fec3d2f | 14650 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14651 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14652 | } |
13520b05 KH |
14653 | |
14654 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14655 | |
e2debe91 | 14656 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14657 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14658 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14659 | } |
27185ae1 | 14660 | |
e2debe91 | 14661 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14662 | |
3fec3d2f | 14663 | if (IS_G4X(dev)) { |
b01f2c3a | 14664 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14665 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14666 | } |
3fec3d2f | 14667 | if (IS_G4X(dev)) |
ab9d7c30 | 14668 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14669 | } |
27185ae1 | 14670 | |
3fec3d2f | 14671 | if (IS_G4X(dev) && |
e7281eab | 14672 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14673 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14674 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14675 | intel_dvo_init(dev); |
14676 | ||
103a196f | 14677 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14678 | intel_tv_init(dev); |
14679 | ||
0bc12bcb | 14680 | intel_psr_init(dev); |
7c8f8a70 | 14681 | |
b2784e15 | 14682 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14683 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14684 | encoder->base.possible_clones = | |
66a9278e | 14685 | intel_encoder_clones(encoder); |
79e53945 | 14686 | } |
47356eb6 | 14687 | |
dde86e2d | 14688 | intel_init_pch_refclk(dev); |
270b3042 DV |
14689 | |
14690 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14691 | } |
14692 | ||
14693 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14694 | { | |
60a5ca01 | 14695 | struct drm_device *dev = fb->dev; |
79e53945 | 14696 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14697 | |
ef2d633e | 14698 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14699 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14700 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14701 | drm_gem_object_unreference(&intel_fb->obj->base); |
14702 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14703 | kfree(intel_fb); |
14704 | } | |
14705 | ||
14706 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14707 | struct drm_file *file, |
79e53945 JB |
14708 | unsigned int *handle) |
14709 | { | |
14710 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14711 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14712 | |
cc917ab4 CW |
14713 | if (obj->userptr.mm) { |
14714 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14715 | return -EINVAL; | |
14716 | } | |
14717 | ||
05394f39 | 14718 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14719 | } |
14720 | ||
86c98588 RV |
14721 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14722 | struct drm_file *file, | |
14723 | unsigned flags, unsigned color, | |
14724 | struct drm_clip_rect *clips, | |
14725 | unsigned num_clips) | |
14726 | { | |
14727 | struct drm_device *dev = fb->dev; | |
14728 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14729 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14730 | ||
14731 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14732 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14733 | mutex_unlock(&dev->struct_mutex); |
14734 | ||
14735 | return 0; | |
14736 | } | |
14737 | ||
79e53945 JB |
14738 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14739 | .destroy = intel_user_framebuffer_destroy, | |
14740 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14741 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14742 | }; |
14743 | ||
b321803d DL |
14744 | static |
14745 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14746 | uint32_t pixel_format) | |
14747 | { | |
14748 | u32 gen = INTEL_INFO(dev)->gen; | |
14749 | ||
14750 | if (gen >= 9) { | |
ac484963 VS |
14751 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14752 | ||
b321803d DL |
14753 | /* "The stride in bytes must not exceed the of the size of 8K |
14754 | * pixels and 32K bytes." | |
14755 | */ | |
ac484963 | 14756 | return min(8192 * cpp, 32768); |
666a4537 | 14757 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14758 | return 32*1024; |
14759 | } else if (gen >= 4) { | |
14760 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14761 | return 16*1024; | |
14762 | else | |
14763 | return 32*1024; | |
14764 | } else if (gen >= 3) { | |
14765 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14766 | return 8*1024; | |
14767 | else | |
14768 | return 16*1024; | |
14769 | } else { | |
14770 | /* XXX DSPC is limited to 4k tiled */ | |
14771 | return 8*1024; | |
14772 | } | |
14773 | } | |
14774 | ||
b5ea642a DV |
14775 | static int intel_framebuffer_init(struct drm_device *dev, |
14776 | struct intel_framebuffer *intel_fb, | |
14777 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14778 | struct drm_i915_gem_object *obj) | |
79e53945 | 14779 | { |
7b49f948 | 14780 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14781 | unsigned int aligned_height; |
79e53945 | 14782 | int ret; |
b321803d | 14783 | u32 pitch_limit, stride_alignment; |
79e53945 | 14784 | |
dd4916c5 DV |
14785 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14786 | ||
2a80eada DV |
14787 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14788 | /* Enforce that fb modifier and tiling mode match, but only for | |
14789 | * X-tiled. This is needed for FBC. */ | |
14790 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14791 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14792 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14793 | return -EINVAL; | |
14794 | } | |
14795 | } else { | |
14796 | if (obj->tiling_mode == I915_TILING_X) | |
14797 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14798 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14799 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14800 | return -EINVAL; | |
14801 | } | |
14802 | } | |
14803 | ||
9a8f0a12 TU |
14804 | /* Passed in modifier sanity checking. */ |
14805 | switch (mode_cmd->modifier[0]) { | |
14806 | case I915_FORMAT_MOD_Y_TILED: | |
14807 | case I915_FORMAT_MOD_Yf_TILED: | |
14808 | if (INTEL_INFO(dev)->gen < 9) { | |
14809 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14810 | mode_cmd->modifier[0]); | |
14811 | return -EINVAL; | |
14812 | } | |
14813 | case DRM_FORMAT_MOD_NONE: | |
14814 | case I915_FORMAT_MOD_X_TILED: | |
14815 | break; | |
14816 | default: | |
c0f40428 JB |
14817 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14818 | mode_cmd->modifier[0]); | |
57cd6508 | 14819 | return -EINVAL; |
c16ed4be | 14820 | } |
57cd6508 | 14821 | |
7b49f948 VS |
14822 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14823 | mode_cmd->modifier[0], | |
b321803d DL |
14824 | mode_cmd->pixel_format); |
14825 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14826 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14827 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14828 | return -EINVAL; |
c16ed4be | 14829 | } |
57cd6508 | 14830 | |
b321803d DL |
14831 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14832 | mode_cmd->pixel_format); | |
a35cdaa0 | 14833 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14834 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14835 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14836 | "tiled" : "linear", |
a35cdaa0 | 14837 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14838 | return -EINVAL; |
c16ed4be | 14839 | } |
5d7bd705 | 14840 | |
2a80eada | 14841 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14842 | mode_cmd->pitches[0] != obj->stride) { |
14843 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14844 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14845 | return -EINVAL; |
c16ed4be | 14846 | } |
5d7bd705 | 14847 | |
57779d06 | 14848 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14849 | switch (mode_cmd->pixel_format) { |
57779d06 | 14850 | case DRM_FORMAT_C8: |
04b3924d VS |
14851 | case DRM_FORMAT_RGB565: |
14852 | case DRM_FORMAT_XRGB8888: | |
14853 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14854 | break; |
14855 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14856 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14857 | DRM_DEBUG("unsupported pixel format: %s\n", |
14858 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14859 | return -EINVAL; |
c16ed4be | 14860 | } |
57779d06 | 14861 | break; |
57779d06 | 14862 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14863 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14864 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14865 | DRM_DEBUG("unsupported pixel format: %s\n", |
14866 | drm_get_format_name(mode_cmd->pixel_format)); | |
14867 | return -EINVAL; | |
14868 | } | |
14869 | break; | |
14870 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14871 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14872 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14873 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14874 | DRM_DEBUG("unsupported pixel format: %s\n", |
14875 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14876 | return -EINVAL; |
c16ed4be | 14877 | } |
b5626747 | 14878 | break; |
7531208b | 14879 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14880 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14881 | DRM_DEBUG("unsupported pixel format: %s\n", |
14882 | drm_get_format_name(mode_cmd->pixel_format)); | |
14883 | return -EINVAL; | |
14884 | } | |
14885 | break; | |
04b3924d VS |
14886 | case DRM_FORMAT_YUYV: |
14887 | case DRM_FORMAT_UYVY: | |
14888 | case DRM_FORMAT_YVYU: | |
14889 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14890 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14891 | DRM_DEBUG("unsupported pixel format: %s\n", |
14892 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14893 | return -EINVAL; |
c16ed4be | 14894 | } |
57cd6508 CW |
14895 | break; |
14896 | default: | |
4ee62c76 VS |
14897 | DRM_DEBUG("unsupported pixel format: %s\n", |
14898 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14899 | return -EINVAL; |
14900 | } | |
14901 | ||
90f9a336 VS |
14902 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14903 | if (mode_cmd->offsets[0] != 0) | |
14904 | return -EINVAL; | |
14905 | ||
ec2c981e | 14906 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14907 | mode_cmd->pixel_format, |
14908 | mode_cmd->modifier[0]); | |
53155c0a DV |
14909 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14910 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14911 | return -EINVAL; | |
14912 | ||
c7d73f6a DV |
14913 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14914 | intel_fb->obj = obj; | |
14915 | ||
79e53945 JB |
14916 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14917 | if (ret) { | |
14918 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14919 | return ret; | |
14920 | } | |
14921 | ||
0b05e1e0 VS |
14922 | intel_fb->obj->framebuffer_references++; |
14923 | ||
79e53945 JB |
14924 | return 0; |
14925 | } | |
14926 | ||
79e53945 JB |
14927 | static struct drm_framebuffer * |
14928 | intel_user_framebuffer_create(struct drm_device *dev, | |
14929 | struct drm_file *filp, | |
1eb83451 | 14930 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14931 | { |
dcb1394e | 14932 | struct drm_framebuffer *fb; |
05394f39 | 14933 | struct drm_i915_gem_object *obj; |
76dc3769 | 14934 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14935 | |
308e5bcb | 14936 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14937 | mode_cmd.handles[0])); |
c8725226 | 14938 | if (&obj->base == NULL) |
cce13ff7 | 14939 | return ERR_PTR(-ENOENT); |
79e53945 | 14940 | |
92907cbb | 14941 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14942 | if (IS_ERR(fb)) |
14943 | drm_gem_object_unreference_unlocked(&obj->base); | |
14944 | ||
14945 | return fb; | |
79e53945 JB |
14946 | } |
14947 | ||
0695726e | 14948 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14949 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14950 | { |
14951 | } | |
14952 | #endif | |
14953 | ||
79e53945 | 14954 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14955 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14956 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14957 | .atomic_check = intel_atomic_check, |
14958 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14959 | .atomic_state_alloc = intel_atomic_state_alloc, |
14960 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14961 | }; |
14962 | ||
e70236a8 JB |
14963 | /* Set up chip specific display functions */ |
14964 | static void intel_init_display(struct drm_device *dev) | |
14965 | { | |
14966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14967 | ||
ee9300bb DV |
14968 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14969 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14970 | else if (IS_CHERRYVIEW(dev)) |
14971 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14972 | else if (IS_VALLEYVIEW(dev)) |
14973 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14974 | else if (IS_PINEVIEW(dev)) | |
14975 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14976 | else | |
14977 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14978 | ||
bc8d7dff DL |
14979 | if (INTEL_INFO(dev)->gen >= 9) { |
14980 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14981 | dev_priv->display.get_initial_plane_config = |
14982 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14983 | dev_priv->display.crtc_compute_clock = |
14984 | haswell_crtc_compute_clock; | |
14985 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14986 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 14987 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 14988 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14989 | dev_priv->display.get_initial_plane_config = |
14990 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14991 | dev_priv->display.crtc_compute_clock = |
14992 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14993 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14994 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 14995 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14996 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14997 | dev_priv->display.get_initial_plane_config = |
14998 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14999 | dev_priv->display.crtc_compute_clock = |
15000 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15001 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15002 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 15003 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 15004 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15005 | dev_priv->display.get_initial_plane_config = |
15006 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15007 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
15008 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15009 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15010 | } else { |
0e8ffe1b | 15011 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15012 | dev_priv->display.get_initial_plane_config = |
15013 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15014 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15015 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15016 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15017 | } |
e70236a8 | 15018 | |
e70236a8 | 15019 | /* Returns the core display clock speed */ |
ef11bdb3 | 15020 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
15021 | dev_priv->display.get_display_clock_speed = |
15022 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
15023 | else if (IS_BROXTON(dev)) |
15024 | dev_priv->display.get_display_clock_speed = | |
15025 | broxton_get_display_clock_speed; | |
1652d19e VS |
15026 | else if (IS_BROADWELL(dev)) |
15027 | dev_priv->display.get_display_clock_speed = | |
15028 | broadwell_get_display_clock_speed; | |
15029 | else if (IS_HASWELL(dev)) | |
15030 | dev_priv->display.get_display_clock_speed = | |
15031 | haswell_get_display_clock_speed; | |
666a4537 | 15032 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
15033 | dev_priv->display.get_display_clock_speed = |
15034 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
15035 | else if (IS_GEN5(dev)) |
15036 | dev_priv->display.get_display_clock_speed = | |
15037 | ilk_get_display_clock_speed; | |
a7c66cd8 | 15038 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 15039 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
15040 | dev_priv->display.get_display_clock_speed = |
15041 | i945_get_display_clock_speed; | |
34edce2f VS |
15042 | else if (IS_GM45(dev)) |
15043 | dev_priv->display.get_display_clock_speed = | |
15044 | gm45_get_display_clock_speed; | |
15045 | else if (IS_CRESTLINE(dev)) | |
15046 | dev_priv->display.get_display_clock_speed = | |
15047 | i965gm_get_display_clock_speed; | |
15048 | else if (IS_PINEVIEW(dev)) | |
15049 | dev_priv->display.get_display_clock_speed = | |
15050 | pnv_get_display_clock_speed; | |
15051 | else if (IS_G33(dev) || IS_G4X(dev)) | |
15052 | dev_priv->display.get_display_clock_speed = | |
15053 | g33_get_display_clock_speed; | |
e70236a8 JB |
15054 | else if (IS_I915G(dev)) |
15055 | dev_priv->display.get_display_clock_speed = | |
15056 | i915_get_display_clock_speed; | |
257a7ffc | 15057 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
15058 | dev_priv->display.get_display_clock_speed = |
15059 | i9xx_misc_get_display_clock_speed; | |
15060 | else if (IS_I915GM(dev)) | |
15061 | dev_priv->display.get_display_clock_speed = | |
15062 | i915gm_get_display_clock_speed; | |
15063 | else if (IS_I865G(dev)) | |
15064 | dev_priv->display.get_display_clock_speed = | |
15065 | i865_get_display_clock_speed; | |
f0f8a9ce | 15066 | else if (IS_I85X(dev)) |
e70236a8 | 15067 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15068 | i85x_get_display_clock_speed; |
623e01e5 VS |
15069 | else { /* 830 */ |
15070 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
15071 | dev_priv->display.get_display_clock_speed = |
15072 | i830_get_display_clock_speed; | |
623e01e5 | 15073 | } |
e70236a8 | 15074 | |
7c10a2b5 | 15075 | if (IS_GEN5(dev)) { |
3bb11b53 | 15076 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
15077 | } else if (IS_GEN6(dev)) { |
15078 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
15079 | } else if (IS_IVYBRIDGE(dev)) { |
15080 | /* FIXME: detect B0+ stepping and use auto training */ | |
15081 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 15082 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 15083 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
15084 | if (IS_BROADWELL(dev)) { |
15085 | dev_priv->display.modeset_commit_cdclk = | |
15086 | broadwell_modeset_commit_cdclk; | |
15087 | dev_priv->display.modeset_calc_cdclk = | |
15088 | broadwell_modeset_calc_cdclk; | |
15089 | } | |
666a4537 | 15090 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15091 | dev_priv->display.modeset_commit_cdclk = |
15092 | valleyview_modeset_commit_cdclk; | |
15093 | dev_priv->display.modeset_calc_cdclk = | |
15094 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15095 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15096 | dev_priv->display.modeset_commit_cdclk = |
15097 | broxton_modeset_commit_cdclk; | |
15098 | dev_priv->display.modeset_calc_cdclk = | |
15099 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15100 | } |
8c9f3aaf | 15101 | |
8c9f3aaf JB |
15102 | switch (INTEL_INFO(dev)->gen) { |
15103 | case 2: | |
15104 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15105 | break; | |
15106 | ||
15107 | case 3: | |
15108 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15109 | break; | |
15110 | ||
15111 | case 4: | |
15112 | case 5: | |
15113 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15114 | break; | |
15115 | ||
15116 | case 6: | |
15117 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15118 | break; | |
7c9017e5 | 15119 | case 7: |
4e0bbc31 | 15120 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15121 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15122 | break; | |
830c81db | 15123 | case 9: |
ba343e02 TU |
15124 | /* Drop through - unsupported since execlist only. */ |
15125 | default: | |
15126 | /* Default just returns -ENODEV to indicate unsupported */ | |
15127 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15128 | } |
7bd688cd | 15129 | |
e39b999a | 15130 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15131 | } |
15132 | ||
b690e96c JB |
15133 | /* |
15134 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15135 | * resume, or other times. This quirk makes sure that's the case for | |
15136 | * affected systems. | |
15137 | */ | |
0206e353 | 15138 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15139 | { |
15140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15141 | ||
15142 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15143 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15144 | } |
15145 | ||
b6b5d049 VS |
15146 | static void quirk_pipeb_force(struct drm_device *dev) |
15147 | { | |
15148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15149 | ||
15150 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15151 | DRM_INFO("applying pipe b force quirk\n"); | |
15152 | } | |
15153 | ||
435793df KP |
15154 | /* |
15155 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15156 | */ | |
15157 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15158 | { | |
15159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15160 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15161 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15162 | } |
15163 | ||
4dca20ef | 15164 | /* |
5a15ab5b CE |
15165 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15166 | * brightness value | |
4dca20ef CE |
15167 | */ |
15168 | static void quirk_invert_brightness(struct drm_device *dev) | |
15169 | { | |
15170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15171 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15172 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15173 | } |
15174 | ||
9c72cc6f SD |
15175 | /* Some VBT's incorrectly indicate no backlight is present */ |
15176 | static void quirk_backlight_present(struct drm_device *dev) | |
15177 | { | |
15178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15179 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15180 | DRM_INFO("applying backlight present quirk\n"); | |
15181 | } | |
15182 | ||
b690e96c JB |
15183 | struct intel_quirk { |
15184 | int device; | |
15185 | int subsystem_vendor; | |
15186 | int subsystem_device; | |
15187 | void (*hook)(struct drm_device *dev); | |
15188 | }; | |
15189 | ||
5f85f176 EE |
15190 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15191 | struct intel_dmi_quirk { | |
15192 | void (*hook)(struct drm_device *dev); | |
15193 | const struct dmi_system_id (*dmi_id_list)[]; | |
15194 | }; | |
15195 | ||
15196 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15197 | { | |
15198 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15199 | return 1; | |
15200 | } | |
15201 | ||
15202 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15203 | { | |
15204 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15205 | { | |
15206 | .callback = intel_dmi_reverse_brightness, | |
15207 | .ident = "NCR Corporation", | |
15208 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15209 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15210 | }, | |
15211 | }, | |
15212 | { } /* terminating entry */ | |
15213 | }, | |
15214 | .hook = quirk_invert_brightness, | |
15215 | }, | |
15216 | }; | |
15217 | ||
c43b5634 | 15218 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15219 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15220 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15221 | ||
b690e96c JB |
15222 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15223 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15224 | ||
5f080c0f VS |
15225 | /* 830 needs to leave pipe A & dpll A up */ |
15226 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15227 | ||
b6b5d049 VS |
15228 | /* 830 needs to leave pipe B & dpll B up */ |
15229 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15230 | ||
435793df KP |
15231 | /* Lenovo U160 cannot use SSC on LVDS */ |
15232 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15233 | |
15234 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15235 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15236 | |
be505f64 AH |
15237 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15238 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15239 | ||
15240 | /* Acer/eMachines G725 */ | |
15241 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15242 | ||
15243 | /* Acer/eMachines e725 */ | |
15244 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15245 | ||
15246 | /* Acer/Packard Bell NCL20 */ | |
15247 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15248 | ||
15249 | /* Acer Aspire 4736Z */ | |
15250 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15251 | |
15252 | /* Acer Aspire 5336 */ | |
15253 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15254 | |
15255 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15256 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15257 | |
dfb3d47b SD |
15258 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15259 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15260 | ||
b2a9601c | 15261 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15262 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15263 | ||
1b9448b0 JN |
15264 | /* Apple Macbook 4,1 */ |
15265 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15266 | ||
d4967d8c SD |
15267 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15268 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15269 | |
15270 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15271 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15272 | |
15273 | /* Dell Chromebook 11 */ | |
15274 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15275 | |
15276 | /* Dell Chromebook 11 (2015 version) */ | |
15277 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15278 | }; |
15279 | ||
15280 | static void intel_init_quirks(struct drm_device *dev) | |
15281 | { | |
15282 | struct pci_dev *d = dev->pdev; | |
15283 | int i; | |
15284 | ||
15285 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15286 | struct intel_quirk *q = &intel_quirks[i]; | |
15287 | ||
15288 | if (d->device == q->device && | |
15289 | (d->subsystem_vendor == q->subsystem_vendor || | |
15290 | q->subsystem_vendor == PCI_ANY_ID) && | |
15291 | (d->subsystem_device == q->subsystem_device || | |
15292 | q->subsystem_device == PCI_ANY_ID)) | |
15293 | q->hook(dev); | |
15294 | } | |
5f85f176 EE |
15295 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15296 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15297 | intel_dmi_quirks[i].hook(dev); | |
15298 | } | |
b690e96c JB |
15299 | } |
15300 | ||
9cce37f4 JB |
15301 | /* Disable the VGA plane that we never use */ |
15302 | static void i915_disable_vga(struct drm_device *dev) | |
15303 | { | |
15304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15305 | u8 sr1; | |
f0f59a00 | 15306 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15307 | |
2b37c616 | 15308 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15309 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15310 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15311 | sr1 = inb(VGA_SR_DATA); |
15312 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15313 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15314 | udelay(300); | |
15315 | ||
01f5a626 | 15316 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15317 | POSTING_READ(vga_reg); |
15318 | } | |
15319 | ||
f817586c DV |
15320 | void intel_modeset_init_hw(struct drm_device *dev) |
15321 | { | |
1a617b77 ML |
15322 | struct drm_i915_private *dev_priv = dev->dev_private; |
15323 | ||
b6283055 | 15324 | intel_update_cdclk(dev); |
1a617b77 ML |
15325 | |
15326 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15327 | ||
f817586c | 15328 | intel_init_clock_gating(dev); |
8090c6b9 | 15329 | intel_enable_gt_powersave(dev); |
f817586c DV |
15330 | } |
15331 | ||
d93c0372 MR |
15332 | /* |
15333 | * Calculate what we think the watermarks should be for the state we've read | |
15334 | * out of the hardware and then immediately program those watermarks so that | |
15335 | * we ensure the hardware settings match our internal state. | |
15336 | * | |
15337 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15338 | * current state (which was constructed during hardware readout) and running it | |
15339 | * through the atomic check code to calculate new watermark values in the | |
15340 | * state object. | |
15341 | */ | |
15342 | static void sanitize_watermarks(struct drm_device *dev) | |
15343 | { | |
15344 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15345 | struct drm_atomic_state *state; | |
15346 | struct drm_crtc *crtc; | |
15347 | struct drm_crtc_state *cstate; | |
15348 | struct drm_modeset_acquire_ctx ctx; | |
15349 | int ret; | |
15350 | int i; | |
15351 | ||
15352 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15353 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15354 | return; |
15355 | ||
15356 | /* | |
15357 | * We need to hold connection_mutex before calling duplicate_state so | |
15358 | * that the connector loop is protected. | |
15359 | */ | |
15360 | drm_modeset_acquire_init(&ctx, 0); | |
15361 | retry: | |
0cd1262d | 15362 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15363 | if (ret == -EDEADLK) { |
15364 | drm_modeset_backoff(&ctx); | |
15365 | goto retry; | |
15366 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15367 | goto fail; |
d93c0372 MR |
15368 | } |
15369 | ||
15370 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15371 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15372 | goto fail; |
d93c0372 | 15373 | |
ed4a6a7c MR |
15374 | /* |
15375 | * Hardware readout is the only time we don't want to calculate | |
15376 | * intermediate watermarks (since we don't trust the current | |
15377 | * watermarks). | |
15378 | */ | |
15379 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15380 | ||
d93c0372 MR |
15381 | ret = intel_atomic_check(dev, state); |
15382 | if (ret) { | |
15383 | /* | |
15384 | * If we fail here, it means that the hardware appears to be | |
15385 | * programmed in a way that shouldn't be possible, given our | |
15386 | * understanding of watermark requirements. This might mean a | |
15387 | * mistake in the hardware readout code or a mistake in the | |
15388 | * watermark calculations for a given platform. Raise a WARN | |
15389 | * so that this is noticeable. | |
15390 | * | |
15391 | * If this actually happens, we'll have to just leave the | |
15392 | * BIOS-programmed watermarks untouched and hope for the best. | |
15393 | */ | |
15394 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15395 | goto fail; |
d93c0372 MR |
15396 | } |
15397 | ||
15398 | /* Write calculated watermark values back */ | |
15399 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15400 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15401 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15402 | ||
ed4a6a7c MR |
15403 | cs->wm.need_postvbl_update = true; |
15404 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15405 | } |
15406 | ||
15407 | drm_atomic_state_free(state); | |
0cd1262d | 15408 | fail: |
d93c0372 MR |
15409 | drm_modeset_drop_locks(&ctx); |
15410 | drm_modeset_acquire_fini(&ctx); | |
15411 | } | |
15412 | ||
79e53945 JB |
15413 | void intel_modeset_init(struct drm_device *dev) |
15414 | { | |
652c393a | 15415 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15416 | int sprite, ret; |
8cc87b75 | 15417 | enum pipe pipe; |
46f297fb | 15418 | struct intel_crtc *crtc; |
79e53945 JB |
15419 | |
15420 | drm_mode_config_init(dev); | |
15421 | ||
15422 | dev->mode_config.min_width = 0; | |
15423 | dev->mode_config.min_height = 0; | |
15424 | ||
019d96cb DA |
15425 | dev->mode_config.preferred_depth = 24; |
15426 | dev->mode_config.prefer_shadow = 1; | |
15427 | ||
25bab385 TU |
15428 | dev->mode_config.allow_fb_modifiers = true; |
15429 | ||
e6ecefaa | 15430 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15431 | |
b690e96c JB |
15432 | intel_init_quirks(dev); |
15433 | ||
1fa61106 ED |
15434 | intel_init_pm(dev); |
15435 | ||
e3c74757 BW |
15436 | if (INTEL_INFO(dev)->num_pipes == 0) |
15437 | return; | |
15438 | ||
69f92f67 LW |
15439 | /* |
15440 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15441 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15442 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15443 | * indicates as much. | |
15444 | */ | |
15445 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15446 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15447 | DREF_SSC1_ENABLE); | |
15448 | ||
15449 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15450 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15451 | bios_lvds_use_ssc ? "en" : "dis", | |
15452 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15453 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15454 | } | |
15455 | } | |
15456 | ||
e70236a8 | 15457 | intel_init_display(dev); |
7c10a2b5 | 15458 | intel_init_audio(dev); |
e70236a8 | 15459 | |
a6c45cf0 CW |
15460 | if (IS_GEN2(dev)) { |
15461 | dev->mode_config.max_width = 2048; | |
15462 | dev->mode_config.max_height = 2048; | |
15463 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15464 | dev->mode_config.max_width = 4096; |
15465 | dev->mode_config.max_height = 4096; | |
79e53945 | 15466 | } else { |
a6c45cf0 CW |
15467 | dev->mode_config.max_width = 8192; |
15468 | dev->mode_config.max_height = 8192; | |
79e53945 | 15469 | } |
068be561 | 15470 | |
dc41c154 VS |
15471 | if (IS_845G(dev) || IS_I865G(dev)) { |
15472 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15473 | dev->mode_config.cursor_height = 1023; | |
15474 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15475 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15476 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15477 | } else { | |
15478 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15479 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15480 | } | |
15481 | ||
5d4545ae | 15482 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15483 | |
28c97730 | 15484 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15485 | INTEL_INFO(dev)->num_pipes, |
15486 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15487 | |
055e393f | 15488 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15489 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15490 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15491 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15492 | if (ret) |
06da8da2 | 15493 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15494 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15495 | } |
79e53945 JB |
15496 | } |
15497 | ||
bfa7df01 VS |
15498 | intel_update_czclk(dev_priv); |
15499 | intel_update_cdclk(dev); | |
15500 | ||
e72f9fbf | 15501 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15502 | |
9cce37f4 JB |
15503 | /* Just disable it once at startup */ |
15504 | i915_disable_vga(dev); | |
79e53945 | 15505 | intel_setup_outputs(dev); |
11be49eb | 15506 | |
6e9f798d | 15507 | drm_modeset_lock_all(dev); |
043e9bda | 15508 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15509 | drm_modeset_unlock_all(dev); |
46f297fb | 15510 | |
d3fcc808 | 15511 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15512 | struct intel_initial_plane_config plane_config = {}; |
15513 | ||
46f297fb JB |
15514 | if (!crtc->active) |
15515 | continue; | |
15516 | ||
46f297fb | 15517 | /* |
46f297fb JB |
15518 | * Note that reserving the BIOS fb up front prevents us |
15519 | * from stuffing other stolen allocations like the ring | |
15520 | * on top. This prevents some ugliness at boot time, and | |
15521 | * can even allow for smooth boot transitions if the BIOS | |
15522 | * fb is large enough for the active pipe configuration. | |
15523 | */ | |
eeebeac5 ML |
15524 | dev_priv->display.get_initial_plane_config(crtc, |
15525 | &plane_config); | |
15526 | ||
15527 | /* | |
15528 | * If the fb is shared between multiple heads, we'll | |
15529 | * just get the first one. | |
15530 | */ | |
15531 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15532 | } |
d93c0372 MR |
15533 | |
15534 | /* | |
15535 | * Make sure hardware watermarks really match the state we read out. | |
15536 | * Note that we need to do this after reconstructing the BIOS fb's | |
15537 | * since the watermark calculation done here will use pstate->fb. | |
15538 | */ | |
15539 | sanitize_watermarks(dev); | |
2c7111db CW |
15540 | } |
15541 | ||
7fad798e DV |
15542 | static void intel_enable_pipe_a(struct drm_device *dev) |
15543 | { | |
15544 | struct intel_connector *connector; | |
15545 | struct drm_connector *crt = NULL; | |
15546 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15547 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15548 | |
15549 | /* We can't just switch on the pipe A, we need to set things up with a | |
15550 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15551 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15552 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15553 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15554 | crt = &connector->base; | |
15555 | break; | |
15556 | } | |
15557 | } | |
15558 | ||
15559 | if (!crt) | |
15560 | return; | |
15561 | ||
208bf9fd | 15562 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15563 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15564 | } |
15565 | ||
fa555837 DV |
15566 | static bool |
15567 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15568 | { | |
7eb552ae BW |
15569 | struct drm_device *dev = crtc->base.dev; |
15570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15571 | u32 val; |
fa555837 | 15572 | |
7eb552ae | 15573 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15574 | return true; |
15575 | ||
649636ef | 15576 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15577 | |
15578 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15579 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15580 | return false; | |
15581 | ||
15582 | return true; | |
15583 | } | |
15584 | ||
02e93c35 VS |
15585 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15586 | { | |
15587 | struct drm_device *dev = crtc->base.dev; | |
15588 | struct intel_encoder *encoder; | |
15589 | ||
15590 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15591 | return true; | |
15592 | ||
15593 | return false; | |
15594 | } | |
15595 | ||
dd756198 VS |
15596 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15597 | { | |
15598 | struct drm_device *dev = encoder->base.dev; | |
15599 | struct intel_connector *connector; | |
15600 | ||
15601 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15602 | return true; | |
15603 | ||
15604 | return false; | |
15605 | } | |
15606 | ||
24929352 DV |
15607 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15608 | { | |
15609 | struct drm_device *dev = crtc->base.dev; | |
15610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15611 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15612 | |
24929352 | 15613 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15614 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15615 | ||
d3eaf884 | 15616 | /* restore vblank interrupts to correct state */ |
9625604c | 15617 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15618 | if (crtc->active) { |
f9cd7b88 VS |
15619 | struct intel_plane *plane; |
15620 | ||
9625604c | 15621 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15622 | |
15623 | /* Disable everything but the primary plane */ | |
15624 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15625 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15626 | continue; | |
15627 | ||
15628 | plane->disable_plane(&plane->base, &crtc->base); | |
15629 | } | |
9625604c | 15630 | } |
d3eaf884 | 15631 | |
24929352 | 15632 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15633 | * disable the crtc (and hence change the state) if it is wrong. Note |
15634 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15635 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15636 | bool plane; |
15637 | ||
24929352 DV |
15638 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15639 | crtc->base.base.id); | |
15640 | ||
15641 | /* Pipe has the wrong plane attached and the plane is active. | |
15642 | * Temporarily change the plane mapping and disable everything | |
15643 | * ... */ | |
15644 | plane = crtc->plane; | |
b70709a6 | 15645 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15646 | crtc->plane = !plane; |
b17d48e2 | 15647 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15648 | crtc->plane = plane; |
24929352 | 15649 | } |
24929352 | 15650 | |
7fad798e DV |
15651 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15652 | crtc->pipe == PIPE_A && !crtc->active) { | |
15653 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15654 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15655 | * call below we restore the pipe to the right state, but leave | |
15656 | * the required bits on. */ | |
15657 | intel_enable_pipe_a(dev); | |
15658 | } | |
15659 | ||
24929352 DV |
15660 | /* Adjust the state of the output pipe according to whether we |
15661 | * have active connectors/encoders. */ | |
02e93c35 | 15662 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15663 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15664 | |
53d9f4e9 | 15665 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15666 | struct intel_encoder *encoder; |
24929352 DV |
15667 | |
15668 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15669 | * functions or because of calls to intel_crtc_disable_noatomic, |
15670 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15671 | * pipe A quirk. */ |
15672 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15673 | crtc->base.base.id, | |
83d65738 | 15674 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15675 | crtc->active ? "enabled" : "disabled"); |
15676 | ||
4be40c98 | 15677 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15678 | crtc->base.state->active = crtc->active; |
24929352 | 15679 | crtc->base.enabled = crtc->active; |
2aa974c9 | 15680 | crtc->base.state->connector_mask = 0; |
e87a52b3 | 15681 | crtc->base.state->encoder_mask = 0; |
24929352 DV |
15682 | |
15683 | /* Because we only establish the connector -> encoder -> | |
15684 | * crtc links if something is active, this means the | |
15685 | * crtc is now deactivated. Break the links. connector | |
15686 | * -> encoder links are only establish when things are | |
15687 | * actually up, hence no need to break them. */ | |
15688 | WARN_ON(crtc->active); | |
15689 | ||
2d406bb0 | 15690 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15691 | encoder->base.crtc = NULL; |
24929352 | 15692 | } |
c5ab3bc0 | 15693 | |
a3ed6aad | 15694 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15695 | /* |
15696 | * We start out with underrun reporting disabled to avoid races. | |
15697 | * For correct bookkeeping mark this on active crtcs. | |
15698 | * | |
c5ab3bc0 DV |
15699 | * Also on gmch platforms we dont have any hardware bits to |
15700 | * disable the underrun reporting. Which means we need to start | |
15701 | * out with underrun reporting disabled also on inactive pipes, | |
15702 | * since otherwise we'll complain about the garbage we read when | |
15703 | * e.g. coming up after runtime pm. | |
15704 | * | |
4cc31489 DV |
15705 | * No protection against concurrent access is required - at |
15706 | * worst a fifo underrun happens which also sets this to false. | |
15707 | */ | |
15708 | crtc->cpu_fifo_underrun_disabled = true; | |
15709 | crtc->pch_fifo_underrun_disabled = true; | |
15710 | } | |
24929352 DV |
15711 | } |
15712 | ||
15713 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15714 | { | |
15715 | struct intel_connector *connector; | |
15716 | struct drm_device *dev = encoder->base.dev; | |
15717 | ||
15718 | /* We need to check both for a crtc link (meaning that the | |
15719 | * encoder is active and trying to read from a pipe) and the | |
15720 | * pipe itself being active. */ | |
15721 | bool has_active_crtc = encoder->base.crtc && | |
15722 | to_intel_crtc(encoder->base.crtc)->active; | |
15723 | ||
dd756198 | 15724 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15725 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15726 | encoder->base.base.id, | |
8e329a03 | 15727 | encoder->base.name); |
24929352 DV |
15728 | |
15729 | /* Connector is active, but has no active pipe. This is | |
15730 | * fallout from our resume register restoring. Disable | |
15731 | * the encoder manually again. */ | |
15732 | if (encoder->base.crtc) { | |
15733 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15734 | encoder->base.base.id, | |
8e329a03 | 15735 | encoder->base.name); |
24929352 | 15736 | encoder->disable(encoder); |
a62d1497 VS |
15737 | if (encoder->post_disable) |
15738 | encoder->post_disable(encoder); | |
24929352 | 15739 | } |
7f1950fb | 15740 | encoder->base.crtc = NULL; |
24929352 DV |
15741 | |
15742 | /* Inconsistent output/port/pipe state happens presumably due to | |
15743 | * a bug in one of the get_hw_state functions. Or someplace else | |
15744 | * in our code, like the register restore mess on resume. Clamp | |
15745 | * things to off as a safer default. */ | |
3a3371ff | 15746 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15747 | if (connector->encoder != encoder) |
15748 | continue; | |
7f1950fb EE |
15749 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15750 | connector->base.encoder = NULL; | |
24929352 DV |
15751 | } |
15752 | } | |
15753 | /* Enabled encoders without active connectors will be fixed in | |
15754 | * the crtc fixup. */ | |
15755 | } | |
15756 | ||
04098753 | 15757 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15758 | { |
15759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15760 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15761 | |
04098753 ID |
15762 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15763 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15764 | i915_disable_vga(dev); | |
15765 | } | |
15766 | } | |
15767 | ||
15768 | void i915_redisable_vga(struct drm_device *dev) | |
15769 | { | |
15770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15771 | ||
8dc8a27c PZ |
15772 | /* This function can be called both from intel_modeset_setup_hw_state or |
15773 | * at a very early point in our resume sequence, where the power well | |
15774 | * structures are not yet restored. Since this function is at a very | |
15775 | * paranoid "someone might have enabled VGA while we were not looking" | |
15776 | * level, just check if the power well is enabled instead of trying to | |
15777 | * follow the "don't touch the power well if we don't need it" policy | |
15778 | * the rest of the driver uses. */ | |
6392f847 | 15779 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15780 | return; |
15781 | ||
04098753 | 15782 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15783 | |
15784 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15785 | } |
15786 | ||
f9cd7b88 | 15787 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15788 | { |
f9cd7b88 | 15789 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15790 | |
f9cd7b88 | 15791 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15792 | } |
15793 | ||
f9cd7b88 VS |
15794 | /* FIXME read out full plane state for all planes */ |
15795 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15796 | { |
b26d3ea3 | 15797 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15798 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15799 | to_intel_plane_state(primary->state); |
d032ffa0 | 15800 | |
19b8d387 | 15801 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15802 | primary_get_hw_state(to_intel_plane(primary)); |
15803 | ||
15804 | if (plane_state->visible) | |
15805 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15806 | } |
15807 | ||
30e984df | 15808 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15809 | { |
15810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15811 | enum pipe pipe; | |
24929352 DV |
15812 | struct intel_crtc *crtc; |
15813 | struct intel_encoder *encoder; | |
15814 | struct intel_connector *connector; | |
5358901f | 15815 | int i; |
24929352 | 15816 | |
565602d7 ML |
15817 | dev_priv->active_crtcs = 0; |
15818 | ||
d3fcc808 | 15819 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15820 | struct intel_crtc_state *crtc_state = crtc->config; |
15821 | int pixclk = 0; | |
3b117c8f | 15822 | |
565602d7 ML |
15823 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15824 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15825 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15826 | |
565602d7 ML |
15827 | crtc_state->base.active = crtc_state->base.enable = |
15828 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15829 | ||
15830 | crtc->base.enabled = crtc_state->base.enable; | |
15831 | crtc->active = crtc_state->base.active; | |
15832 | ||
15833 | if (crtc_state->base.active) { | |
15834 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15835 | ||
15836 | if (IS_BROADWELL(dev_priv)) { | |
15837 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15838 | ||
15839 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15840 | if (crtc_state->ips_enabled) | |
15841 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15842 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15843 | IS_CHERRYVIEW(dev_priv) || | |
15844 | IS_BROXTON(dev_priv)) | |
15845 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15846 | else | |
15847 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15848 | } | |
15849 | ||
15850 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15851 | |
f9cd7b88 | 15852 | readout_plane_state(crtc); |
24929352 DV |
15853 | |
15854 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15855 | crtc->base.base.id, | |
15856 | crtc->active ? "enabled" : "disabled"); | |
15857 | } | |
15858 | ||
5358901f DV |
15859 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15860 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15861 | ||
3e369b76 ACO |
15862 | pll->on = pll->get_hw_state(dev_priv, pll, |
15863 | &pll->config.hw_state); | |
5358901f | 15864 | pll->active = 0; |
3e369b76 | 15865 | pll->config.crtc_mask = 0; |
d3fcc808 | 15866 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15867 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15868 | pll->active++; |
3e369b76 | 15869 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15870 | } |
5358901f | 15871 | } |
5358901f | 15872 | |
1e6f2ddc | 15873 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15874 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15875 | |
3e369b76 | 15876 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15877 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15878 | } |
15879 | ||
b2784e15 | 15880 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15881 | pipe = 0; |
15882 | ||
15883 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15884 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15885 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15886 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15887 | } else { |
15888 | encoder->base.crtc = NULL; | |
15889 | } | |
15890 | ||
6f2bcceb | 15891 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15892 | encoder->base.base.id, |
8e329a03 | 15893 | encoder->base.name, |
24929352 | 15894 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15895 | pipe_name(pipe)); |
24929352 DV |
15896 | } |
15897 | ||
3a3371ff | 15898 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15899 | if (connector->get_hw_state(connector)) { |
15900 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15901 | |
15902 | encoder = connector->encoder; | |
15903 | connector->base.encoder = &encoder->base; | |
15904 | ||
15905 | if (encoder->base.crtc && | |
15906 | encoder->base.crtc->state->active) { | |
15907 | /* | |
15908 | * This has to be done during hardware readout | |
15909 | * because anything calling .crtc_disable may | |
15910 | * rely on the connector_mask being accurate. | |
15911 | */ | |
15912 | encoder->base.crtc->state->connector_mask |= | |
15913 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15914 | encoder->base.crtc->state->encoder_mask |= |
15915 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15916 | } |
15917 | ||
24929352 DV |
15918 | } else { |
15919 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15920 | connector->base.encoder = NULL; | |
15921 | } | |
15922 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15923 | connector->base.base.id, | |
c23cc417 | 15924 | connector->base.name, |
24929352 DV |
15925 | connector->base.encoder ? "enabled" : "disabled"); |
15926 | } | |
7f4c6284 VS |
15927 | |
15928 | for_each_intel_crtc(dev, crtc) { | |
15929 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15930 | ||
15931 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15932 | if (crtc->base.state->active) { | |
15933 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15934 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15935 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15936 | ||
15937 | /* | |
15938 | * The initial mode needs to be set in order to keep | |
15939 | * the atomic core happy. It wants a valid mode if the | |
15940 | * crtc's enabled, so we do the above call. | |
15941 | * | |
15942 | * At this point some state updated by the connectors | |
15943 | * in their ->detect() callback has not run yet, so | |
15944 | * no recalculation can be done yet. | |
15945 | * | |
15946 | * Even if we could do a recalculation and modeset | |
15947 | * right now it would cause a double modeset if | |
15948 | * fbdev or userspace chooses a different initial mode. | |
15949 | * | |
15950 | * If that happens, someone indicated they wanted a | |
15951 | * mode change, which means it's safe to do a full | |
15952 | * recalculation. | |
15953 | */ | |
15954 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15955 | |
15956 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15957 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15958 | } |
15959 | } | |
30e984df DV |
15960 | } |
15961 | ||
043e9bda ML |
15962 | /* Scan out the current hw modeset state, |
15963 | * and sanitizes it to the current state | |
15964 | */ | |
15965 | static void | |
15966 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15967 | { |
15968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15969 | enum pipe pipe; | |
30e984df DV |
15970 | struct intel_crtc *crtc; |
15971 | struct intel_encoder *encoder; | |
35c95375 | 15972 | int i; |
30e984df DV |
15973 | |
15974 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15975 | |
15976 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15977 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15978 | intel_sanitize_encoder(encoder); |
15979 | } | |
15980 | ||
055e393f | 15981 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15982 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15983 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15984 | intel_dump_pipe_config(crtc, crtc->config, |
15985 | "[setup_hw_state]"); | |
24929352 | 15986 | } |
9a935856 | 15987 | |
d29b2f9d ACO |
15988 | intel_modeset_update_connector_atomic_state(dev); |
15989 | ||
35c95375 DV |
15990 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15991 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15992 | ||
15993 | if (!pll->on || pll->active) | |
15994 | continue; | |
15995 | ||
15996 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15997 | ||
15998 | pll->disable(dev_priv, pll); | |
15999 | pll->on = false; | |
16000 | } | |
16001 | ||
666a4537 | 16002 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16003 | vlv_wm_get_hw_state(dev); |
16004 | else if (IS_GEN9(dev)) | |
3078999f PB |
16005 | skl_wm_get_hw_state(dev); |
16006 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16007 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16008 | |
16009 | for_each_intel_crtc(dev, crtc) { | |
16010 | unsigned long put_domains; | |
16011 | ||
74bff5f9 | 16012 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16013 | if (WARN_ON(put_domains)) |
16014 | modeset_put_power_domains(dev_priv, put_domains); | |
16015 | } | |
16016 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16017 | |
16018 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16019 | } |
7d0bc1ea | 16020 | |
043e9bda ML |
16021 | void intel_display_resume(struct drm_device *dev) |
16022 | { | |
e2c8b870 ML |
16023 | struct drm_i915_private *dev_priv = to_i915(dev); |
16024 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16025 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16026 | int ret; |
e2c8b870 | 16027 | bool setup = false; |
f30da187 | 16028 | |
e2c8b870 | 16029 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 16030 | |
ea49c9ac ML |
16031 | /* |
16032 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16033 | * won't be taken. Unfortunately some probed state like | |
16034 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16035 | * it here for now. | |
16036 | */ | |
16037 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16038 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16039 | |
e2c8b870 ML |
16040 | retry: |
16041 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 16042 | |
e2c8b870 ML |
16043 | if (ret == 0 && !setup) { |
16044 | setup = true; | |
043e9bda | 16045 | |
e2c8b870 ML |
16046 | intel_modeset_setup_hw_state(dev); |
16047 | i915_redisable_vga(dev); | |
45e2b5f6 | 16048 | } |
8af6cf88 | 16049 | |
e2c8b870 ML |
16050 | if (ret == 0 && state) { |
16051 | struct drm_crtc_state *crtc_state; | |
16052 | struct drm_crtc *crtc; | |
16053 | int i; | |
043e9bda | 16054 | |
e2c8b870 ML |
16055 | state->acquire_ctx = &ctx; |
16056 | ||
16057 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
16058 | /* | |
16059 | * Force recalculation even if we restore | |
16060 | * current state. With fast modeset this may not result | |
16061 | * in a modeset when the state is compatible. | |
16062 | */ | |
16063 | crtc_state->mode_changed = true; | |
16064 | } | |
16065 | ||
16066 | ret = drm_atomic_commit(state); | |
043e9bda ML |
16067 | } |
16068 | ||
e2c8b870 ML |
16069 | if (ret == -EDEADLK) { |
16070 | drm_modeset_backoff(&ctx); | |
16071 | goto retry; | |
16072 | } | |
043e9bda | 16073 | |
e2c8b870 ML |
16074 | drm_modeset_drop_locks(&ctx); |
16075 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16076 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16077 | |
e2c8b870 ML |
16078 | if (ret) { |
16079 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16080 | drm_atomic_state_free(state); | |
16081 | } | |
2c7111db CW |
16082 | } |
16083 | ||
16084 | void intel_modeset_gem_init(struct drm_device *dev) | |
16085 | { | |
484b41dd | 16086 | struct drm_crtc *c; |
2ff8fde1 | 16087 | struct drm_i915_gem_object *obj; |
e0d6149b | 16088 | int ret; |
484b41dd | 16089 | |
ae48434c | 16090 | intel_init_gt_powersave(dev); |
ae48434c | 16091 | |
1833b134 | 16092 | intel_modeset_init_hw(dev); |
02e792fb DV |
16093 | |
16094 | intel_setup_overlay(dev); | |
484b41dd JB |
16095 | |
16096 | /* | |
16097 | * Make sure any fbs we allocated at startup are properly | |
16098 | * pinned & fenced. When we do the allocation it's too early | |
16099 | * for this. | |
16100 | */ | |
70e1e0ec | 16101 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16102 | obj = intel_fb_obj(c->primary->fb); |
16103 | if (obj == NULL) | |
484b41dd JB |
16104 | continue; |
16105 | ||
e0d6149b TU |
16106 | mutex_lock(&dev->struct_mutex); |
16107 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
16108 | c->primary->fb, | |
7580d774 | 16109 | c->primary->state); |
e0d6149b TU |
16110 | mutex_unlock(&dev->struct_mutex); |
16111 | if (ret) { | |
484b41dd JB |
16112 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16113 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16114 | drm_framebuffer_unreference(c->primary->fb); |
16115 | c->primary->fb = NULL; | |
36750f28 | 16116 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16117 | update_state_fb(c->primary); |
36750f28 | 16118 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16119 | } |
16120 | } | |
0962c3c9 VS |
16121 | |
16122 | intel_backlight_register(dev); | |
79e53945 JB |
16123 | } |
16124 | ||
4932e2c3 ID |
16125 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16126 | { | |
16127 | struct drm_connector *connector = &intel_connector->base; | |
16128 | ||
16129 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16130 | drm_connector_unregister(connector); |
4932e2c3 ID |
16131 | } |
16132 | ||
79e53945 JB |
16133 | void intel_modeset_cleanup(struct drm_device *dev) |
16134 | { | |
652c393a | 16135 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16136 | struct intel_connector *connector; |
652c393a | 16137 | |
2eb5252e ID |
16138 | intel_disable_gt_powersave(dev); |
16139 | ||
0962c3c9 VS |
16140 | intel_backlight_unregister(dev); |
16141 | ||
fd0c0642 DV |
16142 | /* |
16143 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16144 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16145 | * experience fancy races otherwise. |
16146 | */ | |
2aeb7d3a | 16147 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16148 | |
fd0c0642 DV |
16149 | /* |
16150 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16151 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16152 | */ | |
f87ea761 | 16153 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16154 | |
723bfd70 JB |
16155 | intel_unregister_dsm_handler(); |
16156 | ||
c937ab3e | 16157 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16158 | |
1630fe75 CW |
16159 | /* flush any delayed tasks or pending work */ |
16160 | flush_scheduled_work(); | |
16161 | ||
db31af1d | 16162 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16163 | for_each_intel_connector(dev, connector) |
16164 | connector->unregister(connector); | |
d9255d57 | 16165 | |
79e53945 | 16166 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16167 | |
16168 | intel_cleanup_overlay(dev); | |
ae48434c | 16169 | |
ae48434c | 16170 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
16171 | |
16172 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16173 | } |
16174 | ||
f1c79df3 ZW |
16175 | /* |
16176 | * Return which encoder is currently attached for connector. | |
16177 | */ | |
df0e9248 | 16178 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16179 | { |
df0e9248 CW |
16180 | return &intel_attached_encoder(connector)->base; |
16181 | } | |
f1c79df3 | 16182 | |
df0e9248 CW |
16183 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16184 | struct intel_encoder *encoder) | |
16185 | { | |
16186 | connector->encoder = encoder; | |
16187 | drm_mode_connector_attach_encoder(&connector->base, | |
16188 | &encoder->base); | |
79e53945 | 16189 | } |
28d52043 DA |
16190 | |
16191 | /* | |
16192 | * set vga decode state - true == enable VGA decode | |
16193 | */ | |
16194 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16195 | { | |
16196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16197 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16198 | u16 gmch_ctrl; |
16199 | ||
75fa041d CW |
16200 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16201 | DRM_ERROR("failed to read control word\n"); | |
16202 | return -EIO; | |
16203 | } | |
16204 | ||
c0cc8a55 CW |
16205 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16206 | return 0; | |
16207 | ||
28d52043 DA |
16208 | if (state) |
16209 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16210 | else | |
16211 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16212 | |
16213 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16214 | DRM_ERROR("failed to write control word\n"); | |
16215 | return -EIO; | |
16216 | } | |
16217 | ||
28d52043 DA |
16218 | return 0; |
16219 | } | |
c4a1d9e4 | 16220 | |
c4a1d9e4 | 16221 | struct intel_display_error_state { |
ff57f1b0 PZ |
16222 | |
16223 | u32 power_well_driver; | |
16224 | ||
63b66e5b CW |
16225 | int num_transcoders; |
16226 | ||
c4a1d9e4 CW |
16227 | struct intel_cursor_error_state { |
16228 | u32 control; | |
16229 | u32 position; | |
16230 | u32 base; | |
16231 | u32 size; | |
52331309 | 16232 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16233 | |
16234 | struct intel_pipe_error_state { | |
ddf9c536 | 16235 | bool power_domain_on; |
c4a1d9e4 | 16236 | u32 source; |
f301b1e1 | 16237 | u32 stat; |
52331309 | 16238 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16239 | |
16240 | struct intel_plane_error_state { | |
16241 | u32 control; | |
16242 | u32 stride; | |
16243 | u32 size; | |
16244 | u32 pos; | |
16245 | u32 addr; | |
16246 | u32 surface; | |
16247 | u32 tile_offset; | |
52331309 | 16248 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16249 | |
16250 | struct intel_transcoder_error_state { | |
ddf9c536 | 16251 | bool power_domain_on; |
63b66e5b CW |
16252 | enum transcoder cpu_transcoder; |
16253 | ||
16254 | u32 conf; | |
16255 | ||
16256 | u32 htotal; | |
16257 | u32 hblank; | |
16258 | u32 hsync; | |
16259 | u32 vtotal; | |
16260 | u32 vblank; | |
16261 | u32 vsync; | |
16262 | } transcoder[4]; | |
c4a1d9e4 CW |
16263 | }; |
16264 | ||
16265 | struct intel_display_error_state * | |
16266 | intel_display_capture_error_state(struct drm_device *dev) | |
16267 | { | |
fbee40df | 16268 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16269 | struct intel_display_error_state *error; |
63b66e5b CW |
16270 | int transcoders[] = { |
16271 | TRANSCODER_A, | |
16272 | TRANSCODER_B, | |
16273 | TRANSCODER_C, | |
16274 | TRANSCODER_EDP, | |
16275 | }; | |
c4a1d9e4 CW |
16276 | int i; |
16277 | ||
63b66e5b CW |
16278 | if (INTEL_INFO(dev)->num_pipes == 0) |
16279 | return NULL; | |
16280 | ||
9d1cb914 | 16281 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16282 | if (error == NULL) |
16283 | return NULL; | |
16284 | ||
190be112 | 16285 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16286 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16287 | ||
055e393f | 16288 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16289 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16290 | __intel_display_power_is_enabled(dev_priv, |
16291 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16292 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16293 | continue; |
16294 | ||
5efb3e28 VS |
16295 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16296 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16297 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16298 | |
16299 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16300 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16301 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16302 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16303 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16304 | } | |
ca291363 PZ |
16305 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16306 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16307 | if (INTEL_INFO(dev)->gen >= 4) { |
16308 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16309 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16310 | } | |
16311 | ||
c4a1d9e4 | 16312 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16313 | |
3abfce77 | 16314 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16315 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16316 | } |
16317 | ||
16318 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16319 | if (HAS_DDI(dev_priv->dev)) | |
16320 | error->num_transcoders++; /* Account for eDP. */ | |
16321 | ||
16322 | for (i = 0; i < error->num_transcoders; i++) { | |
16323 | enum transcoder cpu_transcoder = transcoders[i]; | |
16324 | ||
ddf9c536 | 16325 | error->transcoder[i].power_domain_on = |
f458ebbc | 16326 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16327 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16328 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16329 | continue; |
16330 | ||
63b66e5b CW |
16331 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16332 | ||
16333 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16334 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16335 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16336 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16337 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16338 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16339 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16340 | } |
16341 | ||
16342 | return error; | |
16343 | } | |
16344 | ||
edc3d884 MK |
16345 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16346 | ||
c4a1d9e4 | 16347 | void |
edc3d884 | 16348 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16349 | struct drm_device *dev, |
16350 | struct intel_display_error_state *error) | |
16351 | { | |
055e393f | 16352 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16353 | int i; |
16354 | ||
63b66e5b CW |
16355 | if (!error) |
16356 | return; | |
16357 | ||
edc3d884 | 16358 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16359 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16360 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16361 | error->power_well_driver); |
055e393f | 16362 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16363 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16364 | err_printf(m, " Power: %s\n", |
87ad3212 | 16365 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16366 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16367 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16368 | |
16369 | err_printf(m, "Plane [%d]:\n", i); | |
16370 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16371 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16372 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16373 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16374 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16375 | } |
4b71a570 | 16376 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16377 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16378 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16379 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16380 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16381 | } |
16382 | ||
edc3d884 MK |
16383 | err_printf(m, "Cursor [%d]:\n", i); |
16384 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16385 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16386 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16387 | } |
63b66e5b CW |
16388 | |
16389 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16390 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16391 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16392 | err_printf(m, " Power: %s\n", |
87ad3212 | 16393 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16394 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16395 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16396 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16397 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16398 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16399 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16400 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16401 | } | |
c4a1d9e4 | 16402 | } |