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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
54 | ||
55 | ||
79e53945 | 56 | typedef struct { |
0206e353 | 57 | int min, max; |
79e53945 JB |
58 | } intel_range_t; |
59 | ||
60 | typedef struct { | |
0206e353 AJ |
61 | int dot_limit; |
62 | int p2_slow, p2_fast; | |
79e53945 JB |
63 | } intel_p2_t; |
64 | ||
d4906093 ML |
65 | typedef struct intel_limit intel_limit_t; |
66 | struct intel_limit { | |
0206e353 AJ |
67 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
68 | intel_p2_t p2; | |
d4906093 | 69 | }; |
79e53945 | 70 | |
d2acd215 DV |
71 | int |
72 | intel_pch_rawclk(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | ||
76 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
77 | ||
78 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
79 | } | |
80 | ||
021357ac CW |
81 | static inline u32 /* units of 100MHz */ |
82 | intel_fdi_link_freq(struct drm_device *dev) | |
83 | { | |
8b99e68c CW |
84 | if (IS_GEN5(dev)) { |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
87 | } else | |
88 | return 27; | |
021357ac CW |
89 | } |
90 | ||
5d536e28 | 91 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 AJ |
92 | .dot = { .min = 25000, .max = 350000 }, |
93 | .vco = { .min = 930000, .max = 1400000 }, | |
94 | .n = { .min = 3, .max = 16 }, | |
95 | .m = { .min = 96, .max = 140 }, | |
96 | .m1 = { .min = 18, .max = 26 }, | |
97 | .m2 = { .min = 6, .max = 16 }, | |
98 | .p = { .min = 4, .max = 128 }, | |
99 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
100 | .p2 = { .dot_limit = 165000, |
101 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
102 | }; |
103 | ||
5d536e28 DV |
104 | static const intel_limit_t intel_limits_i8xx_dvo = { |
105 | .dot = { .min = 25000, .max = 350000 }, | |
106 | .vco = { .min = 930000, .max = 1400000 }, | |
107 | .n = { .min = 3, .max = 16 }, | |
108 | .m = { .min = 96, .max = 140 }, | |
109 | .m1 = { .min = 18, .max = 26 }, | |
110 | .m2 = { .min = 6, .max = 16 }, | |
111 | .p = { .min = 4, .max = 128 }, | |
112 | .p1 = { .min = 2, .max = 33 }, | |
113 | .p2 = { .dot_limit = 165000, | |
114 | .p2_slow = 4, .p2_fast = 4 }, | |
115 | }; | |
116 | ||
e4b36699 | 117 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 AJ |
118 | .dot = { .min = 25000, .max = 350000 }, |
119 | .vco = { .min = 930000, .max = 1400000 }, | |
120 | .n = { .min = 3, .max = 16 }, | |
121 | .m = { .min = 96, .max = 140 }, | |
122 | .m1 = { .min = 18, .max = 26 }, | |
123 | .m2 = { .min = 6, .max = 16 }, | |
124 | .p = { .min = 4, .max = 128 }, | |
125 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
126 | .p2 = { .dot_limit = 165000, |
127 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 128 | }; |
273e27ca | 129 | |
e4b36699 | 130 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
131 | .dot = { .min = 20000, .max = 400000 }, |
132 | .vco = { .min = 1400000, .max = 2800000 }, | |
133 | .n = { .min = 1, .max = 6 }, | |
134 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
135 | .m1 = { .min = 8, .max = 18 }, |
136 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
137 | .p = { .min = 5, .max = 80 }, |
138 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 200000, |
140 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
141 | }; |
142 | ||
143 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
144 | .dot = { .min = 20000, .max = 400000 }, |
145 | .vco = { .min = 1400000, .max = 2800000 }, | |
146 | .n = { .min = 1, .max = 6 }, | |
147 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
148 | .m1 = { .min = 8, .max = 18 }, |
149 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
150 | .p = { .min = 7, .max = 98 }, |
151 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
152 | .p2 = { .dot_limit = 112000, |
153 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
154 | }; |
155 | ||
273e27ca | 156 | |
e4b36699 | 157 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
158 | .dot = { .min = 25000, .max = 270000 }, |
159 | .vco = { .min = 1750000, .max = 3500000}, | |
160 | .n = { .min = 1, .max = 4 }, | |
161 | .m = { .min = 104, .max = 138 }, | |
162 | .m1 = { .min = 17, .max = 23 }, | |
163 | .m2 = { .min = 5, .max = 11 }, | |
164 | .p = { .min = 10, .max = 30 }, | |
165 | .p1 = { .min = 1, .max = 3}, | |
166 | .p2 = { .dot_limit = 270000, | |
167 | .p2_slow = 10, | |
168 | .p2_fast = 10 | |
044c7c41 | 169 | }, |
e4b36699 KP |
170 | }; |
171 | ||
172 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
173 | .dot = { .min = 22000, .max = 400000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 16, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 5, .max = 80 }, | |
180 | .p1 = { .min = 1, .max = 8}, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
186 | .dot = { .min = 20000, .max = 115000 }, |
187 | .vco = { .min = 1750000, .max = 3500000 }, | |
188 | .n = { .min = 1, .max = 3 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 17, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 28, .max = 112 }, | |
193 | .p1 = { .min = 2, .max = 8 }, | |
194 | .p2 = { .dot_limit = 0, | |
195 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 196 | }, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 80000, .max = 224000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 14, .max = 42 }, | |
207 | .p1 = { .min = 2, .max = 6 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 210 | }, |
e4b36699 KP |
211 | }; |
212 | ||
f2b115e6 | 213 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
214 | .dot = { .min = 20000, .max = 400000}, |
215 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 216 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
217 | .n = { .min = 3, .max = 6 }, |
218 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 219 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
220 | .m1 = { .min = 0, .max = 0 }, |
221 | .m2 = { .min = 0, .max = 254 }, | |
222 | .p = { .min = 5, .max = 80 }, | |
223 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
224 | .p2 = { .dot_limit = 200000, |
225 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000 }, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
231 | .n = { .min = 3, .max = 6 }, | |
232 | .m = { .min = 2, .max = 256 }, | |
233 | .m1 = { .min = 0, .max = 0 }, | |
234 | .m2 = { .min = 0, .max = 254 }, | |
235 | .p = { .min = 7, .max = 112 }, | |
236 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 112000, |
238 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
239 | }; |
240 | ||
273e27ca EA |
241 | /* Ironlake / Sandybridge |
242 | * | |
243 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
244 | * the range value for them is (actual_value - 2). | |
245 | */ | |
b91ad0ec | 246 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
247 | .dot = { .min = 25000, .max = 350000 }, |
248 | .vco = { .min = 1760000, .max = 3510000 }, | |
249 | .n = { .min = 1, .max = 5 }, | |
250 | .m = { .min = 79, .max = 127 }, | |
251 | .m1 = { .min = 12, .max = 22 }, | |
252 | .m2 = { .min = 5, .max = 9 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
255 | .p2 = { .dot_limit = 225000, | |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
257 | }; |
258 | ||
b91ad0ec | 259 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
260 | .dot = { .min = 25000, .max = 350000 }, |
261 | .vco = { .min = 1760000, .max = 3510000 }, | |
262 | .n = { .min = 1, .max = 3 }, | |
263 | .m = { .min = 79, .max = 118 }, | |
264 | .m1 = { .min = 12, .max = 22 }, | |
265 | .m2 = { .min = 5, .max = 9 }, | |
266 | .p = { .min = 28, .max = 112 }, | |
267 | .p1 = { .min = 2, .max = 8 }, | |
268 | .p2 = { .dot_limit = 225000, | |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
270 | }; |
271 | ||
272 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
273 | .dot = { .min = 25000, .max = 350000 }, |
274 | .vco = { .min = 1760000, .max = 3510000 }, | |
275 | .n = { .min = 1, .max = 3 }, | |
276 | .m = { .min = 79, .max = 127 }, | |
277 | .m1 = { .min = 12, .max = 22 }, | |
278 | .m2 = { .min = 5, .max = 9 }, | |
279 | .p = { .min = 14, .max = 56 }, | |
280 | .p1 = { .min = 2, .max = 8 }, | |
281 | .p2 = { .dot_limit = 225000, | |
282 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
283 | }; |
284 | ||
273e27ca | 285 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 286 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
287 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, | |
289 | .n = { .min = 1, .max = 2 }, | |
290 | .m = { .min = 79, .max = 126 }, | |
291 | .m1 = { .min = 12, .max = 22 }, | |
292 | .m2 = { .min = 5, .max = 9 }, | |
293 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 294 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
295 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
297 | }; |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 126 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 307 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
308 | .p2 = { .dot_limit = 225000, |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
310 | }; |
311 | ||
dc730512 | 312 | static const intel_limit_t intel_limits_vlv = { |
75e53986 DV |
313 | .dot = { .min = 25000, .max = 270000 }, |
314 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 | 315 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
316 | .m1 = { .min = 2, .max = 3 }, |
317 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 318 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 319 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
320 | }; |
321 | ||
6b4bf1c4 VS |
322 | static void vlv_clock(int refclk, intel_clock_t *clock) |
323 | { | |
324 | clock->m = clock->m1 * clock->m2; | |
325 | clock->p = clock->p1 * clock->p2; | |
326 | clock->vco = refclk * clock->m / clock->n; | |
327 | clock->dot = clock->vco / clock->p; | |
328 | } | |
329 | ||
e0638cdf PZ |
330 | /** |
331 | * Returns whether any output on the specified pipe is of the specified type | |
332 | */ | |
333 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
334 | { | |
335 | struct drm_device *dev = crtc->dev; | |
336 | struct intel_encoder *encoder; | |
337 | ||
338 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
339 | if (encoder->type == type) | |
340 | return true; | |
341 | ||
342 | return false; | |
343 | } | |
344 | ||
1b894b59 CW |
345 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
346 | int refclk) | |
2c07245f | 347 | { |
b91ad0ec | 348 | struct drm_device *dev = crtc->dev; |
2c07245f | 349 | const intel_limit_t *limit; |
b91ad0ec ZW |
350 | |
351 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 352 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 353 | if (refclk == 100000) |
b91ad0ec ZW |
354 | limit = &intel_limits_ironlake_dual_lvds_100m; |
355 | else | |
356 | limit = &intel_limits_ironlake_dual_lvds; | |
357 | } else { | |
1b894b59 | 358 | if (refclk == 100000) |
b91ad0ec ZW |
359 | limit = &intel_limits_ironlake_single_lvds_100m; |
360 | else | |
361 | limit = &intel_limits_ironlake_single_lvds; | |
362 | } | |
c6bb3538 | 363 | } else |
b91ad0ec | 364 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
365 | |
366 | return limit; | |
367 | } | |
368 | ||
044c7c41 ML |
369 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
370 | { | |
371 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
372 | const intel_limit_t *limit; |
373 | ||
374 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 375 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 376 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 377 | else |
e4b36699 | 378 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
379 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
380 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 381 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 382 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 383 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 384 | } else /* The option is for other outputs */ |
e4b36699 | 385 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
386 | |
387 | return limit; | |
388 | } | |
389 | ||
1b894b59 | 390 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
391 | { |
392 | struct drm_device *dev = crtc->dev; | |
393 | const intel_limit_t *limit; | |
394 | ||
bad720ff | 395 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 396 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 397 | else if (IS_G4X(dev)) { |
044c7c41 | 398 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 399 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 400 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 401 | limit = &intel_limits_pineview_lvds; |
2177832f | 402 | else |
f2b115e6 | 403 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 404 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 405 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
406 | } else if (!IS_GEN2(dev)) { |
407 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
408 | limit = &intel_limits_i9xx_lvds; | |
409 | else | |
410 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
411 | } else { |
412 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 413 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 414 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 415 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
416 | else |
417 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
418 | } |
419 | return limit; | |
420 | } | |
421 | ||
f2b115e6 AJ |
422 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
423 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 424 | { |
2177832f SL |
425 | clock->m = clock->m2 + 2; |
426 | clock->p = clock->p1 * clock->p2; | |
427 | clock->vco = refclk * clock->m / clock->n; | |
428 | clock->dot = clock->vco / clock->p; | |
429 | } | |
430 | ||
7429e9d4 DV |
431 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
432 | { | |
433 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
434 | } | |
435 | ||
ac58c3f0 | 436 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 437 | { |
7429e9d4 | 438 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 JB |
439 | clock->p = clock->p1 * clock->p2; |
440 | clock->vco = refclk * clock->m / (clock->n + 2); | |
441 | clock->dot = clock->vco / clock->p; | |
442 | } | |
443 | ||
7c04d1d9 | 444 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
445 | /** |
446 | * Returns whether the given set of divisors are valid for a given refclk with | |
447 | * the given connectors. | |
448 | */ | |
449 | ||
1b894b59 CW |
450 | static bool intel_PLL_is_valid(struct drm_device *dev, |
451 | const intel_limit_t *limit, | |
452 | const intel_clock_t *clock) | |
79e53945 | 453 | { |
79e53945 | 454 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 455 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 456 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 457 | INTELPllInvalid("p out of range\n"); |
79e53945 | 458 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 459 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 460 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 461 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 462 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 463 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 464 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 465 | INTELPllInvalid("m out of range\n"); |
79e53945 | 466 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 467 | INTELPllInvalid("n out of range\n"); |
79e53945 | 468 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 469 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
470 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
471 | * connector, etc., rather than just a single range. | |
472 | */ | |
473 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 474 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
475 | |
476 | return true; | |
477 | } | |
478 | ||
d4906093 | 479 | static bool |
ee9300bb | 480 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
481 | int target, int refclk, intel_clock_t *match_clock, |
482 | intel_clock_t *best_clock) | |
79e53945 JB |
483 | { |
484 | struct drm_device *dev = crtc->dev; | |
79e53945 | 485 | intel_clock_t clock; |
79e53945 JB |
486 | int err = target; |
487 | ||
a210b028 | 488 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 489 | /* |
a210b028 DV |
490 | * For LVDS just rely on its current settings for dual-channel. |
491 | * We haven't figured out how to reliably set up different | |
492 | * single/dual channel state, if we even can. | |
79e53945 | 493 | */ |
1974cad0 | 494 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
495 | clock.p2 = limit->p2.p2_fast; |
496 | else | |
497 | clock.p2 = limit->p2.p2_slow; | |
498 | } else { | |
499 | if (target < limit->p2.dot_limit) | |
500 | clock.p2 = limit->p2.p2_slow; | |
501 | else | |
502 | clock.p2 = limit->p2.p2_fast; | |
503 | } | |
504 | ||
0206e353 | 505 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 506 | |
42158660 ZY |
507 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
508 | clock.m1++) { | |
509 | for (clock.m2 = limit->m2.min; | |
510 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 511 | if (clock.m2 >= clock.m1) |
42158660 ZY |
512 | break; |
513 | for (clock.n = limit->n.min; | |
514 | clock.n <= limit->n.max; clock.n++) { | |
515 | for (clock.p1 = limit->p1.min; | |
516 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
517 | int this_err; |
518 | ||
ac58c3f0 DV |
519 | i9xx_clock(refclk, &clock); |
520 | if (!intel_PLL_is_valid(dev, limit, | |
521 | &clock)) | |
522 | continue; | |
523 | if (match_clock && | |
524 | clock.p != match_clock->p) | |
525 | continue; | |
526 | ||
527 | this_err = abs(clock.dot - target); | |
528 | if (this_err < err) { | |
529 | *best_clock = clock; | |
530 | err = this_err; | |
531 | } | |
532 | } | |
533 | } | |
534 | } | |
535 | } | |
536 | ||
537 | return (err != target); | |
538 | } | |
539 | ||
540 | static bool | |
ee9300bb DV |
541 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
542 | int target, int refclk, intel_clock_t *match_clock, | |
543 | intel_clock_t *best_clock) | |
79e53945 JB |
544 | { |
545 | struct drm_device *dev = crtc->dev; | |
79e53945 | 546 | intel_clock_t clock; |
79e53945 JB |
547 | int err = target; |
548 | ||
a210b028 | 549 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 550 | /* |
a210b028 DV |
551 | * For LVDS just rely on its current settings for dual-channel. |
552 | * We haven't figured out how to reliably set up different | |
553 | * single/dual channel state, if we even can. | |
79e53945 | 554 | */ |
1974cad0 | 555 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
556 | clock.p2 = limit->p2.p2_fast; |
557 | else | |
558 | clock.p2 = limit->p2.p2_slow; | |
559 | } else { | |
560 | if (target < limit->p2.dot_limit) | |
561 | clock.p2 = limit->p2.p2_slow; | |
562 | else | |
563 | clock.p2 = limit->p2.p2_fast; | |
564 | } | |
565 | ||
0206e353 | 566 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 567 | |
42158660 ZY |
568 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
569 | clock.m1++) { | |
570 | for (clock.m2 = limit->m2.min; | |
571 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
572 | for (clock.n = limit->n.min; |
573 | clock.n <= limit->n.max; clock.n++) { | |
574 | for (clock.p1 = limit->p1.min; | |
575 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
576 | int this_err; |
577 | ||
ac58c3f0 | 578 | pineview_clock(refclk, &clock); |
1b894b59 CW |
579 | if (!intel_PLL_is_valid(dev, limit, |
580 | &clock)) | |
79e53945 | 581 | continue; |
cec2f356 SP |
582 | if (match_clock && |
583 | clock.p != match_clock->p) | |
584 | continue; | |
79e53945 JB |
585 | |
586 | this_err = abs(clock.dot - target); | |
587 | if (this_err < err) { | |
588 | *best_clock = clock; | |
589 | err = this_err; | |
590 | } | |
591 | } | |
592 | } | |
593 | } | |
594 | } | |
595 | ||
596 | return (err != target); | |
597 | } | |
598 | ||
d4906093 | 599 | static bool |
ee9300bb DV |
600 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
601 | int target, int refclk, intel_clock_t *match_clock, | |
602 | intel_clock_t *best_clock) | |
d4906093 ML |
603 | { |
604 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
605 | intel_clock_t clock; |
606 | int max_n; | |
607 | bool found; | |
6ba770dc AJ |
608 | /* approximately equals target * 0.00585 */ |
609 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
610 | found = false; |
611 | ||
612 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 613 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
614 | clock.p2 = limit->p2.p2_fast; |
615 | else | |
616 | clock.p2 = limit->p2.p2_slow; | |
617 | } else { | |
618 | if (target < limit->p2.dot_limit) | |
619 | clock.p2 = limit->p2.p2_slow; | |
620 | else | |
621 | clock.p2 = limit->p2.p2_fast; | |
622 | } | |
623 | ||
624 | memset(best_clock, 0, sizeof(*best_clock)); | |
625 | max_n = limit->n.max; | |
f77f13e2 | 626 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 627 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 628 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
629 | for (clock.m1 = limit->m1.max; |
630 | clock.m1 >= limit->m1.min; clock.m1--) { | |
631 | for (clock.m2 = limit->m2.max; | |
632 | clock.m2 >= limit->m2.min; clock.m2--) { | |
633 | for (clock.p1 = limit->p1.max; | |
634 | clock.p1 >= limit->p1.min; clock.p1--) { | |
635 | int this_err; | |
636 | ||
ac58c3f0 | 637 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
638 | if (!intel_PLL_is_valid(dev, limit, |
639 | &clock)) | |
d4906093 | 640 | continue; |
1b894b59 CW |
641 | |
642 | this_err = abs(clock.dot - target); | |
d4906093 ML |
643 | if (this_err < err_most) { |
644 | *best_clock = clock; | |
645 | err_most = this_err; | |
646 | max_n = clock.n; | |
647 | found = true; | |
648 | } | |
649 | } | |
650 | } | |
651 | } | |
652 | } | |
2c07245f ZW |
653 | return found; |
654 | } | |
655 | ||
a0c4da24 | 656 | static bool |
ee9300bb DV |
657 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
658 | int target, int refclk, intel_clock_t *match_clock, | |
659 | intel_clock_t *best_clock) | |
a0c4da24 | 660 | { |
6b4bf1c4 | 661 | intel_clock_t clock; |
69e4f900 | 662 | unsigned int bestppm = 1000000; |
27e639bf VS |
663 | /* min update 19.2 MHz */ |
664 | int max_n = min(limit->n.max, refclk / 19200); | |
a0c4da24 | 665 | |
6b4bf1c4 VS |
666 | target *= 5; /* fast clock */ |
667 | ||
668 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
669 | |
670 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 671 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 672 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 673 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 674 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 675 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 676 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 677 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
678 | unsigned int ppm, diff; |
679 | ||
6b4bf1c4 VS |
680 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
681 | refclk * clock.m1); | |
682 | ||
683 | vlv_clock(refclk, &clock); | |
43b0ac53 | 684 | |
6b4bf1c4 VS |
685 | if (clock.vco < limit->vco.min || |
686 | clock.vco >= limit->vco.max) | |
43b0ac53 VS |
687 | continue; |
688 | ||
6b4bf1c4 VS |
689 | diff = abs(clock.dot - target); |
690 | ppm = div_u64(1000000ULL * diff, target); | |
691 | ||
692 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 693 | bestppm = 0; |
6b4bf1c4 | 694 | *best_clock = clock; |
43b0ac53 | 695 | } |
6b4bf1c4 | 696 | |
c686122c | 697 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 698 | bestppm = ppm; |
6b4bf1c4 | 699 | *best_clock = clock; |
a0c4da24 JB |
700 | } |
701 | } | |
702 | } | |
703 | } | |
704 | } | |
a0c4da24 JB |
705 | |
706 | return true; | |
707 | } | |
a4fc5ed6 | 708 | |
20ddf665 VS |
709 | bool intel_crtc_active(struct drm_crtc *crtc) |
710 | { | |
711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
712 | ||
713 | /* Be paranoid as we can arrive here with only partial | |
714 | * state retrieved from the hardware during setup. | |
715 | * | |
241bfc38 | 716 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
717 | * as Haswell has gained clock readout/fastboot support. |
718 | * | |
719 | * We can ditch the crtc->fb check as soon as we can | |
720 | * properly reconstruct framebuffers. | |
721 | */ | |
722 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 723 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
724 | } |
725 | ||
a5c961d1 PZ |
726 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
727 | enum pipe pipe) | |
728 | { | |
729 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
730 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
731 | ||
3b117c8f | 732 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
733 | } |
734 | ||
a928d536 PZ |
735 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
736 | { | |
737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
738 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
739 | ||
740 | frame = I915_READ(frame_reg); | |
741 | ||
742 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
743 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
744 | } | |
745 | ||
9d0498a2 JB |
746 | /** |
747 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
748 | * @dev: drm device | |
749 | * @pipe: pipe to wait for | |
750 | * | |
751 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
752 | * mode setting code. | |
753 | */ | |
754 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 755 | { |
9d0498a2 | 756 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 757 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 758 | |
a928d536 PZ |
759 | if (INTEL_INFO(dev)->gen >= 5) { |
760 | ironlake_wait_for_vblank(dev, pipe); | |
761 | return; | |
762 | } | |
763 | ||
300387c0 CW |
764 | /* Clear existing vblank status. Note this will clear any other |
765 | * sticky status fields as well. | |
766 | * | |
767 | * This races with i915_driver_irq_handler() with the result | |
768 | * that either function could miss a vblank event. Here it is not | |
769 | * fatal, as we will either wait upon the next vblank interrupt or | |
770 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
771 | * called during modeset at which time the GPU should be idle and | |
772 | * should *not* be performing page flips and thus not waiting on | |
773 | * vblanks... | |
774 | * Currently, the result of us stealing a vblank from the irq | |
775 | * handler is that a single frame will be skipped during swapbuffers. | |
776 | */ | |
777 | I915_WRITE(pipestat_reg, | |
778 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
779 | ||
9d0498a2 | 780 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
781 | if (wait_for(I915_READ(pipestat_reg) & |
782 | PIPE_VBLANK_INTERRUPT_STATUS, | |
783 | 50)) | |
9d0498a2 JB |
784 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
785 | } | |
786 | ||
ab7ad7f6 KP |
787 | /* |
788 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
789 | * @dev: drm device |
790 | * @pipe: pipe to wait for | |
791 | * | |
792 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
793 | * spinning on the vblank interrupt status bit, since we won't actually | |
794 | * see an interrupt when the pipe is disabled. | |
795 | * | |
ab7ad7f6 KP |
796 | * On Gen4 and above: |
797 | * wait for the pipe register state bit to turn off | |
798 | * | |
799 | * Otherwise: | |
800 | * wait for the display line value to settle (it usually | |
801 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 802 | * |
9d0498a2 | 803 | */ |
58e10eb9 | 804 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
805 | { |
806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
807 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
808 | pipe); | |
ab7ad7f6 KP |
809 | |
810 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 811 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
812 | |
813 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
814 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
815 | 100)) | |
284637d9 | 816 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 817 | } else { |
837ba00f | 818 | u32 last_line, line_mask; |
58e10eb9 | 819 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
820 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
821 | ||
837ba00f PZ |
822 | if (IS_GEN2(dev)) |
823 | line_mask = DSL_LINEMASK_GEN2; | |
824 | else | |
825 | line_mask = DSL_LINEMASK_GEN3; | |
826 | ||
ab7ad7f6 KP |
827 | /* Wait for the display line to settle */ |
828 | do { | |
837ba00f | 829 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 830 | mdelay(5); |
837ba00f | 831 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
832 | time_after(timeout, jiffies)); |
833 | if (time_after(jiffies, timeout)) | |
284637d9 | 834 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 835 | } |
79e53945 JB |
836 | } |
837 | ||
b0ea7d37 DL |
838 | /* |
839 | * ibx_digital_port_connected - is the specified port connected? | |
840 | * @dev_priv: i915 private structure | |
841 | * @port: the port to test | |
842 | * | |
843 | * Returns true if @port is connected, false otherwise. | |
844 | */ | |
845 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
846 | struct intel_digital_port *port) | |
847 | { | |
848 | u32 bit; | |
849 | ||
c36346e3 DL |
850 | if (HAS_PCH_IBX(dev_priv->dev)) { |
851 | switch(port->port) { | |
852 | case PORT_B: | |
853 | bit = SDE_PORTB_HOTPLUG; | |
854 | break; | |
855 | case PORT_C: | |
856 | bit = SDE_PORTC_HOTPLUG; | |
857 | break; | |
858 | case PORT_D: | |
859 | bit = SDE_PORTD_HOTPLUG; | |
860 | break; | |
861 | default: | |
862 | return true; | |
863 | } | |
864 | } else { | |
865 | switch(port->port) { | |
866 | case PORT_B: | |
867 | bit = SDE_PORTB_HOTPLUG_CPT; | |
868 | break; | |
869 | case PORT_C: | |
870 | bit = SDE_PORTC_HOTPLUG_CPT; | |
871 | break; | |
872 | case PORT_D: | |
873 | bit = SDE_PORTD_HOTPLUG_CPT; | |
874 | break; | |
875 | default: | |
876 | return true; | |
877 | } | |
b0ea7d37 DL |
878 | } |
879 | ||
880 | return I915_READ(SDEISR) & bit; | |
881 | } | |
882 | ||
b24e7179 JB |
883 | static const char *state_string(bool enabled) |
884 | { | |
885 | return enabled ? "on" : "off"; | |
886 | } | |
887 | ||
888 | /* Only for pre-ILK configs */ | |
55607e8a DV |
889 | void assert_pll(struct drm_i915_private *dev_priv, |
890 | enum pipe pipe, bool state) | |
b24e7179 JB |
891 | { |
892 | int reg; | |
893 | u32 val; | |
894 | bool cur_state; | |
895 | ||
896 | reg = DPLL(pipe); | |
897 | val = I915_READ(reg); | |
898 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
899 | WARN(cur_state != state, | |
900 | "PLL state assertion failure (expected %s, current %s)\n", | |
901 | state_string(state), state_string(cur_state)); | |
902 | } | |
b24e7179 | 903 | |
23538ef1 JN |
904 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
905 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
906 | { | |
907 | u32 val; | |
908 | bool cur_state; | |
909 | ||
910 | mutex_lock(&dev_priv->dpio_lock); | |
911 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
912 | mutex_unlock(&dev_priv->dpio_lock); | |
913 | ||
914 | cur_state = val & DSI_PLL_VCO_EN; | |
915 | WARN(cur_state != state, | |
916 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
917 | state_string(state), state_string(cur_state)); | |
918 | } | |
919 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
920 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
921 | ||
55607e8a | 922 | struct intel_shared_dpll * |
e2b78267 DV |
923 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
924 | { | |
925 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
926 | ||
a43f6e0f | 927 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
928 | return NULL; |
929 | ||
a43f6e0f | 930 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
931 | } |
932 | ||
040484af | 933 | /* For ILK+ */ |
55607e8a DV |
934 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
935 | struct intel_shared_dpll *pll, | |
936 | bool state) | |
040484af | 937 | { |
040484af | 938 | bool cur_state; |
5358901f | 939 | struct intel_dpll_hw_state hw_state; |
040484af | 940 | |
9d82aa17 ED |
941 | if (HAS_PCH_LPT(dev_priv->dev)) { |
942 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
943 | return; | |
944 | } | |
945 | ||
92b27b08 | 946 | if (WARN (!pll, |
46edb027 | 947 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 948 | return; |
ee7b9f93 | 949 | |
5358901f | 950 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 951 | WARN(cur_state != state, |
5358901f DV |
952 | "%s assertion failure (expected %s, current %s)\n", |
953 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 954 | } |
040484af JB |
955 | |
956 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
957 | enum pipe pipe, bool state) | |
958 | { | |
959 | int reg; | |
960 | u32 val; | |
961 | bool cur_state; | |
ad80a810 PZ |
962 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
963 | pipe); | |
040484af | 964 | |
affa9354 PZ |
965 | if (HAS_DDI(dev_priv->dev)) { |
966 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 967 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 968 | val = I915_READ(reg); |
ad80a810 | 969 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
970 | } else { |
971 | reg = FDI_TX_CTL(pipe); | |
972 | val = I915_READ(reg); | |
973 | cur_state = !!(val & FDI_TX_ENABLE); | |
974 | } | |
040484af JB |
975 | WARN(cur_state != state, |
976 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
977 | state_string(state), state_string(cur_state)); | |
978 | } | |
979 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
980 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
981 | ||
982 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
983 | enum pipe pipe, bool state) | |
984 | { | |
985 | int reg; | |
986 | u32 val; | |
987 | bool cur_state; | |
988 | ||
d63fa0dc PZ |
989 | reg = FDI_RX_CTL(pipe); |
990 | val = I915_READ(reg); | |
991 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
992 | WARN(cur_state != state, |
993 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
994 | state_string(state), state_string(cur_state)); | |
995 | } | |
996 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
997 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
998 | ||
999 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1000 | enum pipe pipe) | |
1001 | { | |
1002 | int reg; | |
1003 | u32 val; | |
1004 | ||
1005 | /* ILK FDI PLL is always enabled */ | |
1006 | if (dev_priv->info->gen == 5) | |
1007 | return; | |
1008 | ||
bf507ef7 | 1009 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1010 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1011 | return; |
1012 | ||
040484af JB |
1013 | reg = FDI_TX_CTL(pipe); |
1014 | val = I915_READ(reg); | |
1015 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1016 | } | |
1017 | ||
55607e8a DV |
1018 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1019 | enum pipe pipe, bool state) | |
040484af JB |
1020 | { |
1021 | int reg; | |
1022 | u32 val; | |
55607e8a | 1023 | bool cur_state; |
040484af JB |
1024 | |
1025 | reg = FDI_RX_CTL(pipe); | |
1026 | val = I915_READ(reg); | |
55607e8a DV |
1027 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1028 | WARN(cur_state != state, | |
1029 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1030 | state_string(state), state_string(cur_state)); | |
040484af JB |
1031 | } |
1032 | ||
ea0760cf JB |
1033 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1034 | enum pipe pipe) | |
1035 | { | |
1036 | int pp_reg, lvds_reg; | |
1037 | u32 val; | |
1038 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1039 | bool locked = true; |
ea0760cf JB |
1040 | |
1041 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1042 | pp_reg = PCH_PP_CONTROL; | |
1043 | lvds_reg = PCH_LVDS; | |
1044 | } else { | |
1045 | pp_reg = PP_CONTROL; | |
1046 | lvds_reg = LVDS; | |
1047 | } | |
1048 | ||
1049 | val = I915_READ(pp_reg); | |
1050 | if (!(val & PANEL_POWER_ON) || | |
1051 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1052 | locked = false; | |
1053 | ||
1054 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1055 | panel_pipe = PIPE_B; | |
1056 | ||
1057 | WARN(panel_pipe == pipe && locked, | |
1058 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1059 | pipe_name(pipe)); |
ea0760cf JB |
1060 | } |
1061 | ||
93ce0ba6 JN |
1062 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1063 | enum pipe pipe, bool state) | |
1064 | { | |
1065 | struct drm_device *dev = dev_priv->dev; | |
1066 | bool cur_state; | |
1067 | ||
1068 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1069 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1070 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1071 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1072 | else | |
1073 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1074 | ||
1075 | WARN(cur_state != state, | |
1076 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1077 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1078 | } | |
1079 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1080 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1081 | ||
b840d907 JB |
1082 | void assert_pipe(struct drm_i915_private *dev_priv, |
1083 | enum pipe pipe, bool state) | |
b24e7179 JB |
1084 | { |
1085 | int reg; | |
1086 | u32 val; | |
63d7bbe9 | 1087 | bool cur_state; |
702e7a56 PZ |
1088 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1089 | pipe); | |
b24e7179 | 1090 | |
8e636784 DV |
1091 | /* if we need the pipe A quirk it must be always on */ |
1092 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1093 | state = true; | |
1094 | ||
b97186f0 PZ |
1095 | if (!intel_display_power_enabled(dev_priv->dev, |
1096 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1097 | cur_state = false; |
1098 | } else { | |
1099 | reg = PIPECONF(cpu_transcoder); | |
1100 | val = I915_READ(reg); | |
1101 | cur_state = !!(val & PIPECONF_ENABLE); | |
1102 | } | |
1103 | ||
63d7bbe9 JB |
1104 | WARN(cur_state != state, |
1105 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1106 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1107 | } |
1108 | ||
931872fc CW |
1109 | static void assert_plane(struct drm_i915_private *dev_priv, |
1110 | enum plane plane, bool state) | |
b24e7179 JB |
1111 | { |
1112 | int reg; | |
1113 | u32 val; | |
931872fc | 1114 | bool cur_state; |
b24e7179 JB |
1115 | |
1116 | reg = DSPCNTR(plane); | |
1117 | val = I915_READ(reg); | |
931872fc CW |
1118 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1119 | WARN(cur_state != state, | |
1120 | "plane %c assertion failure (expected %s, current %s)\n", | |
1121 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1122 | } |
1123 | ||
931872fc CW |
1124 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1125 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1126 | ||
b24e7179 JB |
1127 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1128 | enum pipe pipe) | |
1129 | { | |
653e1026 | 1130 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1131 | int reg, i; |
1132 | u32 val; | |
1133 | int cur_pipe; | |
1134 | ||
653e1026 VS |
1135 | /* Primary planes are fixed to pipes on gen4+ */ |
1136 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1137 | reg = DSPCNTR(pipe); |
1138 | val = I915_READ(reg); | |
1139 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1140 | "plane %c assertion failure, should be disabled but not\n", | |
1141 | plane_name(pipe)); | |
19ec1358 | 1142 | return; |
28c05794 | 1143 | } |
19ec1358 | 1144 | |
b24e7179 | 1145 | /* Need to check both planes against the pipe */ |
08e2a7de | 1146 | for_each_pipe(i) { |
b24e7179 JB |
1147 | reg = DSPCNTR(i); |
1148 | val = I915_READ(reg); | |
1149 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1150 | DISPPLANE_SEL_PIPE_SHIFT; | |
1151 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1152 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1153 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1154 | } |
1155 | } | |
1156 | ||
19332d7a JB |
1157 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1158 | enum pipe pipe) | |
1159 | { | |
20674eef | 1160 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1161 | int reg, i; |
1162 | u32 val; | |
1163 | ||
20674eef VS |
1164 | if (IS_VALLEYVIEW(dev)) { |
1165 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1166 | reg = SPCNTR(pipe, i); | |
1167 | val = I915_READ(reg); | |
1168 | WARN((val & SP_ENABLE), | |
1169 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1170 | sprite_name(pipe, i), pipe_name(pipe)); | |
1171 | } | |
1172 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1173 | reg = SPRCTL(pipe); | |
19332d7a | 1174 | val = I915_READ(reg); |
20674eef | 1175 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1176 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1177 | plane_name(pipe), pipe_name(pipe)); |
1178 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1179 | reg = DVSCNTR(pipe); | |
19332d7a | 1180 | val = I915_READ(reg); |
20674eef | 1181 | WARN((val & DVS_ENABLE), |
06da8da2 | 1182 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1183 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1184 | } |
1185 | } | |
1186 | ||
92f2584a JB |
1187 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1188 | { | |
1189 | u32 val; | |
1190 | bool enabled; | |
1191 | ||
9d82aa17 ED |
1192 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1193 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1194 | return; | |
1195 | } | |
1196 | ||
92f2584a JB |
1197 | val = I915_READ(PCH_DREF_CONTROL); |
1198 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1199 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1200 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1201 | } | |
1202 | ||
ab9412ba DV |
1203 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1204 | enum pipe pipe) | |
92f2584a JB |
1205 | { |
1206 | int reg; | |
1207 | u32 val; | |
1208 | bool enabled; | |
1209 | ||
ab9412ba | 1210 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1211 | val = I915_READ(reg); |
1212 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1213 | WARN(enabled, |
1214 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1215 | pipe_name(pipe)); | |
92f2584a JB |
1216 | } |
1217 | ||
4e634389 KP |
1218 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1219 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1220 | { |
1221 | if ((val & DP_PORT_EN) == 0) | |
1222 | return false; | |
1223 | ||
1224 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1225 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1226 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1227 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1228 | return false; | |
1229 | } else { | |
1230 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1231 | return false; | |
1232 | } | |
1233 | return true; | |
1234 | } | |
1235 | ||
1519b995 KP |
1236 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1237 | enum pipe pipe, u32 val) | |
1238 | { | |
dc0fa718 | 1239 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1240 | return false; |
1241 | ||
1242 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1243 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1244 | return false; |
1245 | } else { | |
dc0fa718 | 1246 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1247 | return false; |
1248 | } | |
1249 | return true; | |
1250 | } | |
1251 | ||
1252 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1253 | enum pipe pipe, u32 val) | |
1254 | { | |
1255 | if ((val & LVDS_PORT_EN) == 0) | |
1256 | return false; | |
1257 | ||
1258 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1259 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1260 | return false; | |
1261 | } else { | |
1262 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1263 | return false; | |
1264 | } | |
1265 | return true; | |
1266 | } | |
1267 | ||
1268 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1269 | enum pipe pipe, u32 val) | |
1270 | { | |
1271 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1272 | return false; | |
1273 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1274 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1275 | return false; | |
1276 | } else { | |
1277 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1278 | return false; | |
1279 | } | |
1280 | return true; | |
1281 | } | |
1282 | ||
291906f1 | 1283 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1284 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1285 | { |
47a05eca | 1286 | u32 val = I915_READ(reg); |
4e634389 | 1287 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1288 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1289 | reg, pipe_name(pipe)); |
de9a35ab | 1290 | |
75c5da27 DV |
1291 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1292 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1293 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1294 | } |
1295 | ||
1296 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1297 | enum pipe pipe, int reg) | |
1298 | { | |
47a05eca | 1299 | u32 val = I915_READ(reg); |
b70ad586 | 1300 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1301 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1302 | reg, pipe_name(pipe)); |
de9a35ab | 1303 | |
dc0fa718 | 1304 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1305 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1306 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1307 | } |
1308 | ||
1309 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1310 | enum pipe pipe) | |
1311 | { | |
1312 | int reg; | |
1313 | u32 val; | |
291906f1 | 1314 | |
f0575e92 KP |
1315 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1316 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1317 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1318 | |
1319 | reg = PCH_ADPA; | |
1320 | val = I915_READ(reg); | |
b70ad586 | 1321 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1322 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1323 | pipe_name(pipe)); |
291906f1 JB |
1324 | |
1325 | reg = PCH_LVDS; | |
1326 | val = I915_READ(reg); | |
b70ad586 | 1327 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1328 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1329 | pipe_name(pipe)); |
291906f1 | 1330 | |
e2debe91 PZ |
1331 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1332 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1333 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1334 | } |
1335 | ||
40e9cf64 JB |
1336 | static void intel_init_dpio(struct drm_device *dev) |
1337 | { | |
1338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1339 | ||
1340 | if (!IS_VALLEYVIEW(dev)) | |
1341 | return; | |
1342 | ||
1343 | /* | |
1344 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1345 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1346 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1347 | * b. The other bits such as sfr settings / modesel may all be set | |
1348 | * to 0. | |
1349 | * | |
1350 | * This should only be done on init and resume from S3 with both | |
1351 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1352 | */ | |
1353 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1354 | } | |
1355 | ||
426115cf | 1356 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1357 | { |
426115cf DV |
1358 | struct drm_device *dev = crtc->base.dev; |
1359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1360 | int reg = DPLL(crtc->pipe); | |
1361 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1362 | |
426115cf | 1363 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1364 | |
1365 | /* No really, not for ILK+ */ | |
1366 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1367 | ||
1368 | /* PLL is protected by panel, make sure we can write it */ | |
1369 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1370 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1371 | |
426115cf DV |
1372 | I915_WRITE(reg, dpll); |
1373 | POSTING_READ(reg); | |
1374 | udelay(150); | |
1375 | ||
1376 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1377 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1378 | ||
1379 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1380 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1381 | |
1382 | /* We do this three times for luck */ | |
426115cf | 1383 | I915_WRITE(reg, dpll); |
87442f73 DV |
1384 | POSTING_READ(reg); |
1385 | udelay(150); /* wait for warmup */ | |
426115cf | 1386 | I915_WRITE(reg, dpll); |
87442f73 DV |
1387 | POSTING_READ(reg); |
1388 | udelay(150); /* wait for warmup */ | |
426115cf | 1389 | I915_WRITE(reg, dpll); |
87442f73 DV |
1390 | POSTING_READ(reg); |
1391 | udelay(150); /* wait for warmup */ | |
1392 | } | |
1393 | ||
66e3d5c0 | 1394 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1395 | { |
66e3d5c0 DV |
1396 | struct drm_device *dev = crtc->base.dev; |
1397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1398 | int reg = DPLL(crtc->pipe); | |
1399 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1400 | |
66e3d5c0 | 1401 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1402 | |
63d7bbe9 | 1403 | /* No really, not for ILK+ */ |
87442f73 | 1404 | BUG_ON(dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1405 | |
1406 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1407 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1408 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1409 | |
66e3d5c0 DV |
1410 | I915_WRITE(reg, dpll); |
1411 | ||
1412 | /* Wait for the clocks to stabilize. */ | |
1413 | POSTING_READ(reg); | |
1414 | udelay(150); | |
1415 | ||
1416 | if (INTEL_INFO(dev)->gen >= 4) { | |
1417 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1418 | crtc->config.dpll_hw_state.dpll_md); | |
1419 | } else { | |
1420 | /* The pixel multiplier can only be updated once the | |
1421 | * DPLL is enabled and the clocks are stable. | |
1422 | * | |
1423 | * So write it again. | |
1424 | */ | |
1425 | I915_WRITE(reg, dpll); | |
1426 | } | |
63d7bbe9 JB |
1427 | |
1428 | /* We do this three times for luck */ | |
66e3d5c0 | 1429 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1430 | POSTING_READ(reg); |
1431 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1432 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1433 | POSTING_READ(reg); |
1434 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1435 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1436 | POSTING_READ(reg); |
1437 | udelay(150); /* wait for warmup */ | |
1438 | } | |
1439 | ||
1440 | /** | |
50b44a44 | 1441 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1442 | * @dev_priv: i915 private structure |
1443 | * @pipe: pipe PLL to disable | |
1444 | * | |
1445 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1446 | * | |
1447 | * Note! This is for pre-ILK only. | |
1448 | */ | |
50b44a44 | 1449 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1450 | { |
63d7bbe9 JB |
1451 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1452 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1453 | return; | |
1454 | ||
1455 | /* Make sure the pipe isn't still relying on us */ | |
1456 | assert_pipe_disabled(dev_priv, pipe); | |
1457 | ||
50b44a44 DV |
1458 | I915_WRITE(DPLL(pipe), 0); |
1459 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1460 | } |
1461 | ||
f6071166 JB |
1462 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1463 | { | |
1464 | u32 val = 0; | |
1465 | ||
1466 | /* Make sure the pipe isn't still relying on us */ | |
1467 | assert_pipe_disabled(dev_priv, pipe); | |
1468 | ||
1469 | /* Leave integrated clock source enabled */ | |
1470 | if (pipe == PIPE_B) | |
1471 | val = DPLL_INTEGRATED_CRI_CLK_VLV; | |
1472 | I915_WRITE(DPLL(pipe), val); | |
1473 | POSTING_READ(DPLL(pipe)); | |
1474 | } | |
1475 | ||
89b667f8 JB |
1476 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1477 | { | |
1478 | u32 port_mask; | |
1479 | ||
1480 | if (!port) | |
1481 | port_mask = DPLL_PORTB_READY_MASK; | |
1482 | else | |
1483 | port_mask = DPLL_PORTC_READY_MASK; | |
1484 | ||
1485 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1486 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
1487 | 'B' + port, I915_READ(DPLL(0))); | |
1488 | } | |
1489 | ||
92f2584a | 1490 | /** |
e72f9fbf | 1491 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1492 | * @dev_priv: i915 private structure |
1493 | * @pipe: pipe PLL to enable | |
1494 | * | |
1495 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1496 | * drives the transcoder clock. | |
1497 | */ | |
e2b78267 | 1498 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1499 | { |
e2b78267 DV |
1500 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1501 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
92f2584a | 1502 | |
48da64a8 | 1503 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1504 | BUG_ON(dev_priv->info->gen < 5); |
87a875bb | 1505 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1506 | return; |
1507 | ||
1508 | if (WARN_ON(pll->refcount == 0)) | |
1509 | return; | |
ee7b9f93 | 1510 | |
46edb027 DV |
1511 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1512 | pll->name, pll->active, pll->on, | |
e2b78267 | 1513 | crtc->base.base.id); |
92f2584a | 1514 | |
cdbd2316 DV |
1515 | if (pll->active++) { |
1516 | WARN_ON(!pll->on); | |
e9d6944e | 1517 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1518 | return; |
1519 | } | |
f4a091c7 | 1520 | WARN_ON(pll->on); |
ee7b9f93 | 1521 | |
46edb027 | 1522 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1523 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1524 | pll->on = true; |
92f2584a JB |
1525 | } |
1526 | ||
e2b78267 | 1527 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1528 | { |
e2b78267 DV |
1529 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1530 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
4c609cb8 | 1531 | |
92f2584a JB |
1532 | /* PCH only available on ILK+ */ |
1533 | BUG_ON(dev_priv->info->gen < 5); | |
87a875bb | 1534 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1535 | return; |
92f2584a | 1536 | |
48da64a8 CW |
1537 | if (WARN_ON(pll->refcount == 0)) |
1538 | return; | |
7a419866 | 1539 | |
46edb027 DV |
1540 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1541 | pll->name, pll->active, pll->on, | |
e2b78267 | 1542 | crtc->base.base.id); |
7a419866 | 1543 | |
48da64a8 | 1544 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1545 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1546 | return; |
1547 | } | |
1548 | ||
e9d6944e | 1549 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1550 | WARN_ON(!pll->on); |
cdbd2316 | 1551 | if (--pll->active) |
7a419866 | 1552 | return; |
ee7b9f93 | 1553 | |
46edb027 | 1554 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1555 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1556 | pll->on = false; |
92f2584a JB |
1557 | } |
1558 | ||
b8a4f404 PZ |
1559 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1560 | enum pipe pipe) | |
040484af | 1561 | { |
23670b32 | 1562 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1563 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1564 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1565 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1566 | |
1567 | /* PCH only available on ILK+ */ | |
1568 | BUG_ON(dev_priv->info->gen < 5); | |
1569 | ||
1570 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1571 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1572 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1573 | |
1574 | /* FDI must be feeding us bits for PCH ports */ | |
1575 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1576 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1577 | ||
23670b32 DV |
1578 | if (HAS_PCH_CPT(dev)) { |
1579 | /* Workaround: Set the timing override bit before enabling the | |
1580 | * pch transcoder. */ | |
1581 | reg = TRANS_CHICKEN2(pipe); | |
1582 | val = I915_READ(reg); | |
1583 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1584 | I915_WRITE(reg, val); | |
59c859d6 | 1585 | } |
23670b32 | 1586 | |
ab9412ba | 1587 | reg = PCH_TRANSCONF(pipe); |
040484af | 1588 | val = I915_READ(reg); |
5f7f726d | 1589 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1590 | |
1591 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1592 | /* | |
1593 | * make the BPC in transcoder be consistent with | |
1594 | * that in pipeconf reg. | |
1595 | */ | |
dfd07d72 DV |
1596 | val &= ~PIPECONF_BPC_MASK; |
1597 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1598 | } |
5f7f726d PZ |
1599 | |
1600 | val &= ~TRANS_INTERLACE_MASK; | |
1601 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1602 | if (HAS_PCH_IBX(dev_priv->dev) && |
1603 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1604 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1605 | else | |
1606 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1607 | else |
1608 | val |= TRANS_PROGRESSIVE; | |
1609 | ||
040484af JB |
1610 | I915_WRITE(reg, val | TRANS_ENABLE); |
1611 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1612 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1613 | } |
1614 | ||
8fb033d7 | 1615 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1616 | enum transcoder cpu_transcoder) |
040484af | 1617 | { |
8fb033d7 | 1618 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1619 | |
1620 | /* PCH only available on ILK+ */ | |
1621 | BUG_ON(dev_priv->info->gen < 5); | |
1622 | ||
8fb033d7 | 1623 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1624 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1625 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1626 | |
223a6fdf PZ |
1627 | /* Workaround: set timing override bit. */ |
1628 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1629 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1630 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1631 | ||
25f3ef11 | 1632 | val = TRANS_ENABLE; |
937bb610 | 1633 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1634 | |
9a76b1c6 PZ |
1635 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1636 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1637 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1638 | else |
1639 | val |= TRANS_PROGRESSIVE; | |
1640 | ||
ab9412ba DV |
1641 | I915_WRITE(LPT_TRANSCONF, val); |
1642 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1643 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1644 | } |
1645 | ||
b8a4f404 PZ |
1646 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1647 | enum pipe pipe) | |
040484af | 1648 | { |
23670b32 DV |
1649 | struct drm_device *dev = dev_priv->dev; |
1650 | uint32_t reg, val; | |
040484af JB |
1651 | |
1652 | /* FDI relies on the transcoder */ | |
1653 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1654 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1655 | ||
291906f1 JB |
1656 | /* Ports must be off as well */ |
1657 | assert_pch_ports_disabled(dev_priv, pipe); | |
1658 | ||
ab9412ba | 1659 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1660 | val = I915_READ(reg); |
1661 | val &= ~TRANS_ENABLE; | |
1662 | I915_WRITE(reg, val); | |
1663 | /* wait for PCH transcoder off, transcoder state */ | |
1664 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1665 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1666 | |
1667 | if (!HAS_PCH_IBX(dev)) { | |
1668 | /* Workaround: Clear the timing override chicken bit again. */ | |
1669 | reg = TRANS_CHICKEN2(pipe); | |
1670 | val = I915_READ(reg); | |
1671 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1672 | I915_WRITE(reg, val); | |
1673 | } | |
040484af JB |
1674 | } |
1675 | ||
ab4d966c | 1676 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1677 | { |
8fb033d7 PZ |
1678 | u32 val; |
1679 | ||
ab9412ba | 1680 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1681 | val &= ~TRANS_ENABLE; |
ab9412ba | 1682 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1683 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1684 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1685 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1686 | |
1687 | /* Workaround: clear timing override bit. */ | |
1688 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1689 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1690 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1691 | } |
1692 | ||
b24e7179 | 1693 | /** |
309cfea8 | 1694 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1695 | * @dev_priv: i915 private structure |
1696 | * @pipe: pipe to enable | |
040484af | 1697 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1698 | * |
1699 | * Enable @pipe, making sure that various hardware specific requirements | |
1700 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1701 | * | |
1702 | * @pipe should be %PIPE_A or %PIPE_B. | |
1703 | * | |
1704 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1705 | * returning. | |
1706 | */ | |
040484af | 1707 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
23538ef1 | 1708 | bool pch_port, bool dsi) |
b24e7179 | 1709 | { |
702e7a56 PZ |
1710 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1711 | pipe); | |
1a240d4d | 1712 | enum pipe pch_transcoder; |
b24e7179 JB |
1713 | int reg; |
1714 | u32 val; | |
1715 | ||
58c6eaa2 | 1716 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1717 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1718 | assert_sprites_disabled(dev_priv, pipe); |
1719 | ||
681e5811 | 1720 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1721 | pch_transcoder = TRANSCODER_A; |
1722 | else | |
1723 | pch_transcoder = pipe; | |
1724 | ||
b24e7179 JB |
1725 | /* |
1726 | * A pipe without a PLL won't actually be able to drive bits from | |
1727 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1728 | * need the check. | |
1729 | */ | |
1730 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1731 | if (dsi) |
1732 | assert_dsi_pll_enabled(dev_priv); | |
1733 | else | |
1734 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1735 | else { |
1736 | if (pch_port) { | |
1737 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1738 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1739 | assert_fdi_tx_pll_enabled(dev_priv, |
1740 | (enum pipe) cpu_transcoder); | |
040484af JB |
1741 | } |
1742 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1743 | } | |
b24e7179 | 1744 | |
702e7a56 | 1745 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1746 | val = I915_READ(reg); |
00d70b15 CW |
1747 | if (val & PIPECONF_ENABLE) |
1748 | return; | |
1749 | ||
1750 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1751 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1752 | } | |
1753 | ||
1754 | /** | |
309cfea8 | 1755 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1756 | * @dev_priv: i915 private structure |
1757 | * @pipe: pipe to disable | |
1758 | * | |
1759 | * Disable @pipe, making sure that various hardware specific requirements | |
1760 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1761 | * | |
1762 | * @pipe should be %PIPE_A or %PIPE_B. | |
1763 | * | |
1764 | * Will wait until the pipe has shut down before returning. | |
1765 | */ | |
1766 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1767 | enum pipe pipe) | |
1768 | { | |
702e7a56 PZ |
1769 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1770 | pipe); | |
b24e7179 JB |
1771 | int reg; |
1772 | u32 val; | |
1773 | ||
1774 | /* | |
1775 | * Make sure planes won't keep trying to pump pixels to us, | |
1776 | * or we might hang the display. | |
1777 | */ | |
1778 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1779 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1780 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1781 | |
1782 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1783 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1784 | return; | |
1785 | ||
702e7a56 | 1786 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1787 | val = I915_READ(reg); |
00d70b15 CW |
1788 | if ((val & PIPECONF_ENABLE) == 0) |
1789 | return; | |
1790 | ||
1791 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1792 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1793 | } | |
1794 | ||
d74362c9 KP |
1795 | /* |
1796 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1797 | * trigger in order to latch. The display address reg provides this. | |
1798 | */ | |
6f1d69b0 | 1799 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1800 | enum plane plane) |
1801 | { | |
14f86147 DL |
1802 | if (dev_priv->info->gen >= 4) |
1803 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1804 | else | |
1805 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1806 | } |
1807 | ||
b24e7179 JB |
1808 | /** |
1809 | * intel_enable_plane - enable a display plane on a given pipe | |
1810 | * @dev_priv: i915 private structure | |
1811 | * @plane: plane to enable | |
1812 | * @pipe: pipe being fed | |
1813 | * | |
1814 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1815 | */ | |
1816 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1817 | enum plane plane, enum pipe pipe) | |
1818 | { | |
1819 | int reg; | |
1820 | u32 val; | |
1821 | ||
1822 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1823 | assert_pipe_enabled(dev_priv, pipe); | |
1824 | ||
1825 | reg = DSPCNTR(plane); | |
1826 | val = I915_READ(reg); | |
00d70b15 CW |
1827 | if (val & DISPLAY_PLANE_ENABLE) |
1828 | return; | |
1829 | ||
1830 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1831 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1832 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1833 | } | |
1834 | ||
b24e7179 JB |
1835 | /** |
1836 | * intel_disable_plane - disable a display plane | |
1837 | * @dev_priv: i915 private structure | |
1838 | * @plane: plane to disable | |
1839 | * @pipe: pipe consuming the data | |
1840 | * | |
1841 | * Disable @plane; should be an independent operation. | |
1842 | */ | |
1843 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1844 | enum plane plane, enum pipe pipe) | |
1845 | { | |
1846 | int reg; | |
1847 | u32 val; | |
1848 | ||
1849 | reg = DSPCNTR(plane); | |
1850 | val = I915_READ(reg); | |
00d70b15 CW |
1851 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1852 | return; | |
1853 | ||
1854 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1855 | intel_flush_display_plane(dev_priv, plane); |
1856 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1857 | } | |
1858 | ||
693db184 CW |
1859 | static bool need_vtd_wa(struct drm_device *dev) |
1860 | { | |
1861 | #ifdef CONFIG_INTEL_IOMMU | |
1862 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1863 | return true; | |
1864 | #endif | |
1865 | return false; | |
1866 | } | |
1867 | ||
127bd2ac | 1868 | int |
48b956c5 | 1869 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1870 | struct drm_i915_gem_object *obj, |
919926ae | 1871 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1872 | { |
ce453d81 | 1873 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1874 | u32 alignment; |
1875 | int ret; | |
1876 | ||
05394f39 | 1877 | switch (obj->tiling_mode) { |
6b95a207 | 1878 | case I915_TILING_NONE: |
534843da CW |
1879 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1880 | alignment = 128 * 1024; | |
a6c45cf0 | 1881 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1882 | alignment = 4 * 1024; |
1883 | else | |
1884 | alignment = 64 * 1024; | |
6b95a207 KH |
1885 | break; |
1886 | case I915_TILING_X: | |
1887 | /* pin() will align the object as required by fence */ | |
1888 | alignment = 0; | |
1889 | break; | |
1890 | case I915_TILING_Y: | |
8bb6e959 DV |
1891 | /* Despite that we check this in framebuffer_init userspace can |
1892 | * screw us over and change the tiling after the fact. Only | |
1893 | * pinned buffers can't change their tiling. */ | |
1894 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); | |
6b95a207 KH |
1895 | return -EINVAL; |
1896 | default: | |
1897 | BUG(); | |
1898 | } | |
1899 | ||
693db184 CW |
1900 | /* Note that the w/a also requires 64 PTE of padding following the |
1901 | * bo. We currently fill all unused PTE with the shadow page and so | |
1902 | * we should always have valid PTE following the scanout preventing | |
1903 | * the VT-d warning. | |
1904 | */ | |
1905 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1906 | alignment = 256 * 1024; | |
1907 | ||
ce453d81 | 1908 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1909 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1910 | if (ret) |
ce453d81 | 1911 | goto err_interruptible; |
6b95a207 KH |
1912 | |
1913 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1914 | * fence, whereas 965+ only requires a fence if using | |
1915 | * framebuffer compression. For simplicity, we always install | |
1916 | * a fence as the cost is not that onerous. | |
1917 | */ | |
06d98131 | 1918 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1919 | if (ret) |
1920 | goto err_unpin; | |
1690e1eb | 1921 | |
9a5a53b3 | 1922 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1923 | |
ce453d81 | 1924 | dev_priv->mm.interruptible = true; |
6b95a207 | 1925 | return 0; |
48b956c5 CW |
1926 | |
1927 | err_unpin: | |
cc98b413 | 1928 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
1929 | err_interruptible: |
1930 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1931 | return ret; |
6b95a207 KH |
1932 | } |
1933 | ||
1690e1eb CW |
1934 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1935 | { | |
1936 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 1937 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
1938 | } |
1939 | ||
c2c75131 DV |
1940 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1941 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
1942 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1943 | unsigned int tiling_mode, | |
1944 | unsigned int cpp, | |
1945 | unsigned int pitch) | |
c2c75131 | 1946 | { |
bc752862 CW |
1947 | if (tiling_mode != I915_TILING_NONE) { |
1948 | unsigned int tile_rows, tiles; | |
c2c75131 | 1949 | |
bc752862 CW |
1950 | tile_rows = *y / 8; |
1951 | *y %= 8; | |
c2c75131 | 1952 | |
bc752862 CW |
1953 | tiles = *x / (512/cpp); |
1954 | *x %= 512/cpp; | |
1955 | ||
1956 | return tile_rows * pitch * 8 + tiles * 4096; | |
1957 | } else { | |
1958 | unsigned int offset; | |
1959 | ||
1960 | offset = *y * pitch + *x * cpp; | |
1961 | *y = 0; | |
1962 | *x = (offset & 4095) / cpp; | |
1963 | return offset & -4096; | |
1964 | } | |
c2c75131 DV |
1965 | } |
1966 | ||
17638cd6 JB |
1967 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1968 | int x, int y) | |
81255565 JB |
1969 | { |
1970 | struct drm_device *dev = crtc->dev; | |
1971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1973 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1974 | struct drm_i915_gem_object *obj; |
81255565 | 1975 | int plane = intel_crtc->plane; |
e506a0c6 | 1976 | unsigned long linear_offset; |
81255565 | 1977 | u32 dspcntr; |
5eddb70b | 1978 | u32 reg; |
81255565 JB |
1979 | |
1980 | switch (plane) { | |
1981 | case 0: | |
1982 | case 1: | |
1983 | break; | |
1984 | default: | |
84f44ce7 | 1985 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
1986 | return -EINVAL; |
1987 | } | |
1988 | ||
1989 | intel_fb = to_intel_framebuffer(fb); | |
1990 | obj = intel_fb->obj; | |
81255565 | 1991 | |
5eddb70b CW |
1992 | reg = DSPCNTR(plane); |
1993 | dspcntr = I915_READ(reg); | |
81255565 JB |
1994 | /* Mask out pixel format bits in case we change it */ |
1995 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
1996 | switch (fb->pixel_format) { |
1997 | case DRM_FORMAT_C8: | |
81255565 JB |
1998 | dspcntr |= DISPPLANE_8BPP; |
1999 | break; | |
57779d06 VS |
2000 | case DRM_FORMAT_XRGB1555: |
2001 | case DRM_FORMAT_ARGB1555: | |
2002 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2003 | break; |
57779d06 VS |
2004 | case DRM_FORMAT_RGB565: |
2005 | dspcntr |= DISPPLANE_BGRX565; | |
2006 | break; | |
2007 | case DRM_FORMAT_XRGB8888: | |
2008 | case DRM_FORMAT_ARGB8888: | |
2009 | dspcntr |= DISPPLANE_BGRX888; | |
2010 | break; | |
2011 | case DRM_FORMAT_XBGR8888: | |
2012 | case DRM_FORMAT_ABGR8888: | |
2013 | dspcntr |= DISPPLANE_RGBX888; | |
2014 | break; | |
2015 | case DRM_FORMAT_XRGB2101010: | |
2016 | case DRM_FORMAT_ARGB2101010: | |
2017 | dspcntr |= DISPPLANE_BGRX101010; | |
2018 | break; | |
2019 | case DRM_FORMAT_XBGR2101010: | |
2020 | case DRM_FORMAT_ABGR2101010: | |
2021 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2022 | break; |
2023 | default: | |
baba133a | 2024 | BUG(); |
81255565 | 2025 | } |
57779d06 | 2026 | |
a6c45cf0 | 2027 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2028 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2029 | dspcntr |= DISPPLANE_TILED; |
2030 | else | |
2031 | dspcntr &= ~DISPPLANE_TILED; | |
2032 | } | |
2033 | ||
de1aa629 VS |
2034 | if (IS_G4X(dev)) |
2035 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2036 | ||
5eddb70b | 2037 | I915_WRITE(reg, dspcntr); |
81255565 | 2038 | |
e506a0c6 | 2039 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2040 | |
c2c75131 DV |
2041 | if (INTEL_INFO(dev)->gen >= 4) { |
2042 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2043 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2044 | fb->bits_per_pixel / 8, | |
2045 | fb->pitches[0]); | |
c2c75131 DV |
2046 | linear_offset -= intel_crtc->dspaddr_offset; |
2047 | } else { | |
e506a0c6 | 2048 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2049 | } |
e506a0c6 | 2050 | |
f343c5f6 BW |
2051 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2052 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2053 | fb->pitches[0]); | |
01f2c773 | 2054 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2055 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 | 2056 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2057 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
5eddb70b | 2058 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2059 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2060 | } else |
f343c5f6 | 2061 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2062 | POSTING_READ(reg); |
81255565 | 2063 | |
17638cd6 JB |
2064 | return 0; |
2065 | } | |
2066 | ||
2067 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2068 | struct drm_framebuffer *fb, int x, int y) | |
2069 | { | |
2070 | struct drm_device *dev = crtc->dev; | |
2071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2073 | struct intel_framebuffer *intel_fb; | |
2074 | struct drm_i915_gem_object *obj; | |
2075 | int plane = intel_crtc->plane; | |
e506a0c6 | 2076 | unsigned long linear_offset; |
17638cd6 JB |
2077 | u32 dspcntr; |
2078 | u32 reg; | |
2079 | ||
2080 | switch (plane) { | |
2081 | case 0: | |
2082 | case 1: | |
27f8227b | 2083 | case 2: |
17638cd6 JB |
2084 | break; |
2085 | default: | |
84f44ce7 | 2086 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2087 | return -EINVAL; |
2088 | } | |
2089 | ||
2090 | intel_fb = to_intel_framebuffer(fb); | |
2091 | obj = intel_fb->obj; | |
2092 | ||
2093 | reg = DSPCNTR(plane); | |
2094 | dspcntr = I915_READ(reg); | |
2095 | /* Mask out pixel format bits in case we change it */ | |
2096 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2097 | switch (fb->pixel_format) { |
2098 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2099 | dspcntr |= DISPPLANE_8BPP; |
2100 | break; | |
57779d06 VS |
2101 | case DRM_FORMAT_RGB565: |
2102 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2103 | break; |
57779d06 VS |
2104 | case DRM_FORMAT_XRGB8888: |
2105 | case DRM_FORMAT_ARGB8888: | |
2106 | dspcntr |= DISPPLANE_BGRX888; | |
2107 | break; | |
2108 | case DRM_FORMAT_XBGR8888: | |
2109 | case DRM_FORMAT_ABGR8888: | |
2110 | dspcntr |= DISPPLANE_RGBX888; | |
2111 | break; | |
2112 | case DRM_FORMAT_XRGB2101010: | |
2113 | case DRM_FORMAT_ARGB2101010: | |
2114 | dspcntr |= DISPPLANE_BGRX101010; | |
2115 | break; | |
2116 | case DRM_FORMAT_XBGR2101010: | |
2117 | case DRM_FORMAT_ABGR2101010: | |
2118 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2119 | break; |
2120 | default: | |
baba133a | 2121 | BUG(); |
17638cd6 JB |
2122 | } |
2123 | ||
2124 | if (obj->tiling_mode != I915_TILING_NONE) | |
2125 | dspcntr |= DISPPLANE_TILED; | |
2126 | else | |
2127 | dspcntr &= ~DISPPLANE_TILED; | |
2128 | ||
1f5d76db PZ |
2129 | if (IS_HASWELL(dev)) |
2130 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; | |
2131 | else | |
2132 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2133 | |
2134 | I915_WRITE(reg, dspcntr); | |
2135 | ||
e506a0c6 | 2136 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2137 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2138 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2139 | fb->bits_per_pixel / 8, | |
2140 | fb->pitches[0]); | |
c2c75131 | 2141 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2142 | |
f343c5f6 BW |
2143 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2144 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2145 | fb->pitches[0]); | |
01f2c773 | 2146 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 | 2147 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2148 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
bc1c91eb DL |
2149 | if (IS_HASWELL(dev)) { |
2150 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2151 | } else { | |
2152 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2153 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2154 | } | |
17638cd6 JB |
2155 | POSTING_READ(reg); |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
2160 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2161 | static int | |
2162 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2163 | int x, int y, enum mode_set_atomic state) | |
2164 | { | |
2165 | struct drm_device *dev = crtc->dev; | |
2166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2167 | |
6b8e6ed0 CW |
2168 | if (dev_priv->display.disable_fbc) |
2169 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2170 | intel_increase_pllclock(crtc); |
81255565 | 2171 | |
6b8e6ed0 | 2172 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2173 | } |
2174 | ||
96a02917 VS |
2175 | void intel_display_handle_reset(struct drm_device *dev) |
2176 | { | |
2177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2178 | struct drm_crtc *crtc; | |
2179 | ||
2180 | /* | |
2181 | * Flips in the rings have been nuked by the reset, | |
2182 | * so complete all pending flips so that user space | |
2183 | * will get its events and not get stuck. | |
2184 | * | |
2185 | * Also update the base address of all primary | |
2186 | * planes to the the last fb to make sure we're | |
2187 | * showing the correct fb after a reset. | |
2188 | * | |
2189 | * Need to make two loops over the crtcs so that we | |
2190 | * don't try to grab a crtc mutex before the | |
2191 | * pending_flip_queue really got woken up. | |
2192 | */ | |
2193 | ||
2194 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2196 | enum plane plane = intel_crtc->plane; | |
2197 | ||
2198 | intel_prepare_page_flip(dev, plane); | |
2199 | intel_finish_page_flip_plane(dev, plane); | |
2200 | } | |
2201 | ||
2202 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2204 | ||
2205 | mutex_lock(&crtc->mutex); | |
2206 | if (intel_crtc->active) | |
2207 | dev_priv->display.update_plane(crtc, crtc->fb, | |
2208 | crtc->x, crtc->y); | |
2209 | mutex_unlock(&crtc->mutex); | |
2210 | } | |
2211 | } | |
2212 | ||
14667a4b CW |
2213 | static int |
2214 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2215 | { | |
2216 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2217 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2218 | bool was_interruptible = dev_priv->mm.interruptible; | |
2219 | int ret; | |
2220 | ||
14667a4b CW |
2221 | /* Big Hammer, we also need to ensure that any pending |
2222 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2223 | * current scanout is retired before unpinning the old | |
2224 | * framebuffer. | |
2225 | * | |
2226 | * This should only fail upon a hung GPU, in which case we | |
2227 | * can safely continue. | |
2228 | */ | |
2229 | dev_priv->mm.interruptible = false; | |
2230 | ret = i915_gem_object_finish_gpu(obj); | |
2231 | dev_priv->mm.interruptible = was_interruptible; | |
2232 | ||
2233 | return ret; | |
2234 | } | |
2235 | ||
198598d0 VS |
2236 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2237 | { | |
2238 | struct drm_device *dev = crtc->dev; | |
2239 | struct drm_i915_master_private *master_priv; | |
2240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2241 | ||
2242 | if (!dev->primary->master) | |
2243 | return; | |
2244 | ||
2245 | master_priv = dev->primary->master->driver_priv; | |
2246 | if (!master_priv->sarea_priv) | |
2247 | return; | |
2248 | ||
2249 | switch (intel_crtc->pipe) { | |
2250 | case 0: | |
2251 | master_priv->sarea_priv->pipeA_x = x; | |
2252 | master_priv->sarea_priv->pipeA_y = y; | |
2253 | break; | |
2254 | case 1: | |
2255 | master_priv->sarea_priv->pipeB_x = x; | |
2256 | master_priv->sarea_priv->pipeB_y = y; | |
2257 | break; | |
2258 | default: | |
2259 | break; | |
2260 | } | |
2261 | } | |
2262 | ||
5c3b82e2 | 2263 | static int |
3c4fdcfb | 2264 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2265 | struct drm_framebuffer *fb) |
79e53945 JB |
2266 | { |
2267 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2268 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2270 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2271 | int ret; |
79e53945 JB |
2272 | |
2273 | /* no fb bound */ | |
94352cf9 | 2274 | if (!fb) { |
a5071c2f | 2275 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2276 | return 0; |
2277 | } | |
2278 | ||
7eb552ae | 2279 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2280 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2281 | plane_name(intel_crtc->plane), | |
2282 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2283 | return -EINVAL; |
79e53945 JB |
2284 | } |
2285 | ||
5c3b82e2 | 2286 | mutex_lock(&dev->struct_mutex); |
265db958 | 2287 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2288 | to_intel_framebuffer(fb)->obj, |
919926ae | 2289 | NULL); |
5c3b82e2 CW |
2290 | if (ret != 0) { |
2291 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2292 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2293 | return ret; |
2294 | } | |
79e53945 | 2295 | |
bb2043de DL |
2296 | /* |
2297 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2298 | * that in compute_mode_changes we check the native mode (not the pfit | |
2299 | * mode) to see if we can flip rather than do a full mode set. In the | |
2300 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2301 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2302 | * sized surface. | |
2303 | * | |
2304 | * To fix this properly, we need to hoist the checks up into | |
2305 | * compute_mode_changes (or above), check the actual pfit state and | |
2306 | * whether the platform allows pfit disable with pipe active, and only | |
2307 | * then update the pipesrc and pfit state, even on the flip path. | |
2308 | */ | |
4d6a3e63 | 2309 | if (i915_fastboot) { |
d7bf63f2 DL |
2310 | const struct drm_display_mode *adjusted_mode = |
2311 | &intel_crtc->config.adjusted_mode; | |
2312 | ||
4d6a3e63 | 2313 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2314 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2315 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2316 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2317 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2318 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2319 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2320 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2321 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2322 | } | |
2323 | } | |
2324 | ||
94352cf9 | 2325 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2326 | if (ret) { |
94352cf9 | 2327 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2328 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2329 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2330 | return ret; |
79e53945 | 2331 | } |
3c4fdcfb | 2332 | |
94352cf9 DV |
2333 | old_fb = crtc->fb; |
2334 | crtc->fb = fb; | |
6c4c86f5 DV |
2335 | crtc->x = x; |
2336 | crtc->y = y; | |
94352cf9 | 2337 | |
b7f1de28 | 2338 | if (old_fb) { |
d7697eea DV |
2339 | if (intel_crtc->active && old_fb != fb) |
2340 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2341 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2342 | } |
652c393a | 2343 | |
6b8e6ed0 | 2344 | intel_update_fbc(dev); |
4906557e | 2345 | intel_edp_psr_update(dev); |
5c3b82e2 | 2346 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2347 | |
198598d0 | 2348 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2349 | |
2350 | return 0; | |
79e53945 JB |
2351 | } |
2352 | ||
5e84e1a4 ZW |
2353 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2354 | { | |
2355 | struct drm_device *dev = crtc->dev; | |
2356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2357 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2358 | int pipe = intel_crtc->pipe; | |
2359 | u32 reg, temp; | |
2360 | ||
2361 | /* enable normal train */ | |
2362 | reg = FDI_TX_CTL(pipe); | |
2363 | temp = I915_READ(reg); | |
61e499bf | 2364 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2365 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2366 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2367 | } else { |
2368 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2369 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2370 | } |
5e84e1a4 ZW |
2371 | I915_WRITE(reg, temp); |
2372 | ||
2373 | reg = FDI_RX_CTL(pipe); | |
2374 | temp = I915_READ(reg); | |
2375 | if (HAS_PCH_CPT(dev)) { | |
2376 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2377 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2378 | } else { | |
2379 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2380 | temp |= FDI_LINK_TRAIN_NONE; | |
2381 | } | |
2382 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2383 | ||
2384 | /* wait one idle pattern time */ | |
2385 | POSTING_READ(reg); | |
2386 | udelay(1000); | |
357555c0 JB |
2387 | |
2388 | /* IVB wants error correction enabled */ | |
2389 | if (IS_IVYBRIDGE(dev)) | |
2390 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2391 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2392 | } |
2393 | ||
1e833f40 DV |
2394 | static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) |
2395 | { | |
2396 | return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder; | |
2397 | } | |
2398 | ||
01a415fd DV |
2399 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2400 | { | |
2401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2402 | struct intel_crtc *pipe_B_crtc = | |
2403 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2404 | struct intel_crtc *pipe_C_crtc = | |
2405 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2406 | uint32_t temp; | |
2407 | ||
1e833f40 DV |
2408 | /* |
2409 | * When everything is off disable fdi C so that we could enable fdi B | |
2410 | * with all lanes. Note that we don't care about enabled pipes without | |
2411 | * an enabled pch encoder. | |
2412 | */ | |
2413 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2414 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2415 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2416 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2417 | ||
2418 | temp = I915_READ(SOUTH_CHICKEN1); | |
2419 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2420 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2421 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2422 | } | |
2423 | } | |
2424 | ||
8db9d77b ZW |
2425 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2426 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2427 | { | |
2428 | struct drm_device *dev = crtc->dev; | |
2429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2430 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2431 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2432 | int plane = intel_crtc->plane; |
5eddb70b | 2433 | u32 reg, temp, tries; |
8db9d77b | 2434 | |
0fc932b8 JB |
2435 | /* FDI needs bits from pipe & plane first */ |
2436 | assert_pipe_enabled(dev_priv, pipe); | |
2437 | assert_plane_enabled(dev_priv, plane); | |
2438 | ||
e1a44743 AJ |
2439 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2440 | for train result */ | |
5eddb70b CW |
2441 | reg = FDI_RX_IMR(pipe); |
2442 | temp = I915_READ(reg); | |
e1a44743 AJ |
2443 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2444 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2445 | I915_WRITE(reg, temp); |
2446 | I915_READ(reg); | |
e1a44743 AJ |
2447 | udelay(150); |
2448 | ||
8db9d77b | 2449 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2450 | reg = FDI_TX_CTL(pipe); |
2451 | temp = I915_READ(reg); | |
627eb5a3 DV |
2452 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2453 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2454 | temp &= ~FDI_LINK_TRAIN_NONE; |
2455 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2456 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2457 | |
5eddb70b CW |
2458 | reg = FDI_RX_CTL(pipe); |
2459 | temp = I915_READ(reg); | |
8db9d77b ZW |
2460 | temp &= ~FDI_LINK_TRAIN_NONE; |
2461 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2462 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2463 | ||
2464 | POSTING_READ(reg); | |
8db9d77b ZW |
2465 | udelay(150); |
2466 | ||
5b2adf89 | 2467 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2468 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2469 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2470 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2471 | |
5eddb70b | 2472 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2473 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2474 | temp = I915_READ(reg); |
8db9d77b ZW |
2475 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2476 | ||
2477 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2478 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2479 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2480 | break; |
2481 | } | |
8db9d77b | 2482 | } |
e1a44743 | 2483 | if (tries == 5) |
5eddb70b | 2484 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2485 | |
2486 | /* Train 2 */ | |
5eddb70b CW |
2487 | reg = FDI_TX_CTL(pipe); |
2488 | temp = I915_READ(reg); | |
8db9d77b ZW |
2489 | temp &= ~FDI_LINK_TRAIN_NONE; |
2490 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2491 | I915_WRITE(reg, temp); |
8db9d77b | 2492 | |
5eddb70b CW |
2493 | reg = FDI_RX_CTL(pipe); |
2494 | temp = I915_READ(reg); | |
8db9d77b ZW |
2495 | temp &= ~FDI_LINK_TRAIN_NONE; |
2496 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2497 | I915_WRITE(reg, temp); |
8db9d77b | 2498 | |
5eddb70b CW |
2499 | POSTING_READ(reg); |
2500 | udelay(150); | |
8db9d77b | 2501 | |
5eddb70b | 2502 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2503 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2504 | temp = I915_READ(reg); |
8db9d77b ZW |
2505 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2506 | ||
2507 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2508 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2509 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2510 | break; | |
2511 | } | |
8db9d77b | 2512 | } |
e1a44743 | 2513 | if (tries == 5) |
5eddb70b | 2514 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2515 | |
2516 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2517 | |
8db9d77b ZW |
2518 | } |
2519 | ||
0206e353 | 2520 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2521 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2522 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2523 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2524 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2525 | }; | |
2526 | ||
2527 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2528 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2529 | { | |
2530 | struct drm_device *dev = crtc->dev; | |
2531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2533 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2534 | u32 reg, temp, i, retry; |
8db9d77b | 2535 | |
e1a44743 AJ |
2536 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2537 | for train result */ | |
5eddb70b CW |
2538 | reg = FDI_RX_IMR(pipe); |
2539 | temp = I915_READ(reg); | |
e1a44743 AJ |
2540 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2541 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2542 | I915_WRITE(reg, temp); |
2543 | ||
2544 | POSTING_READ(reg); | |
e1a44743 AJ |
2545 | udelay(150); |
2546 | ||
8db9d77b | 2547 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2548 | reg = FDI_TX_CTL(pipe); |
2549 | temp = I915_READ(reg); | |
627eb5a3 DV |
2550 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2551 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2552 | temp &= ~FDI_LINK_TRAIN_NONE; |
2553 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2554 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2555 | /* SNB-B */ | |
2556 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2557 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2558 | |
d74cf324 DV |
2559 | I915_WRITE(FDI_RX_MISC(pipe), |
2560 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2561 | ||
5eddb70b CW |
2562 | reg = FDI_RX_CTL(pipe); |
2563 | temp = I915_READ(reg); | |
8db9d77b ZW |
2564 | if (HAS_PCH_CPT(dev)) { |
2565 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2566 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2567 | } else { | |
2568 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2569 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2570 | } | |
5eddb70b CW |
2571 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2572 | ||
2573 | POSTING_READ(reg); | |
8db9d77b ZW |
2574 | udelay(150); |
2575 | ||
0206e353 | 2576 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2577 | reg = FDI_TX_CTL(pipe); |
2578 | temp = I915_READ(reg); | |
8db9d77b ZW |
2579 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2580 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2581 | I915_WRITE(reg, temp); |
2582 | ||
2583 | POSTING_READ(reg); | |
8db9d77b ZW |
2584 | udelay(500); |
2585 | ||
fa37d39e SP |
2586 | for (retry = 0; retry < 5; retry++) { |
2587 | reg = FDI_RX_IIR(pipe); | |
2588 | temp = I915_READ(reg); | |
2589 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2590 | if (temp & FDI_RX_BIT_LOCK) { | |
2591 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2592 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2593 | break; | |
2594 | } | |
2595 | udelay(50); | |
8db9d77b | 2596 | } |
fa37d39e SP |
2597 | if (retry < 5) |
2598 | break; | |
8db9d77b ZW |
2599 | } |
2600 | if (i == 4) | |
5eddb70b | 2601 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2602 | |
2603 | /* Train 2 */ | |
5eddb70b CW |
2604 | reg = FDI_TX_CTL(pipe); |
2605 | temp = I915_READ(reg); | |
8db9d77b ZW |
2606 | temp &= ~FDI_LINK_TRAIN_NONE; |
2607 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2608 | if (IS_GEN6(dev)) { | |
2609 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2610 | /* SNB-B */ | |
2611 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2612 | } | |
5eddb70b | 2613 | I915_WRITE(reg, temp); |
8db9d77b | 2614 | |
5eddb70b CW |
2615 | reg = FDI_RX_CTL(pipe); |
2616 | temp = I915_READ(reg); | |
8db9d77b ZW |
2617 | if (HAS_PCH_CPT(dev)) { |
2618 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2619 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2620 | } else { | |
2621 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2622 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2623 | } | |
5eddb70b CW |
2624 | I915_WRITE(reg, temp); |
2625 | ||
2626 | POSTING_READ(reg); | |
8db9d77b ZW |
2627 | udelay(150); |
2628 | ||
0206e353 | 2629 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2630 | reg = FDI_TX_CTL(pipe); |
2631 | temp = I915_READ(reg); | |
8db9d77b ZW |
2632 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2633 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2634 | I915_WRITE(reg, temp); |
2635 | ||
2636 | POSTING_READ(reg); | |
8db9d77b ZW |
2637 | udelay(500); |
2638 | ||
fa37d39e SP |
2639 | for (retry = 0; retry < 5; retry++) { |
2640 | reg = FDI_RX_IIR(pipe); | |
2641 | temp = I915_READ(reg); | |
2642 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2643 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2644 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2645 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2646 | break; | |
2647 | } | |
2648 | udelay(50); | |
8db9d77b | 2649 | } |
fa37d39e SP |
2650 | if (retry < 5) |
2651 | break; | |
8db9d77b ZW |
2652 | } |
2653 | if (i == 4) | |
5eddb70b | 2654 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2655 | |
2656 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2657 | } | |
2658 | ||
357555c0 JB |
2659 | /* Manual link training for Ivy Bridge A0 parts */ |
2660 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2661 | { | |
2662 | struct drm_device *dev = crtc->dev; | |
2663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2665 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2666 | u32 reg, temp, i, j; |
357555c0 JB |
2667 | |
2668 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2669 | for train result */ | |
2670 | reg = FDI_RX_IMR(pipe); | |
2671 | temp = I915_READ(reg); | |
2672 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2673 | temp &= ~FDI_RX_BIT_LOCK; | |
2674 | I915_WRITE(reg, temp); | |
2675 | ||
2676 | POSTING_READ(reg); | |
2677 | udelay(150); | |
2678 | ||
01a415fd DV |
2679 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2680 | I915_READ(FDI_RX_IIR(pipe))); | |
2681 | ||
139ccd3f JB |
2682 | /* Try each vswing and preemphasis setting twice before moving on */ |
2683 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2684 | /* disable first in case we need to retry */ | |
2685 | reg = FDI_TX_CTL(pipe); | |
2686 | temp = I915_READ(reg); | |
2687 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2688 | temp &= ~FDI_TX_ENABLE; | |
2689 | I915_WRITE(reg, temp); | |
357555c0 | 2690 | |
139ccd3f JB |
2691 | reg = FDI_RX_CTL(pipe); |
2692 | temp = I915_READ(reg); | |
2693 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2694 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2695 | temp &= ~FDI_RX_ENABLE; | |
2696 | I915_WRITE(reg, temp); | |
357555c0 | 2697 | |
139ccd3f | 2698 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2699 | reg = FDI_TX_CTL(pipe); |
2700 | temp = I915_READ(reg); | |
139ccd3f JB |
2701 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2702 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2703 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2704 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2705 | temp |= snb_b_fdi_train_param[j/2]; |
2706 | temp |= FDI_COMPOSITE_SYNC; | |
2707 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2708 | |
139ccd3f JB |
2709 | I915_WRITE(FDI_RX_MISC(pipe), |
2710 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2711 | |
139ccd3f | 2712 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2713 | temp = I915_READ(reg); |
139ccd3f JB |
2714 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2715 | temp |= FDI_COMPOSITE_SYNC; | |
2716 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2717 | |
139ccd3f JB |
2718 | POSTING_READ(reg); |
2719 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2720 | |
139ccd3f JB |
2721 | for (i = 0; i < 4; i++) { |
2722 | reg = FDI_RX_IIR(pipe); | |
2723 | temp = I915_READ(reg); | |
2724 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2725 | |
139ccd3f JB |
2726 | if (temp & FDI_RX_BIT_LOCK || |
2727 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2728 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2729 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2730 | i); | |
2731 | break; | |
2732 | } | |
2733 | udelay(1); /* should be 0.5us */ | |
2734 | } | |
2735 | if (i == 4) { | |
2736 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2737 | continue; | |
2738 | } | |
357555c0 | 2739 | |
139ccd3f | 2740 | /* Train 2 */ |
357555c0 JB |
2741 | reg = FDI_TX_CTL(pipe); |
2742 | temp = I915_READ(reg); | |
139ccd3f JB |
2743 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2744 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2745 | I915_WRITE(reg, temp); | |
2746 | ||
2747 | reg = FDI_RX_CTL(pipe); | |
2748 | temp = I915_READ(reg); | |
2749 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2750 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2751 | I915_WRITE(reg, temp); |
2752 | ||
2753 | POSTING_READ(reg); | |
139ccd3f | 2754 | udelay(2); /* should be 1.5us */ |
357555c0 | 2755 | |
139ccd3f JB |
2756 | for (i = 0; i < 4; i++) { |
2757 | reg = FDI_RX_IIR(pipe); | |
2758 | temp = I915_READ(reg); | |
2759 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2760 | |
139ccd3f JB |
2761 | if (temp & FDI_RX_SYMBOL_LOCK || |
2762 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2763 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2764 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2765 | i); | |
2766 | goto train_done; | |
2767 | } | |
2768 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2769 | } |
139ccd3f JB |
2770 | if (i == 4) |
2771 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2772 | } |
357555c0 | 2773 | |
139ccd3f | 2774 | train_done: |
357555c0 JB |
2775 | DRM_DEBUG_KMS("FDI train done.\n"); |
2776 | } | |
2777 | ||
88cefb6c | 2778 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2779 | { |
88cefb6c | 2780 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2781 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2782 | int pipe = intel_crtc->pipe; |
5eddb70b | 2783 | u32 reg, temp; |
79e53945 | 2784 | |
c64e311e | 2785 | |
c98e9dcf | 2786 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2787 | reg = FDI_RX_CTL(pipe); |
2788 | temp = I915_READ(reg); | |
627eb5a3 DV |
2789 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2790 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2791 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2792 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2793 | ||
2794 | POSTING_READ(reg); | |
c98e9dcf JB |
2795 | udelay(200); |
2796 | ||
2797 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2798 | temp = I915_READ(reg); |
2799 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2800 | ||
2801 | POSTING_READ(reg); | |
c98e9dcf JB |
2802 | udelay(200); |
2803 | ||
20749730 PZ |
2804 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2805 | reg = FDI_TX_CTL(pipe); | |
2806 | temp = I915_READ(reg); | |
2807 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2808 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2809 | |
20749730 PZ |
2810 | POSTING_READ(reg); |
2811 | udelay(100); | |
6be4a607 | 2812 | } |
0e23b99d JB |
2813 | } |
2814 | ||
88cefb6c DV |
2815 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2816 | { | |
2817 | struct drm_device *dev = intel_crtc->base.dev; | |
2818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2819 | int pipe = intel_crtc->pipe; | |
2820 | u32 reg, temp; | |
2821 | ||
2822 | /* Switch from PCDclk to Rawclk */ | |
2823 | reg = FDI_RX_CTL(pipe); | |
2824 | temp = I915_READ(reg); | |
2825 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2826 | ||
2827 | /* Disable CPU FDI TX PLL */ | |
2828 | reg = FDI_TX_CTL(pipe); | |
2829 | temp = I915_READ(reg); | |
2830 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2831 | ||
2832 | POSTING_READ(reg); | |
2833 | udelay(100); | |
2834 | ||
2835 | reg = FDI_RX_CTL(pipe); | |
2836 | temp = I915_READ(reg); | |
2837 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2838 | ||
2839 | /* Wait for the clocks to turn off. */ | |
2840 | POSTING_READ(reg); | |
2841 | udelay(100); | |
2842 | } | |
2843 | ||
0fc932b8 JB |
2844 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2845 | { | |
2846 | struct drm_device *dev = crtc->dev; | |
2847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2849 | int pipe = intel_crtc->pipe; | |
2850 | u32 reg, temp; | |
2851 | ||
2852 | /* disable CPU FDI tx and PCH FDI rx */ | |
2853 | reg = FDI_TX_CTL(pipe); | |
2854 | temp = I915_READ(reg); | |
2855 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2856 | POSTING_READ(reg); | |
2857 | ||
2858 | reg = FDI_RX_CTL(pipe); | |
2859 | temp = I915_READ(reg); | |
2860 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2861 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2862 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2863 | ||
2864 | POSTING_READ(reg); | |
2865 | udelay(100); | |
2866 | ||
2867 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2868 | if (HAS_PCH_IBX(dev)) { |
2869 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2870 | } |
0fc932b8 JB |
2871 | |
2872 | /* still set train pattern 1 */ | |
2873 | reg = FDI_TX_CTL(pipe); | |
2874 | temp = I915_READ(reg); | |
2875 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2876 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2877 | I915_WRITE(reg, temp); | |
2878 | ||
2879 | reg = FDI_RX_CTL(pipe); | |
2880 | temp = I915_READ(reg); | |
2881 | if (HAS_PCH_CPT(dev)) { | |
2882 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2883 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2884 | } else { | |
2885 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2886 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2887 | } | |
2888 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2889 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2890 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2891 | I915_WRITE(reg, temp); |
2892 | ||
2893 | POSTING_READ(reg); | |
2894 | udelay(100); | |
2895 | } | |
2896 | ||
5bb61643 CW |
2897 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2898 | { | |
2899 | struct drm_device *dev = crtc->dev; | |
2900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2902 | unsigned long flags; |
2903 | bool pending; | |
2904 | ||
10d83730 VS |
2905 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2906 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2907 | return false; |
2908 | ||
2909 | spin_lock_irqsave(&dev->event_lock, flags); | |
2910 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2911 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2912 | ||
2913 | return pending; | |
2914 | } | |
2915 | ||
e6c3a2a6 CW |
2916 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2917 | { | |
0f91128d | 2918 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2919 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2920 | |
2921 | if (crtc->fb == NULL) | |
2922 | return; | |
2923 | ||
2c10d571 DV |
2924 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2925 | ||
5bb61643 CW |
2926 | wait_event(dev_priv->pending_flip_queue, |
2927 | !intel_crtc_has_pending_flip(crtc)); | |
2928 | ||
0f91128d CW |
2929 | mutex_lock(&dev->struct_mutex); |
2930 | intel_finish_fb(crtc->fb); | |
2931 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2932 | } |
2933 | ||
e615efe4 ED |
2934 | /* Program iCLKIP clock to the desired frequency */ |
2935 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2936 | { | |
2937 | struct drm_device *dev = crtc->dev; | |
2938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 2939 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
2940 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2941 | u32 temp; | |
2942 | ||
09153000 DV |
2943 | mutex_lock(&dev_priv->dpio_lock); |
2944 | ||
e615efe4 ED |
2945 | /* It is necessary to ungate the pixclk gate prior to programming |
2946 | * the divisors, and gate it back when it is done. | |
2947 | */ | |
2948 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2949 | ||
2950 | /* Disable SSCCTL */ | |
2951 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2952 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2953 | SBI_SSCCTL_DISABLE, | |
2954 | SBI_ICLK); | |
e615efe4 ED |
2955 | |
2956 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 2957 | if (clock == 20000) { |
e615efe4 ED |
2958 | auxdiv = 1; |
2959 | divsel = 0x41; | |
2960 | phaseinc = 0x20; | |
2961 | } else { | |
2962 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
2963 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
2964 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
2965 | * convert the virtual clock precision to KHz here for higher |
2966 | * precision. | |
2967 | */ | |
2968 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2969 | u32 iclk_pi_range = 64; | |
2970 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2971 | ||
12d7ceed | 2972 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
2973 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2974 | pi_value = desired_divisor % iclk_pi_range; | |
2975 | ||
2976 | auxdiv = 0; | |
2977 | divsel = msb_divisor_value - 2; | |
2978 | phaseinc = pi_value; | |
2979 | } | |
2980 | ||
2981 | /* This should not happen with any sane values */ | |
2982 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2983 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2984 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2985 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2986 | ||
2987 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 2988 | clock, |
e615efe4 ED |
2989 | auxdiv, |
2990 | divsel, | |
2991 | phasedir, | |
2992 | phaseinc); | |
2993 | ||
2994 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 2995 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
2996 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2997 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2998 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2999 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3000 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3001 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3002 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3003 | |
3004 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3005 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3006 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3007 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3008 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3009 | |
3010 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3011 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3012 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3013 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3014 | |
3015 | /* Wait for initialization time */ | |
3016 | udelay(24); | |
3017 | ||
3018 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3019 | |
3020 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3021 | } |
3022 | ||
275f01b2 DV |
3023 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3024 | enum pipe pch_transcoder) | |
3025 | { | |
3026 | struct drm_device *dev = crtc->base.dev; | |
3027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3028 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3029 | ||
3030 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3031 | I915_READ(HTOTAL(cpu_transcoder))); | |
3032 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3033 | I915_READ(HBLANK(cpu_transcoder))); | |
3034 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3035 | I915_READ(HSYNC(cpu_transcoder))); | |
3036 | ||
3037 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3038 | I915_READ(VTOTAL(cpu_transcoder))); | |
3039 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3040 | I915_READ(VBLANK(cpu_transcoder))); | |
3041 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3042 | I915_READ(VSYNC(cpu_transcoder))); | |
3043 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3044 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3045 | } | |
3046 | ||
f67a559d JB |
3047 | /* |
3048 | * Enable PCH resources required for PCH ports: | |
3049 | * - PCH PLLs | |
3050 | * - FDI training & RX/TX | |
3051 | * - update transcoder timings | |
3052 | * - DP transcoding bits | |
3053 | * - transcoder | |
3054 | */ | |
3055 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3056 | { |
3057 | struct drm_device *dev = crtc->dev; | |
3058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3059 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3060 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3061 | u32 reg, temp; |
2c07245f | 3062 | |
ab9412ba | 3063 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3064 | |
cd986abb DV |
3065 | /* Write the TU size bits before fdi link training, so that error |
3066 | * detection works. */ | |
3067 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3068 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3069 | ||
c98e9dcf | 3070 | /* For PCH output, training FDI link */ |
674cf967 | 3071 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3072 | |
3ad8a208 DV |
3073 | /* We need to program the right clock selection before writing the pixel |
3074 | * mutliplier into the DPLL. */ | |
303b81e0 | 3075 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3076 | u32 sel; |
4b645f14 | 3077 | |
c98e9dcf | 3078 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3079 | temp |= TRANS_DPLL_ENABLE(pipe); |
3080 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3081 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3082 | temp |= sel; |
3083 | else | |
3084 | temp &= ~sel; | |
c98e9dcf | 3085 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3086 | } |
5eddb70b | 3087 | |
3ad8a208 DV |
3088 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3089 | * transcoder, and we actually should do this to not upset any PCH | |
3090 | * transcoder that already use the clock when we share it. | |
3091 | * | |
3092 | * Note that enable_shared_dpll tries to do the right thing, but | |
3093 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3094 | * the right LVDS enable sequence. */ | |
3095 | ironlake_enable_shared_dpll(intel_crtc); | |
3096 | ||
d9b6cb56 JB |
3097 | /* set transcoder timing, panel must allow it */ |
3098 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3099 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3100 | |
303b81e0 | 3101 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3102 | |
c98e9dcf JB |
3103 | /* For PCH DP, enable TRANS_DP_CTL */ |
3104 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3105 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3106 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3107 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3108 | reg = TRANS_DP_CTL(pipe); |
3109 | temp = I915_READ(reg); | |
3110 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3111 | TRANS_DP_SYNC_MASK | |
3112 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3113 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3114 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3115 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3116 | |
3117 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3118 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3119 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3120 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3121 | |
3122 | switch (intel_trans_dp_port_sel(crtc)) { | |
3123 | case PCH_DP_B: | |
5eddb70b | 3124 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3125 | break; |
3126 | case PCH_DP_C: | |
5eddb70b | 3127 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3128 | break; |
3129 | case PCH_DP_D: | |
5eddb70b | 3130 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3131 | break; |
3132 | default: | |
e95d41e1 | 3133 | BUG(); |
32f9d658 | 3134 | } |
2c07245f | 3135 | |
5eddb70b | 3136 | I915_WRITE(reg, temp); |
6be4a607 | 3137 | } |
b52eb4dc | 3138 | |
b8a4f404 | 3139 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3140 | } |
3141 | ||
1507e5bd PZ |
3142 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3143 | { | |
3144 | struct drm_device *dev = crtc->dev; | |
3145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3147 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3148 | |
ab9412ba | 3149 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3150 | |
8c52b5e8 | 3151 | lpt_program_iclkip(crtc); |
1507e5bd | 3152 | |
0540e488 | 3153 | /* Set transcoder timing. */ |
275f01b2 | 3154 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3155 | |
937bb610 | 3156 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3157 | } |
3158 | ||
e2b78267 | 3159 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3160 | { |
e2b78267 | 3161 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3162 | |
3163 | if (pll == NULL) | |
3164 | return; | |
3165 | ||
3166 | if (pll->refcount == 0) { | |
46edb027 | 3167 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3168 | return; |
3169 | } | |
3170 | ||
f4a091c7 DV |
3171 | if (--pll->refcount == 0) { |
3172 | WARN_ON(pll->on); | |
3173 | WARN_ON(pll->active); | |
3174 | } | |
3175 | ||
a43f6e0f | 3176 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3177 | } |
3178 | ||
b89a1d39 | 3179 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3180 | { |
e2b78267 DV |
3181 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3182 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3183 | enum intel_dpll_id i; | |
ee7b9f93 | 3184 | |
ee7b9f93 | 3185 | if (pll) { |
46edb027 DV |
3186 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3187 | crtc->base.base.id, pll->name); | |
e2b78267 | 3188 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3189 | } |
3190 | ||
98b6bd99 DV |
3191 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3192 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3193 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3194 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3195 | |
46edb027 DV |
3196 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3197 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3198 | |
3199 | goto found; | |
3200 | } | |
3201 | ||
e72f9fbf DV |
3202 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3203 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3204 | |
3205 | /* Only want to check enabled timings first */ | |
3206 | if (pll->refcount == 0) | |
3207 | continue; | |
3208 | ||
b89a1d39 DV |
3209 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3210 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3211 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3212 | crtc->base.base.id, |
46edb027 | 3213 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3214 | |
3215 | goto found; | |
3216 | } | |
3217 | } | |
3218 | ||
3219 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3220 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3221 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3222 | if (pll->refcount == 0) { |
46edb027 DV |
3223 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3224 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3225 | goto found; |
3226 | } | |
3227 | } | |
3228 | ||
3229 | return NULL; | |
3230 | ||
3231 | found: | |
a43f6e0f | 3232 | crtc->config.shared_dpll = i; |
46edb027 DV |
3233 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3234 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3235 | |
cdbd2316 | 3236 | if (pll->active == 0) { |
66e985c0 DV |
3237 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3238 | sizeof(pll->hw_state)); | |
3239 | ||
46edb027 | 3240 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3241 | WARN_ON(pll->on); |
e9d6944e | 3242 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3243 | |
15bdd4cf | 3244 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3245 | } |
3246 | pll->refcount++; | |
e04c7350 | 3247 | |
ee7b9f93 JB |
3248 | return pll; |
3249 | } | |
3250 | ||
a1520318 | 3251 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3252 | { |
3253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3254 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3255 | u32 temp; |
3256 | ||
3257 | temp = I915_READ(dslreg); | |
3258 | udelay(500); | |
3259 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3260 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3261 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3262 | } |
3263 | } | |
3264 | ||
b074cec8 JB |
3265 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3266 | { | |
3267 | struct drm_device *dev = crtc->base.dev; | |
3268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3269 | int pipe = crtc->pipe; | |
3270 | ||
fd4daa9c | 3271 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3272 | /* Force use of hard-coded filter coefficients |
3273 | * as some pre-programmed values are broken, | |
3274 | * e.g. x201. | |
3275 | */ | |
3276 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3277 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3278 | PF_PIPE_SEL_IVB(pipe)); | |
3279 | else | |
3280 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3281 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3282 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3283 | } |
3284 | } | |
3285 | ||
bb53d4ae VS |
3286 | static void intel_enable_planes(struct drm_crtc *crtc) |
3287 | { | |
3288 | struct drm_device *dev = crtc->dev; | |
3289 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3290 | struct intel_plane *intel_plane; | |
3291 | ||
3292 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3293 | if (intel_plane->pipe == pipe) | |
3294 | intel_plane_restore(&intel_plane->base); | |
3295 | } | |
3296 | ||
3297 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3298 | { | |
3299 | struct drm_device *dev = crtc->dev; | |
3300 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3301 | struct intel_plane *intel_plane; | |
3302 | ||
3303 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3304 | if (intel_plane->pipe == pipe) | |
3305 | intel_plane_disable(&intel_plane->base); | |
3306 | } | |
3307 | ||
d77e4531 PZ |
3308 | static void hsw_enable_ips(struct intel_crtc *crtc) |
3309 | { | |
3310 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3311 | ||
3312 | if (!crtc->config.ips_enabled) | |
3313 | return; | |
3314 | ||
3315 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3316 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3317 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3318 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3319 | assert_plane_enabled(dev_priv, crtc->plane); | |
3320 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3321 | } | |
3322 | ||
3323 | static void hsw_disable_ips(struct intel_crtc *crtc) | |
3324 | { | |
3325 | struct drm_device *dev = crtc->base.dev; | |
3326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3327 | ||
3328 | if (!crtc->config.ips_enabled) | |
3329 | return; | |
3330 | ||
3331 | assert_plane_enabled(dev_priv, crtc->plane); | |
3332 | I915_WRITE(IPS_CTL, 0); | |
3333 | POSTING_READ(IPS_CTL); | |
3334 | ||
3335 | /* We need to wait for a vblank before we can disable the plane. */ | |
3336 | intel_wait_for_vblank(dev, crtc->pipe); | |
3337 | } | |
3338 | ||
3339 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3340 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3341 | { | |
3342 | struct drm_device *dev = crtc->dev; | |
3343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3344 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3345 | enum pipe pipe = intel_crtc->pipe; | |
3346 | int palreg = PALETTE(pipe); | |
3347 | int i; | |
3348 | bool reenable_ips = false; | |
3349 | ||
3350 | /* The clocks have to be on to load the palette. */ | |
3351 | if (!crtc->enabled || !intel_crtc->active) | |
3352 | return; | |
3353 | ||
3354 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3355 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3356 | assert_dsi_pll_enabled(dev_priv); | |
3357 | else | |
3358 | assert_pll_enabled(dev_priv, pipe); | |
3359 | } | |
3360 | ||
3361 | /* use legacy palette for Ironlake */ | |
3362 | if (HAS_PCH_SPLIT(dev)) | |
3363 | palreg = LGC_PALETTE(pipe); | |
3364 | ||
3365 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3366 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3367 | */ | |
3368 | if (intel_crtc->config.ips_enabled && | |
3369 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == | |
3370 | GAMMA_MODE_MODE_SPLIT)) { | |
3371 | hsw_disable_ips(intel_crtc); | |
3372 | reenable_ips = true; | |
3373 | } | |
3374 | ||
3375 | for (i = 0; i < 256; i++) { | |
3376 | I915_WRITE(palreg + 4 * i, | |
3377 | (intel_crtc->lut_r[i] << 16) | | |
3378 | (intel_crtc->lut_g[i] << 8) | | |
3379 | intel_crtc->lut_b[i]); | |
3380 | } | |
3381 | ||
3382 | if (reenable_ips) | |
3383 | hsw_enable_ips(intel_crtc); | |
3384 | } | |
3385 | ||
f67a559d JB |
3386 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3387 | { | |
3388 | struct drm_device *dev = crtc->dev; | |
3389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3390 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3391 | struct intel_encoder *encoder; |
f67a559d JB |
3392 | int pipe = intel_crtc->pipe; |
3393 | int plane = intel_crtc->plane; | |
f67a559d | 3394 | |
08a48469 DV |
3395 | WARN_ON(!crtc->enabled); |
3396 | ||
f67a559d JB |
3397 | if (intel_crtc->active) |
3398 | return; | |
3399 | ||
3400 | intel_crtc->active = true; | |
8664281b PZ |
3401 | |
3402 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3403 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3404 | ||
f6736a1a | 3405 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3406 | if (encoder->pre_enable) |
3407 | encoder->pre_enable(encoder); | |
f67a559d | 3408 | |
5bfe2ac0 | 3409 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3410 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3411 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3412 | * enabling. */ | |
88cefb6c | 3413 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3414 | } else { |
3415 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3416 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3417 | } | |
f67a559d | 3418 | |
b074cec8 | 3419 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3420 | |
9c54c0dd JB |
3421 | /* |
3422 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3423 | * clocks enabled | |
3424 | */ | |
3425 | intel_crtc_load_lut(crtc); | |
3426 | ||
f37fcc2a | 3427 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3428 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3429 | intel_crtc->config.has_pch_encoder, false); |
f67a559d | 3430 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3431 | intel_enable_planes(crtc); |
5c38d48c | 3432 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3433 | |
5bfe2ac0 | 3434 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3435 | ironlake_pch_enable(crtc); |
c98e9dcf | 3436 | |
d1ebd816 | 3437 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3438 | intel_update_fbc(dev); |
d1ebd816 BW |
3439 | mutex_unlock(&dev->struct_mutex); |
3440 | ||
fa5c73b1 DV |
3441 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3442 | encoder->enable(encoder); | |
61b77ddd DV |
3443 | |
3444 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3445 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3446 | |
3447 | /* | |
3448 | * There seems to be a race in PCH platform hw (at least on some | |
3449 | * outputs) where an enabled pipe still completes any pageflip right | |
3450 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3451 | * as the first vblank happend, everything works as expected. Hence just | |
3452 | * wait for one vblank before returning to avoid strange things | |
3453 | * happening. | |
3454 | */ | |
3455 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3456 | } |
3457 | ||
42db64ef PZ |
3458 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3459 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3460 | { | |
f5adf94e | 3461 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3462 | } |
3463 | ||
dda9a66a VS |
3464 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3465 | { | |
3466 | struct drm_device *dev = crtc->dev; | |
3467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3468 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3469 | int pipe = intel_crtc->pipe; | |
3470 | int plane = intel_crtc->plane; | |
3471 | ||
3472 | intel_enable_plane(dev_priv, plane, pipe); | |
3473 | intel_enable_planes(crtc); | |
3474 | intel_crtc_update_cursor(crtc, true); | |
3475 | ||
3476 | hsw_enable_ips(intel_crtc); | |
3477 | ||
3478 | mutex_lock(&dev->struct_mutex); | |
3479 | intel_update_fbc(dev); | |
3480 | mutex_unlock(&dev->struct_mutex); | |
3481 | } | |
3482 | ||
3483 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3484 | { | |
3485 | struct drm_device *dev = crtc->dev; | |
3486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3488 | int pipe = intel_crtc->pipe; | |
3489 | int plane = intel_crtc->plane; | |
3490 | ||
3491 | intel_crtc_wait_for_pending_flips(crtc); | |
3492 | drm_vblank_off(dev, pipe); | |
3493 | ||
3494 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3495 | if (dev_priv->fbc.plane == plane) | |
3496 | intel_disable_fbc(dev); | |
3497 | ||
3498 | hsw_disable_ips(intel_crtc); | |
3499 | ||
3500 | intel_crtc_update_cursor(crtc, false); | |
3501 | intel_disable_planes(crtc); | |
3502 | intel_disable_plane(dev_priv, plane, pipe); | |
3503 | } | |
3504 | ||
e4916946 PZ |
3505 | /* |
3506 | * This implements the workaround described in the "notes" section of the mode | |
3507 | * set sequence documentation. When going from no pipes or single pipe to | |
3508 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3509 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3510 | */ | |
3511 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3512 | { | |
3513 | struct drm_device *dev = crtc->base.dev; | |
3514 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3515 | ||
3516 | /* We want to get the other_active_crtc only if there's only 1 other | |
3517 | * active crtc. */ | |
3518 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3519 | if (!crtc_it->active || crtc_it == crtc) | |
3520 | continue; | |
3521 | ||
3522 | if (other_active_crtc) | |
3523 | return; | |
3524 | ||
3525 | other_active_crtc = crtc_it; | |
3526 | } | |
3527 | if (!other_active_crtc) | |
3528 | return; | |
3529 | ||
3530 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3531 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3532 | } | |
3533 | ||
4f771f10 PZ |
3534 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3535 | { | |
3536 | struct drm_device *dev = crtc->dev; | |
3537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3539 | struct intel_encoder *encoder; | |
3540 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3541 | |
3542 | WARN_ON(!crtc->enabled); | |
3543 | ||
3544 | if (intel_crtc->active) | |
3545 | return; | |
3546 | ||
3547 | intel_crtc->active = true; | |
8664281b PZ |
3548 | |
3549 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3550 | if (intel_crtc->config.has_pch_encoder) | |
3551 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3552 | ||
5bfe2ac0 | 3553 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3554 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3555 | |
3556 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3557 | if (encoder->pre_enable) | |
3558 | encoder->pre_enable(encoder); | |
3559 | ||
1f544388 | 3560 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3561 | |
b074cec8 | 3562 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3563 | |
3564 | /* | |
3565 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3566 | * clocks enabled | |
3567 | */ | |
3568 | intel_crtc_load_lut(crtc); | |
3569 | ||
1f544388 | 3570 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3571 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3572 | |
f37fcc2a | 3573 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3574 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3575 | intel_crtc->config.has_pch_encoder, false); |
42db64ef | 3576 | |
5bfe2ac0 | 3577 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3578 | lpt_pch_enable(crtc); |
4f771f10 | 3579 | |
8807e55b | 3580 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3581 | encoder->enable(encoder); |
8807e55b JN |
3582 | intel_opregion_notify_encoder(encoder, true); |
3583 | } | |
4f771f10 | 3584 | |
e4916946 PZ |
3585 | /* If we change the relative order between pipe/planes enabling, we need |
3586 | * to change the workaround. */ | |
3587 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a VS |
3588 | haswell_crtc_enable_planes(crtc); |
3589 | ||
4f771f10 PZ |
3590 | /* |
3591 | * There seems to be a race in PCH platform hw (at least on some | |
3592 | * outputs) where an enabled pipe still completes any pageflip right | |
3593 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3594 | * as the first vblank happend, everything works as expected. Hence just | |
3595 | * wait for one vblank before returning to avoid strange things | |
3596 | * happening. | |
3597 | */ | |
3598 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3599 | } | |
3600 | ||
3f8dce3a DV |
3601 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3602 | { | |
3603 | struct drm_device *dev = crtc->base.dev; | |
3604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3605 | int pipe = crtc->pipe; | |
3606 | ||
3607 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3608 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3609 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3610 | I915_WRITE(PF_CTL(pipe), 0); |
3611 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3612 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3613 | } | |
3614 | } | |
3615 | ||
6be4a607 JB |
3616 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3617 | { | |
3618 | struct drm_device *dev = crtc->dev; | |
3619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3621 | struct intel_encoder *encoder; |
6be4a607 JB |
3622 | int pipe = intel_crtc->pipe; |
3623 | int plane = intel_crtc->plane; | |
5eddb70b | 3624 | u32 reg, temp; |
b52eb4dc | 3625 | |
ef9c3aee | 3626 | |
f7abfe8b CW |
3627 | if (!intel_crtc->active) |
3628 | return; | |
3629 | ||
ea9d758d DV |
3630 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3631 | encoder->disable(encoder); | |
3632 | ||
e6c3a2a6 | 3633 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3634 | drm_vblank_off(dev, pipe); |
913d8d11 | 3635 | |
5c3fe8b0 | 3636 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3637 | intel_disable_fbc(dev); |
2c07245f | 3638 | |
0d5b8c61 | 3639 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3640 | intel_disable_planes(crtc); |
0d5b8c61 VS |
3641 | intel_disable_plane(dev_priv, plane, pipe); |
3642 | ||
d925c59a DV |
3643 | if (intel_crtc->config.has_pch_encoder) |
3644 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3645 | ||
b24e7179 | 3646 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3647 | |
3f8dce3a | 3648 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3649 | |
bf49ec8c DV |
3650 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3651 | if (encoder->post_disable) | |
3652 | encoder->post_disable(encoder); | |
2c07245f | 3653 | |
d925c59a DV |
3654 | if (intel_crtc->config.has_pch_encoder) { |
3655 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3656 | |
d925c59a DV |
3657 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3658 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3659 | |
d925c59a DV |
3660 | if (HAS_PCH_CPT(dev)) { |
3661 | /* disable TRANS_DP_CTL */ | |
3662 | reg = TRANS_DP_CTL(pipe); | |
3663 | temp = I915_READ(reg); | |
3664 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3665 | TRANS_DP_PORT_SEL_MASK); | |
3666 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3667 | I915_WRITE(reg, temp); | |
3668 | ||
3669 | /* disable DPLL_SEL */ | |
3670 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3671 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3672 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3673 | } |
e3421a18 | 3674 | |
d925c59a | 3675 | /* disable PCH DPLL */ |
e72f9fbf | 3676 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3677 | |
d925c59a DV |
3678 | ironlake_fdi_pll_disable(intel_crtc); |
3679 | } | |
6b383a7f | 3680 | |
f7abfe8b | 3681 | intel_crtc->active = false; |
46ba614c | 3682 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3683 | |
3684 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3685 | intel_update_fbc(dev); |
d1ebd816 | 3686 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3687 | } |
1b3c7a47 | 3688 | |
4f771f10 | 3689 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3690 | { |
4f771f10 PZ |
3691 | struct drm_device *dev = crtc->dev; |
3692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3694 | struct intel_encoder *encoder; |
3695 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3696 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3697 | |
4f771f10 PZ |
3698 | if (!intel_crtc->active) |
3699 | return; | |
3700 | ||
dda9a66a VS |
3701 | haswell_crtc_disable_planes(crtc); |
3702 | ||
8807e55b JN |
3703 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3704 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3705 | encoder->disable(encoder); |
8807e55b | 3706 | } |
4f771f10 | 3707 | |
8664281b PZ |
3708 | if (intel_crtc->config.has_pch_encoder) |
3709 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3710 | intel_disable_pipe(dev_priv, pipe); |
3711 | ||
ad80a810 | 3712 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3713 | |
3f8dce3a | 3714 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3715 | |
1f544388 | 3716 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3717 | |
3718 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3719 | if (encoder->post_disable) | |
3720 | encoder->post_disable(encoder); | |
3721 | ||
88adfff1 | 3722 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3723 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3724 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3725 | intel_ddi_fdi_disable(crtc); |
83616634 | 3726 | } |
4f771f10 PZ |
3727 | |
3728 | intel_crtc->active = false; | |
46ba614c | 3729 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3730 | |
3731 | mutex_lock(&dev->struct_mutex); | |
3732 | intel_update_fbc(dev); | |
3733 | mutex_unlock(&dev->struct_mutex); | |
3734 | } | |
3735 | ||
ee7b9f93 JB |
3736 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3737 | { | |
3738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3739 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3740 | } |
3741 | ||
6441ab5f PZ |
3742 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3743 | { | |
3744 | intel_ddi_put_crtc_pll(crtc); | |
3745 | } | |
3746 | ||
02e792fb DV |
3747 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3748 | { | |
02e792fb | 3749 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3750 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3751 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3752 | |
23f09ce3 | 3753 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3754 | dev_priv->mm.interruptible = false; |
3755 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3756 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3757 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3758 | } |
02e792fb | 3759 | |
5dcdbcb0 CW |
3760 | /* Let userspace switch the overlay on again. In most cases userspace |
3761 | * has to recompute where to put it anyway. | |
3762 | */ | |
02e792fb DV |
3763 | } |
3764 | ||
61bc95c1 EE |
3765 | /** |
3766 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3767 | * cursor plane briefly if not already running after enabling the display | |
3768 | * plane. | |
3769 | * This workaround avoids occasional blank screens when self refresh is | |
3770 | * enabled. | |
3771 | */ | |
3772 | static void | |
3773 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3774 | { | |
3775 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3776 | ||
3777 | if ((cntl & CURSOR_MODE) == 0) { | |
3778 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3779 | ||
3780 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3781 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3782 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3783 | I915_WRITE(CURCNTR(pipe), cntl); | |
3784 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3785 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3786 | } | |
3787 | } | |
3788 | ||
2dd24552 JB |
3789 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3790 | { | |
3791 | struct drm_device *dev = crtc->base.dev; | |
3792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3793 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3794 | ||
328d8e82 | 3795 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3796 | return; |
3797 | ||
2dd24552 | 3798 | /* |
c0b03411 DV |
3799 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3800 | * according to register description and PRM. | |
2dd24552 | 3801 | */ |
c0b03411 DV |
3802 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3803 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3804 | |
b074cec8 JB |
3805 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3806 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3807 | |
3808 | /* Border color in case we don't scale up to the full screen. Black by | |
3809 | * default, change to something else for debugging. */ | |
3810 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3811 | } |
3812 | ||
89b667f8 JB |
3813 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3814 | { | |
3815 | struct drm_device *dev = crtc->dev; | |
3816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3817 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3818 | struct intel_encoder *encoder; | |
3819 | int pipe = intel_crtc->pipe; | |
3820 | int plane = intel_crtc->plane; | |
23538ef1 | 3821 | bool is_dsi; |
89b667f8 JB |
3822 | |
3823 | WARN_ON(!crtc->enabled); | |
3824 | ||
3825 | if (intel_crtc->active) | |
3826 | return; | |
3827 | ||
3828 | intel_crtc->active = true; | |
89b667f8 | 3829 | |
89b667f8 JB |
3830 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3831 | if (encoder->pre_pll_enable) | |
3832 | encoder->pre_pll_enable(encoder); | |
3833 | ||
23538ef1 JN |
3834 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
3835 | ||
e9fd1c02 JN |
3836 | if (!is_dsi) |
3837 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
3838 | |
3839 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3840 | if (encoder->pre_enable) | |
3841 | encoder->pre_enable(encoder); | |
3842 | ||
2dd24552 JB |
3843 | i9xx_pfit_enable(intel_crtc); |
3844 | ||
63cbb074 VS |
3845 | intel_crtc_load_lut(crtc); |
3846 | ||
f37fcc2a | 3847 | intel_update_watermarks(crtc); |
23538ef1 | 3848 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
89b667f8 | 3849 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3850 | intel_enable_planes(crtc); |
5c38d48c | 3851 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 3852 | |
89b667f8 | 3853 | intel_update_fbc(dev); |
5004945f JN |
3854 | |
3855 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3856 | encoder->enable(encoder); | |
89b667f8 JB |
3857 | } |
3858 | ||
0b8765c6 | 3859 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3860 | { |
3861 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3862 | struct drm_i915_private *dev_priv = dev->dev_private; |
3863 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3864 | struct intel_encoder *encoder; |
79e53945 | 3865 | int pipe = intel_crtc->pipe; |
80824003 | 3866 | int plane = intel_crtc->plane; |
79e53945 | 3867 | |
08a48469 DV |
3868 | WARN_ON(!crtc->enabled); |
3869 | ||
f7abfe8b CW |
3870 | if (intel_crtc->active) |
3871 | return; | |
3872 | ||
3873 | intel_crtc->active = true; | |
6b383a7f | 3874 | |
9d6d9f19 MK |
3875 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3876 | if (encoder->pre_enable) | |
3877 | encoder->pre_enable(encoder); | |
3878 | ||
f6736a1a DV |
3879 | i9xx_enable_pll(intel_crtc); |
3880 | ||
2dd24552 JB |
3881 | i9xx_pfit_enable(intel_crtc); |
3882 | ||
63cbb074 VS |
3883 | intel_crtc_load_lut(crtc); |
3884 | ||
f37fcc2a | 3885 | intel_update_watermarks(crtc); |
23538ef1 | 3886 | intel_enable_pipe(dev_priv, pipe, false, false); |
b24e7179 | 3887 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3888 | intel_enable_planes(crtc); |
22e407d7 | 3889 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
3890 | if (IS_G4X(dev)) |
3891 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 3892 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 3893 | |
0b8765c6 JB |
3894 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3895 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 3896 | |
f440eb13 | 3897 | intel_update_fbc(dev); |
ef9c3aee | 3898 | |
fa5c73b1 DV |
3899 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3900 | encoder->enable(encoder); | |
0b8765c6 | 3901 | } |
79e53945 | 3902 | |
87476d63 DV |
3903 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3904 | { | |
3905 | struct drm_device *dev = crtc->base.dev; | |
3906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 3907 | |
328d8e82 DV |
3908 | if (!crtc->config.gmch_pfit.control) |
3909 | return; | |
87476d63 | 3910 | |
328d8e82 | 3911 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 3912 | |
328d8e82 DV |
3913 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3914 | I915_READ(PFIT_CONTROL)); | |
3915 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
3916 | } |
3917 | ||
0b8765c6 JB |
3918 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3919 | { | |
3920 | struct drm_device *dev = crtc->dev; | |
3921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3923 | struct intel_encoder *encoder; |
0b8765c6 JB |
3924 | int pipe = intel_crtc->pipe; |
3925 | int plane = intel_crtc->plane; | |
ef9c3aee | 3926 | |
f7abfe8b CW |
3927 | if (!intel_crtc->active) |
3928 | return; | |
3929 | ||
ea9d758d DV |
3930 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3931 | encoder->disable(encoder); | |
3932 | ||
0b8765c6 | 3933 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3934 | intel_crtc_wait_for_pending_flips(crtc); |
3935 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3936 | |
5c3fe8b0 | 3937 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3938 | intel_disable_fbc(dev); |
79e53945 | 3939 | |
0d5b8c61 VS |
3940 | intel_crtc_dpms_overlay(intel_crtc, false); |
3941 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 3942 | intel_disable_planes(crtc); |
b24e7179 | 3943 | intel_disable_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3944 | |
b24e7179 | 3945 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 3946 | |
87476d63 | 3947 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 3948 | |
89b667f8 JB |
3949 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3950 | if (encoder->post_disable) | |
3951 | encoder->post_disable(encoder); | |
3952 | ||
f6071166 JB |
3953 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
3954 | vlv_disable_pll(dev_priv, pipe); | |
3955 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 3956 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 3957 | |
f7abfe8b | 3958 | intel_crtc->active = false; |
46ba614c | 3959 | intel_update_watermarks(crtc); |
f37fcc2a | 3960 | |
6b383a7f | 3961 | intel_update_fbc(dev); |
0b8765c6 JB |
3962 | } |
3963 | ||
ee7b9f93 JB |
3964 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3965 | { | |
3966 | } | |
3967 | ||
976f8a20 DV |
3968 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3969 | bool enabled) | |
2c07245f ZW |
3970 | { |
3971 | struct drm_device *dev = crtc->dev; | |
3972 | struct drm_i915_master_private *master_priv; | |
3973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3974 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3975 | |
3976 | if (!dev->primary->master) | |
3977 | return; | |
3978 | ||
3979 | master_priv = dev->primary->master->driver_priv; | |
3980 | if (!master_priv->sarea_priv) | |
3981 | return; | |
3982 | ||
79e53945 JB |
3983 | switch (pipe) { |
3984 | case 0: | |
3985 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3986 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3987 | break; | |
3988 | case 1: | |
3989 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3990 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3991 | break; | |
3992 | default: | |
9db4a9c7 | 3993 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3994 | break; |
3995 | } | |
79e53945 JB |
3996 | } |
3997 | ||
976f8a20 DV |
3998 | /** |
3999 | * Sets the power management mode of the pipe and plane. | |
4000 | */ | |
4001 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4002 | { | |
4003 | struct drm_device *dev = crtc->dev; | |
4004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4005 | struct intel_encoder *intel_encoder; | |
4006 | bool enable = false; | |
4007 | ||
4008 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4009 | enable |= intel_encoder->connectors_active; | |
4010 | ||
4011 | if (enable) | |
4012 | dev_priv->display.crtc_enable(crtc); | |
4013 | else | |
4014 | dev_priv->display.crtc_disable(crtc); | |
4015 | ||
4016 | intel_crtc_update_sarea(crtc, enable); | |
4017 | } | |
4018 | ||
cdd59983 CW |
4019 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4020 | { | |
cdd59983 | 4021 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4022 | struct drm_connector *connector; |
ee7b9f93 | 4023 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4024 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4025 | |
976f8a20 DV |
4026 | /* crtc should still be enabled when we disable it. */ |
4027 | WARN_ON(!crtc->enabled); | |
4028 | ||
4029 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4030 | intel_crtc->eld_vld = false; |
976f8a20 | 4031 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4032 | dev_priv->display.off(crtc); |
4033 | ||
931872fc | 4034 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4035 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4036 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4037 | |
4038 | if (crtc->fb) { | |
4039 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4040 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4041 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4042 | crtc->fb = NULL; |
4043 | } | |
4044 | ||
4045 | /* Update computed state. */ | |
4046 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4047 | if (!connector->encoder || !connector->encoder->crtc) | |
4048 | continue; | |
4049 | ||
4050 | if (connector->encoder->crtc != crtc) | |
4051 | continue; | |
4052 | ||
4053 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4054 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4055 | } |
4056 | } | |
4057 | ||
ea5b213a | 4058 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4059 | { |
4ef69c7a | 4060 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4061 | |
ea5b213a CW |
4062 | drm_encoder_cleanup(encoder); |
4063 | kfree(intel_encoder); | |
7e7d76c3 JB |
4064 | } |
4065 | ||
9237329d | 4066 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4067 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4068 | * state of the entire output pipe. */ | |
9237329d | 4069 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4070 | { |
5ab432ef DV |
4071 | if (mode == DRM_MODE_DPMS_ON) { |
4072 | encoder->connectors_active = true; | |
4073 | ||
b2cabb0e | 4074 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4075 | } else { |
4076 | encoder->connectors_active = false; | |
4077 | ||
b2cabb0e | 4078 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4079 | } |
79e53945 JB |
4080 | } |
4081 | ||
0a91ca29 DV |
4082 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4083 | * internal consistency). */ | |
b980514c | 4084 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4085 | { |
0a91ca29 DV |
4086 | if (connector->get_hw_state(connector)) { |
4087 | struct intel_encoder *encoder = connector->encoder; | |
4088 | struct drm_crtc *crtc; | |
4089 | bool encoder_enabled; | |
4090 | enum pipe pipe; | |
4091 | ||
4092 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4093 | connector->base.base.id, | |
4094 | drm_get_connector_name(&connector->base)); | |
4095 | ||
4096 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4097 | "wrong connector dpms state\n"); | |
4098 | WARN(connector->base.encoder != &encoder->base, | |
4099 | "active connector not linked to encoder\n"); | |
4100 | WARN(!encoder->connectors_active, | |
4101 | "encoder->connectors_active not set\n"); | |
4102 | ||
4103 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4104 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4105 | if (WARN_ON(!encoder->base.crtc)) | |
4106 | return; | |
4107 | ||
4108 | crtc = encoder->base.crtc; | |
4109 | ||
4110 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4111 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4112 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4113 | "encoder active on the wrong pipe\n"); | |
4114 | } | |
79e53945 JB |
4115 | } |
4116 | ||
5ab432ef DV |
4117 | /* Even simpler default implementation, if there's really no special case to |
4118 | * consider. */ | |
4119 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4120 | { |
5ab432ef | 4121 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 4122 | |
5ab432ef DV |
4123 | /* All the simple cases only support two dpms states. */ |
4124 | if (mode != DRM_MODE_DPMS_ON) | |
4125 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4126 | |
5ab432ef DV |
4127 | if (mode == connector->dpms) |
4128 | return; | |
4129 | ||
4130 | connector->dpms = mode; | |
4131 | ||
4132 | /* Only need to change hw state when actually enabled */ | |
4133 | if (encoder->base.crtc) | |
4134 | intel_encoder_dpms(encoder, mode); | |
4135 | else | |
8af6cf88 | 4136 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 4137 | |
b980514c | 4138 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4139 | } |
4140 | ||
f0947c37 DV |
4141 | /* Simple connector->get_hw_state implementation for encoders that support only |
4142 | * one connector and no cloning and hence the encoder state determines the state | |
4143 | * of the connector. */ | |
4144 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4145 | { |
24929352 | 4146 | enum pipe pipe = 0; |
f0947c37 | 4147 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4148 | |
f0947c37 | 4149 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4150 | } |
4151 | ||
1857e1da DV |
4152 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4153 | struct intel_crtc_config *pipe_config) | |
4154 | { | |
4155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4156 | struct intel_crtc *pipe_B_crtc = | |
4157 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4158 | ||
4159 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4160 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4161 | if (pipe_config->fdi_lanes > 4) { | |
4162 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4163 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4164 | return false; | |
4165 | } | |
4166 | ||
4167 | if (IS_HASWELL(dev)) { | |
4168 | if (pipe_config->fdi_lanes > 2) { | |
4169 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4170 | pipe_config->fdi_lanes); | |
4171 | return false; | |
4172 | } else { | |
4173 | return true; | |
4174 | } | |
4175 | } | |
4176 | ||
4177 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4178 | return true; | |
4179 | ||
4180 | /* Ivybridge 3 pipe is really complicated */ | |
4181 | switch (pipe) { | |
4182 | case PIPE_A: | |
4183 | return true; | |
4184 | case PIPE_B: | |
4185 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4186 | pipe_config->fdi_lanes > 2) { | |
4187 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4188 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4189 | return false; | |
4190 | } | |
4191 | return true; | |
4192 | case PIPE_C: | |
1e833f40 | 4193 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4194 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4195 | if (pipe_config->fdi_lanes > 2) { | |
4196 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4197 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4198 | return false; | |
4199 | } | |
4200 | } else { | |
4201 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4202 | return false; | |
4203 | } | |
4204 | return true; | |
4205 | default: | |
4206 | BUG(); | |
4207 | } | |
4208 | } | |
4209 | ||
e29c22c0 DV |
4210 | #define RETRY 1 |
4211 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4212 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4213 | { |
1857e1da | 4214 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4215 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4216 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4217 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4218 | |
e29c22c0 | 4219 | retry: |
877d48d5 DV |
4220 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4221 | * each output octet as 10 bits. The actual frequency | |
4222 | * is stored as a divider into a 100MHz clock, and the | |
4223 | * mode pixel clock is stored in units of 1KHz. | |
4224 | * Hence the bw of each lane in terms of the mode signal | |
4225 | * is: | |
4226 | */ | |
4227 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4228 | ||
241bfc38 | 4229 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4230 | |
2bd89a07 | 4231 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4232 | pipe_config->pipe_bpp); |
4233 | ||
4234 | pipe_config->fdi_lanes = lane; | |
4235 | ||
2bd89a07 | 4236 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4237 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4238 | |
e29c22c0 DV |
4239 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4240 | intel_crtc->pipe, pipe_config); | |
4241 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4242 | pipe_config->pipe_bpp -= 2*3; | |
4243 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4244 | pipe_config->pipe_bpp); | |
4245 | needs_recompute = true; | |
4246 | pipe_config->bw_constrained = true; | |
4247 | ||
4248 | goto retry; | |
4249 | } | |
4250 | ||
4251 | if (needs_recompute) | |
4252 | return RETRY; | |
4253 | ||
4254 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4255 | } |
4256 | ||
42db64ef PZ |
4257 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4258 | struct intel_crtc_config *pipe_config) | |
4259 | { | |
3c4ca58c PZ |
4260 | pipe_config->ips_enabled = i915_enable_ips && |
4261 | hsw_crtc_supports_ips(crtc) && | |
b6dfdc9b | 4262 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4263 | } |
4264 | ||
a43f6e0f | 4265 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4266 | struct intel_crtc_config *pipe_config) |
79e53945 | 4267 | { |
a43f6e0f | 4268 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4269 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4270 | |
ad3a4479 | 4271 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4272 | if (INTEL_INFO(dev)->gen < 4) { |
4273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4274 | int clock_limit = | |
4275 | dev_priv->display.get_display_clock_speed(dev); | |
4276 | ||
4277 | /* | |
4278 | * Enable pixel doubling when the dot clock | |
4279 | * is > 90% of the (display) core speed. | |
4280 | * | |
b397c96b VS |
4281 | * GDG double wide on either pipe, |
4282 | * otherwise pipe A only. | |
cf532bb2 | 4283 | */ |
b397c96b | 4284 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4285 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4286 | clock_limit *= 2; |
cf532bb2 | 4287 | pipe_config->double_wide = true; |
ad3a4479 VS |
4288 | } |
4289 | ||
241bfc38 | 4290 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4291 | return -EINVAL; |
2c07245f | 4292 | } |
89749350 | 4293 | |
1d1d0e27 VS |
4294 | /* |
4295 | * Pipe horizontal size must be even in: | |
4296 | * - DVO ganged mode | |
4297 | * - LVDS dual channel mode | |
4298 | * - Double wide pipe | |
4299 | */ | |
4300 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4301 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4302 | pipe_config->pipe_src_w &= ~1; | |
4303 | ||
8693a824 DL |
4304 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4305 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4306 | */ |
4307 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4308 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4309 | return -EINVAL; |
44f46b42 | 4310 | |
bd080ee5 | 4311 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4312 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4313 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4314 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4315 | * for lvds. */ | |
4316 | pipe_config->pipe_bpp = 8*3; | |
4317 | } | |
4318 | ||
f5adf94e | 4319 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4320 | hsw_compute_ips_config(crtc, pipe_config); |
4321 | ||
4322 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4323 | * clock survives for now. */ | |
4324 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4325 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4326 | |
877d48d5 | 4327 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4328 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4329 | |
e29c22c0 | 4330 | return 0; |
79e53945 JB |
4331 | } |
4332 | ||
25eb05fc JB |
4333 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4334 | { | |
4335 | return 400000; /* FIXME */ | |
4336 | } | |
4337 | ||
e70236a8 JB |
4338 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4339 | { | |
4340 | return 400000; | |
4341 | } | |
79e53945 | 4342 | |
e70236a8 | 4343 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4344 | { |
e70236a8 JB |
4345 | return 333000; |
4346 | } | |
79e53945 | 4347 | |
e70236a8 JB |
4348 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4349 | { | |
4350 | return 200000; | |
4351 | } | |
79e53945 | 4352 | |
257a7ffc DV |
4353 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4354 | { | |
4355 | u16 gcfgc = 0; | |
4356 | ||
4357 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4358 | ||
4359 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4360 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4361 | return 267000; | |
4362 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4363 | return 333000; | |
4364 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4365 | return 444000; | |
4366 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4367 | return 200000; | |
4368 | default: | |
4369 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4370 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4371 | return 133000; | |
4372 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4373 | return 167000; | |
4374 | } | |
4375 | } | |
4376 | ||
e70236a8 JB |
4377 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4378 | { | |
4379 | u16 gcfgc = 0; | |
79e53945 | 4380 | |
e70236a8 JB |
4381 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4382 | ||
4383 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4384 | return 133000; | |
4385 | else { | |
4386 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4387 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4388 | return 333000; | |
4389 | default: | |
4390 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4391 | return 190000; | |
79e53945 | 4392 | } |
e70236a8 JB |
4393 | } |
4394 | } | |
4395 | ||
4396 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4397 | { | |
4398 | return 266000; | |
4399 | } | |
4400 | ||
4401 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4402 | { | |
4403 | u16 hpllcc = 0; | |
4404 | /* Assume that the hardware is in the high speed state. This | |
4405 | * should be the default. | |
4406 | */ | |
4407 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4408 | case GC_CLOCK_133_200: | |
4409 | case GC_CLOCK_100_200: | |
4410 | return 200000; | |
4411 | case GC_CLOCK_166_250: | |
4412 | return 250000; | |
4413 | case GC_CLOCK_100_133: | |
79e53945 | 4414 | return 133000; |
e70236a8 | 4415 | } |
79e53945 | 4416 | |
e70236a8 JB |
4417 | /* Shouldn't happen */ |
4418 | return 0; | |
4419 | } | |
79e53945 | 4420 | |
e70236a8 JB |
4421 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4422 | { | |
4423 | return 133000; | |
79e53945 JB |
4424 | } |
4425 | ||
2c07245f | 4426 | static void |
a65851af | 4427 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4428 | { |
a65851af VS |
4429 | while (*num > DATA_LINK_M_N_MASK || |
4430 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4431 | *num >>= 1; |
4432 | *den >>= 1; | |
4433 | } | |
4434 | } | |
4435 | ||
a65851af VS |
4436 | static void compute_m_n(unsigned int m, unsigned int n, |
4437 | uint32_t *ret_m, uint32_t *ret_n) | |
4438 | { | |
4439 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4440 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4441 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4442 | } | |
4443 | ||
e69d0bc1 DV |
4444 | void |
4445 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4446 | int pixel_clock, int link_clock, | |
4447 | struct intel_link_m_n *m_n) | |
2c07245f | 4448 | { |
e69d0bc1 | 4449 | m_n->tu = 64; |
a65851af VS |
4450 | |
4451 | compute_m_n(bits_per_pixel * pixel_clock, | |
4452 | link_clock * nlanes * 8, | |
4453 | &m_n->gmch_m, &m_n->gmch_n); | |
4454 | ||
4455 | compute_m_n(pixel_clock, link_clock, | |
4456 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4457 | } |
4458 | ||
a7615030 CW |
4459 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4460 | { | |
72bbe58c KP |
4461 | if (i915_panel_use_ssc >= 0) |
4462 | return i915_panel_use_ssc != 0; | |
41aa3448 | 4463 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4464 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4465 | } |
4466 | ||
c65d77d8 JB |
4467 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4468 | { | |
4469 | struct drm_device *dev = crtc->dev; | |
4470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4471 | int refclk; | |
4472 | ||
a0c4da24 | 4473 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4474 | refclk = 100000; |
a0c4da24 | 4475 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4476 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
41aa3448 | 4477 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
c65d77d8 JB |
4478 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4479 | refclk / 1000); | |
4480 | } else if (!IS_GEN2(dev)) { | |
4481 | refclk = 96000; | |
4482 | } else { | |
4483 | refclk = 48000; | |
4484 | } | |
4485 | ||
4486 | return refclk; | |
4487 | } | |
4488 | ||
7429e9d4 | 4489 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4490 | { |
7df00d7a | 4491 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4492 | } |
f47709a9 | 4493 | |
7429e9d4 DV |
4494 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4495 | { | |
4496 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4497 | } |
4498 | ||
f47709a9 | 4499 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4500 | intel_clock_t *reduced_clock) |
4501 | { | |
f47709a9 | 4502 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4503 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4504 | int pipe = crtc->pipe; |
a7516a05 JB |
4505 | u32 fp, fp2 = 0; |
4506 | ||
4507 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4508 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4509 | if (reduced_clock) |
7429e9d4 | 4510 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4511 | } else { |
7429e9d4 | 4512 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4513 | if (reduced_clock) |
7429e9d4 | 4514 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4515 | } |
4516 | ||
4517 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4518 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4519 | |
f47709a9 DV |
4520 | crtc->lowfreq_avail = false; |
4521 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4522 | reduced_clock && i915_powersave) { |
4523 | I915_WRITE(FP1(pipe), fp2); | |
8bcc2795 | 4524 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4525 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4526 | } else { |
4527 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4528 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4529 | } |
4530 | } | |
4531 | ||
5e69f97f CML |
4532 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4533 | pipe) | |
89b667f8 JB |
4534 | { |
4535 | u32 reg_val; | |
4536 | ||
4537 | /* | |
4538 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4539 | * and set it to a reasonable value instead. | |
4540 | */ | |
5e69f97f | 4541 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1)); |
89b667f8 JB |
4542 | reg_val &= 0xffffff00; |
4543 | reg_val |= 0x00000030; | |
5e69f97f | 4544 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val); |
89b667f8 | 4545 | |
5e69f97f | 4546 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION); |
89b667f8 JB |
4547 | reg_val &= 0x8cffffff; |
4548 | reg_val = 0x8c000000; | |
5e69f97f | 4549 | vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val); |
89b667f8 | 4550 | |
5e69f97f | 4551 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1)); |
89b667f8 | 4552 | reg_val &= 0xffffff00; |
5e69f97f | 4553 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val); |
89b667f8 | 4554 | |
5e69f97f | 4555 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION); |
89b667f8 JB |
4556 | reg_val &= 0x00ffffff; |
4557 | reg_val |= 0xb0000000; | |
5e69f97f | 4558 | vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val); |
89b667f8 JB |
4559 | } |
4560 | ||
b551842d DV |
4561 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4562 | struct intel_link_m_n *m_n) | |
4563 | { | |
4564 | struct drm_device *dev = crtc->base.dev; | |
4565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4566 | int pipe = crtc->pipe; | |
4567 | ||
e3b95f1e DV |
4568 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4569 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4570 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4571 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4572 | } |
4573 | ||
4574 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4575 | struct intel_link_m_n *m_n) | |
4576 | { | |
4577 | struct drm_device *dev = crtc->base.dev; | |
4578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4579 | int pipe = crtc->pipe; | |
4580 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4581 | ||
4582 | if (INTEL_INFO(dev)->gen >= 5) { | |
4583 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4584 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4585 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4586 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4587 | } else { | |
e3b95f1e DV |
4588 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4589 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4590 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4591 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4592 | } |
4593 | } | |
4594 | ||
03afc4a2 DV |
4595 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4596 | { | |
4597 | if (crtc->config.has_pch_encoder) | |
4598 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4599 | else | |
4600 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4601 | } | |
4602 | ||
f47709a9 | 4603 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4604 | { |
f47709a9 | 4605 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4606 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4607 | int pipe = crtc->pipe; |
89b667f8 | 4608 | u32 dpll, mdiv; |
a0c4da24 | 4609 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4610 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4611 | |
09153000 DV |
4612 | mutex_lock(&dev_priv->dpio_lock); |
4613 | ||
f47709a9 DV |
4614 | bestn = crtc->config.dpll.n; |
4615 | bestm1 = crtc->config.dpll.m1; | |
4616 | bestm2 = crtc->config.dpll.m2; | |
4617 | bestp1 = crtc->config.dpll.p1; | |
4618 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4619 | |
89b667f8 JB |
4620 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4621 | ||
4622 | /* PLL B needs special handling */ | |
4623 | if (pipe) | |
5e69f97f | 4624 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4625 | |
4626 | /* Set up Tx target for periodic Rcomp update */ | |
5e69f97f | 4627 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f); |
89b667f8 JB |
4628 | |
4629 | /* Disable target IRef on PLL */ | |
5e69f97f | 4630 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe)); |
89b667f8 | 4631 | reg_val &= 0x00ffffff; |
5e69f97f | 4632 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val); |
89b667f8 JB |
4633 | |
4634 | /* Disable fast lock */ | |
5e69f97f | 4635 | vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610); |
89b667f8 JB |
4636 | |
4637 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4638 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4639 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4640 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4641 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4642 | |
4643 | /* | |
4644 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4645 | * but we don't support that). | |
4646 | * Note: don't use the DAC post divider as it seems unstable. | |
4647 | */ | |
4648 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
5e69f97f | 4649 | vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv); |
a0c4da24 | 4650 | |
a0c4da24 | 4651 | mdiv |= DPIO_ENABLE_CALIBRATION; |
5e69f97f | 4652 | vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv); |
a0c4da24 | 4653 | |
89b667f8 | 4654 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4655 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4656 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4657 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
5e69f97f | 4658 | vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe), |
885b0120 | 4659 | 0x009f0003); |
89b667f8 | 4660 | else |
5e69f97f | 4661 | vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe), |
89b667f8 JB |
4662 | 0x00d0000f); |
4663 | ||
4664 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4665 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4666 | /* Use SSC source */ | |
4667 | if (!pipe) | |
5e69f97f | 4668 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4669 | 0x0df40000); |
4670 | else | |
5e69f97f | 4671 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4672 | 0x0df70000); |
4673 | } else { /* HDMI or VGA */ | |
4674 | /* Use bend source */ | |
4675 | if (!pipe) | |
5e69f97f | 4676 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4677 | 0x0df70000); |
4678 | else | |
5e69f97f | 4679 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4680 | 0x0df40000); |
4681 | } | |
a0c4da24 | 4682 | |
5e69f97f | 4683 | coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe)); |
89b667f8 JB |
4684 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4685 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
4686 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
4687 | coreclk |= 0x01000000; | |
5e69f97f | 4688 | vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk); |
a0c4da24 | 4689 | |
5e69f97f | 4690 | vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000); |
a0c4da24 | 4691 | |
89b667f8 JB |
4692 | /* Enable DPIO clock input */ |
4693 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4694 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
4695 | /* We should never disable this, set it here for state tracking */ |
4696 | if (pipe == PIPE_B) | |
89b667f8 | 4697 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 4698 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
4699 | crtc->config.dpll_hw_state.dpll = dpll; |
4700 | ||
ef1b460d DV |
4701 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4702 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
4703 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4704 | ||
89b667f8 JB |
4705 | if (crtc->config.has_dp_encoder) |
4706 | intel_dp_set_m_n(crtc); | |
09153000 DV |
4707 | |
4708 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4709 | } |
4710 | ||
f47709a9 DV |
4711 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4712 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
4713 | int num_connectors) |
4714 | { | |
f47709a9 | 4715 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4716 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
4717 | u32 dpll; |
4718 | bool is_sdvo; | |
f47709a9 | 4719 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4720 | |
f47709a9 | 4721 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4722 | |
f47709a9 DV |
4723 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4724 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
4725 | |
4726 | dpll = DPLL_VGA_MODE_DIS; | |
4727 | ||
f47709a9 | 4728 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
4729 | dpll |= DPLLB_MODE_LVDS; |
4730 | else | |
4731 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 4732 | |
ef1b460d | 4733 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
4734 | dpll |= (crtc->config.pixel_multiplier - 1) |
4735 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 4736 | } |
198a037f DV |
4737 | |
4738 | if (is_sdvo) | |
4a33e48d | 4739 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 4740 | |
f47709a9 | 4741 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 4742 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
4743 | |
4744 | /* compute bitmask from p1 value */ | |
4745 | if (IS_PINEVIEW(dev)) | |
4746 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4747 | else { | |
4748 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4749 | if (IS_G4X(dev) && reduced_clock) | |
4750 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4751 | } | |
4752 | switch (clock->p2) { | |
4753 | case 5: | |
4754 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4755 | break; | |
4756 | case 7: | |
4757 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4758 | break; | |
4759 | case 10: | |
4760 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4761 | break; | |
4762 | case 14: | |
4763 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4764 | break; | |
4765 | } | |
4766 | if (INTEL_INFO(dev)->gen >= 4) | |
4767 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4768 | ||
09ede541 | 4769 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 4770 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 4771 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4772 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4773 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4774 | else | |
4775 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4776 | ||
4777 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
4778 | crtc->config.dpll_hw_state.dpll = dpll; |
4779 | ||
eb1cbe48 | 4780 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
4781 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
4782 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 4783 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 4784 | } |
66e3d5c0 DV |
4785 | |
4786 | if (crtc->config.has_dp_encoder) | |
4787 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
4788 | } |
4789 | ||
f47709a9 | 4790 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 4791 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4792 | int num_connectors) |
4793 | { | |
f47709a9 | 4794 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4795 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 4796 | u32 dpll; |
f47709a9 | 4797 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4798 | |
f47709a9 | 4799 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4800 | |
eb1cbe48 DV |
4801 | dpll = DPLL_VGA_MODE_DIS; |
4802 | ||
f47709a9 | 4803 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
4804 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4805 | } else { | |
4806 | if (clock->p1 == 2) | |
4807 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4808 | else | |
4809 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4810 | if (clock->p2 == 4) | |
4811 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4812 | } | |
4813 | ||
4a33e48d DV |
4814 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4815 | dpll |= DPLL_DVO_2X_MODE; | |
4816 | ||
f47709a9 | 4817 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4818 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4819 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4820 | else | |
4821 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4822 | ||
4823 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 4824 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
4825 | } |
4826 | ||
8a654f3b | 4827 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
4828 | { |
4829 | struct drm_device *dev = intel_crtc->base.dev; | |
4830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4831 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 4832 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
4833 | struct drm_display_mode *adjusted_mode = |
4834 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
4835 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4836 | ||
4837 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
4838 | * the hw state checker will get angry at the mismatch. */ | |
4839 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
4840 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
4841 | |
4842 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4843 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
4844 | crtc_vtotal -= 1; |
4845 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
4846 | vsyncshift = adjusted_mode->crtc_hsync_start |
4847 | - adjusted_mode->crtc_htotal / 2; | |
4848 | } else { | |
4849 | vsyncshift = 0; | |
4850 | } | |
4851 | ||
4852 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4853 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4854 | |
fe2b8f9d | 4855 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4856 | (adjusted_mode->crtc_hdisplay - 1) | |
4857 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4858 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4859 | (adjusted_mode->crtc_hblank_start - 1) | |
4860 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4861 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4862 | (adjusted_mode->crtc_hsync_start - 1) | |
4863 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4864 | ||
fe2b8f9d | 4865 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 4866 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 4867 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 4868 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 4869 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 4870 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 4871 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4872 | (adjusted_mode->crtc_vsync_start - 1) | |
4873 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4874 | ||
b5e508d4 PZ |
4875 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4876 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4877 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4878 | * bits. */ | |
4879 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4880 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4881 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4882 | ||
b0e77b9c PZ |
4883 | /* pipesrc controls the size that is scaled from, which should |
4884 | * always be the user's requested size. | |
4885 | */ | |
4886 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
4887 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
4888 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
4889 | } |
4890 | ||
1bd1bd80 DV |
4891 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4892 | struct intel_crtc_config *pipe_config) | |
4893 | { | |
4894 | struct drm_device *dev = crtc->base.dev; | |
4895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4896 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
4897 | uint32_t tmp; | |
4898 | ||
4899 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
4900 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
4901 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
4902 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
4903 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
4904 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4905 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
4906 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
4907 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4908 | ||
4909 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
4910 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
4911 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
4912 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
4913 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
4914 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4915 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
4916 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
4917 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4918 | ||
4919 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
4920 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
4921 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
4922 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
4923 | } | |
4924 | ||
4925 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
4926 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
4927 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
4928 | ||
4929 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
4930 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
4931 | } |
4932 | ||
babea61d JB |
4933 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
4934 | struct intel_crtc_config *pipe_config) | |
4935 | { | |
4936 | struct drm_crtc *crtc = &intel_crtc->base; | |
4937 | ||
4938 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
4939 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
4940 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
4941 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
4942 | ||
4943 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
4944 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
4945 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
4946 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
4947 | ||
4948 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
4949 | ||
241bfc38 | 4950 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
babea61d JB |
4951 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
4952 | } | |
4953 | ||
84b046f3 DV |
4954 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4955 | { | |
4956 | struct drm_device *dev = intel_crtc->base.dev; | |
4957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4958 | uint32_t pipeconf; | |
4959 | ||
9f11a9e4 | 4960 | pipeconf = 0; |
84b046f3 | 4961 | |
67c72a12 DV |
4962 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4963 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
4964 | pipeconf |= PIPECONF_ENABLE; | |
4965 | ||
cf532bb2 VS |
4966 | if (intel_crtc->config.double_wide) |
4967 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 4968 | |
ff9ce46e DV |
4969 | /* only g4x and later have fancy bpc/dither controls */ |
4970 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
4971 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
4972 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
4973 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 4974 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 4975 | |
ff9ce46e DV |
4976 | switch (intel_crtc->config.pipe_bpp) { |
4977 | case 18: | |
4978 | pipeconf |= PIPECONF_6BPC; | |
4979 | break; | |
4980 | case 24: | |
4981 | pipeconf |= PIPECONF_8BPC; | |
4982 | break; | |
4983 | case 30: | |
4984 | pipeconf |= PIPECONF_10BPC; | |
4985 | break; | |
4986 | default: | |
4987 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
4988 | BUG(); | |
84b046f3 DV |
4989 | } |
4990 | } | |
4991 | ||
4992 | if (HAS_PIPE_CXSR(dev)) { | |
4993 | if (intel_crtc->lowfreq_avail) { | |
4994 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
4995 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
4996 | } else { | |
4997 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
4998 | } |
4999 | } | |
5000 | ||
84b046f3 DV |
5001 | if (!IS_GEN2(dev) && |
5002 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5003 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5004 | else | |
5005 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5006 | ||
9f11a9e4 DV |
5007 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5008 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5009 | |
84b046f3 DV |
5010 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5011 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5012 | } | |
5013 | ||
f564048e | 5014 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5015 | int x, int y, |
94352cf9 | 5016 | struct drm_framebuffer *fb) |
79e53945 JB |
5017 | { |
5018 | struct drm_device *dev = crtc->dev; | |
5019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5021 | int pipe = intel_crtc->pipe; | |
80824003 | 5022 | int plane = intel_crtc->plane; |
c751ce4f | 5023 | int refclk, num_connectors = 0; |
652c393a | 5024 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5025 | u32 dspcntr; |
a16af721 | 5026 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5027 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5028 | struct intel_encoder *encoder; |
d4906093 | 5029 | const intel_limit_t *limit; |
5c3b82e2 | 5030 | int ret; |
79e53945 | 5031 | |
6c2b7c12 | 5032 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5033 | switch (encoder->type) { |
79e53945 JB |
5034 | case INTEL_OUTPUT_LVDS: |
5035 | is_lvds = true; | |
5036 | break; | |
e9fd1c02 JN |
5037 | case INTEL_OUTPUT_DSI: |
5038 | is_dsi = true; | |
5039 | break; | |
79e53945 | 5040 | } |
43565a06 | 5041 | |
c751ce4f | 5042 | num_connectors++; |
79e53945 JB |
5043 | } |
5044 | ||
f2335330 JN |
5045 | if (is_dsi) |
5046 | goto skip_dpll; | |
5047 | ||
5048 | if (!intel_crtc->config.clock_set) { | |
5049 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5050 | |
e9fd1c02 JN |
5051 | /* |
5052 | * Returns a set of divisors for the desired target clock with | |
5053 | * the given refclk, or FALSE. The returned values represent | |
5054 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5055 | * 2) / p1 / p2. | |
5056 | */ | |
5057 | limit = intel_limit(crtc, refclk); | |
5058 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5059 | intel_crtc->config.port_clock, | |
5060 | refclk, NULL, &clock); | |
f2335330 | 5061 | if (!ok) { |
e9fd1c02 JN |
5062 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5063 | return -EINVAL; | |
5064 | } | |
79e53945 | 5065 | |
f2335330 JN |
5066 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5067 | /* | |
5068 | * Ensure we match the reduced clock's P to the target | |
5069 | * clock. If the clocks don't match, we can't switch | |
5070 | * the display clock by using the FP0/FP1. In such case | |
5071 | * we will disable the LVDS downclock feature. | |
5072 | */ | |
5073 | has_reduced_clock = | |
5074 | dev_priv->display.find_dpll(limit, crtc, | |
5075 | dev_priv->lvds_downclock, | |
5076 | refclk, &clock, | |
5077 | &reduced_clock); | |
5078 | } | |
5079 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5080 | intel_crtc->config.dpll.n = clock.n; |
5081 | intel_crtc->config.dpll.m1 = clock.m1; | |
5082 | intel_crtc->config.dpll.m2 = clock.m2; | |
5083 | intel_crtc->config.dpll.p1 = clock.p1; | |
5084 | intel_crtc->config.dpll.p2 = clock.p2; | |
5085 | } | |
7026d4ac | 5086 | |
e9fd1c02 | 5087 | if (IS_GEN2(dev)) { |
8a654f3b | 5088 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5089 | has_reduced_clock ? &reduced_clock : NULL, |
5090 | num_connectors); | |
e9fd1c02 | 5091 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5092 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5093 | } else { |
f47709a9 | 5094 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5095 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5096 | num_connectors); |
e9fd1c02 | 5097 | } |
79e53945 | 5098 | |
f2335330 | 5099 | skip_dpll: |
79e53945 JB |
5100 | /* Set up the display plane register */ |
5101 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5102 | ||
da6ecc5d JB |
5103 | if (!IS_VALLEYVIEW(dev)) { |
5104 | if (pipe == 0) | |
5105 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5106 | else | |
5107 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5108 | } | |
79e53945 | 5109 | |
8a654f3b | 5110 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5111 | |
5112 | /* pipesrc and dspsize control the size that is scaled from, | |
5113 | * which should always be the user's requested size. | |
79e53945 | 5114 | */ |
929c77fb | 5115 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5116 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5117 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5118 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5119 | |
84b046f3 DV |
5120 | i9xx_set_pipeconf(intel_crtc); |
5121 | ||
f564048e EA |
5122 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5123 | POSTING_READ(DSPCNTR(plane)); | |
5124 | ||
94352cf9 | 5125 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5126 | |
f564048e EA |
5127 | return ret; |
5128 | } | |
5129 | ||
2fa2fe9a DV |
5130 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5131 | struct intel_crtc_config *pipe_config) | |
5132 | { | |
5133 | struct drm_device *dev = crtc->base.dev; | |
5134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5135 | uint32_t tmp; | |
5136 | ||
5137 | tmp = I915_READ(PFIT_CONTROL); | |
06922821 DV |
5138 | if (!(tmp & PFIT_ENABLE)) |
5139 | return; | |
2fa2fe9a | 5140 | |
06922821 | 5141 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5142 | if (INTEL_INFO(dev)->gen < 4) { |
5143 | if (crtc->pipe != PIPE_B) | |
5144 | return; | |
2fa2fe9a DV |
5145 | } else { |
5146 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5147 | return; | |
5148 | } | |
5149 | ||
06922821 | 5150 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5151 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5152 | if (INTEL_INFO(dev)->gen < 5) | |
5153 | pipe_config->gmch_pfit.lvds_border_bits = | |
5154 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5155 | } | |
5156 | ||
acbec814 JB |
5157 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5158 | struct intel_crtc_config *pipe_config) | |
5159 | { | |
5160 | struct drm_device *dev = crtc->base.dev; | |
5161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5162 | int pipe = pipe_config->cpu_transcoder; | |
5163 | intel_clock_t clock; | |
5164 | u32 mdiv; | |
662c6ecb | 5165 | int refclk = 100000; |
acbec814 JB |
5166 | |
5167 | mutex_lock(&dev_priv->dpio_lock); | |
5168 | mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe)); | |
5169 | mutex_unlock(&dev_priv->dpio_lock); | |
5170 | ||
5171 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5172 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5173 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5174 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5175 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5176 | ||
662c6ecb CW |
5177 | clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
5178 | clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); | |
acbec814 JB |
5179 | |
5180 | pipe_config->port_clock = clock.dot / 10; | |
5181 | } | |
5182 | ||
0e8ffe1b DV |
5183 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5184 | struct intel_crtc_config *pipe_config) | |
5185 | { | |
5186 | struct drm_device *dev = crtc->base.dev; | |
5187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5188 | uint32_t tmp; | |
5189 | ||
e143a21c | 5190 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5191 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5192 | |
0e8ffe1b DV |
5193 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5194 | if (!(tmp & PIPECONF_ENABLE)) | |
5195 | return false; | |
5196 | ||
42571aef VS |
5197 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5198 | switch (tmp & PIPECONF_BPC_MASK) { | |
5199 | case PIPECONF_6BPC: | |
5200 | pipe_config->pipe_bpp = 18; | |
5201 | break; | |
5202 | case PIPECONF_8BPC: | |
5203 | pipe_config->pipe_bpp = 24; | |
5204 | break; | |
5205 | case PIPECONF_10BPC: | |
5206 | pipe_config->pipe_bpp = 30; | |
5207 | break; | |
5208 | default: | |
5209 | break; | |
5210 | } | |
5211 | } | |
5212 | ||
282740f7 VS |
5213 | if (INTEL_INFO(dev)->gen < 4) |
5214 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5215 | ||
1bd1bd80 DV |
5216 | intel_get_pipe_timings(crtc, pipe_config); |
5217 | ||
2fa2fe9a DV |
5218 | i9xx_get_pfit_config(crtc, pipe_config); |
5219 | ||
6c49f241 DV |
5220 | if (INTEL_INFO(dev)->gen >= 4) { |
5221 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5222 | pipe_config->pixel_multiplier = | |
5223 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5224 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5225 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5226 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5227 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5228 | pipe_config->pixel_multiplier = | |
5229 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5230 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5231 | } else { | |
5232 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5233 | * port and will be fixed up in the encoder->get_config | |
5234 | * function. */ | |
5235 | pipe_config->pixel_multiplier = 1; | |
5236 | } | |
8bcc2795 DV |
5237 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5238 | if (!IS_VALLEYVIEW(dev)) { | |
5239 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5240 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5241 | } else { |
5242 | /* Mask out read-only status bits. */ | |
5243 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5244 | DPLL_PORTC_READY_MASK | | |
5245 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5246 | } |
6c49f241 | 5247 | |
acbec814 JB |
5248 | if (IS_VALLEYVIEW(dev)) |
5249 | vlv_crtc_clock_get(crtc, pipe_config); | |
5250 | else | |
5251 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5252 | |
0e8ffe1b DV |
5253 | return true; |
5254 | } | |
5255 | ||
dde86e2d | 5256 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5257 | { |
5258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5259 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5260 | struct intel_encoder *encoder; |
74cfd7ac | 5261 | u32 val, final; |
13d83a67 | 5262 | bool has_lvds = false; |
199e5d79 | 5263 | bool has_cpu_edp = false; |
199e5d79 | 5264 | bool has_panel = false; |
99eb6a01 KP |
5265 | bool has_ck505 = false; |
5266 | bool can_ssc = false; | |
13d83a67 JB |
5267 | |
5268 | /* We need to take the global config into account */ | |
199e5d79 KP |
5269 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5270 | base.head) { | |
5271 | switch (encoder->type) { | |
5272 | case INTEL_OUTPUT_LVDS: | |
5273 | has_panel = true; | |
5274 | has_lvds = true; | |
5275 | break; | |
5276 | case INTEL_OUTPUT_EDP: | |
5277 | has_panel = true; | |
2de6905f | 5278 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5279 | has_cpu_edp = true; |
5280 | break; | |
13d83a67 JB |
5281 | } |
5282 | } | |
5283 | ||
99eb6a01 | 5284 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5285 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5286 | can_ssc = has_ck505; |
5287 | } else { | |
5288 | has_ck505 = false; | |
5289 | can_ssc = true; | |
5290 | } | |
5291 | ||
2de6905f ID |
5292 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5293 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5294 | |
5295 | /* Ironlake: try to setup display ref clock before DPLL | |
5296 | * enabling. This is only under driver's control after | |
5297 | * PCH B stepping, previous chipset stepping should be | |
5298 | * ignoring this setting. | |
5299 | */ | |
74cfd7ac CW |
5300 | val = I915_READ(PCH_DREF_CONTROL); |
5301 | ||
5302 | /* As we must carefully and slowly disable/enable each source in turn, | |
5303 | * compute the final state we want first and check if we need to | |
5304 | * make any changes at all. | |
5305 | */ | |
5306 | final = val; | |
5307 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5308 | if (has_ck505) | |
5309 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5310 | else | |
5311 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5312 | ||
5313 | final &= ~DREF_SSC_SOURCE_MASK; | |
5314 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5315 | final &= ~DREF_SSC1_ENABLE; | |
5316 | ||
5317 | if (has_panel) { | |
5318 | final |= DREF_SSC_SOURCE_ENABLE; | |
5319 | ||
5320 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5321 | final |= DREF_SSC1_ENABLE; | |
5322 | ||
5323 | if (has_cpu_edp) { | |
5324 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5325 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5326 | else | |
5327 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5328 | } else | |
5329 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5330 | } else { | |
5331 | final |= DREF_SSC_SOURCE_DISABLE; | |
5332 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5333 | } | |
5334 | ||
5335 | if (final == val) | |
5336 | return; | |
5337 | ||
13d83a67 | 5338 | /* Always enable nonspread source */ |
74cfd7ac | 5339 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5340 | |
99eb6a01 | 5341 | if (has_ck505) |
74cfd7ac | 5342 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5343 | else |
74cfd7ac | 5344 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5345 | |
199e5d79 | 5346 | if (has_panel) { |
74cfd7ac CW |
5347 | val &= ~DREF_SSC_SOURCE_MASK; |
5348 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5349 | |
199e5d79 | 5350 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5351 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5352 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5353 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5354 | } else |
74cfd7ac | 5355 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5356 | |
5357 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5358 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5359 | POSTING_READ(PCH_DREF_CONTROL); |
5360 | udelay(200); | |
5361 | ||
74cfd7ac | 5362 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5363 | |
5364 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5365 | if (has_cpu_edp) { |
99eb6a01 | 5366 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5367 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5368 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5369 | } |
13d83a67 | 5370 | else |
74cfd7ac | 5371 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5372 | } else |
74cfd7ac | 5373 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5374 | |
74cfd7ac | 5375 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5376 | POSTING_READ(PCH_DREF_CONTROL); |
5377 | udelay(200); | |
5378 | } else { | |
5379 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5380 | ||
74cfd7ac | 5381 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5382 | |
5383 | /* Turn off CPU output */ | |
74cfd7ac | 5384 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5385 | |
74cfd7ac | 5386 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5387 | POSTING_READ(PCH_DREF_CONTROL); |
5388 | udelay(200); | |
5389 | ||
5390 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5391 | val &= ~DREF_SSC_SOURCE_MASK; |
5392 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5393 | |
5394 | /* Turn off SSC1 */ | |
74cfd7ac | 5395 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5396 | |
74cfd7ac | 5397 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5398 | POSTING_READ(PCH_DREF_CONTROL); |
5399 | udelay(200); | |
5400 | } | |
74cfd7ac CW |
5401 | |
5402 | BUG_ON(val != final); | |
13d83a67 JB |
5403 | } |
5404 | ||
f31f2d55 | 5405 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5406 | { |
f31f2d55 | 5407 | uint32_t tmp; |
dde86e2d | 5408 | |
0ff066a9 PZ |
5409 | tmp = I915_READ(SOUTH_CHICKEN2); |
5410 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5411 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5412 | |
0ff066a9 PZ |
5413 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5414 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5415 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5416 | |
0ff066a9 PZ |
5417 | tmp = I915_READ(SOUTH_CHICKEN2); |
5418 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5419 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5420 | |
0ff066a9 PZ |
5421 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5422 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5423 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5424 | } |
5425 | ||
5426 | /* WaMPhyProgramming:hsw */ | |
5427 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5428 | { | |
5429 | uint32_t tmp; | |
dde86e2d PZ |
5430 | |
5431 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5432 | tmp &= ~(0xFF << 24); | |
5433 | tmp |= (0x12 << 24); | |
5434 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5435 | ||
dde86e2d PZ |
5436 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5437 | tmp |= (1 << 11); | |
5438 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5439 | ||
5440 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5441 | tmp |= (1 << 11); | |
5442 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5443 | ||
dde86e2d PZ |
5444 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5445 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5446 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5447 | ||
5448 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5449 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5450 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5451 | ||
0ff066a9 PZ |
5452 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5453 | tmp &= ~(7 << 13); | |
5454 | tmp |= (5 << 13); | |
5455 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5456 | |
0ff066a9 PZ |
5457 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5458 | tmp &= ~(7 << 13); | |
5459 | tmp |= (5 << 13); | |
5460 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5461 | |
5462 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5463 | tmp &= ~0xFF; | |
5464 | tmp |= 0x1C; | |
5465 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5466 | ||
5467 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5468 | tmp &= ~0xFF; | |
5469 | tmp |= 0x1C; | |
5470 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5471 | ||
5472 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5473 | tmp &= ~(0xFF << 16); | |
5474 | tmp |= (0x1C << 16); | |
5475 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5476 | ||
5477 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5478 | tmp &= ~(0xFF << 16); | |
5479 | tmp |= (0x1C << 16); | |
5480 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5481 | ||
0ff066a9 PZ |
5482 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5483 | tmp |= (1 << 27); | |
5484 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5485 | |
0ff066a9 PZ |
5486 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5487 | tmp |= (1 << 27); | |
5488 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5489 | |
0ff066a9 PZ |
5490 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5491 | tmp &= ~(0xF << 28); | |
5492 | tmp |= (4 << 28); | |
5493 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5494 | |
0ff066a9 PZ |
5495 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5496 | tmp &= ~(0xF << 28); | |
5497 | tmp |= (4 << 28); | |
5498 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5499 | } |
5500 | ||
2fa86a1f PZ |
5501 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5502 | * Programming" based on the parameters passed: | |
5503 | * - Sequence to enable CLKOUT_DP | |
5504 | * - Sequence to enable CLKOUT_DP without spread | |
5505 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5506 | */ | |
5507 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5508 | bool with_fdi) | |
f31f2d55 PZ |
5509 | { |
5510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5511 | uint32_t reg, tmp; |
5512 | ||
5513 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5514 | with_spread = true; | |
5515 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5516 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5517 | with_fdi = false; | |
f31f2d55 PZ |
5518 | |
5519 | mutex_lock(&dev_priv->dpio_lock); | |
5520 | ||
5521 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5522 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5523 | tmp |= SBI_SSCCTL_PATHALT; | |
5524 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5525 | ||
5526 | udelay(24); | |
5527 | ||
2fa86a1f PZ |
5528 | if (with_spread) { |
5529 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5530 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5531 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5532 | |
2fa86a1f PZ |
5533 | if (with_fdi) { |
5534 | lpt_reset_fdi_mphy(dev_priv); | |
5535 | lpt_program_fdi_mphy(dev_priv); | |
5536 | } | |
5537 | } | |
dde86e2d | 5538 | |
2fa86a1f PZ |
5539 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5540 | SBI_GEN0 : SBI_DBUFF0; | |
5541 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5542 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5543 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5544 | |
5545 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5546 | } |
5547 | ||
47701c3b PZ |
5548 | /* Sequence to disable CLKOUT_DP */ |
5549 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5550 | { | |
5551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5552 | uint32_t reg, tmp; | |
5553 | ||
5554 | mutex_lock(&dev_priv->dpio_lock); | |
5555 | ||
5556 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5557 | SBI_GEN0 : SBI_DBUFF0; | |
5558 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5559 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5560 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5561 | ||
5562 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5563 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5564 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5565 | tmp |= SBI_SSCCTL_PATHALT; | |
5566 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5567 | udelay(32); | |
5568 | } | |
5569 | tmp |= SBI_SSCCTL_DISABLE; | |
5570 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5571 | } | |
5572 | ||
5573 | mutex_unlock(&dev_priv->dpio_lock); | |
5574 | } | |
5575 | ||
bf8fa3d3 PZ |
5576 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5577 | { | |
5578 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5579 | struct intel_encoder *encoder; | |
5580 | bool has_vga = false; | |
5581 | ||
5582 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5583 | switch (encoder->type) { | |
5584 | case INTEL_OUTPUT_ANALOG: | |
5585 | has_vga = true; | |
5586 | break; | |
5587 | } | |
5588 | } | |
5589 | ||
47701c3b PZ |
5590 | if (has_vga) |
5591 | lpt_enable_clkout_dp(dev, true, true); | |
5592 | else | |
5593 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5594 | } |
5595 | ||
dde86e2d PZ |
5596 | /* |
5597 | * Initialize reference clocks when the driver loads | |
5598 | */ | |
5599 | void intel_init_pch_refclk(struct drm_device *dev) | |
5600 | { | |
5601 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5602 | ironlake_init_pch_refclk(dev); | |
5603 | else if (HAS_PCH_LPT(dev)) | |
5604 | lpt_init_pch_refclk(dev); | |
5605 | } | |
5606 | ||
d9d444cb JB |
5607 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5608 | { | |
5609 | struct drm_device *dev = crtc->dev; | |
5610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5611 | struct intel_encoder *encoder; | |
d9d444cb JB |
5612 | int num_connectors = 0; |
5613 | bool is_lvds = false; | |
5614 | ||
6c2b7c12 | 5615 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5616 | switch (encoder->type) { |
5617 | case INTEL_OUTPUT_LVDS: | |
5618 | is_lvds = true; | |
5619 | break; | |
d9d444cb JB |
5620 | } |
5621 | num_connectors++; | |
5622 | } | |
5623 | ||
5624 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5625 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
41aa3448 RV |
5626 | dev_priv->vbt.lvds_ssc_freq); |
5627 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
d9d444cb JB |
5628 | } |
5629 | ||
5630 | return 120000; | |
5631 | } | |
5632 | ||
6ff93609 | 5633 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5634 | { |
c8203565 | 5635 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5637 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5638 | uint32_t val; |
5639 | ||
78114071 | 5640 | val = 0; |
c8203565 | 5641 | |
965e0c48 | 5642 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5643 | case 18: |
dfd07d72 | 5644 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5645 | break; |
5646 | case 24: | |
dfd07d72 | 5647 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5648 | break; |
5649 | case 30: | |
dfd07d72 | 5650 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5651 | break; |
5652 | case 36: | |
dfd07d72 | 5653 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5654 | break; |
5655 | default: | |
cc769b62 PZ |
5656 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5657 | BUG(); | |
c8203565 PZ |
5658 | } |
5659 | ||
d8b32247 | 5660 | if (intel_crtc->config.dither) |
c8203565 PZ |
5661 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5662 | ||
6ff93609 | 5663 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5664 | val |= PIPECONF_INTERLACED_ILK; |
5665 | else | |
5666 | val |= PIPECONF_PROGRESSIVE; | |
5667 | ||
50f3b016 | 5668 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 5669 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 5670 | |
c8203565 PZ |
5671 | I915_WRITE(PIPECONF(pipe), val); |
5672 | POSTING_READ(PIPECONF(pipe)); | |
5673 | } | |
5674 | ||
86d3efce VS |
5675 | /* |
5676 | * Set up the pipe CSC unit. | |
5677 | * | |
5678 | * Currently only full range RGB to limited range RGB conversion | |
5679 | * is supported, but eventually this should handle various | |
5680 | * RGB<->YCbCr scenarios as well. | |
5681 | */ | |
50f3b016 | 5682 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5683 | { |
5684 | struct drm_device *dev = crtc->dev; | |
5685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5686 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5687 | int pipe = intel_crtc->pipe; | |
5688 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5689 | ||
5690 | /* | |
5691 | * TODO: Check what kind of values actually come out of the pipe | |
5692 | * with these coeff/postoff values and adjust to get the best | |
5693 | * accuracy. Perhaps we even need to take the bpc value into | |
5694 | * consideration. | |
5695 | */ | |
5696 | ||
50f3b016 | 5697 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5698 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5699 | ||
5700 | /* | |
5701 | * GY/GU and RY/RU should be the other way around according | |
5702 | * to BSpec, but reality doesn't agree. Just set them up in | |
5703 | * a way that results in the correct picture. | |
5704 | */ | |
5705 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5706 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5707 | ||
5708 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5709 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5710 | ||
5711 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5712 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
5713 | ||
5714 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
5715 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
5716 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
5717 | ||
5718 | if (INTEL_INFO(dev)->gen > 6) { | |
5719 | uint16_t postoff = 0; | |
5720 | ||
50f3b016 | 5721 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5722 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5723 | ||
5724 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
5725 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
5726 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
5727 | ||
5728 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
5729 | } else { | |
5730 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
5731 | ||
50f3b016 | 5732 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5733 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5734 | ||
5735 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
5736 | } | |
5737 | } | |
5738 | ||
6ff93609 | 5739 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 PZ |
5740 | { |
5741 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 5743 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
5744 | uint32_t val; |
5745 | ||
3eff4faa | 5746 | val = 0; |
ee2b0b38 | 5747 | |
d8b32247 | 5748 | if (intel_crtc->config.dither) |
ee2b0b38 PZ |
5749 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5750 | ||
6ff93609 | 5751 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
5752 | val |= PIPECONF_INTERLACED_ILK; |
5753 | else | |
5754 | val |= PIPECONF_PROGRESSIVE; | |
5755 | ||
702e7a56 PZ |
5756 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5757 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
5758 | |
5759 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
5760 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
ee2b0b38 PZ |
5761 | } |
5762 | ||
6591c6e4 | 5763 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
5764 | intel_clock_t *clock, |
5765 | bool *has_reduced_clock, | |
5766 | intel_clock_t *reduced_clock) | |
5767 | { | |
5768 | struct drm_device *dev = crtc->dev; | |
5769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5770 | struct intel_encoder *intel_encoder; | |
5771 | int refclk; | |
d4906093 | 5772 | const intel_limit_t *limit; |
a16af721 | 5773 | bool ret, is_lvds = false; |
79e53945 | 5774 | |
6591c6e4 PZ |
5775 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5776 | switch (intel_encoder->type) { | |
79e53945 JB |
5777 | case INTEL_OUTPUT_LVDS: |
5778 | is_lvds = true; | |
5779 | break; | |
79e53945 JB |
5780 | } |
5781 | } | |
5782 | ||
d9d444cb | 5783 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5784 | |
d4906093 ML |
5785 | /* |
5786 | * Returns a set of divisors for the desired target clock with the given | |
5787 | * refclk, or FALSE. The returned values represent the clock equation: | |
5788 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5789 | */ | |
1b894b59 | 5790 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
5791 | ret = dev_priv->display.find_dpll(limit, crtc, |
5792 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 5793 | refclk, NULL, clock); |
6591c6e4 PZ |
5794 | if (!ret) |
5795 | return false; | |
cda4b7d3 | 5796 | |
ddc9003c | 5797 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5798 | /* |
5799 | * Ensure we match the reduced clock's P to the target clock. | |
5800 | * If the clocks don't match, we can't switch the display clock | |
5801 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5802 | * downclock feature. | |
5803 | */ | |
ee9300bb DV |
5804 | *has_reduced_clock = |
5805 | dev_priv->display.find_dpll(limit, crtc, | |
5806 | dev_priv->lvds_downclock, | |
5807 | refclk, clock, | |
5808 | reduced_clock); | |
652c393a | 5809 | } |
61e9653f | 5810 | |
6591c6e4 PZ |
5811 | return true; |
5812 | } | |
5813 | ||
01a415fd DV |
5814 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
5815 | { | |
5816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5817 | uint32_t temp; | |
5818 | ||
5819 | temp = I915_READ(SOUTH_CHICKEN1); | |
5820 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5821 | return; | |
5822 | ||
5823 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5824 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5825 | ||
5826 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5827 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5828 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5829 | POSTING_READ(SOUTH_CHICKEN1); | |
5830 | } | |
5831 | ||
ebfd86fd | 5832 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
01a415fd DV |
5833 | { |
5834 | struct drm_device *dev = intel_crtc->base.dev; | |
5835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01a415fd DV |
5836 | |
5837 | switch (intel_crtc->pipe) { | |
5838 | case PIPE_A: | |
ebfd86fd | 5839 | break; |
01a415fd | 5840 | case PIPE_B: |
ebfd86fd | 5841 | if (intel_crtc->config.fdi_lanes > 2) |
01a415fd DV |
5842 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
5843 | else | |
5844 | cpt_enable_fdi_bc_bifurcation(dev); | |
5845 | ||
ebfd86fd | 5846 | break; |
01a415fd | 5847 | case PIPE_C: |
01a415fd DV |
5848 | cpt_enable_fdi_bc_bifurcation(dev); |
5849 | ||
ebfd86fd | 5850 | break; |
01a415fd DV |
5851 | default: |
5852 | BUG(); | |
5853 | } | |
5854 | } | |
5855 | ||
d4b1931c PZ |
5856 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5857 | { | |
5858 | /* | |
5859 | * Account for spread spectrum to avoid | |
5860 | * oversubscribing the link. Max center spread | |
5861 | * is 2.5%; use 5% for safety's sake. | |
5862 | */ | |
5863 | u32 bps = target_clock * bpp * 21 / 20; | |
5864 | return bps / (link_bw * 8) + 1; | |
5865 | } | |
5866 | ||
7429e9d4 | 5867 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 5868 | { |
7429e9d4 | 5869 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
5870 | } |
5871 | ||
de13a2e3 | 5872 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 5873 | u32 *fp, |
9a7c7890 | 5874 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 5875 | { |
de13a2e3 | 5876 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5877 | struct drm_device *dev = crtc->dev; |
5878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5879 | struct intel_encoder *intel_encoder; |
5880 | uint32_t dpll; | |
6cc5f341 | 5881 | int factor, num_connectors = 0; |
09ede541 | 5882 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 5883 | |
de13a2e3 PZ |
5884 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5885 | switch (intel_encoder->type) { | |
79e53945 JB |
5886 | case INTEL_OUTPUT_LVDS: |
5887 | is_lvds = true; | |
5888 | break; | |
5889 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5890 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5891 | is_sdvo = true; |
79e53945 | 5892 | break; |
79e53945 | 5893 | } |
43565a06 | 5894 | |
c751ce4f | 5895 | num_connectors++; |
79e53945 | 5896 | } |
79e53945 | 5897 | |
c1858123 | 5898 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5899 | factor = 21; |
5900 | if (is_lvds) { | |
5901 | if ((intel_panel_use_ssc(dev_priv) && | |
41aa3448 | 5902 | dev_priv->vbt.lvds_ssc_freq == 100) || |
f0b44056 | 5903 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 5904 | factor = 25; |
09ede541 | 5905 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 5906 | factor = 20; |
c1858123 | 5907 | |
7429e9d4 | 5908 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 5909 | *fp |= FP_CB_TUNE; |
2c07245f | 5910 | |
9a7c7890 DV |
5911 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5912 | *fp2 |= FP_CB_TUNE; | |
5913 | ||
5eddb70b | 5914 | dpll = 0; |
2c07245f | 5915 | |
a07d6787 EA |
5916 | if (is_lvds) |
5917 | dpll |= DPLLB_MODE_LVDS; | |
5918 | else | |
5919 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 5920 | |
ef1b460d DV |
5921 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5922 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
5923 | |
5924 | if (is_sdvo) | |
4a33e48d | 5925 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 5926 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 5927 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 5928 | |
a07d6787 | 5929 | /* compute bitmask from p1 value */ |
7429e9d4 | 5930 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5931 | /* also FPA1 */ |
7429e9d4 | 5932 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5933 | |
7429e9d4 | 5934 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
5935 | case 5: |
5936 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5937 | break; | |
5938 | case 7: | |
5939 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5940 | break; | |
5941 | case 10: | |
5942 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5943 | break; | |
5944 | case 14: | |
5945 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5946 | break; | |
79e53945 JB |
5947 | } |
5948 | ||
b4c09f3b | 5949 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5950 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5951 | else |
5952 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5953 | ||
959e16d6 | 5954 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
5955 | } |
5956 | ||
5957 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
5958 | int x, int y, |
5959 | struct drm_framebuffer *fb) | |
5960 | { | |
5961 | struct drm_device *dev = crtc->dev; | |
5962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5964 | int pipe = intel_crtc->pipe; | |
5965 | int plane = intel_crtc->plane; | |
5966 | int num_connectors = 0; | |
5967 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 5968 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 5969 | bool ok, has_reduced_clock = false; |
8b47047b | 5970 | bool is_lvds = false; |
de13a2e3 | 5971 | struct intel_encoder *encoder; |
e2b78267 | 5972 | struct intel_shared_dpll *pll; |
de13a2e3 | 5973 | int ret; |
de13a2e3 PZ |
5974 | |
5975 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5976 | switch (encoder->type) { | |
5977 | case INTEL_OUTPUT_LVDS: | |
5978 | is_lvds = true; | |
5979 | break; | |
de13a2e3 PZ |
5980 | } |
5981 | ||
5982 | num_connectors++; | |
a07d6787 | 5983 | } |
79e53945 | 5984 | |
5dc5298b PZ |
5985 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5986 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5987 | |
ff9a6750 | 5988 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 5989 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 5990 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
5991 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5992 | return -EINVAL; | |
79e53945 | 5993 | } |
f47709a9 DV |
5994 | /* Compat-code for transition, will disappear. */ |
5995 | if (!intel_crtc->config.clock_set) { | |
5996 | intel_crtc->config.dpll.n = clock.n; | |
5997 | intel_crtc->config.dpll.m1 = clock.m1; | |
5998 | intel_crtc->config.dpll.m2 = clock.m2; | |
5999 | intel_crtc->config.dpll.p1 = clock.p1; | |
6000 | intel_crtc->config.dpll.p2 = clock.p2; | |
6001 | } | |
79e53945 | 6002 | |
5dc5298b | 6003 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6004 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6005 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6006 | if (has_reduced_clock) |
7429e9d4 | 6007 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6008 | |
7429e9d4 | 6009 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6010 | &fp, &reduced_clock, |
6011 | has_reduced_clock ? &fp2 : NULL); | |
6012 | ||
959e16d6 | 6013 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6014 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6015 | if (has_reduced_clock) | |
6016 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6017 | else | |
6018 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6019 | ||
b89a1d39 | 6020 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6021 | if (pll == NULL) { |
84f44ce7 VS |
6022 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6023 | pipe_name(pipe)); | |
4b645f14 JB |
6024 | return -EINVAL; |
6025 | } | |
ee7b9f93 | 6026 | } else |
e72f9fbf | 6027 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6028 | |
03afc4a2 DV |
6029 | if (intel_crtc->config.has_dp_encoder) |
6030 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6031 | |
bcd644e0 DV |
6032 | if (is_lvds && has_reduced_clock && i915_powersave) |
6033 | intel_crtc->lowfreq_avail = true; | |
6034 | else | |
6035 | intel_crtc->lowfreq_avail = false; | |
e2b78267 DV |
6036 | |
6037 | if (intel_crtc->config.has_pch_encoder) { | |
6038 | pll = intel_crtc_to_shared_dpll(intel_crtc); | |
6039 | ||
652c393a JB |
6040 | } |
6041 | ||
8a654f3b | 6042 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6043 | |
ca3a0ff8 | 6044 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6045 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6046 | &intel_crtc->config.fdi_m_n); | |
6047 | } | |
2c07245f | 6048 | |
ebfd86fd DV |
6049 | if (IS_IVYBRIDGE(dev)) |
6050 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
79e53945 | 6051 | |
6ff93609 | 6052 | ironlake_set_pipeconf(crtc); |
79e53945 | 6053 | |
a1f9e77e PZ |
6054 | /* Set up the display plane register */ |
6055 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6056 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6057 | |
94352cf9 | 6058 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6059 | |
1857e1da | 6060 | return ret; |
79e53945 JB |
6061 | } |
6062 | ||
eb14cb74 VS |
6063 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6064 | struct intel_link_m_n *m_n) | |
6065 | { | |
6066 | struct drm_device *dev = crtc->base.dev; | |
6067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6068 | enum pipe pipe = crtc->pipe; | |
6069 | ||
6070 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6071 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6072 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6073 | & ~TU_SIZE_MASK; | |
6074 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6075 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6076 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6077 | } | |
6078 | ||
6079 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6080 | enum transcoder transcoder, | |
6081 | struct intel_link_m_n *m_n) | |
72419203 DV |
6082 | { |
6083 | struct drm_device *dev = crtc->base.dev; | |
6084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6085 | enum pipe pipe = crtc->pipe; |
72419203 | 6086 | |
eb14cb74 VS |
6087 | if (INTEL_INFO(dev)->gen >= 5) { |
6088 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6089 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6090 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6091 | & ~TU_SIZE_MASK; | |
6092 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6093 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6094 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6095 | } else { | |
6096 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6097 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6098 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6099 | & ~TU_SIZE_MASK; | |
6100 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6101 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6102 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6103 | } | |
6104 | } | |
6105 | ||
6106 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6107 | struct intel_crtc_config *pipe_config) | |
6108 | { | |
6109 | if (crtc->config.has_pch_encoder) | |
6110 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6111 | else | |
6112 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6113 | &pipe_config->dp_m_n); | |
6114 | } | |
72419203 | 6115 | |
eb14cb74 VS |
6116 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6117 | struct intel_crtc_config *pipe_config) | |
6118 | { | |
6119 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6120 | &pipe_config->fdi_m_n); | |
72419203 DV |
6121 | } |
6122 | ||
2fa2fe9a DV |
6123 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6124 | struct intel_crtc_config *pipe_config) | |
6125 | { | |
6126 | struct drm_device *dev = crtc->base.dev; | |
6127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6128 | uint32_t tmp; | |
6129 | ||
6130 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6131 | ||
6132 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6133 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6134 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6135 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6136 | |
6137 | /* We currently do not free assignements of panel fitters on | |
6138 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6139 | * differentiates them) so just WARN about this case for now. */ | |
6140 | if (IS_GEN7(dev)) { | |
6141 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6142 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6143 | } | |
2fa2fe9a | 6144 | } |
79e53945 JB |
6145 | } |
6146 | ||
0e8ffe1b DV |
6147 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6148 | struct intel_crtc_config *pipe_config) | |
6149 | { | |
6150 | struct drm_device *dev = crtc->base.dev; | |
6151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6152 | uint32_t tmp; | |
6153 | ||
e143a21c | 6154 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6155 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6156 | |
0e8ffe1b DV |
6157 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6158 | if (!(tmp & PIPECONF_ENABLE)) | |
6159 | return false; | |
6160 | ||
42571aef VS |
6161 | switch (tmp & PIPECONF_BPC_MASK) { |
6162 | case PIPECONF_6BPC: | |
6163 | pipe_config->pipe_bpp = 18; | |
6164 | break; | |
6165 | case PIPECONF_8BPC: | |
6166 | pipe_config->pipe_bpp = 24; | |
6167 | break; | |
6168 | case PIPECONF_10BPC: | |
6169 | pipe_config->pipe_bpp = 30; | |
6170 | break; | |
6171 | case PIPECONF_12BPC: | |
6172 | pipe_config->pipe_bpp = 36; | |
6173 | break; | |
6174 | default: | |
6175 | break; | |
6176 | } | |
6177 | ||
ab9412ba | 6178 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6179 | struct intel_shared_dpll *pll; |
6180 | ||
88adfff1 DV |
6181 | pipe_config->has_pch_encoder = true; |
6182 | ||
627eb5a3 DV |
6183 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6184 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6185 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6186 | |
6187 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6188 | |
c0d43d62 | 6189 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6190 | pipe_config->shared_dpll = |
6191 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6192 | } else { |
6193 | tmp = I915_READ(PCH_DPLL_SEL); | |
6194 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6195 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6196 | else | |
6197 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6198 | } | |
66e985c0 DV |
6199 | |
6200 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6201 | ||
6202 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6203 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6204 | |
6205 | tmp = pipe_config->dpll_hw_state.dpll; | |
6206 | pipe_config->pixel_multiplier = | |
6207 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6208 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6209 | |
6210 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6211 | } else { |
6212 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6213 | } |
6214 | ||
1bd1bd80 DV |
6215 | intel_get_pipe_timings(crtc, pipe_config); |
6216 | ||
2fa2fe9a DV |
6217 | ironlake_get_pfit_config(crtc, pipe_config); |
6218 | ||
0e8ffe1b DV |
6219 | return true; |
6220 | } | |
6221 | ||
be256dc7 PZ |
6222 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6223 | { | |
6224 | struct drm_device *dev = dev_priv->dev; | |
6225 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6226 | struct intel_crtc *crtc; | |
6227 | unsigned long irqflags; | |
bd633a7c | 6228 | uint32_t val; |
be256dc7 PZ |
6229 | |
6230 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6231 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", | |
6232 | pipe_name(crtc->pipe)); | |
6233 | ||
6234 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6235 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6236 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6237 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6238 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6239 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6240 | "CPU PWM1 enabled\n"); | |
6241 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6242 | "CPU PWM2 enabled\n"); | |
6243 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6244 | "PCH PWM1 enabled\n"); | |
6245 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6246 | "Utility pin enabled\n"); | |
6247 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6248 | ||
6249 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6250 | val = I915_READ(DEIMR); | |
6251 | WARN((val & ~DE_PCH_EVENT_IVB) != val, | |
6252 | "Unexpected DEIMR bits enabled: 0x%x\n", val); | |
6253 | val = I915_READ(SDEIMR); | |
bd633a7c | 6254 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6255 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6256 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6257 | } | |
6258 | ||
6259 | /* | |
6260 | * This function implements pieces of two sequences from BSpec: | |
6261 | * - Sequence for display software to disable LCPLL | |
6262 | * - Sequence for display software to allow package C8+ | |
6263 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6264 | * register. Callers should take care of disabling all the display engine | |
6265 | * functions, doing the mode unset, fixing interrupts, etc. | |
6266 | */ | |
6ff58d53 PZ |
6267 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6268 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6269 | { |
6270 | uint32_t val; | |
6271 | ||
6272 | assert_can_disable_lcpll(dev_priv); | |
6273 | ||
6274 | val = I915_READ(LCPLL_CTL); | |
6275 | ||
6276 | if (switch_to_fclk) { | |
6277 | val |= LCPLL_CD_SOURCE_FCLK; | |
6278 | I915_WRITE(LCPLL_CTL, val); | |
6279 | ||
6280 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6281 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6282 | DRM_ERROR("Switching to FCLK failed\n"); | |
6283 | ||
6284 | val = I915_READ(LCPLL_CTL); | |
6285 | } | |
6286 | ||
6287 | val |= LCPLL_PLL_DISABLE; | |
6288 | I915_WRITE(LCPLL_CTL, val); | |
6289 | POSTING_READ(LCPLL_CTL); | |
6290 | ||
6291 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6292 | DRM_ERROR("LCPLL still locked\n"); | |
6293 | ||
6294 | val = I915_READ(D_COMP); | |
6295 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6296 | mutex_lock(&dev_priv->rps.hw_lock); |
6297 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6298 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6299 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6300 | POSTING_READ(D_COMP); |
6301 | ndelay(100); | |
6302 | ||
6303 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6304 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6305 | ||
6306 | if (allow_power_down) { | |
6307 | val = I915_READ(LCPLL_CTL); | |
6308 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6309 | I915_WRITE(LCPLL_CTL, val); | |
6310 | POSTING_READ(LCPLL_CTL); | |
6311 | } | |
6312 | } | |
6313 | ||
6314 | /* | |
6315 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6316 | * source. | |
6317 | */ | |
6ff58d53 | 6318 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6319 | { |
6320 | uint32_t val; | |
6321 | ||
6322 | val = I915_READ(LCPLL_CTL); | |
6323 | ||
6324 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6325 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6326 | return; | |
6327 | ||
215733fa PZ |
6328 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6329 | * we'll hang the machine! */ | |
6330 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
6331 | ||
be256dc7 PZ |
6332 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6333 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6334 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6335 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6336 | } |
6337 | ||
6338 | val = I915_READ(D_COMP); | |
6339 | val |= D_COMP_COMP_FORCE; | |
6340 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6341 | mutex_lock(&dev_priv->rps.hw_lock); |
6342 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6343 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6344 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6345 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6346 | |
6347 | val = I915_READ(LCPLL_CTL); | |
6348 | val &= ~LCPLL_PLL_DISABLE; | |
6349 | I915_WRITE(LCPLL_CTL, val); | |
6350 | ||
6351 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6352 | DRM_ERROR("LCPLL not locked yet\n"); | |
6353 | ||
6354 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6355 | val = I915_READ(LCPLL_CTL); | |
6356 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6357 | I915_WRITE(LCPLL_CTL, val); | |
6358 | ||
6359 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6360 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6361 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6362 | } | |
215733fa PZ |
6363 | |
6364 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
be256dc7 PZ |
6365 | } |
6366 | ||
c67a470b PZ |
6367 | void hsw_enable_pc8_work(struct work_struct *__work) |
6368 | { | |
6369 | struct drm_i915_private *dev_priv = | |
6370 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6371 | pc8.enable_work); | |
6372 | struct drm_device *dev = dev_priv->dev; | |
6373 | uint32_t val; | |
6374 | ||
6375 | if (dev_priv->pc8.enabled) | |
6376 | return; | |
6377 | ||
6378 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6379 | ||
6380 | dev_priv->pc8.enabled = true; | |
6381 | ||
6382 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6383 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6384 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6385 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6386 | } | |
6387 | ||
6388 | lpt_disable_clkout_dp(dev); | |
6389 | hsw_pc8_disable_interrupts(dev); | |
6390 | hsw_disable_lcpll(dev_priv, true, true); | |
6391 | } | |
6392 | ||
6393 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6394 | { | |
6395 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6396 | WARN(dev_priv->pc8.disable_count < 1, | |
6397 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6398 | ||
6399 | dev_priv->pc8.disable_count--; | |
6400 | if (dev_priv->pc8.disable_count != 0) | |
6401 | return; | |
6402 | ||
6403 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
90058745 | 6404 | msecs_to_jiffies(i915_pc8_timeout)); |
c67a470b PZ |
6405 | } |
6406 | ||
6407 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6408 | { | |
6409 | struct drm_device *dev = dev_priv->dev; | |
6410 | uint32_t val; | |
6411 | ||
6412 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6413 | WARN(dev_priv->pc8.disable_count < 0, | |
6414 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6415 | ||
6416 | dev_priv->pc8.disable_count++; | |
6417 | if (dev_priv->pc8.disable_count != 1) | |
6418 | return; | |
6419 | ||
6420 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); | |
6421 | if (!dev_priv->pc8.enabled) | |
6422 | return; | |
6423 | ||
6424 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6425 | ||
6426 | hsw_restore_lcpll(dev_priv); | |
6427 | hsw_pc8_restore_interrupts(dev); | |
6428 | lpt_init_pch_refclk(dev); | |
6429 | ||
6430 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6431 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6432 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6433 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6434 | } | |
6435 | ||
6436 | intel_prepare_ddi(dev); | |
6437 | i915_gem_init_swizzling(dev); | |
6438 | mutex_lock(&dev_priv->rps.hw_lock); | |
6439 | gen6_update_ring_freq(dev); | |
6440 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6441 | dev_priv->pc8.enabled = false; | |
6442 | } | |
6443 | ||
6444 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6445 | { | |
6446 | mutex_lock(&dev_priv->pc8.lock); | |
6447 | __hsw_enable_package_c8(dev_priv); | |
6448 | mutex_unlock(&dev_priv->pc8.lock); | |
6449 | } | |
6450 | ||
6451 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6452 | { | |
6453 | mutex_lock(&dev_priv->pc8.lock); | |
6454 | __hsw_disable_package_c8(dev_priv); | |
6455 | mutex_unlock(&dev_priv->pc8.lock); | |
6456 | } | |
6457 | ||
6458 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6459 | { | |
6460 | struct drm_device *dev = dev_priv->dev; | |
6461 | struct intel_crtc *crtc; | |
6462 | uint32_t val; | |
6463 | ||
6464 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6465 | if (crtc->base.enabled) | |
6466 | return false; | |
6467 | ||
6468 | /* This case is still possible since we have the i915.disable_power_well | |
6469 | * parameter and also the KVMr or something else might be requesting the | |
6470 | * power well. */ | |
6471 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6472 | if (val != 0) { | |
6473 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6474 | return false; | |
6475 | } | |
6476 | ||
6477 | return true; | |
6478 | } | |
6479 | ||
6480 | /* Since we're called from modeset_global_resources there's no way to | |
6481 | * symmetrically increase and decrease the refcount, so we use | |
6482 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6483 | * or not. | |
6484 | */ | |
6485 | static void hsw_update_package_c8(struct drm_device *dev) | |
6486 | { | |
6487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6488 | bool allow; | |
6489 | ||
6490 | if (!i915_enable_pc8) | |
6491 | return; | |
6492 | ||
6493 | mutex_lock(&dev_priv->pc8.lock); | |
6494 | ||
6495 | allow = hsw_can_enable_package_c8(dev_priv); | |
6496 | ||
6497 | if (allow == dev_priv->pc8.requirements_met) | |
6498 | goto done; | |
6499 | ||
6500 | dev_priv->pc8.requirements_met = allow; | |
6501 | ||
6502 | if (allow) | |
6503 | __hsw_enable_package_c8(dev_priv); | |
6504 | else | |
6505 | __hsw_disable_package_c8(dev_priv); | |
6506 | ||
6507 | done: | |
6508 | mutex_unlock(&dev_priv->pc8.lock); | |
6509 | } | |
6510 | ||
6511 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6512 | { | |
6513 | if (!dev_priv->pc8.gpu_idle) { | |
6514 | dev_priv->pc8.gpu_idle = true; | |
6515 | hsw_enable_package_c8(dev_priv); | |
6516 | } | |
6517 | } | |
6518 | ||
6519 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6520 | { | |
6521 | if (dev_priv->pc8.gpu_idle) { | |
6522 | dev_priv->pc8.gpu_idle = false; | |
6523 | hsw_disable_package_c8(dev_priv); | |
6524 | } | |
be256dc7 PZ |
6525 | } |
6526 | ||
d6dd9eb1 DV |
6527 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6528 | { | |
d6dd9eb1 DV |
6529 | bool enable = false; |
6530 | struct intel_crtc *crtc; | |
d6dd9eb1 DV |
6531 | |
6532 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
e7a639c4 DV |
6533 | if (!crtc->base.enabled) |
6534 | continue; | |
d6dd9eb1 | 6535 | |
fd4daa9c | 6536 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
e7a639c4 | 6537 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
d6dd9eb1 DV |
6538 | enable = true; |
6539 | } | |
6540 | ||
d6dd9eb1 | 6541 | intel_set_power_well(dev, enable); |
c67a470b PZ |
6542 | |
6543 | hsw_update_package_c8(dev); | |
d6dd9eb1 DV |
6544 | } |
6545 | ||
09b4ddf9 | 6546 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6547 | int x, int y, |
6548 | struct drm_framebuffer *fb) | |
6549 | { | |
6550 | struct drm_device *dev = crtc->dev; | |
6551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6552 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6553 | int plane = intel_crtc->plane; |
09b4ddf9 | 6554 | int ret; |
09b4ddf9 | 6555 | |
ff9a6750 | 6556 | if (!intel_ddi_pll_mode_set(crtc)) |
6441ab5f PZ |
6557 | return -EINVAL; |
6558 | ||
03afc4a2 DV |
6559 | if (intel_crtc->config.has_dp_encoder) |
6560 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6561 | |
6562 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6563 | |
8a654f3b | 6564 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6565 | |
ca3a0ff8 | 6566 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6567 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6568 | &intel_crtc->config.fdi_m_n); | |
6569 | } | |
09b4ddf9 | 6570 | |
6ff93609 | 6571 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6572 | |
50f3b016 | 6573 | intel_set_pipe_csc(crtc); |
86d3efce | 6574 | |
09b4ddf9 | 6575 | /* Set up the display plane register */ |
86d3efce | 6576 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6577 | POSTING_READ(DSPCNTR(plane)); |
6578 | ||
6579 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6580 | ||
1f803ee5 | 6581 | return ret; |
79e53945 JB |
6582 | } |
6583 | ||
0e8ffe1b DV |
6584 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6585 | struct intel_crtc_config *pipe_config) | |
6586 | { | |
6587 | struct drm_device *dev = crtc->base.dev; | |
6588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6589 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6590 | uint32_t tmp; |
6591 | ||
e143a21c | 6592 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6593 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6594 | ||
eccb140b DV |
6595 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6596 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6597 | enum pipe trans_edp_pipe; | |
6598 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6599 | default: | |
6600 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6601 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6602 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6603 | trans_edp_pipe = PIPE_A; | |
6604 | break; | |
6605 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
6606 | trans_edp_pipe = PIPE_B; | |
6607 | break; | |
6608 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
6609 | trans_edp_pipe = PIPE_C; | |
6610 | break; | |
6611 | } | |
6612 | ||
6613 | if (trans_edp_pipe == crtc->pipe) | |
6614 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
6615 | } | |
6616 | ||
b97186f0 | 6617 | if (!intel_display_power_enabled(dev, |
eccb140b | 6618 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
6619 | return false; |
6620 | ||
eccb140b | 6621 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
6622 | if (!(tmp & PIPECONF_ENABLE)) |
6623 | return false; | |
6624 | ||
88adfff1 | 6625 | /* |
f196e6be | 6626 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
6627 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6628 | * the PCH transcoder is on. | |
6629 | */ | |
eccb140b | 6630 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 6631 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 6632 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
6633 | pipe_config->has_pch_encoder = true; |
6634 | ||
627eb5a3 DV |
6635 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6636 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6637 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6638 | |
6639 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
6640 | } |
6641 | ||
1bd1bd80 DV |
6642 | intel_get_pipe_timings(crtc, pipe_config); |
6643 | ||
2fa2fe9a DV |
6644 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6645 | if (intel_display_power_enabled(dev, pfit_domain)) | |
6646 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 6647 | |
42db64ef PZ |
6648 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6649 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
6650 | ||
6c49f241 DV |
6651 | pipe_config->pixel_multiplier = 1; |
6652 | ||
0e8ffe1b DV |
6653 | return true; |
6654 | } | |
6655 | ||
f564048e | 6656 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6657 | int x, int y, |
94352cf9 | 6658 | struct drm_framebuffer *fb) |
f564048e EA |
6659 | { |
6660 | struct drm_device *dev = crtc->dev; | |
6661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 6662 | struct intel_encoder *encoder; |
0b701d27 | 6663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 6664 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 6665 | int pipe = intel_crtc->pipe; |
f564048e EA |
6666 | int ret; |
6667 | ||
0b701d27 | 6668 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6669 | |
b8cecdf5 DV |
6670 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6671 | ||
79e53945 | 6672 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6673 | |
9256aa19 DV |
6674 | if (ret != 0) |
6675 | return ret; | |
6676 | ||
6677 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6678 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
6679 | encoder->base.base.id, | |
6680 | drm_get_encoder_name(&encoder->base), | |
6681 | mode->base.id, mode->name); | |
36f2d1f1 | 6682 | encoder->mode_set(encoder); |
9256aa19 DV |
6683 | } |
6684 | ||
6685 | return 0; | |
79e53945 JB |
6686 | } |
6687 | ||
3a9627f4 WF |
6688 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6689 | int reg_eldv, uint32_t bits_eldv, | |
6690 | int reg_elda, uint32_t bits_elda, | |
6691 | int reg_edid) | |
6692 | { | |
6693 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6694 | uint8_t *eld = connector->eld; | |
6695 | uint32_t i; | |
6696 | ||
6697 | i = I915_READ(reg_eldv); | |
6698 | i &= bits_eldv; | |
6699 | ||
6700 | if (!eld[0]) | |
6701 | return !i; | |
6702 | ||
6703 | if (!i) | |
6704 | return false; | |
6705 | ||
6706 | i = I915_READ(reg_elda); | |
6707 | i &= ~bits_elda; | |
6708 | I915_WRITE(reg_elda, i); | |
6709 | ||
6710 | for (i = 0; i < eld[2]; i++) | |
6711 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6712 | return false; | |
6713 | ||
6714 | return true; | |
6715 | } | |
6716 | ||
e0dac65e WF |
6717 | static void g4x_write_eld(struct drm_connector *connector, |
6718 | struct drm_crtc *crtc) | |
6719 | { | |
6720 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6721 | uint8_t *eld = connector->eld; | |
6722 | uint32_t eldv; | |
6723 | uint32_t len; | |
6724 | uint32_t i; | |
6725 | ||
6726 | i = I915_READ(G4X_AUD_VID_DID); | |
6727 | ||
6728 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6729 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6730 | else | |
6731 | eldv = G4X_ELDV_DEVCTG; | |
6732 | ||
3a9627f4 WF |
6733 | if (intel_eld_uptodate(connector, |
6734 | G4X_AUD_CNTL_ST, eldv, | |
6735 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6736 | G4X_HDMIW_HDMIEDID)) | |
6737 | return; | |
6738 | ||
e0dac65e WF |
6739 | i = I915_READ(G4X_AUD_CNTL_ST); |
6740 | i &= ~(eldv | G4X_ELD_ADDR); | |
6741 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6742 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6743 | ||
6744 | if (!eld[0]) | |
6745 | return; | |
6746 | ||
6747 | len = min_t(uint8_t, eld[2], len); | |
6748 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6749 | for (i = 0; i < len; i++) | |
6750 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6751 | ||
6752 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6753 | i |= eldv; | |
6754 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6755 | } | |
6756 | ||
83358c85 WX |
6757 | static void haswell_write_eld(struct drm_connector *connector, |
6758 | struct drm_crtc *crtc) | |
6759 | { | |
6760 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6761 | uint8_t *eld = connector->eld; | |
6762 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 6763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
6764 | uint32_t eldv; |
6765 | uint32_t i; | |
6766 | int len; | |
6767 | int pipe = to_intel_crtc(crtc)->pipe; | |
6768 | int tmp; | |
6769 | ||
6770 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
6771 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
6772 | int aud_config = HSW_AUD_CFG(pipe); | |
6773 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
6774 | ||
6775 | ||
6776 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
6777 | ||
6778 | /* Audio output enable */ | |
6779 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
6780 | tmp = I915_READ(aud_cntrl_st2); | |
6781 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
6782 | I915_WRITE(aud_cntrl_st2, tmp); | |
6783 | ||
6784 | /* Wait for 1 vertical blank */ | |
6785 | intel_wait_for_vblank(dev, pipe); | |
6786 | ||
6787 | /* Set ELD valid state */ | |
6788 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 6789 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
6790 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6791 | I915_WRITE(aud_cntrl_st2, tmp); | |
6792 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 6793 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
6794 | |
6795 | /* Enable HDMI mode */ | |
6796 | tmp = I915_READ(aud_config); | |
7e7cb34f | 6797 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
6798 | /* clear N_programing_enable and N_value_index */ |
6799 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
6800 | I915_WRITE(aud_config, tmp); | |
6801 | ||
6802 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
6803 | ||
6804 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 6805 | intel_crtc->eld_vld = true; |
83358c85 WX |
6806 | |
6807 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
6808 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6809 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
6810 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
6811 | } else | |
6812 | I915_WRITE(aud_config, 0); | |
6813 | ||
6814 | if (intel_eld_uptodate(connector, | |
6815 | aud_cntrl_st2, eldv, | |
6816 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6817 | hdmiw_hdmiedid)) | |
6818 | return; | |
6819 | ||
6820 | i = I915_READ(aud_cntrl_st2); | |
6821 | i &= ~eldv; | |
6822 | I915_WRITE(aud_cntrl_st2, i); | |
6823 | ||
6824 | if (!eld[0]) | |
6825 | return; | |
6826 | ||
6827 | i = I915_READ(aud_cntl_st); | |
6828 | i &= ~IBX_ELD_ADDRESS; | |
6829 | I915_WRITE(aud_cntl_st, i); | |
6830 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
6831 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
6832 | ||
6833 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6834 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6835 | for (i = 0; i < len; i++) | |
6836 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6837 | ||
6838 | i = I915_READ(aud_cntrl_st2); | |
6839 | i |= eldv; | |
6840 | I915_WRITE(aud_cntrl_st2, i); | |
6841 | ||
6842 | } | |
6843 | ||
e0dac65e WF |
6844 | static void ironlake_write_eld(struct drm_connector *connector, |
6845 | struct drm_crtc *crtc) | |
6846 | { | |
6847 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6848 | uint8_t *eld = connector->eld; | |
6849 | uint32_t eldv; | |
6850 | uint32_t i; | |
6851 | int len; | |
6852 | int hdmiw_hdmiedid; | |
b6daa025 | 6853 | int aud_config; |
e0dac65e WF |
6854 | int aud_cntl_st; |
6855 | int aud_cntrl_st2; | |
9b138a83 | 6856 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 6857 | |
b3f33cbf | 6858 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
6859 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6860 | aud_config = IBX_AUD_CFG(pipe); | |
6861 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6862 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 6863 | } else { |
9b138a83 WX |
6864 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6865 | aud_config = CPT_AUD_CFG(pipe); | |
6866 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6867 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
6868 | } |
6869 | ||
9b138a83 | 6870 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
6871 | |
6872 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 6873 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
6874 | if (!i) { |
6875 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6876 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6877 | eldv = IBX_ELD_VALIDB; |
6878 | eldv |= IBX_ELD_VALIDB << 4; | |
6879 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 6880 | } else { |
2582a850 | 6881 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 6882 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6883 | } |
6884 | ||
3a9627f4 WF |
6885 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6886 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6887 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6888 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6889 | } else | |
6890 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6891 | |
3a9627f4 WF |
6892 | if (intel_eld_uptodate(connector, |
6893 | aud_cntrl_st2, eldv, | |
6894 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6895 | hdmiw_hdmiedid)) | |
6896 | return; | |
6897 | ||
e0dac65e WF |
6898 | i = I915_READ(aud_cntrl_st2); |
6899 | i &= ~eldv; | |
6900 | I915_WRITE(aud_cntrl_st2, i); | |
6901 | ||
6902 | if (!eld[0]) | |
6903 | return; | |
6904 | ||
e0dac65e | 6905 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6906 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6907 | I915_WRITE(aud_cntl_st, i); |
6908 | ||
6909 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6910 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6911 | for (i = 0; i < len; i++) | |
6912 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6913 | ||
6914 | i = I915_READ(aud_cntrl_st2); | |
6915 | i |= eldv; | |
6916 | I915_WRITE(aud_cntrl_st2, i); | |
6917 | } | |
6918 | ||
6919 | void intel_write_eld(struct drm_encoder *encoder, | |
6920 | struct drm_display_mode *mode) | |
6921 | { | |
6922 | struct drm_crtc *crtc = encoder->crtc; | |
6923 | struct drm_connector *connector; | |
6924 | struct drm_device *dev = encoder->dev; | |
6925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6926 | ||
6927 | connector = drm_select_eld(encoder, mode); | |
6928 | if (!connector) | |
6929 | return; | |
6930 | ||
6931 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6932 | connector->base.id, | |
6933 | drm_get_connector_name(connector), | |
6934 | connector->encoder->base.id, | |
6935 | drm_get_encoder_name(connector->encoder)); | |
6936 | ||
6937 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6938 | ||
6939 | if (dev_priv->display.write_eld) | |
6940 | dev_priv->display.write_eld(connector, crtc); | |
6941 | } | |
6942 | ||
560b85bb CW |
6943 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6944 | { | |
6945 | struct drm_device *dev = crtc->dev; | |
6946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6948 | bool visible = base != 0; | |
6949 | u32 cntl; | |
6950 | ||
6951 | if (intel_crtc->cursor_visible == visible) | |
6952 | return; | |
6953 | ||
9db4a9c7 | 6954 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6955 | if (visible) { |
6956 | /* On these chipsets we can only modify the base whilst | |
6957 | * the cursor is disabled. | |
6958 | */ | |
9db4a9c7 | 6959 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6960 | |
6961 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6962 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6963 | cntl |= CURSOR_ENABLE | | |
6964 | CURSOR_GAMMA_ENABLE | | |
6965 | CURSOR_FORMAT_ARGB; | |
6966 | } else | |
6967 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6968 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6969 | |
6970 | intel_crtc->cursor_visible = visible; | |
6971 | } | |
6972 | ||
6973 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6974 | { | |
6975 | struct drm_device *dev = crtc->dev; | |
6976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6977 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6978 | int pipe = intel_crtc->pipe; | |
6979 | bool visible = base != 0; | |
6980 | ||
6981 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6982 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6983 | if (base) { |
6984 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6985 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6986 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6987 | } else { | |
6988 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6989 | cntl |= CURSOR_MODE_DISABLE; | |
6990 | } | |
9db4a9c7 | 6991 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6992 | |
6993 | intel_crtc->cursor_visible = visible; | |
6994 | } | |
6995 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6996 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6997 | } |
6998 | ||
65a21cd6 JB |
6999 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7000 | { | |
7001 | struct drm_device *dev = crtc->dev; | |
7002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7004 | int pipe = intel_crtc->pipe; | |
7005 | bool visible = base != 0; | |
7006 | ||
7007 | if (intel_crtc->cursor_visible != visible) { | |
7008 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7009 | if (base) { | |
7010 | cntl &= ~CURSOR_MODE; | |
7011 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7012 | } else { | |
7013 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7014 | cntl |= CURSOR_MODE_DISABLE; | |
7015 | } | |
1f5d76db | 7016 | if (IS_HASWELL(dev)) { |
86d3efce | 7017 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7018 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7019 | } | |
65a21cd6 JB |
7020 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7021 | ||
7022 | intel_crtc->cursor_visible = visible; | |
7023 | } | |
7024 | /* and commit changes on next vblank */ | |
7025 | I915_WRITE(CURBASE_IVB(pipe), base); | |
7026 | } | |
7027 | ||
cda4b7d3 | 7028 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7029 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7030 | bool on) | |
cda4b7d3 CW |
7031 | { |
7032 | struct drm_device *dev = crtc->dev; | |
7033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7034 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7035 | int pipe = intel_crtc->pipe; | |
7036 | int x = intel_crtc->cursor_x; | |
7037 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7038 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7039 | bool visible; |
7040 | ||
d6e4db15 | 7041 | if (on) |
cda4b7d3 | 7042 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7043 | |
d6e4db15 VS |
7044 | if (x >= intel_crtc->config.pipe_src_w) |
7045 | base = 0; | |
7046 | ||
7047 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7048 | base = 0; |
7049 | ||
7050 | if (x < 0) { | |
efc9064e | 7051 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7052 | base = 0; |
7053 | ||
7054 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7055 | x = -x; | |
7056 | } | |
7057 | pos |= x << CURSOR_X_SHIFT; | |
7058 | ||
7059 | if (y < 0) { | |
efc9064e | 7060 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7061 | base = 0; |
7062 | ||
7063 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7064 | y = -y; | |
7065 | } | |
7066 | pos |= y << CURSOR_Y_SHIFT; | |
7067 | ||
7068 | visible = base != 0; | |
560b85bb | 7069 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7070 | return; |
7071 | ||
0cd83aa9 | 7072 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
7073 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7074 | ivb_update_cursor(crtc, base); | |
7075 | } else { | |
7076 | I915_WRITE(CURPOS(pipe), pos); | |
7077 | if (IS_845G(dev) || IS_I865G(dev)) | |
7078 | i845_update_cursor(crtc, base); | |
7079 | else | |
7080 | i9xx_update_cursor(crtc, base); | |
7081 | } | |
cda4b7d3 CW |
7082 | } |
7083 | ||
79e53945 | 7084 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7085 | struct drm_file *file, |
79e53945 JB |
7086 | uint32_t handle, |
7087 | uint32_t width, uint32_t height) | |
7088 | { | |
7089 | struct drm_device *dev = crtc->dev; | |
7090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7091 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7092 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7093 | uint32_t addr; |
3f8bc370 | 7094 | int ret; |
79e53945 | 7095 | |
79e53945 JB |
7096 | /* if we want to turn off the cursor ignore width and height */ |
7097 | if (!handle) { | |
28c97730 | 7098 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7099 | addr = 0; |
05394f39 | 7100 | obj = NULL; |
5004417d | 7101 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7102 | goto finish; |
79e53945 JB |
7103 | } |
7104 | ||
7105 | /* Currently we only support 64x64 cursors */ | |
7106 | if (width != 64 || height != 64) { | |
7107 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7108 | return -EINVAL; | |
7109 | } | |
7110 | ||
05394f39 | 7111 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7112 | if (&obj->base == NULL) |
79e53945 JB |
7113 | return -ENOENT; |
7114 | ||
05394f39 | 7115 | if (obj->base.size < width * height * 4) { |
79e53945 | 7116 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7117 | ret = -ENOMEM; |
7118 | goto fail; | |
79e53945 JB |
7119 | } |
7120 | ||
71acb5eb | 7121 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7122 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 7123 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
7124 | unsigned alignment; |
7125 | ||
d9e86c0e CW |
7126 | if (obj->tiling_mode) { |
7127 | DRM_ERROR("cursor cannot be tiled\n"); | |
7128 | ret = -EINVAL; | |
7129 | goto fail_locked; | |
7130 | } | |
7131 | ||
693db184 CW |
7132 | /* Note that the w/a also requires 2 PTE of padding following |
7133 | * the bo. We currently fill all unused PTE with the shadow | |
7134 | * page and so we should always have valid PTE following the | |
7135 | * cursor preventing the VT-d warning. | |
7136 | */ | |
7137 | alignment = 0; | |
7138 | if (need_vtd_wa(dev)) | |
7139 | alignment = 64*1024; | |
7140 | ||
7141 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7142 | if (ret) { |
7143 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7144 | goto fail_locked; |
e7b526bb CW |
7145 | } |
7146 | ||
d9e86c0e CW |
7147 | ret = i915_gem_object_put_fence(obj); |
7148 | if (ret) { | |
2da3b9b9 | 7149 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7150 | goto fail_unpin; |
7151 | } | |
7152 | ||
f343c5f6 | 7153 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7154 | } else { |
6eeefaf3 | 7155 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7156 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7157 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7158 | align); | |
71acb5eb DA |
7159 | if (ret) { |
7160 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7161 | goto fail_locked; |
71acb5eb | 7162 | } |
05394f39 | 7163 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7164 | } |
7165 | ||
a6c45cf0 | 7166 | if (IS_GEN2(dev)) |
14b60391 JB |
7167 | I915_WRITE(CURSIZE, (height << 12) | width); |
7168 | ||
3f8bc370 | 7169 | finish: |
3f8bc370 | 7170 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 7171 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 7172 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7173 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7174 | } else | |
cc98b413 | 7175 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7176 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7177 | } |
80824003 | 7178 | |
7f9872e0 | 7179 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7180 | |
7181 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7182 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7183 | intel_crtc->cursor_width = width; |
7184 | intel_crtc->cursor_height = height; | |
7185 | ||
f2f5f771 VS |
7186 | if (intel_crtc->active) |
7187 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7188 | |
79e53945 | 7189 | return 0; |
e7b526bb | 7190 | fail_unpin: |
cc98b413 | 7191 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7192 | fail_locked: |
34b8686e | 7193 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7194 | fail: |
05394f39 | 7195 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7196 | return ret; |
79e53945 JB |
7197 | } |
7198 | ||
7199 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7200 | { | |
79e53945 | 7201 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7202 | |
cda4b7d3 CW |
7203 | intel_crtc->cursor_x = x; |
7204 | intel_crtc->cursor_y = y; | |
652c393a | 7205 | |
f2f5f771 VS |
7206 | if (intel_crtc->active) |
7207 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7208 | |
7209 | return 0; | |
b8c00ac5 DA |
7210 | } |
7211 | ||
79e53945 | 7212 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7213 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7214 | { |
7203425a | 7215 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7216 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7217 | |
7203425a | 7218 | for (i = start; i < end; i++) { |
79e53945 JB |
7219 | intel_crtc->lut_r[i] = red[i] >> 8; |
7220 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7221 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7222 | } | |
7223 | ||
7224 | intel_crtc_load_lut(crtc); | |
7225 | } | |
7226 | ||
79e53945 JB |
7227 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7228 | static struct drm_display_mode load_detect_mode = { | |
7229 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7230 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7231 | }; | |
7232 | ||
d2dff872 CW |
7233 | static struct drm_framebuffer * |
7234 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 7235 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
7236 | struct drm_i915_gem_object *obj) |
7237 | { | |
7238 | struct intel_framebuffer *intel_fb; | |
7239 | int ret; | |
7240 | ||
7241 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7242 | if (!intel_fb) { | |
7243 | drm_gem_object_unreference_unlocked(&obj->base); | |
7244 | return ERR_PTR(-ENOMEM); | |
7245 | } | |
7246 | ||
7247 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
7248 | if (ret) { | |
7249 | drm_gem_object_unreference_unlocked(&obj->base); | |
7250 | kfree(intel_fb); | |
7251 | return ERR_PTR(ret); | |
7252 | } | |
7253 | ||
7254 | return &intel_fb->base; | |
7255 | } | |
7256 | ||
7257 | static u32 | |
7258 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7259 | { | |
7260 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7261 | return ALIGN(pitch, 64); | |
7262 | } | |
7263 | ||
7264 | static u32 | |
7265 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7266 | { | |
7267 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7268 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7269 | } | |
7270 | ||
7271 | static struct drm_framebuffer * | |
7272 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7273 | struct drm_display_mode *mode, | |
7274 | int depth, int bpp) | |
7275 | { | |
7276 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7277 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7278 | |
7279 | obj = i915_gem_alloc_object(dev, | |
7280 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7281 | if (obj == NULL) | |
7282 | return ERR_PTR(-ENOMEM); | |
7283 | ||
7284 | mode_cmd.width = mode->hdisplay; | |
7285 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7286 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7287 | bpp); | |
5ca0c34a | 7288 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7289 | |
7290 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7291 | } | |
7292 | ||
7293 | static struct drm_framebuffer * | |
7294 | mode_fits_in_fbdev(struct drm_device *dev, | |
7295 | struct drm_display_mode *mode) | |
7296 | { | |
7297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7298 | struct drm_i915_gem_object *obj; | |
7299 | struct drm_framebuffer *fb; | |
7300 | ||
7301 | if (dev_priv->fbdev == NULL) | |
7302 | return NULL; | |
7303 | ||
7304 | obj = dev_priv->fbdev->ifb.obj; | |
7305 | if (obj == NULL) | |
7306 | return NULL; | |
7307 | ||
7308 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
7309 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7310 | fb->bits_per_pixel)) | |
d2dff872 CW |
7311 | return NULL; |
7312 | ||
01f2c773 | 7313 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7314 | return NULL; |
7315 | ||
7316 | return fb; | |
7317 | } | |
7318 | ||
d2434ab7 | 7319 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7320 | struct drm_display_mode *mode, |
8261b191 | 7321 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7322 | { |
7323 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7324 | struct intel_encoder *intel_encoder = |
7325 | intel_attached_encoder(connector); | |
79e53945 | 7326 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7327 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7328 | struct drm_crtc *crtc = NULL; |
7329 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7330 | struct drm_framebuffer *fb; |
79e53945 JB |
7331 | int i = -1; |
7332 | ||
d2dff872 CW |
7333 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7334 | connector->base.id, drm_get_connector_name(connector), | |
7335 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7336 | ||
79e53945 JB |
7337 | /* |
7338 | * Algorithm gets a little messy: | |
7a5e4805 | 7339 | * |
79e53945 JB |
7340 | * - if the connector already has an assigned crtc, use it (but make |
7341 | * sure it's on first) | |
7a5e4805 | 7342 | * |
79e53945 JB |
7343 | * - try to find the first unused crtc that can drive this connector, |
7344 | * and use that if we find one | |
79e53945 JB |
7345 | */ |
7346 | ||
7347 | /* See if we already have a CRTC for this connector */ | |
7348 | if (encoder->crtc) { | |
7349 | crtc = encoder->crtc; | |
8261b191 | 7350 | |
7b24056b DV |
7351 | mutex_lock(&crtc->mutex); |
7352 | ||
24218aac | 7353 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7354 | old->load_detect_temp = false; |
7355 | ||
7356 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7357 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7358 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7359 | |
7173188d | 7360 | return true; |
79e53945 JB |
7361 | } |
7362 | ||
7363 | /* Find an unused one (if possible) */ | |
7364 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7365 | i++; | |
7366 | if (!(encoder->possible_crtcs & (1 << i))) | |
7367 | continue; | |
7368 | if (!possible_crtc->enabled) { | |
7369 | crtc = possible_crtc; | |
7370 | break; | |
7371 | } | |
79e53945 JB |
7372 | } |
7373 | ||
7374 | /* | |
7375 | * If we didn't find an unused CRTC, don't use any. | |
7376 | */ | |
7377 | if (!crtc) { | |
7173188d CW |
7378 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7379 | return false; | |
79e53945 JB |
7380 | } |
7381 | ||
7b24056b | 7382 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7383 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7384 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7385 | |
7386 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 7387 | old->dpms_mode = connector->dpms; |
8261b191 | 7388 | old->load_detect_temp = true; |
d2dff872 | 7389 | old->release_fb = NULL; |
79e53945 | 7390 | |
6492711d CW |
7391 | if (!mode) |
7392 | mode = &load_detect_mode; | |
79e53945 | 7393 | |
d2dff872 CW |
7394 | /* We need a framebuffer large enough to accommodate all accesses |
7395 | * that the plane may generate whilst we perform load detection. | |
7396 | * We can not rely on the fbcon either being present (we get called | |
7397 | * during its initialisation to detect all boot displays, or it may | |
7398 | * not even exist) or that it is large enough to satisfy the | |
7399 | * requested mode. | |
7400 | */ | |
94352cf9 DV |
7401 | fb = mode_fits_in_fbdev(dev, mode); |
7402 | if (fb == NULL) { | |
d2dff872 | 7403 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7404 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7405 | old->release_fb = fb; | |
d2dff872 CW |
7406 | } else |
7407 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7408 | if (IS_ERR(fb)) { |
d2dff872 | 7409 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 7410 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7411 | return false; |
79e53945 | 7412 | } |
79e53945 | 7413 | |
c0c36b94 | 7414 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7415 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7416 | if (old->release_fb) |
7417 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 7418 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7419 | return false; |
79e53945 | 7420 | } |
7173188d | 7421 | |
79e53945 | 7422 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7423 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7424 | return true; |
79e53945 JB |
7425 | } |
7426 | ||
d2434ab7 | 7427 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7428 | struct intel_load_detect_pipe *old) |
79e53945 | 7429 | { |
d2434ab7 DV |
7430 | struct intel_encoder *intel_encoder = |
7431 | intel_attached_encoder(connector); | |
4ef69c7a | 7432 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7433 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 7434 | |
d2dff872 CW |
7435 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7436 | connector->base.id, drm_get_connector_name(connector), | |
7437 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7438 | ||
8261b191 | 7439 | if (old->load_detect_temp) { |
fc303101 DV |
7440 | to_intel_connector(connector)->new_encoder = NULL; |
7441 | intel_encoder->new_crtc = NULL; | |
7442 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 7443 | |
36206361 DV |
7444 | if (old->release_fb) { |
7445 | drm_framebuffer_unregister_private(old->release_fb); | |
7446 | drm_framebuffer_unreference(old->release_fb); | |
7447 | } | |
d2dff872 | 7448 | |
67c96400 | 7449 | mutex_unlock(&crtc->mutex); |
0622a53c | 7450 | return; |
79e53945 JB |
7451 | } |
7452 | ||
c751ce4f | 7453 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7454 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7455 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7456 | |
7457 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7458 | } |
7459 | ||
da4a1efa VS |
7460 | static int i9xx_pll_refclk(struct drm_device *dev, |
7461 | const struct intel_crtc_config *pipe_config) | |
7462 | { | |
7463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7464 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7465 | ||
7466 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
7467 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
7468 | else if (HAS_PCH_SPLIT(dev)) | |
7469 | return 120000; | |
7470 | else if (!IS_GEN2(dev)) | |
7471 | return 96000; | |
7472 | else | |
7473 | return 48000; | |
7474 | } | |
7475 | ||
79e53945 | 7476 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7477 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7478 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7479 | { |
f1f644dc | 7480 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7481 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7482 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7483 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7484 | u32 fp; |
7485 | intel_clock_t clock; | |
da4a1efa | 7486 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7487 | |
7488 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7489 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7490 | else |
293623f7 | 7491 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7492 | |
7493 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7494 | if (IS_PINEVIEW(dev)) { |
7495 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7496 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7497 | } else { |
7498 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7499 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7500 | } | |
7501 | ||
a6c45cf0 | 7502 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7503 | if (IS_PINEVIEW(dev)) |
7504 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7505 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7506 | else |
7507 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7508 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7509 | ||
7510 | switch (dpll & DPLL_MODE_MASK) { | |
7511 | case DPLLB_MODE_DAC_SERIAL: | |
7512 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7513 | 5 : 10; | |
7514 | break; | |
7515 | case DPLLB_MODE_LVDS: | |
7516 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
7517 | 7 : 14; | |
7518 | break; | |
7519 | default: | |
28c97730 | 7520 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 7521 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 7522 | return; |
79e53945 JB |
7523 | } |
7524 | ||
ac58c3f0 | 7525 | if (IS_PINEVIEW(dev)) |
da4a1efa | 7526 | pineview_clock(refclk, &clock); |
ac58c3f0 | 7527 | else |
da4a1efa | 7528 | i9xx_clock(refclk, &clock); |
79e53945 JB |
7529 | } else { |
7530 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
7531 | ||
7532 | if (is_lvds) { | |
7533 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
7534 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
7535 | clock.p2 = 14; | |
79e53945 JB |
7536 | } else { |
7537 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
7538 | clock.p1 = 2; | |
7539 | else { | |
7540 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
7541 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
7542 | } | |
7543 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7544 | clock.p2 = 4; | |
7545 | else | |
7546 | clock.p2 = 2; | |
79e53945 | 7547 | } |
da4a1efa VS |
7548 | |
7549 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
7550 | } |
7551 | ||
18442d08 VS |
7552 | /* |
7553 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 7554 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
7555 | * encoder's get_config() function. |
7556 | */ | |
7557 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
7558 | } |
7559 | ||
6878da05 VS |
7560 | int intel_dotclock_calculate(int link_freq, |
7561 | const struct intel_link_m_n *m_n) | |
f1f644dc | 7562 | { |
f1f644dc JB |
7563 | /* |
7564 | * The calculation for the data clock is: | |
1041a02f | 7565 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 7566 | * But we want to avoid losing precison if possible, so: |
1041a02f | 7567 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
7568 | * |
7569 | * and the link clock is simpler: | |
1041a02f | 7570 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
7571 | */ |
7572 | ||
6878da05 VS |
7573 | if (!m_n->link_n) |
7574 | return 0; | |
f1f644dc | 7575 | |
6878da05 VS |
7576 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
7577 | } | |
f1f644dc | 7578 | |
18442d08 VS |
7579 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
7580 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
7581 | { |
7582 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 7583 | |
18442d08 VS |
7584 | /* read out port_clock from the DPLL */ |
7585 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 7586 | |
f1f644dc | 7587 | /* |
18442d08 | 7588 | * This value does not include pixel_multiplier. |
241bfc38 | 7589 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
7590 | * agree once we know their relationship in the encoder's |
7591 | * get_config() function. | |
79e53945 | 7592 | */ |
241bfc38 | 7593 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
7594 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
7595 | &pipe_config->fdi_m_n); | |
79e53945 JB |
7596 | } |
7597 | ||
7598 | /** Returns the currently programmed mode of the given pipe. */ | |
7599 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
7600 | struct drm_crtc *crtc) | |
7601 | { | |
548f245b | 7602 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 7603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 7604 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 7605 | struct drm_display_mode *mode; |
f1f644dc | 7606 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
7607 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7608 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
7609 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
7610 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 7611 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
7612 | |
7613 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
7614 | if (!mode) | |
7615 | return NULL; | |
7616 | ||
f1f644dc JB |
7617 | /* |
7618 | * Construct a pipe_config sufficient for getting the clock info | |
7619 | * back out of crtc_clock_get. | |
7620 | * | |
7621 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
7622 | * to use a real value here instead. | |
7623 | */ | |
293623f7 | 7624 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 7625 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
7626 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
7627 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
7628 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
7629 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
7630 | ||
773ae034 | 7631 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
7632 | mode->hdisplay = (htot & 0xffff) + 1; |
7633 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
7634 | mode->hsync_start = (hsync & 0xffff) + 1; | |
7635 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
7636 | mode->vdisplay = (vtot & 0xffff) + 1; | |
7637 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
7638 | mode->vsync_start = (vsync & 0xffff) + 1; | |
7639 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
7640 | ||
7641 | drm_mode_set_name(mode); | |
79e53945 JB |
7642 | |
7643 | return mode; | |
7644 | } | |
7645 | ||
3dec0095 | 7646 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
7647 | { |
7648 | struct drm_device *dev = crtc->dev; | |
7649 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7651 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
7652 | int dpll_reg = DPLL(pipe); |
7653 | int dpll; | |
652c393a | 7654 | |
bad720ff | 7655 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7656 | return; |
7657 | ||
7658 | if (!dev_priv->lvds_downclock_avail) | |
7659 | return; | |
7660 | ||
dbdc6479 | 7661 | dpll = I915_READ(dpll_reg); |
652c393a | 7662 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7663 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 7664 | |
8ac5a6d5 | 7665 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7666 | |
7667 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7668 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7669 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7670 | |
652c393a JB |
7671 | dpll = I915_READ(dpll_reg); |
7672 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7673 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 7674 | } |
652c393a JB |
7675 | } |
7676 | ||
7677 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7678 | { | |
7679 | struct drm_device *dev = crtc->dev; | |
7680 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 7682 | |
bad720ff | 7683 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7684 | return; |
7685 | ||
7686 | if (!dev_priv->lvds_downclock_avail) | |
7687 | return; | |
7688 | ||
7689 | /* | |
7690 | * Since this is called by a timer, we should never get here in | |
7691 | * the manual case. | |
7692 | */ | |
7693 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
7694 | int pipe = intel_crtc->pipe; |
7695 | int dpll_reg = DPLL(pipe); | |
7696 | int dpll; | |
f6e5b160 | 7697 | |
44d98a61 | 7698 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 7699 | |
8ac5a6d5 | 7700 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 7701 | |
dc257cf1 | 7702 | dpll = I915_READ(dpll_reg); |
652c393a JB |
7703 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7704 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7705 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7706 | dpll = I915_READ(dpll_reg); |
7707 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7708 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7709 | } |
7710 | ||
7711 | } | |
7712 | ||
f047e395 CW |
7713 | void intel_mark_busy(struct drm_device *dev) |
7714 | { | |
c67a470b PZ |
7715 | struct drm_i915_private *dev_priv = dev->dev_private; |
7716 | ||
7717 | hsw_package_c8_gpu_busy(dev_priv); | |
7718 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
7719 | } |
7720 | ||
7721 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 7722 | { |
c67a470b | 7723 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 7724 | struct drm_crtc *crtc; |
652c393a | 7725 | |
c67a470b PZ |
7726 | hsw_package_c8_gpu_idle(dev_priv); |
7727 | ||
652c393a JB |
7728 | if (!i915_powersave) |
7729 | return; | |
7730 | ||
652c393a | 7731 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
7732 | if (!crtc->fb) |
7733 | continue; | |
7734 | ||
725a5b54 | 7735 | intel_decrease_pllclock(crtc); |
652c393a | 7736 | } |
b29c19b6 CW |
7737 | |
7738 | if (dev_priv->info->gen >= 6) | |
7739 | gen6_rps_idle(dev->dev_private); | |
652c393a JB |
7740 | } |
7741 | ||
c65355bb CW |
7742 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7743 | struct intel_ring_buffer *ring) | |
652c393a | 7744 | { |
f047e395 CW |
7745 | struct drm_device *dev = obj->base.dev; |
7746 | struct drm_crtc *crtc; | |
652c393a | 7747 | |
f047e395 | 7748 | if (!i915_powersave) |
acb87dfb CW |
7749 | return; |
7750 | ||
652c393a JB |
7751 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7752 | if (!crtc->fb) | |
7753 | continue; | |
7754 | ||
c65355bb CW |
7755 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7756 | continue; | |
7757 | ||
7758 | intel_increase_pllclock(crtc); | |
7759 | if (ring && intel_fbc_enabled(dev)) | |
7760 | ring->fbc_dirty = true; | |
652c393a JB |
7761 | } |
7762 | } | |
7763 | ||
79e53945 JB |
7764 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7765 | { | |
7766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7767 | struct drm_device *dev = crtc->dev; |
7768 | struct intel_unpin_work *work; | |
7769 | unsigned long flags; | |
7770 | ||
7771 | spin_lock_irqsave(&dev->event_lock, flags); | |
7772 | work = intel_crtc->unpin_work; | |
7773 | intel_crtc->unpin_work = NULL; | |
7774 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7775 | ||
7776 | if (work) { | |
7777 | cancel_work_sync(&work->work); | |
7778 | kfree(work); | |
7779 | } | |
79e53945 | 7780 | |
40ccc72b MK |
7781 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
7782 | ||
79e53945 | 7783 | drm_crtc_cleanup(crtc); |
67e77c5a | 7784 | |
79e53945 JB |
7785 | kfree(intel_crtc); |
7786 | } | |
7787 | ||
6b95a207 KH |
7788 | static void intel_unpin_work_fn(struct work_struct *__work) |
7789 | { | |
7790 | struct intel_unpin_work *work = | |
7791 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 7792 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 7793 | |
b4a98e57 | 7794 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 7795 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7796 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7797 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7798 | |
b4a98e57 CW |
7799 | intel_update_fbc(dev); |
7800 | mutex_unlock(&dev->struct_mutex); | |
7801 | ||
7802 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
7803 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
7804 | ||
6b95a207 KH |
7805 | kfree(work); |
7806 | } | |
7807 | ||
1afe3e9d | 7808 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7809 | struct drm_crtc *crtc) |
6b95a207 KH |
7810 | { |
7811 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7812 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7813 | struct intel_unpin_work *work; | |
6b95a207 KH |
7814 | unsigned long flags; |
7815 | ||
7816 | /* Ignore early vblank irqs */ | |
7817 | if (intel_crtc == NULL) | |
7818 | return; | |
7819 | ||
7820 | spin_lock_irqsave(&dev->event_lock, flags); | |
7821 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
7822 | |
7823 | /* Ensure we don't miss a work->pending update ... */ | |
7824 | smp_rmb(); | |
7825 | ||
7826 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
7827 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7828 | return; | |
7829 | } | |
7830 | ||
e7d841ca CW |
7831 | /* and that the unpin work is consistent wrt ->pending. */ |
7832 | smp_rmb(); | |
7833 | ||
6b95a207 | 7834 | intel_crtc->unpin_work = NULL; |
6b95a207 | 7835 | |
45a066eb RC |
7836 | if (work->event) |
7837 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 7838 | |
0af7e4df MK |
7839 | drm_vblank_put(dev, intel_crtc->pipe); |
7840 | ||
6b95a207 KH |
7841 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7842 | ||
2c10d571 | 7843 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
7844 | |
7845 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
7846 | |
7847 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7848 | } |
7849 | ||
1afe3e9d JB |
7850 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7851 | { | |
7852 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7853 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7854 | ||
49b14a5c | 7855 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7856 | } |
7857 | ||
7858 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7859 | { | |
7860 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7861 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7862 | ||
49b14a5c | 7863 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7864 | } |
7865 | ||
6b95a207 KH |
7866 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7867 | { | |
7868 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7869 | struct intel_crtc *intel_crtc = | |
7870 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7871 | unsigned long flags; | |
7872 | ||
e7d841ca CW |
7873 | /* NB: An MMIO update of the plane base pointer will also |
7874 | * generate a page-flip completion irq, i.e. every modeset | |
7875 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
7876 | */ | |
6b95a207 | 7877 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
7878 | if (intel_crtc->unpin_work) |
7879 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
7880 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7881 | } | |
7882 | ||
e7d841ca CW |
7883 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7884 | { | |
7885 | /* Ensure that the work item is consistent when activating it ... */ | |
7886 | smp_wmb(); | |
7887 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
7888 | /* and that it is marked active as soon as the irq could fire. */ | |
7889 | smp_wmb(); | |
7890 | } | |
7891 | ||
8c9f3aaf JB |
7892 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7893 | struct drm_crtc *crtc, | |
7894 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7895 | struct drm_i915_gem_object *obj, |
7896 | uint32_t flags) | |
8c9f3aaf JB |
7897 | { |
7898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7900 | u32 flip_mask; |
6d90c952 | 7901 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7902 | int ret; |
7903 | ||
6d90c952 | 7904 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7905 | if (ret) |
83d4092b | 7906 | goto err; |
8c9f3aaf | 7907 | |
6d90c952 | 7908 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7909 | if (ret) |
83d4092b | 7910 | goto err_unpin; |
8c9f3aaf JB |
7911 | |
7912 | /* Can't queue multiple flips, so wait for the previous | |
7913 | * one to finish before executing the next. | |
7914 | */ | |
7915 | if (intel_crtc->plane) | |
7916 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7917 | else | |
7918 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7919 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7920 | intel_ring_emit(ring, MI_NOOP); | |
7921 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
7922 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7923 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 7924 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 7925 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
7926 | |
7927 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 7928 | __intel_ring_advance(ring); |
83d4092b CW |
7929 | return 0; |
7930 | ||
7931 | err_unpin: | |
7932 | intel_unpin_fb_obj(obj); | |
7933 | err: | |
8c9f3aaf JB |
7934 | return ret; |
7935 | } | |
7936 | ||
7937 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7938 | struct drm_crtc *crtc, | |
7939 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7940 | struct drm_i915_gem_object *obj, |
7941 | uint32_t flags) | |
8c9f3aaf JB |
7942 | { |
7943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7944 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7945 | u32 flip_mask; |
6d90c952 | 7946 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7947 | int ret; |
7948 | ||
6d90c952 | 7949 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7950 | if (ret) |
83d4092b | 7951 | goto err; |
8c9f3aaf | 7952 | |
6d90c952 | 7953 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7954 | if (ret) |
83d4092b | 7955 | goto err_unpin; |
8c9f3aaf JB |
7956 | |
7957 | if (intel_crtc->plane) | |
7958 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7959 | else | |
7960 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7961 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7962 | intel_ring_emit(ring, MI_NOOP); | |
7963 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
7964 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7965 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 7966 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
7967 | intel_ring_emit(ring, MI_NOOP); |
7968 | ||
e7d841ca | 7969 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 7970 | __intel_ring_advance(ring); |
83d4092b CW |
7971 | return 0; |
7972 | ||
7973 | err_unpin: | |
7974 | intel_unpin_fb_obj(obj); | |
7975 | err: | |
8c9f3aaf JB |
7976 | return ret; |
7977 | } | |
7978 | ||
7979 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7980 | struct drm_crtc *crtc, | |
7981 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7982 | struct drm_i915_gem_object *obj, |
7983 | uint32_t flags) | |
8c9f3aaf JB |
7984 | { |
7985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7987 | uint32_t pf, pipesrc; | |
6d90c952 | 7988 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7989 | int ret; |
7990 | ||
6d90c952 | 7991 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7992 | if (ret) |
83d4092b | 7993 | goto err; |
8c9f3aaf | 7994 | |
6d90c952 | 7995 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7996 | if (ret) |
83d4092b | 7997 | goto err_unpin; |
8c9f3aaf JB |
7998 | |
7999 | /* i965+ uses the linear or tiled offsets from the | |
8000 | * Display Registers (which do not change across a page-flip) | |
8001 | * so we need only reprogram the base address. | |
8002 | */ | |
6d90c952 DV |
8003 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8004 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8005 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8006 | intel_ring_emit(ring, |
f343c5f6 | 8007 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8008 | obj->tiling_mode); |
8c9f3aaf JB |
8009 | |
8010 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8011 | * untested on non-native modes, so ignore it for now. | |
8012 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8013 | */ | |
8014 | pf = 0; | |
8015 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8016 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8017 | |
8018 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8019 | __intel_ring_advance(ring); |
83d4092b CW |
8020 | return 0; |
8021 | ||
8022 | err_unpin: | |
8023 | intel_unpin_fb_obj(obj); | |
8024 | err: | |
8c9f3aaf JB |
8025 | return ret; |
8026 | } | |
8027 | ||
8028 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8029 | struct drm_crtc *crtc, | |
8030 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8031 | struct drm_i915_gem_object *obj, |
8032 | uint32_t flags) | |
8c9f3aaf JB |
8033 | { |
8034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8036 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8037 | uint32_t pf, pipesrc; |
8038 | int ret; | |
8039 | ||
6d90c952 | 8040 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8041 | if (ret) |
83d4092b | 8042 | goto err; |
8c9f3aaf | 8043 | |
6d90c952 | 8044 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8045 | if (ret) |
83d4092b | 8046 | goto err_unpin; |
8c9f3aaf | 8047 | |
6d90c952 DV |
8048 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8049 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8050 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8051 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8052 | |
dc257cf1 DV |
8053 | /* Contrary to the suggestions in the documentation, |
8054 | * "Enable Panel Fitter" does not seem to be required when page | |
8055 | * flipping with a non-native mode, and worse causes a normal | |
8056 | * modeset to fail. | |
8057 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8058 | */ | |
8059 | pf = 0; | |
8c9f3aaf | 8060 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8061 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8062 | |
8063 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8064 | __intel_ring_advance(ring); |
83d4092b CW |
8065 | return 0; |
8066 | ||
8067 | err_unpin: | |
8068 | intel_unpin_fb_obj(obj); | |
8069 | err: | |
8c9f3aaf JB |
8070 | return ret; |
8071 | } | |
8072 | ||
7c9017e5 JB |
8073 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8074 | struct drm_crtc *crtc, | |
8075 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8076 | struct drm_i915_gem_object *obj, |
8077 | uint32_t flags) | |
7c9017e5 JB |
8078 | { |
8079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8081 | struct intel_ring_buffer *ring; |
cb05d8de | 8082 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8083 | int len, ret; |
8084 | ||
8085 | ring = obj->ring; | |
1c5fd085 | 8086 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8087 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8088 | |
8089 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8090 | if (ret) | |
83d4092b | 8091 | goto err; |
7c9017e5 | 8092 | |
cb05d8de DV |
8093 | switch(intel_crtc->plane) { |
8094 | case PLANE_A: | |
8095 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8096 | break; | |
8097 | case PLANE_B: | |
8098 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8099 | break; | |
8100 | case PLANE_C: | |
8101 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8102 | break; | |
8103 | default: | |
8104 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8105 | ret = -ENODEV; | |
ab3951eb | 8106 | goto err_unpin; |
cb05d8de DV |
8107 | } |
8108 | ||
ffe74d75 CW |
8109 | len = 4; |
8110 | if (ring->id == RCS) | |
8111 | len += 6; | |
8112 | ||
8113 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8114 | if (ret) |
83d4092b | 8115 | goto err_unpin; |
7c9017e5 | 8116 | |
ffe74d75 CW |
8117 | /* Unmask the flip-done completion message. Note that the bspec says that |
8118 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8119 | * more than one flip event at any time (or ensure that one flip message | |
8120 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8121 | * Experimentation says that BCS works despite DERRMR masking all | |
8122 | * flip-done completion events and that unmasking all planes at once | |
8123 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8124 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8125 | */ | |
8126 | if (ring->id == RCS) { | |
8127 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8128 | intel_ring_emit(ring, DERRMR); | |
8129 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8130 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8131 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
8132 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | |
8133 | intel_ring_emit(ring, DERRMR); | |
8134 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8135 | } | |
8136 | ||
cb05d8de | 8137 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8138 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8139 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8140 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8141 | |
8142 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8143 | __intel_ring_advance(ring); |
83d4092b CW |
8144 | return 0; |
8145 | ||
8146 | err_unpin: | |
8147 | intel_unpin_fb_obj(obj); | |
8148 | err: | |
7c9017e5 JB |
8149 | return ret; |
8150 | } | |
8151 | ||
8c9f3aaf JB |
8152 | static int intel_default_queue_flip(struct drm_device *dev, |
8153 | struct drm_crtc *crtc, | |
8154 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8155 | struct drm_i915_gem_object *obj, |
8156 | uint32_t flags) | |
8c9f3aaf JB |
8157 | { |
8158 | return -ENODEV; | |
8159 | } | |
8160 | ||
6b95a207 KH |
8161 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8162 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8163 | struct drm_pending_vblank_event *event, |
8164 | uint32_t page_flip_flags) | |
6b95a207 KH |
8165 | { |
8166 | struct drm_device *dev = crtc->dev; | |
8167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8168 | struct drm_framebuffer *old_fb = crtc->fb; |
8169 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8171 | struct intel_unpin_work *work; | |
8c9f3aaf | 8172 | unsigned long flags; |
52e68630 | 8173 | int ret; |
6b95a207 | 8174 | |
e6a595d2 VS |
8175 | /* Can't change pixel format via MI display flips. */ |
8176 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8177 | return -EINVAL; | |
8178 | ||
8179 | /* | |
8180 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8181 | * Note that pitch changes could also affect these register. | |
8182 | */ | |
8183 | if (INTEL_INFO(dev)->gen > 3 && | |
8184 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8185 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8186 | return -EINVAL; | |
8187 | ||
b14c5679 | 8188 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8189 | if (work == NULL) |
8190 | return -ENOMEM; | |
8191 | ||
6b95a207 | 8192 | work->event = event; |
b4a98e57 | 8193 | work->crtc = crtc; |
4a35f83b | 8194 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8195 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8196 | ||
7317c75e JB |
8197 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8198 | if (ret) | |
8199 | goto free_work; | |
8200 | ||
6b95a207 KH |
8201 | /* We borrow the event spin lock for protecting unpin_work */ |
8202 | spin_lock_irqsave(&dev->event_lock, flags); | |
8203 | if (intel_crtc->unpin_work) { | |
8204 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8205 | kfree(work); | |
7317c75e | 8206 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8207 | |
8208 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8209 | return -EBUSY; |
8210 | } | |
8211 | intel_crtc->unpin_work = work; | |
8212 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8213 | ||
b4a98e57 CW |
8214 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8215 | flush_workqueue(dev_priv->wq); | |
8216 | ||
79158103 CW |
8217 | ret = i915_mutex_lock_interruptible(dev); |
8218 | if (ret) | |
8219 | goto cleanup; | |
6b95a207 | 8220 | |
75dfca80 | 8221 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8222 | drm_gem_object_reference(&work->old_fb_obj->base); |
8223 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8224 | |
8225 | crtc->fb = fb; | |
96b099fd | 8226 | |
e1f99ce6 | 8227 | work->pending_flip_obj = obj; |
e1f99ce6 | 8228 | |
4e5359cd SF |
8229 | work->enable_stall_check = true; |
8230 | ||
b4a98e57 | 8231 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8232 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8233 | |
ed8d1975 | 8234 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8235 | if (ret) |
8236 | goto cleanup_pending; | |
6b95a207 | 8237 | |
7782de3b | 8238 | intel_disable_fbc(dev); |
c65355bb | 8239 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8240 | mutex_unlock(&dev->struct_mutex); |
8241 | ||
e5510fac JB |
8242 | trace_i915_flip_request(intel_crtc->plane, obj); |
8243 | ||
6b95a207 | 8244 | return 0; |
96b099fd | 8245 | |
8c9f3aaf | 8246 | cleanup_pending: |
b4a98e57 | 8247 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8248 | crtc->fb = old_fb; |
05394f39 CW |
8249 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8250 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8251 | mutex_unlock(&dev->struct_mutex); |
8252 | ||
79158103 | 8253 | cleanup: |
96b099fd CW |
8254 | spin_lock_irqsave(&dev->event_lock, flags); |
8255 | intel_crtc->unpin_work = NULL; | |
8256 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8257 | ||
7317c75e JB |
8258 | drm_vblank_put(dev, intel_crtc->pipe); |
8259 | free_work: | |
96b099fd CW |
8260 | kfree(work); |
8261 | ||
8262 | return ret; | |
6b95a207 KH |
8263 | } |
8264 | ||
f6e5b160 | 8265 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8266 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8267 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8268 | }; |
8269 | ||
50f56119 DV |
8270 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8271 | struct drm_crtc *crtc) | |
8272 | { | |
8273 | struct drm_device *dev; | |
8274 | struct drm_crtc *tmp; | |
8275 | int crtc_mask = 1; | |
47f1c6c9 | 8276 | |
50f56119 | 8277 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 8278 | |
50f56119 | 8279 | dev = crtc->dev; |
47f1c6c9 | 8280 | |
50f56119 DV |
8281 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8282 | if (tmp == crtc) | |
8283 | break; | |
8284 | crtc_mask <<= 1; | |
8285 | } | |
47f1c6c9 | 8286 | |
50f56119 DV |
8287 | if (encoder->possible_crtcs & crtc_mask) |
8288 | return true; | |
8289 | return false; | |
47f1c6c9 | 8290 | } |
79e53945 | 8291 | |
9a935856 DV |
8292 | /** |
8293 | * intel_modeset_update_staged_output_state | |
8294 | * | |
8295 | * Updates the staged output configuration state, e.g. after we've read out the | |
8296 | * current hw state. | |
8297 | */ | |
8298 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8299 | { |
9a935856 DV |
8300 | struct intel_encoder *encoder; |
8301 | struct intel_connector *connector; | |
f6e5b160 | 8302 | |
9a935856 DV |
8303 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8304 | base.head) { | |
8305 | connector->new_encoder = | |
8306 | to_intel_encoder(connector->base.encoder); | |
8307 | } | |
f6e5b160 | 8308 | |
9a935856 DV |
8309 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8310 | base.head) { | |
8311 | encoder->new_crtc = | |
8312 | to_intel_crtc(encoder->base.crtc); | |
8313 | } | |
f6e5b160 CW |
8314 | } |
8315 | ||
9a935856 DV |
8316 | /** |
8317 | * intel_modeset_commit_output_state | |
8318 | * | |
8319 | * This function copies the stage display pipe configuration to the real one. | |
8320 | */ | |
8321 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8322 | { | |
8323 | struct intel_encoder *encoder; | |
8324 | struct intel_connector *connector; | |
f6e5b160 | 8325 | |
9a935856 DV |
8326 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8327 | base.head) { | |
8328 | connector->base.encoder = &connector->new_encoder->base; | |
8329 | } | |
f6e5b160 | 8330 | |
9a935856 DV |
8331 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8332 | base.head) { | |
8333 | encoder->base.crtc = &encoder->new_crtc->base; | |
8334 | } | |
8335 | } | |
8336 | ||
050f7aeb DV |
8337 | static void |
8338 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8339 | struct intel_crtc_config *pipe_config) | |
8340 | { | |
8341 | int bpp = pipe_config->pipe_bpp; | |
8342 | ||
8343 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8344 | connector->base.base.id, | |
8345 | drm_get_connector_name(&connector->base)); | |
8346 | ||
8347 | /* Don't use an invalid EDID bpc value */ | |
8348 | if (connector->base.display_info.bpc && | |
8349 | connector->base.display_info.bpc * 3 < bpp) { | |
8350 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8351 | bpp, connector->base.display_info.bpc*3); | |
8352 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8353 | } | |
8354 | ||
8355 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8356 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8357 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8358 | bpp); | |
8359 | pipe_config->pipe_bpp = 24; | |
8360 | } | |
8361 | } | |
8362 | ||
4e53c2e0 | 8363 | static int |
050f7aeb DV |
8364 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8365 | struct drm_framebuffer *fb, | |
8366 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8367 | { |
050f7aeb DV |
8368 | struct drm_device *dev = crtc->base.dev; |
8369 | struct intel_connector *connector; | |
4e53c2e0 DV |
8370 | int bpp; |
8371 | ||
d42264b1 DV |
8372 | switch (fb->pixel_format) { |
8373 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8374 | bpp = 8*3; /* since we go through a colormap */ |
8375 | break; | |
d42264b1 DV |
8376 | case DRM_FORMAT_XRGB1555: |
8377 | case DRM_FORMAT_ARGB1555: | |
8378 | /* checked in intel_framebuffer_init already */ | |
8379 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8380 | return -EINVAL; | |
8381 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8382 | bpp = 6*3; /* min is 18bpp */ |
8383 | break; | |
d42264b1 DV |
8384 | case DRM_FORMAT_XBGR8888: |
8385 | case DRM_FORMAT_ABGR8888: | |
8386 | /* checked in intel_framebuffer_init already */ | |
8387 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8388 | return -EINVAL; | |
8389 | case DRM_FORMAT_XRGB8888: | |
8390 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8391 | bpp = 8*3; |
8392 | break; | |
d42264b1 DV |
8393 | case DRM_FORMAT_XRGB2101010: |
8394 | case DRM_FORMAT_ARGB2101010: | |
8395 | case DRM_FORMAT_XBGR2101010: | |
8396 | case DRM_FORMAT_ABGR2101010: | |
8397 | /* checked in intel_framebuffer_init already */ | |
8398 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8399 | return -EINVAL; |
4e53c2e0 DV |
8400 | bpp = 10*3; |
8401 | break; | |
baba133a | 8402 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8403 | default: |
8404 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8405 | return -EINVAL; | |
8406 | } | |
8407 | ||
4e53c2e0 DV |
8408 | pipe_config->pipe_bpp = bpp; |
8409 | ||
8410 | /* Clamp display bpp to EDID value */ | |
8411 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8412 | base.head) { |
1b829e05 DV |
8413 | if (!connector->new_encoder || |
8414 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8415 | continue; |
8416 | ||
050f7aeb | 8417 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8418 | } |
8419 | ||
8420 | return bpp; | |
8421 | } | |
8422 | ||
644db711 DV |
8423 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8424 | { | |
8425 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8426 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8427 | mode->crtc_clock, |
644db711 DV |
8428 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8429 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8430 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8431 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8432 | } | |
8433 | ||
c0b03411 DV |
8434 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8435 | struct intel_crtc_config *pipe_config, | |
8436 | const char *context) | |
8437 | { | |
8438 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8439 | context, pipe_name(crtc->pipe)); | |
8440 | ||
8441 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8442 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8443 | pipe_config->pipe_bpp, pipe_config->dither); | |
8444 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8445 | pipe_config->has_pch_encoder, | |
8446 | pipe_config->fdi_lanes, | |
8447 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8448 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8449 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8450 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8451 | pipe_config->has_dp_encoder, | |
8452 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8453 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8454 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8455 | DRM_DEBUG_KMS("requested mode:\n"); |
8456 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8457 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8458 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8459 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8460 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8461 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8462 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8463 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8464 | pipe_config->gmch_pfit.control, | |
8465 | pipe_config->gmch_pfit.pgm_ratios, | |
8466 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8467 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8468 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8469 | pipe_config->pch_pfit.size, |
8470 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8471 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8472 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8473 | } |
8474 | ||
accfc0c5 DV |
8475 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8476 | { | |
8477 | int num_encoders = 0; | |
8478 | bool uncloneable_encoders = false; | |
8479 | struct intel_encoder *encoder; | |
8480 | ||
8481 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8482 | base.head) { | |
8483 | if (&encoder->new_crtc->base != crtc) | |
8484 | continue; | |
8485 | ||
8486 | num_encoders++; | |
8487 | if (!encoder->cloneable) | |
8488 | uncloneable_encoders = true; | |
8489 | } | |
8490 | ||
8491 | return !(num_encoders > 1 && uncloneable_encoders); | |
8492 | } | |
8493 | ||
b8cecdf5 DV |
8494 | static struct intel_crtc_config * |
8495 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8496 | struct drm_framebuffer *fb, |
b8cecdf5 | 8497 | struct drm_display_mode *mode) |
ee7b9f93 | 8498 | { |
7758a113 | 8499 | struct drm_device *dev = crtc->dev; |
7758a113 | 8500 | struct intel_encoder *encoder; |
b8cecdf5 | 8501 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
8502 | int plane_bpp, ret = -EINVAL; |
8503 | bool retry = true; | |
ee7b9f93 | 8504 | |
accfc0c5 DV |
8505 | if (!check_encoder_cloning(crtc)) { |
8506 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
8507 | return ERR_PTR(-EINVAL); | |
8508 | } | |
8509 | ||
b8cecdf5 DV |
8510 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8511 | if (!pipe_config) | |
7758a113 DV |
8512 | return ERR_PTR(-ENOMEM); |
8513 | ||
b8cecdf5 DV |
8514 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8515 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 8516 | |
e143a21c DV |
8517 | pipe_config->cpu_transcoder = |
8518 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 8519 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 8520 | |
2960bc9c ID |
8521 | /* |
8522 | * Sanitize sync polarity flags based on requested ones. If neither | |
8523 | * positive or negative polarity is requested, treat this as meaning | |
8524 | * negative polarity. | |
8525 | */ | |
8526 | if (!(pipe_config->adjusted_mode.flags & | |
8527 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
8528 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
8529 | ||
8530 | if (!(pipe_config->adjusted_mode.flags & | |
8531 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
8532 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
8533 | ||
050f7aeb DV |
8534 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8535 | * plane pixel format and any sink constraints into account. Returns the | |
8536 | * source plane bpp so that dithering can be selected on mismatches | |
8537 | * after encoders and crtc also have had their say. */ | |
8538 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
8539 | fb, pipe_config); | |
4e53c2e0 DV |
8540 | if (plane_bpp < 0) |
8541 | goto fail; | |
8542 | ||
e41a56be VS |
8543 | /* |
8544 | * Determine the real pipe dimensions. Note that stereo modes can | |
8545 | * increase the actual pipe size due to the frame doubling and | |
8546 | * insertion of additional space for blanks between the frame. This | |
8547 | * is stored in the crtc timings. We use the requested mode to do this | |
8548 | * computation to clearly distinguish it from the adjusted mode, which | |
8549 | * can be changed by the connectors in the below retry loop. | |
8550 | */ | |
8551 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
8552 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
8553 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
8554 | ||
e29c22c0 | 8555 | encoder_retry: |
ef1b460d | 8556 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 8557 | pipe_config->port_clock = 0; |
ef1b460d | 8558 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 8559 | |
135c81b8 | 8560 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 8561 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 8562 | |
7758a113 DV |
8563 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8564 | * adjust it according to limitations or connector properties, and also | |
8565 | * a chance to reject the mode entirely. | |
47f1c6c9 | 8566 | */ |
7758a113 DV |
8567 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8568 | base.head) { | |
47f1c6c9 | 8569 | |
7758a113 DV |
8570 | if (&encoder->new_crtc->base != crtc) |
8571 | continue; | |
7ae89233 | 8572 | |
efea6e8e DV |
8573 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8574 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
8575 | goto fail; |
8576 | } | |
ee7b9f93 | 8577 | } |
47f1c6c9 | 8578 | |
ff9a6750 DV |
8579 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8580 | * done afterwards in case the encoder adjusts the mode. */ | |
8581 | if (!pipe_config->port_clock) | |
241bfc38 DL |
8582 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
8583 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 8584 | |
a43f6e0f | 8585 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 8586 | if (ret < 0) { |
7758a113 DV |
8587 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8588 | goto fail; | |
ee7b9f93 | 8589 | } |
e29c22c0 DV |
8590 | |
8591 | if (ret == RETRY) { | |
8592 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
8593 | ret = -EINVAL; | |
8594 | goto fail; | |
8595 | } | |
8596 | ||
8597 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
8598 | retry = false; | |
8599 | goto encoder_retry; | |
8600 | } | |
8601 | ||
4e53c2e0 DV |
8602 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8603 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
8604 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
8605 | ||
b8cecdf5 | 8606 | return pipe_config; |
7758a113 | 8607 | fail: |
b8cecdf5 | 8608 | kfree(pipe_config); |
e29c22c0 | 8609 | return ERR_PTR(ret); |
ee7b9f93 | 8610 | } |
47f1c6c9 | 8611 | |
e2e1ed41 DV |
8612 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8613 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
8614 | static void | |
8615 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
8616 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
8617 | { |
8618 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
8619 | struct drm_device *dev = crtc->dev; |
8620 | struct intel_encoder *encoder; | |
8621 | struct intel_connector *connector; | |
8622 | struct drm_crtc *tmp_crtc; | |
79e53945 | 8623 | |
e2e1ed41 | 8624 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 8625 | |
e2e1ed41 DV |
8626 | /* Check which crtcs have changed outputs connected to them, these need |
8627 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
8628 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
8629 | * bit set at most. */ | |
8630 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8631 | base.head) { | |
8632 | if (connector->base.encoder == &connector->new_encoder->base) | |
8633 | continue; | |
79e53945 | 8634 | |
e2e1ed41 DV |
8635 | if (connector->base.encoder) { |
8636 | tmp_crtc = connector->base.encoder->crtc; | |
8637 | ||
8638 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
8639 | } | |
8640 | ||
8641 | if (connector->new_encoder) | |
8642 | *prepare_pipes |= | |
8643 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
8644 | } |
8645 | ||
e2e1ed41 DV |
8646 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8647 | base.head) { | |
8648 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
8649 | continue; | |
8650 | ||
8651 | if (encoder->base.crtc) { | |
8652 | tmp_crtc = encoder->base.crtc; | |
8653 | ||
8654 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
8655 | } | |
8656 | ||
8657 | if (encoder->new_crtc) | |
8658 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
8659 | } |
8660 | ||
e2e1ed41 DV |
8661 | /* Check for any pipes that will be fully disabled ... */ |
8662 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
8663 | base.head) { | |
8664 | bool used = false; | |
22fd0fab | 8665 | |
e2e1ed41 DV |
8666 | /* Don't try to disable disabled crtcs. */ |
8667 | if (!intel_crtc->base.enabled) | |
8668 | continue; | |
7e7d76c3 | 8669 | |
e2e1ed41 DV |
8670 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8671 | base.head) { | |
8672 | if (encoder->new_crtc == intel_crtc) | |
8673 | used = true; | |
8674 | } | |
8675 | ||
8676 | if (!used) | |
8677 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
8678 | } |
8679 | ||
e2e1ed41 DV |
8680 | |
8681 | /* set_mode is also used to update properties on life display pipes. */ | |
8682 | intel_crtc = to_intel_crtc(crtc); | |
8683 | if (crtc->enabled) | |
8684 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
8685 | ||
b6c5164d DV |
8686 | /* |
8687 | * For simplicity do a full modeset on any pipe where the output routing | |
8688 | * changed. We could be more clever, but that would require us to be | |
8689 | * more careful with calling the relevant encoder->mode_set functions. | |
8690 | */ | |
e2e1ed41 DV |
8691 | if (*prepare_pipes) |
8692 | *modeset_pipes = *prepare_pipes; | |
8693 | ||
8694 | /* ... and mask these out. */ | |
8695 | *modeset_pipes &= ~(*disable_pipes); | |
8696 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
8697 | |
8698 | /* | |
8699 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
8700 | * obies this rule, but the modeset restore mode of | |
8701 | * intel_modeset_setup_hw_state does not. | |
8702 | */ | |
8703 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
8704 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
8705 | |
8706 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
8707 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 8708 | } |
79e53945 | 8709 | |
ea9d758d | 8710 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 8711 | { |
ea9d758d | 8712 | struct drm_encoder *encoder; |
f6e5b160 | 8713 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 8714 | |
ea9d758d DV |
8715 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8716 | if (encoder->crtc == crtc) | |
8717 | return true; | |
8718 | ||
8719 | return false; | |
8720 | } | |
8721 | ||
8722 | static void | |
8723 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
8724 | { | |
8725 | struct intel_encoder *intel_encoder; | |
8726 | struct intel_crtc *intel_crtc; | |
8727 | struct drm_connector *connector; | |
8728 | ||
8729 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
8730 | base.head) { | |
8731 | if (!intel_encoder->base.crtc) | |
8732 | continue; | |
8733 | ||
8734 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
8735 | ||
8736 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
8737 | intel_encoder->connectors_active = false; | |
8738 | } | |
8739 | ||
8740 | intel_modeset_commit_output_state(dev); | |
8741 | ||
8742 | /* Update computed state. */ | |
8743 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
8744 | base.head) { | |
8745 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
8746 | } | |
8747 | ||
8748 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
8749 | if (!connector->encoder || !connector->encoder->crtc) | |
8750 | continue; | |
8751 | ||
8752 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
8753 | ||
8754 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
8755 | struct drm_property *dpms_property = |
8756 | dev->mode_config.dpms_property; | |
8757 | ||
ea9d758d | 8758 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 8759 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
8760 | dpms_property, |
8761 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
8762 | |
8763 | intel_encoder = to_intel_encoder(connector->encoder); | |
8764 | intel_encoder->connectors_active = true; | |
8765 | } | |
8766 | } | |
8767 | ||
8768 | } | |
8769 | ||
3bd26263 | 8770 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 8771 | { |
3bd26263 | 8772 | int diff; |
f1f644dc JB |
8773 | |
8774 | if (clock1 == clock2) | |
8775 | return true; | |
8776 | ||
8777 | if (!clock1 || !clock2) | |
8778 | return false; | |
8779 | ||
8780 | diff = abs(clock1 - clock2); | |
8781 | ||
8782 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
8783 | return true; | |
8784 | ||
8785 | return false; | |
8786 | } | |
8787 | ||
25c5b266 DV |
8788 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8789 | list_for_each_entry((intel_crtc), \ | |
8790 | &(dev)->mode_config.crtc_list, \ | |
8791 | base.head) \ | |
0973f18f | 8792 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 8793 | |
0e8ffe1b | 8794 | static bool |
2fa2fe9a DV |
8795 | intel_pipe_config_compare(struct drm_device *dev, |
8796 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
8797 | struct intel_crtc_config *pipe_config) |
8798 | { | |
66e985c0 DV |
8799 | #define PIPE_CONF_CHECK_X(name) \ |
8800 | if (current_config->name != pipe_config->name) { \ | |
8801 | DRM_ERROR("mismatch in " #name " " \ | |
8802 | "(expected 0x%08x, found 0x%08x)\n", \ | |
8803 | current_config->name, \ | |
8804 | pipe_config->name); \ | |
8805 | return false; \ | |
8806 | } | |
8807 | ||
08a24034 DV |
8808 | #define PIPE_CONF_CHECK_I(name) \ |
8809 | if (current_config->name != pipe_config->name) { \ | |
8810 | DRM_ERROR("mismatch in " #name " " \ | |
8811 | "(expected %i, found %i)\n", \ | |
8812 | current_config->name, \ | |
8813 | pipe_config->name); \ | |
8814 | return false; \ | |
88adfff1 DV |
8815 | } |
8816 | ||
1bd1bd80 DV |
8817 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8818 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 8819 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
8820 | "(expected %i, found %i)\n", \ |
8821 | current_config->name & (mask), \ | |
8822 | pipe_config->name & (mask)); \ | |
8823 | return false; \ | |
8824 | } | |
8825 | ||
5e550656 VS |
8826 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
8827 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
8828 | DRM_ERROR("mismatch in " #name " " \ | |
8829 | "(expected %i, found %i)\n", \ | |
8830 | current_config->name, \ | |
8831 | pipe_config->name); \ | |
8832 | return false; \ | |
8833 | } | |
8834 | ||
bb760063 DV |
8835 | #define PIPE_CONF_QUIRK(quirk) \ |
8836 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
8837 | ||
eccb140b DV |
8838 | PIPE_CONF_CHECK_I(cpu_transcoder); |
8839 | ||
08a24034 DV |
8840 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8841 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
8842 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8843 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
8844 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
8845 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
8846 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 8847 | |
eb14cb74 VS |
8848 | PIPE_CONF_CHECK_I(has_dp_encoder); |
8849 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
8850 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
8851 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
8852 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
8853 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
8854 | ||
1bd1bd80 DV |
8855 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8856 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
8857 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
8858 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
8859 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
8860 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
8861 | ||
8862 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
8863 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
8864 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
8865 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
8866 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
8867 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
8868 | ||
c93f54cf | 8869 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 8870 | |
1bd1bd80 DV |
8871 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8872 | DRM_MODE_FLAG_INTERLACE); | |
8873 | ||
bb760063 DV |
8874 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
8875 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8876 | DRM_MODE_FLAG_PHSYNC); | |
8877 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8878 | DRM_MODE_FLAG_NHSYNC); | |
8879 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8880 | DRM_MODE_FLAG_PVSYNC); | |
8881 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8882 | DRM_MODE_FLAG_NVSYNC); | |
8883 | } | |
045ac3b5 | 8884 | |
37327abd VS |
8885 | PIPE_CONF_CHECK_I(pipe_src_w); |
8886 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 8887 | |
2fa2fe9a DV |
8888 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8889 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
8890 | if (INTEL_INFO(dev)->gen < 4) | |
8891 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
8892 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
8893 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
8894 | if (current_config->pch_pfit.enabled) { | |
8895 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
8896 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
8897 | } | |
2fa2fe9a | 8898 | |
42db64ef PZ |
8899 | PIPE_CONF_CHECK_I(ips_enabled); |
8900 | ||
282740f7 VS |
8901 | PIPE_CONF_CHECK_I(double_wide); |
8902 | ||
c0d43d62 | 8903 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 8904 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 8905 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
8906 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8907 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 8908 | |
42571aef VS |
8909 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
8910 | PIPE_CONF_CHECK_I(pipe_bpp); | |
8911 | ||
d71b8d4a | 8912 | if (!IS_HASWELL(dev)) { |
241bfc38 | 8913 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
d71b8d4a VS |
8914 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
8915 | } | |
5e550656 | 8916 | |
66e985c0 | 8917 | #undef PIPE_CONF_CHECK_X |
08a24034 | 8918 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 8919 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 8920 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 8921 | #undef PIPE_CONF_QUIRK |
88adfff1 | 8922 | |
0e8ffe1b DV |
8923 | return true; |
8924 | } | |
8925 | ||
91d1b4bd DV |
8926 | static void |
8927 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 8928 | { |
8af6cf88 DV |
8929 | struct intel_connector *connector; |
8930 | ||
8931 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8932 | base.head) { | |
8933 | /* This also checks the encoder/connector hw state with the | |
8934 | * ->get_hw_state callbacks. */ | |
8935 | intel_connector_check_state(connector); | |
8936 | ||
8937 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
8938 | "connector's staged encoder doesn't match current encoder\n"); | |
8939 | } | |
91d1b4bd DV |
8940 | } |
8941 | ||
8942 | static void | |
8943 | check_encoder_state(struct drm_device *dev) | |
8944 | { | |
8945 | struct intel_encoder *encoder; | |
8946 | struct intel_connector *connector; | |
8af6cf88 DV |
8947 | |
8948 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8949 | base.head) { | |
8950 | bool enabled = false; | |
8951 | bool active = false; | |
8952 | enum pipe pipe, tracked_pipe; | |
8953 | ||
8954 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
8955 | encoder->base.base.id, | |
8956 | drm_get_encoder_name(&encoder->base)); | |
8957 | ||
8958 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
8959 | "encoder's stage crtc doesn't match current crtc\n"); | |
8960 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
8961 | "encoder's active_connectors set, but no crtc\n"); | |
8962 | ||
8963 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8964 | base.head) { | |
8965 | if (connector->base.encoder != &encoder->base) | |
8966 | continue; | |
8967 | enabled = true; | |
8968 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
8969 | active = true; | |
8970 | } | |
8971 | WARN(!!encoder->base.crtc != enabled, | |
8972 | "encoder's enabled state mismatch " | |
8973 | "(expected %i, found %i)\n", | |
8974 | !!encoder->base.crtc, enabled); | |
8975 | WARN(active && !encoder->base.crtc, | |
8976 | "active encoder with no crtc\n"); | |
8977 | ||
8978 | WARN(encoder->connectors_active != active, | |
8979 | "encoder's computed active state doesn't match tracked active state " | |
8980 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
8981 | ||
8982 | active = encoder->get_hw_state(encoder, &pipe); | |
8983 | WARN(active != encoder->connectors_active, | |
8984 | "encoder's hw state doesn't match sw tracking " | |
8985 | "(expected %i, found %i)\n", | |
8986 | encoder->connectors_active, active); | |
8987 | ||
8988 | if (!encoder->base.crtc) | |
8989 | continue; | |
8990 | ||
8991 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
8992 | WARN(active && pipe != tracked_pipe, | |
8993 | "active encoder's pipe doesn't match" | |
8994 | "(expected %i, found %i)\n", | |
8995 | tracked_pipe, pipe); | |
8996 | ||
8997 | } | |
91d1b4bd DV |
8998 | } |
8999 | ||
9000 | static void | |
9001 | check_crtc_state(struct drm_device *dev) | |
9002 | { | |
9003 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9004 | struct intel_crtc *crtc; | |
9005 | struct intel_encoder *encoder; | |
9006 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9007 | |
9008 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9009 | base.head) { | |
9010 | bool enabled = false; | |
9011 | bool active = false; | |
9012 | ||
045ac3b5 JB |
9013 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9014 | ||
8af6cf88 DV |
9015 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9016 | crtc->base.base.id); | |
9017 | ||
9018 | WARN(crtc->active && !crtc->base.enabled, | |
9019 | "active crtc, but not enabled in sw tracking\n"); | |
9020 | ||
9021 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9022 | base.head) { | |
9023 | if (encoder->base.crtc != &crtc->base) | |
9024 | continue; | |
9025 | enabled = true; | |
9026 | if (encoder->connectors_active) | |
9027 | active = true; | |
9028 | } | |
6c49f241 | 9029 | |
8af6cf88 DV |
9030 | WARN(active != crtc->active, |
9031 | "crtc's computed active state doesn't match tracked active state " | |
9032 | "(expected %i, found %i)\n", active, crtc->active); | |
9033 | WARN(enabled != crtc->base.enabled, | |
9034 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9035 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9036 | ||
0e8ffe1b DV |
9037 | active = dev_priv->display.get_pipe_config(crtc, |
9038 | &pipe_config); | |
d62cf62a DV |
9039 | |
9040 | /* hw state is inconsistent with the pipe A quirk */ | |
9041 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9042 | active = crtc->active; | |
9043 | ||
6c49f241 DV |
9044 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9045 | base.head) { | |
3eaba51c | 9046 | enum pipe pipe; |
6c49f241 DV |
9047 | if (encoder->base.crtc != &crtc->base) |
9048 | continue; | |
3eaba51c VS |
9049 | if (encoder->get_config && |
9050 | encoder->get_hw_state(encoder, &pipe)) | |
6c49f241 DV |
9051 | encoder->get_config(encoder, &pipe_config); |
9052 | } | |
9053 | ||
0e8ffe1b DV |
9054 | WARN(crtc->active != active, |
9055 | "crtc active state doesn't match with hw state " | |
9056 | "(expected %i, found %i)\n", crtc->active, active); | |
9057 | ||
c0b03411 DV |
9058 | if (active && |
9059 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9060 | WARN(1, "pipe state doesn't match!\n"); | |
9061 | intel_dump_pipe_config(crtc, &pipe_config, | |
9062 | "[hw state]"); | |
9063 | intel_dump_pipe_config(crtc, &crtc->config, | |
9064 | "[sw state]"); | |
9065 | } | |
8af6cf88 DV |
9066 | } |
9067 | } | |
9068 | ||
91d1b4bd DV |
9069 | static void |
9070 | check_shared_dpll_state(struct drm_device *dev) | |
9071 | { | |
9072 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9073 | struct intel_crtc *crtc; | |
9074 | struct intel_dpll_hw_state dpll_hw_state; | |
9075 | int i; | |
5358901f DV |
9076 | |
9077 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9078 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9079 | int enabled_crtcs = 0, active_crtcs = 0; | |
9080 | bool active; | |
9081 | ||
9082 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9083 | ||
9084 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9085 | ||
9086 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9087 | ||
9088 | WARN(pll->active > pll->refcount, | |
9089 | "more active pll users than references: %i vs %i\n", | |
9090 | pll->active, pll->refcount); | |
9091 | WARN(pll->active && !pll->on, | |
9092 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9093 | WARN(pll->on && !pll->active, |
9094 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9095 | WARN(pll->on != active, |
9096 | "pll on state mismatch (expected %i, found %i)\n", | |
9097 | pll->on, active); | |
9098 | ||
9099 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9100 | base.head) { | |
9101 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9102 | enabled_crtcs++; | |
9103 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9104 | active_crtcs++; | |
9105 | } | |
9106 | WARN(pll->active != active_crtcs, | |
9107 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9108 | pll->active, active_crtcs); | |
9109 | WARN(pll->refcount != enabled_crtcs, | |
9110 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9111 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9112 | |
9113 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9114 | sizeof(dpll_hw_state)), | |
9115 | "pll hw state mismatch\n"); | |
5358901f | 9116 | } |
8af6cf88 DV |
9117 | } |
9118 | ||
91d1b4bd DV |
9119 | void |
9120 | intel_modeset_check_state(struct drm_device *dev) | |
9121 | { | |
9122 | check_connector_state(dev); | |
9123 | check_encoder_state(dev); | |
9124 | check_crtc_state(dev); | |
9125 | check_shared_dpll_state(dev); | |
9126 | } | |
9127 | ||
18442d08 VS |
9128 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9129 | int dotclock) | |
9130 | { | |
9131 | /* | |
9132 | * FDI already provided one idea for the dotclock. | |
9133 | * Yell if the encoder disagrees. | |
9134 | */ | |
241bfc38 | 9135 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9136 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9137 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9138 | } |
9139 | ||
f30da187 DV |
9140 | static int __intel_set_mode(struct drm_crtc *crtc, |
9141 | struct drm_display_mode *mode, | |
9142 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9143 | { |
9144 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9145 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
9146 | struct drm_display_mode *saved_mode, *saved_hwmode; |
9147 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
9148 | struct intel_crtc *intel_crtc; |
9149 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9150 | int ret = 0; |
a6778b3c | 9151 | |
a1e22653 | 9152 | saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9153 | if (!saved_mode) |
9154 | return -ENOMEM; | |
3ac18232 | 9155 | saved_hwmode = saved_mode + 1; |
a6778b3c | 9156 | |
e2e1ed41 | 9157 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9158 | &prepare_pipes, &disable_pipes); |
9159 | ||
3ac18232 TG |
9160 | *saved_hwmode = crtc->hwmode; |
9161 | *saved_mode = crtc->mode; | |
a6778b3c | 9162 | |
25c5b266 DV |
9163 | /* Hack: Because we don't (yet) support global modeset on multiple |
9164 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9165 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9166 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9167 | * changing their mode at the same time. */ | |
25c5b266 | 9168 | if (modeset_pipes) { |
4e53c2e0 | 9169 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9170 | if (IS_ERR(pipe_config)) { |
9171 | ret = PTR_ERR(pipe_config); | |
9172 | pipe_config = NULL; | |
9173 | ||
3ac18232 | 9174 | goto out; |
25c5b266 | 9175 | } |
c0b03411 DV |
9176 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9177 | "[modeset]"); | |
25c5b266 | 9178 | } |
a6778b3c | 9179 | |
460da916 DV |
9180 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9181 | intel_crtc_disable(&intel_crtc->base); | |
9182 | ||
ea9d758d DV |
9183 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9184 | if (intel_crtc->base.enabled) | |
9185 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9186 | } | |
a6778b3c | 9187 | |
6c4c86f5 DV |
9188 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9189 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9190 | */ |
b8cecdf5 | 9191 | if (modeset_pipes) { |
25c5b266 | 9192 | crtc->mode = *mode; |
b8cecdf5 DV |
9193 | /* mode_set/enable/disable functions rely on a correct pipe |
9194 | * config. */ | |
9195 | to_intel_crtc(crtc)->config = *pipe_config; | |
9196 | } | |
7758a113 | 9197 | |
ea9d758d DV |
9198 | /* Only after disabling all output pipelines that will be changed can we |
9199 | * update the the output configuration. */ | |
9200 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9201 | |
47fab737 DV |
9202 | if (dev_priv->display.modeset_global_resources) |
9203 | dev_priv->display.modeset_global_resources(dev); | |
9204 | ||
a6778b3c DV |
9205 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9206 | * on the DPLL. | |
f6e5b160 | 9207 | */ |
25c5b266 | 9208 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9209 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9210 | x, y, fb); |
9211 | if (ret) | |
9212 | goto done; | |
a6778b3c DV |
9213 | } |
9214 | ||
9215 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9216 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9217 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9218 | |
25c5b266 DV |
9219 | if (modeset_pipes) { |
9220 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 9221 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 9222 | |
25c5b266 DV |
9223 | /* Calculate and store various constants which |
9224 | * are later needed by vblank and swap-completion | |
9225 | * timestamping. They are derived from true hwmode. | |
9226 | */ | |
9227 | drm_calc_timestamping_constants(crtc); | |
9228 | } | |
a6778b3c DV |
9229 | |
9230 | /* FIXME: add subpixel order */ | |
9231 | done: | |
c0c36b94 | 9232 | if (ret && crtc->enabled) { |
3ac18232 TG |
9233 | crtc->hwmode = *saved_hwmode; |
9234 | crtc->mode = *saved_mode; | |
a6778b3c DV |
9235 | } |
9236 | ||
3ac18232 | 9237 | out: |
b8cecdf5 | 9238 | kfree(pipe_config); |
3ac18232 | 9239 | kfree(saved_mode); |
a6778b3c | 9240 | return ret; |
f6e5b160 CW |
9241 | } |
9242 | ||
e7457a9a DL |
9243 | static int intel_set_mode(struct drm_crtc *crtc, |
9244 | struct drm_display_mode *mode, | |
9245 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9246 | { |
9247 | int ret; | |
9248 | ||
9249 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9250 | ||
9251 | if (ret == 0) | |
9252 | intel_modeset_check_state(crtc->dev); | |
9253 | ||
9254 | return ret; | |
9255 | } | |
9256 | ||
c0c36b94 CW |
9257 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9258 | { | |
9259 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9260 | } | |
9261 | ||
25c5b266 DV |
9262 | #undef for_each_intel_crtc_masked |
9263 | ||
d9e55608 DV |
9264 | static void intel_set_config_free(struct intel_set_config *config) |
9265 | { | |
9266 | if (!config) | |
9267 | return; | |
9268 | ||
1aa4b628 DV |
9269 | kfree(config->save_connector_encoders); |
9270 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
9271 | kfree(config); |
9272 | } | |
9273 | ||
85f9eb71 DV |
9274 | static int intel_set_config_save_state(struct drm_device *dev, |
9275 | struct intel_set_config *config) | |
9276 | { | |
85f9eb71 DV |
9277 | struct drm_encoder *encoder; |
9278 | struct drm_connector *connector; | |
9279 | int count; | |
9280 | ||
1aa4b628 DV |
9281 | config->save_encoder_crtcs = |
9282 | kcalloc(dev->mode_config.num_encoder, | |
9283 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9284 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9285 | return -ENOMEM; |
9286 | ||
1aa4b628 DV |
9287 | config->save_connector_encoders = |
9288 | kcalloc(dev->mode_config.num_connector, | |
9289 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9290 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9291 | return -ENOMEM; |
9292 | ||
9293 | /* Copy data. Note that driver private data is not affected. | |
9294 | * Should anything bad happen only the expected state is | |
9295 | * restored, not the drivers personal bookkeeping. | |
9296 | */ | |
85f9eb71 DV |
9297 | count = 0; |
9298 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9299 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9300 | } |
9301 | ||
9302 | count = 0; | |
9303 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9304 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9305 | } |
9306 | ||
9307 | return 0; | |
9308 | } | |
9309 | ||
9310 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9311 | struct intel_set_config *config) | |
9312 | { | |
9a935856 DV |
9313 | struct intel_encoder *encoder; |
9314 | struct intel_connector *connector; | |
85f9eb71 DV |
9315 | int count; |
9316 | ||
85f9eb71 | 9317 | count = 0; |
9a935856 DV |
9318 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9319 | encoder->new_crtc = | |
9320 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9321 | } |
9322 | ||
9323 | count = 0; | |
9a935856 DV |
9324 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9325 | connector->new_encoder = | |
9326 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9327 | } |
9328 | } | |
9329 | ||
e3de42b6 | 9330 | static bool |
2e57f47d | 9331 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9332 | { |
9333 | int i; | |
9334 | ||
2e57f47d CW |
9335 | if (set->num_connectors == 0) |
9336 | return false; | |
9337 | ||
9338 | if (WARN_ON(set->connectors == NULL)) | |
9339 | return false; | |
9340 | ||
9341 | for (i = 0; i < set->num_connectors; i++) | |
9342 | if (set->connectors[i]->encoder && | |
9343 | set->connectors[i]->encoder->crtc == set->crtc && | |
9344 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9345 | return true; |
9346 | ||
9347 | return false; | |
9348 | } | |
9349 | ||
5e2b584e DV |
9350 | static void |
9351 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9352 | struct intel_set_config *config) | |
9353 | { | |
9354 | ||
9355 | /* We should be able to check here if the fb has the same properties | |
9356 | * and then just flip_or_move it */ | |
2e57f47d CW |
9357 | if (is_crtc_connector_off(set)) { |
9358 | config->mode_changed = true; | |
e3de42b6 | 9359 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9360 | /* If we have no fb then treat it as a full mode set */ |
9361 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9362 | struct intel_crtc *intel_crtc = |
9363 | to_intel_crtc(set->crtc); | |
9364 | ||
9365 | if (intel_crtc->active && i915_fastboot) { | |
9366 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); | |
9367 | config->fb_changed = true; | |
9368 | } else { | |
9369 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9370 | config->mode_changed = true; | |
9371 | } | |
5e2b584e DV |
9372 | } else if (set->fb == NULL) { |
9373 | config->mode_changed = true; | |
72f4901e DV |
9374 | } else if (set->fb->pixel_format != |
9375 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9376 | config->mode_changed = true; |
e3de42b6 | 9377 | } else { |
5e2b584e | 9378 | config->fb_changed = true; |
e3de42b6 | 9379 | } |
5e2b584e DV |
9380 | } |
9381 | ||
835c5873 | 9382 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9383 | config->fb_changed = true; |
9384 | ||
9385 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9386 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9387 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9388 | drm_mode_debug_printmodeline(set->mode); | |
9389 | config->mode_changed = true; | |
9390 | } | |
a1d95703 CW |
9391 | |
9392 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9393 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9394 | } |
9395 | ||
2e431051 | 9396 | static int |
9a935856 DV |
9397 | intel_modeset_stage_output_state(struct drm_device *dev, |
9398 | struct drm_mode_set *set, | |
9399 | struct intel_set_config *config) | |
50f56119 | 9400 | { |
85f9eb71 | 9401 | struct drm_crtc *new_crtc; |
9a935856 DV |
9402 | struct intel_connector *connector; |
9403 | struct intel_encoder *encoder; | |
f3f08572 | 9404 | int ro; |
50f56119 | 9405 | |
9abdda74 | 9406 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9407 | * of connectors. For paranoia, double-check this. */ |
9408 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9409 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9410 | ||
9a935856 DV |
9411 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9412 | base.head) { | |
9413 | /* Otherwise traverse passed in connector list and get encoders | |
9414 | * for them. */ | |
50f56119 | 9415 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9416 | if (set->connectors[ro] == &connector->base) { |
9417 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9418 | break; |
9419 | } | |
9420 | } | |
9421 | ||
9a935856 DV |
9422 | /* If we disable the crtc, disable all its connectors. Also, if |
9423 | * the connector is on the changing crtc but not on the new | |
9424 | * connector list, disable it. */ | |
9425 | if ((!set->fb || ro == set->num_connectors) && | |
9426 | connector->base.encoder && | |
9427 | connector->base.encoder->crtc == set->crtc) { | |
9428 | connector->new_encoder = NULL; | |
9429 | ||
9430 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9431 | connector->base.base.id, | |
9432 | drm_get_connector_name(&connector->base)); | |
9433 | } | |
9434 | ||
9435 | ||
9436 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9437 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9438 | config->mode_changed = true; |
50f56119 DV |
9439 | } |
9440 | } | |
9a935856 | 9441 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9442 | |
9a935856 | 9443 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9444 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9445 | base.head) { | |
9446 | if (!connector->new_encoder) | |
50f56119 DV |
9447 | continue; |
9448 | ||
9a935856 | 9449 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9450 | |
9451 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9452 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9453 | new_crtc = set->crtc; |
9454 | } | |
9455 | ||
9456 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
9457 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9458 | new_crtc)) { | |
5e2b584e | 9459 | return -EINVAL; |
50f56119 | 9460 | } |
9a935856 DV |
9461 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9462 | ||
9463 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9464 | connector->base.base.id, | |
9465 | drm_get_connector_name(&connector->base), | |
9466 | new_crtc->base.id); | |
9467 | } | |
9468 | ||
9469 | /* Check for any encoders that needs to be disabled. */ | |
9470 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9471 | base.head) { | |
9472 | list_for_each_entry(connector, | |
9473 | &dev->mode_config.connector_list, | |
9474 | base.head) { | |
9475 | if (connector->new_encoder == encoder) { | |
9476 | WARN_ON(!connector->new_encoder->new_crtc); | |
9477 | ||
9478 | goto next_encoder; | |
9479 | } | |
9480 | } | |
9481 | encoder->new_crtc = NULL; | |
9482 | next_encoder: | |
9483 | /* Only now check for crtc changes so we don't miss encoders | |
9484 | * that will be disabled. */ | |
9485 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 9486 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 9487 | config->mode_changed = true; |
50f56119 DV |
9488 | } |
9489 | } | |
9a935856 | 9490 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 9491 | |
2e431051 DV |
9492 | return 0; |
9493 | } | |
9494 | ||
9495 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
9496 | { | |
9497 | struct drm_device *dev; | |
2e431051 DV |
9498 | struct drm_mode_set save_set; |
9499 | struct intel_set_config *config; | |
9500 | int ret; | |
2e431051 | 9501 | |
8d3e375e DV |
9502 | BUG_ON(!set); |
9503 | BUG_ON(!set->crtc); | |
9504 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 9505 | |
7e53f3a4 DV |
9506 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9507 | BUG_ON(!set->mode && set->fb); | |
9508 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 9509 | |
2e431051 DV |
9510 | if (set->fb) { |
9511 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
9512 | set->crtc->base.id, set->fb->base.id, | |
9513 | (int)set->num_connectors, set->x, set->y); | |
9514 | } else { | |
9515 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
9516 | } |
9517 | ||
9518 | dev = set->crtc->dev; | |
9519 | ||
9520 | ret = -ENOMEM; | |
9521 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
9522 | if (!config) | |
9523 | goto out_config; | |
9524 | ||
9525 | ret = intel_set_config_save_state(dev, config); | |
9526 | if (ret) | |
9527 | goto out_config; | |
9528 | ||
9529 | save_set.crtc = set->crtc; | |
9530 | save_set.mode = &set->crtc->mode; | |
9531 | save_set.x = set->crtc->x; | |
9532 | save_set.y = set->crtc->y; | |
9533 | save_set.fb = set->crtc->fb; | |
9534 | ||
9535 | /* Compute whether we need a full modeset, only an fb base update or no | |
9536 | * change at all. In the future we might also check whether only the | |
9537 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
9538 | * such cases. */ | |
9539 | intel_set_config_compute_mode_changes(set, config); | |
9540 | ||
9a935856 | 9541 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
9542 | if (ret) |
9543 | goto fail; | |
9544 | ||
5e2b584e | 9545 | if (config->mode_changed) { |
c0c36b94 CW |
9546 | ret = intel_set_mode(set->crtc, set->mode, |
9547 | set->x, set->y, set->fb); | |
5e2b584e | 9548 | } else if (config->fb_changed) { |
4878cae2 VS |
9549 | intel_crtc_wait_for_pending_flips(set->crtc); |
9550 | ||
4f660f49 | 9551 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 9552 | set->x, set->y, set->fb); |
50f56119 DV |
9553 | } |
9554 | ||
2d05eae1 | 9555 | if (ret) { |
bf67dfeb DV |
9556 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9557 | set->crtc->base.id, ret); | |
50f56119 | 9558 | fail: |
2d05eae1 | 9559 | intel_set_config_restore_state(dev, config); |
50f56119 | 9560 | |
2d05eae1 CW |
9561 | /* Try to restore the config */ |
9562 | if (config->mode_changed && | |
9563 | intel_set_mode(save_set.crtc, save_set.mode, | |
9564 | save_set.x, save_set.y, save_set.fb)) | |
9565 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
9566 | } | |
50f56119 | 9567 | |
d9e55608 DV |
9568 | out_config: |
9569 | intel_set_config_free(config); | |
50f56119 DV |
9570 | return ret; |
9571 | } | |
f6e5b160 CW |
9572 | |
9573 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
9574 | .cursor_set = intel_crtc_cursor_set, |
9575 | .cursor_move = intel_crtc_cursor_move, | |
9576 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 9577 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
9578 | .destroy = intel_crtc_destroy, |
9579 | .page_flip = intel_crtc_page_flip, | |
9580 | }; | |
9581 | ||
79f689aa PZ |
9582 | static void intel_cpu_pll_init(struct drm_device *dev) |
9583 | { | |
affa9354 | 9584 | if (HAS_DDI(dev)) |
79f689aa PZ |
9585 | intel_ddi_pll_init(dev); |
9586 | } | |
9587 | ||
5358901f DV |
9588 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9589 | struct intel_shared_dpll *pll, | |
9590 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 9591 | { |
5358901f | 9592 | uint32_t val; |
ee7b9f93 | 9593 | |
5358901f | 9594 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
9595 | hw_state->dpll = val; |
9596 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
9597 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
9598 | |
9599 | return val & DPLL_VCO_ENABLE; | |
9600 | } | |
9601 | ||
15bdd4cf DV |
9602 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
9603 | struct intel_shared_dpll *pll) | |
9604 | { | |
9605 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
9606 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
9607 | } | |
9608 | ||
e7b903d2 DV |
9609 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9610 | struct intel_shared_dpll *pll) | |
9611 | { | |
e7b903d2 DV |
9612 | /* PCH refclock must be enabled first */ |
9613 | assert_pch_refclk_enabled(dev_priv); | |
9614 | ||
15bdd4cf DV |
9615 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9616 | ||
9617 | /* Wait for the clocks to stabilize. */ | |
9618 | POSTING_READ(PCH_DPLL(pll->id)); | |
9619 | udelay(150); | |
9620 | ||
9621 | /* The pixel multiplier can only be updated once the | |
9622 | * DPLL is enabled and the clocks are stable. | |
9623 | * | |
9624 | * So write it again. | |
9625 | */ | |
9626 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
9627 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
9628 | udelay(200); |
9629 | } | |
9630 | ||
9631 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
9632 | struct intel_shared_dpll *pll) | |
9633 | { | |
9634 | struct drm_device *dev = dev_priv->dev; | |
9635 | struct intel_crtc *crtc; | |
e7b903d2 DV |
9636 | |
9637 | /* Make sure no transcoder isn't still depending on us. */ | |
9638 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9639 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
9640 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
9641 | } |
9642 | ||
15bdd4cf DV |
9643 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9644 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
9645 | udelay(200); |
9646 | } | |
9647 | ||
46edb027 DV |
9648 | static char *ibx_pch_dpll_names[] = { |
9649 | "PCH DPLL A", | |
9650 | "PCH DPLL B", | |
9651 | }; | |
9652 | ||
7c74ade1 | 9653 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 9654 | { |
e7b903d2 | 9655 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
9656 | int i; |
9657 | ||
7c74ade1 | 9658 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 9659 | |
e72f9fbf | 9660 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
9661 | dev_priv->shared_dplls[i].id = i; |
9662 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 9663 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
9664 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
9665 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
9666 | dev_priv->shared_dplls[i].get_hw_state = |
9667 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
9668 | } |
9669 | } | |
9670 | ||
7c74ade1 DV |
9671 | static void intel_shared_dpll_init(struct drm_device *dev) |
9672 | { | |
e7b903d2 | 9673 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
9674 | |
9675 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
9676 | ibx_pch_dpll_init(dev); | |
9677 | else | |
9678 | dev_priv->num_shared_dpll = 0; | |
9679 | ||
9680 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
9681 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", | |
9682 | dev_priv->num_shared_dpll); | |
9683 | } | |
9684 | ||
b358d0a6 | 9685 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 9686 | { |
22fd0fab | 9687 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
9688 | struct intel_crtc *intel_crtc; |
9689 | int i; | |
9690 | ||
955382f3 | 9691 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
9692 | if (intel_crtc == NULL) |
9693 | return; | |
9694 | ||
9695 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
9696 | ||
9697 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
9698 | for (i = 0; i < 256; i++) { |
9699 | intel_crtc->lut_r[i] = i; | |
9700 | intel_crtc->lut_g[i] = i; | |
9701 | intel_crtc->lut_b[i] = i; | |
9702 | } | |
9703 | ||
80824003 JB |
9704 | /* Swap pipes & planes for FBC on pre-965 */ |
9705 | intel_crtc->pipe = pipe; | |
9706 | intel_crtc->plane = pipe; | |
e2e767ab | 9707 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 9708 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 9709 | intel_crtc->plane = !pipe; |
80824003 JB |
9710 | } |
9711 | ||
22fd0fab JB |
9712 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9713 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
9714 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
9715 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
9716 | ||
79e53945 | 9717 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
9718 | } |
9719 | ||
08d7b3d1 | 9720 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 9721 | struct drm_file *file) |
08d7b3d1 | 9722 | { |
08d7b3d1 | 9723 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
9724 | struct drm_mode_object *drmmode_obj; |
9725 | struct intel_crtc *crtc; | |
08d7b3d1 | 9726 | |
1cff8f6b DV |
9727 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9728 | return -ENODEV; | |
08d7b3d1 | 9729 | |
c05422d5 DV |
9730 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9731 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 9732 | |
c05422d5 | 9733 | if (!drmmode_obj) { |
08d7b3d1 CW |
9734 | DRM_ERROR("no such CRTC id\n"); |
9735 | return -EINVAL; | |
9736 | } | |
9737 | ||
c05422d5 DV |
9738 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9739 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 9740 | |
c05422d5 | 9741 | return 0; |
08d7b3d1 CW |
9742 | } |
9743 | ||
66a9278e | 9744 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 9745 | { |
66a9278e DV |
9746 | struct drm_device *dev = encoder->base.dev; |
9747 | struct intel_encoder *source_encoder; | |
79e53945 | 9748 | int index_mask = 0; |
79e53945 JB |
9749 | int entry = 0; |
9750 | ||
66a9278e DV |
9751 | list_for_each_entry(source_encoder, |
9752 | &dev->mode_config.encoder_list, base.head) { | |
9753 | ||
9754 | if (encoder == source_encoder) | |
79e53945 | 9755 | index_mask |= (1 << entry); |
66a9278e DV |
9756 | |
9757 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
9758 | if (encoder->cloneable && source_encoder->cloneable) | |
9759 | index_mask |= (1 << entry); | |
9760 | ||
79e53945 JB |
9761 | entry++; |
9762 | } | |
4ef69c7a | 9763 | |
79e53945 JB |
9764 | return index_mask; |
9765 | } | |
9766 | ||
4d302442 CW |
9767 | static bool has_edp_a(struct drm_device *dev) |
9768 | { | |
9769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9770 | ||
9771 | if (!IS_MOBILE(dev)) | |
9772 | return false; | |
9773 | ||
9774 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
9775 | return false; | |
9776 | ||
9777 | if (IS_GEN5(dev) && | |
9778 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
9779 | return false; | |
9780 | ||
9781 | return true; | |
9782 | } | |
9783 | ||
79e53945 JB |
9784 | static void intel_setup_outputs(struct drm_device *dev) |
9785 | { | |
725e30ad | 9786 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 9787 | struct intel_encoder *encoder; |
cb0953d7 | 9788 | bool dpd_is_edp = false; |
79e53945 | 9789 | |
c9093354 | 9790 | intel_lvds_init(dev); |
79e53945 | 9791 | |
c40c0f5b | 9792 | if (!IS_ULT(dev)) |
79935fca | 9793 | intel_crt_init(dev); |
cb0953d7 | 9794 | |
affa9354 | 9795 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
9796 | int found; |
9797 | ||
9798 | /* Haswell uses DDI functions to detect digital outputs */ | |
9799 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
9800 | /* DDI A only supports eDP */ | |
9801 | if (found) | |
9802 | intel_ddi_init(dev, PORT_A); | |
9803 | ||
9804 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
9805 | * register */ | |
9806 | found = I915_READ(SFUSE_STRAP); | |
9807 | ||
9808 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
9809 | intel_ddi_init(dev, PORT_B); | |
9810 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
9811 | intel_ddi_init(dev, PORT_C); | |
9812 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
9813 | intel_ddi_init(dev, PORT_D); | |
9814 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 9815 | int found; |
270b3042 DV |
9816 | dpd_is_edp = intel_dpd_is_edp(dev); |
9817 | ||
9818 | if (has_edp_a(dev)) | |
9819 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 9820 | |
dc0fa718 | 9821 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 9822 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 9823 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 9824 | if (!found) |
e2debe91 | 9825 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 9826 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 9827 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
9828 | } |
9829 | ||
dc0fa718 | 9830 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 9831 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 9832 | |
dc0fa718 | 9833 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 9834 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 9835 | |
5eb08b69 | 9836 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 9837 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 9838 | |
270b3042 | 9839 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 9840 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 9841 | } else if (IS_VALLEYVIEW(dev)) { |
19c03924 | 9842 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
6f6005a5 JB |
9843 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9844 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
9845 | PORT_C); | |
9846 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
9847 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | |
9848 | PORT_C); | |
9849 | } | |
19c03924 | 9850 | |
dc0fa718 | 9851 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
e2debe91 PZ |
9852 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9853 | PORT_B); | |
67cfc203 VS |
9854 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9855 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
4a87d65d | 9856 | } |
3cfca973 JN |
9857 | |
9858 | intel_dsi_init(dev); | |
103a196f | 9859 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 9860 | bool found = false; |
7d57382e | 9861 | |
e2debe91 | 9862 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 9863 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 9864 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
9865 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9866 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 9867 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 9868 | } |
27185ae1 | 9869 | |
e7281eab | 9870 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 9871 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 9872 | } |
13520b05 KH |
9873 | |
9874 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 9875 | |
e2debe91 | 9876 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 9877 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 9878 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 9879 | } |
27185ae1 | 9880 | |
e2debe91 | 9881 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 9882 | |
b01f2c3a JB |
9883 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9884 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 9885 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 9886 | } |
e7281eab | 9887 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 9888 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 9889 | } |
27185ae1 | 9890 | |
b01f2c3a | 9891 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 9892 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 9893 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 9894 | } else if (IS_GEN2(dev)) |
79e53945 JB |
9895 | intel_dvo_init(dev); |
9896 | ||
103a196f | 9897 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
9898 | intel_tv_init(dev); |
9899 | ||
4ef69c7a CW |
9900 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9901 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
9902 | encoder->base.possible_clones = | |
66a9278e | 9903 | intel_encoder_clones(encoder); |
79e53945 | 9904 | } |
47356eb6 | 9905 | |
dde86e2d | 9906 | intel_init_pch_refclk(dev); |
270b3042 DV |
9907 | |
9908 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
9909 | } |
9910 | ||
ddfe1567 CW |
9911 | void intel_framebuffer_fini(struct intel_framebuffer *fb) |
9912 | { | |
9913 | drm_framebuffer_cleanup(&fb->base); | |
9914 | drm_gem_object_unreference_unlocked(&fb->obj->base); | |
9915 | } | |
9916 | ||
79e53945 JB |
9917 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
9918 | { | |
9919 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 9920 | |
ddfe1567 | 9921 | intel_framebuffer_fini(intel_fb); |
79e53945 JB |
9922 | kfree(intel_fb); |
9923 | } | |
9924 | ||
9925 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 9926 | struct drm_file *file, |
79e53945 JB |
9927 | unsigned int *handle) |
9928 | { | |
9929 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 9930 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 9931 | |
05394f39 | 9932 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
9933 | } |
9934 | ||
9935 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
9936 | .destroy = intel_user_framebuffer_destroy, | |
9937 | .create_handle = intel_user_framebuffer_create_handle, | |
9938 | }; | |
9939 | ||
38651674 DA |
9940 | int intel_framebuffer_init(struct drm_device *dev, |
9941 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 9942 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 9943 | struct drm_i915_gem_object *obj) |
79e53945 | 9944 | { |
a35cdaa0 | 9945 | int pitch_limit; |
79e53945 JB |
9946 | int ret; |
9947 | ||
c16ed4be CW |
9948 | if (obj->tiling_mode == I915_TILING_Y) { |
9949 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 9950 | return -EINVAL; |
c16ed4be | 9951 | } |
57cd6508 | 9952 | |
c16ed4be CW |
9953 | if (mode_cmd->pitches[0] & 63) { |
9954 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
9955 | mode_cmd->pitches[0]); | |
57cd6508 | 9956 | return -EINVAL; |
c16ed4be | 9957 | } |
57cd6508 | 9958 | |
a35cdaa0 CW |
9959 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9960 | pitch_limit = 32*1024; | |
9961 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
9962 | if (obj->tiling_mode) | |
9963 | pitch_limit = 16*1024; | |
9964 | else | |
9965 | pitch_limit = 32*1024; | |
9966 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
9967 | if (obj->tiling_mode) | |
9968 | pitch_limit = 8*1024; | |
9969 | else | |
9970 | pitch_limit = 16*1024; | |
9971 | } else | |
9972 | /* XXX DSPC is limited to 4k tiled */ | |
9973 | pitch_limit = 8*1024; | |
9974 | ||
9975 | if (mode_cmd->pitches[0] > pitch_limit) { | |
9976 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
9977 | obj->tiling_mode ? "tiled" : "linear", | |
9978 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 9979 | return -EINVAL; |
c16ed4be | 9980 | } |
5d7bd705 VS |
9981 | |
9982 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
9983 | mode_cmd->pitches[0] != obj->stride) { |
9984 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
9985 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 9986 | return -EINVAL; |
c16ed4be | 9987 | } |
5d7bd705 | 9988 | |
57779d06 | 9989 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 9990 | switch (mode_cmd->pixel_format) { |
57779d06 | 9991 | case DRM_FORMAT_C8: |
04b3924d VS |
9992 | case DRM_FORMAT_RGB565: |
9993 | case DRM_FORMAT_XRGB8888: | |
9994 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
9995 | break; |
9996 | case DRM_FORMAT_XRGB1555: | |
9997 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 9998 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
9999 | DRM_DEBUG("unsupported pixel format: %s\n", |
10000 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10001 | return -EINVAL; |
c16ed4be | 10002 | } |
57779d06 VS |
10003 | break; |
10004 | case DRM_FORMAT_XBGR8888: | |
10005 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10006 | case DRM_FORMAT_XRGB2101010: |
10007 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10008 | case DRM_FORMAT_XBGR2101010: |
10009 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10010 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10011 | DRM_DEBUG("unsupported pixel format: %s\n", |
10012 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10013 | return -EINVAL; |
c16ed4be | 10014 | } |
b5626747 | 10015 | break; |
04b3924d VS |
10016 | case DRM_FORMAT_YUYV: |
10017 | case DRM_FORMAT_UYVY: | |
10018 | case DRM_FORMAT_YVYU: | |
10019 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10020 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10021 | DRM_DEBUG("unsupported pixel format: %s\n", |
10022 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10023 | return -EINVAL; |
c16ed4be | 10024 | } |
57cd6508 CW |
10025 | break; |
10026 | default: | |
4ee62c76 VS |
10027 | DRM_DEBUG("unsupported pixel format: %s\n", |
10028 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10029 | return -EINVAL; |
10030 | } | |
10031 | ||
90f9a336 VS |
10032 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10033 | if (mode_cmd->offsets[0] != 0) | |
10034 | return -EINVAL; | |
10035 | ||
c7d73f6a DV |
10036 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10037 | intel_fb->obj = obj; | |
10038 | ||
79e53945 JB |
10039 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10040 | if (ret) { | |
10041 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10042 | return ret; | |
10043 | } | |
10044 | ||
79e53945 JB |
10045 | return 0; |
10046 | } | |
10047 | ||
79e53945 JB |
10048 | static struct drm_framebuffer * |
10049 | intel_user_framebuffer_create(struct drm_device *dev, | |
10050 | struct drm_file *filp, | |
308e5bcb | 10051 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10052 | { |
05394f39 | 10053 | struct drm_i915_gem_object *obj; |
79e53945 | 10054 | |
308e5bcb JB |
10055 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10056 | mode_cmd->handles[0])); | |
c8725226 | 10057 | if (&obj->base == NULL) |
cce13ff7 | 10058 | return ERR_PTR(-ENOENT); |
79e53945 | 10059 | |
d2dff872 | 10060 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10061 | } |
10062 | ||
79e53945 | 10063 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10064 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 10065 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
10066 | }; |
10067 | ||
e70236a8 JB |
10068 | /* Set up chip specific display functions */ |
10069 | static void intel_init_display(struct drm_device *dev) | |
10070 | { | |
10071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10072 | ||
ee9300bb DV |
10073 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10074 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10075 | else if (IS_VALLEYVIEW(dev)) | |
10076 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10077 | else if (IS_PINEVIEW(dev)) | |
10078 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10079 | else | |
10080 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10081 | ||
affa9354 | 10082 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10083 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10084 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10085 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10086 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10087 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10088 | dev_priv->display.update_plane = ironlake_update_plane; |
10089 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10090 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10091 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10092 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10093 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10094 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10095 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10096 | } else if (IS_VALLEYVIEW(dev)) { |
10097 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10098 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10099 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10100 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10101 | dev_priv->display.off = i9xx_crtc_off; | |
10102 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10103 | } else { |
0e8ffe1b | 10104 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10105 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10106 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10107 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10108 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10109 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10110 | } |
e70236a8 | 10111 | |
e70236a8 | 10112 | /* Returns the core display clock speed */ |
25eb05fc JB |
10113 | if (IS_VALLEYVIEW(dev)) |
10114 | dev_priv->display.get_display_clock_speed = | |
10115 | valleyview_get_display_clock_speed; | |
10116 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10117 | dev_priv->display.get_display_clock_speed = |
10118 | i945_get_display_clock_speed; | |
10119 | else if (IS_I915G(dev)) | |
10120 | dev_priv->display.get_display_clock_speed = | |
10121 | i915_get_display_clock_speed; | |
257a7ffc | 10122 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10123 | dev_priv->display.get_display_clock_speed = |
10124 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10125 | else if (IS_PINEVIEW(dev)) |
10126 | dev_priv->display.get_display_clock_speed = | |
10127 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10128 | else if (IS_I915GM(dev)) |
10129 | dev_priv->display.get_display_clock_speed = | |
10130 | i915gm_get_display_clock_speed; | |
10131 | else if (IS_I865G(dev)) | |
10132 | dev_priv->display.get_display_clock_speed = | |
10133 | i865_get_display_clock_speed; | |
f0f8a9ce | 10134 | else if (IS_I85X(dev)) |
e70236a8 JB |
10135 | dev_priv->display.get_display_clock_speed = |
10136 | i855_get_display_clock_speed; | |
10137 | else /* 852, 830 */ | |
10138 | dev_priv->display.get_display_clock_speed = | |
10139 | i830_get_display_clock_speed; | |
10140 | ||
7f8a8569 | 10141 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10142 | if (IS_GEN5(dev)) { |
674cf967 | 10143 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10144 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10145 | } else if (IS_GEN6(dev)) { |
674cf967 | 10146 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10147 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10148 | } else if (IS_IVYBRIDGE(dev)) { |
10149 | /* FIXME: detect B0+ stepping and use auto training */ | |
10150 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10151 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10152 | dev_priv->display.modeset_global_resources = |
10153 | ivb_modeset_global_resources; | |
c82e4d26 ED |
10154 | } else if (IS_HASWELL(dev)) { |
10155 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 10156 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10157 | dev_priv->display.modeset_global_resources = |
10158 | haswell_modeset_global_resources; | |
a0e63c22 | 10159 | } |
6067aaea | 10160 | } else if (IS_G4X(dev)) { |
e0dac65e | 10161 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 10162 | } |
8c9f3aaf JB |
10163 | |
10164 | /* Default just returns -ENODEV to indicate unsupported */ | |
10165 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10166 | ||
10167 | switch (INTEL_INFO(dev)->gen) { | |
10168 | case 2: | |
10169 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10170 | break; | |
10171 | ||
10172 | case 3: | |
10173 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10174 | break; | |
10175 | ||
10176 | case 4: | |
10177 | case 5: | |
10178 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10179 | break; | |
10180 | ||
10181 | case 6: | |
10182 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10183 | break; | |
7c9017e5 JB |
10184 | case 7: |
10185 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
10186 | break; | |
8c9f3aaf | 10187 | } |
e70236a8 JB |
10188 | } |
10189 | ||
b690e96c JB |
10190 | /* |
10191 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10192 | * resume, or other times. This quirk makes sure that's the case for | |
10193 | * affected systems. | |
10194 | */ | |
0206e353 | 10195 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10196 | { |
10197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10198 | ||
10199 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10200 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10201 | } |
10202 | ||
435793df KP |
10203 | /* |
10204 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10205 | */ | |
10206 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10207 | { | |
10208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10209 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10210 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10211 | } |
10212 | ||
4dca20ef | 10213 | /* |
5a15ab5b CE |
10214 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10215 | * brightness value | |
4dca20ef CE |
10216 | */ |
10217 | static void quirk_invert_brightness(struct drm_device *dev) | |
10218 | { | |
10219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10220 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10221 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10222 | } |
10223 | ||
e85843be KM |
10224 | /* |
10225 | * Some machines (Dell XPS13) suffer broken backlight controls if | |
10226 | * BLM_PCH_PWM_ENABLE is set. | |
10227 | */ | |
10228 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) | |
10229 | { | |
10230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10231 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; | |
10232 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); | |
10233 | } | |
10234 | ||
b690e96c JB |
10235 | struct intel_quirk { |
10236 | int device; | |
10237 | int subsystem_vendor; | |
10238 | int subsystem_device; | |
10239 | void (*hook)(struct drm_device *dev); | |
10240 | }; | |
10241 | ||
5f85f176 EE |
10242 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10243 | struct intel_dmi_quirk { | |
10244 | void (*hook)(struct drm_device *dev); | |
10245 | const struct dmi_system_id (*dmi_id_list)[]; | |
10246 | }; | |
10247 | ||
10248 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10249 | { | |
10250 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10251 | return 1; | |
10252 | } | |
10253 | ||
10254 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10255 | { | |
10256 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10257 | { | |
10258 | .callback = intel_dmi_reverse_brightness, | |
10259 | .ident = "NCR Corporation", | |
10260 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10261 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10262 | }, | |
10263 | }, | |
10264 | { } /* terminating entry */ | |
10265 | }, | |
10266 | .hook = quirk_invert_brightness, | |
10267 | }, | |
10268 | }; | |
10269 | ||
c43b5634 | 10270 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10271 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10272 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10273 | |
b690e96c JB |
10274 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10275 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10276 | ||
b690e96c JB |
10277 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10278 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10279 | ||
ccd0d36e | 10280 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 10281 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 10282 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10283 | |
10284 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10285 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10286 | |
10287 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10288 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10289 | |
ee1452d7 JN |
10290 | /* |
10291 | * All GM45 Acer (and its brands eMachines and Packard Bell) laptops | |
10292 | * seem to use inverted backlight PWM. | |
10293 | */ | |
10294 | { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness }, | |
e85843be KM |
10295 | |
10296 | /* Dell XPS13 HD Sandy Bridge */ | |
10297 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, | |
10298 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ | |
10299 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, | |
b690e96c JB |
10300 | }; |
10301 | ||
10302 | static void intel_init_quirks(struct drm_device *dev) | |
10303 | { | |
10304 | struct pci_dev *d = dev->pdev; | |
10305 | int i; | |
10306 | ||
10307 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10308 | struct intel_quirk *q = &intel_quirks[i]; | |
10309 | ||
10310 | if (d->device == q->device && | |
10311 | (d->subsystem_vendor == q->subsystem_vendor || | |
10312 | q->subsystem_vendor == PCI_ANY_ID) && | |
10313 | (d->subsystem_device == q->subsystem_device || | |
10314 | q->subsystem_device == PCI_ANY_ID)) | |
10315 | q->hook(dev); | |
10316 | } | |
5f85f176 EE |
10317 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10318 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10319 | intel_dmi_quirks[i].hook(dev); | |
10320 | } | |
b690e96c JB |
10321 | } |
10322 | ||
9cce37f4 JB |
10323 | /* Disable the VGA plane that we never use */ |
10324 | static void i915_disable_vga(struct drm_device *dev) | |
10325 | { | |
10326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10327 | u8 sr1; | |
766aa1c4 | 10328 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
10329 | |
10330 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 10331 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10332 | sr1 = inb(VGA_SR_DATA); |
10333 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10334 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10335 | udelay(300); | |
10336 | ||
10337 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10338 | POSTING_READ(vga_reg); | |
10339 | } | |
10340 | ||
6e1b4fda | 10341 | static void i915_enable_vga_mem(struct drm_device *dev) |
81b5c7bc AW |
10342 | { |
10343 | /* Enable VGA memory on Intel HD */ | |
10344 | if (HAS_PCH_SPLIT(dev)) { | |
10345 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10346 | outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE); | |
10347 | vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | | |
10348 | VGA_RSRC_LEGACY_MEM | | |
10349 | VGA_RSRC_NORMAL_IO | | |
10350 | VGA_RSRC_NORMAL_MEM); | |
10351 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10352 | } | |
10353 | } | |
10354 | ||
6e1b4fda VS |
10355 | void i915_disable_vga_mem(struct drm_device *dev) |
10356 | { | |
10357 | /* Disable VGA memory on Intel HD */ | |
10358 | if (HAS_PCH_SPLIT(dev)) { | |
10359 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10360 | outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE); | |
10361 | vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | | |
10362 | VGA_RSRC_NORMAL_IO | | |
10363 | VGA_RSRC_NORMAL_MEM); | |
10364 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10365 | } | |
10366 | } | |
10367 | ||
f817586c DV |
10368 | void intel_modeset_init_hw(struct drm_device *dev) |
10369 | { | |
f6071166 JB |
10370 | struct drm_i915_private *dev_priv = dev->dev_private; |
10371 | ||
a8f78b58 ED |
10372 | intel_prepare_ddi(dev); |
10373 | ||
f817586c DV |
10374 | intel_init_clock_gating(dev); |
10375 | ||
f6071166 JB |
10376 | /* Enable the CRI clock source so we can get at the display */ |
10377 | if (IS_VALLEYVIEW(dev)) | |
10378 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
10379 | DPLL_INTEGRATED_CRI_CLK_VLV); | |
10380 | ||
40e9cf64 JB |
10381 | intel_init_dpio(dev); |
10382 | ||
79f5b2c7 | 10383 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10384 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 10385 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
10386 | } |
10387 | ||
7d708ee4 ID |
10388 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10389 | { | |
10390 | intel_suspend_hw(dev); | |
10391 | } | |
10392 | ||
79e53945 JB |
10393 | void intel_modeset_init(struct drm_device *dev) |
10394 | { | |
652c393a | 10395 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 10396 | int i, j, ret; |
79e53945 JB |
10397 | |
10398 | drm_mode_config_init(dev); | |
10399 | ||
10400 | dev->mode_config.min_width = 0; | |
10401 | dev->mode_config.min_height = 0; | |
10402 | ||
019d96cb DA |
10403 | dev->mode_config.preferred_depth = 24; |
10404 | dev->mode_config.prefer_shadow = 1; | |
10405 | ||
e6ecefaa | 10406 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 10407 | |
b690e96c JB |
10408 | intel_init_quirks(dev); |
10409 | ||
1fa61106 ED |
10410 | intel_init_pm(dev); |
10411 | ||
e3c74757 BW |
10412 | if (INTEL_INFO(dev)->num_pipes == 0) |
10413 | return; | |
10414 | ||
e70236a8 JB |
10415 | intel_init_display(dev); |
10416 | ||
a6c45cf0 CW |
10417 | if (IS_GEN2(dev)) { |
10418 | dev->mode_config.max_width = 2048; | |
10419 | dev->mode_config.max_height = 2048; | |
10420 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
10421 | dev->mode_config.max_width = 4096; |
10422 | dev->mode_config.max_height = 4096; | |
79e53945 | 10423 | } else { |
a6c45cf0 CW |
10424 | dev->mode_config.max_width = 8192; |
10425 | dev->mode_config.max_height = 8192; | |
79e53945 | 10426 | } |
5d4545ae | 10427 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 10428 | |
28c97730 | 10429 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
10430 | INTEL_INFO(dev)->num_pipes, |
10431 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 10432 | |
08e2a7de | 10433 | for_each_pipe(i) { |
79e53945 | 10434 | intel_crtc_init(dev, i); |
7f1f3851 JB |
10435 | for (j = 0; j < dev_priv->num_plane; j++) { |
10436 | ret = intel_plane_init(dev, i, j); | |
10437 | if (ret) | |
06da8da2 VS |
10438 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10439 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 10440 | } |
79e53945 JB |
10441 | } |
10442 | ||
79f689aa | 10443 | intel_cpu_pll_init(dev); |
e72f9fbf | 10444 | intel_shared_dpll_init(dev); |
ee7b9f93 | 10445 | |
9cce37f4 JB |
10446 | /* Just disable it once at startup */ |
10447 | i915_disable_vga(dev); | |
79e53945 | 10448 | intel_setup_outputs(dev); |
11be49eb CW |
10449 | |
10450 | /* Just in case the BIOS is doing something questionable. */ | |
10451 | intel_disable_fbc(dev); | |
2c7111db CW |
10452 | } |
10453 | ||
24929352 DV |
10454 | static void |
10455 | intel_connector_break_all_links(struct intel_connector *connector) | |
10456 | { | |
10457 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10458 | connector->base.encoder = NULL; | |
10459 | connector->encoder->connectors_active = false; | |
10460 | connector->encoder->base.crtc = NULL; | |
10461 | } | |
10462 | ||
7fad798e DV |
10463 | static void intel_enable_pipe_a(struct drm_device *dev) |
10464 | { | |
10465 | struct intel_connector *connector; | |
10466 | struct drm_connector *crt = NULL; | |
10467 | struct intel_load_detect_pipe load_detect_temp; | |
10468 | ||
10469 | /* We can't just switch on the pipe A, we need to set things up with a | |
10470 | * proper mode and output configuration. As a gross hack, enable pipe A | |
10471 | * by enabling the load detect pipe once. */ | |
10472 | list_for_each_entry(connector, | |
10473 | &dev->mode_config.connector_list, | |
10474 | base.head) { | |
10475 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
10476 | crt = &connector->base; | |
10477 | break; | |
10478 | } | |
10479 | } | |
10480 | ||
10481 | if (!crt) | |
10482 | return; | |
10483 | ||
10484 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
10485 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
10486 | ||
652c393a | 10487 | |
7fad798e DV |
10488 | } |
10489 | ||
fa555837 DV |
10490 | static bool |
10491 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
10492 | { | |
7eb552ae BW |
10493 | struct drm_device *dev = crtc->base.dev; |
10494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
10495 | u32 reg, val; |
10496 | ||
7eb552ae | 10497 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
10498 | return true; |
10499 | ||
10500 | reg = DSPCNTR(!crtc->plane); | |
10501 | val = I915_READ(reg); | |
10502 | ||
10503 | if ((val & DISPLAY_PLANE_ENABLE) && | |
10504 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
10505 | return false; | |
10506 | ||
10507 | return true; | |
10508 | } | |
10509 | ||
24929352 DV |
10510 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10511 | { | |
10512 | struct drm_device *dev = crtc->base.dev; | |
10513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 10514 | u32 reg; |
24929352 | 10515 | |
24929352 | 10516 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 10517 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
10518 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10519 | ||
10520 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
10521 | * disable the crtc (and hence change the state) if it is wrong. Note |
10522 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
10523 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
10524 | struct intel_connector *connector; |
10525 | bool plane; | |
10526 | ||
24929352 DV |
10527 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10528 | crtc->base.base.id); | |
10529 | ||
10530 | /* Pipe has the wrong plane attached and the plane is active. | |
10531 | * Temporarily change the plane mapping and disable everything | |
10532 | * ... */ | |
10533 | plane = crtc->plane; | |
10534 | crtc->plane = !plane; | |
10535 | dev_priv->display.crtc_disable(&crtc->base); | |
10536 | crtc->plane = plane; | |
10537 | ||
10538 | /* ... and break all links. */ | |
10539 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10540 | base.head) { | |
10541 | if (connector->encoder->base.crtc != &crtc->base) | |
10542 | continue; | |
10543 | ||
10544 | intel_connector_break_all_links(connector); | |
10545 | } | |
10546 | ||
10547 | WARN_ON(crtc->active); | |
10548 | crtc->base.enabled = false; | |
10549 | } | |
24929352 | 10550 | |
7fad798e DV |
10551 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10552 | crtc->pipe == PIPE_A && !crtc->active) { | |
10553 | /* BIOS forgot to enable pipe A, this mostly happens after | |
10554 | * resume. Force-enable the pipe to fix this, the update_dpms | |
10555 | * call below we restore the pipe to the right state, but leave | |
10556 | * the required bits on. */ | |
10557 | intel_enable_pipe_a(dev); | |
10558 | } | |
10559 | ||
24929352 DV |
10560 | /* Adjust the state of the output pipe according to whether we |
10561 | * have active connectors/encoders. */ | |
10562 | intel_crtc_update_dpms(&crtc->base); | |
10563 | ||
10564 | if (crtc->active != crtc->base.enabled) { | |
10565 | struct intel_encoder *encoder; | |
10566 | ||
10567 | /* This can happen either due to bugs in the get_hw_state | |
10568 | * functions or because the pipe is force-enabled due to the | |
10569 | * pipe A quirk. */ | |
10570 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
10571 | crtc->base.base.id, | |
10572 | crtc->base.enabled ? "enabled" : "disabled", | |
10573 | crtc->active ? "enabled" : "disabled"); | |
10574 | ||
10575 | crtc->base.enabled = crtc->active; | |
10576 | ||
10577 | /* Because we only establish the connector -> encoder -> | |
10578 | * crtc links if something is active, this means the | |
10579 | * crtc is now deactivated. Break the links. connector | |
10580 | * -> encoder links are only establish when things are | |
10581 | * actually up, hence no need to break them. */ | |
10582 | WARN_ON(crtc->active); | |
10583 | ||
10584 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
10585 | WARN_ON(encoder->connectors_active); | |
10586 | encoder->base.crtc = NULL; | |
10587 | } | |
10588 | } | |
10589 | } | |
10590 | ||
10591 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
10592 | { | |
10593 | struct intel_connector *connector; | |
10594 | struct drm_device *dev = encoder->base.dev; | |
10595 | ||
10596 | /* We need to check both for a crtc link (meaning that the | |
10597 | * encoder is active and trying to read from a pipe) and the | |
10598 | * pipe itself being active. */ | |
10599 | bool has_active_crtc = encoder->base.crtc && | |
10600 | to_intel_crtc(encoder->base.crtc)->active; | |
10601 | ||
10602 | if (encoder->connectors_active && !has_active_crtc) { | |
10603 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
10604 | encoder->base.base.id, | |
10605 | drm_get_encoder_name(&encoder->base)); | |
10606 | ||
10607 | /* Connector is active, but has no active pipe. This is | |
10608 | * fallout from our resume register restoring. Disable | |
10609 | * the encoder manually again. */ | |
10610 | if (encoder->base.crtc) { | |
10611 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
10612 | encoder->base.base.id, | |
10613 | drm_get_encoder_name(&encoder->base)); | |
10614 | encoder->disable(encoder); | |
10615 | } | |
10616 | ||
10617 | /* Inconsistent output/port/pipe state happens presumably due to | |
10618 | * a bug in one of the get_hw_state functions. Or someplace else | |
10619 | * in our code, like the register restore mess on resume. Clamp | |
10620 | * things to off as a safer default. */ | |
10621 | list_for_each_entry(connector, | |
10622 | &dev->mode_config.connector_list, | |
10623 | base.head) { | |
10624 | if (connector->encoder != encoder) | |
10625 | continue; | |
10626 | ||
10627 | intel_connector_break_all_links(connector); | |
10628 | } | |
10629 | } | |
10630 | /* Enabled encoders without active connectors will be fixed in | |
10631 | * the crtc fixup. */ | |
10632 | } | |
10633 | ||
44cec740 | 10634 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
10635 | { |
10636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 10637 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 10638 | |
8dc8a27c PZ |
10639 | /* This function can be called both from intel_modeset_setup_hw_state or |
10640 | * at a very early point in our resume sequence, where the power well | |
10641 | * structures are not yet restored. Since this function is at a very | |
10642 | * paranoid "someone might have enabled VGA while we were not looking" | |
10643 | * level, just check if the power well is enabled instead of trying to | |
10644 | * follow the "don't touch the power well if we don't need it" policy | |
10645 | * the rest of the driver uses. */ | |
10646 | if (HAS_POWER_WELL(dev) && | |
6aedd1f5 | 10647 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
10648 | return; |
10649 | ||
0fde901f KM |
10650 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10651 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
209d5211 | 10652 | i915_disable_vga(dev); |
6e1b4fda | 10653 | i915_disable_vga_mem(dev); |
0fde901f KM |
10654 | } |
10655 | } | |
10656 | ||
30e984df | 10657 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
10658 | { |
10659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10660 | enum pipe pipe; | |
24929352 DV |
10661 | struct intel_crtc *crtc; |
10662 | struct intel_encoder *encoder; | |
10663 | struct intel_connector *connector; | |
5358901f | 10664 | int i; |
24929352 | 10665 | |
0e8ffe1b DV |
10666 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10667 | base.head) { | |
88adfff1 | 10668 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 10669 | |
0e8ffe1b DV |
10670 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10671 | &crtc->config); | |
24929352 DV |
10672 | |
10673 | crtc->base.enabled = crtc->active; | |
10674 | ||
10675 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
10676 | crtc->base.base.id, | |
10677 | crtc->active ? "enabled" : "disabled"); | |
10678 | } | |
10679 | ||
5358901f | 10680 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 10681 | if (HAS_DDI(dev)) |
6441ab5f PZ |
10682 | intel_ddi_setup_hw_pll_state(dev); |
10683 | ||
5358901f DV |
10684 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10685 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10686 | ||
10687 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
10688 | pll->active = 0; | |
10689 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
10690 | base.head) { | |
10691 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10692 | pll->active++; | |
10693 | } | |
10694 | pll->refcount = pll->active; | |
10695 | ||
35c95375 DV |
10696 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
10697 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
10698 | } |
10699 | ||
24929352 DV |
10700 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10701 | base.head) { | |
10702 | pipe = 0; | |
10703 | ||
10704 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
10705 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10706 | encoder->base.crtc = &crtc->base; | |
510d5f2f | 10707 | if (encoder->get_config) |
045ac3b5 | 10708 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
10709 | } else { |
10710 | encoder->base.crtc = NULL; | |
10711 | } | |
10712 | ||
10713 | encoder->connectors_active = false; | |
10714 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
10715 | encoder->base.base.id, | |
10716 | drm_get_encoder_name(&encoder->base), | |
10717 | encoder->base.crtc ? "enabled" : "disabled", | |
10718 | pipe); | |
10719 | } | |
10720 | ||
10721 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10722 | base.head) { | |
10723 | if (connector->get_hw_state(connector)) { | |
10724 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
10725 | connector->encoder->connectors_active = true; | |
10726 | connector->base.encoder = &connector->encoder->base; | |
10727 | } else { | |
10728 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10729 | connector->base.encoder = NULL; | |
10730 | } | |
10731 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
10732 | connector->base.base.id, | |
10733 | drm_get_connector_name(&connector->base), | |
10734 | connector->base.encoder ? "enabled" : "disabled"); | |
10735 | } | |
30e984df DV |
10736 | } |
10737 | ||
10738 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
10739 | * and i915 state tracking structures. */ | |
10740 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
10741 | bool force_restore) | |
10742 | { | |
10743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10744 | enum pipe pipe; | |
30e984df DV |
10745 | struct intel_crtc *crtc; |
10746 | struct intel_encoder *encoder; | |
35c95375 | 10747 | int i; |
30e984df DV |
10748 | |
10749 | intel_modeset_readout_hw_state(dev); | |
24929352 | 10750 | |
babea61d JB |
10751 | /* |
10752 | * Now that we have the config, copy it to each CRTC struct | |
10753 | * Note that this could go away if we move to using crtc_config | |
10754 | * checking everywhere. | |
10755 | */ | |
10756 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
10757 | base.head) { | |
10758 | if (crtc->active && i915_fastboot) { | |
10759 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); | |
10760 | ||
10761 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
10762 | crtc->base.base.id); | |
10763 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
10764 | } | |
10765 | } | |
10766 | ||
24929352 DV |
10767 | /* HW state is read out, now we need to sanitize this mess. */ |
10768 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10769 | base.head) { | |
10770 | intel_sanitize_encoder(encoder); | |
10771 | } | |
10772 | ||
10773 | for_each_pipe(pipe) { | |
10774 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
10775 | intel_sanitize_crtc(crtc); | |
c0b03411 | 10776 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 10777 | } |
9a935856 | 10778 | |
35c95375 DV |
10779 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10780 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10781 | ||
10782 | if (!pll->on || pll->active) | |
10783 | continue; | |
10784 | ||
10785 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
10786 | ||
10787 | pll->disable(dev_priv, pll); | |
10788 | pll->on = false; | |
10789 | } | |
10790 | ||
45e2b5f6 | 10791 | if (force_restore) { |
7d0bc1ea VS |
10792 | i915_redisable_vga(dev); |
10793 | ||
f30da187 DV |
10794 | /* |
10795 | * We need to use raw interfaces for restoring state to avoid | |
10796 | * checking (bogus) intermediate states. | |
10797 | */ | |
45e2b5f6 | 10798 | for_each_pipe(pipe) { |
b5644d05 JB |
10799 | struct drm_crtc *crtc = |
10800 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
10801 | |
10802 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
10803 | crtc->fb); | |
45e2b5f6 DV |
10804 | } |
10805 | } else { | |
10806 | intel_modeset_update_staged_output_state(dev); | |
10807 | } | |
8af6cf88 DV |
10808 | |
10809 | intel_modeset_check_state(dev); | |
2e938892 DV |
10810 | |
10811 | drm_mode_config_reset(dev); | |
2c7111db CW |
10812 | } |
10813 | ||
10814 | void intel_modeset_gem_init(struct drm_device *dev) | |
10815 | { | |
1833b134 | 10816 | intel_modeset_init_hw(dev); |
02e792fb DV |
10817 | |
10818 | intel_setup_overlay(dev); | |
24929352 | 10819 | |
45e2b5f6 | 10820 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
10821 | } |
10822 | ||
10823 | void intel_modeset_cleanup(struct drm_device *dev) | |
10824 | { | |
652c393a JB |
10825 | struct drm_i915_private *dev_priv = dev->dev_private; |
10826 | struct drm_crtc *crtc; | |
d9255d57 | 10827 | struct drm_connector *connector; |
652c393a | 10828 | |
fd0c0642 DV |
10829 | /* |
10830 | * Interrupts and polling as the first thing to avoid creating havoc. | |
10831 | * Too much stuff here (turning of rps, connectors, ...) would | |
10832 | * experience fancy races otherwise. | |
10833 | */ | |
10834 | drm_irq_uninstall(dev); | |
10835 | cancel_work_sync(&dev_priv->hotplug_work); | |
10836 | /* | |
10837 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
10838 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
10839 | */ | |
f87ea761 | 10840 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 10841 | |
652c393a JB |
10842 | mutex_lock(&dev->struct_mutex); |
10843 | ||
723bfd70 JB |
10844 | intel_unregister_dsm_handler(); |
10845 | ||
652c393a JB |
10846 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10847 | /* Skip inactive CRTCs */ | |
10848 | if (!crtc->fb) | |
10849 | continue; | |
10850 | ||
3dec0095 | 10851 | intel_increase_pllclock(crtc); |
652c393a JB |
10852 | } |
10853 | ||
973d04f9 | 10854 | intel_disable_fbc(dev); |
e70236a8 | 10855 | |
6e1b4fda | 10856 | i915_enable_vga_mem(dev); |
81b5c7bc | 10857 | |
8090c6b9 | 10858 | intel_disable_gt_powersave(dev); |
0cdab21f | 10859 | |
930ebb46 DV |
10860 | ironlake_teardown_rc6(dev); |
10861 | ||
69341a5e KH |
10862 | mutex_unlock(&dev->struct_mutex); |
10863 | ||
1630fe75 CW |
10864 | /* flush any delayed tasks or pending work */ |
10865 | flush_scheduled_work(); | |
10866 | ||
dc652f90 JN |
10867 | /* destroy backlight, if any, before the connectors */ |
10868 | intel_panel_destroy_backlight(dev); | |
10869 | ||
d9255d57 PZ |
10870 | /* destroy the sysfs files before encoders/connectors */ |
10871 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) | |
10872 | drm_sysfs_connector_remove(connector); | |
10873 | ||
79e53945 | 10874 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
10875 | |
10876 | intel_cleanup_overlay(dev); | |
79e53945 JB |
10877 | } |
10878 | ||
f1c79df3 ZW |
10879 | /* |
10880 | * Return which encoder is currently attached for connector. | |
10881 | */ | |
df0e9248 | 10882 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 10883 | { |
df0e9248 CW |
10884 | return &intel_attached_encoder(connector)->base; |
10885 | } | |
f1c79df3 | 10886 | |
df0e9248 CW |
10887 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10888 | struct intel_encoder *encoder) | |
10889 | { | |
10890 | connector->encoder = encoder; | |
10891 | drm_mode_connector_attach_encoder(&connector->base, | |
10892 | &encoder->base); | |
79e53945 | 10893 | } |
28d52043 DA |
10894 | |
10895 | /* | |
10896 | * set vga decode state - true == enable VGA decode | |
10897 | */ | |
10898 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
10899 | { | |
10900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10901 | u16 gmch_ctrl; | |
10902 | ||
10903 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
10904 | if (state) | |
10905 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
10906 | else | |
10907 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
10908 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
10909 | return 0; | |
10910 | } | |
c4a1d9e4 | 10911 | |
c4a1d9e4 | 10912 | struct intel_display_error_state { |
ff57f1b0 PZ |
10913 | |
10914 | u32 power_well_driver; | |
10915 | ||
63b66e5b CW |
10916 | int num_transcoders; |
10917 | ||
c4a1d9e4 CW |
10918 | struct intel_cursor_error_state { |
10919 | u32 control; | |
10920 | u32 position; | |
10921 | u32 base; | |
10922 | u32 size; | |
52331309 | 10923 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
10924 | |
10925 | struct intel_pipe_error_state { | |
c4a1d9e4 | 10926 | u32 source; |
52331309 | 10927 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
10928 | |
10929 | struct intel_plane_error_state { | |
10930 | u32 control; | |
10931 | u32 stride; | |
10932 | u32 size; | |
10933 | u32 pos; | |
10934 | u32 addr; | |
10935 | u32 surface; | |
10936 | u32 tile_offset; | |
52331309 | 10937 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
10938 | |
10939 | struct intel_transcoder_error_state { | |
10940 | enum transcoder cpu_transcoder; | |
10941 | ||
10942 | u32 conf; | |
10943 | ||
10944 | u32 htotal; | |
10945 | u32 hblank; | |
10946 | u32 hsync; | |
10947 | u32 vtotal; | |
10948 | u32 vblank; | |
10949 | u32 vsync; | |
10950 | } transcoder[4]; | |
c4a1d9e4 CW |
10951 | }; |
10952 | ||
10953 | struct intel_display_error_state * | |
10954 | intel_display_capture_error_state(struct drm_device *dev) | |
10955 | { | |
0206e353 | 10956 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 10957 | struct intel_display_error_state *error; |
63b66e5b CW |
10958 | int transcoders[] = { |
10959 | TRANSCODER_A, | |
10960 | TRANSCODER_B, | |
10961 | TRANSCODER_C, | |
10962 | TRANSCODER_EDP, | |
10963 | }; | |
c4a1d9e4 CW |
10964 | int i; |
10965 | ||
63b66e5b CW |
10966 | if (INTEL_INFO(dev)->num_pipes == 0) |
10967 | return NULL; | |
10968 | ||
c4a1d9e4 CW |
10969 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10970 | if (error == NULL) | |
10971 | return NULL; | |
10972 | ||
ff57f1b0 PZ |
10973 | if (HAS_POWER_WELL(dev)) |
10974 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); | |
10975 | ||
52331309 | 10976 | for_each_pipe(i) { |
a18c4c3d PZ |
10977 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
10978 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
10979 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
10980 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
10981 | } else { | |
10982 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
10983 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
10984 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
10985 | } | |
c4a1d9e4 CW |
10986 | |
10987 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
10988 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 10989 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 10990 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
10991 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
10992 | } | |
ca291363 PZ |
10993 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10994 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
10995 | if (INTEL_INFO(dev)->gen >= 4) { |
10996 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
10997 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
10998 | } | |
10999 | ||
c4a1d9e4 | 11000 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11001 | } |
11002 | ||
11003 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11004 | if (HAS_DDI(dev_priv->dev)) | |
11005 | error->num_transcoders++; /* Account for eDP. */ | |
11006 | ||
11007 | for (i = 0; i < error->num_transcoders; i++) { | |
11008 | enum transcoder cpu_transcoder = transcoders[i]; | |
11009 | ||
11010 | error->transcoder[i].cpu_transcoder = cpu_transcoder; | |
11011 | ||
11012 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11013 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11014 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11015 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11016 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11017 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11018 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11019 | } |
11020 | ||
12d217c7 PZ |
11021 | /* In the code above we read the registers without checking if the power |
11022 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to | |
11023 | * prevent the next I915_WRITE from detecting it and printing an error | |
11024 | * message. */ | |
907b28c5 | 11025 | intel_uncore_clear_errors(dev); |
12d217c7 | 11026 | |
c4a1d9e4 CW |
11027 | return error; |
11028 | } | |
11029 | ||
edc3d884 MK |
11030 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11031 | ||
c4a1d9e4 | 11032 | void |
edc3d884 | 11033 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11034 | struct drm_device *dev, |
11035 | struct intel_display_error_state *error) | |
11036 | { | |
11037 | int i; | |
11038 | ||
63b66e5b CW |
11039 | if (!error) |
11040 | return; | |
11041 | ||
edc3d884 | 11042 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
ff57f1b0 | 11043 | if (HAS_POWER_WELL(dev)) |
edc3d884 | 11044 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11045 | error->power_well_driver); |
52331309 | 11046 | for_each_pipe(i) { |
edc3d884 | 11047 | err_printf(m, "Pipe [%d]:\n", i); |
edc3d884 | 11048 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11049 | |
11050 | err_printf(m, "Plane [%d]:\n", i); | |
11051 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11052 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11053 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11054 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11055 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11056 | } |
4b71a570 | 11057 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11058 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11059 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11060 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11061 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11062 | } |
11063 | ||
edc3d884 MK |
11064 | err_printf(m, "Cursor [%d]:\n", i); |
11065 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11066 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11067 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11068 | } |
63b66e5b CW |
11069 | |
11070 | for (i = 0; i < error->num_transcoders; i++) { | |
11071 | err_printf(m, " CPU transcoder: %c\n", | |
11072 | transcoder_name(error->transcoder[i].cpu_transcoder)); | |
11073 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); | |
11074 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11075 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11076 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11077 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11078 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11079 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11080 | } | |
c4a1d9e4 | 11081 | } |