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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 99 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 100 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
101 | struct intel_link_m_n *m_n, |
102 | struct intel_link_m_n *m2_n2); | |
29407aab | 103 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 104 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 105 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 106 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 107 | const struct intel_crtc_state *pipe_config); |
d288f65f | 108 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 109 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
110 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
111 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
112 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
113 | struct intel_crtc_state *crtc_state); | |
ceb41007 | 114 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state); |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 119 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
e7dc33f3 VS |
172 | static int |
173 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 174 | { |
e7dc33f3 VS |
175 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
176 | } | |
d2acd215 | 177 | |
e7dc33f3 VS |
178 | static int |
179 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
180 | { | |
35d38d1f VS |
181 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
182 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
183 | } |
184 | ||
e7dc33f3 VS |
185 | static int |
186 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 187 | { |
79e50a4f JN |
188 | uint32_t clkcfg; |
189 | ||
e7dc33f3 | 190 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
191 | clkcfg = I915_READ(CLKCFG); |
192 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
193 | case CLKCFG_FSB_400: | |
e7dc33f3 | 194 | return 100000; |
79e50a4f | 195 | case CLKCFG_FSB_533: |
e7dc33f3 | 196 | return 133333; |
79e50a4f | 197 | case CLKCFG_FSB_667: |
e7dc33f3 | 198 | return 166667; |
79e50a4f | 199 | case CLKCFG_FSB_800: |
e7dc33f3 | 200 | return 200000; |
79e50a4f | 201 | case CLKCFG_FSB_1067: |
e7dc33f3 | 202 | return 266667; |
79e50a4f | 203 | case CLKCFG_FSB_1333: |
e7dc33f3 | 204 | return 333333; |
79e50a4f JN |
205 | /* these two are just a guess; one of them might be right */ |
206 | case CLKCFG_FSB_1600: | |
207 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 208 | return 400000; |
79e50a4f | 209 | default: |
e7dc33f3 | 210 | return 133333; |
79e50a4f JN |
211 | } |
212 | } | |
213 | ||
e7dc33f3 VS |
214 | static void intel_update_rawclk(struct drm_i915_private *dev_priv) |
215 | { | |
216 | if (HAS_PCH_SPLIT(dev_priv)) | |
217 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
218 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
219 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
220 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
221 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
222 | else | |
223 | return; /* no rawclk on other platforms, or no need to know it */ | |
224 | ||
225 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
226 | } | |
227 | ||
bfa7df01 VS |
228 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
229 | { | |
666a4537 | 230 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
231 | return; |
232 | ||
233 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
234 | CCK_CZ_CLOCK_CONTROL); | |
235 | ||
236 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
237 | } | |
238 | ||
021357ac | 239 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
240 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
241 | const struct intel_crtc_state *pipe_config) | |
021357ac | 242 | { |
21a727b3 VS |
243 | if (HAS_DDI(dev_priv)) |
244 | return pipe_config->port_clock; /* SPLL */ | |
245 | else if (IS_GEN5(dev_priv)) | |
246 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 247 | else |
21a727b3 | 248 | return 270000; |
021357ac CW |
249 | } |
250 | ||
5d536e28 | 251 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 252 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 253 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 254 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
255 | .m = { .min = 96, .max = 140 }, |
256 | .m1 = { .min = 18, .max = 26 }, | |
257 | .m2 = { .min = 6, .max = 16 }, | |
258 | .p = { .min = 4, .max = 128 }, | |
259 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
260 | .p2 = { .dot_limit = 165000, |
261 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
262 | }; |
263 | ||
5d536e28 DV |
264 | static const intel_limit_t intel_limits_i8xx_dvo = { |
265 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 2, .max = 33 }, | |
273 | .p2 = { .dot_limit = 165000, | |
274 | .p2_slow = 4, .p2_fast = 4 }, | |
275 | }; | |
276 | ||
e4b36699 | 277 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 278 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 279 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 280 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
281 | .m = { .min = 96, .max = 140 }, |
282 | .m1 = { .min = 18, .max = 26 }, | |
283 | .m2 = { .min = 6, .max = 16 }, | |
284 | .p = { .min = 4, .max = 128 }, | |
285 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
286 | .p2 = { .dot_limit = 165000, |
287 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 288 | }; |
273e27ca | 289 | |
e4b36699 | 290 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
291 | .dot = { .min = 20000, .max = 400000 }, |
292 | .vco = { .min = 1400000, .max = 2800000 }, | |
293 | .n = { .min = 1, .max = 6 }, | |
294 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
295 | .m1 = { .min = 8, .max = 18 }, |
296 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
297 | .p = { .min = 5, .max = 80 }, |
298 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 200000, |
300 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
301 | }; |
302 | ||
303 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
304 | .dot = { .min = 20000, .max = 400000 }, |
305 | .vco = { .min = 1400000, .max = 2800000 }, | |
306 | .n = { .min = 1, .max = 6 }, | |
307 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
308 | .m1 = { .min = 8, .max = 18 }, |
309 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
310 | .p = { .min = 7, .max = 98 }, |
311 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
312 | .p2 = { .dot_limit = 112000, |
313 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
314 | }; |
315 | ||
273e27ca | 316 | |
e4b36699 | 317 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
318 | .dot = { .min = 25000, .max = 270000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 17, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 10, .max = 30 }, | |
325 | .p1 = { .min = 1, .max = 3}, | |
326 | .p2 = { .dot_limit = 270000, | |
327 | .p2_slow = 10, | |
328 | .p2_fast = 10 | |
044c7c41 | 329 | }, |
e4b36699 KP |
330 | }; |
331 | ||
332 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
333 | .dot = { .min = 22000, .max = 400000 }, |
334 | .vco = { .min = 1750000, .max = 3500000}, | |
335 | .n = { .min = 1, .max = 4 }, | |
336 | .m = { .min = 104, .max = 138 }, | |
337 | .m1 = { .min = 16, .max = 23 }, | |
338 | .m2 = { .min = 5, .max = 11 }, | |
339 | .p = { .min = 5, .max = 80 }, | |
340 | .p1 = { .min = 1, .max = 8}, | |
341 | .p2 = { .dot_limit = 165000, | |
342 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
343 | }; |
344 | ||
345 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
346 | .dot = { .min = 20000, .max = 115000 }, |
347 | .vco = { .min = 1750000, .max = 3500000 }, | |
348 | .n = { .min = 1, .max = 3 }, | |
349 | .m = { .min = 104, .max = 138 }, | |
350 | .m1 = { .min = 17, .max = 23 }, | |
351 | .m2 = { .min = 5, .max = 11 }, | |
352 | .p = { .min = 28, .max = 112 }, | |
353 | .p1 = { .min = 2, .max = 8 }, | |
354 | .p2 = { .dot_limit = 0, | |
355 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 356 | }, |
e4b36699 KP |
357 | }; |
358 | ||
359 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
360 | .dot = { .min = 80000, .max = 224000 }, |
361 | .vco = { .min = 1750000, .max = 3500000 }, | |
362 | .n = { .min = 1, .max = 3 }, | |
363 | .m = { .min = 104, .max = 138 }, | |
364 | .m1 = { .min = 17, .max = 23 }, | |
365 | .m2 = { .min = 5, .max = 11 }, | |
366 | .p = { .min = 14, .max = 42 }, | |
367 | .p1 = { .min = 2, .max = 6 }, | |
368 | .p2 = { .dot_limit = 0, | |
369 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 370 | }, |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000}, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 376 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
377 | .n = { .min = 3, .max = 6 }, |
378 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 379 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
380 | .m1 = { .min = 0, .max = 0 }, |
381 | .m2 = { .min = 0, .max = 254 }, | |
382 | .p = { .min = 5, .max = 80 }, | |
383 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
384 | .p2 = { .dot_limit = 200000, |
385 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
386 | }; |
387 | ||
f2b115e6 | 388 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
389 | .dot = { .min = 20000, .max = 400000 }, |
390 | .vco = { .min = 1700000, .max = 3500000 }, | |
391 | .n = { .min = 3, .max = 6 }, | |
392 | .m = { .min = 2, .max = 256 }, | |
393 | .m1 = { .min = 0, .max = 0 }, | |
394 | .m2 = { .min = 0, .max = 254 }, | |
395 | .p = { .min = 7, .max = 112 }, | |
396 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
397 | .p2 = { .dot_limit = 112000, |
398 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
399 | }; |
400 | ||
273e27ca EA |
401 | /* Ironlake / Sandybridge |
402 | * | |
403 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
404 | * the range value for them is (actual_value - 2). | |
405 | */ | |
b91ad0ec | 406 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
407 | .dot = { .min = 25000, .max = 350000 }, |
408 | .vco = { .min = 1760000, .max = 3510000 }, | |
409 | .n = { .min = 1, .max = 5 }, | |
410 | .m = { .min = 79, .max = 127 }, | |
411 | .m1 = { .min = 12, .max = 22 }, | |
412 | .m2 = { .min = 5, .max = 9 }, | |
413 | .p = { .min = 5, .max = 80 }, | |
414 | .p1 = { .min = 1, .max = 8 }, | |
415 | .p2 = { .dot_limit = 225000, | |
416 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
417 | }; |
418 | ||
b91ad0ec | 419 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 3 }, | |
423 | .m = { .min = 79, .max = 118 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 28, .max = 112 }, | |
427 | .p1 = { .min = 2, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
430 | }; |
431 | ||
432 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
433 | .dot = { .min = 25000, .max = 350000 }, |
434 | .vco = { .min = 1760000, .max = 3510000 }, | |
435 | .n = { .min = 1, .max = 3 }, | |
436 | .m = { .min = 79, .max = 127 }, | |
437 | .m1 = { .min = 12, .max = 22 }, | |
438 | .m2 = { .min = 5, .max = 9 }, | |
439 | .p = { .min = 14, .max = 56 }, | |
440 | .p1 = { .min = 2, .max = 8 }, | |
441 | .p2 = { .dot_limit = 225000, | |
442 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
443 | }; |
444 | ||
273e27ca | 445 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 446 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
447 | .dot = { .min = 25000, .max = 350000 }, |
448 | .vco = { .min = 1760000, .max = 3510000 }, | |
449 | .n = { .min = 1, .max = 2 }, | |
450 | .m = { .min = 79, .max = 126 }, | |
451 | .m1 = { .min = 12, .max = 22 }, | |
452 | .m2 = { .min = 5, .max = 9 }, | |
453 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 454 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
455 | .p2 = { .dot_limit = 225000, |
456 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
457 | }; |
458 | ||
459 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
460 | .dot = { .min = 25000, .max = 350000 }, |
461 | .vco = { .min = 1760000, .max = 3510000 }, | |
462 | .n = { .min = 1, .max = 3 }, | |
463 | .m = { .min = 79, .max = 126 }, | |
464 | .m1 = { .min = 12, .max = 22 }, | |
465 | .m2 = { .min = 5, .max = 9 }, | |
466 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 467 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
468 | .p2 = { .dot_limit = 225000, |
469 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
470 | }; |
471 | ||
dc730512 | 472 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
473 | /* |
474 | * These are the data rate limits (measured in fast clocks) | |
475 | * since those are the strictest limits we have. The fast | |
476 | * clock and actual rate limits are more relaxed, so checking | |
477 | * them would make no difference. | |
478 | */ | |
479 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 480 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 481 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
482 | .m1 = { .min = 2, .max = 3 }, |
483 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 484 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 485 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
486 | }; |
487 | ||
ef9348c8 CML |
488 | static const intel_limit_t intel_limits_chv = { |
489 | /* | |
490 | * These are the data rate limits (measured in fast clocks) | |
491 | * since those are the strictest limits we have. The fast | |
492 | * clock and actual rate limits are more relaxed, so checking | |
493 | * them would make no difference. | |
494 | */ | |
495 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 496 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
497 | .n = { .min = 1, .max = 1 }, |
498 | .m1 = { .min = 2, .max = 2 }, | |
499 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
500 | .p1 = { .min = 2, .max = 4 }, | |
501 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
502 | }; | |
503 | ||
5ab7b0b7 ID |
504 | static const intel_limit_t intel_limits_bxt = { |
505 | /* FIXME: find real dot limits */ | |
506 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 507 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
508 | .n = { .min = 1, .max = 1 }, |
509 | .m1 = { .min = 2, .max = 2 }, | |
510 | /* FIXME: find real m2 limits */ | |
511 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
514 | }; | |
515 | ||
cdba954e ACO |
516 | static bool |
517 | needs_modeset(struct drm_crtc_state *state) | |
518 | { | |
fc596660 | 519 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
520 | } |
521 | ||
e0638cdf PZ |
522 | /** |
523 | * Returns whether any output on the specified pipe is of the specified type | |
524 | */ | |
4093561b | 525 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 526 | { |
409ee761 | 527 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
528 | struct intel_encoder *encoder; |
529 | ||
409ee761 | 530 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
531 | if (encoder->type == type) |
532 | return true; | |
533 | ||
534 | return false; | |
535 | } | |
536 | ||
d0737e1d ACO |
537 | /** |
538 | * Returns whether any output on the specified pipe will have the specified | |
539 | * type after a staged modeset is complete, i.e., the same as | |
540 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
541 | * encoder->crtc. | |
542 | */ | |
a93e255f ACO |
543 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
544 | int type) | |
d0737e1d | 545 | { |
a93e255f | 546 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 547 | struct drm_connector *connector; |
a93e255f | 548 | struct drm_connector_state *connector_state; |
d0737e1d | 549 | struct intel_encoder *encoder; |
a93e255f ACO |
550 | int i, num_connectors = 0; |
551 | ||
da3ced29 | 552 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
553 | if (connector_state->crtc != crtc_state->base.crtc) |
554 | continue; | |
555 | ||
556 | num_connectors++; | |
d0737e1d | 557 | |
a93e255f ACO |
558 | encoder = to_intel_encoder(connector_state->best_encoder); |
559 | if (encoder->type == type) | |
d0737e1d | 560 | return true; |
a93e255f ACO |
561 | } |
562 | ||
563 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
564 | |
565 | return false; | |
566 | } | |
567 | ||
a93e255f ACO |
568 | static const intel_limit_t * |
569 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 570 | { |
a93e255f | 571 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
572 | const intel_limit_t *limit; |
573 | ||
a93e255f | 574 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 575 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 576 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 577 | else |
e4b36699 | 578 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
579 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
580 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 581 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 582 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 583 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 584 | } else /* The option is for other outputs */ |
e4b36699 | 585 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
586 | |
587 | return limit; | |
588 | } | |
589 | ||
a93e255f ACO |
590 | static const intel_limit_t * |
591 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 592 | { |
a93e255f | 593 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
594 | const intel_limit_t *limit; |
595 | ||
5ab7b0b7 ID |
596 | if (IS_BROXTON(dev)) |
597 | limit = &intel_limits_bxt; | |
8f0d5b9b ACO |
598 | else if (WARN_ON(HAS_PCH_SPLIT(dev))) |
599 | limit = NULL; | |
2c07245f | 600 | else if (IS_G4X(dev)) { |
a93e255f | 601 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 602 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 603 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 604 | limit = &intel_limits_pineview_lvds; |
2177832f | 605 | else |
f2b115e6 | 606 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
607 | } else if (IS_CHERRYVIEW(dev)) { |
608 | limit = &intel_limits_chv; | |
a0c4da24 | 609 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 610 | limit = &intel_limits_vlv; |
a6c45cf0 | 611 | } else if (!IS_GEN2(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
613 | limit = &intel_limits_i9xx_lvds; |
614 | else | |
615 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 616 | } else { |
a93e255f | 617 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 618 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 619 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 620 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
621 | else |
622 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
623 | } |
624 | return limit; | |
625 | } | |
626 | ||
dccbea3b ID |
627 | /* |
628 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
629 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
630 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
631 | * The helpers' return value is the rate of the clock that is fed to the | |
632 | * display engine's pipe which can be the above fast dot clock rate or a | |
633 | * divided-down version of it. | |
634 | */ | |
f2b115e6 | 635 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 636 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 637 | { |
2177832f SL |
638 | clock->m = clock->m2 + 2; |
639 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 640 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 641 | return 0; |
fb03ac01 VS |
642 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
643 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
644 | |
645 | return clock->dot; | |
2177832f SL |
646 | } |
647 | ||
7429e9d4 DV |
648 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
649 | { | |
650 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
651 | } | |
652 | ||
dccbea3b | 653 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 654 | { |
7429e9d4 | 655 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 656 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 657 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 658 | return 0; |
fb03ac01 VS |
659 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
660 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
661 | |
662 | return clock->dot; | |
79e53945 JB |
663 | } |
664 | ||
dccbea3b | 665 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
666 | { |
667 | clock->m = clock->m1 * clock->m2; | |
668 | clock->p = clock->p1 * clock->p2; | |
669 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 670 | return 0; |
589eca67 ID |
671 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
672 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
673 | |
674 | return clock->dot / 5; | |
589eca67 ID |
675 | } |
676 | ||
dccbea3b | 677 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
678 | { |
679 | clock->m = clock->m1 * clock->m2; | |
680 | clock->p = clock->p1 * clock->p2; | |
681 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 682 | return 0; |
ef9348c8 CML |
683 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
684 | clock->n << 22); | |
685 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
686 | |
687 | return clock->dot / 5; | |
ef9348c8 CML |
688 | } |
689 | ||
7c04d1d9 | 690 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
691 | /** |
692 | * Returns whether the given set of divisors are valid for a given refclk with | |
693 | * the given connectors. | |
694 | */ | |
695 | ||
1b894b59 CW |
696 | static bool intel_PLL_is_valid(struct drm_device *dev, |
697 | const intel_limit_t *limit, | |
698 | const intel_clock_t *clock) | |
79e53945 | 699 | { |
f01b7962 VS |
700 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
701 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 702 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 703 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 704 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 705 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 706 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 707 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 708 | |
666a4537 WB |
709 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
710 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
711 | if (clock->m1 <= clock->m2) |
712 | INTELPllInvalid("m1 <= m2\n"); | |
713 | ||
666a4537 | 714 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
715 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
716 | INTELPllInvalid("p out of range\n"); | |
717 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
718 | INTELPllInvalid("m out of range\n"); | |
719 | } | |
720 | ||
79e53945 | 721 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 722 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
723 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
724 | * connector, etc., rather than just a single range. | |
725 | */ | |
726 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 727 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
728 | |
729 | return true; | |
730 | } | |
731 | ||
3b1429d9 VS |
732 | static int |
733 | i9xx_select_p2_div(const intel_limit_t *limit, | |
734 | const struct intel_crtc_state *crtc_state, | |
735 | int target) | |
79e53945 | 736 | { |
3b1429d9 | 737 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 738 | |
a93e255f | 739 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 740 | /* |
a210b028 DV |
741 | * For LVDS just rely on its current settings for dual-channel. |
742 | * We haven't figured out how to reliably set up different | |
743 | * single/dual channel state, if we even can. | |
79e53945 | 744 | */ |
1974cad0 | 745 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 746 | return limit->p2.p2_fast; |
79e53945 | 747 | else |
3b1429d9 | 748 | return limit->p2.p2_slow; |
79e53945 JB |
749 | } else { |
750 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 751 | return limit->p2.p2_slow; |
79e53945 | 752 | else |
3b1429d9 | 753 | return limit->p2.p2_fast; |
79e53945 | 754 | } |
3b1429d9 VS |
755 | } |
756 | ||
757 | static bool | |
758 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
759 | struct intel_crtc_state *crtc_state, | |
760 | int target, int refclk, intel_clock_t *match_clock, | |
761 | intel_clock_t *best_clock) | |
762 | { | |
763 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
764 | intel_clock_t clock; | |
765 | int err = target; | |
79e53945 | 766 | |
0206e353 | 767 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 768 | |
3b1429d9 VS |
769 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
770 | ||
42158660 ZY |
771 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
772 | clock.m1++) { | |
773 | for (clock.m2 = limit->m2.min; | |
774 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 775 | if (clock.m2 >= clock.m1) |
42158660 ZY |
776 | break; |
777 | for (clock.n = limit->n.min; | |
778 | clock.n <= limit->n.max; clock.n++) { | |
779 | for (clock.p1 = limit->p1.min; | |
780 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
781 | int this_err; |
782 | ||
dccbea3b | 783 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
784 | if (!intel_PLL_is_valid(dev, limit, |
785 | &clock)) | |
786 | continue; | |
787 | if (match_clock && | |
788 | clock.p != match_clock->p) | |
789 | continue; | |
790 | ||
791 | this_err = abs(clock.dot - target); | |
792 | if (this_err < err) { | |
793 | *best_clock = clock; | |
794 | err = this_err; | |
795 | } | |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
800 | ||
801 | return (err != target); | |
802 | } | |
803 | ||
804 | static bool | |
a93e255f ACO |
805 | pnv_find_best_dpll(const intel_limit_t *limit, |
806 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
807 | int target, int refclk, intel_clock_t *match_clock, |
808 | intel_clock_t *best_clock) | |
79e53945 | 809 | { |
3b1429d9 | 810 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 811 | intel_clock_t clock; |
79e53945 JB |
812 | int err = target; |
813 | ||
0206e353 | 814 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 815 | |
3b1429d9 VS |
816 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
817 | ||
42158660 ZY |
818 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
819 | clock.m1++) { | |
820 | for (clock.m2 = limit->m2.min; | |
821 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
822 | for (clock.n = limit->n.min; |
823 | clock.n <= limit->n.max; clock.n++) { | |
824 | for (clock.p1 = limit->p1.min; | |
825 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
826 | int this_err; |
827 | ||
dccbea3b | 828 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
829 | if (!intel_PLL_is_valid(dev, limit, |
830 | &clock)) | |
79e53945 | 831 | continue; |
cec2f356 SP |
832 | if (match_clock && |
833 | clock.p != match_clock->p) | |
834 | continue; | |
79e53945 JB |
835 | |
836 | this_err = abs(clock.dot - target); | |
837 | if (this_err < err) { | |
838 | *best_clock = clock; | |
839 | err = this_err; | |
840 | } | |
841 | } | |
842 | } | |
843 | } | |
844 | } | |
845 | ||
846 | return (err != target); | |
847 | } | |
848 | ||
d4906093 | 849 | static bool |
a93e255f ACO |
850 | g4x_find_best_dpll(const intel_limit_t *limit, |
851 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
852 | int target, int refclk, intel_clock_t *match_clock, |
853 | intel_clock_t *best_clock) | |
d4906093 | 854 | { |
3b1429d9 | 855 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
856 | intel_clock_t clock; |
857 | int max_n; | |
3b1429d9 | 858 | bool found = false; |
6ba770dc AJ |
859 | /* approximately equals target * 0.00585 */ |
860 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
861 | |
862 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
863 | |
864 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
865 | ||
d4906093 | 866 | max_n = limit->n.max; |
f77f13e2 | 867 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 868 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 869 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
870 | for (clock.m1 = limit->m1.max; |
871 | clock.m1 >= limit->m1.min; clock.m1--) { | |
872 | for (clock.m2 = limit->m2.max; | |
873 | clock.m2 >= limit->m2.min; clock.m2--) { | |
874 | for (clock.p1 = limit->p1.max; | |
875 | clock.p1 >= limit->p1.min; clock.p1--) { | |
876 | int this_err; | |
877 | ||
dccbea3b | 878 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
879 | if (!intel_PLL_is_valid(dev, limit, |
880 | &clock)) | |
d4906093 | 881 | continue; |
1b894b59 CW |
882 | |
883 | this_err = abs(clock.dot - target); | |
d4906093 ML |
884 | if (this_err < err_most) { |
885 | *best_clock = clock; | |
886 | err_most = this_err; | |
887 | max_n = clock.n; | |
888 | found = true; | |
889 | } | |
890 | } | |
891 | } | |
892 | } | |
893 | } | |
2c07245f ZW |
894 | return found; |
895 | } | |
896 | ||
d5dd62bd ID |
897 | /* |
898 | * Check if the calculated PLL configuration is more optimal compared to the | |
899 | * best configuration and error found so far. Return the calculated error. | |
900 | */ | |
901 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
902 | const intel_clock_t *calculated_clock, | |
903 | const intel_clock_t *best_clock, | |
904 | unsigned int best_error_ppm, | |
905 | unsigned int *error_ppm) | |
906 | { | |
9ca3ba01 ID |
907 | /* |
908 | * For CHV ignore the error and consider only the P value. | |
909 | * Prefer a bigger P value based on HW requirements. | |
910 | */ | |
911 | if (IS_CHERRYVIEW(dev)) { | |
912 | *error_ppm = 0; | |
913 | ||
914 | return calculated_clock->p > best_clock->p; | |
915 | } | |
916 | ||
24be4e46 ID |
917 | if (WARN_ON_ONCE(!target_freq)) |
918 | return false; | |
919 | ||
d5dd62bd ID |
920 | *error_ppm = div_u64(1000000ULL * |
921 | abs(target_freq - calculated_clock->dot), | |
922 | target_freq); | |
923 | /* | |
924 | * Prefer a better P value over a better (smaller) error if the error | |
925 | * is small. Ensure this preference for future configurations too by | |
926 | * setting the error to 0. | |
927 | */ | |
928 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
929 | *error_ppm = 0; | |
930 | ||
931 | return true; | |
932 | } | |
933 | ||
934 | return *error_ppm + 10 < best_error_ppm; | |
935 | } | |
936 | ||
a0c4da24 | 937 | static bool |
a93e255f ACO |
938 | vlv_find_best_dpll(const intel_limit_t *limit, |
939 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
940 | int target, int refclk, intel_clock_t *match_clock, |
941 | intel_clock_t *best_clock) | |
a0c4da24 | 942 | { |
a93e255f | 943 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 944 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 945 | intel_clock_t clock; |
69e4f900 | 946 | unsigned int bestppm = 1000000; |
27e639bf VS |
947 | /* min update 19.2 MHz */ |
948 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 949 | bool found = false; |
a0c4da24 | 950 | |
6b4bf1c4 VS |
951 | target *= 5; /* fast clock */ |
952 | ||
953 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
954 | |
955 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 956 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 957 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 958 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 959 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 960 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 961 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 962 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 963 | unsigned int ppm; |
69e4f900 | 964 | |
6b4bf1c4 VS |
965 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
966 | refclk * clock.m1); | |
967 | ||
dccbea3b | 968 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 969 | |
f01b7962 VS |
970 | if (!intel_PLL_is_valid(dev, limit, |
971 | &clock)) | |
43b0ac53 VS |
972 | continue; |
973 | ||
d5dd62bd ID |
974 | if (!vlv_PLL_is_optimal(dev, target, |
975 | &clock, | |
976 | best_clock, | |
977 | bestppm, &ppm)) | |
978 | continue; | |
6b4bf1c4 | 979 | |
d5dd62bd ID |
980 | *best_clock = clock; |
981 | bestppm = ppm; | |
982 | found = true; | |
a0c4da24 JB |
983 | } |
984 | } | |
985 | } | |
986 | } | |
a0c4da24 | 987 | |
49e497ef | 988 | return found; |
a0c4da24 | 989 | } |
a4fc5ed6 | 990 | |
ef9348c8 | 991 | static bool |
a93e255f ACO |
992 | chv_find_best_dpll(const intel_limit_t *limit, |
993 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
994 | int target, int refclk, intel_clock_t *match_clock, |
995 | intel_clock_t *best_clock) | |
996 | { | |
a93e255f | 997 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 998 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 999 | unsigned int best_error_ppm; |
ef9348c8 CML |
1000 | intel_clock_t clock; |
1001 | uint64_t m2; | |
1002 | int found = false; | |
1003 | ||
1004 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1005 | best_error_ppm = 1000000; |
ef9348c8 CML |
1006 | |
1007 | /* | |
1008 | * Based on hardware doc, the n always set to 1, and m1 always | |
1009 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1010 | * revisit this because n may not 1 anymore. | |
1011 | */ | |
1012 | clock.n = 1, clock.m1 = 2; | |
1013 | target *= 5; /* fast clock */ | |
1014 | ||
1015 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1016 | for (clock.p2 = limit->p2.p2_fast; | |
1017 | clock.p2 >= limit->p2.p2_slow; | |
1018 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1019 | unsigned int error_ppm; |
ef9348c8 CML |
1020 | |
1021 | clock.p = clock.p1 * clock.p2; | |
1022 | ||
1023 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1024 | clock.n) << 22, refclk * clock.m1); | |
1025 | ||
1026 | if (m2 > INT_MAX/clock.m1) | |
1027 | continue; | |
1028 | ||
1029 | clock.m2 = m2; | |
1030 | ||
dccbea3b | 1031 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1032 | |
1033 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1034 | continue; | |
1035 | ||
9ca3ba01 ID |
1036 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1037 | best_error_ppm, &error_ppm)) | |
1038 | continue; | |
1039 | ||
1040 | *best_clock = clock; | |
1041 | best_error_ppm = error_ppm; | |
1042 | found = true; | |
ef9348c8 CML |
1043 | } |
1044 | } | |
1045 | ||
1046 | return found; | |
1047 | } | |
1048 | ||
5ab7b0b7 ID |
1049 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1050 | intel_clock_t *best_clock) | |
1051 | { | |
ceb41007 | 1052 | int refclk = i9xx_get_refclk(crtc_state); |
5ab7b0b7 ID |
1053 | |
1054 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1055 | target_clock, refclk, NULL, best_clock); | |
1056 | } | |
1057 | ||
20ddf665 VS |
1058 | bool intel_crtc_active(struct drm_crtc *crtc) |
1059 | { | |
1060 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1061 | ||
1062 | /* Be paranoid as we can arrive here with only partial | |
1063 | * state retrieved from the hardware during setup. | |
1064 | * | |
241bfc38 | 1065 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1066 | * as Haswell has gained clock readout/fastboot support. |
1067 | * | |
66e514c1 | 1068 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1069 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1070 | * |
1071 | * FIXME: The intel_crtc->active here should be switched to | |
1072 | * crtc->state->active once we have proper CRTC states wired up | |
1073 | * for atomic. | |
20ddf665 | 1074 | */ |
c3d1f436 | 1075 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1076 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1077 | } |
1078 | ||
a5c961d1 PZ |
1079 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1080 | enum pipe pipe) | |
1081 | { | |
1082 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1084 | ||
6e3c9717 | 1085 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1086 | } |
1087 | ||
fbf49ea2 VS |
1088 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1089 | { | |
1090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1091 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1092 | u32 line1, line2; |
1093 | u32 line_mask; | |
1094 | ||
1095 | if (IS_GEN2(dev)) | |
1096 | line_mask = DSL_LINEMASK_GEN2; | |
1097 | else | |
1098 | line_mask = DSL_LINEMASK_GEN3; | |
1099 | ||
1100 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1101 | msleep(5); |
fbf49ea2 VS |
1102 | line2 = I915_READ(reg) & line_mask; |
1103 | ||
1104 | return line1 == line2; | |
1105 | } | |
1106 | ||
ab7ad7f6 KP |
1107 | /* |
1108 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1109 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1110 | * |
1111 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1112 | * spinning on the vblank interrupt status bit, since we won't actually | |
1113 | * see an interrupt when the pipe is disabled. | |
1114 | * | |
ab7ad7f6 KP |
1115 | * On Gen4 and above: |
1116 | * wait for the pipe register state bit to turn off | |
1117 | * | |
1118 | * Otherwise: | |
1119 | * wait for the display line value to settle (it usually | |
1120 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1121 | * |
9d0498a2 | 1122 | */ |
575f7ab7 | 1123 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1124 | { |
575f7ab7 | 1125 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1126 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1127 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1128 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1129 | |
1130 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1131 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1132 | |
1133 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1134 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1135 | 100)) | |
284637d9 | 1136 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1137 | } else { |
ab7ad7f6 | 1138 | /* Wait for the display line to settle */ |
fbf49ea2 | 1139 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1140 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1141 | } |
79e53945 JB |
1142 | } |
1143 | ||
b24e7179 | 1144 | /* Only for pre-ILK configs */ |
55607e8a DV |
1145 | void assert_pll(struct drm_i915_private *dev_priv, |
1146 | enum pipe pipe, bool state) | |
b24e7179 | 1147 | { |
b24e7179 JB |
1148 | u32 val; |
1149 | bool cur_state; | |
1150 | ||
649636ef | 1151 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1152 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1154 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1155 | onoff(state), onoff(cur_state)); |
b24e7179 | 1156 | } |
b24e7179 | 1157 | |
23538ef1 | 1158 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1159 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1160 | { |
1161 | u32 val; | |
1162 | bool cur_state; | |
1163 | ||
a580516d | 1164 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1165 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1166 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1167 | |
1168 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1169 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1170 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1171 | onoff(state), onoff(cur_state)); |
23538ef1 | 1172 | } |
23538ef1 | 1173 | |
040484af JB |
1174 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1175 | enum pipe pipe, bool state) | |
1176 | { | |
040484af | 1177 | bool cur_state; |
ad80a810 PZ |
1178 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1179 | pipe); | |
040484af | 1180 | |
affa9354 PZ |
1181 | if (HAS_DDI(dev_priv->dev)) { |
1182 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1183 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1184 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1185 | } else { |
649636ef | 1186 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1187 | cur_state = !!(val & FDI_TX_ENABLE); |
1188 | } | |
e2c719b7 | 1189 | I915_STATE_WARN(cur_state != state, |
040484af | 1190 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1191 | onoff(state), onoff(cur_state)); |
040484af JB |
1192 | } |
1193 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1194 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1195 | ||
1196 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1197 | enum pipe pipe, bool state) | |
1198 | { | |
040484af JB |
1199 | u32 val; |
1200 | bool cur_state; | |
1201 | ||
649636ef | 1202 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1203 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1204 | I915_STATE_WARN(cur_state != state, |
040484af | 1205 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1206 | onoff(state), onoff(cur_state)); |
040484af JB |
1207 | } |
1208 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1209 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1210 | ||
1211 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1212 | enum pipe pipe) | |
1213 | { | |
040484af JB |
1214 | u32 val; |
1215 | ||
1216 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1217 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1218 | return; |
1219 | ||
bf507ef7 | 1220 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1221 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1222 | return; |
1223 | ||
649636ef | 1224 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1225 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1226 | } |
1227 | ||
55607e8a DV |
1228 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1229 | enum pipe pipe, bool state) | |
040484af | 1230 | { |
040484af | 1231 | u32 val; |
55607e8a | 1232 | bool cur_state; |
040484af | 1233 | |
649636ef | 1234 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1235 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1236 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1237 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1238 | onoff(state), onoff(cur_state)); |
040484af JB |
1239 | } |
1240 | ||
b680c37a DV |
1241 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1242 | enum pipe pipe) | |
ea0760cf | 1243 | { |
bedd4dba | 1244 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1245 | i915_reg_t pp_reg; |
ea0760cf JB |
1246 | u32 val; |
1247 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1248 | bool locked = true; |
ea0760cf | 1249 | |
bedd4dba JN |
1250 | if (WARN_ON(HAS_DDI(dev))) |
1251 | return; | |
1252 | ||
1253 | if (HAS_PCH_SPLIT(dev)) { | |
1254 | u32 port_sel; | |
1255 | ||
ea0760cf | 1256 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1257 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1258 | ||
1259 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1260 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1261 | panel_pipe = PIPE_B; | |
1262 | /* XXX: else fix for eDP */ | |
666a4537 | 1263 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1264 | /* presumably write lock depends on pipe, not port select */ |
1265 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1266 | panel_pipe = pipe; | |
ea0760cf JB |
1267 | } else { |
1268 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1269 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1270 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1271 | } |
1272 | ||
1273 | val = I915_READ(pp_reg); | |
1274 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1275 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1276 | locked = false; |
1277 | ||
e2c719b7 | 1278 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1279 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1280 | pipe_name(pipe)); |
ea0760cf JB |
1281 | } |
1282 | ||
93ce0ba6 JN |
1283 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1284 | enum pipe pipe, bool state) | |
1285 | { | |
1286 | struct drm_device *dev = dev_priv->dev; | |
1287 | bool cur_state; | |
1288 | ||
d9d82081 | 1289 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1290 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1291 | else |
5efb3e28 | 1292 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1293 | |
e2c719b7 | 1294 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1295 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1296 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1297 | } |
1298 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1299 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1300 | ||
b840d907 JB |
1301 | void assert_pipe(struct drm_i915_private *dev_priv, |
1302 | enum pipe pipe, bool state) | |
b24e7179 | 1303 | { |
63d7bbe9 | 1304 | bool cur_state; |
702e7a56 PZ |
1305 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1306 | pipe); | |
4feed0eb | 1307 | enum intel_display_power_domain power_domain; |
b24e7179 | 1308 | |
b6b5d049 VS |
1309 | /* if we need the pipe quirk it must be always on */ |
1310 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1311 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1312 | state = true; |
1313 | ||
4feed0eb ID |
1314 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1315 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1316 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1317 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1318 | |
1319 | intel_display_power_put(dev_priv, power_domain); | |
1320 | } else { | |
1321 | cur_state = false; | |
69310161 PZ |
1322 | } |
1323 | ||
e2c719b7 | 1324 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1325 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1326 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1327 | } |
1328 | ||
931872fc CW |
1329 | static void assert_plane(struct drm_i915_private *dev_priv, |
1330 | enum plane plane, bool state) | |
b24e7179 | 1331 | { |
b24e7179 | 1332 | u32 val; |
931872fc | 1333 | bool cur_state; |
b24e7179 | 1334 | |
649636ef | 1335 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1336 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1337 | I915_STATE_WARN(cur_state != state, |
931872fc | 1338 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1339 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1340 | } |
1341 | ||
931872fc CW |
1342 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1343 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1344 | ||
b24e7179 JB |
1345 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1346 | enum pipe pipe) | |
1347 | { | |
653e1026 | 1348 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1349 | int i; |
b24e7179 | 1350 | |
653e1026 VS |
1351 | /* Primary planes are fixed to pipes on gen4+ */ |
1352 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1353 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1354 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1355 | "plane %c assertion failure, should be disabled but not\n", |
1356 | plane_name(pipe)); | |
19ec1358 | 1357 | return; |
28c05794 | 1358 | } |
19ec1358 | 1359 | |
b24e7179 | 1360 | /* Need to check both planes against the pipe */ |
055e393f | 1361 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1362 | u32 val = I915_READ(DSPCNTR(i)); |
1363 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1364 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1365 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1366 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1367 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1368 | } |
1369 | } | |
1370 | ||
19332d7a JB |
1371 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1372 | enum pipe pipe) | |
1373 | { | |
20674eef | 1374 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1375 | int sprite; |
19332d7a | 1376 | |
7feb8b88 | 1377 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1378 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1379 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1380 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1381 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1382 | sprite, pipe_name(pipe)); | |
1383 | } | |
666a4537 | 1384 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1385 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1386 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1387 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1388 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1389 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1390 | } |
1391 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1392 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1393 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1394 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1395 | plane_name(pipe), pipe_name(pipe)); |
1396 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1397 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1398 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1399 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1400 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1401 | } |
1402 | } | |
1403 | ||
08c71e5e VS |
1404 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1405 | { | |
e2c719b7 | 1406 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1407 | drm_crtc_vblank_put(crtc); |
1408 | } | |
1409 | ||
7abd4b35 ACO |
1410 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1411 | enum pipe pipe) | |
92f2584a | 1412 | { |
92f2584a JB |
1413 | u32 val; |
1414 | bool enabled; | |
1415 | ||
649636ef | 1416 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1417 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1418 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1419 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1420 | pipe_name(pipe)); | |
92f2584a JB |
1421 | } |
1422 | ||
4e634389 KP |
1423 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1424 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1425 | { |
1426 | if ((val & DP_PORT_EN) == 0) | |
1427 | return false; | |
1428 | ||
1429 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1430 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1431 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1432 | return false; | |
44f37d1f CML |
1433 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1434 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1435 | return false; | |
f0575e92 KP |
1436 | } else { |
1437 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1438 | return false; | |
1439 | } | |
1440 | return true; | |
1441 | } | |
1442 | ||
1519b995 KP |
1443 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1444 | enum pipe pipe, u32 val) | |
1445 | { | |
dc0fa718 | 1446 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1447 | return false; |
1448 | ||
1449 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1450 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1451 | return false; |
44f37d1f CML |
1452 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1453 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1454 | return false; | |
1519b995 | 1455 | } else { |
dc0fa718 | 1456 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1457 | return false; |
1458 | } | |
1459 | return true; | |
1460 | } | |
1461 | ||
1462 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1463 | enum pipe pipe, u32 val) | |
1464 | { | |
1465 | if ((val & LVDS_PORT_EN) == 0) | |
1466 | return false; | |
1467 | ||
1468 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1469 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1470 | return false; | |
1471 | } else { | |
1472 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1473 | return false; | |
1474 | } | |
1475 | return true; | |
1476 | } | |
1477 | ||
1478 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1479 | enum pipe pipe, u32 val) | |
1480 | { | |
1481 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1482 | return false; | |
1483 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1484 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1485 | return false; | |
1486 | } else { | |
1487 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1488 | return false; | |
1489 | } | |
1490 | return true; | |
1491 | } | |
1492 | ||
291906f1 | 1493 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1494 | enum pipe pipe, i915_reg_t reg, |
1495 | u32 port_sel) | |
291906f1 | 1496 | { |
47a05eca | 1497 | u32 val = I915_READ(reg); |
e2c719b7 | 1498 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1499 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1500 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1501 | |
e2c719b7 | 1502 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1503 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1504 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1505 | } |
1506 | ||
1507 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1508 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1509 | { |
47a05eca | 1510 | u32 val = I915_READ(reg); |
e2c719b7 | 1511 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1512 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1513 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1514 | |
e2c719b7 | 1515 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1516 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1517 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1518 | } |
1519 | ||
1520 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1521 | enum pipe pipe) | |
1522 | { | |
291906f1 | 1523 | u32 val; |
291906f1 | 1524 | |
f0575e92 KP |
1525 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1526 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1527 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1528 | |
649636ef | 1529 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1530 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1531 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1532 | pipe_name(pipe)); |
291906f1 | 1533 | |
649636ef | 1534 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1535 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1536 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1537 | pipe_name(pipe)); |
291906f1 | 1538 | |
e2debe91 PZ |
1539 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1540 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1541 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1542 | } |
1543 | ||
d288f65f | 1544 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1545 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1546 | { |
426115cf DV |
1547 | struct drm_device *dev = crtc->base.dev; |
1548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1549 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1550 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1551 | |
426115cf | 1552 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1553 | |
87442f73 | 1554 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1555 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1556 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1557 | |
426115cf DV |
1558 | I915_WRITE(reg, dpll); |
1559 | POSTING_READ(reg); | |
1560 | udelay(150); | |
1561 | ||
1562 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1563 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1564 | ||
d288f65f | 1565 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1566 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1567 | |
1568 | /* We do this three times for luck */ | |
426115cf | 1569 | I915_WRITE(reg, dpll); |
87442f73 DV |
1570 | POSTING_READ(reg); |
1571 | udelay(150); /* wait for warmup */ | |
426115cf | 1572 | I915_WRITE(reg, dpll); |
87442f73 DV |
1573 | POSTING_READ(reg); |
1574 | udelay(150); /* wait for warmup */ | |
426115cf | 1575 | I915_WRITE(reg, dpll); |
87442f73 DV |
1576 | POSTING_READ(reg); |
1577 | udelay(150); /* wait for warmup */ | |
1578 | } | |
1579 | ||
d288f65f | 1580 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1581 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1582 | { |
1583 | struct drm_device *dev = crtc->base.dev; | |
1584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1585 | int pipe = crtc->pipe; | |
1586 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1587 | u32 tmp; |
1588 | ||
1589 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1590 | ||
a580516d | 1591 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1592 | |
1593 | /* Enable back the 10bit clock to display controller */ | |
1594 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1595 | tmp |= DPIO_DCLKP_EN; | |
1596 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1597 | ||
54433e91 VS |
1598 | mutex_unlock(&dev_priv->sb_lock); |
1599 | ||
9d556c99 CML |
1600 | /* |
1601 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1602 | */ | |
1603 | udelay(1); | |
1604 | ||
1605 | /* Enable PLL */ | |
d288f65f | 1606 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1607 | |
1608 | /* Check PLL is locked */ | |
a11b0703 | 1609 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1610 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1611 | ||
a11b0703 | 1612 | /* not sure when this should be written */ |
d288f65f | 1613 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1614 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1615 | } |
1616 | ||
1c4e0274 VS |
1617 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1618 | { | |
1619 | struct intel_crtc *crtc; | |
1620 | int count = 0; | |
1621 | ||
1622 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1623 | count += crtc->base.state->active && |
409ee761 | 1624 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1625 | |
1626 | return count; | |
1627 | } | |
1628 | ||
66e3d5c0 | 1629 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1630 | { |
66e3d5c0 DV |
1631 | struct drm_device *dev = crtc->base.dev; |
1632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1633 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1634 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1635 | |
66e3d5c0 | 1636 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1637 | |
63d7bbe9 | 1638 | /* No really, not for ILK+ */ |
3d13ef2e | 1639 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1640 | |
1641 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1642 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1643 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1644 | |
1c4e0274 VS |
1645 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1646 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1647 | /* | |
1648 | * It appears to be important that we don't enable this | |
1649 | * for the current pipe before otherwise configuring the | |
1650 | * PLL. No idea how this should be handled if multiple | |
1651 | * DVO outputs are enabled simultaneosly. | |
1652 | */ | |
1653 | dpll |= DPLL_DVO_2X_MODE; | |
1654 | I915_WRITE(DPLL(!crtc->pipe), | |
1655 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1656 | } | |
66e3d5c0 | 1657 | |
c2b63374 VS |
1658 | /* |
1659 | * Apparently we need to have VGA mode enabled prior to changing | |
1660 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1661 | * dividers, even though the register value does change. | |
1662 | */ | |
1663 | I915_WRITE(reg, 0); | |
1664 | ||
8e7a65aa VS |
1665 | I915_WRITE(reg, dpll); |
1666 | ||
66e3d5c0 DV |
1667 | /* Wait for the clocks to stabilize. */ |
1668 | POSTING_READ(reg); | |
1669 | udelay(150); | |
1670 | ||
1671 | if (INTEL_INFO(dev)->gen >= 4) { | |
1672 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1673 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1674 | } else { |
1675 | /* The pixel multiplier can only be updated once the | |
1676 | * DPLL is enabled and the clocks are stable. | |
1677 | * | |
1678 | * So write it again. | |
1679 | */ | |
1680 | I915_WRITE(reg, dpll); | |
1681 | } | |
63d7bbe9 JB |
1682 | |
1683 | /* We do this three times for luck */ | |
66e3d5c0 | 1684 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1685 | POSTING_READ(reg); |
1686 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1687 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1688 | POSTING_READ(reg); |
1689 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1690 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1691 | POSTING_READ(reg); |
1692 | udelay(150); /* wait for warmup */ | |
1693 | } | |
1694 | ||
1695 | /** | |
50b44a44 | 1696 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1697 | * @dev_priv: i915 private structure |
1698 | * @pipe: pipe PLL to disable | |
1699 | * | |
1700 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1701 | * | |
1702 | * Note! This is for pre-ILK only. | |
1703 | */ | |
1c4e0274 | 1704 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1705 | { |
1c4e0274 VS |
1706 | struct drm_device *dev = crtc->base.dev; |
1707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1708 | enum pipe pipe = crtc->pipe; | |
1709 | ||
1710 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1711 | if (IS_I830(dev) && | |
409ee761 | 1712 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1713 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1714 | I915_WRITE(DPLL(PIPE_B), |
1715 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1716 | I915_WRITE(DPLL(PIPE_A), | |
1717 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1718 | } | |
1719 | ||
b6b5d049 VS |
1720 | /* Don't disable pipe or pipe PLLs if needed */ |
1721 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1722 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1723 | return; |
1724 | ||
1725 | /* Make sure the pipe isn't still relying on us */ | |
1726 | assert_pipe_disabled(dev_priv, pipe); | |
1727 | ||
b8afb911 | 1728 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1729 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1730 | } |
1731 | ||
f6071166 JB |
1732 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1733 | { | |
b8afb911 | 1734 | u32 val; |
f6071166 JB |
1735 | |
1736 | /* Make sure the pipe isn't still relying on us */ | |
1737 | assert_pipe_disabled(dev_priv, pipe); | |
1738 | ||
e5cbfbfb ID |
1739 | /* |
1740 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1741 | * The latter is needed for VGA hotplug / manual detection. | |
1742 | */ | |
b8afb911 | 1743 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1744 | if (pipe == PIPE_B) |
60bfe44f | 1745 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1746 | I915_WRITE(DPLL(pipe), val); |
1747 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1748 | |
1749 | } | |
1750 | ||
1751 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1752 | { | |
d752048d | 1753 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1754 | u32 val; |
1755 | ||
a11b0703 VS |
1756 | /* Make sure the pipe isn't still relying on us */ |
1757 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1758 | |
a11b0703 | 1759 | /* Set PLL en = 0 */ |
60bfe44f VS |
1760 | val = DPLL_SSC_REF_CLK_CHV | |
1761 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1762 | if (pipe != PIPE_A) |
1763 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1764 | I915_WRITE(DPLL(pipe), val); | |
1765 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1766 | |
a580516d | 1767 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1768 | |
1769 | /* Disable 10bit clock to display controller */ | |
1770 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1771 | val &= ~DPIO_DCLKP_EN; | |
1772 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1773 | ||
a580516d | 1774 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1775 | } |
1776 | ||
e4607fcf | 1777 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1778 | struct intel_digital_port *dport, |
1779 | unsigned int expected_mask) | |
89b667f8 JB |
1780 | { |
1781 | u32 port_mask; | |
f0f59a00 | 1782 | i915_reg_t dpll_reg; |
89b667f8 | 1783 | |
e4607fcf CML |
1784 | switch (dport->port) { |
1785 | case PORT_B: | |
89b667f8 | 1786 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1787 | dpll_reg = DPLL(0); |
e4607fcf CML |
1788 | break; |
1789 | case PORT_C: | |
89b667f8 | 1790 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1791 | dpll_reg = DPLL(0); |
9b6de0a1 | 1792 | expected_mask <<= 4; |
00fc31b7 CML |
1793 | break; |
1794 | case PORT_D: | |
1795 | port_mask = DPLL_PORTD_READY_MASK; | |
1796 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1797 | break; |
1798 | default: | |
1799 | BUG(); | |
1800 | } | |
89b667f8 | 1801 | |
9b6de0a1 VS |
1802 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1803 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1804 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1805 | } |
1806 | ||
b8a4f404 PZ |
1807 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1808 | enum pipe pipe) | |
040484af | 1809 | { |
23670b32 | 1810 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1811 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1812 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1813 | i915_reg_t reg; |
1814 | uint32_t val, pipeconf_val; | |
040484af JB |
1815 | |
1816 | /* PCH only available on ILK+ */ | |
55522f37 | 1817 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1818 | |
1819 | /* Make sure PCH DPLL is enabled */ | |
8106ddbd | 1820 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1821 | |
1822 | /* FDI must be feeding us bits for PCH ports */ | |
1823 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1824 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1825 | ||
23670b32 DV |
1826 | if (HAS_PCH_CPT(dev)) { |
1827 | /* Workaround: Set the timing override bit before enabling the | |
1828 | * pch transcoder. */ | |
1829 | reg = TRANS_CHICKEN2(pipe); | |
1830 | val = I915_READ(reg); | |
1831 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1832 | I915_WRITE(reg, val); | |
59c859d6 | 1833 | } |
23670b32 | 1834 | |
ab9412ba | 1835 | reg = PCH_TRANSCONF(pipe); |
040484af | 1836 | val = I915_READ(reg); |
5f7f726d | 1837 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1838 | |
1839 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1840 | /* | |
c5de7c6f VS |
1841 | * Make the BPC in transcoder be consistent with |
1842 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1843 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1844 | */ |
dfd07d72 | 1845 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1846 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1847 | val |= PIPECONF_8BPC; | |
1848 | else | |
1849 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1850 | } |
5f7f726d PZ |
1851 | |
1852 | val &= ~TRANS_INTERLACE_MASK; | |
1853 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1854 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1855 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1856 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1857 | else | |
1858 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1859 | else |
1860 | val |= TRANS_PROGRESSIVE; | |
1861 | ||
040484af JB |
1862 | I915_WRITE(reg, val | TRANS_ENABLE); |
1863 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1864 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1865 | } |
1866 | ||
8fb033d7 | 1867 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1868 | enum transcoder cpu_transcoder) |
040484af | 1869 | { |
8fb033d7 | 1870 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1871 | |
1872 | /* PCH only available on ILK+ */ | |
55522f37 | 1873 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1874 | |
8fb033d7 | 1875 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1876 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1877 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1878 | |
223a6fdf | 1879 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1880 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1881 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1882 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1883 | |
25f3ef11 | 1884 | val = TRANS_ENABLE; |
937bb610 | 1885 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1886 | |
9a76b1c6 PZ |
1887 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1888 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1889 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1890 | else |
1891 | val |= TRANS_PROGRESSIVE; | |
1892 | ||
ab9412ba DV |
1893 | I915_WRITE(LPT_TRANSCONF, val); |
1894 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1895 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1896 | } |
1897 | ||
b8a4f404 PZ |
1898 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1899 | enum pipe pipe) | |
040484af | 1900 | { |
23670b32 | 1901 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1902 | i915_reg_t reg; |
1903 | uint32_t val; | |
040484af JB |
1904 | |
1905 | /* FDI relies on the transcoder */ | |
1906 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1907 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1908 | ||
291906f1 JB |
1909 | /* Ports must be off as well */ |
1910 | assert_pch_ports_disabled(dev_priv, pipe); | |
1911 | ||
ab9412ba | 1912 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1913 | val = I915_READ(reg); |
1914 | val &= ~TRANS_ENABLE; | |
1915 | I915_WRITE(reg, val); | |
1916 | /* wait for PCH transcoder off, transcoder state */ | |
1917 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1918 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1919 | |
c465613b | 1920 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1921 | /* Workaround: Clear the timing override chicken bit again. */ |
1922 | reg = TRANS_CHICKEN2(pipe); | |
1923 | val = I915_READ(reg); | |
1924 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1925 | I915_WRITE(reg, val); | |
1926 | } | |
040484af JB |
1927 | } |
1928 | ||
ab4d966c | 1929 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1930 | { |
8fb033d7 PZ |
1931 | u32 val; |
1932 | ||
ab9412ba | 1933 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1934 | val &= ~TRANS_ENABLE; |
ab9412ba | 1935 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1936 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1937 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1938 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1939 | |
1940 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1941 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1942 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1943 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1944 | } |
1945 | ||
b24e7179 | 1946 | /** |
309cfea8 | 1947 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1948 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1949 | * |
0372264a | 1950 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1951 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1952 | */ |
e1fdc473 | 1953 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1954 | { |
0372264a PZ |
1955 | struct drm_device *dev = crtc->base.dev; |
1956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1957 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1958 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1959 | enum pipe pch_transcoder; |
f0f59a00 | 1960 | i915_reg_t reg; |
b24e7179 JB |
1961 | u32 val; |
1962 | ||
9e2ee2dd VS |
1963 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1964 | ||
58c6eaa2 | 1965 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1966 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1967 | assert_sprites_disabled(dev_priv, pipe); |
1968 | ||
681e5811 | 1969 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1970 | pch_transcoder = TRANSCODER_A; |
1971 | else | |
1972 | pch_transcoder = pipe; | |
1973 | ||
b24e7179 JB |
1974 | /* |
1975 | * A pipe without a PLL won't actually be able to drive bits from | |
1976 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1977 | * need the check. | |
1978 | */ | |
50360403 | 1979 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 1980 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
1981 | assert_dsi_pll_enabled(dev_priv); |
1982 | else | |
1983 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1984 | else { |
6e3c9717 | 1985 | if (crtc->config->has_pch_encoder) { |
040484af | 1986 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1987 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1988 | assert_fdi_tx_pll_enabled(dev_priv, |
1989 | (enum pipe) cpu_transcoder); | |
040484af JB |
1990 | } |
1991 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1992 | } | |
b24e7179 | 1993 | |
702e7a56 | 1994 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1995 | val = I915_READ(reg); |
7ad25d48 | 1996 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1997 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1998 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1999 | return; |
7ad25d48 | 2000 | } |
00d70b15 CW |
2001 | |
2002 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2003 | POSTING_READ(reg); |
b7792d8b VS |
2004 | |
2005 | /* | |
2006 | * Until the pipe starts DSL will read as 0, which would cause | |
2007 | * an apparent vblank timestamp jump, which messes up also the | |
2008 | * frame count when it's derived from the timestamps. So let's | |
2009 | * wait for the pipe to start properly before we call | |
2010 | * drm_crtc_vblank_on() | |
2011 | */ | |
2012 | if (dev->max_vblank_count == 0 && | |
2013 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2014 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2015 | } |
2016 | ||
2017 | /** | |
309cfea8 | 2018 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2019 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2020 | * |
575f7ab7 VS |
2021 | * Disable the pipe of @crtc, making sure that various hardware |
2022 | * specific requirements are met, if applicable, e.g. plane | |
2023 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2024 | * |
2025 | * Will wait until the pipe has shut down before returning. | |
2026 | */ | |
575f7ab7 | 2027 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2028 | { |
575f7ab7 | 2029 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2030 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2031 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2032 | i915_reg_t reg; |
b24e7179 JB |
2033 | u32 val; |
2034 | ||
9e2ee2dd VS |
2035 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2036 | ||
b24e7179 JB |
2037 | /* |
2038 | * Make sure planes won't keep trying to pump pixels to us, | |
2039 | * or we might hang the display. | |
2040 | */ | |
2041 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2042 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2043 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2044 | |
702e7a56 | 2045 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2046 | val = I915_READ(reg); |
00d70b15 CW |
2047 | if ((val & PIPECONF_ENABLE) == 0) |
2048 | return; | |
2049 | ||
67adc644 VS |
2050 | /* |
2051 | * Double wide has implications for planes | |
2052 | * so best keep it disabled when not needed. | |
2053 | */ | |
6e3c9717 | 2054 | if (crtc->config->double_wide) |
67adc644 VS |
2055 | val &= ~PIPECONF_DOUBLE_WIDE; |
2056 | ||
2057 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2058 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2059 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2060 | val &= ~PIPECONF_ENABLE; |
2061 | ||
2062 | I915_WRITE(reg, val); | |
2063 | if ((val & PIPECONF_ENABLE) == 0) | |
2064 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2065 | } |
2066 | ||
693db184 CW |
2067 | static bool need_vtd_wa(struct drm_device *dev) |
2068 | { | |
2069 | #ifdef CONFIG_INTEL_IOMMU | |
2070 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2071 | return true; | |
2072 | #endif | |
2073 | return false; | |
2074 | } | |
2075 | ||
832be82f VS |
2076 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2077 | { | |
2078 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2079 | } | |
2080 | ||
27ba3910 VS |
2081 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2082 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2083 | { |
2084 | switch (fb_modifier) { | |
2085 | case DRM_FORMAT_MOD_NONE: | |
2086 | return cpp; | |
2087 | case I915_FORMAT_MOD_X_TILED: | |
2088 | if (IS_GEN2(dev_priv)) | |
2089 | return 128; | |
2090 | else | |
2091 | return 512; | |
2092 | case I915_FORMAT_MOD_Y_TILED: | |
2093 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2094 | return 128; | |
2095 | else | |
2096 | return 512; | |
2097 | case I915_FORMAT_MOD_Yf_TILED: | |
2098 | switch (cpp) { | |
2099 | case 1: | |
2100 | return 64; | |
2101 | case 2: | |
2102 | case 4: | |
2103 | return 128; | |
2104 | case 8: | |
2105 | case 16: | |
2106 | return 256; | |
2107 | default: | |
2108 | MISSING_CASE(cpp); | |
2109 | return cpp; | |
2110 | } | |
2111 | break; | |
2112 | default: | |
2113 | MISSING_CASE(fb_modifier); | |
2114 | return cpp; | |
2115 | } | |
2116 | } | |
2117 | ||
832be82f VS |
2118 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2119 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2120 | { |
832be82f VS |
2121 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2122 | return 1; | |
2123 | else | |
2124 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2125 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2126 | } |
2127 | ||
8d0deca8 VS |
2128 | /* Return the tile dimensions in pixel units */ |
2129 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2130 | unsigned int *tile_width, | |
2131 | unsigned int *tile_height, | |
2132 | uint64_t fb_modifier, | |
2133 | unsigned int cpp) | |
2134 | { | |
2135 | unsigned int tile_width_bytes = | |
2136 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2137 | ||
2138 | *tile_width = tile_width_bytes / cpp; | |
2139 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2140 | } | |
2141 | ||
6761dd31 TU |
2142 | unsigned int |
2143 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2144 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2145 | { |
832be82f VS |
2146 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2147 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2148 | ||
2149 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2150 | } |
2151 | ||
1663b9d6 VS |
2152 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2153 | { | |
2154 | unsigned int size = 0; | |
2155 | int i; | |
2156 | ||
2157 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2158 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2159 | ||
2160 | return size; | |
2161 | } | |
2162 | ||
75c82a53 | 2163 | static void |
3465c580 VS |
2164 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2165 | const struct drm_framebuffer *fb, | |
2166 | unsigned int rotation) | |
f64b98cd | 2167 | { |
2d7a215f VS |
2168 | if (intel_rotation_90_or_270(rotation)) { |
2169 | *view = i915_ggtt_view_rotated; | |
2170 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2171 | } else { | |
2172 | *view = i915_ggtt_view_normal; | |
2173 | } | |
2174 | } | |
50470bb0 | 2175 | |
2d7a215f VS |
2176 | static void |
2177 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2178 | struct drm_framebuffer *fb) | |
2179 | { | |
2180 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2181 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2182 | |
d9b3288e VS |
2183 | tile_size = intel_tile_size(dev_priv); |
2184 | ||
2185 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2186 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2187 | fb->modifier[0], cpp); | |
d9b3288e | 2188 | |
1663b9d6 VS |
2189 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2190 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2191 | |
89e3e142 | 2192 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2193 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2194 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2195 | fb->modifier[1], cpp); | |
d9b3288e | 2196 | |
2d7a215f | 2197 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2198 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2199 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2200 | } |
f64b98cd TU |
2201 | } |
2202 | ||
603525d7 | 2203 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2204 | { |
2205 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2206 | return 256 * 1024; | |
985b8bb4 | 2207 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2208 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2209 | return 128 * 1024; |
2210 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2211 | return 4 * 1024; | |
2212 | else | |
44c5905e | 2213 | return 0; |
4e9a86b6 VS |
2214 | } |
2215 | ||
603525d7 VS |
2216 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2217 | uint64_t fb_modifier) | |
2218 | { | |
2219 | switch (fb_modifier) { | |
2220 | case DRM_FORMAT_MOD_NONE: | |
2221 | return intel_linear_alignment(dev_priv); | |
2222 | case I915_FORMAT_MOD_X_TILED: | |
2223 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2224 | return 256 * 1024; | |
2225 | return 0; | |
2226 | case I915_FORMAT_MOD_Y_TILED: | |
2227 | case I915_FORMAT_MOD_Yf_TILED: | |
2228 | return 1 * 1024 * 1024; | |
2229 | default: | |
2230 | MISSING_CASE(fb_modifier); | |
2231 | return 0; | |
2232 | } | |
2233 | } | |
2234 | ||
127bd2ac | 2235 | int |
3465c580 VS |
2236 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2237 | unsigned int rotation) | |
6b95a207 | 2238 | { |
850c4cdc | 2239 | struct drm_device *dev = fb->dev; |
ce453d81 | 2240 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2241 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2242 | struct i915_ggtt_view view; |
6b95a207 KH |
2243 | u32 alignment; |
2244 | int ret; | |
2245 | ||
ebcdd39e MR |
2246 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2247 | ||
603525d7 | 2248 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2249 | |
3465c580 | 2250 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2251 | |
693db184 CW |
2252 | /* Note that the w/a also requires 64 PTE of padding following the |
2253 | * bo. We currently fill all unused PTE with the shadow page and so | |
2254 | * we should always have valid PTE following the scanout preventing | |
2255 | * the VT-d warning. | |
2256 | */ | |
2257 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2258 | alignment = 256 * 1024; | |
2259 | ||
d6dd6843 PZ |
2260 | /* |
2261 | * Global gtt pte registers are special registers which actually forward | |
2262 | * writes to a chunk of system memory. Which means that there is no risk | |
2263 | * that the register values disappear as soon as we call | |
2264 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2265 | * pin/unpin/fence and not more. | |
2266 | */ | |
2267 | intel_runtime_pm_get(dev_priv); | |
2268 | ||
7580d774 ML |
2269 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2270 | &view); | |
48b956c5 | 2271 | if (ret) |
b26a6b35 | 2272 | goto err_pm; |
6b95a207 KH |
2273 | |
2274 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2275 | * fence, whereas 965+ only requires a fence if using | |
2276 | * framebuffer compression. For simplicity, we always install | |
2277 | * a fence as the cost is not that onerous. | |
2278 | */ | |
9807216f VK |
2279 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2280 | ret = i915_gem_object_get_fence(obj); | |
2281 | if (ret == -EDEADLK) { | |
2282 | /* | |
2283 | * -EDEADLK means there are no free fences | |
2284 | * no pending flips. | |
2285 | * | |
2286 | * This is propagated to atomic, but it uses | |
2287 | * -EDEADLK to force a locking recovery, so | |
2288 | * change the returned error to -EBUSY. | |
2289 | */ | |
2290 | ret = -EBUSY; | |
2291 | goto err_unpin; | |
2292 | } else if (ret) | |
2293 | goto err_unpin; | |
1690e1eb | 2294 | |
9807216f VK |
2295 | i915_gem_object_pin_fence(obj); |
2296 | } | |
6b95a207 | 2297 | |
d6dd6843 | 2298 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2299 | return 0; |
48b956c5 CW |
2300 | |
2301 | err_unpin: | |
f64b98cd | 2302 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2303 | err_pm: |
d6dd6843 | 2304 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2305 | return ret; |
6b95a207 KH |
2306 | } |
2307 | ||
3465c580 | 2308 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2309 | { |
82bc3b2d | 2310 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2311 | struct i915_ggtt_view view; |
82bc3b2d | 2312 | |
ebcdd39e MR |
2313 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2314 | ||
3465c580 | 2315 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2316 | |
9807216f VK |
2317 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2318 | i915_gem_object_unpin_fence(obj); | |
2319 | ||
f64b98cd | 2320 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2321 | } |
2322 | ||
29cf9491 VS |
2323 | /* |
2324 | * Adjust the tile offset by moving the difference into | |
2325 | * the x/y offsets. | |
2326 | * | |
2327 | * Input tile dimensions and pitch must already be | |
2328 | * rotated to match x and y, and in pixel units. | |
2329 | */ | |
2330 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2331 | unsigned int tile_width, | |
2332 | unsigned int tile_height, | |
2333 | unsigned int tile_size, | |
2334 | unsigned int pitch_tiles, | |
2335 | u32 old_offset, | |
2336 | u32 new_offset) | |
2337 | { | |
2338 | unsigned int tiles; | |
2339 | ||
2340 | WARN_ON(old_offset & (tile_size - 1)); | |
2341 | WARN_ON(new_offset & (tile_size - 1)); | |
2342 | WARN_ON(new_offset > old_offset); | |
2343 | ||
2344 | tiles = (old_offset - new_offset) / tile_size; | |
2345 | ||
2346 | *y += tiles / pitch_tiles * tile_height; | |
2347 | *x += tiles % pitch_tiles * tile_width; | |
2348 | ||
2349 | return new_offset; | |
2350 | } | |
2351 | ||
8d0deca8 VS |
2352 | /* |
2353 | * Computes the linear offset to the base tile and adjusts | |
2354 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2355 | * | |
2356 | * In the 90/270 rotated case, x and y are assumed | |
2357 | * to be already rotated to match the rotated GTT view, and | |
2358 | * pitch is the tile_height aligned framebuffer height. | |
2359 | */ | |
4f2d9934 VS |
2360 | u32 intel_compute_tile_offset(int *x, int *y, |
2361 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2362 | unsigned int pitch, |
2363 | unsigned int rotation) | |
c2c75131 | 2364 | { |
4f2d9934 VS |
2365 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2366 | uint64_t fb_modifier = fb->modifier[plane]; | |
2367 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2368 | u32 offset, offset_aligned, alignment; |
2369 | ||
2370 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2371 | if (alignment) | |
2372 | alignment--; | |
2373 | ||
b5c65338 | 2374 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2375 | unsigned int tile_size, tile_width, tile_height; |
2376 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2377 | |
d843310d | 2378 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2379 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2380 | fb_modifier, cpp); | |
2381 | ||
2382 | if (intel_rotation_90_or_270(rotation)) { | |
2383 | pitch_tiles = pitch / tile_height; | |
2384 | swap(tile_width, tile_height); | |
2385 | } else { | |
2386 | pitch_tiles = pitch / (tile_width * cpp); | |
2387 | } | |
d843310d VS |
2388 | |
2389 | tile_rows = *y / tile_height; | |
2390 | *y %= tile_height; | |
c2c75131 | 2391 | |
8d0deca8 VS |
2392 | tiles = *x / tile_width; |
2393 | *x %= tile_width; | |
bc752862 | 2394 | |
29cf9491 VS |
2395 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2396 | offset_aligned = offset & ~alignment; | |
bc752862 | 2397 | |
29cf9491 VS |
2398 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2399 | tile_size, pitch_tiles, | |
2400 | offset, offset_aligned); | |
2401 | } else { | |
bc752862 | 2402 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2403 | offset_aligned = offset & ~alignment; |
2404 | ||
4e9a86b6 VS |
2405 | *y = (offset & alignment) / pitch; |
2406 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2407 | } |
29cf9491 VS |
2408 | |
2409 | return offset_aligned; | |
c2c75131 DV |
2410 | } |
2411 | ||
b35d63fa | 2412 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2413 | { |
2414 | switch (format) { | |
2415 | case DISPPLANE_8BPP: | |
2416 | return DRM_FORMAT_C8; | |
2417 | case DISPPLANE_BGRX555: | |
2418 | return DRM_FORMAT_XRGB1555; | |
2419 | case DISPPLANE_BGRX565: | |
2420 | return DRM_FORMAT_RGB565; | |
2421 | default: | |
2422 | case DISPPLANE_BGRX888: | |
2423 | return DRM_FORMAT_XRGB8888; | |
2424 | case DISPPLANE_RGBX888: | |
2425 | return DRM_FORMAT_XBGR8888; | |
2426 | case DISPPLANE_BGRX101010: | |
2427 | return DRM_FORMAT_XRGB2101010; | |
2428 | case DISPPLANE_RGBX101010: | |
2429 | return DRM_FORMAT_XBGR2101010; | |
2430 | } | |
2431 | } | |
2432 | ||
bc8d7dff DL |
2433 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2434 | { | |
2435 | switch (format) { | |
2436 | case PLANE_CTL_FORMAT_RGB_565: | |
2437 | return DRM_FORMAT_RGB565; | |
2438 | default: | |
2439 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2440 | if (rgb_order) { | |
2441 | if (alpha) | |
2442 | return DRM_FORMAT_ABGR8888; | |
2443 | else | |
2444 | return DRM_FORMAT_XBGR8888; | |
2445 | } else { | |
2446 | if (alpha) | |
2447 | return DRM_FORMAT_ARGB8888; | |
2448 | else | |
2449 | return DRM_FORMAT_XRGB8888; | |
2450 | } | |
2451 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2452 | if (rgb_order) | |
2453 | return DRM_FORMAT_XBGR2101010; | |
2454 | else | |
2455 | return DRM_FORMAT_XRGB2101010; | |
2456 | } | |
2457 | } | |
2458 | ||
5724dbd1 | 2459 | static bool |
f6936e29 DV |
2460 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2461 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2462 | { |
2463 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2464 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2465 | struct drm_i915_gem_object *obj = NULL; |
2466 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2467 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2468 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2469 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2470 | PAGE_SIZE); | |
2471 | ||
2472 | size_aligned -= base_aligned; | |
46f297fb | 2473 | |
ff2652ea CW |
2474 | if (plane_config->size == 0) |
2475 | return false; | |
2476 | ||
3badb49f PZ |
2477 | /* If the FB is too big, just don't use it since fbdev is not very |
2478 | * important and we should probably use that space with FBC or other | |
2479 | * features. */ | |
62106b4f | 2480 | if (size_aligned * 2 > dev_priv->ggtt.stolen_usable_size) |
3badb49f PZ |
2481 | return false; |
2482 | ||
12c83d99 TU |
2483 | mutex_lock(&dev->struct_mutex); |
2484 | ||
f37b5c2b DV |
2485 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2486 | base_aligned, | |
2487 | base_aligned, | |
2488 | size_aligned); | |
12c83d99 TU |
2489 | if (!obj) { |
2490 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2491 | return false; |
12c83d99 | 2492 | } |
46f297fb | 2493 | |
49af449b DL |
2494 | obj->tiling_mode = plane_config->tiling; |
2495 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2496 | obj->stride = fb->pitches[0]; |
46f297fb | 2497 | |
6bf129df DL |
2498 | mode_cmd.pixel_format = fb->pixel_format; |
2499 | mode_cmd.width = fb->width; | |
2500 | mode_cmd.height = fb->height; | |
2501 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2502 | mode_cmd.modifier[0] = fb->modifier[0]; |
2503 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2504 | |
6bf129df | 2505 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2506 | &mode_cmd, obj)) { |
46f297fb JB |
2507 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2508 | goto out_unref_obj; | |
2509 | } | |
12c83d99 | 2510 | |
46f297fb | 2511 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2512 | |
f6936e29 | 2513 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2514 | return true; |
46f297fb JB |
2515 | |
2516 | out_unref_obj: | |
2517 | drm_gem_object_unreference(&obj->base); | |
2518 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2519 | return false; |
2520 | } | |
2521 | ||
afd65eb4 MR |
2522 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2523 | static void | |
2524 | update_state_fb(struct drm_plane *plane) | |
2525 | { | |
2526 | if (plane->fb == plane->state->fb) | |
2527 | return; | |
2528 | ||
2529 | if (plane->state->fb) | |
2530 | drm_framebuffer_unreference(plane->state->fb); | |
2531 | plane->state->fb = plane->fb; | |
2532 | if (plane->state->fb) | |
2533 | drm_framebuffer_reference(plane->state->fb); | |
2534 | } | |
2535 | ||
5724dbd1 | 2536 | static void |
f6936e29 DV |
2537 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2538 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2539 | { |
2540 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2541 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2542 | struct drm_crtc *c; |
2543 | struct intel_crtc *i; | |
2ff8fde1 | 2544 | struct drm_i915_gem_object *obj; |
88595ac9 | 2545 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2546 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2547 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2548 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2549 | struct intel_plane_state *intel_state = |
2550 | to_intel_plane_state(plane_state); | |
88595ac9 | 2551 | struct drm_framebuffer *fb; |
484b41dd | 2552 | |
2d14030b | 2553 | if (!plane_config->fb) |
484b41dd JB |
2554 | return; |
2555 | ||
f6936e29 | 2556 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2557 | fb = &plane_config->fb->base; |
2558 | goto valid_fb; | |
f55548b5 | 2559 | } |
484b41dd | 2560 | |
2d14030b | 2561 | kfree(plane_config->fb); |
484b41dd JB |
2562 | |
2563 | /* | |
2564 | * Failed to alloc the obj, check to see if we should share | |
2565 | * an fb with another CRTC instead | |
2566 | */ | |
70e1e0ec | 2567 | for_each_crtc(dev, c) { |
484b41dd JB |
2568 | i = to_intel_crtc(c); |
2569 | ||
2570 | if (c == &intel_crtc->base) | |
2571 | continue; | |
2572 | ||
2ff8fde1 MR |
2573 | if (!i->active) |
2574 | continue; | |
2575 | ||
88595ac9 DV |
2576 | fb = c->primary->fb; |
2577 | if (!fb) | |
484b41dd JB |
2578 | continue; |
2579 | ||
88595ac9 | 2580 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2581 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2582 | drm_framebuffer_reference(fb); |
2583 | goto valid_fb; | |
484b41dd JB |
2584 | } |
2585 | } | |
88595ac9 | 2586 | |
200757f5 MR |
2587 | /* |
2588 | * We've failed to reconstruct the BIOS FB. Current display state | |
2589 | * indicates that the primary plane is visible, but has a NULL FB, | |
2590 | * which will lead to problems later if we don't fix it up. The | |
2591 | * simplest solution is to just disable the primary plane now and | |
2592 | * pretend the BIOS never had it enabled. | |
2593 | */ | |
2594 | to_intel_plane_state(plane_state)->visible = false; | |
2595 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2596 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2597 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2598 | ||
88595ac9 DV |
2599 | return; |
2600 | ||
2601 | valid_fb: | |
f44e2659 VS |
2602 | plane_state->src_x = 0; |
2603 | plane_state->src_y = 0; | |
be5651f2 ML |
2604 | plane_state->src_w = fb->width << 16; |
2605 | plane_state->src_h = fb->height << 16; | |
2606 | ||
f44e2659 VS |
2607 | plane_state->crtc_x = 0; |
2608 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2609 | plane_state->crtc_w = fb->width; |
2610 | plane_state->crtc_h = fb->height; | |
2611 | ||
0a8d8a86 MR |
2612 | intel_state->src.x1 = plane_state->src_x; |
2613 | intel_state->src.y1 = plane_state->src_y; | |
2614 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2615 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2616 | intel_state->dst.x1 = plane_state->crtc_x; | |
2617 | intel_state->dst.y1 = plane_state->crtc_y; | |
2618 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2619 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2620 | ||
88595ac9 DV |
2621 | obj = intel_fb_obj(fb); |
2622 | if (obj->tiling_mode != I915_TILING_NONE) | |
2623 | dev_priv->preserve_bios_swizzle = true; | |
2624 | ||
be5651f2 ML |
2625 | drm_framebuffer_reference(fb); |
2626 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2627 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2628 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2629 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2630 | } |
2631 | ||
a8d201af ML |
2632 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2633 | const struct intel_crtc_state *crtc_state, | |
2634 | const struct intel_plane_state *plane_state) | |
81255565 | 2635 | { |
a8d201af | 2636 | struct drm_device *dev = primary->dev; |
81255565 | 2637 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2638 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2639 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2640 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2641 | int plane = intel_crtc->plane; |
54ea9da8 | 2642 | u32 linear_offset; |
81255565 | 2643 | u32 dspcntr; |
f0f59a00 | 2644 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2645 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2646 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2647 | int x = plane_state->src.x1 >> 16; |
2648 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2649 | |
f45651ba VS |
2650 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2651 | ||
fdd508a6 | 2652 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2653 | |
2654 | if (INTEL_INFO(dev)->gen < 4) { | |
2655 | if (intel_crtc->pipe == PIPE_B) | |
2656 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2657 | ||
2658 | /* pipesrc and dspsize control the size that is scaled from, | |
2659 | * which should always be the user's requested size. | |
2660 | */ | |
2661 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2662 | ((crtc_state->pipe_src_h - 1) << 16) | |
2663 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2664 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2665 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2666 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2667 | ((crtc_state->pipe_src_h - 1) << 16) | |
2668 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2669 | I915_WRITE(PRIMPOS(plane), 0); |
2670 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2671 | } |
81255565 | 2672 | |
57779d06 VS |
2673 | switch (fb->pixel_format) { |
2674 | case DRM_FORMAT_C8: | |
81255565 JB |
2675 | dspcntr |= DISPPLANE_8BPP; |
2676 | break; | |
57779d06 | 2677 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2678 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2679 | break; |
57779d06 VS |
2680 | case DRM_FORMAT_RGB565: |
2681 | dspcntr |= DISPPLANE_BGRX565; | |
2682 | break; | |
2683 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2684 | dspcntr |= DISPPLANE_BGRX888; |
2685 | break; | |
2686 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2687 | dspcntr |= DISPPLANE_RGBX888; |
2688 | break; | |
2689 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2690 | dspcntr |= DISPPLANE_BGRX101010; |
2691 | break; | |
2692 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2693 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2694 | break; |
2695 | default: | |
baba133a | 2696 | BUG(); |
81255565 | 2697 | } |
57779d06 | 2698 | |
f45651ba VS |
2699 | if (INTEL_INFO(dev)->gen >= 4 && |
2700 | obj->tiling_mode != I915_TILING_NONE) | |
2701 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2702 | |
de1aa629 VS |
2703 | if (IS_G4X(dev)) |
2704 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2705 | ||
ac484963 | 2706 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2707 | |
c2c75131 DV |
2708 | if (INTEL_INFO(dev)->gen >= 4) { |
2709 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2710 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2711 | fb->pitches[0], rotation); |
c2c75131 DV |
2712 | linear_offset -= intel_crtc->dspaddr_offset; |
2713 | } else { | |
e506a0c6 | 2714 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2715 | } |
e506a0c6 | 2716 | |
8d0deca8 | 2717 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2718 | dspcntr |= DISPPLANE_ROTATE_180; |
2719 | ||
a8d201af ML |
2720 | x += (crtc_state->pipe_src_w - 1); |
2721 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2722 | |
2723 | /* Finding the last pixel of the last line of the display | |
2724 | data and adding to linear_offset*/ | |
2725 | linear_offset += | |
a8d201af | 2726 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2727 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2728 | } |
2729 | ||
2db3366b PZ |
2730 | intel_crtc->adjusted_x = x; |
2731 | intel_crtc->adjusted_y = y; | |
2732 | ||
48404c1e SJ |
2733 | I915_WRITE(reg, dspcntr); |
2734 | ||
01f2c773 | 2735 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2736 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2737 | I915_WRITE(DSPSURF(plane), |
2738 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2739 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2740 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2741 | } else |
f343c5f6 | 2742 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2743 | POSTING_READ(reg); |
17638cd6 JB |
2744 | } |
2745 | ||
a8d201af ML |
2746 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2747 | struct drm_crtc *crtc) | |
17638cd6 JB |
2748 | { |
2749 | struct drm_device *dev = crtc->dev; | |
2750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2751 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2752 | int plane = intel_crtc->plane; |
f45651ba | 2753 | |
a8d201af ML |
2754 | I915_WRITE(DSPCNTR(plane), 0); |
2755 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2756 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2757 | else |
2758 | I915_WRITE(DSPADDR(plane), 0); | |
2759 | POSTING_READ(DSPCNTR(plane)); | |
2760 | } | |
c9ba6fad | 2761 | |
a8d201af ML |
2762 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2763 | const struct intel_crtc_state *crtc_state, | |
2764 | const struct intel_plane_state *plane_state) | |
2765 | { | |
2766 | struct drm_device *dev = primary->dev; | |
2767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2769 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2770 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2771 | int plane = intel_crtc->plane; | |
54ea9da8 | 2772 | u32 linear_offset; |
a8d201af ML |
2773 | u32 dspcntr; |
2774 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2775 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2776 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2777 | int x = plane_state->src.x1 >> 16; |
2778 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2779 | |
f45651ba | 2780 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2781 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2782 | |
2783 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2784 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2785 | |
57779d06 VS |
2786 | switch (fb->pixel_format) { |
2787 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2788 | dspcntr |= DISPPLANE_8BPP; |
2789 | break; | |
57779d06 VS |
2790 | case DRM_FORMAT_RGB565: |
2791 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2792 | break; |
57779d06 | 2793 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2794 | dspcntr |= DISPPLANE_BGRX888; |
2795 | break; | |
2796 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2797 | dspcntr |= DISPPLANE_RGBX888; |
2798 | break; | |
2799 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2800 | dspcntr |= DISPPLANE_BGRX101010; |
2801 | break; | |
2802 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2803 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2804 | break; |
2805 | default: | |
baba133a | 2806 | BUG(); |
17638cd6 JB |
2807 | } |
2808 | ||
2809 | if (obj->tiling_mode != I915_TILING_NONE) | |
2810 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2811 | |
f45651ba | 2812 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2813 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2814 | |
ac484963 | 2815 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2816 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2817 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2818 | fb->pitches[0], rotation); |
c2c75131 | 2819 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2820 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2821 | dspcntr |= DISPPLANE_ROTATE_180; |
2822 | ||
2823 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2824 | x += (crtc_state->pipe_src_w - 1); |
2825 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2826 | |
2827 | /* Finding the last pixel of the last line of the display | |
2828 | data and adding to linear_offset*/ | |
2829 | linear_offset += | |
a8d201af | 2830 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2831 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2832 | } |
2833 | } | |
2834 | ||
2db3366b PZ |
2835 | intel_crtc->adjusted_x = x; |
2836 | intel_crtc->adjusted_y = y; | |
2837 | ||
48404c1e | 2838 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2839 | |
01f2c773 | 2840 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2841 | I915_WRITE(DSPSURF(plane), |
2842 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2843 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2844 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2845 | } else { | |
2846 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2847 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2848 | } | |
17638cd6 | 2849 | POSTING_READ(reg); |
17638cd6 JB |
2850 | } |
2851 | ||
7b49f948 VS |
2852 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2853 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2854 | { |
7b49f948 | 2855 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2856 | return 64; |
7b49f948 VS |
2857 | } else { |
2858 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2859 | ||
27ba3910 | 2860 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2861 | } |
2862 | } | |
2863 | ||
44eb0cb9 MK |
2864 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2865 | struct drm_i915_gem_object *obj, | |
2866 | unsigned int plane) | |
121920fa | 2867 | { |
ce7f1728 | 2868 | struct i915_ggtt_view view; |
dedf278c | 2869 | struct i915_vma *vma; |
44eb0cb9 | 2870 | u64 offset; |
121920fa | 2871 | |
e7941294 | 2872 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2873 | intel_plane->base.state->rotation); |
121920fa | 2874 | |
ce7f1728 | 2875 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2876 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2877 | view.type)) |
dedf278c TU |
2878 | return -1; |
2879 | ||
44eb0cb9 | 2880 | offset = vma->node.start; |
dedf278c TU |
2881 | |
2882 | if (plane == 1) { | |
7723f47d | 2883 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2884 | PAGE_SIZE; |
2885 | } | |
2886 | ||
44eb0cb9 MK |
2887 | WARN_ON(upper_32_bits(offset)); |
2888 | ||
2889 | return lower_32_bits(offset); | |
121920fa TU |
2890 | } |
2891 | ||
e435d6e5 ML |
2892 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2893 | { | |
2894 | struct drm_device *dev = intel_crtc->base.dev; | |
2895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2896 | ||
2897 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2898 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2899 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2900 | } |
2901 | ||
a1b2278e CK |
2902 | /* |
2903 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2904 | */ | |
0583236e | 2905 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2906 | { |
a1b2278e CK |
2907 | struct intel_crtc_scaler_state *scaler_state; |
2908 | int i; | |
2909 | ||
a1b2278e CK |
2910 | scaler_state = &intel_crtc->config->scaler_state; |
2911 | ||
2912 | /* loop through and disable scalers that aren't in use */ | |
2913 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2914 | if (!scaler_state->scalers[i].in_use) |
2915 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2916 | } |
2917 | } | |
2918 | ||
6156a456 | 2919 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2920 | { |
6156a456 | 2921 | switch (pixel_format) { |
d161cf7a | 2922 | case DRM_FORMAT_C8: |
c34ce3d1 | 2923 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2924 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2925 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2926 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2927 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2928 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2929 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2930 | /* |
2931 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2932 | * to be already pre-multiplied. We need to add a knob (or a different | |
2933 | * DRM_FORMAT) for user-space to configure that. | |
2934 | */ | |
f75fb42a | 2935 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2936 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2937 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2938 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2939 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2940 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2941 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2942 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2943 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2944 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2945 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2946 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2947 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2948 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2949 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2950 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2951 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2952 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2953 | default: |
4249eeef | 2954 | MISSING_CASE(pixel_format); |
70d21f0e | 2955 | } |
8cfcba41 | 2956 | |
c34ce3d1 | 2957 | return 0; |
6156a456 | 2958 | } |
70d21f0e | 2959 | |
6156a456 CK |
2960 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2961 | { | |
6156a456 | 2962 | switch (fb_modifier) { |
30af77c4 | 2963 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2964 | break; |
30af77c4 | 2965 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2966 | return PLANE_CTL_TILED_X; |
b321803d | 2967 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2968 | return PLANE_CTL_TILED_Y; |
b321803d | 2969 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2970 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2971 | default: |
6156a456 | 2972 | MISSING_CASE(fb_modifier); |
70d21f0e | 2973 | } |
8cfcba41 | 2974 | |
c34ce3d1 | 2975 | return 0; |
6156a456 | 2976 | } |
70d21f0e | 2977 | |
6156a456 CK |
2978 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2979 | { | |
3b7a5119 | 2980 | switch (rotation) { |
6156a456 CK |
2981 | case BIT(DRM_ROTATE_0): |
2982 | break; | |
1e8df167 SJ |
2983 | /* |
2984 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2985 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2986 | */ | |
3b7a5119 | 2987 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2988 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2989 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2990 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2991 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2992 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2993 | default: |
2994 | MISSING_CASE(rotation); | |
2995 | } | |
2996 | ||
c34ce3d1 | 2997 | return 0; |
6156a456 CK |
2998 | } |
2999 | ||
a8d201af ML |
3000 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3001 | const struct intel_crtc_state *crtc_state, | |
3002 | const struct intel_plane_state *plane_state) | |
6156a456 | 3003 | { |
a8d201af | 3004 | struct drm_device *dev = plane->dev; |
6156a456 | 3005 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3006 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3007 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3008 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3009 | int pipe = intel_crtc->pipe; |
3010 | u32 plane_ctl, stride_div, stride; | |
3011 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3012 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3013 | int x_offset, y_offset; |
44eb0cb9 | 3014 | u32 surf_addr; |
a8d201af ML |
3015 | int scaler_id = plane_state->scaler_id; |
3016 | int src_x = plane_state->src.x1 >> 16; | |
3017 | int src_y = plane_state->src.y1 >> 16; | |
3018 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3019 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3020 | int dst_x = plane_state->dst.x1; | |
3021 | int dst_y = plane_state->dst.y1; | |
3022 | int dst_w = drm_rect_width(&plane_state->dst); | |
3023 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3024 | |
6156a456 CK |
3025 | plane_ctl = PLANE_CTL_ENABLE | |
3026 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3027 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3028 | ||
3029 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3030 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3031 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3032 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3033 | ||
7b49f948 | 3034 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3035 | fb->pixel_format); |
dedf278c | 3036 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3037 | |
a42e5a23 PZ |
3038 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3039 | ||
3b7a5119 | 3040 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3041 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3042 | ||
3b7a5119 | 3043 | /* stride = Surface height in tiles */ |
832be82f | 3044 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3045 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3046 | x_offset = stride * tile_height - src_y - src_h; |
3047 | y_offset = src_x; | |
6156a456 | 3048 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3049 | } else { |
3050 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3051 | x_offset = src_x; |
3052 | y_offset = src_y; | |
6156a456 | 3053 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3054 | } |
3055 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3056 | |
2db3366b PZ |
3057 | intel_crtc->adjusted_x = x_offset; |
3058 | intel_crtc->adjusted_y = y_offset; | |
3059 | ||
70d21f0e | 3060 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3061 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3062 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3063 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3064 | |
3065 | if (scaler_id >= 0) { | |
3066 | uint32_t ps_ctrl = 0; | |
3067 | ||
3068 | WARN_ON(!dst_w || !dst_h); | |
3069 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3070 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3071 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3072 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3073 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3074 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3075 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3076 | } else { | |
3077 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3078 | } | |
3079 | ||
121920fa | 3080 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3081 | |
3082 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3083 | } | |
3084 | ||
a8d201af ML |
3085 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3086 | struct drm_crtc *crtc) | |
17638cd6 JB |
3087 | { |
3088 | struct drm_device *dev = crtc->dev; | |
3089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3090 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3091 | |
a8d201af ML |
3092 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3093 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3094 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3095 | } | |
29b9bde6 | 3096 | |
a8d201af ML |
3097 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3098 | static int | |
3099 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3100 | int x, int y, enum mode_set_atomic state) | |
3101 | { | |
3102 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3103 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3104 | ||
3105 | return -ENODEV; | |
81255565 JB |
3106 | } |
3107 | ||
7514747d | 3108 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3109 | { |
96a02917 VS |
3110 | struct drm_crtc *crtc; |
3111 | ||
70e1e0ec | 3112 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3113 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3114 | enum plane plane = intel_crtc->plane; | |
3115 | ||
3116 | intel_prepare_page_flip(dev, plane); | |
3117 | intel_finish_page_flip_plane(dev, plane); | |
3118 | } | |
7514747d VS |
3119 | } |
3120 | ||
3121 | static void intel_update_primary_planes(struct drm_device *dev) | |
3122 | { | |
7514747d | 3123 | struct drm_crtc *crtc; |
96a02917 | 3124 | |
70e1e0ec | 3125 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3126 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3127 | struct intel_plane_state *plane_state; | |
96a02917 | 3128 | |
11c22da6 | 3129 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3130 | plane_state = to_intel_plane_state(plane->base.state); |
3131 | ||
a8d201af ML |
3132 | if (plane_state->visible) |
3133 | plane->update_plane(&plane->base, | |
3134 | to_intel_crtc_state(crtc->state), | |
3135 | plane_state); | |
11c22da6 ML |
3136 | |
3137 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3138 | } |
3139 | } | |
3140 | ||
7514747d VS |
3141 | void intel_prepare_reset(struct drm_device *dev) |
3142 | { | |
3143 | /* no reset support for gen2 */ | |
3144 | if (IS_GEN2(dev)) | |
3145 | return; | |
3146 | ||
3147 | /* reset doesn't touch the display */ | |
3148 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3149 | return; | |
3150 | ||
3151 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3152 | /* |
3153 | * Disabling the crtcs gracefully seems nicer. Also the | |
3154 | * g33 docs say we should at least disable all the planes. | |
3155 | */ | |
6b72d486 | 3156 | intel_display_suspend(dev); |
7514747d VS |
3157 | } |
3158 | ||
3159 | void intel_finish_reset(struct drm_device *dev) | |
3160 | { | |
3161 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3162 | ||
3163 | /* | |
3164 | * Flips in the rings will be nuked by the reset, | |
3165 | * so complete all pending flips so that user space | |
3166 | * will get its events and not get stuck. | |
3167 | */ | |
3168 | intel_complete_page_flips(dev); | |
3169 | ||
3170 | /* no reset support for gen2 */ | |
3171 | if (IS_GEN2(dev)) | |
3172 | return; | |
3173 | ||
3174 | /* reset doesn't touch the display */ | |
3175 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3176 | /* | |
3177 | * Flips in the rings have been nuked by the reset, | |
3178 | * so update the base address of all primary | |
3179 | * planes to the the last fb to make sure we're | |
3180 | * showing the correct fb after a reset. | |
11c22da6 ML |
3181 | * |
3182 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3183 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3184 | */ |
3185 | intel_update_primary_planes(dev); | |
3186 | return; | |
3187 | } | |
3188 | ||
3189 | /* | |
3190 | * The display has been reset as well, | |
3191 | * so need a full re-initialization. | |
3192 | */ | |
3193 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3194 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3195 | ||
3196 | intel_modeset_init_hw(dev); | |
3197 | ||
3198 | spin_lock_irq(&dev_priv->irq_lock); | |
3199 | if (dev_priv->display.hpd_irq_setup) | |
3200 | dev_priv->display.hpd_irq_setup(dev); | |
3201 | spin_unlock_irq(&dev_priv->irq_lock); | |
3202 | ||
043e9bda | 3203 | intel_display_resume(dev); |
7514747d VS |
3204 | |
3205 | intel_hpd_init(dev_priv); | |
3206 | ||
3207 | drm_modeset_unlock_all(dev); | |
3208 | } | |
3209 | ||
7d5e3799 CW |
3210 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3211 | { | |
3212 | struct drm_device *dev = crtc->dev; | |
3213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3215 | bool pending; |
3216 | ||
3217 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3218 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3219 | return false; | |
3220 | ||
5e2d7afc | 3221 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3222 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3223 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3224 | |
3225 | return pending; | |
3226 | } | |
3227 | ||
bfd16b2a ML |
3228 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3229 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3230 | { |
3231 | struct drm_device *dev = crtc->base.dev; | |
3232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3233 | struct intel_crtc_state *pipe_config = |
3234 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3235 | |
bfd16b2a ML |
3236 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3237 | crtc->base.mode = crtc->base.state->mode; | |
3238 | ||
3239 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3240 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3241 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3242 | |
44522d85 | 3243 | if (HAS_DDI(dev)) |
8563b1e8 | 3244 | intel_color_set_csc(&crtc->base); |
44522d85 | 3245 | |
e30e8f75 GP |
3246 | /* |
3247 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3248 | * that in compute_mode_changes we check the native mode (not the pfit | |
3249 | * mode) to see if we can flip rather than do a full mode set. In the | |
3250 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3251 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3252 | * sized surface. | |
e30e8f75 GP |
3253 | */ |
3254 | ||
e30e8f75 | 3255 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3256 | ((pipe_config->pipe_src_w - 1) << 16) | |
3257 | (pipe_config->pipe_src_h - 1)); | |
3258 | ||
3259 | /* on skylake this is done by detaching scalers */ | |
3260 | if (INTEL_INFO(dev)->gen >= 9) { | |
3261 | skl_detach_scalers(crtc); | |
3262 | ||
3263 | if (pipe_config->pch_pfit.enabled) | |
3264 | skylake_pfit_enable(crtc); | |
3265 | } else if (HAS_PCH_SPLIT(dev)) { | |
3266 | if (pipe_config->pch_pfit.enabled) | |
3267 | ironlake_pfit_enable(crtc); | |
3268 | else if (old_crtc_state->pch_pfit.enabled) | |
3269 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3270 | } |
e30e8f75 GP |
3271 | } |
3272 | ||
5e84e1a4 ZW |
3273 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3274 | { | |
3275 | struct drm_device *dev = crtc->dev; | |
3276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3278 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3279 | i915_reg_t reg; |
3280 | u32 temp; | |
5e84e1a4 ZW |
3281 | |
3282 | /* enable normal train */ | |
3283 | reg = FDI_TX_CTL(pipe); | |
3284 | temp = I915_READ(reg); | |
61e499bf | 3285 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3286 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3287 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3288 | } else { |
3289 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3290 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3291 | } |
5e84e1a4 ZW |
3292 | I915_WRITE(reg, temp); |
3293 | ||
3294 | reg = FDI_RX_CTL(pipe); | |
3295 | temp = I915_READ(reg); | |
3296 | if (HAS_PCH_CPT(dev)) { | |
3297 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3298 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3299 | } else { | |
3300 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3301 | temp |= FDI_LINK_TRAIN_NONE; | |
3302 | } | |
3303 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3304 | ||
3305 | /* wait one idle pattern time */ | |
3306 | POSTING_READ(reg); | |
3307 | udelay(1000); | |
357555c0 JB |
3308 | |
3309 | /* IVB wants error correction enabled */ | |
3310 | if (IS_IVYBRIDGE(dev)) | |
3311 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3312 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3313 | } |
3314 | ||
8db9d77b ZW |
3315 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3316 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3317 | { | |
3318 | struct drm_device *dev = crtc->dev; | |
3319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3320 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3321 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3322 | i915_reg_t reg; |
3323 | u32 temp, tries; | |
8db9d77b | 3324 | |
1c8562f6 | 3325 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3326 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3327 | |
e1a44743 AJ |
3328 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3329 | for train result */ | |
5eddb70b CW |
3330 | reg = FDI_RX_IMR(pipe); |
3331 | temp = I915_READ(reg); | |
e1a44743 AJ |
3332 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3333 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3334 | I915_WRITE(reg, temp); |
3335 | I915_READ(reg); | |
e1a44743 AJ |
3336 | udelay(150); |
3337 | ||
8db9d77b | 3338 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3339 | reg = FDI_TX_CTL(pipe); |
3340 | temp = I915_READ(reg); | |
627eb5a3 | 3341 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3342 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3343 | temp &= ~FDI_LINK_TRAIN_NONE; |
3344 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3345 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3346 | |
5eddb70b CW |
3347 | reg = FDI_RX_CTL(pipe); |
3348 | temp = I915_READ(reg); | |
8db9d77b ZW |
3349 | temp &= ~FDI_LINK_TRAIN_NONE; |
3350 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3351 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3352 | ||
3353 | POSTING_READ(reg); | |
8db9d77b ZW |
3354 | udelay(150); |
3355 | ||
5b2adf89 | 3356 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3357 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3358 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3359 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3360 | |
5eddb70b | 3361 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3362 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3363 | temp = I915_READ(reg); |
8db9d77b ZW |
3364 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3365 | ||
3366 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3367 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3368 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3369 | break; |
3370 | } | |
8db9d77b | 3371 | } |
e1a44743 | 3372 | if (tries == 5) |
5eddb70b | 3373 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3374 | |
3375 | /* Train 2 */ | |
5eddb70b CW |
3376 | reg = FDI_TX_CTL(pipe); |
3377 | temp = I915_READ(reg); | |
8db9d77b ZW |
3378 | temp &= ~FDI_LINK_TRAIN_NONE; |
3379 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3380 | I915_WRITE(reg, temp); |
8db9d77b | 3381 | |
5eddb70b CW |
3382 | reg = FDI_RX_CTL(pipe); |
3383 | temp = I915_READ(reg); | |
8db9d77b ZW |
3384 | temp &= ~FDI_LINK_TRAIN_NONE; |
3385 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3386 | I915_WRITE(reg, temp); |
8db9d77b | 3387 | |
5eddb70b CW |
3388 | POSTING_READ(reg); |
3389 | udelay(150); | |
8db9d77b | 3390 | |
5eddb70b | 3391 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3392 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3393 | temp = I915_READ(reg); |
8db9d77b ZW |
3394 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3395 | ||
3396 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3397 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3398 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3399 | break; | |
3400 | } | |
8db9d77b | 3401 | } |
e1a44743 | 3402 | if (tries == 5) |
5eddb70b | 3403 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3404 | |
3405 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3406 | |
8db9d77b ZW |
3407 | } |
3408 | ||
0206e353 | 3409 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3410 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3411 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3412 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3413 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3414 | }; | |
3415 | ||
3416 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3417 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3418 | { | |
3419 | struct drm_device *dev = crtc->dev; | |
3420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3422 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3423 | i915_reg_t reg; |
3424 | u32 temp, i, retry; | |
8db9d77b | 3425 | |
e1a44743 AJ |
3426 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3427 | for train result */ | |
5eddb70b CW |
3428 | reg = FDI_RX_IMR(pipe); |
3429 | temp = I915_READ(reg); | |
e1a44743 AJ |
3430 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3431 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3432 | I915_WRITE(reg, temp); |
3433 | ||
3434 | POSTING_READ(reg); | |
e1a44743 AJ |
3435 | udelay(150); |
3436 | ||
8db9d77b | 3437 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3438 | reg = FDI_TX_CTL(pipe); |
3439 | temp = I915_READ(reg); | |
627eb5a3 | 3440 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3441 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3442 | temp &= ~FDI_LINK_TRAIN_NONE; |
3443 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3444 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3445 | /* SNB-B */ | |
3446 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3447 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3448 | |
d74cf324 DV |
3449 | I915_WRITE(FDI_RX_MISC(pipe), |
3450 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3451 | ||
5eddb70b CW |
3452 | reg = FDI_RX_CTL(pipe); |
3453 | temp = I915_READ(reg); | |
8db9d77b ZW |
3454 | if (HAS_PCH_CPT(dev)) { |
3455 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3456 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3457 | } else { | |
3458 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3459 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3460 | } | |
5eddb70b CW |
3461 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3462 | ||
3463 | POSTING_READ(reg); | |
8db9d77b ZW |
3464 | udelay(150); |
3465 | ||
0206e353 | 3466 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3467 | reg = FDI_TX_CTL(pipe); |
3468 | temp = I915_READ(reg); | |
8db9d77b ZW |
3469 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3470 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3471 | I915_WRITE(reg, temp); |
3472 | ||
3473 | POSTING_READ(reg); | |
8db9d77b ZW |
3474 | udelay(500); |
3475 | ||
fa37d39e SP |
3476 | for (retry = 0; retry < 5; retry++) { |
3477 | reg = FDI_RX_IIR(pipe); | |
3478 | temp = I915_READ(reg); | |
3479 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3480 | if (temp & FDI_RX_BIT_LOCK) { | |
3481 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3482 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3483 | break; | |
3484 | } | |
3485 | udelay(50); | |
8db9d77b | 3486 | } |
fa37d39e SP |
3487 | if (retry < 5) |
3488 | break; | |
8db9d77b ZW |
3489 | } |
3490 | if (i == 4) | |
5eddb70b | 3491 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3492 | |
3493 | /* Train 2 */ | |
5eddb70b CW |
3494 | reg = FDI_TX_CTL(pipe); |
3495 | temp = I915_READ(reg); | |
8db9d77b ZW |
3496 | temp &= ~FDI_LINK_TRAIN_NONE; |
3497 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3498 | if (IS_GEN6(dev)) { | |
3499 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3500 | /* SNB-B */ | |
3501 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3502 | } | |
5eddb70b | 3503 | I915_WRITE(reg, temp); |
8db9d77b | 3504 | |
5eddb70b CW |
3505 | reg = FDI_RX_CTL(pipe); |
3506 | temp = I915_READ(reg); | |
8db9d77b ZW |
3507 | if (HAS_PCH_CPT(dev)) { |
3508 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3509 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3510 | } else { | |
3511 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3512 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3513 | } | |
5eddb70b CW |
3514 | I915_WRITE(reg, temp); |
3515 | ||
3516 | POSTING_READ(reg); | |
8db9d77b ZW |
3517 | udelay(150); |
3518 | ||
0206e353 | 3519 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3520 | reg = FDI_TX_CTL(pipe); |
3521 | temp = I915_READ(reg); | |
8db9d77b ZW |
3522 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3523 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3524 | I915_WRITE(reg, temp); |
3525 | ||
3526 | POSTING_READ(reg); | |
8db9d77b ZW |
3527 | udelay(500); |
3528 | ||
fa37d39e SP |
3529 | for (retry = 0; retry < 5; retry++) { |
3530 | reg = FDI_RX_IIR(pipe); | |
3531 | temp = I915_READ(reg); | |
3532 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3533 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3534 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3535 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3536 | break; | |
3537 | } | |
3538 | udelay(50); | |
8db9d77b | 3539 | } |
fa37d39e SP |
3540 | if (retry < 5) |
3541 | break; | |
8db9d77b ZW |
3542 | } |
3543 | if (i == 4) | |
5eddb70b | 3544 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3545 | |
3546 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3547 | } | |
3548 | ||
357555c0 JB |
3549 | /* Manual link training for Ivy Bridge A0 parts */ |
3550 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3551 | { | |
3552 | struct drm_device *dev = crtc->dev; | |
3553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3554 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3555 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3556 | i915_reg_t reg; |
3557 | u32 temp, i, j; | |
357555c0 JB |
3558 | |
3559 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3560 | for train result */ | |
3561 | reg = FDI_RX_IMR(pipe); | |
3562 | temp = I915_READ(reg); | |
3563 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3564 | temp &= ~FDI_RX_BIT_LOCK; | |
3565 | I915_WRITE(reg, temp); | |
3566 | ||
3567 | POSTING_READ(reg); | |
3568 | udelay(150); | |
3569 | ||
01a415fd DV |
3570 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3571 | I915_READ(FDI_RX_IIR(pipe))); | |
3572 | ||
139ccd3f JB |
3573 | /* Try each vswing and preemphasis setting twice before moving on */ |
3574 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3575 | /* disable first in case we need to retry */ | |
3576 | reg = FDI_TX_CTL(pipe); | |
3577 | temp = I915_READ(reg); | |
3578 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3579 | temp &= ~FDI_TX_ENABLE; | |
3580 | I915_WRITE(reg, temp); | |
357555c0 | 3581 | |
139ccd3f JB |
3582 | reg = FDI_RX_CTL(pipe); |
3583 | temp = I915_READ(reg); | |
3584 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3585 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3586 | temp &= ~FDI_RX_ENABLE; | |
3587 | I915_WRITE(reg, temp); | |
357555c0 | 3588 | |
139ccd3f | 3589 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3590 | reg = FDI_TX_CTL(pipe); |
3591 | temp = I915_READ(reg); | |
139ccd3f | 3592 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3593 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3594 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3595 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3596 | temp |= snb_b_fdi_train_param[j/2]; |
3597 | temp |= FDI_COMPOSITE_SYNC; | |
3598 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3599 | |
139ccd3f JB |
3600 | I915_WRITE(FDI_RX_MISC(pipe), |
3601 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3602 | |
139ccd3f | 3603 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3604 | temp = I915_READ(reg); |
139ccd3f JB |
3605 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3606 | temp |= FDI_COMPOSITE_SYNC; | |
3607 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3608 | |
139ccd3f JB |
3609 | POSTING_READ(reg); |
3610 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3611 | |
139ccd3f JB |
3612 | for (i = 0; i < 4; i++) { |
3613 | reg = FDI_RX_IIR(pipe); | |
3614 | temp = I915_READ(reg); | |
3615 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3616 | |
139ccd3f JB |
3617 | if (temp & FDI_RX_BIT_LOCK || |
3618 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3619 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3620 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3621 | i); | |
3622 | break; | |
3623 | } | |
3624 | udelay(1); /* should be 0.5us */ | |
3625 | } | |
3626 | if (i == 4) { | |
3627 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3628 | continue; | |
3629 | } | |
357555c0 | 3630 | |
139ccd3f | 3631 | /* Train 2 */ |
357555c0 JB |
3632 | reg = FDI_TX_CTL(pipe); |
3633 | temp = I915_READ(reg); | |
139ccd3f JB |
3634 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3635 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3636 | I915_WRITE(reg, temp); | |
3637 | ||
3638 | reg = FDI_RX_CTL(pipe); | |
3639 | temp = I915_READ(reg); | |
3640 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3641 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3642 | I915_WRITE(reg, temp); |
3643 | ||
3644 | POSTING_READ(reg); | |
139ccd3f | 3645 | udelay(2); /* should be 1.5us */ |
357555c0 | 3646 | |
139ccd3f JB |
3647 | for (i = 0; i < 4; i++) { |
3648 | reg = FDI_RX_IIR(pipe); | |
3649 | temp = I915_READ(reg); | |
3650 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3651 | |
139ccd3f JB |
3652 | if (temp & FDI_RX_SYMBOL_LOCK || |
3653 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3654 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3655 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3656 | i); | |
3657 | goto train_done; | |
3658 | } | |
3659 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3660 | } |
139ccd3f JB |
3661 | if (i == 4) |
3662 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3663 | } |
357555c0 | 3664 | |
139ccd3f | 3665 | train_done: |
357555c0 JB |
3666 | DRM_DEBUG_KMS("FDI train done.\n"); |
3667 | } | |
3668 | ||
88cefb6c | 3669 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3670 | { |
88cefb6c | 3671 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3672 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3673 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3674 | i915_reg_t reg; |
3675 | u32 temp; | |
c64e311e | 3676 | |
c98e9dcf | 3677 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3678 | reg = FDI_RX_CTL(pipe); |
3679 | temp = I915_READ(reg); | |
627eb5a3 | 3680 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3681 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3682 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3683 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3684 | ||
3685 | POSTING_READ(reg); | |
c98e9dcf JB |
3686 | udelay(200); |
3687 | ||
3688 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3689 | temp = I915_READ(reg); |
3690 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3691 | ||
3692 | POSTING_READ(reg); | |
c98e9dcf JB |
3693 | udelay(200); |
3694 | ||
20749730 PZ |
3695 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3696 | reg = FDI_TX_CTL(pipe); | |
3697 | temp = I915_READ(reg); | |
3698 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3699 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3700 | |
20749730 PZ |
3701 | POSTING_READ(reg); |
3702 | udelay(100); | |
6be4a607 | 3703 | } |
0e23b99d JB |
3704 | } |
3705 | ||
88cefb6c DV |
3706 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3707 | { | |
3708 | struct drm_device *dev = intel_crtc->base.dev; | |
3709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3710 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3711 | i915_reg_t reg; |
3712 | u32 temp; | |
88cefb6c DV |
3713 | |
3714 | /* Switch from PCDclk to Rawclk */ | |
3715 | reg = FDI_RX_CTL(pipe); | |
3716 | temp = I915_READ(reg); | |
3717 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3718 | ||
3719 | /* Disable CPU FDI TX PLL */ | |
3720 | reg = FDI_TX_CTL(pipe); | |
3721 | temp = I915_READ(reg); | |
3722 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3723 | ||
3724 | POSTING_READ(reg); | |
3725 | udelay(100); | |
3726 | ||
3727 | reg = FDI_RX_CTL(pipe); | |
3728 | temp = I915_READ(reg); | |
3729 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3730 | ||
3731 | /* Wait for the clocks to turn off. */ | |
3732 | POSTING_READ(reg); | |
3733 | udelay(100); | |
3734 | } | |
3735 | ||
0fc932b8 JB |
3736 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3737 | { | |
3738 | struct drm_device *dev = crtc->dev; | |
3739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3741 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3742 | i915_reg_t reg; |
3743 | u32 temp; | |
0fc932b8 JB |
3744 | |
3745 | /* disable CPU FDI tx and PCH FDI rx */ | |
3746 | reg = FDI_TX_CTL(pipe); | |
3747 | temp = I915_READ(reg); | |
3748 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3749 | POSTING_READ(reg); | |
3750 | ||
3751 | reg = FDI_RX_CTL(pipe); | |
3752 | temp = I915_READ(reg); | |
3753 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3754 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3755 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3756 | ||
3757 | POSTING_READ(reg); | |
3758 | udelay(100); | |
3759 | ||
3760 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3761 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3762 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3763 | |
3764 | /* still set train pattern 1 */ | |
3765 | reg = FDI_TX_CTL(pipe); | |
3766 | temp = I915_READ(reg); | |
3767 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3768 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3769 | I915_WRITE(reg, temp); | |
3770 | ||
3771 | reg = FDI_RX_CTL(pipe); | |
3772 | temp = I915_READ(reg); | |
3773 | if (HAS_PCH_CPT(dev)) { | |
3774 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3775 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3776 | } else { | |
3777 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3778 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3779 | } | |
3780 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3781 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3782 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3783 | I915_WRITE(reg, temp); |
3784 | ||
3785 | POSTING_READ(reg); | |
3786 | udelay(100); | |
3787 | } | |
3788 | ||
5dce5b93 CW |
3789 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3790 | { | |
3791 | struct intel_crtc *crtc; | |
3792 | ||
3793 | /* Note that we don't need to be called with mode_config.lock here | |
3794 | * as our list of CRTC objects is static for the lifetime of the | |
3795 | * device and so cannot disappear as we iterate. Similarly, we can | |
3796 | * happily treat the predicates as racy, atomic checks as userspace | |
3797 | * cannot claim and pin a new fb without at least acquring the | |
3798 | * struct_mutex and so serialising with us. | |
3799 | */ | |
d3fcc808 | 3800 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3801 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3802 | continue; | |
3803 | ||
3804 | if (crtc->unpin_work) | |
3805 | intel_wait_for_vblank(dev, crtc->pipe); | |
3806 | ||
3807 | return true; | |
3808 | } | |
3809 | ||
3810 | return false; | |
3811 | } | |
3812 | ||
d6bbafa1 CW |
3813 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3814 | { | |
3815 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3816 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3817 | ||
3818 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3819 | smp_rmb(); | |
3820 | intel_crtc->unpin_work = NULL; | |
3821 | ||
3822 | if (work->event) | |
3823 | drm_send_vblank_event(intel_crtc->base.dev, | |
3824 | intel_crtc->pipe, | |
3825 | work->event); | |
3826 | ||
3827 | drm_crtc_vblank_put(&intel_crtc->base); | |
3828 | ||
3829 | wake_up_all(&dev_priv->pending_flip_queue); | |
3830 | queue_work(dev_priv->wq, &work->work); | |
3831 | ||
3832 | trace_i915_flip_complete(intel_crtc->plane, | |
3833 | work->pending_flip_obj); | |
3834 | } | |
3835 | ||
5008e874 | 3836 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3837 | { |
0f91128d | 3838 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3839 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3840 | long ret; |
e6c3a2a6 | 3841 | |
2c10d571 | 3842 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3843 | |
3844 | ret = wait_event_interruptible_timeout( | |
3845 | dev_priv->pending_flip_queue, | |
3846 | !intel_crtc_has_pending_flip(crtc), | |
3847 | 60*HZ); | |
3848 | ||
3849 | if (ret < 0) | |
3850 | return ret; | |
3851 | ||
3852 | if (ret == 0) { | |
9c787942 | 3853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3854 | |
5e2d7afc | 3855 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3856 | if (intel_crtc->unpin_work) { |
3857 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3858 | page_flip_completed(intel_crtc); | |
3859 | } | |
5e2d7afc | 3860 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3861 | } |
5bb61643 | 3862 | |
5008e874 | 3863 | return 0; |
e6c3a2a6 CW |
3864 | } |
3865 | ||
060f02d8 VS |
3866 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3867 | { | |
3868 | u32 temp; | |
3869 | ||
3870 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3871 | ||
3872 | mutex_lock(&dev_priv->sb_lock); | |
3873 | ||
3874 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3875 | temp |= SBI_SSCCTL_DISABLE; | |
3876 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3877 | ||
3878 | mutex_unlock(&dev_priv->sb_lock); | |
3879 | } | |
3880 | ||
e615efe4 ED |
3881 | /* Program iCLKIP clock to the desired frequency */ |
3882 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3883 | { | |
64b46a06 | 3884 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3885 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3886 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3887 | u32 temp; | |
3888 | ||
060f02d8 | 3889 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3890 | |
64b46a06 VS |
3891 | /* The iCLK virtual clock root frequency is in MHz, |
3892 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3893 | * divisors, it is necessary to divide one by another, so we | |
3894 | * convert the virtual clock precision to KHz here for higher | |
3895 | * precision. | |
3896 | */ | |
3897 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3898 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3899 | u32 iclk_pi_range = 64; | |
64b46a06 | 3900 | u32 desired_divisor; |
e615efe4 | 3901 | |
64b46a06 VS |
3902 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3903 | clock << auxdiv); | |
3904 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3905 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3906 | |
64b46a06 VS |
3907 | /* |
3908 | * Near 20MHz is a corner case which is | |
3909 | * out of range for the 7-bit divisor | |
3910 | */ | |
3911 | if (divsel <= 0x7f) | |
3912 | break; | |
e615efe4 ED |
3913 | } |
3914 | ||
3915 | /* This should not happen with any sane values */ | |
3916 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3917 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3918 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3919 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3920 | ||
3921 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3922 | clock, |
e615efe4 ED |
3923 | auxdiv, |
3924 | divsel, | |
3925 | phasedir, | |
3926 | phaseinc); | |
3927 | ||
060f02d8 VS |
3928 | mutex_lock(&dev_priv->sb_lock); |
3929 | ||
e615efe4 | 3930 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3931 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3932 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3933 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3934 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3935 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3936 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3937 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3938 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3939 | |
3940 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3941 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3942 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3943 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3944 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3945 | |
3946 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3947 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3948 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3949 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3950 | |
060f02d8 VS |
3951 | mutex_unlock(&dev_priv->sb_lock); |
3952 | ||
e615efe4 ED |
3953 | /* Wait for initialization time */ |
3954 | udelay(24); | |
3955 | ||
3956 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3957 | } | |
3958 | ||
8802e5b6 VS |
3959 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3960 | { | |
3961 | u32 divsel, phaseinc, auxdiv; | |
3962 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3963 | u32 iclk_pi_range = 64; | |
3964 | u32 desired_divisor; | |
3965 | u32 temp; | |
3966 | ||
3967 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3968 | return 0; | |
3969 | ||
3970 | mutex_lock(&dev_priv->sb_lock); | |
3971 | ||
3972 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3973 | if (temp & SBI_SSCCTL_DISABLE) { | |
3974 | mutex_unlock(&dev_priv->sb_lock); | |
3975 | return 0; | |
3976 | } | |
3977 | ||
3978 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3979 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3980 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3981 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3982 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3983 | ||
3984 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3985 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3986 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3987 | ||
3988 | mutex_unlock(&dev_priv->sb_lock); | |
3989 | ||
3990 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3991 | ||
3992 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3993 | desired_divisor << auxdiv); | |
3994 | } | |
3995 | ||
275f01b2 DV |
3996 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3997 | enum pipe pch_transcoder) | |
3998 | { | |
3999 | struct drm_device *dev = crtc->base.dev; | |
4000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4001 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4002 | |
4003 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4004 | I915_READ(HTOTAL(cpu_transcoder))); | |
4005 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4006 | I915_READ(HBLANK(cpu_transcoder))); | |
4007 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4008 | I915_READ(HSYNC(cpu_transcoder))); | |
4009 | ||
4010 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4011 | I915_READ(VTOTAL(cpu_transcoder))); | |
4012 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4013 | I915_READ(VBLANK(cpu_transcoder))); | |
4014 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4015 | I915_READ(VSYNC(cpu_transcoder))); | |
4016 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4017 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4018 | } | |
4019 | ||
003632d9 | 4020 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4021 | { |
4022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4023 | uint32_t temp; | |
4024 | ||
4025 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4026 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4027 | return; |
4028 | ||
4029 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4030 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4031 | ||
003632d9 ACO |
4032 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4033 | if (enable) | |
4034 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4035 | ||
4036 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4037 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4038 | POSTING_READ(SOUTH_CHICKEN1); | |
4039 | } | |
4040 | ||
4041 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4042 | { | |
4043 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4044 | |
4045 | switch (intel_crtc->pipe) { | |
4046 | case PIPE_A: | |
4047 | break; | |
4048 | case PIPE_B: | |
6e3c9717 | 4049 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4050 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4051 | else |
003632d9 | 4052 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4053 | |
4054 | break; | |
4055 | case PIPE_C: | |
003632d9 | 4056 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4057 | |
4058 | break; | |
4059 | default: | |
4060 | BUG(); | |
4061 | } | |
4062 | } | |
4063 | ||
c48b5305 VS |
4064 | /* Return which DP Port should be selected for Transcoder DP control */ |
4065 | static enum port | |
4066 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4067 | { | |
4068 | struct drm_device *dev = crtc->dev; | |
4069 | struct intel_encoder *encoder; | |
4070 | ||
4071 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4072 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4073 | encoder->type == INTEL_OUTPUT_EDP) | |
4074 | return enc_to_dig_port(&encoder->base)->port; | |
4075 | } | |
4076 | ||
4077 | return -1; | |
4078 | } | |
4079 | ||
f67a559d JB |
4080 | /* |
4081 | * Enable PCH resources required for PCH ports: | |
4082 | * - PCH PLLs | |
4083 | * - FDI training & RX/TX | |
4084 | * - update transcoder timings | |
4085 | * - DP transcoding bits | |
4086 | * - transcoder | |
4087 | */ | |
4088 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4089 | { |
4090 | struct drm_device *dev = crtc->dev; | |
4091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4093 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4094 | u32 temp; |
2c07245f | 4095 | |
ab9412ba | 4096 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4097 | |
1fbc0d78 DV |
4098 | if (IS_IVYBRIDGE(dev)) |
4099 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4100 | ||
cd986abb DV |
4101 | /* Write the TU size bits before fdi link training, so that error |
4102 | * detection works. */ | |
4103 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4104 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4105 | ||
3860b2ec VS |
4106 | /* |
4107 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4108 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4109 | */ | |
4110 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4111 | ||
c98e9dcf | 4112 | /* For PCH output, training FDI link */ |
674cf967 | 4113 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4114 | |
3ad8a208 DV |
4115 | /* We need to program the right clock selection before writing the pixel |
4116 | * mutliplier into the DPLL. */ | |
303b81e0 | 4117 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4118 | u32 sel; |
4b645f14 | 4119 | |
c98e9dcf | 4120 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4121 | temp |= TRANS_DPLL_ENABLE(pipe); |
4122 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4123 | if (intel_crtc->config->shared_dpll == |
4124 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4125 | temp |= sel; |
4126 | else | |
4127 | temp &= ~sel; | |
c98e9dcf | 4128 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4129 | } |
5eddb70b | 4130 | |
3ad8a208 DV |
4131 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4132 | * transcoder, and we actually should do this to not upset any PCH | |
4133 | * transcoder that already use the clock when we share it. | |
4134 | * | |
4135 | * Note that enable_shared_dpll tries to do the right thing, but | |
4136 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4137 | * the right LVDS enable sequence. */ | |
85b3894f | 4138 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4139 | |
d9b6cb56 JB |
4140 | /* set transcoder timing, panel must allow it */ |
4141 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4142 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4143 | |
303b81e0 | 4144 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4145 | |
3860b2ec VS |
4146 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4147 | ||
c98e9dcf | 4148 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4149 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4150 | const struct drm_display_mode *adjusted_mode = |
4151 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4152 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4153 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4154 | temp = I915_READ(reg); |
4155 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4156 | TRANS_DP_SYNC_MASK | |
4157 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4158 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4159 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4160 | |
9c4edaee | 4161 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4162 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4163 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4164 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4165 | |
4166 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4167 | case PORT_B: |
5eddb70b | 4168 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4169 | break; |
c48b5305 | 4170 | case PORT_C: |
5eddb70b | 4171 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4172 | break; |
c48b5305 | 4173 | case PORT_D: |
5eddb70b | 4174 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4175 | break; |
4176 | default: | |
e95d41e1 | 4177 | BUG(); |
32f9d658 | 4178 | } |
2c07245f | 4179 | |
5eddb70b | 4180 | I915_WRITE(reg, temp); |
6be4a607 | 4181 | } |
b52eb4dc | 4182 | |
b8a4f404 | 4183 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4184 | } |
4185 | ||
1507e5bd PZ |
4186 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4187 | { | |
4188 | struct drm_device *dev = crtc->dev; | |
4189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4191 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4192 | |
ab9412ba | 4193 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4194 | |
8c52b5e8 | 4195 | lpt_program_iclkip(crtc); |
1507e5bd | 4196 | |
0540e488 | 4197 | /* Set transcoder timing. */ |
275f01b2 | 4198 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4199 | |
937bb610 | 4200 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4201 | } |
4202 | ||
a1520318 | 4203 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4204 | { |
4205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4206 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4207 | u32 temp; |
4208 | ||
4209 | temp = I915_READ(dslreg); | |
4210 | udelay(500); | |
4211 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4212 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4213 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4214 | } |
4215 | } | |
4216 | ||
86adf9d7 ML |
4217 | static int |
4218 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4219 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4220 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4221 | { |
86adf9d7 ML |
4222 | struct intel_crtc_scaler_state *scaler_state = |
4223 | &crtc_state->scaler_state; | |
4224 | struct intel_crtc *intel_crtc = | |
4225 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4226 | int need_scaling; |
6156a456 CK |
4227 | |
4228 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4229 | (src_h != dst_w || src_w != dst_h): | |
4230 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4231 | |
4232 | /* | |
4233 | * if plane is being disabled or scaler is no more required or force detach | |
4234 | * - free scaler binded to this plane/crtc | |
4235 | * - in order to do this, update crtc->scaler_usage | |
4236 | * | |
4237 | * Here scaler state in crtc_state is set free so that | |
4238 | * scaler can be assigned to other user. Actual register | |
4239 | * update to free the scaler is done in plane/panel-fit programming. | |
4240 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4241 | */ | |
86adf9d7 | 4242 | if (force_detach || !need_scaling) { |
a1b2278e | 4243 | if (*scaler_id >= 0) { |
86adf9d7 | 4244 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4245 | scaler_state->scalers[*scaler_id].in_use = 0; |
4246 | ||
86adf9d7 ML |
4247 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4248 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4249 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4250 | scaler_state->scaler_users); |
4251 | *scaler_id = -1; | |
4252 | } | |
4253 | return 0; | |
4254 | } | |
4255 | ||
4256 | /* range checks */ | |
4257 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4258 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4259 | ||
4260 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4261 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4262 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4263 | "size is out of scaler range\n", |
86adf9d7 | 4264 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4265 | return -EINVAL; |
4266 | } | |
4267 | ||
86adf9d7 ML |
4268 | /* mark this plane as a scaler user in crtc_state */ |
4269 | scaler_state->scaler_users |= (1 << scaler_user); | |
4270 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4271 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4272 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4273 | scaler_state->scaler_users); | |
4274 | ||
4275 | return 0; | |
4276 | } | |
4277 | ||
4278 | /** | |
4279 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4280 | * | |
4281 | * @state: crtc's scaler state | |
86adf9d7 ML |
4282 | * |
4283 | * Return | |
4284 | * 0 - scaler_usage updated successfully | |
4285 | * error - requested scaling cannot be supported or other error condition | |
4286 | */ | |
e435d6e5 | 4287 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4288 | { |
4289 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4290 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4291 | |
4292 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4293 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4294 | ||
e435d6e5 | 4295 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4296 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4297 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4298 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4299 | } |
4300 | ||
4301 | /** | |
4302 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4303 | * | |
4304 | * @state: crtc's scaler state | |
86adf9d7 ML |
4305 | * @plane_state: atomic plane state to update |
4306 | * | |
4307 | * Return | |
4308 | * 0 - scaler_usage updated successfully | |
4309 | * error - requested scaling cannot be supported or other error condition | |
4310 | */ | |
da20eabd ML |
4311 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4312 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4313 | { |
4314 | ||
4315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4316 | struct intel_plane *intel_plane = |
4317 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4318 | struct drm_framebuffer *fb = plane_state->base.fb; |
4319 | int ret; | |
4320 | ||
4321 | bool force_detach = !fb || !plane_state->visible; | |
4322 | ||
4323 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4324 | intel_plane->base.base.id, intel_crtc->pipe, | |
4325 | drm_plane_index(&intel_plane->base)); | |
4326 | ||
4327 | ret = skl_update_scaler(crtc_state, force_detach, | |
4328 | drm_plane_index(&intel_plane->base), | |
4329 | &plane_state->scaler_id, | |
4330 | plane_state->base.rotation, | |
4331 | drm_rect_width(&plane_state->src) >> 16, | |
4332 | drm_rect_height(&plane_state->src) >> 16, | |
4333 | drm_rect_width(&plane_state->dst), | |
4334 | drm_rect_height(&plane_state->dst)); | |
4335 | ||
4336 | if (ret || plane_state->scaler_id < 0) | |
4337 | return ret; | |
4338 | ||
a1b2278e | 4339 | /* check colorkey */ |
818ed961 | 4340 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4341 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4342 | intel_plane->base.base.id); |
a1b2278e CK |
4343 | return -EINVAL; |
4344 | } | |
4345 | ||
4346 | /* Check src format */ | |
86adf9d7 ML |
4347 | switch (fb->pixel_format) { |
4348 | case DRM_FORMAT_RGB565: | |
4349 | case DRM_FORMAT_XBGR8888: | |
4350 | case DRM_FORMAT_XRGB8888: | |
4351 | case DRM_FORMAT_ABGR8888: | |
4352 | case DRM_FORMAT_ARGB8888: | |
4353 | case DRM_FORMAT_XRGB2101010: | |
4354 | case DRM_FORMAT_XBGR2101010: | |
4355 | case DRM_FORMAT_YUYV: | |
4356 | case DRM_FORMAT_YVYU: | |
4357 | case DRM_FORMAT_UYVY: | |
4358 | case DRM_FORMAT_VYUY: | |
4359 | break; | |
4360 | default: | |
4361 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4362 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4363 | return -EINVAL; | |
a1b2278e CK |
4364 | } |
4365 | ||
a1b2278e CK |
4366 | return 0; |
4367 | } | |
4368 | ||
e435d6e5 ML |
4369 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4370 | { | |
4371 | int i; | |
4372 | ||
4373 | for (i = 0; i < crtc->num_scalers; i++) | |
4374 | skl_detach_scaler(crtc, i); | |
4375 | } | |
4376 | ||
4377 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4378 | { |
4379 | struct drm_device *dev = crtc->base.dev; | |
4380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4381 | int pipe = crtc->pipe; | |
a1b2278e CK |
4382 | struct intel_crtc_scaler_state *scaler_state = |
4383 | &crtc->config->scaler_state; | |
4384 | ||
4385 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4386 | ||
6e3c9717 | 4387 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4388 | int id; |
4389 | ||
4390 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4391 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4392 | return; | |
4393 | } | |
4394 | ||
4395 | id = scaler_state->scaler_id; | |
4396 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4397 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4398 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4399 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4400 | ||
4401 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4402 | } |
4403 | } | |
4404 | ||
b074cec8 JB |
4405 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4406 | { | |
4407 | struct drm_device *dev = crtc->base.dev; | |
4408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4409 | int pipe = crtc->pipe; | |
4410 | ||
6e3c9717 | 4411 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4412 | /* Force use of hard-coded filter coefficients |
4413 | * as some pre-programmed values are broken, | |
4414 | * e.g. x201. | |
4415 | */ | |
4416 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4417 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4418 | PF_PIPE_SEL_IVB(pipe)); | |
4419 | else | |
4420 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4421 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4422 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4423 | } |
4424 | } | |
4425 | ||
20bc8673 | 4426 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4427 | { |
cea165c3 VS |
4428 | struct drm_device *dev = crtc->base.dev; |
4429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4430 | |
6e3c9717 | 4431 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4432 | return; |
4433 | ||
cea165c3 VS |
4434 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4435 | intel_wait_for_vblank(dev, crtc->pipe); | |
4436 | ||
d77e4531 | 4437 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4438 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4439 | mutex_lock(&dev_priv->rps.hw_lock); |
4440 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4441 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4442 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4443 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4444 | * mailbox." Moreover, the mailbox may return a bogus state, |
4445 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4446 | */ |
4447 | } else { | |
4448 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4449 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4450 | * is essentially intel_wait_for_vblank. If we don't have this | |
4451 | * and don't wait for vblanks until the end of crtc_enable, then | |
4452 | * the HW state readout code will complain that the expected | |
4453 | * IPS_CTL value is not the one we read. */ | |
4454 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4455 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4456 | } | |
d77e4531 PZ |
4457 | } |
4458 | ||
20bc8673 | 4459 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4460 | { |
4461 | struct drm_device *dev = crtc->base.dev; | |
4462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4463 | ||
6e3c9717 | 4464 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4465 | return; |
4466 | ||
4467 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4468 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4469 | mutex_lock(&dev_priv->rps.hw_lock); |
4470 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4471 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4472 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4473 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4474 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4475 | } else { |
2a114cc1 | 4476 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4477 | POSTING_READ(IPS_CTL); |
4478 | } | |
d77e4531 PZ |
4479 | |
4480 | /* We need to wait for a vblank before we can disable the plane. */ | |
4481 | intel_wait_for_vblank(dev, crtc->pipe); | |
4482 | } | |
4483 | ||
7cac945f | 4484 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4485 | { |
7cac945f | 4486 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4487 | struct drm_device *dev = intel_crtc->base.dev; |
4488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4489 | ||
4490 | mutex_lock(&dev->struct_mutex); | |
4491 | dev_priv->mm.interruptible = false; | |
4492 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4493 | dev_priv->mm.interruptible = true; | |
4494 | mutex_unlock(&dev->struct_mutex); | |
4495 | } | |
4496 | ||
4497 | /* Let userspace switch the overlay on again. In most cases userspace | |
4498 | * has to recompute where to put it anyway. | |
4499 | */ | |
4500 | } | |
4501 | ||
87d4300a ML |
4502 | /** |
4503 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4504 | * @crtc: the CRTC whose primary plane was just enabled | |
4505 | * | |
4506 | * Performs potentially sleeping operations that must be done after the primary | |
4507 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4508 | * called due to an explicit primary plane update, or due to an implicit | |
4509 | * re-enable that is caused when a sprite plane is updated to no longer | |
4510 | * completely hide the primary plane. | |
4511 | */ | |
4512 | static void | |
4513 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4514 | { |
4515 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4516 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4517 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4518 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4519 | |
87d4300a ML |
4520 | /* |
4521 | * FIXME IPS should be fine as long as one plane is | |
4522 | * enabled, but in practice it seems to have problems | |
4523 | * when going from primary only to sprite only and vice | |
4524 | * versa. | |
4525 | */ | |
a5c4d7bc VS |
4526 | hsw_enable_ips(intel_crtc); |
4527 | ||
f99d7069 | 4528 | /* |
87d4300a ML |
4529 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4530 | * So don't enable underrun reporting before at least some planes | |
4531 | * are enabled. | |
4532 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4533 | * but leave the pipe running. | |
f99d7069 | 4534 | */ |
87d4300a ML |
4535 | if (IS_GEN2(dev)) |
4536 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4537 | ||
aca7b684 VS |
4538 | /* Underruns don't always raise interrupts, so check manually. */ |
4539 | intel_check_cpu_fifo_underruns(dev_priv); | |
4540 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4541 | } |
4542 | ||
2622a081 | 4543 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4544 | static void |
4545 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4546 | { |
4547 | struct drm_device *dev = crtc->dev; | |
4548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4549 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4550 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4551 | |
87d4300a ML |
4552 | /* |
4553 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4554 | * So diasble underrun reporting before all the planes get disabled. | |
4555 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4556 | * but leave the pipe running. | |
4557 | */ | |
4558 | if (IS_GEN2(dev)) | |
4559 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4560 | |
2622a081 VS |
4561 | /* |
4562 | * FIXME IPS should be fine as long as one plane is | |
4563 | * enabled, but in practice it seems to have problems | |
4564 | * when going from primary only to sprite only and vice | |
4565 | * versa. | |
4566 | */ | |
4567 | hsw_disable_ips(intel_crtc); | |
4568 | } | |
4569 | ||
4570 | /* FIXME get rid of this and use pre_plane_update */ | |
4571 | static void | |
4572 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4573 | { | |
4574 | struct drm_device *dev = crtc->dev; | |
4575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4577 | int pipe = intel_crtc->pipe; | |
4578 | ||
4579 | intel_pre_disable_primary(crtc); | |
4580 | ||
87d4300a ML |
4581 | /* |
4582 | * Vblank time updates from the shadow to live plane control register | |
4583 | * are blocked if the memory self-refresh mode is active at that | |
4584 | * moment. So to make sure the plane gets truly disabled, disable | |
4585 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4586 | * will be checked/applied by the HW only at the next frame start | |
4587 | * event which is after the vblank start event, so we need to have a | |
4588 | * wait-for-vblank between disabling the plane and the pipe. | |
4589 | */ | |
262cd2e1 | 4590 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4591 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4592 | dev_priv->wm.vlv.cxsr = false; |
4593 | intel_wait_for_vblank(dev, pipe); | |
4594 | } | |
87d4300a ML |
4595 | } |
4596 | ||
cd202f69 | 4597 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4598 | { |
cd202f69 ML |
4599 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
4600 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
92826fcd ML |
4601 | struct intel_crtc_state *pipe_config = |
4602 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4603 | struct drm_device *dev = crtc->base.dev; |
cd202f69 ML |
4604 | struct drm_plane *primary = crtc->base.primary; |
4605 | struct drm_plane_state *old_pri_state = | |
4606 | drm_atomic_get_existing_plane_state(old_state, primary); | |
ac21b225 | 4607 | |
cd202f69 | 4608 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); |
ac21b225 | 4609 | |
ab1d3a0e | 4610 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4611 | |
caed361d | 4612 | if (pipe_config->update_wm_post && pipe_config->base.active) |
f015c551 VS |
4613 | intel_update_watermarks(&crtc->base); |
4614 | ||
cd202f69 ML |
4615 | if (old_pri_state) { |
4616 | struct intel_plane_state *primary_state = | |
4617 | to_intel_plane_state(primary->state); | |
4618 | struct intel_plane_state *old_primary_state = | |
4619 | to_intel_plane_state(old_pri_state); | |
4620 | ||
31ae71fc ML |
4621 | intel_fbc_post_update(crtc); |
4622 | ||
cd202f69 ML |
4623 | if (primary_state->visible && |
4624 | (needs_modeset(&pipe_config->base) || | |
4625 | !old_primary_state->visible)) | |
4626 | intel_post_enable_primary(&crtc->base); | |
4627 | } | |
ac21b225 ML |
4628 | } |
4629 | ||
5c74cd73 | 4630 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4631 | { |
5c74cd73 | 4632 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4633 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4634 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4635 | struct intel_crtc_state *pipe_config = |
4636 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4637 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4638 | struct drm_plane *primary = crtc->base.primary; | |
4639 | struct drm_plane_state *old_pri_state = | |
4640 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4641 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4642 | |
5c74cd73 ML |
4643 | if (old_pri_state) { |
4644 | struct intel_plane_state *primary_state = | |
4645 | to_intel_plane_state(primary->state); | |
4646 | struct intel_plane_state *old_primary_state = | |
4647 | to_intel_plane_state(old_pri_state); | |
4648 | ||
31ae71fc ML |
4649 | intel_fbc_pre_update(crtc); |
4650 | ||
5c74cd73 ML |
4651 | if (old_primary_state->visible && |
4652 | (modeset || !primary_state->visible)) | |
4653 | intel_pre_disable_primary(&crtc->base); | |
4654 | } | |
852eb00d | 4655 | |
ab1d3a0e | 4656 | if (pipe_config->disable_cxsr) { |
852eb00d | 4657 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4658 | |
2622a081 VS |
4659 | /* |
4660 | * Vblank time updates from the shadow to live plane control register | |
4661 | * are blocked if the memory self-refresh mode is active at that | |
4662 | * moment. So to make sure the plane gets truly disabled, disable | |
4663 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4664 | * will be checked/applied by the HW only at the next frame start | |
4665 | * event which is after the vblank start event, so we need to have a | |
4666 | * wait-for-vblank between disabling the plane and the pipe. | |
4667 | */ | |
4668 | if (old_crtc_state->base.active) { | |
2dfd178d | 4669 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4670 | dev_priv->wm.vlv.cxsr = false; |
4671 | intel_wait_for_vblank(dev, crtc->pipe); | |
4672 | } | |
852eb00d | 4673 | } |
92826fcd | 4674 | |
ed4a6a7c MR |
4675 | /* |
4676 | * IVB workaround: must disable low power watermarks for at least | |
4677 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4678 | * when scaling is disabled. | |
4679 | * | |
4680 | * WaCxSRDisabledForSpriteScaling:ivb | |
4681 | */ | |
4682 | if (pipe_config->disable_lp_wm) { | |
4683 | ilk_disable_lp_wm(dev); | |
4684 | intel_wait_for_vblank(dev, crtc->pipe); | |
4685 | } | |
4686 | ||
4687 | /* | |
4688 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4689 | * watermark programming here. | |
4690 | */ | |
4691 | if (needs_modeset(&pipe_config->base)) | |
4692 | return; | |
4693 | ||
4694 | /* | |
4695 | * For platforms that support atomic watermarks, program the | |
4696 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4697 | * will be the intermediate values that are safe for both pre- and | |
4698 | * post- vblank; when vblank happens, the 'active' values will be set | |
4699 | * to the final 'target' values and we'll do this again to get the | |
4700 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4701 | * will be the final target values which will get automatically latched | |
4702 | * at vblank time; no further programming will be necessary. | |
4703 | * | |
4704 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4705 | * we'll continue to update watermarks the old way, if flags tell | |
4706 | * us to. | |
4707 | */ | |
4708 | if (dev_priv->display.initial_watermarks != NULL) | |
4709 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4710 | else if (pipe_config->update_wm_pre) |
92826fcd | 4711 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4712 | } |
4713 | ||
d032ffa0 | 4714 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4715 | { |
4716 | struct drm_device *dev = crtc->dev; | |
4717 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4718 | struct drm_plane *p; |
87d4300a ML |
4719 | int pipe = intel_crtc->pipe; |
4720 | ||
7cac945f | 4721 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4722 | |
d032ffa0 ML |
4723 | drm_for_each_plane_mask(p, dev, plane_mask) |
4724 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4725 | |
f99d7069 DV |
4726 | /* |
4727 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4728 | * to compute the mask of flip planes precisely. For the time being | |
4729 | * consider this a flip to a NULL plane. | |
4730 | */ | |
4731 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4732 | } |
4733 | ||
f67a559d JB |
4734 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4735 | { | |
4736 | struct drm_device *dev = crtc->dev; | |
4737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4739 | struct intel_encoder *encoder; |
f67a559d | 4740 | int pipe = intel_crtc->pipe; |
f67a559d | 4741 | |
53d9f4e9 | 4742 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4743 | return; |
4744 | ||
81b088ca VS |
4745 | if (intel_crtc->config->has_pch_encoder) |
4746 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4747 | ||
6e3c9717 | 4748 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4749 | intel_prepare_shared_dpll(intel_crtc); |
4750 | ||
6e3c9717 | 4751 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4752 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4753 | |
4754 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4755 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4756 | |
6e3c9717 | 4757 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4758 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4759 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4760 | } |
4761 | ||
4762 | ironlake_set_pipeconf(crtc); | |
4763 | ||
f67a559d | 4764 | intel_crtc->active = true; |
8664281b | 4765 | |
a72e4c9f | 4766 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4767 | |
f6736a1a | 4768 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4769 | if (encoder->pre_enable) |
4770 | encoder->pre_enable(encoder); | |
f67a559d | 4771 | |
6e3c9717 | 4772 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4773 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4774 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4775 | * enabling. */ | |
88cefb6c | 4776 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4777 | } else { |
4778 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4779 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4780 | } | |
f67a559d | 4781 | |
b074cec8 | 4782 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4783 | |
9c54c0dd JB |
4784 | /* |
4785 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4786 | * clocks enabled | |
4787 | */ | |
8563b1e8 | 4788 | intel_color_load_luts(crtc); |
9c54c0dd | 4789 | |
1d5bf5d9 ID |
4790 | if (dev_priv->display.initial_watermarks != NULL) |
4791 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4792 | intel_enable_pipe(intel_crtc); |
f67a559d | 4793 | |
6e3c9717 | 4794 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4795 | ironlake_pch_enable(crtc); |
c98e9dcf | 4796 | |
f9b61ff6 DV |
4797 | assert_vblank_disabled(crtc); |
4798 | drm_crtc_vblank_on(crtc); | |
4799 | ||
fa5c73b1 DV |
4800 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4801 | encoder->enable(encoder); | |
61b77ddd DV |
4802 | |
4803 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4804 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4805 | |
4806 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4807 | if (intel_crtc->config->has_pch_encoder) | |
4808 | intel_wait_for_vblank(dev, pipe); | |
4809 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4810 | } |
4811 | ||
42db64ef PZ |
4812 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4813 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4814 | { | |
f5adf94e | 4815 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4816 | } |
4817 | ||
4f771f10 PZ |
4818 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4819 | { | |
4820 | struct drm_device *dev = crtc->dev; | |
4821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4823 | struct intel_encoder *encoder; | |
99d736a2 | 4824 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4825 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4826 | struct intel_crtc_state *pipe_config = |
4827 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4828 | |
53d9f4e9 | 4829 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4830 | return; |
4831 | ||
81b088ca VS |
4832 | if (intel_crtc->config->has_pch_encoder) |
4833 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4834 | false); | |
4835 | ||
8106ddbd | 4836 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4837 | intel_enable_shared_dpll(intel_crtc); |
4838 | ||
6e3c9717 | 4839 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4840 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4841 | |
4d1de975 JN |
4842 | if (!intel_crtc->config->has_dsi_encoder) |
4843 | intel_set_pipe_timings(intel_crtc); | |
4844 | ||
bc58be60 | 4845 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4846 | |
4d1de975 JN |
4847 | if (cpu_transcoder != TRANSCODER_EDP && |
4848 | !transcoder_is_dsi(cpu_transcoder)) { | |
4849 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4850 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4851 | } |
4852 | ||
6e3c9717 | 4853 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4854 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4855 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4856 | } |
4857 | ||
4d1de975 JN |
4858 | if (!intel_crtc->config->has_dsi_encoder) |
4859 | haswell_set_pipeconf(crtc); | |
4860 | ||
391bf048 | 4861 | haswell_set_pipemisc(crtc); |
229fca97 | 4862 | |
8563b1e8 | 4863 | intel_color_set_csc(crtc); |
229fca97 | 4864 | |
4f771f10 | 4865 | intel_crtc->active = true; |
8664281b | 4866 | |
6b698516 DV |
4867 | if (intel_crtc->config->has_pch_encoder) |
4868 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4869 | else | |
4870 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4871 | ||
7d4aefd0 | 4872 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4873 | if (encoder->pre_enable) |
4874 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4875 | } |
4f771f10 | 4876 | |
d2d65408 | 4877 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4878 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4879 | |
a65347ba | 4880 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4881 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4882 | |
1c132b44 | 4883 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4884 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4885 | else |
1c132b44 | 4886 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4887 | |
4888 | /* | |
4889 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4890 | * clocks enabled | |
4891 | */ | |
8563b1e8 | 4892 | intel_color_load_luts(crtc); |
4f771f10 | 4893 | |
1f544388 | 4894 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4895 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4896 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4897 | |
1d5bf5d9 ID |
4898 | if (dev_priv->display.initial_watermarks != NULL) |
4899 | dev_priv->display.initial_watermarks(pipe_config); | |
4900 | else | |
4901 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4902 | |
4903 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4904 | if (!intel_crtc->config->has_dsi_encoder) | |
4905 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4906 | |
6e3c9717 | 4907 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4908 | lpt_pch_enable(crtc); |
4f771f10 | 4909 | |
a65347ba | 4910 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4911 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4912 | ||
f9b61ff6 DV |
4913 | assert_vblank_disabled(crtc); |
4914 | drm_crtc_vblank_on(crtc); | |
4915 | ||
8807e55b | 4916 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4917 | encoder->enable(encoder); |
8807e55b JN |
4918 | intel_opregion_notify_encoder(encoder, true); |
4919 | } | |
4f771f10 | 4920 | |
6b698516 DV |
4921 | if (intel_crtc->config->has_pch_encoder) { |
4922 | intel_wait_for_vblank(dev, pipe); | |
4923 | intel_wait_for_vblank(dev, pipe); | |
4924 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4925 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4926 | true); | |
6b698516 | 4927 | } |
d2d65408 | 4928 | |
e4916946 PZ |
4929 | /* If we change the relative order between pipe/planes enabling, we need |
4930 | * to change the workaround. */ | |
99d736a2 ML |
4931 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4932 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4933 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4934 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4935 | } | |
4f771f10 PZ |
4936 | } |
4937 | ||
bfd16b2a | 4938 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4939 | { |
4940 | struct drm_device *dev = crtc->base.dev; | |
4941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4942 | int pipe = crtc->pipe; | |
4943 | ||
4944 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4945 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4946 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4947 | I915_WRITE(PF_CTL(pipe), 0); |
4948 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4949 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4950 | } | |
4951 | } | |
4952 | ||
6be4a607 JB |
4953 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4954 | { | |
4955 | struct drm_device *dev = crtc->dev; | |
4956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4957 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4958 | struct intel_encoder *encoder; |
6be4a607 | 4959 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4960 | |
37ca8d4c VS |
4961 | if (intel_crtc->config->has_pch_encoder) |
4962 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4963 | ||
ea9d758d DV |
4964 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4965 | encoder->disable(encoder); | |
4966 | ||
f9b61ff6 DV |
4967 | drm_crtc_vblank_off(crtc); |
4968 | assert_vblank_disabled(crtc); | |
4969 | ||
3860b2ec VS |
4970 | /* |
4971 | * Sometimes spurious CPU pipe underruns happen when the | |
4972 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4973 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4974 | */ | |
4975 | if (intel_crtc->config->has_pch_encoder) | |
4976 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4977 | ||
575f7ab7 | 4978 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4979 | |
bfd16b2a | 4980 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4981 | |
3860b2ec | 4982 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 4983 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
4984 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4985 | } | |
5a74f70a | 4986 | |
bf49ec8c DV |
4987 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4988 | if (encoder->post_disable) | |
4989 | encoder->post_disable(encoder); | |
2c07245f | 4990 | |
6e3c9717 | 4991 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4992 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4993 | |
d925c59a | 4994 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
4995 | i915_reg_t reg; |
4996 | u32 temp; | |
4997 | ||
d925c59a DV |
4998 | /* disable TRANS_DP_CTL */ |
4999 | reg = TRANS_DP_CTL(pipe); | |
5000 | temp = I915_READ(reg); | |
5001 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5002 | TRANS_DP_PORT_SEL_MASK); | |
5003 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5004 | I915_WRITE(reg, temp); | |
5005 | ||
5006 | /* disable DPLL_SEL */ | |
5007 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5008 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5009 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5010 | } |
e3421a18 | 5011 | |
d925c59a DV |
5012 | ironlake_fdi_pll_disable(intel_crtc); |
5013 | } | |
81b088ca VS |
5014 | |
5015 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5016 | } |
1b3c7a47 | 5017 | |
4f771f10 | 5018 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5019 | { |
4f771f10 PZ |
5020 | struct drm_device *dev = crtc->dev; |
5021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5023 | struct intel_encoder *encoder; |
6e3c9717 | 5024 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5025 | |
d2d65408 VS |
5026 | if (intel_crtc->config->has_pch_encoder) |
5027 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5028 | false); | |
5029 | ||
8807e55b JN |
5030 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5031 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5032 | encoder->disable(encoder); |
8807e55b | 5033 | } |
4f771f10 | 5034 | |
f9b61ff6 DV |
5035 | drm_crtc_vblank_off(crtc); |
5036 | assert_vblank_disabled(crtc); | |
5037 | ||
4d1de975 JN |
5038 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5039 | if (!intel_crtc->config->has_dsi_encoder) | |
5040 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5041 | |
6e3c9717 | 5042 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5043 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5044 | ||
a65347ba | 5045 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5046 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5047 | |
1c132b44 | 5048 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5049 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5050 | else |
bfd16b2a | 5051 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5052 | |
a65347ba | 5053 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5054 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5055 | |
97b040aa ID |
5056 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5057 | if (encoder->post_disable) | |
5058 | encoder->post_disable(encoder); | |
81b088ca | 5059 | |
92966a37 VS |
5060 | if (intel_crtc->config->has_pch_encoder) { |
5061 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5062 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5063 | intel_ddi_fdi_disable(crtc); |
5064 | ||
81b088ca VS |
5065 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5066 | true); | |
92966a37 | 5067 | } |
4f771f10 PZ |
5068 | } |
5069 | ||
2dd24552 JB |
5070 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5071 | { | |
5072 | struct drm_device *dev = crtc->base.dev; | |
5073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5074 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5075 | |
681a8504 | 5076 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5077 | return; |
5078 | ||
2dd24552 | 5079 | /* |
c0b03411 DV |
5080 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5081 | * according to register description and PRM. | |
2dd24552 | 5082 | */ |
c0b03411 DV |
5083 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5084 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5085 | |
b074cec8 JB |
5086 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5087 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5088 | |
5089 | /* Border color in case we don't scale up to the full screen. Black by | |
5090 | * default, change to something else for debugging. */ | |
5091 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5092 | } |
5093 | ||
d05410f9 DA |
5094 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5095 | { | |
5096 | switch (port) { | |
5097 | case PORT_A: | |
6331a704 | 5098 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5099 | case PORT_B: |
6331a704 | 5100 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5101 | case PORT_C: |
6331a704 | 5102 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5103 | case PORT_D: |
6331a704 | 5104 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5105 | case PORT_E: |
6331a704 | 5106 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5107 | default: |
b9fec167 | 5108 | MISSING_CASE(port); |
d05410f9 DA |
5109 | return POWER_DOMAIN_PORT_OTHER; |
5110 | } | |
5111 | } | |
5112 | ||
25f78f58 VS |
5113 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5114 | { | |
5115 | switch (port) { | |
5116 | case PORT_A: | |
5117 | return POWER_DOMAIN_AUX_A; | |
5118 | case PORT_B: | |
5119 | return POWER_DOMAIN_AUX_B; | |
5120 | case PORT_C: | |
5121 | return POWER_DOMAIN_AUX_C; | |
5122 | case PORT_D: | |
5123 | return POWER_DOMAIN_AUX_D; | |
5124 | case PORT_E: | |
5125 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5126 | return POWER_DOMAIN_AUX_D; | |
5127 | default: | |
b9fec167 | 5128 | MISSING_CASE(port); |
25f78f58 VS |
5129 | return POWER_DOMAIN_AUX_A; |
5130 | } | |
5131 | } | |
5132 | ||
319be8ae ID |
5133 | enum intel_display_power_domain |
5134 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5135 | { | |
5136 | struct drm_device *dev = intel_encoder->base.dev; | |
5137 | struct intel_digital_port *intel_dig_port; | |
5138 | ||
5139 | switch (intel_encoder->type) { | |
5140 | case INTEL_OUTPUT_UNKNOWN: | |
5141 | /* Only DDI platforms should ever use this output type */ | |
5142 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5143 | case INTEL_OUTPUT_DISPLAYPORT: | |
5144 | case INTEL_OUTPUT_HDMI: | |
5145 | case INTEL_OUTPUT_EDP: | |
5146 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5147 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5148 | case INTEL_OUTPUT_DP_MST: |
5149 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5150 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5151 | case INTEL_OUTPUT_ANALOG: |
5152 | return POWER_DOMAIN_PORT_CRT; | |
5153 | case INTEL_OUTPUT_DSI: | |
5154 | return POWER_DOMAIN_PORT_DSI; | |
5155 | default: | |
5156 | return POWER_DOMAIN_PORT_OTHER; | |
5157 | } | |
5158 | } | |
5159 | ||
25f78f58 VS |
5160 | enum intel_display_power_domain |
5161 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5162 | { | |
5163 | struct drm_device *dev = intel_encoder->base.dev; | |
5164 | struct intel_digital_port *intel_dig_port; | |
5165 | ||
5166 | switch (intel_encoder->type) { | |
5167 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5168 | case INTEL_OUTPUT_HDMI: |
5169 | /* | |
5170 | * Only DDI platforms should ever use these output types. | |
5171 | * We can get here after the HDMI detect code has already set | |
5172 | * the type of the shared encoder. Since we can't be sure | |
5173 | * what's the status of the given connectors, play safe and | |
5174 | * run the DP detection too. | |
5175 | */ | |
25f78f58 VS |
5176 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5177 | case INTEL_OUTPUT_DISPLAYPORT: | |
5178 | case INTEL_OUTPUT_EDP: | |
5179 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5180 | return port_to_aux_power_domain(intel_dig_port->port); | |
5181 | case INTEL_OUTPUT_DP_MST: | |
5182 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5183 | return port_to_aux_power_domain(intel_dig_port->port); | |
5184 | default: | |
b9fec167 | 5185 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5186 | return POWER_DOMAIN_AUX_A; |
5187 | } | |
5188 | } | |
5189 | ||
74bff5f9 ML |
5190 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5191 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5192 | { |
319be8ae | 5193 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5194 | struct drm_encoder *encoder; |
319be8ae ID |
5195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5196 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5197 | unsigned long mask; |
74bff5f9 | 5198 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5199 | |
74bff5f9 | 5200 | if (!crtc_state->base.active) |
292b990e ML |
5201 | return 0; |
5202 | ||
77d22dca ID |
5203 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5204 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5205 | if (crtc_state->pch_pfit.enabled || |
5206 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5207 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5208 | ||
74bff5f9 ML |
5209 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5210 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5211 | ||
319be8ae | 5212 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5213 | } |
319be8ae | 5214 | |
15e7ec29 ML |
5215 | if (crtc_state->shared_dpll) |
5216 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5217 | ||
77d22dca ID |
5218 | return mask; |
5219 | } | |
5220 | ||
74bff5f9 ML |
5221 | static unsigned long |
5222 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5223 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5224 | { |
292b990e ML |
5225 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5227 | enum intel_display_power_domain domain; | |
5228 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5229 | |
292b990e | 5230 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5231 | intel_crtc->enabled_power_domains = new_domains = |
5232 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5233 | |
292b990e ML |
5234 | domains = new_domains & ~old_domains; |
5235 | ||
5236 | for_each_power_domain(domain, domains) | |
5237 | intel_display_power_get(dev_priv, domain); | |
5238 | ||
5239 | return old_domains & ~new_domains; | |
5240 | } | |
5241 | ||
5242 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5243 | unsigned long domains) | |
5244 | { | |
5245 | enum intel_display_power_domain domain; | |
5246 | ||
5247 | for_each_power_domain(domain, domains) | |
5248 | intel_display_power_put(dev_priv, domain); | |
5249 | } | |
77d22dca | 5250 | |
adafdc6f MK |
5251 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5252 | { | |
5253 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5254 | ||
5255 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5256 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5257 | return max_cdclk_freq; | |
5258 | else if (IS_CHERRYVIEW(dev_priv)) | |
5259 | return max_cdclk_freq*95/100; | |
5260 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5261 | return 2*max_cdclk_freq*90/100; | |
5262 | else | |
5263 | return max_cdclk_freq*90/100; | |
5264 | } | |
5265 | ||
560a7ae4 DL |
5266 | static void intel_update_max_cdclk(struct drm_device *dev) |
5267 | { | |
5268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5269 | ||
ef11bdb3 | 5270 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5271 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5272 | ||
5273 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5274 | dev_priv->max_cdclk_freq = 675000; | |
5275 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5276 | dev_priv->max_cdclk_freq = 540000; | |
5277 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5278 | dev_priv->max_cdclk_freq = 450000; | |
5279 | else | |
5280 | dev_priv->max_cdclk_freq = 337500; | |
5281 | } else if (IS_BROADWELL(dev)) { | |
5282 | /* | |
5283 | * FIXME with extra cooling we can allow | |
5284 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5285 | * How can we know if extra cooling is | |
5286 | * available? PCI ID, VTB, something else? | |
5287 | */ | |
5288 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5289 | dev_priv->max_cdclk_freq = 450000; | |
5290 | else if (IS_BDW_ULX(dev)) | |
5291 | dev_priv->max_cdclk_freq = 450000; | |
5292 | else if (IS_BDW_ULT(dev)) | |
5293 | dev_priv->max_cdclk_freq = 540000; | |
5294 | else | |
5295 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5296 | } else if (IS_CHERRYVIEW(dev)) { |
5297 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5298 | } else if (IS_VALLEYVIEW(dev)) { |
5299 | dev_priv->max_cdclk_freq = 400000; | |
5300 | } else { | |
5301 | /* otherwise assume cdclk is fixed */ | |
5302 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5303 | } | |
5304 | ||
adafdc6f MK |
5305 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5306 | ||
560a7ae4 DL |
5307 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5308 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5309 | |
5310 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5311 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5312 | } |
5313 | ||
5314 | static void intel_update_cdclk(struct drm_device *dev) | |
5315 | { | |
5316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5317 | ||
5318 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5319 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5320 | dev_priv->cdclk_freq); | |
5321 | ||
5322 | /* | |
5323 | * Program the gmbus_freq based on the cdclk frequency. | |
5324 | * BSpec erroneously claims we should aim for 4MHz, but | |
5325 | * in fact 1MHz is the correct frequency. | |
5326 | */ | |
666a4537 | 5327 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5328 | /* |
5329 | * Program the gmbus_freq based on the cdclk frequency. | |
5330 | * BSpec erroneously claims we should aim for 4MHz, but | |
5331 | * in fact 1MHz is the correct frequency. | |
5332 | */ | |
5333 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5334 | } | |
5335 | ||
5336 | if (dev_priv->max_cdclk_freq == 0) | |
5337 | intel_update_max_cdclk(dev); | |
5338 | } | |
5339 | ||
70d0c574 | 5340 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5341 | { |
5342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5343 | uint32_t divider; | |
5344 | uint32_t ratio; | |
5345 | uint32_t current_freq; | |
5346 | int ret; | |
5347 | ||
5348 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5349 | switch (frequency) { | |
5350 | case 144000: | |
5351 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5352 | ratio = BXT_DE_PLL_RATIO(60); | |
5353 | break; | |
5354 | case 288000: | |
5355 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5356 | ratio = BXT_DE_PLL_RATIO(60); | |
5357 | break; | |
5358 | case 384000: | |
5359 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5360 | ratio = BXT_DE_PLL_RATIO(60); | |
5361 | break; | |
5362 | case 576000: | |
5363 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5364 | ratio = BXT_DE_PLL_RATIO(60); | |
5365 | break; | |
5366 | case 624000: | |
5367 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5368 | ratio = BXT_DE_PLL_RATIO(65); | |
5369 | break; | |
5370 | case 19200: | |
5371 | /* | |
5372 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5373 | * to suppress GCC warning. | |
5374 | */ | |
5375 | ratio = 0; | |
5376 | divider = 0; | |
5377 | break; | |
5378 | default: | |
5379 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5380 | ||
5381 | return; | |
5382 | } | |
5383 | ||
5384 | mutex_lock(&dev_priv->rps.hw_lock); | |
5385 | /* Inform power controller of upcoming frequency change */ | |
5386 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5387 | 0x80000000); | |
5388 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5389 | ||
5390 | if (ret) { | |
5391 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5392 | ret, frequency); | |
5393 | return; | |
5394 | } | |
5395 | ||
5396 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5397 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5398 | current_freq = current_freq * 500 + 1000; | |
5399 | ||
5400 | /* | |
5401 | * DE PLL has to be disabled when | |
5402 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5403 | * - before setting to 624MHz (PLL needs toggling) | |
5404 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5405 | */ | |
5406 | if (frequency == 19200 || frequency == 624000 || | |
5407 | current_freq == 624000) { | |
5408 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5409 | /* Timeout 200us */ | |
5410 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5411 | 1)) | |
5412 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5413 | } | |
5414 | ||
5415 | if (frequency != 19200) { | |
5416 | uint32_t val; | |
5417 | ||
5418 | val = I915_READ(BXT_DE_PLL_CTL); | |
5419 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5420 | val |= ratio; | |
5421 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5422 | ||
5423 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5424 | /* Timeout 200us */ | |
5425 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5426 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5427 | ||
5428 | val = I915_READ(CDCLK_CTL); | |
5429 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5430 | val |= divider; | |
5431 | /* | |
5432 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5433 | * enable otherwise. | |
5434 | */ | |
5435 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5436 | if (frequency >= 500000) | |
5437 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5438 | ||
5439 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5440 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5441 | val |= (frequency - 1000) / 500; | |
5442 | I915_WRITE(CDCLK_CTL, val); | |
5443 | } | |
5444 | ||
5445 | mutex_lock(&dev_priv->rps.hw_lock); | |
5446 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5447 | DIV_ROUND_UP(frequency, 25000)); | |
5448 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5449 | ||
5450 | if (ret) { | |
5451 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5452 | ret, frequency); | |
5453 | return; | |
5454 | } | |
5455 | ||
a47871bd | 5456 | intel_update_cdclk(dev); |
f8437dd1 VK |
5457 | } |
5458 | ||
5459 | void broxton_init_cdclk(struct drm_device *dev) | |
5460 | { | |
5461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5462 | uint32_t val; | |
5463 | ||
5464 | /* | |
5465 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5466 | * or else the reset will hang because there is no PCH to respond. | |
5467 | * Move the handshake programming to initialization sequence. | |
5468 | * Previously was left up to BIOS. | |
5469 | */ | |
5470 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5471 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5472 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5473 | ||
5474 | /* Enable PG1 for cdclk */ | |
5475 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5476 | ||
5477 | /* check if cd clock is enabled */ | |
5478 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5479 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5480 | return; | |
5481 | } | |
5482 | ||
5483 | /* | |
5484 | * FIXME: | |
5485 | * - The initial CDCLK needs to be read from VBT. | |
5486 | * Need to make this change after VBT has changes for BXT. | |
5487 | * - check if setting the max (or any) cdclk freq is really necessary | |
5488 | * here, it belongs to modeset time | |
5489 | */ | |
5490 | broxton_set_cdclk(dev, 624000); | |
5491 | ||
5492 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5493 | POSTING_READ(DBUF_CTL); |
5494 | ||
f8437dd1 VK |
5495 | udelay(10); |
5496 | ||
5497 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5498 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5499 | } | |
5500 | ||
5501 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5502 | { | |
5503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5504 | ||
5505 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5506 | POSTING_READ(DBUF_CTL); |
5507 | ||
f8437dd1 VK |
5508 | udelay(10); |
5509 | ||
5510 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5511 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5512 | ||
5513 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5514 | broxton_set_cdclk(dev, 19200); | |
5515 | ||
5516 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5517 | } | |
5518 | ||
5d96d8af DL |
5519 | static const struct skl_cdclk_entry { |
5520 | unsigned int freq; | |
5521 | unsigned int vco; | |
5522 | } skl_cdclk_frequencies[] = { | |
5523 | { .freq = 308570, .vco = 8640 }, | |
5524 | { .freq = 337500, .vco = 8100 }, | |
5525 | { .freq = 432000, .vco = 8640 }, | |
5526 | { .freq = 450000, .vco = 8100 }, | |
5527 | { .freq = 540000, .vco = 8100 }, | |
5528 | { .freq = 617140, .vco = 8640 }, | |
5529 | { .freq = 675000, .vco = 8100 }, | |
5530 | }; | |
5531 | ||
5532 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5533 | { | |
5534 | return (freq - 1000) / 500; | |
5535 | } | |
5536 | ||
5537 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5538 | { | |
5539 | unsigned int i; | |
5540 | ||
5541 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5542 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5543 | ||
5544 | if (e->freq == freq) | |
5545 | return e->vco; | |
5546 | } | |
5547 | ||
5548 | return 8100; | |
5549 | } | |
5550 | ||
5551 | static void | |
5552 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5553 | { | |
5554 | unsigned int min_freq; | |
5555 | u32 val; | |
5556 | ||
5557 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5558 | val = I915_READ(CDCLK_CTL); | |
5559 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5560 | val |= CDCLK_FREQ_337_308; | |
5561 | ||
5562 | if (required_vco == 8640) | |
5563 | min_freq = 308570; | |
5564 | else | |
5565 | min_freq = 337500; | |
5566 | ||
5567 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5568 | ||
5569 | I915_WRITE(CDCLK_CTL, val); | |
5570 | POSTING_READ(CDCLK_CTL); | |
5571 | ||
5572 | /* | |
5573 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5574 | * taking into account the VCO required to operate the eDP panel at the | |
5575 | * desired frequency. The usual DP link rates operate with a VCO of | |
5576 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5577 | * The modeset code is responsible for the selection of the exact link | |
5578 | * rate later on, with the constraint of choosing a frequency that | |
5579 | * works with required_vco. | |
5580 | */ | |
5581 | val = I915_READ(DPLL_CTRL1); | |
5582 | ||
5583 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5584 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5585 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5586 | if (required_vco == 8640) | |
5587 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5588 | SKL_DPLL0); | |
5589 | else | |
5590 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5591 | SKL_DPLL0); | |
5592 | ||
5593 | I915_WRITE(DPLL_CTRL1, val); | |
5594 | POSTING_READ(DPLL_CTRL1); | |
5595 | ||
5596 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5597 | ||
5598 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5599 | DRM_ERROR("DPLL0 not locked\n"); | |
5600 | } | |
5601 | ||
5602 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5603 | { | |
5604 | int ret; | |
5605 | u32 val; | |
5606 | ||
5607 | /* inform PCU we want to change CDCLK */ | |
5608 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5609 | mutex_lock(&dev_priv->rps.hw_lock); | |
5610 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5611 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5612 | ||
5613 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5614 | } | |
5615 | ||
5616 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5617 | { | |
5618 | unsigned int i; | |
5619 | ||
5620 | for (i = 0; i < 15; i++) { | |
5621 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5622 | return true; | |
5623 | udelay(10); | |
5624 | } | |
5625 | ||
5626 | return false; | |
5627 | } | |
5628 | ||
5629 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5630 | { | |
560a7ae4 | 5631 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5632 | u32 freq_select, pcu_ack; |
5633 | ||
5634 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5635 | ||
5636 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5637 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5638 | return; | |
5639 | } | |
5640 | ||
5641 | /* set CDCLK_CTL */ | |
5642 | switch(freq) { | |
5643 | case 450000: | |
5644 | case 432000: | |
5645 | freq_select = CDCLK_FREQ_450_432; | |
5646 | pcu_ack = 1; | |
5647 | break; | |
5648 | case 540000: | |
5649 | freq_select = CDCLK_FREQ_540; | |
5650 | pcu_ack = 2; | |
5651 | break; | |
5652 | case 308570: | |
5653 | case 337500: | |
5654 | default: | |
5655 | freq_select = CDCLK_FREQ_337_308; | |
5656 | pcu_ack = 0; | |
5657 | break; | |
5658 | case 617140: | |
5659 | case 675000: | |
5660 | freq_select = CDCLK_FREQ_675_617; | |
5661 | pcu_ack = 3; | |
5662 | break; | |
5663 | } | |
5664 | ||
5665 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5666 | POSTING_READ(CDCLK_CTL); | |
5667 | ||
5668 | /* inform PCU of the change */ | |
5669 | mutex_lock(&dev_priv->rps.hw_lock); | |
5670 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5671 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5672 | |
5673 | intel_update_cdclk(dev); | |
5d96d8af DL |
5674 | } |
5675 | ||
5676 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5677 | { | |
5678 | /* disable DBUF power */ | |
5679 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5680 | POSTING_READ(DBUF_CTL); | |
5681 | ||
5682 | udelay(10); | |
5683 | ||
5684 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5685 | DRM_ERROR("DBuf power disable timeout\n"); | |
5686 | ||
ab96c1ee ID |
5687 | /* disable DPLL0 */ |
5688 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5689 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5690 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5691 | } |
5692 | ||
5693 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5694 | { | |
5d96d8af DL |
5695 | unsigned int required_vco; |
5696 | ||
39d9b85a GW |
5697 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5698 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5699 | /* enable DPLL0 */ | |
5700 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5701 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5702 | } |
5703 | ||
5d96d8af DL |
5704 | /* set CDCLK to the frequency the BIOS chose */ |
5705 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5706 | ||
5707 | /* enable DBUF power */ | |
5708 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5709 | POSTING_READ(DBUF_CTL); | |
5710 | ||
5711 | udelay(10); | |
5712 | ||
5713 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5714 | DRM_ERROR("DBuf power enable timeout\n"); | |
5715 | } | |
5716 | ||
c73666f3 SK |
5717 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5718 | { | |
5719 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5720 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5721 | int freq = dev_priv->skl_boot_cdclk; | |
5722 | ||
f1b391a5 SK |
5723 | /* |
5724 | * check if the pre-os intialized the display | |
5725 | * There is SWF18 scratchpad register defined which is set by the | |
5726 | * pre-os which can be used by the OS drivers to check the status | |
5727 | */ | |
5728 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5729 | goto sanitize; | |
5730 | ||
c73666f3 SK |
5731 | /* Is PLL enabled and locked ? */ |
5732 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5733 | goto sanitize; | |
5734 | ||
5735 | /* DPLL okay; verify the cdclock | |
5736 | * | |
5737 | * Noticed in some instances that the freq selection is correct but | |
5738 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5739 | * enable display. Verify the same as well. | |
5740 | */ | |
5741 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5742 | /* All well; nothing to sanitize */ | |
5743 | return false; | |
5744 | sanitize: | |
5745 | /* | |
5746 | * As of now initialize with max cdclk till | |
5747 | * we get dynamic cdclk support | |
5748 | * */ | |
5749 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5750 | skl_init_cdclk(dev_priv); | |
5751 | ||
5752 | /* we did have to sanitize */ | |
5753 | return true; | |
5754 | } | |
5755 | ||
30a970c6 JB |
5756 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5757 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5758 | { | |
5759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5760 | u32 val, cmd; | |
5761 | ||
164dfd28 VK |
5762 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5763 | != dev_priv->cdclk_freq); | |
d60c4473 | 5764 | |
dfcab17e | 5765 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5766 | cmd = 2; |
dfcab17e | 5767 | else if (cdclk == 266667) |
30a970c6 JB |
5768 | cmd = 1; |
5769 | else | |
5770 | cmd = 0; | |
5771 | ||
5772 | mutex_lock(&dev_priv->rps.hw_lock); | |
5773 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5774 | val &= ~DSPFREQGUAR_MASK; | |
5775 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5776 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5777 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5778 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5779 | 50)) { | |
5780 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5781 | } | |
5782 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5783 | ||
54433e91 VS |
5784 | mutex_lock(&dev_priv->sb_lock); |
5785 | ||
dfcab17e | 5786 | if (cdclk == 400000) { |
6bcda4f0 | 5787 | u32 divider; |
30a970c6 | 5788 | |
6bcda4f0 | 5789 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5790 | |
30a970c6 JB |
5791 | /* adjust cdclk divider */ |
5792 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5793 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5794 | val |= divider; |
5795 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5796 | |
5797 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5798 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5799 | 50)) |
5800 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5801 | } |
5802 | ||
30a970c6 JB |
5803 | /* adjust self-refresh exit latency value */ |
5804 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5805 | val &= ~0x7f; | |
5806 | ||
5807 | /* | |
5808 | * For high bandwidth configs, we set a higher latency in the bunit | |
5809 | * so that the core display fetch happens in time to avoid underruns. | |
5810 | */ | |
dfcab17e | 5811 | if (cdclk == 400000) |
30a970c6 JB |
5812 | val |= 4500 / 250; /* 4.5 usec */ |
5813 | else | |
5814 | val |= 3000 / 250; /* 3.0 usec */ | |
5815 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5816 | |
a580516d | 5817 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5818 | |
b6283055 | 5819 | intel_update_cdclk(dev); |
30a970c6 JB |
5820 | } |
5821 | ||
383c5a6a VS |
5822 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5823 | { | |
5824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5825 | u32 val, cmd; | |
5826 | ||
164dfd28 VK |
5827 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5828 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5829 | |
5830 | switch (cdclk) { | |
383c5a6a VS |
5831 | case 333333: |
5832 | case 320000: | |
383c5a6a | 5833 | case 266667: |
383c5a6a | 5834 | case 200000: |
383c5a6a VS |
5835 | break; |
5836 | default: | |
5f77eeb0 | 5837 | MISSING_CASE(cdclk); |
383c5a6a VS |
5838 | return; |
5839 | } | |
5840 | ||
9d0d3fda VS |
5841 | /* |
5842 | * Specs are full of misinformation, but testing on actual | |
5843 | * hardware has shown that we just need to write the desired | |
5844 | * CCK divider into the Punit register. | |
5845 | */ | |
5846 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5847 | ||
383c5a6a VS |
5848 | mutex_lock(&dev_priv->rps.hw_lock); |
5849 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5850 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5851 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5852 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5853 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5854 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5855 | 50)) { | |
5856 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5857 | } | |
5858 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5859 | ||
b6283055 | 5860 | intel_update_cdclk(dev); |
383c5a6a VS |
5861 | } |
5862 | ||
30a970c6 JB |
5863 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5864 | int max_pixclk) | |
5865 | { | |
6bcda4f0 | 5866 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5867 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5868 | |
30a970c6 JB |
5869 | /* |
5870 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5871 | * 200MHz | |
5872 | * 267MHz | |
29dc7ef3 | 5873 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5874 | * 400MHz (VLV only) |
5875 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5876 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5877 | * |
5878 | * We seem to get an unstable or solid color picture at 200MHz. | |
5879 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5880 | * are off. | |
30a970c6 | 5881 | */ |
6cca3195 VS |
5882 | if (!IS_CHERRYVIEW(dev_priv) && |
5883 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5884 | return 400000; |
6cca3195 | 5885 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5886 | return freq_320; |
e37c67a1 | 5887 | else if (max_pixclk > 0) |
dfcab17e | 5888 | return 266667; |
e37c67a1 VS |
5889 | else |
5890 | return 200000; | |
30a970c6 JB |
5891 | } |
5892 | ||
f8437dd1 VK |
5893 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5894 | int max_pixclk) | |
5895 | { | |
5896 | /* | |
5897 | * FIXME: | |
5898 | * - remove the guardband, it's not needed on BXT | |
5899 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5900 | */ | |
5901 | if (max_pixclk > 576000*9/10) | |
5902 | return 624000; | |
5903 | else if (max_pixclk > 384000*9/10) | |
5904 | return 576000; | |
5905 | else if (max_pixclk > 288000*9/10) | |
5906 | return 384000; | |
5907 | else if (max_pixclk > 144000*9/10) | |
5908 | return 288000; | |
5909 | else | |
5910 | return 144000; | |
5911 | } | |
5912 | ||
e8788cbc | 5913 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5914 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5915 | struct drm_atomic_state *state) | |
30a970c6 | 5916 | { |
565602d7 ML |
5917 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
5918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5919 | struct drm_crtc *crtc; | |
5920 | struct drm_crtc_state *crtc_state; | |
5921 | unsigned max_pixclk = 0, i; | |
5922 | enum pipe pipe; | |
30a970c6 | 5923 | |
565602d7 ML |
5924 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5925 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5926 | |
565602d7 ML |
5927 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5928 | int pixclk = 0; | |
5929 | ||
5930 | if (crtc_state->enable) | |
5931 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5932 | |
565602d7 | 5933 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5934 | } |
5935 | ||
565602d7 ML |
5936 | for_each_pipe(dev_priv, pipe) |
5937 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5938 | ||
30a970c6 JB |
5939 | return max_pixclk; |
5940 | } | |
5941 | ||
27c329ed | 5942 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5943 | { |
27c329ed ML |
5944 | struct drm_device *dev = state->dev; |
5945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5946 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5947 | struct intel_atomic_state *intel_state = |
5948 | to_intel_atomic_state(state); | |
30a970c6 | 5949 | |
304603f4 ACO |
5950 | if (max_pixclk < 0) |
5951 | return max_pixclk; | |
30a970c6 | 5952 | |
1a617b77 | 5953 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5954 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 5955 | |
1a617b77 ML |
5956 | if (!intel_state->active_crtcs) |
5957 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5958 | ||
27c329ed ML |
5959 | return 0; |
5960 | } | |
304603f4 | 5961 | |
27c329ed ML |
5962 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5963 | { | |
5964 | struct drm_device *dev = state->dev; | |
5965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5966 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5967 | struct intel_atomic_state *intel_state = |
5968 | to_intel_atomic_state(state); | |
85a96e7a | 5969 | |
27c329ed ML |
5970 | if (max_pixclk < 0) |
5971 | return max_pixclk; | |
85a96e7a | 5972 | |
1a617b77 | 5973 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5974 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 5975 | |
1a617b77 ML |
5976 | if (!intel_state->active_crtcs) |
5977 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
5978 | ||
27c329ed | 5979 | return 0; |
30a970c6 JB |
5980 | } |
5981 | ||
1e69cd74 VS |
5982 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5983 | { | |
5984 | unsigned int credits, default_credits; | |
5985 | ||
5986 | if (IS_CHERRYVIEW(dev_priv)) | |
5987 | default_credits = PFI_CREDIT(12); | |
5988 | else | |
5989 | default_credits = PFI_CREDIT(8); | |
5990 | ||
bfa7df01 | 5991 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
5992 | /* CHV suggested value is 31 or 63 */ |
5993 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5994 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5995 | else |
5996 | credits = PFI_CREDIT(15); | |
5997 | } else { | |
5998 | credits = default_credits; | |
5999 | } | |
6000 | ||
6001 | /* | |
6002 | * WA - write default credits before re-programming | |
6003 | * FIXME: should we also set the resend bit here? | |
6004 | */ | |
6005 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6006 | default_credits); | |
6007 | ||
6008 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6009 | credits | PFI_CREDIT_RESEND); | |
6010 | ||
6011 | /* | |
6012 | * FIXME is this guaranteed to clear | |
6013 | * immediately or should we poll for it? | |
6014 | */ | |
6015 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6016 | } | |
6017 | ||
27c329ed | 6018 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6019 | { |
a821fc46 | 6020 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6021 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6022 | struct intel_atomic_state *old_intel_state = |
6023 | to_intel_atomic_state(old_state); | |
6024 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6025 | |
27c329ed ML |
6026 | /* |
6027 | * FIXME: We can end up here with all power domains off, yet | |
6028 | * with a CDCLK frequency other than the minimum. To account | |
6029 | * for this take the PIPE-A power domain, which covers the HW | |
6030 | * blocks needed for the following programming. This can be | |
6031 | * removed once it's guaranteed that we get here either with | |
6032 | * the minimum CDCLK set, or the required power domains | |
6033 | * enabled. | |
6034 | */ | |
6035 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6036 | |
27c329ed ML |
6037 | if (IS_CHERRYVIEW(dev)) |
6038 | cherryview_set_cdclk(dev, req_cdclk); | |
6039 | else | |
6040 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6041 | |
27c329ed | 6042 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6043 | |
27c329ed | 6044 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6045 | } |
6046 | ||
89b667f8 JB |
6047 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6048 | { | |
6049 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6050 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6052 | struct intel_encoder *encoder; | |
6053 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6054 | |
53d9f4e9 | 6055 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6056 | return; |
6057 | ||
6e3c9717 | 6058 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6059 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6060 | |
6061 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6062 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6063 | |
c14b0485 VS |
6064 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6066 | ||
6067 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6068 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6069 | } | |
6070 | ||
5b18e57c DV |
6071 | i9xx_set_pipeconf(intel_crtc); |
6072 | ||
89b667f8 | 6073 | intel_crtc->active = true; |
89b667f8 | 6074 | |
a72e4c9f | 6075 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6076 | |
89b667f8 JB |
6077 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6078 | if (encoder->pre_pll_enable) | |
6079 | encoder->pre_pll_enable(encoder); | |
6080 | ||
a65347ba | 6081 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6082 | if (IS_CHERRYVIEW(dev)) { |
6083 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6084 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6085 | } else { |
6086 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6087 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6088 | } |
9d556c99 | 6089 | } |
89b667f8 JB |
6090 | |
6091 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6092 | if (encoder->pre_enable) | |
6093 | encoder->pre_enable(encoder); | |
6094 | ||
2dd24552 JB |
6095 | i9xx_pfit_enable(intel_crtc); |
6096 | ||
8563b1e8 | 6097 | intel_color_load_luts(crtc); |
63cbb074 | 6098 | |
caed361d | 6099 | intel_update_watermarks(crtc); |
e1fdc473 | 6100 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6101 | |
4b3a9526 VS |
6102 | assert_vblank_disabled(crtc); |
6103 | drm_crtc_vblank_on(crtc); | |
6104 | ||
f9b61ff6 DV |
6105 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6106 | encoder->enable(encoder); | |
89b667f8 JB |
6107 | } |
6108 | ||
f13c2ef3 DV |
6109 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6110 | { | |
6111 | struct drm_device *dev = crtc->base.dev; | |
6112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6113 | ||
6e3c9717 ACO |
6114 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6115 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6116 | } |
6117 | ||
0b8765c6 | 6118 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6119 | { |
6120 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6121 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6122 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6123 | struct intel_encoder *encoder; |
79e53945 | 6124 | int pipe = intel_crtc->pipe; |
79e53945 | 6125 | |
53d9f4e9 | 6126 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6127 | return; |
6128 | ||
f13c2ef3 DV |
6129 | i9xx_set_pll_dividers(intel_crtc); |
6130 | ||
6e3c9717 | 6131 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6132 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6133 | |
6134 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6135 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6136 | |
5b18e57c DV |
6137 | i9xx_set_pipeconf(intel_crtc); |
6138 | ||
f7abfe8b | 6139 | intel_crtc->active = true; |
6b383a7f | 6140 | |
4a3436e8 | 6141 | if (!IS_GEN2(dev)) |
a72e4c9f | 6142 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6143 | |
9d6d9f19 MK |
6144 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6145 | if (encoder->pre_enable) | |
6146 | encoder->pre_enable(encoder); | |
6147 | ||
f6736a1a DV |
6148 | i9xx_enable_pll(intel_crtc); |
6149 | ||
2dd24552 JB |
6150 | i9xx_pfit_enable(intel_crtc); |
6151 | ||
8563b1e8 | 6152 | intel_color_load_luts(crtc); |
63cbb074 | 6153 | |
f37fcc2a | 6154 | intel_update_watermarks(crtc); |
e1fdc473 | 6155 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6156 | |
4b3a9526 VS |
6157 | assert_vblank_disabled(crtc); |
6158 | drm_crtc_vblank_on(crtc); | |
6159 | ||
f9b61ff6 DV |
6160 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6161 | encoder->enable(encoder); | |
0b8765c6 | 6162 | } |
79e53945 | 6163 | |
87476d63 DV |
6164 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6165 | { | |
6166 | struct drm_device *dev = crtc->base.dev; | |
6167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6168 | |
6e3c9717 | 6169 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6170 | return; |
87476d63 | 6171 | |
328d8e82 | 6172 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6173 | |
328d8e82 DV |
6174 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6175 | I915_READ(PFIT_CONTROL)); | |
6176 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6177 | } |
6178 | ||
0b8765c6 JB |
6179 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6180 | { | |
6181 | struct drm_device *dev = crtc->dev; | |
6182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6184 | struct intel_encoder *encoder; |
0b8765c6 | 6185 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6186 | |
6304cd91 VS |
6187 | /* |
6188 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6189 | * wait for planes to fully turn off before disabling the pipe. | |
6190 | */ | |
90e83e53 ACO |
6191 | if (IS_GEN2(dev)) |
6192 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6193 | |
4b3a9526 VS |
6194 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6195 | encoder->disable(encoder); | |
6196 | ||
f9b61ff6 DV |
6197 | drm_crtc_vblank_off(crtc); |
6198 | assert_vblank_disabled(crtc); | |
6199 | ||
575f7ab7 | 6200 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6201 | |
87476d63 | 6202 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6203 | |
89b667f8 JB |
6204 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6205 | if (encoder->post_disable) | |
6206 | encoder->post_disable(encoder); | |
6207 | ||
a65347ba | 6208 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6209 | if (IS_CHERRYVIEW(dev)) |
6210 | chv_disable_pll(dev_priv, pipe); | |
6211 | else if (IS_VALLEYVIEW(dev)) | |
6212 | vlv_disable_pll(dev_priv, pipe); | |
6213 | else | |
1c4e0274 | 6214 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6215 | } |
0b8765c6 | 6216 | |
d6db995f VS |
6217 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6218 | if (encoder->post_pll_disable) | |
6219 | encoder->post_pll_disable(encoder); | |
6220 | ||
4a3436e8 | 6221 | if (!IS_GEN2(dev)) |
a72e4c9f | 6222 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6223 | } |
6224 | ||
b17d48e2 ML |
6225 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6226 | { | |
842e0307 | 6227 | struct intel_encoder *encoder; |
b17d48e2 ML |
6228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6229 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6230 | enum intel_display_power_domain domain; | |
6231 | unsigned long domains; | |
6232 | ||
6233 | if (!intel_crtc->active) | |
6234 | return; | |
6235 | ||
a539205a | 6236 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6237 | WARN_ON(intel_crtc->unpin_work); |
6238 | ||
2622a081 | 6239 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6240 | |
6241 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6242 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6243 | } |
6244 | ||
b17d48e2 | 6245 | dev_priv->display.crtc_disable(crtc); |
842e0307 ML |
6246 | |
6247 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6248 | crtc->base.id); | |
6249 | ||
6250 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6251 | crtc->state->active = false; | |
37d9078b | 6252 | intel_crtc->active = false; |
842e0307 ML |
6253 | crtc->enabled = false; |
6254 | crtc->state->connector_mask = 0; | |
6255 | crtc->state->encoder_mask = 0; | |
6256 | ||
6257 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6258 | encoder->base.crtc = NULL; | |
6259 | ||
58f9c0bc | 6260 | intel_fbc_disable(intel_crtc); |
37d9078b | 6261 | intel_update_watermarks(crtc); |
1f7457b1 | 6262 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6263 | |
6264 | domains = intel_crtc->enabled_power_domains; | |
6265 | for_each_power_domain(domain, domains) | |
6266 | intel_display_power_put(dev_priv, domain); | |
6267 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6268 | |
6269 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6270 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6271 | } |
6272 | ||
6b72d486 ML |
6273 | /* |
6274 | * turn all crtc's off, but do not adjust state | |
6275 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6276 | */ | |
70e0bd74 | 6277 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6278 | { |
e2c8b870 | 6279 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6280 | struct drm_atomic_state *state; |
e2c8b870 | 6281 | int ret; |
70e0bd74 | 6282 | |
e2c8b870 ML |
6283 | state = drm_atomic_helper_suspend(dev); |
6284 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6285 | if (ret) |
6286 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6287 | else |
6288 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6289 | return ret; |
ee7b9f93 JB |
6290 | } |
6291 | ||
ea5b213a | 6292 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6293 | { |
4ef69c7a | 6294 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6295 | |
ea5b213a CW |
6296 | drm_encoder_cleanup(encoder); |
6297 | kfree(intel_encoder); | |
7e7d76c3 JB |
6298 | } |
6299 | ||
0a91ca29 DV |
6300 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6301 | * internal consistency). */ | |
b980514c | 6302 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6303 | { |
35dd3c64 ML |
6304 | struct drm_crtc *crtc = connector->base.state->crtc; |
6305 | ||
6306 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6307 | connector->base.base.id, | |
6308 | connector->base.name); | |
6309 | ||
0a91ca29 | 6310 | if (connector->get_hw_state(connector)) { |
e85376cb | 6311 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6312 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6313 | |
35dd3c64 ML |
6314 | I915_STATE_WARN(!crtc, |
6315 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6316 | |
35dd3c64 ML |
6317 | if (!crtc) |
6318 | return; | |
6319 | ||
6320 | I915_STATE_WARN(!crtc->state->active, | |
6321 | "connector is active, but attached crtc isn't\n"); | |
6322 | ||
e85376cb | 6323 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6324 | return; |
6325 | ||
e85376cb | 6326 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6327 | "atomic encoder doesn't match attached encoder\n"); |
6328 | ||
e85376cb | 6329 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6330 | "attached encoder crtc differs from connector crtc\n"); |
6331 | } else { | |
4d688a2a ML |
6332 | I915_STATE_WARN(crtc && crtc->state->active, |
6333 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6334 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6335 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6336 | } |
79e53945 JB |
6337 | } |
6338 | ||
08d9bc92 ACO |
6339 | int intel_connector_init(struct intel_connector *connector) |
6340 | { | |
5350a031 | 6341 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6342 | |
5350a031 | 6343 | if (!connector->base.state) |
08d9bc92 ACO |
6344 | return -ENOMEM; |
6345 | ||
08d9bc92 ACO |
6346 | return 0; |
6347 | } | |
6348 | ||
6349 | struct intel_connector *intel_connector_alloc(void) | |
6350 | { | |
6351 | struct intel_connector *connector; | |
6352 | ||
6353 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6354 | if (!connector) | |
6355 | return NULL; | |
6356 | ||
6357 | if (intel_connector_init(connector) < 0) { | |
6358 | kfree(connector); | |
6359 | return NULL; | |
6360 | } | |
6361 | ||
6362 | return connector; | |
6363 | } | |
6364 | ||
f0947c37 DV |
6365 | /* Simple connector->get_hw_state implementation for encoders that support only |
6366 | * one connector and no cloning and hence the encoder state determines the state | |
6367 | * of the connector. */ | |
6368 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6369 | { |
24929352 | 6370 | enum pipe pipe = 0; |
f0947c37 | 6371 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6372 | |
f0947c37 | 6373 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6374 | } |
6375 | ||
6d293983 | 6376 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6377 | { |
6d293983 ACO |
6378 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6379 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6380 | |
6381 | return 0; | |
6382 | } | |
6383 | ||
6d293983 | 6384 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6385 | struct intel_crtc_state *pipe_config) |
1857e1da | 6386 | { |
6d293983 ACO |
6387 | struct drm_atomic_state *state = pipe_config->base.state; |
6388 | struct intel_crtc *other_crtc; | |
6389 | struct intel_crtc_state *other_crtc_state; | |
6390 | ||
1857e1da DV |
6391 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6392 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6393 | if (pipe_config->fdi_lanes > 4) { | |
6394 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6395 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6396 | return -EINVAL; |
1857e1da DV |
6397 | } |
6398 | ||
bafb6553 | 6399 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6400 | if (pipe_config->fdi_lanes > 2) { |
6401 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6402 | pipe_config->fdi_lanes); | |
6d293983 | 6403 | return -EINVAL; |
1857e1da | 6404 | } else { |
6d293983 | 6405 | return 0; |
1857e1da DV |
6406 | } |
6407 | } | |
6408 | ||
6409 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6410 | return 0; |
1857e1da DV |
6411 | |
6412 | /* Ivybridge 3 pipe is really complicated */ | |
6413 | switch (pipe) { | |
6414 | case PIPE_A: | |
6d293983 | 6415 | return 0; |
1857e1da | 6416 | case PIPE_B: |
6d293983 ACO |
6417 | if (pipe_config->fdi_lanes <= 2) |
6418 | return 0; | |
6419 | ||
6420 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6421 | other_crtc_state = | |
6422 | intel_atomic_get_crtc_state(state, other_crtc); | |
6423 | if (IS_ERR(other_crtc_state)) | |
6424 | return PTR_ERR(other_crtc_state); | |
6425 | ||
6426 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6427 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6428 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6429 | return -EINVAL; |
1857e1da | 6430 | } |
6d293983 | 6431 | return 0; |
1857e1da | 6432 | case PIPE_C: |
251cc67c VS |
6433 | if (pipe_config->fdi_lanes > 2) { |
6434 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6435 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6436 | return -EINVAL; |
251cc67c | 6437 | } |
6d293983 ACO |
6438 | |
6439 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6440 | other_crtc_state = | |
6441 | intel_atomic_get_crtc_state(state, other_crtc); | |
6442 | if (IS_ERR(other_crtc_state)) | |
6443 | return PTR_ERR(other_crtc_state); | |
6444 | ||
6445 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6446 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6447 | return -EINVAL; |
1857e1da | 6448 | } |
6d293983 | 6449 | return 0; |
1857e1da DV |
6450 | default: |
6451 | BUG(); | |
6452 | } | |
6453 | } | |
6454 | ||
e29c22c0 DV |
6455 | #define RETRY 1 |
6456 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6457 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6458 | { |
1857e1da | 6459 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6460 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6461 | int lane, link_bw, fdi_dotclock, ret; |
6462 | bool needs_recompute = false; | |
877d48d5 | 6463 | |
e29c22c0 | 6464 | retry: |
877d48d5 DV |
6465 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6466 | * each output octet as 10 bits. The actual frequency | |
6467 | * is stored as a divider into a 100MHz clock, and the | |
6468 | * mode pixel clock is stored in units of 1KHz. | |
6469 | * Hence the bw of each lane in terms of the mode signal | |
6470 | * is: | |
6471 | */ | |
21a727b3 | 6472 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6473 | |
241bfc38 | 6474 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6475 | |
2bd89a07 | 6476 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6477 | pipe_config->pipe_bpp); |
6478 | ||
6479 | pipe_config->fdi_lanes = lane; | |
6480 | ||
2bd89a07 | 6481 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6482 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6483 | |
e3b247da | 6484 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6485 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6486 | pipe_config->pipe_bpp -= 2*3; |
6487 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6488 | pipe_config->pipe_bpp); | |
6489 | needs_recompute = true; | |
6490 | pipe_config->bw_constrained = true; | |
6491 | ||
6492 | goto retry; | |
6493 | } | |
6494 | ||
6495 | if (needs_recompute) | |
6496 | return RETRY; | |
6497 | ||
6d293983 | 6498 | return ret; |
877d48d5 DV |
6499 | } |
6500 | ||
8cfb3407 VS |
6501 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6502 | struct intel_crtc_state *pipe_config) | |
6503 | { | |
6504 | if (pipe_config->pipe_bpp > 24) | |
6505 | return false; | |
6506 | ||
6507 | /* HSW can handle pixel rate up to cdclk? */ | |
6508 | if (IS_HASWELL(dev_priv->dev)) | |
6509 | return true; | |
6510 | ||
6511 | /* | |
b432e5cf VS |
6512 | * We compare against max which means we must take |
6513 | * the increased cdclk requirement into account when | |
6514 | * calculating the new cdclk. | |
6515 | * | |
6516 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6517 | */ |
6518 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6519 | dev_priv->max_cdclk_freq * 95 / 100; | |
6520 | } | |
6521 | ||
42db64ef | 6522 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6523 | struct intel_crtc_state *pipe_config) |
42db64ef | 6524 | { |
8cfb3407 VS |
6525 | struct drm_device *dev = crtc->base.dev; |
6526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6527 | ||
d330a953 | 6528 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6529 | hsw_crtc_supports_ips(crtc) && |
6530 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6531 | } |
6532 | ||
39acb4aa VS |
6533 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6534 | { | |
6535 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6536 | ||
6537 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6538 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6539 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6540 | } | |
6541 | ||
a43f6e0f | 6542 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6543 | struct intel_crtc_state *pipe_config) |
79e53945 | 6544 | { |
a43f6e0f | 6545 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6546 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6547 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6548 | |
ad3a4479 | 6549 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6550 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6551 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6552 | |
6553 | /* | |
39acb4aa | 6554 | * Enable double wide mode when the dot clock |
cf532bb2 | 6555 | * is > 90% of the (display) core speed. |
cf532bb2 | 6556 | */ |
39acb4aa VS |
6557 | if (intel_crtc_supports_double_wide(crtc) && |
6558 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6559 | clock_limit *= 2; |
cf532bb2 | 6560 | pipe_config->double_wide = true; |
ad3a4479 VS |
6561 | } |
6562 | ||
39acb4aa VS |
6563 | if (adjusted_mode->crtc_clock > clock_limit) { |
6564 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6565 | adjusted_mode->crtc_clock, clock_limit, | |
6566 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6567 | return -EINVAL; |
39acb4aa | 6568 | } |
2c07245f | 6569 | } |
89749350 | 6570 | |
1d1d0e27 VS |
6571 | /* |
6572 | * Pipe horizontal size must be even in: | |
6573 | * - DVO ganged mode | |
6574 | * - LVDS dual channel mode | |
6575 | * - Double wide pipe | |
6576 | */ | |
a93e255f | 6577 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6578 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6579 | pipe_config->pipe_src_w &= ~1; | |
6580 | ||
8693a824 DL |
6581 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6582 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6583 | */ |
6584 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6585 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6586 | return -EINVAL; |
44f46b42 | 6587 | |
f5adf94e | 6588 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6589 | hsw_compute_ips_config(crtc, pipe_config); |
6590 | ||
877d48d5 | 6591 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6592 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6593 | |
cf5a15be | 6594 | return 0; |
79e53945 JB |
6595 | } |
6596 | ||
1652d19e VS |
6597 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6598 | { | |
6599 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6600 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6601 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6602 | uint32_t linkrate; | |
6603 | ||
414355a7 | 6604 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6605 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6606 | |
6607 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6608 | return 540000; | |
6609 | ||
6610 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6611 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6612 | |
71cd8423 DL |
6613 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6614 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6615 | /* vco 8640 */ |
6616 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6617 | case CDCLK_FREQ_450_432: | |
6618 | return 432000; | |
6619 | case CDCLK_FREQ_337_308: | |
6620 | return 308570; | |
6621 | case CDCLK_FREQ_675_617: | |
6622 | return 617140; | |
6623 | default: | |
6624 | WARN(1, "Unknown cd freq selection\n"); | |
6625 | } | |
6626 | } else { | |
6627 | /* vco 8100 */ | |
6628 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6629 | case CDCLK_FREQ_450_432: | |
6630 | return 450000; | |
6631 | case CDCLK_FREQ_337_308: | |
6632 | return 337500; | |
6633 | case CDCLK_FREQ_675_617: | |
6634 | return 675000; | |
6635 | default: | |
6636 | WARN(1, "Unknown cd freq selection\n"); | |
6637 | } | |
6638 | } | |
6639 | ||
6640 | /* error case, do as if DPLL0 isn't enabled */ | |
6641 | return 24000; | |
6642 | } | |
6643 | ||
acd3f3d3 BP |
6644 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6645 | { | |
6646 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6647 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6648 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6649 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6650 | int cdclk; | |
6651 | ||
6652 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6653 | return 19200; | |
6654 | ||
6655 | cdclk = 19200 * pll_ratio / 2; | |
6656 | ||
6657 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6658 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6659 | return cdclk; /* 576MHz or 624MHz */ | |
6660 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6661 | return cdclk * 2 / 3; /* 384MHz */ | |
6662 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6663 | return cdclk / 2; /* 288MHz */ | |
6664 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6665 | return cdclk / 4; /* 144MHz */ | |
6666 | } | |
6667 | ||
6668 | /* error case, do as if DE PLL isn't enabled */ | |
6669 | return 19200; | |
6670 | } | |
6671 | ||
1652d19e VS |
6672 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6673 | { | |
6674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6675 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6676 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6677 | ||
6678 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6679 | return 800000; | |
6680 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6681 | return 450000; | |
6682 | else if (freq == LCPLL_CLK_FREQ_450) | |
6683 | return 450000; | |
6684 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6685 | return 540000; | |
6686 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6687 | return 337500; | |
6688 | else | |
6689 | return 675000; | |
6690 | } | |
6691 | ||
6692 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6693 | { | |
6694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6695 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6696 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6697 | ||
6698 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6699 | return 800000; | |
6700 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6701 | return 450000; | |
6702 | else if (freq == LCPLL_CLK_FREQ_450) | |
6703 | return 450000; | |
6704 | else if (IS_HSW_ULT(dev)) | |
6705 | return 337500; | |
6706 | else | |
6707 | return 540000; | |
79e53945 JB |
6708 | } |
6709 | ||
25eb05fc JB |
6710 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6711 | { | |
bfa7df01 VS |
6712 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6713 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6714 | } |
6715 | ||
b37a6434 VS |
6716 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6717 | { | |
6718 | return 450000; | |
6719 | } | |
6720 | ||
e70236a8 JB |
6721 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6722 | { | |
6723 | return 400000; | |
6724 | } | |
79e53945 | 6725 | |
e70236a8 | 6726 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6727 | { |
e907f170 | 6728 | return 333333; |
e70236a8 | 6729 | } |
79e53945 | 6730 | |
e70236a8 JB |
6731 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6732 | { | |
6733 | return 200000; | |
6734 | } | |
79e53945 | 6735 | |
257a7ffc DV |
6736 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6737 | { | |
6738 | u16 gcfgc = 0; | |
6739 | ||
6740 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6741 | ||
6742 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6743 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6744 | return 266667; |
257a7ffc | 6745 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6746 | return 333333; |
257a7ffc | 6747 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6748 | return 444444; |
257a7ffc DV |
6749 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6750 | return 200000; | |
6751 | default: | |
6752 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6753 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6754 | return 133333; |
257a7ffc | 6755 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6756 | return 166667; |
257a7ffc DV |
6757 | } |
6758 | } | |
6759 | ||
e70236a8 JB |
6760 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6761 | { | |
6762 | u16 gcfgc = 0; | |
79e53945 | 6763 | |
e70236a8 JB |
6764 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6765 | ||
6766 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6767 | return 133333; |
e70236a8 JB |
6768 | else { |
6769 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6770 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6771 | return 333333; |
e70236a8 JB |
6772 | default: |
6773 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6774 | return 190000; | |
79e53945 | 6775 | } |
e70236a8 JB |
6776 | } |
6777 | } | |
6778 | ||
6779 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6780 | { | |
e907f170 | 6781 | return 266667; |
e70236a8 JB |
6782 | } |
6783 | ||
1b1d2716 | 6784 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6785 | { |
6786 | u16 hpllcc = 0; | |
1b1d2716 | 6787 | |
65cd2b3f VS |
6788 | /* |
6789 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6790 | * encoding is different :( | |
6791 | * FIXME is this the right way to detect 852GM/852GMV? | |
6792 | */ | |
6793 | if (dev->pdev->revision == 0x1) | |
6794 | return 133333; | |
6795 | ||
1b1d2716 VS |
6796 | pci_bus_read_config_word(dev->pdev->bus, |
6797 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6798 | ||
e70236a8 JB |
6799 | /* Assume that the hardware is in the high speed state. This |
6800 | * should be the default. | |
6801 | */ | |
6802 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6803 | case GC_CLOCK_133_200: | |
1b1d2716 | 6804 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6805 | case GC_CLOCK_100_200: |
6806 | return 200000; | |
6807 | case GC_CLOCK_166_250: | |
6808 | return 250000; | |
6809 | case GC_CLOCK_100_133: | |
e907f170 | 6810 | return 133333; |
1b1d2716 VS |
6811 | case GC_CLOCK_133_266: |
6812 | case GC_CLOCK_133_266_2: | |
6813 | case GC_CLOCK_166_266: | |
6814 | return 266667; | |
e70236a8 | 6815 | } |
79e53945 | 6816 | |
e70236a8 JB |
6817 | /* Shouldn't happen */ |
6818 | return 0; | |
6819 | } | |
79e53945 | 6820 | |
e70236a8 JB |
6821 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6822 | { | |
e907f170 | 6823 | return 133333; |
79e53945 JB |
6824 | } |
6825 | ||
34edce2f VS |
6826 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6827 | { | |
6828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6829 | static const unsigned int blb_vco[8] = { | |
6830 | [0] = 3200000, | |
6831 | [1] = 4000000, | |
6832 | [2] = 5333333, | |
6833 | [3] = 4800000, | |
6834 | [4] = 6400000, | |
6835 | }; | |
6836 | static const unsigned int pnv_vco[8] = { | |
6837 | [0] = 3200000, | |
6838 | [1] = 4000000, | |
6839 | [2] = 5333333, | |
6840 | [3] = 4800000, | |
6841 | [4] = 2666667, | |
6842 | }; | |
6843 | static const unsigned int cl_vco[8] = { | |
6844 | [0] = 3200000, | |
6845 | [1] = 4000000, | |
6846 | [2] = 5333333, | |
6847 | [3] = 6400000, | |
6848 | [4] = 3333333, | |
6849 | [5] = 3566667, | |
6850 | [6] = 4266667, | |
6851 | }; | |
6852 | static const unsigned int elk_vco[8] = { | |
6853 | [0] = 3200000, | |
6854 | [1] = 4000000, | |
6855 | [2] = 5333333, | |
6856 | [3] = 4800000, | |
6857 | }; | |
6858 | static const unsigned int ctg_vco[8] = { | |
6859 | [0] = 3200000, | |
6860 | [1] = 4000000, | |
6861 | [2] = 5333333, | |
6862 | [3] = 6400000, | |
6863 | [4] = 2666667, | |
6864 | [5] = 4266667, | |
6865 | }; | |
6866 | const unsigned int *vco_table; | |
6867 | unsigned int vco; | |
6868 | uint8_t tmp = 0; | |
6869 | ||
6870 | /* FIXME other chipsets? */ | |
6871 | if (IS_GM45(dev)) | |
6872 | vco_table = ctg_vco; | |
6873 | else if (IS_G4X(dev)) | |
6874 | vco_table = elk_vco; | |
6875 | else if (IS_CRESTLINE(dev)) | |
6876 | vco_table = cl_vco; | |
6877 | else if (IS_PINEVIEW(dev)) | |
6878 | vco_table = pnv_vco; | |
6879 | else if (IS_G33(dev)) | |
6880 | vco_table = blb_vco; | |
6881 | else | |
6882 | return 0; | |
6883 | ||
6884 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6885 | ||
6886 | vco = vco_table[tmp & 0x7]; | |
6887 | if (vco == 0) | |
6888 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6889 | else | |
6890 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6891 | ||
6892 | return vco; | |
6893 | } | |
6894 | ||
6895 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6896 | { | |
6897 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6898 | uint16_t tmp = 0; | |
6899 | ||
6900 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6901 | ||
6902 | cdclk_sel = (tmp >> 12) & 0x1; | |
6903 | ||
6904 | switch (vco) { | |
6905 | case 2666667: | |
6906 | case 4000000: | |
6907 | case 5333333: | |
6908 | return cdclk_sel ? 333333 : 222222; | |
6909 | case 3200000: | |
6910 | return cdclk_sel ? 320000 : 228571; | |
6911 | default: | |
6912 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6913 | return 222222; | |
6914 | } | |
6915 | } | |
6916 | ||
6917 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6918 | { | |
6919 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6920 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6921 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6922 | const uint8_t *div_table; | |
6923 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6924 | uint16_t tmp = 0; | |
6925 | ||
6926 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6927 | ||
6928 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6929 | ||
6930 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6931 | goto fail; | |
6932 | ||
6933 | switch (vco) { | |
6934 | case 3200000: | |
6935 | div_table = div_3200; | |
6936 | break; | |
6937 | case 4000000: | |
6938 | div_table = div_4000; | |
6939 | break; | |
6940 | case 5333333: | |
6941 | div_table = div_5333; | |
6942 | break; | |
6943 | default: | |
6944 | goto fail; | |
6945 | } | |
6946 | ||
6947 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6948 | ||
caf4e252 | 6949 | fail: |
34edce2f VS |
6950 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6951 | return 200000; | |
6952 | } | |
6953 | ||
6954 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6955 | { | |
6956 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6957 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6958 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6959 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6960 | const uint8_t *div_table; | |
6961 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6962 | uint16_t tmp = 0; | |
6963 | ||
6964 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6965 | ||
6966 | cdclk_sel = (tmp >> 4) & 0x7; | |
6967 | ||
6968 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6969 | goto fail; | |
6970 | ||
6971 | switch (vco) { | |
6972 | case 3200000: | |
6973 | div_table = div_3200; | |
6974 | break; | |
6975 | case 4000000: | |
6976 | div_table = div_4000; | |
6977 | break; | |
6978 | case 4800000: | |
6979 | div_table = div_4800; | |
6980 | break; | |
6981 | case 5333333: | |
6982 | div_table = div_5333; | |
6983 | break; | |
6984 | default: | |
6985 | goto fail; | |
6986 | } | |
6987 | ||
6988 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6989 | ||
caf4e252 | 6990 | fail: |
34edce2f VS |
6991 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
6992 | return 190476; | |
6993 | } | |
6994 | ||
2c07245f | 6995 | static void |
a65851af | 6996 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6997 | { |
a65851af VS |
6998 | while (*num > DATA_LINK_M_N_MASK || |
6999 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7000 | *num >>= 1; |
7001 | *den >>= 1; | |
7002 | } | |
7003 | } | |
7004 | ||
a65851af VS |
7005 | static void compute_m_n(unsigned int m, unsigned int n, |
7006 | uint32_t *ret_m, uint32_t *ret_n) | |
7007 | { | |
7008 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7009 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7010 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7011 | } | |
7012 | ||
e69d0bc1 DV |
7013 | void |
7014 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7015 | int pixel_clock, int link_clock, | |
7016 | struct intel_link_m_n *m_n) | |
2c07245f | 7017 | { |
e69d0bc1 | 7018 | m_n->tu = 64; |
a65851af VS |
7019 | |
7020 | compute_m_n(bits_per_pixel * pixel_clock, | |
7021 | link_clock * nlanes * 8, | |
7022 | &m_n->gmch_m, &m_n->gmch_n); | |
7023 | ||
7024 | compute_m_n(pixel_clock, link_clock, | |
7025 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7026 | } |
7027 | ||
a7615030 CW |
7028 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7029 | { | |
d330a953 JN |
7030 | if (i915.panel_use_ssc >= 0) |
7031 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7032 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7033 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7034 | } |
7035 | ||
ceb41007 | 7036 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state) |
c65d77d8 | 7037 | { |
a93e255f | 7038 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7039 | struct drm_i915_private *dev_priv = dev->dev_private; |
7040 | int refclk; | |
7041 | ||
a93e255f ACO |
7042 | WARN_ON(!crtc_state->base.state); |
7043 | ||
666a4537 | 7044 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7045 | refclk = 100000; |
a93e255f | 7046 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7047 | intel_panel_use_ssc(dev_priv)) { |
e91e941b VS |
7048 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7049 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7050 | } else if (!IS_GEN2(dev)) { |
7051 | refclk = 96000; | |
7052 | } else { | |
7053 | refclk = 48000; | |
7054 | } | |
7055 | ||
7056 | return refclk; | |
7057 | } | |
7058 | ||
7429e9d4 | 7059 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7060 | { |
7df00d7a | 7061 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7062 | } |
f47709a9 | 7063 | |
7429e9d4 DV |
7064 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7065 | { | |
7066 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7067 | } |
7068 | ||
f47709a9 | 7069 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7070 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7071 | intel_clock_t *reduced_clock) |
7072 | { | |
f47709a9 | 7073 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7074 | u32 fp, fp2 = 0; |
7075 | ||
7076 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7077 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7078 | if (reduced_clock) |
7429e9d4 | 7079 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7080 | } else { |
190f68c5 | 7081 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7082 | if (reduced_clock) |
7429e9d4 | 7083 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7084 | } |
7085 | ||
190f68c5 | 7086 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7087 | |
f47709a9 | 7088 | crtc->lowfreq_avail = false; |
a93e255f | 7089 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7090 | reduced_clock) { |
190f68c5 | 7091 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7092 | crtc->lowfreq_avail = true; |
a7516a05 | 7093 | } else { |
190f68c5 | 7094 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7095 | } |
7096 | } | |
7097 | ||
5e69f97f CML |
7098 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7099 | pipe) | |
89b667f8 JB |
7100 | { |
7101 | u32 reg_val; | |
7102 | ||
7103 | /* | |
7104 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7105 | * and set it to a reasonable value instead. | |
7106 | */ | |
ab3c759a | 7107 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7108 | reg_val &= 0xffffff00; |
7109 | reg_val |= 0x00000030; | |
ab3c759a | 7110 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7111 | |
ab3c759a | 7112 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7113 | reg_val &= 0x8cffffff; |
7114 | reg_val = 0x8c000000; | |
ab3c759a | 7115 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7116 | |
ab3c759a | 7117 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7118 | reg_val &= 0xffffff00; |
ab3c759a | 7119 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7120 | |
ab3c759a | 7121 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7122 | reg_val &= 0x00ffffff; |
7123 | reg_val |= 0xb0000000; | |
ab3c759a | 7124 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7125 | } |
7126 | ||
b551842d DV |
7127 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7128 | struct intel_link_m_n *m_n) | |
7129 | { | |
7130 | struct drm_device *dev = crtc->base.dev; | |
7131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7132 | int pipe = crtc->pipe; | |
7133 | ||
e3b95f1e DV |
7134 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7135 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7136 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7137 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7138 | } |
7139 | ||
7140 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7141 | struct intel_link_m_n *m_n, |
7142 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7143 | { |
7144 | struct drm_device *dev = crtc->base.dev; | |
7145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7146 | int pipe = crtc->pipe; | |
6e3c9717 | 7147 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7148 | |
7149 | if (INTEL_INFO(dev)->gen >= 5) { | |
7150 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7151 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7152 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7153 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7154 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7155 | * for gen < 8) and if DRRS is supported (to make sure the | |
7156 | * registers are not unnecessarily accessed). | |
7157 | */ | |
44395bfe | 7158 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7159 | crtc->config->has_drrs) { |
f769cd24 VK |
7160 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7161 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7162 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7163 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7164 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7165 | } | |
b551842d | 7166 | } else { |
e3b95f1e DV |
7167 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7168 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7169 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7170 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7171 | } |
7172 | } | |
7173 | ||
fe3cd48d | 7174 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7175 | { |
fe3cd48d R |
7176 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7177 | ||
7178 | if (m_n == M1_N1) { | |
7179 | dp_m_n = &crtc->config->dp_m_n; | |
7180 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7181 | } else if (m_n == M2_N2) { | |
7182 | ||
7183 | /* | |
7184 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7185 | * needs to be programmed into M1_N1. | |
7186 | */ | |
7187 | dp_m_n = &crtc->config->dp_m2_n2; | |
7188 | } else { | |
7189 | DRM_ERROR("Unsupported divider value\n"); | |
7190 | return; | |
7191 | } | |
7192 | ||
6e3c9717 ACO |
7193 | if (crtc->config->has_pch_encoder) |
7194 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7195 | else |
fe3cd48d | 7196 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7197 | } |
7198 | ||
251ac862 DV |
7199 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7200 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7201 | { |
7202 | u32 dpll, dpll_md; | |
7203 | ||
7204 | /* | |
7205 | * Enable DPIO clock input. We should never disable the reference | |
7206 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7207 | * on it. | |
7208 | */ | |
60bfe44f VS |
7209 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7210 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7211 | /* We should never disable this, set it here for state tracking */ |
7212 | if (crtc->pipe == PIPE_B) | |
7213 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7214 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7215 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7216 | |
d288f65f | 7217 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7218 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7219 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7220 | } |
7221 | ||
d288f65f | 7222 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7223 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7224 | { |
f47709a9 | 7225 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7226 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7227 | int pipe = crtc->pipe; |
bdd4b6a6 | 7228 | u32 mdiv; |
a0c4da24 | 7229 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7230 | u32 coreclk, reg_val; |
a0c4da24 | 7231 | |
a580516d | 7232 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7233 | |
d288f65f VS |
7234 | bestn = pipe_config->dpll.n; |
7235 | bestm1 = pipe_config->dpll.m1; | |
7236 | bestm2 = pipe_config->dpll.m2; | |
7237 | bestp1 = pipe_config->dpll.p1; | |
7238 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7239 | |
89b667f8 JB |
7240 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7241 | ||
7242 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7243 | if (pipe == PIPE_B) |
5e69f97f | 7244 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7245 | |
7246 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7247 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7248 | |
7249 | /* Disable target IRef on PLL */ | |
ab3c759a | 7250 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7251 | reg_val &= 0x00ffffff; |
ab3c759a | 7252 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7253 | |
7254 | /* Disable fast lock */ | |
ab3c759a | 7255 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7256 | |
7257 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7258 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7259 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7260 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7261 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7262 | |
7263 | /* | |
7264 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7265 | * but we don't support that). | |
7266 | * Note: don't use the DAC post divider as it seems unstable. | |
7267 | */ | |
7268 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7269 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7270 | |
a0c4da24 | 7271 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7272 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7273 | |
89b667f8 | 7274 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7275 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7276 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7277 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7278 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7279 | 0x009f0003); |
89b667f8 | 7280 | else |
ab3c759a | 7281 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7282 | 0x00d0000f); |
7283 | ||
681a8504 | 7284 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7285 | /* Use SSC source */ |
bdd4b6a6 | 7286 | if (pipe == PIPE_A) |
ab3c759a | 7287 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7288 | 0x0df40000); |
7289 | else | |
ab3c759a | 7290 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7291 | 0x0df70000); |
7292 | } else { /* HDMI or VGA */ | |
7293 | /* Use bend source */ | |
bdd4b6a6 | 7294 | if (pipe == PIPE_A) |
ab3c759a | 7295 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7296 | 0x0df70000); |
7297 | else | |
ab3c759a | 7298 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7299 | 0x0df40000); |
7300 | } | |
a0c4da24 | 7301 | |
ab3c759a | 7302 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7303 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7304 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7305 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7306 | coreclk |= 0x01000000; |
ab3c759a | 7307 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7308 | |
ab3c759a | 7309 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7310 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7311 | } |
7312 | ||
251ac862 DV |
7313 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7314 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7315 | { |
60bfe44f VS |
7316 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7317 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7318 | DPLL_VCO_ENABLE; |
7319 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7320 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7321 | |
d288f65f VS |
7322 | pipe_config->dpll_hw_state.dpll_md = |
7323 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7324 | } |
7325 | ||
d288f65f | 7326 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7327 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7328 | { |
7329 | struct drm_device *dev = crtc->base.dev; | |
7330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7331 | int pipe = crtc->pipe; | |
f0f59a00 | 7332 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7333 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7334 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7335 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7336 | u32 dpio_val; |
9cbe40c1 | 7337 | int vco; |
9d556c99 | 7338 | |
d288f65f VS |
7339 | bestn = pipe_config->dpll.n; |
7340 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7341 | bestm1 = pipe_config->dpll.m1; | |
7342 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7343 | bestp1 = pipe_config->dpll.p1; | |
7344 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7345 | vco = pipe_config->dpll.vco; |
a945ce7e | 7346 | dpio_val = 0; |
9cbe40c1 | 7347 | loopfilter = 0; |
9d556c99 CML |
7348 | |
7349 | /* | |
7350 | * Enable Refclk and SSC | |
7351 | */ | |
a11b0703 | 7352 | I915_WRITE(dpll_reg, |
d288f65f | 7353 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7354 | |
a580516d | 7355 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7356 | |
9d556c99 CML |
7357 | /* p1 and p2 divider */ |
7358 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7359 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7360 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7361 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7362 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7363 | ||
7364 | /* Feedback post-divider - m2 */ | |
7365 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7366 | ||
7367 | /* Feedback refclk divider - n and m1 */ | |
7368 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7369 | DPIO_CHV_M1_DIV_BY_2 | | |
7370 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7371 | ||
7372 | /* M2 fraction division */ | |
25a25dfc | 7373 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7374 | |
7375 | /* M2 fraction division enable */ | |
a945ce7e VP |
7376 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7377 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7378 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7379 | if (bestm2_frac) | |
7380 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7381 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7382 | |
de3a0fde VP |
7383 | /* Program digital lock detect threshold */ |
7384 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7385 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7386 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7387 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7388 | if (!bestm2_frac) | |
7389 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7390 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7391 | ||
9d556c99 | 7392 | /* Loop filter */ |
9cbe40c1 VP |
7393 | if (vco == 5400000) { |
7394 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7395 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7396 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7397 | tribuf_calcntr = 0x9; | |
7398 | } else if (vco <= 6200000) { | |
7399 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7400 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7401 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7402 | tribuf_calcntr = 0x9; | |
7403 | } else if (vco <= 6480000) { | |
7404 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7405 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7406 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7407 | tribuf_calcntr = 0x8; | |
7408 | } else { | |
7409 | /* Not supported. Apply the same limits as in the max case */ | |
7410 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7411 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7412 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7413 | tribuf_calcntr = 0; | |
7414 | } | |
9d556c99 CML |
7415 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7416 | ||
968040b2 | 7417 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7418 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7419 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7420 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7421 | ||
9d556c99 CML |
7422 | /* AFC Recal */ |
7423 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7424 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7425 | DPIO_AFC_RECAL); | |
7426 | ||
a580516d | 7427 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7428 | } |
7429 | ||
d288f65f VS |
7430 | /** |
7431 | * vlv_force_pll_on - forcibly enable just the PLL | |
7432 | * @dev_priv: i915 private structure | |
7433 | * @pipe: pipe PLL to enable | |
7434 | * @dpll: PLL configuration | |
7435 | * | |
7436 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7437 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7438 | * be enabled. | |
7439 | */ | |
3f36b937 TU |
7440 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7441 | const struct dpll *dpll) | |
d288f65f VS |
7442 | { |
7443 | struct intel_crtc *crtc = | |
7444 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7445 | struct intel_crtc_state *pipe_config; |
7446 | ||
7447 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7448 | if (!pipe_config) | |
7449 | return -ENOMEM; | |
7450 | ||
7451 | pipe_config->base.crtc = &crtc->base; | |
7452 | pipe_config->pixel_multiplier = 1; | |
7453 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7454 | |
7455 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7456 | chv_compute_dpll(crtc, pipe_config); |
7457 | chv_prepare_pll(crtc, pipe_config); | |
7458 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7459 | } else { |
3f36b937 TU |
7460 | vlv_compute_dpll(crtc, pipe_config); |
7461 | vlv_prepare_pll(crtc, pipe_config); | |
7462 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7463 | } |
3f36b937 TU |
7464 | |
7465 | kfree(pipe_config); | |
7466 | ||
7467 | return 0; | |
d288f65f VS |
7468 | } |
7469 | ||
7470 | /** | |
7471 | * vlv_force_pll_off - forcibly disable just the PLL | |
7472 | * @dev_priv: i915 private structure | |
7473 | * @pipe: pipe PLL to disable | |
7474 | * | |
7475 | * Disable the PLL for @pipe. To be used in cases where we need | |
7476 | * the PLL enabled even when @pipe is not going to be enabled. | |
7477 | */ | |
7478 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7479 | { | |
7480 | if (IS_CHERRYVIEW(dev)) | |
7481 | chv_disable_pll(to_i915(dev), pipe); | |
7482 | else | |
7483 | vlv_disable_pll(to_i915(dev), pipe); | |
7484 | } | |
7485 | ||
251ac862 DV |
7486 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7487 | struct intel_crtc_state *crtc_state, | |
ceb41007 | 7488 | intel_clock_t *reduced_clock) |
eb1cbe48 | 7489 | { |
f47709a9 | 7490 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7491 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7492 | u32 dpll; |
7493 | bool is_sdvo; | |
190f68c5 | 7494 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7495 | |
190f68c5 | 7496 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7497 | |
a93e255f ACO |
7498 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7499 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7500 | |
7501 | dpll = DPLL_VGA_MODE_DIS; | |
7502 | ||
a93e255f | 7503 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7504 | dpll |= DPLLB_MODE_LVDS; |
7505 | else | |
7506 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7507 | |
ef1b460d | 7508 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7509 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7510 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7511 | } |
198a037f DV |
7512 | |
7513 | if (is_sdvo) | |
4a33e48d | 7514 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7515 | |
190f68c5 | 7516 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7517 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7518 | |
7519 | /* compute bitmask from p1 value */ | |
7520 | if (IS_PINEVIEW(dev)) | |
7521 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7522 | else { | |
7523 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7524 | if (IS_G4X(dev) && reduced_clock) | |
7525 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7526 | } | |
7527 | switch (clock->p2) { | |
7528 | case 5: | |
7529 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7530 | break; | |
7531 | case 7: | |
7532 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7533 | break; | |
7534 | case 10: | |
7535 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7536 | break; | |
7537 | case 14: | |
7538 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7539 | break; | |
7540 | } | |
7541 | if (INTEL_INFO(dev)->gen >= 4) | |
7542 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7543 | ||
190f68c5 | 7544 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7545 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7546 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7547 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7548 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7549 | else | |
7550 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7551 | ||
7552 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7553 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7554 | |
eb1cbe48 | 7555 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7556 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7557 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7558 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7559 | } |
7560 | } | |
7561 | ||
251ac862 DV |
7562 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7563 | struct intel_crtc_state *crtc_state, | |
ceb41007 | 7564 | intel_clock_t *reduced_clock) |
eb1cbe48 | 7565 | { |
f47709a9 | 7566 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7567 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7568 | u32 dpll; |
190f68c5 | 7569 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7570 | |
190f68c5 | 7571 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7572 | |
eb1cbe48 DV |
7573 | dpll = DPLL_VGA_MODE_DIS; |
7574 | ||
a93e255f | 7575 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7576 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7577 | } else { | |
7578 | if (clock->p1 == 2) | |
7579 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7580 | else | |
7581 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7582 | if (clock->p2 == 4) | |
7583 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7584 | } | |
7585 | ||
a93e255f | 7586 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7587 | dpll |= DPLL_DVO_2X_MODE; |
7588 | ||
a93e255f | 7589 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7590 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7591 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7592 | else | |
7593 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7594 | ||
7595 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7596 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7597 | } |
7598 | ||
8a654f3b | 7599 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7600 | { |
7601 | struct drm_device *dev = intel_crtc->base.dev; | |
7602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7603 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7604 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7605 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7606 | uint32_t crtc_vtotal, crtc_vblank_end; |
7607 | int vsyncshift = 0; | |
4d8a62ea DV |
7608 | |
7609 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7610 | * the hw state checker will get angry at the mismatch. */ | |
7611 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7612 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7613 | |
609aeaca | 7614 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7615 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7616 | crtc_vtotal -= 1; |
7617 | crtc_vblank_end -= 1; | |
609aeaca | 7618 | |
409ee761 | 7619 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7620 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7621 | else | |
7622 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7623 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7624 | if (vsyncshift < 0) |
7625 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7626 | } |
7627 | ||
7628 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7629 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7630 | |
fe2b8f9d | 7631 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7632 | (adjusted_mode->crtc_hdisplay - 1) | |
7633 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7634 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7635 | (adjusted_mode->crtc_hblank_start - 1) | |
7636 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7637 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7638 | (adjusted_mode->crtc_hsync_start - 1) | |
7639 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7640 | ||
fe2b8f9d | 7641 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7642 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7643 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7644 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7645 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7646 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7647 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7648 | (adjusted_mode->crtc_vsync_start - 1) | |
7649 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7650 | ||
b5e508d4 PZ |
7651 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7652 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7653 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7654 | * bits. */ | |
7655 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7656 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7657 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7658 | ||
bc58be60 JN |
7659 | } |
7660 | ||
7661 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7662 | { | |
7663 | struct drm_device *dev = intel_crtc->base.dev; | |
7664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7665 | enum pipe pipe = intel_crtc->pipe; | |
7666 | ||
b0e77b9c PZ |
7667 | /* pipesrc controls the size that is scaled from, which should |
7668 | * always be the user's requested size. | |
7669 | */ | |
7670 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7671 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7672 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7673 | } |
7674 | ||
1bd1bd80 | 7675 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7676 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7677 | { |
7678 | struct drm_device *dev = crtc->base.dev; | |
7679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7680 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7681 | uint32_t tmp; | |
7682 | ||
7683 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7684 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7685 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7686 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7687 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7688 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7689 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7690 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7691 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7692 | |
7693 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7694 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7695 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7696 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7697 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7698 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7699 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7700 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7701 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7702 | |
7703 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7704 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7705 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7706 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7707 | } |
bc58be60 JN |
7708 | } |
7709 | ||
7710 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7711 | struct intel_crtc_state *pipe_config) | |
7712 | { | |
7713 | struct drm_device *dev = crtc->base.dev; | |
7714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7715 | u32 tmp; | |
1bd1bd80 DV |
7716 | |
7717 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7718 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7719 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7720 | ||
2d112de7 ACO |
7721 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7722 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7723 | } |
7724 | ||
f6a83288 | 7725 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7726 | struct intel_crtc_state *pipe_config) |
babea61d | 7727 | { |
2d112de7 ACO |
7728 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7729 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7730 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7731 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7732 | |
2d112de7 ACO |
7733 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7734 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7735 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7736 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7737 | |
2d112de7 | 7738 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7739 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7740 | |
2d112de7 ACO |
7741 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7742 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7743 | |
7744 | mode->hsync = drm_mode_hsync(mode); | |
7745 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7746 | drm_mode_set_name(mode); | |
babea61d JB |
7747 | } |
7748 | ||
84b046f3 DV |
7749 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7750 | { | |
7751 | struct drm_device *dev = intel_crtc->base.dev; | |
7752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7753 | uint32_t pipeconf; | |
7754 | ||
9f11a9e4 | 7755 | pipeconf = 0; |
84b046f3 | 7756 | |
b6b5d049 VS |
7757 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7758 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7759 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7760 | |
6e3c9717 | 7761 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7762 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7763 | |
ff9ce46e | 7764 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7765 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7766 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7767 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7768 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7769 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7770 | |
6e3c9717 | 7771 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7772 | case 18: |
7773 | pipeconf |= PIPECONF_6BPC; | |
7774 | break; | |
7775 | case 24: | |
7776 | pipeconf |= PIPECONF_8BPC; | |
7777 | break; | |
7778 | case 30: | |
7779 | pipeconf |= PIPECONF_10BPC; | |
7780 | break; | |
7781 | default: | |
7782 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7783 | BUG(); | |
84b046f3 DV |
7784 | } |
7785 | } | |
7786 | ||
7787 | if (HAS_PIPE_CXSR(dev)) { | |
7788 | if (intel_crtc->lowfreq_avail) { | |
7789 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7790 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7791 | } else { | |
7792 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7793 | } |
7794 | } | |
7795 | ||
6e3c9717 | 7796 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7797 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7798 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7799 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7800 | else | |
7801 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7802 | } else | |
84b046f3 DV |
7803 | pipeconf |= PIPECONF_PROGRESSIVE; |
7804 | ||
666a4537 WB |
7805 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7806 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7807 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7808 | |
84b046f3 DV |
7809 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7810 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7811 | } | |
7812 | ||
190f68c5 ACO |
7813 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7814 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7815 | { |
c7653199 | 7816 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7817 | struct drm_i915_private *dev_priv = dev->dev_private; |
ceb41007 | 7818 | int refclk; |
c329a4ec DV |
7819 | intel_clock_t clock; |
7820 | bool ok; | |
d4906093 | 7821 | const intel_limit_t *limit; |
79e53945 | 7822 | |
dd3cd74a ACO |
7823 | memset(&crtc_state->dpll_hw_state, 0, |
7824 | sizeof(crtc_state->dpll_hw_state)); | |
7825 | ||
a65347ba JN |
7826 | if (crtc_state->has_dsi_encoder) |
7827 | return 0; | |
43565a06 | 7828 | |
190f68c5 | 7829 | if (!crtc_state->clock_set) { |
ceb41007 | 7830 | refclk = i9xx_get_refclk(crtc_state); |
79e53945 | 7831 | |
e9fd1c02 JN |
7832 | /* |
7833 | * Returns a set of divisors for the desired target clock with | |
7834 | * the given refclk, or FALSE. The returned values represent | |
7835 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7836 | * 2) / p1 / p2. | |
7837 | */ | |
a93e255f ACO |
7838 | limit = intel_limit(crtc_state, refclk); |
7839 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7840 | crtc_state->port_clock, |
e9fd1c02 | 7841 | refclk, NULL, &clock); |
f2335330 | 7842 | if (!ok) { |
e9fd1c02 JN |
7843 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7844 | return -EINVAL; | |
7845 | } | |
79e53945 | 7846 | |
f2335330 | 7847 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7848 | crtc_state->dpll.n = clock.n; |
7849 | crtc_state->dpll.m1 = clock.m1; | |
7850 | crtc_state->dpll.m2 = clock.m2; | |
7851 | crtc_state->dpll.p1 = clock.p1; | |
7852 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7853 | } |
7026d4ac | 7854 | |
e9fd1c02 | 7855 | if (IS_GEN2(dev)) { |
ceb41007 | 7856 | i8xx_compute_dpll(crtc, crtc_state, NULL); |
9d556c99 | 7857 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7858 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7859 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7860 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7861 | } else { |
ceb41007 | 7862 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
e9fd1c02 | 7863 | } |
79e53945 | 7864 | |
c8f7a0db | 7865 | return 0; |
f564048e EA |
7866 | } |
7867 | ||
2fa2fe9a | 7868 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7869 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7870 | { |
7871 | struct drm_device *dev = crtc->base.dev; | |
7872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7873 | uint32_t tmp; | |
7874 | ||
dc9e7dec VS |
7875 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7876 | return; | |
7877 | ||
2fa2fe9a | 7878 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7879 | if (!(tmp & PFIT_ENABLE)) |
7880 | return; | |
2fa2fe9a | 7881 | |
06922821 | 7882 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7883 | if (INTEL_INFO(dev)->gen < 4) { |
7884 | if (crtc->pipe != PIPE_B) | |
7885 | return; | |
2fa2fe9a DV |
7886 | } else { |
7887 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7888 | return; | |
7889 | } | |
7890 | ||
06922821 | 7891 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7892 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7893 | if (INTEL_INFO(dev)->gen < 5) | |
7894 | pipe_config->gmch_pfit.lvds_border_bits = | |
7895 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7896 | } | |
7897 | ||
acbec814 | 7898 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7899 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7900 | { |
7901 | struct drm_device *dev = crtc->base.dev; | |
7902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7903 | int pipe = pipe_config->cpu_transcoder; | |
7904 | intel_clock_t clock; | |
7905 | u32 mdiv; | |
662c6ecb | 7906 | int refclk = 100000; |
acbec814 | 7907 | |
f573de5a SK |
7908 | /* In case of MIPI DPLL will not even be used */ |
7909 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7910 | return; | |
7911 | ||
a580516d | 7912 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7913 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7914 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7915 | |
7916 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7917 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7918 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7919 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7920 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7921 | ||
dccbea3b | 7922 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7923 | } |
7924 | ||
5724dbd1 DL |
7925 | static void |
7926 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7927 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7928 | { |
7929 | struct drm_device *dev = crtc->base.dev; | |
7930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7931 | u32 val, base, offset; | |
7932 | int pipe = crtc->pipe, plane = crtc->plane; | |
7933 | int fourcc, pixel_format; | |
6761dd31 | 7934 | unsigned int aligned_height; |
b113d5ee | 7935 | struct drm_framebuffer *fb; |
1b842c89 | 7936 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7937 | |
42a7b088 DL |
7938 | val = I915_READ(DSPCNTR(plane)); |
7939 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7940 | return; | |
7941 | ||
d9806c9f | 7942 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7943 | if (!intel_fb) { |
1ad292b5 JB |
7944 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7945 | return; | |
7946 | } | |
7947 | ||
1b842c89 DL |
7948 | fb = &intel_fb->base; |
7949 | ||
18c5247e DV |
7950 | if (INTEL_INFO(dev)->gen >= 4) { |
7951 | if (val & DISPPLANE_TILED) { | |
49af449b | 7952 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7953 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7954 | } | |
7955 | } | |
1ad292b5 JB |
7956 | |
7957 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7958 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7959 | fb->pixel_format = fourcc; |
7960 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7961 | |
7962 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7963 | if (plane_config->tiling) |
1ad292b5 JB |
7964 | offset = I915_READ(DSPTILEOFF(plane)); |
7965 | else | |
7966 | offset = I915_READ(DSPLINOFF(plane)); | |
7967 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7968 | } else { | |
7969 | base = I915_READ(DSPADDR(plane)); | |
7970 | } | |
7971 | plane_config->base = base; | |
7972 | ||
7973 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7974 | fb->width = ((val >> 16) & 0xfff) + 1; |
7975 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7976 | |
7977 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7978 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7979 | |
b113d5ee | 7980 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7981 | fb->pixel_format, |
7982 | fb->modifier[0]); | |
1ad292b5 | 7983 | |
f37b5c2b | 7984 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7985 | |
2844a921 DL |
7986 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7987 | pipe_name(pipe), plane, fb->width, fb->height, | |
7988 | fb->bits_per_pixel, base, fb->pitches[0], | |
7989 | plane_config->size); | |
1ad292b5 | 7990 | |
2d14030b | 7991 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7992 | } |
7993 | ||
70b23a98 | 7994 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7995 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7996 | { |
7997 | struct drm_device *dev = crtc->base.dev; | |
7998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7999 | int pipe = pipe_config->cpu_transcoder; | |
8000 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8001 | intel_clock_t clock; | |
0d7b6b11 | 8002 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8003 | int refclk = 100000; |
8004 | ||
a580516d | 8005 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8006 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8007 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8008 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8009 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8010 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8011 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8012 | |
8013 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8014 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8015 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8016 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8017 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8018 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8019 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8020 | ||
dccbea3b | 8021 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8022 | } |
8023 | ||
0e8ffe1b | 8024 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8025 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8026 | { |
8027 | struct drm_device *dev = crtc->base.dev; | |
8028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8029 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8030 | uint32_t tmp; |
1729050e | 8031 | bool ret; |
0e8ffe1b | 8032 | |
1729050e ID |
8033 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8034 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8035 | return false; |
8036 | ||
e143a21c | 8037 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8038 | pipe_config->shared_dpll = NULL; |
eccb140b | 8039 | |
1729050e ID |
8040 | ret = false; |
8041 | ||
0e8ffe1b DV |
8042 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8043 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8044 | goto out; |
0e8ffe1b | 8045 | |
666a4537 | 8046 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8047 | switch (tmp & PIPECONF_BPC_MASK) { |
8048 | case PIPECONF_6BPC: | |
8049 | pipe_config->pipe_bpp = 18; | |
8050 | break; | |
8051 | case PIPECONF_8BPC: | |
8052 | pipe_config->pipe_bpp = 24; | |
8053 | break; | |
8054 | case PIPECONF_10BPC: | |
8055 | pipe_config->pipe_bpp = 30; | |
8056 | break; | |
8057 | default: | |
8058 | break; | |
8059 | } | |
8060 | } | |
8061 | ||
666a4537 WB |
8062 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8063 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8064 | pipe_config->limited_color_range = true; |
8065 | ||
282740f7 VS |
8066 | if (INTEL_INFO(dev)->gen < 4) |
8067 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8068 | ||
1bd1bd80 | 8069 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8070 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8071 | |
2fa2fe9a DV |
8072 | i9xx_get_pfit_config(crtc, pipe_config); |
8073 | ||
6c49f241 DV |
8074 | if (INTEL_INFO(dev)->gen >= 4) { |
8075 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8076 | pipe_config->pixel_multiplier = | |
8077 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8078 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8079 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8080 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8081 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8082 | pipe_config->pixel_multiplier = | |
8083 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8084 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8085 | } else { | |
8086 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8087 | * port and will be fixed up in the encoder->get_config | |
8088 | * function. */ | |
8089 | pipe_config->pixel_multiplier = 1; | |
8090 | } | |
8bcc2795 | 8091 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8092 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8093 | /* |
8094 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8095 | * on 830. Filter it out here so that we don't | |
8096 | * report errors due to that. | |
8097 | */ | |
8098 | if (IS_I830(dev)) | |
8099 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8100 | ||
8bcc2795 DV |
8101 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8102 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8103 | } else { |
8104 | /* Mask out read-only status bits. */ | |
8105 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8106 | DPLL_PORTC_READY_MASK | | |
8107 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8108 | } |
6c49f241 | 8109 | |
70b23a98 VS |
8110 | if (IS_CHERRYVIEW(dev)) |
8111 | chv_crtc_clock_get(crtc, pipe_config); | |
8112 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8113 | vlv_crtc_clock_get(crtc, pipe_config); |
8114 | else | |
8115 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8116 | |
0f64614d VS |
8117 | /* |
8118 | * Normally the dotclock is filled in by the encoder .get_config() | |
8119 | * but in case the pipe is enabled w/o any ports we need a sane | |
8120 | * default. | |
8121 | */ | |
8122 | pipe_config->base.adjusted_mode.crtc_clock = | |
8123 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8124 | ||
1729050e ID |
8125 | ret = true; |
8126 | ||
8127 | out: | |
8128 | intel_display_power_put(dev_priv, power_domain); | |
8129 | ||
8130 | return ret; | |
0e8ffe1b DV |
8131 | } |
8132 | ||
dde86e2d | 8133 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8134 | { |
8135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8136 | struct intel_encoder *encoder; |
74cfd7ac | 8137 | u32 val, final; |
13d83a67 | 8138 | bool has_lvds = false; |
199e5d79 | 8139 | bool has_cpu_edp = false; |
199e5d79 | 8140 | bool has_panel = false; |
99eb6a01 KP |
8141 | bool has_ck505 = false; |
8142 | bool can_ssc = false; | |
13d83a67 JB |
8143 | |
8144 | /* We need to take the global config into account */ | |
b2784e15 | 8145 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8146 | switch (encoder->type) { |
8147 | case INTEL_OUTPUT_LVDS: | |
8148 | has_panel = true; | |
8149 | has_lvds = true; | |
8150 | break; | |
8151 | case INTEL_OUTPUT_EDP: | |
8152 | has_panel = true; | |
2de6905f | 8153 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8154 | has_cpu_edp = true; |
8155 | break; | |
6847d71b PZ |
8156 | default: |
8157 | break; | |
13d83a67 JB |
8158 | } |
8159 | } | |
8160 | ||
99eb6a01 | 8161 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8162 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8163 | can_ssc = has_ck505; |
8164 | } else { | |
8165 | has_ck505 = false; | |
8166 | can_ssc = true; | |
8167 | } | |
8168 | ||
2de6905f ID |
8169 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8170 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8171 | |
8172 | /* Ironlake: try to setup display ref clock before DPLL | |
8173 | * enabling. This is only under driver's control after | |
8174 | * PCH B stepping, previous chipset stepping should be | |
8175 | * ignoring this setting. | |
8176 | */ | |
74cfd7ac CW |
8177 | val = I915_READ(PCH_DREF_CONTROL); |
8178 | ||
8179 | /* As we must carefully and slowly disable/enable each source in turn, | |
8180 | * compute the final state we want first and check if we need to | |
8181 | * make any changes at all. | |
8182 | */ | |
8183 | final = val; | |
8184 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8185 | if (has_ck505) | |
8186 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8187 | else | |
8188 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8189 | ||
8190 | final &= ~DREF_SSC_SOURCE_MASK; | |
8191 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8192 | final &= ~DREF_SSC1_ENABLE; | |
8193 | ||
8194 | if (has_panel) { | |
8195 | final |= DREF_SSC_SOURCE_ENABLE; | |
8196 | ||
8197 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8198 | final |= DREF_SSC1_ENABLE; | |
8199 | ||
8200 | if (has_cpu_edp) { | |
8201 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8202 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8203 | else | |
8204 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8205 | } else | |
8206 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8207 | } else { | |
8208 | final |= DREF_SSC_SOURCE_DISABLE; | |
8209 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8210 | } | |
8211 | ||
8212 | if (final == val) | |
8213 | return; | |
8214 | ||
13d83a67 | 8215 | /* Always enable nonspread source */ |
74cfd7ac | 8216 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8217 | |
99eb6a01 | 8218 | if (has_ck505) |
74cfd7ac | 8219 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8220 | else |
74cfd7ac | 8221 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8222 | |
199e5d79 | 8223 | if (has_panel) { |
74cfd7ac CW |
8224 | val &= ~DREF_SSC_SOURCE_MASK; |
8225 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8226 | |
199e5d79 | 8227 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8228 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8229 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8230 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8231 | } else |
74cfd7ac | 8232 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8233 | |
8234 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8235 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8236 | POSTING_READ(PCH_DREF_CONTROL); |
8237 | udelay(200); | |
8238 | ||
74cfd7ac | 8239 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8240 | |
8241 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8242 | if (has_cpu_edp) { |
99eb6a01 | 8243 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8244 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8245 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8246 | } else |
74cfd7ac | 8247 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8248 | } else |
74cfd7ac | 8249 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8250 | |
74cfd7ac | 8251 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8252 | POSTING_READ(PCH_DREF_CONTROL); |
8253 | udelay(200); | |
8254 | } else { | |
8255 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8256 | ||
74cfd7ac | 8257 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8258 | |
8259 | /* Turn off CPU output */ | |
74cfd7ac | 8260 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8261 | |
74cfd7ac | 8262 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8263 | POSTING_READ(PCH_DREF_CONTROL); |
8264 | udelay(200); | |
8265 | ||
8266 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8267 | val &= ~DREF_SSC_SOURCE_MASK; |
8268 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8269 | |
8270 | /* Turn off SSC1 */ | |
74cfd7ac | 8271 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8272 | |
74cfd7ac | 8273 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8274 | POSTING_READ(PCH_DREF_CONTROL); |
8275 | udelay(200); | |
8276 | } | |
74cfd7ac CW |
8277 | |
8278 | BUG_ON(val != final); | |
13d83a67 JB |
8279 | } |
8280 | ||
f31f2d55 | 8281 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8282 | { |
f31f2d55 | 8283 | uint32_t tmp; |
dde86e2d | 8284 | |
0ff066a9 PZ |
8285 | tmp = I915_READ(SOUTH_CHICKEN2); |
8286 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8287 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8288 | |
0ff066a9 PZ |
8289 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8290 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8291 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8292 | |
0ff066a9 PZ |
8293 | tmp = I915_READ(SOUTH_CHICKEN2); |
8294 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8295 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8296 | |
0ff066a9 PZ |
8297 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8298 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8299 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8300 | } |
8301 | ||
8302 | /* WaMPhyProgramming:hsw */ | |
8303 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8304 | { | |
8305 | uint32_t tmp; | |
dde86e2d PZ |
8306 | |
8307 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8308 | tmp &= ~(0xFF << 24); | |
8309 | tmp |= (0x12 << 24); | |
8310 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8311 | ||
dde86e2d PZ |
8312 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8313 | tmp |= (1 << 11); | |
8314 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8315 | ||
8316 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8317 | tmp |= (1 << 11); | |
8318 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8319 | ||
dde86e2d PZ |
8320 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8321 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8322 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8323 | ||
8324 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8325 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8326 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8327 | ||
0ff066a9 PZ |
8328 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8329 | tmp &= ~(7 << 13); | |
8330 | tmp |= (5 << 13); | |
8331 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8332 | |
0ff066a9 PZ |
8333 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8334 | tmp &= ~(7 << 13); | |
8335 | tmp |= (5 << 13); | |
8336 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8337 | |
8338 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8339 | tmp &= ~0xFF; | |
8340 | tmp |= 0x1C; | |
8341 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8342 | ||
8343 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8344 | tmp &= ~0xFF; | |
8345 | tmp |= 0x1C; | |
8346 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8347 | ||
8348 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8349 | tmp &= ~(0xFF << 16); | |
8350 | tmp |= (0x1C << 16); | |
8351 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8352 | ||
8353 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8354 | tmp &= ~(0xFF << 16); | |
8355 | tmp |= (0x1C << 16); | |
8356 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8357 | ||
0ff066a9 PZ |
8358 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8359 | tmp |= (1 << 27); | |
8360 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8361 | |
0ff066a9 PZ |
8362 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8363 | tmp |= (1 << 27); | |
8364 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8365 | |
0ff066a9 PZ |
8366 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8367 | tmp &= ~(0xF << 28); | |
8368 | tmp |= (4 << 28); | |
8369 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8370 | |
0ff066a9 PZ |
8371 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8372 | tmp &= ~(0xF << 28); | |
8373 | tmp |= (4 << 28); | |
8374 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8375 | } |
8376 | ||
2fa86a1f PZ |
8377 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8378 | * Programming" based on the parameters passed: | |
8379 | * - Sequence to enable CLKOUT_DP | |
8380 | * - Sequence to enable CLKOUT_DP without spread | |
8381 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8382 | */ | |
8383 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8384 | bool with_fdi) | |
f31f2d55 PZ |
8385 | { |
8386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8387 | uint32_t reg, tmp; |
8388 | ||
8389 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8390 | with_spread = true; | |
c2699524 | 8391 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8392 | with_fdi = false; |
f31f2d55 | 8393 | |
a580516d | 8394 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8395 | |
8396 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8397 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8398 | tmp |= SBI_SSCCTL_PATHALT; | |
8399 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8400 | ||
8401 | udelay(24); | |
8402 | ||
2fa86a1f PZ |
8403 | if (with_spread) { |
8404 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8405 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8406 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8407 | |
2fa86a1f PZ |
8408 | if (with_fdi) { |
8409 | lpt_reset_fdi_mphy(dev_priv); | |
8410 | lpt_program_fdi_mphy(dev_priv); | |
8411 | } | |
8412 | } | |
dde86e2d | 8413 | |
c2699524 | 8414 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8415 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8416 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8417 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8418 | |
a580516d | 8419 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8420 | } |
8421 | ||
47701c3b PZ |
8422 | /* Sequence to disable CLKOUT_DP */ |
8423 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8424 | { | |
8425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8426 | uint32_t reg, tmp; | |
8427 | ||
a580516d | 8428 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8429 | |
c2699524 | 8430 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8431 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8432 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8433 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8434 | ||
8435 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8436 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8437 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8438 | tmp |= SBI_SSCCTL_PATHALT; | |
8439 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8440 | udelay(32); | |
8441 | } | |
8442 | tmp |= SBI_SSCCTL_DISABLE; | |
8443 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8444 | } | |
8445 | ||
a580516d | 8446 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8447 | } |
8448 | ||
f7be2c21 VS |
8449 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8450 | ||
8451 | static const uint16_t sscdivintphase[] = { | |
8452 | [BEND_IDX( 50)] = 0x3B23, | |
8453 | [BEND_IDX( 45)] = 0x3B23, | |
8454 | [BEND_IDX( 40)] = 0x3C23, | |
8455 | [BEND_IDX( 35)] = 0x3C23, | |
8456 | [BEND_IDX( 30)] = 0x3D23, | |
8457 | [BEND_IDX( 25)] = 0x3D23, | |
8458 | [BEND_IDX( 20)] = 0x3E23, | |
8459 | [BEND_IDX( 15)] = 0x3E23, | |
8460 | [BEND_IDX( 10)] = 0x3F23, | |
8461 | [BEND_IDX( 5)] = 0x3F23, | |
8462 | [BEND_IDX( 0)] = 0x0025, | |
8463 | [BEND_IDX( -5)] = 0x0025, | |
8464 | [BEND_IDX(-10)] = 0x0125, | |
8465 | [BEND_IDX(-15)] = 0x0125, | |
8466 | [BEND_IDX(-20)] = 0x0225, | |
8467 | [BEND_IDX(-25)] = 0x0225, | |
8468 | [BEND_IDX(-30)] = 0x0325, | |
8469 | [BEND_IDX(-35)] = 0x0325, | |
8470 | [BEND_IDX(-40)] = 0x0425, | |
8471 | [BEND_IDX(-45)] = 0x0425, | |
8472 | [BEND_IDX(-50)] = 0x0525, | |
8473 | }; | |
8474 | ||
8475 | /* | |
8476 | * Bend CLKOUT_DP | |
8477 | * steps -50 to 50 inclusive, in steps of 5 | |
8478 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8479 | * change in clock period = -(steps / 10) * 5.787 ps | |
8480 | */ | |
8481 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8482 | { | |
8483 | uint32_t tmp; | |
8484 | int idx = BEND_IDX(steps); | |
8485 | ||
8486 | if (WARN_ON(steps % 5 != 0)) | |
8487 | return; | |
8488 | ||
8489 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8490 | return; | |
8491 | ||
8492 | mutex_lock(&dev_priv->sb_lock); | |
8493 | ||
8494 | if (steps % 10 != 0) | |
8495 | tmp = 0xAAAAAAAB; | |
8496 | else | |
8497 | tmp = 0x00000000; | |
8498 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8499 | ||
8500 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8501 | tmp &= 0xffff0000; | |
8502 | tmp |= sscdivintphase[idx]; | |
8503 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8504 | ||
8505 | mutex_unlock(&dev_priv->sb_lock); | |
8506 | } | |
8507 | ||
8508 | #undef BEND_IDX | |
8509 | ||
bf8fa3d3 PZ |
8510 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8511 | { | |
bf8fa3d3 PZ |
8512 | struct intel_encoder *encoder; |
8513 | bool has_vga = false; | |
8514 | ||
b2784e15 | 8515 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8516 | switch (encoder->type) { |
8517 | case INTEL_OUTPUT_ANALOG: | |
8518 | has_vga = true; | |
8519 | break; | |
6847d71b PZ |
8520 | default: |
8521 | break; | |
bf8fa3d3 PZ |
8522 | } |
8523 | } | |
8524 | ||
f7be2c21 VS |
8525 | if (has_vga) { |
8526 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8527 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8528 | } else { |
47701c3b | 8529 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8530 | } |
bf8fa3d3 PZ |
8531 | } |
8532 | ||
dde86e2d PZ |
8533 | /* |
8534 | * Initialize reference clocks when the driver loads | |
8535 | */ | |
8536 | void intel_init_pch_refclk(struct drm_device *dev) | |
8537 | { | |
8538 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8539 | ironlake_init_pch_refclk(dev); | |
8540 | else if (HAS_PCH_LPT(dev)) | |
8541 | lpt_init_pch_refclk(dev); | |
8542 | } | |
8543 | ||
6ff93609 | 8544 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8545 | { |
c8203565 | 8546 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8548 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8549 | uint32_t val; |
8550 | ||
78114071 | 8551 | val = 0; |
c8203565 | 8552 | |
6e3c9717 | 8553 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8554 | case 18: |
dfd07d72 | 8555 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8556 | break; |
8557 | case 24: | |
dfd07d72 | 8558 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8559 | break; |
8560 | case 30: | |
dfd07d72 | 8561 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8562 | break; |
8563 | case 36: | |
dfd07d72 | 8564 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8565 | break; |
8566 | default: | |
cc769b62 PZ |
8567 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8568 | BUG(); | |
c8203565 PZ |
8569 | } |
8570 | ||
6e3c9717 | 8571 | if (intel_crtc->config->dither) |
c8203565 PZ |
8572 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8573 | ||
6e3c9717 | 8574 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8575 | val |= PIPECONF_INTERLACED_ILK; |
8576 | else | |
8577 | val |= PIPECONF_PROGRESSIVE; | |
8578 | ||
6e3c9717 | 8579 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8580 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8581 | |
c8203565 PZ |
8582 | I915_WRITE(PIPECONF(pipe), val); |
8583 | POSTING_READ(PIPECONF(pipe)); | |
8584 | } | |
8585 | ||
6ff93609 | 8586 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8587 | { |
391bf048 | 8588 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8589 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8590 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8591 | u32 val = 0; |
ee2b0b38 | 8592 | |
391bf048 | 8593 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8594 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8595 | ||
6e3c9717 | 8596 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8597 | val |= PIPECONF_INTERLACED_ILK; |
8598 | else | |
8599 | val |= PIPECONF_PROGRESSIVE; | |
8600 | ||
702e7a56 PZ |
8601 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8602 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8603 | } |
8604 | ||
391bf048 JN |
8605 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8606 | { | |
8607 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8608 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8609 | |
391bf048 JN |
8610 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8611 | u32 val = 0; | |
756f85cf | 8612 | |
6e3c9717 | 8613 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8614 | case 18: |
8615 | val |= PIPEMISC_DITHER_6_BPC; | |
8616 | break; | |
8617 | case 24: | |
8618 | val |= PIPEMISC_DITHER_8_BPC; | |
8619 | break; | |
8620 | case 30: | |
8621 | val |= PIPEMISC_DITHER_10_BPC; | |
8622 | break; | |
8623 | case 36: | |
8624 | val |= PIPEMISC_DITHER_12_BPC; | |
8625 | break; | |
8626 | default: | |
8627 | /* Case prevented by pipe_config_set_bpp. */ | |
8628 | BUG(); | |
8629 | } | |
8630 | ||
6e3c9717 | 8631 | if (intel_crtc->config->dither) |
756f85cf PZ |
8632 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8633 | ||
391bf048 | 8634 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8635 | } |
ee2b0b38 PZ |
8636 | } |
8637 | ||
6591c6e4 | 8638 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8639 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8640 | intel_clock_t *clock, |
8641 | bool *has_reduced_clock, | |
8642 | intel_clock_t *reduced_clock) | |
8643 | { | |
8644 | struct drm_device *dev = crtc->dev; | |
8645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8646 | int refclk; |
d4906093 | 8647 | const intel_limit_t *limit; |
c329a4ec | 8648 | bool ret; |
79e53945 | 8649 | |
8f0d5b9b ACO |
8650 | refclk = 120000; |
8651 | ||
8652 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
8653 | if (intel_panel_use_ssc(dev_priv)) { | |
8654 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8655 | dev_priv->vbt.lvds_ssc_freq); | |
8656 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8657 | } | |
8658 | ||
8659 | if (intel_is_dual_link_lvds(dev)) { | |
8660 | if (refclk == 100000) | |
8661 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8662 | else | |
8663 | limit = &intel_limits_ironlake_dual_lvds; | |
8664 | } else { | |
8665 | if (refclk == 100000) | |
8666 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8667 | else | |
8668 | limit = &intel_limits_ironlake_single_lvds; | |
8669 | } | |
26ce6d59 | 8670 | } else { |
8f0d5b9b | 8671 | limit = &intel_limits_ironlake_dac; |
26ce6d59 | 8672 | } |
79e53945 | 8673 | |
d4906093 ML |
8674 | /* |
8675 | * Returns a set of divisors for the desired target clock with the given | |
8676 | * refclk, or FALSE. The returned values represent the clock equation: | |
8677 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8678 | */ | |
2d7feacc ACO |
8679 | ret = g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8680 | refclk, NULL, clock); | |
6591c6e4 PZ |
8681 | if (!ret) |
8682 | return false; | |
cda4b7d3 | 8683 | |
6591c6e4 PZ |
8684 | return true; |
8685 | } | |
8686 | ||
d4b1931c PZ |
8687 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8688 | { | |
8689 | /* | |
8690 | * Account for spread spectrum to avoid | |
8691 | * oversubscribing the link. Max center spread | |
8692 | * is 2.5%; use 5% for safety's sake. | |
8693 | */ | |
8694 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8695 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8696 | } |
8697 | ||
7429e9d4 | 8698 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8699 | { |
7429e9d4 | 8700 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8701 | } |
8702 | ||
de13a2e3 | 8703 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8704 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8705 | u32 *fp, |
9a7c7890 | 8706 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8707 | { |
de13a2e3 | 8708 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8709 | struct drm_device *dev = crtc->dev; |
8710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8711 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8712 | struct drm_connector *connector; |
55bb9992 ACO |
8713 | struct drm_connector_state *connector_state; |
8714 | struct intel_encoder *encoder; | |
de13a2e3 | 8715 | uint32_t dpll; |
ceb41007 | 8716 | int factor, i; |
09ede541 | 8717 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8718 | |
da3ced29 | 8719 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8720 | if (connector_state->crtc != crtc_state->base.crtc) |
8721 | continue; | |
8722 | ||
8723 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8724 | ||
8725 | switch (encoder->type) { | |
79e53945 JB |
8726 | case INTEL_OUTPUT_LVDS: |
8727 | is_lvds = true; | |
8728 | break; | |
8729 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8730 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8731 | is_sdvo = true; |
79e53945 | 8732 | break; |
6847d71b PZ |
8733 | default: |
8734 | break; | |
79e53945 JB |
8735 | } |
8736 | } | |
79e53945 | 8737 | |
c1858123 | 8738 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8739 | factor = 21; |
8740 | if (is_lvds) { | |
8741 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8742 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8743 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8744 | factor = 25; |
190f68c5 | 8745 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8746 | factor = 20; |
c1858123 | 8747 | |
190f68c5 | 8748 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8749 | *fp |= FP_CB_TUNE; |
2c07245f | 8750 | |
9a7c7890 DV |
8751 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8752 | *fp2 |= FP_CB_TUNE; | |
8753 | ||
5eddb70b | 8754 | dpll = 0; |
2c07245f | 8755 | |
a07d6787 EA |
8756 | if (is_lvds) |
8757 | dpll |= DPLLB_MODE_LVDS; | |
8758 | else | |
8759 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8760 | |
190f68c5 | 8761 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8762 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8763 | |
8764 | if (is_sdvo) | |
4a33e48d | 8765 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8766 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8767 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8768 | |
a07d6787 | 8769 | /* compute bitmask from p1 value */ |
190f68c5 | 8770 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8771 | /* also FPA1 */ |
190f68c5 | 8772 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8773 | |
190f68c5 | 8774 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8775 | case 5: |
8776 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8777 | break; | |
8778 | case 7: | |
8779 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8780 | break; | |
8781 | case 10: | |
8782 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8783 | break; | |
8784 | case 14: | |
8785 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8786 | break; | |
79e53945 JB |
8787 | } |
8788 | ||
ceb41007 | 8789 | if (is_lvds && intel_panel_use_ssc(dev_priv)) |
43565a06 | 8790 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8791 | else |
8792 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8793 | ||
959e16d6 | 8794 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8795 | } |
8796 | ||
190f68c5 ACO |
8797 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8798 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8799 | { |
de13a2e3 | 8800 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8801 | u32 dpll = 0, fp = 0, fp2 = 0; |
7ed9f894 | 8802 | bool has_reduced_clock = false; |
e2b78267 | 8803 | struct intel_shared_dpll *pll; |
de13a2e3 | 8804 | |
dd3cd74a ACO |
8805 | memset(&crtc_state->dpll_hw_state, 0, |
8806 | sizeof(crtc_state->dpll_hw_state)); | |
8807 | ||
ded220e2 ACO |
8808 | crtc->lowfreq_avail = false; |
8809 | ||
8810 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8811 | if (!crtc_state->has_pch_encoder) | |
8812 | return 0; | |
79e53945 | 8813 | |
190f68c5 | 8814 | if (!crtc_state->clock_set) { |
7ed9f894 ACO |
8815 | if (!ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
8816 | &has_reduced_clock, | |
8817 | &reduced_clock)) { | |
8818 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8819 | return -EINVAL; | |
8820 | } | |
8821 | ||
8822 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
8823 | crtc_state->dpll.n = clock.n; |
8824 | crtc_state->dpll.m1 = clock.m1; | |
8825 | crtc_state->dpll.m2 = clock.m2; | |
8826 | crtc_state->dpll.p1 = clock.p1; | |
8827 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8828 | } |
79e53945 | 8829 | |
ded220e2 ACO |
8830 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8831 | if (has_reduced_clock) | |
8832 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); | |
8833 | else | |
8834 | fp2 = fp; | |
cbbab5bd | 8835 | |
ded220e2 ACO |
8836 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
8837 | &fp, &reduced_clock, | |
8838 | has_reduced_clock ? &fp2 : NULL); | |
cbbab5bd | 8839 | |
ded220e2 ACO |
8840 | crtc_state->dpll_hw_state.dpll = dpll; |
8841 | crtc_state->dpll_hw_state.fp0 = fp; | |
8842 | crtc_state->dpll_hw_state.fp1 = fp2; | |
66e985c0 | 8843 | |
ded220e2 ACO |
8844 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8845 | if (pll == NULL) { | |
8846 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8847 | pipe_name(crtc->pipe)); | |
8848 | return -EINVAL; | |
3fb37703 | 8849 | } |
79e53945 | 8850 | |
ded220e2 ACO |
8851 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8852 | has_reduced_clock) | |
c7653199 | 8853 | crtc->lowfreq_avail = true; |
e2b78267 | 8854 | |
c8f7a0db | 8855 | return 0; |
79e53945 JB |
8856 | } |
8857 | ||
eb14cb74 VS |
8858 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8859 | struct intel_link_m_n *m_n) | |
8860 | { | |
8861 | struct drm_device *dev = crtc->base.dev; | |
8862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8863 | enum pipe pipe = crtc->pipe; | |
8864 | ||
8865 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8866 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8867 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8868 | & ~TU_SIZE_MASK; | |
8869 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8870 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8871 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8872 | } | |
8873 | ||
8874 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8875 | enum transcoder transcoder, | |
b95af8be VK |
8876 | struct intel_link_m_n *m_n, |
8877 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8878 | { |
8879 | struct drm_device *dev = crtc->base.dev; | |
8880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8881 | enum pipe pipe = crtc->pipe; |
72419203 | 8882 | |
eb14cb74 VS |
8883 | if (INTEL_INFO(dev)->gen >= 5) { |
8884 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8885 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8886 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8887 | & ~TU_SIZE_MASK; | |
8888 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8889 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8890 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8891 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8892 | * gen < 8) and if DRRS is supported (to make sure the | |
8893 | * registers are not unnecessarily read). | |
8894 | */ | |
8895 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8896 | crtc->config->has_drrs) { |
b95af8be VK |
8897 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8898 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8899 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8900 | & ~TU_SIZE_MASK; | |
8901 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8902 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8903 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8904 | } | |
eb14cb74 VS |
8905 | } else { |
8906 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8907 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8908 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8909 | & ~TU_SIZE_MASK; | |
8910 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8911 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8912 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8913 | } | |
8914 | } | |
8915 | ||
8916 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8917 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8918 | { |
681a8504 | 8919 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8920 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8921 | else | |
8922 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8923 | &pipe_config->dp_m_n, |
8924 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8925 | } |
72419203 | 8926 | |
eb14cb74 | 8927 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8928 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8929 | { |
8930 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8931 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8932 | } |
8933 | ||
bd2e244f | 8934 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8935 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8936 | { |
8937 | struct drm_device *dev = crtc->base.dev; | |
8938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8939 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8940 | uint32_t ps_ctrl = 0; | |
8941 | int id = -1; | |
8942 | int i; | |
bd2e244f | 8943 | |
a1b2278e CK |
8944 | /* find scaler attached to this pipe */ |
8945 | for (i = 0; i < crtc->num_scalers; i++) { | |
8946 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8947 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8948 | id = i; | |
8949 | pipe_config->pch_pfit.enabled = true; | |
8950 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8951 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8952 | break; | |
8953 | } | |
8954 | } | |
bd2e244f | 8955 | |
a1b2278e CK |
8956 | scaler_state->scaler_id = id; |
8957 | if (id >= 0) { | |
8958 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8959 | } else { | |
8960 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8961 | } |
8962 | } | |
8963 | ||
5724dbd1 DL |
8964 | static void |
8965 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8966 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8967 | { |
8968 | struct drm_device *dev = crtc->base.dev; | |
8969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8970 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8971 | int pipe = crtc->pipe; |
8972 | int fourcc, pixel_format; | |
6761dd31 | 8973 | unsigned int aligned_height; |
bc8d7dff | 8974 | struct drm_framebuffer *fb; |
1b842c89 | 8975 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8976 | |
d9806c9f | 8977 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8978 | if (!intel_fb) { |
bc8d7dff DL |
8979 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8980 | return; | |
8981 | } | |
8982 | ||
1b842c89 DL |
8983 | fb = &intel_fb->base; |
8984 | ||
bc8d7dff | 8985 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8986 | if (!(val & PLANE_CTL_ENABLE)) |
8987 | goto error; | |
8988 | ||
bc8d7dff DL |
8989 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8990 | fourcc = skl_format_to_fourcc(pixel_format, | |
8991 | val & PLANE_CTL_ORDER_RGBX, | |
8992 | val & PLANE_CTL_ALPHA_MASK); | |
8993 | fb->pixel_format = fourcc; | |
8994 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8995 | ||
40f46283 DL |
8996 | tiling = val & PLANE_CTL_TILED_MASK; |
8997 | switch (tiling) { | |
8998 | case PLANE_CTL_TILED_LINEAR: | |
8999 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9000 | break; | |
9001 | case PLANE_CTL_TILED_X: | |
9002 | plane_config->tiling = I915_TILING_X; | |
9003 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9004 | break; | |
9005 | case PLANE_CTL_TILED_Y: | |
9006 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9007 | break; | |
9008 | case PLANE_CTL_TILED_YF: | |
9009 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9010 | break; | |
9011 | default: | |
9012 | MISSING_CASE(tiling); | |
9013 | goto error; | |
9014 | } | |
9015 | ||
bc8d7dff DL |
9016 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9017 | plane_config->base = base; | |
9018 | ||
9019 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9020 | ||
9021 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9022 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9023 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9024 | ||
9025 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9026 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9027 | fb->pixel_format); |
bc8d7dff DL |
9028 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9029 | ||
9030 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9031 | fb->pixel_format, |
9032 | fb->modifier[0]); | |
bc8d7dff | 9033 | |
f37b5c2b | 9034 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9035 | |
9036 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9037 | pipe_name(pipe), fb->width, fb->height, | |
9038 | fb->bits_per_pixel, base, fb->pitches[0], | |
9039 | plane_config->size); | |
9040 | ||
2d14030b | 9041 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9042 | return; |
9043 | ||
9044 | error: | |
9045 | kfree(fb); | |
9046 | } | |
9047 | ||
2fa2fe9a | 9048 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9049 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9050 | { |
9051 | struct drm_device *dev = crtc->base.dev; | |
9052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9053 | uint32_t tmp; | |
9054 | ||
9055 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9056 | ||
9057 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9058 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9059 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9060 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9061 | |
9062 | /* We currently do not free assignements of panel fitters on | |
9063 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9064 | * differentiates them) so just WARN about this case for now. */ | |
9065 | if (IS_GEN7(dev)) { | |
9066 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9067 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9068 | } | |
2fa2fe9a | 9069 | } |
79e53945 JB |
9070 | } |
9071 | ||
5724dbd1 DL |
9072 | static void |
9073 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9074 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9075 | { |
9076 | struct drm_device *dev = crtc->base.dev; | |
9077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9078 | u32 val, base, offset; | |
aeee5a49 | 9079 | int pipe = crtc->pipe; |
4c6baa59 | 9080 | int fourcc, pixel_format; |
6761dd31 | 9081 | unsigned int aligned_height; |
b113d5ee | 9082 | struct drm_framebuffer *fb; |
1b842c89 | 9083 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9084 | |
42a7b088 DL |
9085 | val = I915_READ(DSPCNTR(pipe)); |
9086 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9087 | return; | |
9088 | ||
d9806c9f | 9089 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9090 | if (!intel_fb) { |
4c6baa59 JB |
9091 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9092 | return; | |
9093 | } | |
9094 | ||
1b842c89 DL |
9095 | fb = &intel_fb->base; |
9096 | ||
18c5247e DV |
9097 | if (INTEL_INFO(dev)->gen >= 4) { |
9098 | if (val & DISPPLANE_TILED) { | |
49af449b | 9099 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9100 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9101 | } | |
9102 | } | |
4c6baa59 JB |
9103 | |
9104 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9105 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9106 | fb->pixel_format = fourcc; |
9107 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9108 | |
aeee5a49 | 9109 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9110 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9111 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9112 | } else { |
49af449b | 9113 | if (plane_config->tiling) |
aeee5a49 | 9114 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9115 | else |
aeee5a49 | 9116 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9117 | } |
9118 | plane_config->base = base; | |
9119 | ||
9120 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9121 | fb->width = ((val >> 16) & 0xfff) + 1; |
9122 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9123 | |
9124 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9125 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9126 | |
b113d5ee | 9127 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9128 | fb->pixel_format, |
9129 | fb->modifier[0]); | |
4c6baa59 | 9130 | |
f37b5c2b | 9131 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9132 | |
2844a921 DL |
9133 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9134 | pipe_name(pipe), fb->width, fb->height, | |
9135 | fb->bits_per_pixel, base, fb->pitches[0], | |
9136 | plane_config->size); | |
b113d5ee | 9137 | |
2d14030b | 9138 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9139 | } |
9140 | ||
0e8ffe1b | 9141 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9142 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9143 | { |
9144 | struct drm_device *dev = crtc->base.dev; | |
9145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9146 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9147 | uint32_t tmp; |
1729050e | 9148 | bool ret; |
0e8ffe1b | 9149 | |
1729050e ID |
9150 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9151 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9152 | return false; |
9153 | ||
e143a21c | 9154 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9155 | pipe_config->shared_dpll = NULL; |
eccb140b | 9156 | |
1729050e | 9157 | ret = false; |
0e8ffe1b DV |
9158 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9159 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9160 | goto out; |
0e8ffe1b | 9161 | |
42571aef VS |
9162 | switch (tmp & PIPECONF_BPC_MASK) { |
9163 | case PIPECONF_6BPC: | |
9164 | pipe_config->pipe_bpp = 18; | |
9165 | break; | |
9166 | case PIPECONF_8BPC: | |
9167 | pipe_config->pipe_bpp = 24; | |
9168 | break; | |
9169 | case PIPECONF_10BPC: | |
9170 | pipe_config->pipe_bpp = 30; | |
9171 | break; | |
9172 | case PIPECONF_12BPC: | |
9173 | pipe_config->pipe_bpp = 36; | |
9174 | break; | |
9175 | default: | |
9176 | break; | |
9177 | } | |
9178 | ||
b5a9fa09 DV |
9179 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9180 | pipe_config->limited_color_range = true; | |
9181 | ||
ab9412ba | 9182 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9183 | struct intel_shared_dpll *pll; |
8106ddbd | 9184 | enum intel_dpll_id pll_id; |
66e985c0 | 9185 | |
88adfff1 DV |
9186 | pipe_config->has_pch_encoder = true; |
9187 | ||
627eb5a3 DV |
9188 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9189 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9190 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9191 | |
9192 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9193 | |
c0d43d62 | 9194 | if (HAS_PCH_IBX(dev_priv->dev)) { |
8106ddbd | 9195 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9196 | } else { |
9197 | tmp = I915_READ(PCH_DPLL_SEL); | |
9198 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9199 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9200 | else |
8106ddbd | 9201 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9202 | } |
66e985c0 | 9203 | |
8106ddbd ACO |
9204 | pipe_config->shared_dpll = |
9205 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9206 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9207 | |
2edd6443 ACO |
9208 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9209 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9210 | |
9211 | tmp = pipe_config->dpll_hw_state.dpll; | |
9212 | pipe_config->pixel_multiplier = | |
9213 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9214 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9215 | |
9216 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9217 | } else { |
9218 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9219 | } |
9220 | ||
1bd1bd80 | 9221 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9222 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9223 | |
2fa2fe9a DV |
9224 | ironlake_get_pfit_config(crtc, pipe_config); |
9225 | ||
1729050e ID |
9226 | ret = true; |
9227 | ||
9228 | out: | |
9229 | intel_display_power_put(dev_priv, power_domain); | |
9230 | ||
9231 | return ret; | |
0e8ffe1b DV |
9232 | } |
9233 | ||
be256dc7 PZ |
9234 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9235 | { | |
9236 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9237 | struct intel_crtc *crtc; |
be256dc7 | 9238 | |
d3fcc808 | 9239 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9240 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9241 | pipe_name(crtc->pipe)); |
9242 | ||
e2c719b7 RC |
9243 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9244 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9245 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9246 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9247 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9248 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9249 | "CPU PWM1 enabled\n"); |
c5107b87 | 9250 | if (IS_HASWELL(dev)) |
e2c719b7 | 9251 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9252 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9253 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9254 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9255 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9256 | "Utility pin enabled\n"); |
e2c719b7 | 9257 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9258 | |
9926ada1 PZ |
9259 | /* |
9260 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9261 | * interrupts remain enabled. We used to check for that, but since it's | |
9262 | * gen-specific and since we only disable LCPLL after we fully disable | |
9263 | * the interrupts, the check below should be enough. | |
9264 | */ | |
e2c719b7 | 9265 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9266 | } |
9267 | ||
9ccd5aeb PZ |
9268 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9269 | { | |
9270 | struct drm_device *dev = dev_priv->dev; | |
9271 | ||
9272 | if (IS_HASWELL(dev)) | |
9273 | return I915_READ(D_COMP_HSW); | |
9274 | else | |
9275 | return I915_READ(D_COMP_BDW); | |
9276 | } | |
9277 | ||
3c4c9b81 PZ |
9278 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9279 | { | |
9280 | struct drm_device *dev = dev_priv->dev; | |
9281 | ||
9282 | if (IS_HASWELL(dev)) { | |
9283 | mutex_lock(&dev_priv->rps.hw_lock); | |
9284 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9285 | val)) | |
f475dadf | 9286 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9287 | mutex_unlock(&dev_priv->rps.hw_lock); |
9288 | } else { | |
9ccd5aeb PZ |
9289 | I915_WRITE(D_COMP_BDW, val); |
9290 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9291 | } |
be256dc7 PZ |
9292 | } |
9293 | ||
9294 | /* | |
9295 | * This function implements pieces of two sequences from BSpec: | |
9296 | * - Sequence for display software to disable LCPLL | |
9297 | * - Sequence for display software to allow package C8+ | |
9298 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9299 | * register. Callers should take care of disabling all the display engine | |
9300 | * functions, doing the mode unset, fixing interrupts, etc. | |
9301 | */ | |
6ff58d53 PZ |
9302 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9303 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9304 | { |
9305 | uint32_t val; | |
9306 | ||
9307 | assert_can_disable_lcpll(dev_priv); | |
9308 | ||
9309 | val = I915_READ(LCPLL_CTL); | |
9310 | ||
9311 | if (switch_to_fclk) { | |
9312 | val |= LCPLL_CD_SOURCE_FCLK; | |
9313 | I915_WRITE(LCPLL_CTL, val); | |
9314 | ||
9315 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9316 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9317 | DRM_ERROR("Switching to FCLK failed\n"); | |
9318 | ||
9319 | val = I915_READ(LCPLL_CTL); | |
9320 | } | |
9321 | ||
9322 | val |= LCPLL_PLL_DISABLE; | |
9323 | I915_WRITE(LCPLL_CTL, val); | |
9324 | POSTING_READ(LCPLL_CTL); | |
9325 | ||
9326 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9327 | DRM_ERROR("LCPLL still locked\n"); | |
9328 | ||
9ccd5aeb | 9329 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9330 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9331 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9332 | ndelay(100); |
9333 | ||
9ccd5aeb PZ |
9334 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9335 | 1)) | |
be256dc7 PZ |
9336 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9337 | ||
9338 | if (allow_power_down) { | |
9339 | val = I915_READ(LCPLL_CTL); | |
9340 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9341 | I915_WRITE(LCPLL_CTL, val); | |
9342 | POSTING_READ(LCPLL_CTL); | |
9343 | } | |
9344 | } | |
9345 | ||
9346 | /* | |
9347 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9348 | * source. | |
9349 | */ | |
6ff58d53 | 9350 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9351 | { |
9352 | uint32_t val; | |
9353 | ||
9354 | val = I915_READ(LCPLL_CTL); | |
9355 | ||
9356 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9357 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9358 | return; | |
9359 | ||
a8a8bd54 PZ |
9360 | /* |
9361 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9362 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9363 | */ |
59bad947 | 9364 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9365 | |
be256dc7 PZ |
9366 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9367 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9368 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9369 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9370 | } |
9371 | ||
9ccd5aeb | 9372 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9373 | val |= D_COMP_COMP_FORCE; |
9374 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9375 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9376 | |
9377 | val = I915_READ(LCPLL_CTL); | |
9378 | val &= ~LCPLL_PLL_DISABLE; | |
9379 | I915_WRITE(LCPLL_CTL, val); | |
9380 | ||
9381 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9382 | DRM_ERROR("LCPLL not locked yet\n"); | |
9383 | ||
9384 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9385 | val = I915_READ(LCPLL_CTL); | |
9386 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9387 | I915_WRITE(LCPLL_CTL, val); | |
9388 | ||
9389 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9390 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9391 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9392 | } | |
215733fa | 9393 | |
59bad947 | 9394 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9395 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9396 | } |
9397 | ||
765dab67 PZ |
9398 | /* |
9399 | * Package states C8 and deeper are really deep PC states that can only be | |
9400 | * reached when all the devices on the system allow it, so even if the graphics | |
9401 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9402 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9403 | * | |
9404 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9405 | * well is disabled and most interrupts are disabled, and these are also | |
9406 | * requirements for runtime PM. When these conditions are met, we manually do | |
9407 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9408 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9409 | * hang the machine. | |
9410 | * | |
9411 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9412 | * the state of some registers, so when we come back from PC8+ we need to | |
9413 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9414 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9415 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9416 | * because of the runtime PM support). | |
9417 | * | |
9418 | * For more, read "Display Sequences for Package C8" on the hardware | |
9419 | * documentation. | |
9420 | */ | |
a14cb6fc | 9421 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9422 | { |
c67a470b PZ |
9423 | struct drm_device *dev = dev_priv->dev; |
9424 | uint32_t val; | |
9425 | ||
c67a470b PZ |
9426 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9427 | ||
c2699524 | 9428 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9429 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9430 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9431 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9432 | } | |
9433 | ||
9434 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9435 | hsw_disable_lcpll(dev_priv, true, true); |
9436 | } | |
9437 | ||
a14cb6fc | 9438 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9439 | { |
9440 | struct drm_device *dev = dev_priv->dev; | |
9441 | uint32_t val; | |
9442 | ||
c67a470b PZ |
9443 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9444 | ||
9445 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9446 | lpt_init_pch_refclk(dev); |
9447 | ||
c2699524 | 9448 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9449 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9450 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9451 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9452 | } | |
c67a470b PZ |
9453 | } |
9454 | ||
27c329ed | 9455 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9456 | { |
a821fc46 | 9457 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9458 | struct intel_atomic_state *old_intel_state = |
9459 | to_intel_atomic_state(old_state); | |
9460 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9461 | |
27c329ed | 9462 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9463 | } |
9464 | ||
b432e5cf | 9465 | /* compute the max rate for new configuration */ |
27c329ed | 9466 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9467 | { |
565602d7 ML |
9468 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9469 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9470 | struct drm_crtc *crtc; | |
9471 | struct drm_crtc_state *cstate; | |
27c329ed | 9472 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9473 | unsigned max_pixel_rate = 0, i; |
9474 | enum pipe pipe; | |
b432e5cf | 9475 | |
565602d7 ML |
9476 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9477 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9478 | |
565602d7 ML |
9479 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9480 | int pixel_rate; | |
27c329ed | 9481 | |
565602d7 ML |
9482 | crtc_state = to_intel_crtc_state(cstate); |
9483 | if (!crtc_state->base.enable) { | |
9484 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9485 | continue; |
565602d7 | 9486 | } |
b432e5cf | 9487 | |
27c329ed | 9488 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9489 | |
9490 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9491 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9492 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9493 | ||
565602d7 | 9494 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9495 | } |
9496 | ||
565602d7 ML |
9497 | for_each_pipe(dev_priv, pipe) |
9498 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9499 | ||
b432e5cf VS |
9500 | return max_pixel_rate; |
9501 | } | |
9502 | ||
9503 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9504 | { | |
9505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9506 | uint32_t val, data; | |
9507 | int ret; | |
9508 | ||
9509 | if (WARN((I915_READ(LCPLL_CTL) & | |
9510 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9511 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9512 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9513 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9514 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9515 | return; | |
9516 | ||
9517 | mutex_lock(&dev_priv->rps.hw_lock); | |
9518 | ret = sandybridge_pcode_write(dev_priv, | |
9519 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9520 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9521 | if (ret) { | |
9522 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9523 | return; | |
9524 | } | |
9525 | ||
9526 | val = I915_READ(LCPLL_CTL); | |
9527 | val |= LCPLL_CD_SOURCE_FCLK; | |
9528 | I915_WRITE(LCPLL_CTL, val); | |
9529 | ||
5ba00178 TU |
9530 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9531 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9532 | DRM_ERROR("Switching to FCLK failed\n"); |
9533 | ||
9534 | val = I915_READ(LCPLL_CTL); | |
9535 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9536 | ||
9537 | switch (cdclk) { | |
9538 | case 450000: | |
9539 | val |= LCPLL_CLK_FREQ_450; | |
9540 | data = 0; | |
9541 | break; | |
9542 | case 540000: | |
9543 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9544 | data = 1; | |
9545 | break; | |
9546 | case 337500: | |
9547 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9548 | data = 2; | |
9549 | break; | |
9550 | case 675000: | |
9551 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9552 | data = 3; | |
9553 | break; | |
9554 | default: | |
9555 | WARN(1, "invalid cdclk frequency\n"); | |
9556 | return; | |
9557 | } | |
9558 | ||
9559 | I915_WRITE(LCPLL_CTL, val); | |
9560 | ||
9561 | val = I915_READ(LCPLL_CTL); | |
9562 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9563 | I915_WRITE(LCPLL_CTL, val); | |
9564 | ||
5ba00178 TU |
9565 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9566 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9567 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9568 | ||
9569 | mutex_lock(&dev_priv->rps.hw_lock); | |
9570 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9571 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9572 | ||
9573 | intel_update_cdclk(dev); | |
9574 | ||
9575 | WARN(cdclk != dev_priv->cdclk_freq, | |
9576 | "cdclk requested %d kHz but got %d kHz\n", | |
9577 | cdclk, dev_priv->cdclk_freq); | |
9578 | } | |
9579 | ||
27c329ed | 9580 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9581 | { |
27c329ed | 9582 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9583 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9584 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9585 | int cdclk; |
9586 | ||
9587 | /* | |
9588 | * FIXME should also account for plane ratio | |
9589 | * once 64bpp pixel formats are supported. | |
9590 | */ | |
27c329ed | 9591 | if (max_pixclk > 540000) |
b432e5cf | 9592 | cdclk = 675000; |
27c329ed | 9593 | else if (max_pixclk > 450000) |
b432e5cf | 9594 | cdclk = 540000; |
27c329ed | 9595 | else if (max_pixclk > 337500) |
b432e5cf VS |
9596 | cdclk = 450000; |
9597 | else | |
9598 | cdclk = 337500; | |
9599 | ||
b432e5cf | 9600 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9601 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9602 | cdclk, dev_priv->max_cdclk_freq); | |
9603 | return -EINVAL; | |
b432e5cf VS |
9604 | } |
9605 | ||
1a617b77 ML |
9606 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9607 | if (!intel_state->active_crtcs) | |
9608 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9609 | |
9610 | return 0; | |
9611 | } | |
9612 | ||
27c329ed | 9613 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9614 | { |
27c329ed | 9615 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9616 | struct intel_atomic_state *old_intel_state = |
9617 | to_intel_atomic_state(old_state); | |
9618 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9619 | |
27c329ed | 9620 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9621 | } |
9622 | ||
190f68c5 ACO |
9623 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9624 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9625 | { |
af3997b5 MK |
9626 | struct intel_encoder *intel_encoder = |
9627 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9628 | ||
9629 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9630 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9631 | return -EINVAL; | |
9632 | } | |
716c2e55 | 9633 | |
c7653199 | 9634 | crtc->lowfreq_avail = false; |
644cef34 | 9635 | |
c8f7a0db | 9636 | return 0; |
79e53945 JB |
9637 | } |
9638 | ||
3760b59c S |
9639 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9640 | enum port port, | |
9641 | struct intel_crtc_state *pipe_config) | |
9642 | { | |
8106ddbd ACO |
9643 | enum intel_dpll_id id; |
9644 | ||
3760b59c S |
9645 | switch (port) { |
9646 | case PORT_A: | |
9647 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9648 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9649 | break; |
9650 | case PORT_B: | |
9651 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9652 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9653 | break; |
9654 | case PORT_C: | |
9655 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9656 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9657 | break; |
9658 | default: | |
9659 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9660 | return; |
3760b59c | 9661 | } |
8106ddbd ACO |
9662 | |
9663 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9664 | } |
9665 | ||
96b7dfb7 S |
9666 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9667 | enum port port, | |
5cec258b | 9668 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9669 | { |
8106ddbd | 9670 | enum intel_dpll_id id; |
a3c988ea | 9671 | u32 temp; |
96b7dfb7 S |
9672 | |
9673 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9674 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9675 | ||
9676 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9677 | case SKL_DPLL0: |
a3c988ea ACO |
9678 | id = DPLL_ID_SKL_DPLL0; |
9679 | break; | |
96b7dfb7 | 9680 | case SKL_DPLL1: |
8106ddbd | 9681 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9682 | break; |
9683 | case SKL_DPLL2: | |
8106ddbd | 9684 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9685 | break; |
9686 | case SKL_DPLL3: | |
8106ddbd | 9687 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9688 | break; |
8106ddbd ACO |
9689 | default: |
9690 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9691 | return; | |
96b7dfb7 | 9692 | } |
8106ddbd ACO |
9693 | |
9694 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9695 | } |
9696 | ||
7d2c8175 DL |
9697 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9698 | enum port port, | |
5cec258b | 9699 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9700 | { |
8106ddbd ACO |
9701 | enum intel_dpll_id id; |
9702 | ||
7d2c8175 DL |
9703 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9704 | ||
9705 | switch (pipe_config->ddi_pll_sel) { | |
9706 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9707 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9708 | break; |
9709 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9710 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9711 | break; |
00490c22 | 9712 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9713 | id = DPLL_ID_SPLL; |
79bd23da | 9714 | break; |
9d16da65 ACO |
9715 | case PORT_CLK_SEL_LCPLL_810: |
9716 | id = DPLL_ID_LCPLL_810; | |
9717 | break; | |
9718 | case PORT_CLK_SEL_LCPLL_1350: | |
9719 | id = DPLL_ID_LCPLL_1350; | |
9720 | break; | |
9721 | case PORT_CLK_SEL_LCPLL_2700: | |
9722 | id = DPLL_ID_LCPLL_2700; | |
9723 | break; | |
8106ddbd ACO |
9724 | default: |
9725 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9726 | /* fall through */ | |
9727 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9728 | return; |
7d2c8175 | 9729 | } |
8106ddbd ACO |
9730 | |
9731 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9732 | } |
9733 | ||
cf30429e JN |
9734 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9735 | struct intel_crtc_state *pipe_config, | |
9736 | unsigned long *power_domain_mask) | |
9737 | { | |
9738 | struct drm_device *dev = crtc->base.dev; | |
9739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9740 | enum intel_display_power_domain power_domain; | |
9741 | u32 tmp; | |
9742 | ||
9743 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; | |
9744 | ||
9745 | /* | |
9746 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9747 | * consistency and less surprising code; it's in always on power). | |
9748 | */ | |
9749 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9750 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9751 | enum pipe trans_edp_pipe; | |
9752 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9753 | default: | |
9754 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9755 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9756 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9757 | trans_edp_pipe = PIPE_A; | |
9758 | break; | |
9759 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9760 | trans_edp_pipe = PIPE_B; | |
9761 | break; | |
9762 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9763 | trans_edp_pipe = PIPE_C; | |
9764 | break; | |
9765 | } | |
9766 | ||
9767 | if (trans_edp_pipe == crtc->pipe) | |
9768 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9769 | } | |
9770 | ||
9771 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9772 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9773 | return false; | |
9774 | *power_domain_mask |= BIT(power_domain); | |
9775 | ||
9776 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9777 | ||
9778 | return tmp & PIPECONF_ENABLE; | |
9779 | } | |
9780 | ||
4d1de975 JN |
9781 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9782 | struct intel_crtc_state *pipe_config, | |
9783 | unsigned long *power_domain_mask) | |
9784 | { | |
9785 | struct drm_device *dev = crtc->base.dev; | |
9786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9787 | enum intel_display_power_domain power_domain; | |
9788 | enum port port; | |
9789 | enum transcoder cpu_transcoder; | |
9790 | u32 tmp; | |
9791 | ||
9792 | pipe_config->has_dsi_encoder = false; | |
9793 | ||
9794 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9795 | if (port == PORT_A) | |
9796 | cpu_transcoder = TRANSCODER_DSI_A; | |
9797 | else | |
9798 | cpu_transcoder = TRANSCODER_DSI_C; | |
9799 | ||
9800 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9801 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9802 | continue; | |
9803 | *power_domain_mask |= BIT(power_domain); | |
9804 | ||
9805 | /* XXX: this works for video mode only */ | |
9806 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9807 | if (!(tmp & DPI_ENABLE)) | |
9808 | continue; | |
9809 | ||
9810 | tmp = I915_READ(MIPI_CTRL(port)); | |
9811 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9812 | continue; | |
9813 | ||
9814 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9815 | pipe_config->has_dsi_encoder = true; | |
9816 | break; | |
9817 | } | |
9818 | ||
9819 | return pipe_config->has_dsi_encoder; | |
9820 | } | |
9821 | ||
26804afd | 9822 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9823 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9824 | { |
9825 | struct drm_device *dev = crtc->base.dev; | |
9826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9827 | struct intel_shared_dpll *pll; |
26804afd DV |
9828 | enum port port; |
9829 | uint32_t tmp; | |
9830 | ||
9831 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9832 | ||
9833 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9834 | ||
ef11bdb3 | 9835 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9836 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9837 | else if (IS_BROXTON(dev)) |
9838 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9839 | else |
9840 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9841 | |
8106ddbd ACO |
9842 | pll = pipe_config->shared_dpll; |
9843 | if (pll) { | |
2edd6443 ACO |
9844 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9845 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9846 | } |
9847 | ||
26804afd DV |
9848 | /* |
9849 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9850 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9851 | * the PCH transcoder is on. | |
9852 | */ | |
ca370455 DL |
9853 | if (INTEL_INFO(dev)->gen < 9 && |
9854 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9855 | pipe_config->has_pch_encoder = true; |
9856 | ||
9857 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9858 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9859 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9860 | ||
9861 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9862 | } | |
9863 | } | |
9864 | ||
0e8ffe1b | 9865 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9866 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9867 | { |
9868 | struct drm_device *dev = crtc->base.dev; | |
9869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9870 | enum intel_display_power_domain power_domain; |
9871 | unsigned long power_domain_mask; | |
cf30429e | 9872 | bool active; |
0e8ffe1b | 9873 | |
1729050e ID |
9874 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9875 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9876 | return false; |
1729050e ID |
9877 | power_domain_mask = BIT(power_domain); |
9878 | ||
8106ddbd | 9879 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9880 | |
cf30429e | 9881 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9882 | |
4d1de975 JN |
9883 | if (IS_BROXTON(dev_priv)) { |
9884 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
9885 | &power_domain_mask); | |
9886 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
9887 | if (pipe_config->has_dsi_encoder) | |
9888 | active = true; | |
9889 | } | |
9890 | ||
cf30429e | 9891 | if (!active) |
1729050e | 9892 | goto out; |
0e8ffe1b | 9893 | |
4d1de975 JN |
9894 | if (!pipe_config->has_dsi_encoder) { |
9895 | haswell_get_ddi_port_state(crtc, pipe_config); | |
9896 | intel_get_pipe_timings(crtc, pipe_config); | |
9897 | } | |
627eb5a3 | 9898 | |
bc58be60 | 9899 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9900 | |
05dc698c LL |
9901 | pipe_config->gamma_mode = |
9902 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9903 | ||
a1b2278e CK |
9904 | if (INTEL_INFO(dev)->gen >= 9) { |
9905 | skl_init_scalers(dev, crtc, pipe_config); | |
9906 | } | |
9907 | ||
af99ceda CK |
9908 | if (INTEL_INFO(dev)->gen >= 9) { |
9909 | pipe_config->scaler_state.scaler_id = -1; | |
9910 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9911 | } | |
9912 | ||
1729050e ID |
9913 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9914 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9915 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 9916 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9917 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9918 | else |
1c132b44 | 9919 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9920 | } |
88adfff1 | 9921 | |
e59150dc JB |
9922 | if (IS_HASWELL(dev)) |
9923 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9924 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9925 | |
4d1de975 JN |
9926 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9927 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9928 | pipe_config->pixel_multiplier = |
9929 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9930 | } else { | |
9931 | pipe_config->pixel_multiplier = 1; | |
9932 | } | |
6c49f241 | 9933 | |
1729050e ID |
9934 | out: |
9935 | for_each_power_domain(power_domain, power_domain_mask) | |
9936 | intel_display_power_put(dev_priv, power_domain); | |
9937 | ||
cf30429e | 9938 | return active; |
0e8ffe1b DV |
9939 | } |
9940 | ||
55a08b3f ML |
9941 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
9942 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
9943 | { |
9944 | struct drm_device *dev = crtc->dev; | |
9945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9946 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9947 | uint32_t cntl = 0, size = 0; |
560b85bb | 9948 | |
55a08b3f ML |
9949 | if (plane_state && plane_state->visible) { |
9950 | unsigned int width = plane_state->base.crtc_w; | |
9951 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
9952 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9953 | ||
9954 | switch (stride) { | |
9955 | default: | |
9956 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9957 | width, stride); | |
9958 | stride = 256; | |
9959 | /* fallthrough */ | |
9960 | case 256: | |
9961 | case 512: | |
9962 | case 1024: | |
9963 | case 2048: | |
9964 | break; | |
4b0e333e CW |
9965 | } |
9966 | ||
dc41c154 VS |
9967 | cntl |= CURSOR_ENABLE | |
9968 | CURSOR_GAMMA_ENABLE | | |
9969 | CURSOR_FORMAT_ARGB | | |
9970 | CURSOR_STRIDE(stride); | |
9971 | ||
9972 | size = (height << 12) | width; | |
4b0e333e | 9973 | } |
560b85bb | 9974 | |
dc41c154 VS |
9975 | if (intel_crtc->cursor_cntl != 0 && |
9976 | (intel_crtc->cursor_base != base || | |
9977 | intel_crtc->cursor_size != size || | |
9978 | intel_crtc->cursor_cntl != cntl)) { | |
9979 | /* On these chipsets we can only modify the base/size/stride | |
9980 | * whilst the cursor is disabled. | |
9981 | */ | |
0b87c24e VS |
9982 | I915_WRITE(CURCNTR(PIPE_A), 0); |
9983 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 9984 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9985 | } |
560b85bb | 9986 | |
99d1f387 | 9987 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 9988 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
9989 | intel_crtc->cursor_base = base; |
9990 | } | |
4726e0b0 | 9991 | |
dc41c154 VS |
9992 | if (intel_crtc->cursor_size != size) { |
9993 | I915_WRITE(CURSIZE, size); | |
9994 | intel_crtc->cursor_size = size; | |
4b0e333e | 9995 | } |
560b85bb | 9996 | |
4b0e333e | 9997 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
9998 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
9999 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10000 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10001 | } |
560b85bb CW |
10002 | } |
10003 | ||
55a08b3f ML |
10004 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10005 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10006 | { |
10007 | struct drm_device *dev = crtc->dev; | |
10008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10010 | int pipe = intel_crtc->pipe; | |
663f3122 | 10011 | uint32_t cntl = 0; |
4b0e333e | 10012 | |
55a08b3f | 10013 | if (plane_state && plane_state->visible) { |
4b0e333e | 10014 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10015 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10016 | case 64: |
10017 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10018 | break; | |
10019 | case 128: | |
10020 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10021 | break; | |
10022 | case 256: | |
10023 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10024 | break; | |
10025 | default: | |
55a08b3f | 10026 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10027 | return; |
65a21cd6 | 10028 | } |
4b0e333e | 10029 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10030 | |
fc6f93bc | 10031 | if (HAS_DDI(dev)) |
47bf17a7 | 10032 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10033 | |
55a08b3f ML |
10034 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10035 | cntl |= CURSOR_ROTATE_180; | |
10036 | } | |
4398ad45 | 10037 | |
4b0e333e CW |
10038 | if (intel_crtc->cursor_cntl != cntl) { |
10039 | I915_WRITE(CURCNTR(pipe), cntl); | |
10040 | POSTING_READ(CURCNTR(pipe)); | |
10041 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10042 | } |
4b0e333e | 10043 | |
65a21cd6 | 10044 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10045 | I915_WRITE(CURBASE(pipe), base); |
10046 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10047 | |
10048 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10049 | } |
10050 | ||
cda4b7d3 | 10051 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10052 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10053 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10054 | { |
10055 | struct drm_device *dev = crtc->dev; | |
10056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10057 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10058 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10059 | u32 base = intel_crtc->cursor_addr; |
10060 | u32 pos = 0; | |
cda4b7d3 | 10061 | |
55a08b3f ML |
10062 | if (plane_state) { |
10063 | int x = plane_state->base.crtc_x; | |
10064 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10065 | |
55a08b3f ML |
10066 | if (x < 0) { |
10067 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10068 | x = -x; | |
10069 | } | |
10070 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10071 | |
55a08b3f ML |
10072 | if (y < 0) { |
10073 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10074 | y = -y; | |
10075 | } | |
10076 | pos |= y << CURSOR_Y_SHIFT; | |
10077 | ||
10078 | /* ILK+ do this automagically */ | |
10079 | if (HAS_GMCH_DISPLAY(dev) && | |
10080 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10081 | base += (plane_state->base.crtc_h * | |
10082 | plane_state->base.crtc_w - 1) * 4; | |
10083 | } | |
cda4b7d3 | 10084 | } |
cda4b7d3 | 10085 | |
5efb3e28 VS |
10086 | I915_WRITE(CURPOS(pipe), pos); |
10087 | ||
8ac54669 | 10088 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10089 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10090 | else |
55a08b3f | 10091 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10092 | } |
10093 | ||
dc41c154 VS |
10094 | static bool cursor_size_ok(struct drm_device *dev, |
10095 | uint32_t width, uint32_t height) | |
10096 | { | |
10097 | if (width == 0 || height == 0) | |
10098 | return false; | |
10099 | ||
10100 | /* | |
10101 | * 845g/865g are special in that they are only limited by | |
10102 | * the width of their cursors, the height is arbitrary up to | |
10103 | * the precision of the register. Everything else requires | |
10104 | * square cursors, limited to a few power-of-two sizes. | |
10105 | */ | |
10106 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10107 | if ((width & 63) != 0) | |
10108 | return false; | |
10109 | ||
10110 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10111 | return false; | |
10112 | ||
10113 | if (height > 1023) | |
10114 | return false; | |
10115 | } else { | |
10116 | switch (width | height) { | |
10117 | case 256: | |
10118 | case 128: | |
10119 | if (IS_GEN2(dev)) | |
10120 | return false; | |
10121 | case 64: | |
10122 | break; | |
10123 | default: | |
10124 | return false; | |
10125 | } | |
10126 | } | |
10127 | ||
10128 | return true; | |
10129 | } | |
10130 | ||
79e53945 JB |
10131 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10132 | static struct drm_display_mode load_detect_mode = { | |
10133 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10134 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10135 | }; | |
10136 | ||
a8bb6818 DV |
10137 | struct drm_framebuffer * |
10138 | __intel_framebuffer_create(struct drm_device *dev, | |
10139 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10140 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10141 | { |
10142 | struct intel_framebuffer *intel_fb; | |
10143 | int ret; | |
10144 | ||
10145 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10146 | if (!intel_fb) |
d2dff872 | 10147 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10148 | |
10149 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10150 | if (ret) |
10151 | goto err; | |
d2dff872 CW |
10152 | |
10153 | return &intel_fb->base; | |
dcb1394e | 10154 | |
dd4916c5 | 10155 | err: |
dd4916c5 | 10156 | kfree(intel_fb); |
dd4916c5 | 10157 | return ERR_PTR(ret); |
d2dff872 CW |
10158 | } |
10159 | ||
b5ea642a | 10160 | static struct drm_framebuffer * |
a8bb6818 DV |
10161 | intel_framebuffer_create(struct drm_device *dev, |
10162 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10163 | struct drm_i915_gem_object *obj) | |
10164 | { | |
10165 | struct drm_framebuffer *fb; | |
10166 | int ret; | |
10167 | ||
10168 | ret = i915_mutex_lock_interruptible(dev); | |
10169 | if (ret) | |
10170 | return ERR_PTR(ret); | |
10171 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10172 | mutex_unlock(&dev->struct_mutex); | |
10173 | ||
10174 | return fb; | |
10175 | } | |
10176 | ||
d2dff872 CW |
10177 | static u32 |
10178 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10179 | { | |
10180 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10181 | return ALIGN(pitch, 64); | |
10182 | } | |
10183 | ||
10184 | static u32 | |
10185 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10186 | { | |
10187 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10188 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10189 | } |
10190 | ||
10191 | static struct drm_framebuffer * | |
10192 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10193 | struct drm_display_mode *mode, | |
10194 | int depth, int bpp) | |
10195 | { | |
dcb1394e | 10196 | struct drm_framebuffer *fb; |
d2dff872 | 10197 | struct drm_i915_gem_object *obj; |
0fed39bd | 10198 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10199 | |
10200 | obj = i915_gem_alloc_object(dev, | |
10201 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10202 | if (obj == NULL) | |
10203 | return ERR_PTR(-ENOMEM); | |
10204 | ||
10205 | mode_cmd.width = mode->hdisplay; | |
10206 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10207 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10208 | bpp); | |
5ca0c34a | 10209 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10210 | |
dcb1394e LW |
10211 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10212 | if (IS_ERR(fb)) | |
10213 | drm_gem_object_unreference_unlocked(&obj->base); | |
10214 | ||
10215 | return fb; | |
d2dff872 CW |
10216 | } |
10217 | ||
10218 | static struct drm_framebuffer * | |
10219 | mode_fits_in_fbdev(struct drm_device *dev, | |
10220 | struct drm_display_mode *mode) | |
10221 | { | |
0695726e | 10222 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10223 | struct drm_i915_private *dev_priv = dev->dev_private; |
10224 | struct drm_i915_gem_object *obj; | |
10225 | struct drm_framebuffer *fb; | |
10226 | ||
4c0e5528 | 10227 | if (!dev_priv->fbdev) |
d2dff872 CW |
10228 | return NULL; |
10229 | ||
4c0e5528 | 10230 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10231 | return NULL; |
10232 | ||
4c0e5528 DV |
10233 | obj = dev_priv->fbdev->fb->obj; |
10234 | BUG_ON(!obj); | |
10235 | ||
8bcd4553 | 10236 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10237 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10238 | fb->bits_per_pixel)) | |
d2dff872 CW |
10239 | return NULL; |
10240 | ||
01f2c773 | 10241 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10242 | return NULL; |
10243 | ||
edde3617 | 10244 | drm_framebuffer_reference(fb); |
d2dff872 | 10245 | return fb; |
4520f53a DV |
10246 | #else |
10247 | return NULL; | |
10248 | #endif | |
d2dff872 CW |
10249 | } |
10250 | ||
d3a40d1b ACO |
10251 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10252 | struct drm_crtc *crtc, | |
10253 | struct drm_display_mode *mode, | |
10254 | struct drm_framebuffer *fb, | |
10255 | int x, int y) | |
10256 | { | |
10257 | struct drm_plane_state *plane_state; | |
10258 | int hdisplay, vdisplay; | |
10259 | int ret; | |
10260 | ||
10261 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10262 | if (IS_ERR(plane_state)) | |
10263 | return PTR_ERR(plane_state); | |
10264 | ||
10265 | if (mode) | |
10266 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10267 | else | |
10268 | hdisplay = vdisplay = 0; | |
10269 | ||
10270 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10271 | if (ret) | |
10272 | return ret; | |
10273 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10274 | plane_state->crtc_x = 0; | |
10275 | plane_state->crtc_y = 0; | |
10276 | plane_state->crtc_w = hdisplay; | |
10277 | plane_state->crtc_h = vdisplay; | |
10278 | plane_state->src_x = x << 16; | |
10279 | plane_state->src_y = y << 16; | |
10280 | plane_state->src_w = hdisplay << 16; | |
10281 | plane_state->src_h = vdisplay << 16; | |
10282 | ||
10283 | return 0; | |
10284 | } | |
10285 | ||
d2434ab7 | 10286 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10287 | struct drm_display_mode *mode, |
51fd371b RC |
10288 | struct intel_load_detect_pipe *old, |
10289 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10290 | { |
10291 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10292 | struct intel_encoder *intel_encoder = |
10293 | intel_attached_encoder(connector); | |
79e53945 | 10294 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10295 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10296 | struct drm_crtc *crtc = NULL; |
10297 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10298 | struct drm_framebuffer *fb; |
51fd371b | 10299 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10300 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10301 | struct drm_connector_state *connector_state; |
4be07317 | 10302 | struct intel_crtc_state *crtc_state; |
51fd371b | 10303 | int ret, i = -1; |
79e53945 | 10304 | |
d2dff872 | 10305 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10306 | connector->base.id, connector->name, |
8e329a03 | 10307 | encoder->base.id, encoder->name); |
d2dff872 | 10308 | |
edde3617 ML |
10309 | old->restore_state = NULL; |
10310 | ||
51fd371b RC |
10311 | retry: |
10312 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10313 | if (ret) | |
ad3c558f | 10314 | goto fail; |
6e9f798d | 10315 | |
79e53945 JB |
10316 | /* |
10317 | * Algorithm gets a little messy: | |
7a5e4805 | 10318 | * |
79e53945 JB |
10319 | * - if the connector already has an assigned crtc, use it (but make |
10320 | * sure it's on first) | |
7a5e4805 | 10321 | * |
79e53945 JB |
10322 | * - try to find the first unused crtc that can drive this connector, |
10323 | * and use that if we find one | |
79e53945 JB |
10324 | */ |
10325 | ||
10326 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10327 | if (connector->state->crtc) { |
10328 | crtc = connector->state->crtc; | |
8261b191 | 10329 | |
51fd371b | 10330 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10331 | if (ret) |
ad3c558f | 10332 | goto fail; |
8261b191 CW |
10333 | |
10334 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10335 | goto found; |
79e53945 JB |
10336 | } |
10337 | ||
10338 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10339 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10340 | i++; |
10341 | if (!(encoder->possible_crtcs & (1 << i))) | |
10342 | continue; | |
edde3617 ML |
10343 | |
10344 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10345 | if (ret) | |
10346 | goto fail; | |
10347 | ||
10348 | if (possible_crtc->state->enable) { | |
10349 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10350 | continue; |
edde3617 | 10351 | } |
a459249c VS |
10352 | |
10353 | crtc = possible_crtc; | |
10354 | break; | |
79e53945 JB |
10355 | } |
10356 | ||
10357 | /* | |
10358 | * If we didn't find an unused CRTC, don't use any. | |
10359 | */ | |
10360 | if (!crtc) { | |
7173188d | 10361 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10362 | goto fail; |
79e53945 JB |
10363 | } |
10364 | ||
edde3617 ML |
10365 | found: |
10366 | intel_crtc = to_intel_crtc(crtc); | |
10367 | ||
4d02e2de DV |
10368 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10369 | if (ret) | |
ad3c558f | 10370 | goto fail; |
79e53945 | 10371 | |
83a57153 | 10372 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10373 | restore_state = drm_atomic_state_alloc(dev); |
10374 | if (!state || !restore_state) { | |
10375 | ret = -ENOMEM; | |
10376 | goto fail; | |
10377 | } | |
83a57153 ACO |
10378 | |
10379 | state->acquire_ctx = ctx; | |
edde3617 | 10380 | restore_state->acquire_ctx = ctx; |
83a57153 | 10381 | |
944b0c76 ACO |
10382 | connector_state = drm_atomic_get_connector_state(state, connector); |
10383 | if (IS_ERR(connector_state)) { | |
10384 | ret = PTR_ERR(connector_state); | |
10385 | goto fail; | |
10386 | } | |
10387 | ||
edde3617 ML |
10388 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10389 | if (ret) | |
10390 | goto fail; | |
944b0c76 | 10391 | |
4be07317 ACO |
10392 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10393 | if (IS_ERR(crtc_state)) { | |
10394 | ret = PTR_ERR(crtc_state); | |
10395 | goto fail; | |
10396 | } | |
10397 | ||
49d6fa21 | 10398 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10399 | |
6492711d CW |
10400 | if (!mode) |
10401 | mode = &load_detect_mode; | |
79e53945 | 10402 | |
d2dff872 CW |
10403 | /* We need a framebuffer large enough to accommodate all accesses |
10404 | * that the plane may generate whilst we perform load detection. | |
10405 | * We can not rely on the fbcon either being present (we get called | |
10406 | * during its initialisation to detect all boot displays, or it may | |
10407 | * not even exist) or that it is large enough to satisfy the | |
10408 | * requested mode. | |
10409 | */ | |
94352cf9 DV |
10410 | fb = mode_fits_in_fbdev(dev, mode); |
10411 | if (fb == NULL) { | |
d2dff872 | 10412 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10413 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10414 | } else |
10415 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10416 | if (IS_ERR(fb)) { |
d2dff872 | 10417 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10418 | goto fail; |
79e53945 | 10419 | } |
79e53945 | 10420 | |
d3a40d1b ACO |
10421 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10422 | if (ret) | |
10423 | goto fail; | |
10424 | ||
edde3617 ML |
10425 | drm_framebuffer_unreference(fb); |
10426 | ||
10427 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10428 | if (ret) | |
10429 | goto fail; | |
10430 | ||
10431 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10432 | if (!ret) | |
10433 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10434 | if (!ret) | |
10435 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10436 | if (ret) { | |
10437 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10438 | goto fail; | |
10439 | } | |
8c7b5ccb | 10440 | |
3ba86073 ML |
10441 | ret = drm_atomic_commit(state); |
10442 | if (ret) { | |
6492711d | 10443 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10444 | goto fail; |
79e53945 | 10445 | } |
edde3617 ML |
10446 | |
10447 | old->restore_state = restore_state; | |
7173188d | 10448 | |
79e53945 | 10449 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10450 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10451 | return true; |
412b61d8 | 10452 | |
ad3c558f | 10453 | fail: |
e5d958ef | 10454 | drm_atomic_state_free(state); |
edde3617 ML |
10455 | drm_atomic_state_free(restore_state); |
10456 | restore_state = state = NULL; | |
83a57153 | 10457 | |
51fd371b RC |
10458 | if (ret == -EDEADLK) { |
10459 | drm_modeset_backoff(ctx); | |
10460 | goto retry; | |
10461 | } | |
10462 | ||
412b61d8 | 10463 | return false; |
79e53945 JB |
10464 | } |
10465 | ||
d2434ab7 | 10466 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10467 | struct intel_load_detect_pipe *old, |
10468 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10469 | { |
d2434ab7 DV |
10470 | struct intel_encoder *intel_encoder = |
10471 | intel_attached_encoder(connector); | |
4ef69c7a | 10472 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10473 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10474 | int ret; |
79e53945 | 10475 | |
d2dff872 | 10476 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10477 | connector->base.id, connector->name, |
8e329a03 | 10478 | encoder->base.id, encoder->name); |
d2dff872 | 10479 | |
edde3617 | 10480 | if (!state) |
0622a53c | 10481 | return; |
79e53945 | 10482 | |
edde3617 ML |
10483 | ret = drm_atomic_commit(state); |
10484 | if (ret) { | |
10485 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10486 | drm_atomic_state_free(state); | |
10487 | } | |
79e53945 JB |
10488 | } |
10489 | ||
da4a1efa | 10490 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10491 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10492 | { |
10493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10494 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10495 | ||
10496 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10497 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10498 | else if (HAS_PCH_SPLIT(dev)) |
10499 | return 120000; | |
10500 | else if (!IS_GEN2(dev)) | |
10501 | return 96000; | |
10502 | else | |
10503 | return 48000; | |
10504 | } | |
10505 | ||
79e53945 | 10506 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10507 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10508 | struct intel_crtc_state *pipe_config) |
79e53945 | 10509 | { |
f1f644dc | 10510 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10511 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10512 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10513 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10514 | u32 fp; |
10515 | intel_clock_t clock; | |
dccbea3b | 10516 | int port_clock; |
da4a1efa | 10517 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10518 | |
10519 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10520 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10521 | else |
293623f7 | 10522 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10523 | |
10524 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10525 | if (IS_PINEVIEW(dev)) { |
10526 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10527 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10528 | } else { |
10529 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10530 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10531 | } | |
10532 | ||
a6c45cf0 | 10533 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10534 | if (IS_PINEVIEW(dev)) |
10535 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10536 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10537 | else |
10538 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10539 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10540 | ||
10541 | switch (dpll & DPLL_MODE_MASK) { | |
10542 | case DPLLB_MODE_DAC_SERIAL: | |
10543 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10544 | 5 : 10; | |
10545 | break; | |
10546 | case DPLLB_MODE_LVDS: | |
10547 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10548 | 7 : 14; | |
10549 | break; | |
10550 | default: | |
28c97730 | 10551 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10552 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10553 | return; |
79e53945 JB |
10554 | } |
10555 | ||
ac58c3f0 | 10556 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10557 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10558 | else |
dccbea3b | 10559 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10560 | } else { |
0fb58223 | 10561 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10562 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10563 | |
10564 | if (is_lvds) { | |
10565 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10566 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10567 | |
10568 | if (lvds & LVDS_CLKB_POWER_UP) | |
10569 | clock.p2 = 7; | |
10570 | else | |
10571 | clock.p2 = 14; | |
79e53945 JB |
10572 | } else { |
10573 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10574 | clock.p1 = 2; | |
10575 | else { | |
10576 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10577 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10578 | } | |
10579 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10580 | clock.p2 = 4; | |
10581 | else | |
10582 | clock.p2 = 2; | |
79e53945 | 10583 | } |
da4a1efa | 10584 | |
dccbea3b | 10585 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10586 | } |
10587 | ||
18442d08 VS |
10588 | /* |
10589 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10590 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10591 | * encoder's get_config() function. |
10592 | */ | |
dccbea3b | 10593 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10594 | } |
10595 | ||
6878da05 VS |
10596 | int intel_dotclock_calculate(int link_freq, |
10597 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10598 | { |
f1f644dc JB |
10599 | /* |
10600 | * The calculation for the data clock is: | |
1041a02f | 10601 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10602 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10603 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10604 | * |
10605 | * and the link clock is simpler: | |
1041a02f | 10606 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10607 | */ |
10608 | ||
6878da05 VS |
10609 | if (!m_n->link_n) |
10610 | return 0; | |
f1f644dc | 10611 | |
6878da05 VS |
10612 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10613 | } | |
f1f644dc | 10614 | |
18442d08 | 10615 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10616 | struct intel_crtc_state *pipe_config) |
6878da05 | 10617 | { |
e3b247da | 10618 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10619 | |
18442d08 VS |
10620 | /* read out port_clock from the DPLL */ |
10621 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10622 | |
f1f644dc | 10623 | /* |
e3b247da VS |
10624 | * In case there is an active pipe without active ports, |
10625 | * we may need some idea for the dotclock anyway. | |
10626 | * Calculate one based on the FDI configuration. | |
79e53945 | 10627 | */ |
2d112de7 | 10628 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10629 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10630 | &pipe_config->fdi_m_n); |
79e53945 JB |
10631 | } |
10632 | ||
10633 | /** Returns the currently programmed mode of the given pipe. */ | |
10634 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10635 | struct drm_crtc *crtc) | |
10636 | { | |
548f245b | 10637 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10638 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10639 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10640 | struct drm_display_mode *mode; |
3f36b937 | 10641 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10642 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10643 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10644 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10645 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10646 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10647 | |
10648 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10649 | if (!mode) | |
10650 | return NULL; | |
10651 | ||
3f36b937 TU |
10652 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10653 | if (!pipe_config) { | |
10654 | kfree(mode); | |
10655 | return NULL; | |
10656 | } | |
10657 | ||
f1f644dc JB |
10658 | /* |
10659 | * Construct a pipe_config sufficient for getting the clock info | |
10660 | * back out of crtc_clock_get. | |
10661 | * | |
10662 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10663 | * to use a real value here instead. | |
10664 | */ | |
3f36b937 TU |
10665 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10666 | pipe_config->pixel_multiplier = 1; | |
10667 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10668 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10669 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10670 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10671 | ||
10672 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10673 | mode->hdisplay = (htot & 0xffff) + 1; |
10674 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10675 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10676 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10677 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10678 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10679 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10680 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10681 | ||
10682 | drm_mode_set_name(mode); | |
79e53945 | 10683 | |
3f36b937 TU |
10684 | kfree(pipe_config); |
10685 | ||
79e53945 JB |
10686 | return mode; |
10687 | } | |
10688 | ||
f047e395 CW |
10689 | void intel_mark_busy(struct drm_device *dev) |
10690 | { | |
c67a470b PZ |
10691 | struct drm_i915_private *dev_priv = dev->dev_private; |
10692 | ||
f62a0076 CW |
10693 | if (dev_priv->mm.busy) |
10694 | return; | |
10695 | ||
43694d69 | 10696 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10697 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10698 | if (INTEL_INFO(dev)->gen >= 6) |
10699 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10700 | dev_priv->mm.busy = true; |
f047e395 CW |
10701 | } |
10702 | ||
10703 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10704 | { |
c67a470b | 10705 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10706 | |
f62a0076 CW |
10707 | if (!dev_priv->mm.busy) |
10708 | return; | |
10709 | ||
10710 | dev_priv->mm.busy = false; | |
10711 | ||
3d13ef2e | 10712 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10713 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10714 | |
43694d69 | 10715 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10716 | } |
10717 | ||
79e53945 JB |
10718 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10719 | { | |
10720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10721 | struct drm_device *dev = crtc->dev; |
10722 | struct intel_unpin_work *work; | |
67e77c5a | 10723 | |
5e2d7afc | 10724 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10725 | work = intel_crtc->unpin_work; |
10726 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10727 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10728 | |
10729 | if (work) { | |
10730 | cancel_work_sync(&work->work); | |
10731 | kfree(work); | |
10732 | } | |
79e53945 JB |
10733 | |
10734 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10735 | |
79e53945 JB |
10736 | kfree(intel_crtc); |
10737 | } | |
10738 | ||
6b95a207 KH |
10739 | static void intel_unpin_work_fn(struct work_struct *__work) |
10740 | { | |
10741 | struct intel_unpin_work *work = | |
10742 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10743 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10744 | struct drm_device *dev = crtc->base.dev; | |
10745 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10746 | |
b4a98e57 | 10747 | mutex_lock(&dev->struct_mutex); |
3465c580 | 10748 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 10749 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10750 | |
f06cc1b9 | 10751 | if (work->flip_queued_req) |
146d84f0 | 10752 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10753 | mutex_unlock(&dev->struct_mutex); |
10754 | ||
a9ff8714 | 10755 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10756 | intel_fbc_post_update(crtc); |
89ed88ba | 10757 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10758 | |
a9ff8714 VS |
10759 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10760 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10761 | |
6b95a207 KH |
10762 | kfree(work); |
10763 | } | |
10764 | ||
1afe3e9d | 10765 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10766 | struct drm_crtc *crtc) |
6b95a207 | 10767 | { |
6b95a207 KH |
10768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10769 | struct intel_unpin_work *work; | |
6b95a207 KH |
10770 | unsigned long flags; |
10771 | ||
10772 | /* Ignore early vblank irqs */ | |
10773 | if (intel_crtc == NULL) | |
10774 | return; | |
10775 | ||
f326038a DV |
10776 | /* |
10777 | * This is called both by irq handlers and the reset code (to complete | |
10778 | * lost pageflips) so needs the full irqsave spinlocks. | |
10779 | */ | |
6b95a207 KH |
10780 | spin_lock_irqsave(&dev->event_lock, flags); |
10781 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10782 | |
10783 | /* Ensure we don't miss a work->pending update ... */ | |
10784 | smp_rmb(); | |
10785 | ||
10786 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10787 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10788 | return; | |
10789 | } | |
10790 | ||
d6bbafa1 | 10791 | page_flip_completed(intel_crtc); |
0af7e4df | 10792 | |
6b95a207 | 10793 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10794 | } |
10795 | ||
1afe3e9d JB |
10796 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10797 | { | |
fbee40df | 10798 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10799 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10800 | ||
49b14a5c | 10801 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10802 | } |
10803 | ||
10804 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10805 | { | |
fbee40df | 10806 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10807 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10808 | ||
49b14a5c | 10809 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10810 | } |
10811 | ||
75f7f3ec VS |
10812 | /* Is 'a' after or equal to 'b'? */ |
10813 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10814 | { | |
10815 | return !((a - b) & 0x80000000); | |
10816 | } | |
10817 | ||
10818 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10819 | { | |
10820 | struct drm_device *dev = crtc->base.dev; | |
10821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10822 | ||
bdfa7542 VS |
10823 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10824 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10825 | return true; | |
10826 | ||
75f7f3ec VS |
10827 | /* |
10828 | * The relevant registers doen't exist on pre-ctg. | |
10829 | * As the flip done interrupt doesn't trigger for mmio | |
10830 | * flips on gmch platforms, a flip count check isn't | |
10831 | * really needed there. But since ctg has the registers, | |
10832 | * include it in the check anyway. | |
10833 | */ | |
10834 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10835 | return true; | |
10836 | ||
e8861675 ML |
10837 | /* |
10838 | * BDW signals flip done immediately if the plane | |
10839 | * is disabled, even if the plane enable is already | |
10840 | * armed to occur at the next vblank :( | |
10841 | */ | |
10842 | ||
75f7f3ec VS |
10843 | /* |
10844 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10845 | * used the same base address. In that case the mmio flip might | |
10846 | * have completed, but the CS hasn't even executed the flip yet. | |
10847 | * | |
10848 | * A flip count check isn't enough as the CS might have updated | |
10849 | * the base address just after start of vblank, but before we | |
10850 | * managed to process the interrupt. This means we'd complete the | |
10851 | * CS flip too soon. | |
10852 | * | |
10853 | * Combining both checks should get us a good enough result. It may | |
10854 | * still happen that the CS flip has been executed, but has not | |
10855 | * yet actually completed. But in case the base address is the same | |
10856 | * anyway, we don't really care. | |
10857 | */ | |
10858 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10859 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10860 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10861 | crtc->unpin_work->flip_count); |
10862 | } | |
10863 | ||
6b95a207 KH |
10864 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10865 | { | |
fbee40df | 10866 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10867 | struct intel_crtc *intel_crtc = |
10868 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10869 | unsigned long flags; | |
10870 | ||
f326038a DV |
10871 | |
10872 | /* | |
10873 | * This is called both by irq handlers and the reset code (to complete | |
10874 | * lost pageflips) so needs the full irqsave spinlocks. | |
10875 | * | |
10876 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10877 | * generate a page-flip completion irq, i.e. every modeset |
10878 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10879 | */ | |
6b95a207 | 10880 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10881 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10882 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10883 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10884 | } | |
10885 | ||
6042639c | 10886 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10887 | { |
10888 | /* Ensure that the work item is consistent when activating it ... */ | |
10889 | smp_wmb(); | |
6042639c | 10890 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
10891 | /* and that it is marked active as soon as the irq could fire. */ |
10892 | smp_wmb(); | |
10893 | } | |
10894 | ||
8c9f3aaf JB |
10895 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10896 | struct drm_crtc *crtc, | |
10897 | struct drm_framebuffer *fb, | |
ed8d1975 | 10898 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10899 | struct drm_i915_gem_request *req, |
ed8d1975 | 10900 | uint32_t flags) |
8c9f3aaf | 10901 | { |
4a570db5 | 10902 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10904 | u32 flip_mask; |
10905 | int ret; | |
10906 | ||
5fb9de1a | 10907 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10908 | if (ret) |
4fa62c89 | 10909 | return ret; |
8c9f3aaf JB |
10910 | |
10911 | /* Can't queue multiple flips, so wait for the previous | |
10912 | * one to finish before executing the next. | |
10913 | */ | |
10914 | if (intel_crtc->plane) | |
10915 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10916 | else | |
10917 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
10918 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
10919 | intel_ring_emit(engine, MI_NOOP); | |
10920 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
6d90c952 | 10921 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10922 | intel_ring_emit(engine, fb->pitches[0]); |
10923 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
10924 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
e7d841ca | 10925 | |
6042639c | 10926 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10927 | return 0; |
8c9f3aaf JB |
10928 | } |
10929 | ||
10930 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10931 | struct drm_crtc *crtc, | |
10932 | struct drm_framebuffer *fb, | |
ed8d1975 | 10933 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10934 | struct drm_i915_gem_request *req, |
ed8d1975 | 10935 | uint32_t flags) |
8c9f3aaf | 10936 | { |
4a570db5 | 10937 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10939 | u32 flip_mask; |
10940 | int ret; | |
10941 | ||
5fb9de1a | 10942 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10943 | if (ret) |
4fa62c89 | 10944 | return ret; |
8c9f3aaf JB |
10945 | |
10946 | if (intel_crtc->plane) | |
10947 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10948 | else | |
10949 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
10950 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
10951 | intel_ring_emit(engine, MI_NOOP); | |
10952 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
6d90c952 | 10953 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10954 | intel_ring_emit(engine, fb->pitches[0]); |
10955 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
10956 | intel_ring_emit(engine, MI_NOOP); | |
6d90c952 | 10957 | |
6042639c | 10958 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10959 | return 0; |
8c9f3aaf JB |
10960 | } |
10961 | ||
10962 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10963 | struct drm_crtc *crtc, | |
10964 | struct drm_framebuffer *fb, | |
ed8d1975 | 10965 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10966 | struct drm_i915_gem_request *req, |
ed8d1975 | 10967 | uint32_t flags) |
8c9f3aaf | 10968 | { |
4a570db5 | 10969 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
10970 | struct drm_i915_private *dev_priv = dev->dev_private; |
10971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10972 | uint32_t pf, pipesrc; | |
10973 | int ret; | |
10974 | ||
5fb9de1a | 10975 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10976 | if (ret) |
4fa62c89 | 10977 | return ret; |
8c9f3aaf JB |
10978 | |
10979 | /* i965+ uses the linear or tiled offsets from the | |
10980 | * Display Registers (which do not change across a page-flip) | |
10981 | * so we need only reprogram the base address. | |
10982 | */ | |
e2f80391 | 10983 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 10984 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10985 | intel_ring_emit(engine, fb->pitches[0]); |
10986 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | | |
c2c75131 | 10987 | obj->tiling_mode); |
8c9f3aaf JB |
10988 | |
10989 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10990 | * untested on non-native modes, so ignore it for now. | |
10991 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10992 | */ | |
10993 | pf = 0; | |
10994 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
e2f80391 | 10995 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 10996 | |
6042639c | 10997 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 10998 | return 0; |
8c9f3aaf JB |
10999 | } |
11000 | ||
11001 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11002 | struct drm_crtc *crtc, | |
11003 | struct drm_framebuffer *fb, | |
ed8d1975 | 11004 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11005 | struct drm_i915_gem_request *req, |
ed8d1975 | 11006 | uint32_t flags) |
8c9f3aaf | 11007 | { |
4a570db5 | 11008 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11009 | struct drm_i915_private *dev_priv = dev->dev_private; |
11010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11011 | uint32_t pf, pipesrc; | |
11012 | int ret; | |
11013 | ||
5fb9de1a | 11014 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11015 | if (ret) |
4fa62c89 | 11016 | return ret; |
8c9f3aaf | 11017 | |
e2f80391 | 11018 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11019 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11020 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); |
11021 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
8c9f3aaf | 11022 | |
dc257cf1 DV |
11023 | /* Contrary to the suggestions in the documentation, |
11024 | * "Enable Panel Fitter" does not seem to be required when page | |
11025 | * flipping with a non-native mode, and worse causes a normal | |
11026 | * modeset to fail. | |
11027 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11028 | */ | |
11029 | pf = 0; | |
8c9f3aaf | 11030 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
e2f80391 | 11031 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11032 | |
6042639c | 11033 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11034 | return 0; |
8c9f3aaf JB |
11035 | } |
11036 | ||
7c9017e5 JB |
11037 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11038 | struct drm_crtc *crtc, | |
11039 | struct drm_framebuffer *fb, | |
ed8d1975 | 11040 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11041 | struct drm_i915_gem_request *req, |
ed8d1975 | 11042 | uint32_t flags) |
7c9017e5 | 11043 | { |
4a570db5 | 11044 | struct intel_engine_cs *engine = req->engine; |
7c9017e5 | 11045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11046 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11047 | int len, ret; |
11048 | ||
eba905b2 | 11049 | switch (intel_crtc->plane) { |
cb05d8de DV |
11050 | case PLANE_A: |
11051 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11052 | break; | |
11053 | case PLANE_B: | |
11054 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11055 | break; | |
11056 | case PLANE_C: | |
11057 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11058 | break; | |
11059 | default: | |
11060 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11061 | return -ENODEV; |
cb05d8de DV |
11062 | } |
11063 | ||
ffe74d75 | 11064 | len = 4; |
e2f80391 | 11065 | if (engine->id == RCS) { |
ffe74d75 | 11066 | len += 6; |
f476828a DL |
11067 | /* |
11068 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11069 | * 48bits addresses, and we need a NOOP for the batch size to | |
11070 | * stay even. | |
11071 | */ | |
11072 | if (IS_GEN8(dev)) | |
11073 | len += 2; | |
11074 | } | |
ffe74d75 | 11075 | |
f66fab8e VS |
11076 | /* |
11077 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11078 | * "The full packet must be contained within the same cache line." | |
11079 | * | |
11080 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11081 | * cacheline, if we ever start emitting more commands before | |
11082 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11083 | * then do the cacheline alignment, and finally emit the | |
11084 | * MI_DISPLAY_FLIP. | |
11085 | */ | |
bba09b12 | 11086 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11087 | if (ret) |
4fa62c89 | 11088 | return ret; |
f66fab8e | 11089 | |
5fb9de1a | 11090 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11091 | if (ret) |
4fa62c89 | 11092 | return ret; |
7c9017e5 | 11093 | |
ffe74d75 CW |
11094 | /* Unmask the flip-done completion message. Note that the bspec says that |
11095 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11096 | * more than one flip event at any time (or ensure that one flip message | |
11097 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11098 | * Experimentation says that BCS works despite DERRMR masking all | |
11099 | * flip-done completion events and that unmasking all planes at once | |
11100 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11101 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11102 | */ | |
e2f80391 TU |
11103 | if (engine->id == RCS) { |
11104 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11105 | intel_ring_emit_reg(engine, DERRMR); | |
11106 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11107 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11108 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11109 | if (IS_GEN8(dev)) |
e2f80391 | 11110 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11111 | MI_SRM_LRM_GLOBAL_GTT); |
11112 | else | |
e2f80391 | 11113 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | |
f476828a | 11114 | MI_SRM_LRM_GLOBAL_GTT); |
e2f80391 TU |
11115 | intel_ring_emit_reg(engine, DERRMR); |
11116 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
f476828a | 11117 | if (IS_GEN8(dev)) { |
e2f80391 TU |
11118 | intel_ring_emit(engine, 0); |
11119 | intel_ring_emit(engine, MI_NOOP); | |
f476828a | 11120 | } |
ffe74d75 CW |
11121 | } |
11122 | ||
e2f80391 TU |
11123 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); |
11124 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11125 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11126 | intel_ring_emit(engine, (MI_NOOP)); | |
e7d841ca | 11127 | |
6042639c | 11128 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11129 | return 0; |
7c9017e5 JB |
11130 | } |
11131 | ||
0bc40be8 | 11132 | static bool use_mmio_flip(struct intel_engine_cs *engine, |
84c33a64 SG |
11133 | struct drm_i915_gem_object *obj) |
11134 | { | |
11135 | /* | |
11136 | * This is not being used for older platforms, because | |
11137 | * non-availability of flip done interrupt forces us to use | |
11138 | * CS flips. Older platforms derive flip done using some clever | |
11139 | * tricks involving the flip_pending status bits and vblank irqs. | |
11140 | * So using MMIO flips there would disrupt this mechanism. | |
11141 | */ | |
11142 | ||
0bc40be8 | 11143 | if (engine == NULL) |
8e09bf83 CW |
11144 | return true; |
11145 | ||
0bc40be8 | 11146 | if (INTEL_INFO(engine->dev)->gen < 5) |
84c33a64 SG |
11147 | return false; |
11148 | ||
11149 | if (i915.use_mmio_flip < 0) | |
11150 | return false; | |
11151 | else if (i915.use_mmio_flip > 0) | |
11152 | return true; | |
14bf993e OM |
11153 | else if (i915.enable_execlists) |
11154 | return true; | |
fd8e058a AG |
11155 | else if (obj->base.dma_buf && |
11156 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11157 | false)) | |
11158 | return true; | |
84c33a64 | 11159 | else |
666796da | 11160 | return engine != i915_gem_request_get_engine(obj->last_write_req); |
84c33a64 SG |
11161 | } |
11162 | ||
6042639c | 11163 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11164 | unsigned int rotation, |
6042639c | 11165 | struct intel_unpin_work *work) |
ff944564 DL |
11166 | { |
11167 | struct drm_device *dev = intel_crtc->base.dev; | |
11168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11169 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11170 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11171 | u32 ctl, stride, tile_height; |
ff944564 DL |
11172 | |
11173 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11174 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11175 | switch (fb->modifier[0]) { |
11176 | case DRM_FORMAT_MOD_NONE: | |
11177 | break; | |
11178 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11179 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11180 | break; |
11181 | case I915_FORMAT_MOD_Y_TILED: | |
11182 | ctl |= PLANE_CTL_TILED_Y; | |
11183 | break; | |
11184 | case I915_FORMAT_MOD_Yf_TILED: | |
11185 | ctl |= PLANE_CTL_TILED_YF; | |
11186 | break; | |
11187 | default: | |
11188 | MISSING_CASE(fb->modifier[0]); | |
11189 | } | |
ff944564 DL |
11190 | |
11191 | /* | |
11192 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11193 | * linear buffers or in number of tiles for tiled buffers. | |
11194 | */ | |
86efe24a TU |
11195 | if (intel_rotation_90_or_270(rotation)) { |
11196 | /* stride = Surface height in tiles */ | |
832be82f | 11197 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11198 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11199 | } else { | |
11200 | stride = fb->pitches[0] / | |
7b49f948 VS |
11201 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11202 | fb->pixel_format); | |
86efe24a | 11203 | } |
ff944564 DL |
11204 | |
11205 | /* | |
11206 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11207 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11208 | */ | |
11209 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11210 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11211 | ||
6042639c | 11212 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11213 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11214 | } | |
11215 | ||
6042639c CW |
11216 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11217 | struct intel_unpin_work *work) | |
84c33a64 SG |
11218 | { |
11219 | struct drm_device *dev = intel_crtc->base.dev; | |
11220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11221 | struct intel_framebuffer *intel_fb = | |
11222 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11223 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11224 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11225 | u32 dspcntr; |
84c33a64 | 11226 | |
84c33a64 SG |
11227 | dspcntr = I915_READ(reg); |
11228 | ||
c5d97472 DL |
11229 | if (obj->tiling_mode != I915_TILING_NONE) |
11230 | dspcntr |= DISPPLANE_TILED; | |
11231 | else | |
11232 | dspcntr &= ~DISPPLANE_TILED; | |
11233 | ||
84c33a64 SG |
11234 | I915_WRITE(reg, dspcntr); |
11235 | ||
6042639c | 11236 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11237 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11238 | } |
11239 | ||
11240 | /* | |
11241 | * XXX: This is the temporary way to update the plane registers until we get | |
11242 | * around to using the usual plane update functions for MMIO flips | |
11243 | */ | |
6042639c | 11244 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11245 | { |
6042639c CW |
11246 | struct intel_crtc *crtc = mmio_flip->crtc; |
11247 | struct intel_unpin_work *work; | |
11248 | ||
11249 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11250 | work = crtc->unpin_work; | |
11251 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11252 | if (work == NULL) | |
11253 | return; | |
ff944564 | 11254 | |
6042639c | 11255 | intel_mark_page_flip_active(work); |
ff944564 | 11256 | |
6042639c | 11257 | intel_pipe_update_start(crtc); |
ff944564 | 11258 | |
6042639c | 11259 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11260 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11261 | else |
11262 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11263 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11264 | |
6042639c | 11265 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11266 | } |
11267 | ||
9362c7c5 | 11268 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11269 | { |
b2cfe0ab CW |
11270 | struct intel_mmio_flip *mmio_flip = |
11271 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11272 | struct intel_framebuffer *intel_fb = |
11273 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11274 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11275 | |
6042639c | 11276 | if (mmio_flip->req) { |
eed29a5b | 11277 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11278 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11279 | false, NULL, |
11280 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11281 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11282 | } | |
84c33a64 | 11283 | |
fd8e058a AG |
11284 | /* For framebuffer backed by dmabuf, wait for fence */ |
11285 | if (obj->base.dma_buf) | |
11286 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11287 | false, false, | |
11288 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11289 | ||
6042639c | 11290 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11291 | kfree(mmio_flip); |
84c33a64 SG |
11292 | } |
11293 | ||
11294 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11295 | struct drm_crtc *crtc, | |
86efe24a | 11296 | struct drm_i915_gem_object *obj) |
84c33a64 | 11297 | { |
b2cfe0ab CW |
11298 | struct intel_mmio_flip *mmio_flip; |
11299 | ||
11300 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11301 | if (mmio_flip == NULL) | |
11302 | return -ENOMEM; | |
84c33a64 | 11303 | |
bcafc4e3 | 11304 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11305 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11306 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11307 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11308 | |
b2cfe0ab CW |
11309 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11310 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11311 | |
84c33a64 SG |
11312 | return 0; |
11313 | } | |
11314 | ||
8c9f3aaf JB |
11315 | static int intel_default_queue_flip(struct drm_device *dev, |
11316 | struct drm_crtc *crtc, | |
11317 | struct drm_framebuffer *fb, | |
ed8d1975 | 11318 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11319 | struct drm_i915_gem_request *req, |
ed8d1975 | 11320 | uint32_t flags) |
8c9f3aaf JB |
11321 | { |
11322 | return -ENODEV; | |
11323 | } | |
11324 | ||
d6bbafa1 CW |
11325 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11326 | struct drm_crtc *crtc) | |
11327 | { | |
11328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11330 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11331 | u32 addr; | |
11332 | ||
11333 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11334 | return true; | |
11335 | ||
908565c2 CW |
11336 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11337 | return false; | |
11338 | ||
d6bbafa1 CW |
11339 | if (!work->enable_stall_check) |
11340 | return false; | |
11341 | ||
11342 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11343 | if (work->flip_queued_req && |
11344 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11345 | return false; |
11346 | ||
1e3feefd | 11347 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11348 | } |
11349 | ||
1e3feefd | 11350 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11351 | return false; |
11352 | ||
11353 | /* Potential stall - if we see that the flip has happened, | |
11354 | * assume a missed interrupt. */ | |
11355 | if (INTEL_INFO(dev)->gen >= 4) | |
11356 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11357 | else | |
11358 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11359 | ||
11360 | /* There is a potential issue here with a false positive after a flip | |
11361 | * to the same address. We could address this by checking for a | |
11362 | * non-incrementing frame counter. | |
11363 | */ | |
11364 | return addr == work->gtt_offset; | |
11365 | } | |
11366 | ||
11367 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11368 | { | |
11369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11370 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11372 | struct intel_unpin_work *work; |
f326038a | 11373 | |
6c51d46f | 11374 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11375 | |
11376 | if (crtc == NULL) | |
11377 | return; | |
11378 | ||
f326038a | 11379 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11380 | work = intel_crtc->unpin_work; |
11381 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11382 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11383 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11384 | page_flip_completed(intel_crtc); |
6ad790c0 | 11385 | work = NULL; |
d6bbafa1 | 11386 | } |
6ad790c0 CW |
11387 | if (work != NULL && |
11388 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11389 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11390 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11391 | } |
11392 | ||
6b95a207 KH |
11393 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11394 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11395 | struct drm_pending_vblank_event *event, |
11396 | uint32_t page_flip_flags) | |
6b95a207 KH |
11397 | { |
11398 | struct drm_device *dev = crtc->dev; | |
11399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11400 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11401 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11403 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11404 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11405 | struct intel_unpin_work *work; |
e2f80391 | 11406 | struct intel_engine_cs *engine; |
cf5d8a46 | 11407 | bool mmio_flip; |
91af127f | 11408 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11409 | int ret; |
6b95a207 | 11410 | |
2ff8fde1 MR |
11411 | /* |
11412 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11413 | * check to be safe. In the future we may enable pageflipping from | |
11414 | * a disabled primary plane. | |
11415 | */ | |
11416 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11417 | return -EBUSY; | |
11418 | ||
e6a595d2 | 11419 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11420 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11421 | return -EINVAL; |
11422 | ||
11423 | /* | |
11424 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11425 | * Note that pitch changes could also affect these register. | |
11426 | */ | |
11427 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11428 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11429 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11430 | return -EINVAL; |
11431 | ||
f900db47 CW |
11432 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11433 | goto out_hang; | |
11434 | ||
b14c5679 | 11435 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11436 | if (work == NULL) |
11437 | return -ENOMEM; | |
11438 | ||
6b95a207 | 11439 | work->event = event; |
b4a98e57 | 11440 | work->crtc = crtc; |
ab8d6675 | 11441 | work->old_fb = old_fb; |
6b95a207 KH |
11442 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11443 | ||
87b6b101 | 11444 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11445 | if (ret) |
11446 | goto free_work; | |
11447 | ||
6b95a207 | 11448 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11449 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11450 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11451 | /* Before declaring the flip queue wedged, check if |
11452 | * the hardware completed the operation behind our backs. | |
11453 | */ | |
11454 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11455 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11456 | page_flip_completed(intel_crtc); | |
11457 | } else { | |
11458 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11459 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11460 | |
d6bbafa1 CW |
11461 | drm_crtc_vblank_put(crtc); |
11462 | kfree(work); | |
11463 | return -EBUSY; | |
11464 | } | |
6b95a207 KH |
11465 | } |
11466 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11467 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11468 | |
b4a98e57 CW |
11469 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11470 | flush_workqueue(dev_priv->wq); | |
11471 | ||
75dfca80 | 11472 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11473 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11474 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11475 | |
f4510a27 | 11476 | crtc->primary->fb = fb; |
afd65eb4 | 11477 | update_state_fb(crtc->primary); |
e8216e50 | 11478 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11479 | |
e1f99ce6 | 11480 | work->pending_flip_obj = obj; |
e1f99ce6 | 11481 | |
89ed88ba CW |
11482 | ret = i915_mutex_lock_interruptible(dev); |
11483 | if (ret) | |
11484 | goto cleanup; | |
11485 | ||
b4a98e57 | 11486 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11487 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11488 | |
75f7f3ec | 11489 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11490 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11491 | |
666a4537 | 11492 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4a570db5 | 11493 | engine = &dev_priv->engine[BCS]; |
ab8d6675 | 11494 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 | 11495 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
e2f80391 | 11496 | engine = NULL; |
48bf5b2d | 11497 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4a570db5 | 11498 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11499 | } else if (INTEL_INFO(dev)->gen >= 7) { |
666796da | 11500 | engine = i915_gem_request_get_engine(obj->last_write_req); |
e2f80391 | 11501 | if (engine == NULL || engine->id != RCS) |
4a570db5 | 11502 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11503 | } else { |
4a570db5 | 11504 | engine = &dev_priv->engine[RCS]; |
4fa62c89 VS |
11505 | } |
11506 | ||
e2f80391 | 11507 | mmio_flip = use_mmio_flip(engine, obj); |
cf5d8a46 CW |
11508 | |
11509 | /* When using CS flips, we want to emit semaphores between rings. | |
11510 | * However, when using mmio flips we will create a task to do the | |
11511 | * synchronisation, so all we want here is to pin the framebuffer | |
11512 | * into the display plane and skip any waits. | |
11513 | */ | |
7580d774 | 11514 | if (!mmio_flip) { |
e2f80391 | 11515 | ret = i915_gem_object_sync(obj, engine, &request); |
7580d774 ML |
11516 | if (ret) |
11517 | goto cleanup_pending; | |
11518 | } | |
11519 | ||
3465c580 | 11520 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11521 | if (ret) |
11522 | goto cleanup_pending; | |
6b95a207 | 11523 | |
dedf278c TU |
11524 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11525 | obj, 0); | |
11526 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11527 | |
cf5d8a46 | 11528 | if (mmio_flip) { |
86efe24a | 11529 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11530 | if (ret) |
11531 | goto cleanup_unpin; | |
11532 | ||
f06cc1b9 JH |
11533 | i915_gem_request_assign(&work->flip_queued_req, |
11534 | obj->last_write_req); | |
d6bbafa1 | 11535 | } else { |
6258fbe2 | 11536 | if (!request) { |
e2f80391 | 11537 | request = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
11538 | if (IS_ERR(request)) { |
11539 | ret = PTR_ERR(request); | |
6258fbe2 | 11540 | goto cleanup_unpin; |
26827088 | 11541 | } |
6258fbe2 JH |
11542 | } |
11543 | ||
11544 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11545 | page_flip_flags); |
11546 | if (ret) | |
11547 | goto cleanup_unpin; | |
11548 | ||
6258fbe2 | 11549 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11550 | } |
11551 | ||
91af127f | 11552 | if (request) |
75289874 | 11553 | i915_add_request_no_flush(request); |
91af127f | 11554 | |
1e3feefd | 11555 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11556 | work->enable_stall_check = true; |
4fa62c89 | 11557 | |
ab8d6675 | 11558 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11559 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11560 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11561 | |
a9ff8714 VS |
11562 | intel_frontbuffer_flip_prepare(dev, |
11563 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11564 | |
e5510fac JB |
11565 | trace_i915_flip_request(intel_crtc->plane, obj); |
11566 | ||
6b95a207 | 11567 | return 0; |
96b099fd | 11568 | |
4fa62c89 | 11569 | cleanup_unpin: |
3465c580 | 11570 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11571 | cleanup_pending: |
0aa498d5 | 11572 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11573 | i915_gem_request_cancel(request); |
b4a98e57 | 11574 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11575 | mutex_unlock(&dev->struct_mutex); |
11576 | cleanup: | |
f4510a27 | 11577 | crtc->primary->fb = old_fb; |
afd65eb4 | 11578 | update_state_fb(crtc->primary); |
89ed88ba CW |
11579 | |
11580 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11581 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11582 | |
5e2d7afc | 11583 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11584 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11585 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11586 | |
87b6b101 | 11587 | drm_crtc_vblank_put(crtc); |
7317c75e | 11588 | free_work: |
96b099fd CW |
11589 | kfree(work); |
11590 | ||
f900db47 | 11591 | if (ret == -EIO) { |
02e0efb5 ML |
11592 | struct drm_atomic_state *state; |
11593 | struct drm_plane_state *plane_state; | |
11594 | ||
f900db47 | 11595 | out_hang: |
02e0efb5 ML |
11596 | state = drm_atomic_state_alloc(dev); |
11597 | if (!state) | |
11598 | return -ENOMEM; | |
11599 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11600 | ||
11601 | retry: | |
11602 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11603 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11604 | if (!ret) { | |
11605 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11606 | ||
11607 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11608 | if (!ret) | |
11609 | ret = drm_atomic_commit(state); | |
11610 | } | |
11611 | ||
11612 | if (ret == -EDEADLK) { | |
11613 | drm_modeset_backoff(state->acquire_ctx); | |
11614 | drm_atomic_state_clear(state); | |
11615 | goto retry; | |
11616 | } | |
11617 | ||
11618 | if (ret) | |
11619 | drm_atomic_state_free(state); | |
11620 | ||
f0d3dad3 | 11621 | if (ret == 0 && event) { |
5e2d7afc | 11622 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11623 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11624 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11625 | } |
f900db47 | 11626 | } |
96b099fd | 11627 | return ret; |
6b95a207 KH |
11628 | } |
11629 | ||
da20eabd ML |
11630 | |
11631 | /** | |
11632 | * intel_wm_need_update - Check whether watermarks need updating | |
11633 | * @plane: drm plane | |
11634 | * @state: new plane state | |
11635 | * | |
11636 | * Check current plane state versus the new one to determine whether | |
11637 | * watermarks need to be recalculated. | |
11638 | * | |
11639 | * Returns true or false. | |
11640 | */ | |
11641 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11642 | struct drm_plane_state *state) | |
11643 | { | |
d21fbe87 MR |
11644 | struct intel_plane_state *new = to_intel_plane_state(state); |
11645 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11646 | ||
11647 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11648 | if (new->visible != cur->visible) |
11649 | return true; | |
11650 | ||
11651 | if (!cur->base.fb || !new->base.fb) | |
11652 | return false; | |
11653 | ||
11654 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11655 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11656 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11657 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11658 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11659 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11660 | return true; |
7809e5ae | 11661 | |
2791a16c | 11662 | return false; |
7809e5ae MR |
11663 | } |
11664 | ||
d21fbe87 MR |
11665 | static bool needs_scaling(struct intel_plane_state *state) |
11666 | { | |
11667 | int src_w = drm_rect_width(&state->src) >> 16; | |
11668 | int src_h = drm_rect_height(&state->src) >> 16; | |
11669 | int dst_w = drm_rect_width(&state->dst); | |
11670 | int dst_h = drm_rect_height(&state->dst); | |
11671 | ||
11672 | return (src_w != dst_w || src_h != dst_h); | |
11673 | } | |
11674 | ||
da20eabd ML |
11675 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11676 | struct drm_plane_state *plane_state) | |
11677 | { | |
ab1d3a0e | 11678 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11679 | struct drm_crtc *crtc = crtc_state->crtc; |
11680 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11681 | struct drm_plane *plane = plane_state->plane; | |
11682 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11683 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11684 | struct intel_plane_state *old_plane_state = |
11685 | to_intel_plane_state(plane->state); | |
11686 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11687 | bool mode_changed = needs_modeset(crtc_state); |
11688 | bool was_crtc_enabled = crtc->state->active; | |
11689 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11690 | bool turn_off, turn_on, visible, was_visible; |
11691 | struct drm_framebuffer *fb = plane_state->fb; | |
11692 | ||
11693 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11694 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11695 | ret = skl_update_scaler_plane( | |
11696 | to_intel_crtc_state(crtc_state), | |
11697 | to_intel_plane_state(plane_state)); | |
11698 | if (ret) | |
11699 | return ret; | |
11700 | } | |
11701 | ||
da20eabd ML |
11702 | was_visible = old_plane_state->visible; |
11703 | visible = to_intel_plane_state(plane_state)->visible; | |
11704 | ||
11705 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11706 | was_visible = false; | |
11707 | ||
35c08f43 ML |
11708 | /* |
11709 | * Visibility is calculated as if the crtc was on, but | |
11710 | * after scaler setup everything depends on it being off | |
11711 | * when the crtc isn't active. | |
11712 | */ | |
11713 | if (!is_crtc_enabled) | |
11714 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11715 | |
11716 | if (!was_visible && !visible) | |
11717 | return 0; | |
11718 | ||
e8861675 ML |
11719 | if (fb != old_plane_state->base.fb) |
11720 | pipe_config->fb_changed = true; | |
11721 | ||
da20eabd ML |
11722 | turn_off = was_visible && (!visible || mode_changed); |
11723 | turn_on = visible && (!was_visible || mode_changed); | |
11724 | ||
11725 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11726 | plane->base.id, fb ? fb->base.id : -1); | |
11727 | ||
11728 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11729 | plane->base.id, was_visible, visible, | |
11730 | turn_off, turn_on, mode_changed); | |
11731 | ||
caed361d VS |
11732 | if (turn_on) { |
11733 | pipe_config->update_wm_pre = true; | |
11734 | ||
11735 | /* must disable cxsr around plane enable/disable */ | |
11736 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11737 | pipe_config->disable_cxsr = true; | |
11738 | } else if (turn_off) { | |
11739 | pipe_config->update_wm_post = true; | |
92826fcd | 11740 | |
852eb00d | 11741 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11742 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11743 | pipe_config->disable_cxsr = true; |
852eb00d | 11744 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11745 | /* FIXME bollocks */ |
11746 | pipe_config->update_wm_pre = true; | |
11747 | pipe_config->update_wm_post = true; | |
852eb00d | 11748 | } |
da20eabd | 11749 | |
ed4a6a7c | 11750 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11751 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11752 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11753 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11754 | ||
8be6ca85 | 11755 | if (visible || was_visible) |
cd202f69 | 11756 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11757 | |
31ae71fc ML |
11758 | /* |
11759 | * WaCxSRDisabledForSpriteScaling:ivb | |
11760 | * | |
11761 | * cstate->update_wm was already set above, so this flag will | |
11762 | * take effect when we commit and program watermarks. | |
11763 | */ | |
11764 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11765 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11766 | !needs_scaling(old_plane_state)) | |
11767 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11768 | |
da20eabd ML |
11769 | return 0; |
11770 | } | |
11771 | ||
6d3a1ce7 ML |
11772 | static bool encoders_cloneable(const struct intel_encoder *a, |
11773 | const struct intel_encoder *b) | |
11774 | { | |
11775 | /* masks could be asymmetric, so check both ways */ | |
11776 | return a == b || (a->cloneable & (1 << b->type) && | |
11777 | b->cloneable & (1 << a->type)); | |
11778 | } | |
11779 | ||
11780 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11781 | struct intel_crtc *crtc, | |
11782 | struct intel_encoder *encoder) | |
11783 | { | |
11784 | struct intel_encoder *source_encoder; | |
11785 | struct drm_connector *connector; | |
11786 | struct drm_connector_state *connector_state; | |
11787 | int i; | |
11788 | ||
11789 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11790 | if (connector_state->crtc != &crtc->base) | |
11791 | continue; | |
11792 | ||
11793 | source_encoder = | |
11794 | to_intel_encoder(connector_state->best_encoder); | |
11795 | if (!encoders_cloneable(encoder, source_encoder)) | |
11796 | return false; | |
11797 | } | |
11798 | ||
11799 | return true; | |
11800 | } | |
11801 | ||
11802 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11803 | struct intel_crtc *crtc) | |
11804 | { | |
11805 | struct intel_encoder *encoder; | |
11806 | struct drm_connector *connector; | |
11807 | struct drm_connector_state *connector_state; | |
11808 | int i; | |
11809 | ||
11810 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11811 | if (connector_state->crtc != &crtc->base) | |
11812 | continue; | |
11813 | ||
11814 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11815 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11816 | return false; | |
11817 | } | |
11818 | ||
11819 | return true; | |
11820 | } | |
11821 | ||
11822 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11823 | struct drm_crtc_state *crtc_state) | |
11824 | { | |
cf5a15be | 11825 | struct drm_device *dev = crtc->dev; |
ad421372 | 11826 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11828 | struct intel_crtc_state *pipe_config = |
11829 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11830 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11831 | int ret; |
6d3a1ce7 ML |
11832 | bool mode_changed = needs_modeset(crtc_state); |
11833 | ||
11834 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11835 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11836 | return -EINVAL; | |
11837 | } | |
11838 | ||
852eb00d | 11839 | if (mode_changed && !crtc_state->active) |
caed361d | 11840 | pipe_config->update_wm_post = true; |
eddfcbcd | 11841 | |
ad421372 ML |
11842 | if (mode_changed && crtc_state->enable && |
11843 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11844 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11845 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11846 | pipe_config); | |
11847 | if (ret) | |
11848 | return ret; | |
11849 | } | |
11850 | ||
82cf435b LL |
11851 | if (crtc_state->color_mgmt_changed) { |
11852 | ret = intel_color_check(crtc, crtc_state); | |
11853 | if (ret) | |
11854 | return ret; | |
11855 | } | |
11856 | ||
e435d6e5 | 11857 | ret = 0; |
86c8bbbe | 11858 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11859 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11860 | if (ret) { |
11861 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11862 | return ret; | |
11863 | } | |
11864 | } | |
11865 | ||
11866 | if (dev_priv->display.compute_intermediate_wm && | |
11867 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11868 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11869 | return 0; | |
11870 | ||
11871 | /* | |
11872 | * Calculate 'intermediate' watermarks that satisfy both the | |
11873 | * old state and the new state. We can program these | |
11874 | * immediately. | |
11875 | */ | |
11876 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11877 | intel_crtc, | |
11878 | pipe_config); | |
11879 | if (ret) { | |
11880 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 11881 | return ret; |
ed4a6a7c | 11882 | } |
86c8bbbe MR |
11883 | } |
11884 | ||
e435d6e5 ML |
11885 | if (INTEL_INFO(dev)->gen >= 9) { |
11886 | if (mode_changed) | |
11887 | ret = skl_update_scaler_crtc(pipe_config); | |
11888 | ||
11889 | if (!ret) | |
11890 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11891 | pipe_config); | |
11892 | } | |
11893 | ||
11894 | return ret; | |
6d3a1ce7 ML |
11895 | } |
11896 | ||
65b38e0d | 11897 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 11898 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
ea2c67bb MR |
11899 | .atomic_begin = intel_begin_crtc_commit, |
11900 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11901 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11902 | }; |
11903 | ||
d29b2f9d ACO |
11904 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11905 | { | |
11906 | struct intel_connector *connector; | |
11907 | ||
11908 | for_each_intel_connector(dev, connector) { | |
11909 | if (connector->base.encoder) { | |
11910 | connector->base.state->best_encoder = | |
11911 | connector->base.encoder; | |
11912 | connector->base.state->crtc = | |
11913 | connector->base.encoder->crtc; | |
11914 | } else { | |
11915 | connector->base.state->best_encoder = NULL; | |
11916 | connector->base.state->crtc = NULL; | |
11917 | } | |
11918 | } | |
11919 | } | |
11920 | ||
050f7aeb | 11921 | static void |
eba905b2 | 11922 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11923 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11924 | { |
11925 | int bpp = pipe_config->pipe_bpp; | |
11926 | ||
11927 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11928 | connector->base.base.id, | |
c23cc417 | 11929 | connector->base.name); |
050f7aeb DV |
11930 | |
11931 | /* Don't use an invalid EDID bpc value */ | |
11932 | if (connector->base.display_info.bpc && | |
11933 | connector->base.display_info.bpc * 3 < bpp) { | |
11934 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11935 | bpp, connector->base.display_info.bpc*3); | |
11936 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11937 | } | |
11938 | ||
013dd9e0 JN |
11939 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
11940 | if (connector->base.display_info.bpc == 0) { | |
11941 | int type = connector->base.connector_type; | |
11942 | int clamp_bpp = 24; | |
11943 | ||
11944 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
11945 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
11946 | type == DRM_MODE_CONNECTOR_eDP) | |
11947 | clamp_bpp = 18; | |
11948 | ||
11949 | if (bpp > clamp_bpp) { | |
11950 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
11951 | bpp, clamp_bpp); | |
11952 | pipe_config->pipe_bpp = clamp_bpp; | |
11953 | } | |
050f7aeb DV |
11954 | } |
11955 | } | |
11956 | ||
4e53c2e0 | 11957 | static int |
050f7aeb | 11958 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11959 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11960 | { |
050f7aeb | 11961 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11962 | struct drm_atomic_state *state; |
da3ced29 ACO |
11963 | struct drm_connector *connector; |
11964 | struct drm_connector_state *connector_state; | |
1486017f | 11965 | int bpp, i; |
4e53c2e0 | 11966 | |
666a4537 | 11967 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 11968 | bpp = 10*3; |
d328c9d7 DV |
11969 | else if (INTEL_INFO(dev)->gen >= 5) |
11970 | bpp = 12*3; | |
11971 | else | |
11972 | bpp = 8*3; | |
11973 | ||
4e53c2e0 | 11974 | |
4e53c2e0 DV |
11975 | pipe_config->pipe_bpp = bpp; |
11976 | ||
1486017f ACO |
11977 | state = pipe_config->base.state; |
11978 | ||
4e53c2e0 | 11979 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11980 | for_each_connector_in_state(state, connector, connector_state, i) { |
11981 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11982 | continue; |
11983 | ||
da3ced29 ACO |
11984 | connected_sink_compute_bpp(to_intel_connector(connector), |
11985 | pipe_config); | |
4e53c2e0 DV |
11986 | } |
11987 | ||
11988 | return bpp; | |
11989 | } | |
11990 | ||
644db711 DV |
11991 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11992 | { | |
11993 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11994 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11995 | mode->crtc_clock, |
644db711 DV |
11996 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11997 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11998 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11999 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12000 | } | |
12001 | ||
c0b03411 | 12002 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12003 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12004 | const char *context) |
12005 | { | |
6a60cd87 CK |
12006 | struct drm_device *dev = crtc->base.dev; |
12007 | struct drm_plane *plane; | |
12008 | struct intel_plane *intel_plane; | |
12009 | struct intel_plane_state *state; | |
12010 | struct drm_framebuffer *fb; | |
12011 | ||
12012 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12013 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 | 12014 | |
da205630 | 12015 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12016 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12017 | pipe_config->pipe_bpp, pipe_config->dither); | |
12018 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12019 | pipe_config->has_pch_encoder, | |
12020 | pipe_config->fdi_lanes, | |
12021 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12022 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12023 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12024 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12025 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12026 | pipe_config->lane_count, |
eb14cb74 VS |
12027 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12028 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12029 | pipe_config->dp_m_n.tu); | |
b95af8be | 12030 | |
90a6b7b0 | 12031 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12032 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12033 | pipe_config->lane_count, |
b95af8be VK |
12034 | pipe_config->dp_m2_n2.gmch_m, |
12035 | pipe_config->dp_m2_n2.gmch_n, | |
12036 | pipe_config->dp_m2_n2.link_m, | |
12037 | pipe_config->dp_m2_n2.link_n, | |
12038 | pipe_config->dp_m2_n2.tu); | |
12039 | ||
55072d19 DV |
12040 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12041 | pipe_config->has_audio, | |
12042 | pipe_config->has_infoframe); | |
12043 | ||
c0b03411 | 12044 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12045 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12046 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12047 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12048 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12049 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12050 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12051 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12052 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12053 | crtc->num_scalers, | |
12054 | pipe_config->scaler_state.scaler_users, | |
12055 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12056 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12057 | pipe_config->gmch_pfit.control, | |
12058 | pipe_config->gmch_pfit.pgm_ratios, | |
12059 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12060 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12061 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12062 | pipe_config->pch_pfit.size, |
12063 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12064 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12065 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12066 | |
415ff0f6 | 12067 | if (IS_BROXTON(dev)) { |
05712c15 | 12068 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12069 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12070 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12071 | pipe_config->ddi_pll_sel, |
12072 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12073 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12074 | pipe_config->dpll_hw_state.pll0, |
12075 | pipe_config->dpll_hw_state.pll1, | |
12076 | pipe_config->dpll_hw_state.pll2, | |
12077 | pipe_config->dpll_hw_state.pll3, | |
12078 | pipe_config->dpll_hw_state.pll6, | |
12079 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12080 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12081 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12082 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12083 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12084 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12085 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12086 | pipe_config->ddi_pll_sel, | |
12087 | pipe_config->dpll_hw_state.ctrl1, | |
12088 | pipe_config->dpll_hw_state.cfgcr1, | |
12089 | pipe_config->dpll_hw_state.cfgcr2); | |
12090 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12091 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12092 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12093 | pipe_config->dpll_hw_state.wrpll, |
12094 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12095 | } else { |
12096 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12097 | "fp0: 0x%x, fp1: 0x%x\n", | |
12098 | pipe_config->dpll_hw_state.dpll, | |
12099 | pipe_config->dpll_hw_state.dpll_md, | |
12100 | pipe_config->dpll_hw_state.fp0, | |
12101 | pipe_config->dpll_hw_state.fp1); | |
12102 | } | |
12103 | ||
6a60cd87 CK |
12104 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12105 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12106 | intel_plane = to_intel_plane(plane); | |
12107 | if (intel_plane->pipe != crtc->pipe) | |
12108 | continue; | |
12109 | ||
12110 | state = to_intel_plane_state(plane->state); | |
12111 | fb = state->base.fb; | |
12112 | if (!fb) { | |
12113 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12114 | "disabled, scaler_id = %d\n", | |
12115 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12116 | plane->base.id, intel_plane->pipe, | |
12117 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12118 | drm_plane_index(plane), state->scaler_id); | |
12119 | continue; | |
12120 | } | |
12121 | ||
12122 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12123 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12124 | plane->base.id, intel_plane->pipe, | |
12125 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12126 | drm_plane_index(plane)); | |
12127 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12128 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12129 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12130 | state->scaler_id, | |
12131 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12132 | drm_rect_width(&state->src) >> 16, | |
12133 | drm_rect_height(&state->src) >> 16, | |
12134 | state->dst.x1, state->dst.y1, | |
12135 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12136 | } | |
c0b03411 DV |
12137 | } |
12138 | ||
5448a00d | 12139 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12140 | { |
5448a00d | 12141 | struct drm_device *dev = state->dev; |
da3ced29 | 12142 | struct drm_connector *connector; |
00f0b378 VS |
12143 | unsigned int used_ports = 0; |
12144 | ||
12145 | /* | |
12146 | * Walk the connector list instead of the encoder | |
12147 | * list to detect the problem on ddi platforms | |
12148 | * where there's just one encoder per digital port. | |
12149 | */ | |
0bff4858 VS |
12150 | drm_for_each_connector(connector, dev) { |
12151 | struct drm_connector_state *connector_state; | |
12152 | struct intel_encoder *encoder; | |
12153 | ||
12154 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12155 | if (!connector_state) | |
12156 | connector_state = connector->state; | |
12157 | ||
5448a00d | 12158 | if (!connector_state->best_encoder) |
00f0b378 VS |
12159 | continue; |
12160 | ||
5448a00d ACO |
12161 | encoder = to_intel_encoder(connector_state->best_encoder); |
12162 | ||
12163 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12164 | |
12165 | switch (encoder->type) { | |
12166 | unsigned int port_mask; | |
12167 | case INTEL_OUTPUT_UNKNOWN: | |
12168 | if (WARN_ON(!HAS_DDI(dev))) | |
12169 | break; | |
12170 | case INTEL_OUTPUT_DISPLAYPORT: | |
12171 | case INTEL_OUTPUT_HDMI: | |
12172 | case INTEL_OUTPUT_EDP: | |
12173 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12174 | ||
12175 | /* the same port mustn't appear more than once */ | |
12176 | if (used_ports & port_mask) | |
12177 | return false; | |
12178 | ||
12179 | used_ports |= port_mask; | |
12180 | default: | |
12181 | break; | |
12182 | } | |
12183 | } | |
12184 | ||
12185 | return true; | |
12186 | } | |
12187 | ||
83a57153 ACO |
12188 | static void |
12189 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12190 | { | |
12191 | struct drm_crtc_state tmp_state; | |
663a3640 | 12192 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12193 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12194 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12195 | uint32_t ddi_pll_sel; |
c4e2d043 | 12196 | bool force_thru; |
83a57153 | 12197 | |
7546a384 ACO |
12198 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12199 | * kzalloc'd. Code that depends on any field being zero should be | |
12200 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12201 | * only fields that are know to not cause problems are preserved. */ | |
12202 | ||
83a57153 | 12203 | tmp_state = crtc_state->base; |
663a3640 | 12204 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12205 | shared_dpll = crtc_state->shared_dpll; |
12206 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12207 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12208 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12209 | |
83a57153 | 12210 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12211 | |
83a57153 | 12212 | crtc_state->base = tmp_state; |
663a3640 | 12213 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12214 | crtc_state->shared_dpll = shared_dpll; |
12215 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12216 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12217 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12218 | } |
12219 | ||
548ee15b | 12220 | static int |
b8cecdf5 | 12221 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12222 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12223 | { |
b359283a | 12224 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12225 | struct intel_encoder *encoder; |
da3ced29 | 12226 | struct drm_connector *connector; |
0b901879 | 12227 | struct drm_connector_state *connector_state; |
d328c9d7 | 12228 | int base_bpp, ret = -EINVAL; |
0b901879 | 12229 | int i; |
e29c22c0 | 12230 | bool retry = true; |
ee7b9f93 | 12231 | |
83a57153 | 12232 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12233 | |
e143a21c DV |
12234 | pipe_config->cpu_transcoder = |
12235 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12236 | |
2960bc9c ID |
12237 | /* |
12238 | * Sanitize sync polarity flags based on requested ones. If neither | |
12239 | * positive or negative polarity is requested, treat this as meaning | |
12240 | * negative polarity. | |
12241 | */ | |
2d112de7 | 12242 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12243 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12244 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12245 | |
2d112de7 | 12246 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12247 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12248 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12249 | |
d328c9d7 DV |
12250 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12251 | pipe_config); | |
12252 | if (base_bpp < 0) | |
4e53c2e0 DV |
12253 | goto fail; |
12254 | ||
e41a56be VS |
12255 | /* |
12256 | * Determine the real pipe dimensions. Note that stereo modes can | |
12257 | * increase the actual pipe size due to the frame doubling and | |
12258 | * insertion of additional space for blanks between the frame. This | |
12259 | * is stored in the crtc timings. We use the requested mode to do this | |
12260 | * computation to clearly distinguish it from the adjusted mode, which | |
12261 | * can be changed by the connectors in the below retry loop. | |
12262 | */ | |
2d112de7 | 12263 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12264 | &pipe_config->pipe_src_w, |
12265 | &pipe_config->pipe_src_h); | |
e41a56be | 12266 | |
e29c22c0 | 12267 | encoder_retry: |
ef1b460d | 12268 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12269 | pipe_config->port_clock = 0; |
ef1b460d | 12270 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12271 | |
135c81b8 | 12272 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12273 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12274 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12275 | |
7758a113 DV |
12276 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12277 | * adjust it according to limitations or connector properties, and also | |
12278 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12279 | */ |
da3ced29 | 12280 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12281 | if (connector_state->crtc != crtc) |
7758a113 | 12282 | continue; |
7ae89233 | 12283 | |
0b901879 ACO |
12284 | encoder = to_intel_encoder(connector_state->best_encoder); |
12285 | ||
efea6e8e DV |
12286 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12287 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12288 | goto fail; |
12289 | } | |
ee7b9f93 | 12290 | } |
47f1c6c9 | 12291 | |
ff9a6750 DV |
12292 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12293 | * done afterwards in case the encoder adjusts the mode. */ | |
12294 | if (!pipe_config->port_clock) | |
2d112de7 | 12295 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12296 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12297 | |
a43f6e0f | 12298 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12299 | if (ret < 0) { |
7758a113 DV |
12300 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12301 | goto fail; | |
ee7b9f93 | 12302 | } |
e29c22c0 DV |
12303 | |
12304 | if (ret == RETRY) { | |
12305 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12306 | ret = -EINVAL; | |
12307 | goto fail; | |
12308 | } | |
12309 | ||
12310 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12311 | retry = false; | |
12312 | goto encoder_retry; | |
12313 | } | |
12314 | ||
e8fa4270 DV |
12315 | /* Dithering seems to not pass-through bits correctly when it should, so |
12316 | * only enable it on 6bpc panels. */ | |
12317 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12318 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12319 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12320 | |
7758a113 | 12321 | fail: |
548ee15b | 12322 | return ret; |
ee7b9f93 | 12323 | } |
47f1c6c9 | 12324 | |
ea9d758d | 12325 | static void |
4740b0f2 | 12326 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12327 | { |
0a9ab303 ACO |
12328 | struct drm_crtc *crtc; |
12329 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12330 | int i; |
ea9d758d | 12331 | |
7668851f | 12332 | /* Double check state. */ |
8a75d157 | 12333 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12334 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12335 | |
12336 | /* Update hwmode for vblank functions */ | |
12337 | if (crtc->state->active) | |
12338 | crtc->hwmode = crtc->state->adjusted_mode; | |
12339 | else | |
12340 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12341 | |
12342 | /* | |
12343 | * Update legacy state to satisfy fbc code. This can | |
12344 | * be removed when fbc uses the atomic state. | |
12345 | */ | |
12346 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12347 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12348 | ||
12349 | crtc->primary->fb = plane_state->fb; | |
12350 | crtc->x = plane_state->src_x >> 16; | |
12351 | crtc->y = plane_state->src_y >> 16; | |
12352 | } | |
ea9d758d | 12353 | } |
ea9d758d DV |
12354 | } |
12355 | ||
3bd26263 | 12356 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12357 | { |
3bd26263 | 12358 | int diff; |
f1f644dc JB |
12359 | |
12360 | if (clock1 == clock2) | |
12361 | return true; | |
12362 | ||
12363 | if (!clock1 || !clock2) | |
12364 | return false; | |
12365 | ||
12366 | diff = abs(clock1 - clock2); | |
12367 | ||
12368 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12369 | return true; | |
12370 | ||
12371 | return false; | |
12372 | } | |
12373 | ||
25c5b266 DV |
12374 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12375 | list_for_each_entry((intel_crtc), \ | |
12376 | &(dev)->mode_config.crtc_list, \ | |
12377 | base.head) \ | |
95150bdf | 12378 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12379 | |
cfb23ed6 ML |
12380 | static bool |
12381 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12382 | unsigned int m2, unsigned int n2, | |
12383 | bool exact) | |
12384 | { | |
12385 | if (m == m2 && n == n2) | |
12386 | return true; | |
12387 | ||
12388 | if (exact || !m || !n || !m2 || !n2) | |
12389 | return false; | |
12390 | ||
12391 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12392 | ||
31d10b57 ML |
12393 | if (n > n2) { |
12394 | while (n > n2) { | |
cfb23ed6 ML |
12395 | m2 <<= 1; |
12396 | n2 <<= 1; | |
12397 | } | |
31d10b57 ML |
12398 | } else if (n < n2) { |
12399 | while (n < n2) { | |
cfb23ed6 ML |
12400 | m <<= 1; |
12401 | n <<= 1; | |
12402 | } | |
12403 | } | |
12404 | ||
31d10b57 ML |
12405 | if (n != n2) |
12406 | return false; | |
12407 | ||
12408 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12409 | } |
12410 | ||
12411 | static bool | |
12412 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12413 | struct intel_link_m_n *m2_n2, | |
12414 | bool adjust) | |
12415 | { | |
12416 | if (m_n->tu == m2_n2->tu && | |
12417 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12418 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12419 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12420 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12421 | if (adjust) | |
12422 | *m2_n2 = *m_n; | |
12423 | ||
12424 | return true; | |
12425 | } | |
12426 | ||
12427 | return false; | |
12428 | } | |
12429 | ||
0e8ffe1b | 12430 | static bool |
2fa2fe9a | 12431 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12432 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12433 | struct intel_crtc_state *pipe_config, |
12434 | bool adjust) | |
0e8ffe1b | 12435 | { |
cfb23ed6 ML |
12436 | bool ret = true; |
12437 | ||
12438 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12439 | do { \ | |
12440 | if (!adjust) \ | |
12441 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12442 | else \ | |
12443 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12444 | } while (0) | |
12445 | ||
66e985c0 DV |
12446 | #define PIPE_CONF_CHECK_X(name) \ |
12447 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12448 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12449 | "(expected 0x%08x, found 0x%08x)\n", \ |
12450 | current_config->name, \ | |
12451 | pipe_config->name); \ | |
cfb23ed6 | 12452 | ret = false; \ |
66e985c0 DV |
12453 | } |
12454 | ||
08a24034 DV |
12455 | #define PIPE_CONF_CHECK_I(name) \ |
12456 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12457 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12458 | "(expected %i, found %i)\n", \ |
12459 | current_config->name, \ | |
12460 | pipe_config->name); \ | |
cfb23ed6 ML |
12461 | ret = false; \ |
12462 | } | |
12463 | ||
8106ddbd ACO |
12464 | #define PIPE_CONF_CHECK_P(name) \ |
12465 | if (current_config->name != pipe_config->name) { \ | |
12466 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12467 | "(expected %p, found %p)\n", \ | |
12468 | current_config->name, \ | |
12469 | pipe_config->name); \ | |
12470 | ret = false; \ | |
12471 | } | |
12472 | ||
cfb23ed6 ML |
12473 | #define PIPE_CONF_CHECK_M_N(name) \ |
12474 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12475 | &pipe_config->name,\ | |
12476 | adjust)) { \ | |
12477 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12478 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12479 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12480 | current_config->name.tu, \ | |
12481 | current_config->name.gmch_m, \ | |
12482 | current_config->name.gmch_n, \ | |
12483 | current_config->name.link_m, \ | |
12484 | current_config->name.link_n, \ | |
12485 | pipe_config->name.tu, \ | |
12486 | pipe_config->name.gmch_m, \ | |
12487 | pipe_config->name.gmch_n, \ | |
12488 | pipe_config->name.link_m, \ | |
12489 | pipe_config->name.link_n); \ | |
12490 | ret = false; \ | |
12491 | } | |
12492 | ||
12493 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12494 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12495 | &pipe_config->name, adjust) && \ | |
12496 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12497 | &pipe_config->name, adjust)) { \ | |
12498 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12499 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12500 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12501 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12502 | current_config->name.tu, \ | |
12503 | current_config->name.gmch_m, \ | |
12504 | current_config->name.gmch_n, \ | |
12505 | current_config->name.link_m, \ | |
12506 | current_config->name.link_n, \ | |
12507 | current_config->alt_name.tu, \ | |
12508 | current_config->alt_name.gmch_m, \ | |
12509 | current_config->alt_name.gmch_n, \ | |
12510 | current_config->alt_name.link_m, \ | |
12511 | current_config->alt_name.link_n, \ | |
12512 | pipe_config->name.tu, \ | |
12513 | pipe_config->name.gmch_m, \ | |
12514 | pipe_config->name.gmch_n, \ | |
12515 | pipe_config->name.link_m, \ | |
12516 | pipe_config->name.link_n); \ | |
12517 | ret = false; \ | |
88adfff1 DV |
12518 | } |
12519 | ||
b95af8be VK |
12520 | /* This is required for BDW+ where there is only one set of registers for |
12521 | * switching between high and low RR. | |
12522 | * This macro can be used whenever a comparison has to be made between one | |
12523 | * hw state and multiple sw state variables. | |
12524 | */ | |
12525 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12526 | if ((current_config->name != pipe_config->name) && \ | |
12527 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12528 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12529 | "(expected %i or %i, found %i)\n", \ |
12530 | current_config->name, \ | |
12531 | current_config->alt_name, \ | |
12532 | pipe_config->name); \ | |
cfb23ed6 | 12533 | ret = false; \ |
b95af8be VK |
12534 | } |
12535 | ||
1bd1bd80 DV |
12536 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12537 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12538 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12539 | "(expected %i, found %i)\n", \ |
12540 | current_config->name & (mask), \ | |
12541 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12542 | ret = false; \ |
1bd1bd80 DV |
12543 | } |
12544 | ||
5e550656 VS |
12545 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12546 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12547 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12548 | "(expected %i, found %i)\n", \ |
12549 | current_config->name, \ | |
12550 | pipe_config->name); \ | |
cfb23ed6 | 12551 | ret = false; \ |
5e550656 VS |
12552 | } |
12553 | ||
bb760063 DV |
12554 | #define PIPE_CONF_QUIRK(quirk) \ |
12555 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12556 | ||
eccb140b DV |
12557 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12558 | ||
08a24034 DV |
12559 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12560 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12561 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12562 | |
eb14cb74 | 12563 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12564 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12565 | |
12566 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12567 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12568 | ||
cfb23ed6 ML |
12569 | if (current_config->has_drrs) |
12570 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12571 | } else | |
12572 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12573 | |
a65347ba JN |
12574 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12575 | ||
2d112de7 ACO |
12576 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12577 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12578 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12579 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12580 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12581 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12582 | |
2d112de7 ACO |
12583 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12584 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12585 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12586 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12587 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12588 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12589 | |
c93f54cf | 12590 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12591 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12592 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12593 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12594 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12595 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12596 | |
9ed109a7 DV |
12597 | PIPE_CONF_CHECK_I(has_audio); |
12598 | ||
2d112de7 | 12599 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12600 | DRM_MODE_FLAG_INTERLACE); |
12601 | ||
bb760063 | 12602 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12603 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12604 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12605 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12606 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12607 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12608 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12609 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12610 | DRM_MODE_FLAG_NVSYNC); |
12611 | } | |
045ac3b5 | 12612 | |
333b8ca8 | 12613 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12614 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12615 | if (INTEL_INFO(dev)->gen < 4) | |
12616 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12617 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12618 | |
bfd16b2a ML |
12619 | if (!adjust) { |
12620 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12621 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12622 | ||
12623 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12624 | if (current_config->pch_pfit.enabled) { | |
12625 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12626 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12627 | } | |
2fa2fe9a | 12628 | |
7aefe2b5 ML |
12629 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12630 | } | |
a1b2278e | 12631 | |
e59150dc JB |
12632 | /* BDW+ don't expose a synchronous way to read the state */ |
12633 | if (IS_HASWELL(dev)) | |
12634 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12635 | |
282740f7 VS |
12636 | PIPE_CONF_CHECK_I(double_wide); |
12637 | ||
26804afd DV |
12638 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12639 | ||
8106ddbd | 12640 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12641 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12642 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12643 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12644 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12645 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12646 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12647 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12648 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12649 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12650 | |
42571aef VS |
12651 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12652 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12653 | ||
2d112de7 | 12654 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12655 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12656 | |
66e985c0 | 12657 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12658 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12659 | #undef PIPE_CONF_CHECK_P |
b95af8be | 12660 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12661 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12662 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12663 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12664 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12665 | |
cfb23ed6 | 12666 | return ret; |
0e8ffe1b DV |
12667 | } |
12668 | ||
e3b247da VS |
12669 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12670 | const struct intel_crtc_state *pipe_config) | |
12671 | { | |
12672 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12673 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12674 | &pipe_config->fdi_m_n); |
12675 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12676 | ||
12677 | /* | |
12678 | * FDI already provided one idea for the dotclock. | |
12679 | * Yell if the encoder disagrees. | |
12680 | */ | |
12681 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12682 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12683 | fdi_dotclock, dotclock); | |
12684 | } | |
12685 | } | |
12686 | ||
08db6652 DL |
12687 | static void check_wm_state(struct drm_device *dev) |
12688 | { | |
12689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12690 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12691 | struct intel_crtc *intel_crtc; | |
12692 | int plane; | |
12693 | ||
12694 | if (INTEL_INFO(dev)->gen < 9) | |
12695 | return; | |
12696 | ||
12697 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12698 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12699 | ||
12700 | for_each_intel_crtc(dev, intel_crtc) { | |
12701 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12702 | const enum pipe pipe = intel_crtc->pipe; | |
12703 | ||
12704 | if (!intel_crtc->active) | |
12705 | continue; | |
12706 | ||
12707 | /* planes */ | |
dd740780 | 12708 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12709 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12710 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12711 | ||
12712 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12713 | continue; | |
12714 | ||
12715 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12716 | "(expected (%u,%u), found (%u,%u))\n", | |
12717 | pipe_name(pipe), plane + 1, | |
12718 | sw_entry->start, sw_entry->end, | |
12719 | hw_entry->start, hw_entry->end); | |
12720 | } | |
12721 | ||
12722 | /* cursor */ | |
4969d33e MR |
12723 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12724 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12725 | |
12726 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12727 | continue; | |
12728 | ||
12729 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12730 | "(expected (%u,%u), found (%u,%u))\n", | |
12731 | pipe_name(pipe), | |
12732 | sw_entry->start, sw_entry->end, | |
12733 | hw_entry->start, hw_entry->end); | |
12734 | } | |
12735 | } | |
12736 | ||
91d1b4bd | 12737 | static void |
35dd3c64 ML |
12738 | check_connector_state(struct drm_device *dev, |
12739 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12740 | { |
35dd3c64 ML |
12741 | struct drm_connector_state *old_conn_state; |
12742 | struct drm_connector *connector; | |
12743 | int i; | |
8af6cf88 | 12744 | |
35dd3c64 ML |
12745 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12746 | struct drm_encoder *encoder = connector->encoder; | |
12747 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12748 | |
8af6cf88 DV |
12749 | /* This also checks the encoder/connector hw state with the |
12750 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12751 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12752 | |
ad3c558f | 12753 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12754 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12755 | } |
91d1b4bd DV |
12756 | } |
12757 | ||
12758 | static void | |
12759 | check_encoder_state(struct drm_device *dev) | |
12760 | { | |
12761 | struct intel_encoder *encoder; | |
12762 | struct intel_connector *connector; | |
8af6cf88 | 12763 | |
b2784e15 | 12764 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12765 | bool enabled = false; |
4d20cd86 | 12766 | enum pipe pipe; |
8af6cf88 DV |
12767 | |
12768 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12769 | encoder->base.base.id, | |
8e329a03 | 12770 | encoder->base.name); |
8af6cf88 | 12771 | |
3a3371ff | 12772 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12773 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12774 | continue; |
12775 | enabled = true; | |
ad3c558f ML |
12776 | |
12777 | I915_STATE_WARN(connector->base.state->crtc != | |
12778 | encoder->base.crtc, | |
12779 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12780 | } |
0e32b39c | 12781 | |
e2c719b7 | 12782 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12783 | "encoder's enabled state mismatch " |
12784 | "(expected %i, found %i)\n", | |
12785 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12786 | |
12787 | if (!encoder->base.crtc) { | |
4d20cd86 | 12788 | bool active; |
7c60d198 | 12789 | |
4d20cd86 ML |
12790 | active = encoder->get_hw_state(encoder, &pipe); |
12791 | I915_STATE_WARN(active, | |
12792 | "encoder detached but still enabled on pipe %c.\n", | |
12793 | pipe_name(pipe)); | |
7c60d198 | 12794 | } |
8af6cf88 | 12795 | } |
91d1b4bd DV |
12796 | } |
12797 | ||
12798 | static void | |
4d20cd86 | 12799 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12800 | { |
fbee40df | 12801 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12802 | struct intel_encoder *encoder; |
4d20cd86 ML |
12803 | struct drm_crtc_state *old_crtc_state; |
12804 | struct drm_crtc *crtc; | |
12805 | int i; | |
8af6cf88 | 12806 | |
4d20cd86 ML |
12807 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12808 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12809 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12810 | bool active; |
8af6cf88 | 12811 | |
bfd16b2a ML |
12812 | if (!needs_modeset(crtc->state) && |
12813 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12814 | continue; |
045ac3b5 | 12815 | |
4d20cd86 ML |
12816 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12817 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12818 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12819 | pipe_config->base.crtc = crtc; | |
12820 | pipe_config->base.state = old_state; | |
8af6cf88 | 12821 | |
4d20cd86 ML |
12822 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12823 | crtc->base.id); | |
8af6cf88 | 12824 | |
4d20cd86 ML |
12825 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12826 | pipe_config); | |
d62cf62a | 12827 | |
b6b5d049 | 12828 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12829 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12830 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12831 | active = crtc->state->active; | |
6c49f241 | 12832 | |
4d20cd86 | 12833 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12834 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12835 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12836 | |
4d20cd86 | 12837 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12838 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12839 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12840 | ||
12841 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12842 | enum pipe pipe; | |
12843 | ||
12844 | active = encoder->get_hw_state(encoder, &pipe); | |
12845 | I915_STATE_WARN(active != crtc->state->active, | |
12846 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12847 | encoder->base.base.id, active, crtc->state->active); | |
12848 | ||
12849 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12850 | "Encoder connected to wrong pipe %c\n", | |
12851 | pipe_name(pipe)); | |
12852 | ||
12853 | if (active) | |
12854 | encoder->get_config(encoder, pipe_config); | |
12855 | } | |
53d9f4e9 | 12856 | |
4d20cd86 | 12857 | if (!crtc->state->active) |
cfb23ed6 ML |
12858 | continue; |
12859 | ||
e3b247da VS |
12860 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
12861 | ||
4d20cd86 ML |
12862 | sw_config = to_intel_crtc_state(crtc->state); |
12863 | if (!intel_pipe_config_compare(dev, sw_config, | |
12864 | pipe_config, false)) { | |
e2c719b7 | 12865 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12866 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12867 | "[hw state]"); |
4d20cd86 | 12868 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12869 | "[sw state]"); |
12870 | } | |
8af6cf88 DV |
12871 | } |
12872 | } | |
12873 | ||
91d1b4bd DV |
12874 | static void |
12875 | check_shared_dpll_state(struct drm_device *dev) | |
12876 | { | |
fbee40df | 12877 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12878 | struct intel_crtc *crtc; |
12879 | struct intel_dpll_hw_state dpll_hw_state; | |
12880 | int i; | |
5358901f DV |
12881 | |
12882 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8106ddbd ACO |
12883 | struct intel_shared_dpll *pll = |
12884 | intel_get_shared_dpll_by_id(dev_priv, i); | |
2dd66ebd | 12885 | unsigned enabled_crtcs = 0, active_crtcs = 0; |
5358901f DV |
12886 | bool active; |
12887 | ||
12888 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12889 | ||
12890 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12891 | ||
2edd6443 | 12892 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12893 | |
2dd66ebd ML |
12894 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
12895 | "more active pll users than references: %x vs %x\n", | |
12896 | pll->active_mask, pll->config.crtc_mask); | |
9d16da65 ACO |
12897 | |
12898 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { | |
2dd66ebd ML |
12899 | I915_STATE_WARN(!pll->on && pll->active_mask, |
12900 | "pll in active use but not on in sw tracking\n"); | |
12901 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12902 | "pll is on but not used by any active crtc\n"); | |
9d16da65 ACO |
12903 | I915_STATE_WARN(pll->on != active, |
12904 | "pll on state mismatch (expected %i, found %i)\n", | |
12905 | pll->on, active); | |
12906 | } | |
5358901f | 12907 | |
d3fcc808 | 12908 | for_each_intel_crtc(dev, crtc) { |
8106ddbd | 12909 | if (crtc->base.state->enable && crtc->config->shared_dpll == pll) |
2dd66ebd ML |
12910 | enabled_crtcs |= 1 << drm_crtc_index(&crtc->base); |
12911 | if (crtc->base.state->active && crtc->config->shared_dpll == pll) | |
12912 | active_crtcs |= 1 << drm_crtc_index(&crtc->base); | |
5358901f | 12913 | } |
2dd66ebd ML |
12914 | |
12915 | I915_STATE_WARN(pll->active_mask != active_crtcs, | |
12916 | "pll active crtcs mismatch (expected %x, found %x)\n", | |
12917 | pll->active_mask, active_crtcs); | |
12918 | I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs, | |
12919 | "pll enabled crtcs mismatch (expected %x, found %x)\n", | |
12920 | pll->config.crtc_mask, enabled_crtcs); | |
66e985c0 | 12921 | |
e2c719b7 | 12922 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12923 | sizeof(dpll_hw_state)), |
12924 | "pll hw state mismatch\n"); | |
5358901f | 12925 | } |
8af6cf88 DV |
12926 | } |
12927 | ||
ee165b1a ML |
12928 | static void |
12929 | intel_modeset_check_state(struct drm_device *dev, | |
12930 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12931 | { |
08db6652 | 12932 | check_wm_state(dev); |
35dd3c64 | 12933 | check_connector_state(dev, old_state); |
91d1b4bd | 12934 | check_encoder_state(dev); |
4d20cd86 | 12935 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12936 | check_shared_dpll_state(dev); |
12937 | } | |
12938 | ||
80715b2f VS |
12939 | static void update_scanline_offset(struct intel_crtc *crtc) |
12940 | { | |
12941 | struct drm_device *dev = crtc->base.dev; | |
12942 | ||
12943 | /* | |
12944 | * The scanline counter increments at the leading edge of hsync. | |
12945 | * | |
12946 | * On most platforms it starts counting from vtotal-1 on the | |
12947 | * first active line. That means the scanline counter value is | |
12948 | * always one less than what we would expect. Ie. just after | |
12949 | * start of vblank, which also occurs at start of hsync (on the | |
12950 | * last active line), the scanline counter will read vblank_start-1. | |
12951 | * | |
12952 | * On gen2 the scanline counter starts counting from 1 instead | |
12953 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12954 | * to keep the value positive), instead of adding one. | |
12955 | * | |
12956 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12957 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12958 | * there's an extra 1 line difference. So we need to add two instead of | |
12959 | * one to the value. | |
12960 | */ | |
12961 | if (IS_GEN2(dev)) { | |
124abe07 | 12962 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12963 | int vtotal; |
12964 | ||
124abe07 VS |
12965 | vtotal = adjusted_mode->crtc_vtotal; |
12966 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12967 | vtotal /= 2; |
12968 | ||
12969 | crtc->scanline_offset = vtotal - 1; | |
12970 | } else if (HAS_DDI(dev) && | |
409ee761 | 12971 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12972 | crtc->scanline_offset = 2; |
12973 | } else | |
12974 | crtc->scanline_offset = 1; | |
12975 | } | |
12976 | ||
ad421372 | 12977 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12978 | { |
225da59b | 12979 | struct drm_device *dev = state->dev; |
ed6739ef | 12980 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12981 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
12982 | struct drm_crtc *crtc; |
12983 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12984 | int i; |
ed6739ef ACO |
12985 | |
12986 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12987 | return; |
ed6739ef | 12988 | |
0a9ab303 | 12989 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 12990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
12991 | struct intel_shared_dpll *old_dpll = |
12992 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 12993 | |
fb1a38a9 | 12994 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
12995 | continue; |
12996 | ||
8106ddbd | 12997 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12998 | |
8106ddbd | 12999 | if (!old_dpll) |
fb1a38a9 | 13000 | continue; |
0a9ab303 | 13001 | |
ad421372 ML |
13002 | if (!shared_dpll) |
13003 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13004 | |
8106ddbd | 13005 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13006 | } |
ed6739ef ACO |
13007 | } |
13008 | ||
99d736a2 ML |
13009 | /* |
13010 | * This implements the workaround described in the "notes" section of the mode | |
13011 | * set sequence documentation. When going from no pipes or single pipe to | |
13012 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13013 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13014 | */ | |
13015 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13016 | { | |
13017 | struct drm_crtc_state *crtc_state; | |
13018 | struct intel_crtc *intel_crtc; | |
13019 | struct drm_crtc *crtc; | |
13020 | struct intel_crtc_state *first_crtc_state = NULL; | |
13021 | struct intel_crtc_state *other_crtc_state = NULL; | |
13022 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13023 | int i; | |
13024 | ||
13025 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13026 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13027 | intel_crtc = to_intel_crtc(crtc); | |
13028 | ||
13029 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13030 | continue; | |
13031 | ||
13032 | if (first_crtc_state) { | |
13033 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13034 | break; | |
13035 | } else { | |
13036 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13037 | first_pipe = intel_crtc->pipe; | |
13038 | } | |
13039 | } | |
13040 | ||
13041 | /* No workaround needed? */ | |
13042 | if (!first_crtc_state) | |
13043 | return 0; | |
13044 | ||
13045 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13046 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13047 | struct intel_crtc_state *pipe_config; | |
13048 | ||
13049 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13050 | if (IS_ERR(pipe_config)) | |
13051 | return PTR_ERR(pipe_config); | |
13052 | ||
13053 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13054 | ||
13055 | if (!pipe_config->base.active || | |
13056 | needs_modeset(&pipe_config->base)) | |
13057 | continue; | |
13058 | ||
13059 | /* 2 or more enabled crtcs means no need for w/a */ | |
13060 | if (enabled_pipe != INVALID_PIPE) | |
13061 | return 0; | |
13062 | ||
13063 | enabled_pipe = intel_crtc->pipe; | |
13064 | } | |
13065 | ||
13066 | if (enabled_pipe != INVALID_PIPE) | |
13067 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13068 | else if (other_crtc_state) | |
13069 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13070 | ||
13071 | return 0; | |
13072 | } | |
13073 | ||
27c329ed ML |
13074 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13075 | { | |
13076 | struct drm_crtc *crtc; | |
13077 | struct drm_crtc_state *crtc_state; | |
13078 | int ret = 0; | |
13079 | ||
13080 | /* add all active pipes to the state */ | |
13081 | for_each_crtc(state->dev, crtc) { | |
13082 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13083 | if (IS_ERR(crtc_state)) | |
13084 | return PTR_ERR(crtc_state); | |
13085 | ||
13086 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13087 | continue; | |
13088 | ||
13089 | crtc_state->mode_changed = true; | |
13090 | ||
13091 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13092 | if (ret) | |
13093 | break; | |
13094 | ||
13095 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13096 | if (ret) | |
13097 | break; | |
13098 | } | |
13099 | ||
13100 | return ret; | |
13101 | } | |
13102 | ||
c347a676 | 13103 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13104 | { |
565602d7 ML |
13105 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13106 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13107 | struct drm_crtc *crtc; | |
13108 | struct drm_crtc_state *crtc_state; | |
13109 | int ret = 0, i; | |
054518dd | 13110 | |
b359283a ML |
13111 | if (!check_digital_port_conflicts(state)) { |
13112 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13113 | return -EINVAL; | |
13114 | } | |
13115 | ||
565602d7 ML |
13116 | intel_state->modeset = true; |
13117 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13118 | ||
13119 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13120 | if (crtc_state->active) | |
13121 | intel_state->active_crtcs |= 1 << i; | |
13122 | else | |
13123 | intel_state->active_crtcs &= ~(1 << i); | |
13124 | } | |
13125 | ||
054518dd ACO |
13126 | /* |
13127 | * See if the config requires any additional preparation, e.g. | |
13128 | * to adjust global state with pipes off. We need to do this | |
13129 | * here so we can get the modeset_pipe updated config for the new | |
13130 | * mode set on this crtc. For other crtcs we need to use the | |
13131 | * adjusted_mode bits in the crtc directly. | |
13132 | */ | |
27c329ed | 13133 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13134 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13135 | ||
1a617b77 | 13136 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13137 | ret = intel_modeset_all_pipes(state); |
13138 | ||
13139 | if (ret < 0) | |
054518dd | 13140 | return ret; |
e8788cbc ML |
13141 | |
13142 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13143 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13144 | } else |
1a617b77 | 13145 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13146 | |
ad421372 | 13147 | intel_modeset_clear_plls(state); |
054518dd | 13148 | |
565602d7 | 13149 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13150 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13151 | |
ad421372 | 13152 | return 0; |
c347a676 ACO |
13153 | } |
13154 | ||
aa363136 MR |
13155 | /* |
13156 | * Handle calculation of various watermark data at the end of the atomic check | |
13157 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13158 | * handlers to ensure that all derived state has been updated. | |
13159 | */ | |
13160 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13161 | { | |
13162 | struct drm_device *dev = state->dev; | |
13163 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13164 | struct drm_crtc *crtc; | |
13165 | struct drm_crtc_state *cstate; | |
13166 | struct drm_plane *plane; | |
13167 | struct drm_plane_state *pstate; | |
13168 | ||
13169 | /* | |
13170 | * Calculate watermark configuration details now that derived | |
13171 | * plane/crtc state is all properly updated. | |
13172 | */ | |
13173 | drm_for_each_crtc(crtc, dev) { | |
13174 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13175 | crtc->state; | |
13176 | ||
13177 | if (cstate->active) | |
13178 | intel_state->wm_config.num_pipes_active++; | |
13179 | } | |
13180 | drm_for_each_legacy_plane(plane, dev) { | |
13181 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13182 | plane->state; | |
13183 | ||
13184 | if (!to_intel_plane_state(pstate)->visible) | |
13185 | continue; | |
13186 | ||
13187 | intel_state->wm_config.sprites_enabled = true; | |
13188 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13189 | pstate->crtc_h != pstate->src_h >> 16) | |
13190 | intel_state->wm_config.sprites_scaled = true; | |
13191 | } | |
13192 | } | |
13193 | ||
74c090b1 ML |
13194 | /** |
13195 | * intel_atomic_check - validate state object | |
13196 | * @dev: drm device | |
13197 | * @state: state to validate | |
13198 | */ | |
13199 | static int intel_atomic_check(struct drm_device *dev, | |
13200 | struct drm_atomic_state *state) | |
c347a676 | 13201 | { |
dd8b3bdb | 13202 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13203 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13204 | struct drm_crtc *crtc; |
13205 | struct drm_crtc_state *crtc_state; | |
13206 | int ret, i; | |
61333b60 | 13207 | bool any_ms = false; |
c347a676 | 13208 | |
74c090b1 | 13209 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13210 | if (ret) |
13211 | return ret; | |
13212 | ||
c347a676 | 13213 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13214 | struct intel_crtc_state *pipe_config = |
13215 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13216 | |
13217 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13218 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13219 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13220 | |
61333b60 ML |
13221 | if (!crtc_state->enable) { |
13222 | if (needs_modeset(crtc_state)) | |
13223 | any_ms = true; | |
c347a676 | 13224 | continue; |
61333b60 | 13225 | } |
c347a676 | 13226 | |
26495481 | 13227 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13228 | continue; |
13229 | ||
26495481 DV |
13230 | /* FIXME: For only active_changed we shouldn't need to do any |
13231 | * state recomputation at all. */ | |
13232 | ||
1ed51de9 DV |
13233 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13234 | if (ret) | |
13235 | return ret; | |
b359283a | 13236 | |
cfb23ed6 | 13237 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13238 | if (ret) |
13239 | return ret; | |
13240 | ||
73831236 | 13241 | if (i915.fastboot && |
dd8b3bdb | 13242 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13243 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13244 | pipe_config, true)) { |
26495481 | 13245 | crtc_state->mode_changed = false; |
bfd16b2a | 13246 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13247 | } |
13248 | ||
13249 | if (needs_modeset(crtc_state)) { | |
13250 | any_ms = true; | |
cfb23ed6 ML |
13251 | |
13252 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13253 | if (ret) | |
13254 | return ret; | |
13255 | } | |
61333b60 | 13256 | |
26495481 DV |
13257 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13258 | needs_modeset(crtc_state) ? | |
13259 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13260 | } |
13261 | ||
61333b60 ML |
13262 | if (any_ms) { |
13263 | ret = intel_modeset_checks(state); | |
13264 | ||
13265 | if (ret) | |
13266 | return ret; | |
27c329ed | 13267 | } else |
dd8b3bdb | 13268 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13269 | |
dd8b3bdb | 13270 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13271 | if (ret) |
13272 | return ret; | |
13273 | ||
f51be2e0 | 13274 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13275 | calc_watermark_data(state); |
13276 | ||
13277 | return 0; | |
054518dd ACO |
13278 | } |
13279 | ||
5008e874 ML |
13280 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13281 | struct drm_atomic_state *state, | |
13282 | bool async) | |
13283 | { | |
7580d774 ML |
13284 | struct drm_i915_private *dev_priv = dev->dev_private; |
13285 | struct drm_plane_state *plane_state; | |
5008e874 | 13286 | struct drm_crtc_state *crtc_state; |
7580d774 | 13287 | struct drm_plane *plane; |
5008e874 ML |
13288 | struct drm_crtc *crtc; |
13289 | int i, ret; | |
13290 | ||
13291 | if (async) { | |
13292 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13293 | return -EINVAL; | |
13294 | } | |
13295 | ||
13296 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13297 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13298 | if (ret) | |
13299 | return ret; | |
7580d774 ML |
13300 | |
13301 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13302 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13303 | } |
13304 | ||
f935675f ML |
13305 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13306 | if (ret) | |
13307 | return ret; | |
13308 | ||
5008e874 | 13309 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13310 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13311 | u32 reset_counter; | |
13312 | ||
13313 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13314 | mutex_unlock(&dev->struct_mutex); | |
13315 | ||
13316 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13317 | struct intel_plane_state *intel_plane_state = | |
13318 | to_intel_plane_state(plane_state); | |
13319 | ||
13320 | if (!intel_plane_state->wait_req) | |
13321 | continue; | |
13322 | ||
13323 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13324 | reset_counter, true, | |
13325 | NULL, NULL); | |
13326 | ||
13327 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13328 | if (ret == -EIO) | |
13329 | ret = 0; | |
13330 | ||
13331 | if (ret) | |
13332 | break; | |
13333 | } | |
13334 | ||
13335 | if (!ret) | |
13336 | return 0; | |
13337 | ||
13338 | mutex_lock(&dev->struct_mutex); | |
13339 | drm_atomic_helper_cleanup_planes(dev, state); | |
13340 | } | |
5008e874 | 13341 | |
f935675f | 13342 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13343 | return ret; |
13344 | } | |
13345 | ||
e8861675 ML |
13346 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13347 | struct drm_i915_private *dev_priv, | |
13348 | unsigned crtc_mask) | |
13349 | { | |
13350 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13351 | enum pipe pipe; | |
13352 | int ret; | |
13353 | ||
13354 | if (!crtc_mask) | |
13355 | return; | |
13356 | ||
13357 | for_each_pipe(dev_priv, pipe) { | |
13358 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13359 | ||
13360 | if (!((1 << pipe) & crtc_mask)) | |
13361 | continue; | |
13362 | ||
13363 | ret = drm_crtc_vblank_get(crtc); | |
13364 | if (WARN_ON(ret != 0)) { | |
13365 | crtc_mask &= ~(1 << pipe); | |
13366 | continue; | |
13367 | } | |
13368 | ||
13369 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13370 | } | |
13371 | ||
13372 | for_each_pipe(dev_priv, pipe) { | |
13373 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13374 | long lret; | |
13375 | ||
13376 | if (!((1 << pipe) & crtc_mask)) | |
13377 | continue; | |
13378 | ||
13379 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13380 | last_vblank_count[pipe] != | |
13381 | drm_crtc_vblank_count(crtc), | |
13382 | msecs_to_jiffies(50)); | |
13383 | ||
13384 | WARN_ON(!lret); | |
13385 | ||
13386 | drm_crtc_vblank_put(crtc); | |
13387 | } | |
13388 | } | |
13389 | ||
13390 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13391 | { | |
13392 | /* fb updated, need to unpin old fb */ | |
13393 | if (crtc_state->fb_changed) | |
13394 | return true; | |
13395 | ||
13396 | /* wm changes, need vblank before final wm's */ | |
caed361d | 13397 | if (crtc_state->update_wm_post) |
e8861675 ML |
13398 | return true; |
13399 | ||
13400 | /* | |
13401 | * cxsr is re-enabled after vblank. | |
caed361d | 13402 | * This is already handled by crtc_state->update_wm_post, |
e8861675 ML |
13403 | * but added for clarity. |
13404 | */ | |
13405 | if (crtc_state->disable_cxsr) | |
13406 | return true; | |
13407 | ||
13408 | return false; | |
13409 | } | |
13410 | ||
74c090b1 ML |
13411 | /** |
13412 | * intel_atomic_commit - commit validated state object | |
13413 | * @dev: DRM device | |
13414 | * @state: the top-level driver state object | |
13415 | * @async: asynchronous commit | |
13416 | * | |
13417 | * This function commits a top-level state object that has been validated | |
13418 | * with drm_atomic_helper_check(). | |
13419 | * | |
13420 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13421 | * we can only handle plane-related operations and do not yet support | |
13422 | * asynchronous commit. | |
13423 | * | |
13424 | * RETURNS | |
13425 | * Zero for success or -errno. | |
13426 | */ | |
13427 | static int intel_atomic_commit(struct drm_device *dev, | |
13428 | struct drm_atomic_state *state, | |
13429 | bool async) | |
a6778b3c | 13430 | { |
565602d7 | 13431 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13432 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13433 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13434 | struct drm_crtc *crtc; |
ed4a6a7c | 13435 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13436 | int ret = 0, i; |
13437 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13438 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13439 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13440 | |
5008e874 | 13441 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13442 | if (ret) { |
13443 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13444 | return ret; |
7580d774 | 13445 | } |
d4afb8cc | 13446 | |
1c5e19f8 | 13447 | drm_atomic_helper_swap_state(dev, state); |
a1475e77 ML |
13448 | dev_priv->wm.config = intel_state->wm_config; |
13449 | intel_shared_dpll_commit(state); | |
1c5e19f8 | 13450 | |
565602d7 ML |
13451 | if (intel_state->modeset) { |
13452 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13453 | sizeof(intel_state->min_pixclk)); | |
13454 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13455 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13456 | |
13457 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13458 | } |
13459 | ||
29ceb0e6 | 13460 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13461 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13462 | ||
33c8df89 ML |
13463 | if (needs_modeset(crtc->state) || |
13464 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13465 | hw_check = true; | |
13466 | ||
13467 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13468 | modeset_get_crtc_power_domains(crtc, | |
13469 | to_intel_crtc_state(crtc->state)); | |
13470 | } | |
13471 | ||
61333b60 ML |
13472 | if (!needs_modeset(crtc->state)) |
13473 | continue; | |
13474 | ||
29ceb0e6 | 13475 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13476 | |
29ceb0e6 VS |
13477 | if (old_crtc_state->active) { |
13478 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13479 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13480 | intel_crtc->active = false; |
58f9c0bc | 13481 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13482 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13483 | |
13484 | /* | |
13485 | * Underruns don't always raise | |
13486 | * interrupts, so check manually. | |
13487 | */ | |
13488 | intel_check_cpu_fifo_underruns(dev_priv); | |
13489 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13490 | |
13491 | if (!crtc->state->active) | |
13492 | intel_update_watermarks(crtc); | |
a539205a | 13493 | } |
b8cecdf5 | 13494 | } |
7758a113 | 13495 | |
ea9d758d DV |
13496 | /* Only after disabling all output pipelines that will be changed can we |
13497 | * update the the output configuration. */ | |
4740b0f2 | 13498 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13499 | |
565602d7 | 13500 | if (intel_state->modeset) { |
4740b0f2 | 13501 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13502 | |
13503 | if (dev_priv->display.modeset_commit_cdclk && | |
13504 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13505 | dev_priv->display.modeset_commit_cdclk(state); | |
4740b0f2 | 13506 | } |
47fab737 | 13507 | |
a6778b3c | 13508 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13509 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13511 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13512 | struct intel_crtc_state *pipe_config = |
13513 | to_intel_crtc_state(crtc->state); | |
13514 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13515 | |
f6ac4b2a | 13516 | if (modeset && crtc->state->active) { |
a539205a ML |
13517 | update_scanline_offset(to_intel_crtc(crtc)); |
13518 | dev_priv->display.crtc_enable(crtc); | |
13519 | } | |
80715b2f | 13520 | |
82cf435b LL |
13521 | if (!modeset && |
13522 | crtc->state->active && | |
13523 | crtc->state->color_mgmt_changed) { | |
13524 | /* | |
13525 | * Only update color management when not doing | |
13526 | * a modeset as this will be done by | |
13527 | * crtc_enable already. | |
13528 | */ | |
13529 | intel_color_set_csc(crtc); | |
13530 | intel_color_load_luts(crtc); | |
13531 | } | |
13532 | ||
f6ac4b2a | 13533 | if (!modeset) |
29ceb0e6 | 13534 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13535 | |
31ae71fc ML |
13536 | if (crtc->state->active && |
13537 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
49227c4a PZ |
13538 | intel_fbc_enable(intel_crtc); |
13539 | ||
6173ee28 ML |
13540 | if (crtc->state->active && |
13541 | (crtc->state->planes_changed || update_pipe)) | |
29ceb0e6 | 13542 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
bfd16b2a | 13543 | |
e8861675 ML |
13544 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13545 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13546 | } |
a6778b3c | 13547 | |
a6778b3c | 13548 | /* FIXME: add subpixel order */ |
83a57153 | 13549 | |
e8861675 ML |
13550 | if (!state->legacy_cursor_update) |
13551 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13552 | |
ed4a6a7c MR |
13553 | /* |
13554 | * Now that the vblank has passed, we can go ahead and program the | |
13555 | * optimal watermarks on platforms that need two-step watermark | |
13556 | * programming. | |
13557 | * | |
13558 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13559 | */ | |
29ceb0e6 | 13560 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
ed4a6a7c MR |
13561 | intel_cstate = to_intel_crtc_state(crtc->state); |
13562 | ||
13563 | if (dev_priv->display.optimize_watermarks) | |
13564 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13565 | } | |
13566 | ||
177246a8 MR |
13567 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
13568 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13569 | ||
13570 | if (put_domains[i]) | |
13571 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13572 | } | |
13573 | ||
13574 | if (intel_state->modeset) | |
13575 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13576 | ||
f935675f | 13577 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13578 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13579 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13580 | |
565602d7 | 13581 | if (hw_check) |
ee165b1a ML |
13582 | intel_modeset_check_state(dev, state); |
13583 | ||
13584 | drm_atomic_state_free(state); | |
f30da187 | 13585 | |
75714940 MK |
13586 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13587 | * of triggering bugs in unclaimed access. After we finish | |
13588 | * modesetting, see if an error has been flagged, and if so | |
13589 | * enable debugging for the next modeset - and hope we catch | |
13590 | * the culprit. | |
13591 | * | |
13592 | * XXX note that we assume display power is on at this point. | |
13593 | * This might hold true now but we need to add pm helper to check | |
13594 | * unclaimed only when the hardware is on, as atomic commits | |
13595 | * can happen also when the device is completely off. | |
13596 | */ | |
13597 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13598 | ||
74c090b1 | 13599 | return 0; |
7f27126e JB |
13600 | } |
13601 | ||
c0c36b94 CW |
13602 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13603 | { | |
83a57153 ACO |
13604 | struct drm_device *dev = crtc->dev; |
13605 | struct drm_atomic_state *state; | |
e694eb02 | 13606 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13607 | int ret; |
83a57153 ACO |
13608 | |
13609 | state = drm_atomic_state_alloc(dev); | |
13610 | if (!state) { | |
e694eb02 | 13611 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13612 | crtc->base.id); |
13613 | return; | |
13614 | } | |
13615 | ||
e694eb02 | 13616 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13617 | |
e694eb02 ML |
13618 | retry: |
13619 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13620 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13621 | if (!ret) { | |
13622 | if (!crtc_state->active) | |
13623 | goto out; | |
83a57153 | 13624 | |
e694eb02 | 13625 | crtc_state->mode_changed = true; |
74c090b1 | 13626 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13627 | } |
13628 | ||
e694eb02 ML |
13629 | if (ret == -EDEADLK) { |
13630 | drm_atomic_state_clear(state); | |
13631 | drm_modeset_backoff(state->acquire_ctx); | |
13632 | goto retry; | |
4ed9fb37 | 13633 | } |
4be07317 | 13634 | |
2bfb4627 | 13635 | if (ret) |
e694eb02 | 13636 | out: |
2bfb4627 | 13637 | drm_atomic_state_free(state); |
c0c36b94 CW |
13638 | } |
13639 | ||
25c5b266 DV |
13640 | #undef for_each_intel_crtc_masked |
13641 | ||
f6e5b160 | 13642 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13643 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13644 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13645 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 CW |
13646 | .destroy = intel_crtc_destroy, |
13647 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13648 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13649 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13650 | }; |
13651 | ||
6beb8c23 MR |
13652 | /** |
13653 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13654 | * @plane: drm plane to prepare for | |
13655 | * @fb: framebuffer to prepare for presentation | |
13656 | * | |
13657 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13658 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13659 | * bits. Some older platforms need special physical address handling for | |
13660 | * cursor planes. | |
13661 | * | |
f935675f ML |
13662 | * Must be called with struct_mutex held. |
13663 | * | |
6beb8c23 MR |
13664 | * Returns 0 on success, negative error code on failure. |
13665 | */ | |
13666 | int | |
13667 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13668 | const struct drm_plane_state *new_state) |
465c120c MR |
13669 | { |
13670 | struct drm_device *dev = plane->dev; | |
844f9111 | 13671 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13672 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13673 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13674 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13675 | int ret = 0; |
465c120c | 13676 | |
1ee49399 | 13677 | if (!obj && !old_obj) |
465c120c MR |
13678 | return 0; |
13679 | ||
5008e874 ML |
13680 | if (old_obj) { |
13681 | struct drm_crtc_state *crtc_state = | |
13682 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13683 | ||
13684 | /* Big Hammer, we also need to ensure that any pending | |
13685 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13686 | * current scanout is retired before unpinning the old | |
13687 | * framebuffer. Note that we rely on userspace rendering | |
13688 | * into the buffer attached to the pipe they are waiting | |
13689 | * on. If not, userspace generates a GPU hang with IPEHR | |
13690 | * point to the MI_WAIT_FOR_EVENT. | |
13691 | * | |
13692 | * This should only fail upon a hung GPU, in which case we | |
13693 | * can safely continue. | |
13694 | */ | |
13695 | if (needs_modeset(crtc_state)) | |
13696 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13697 | ||
13698 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13699 | if (ret && ret != -EIO) | |
f935675f | 13700 | return ret; |
5008e874 ML |
13701 | } |
13702 | ||
3c28ff22 AG |
13703 | /* For framebuffer backed by dmabuf, wait for fence */ |
13704 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13705 | long lret; |
13706 | ||
13707 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13708 | false, true, | |
13709 | MAX_SCHEDULE_TIMEOUT); | |
13710 | if (lret == -ERESTARTSYS) | |
13711 | return lret; | |
3c28ff22 | 13712 | |
bcf8be27 | 13713 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13714 | } |
13715 | ||
1ee49399 ML |
13716 | if (!obj) { |
13717 | ret = 0; | |
13718 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13719 | INTEL_INFO(dev)->cursor_needs_physical) { |
13720 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13721 | ret = i915_gem_object_attach_phys(obj, align); | |
13722 | if (ret) | |
13723 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13724 | } else { | |
3465c580 | 13725 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 13726 | } |
465c120c | 13727 | |
7580d774 ML |
13728 | if (ret == 0) { |
13729 | if (obj) { | |
13730 | struct intel_plane_state *plane_state = | |
13731 | to_intel_plane_state(new_state); | |
13732 | ||
13733 | i915_gem_request_assign(&plane_state->wait_req, | |
13734 | obj->last_write_req); | |
13735 | } | |
13736 | ||
a9ff8714 | 13737 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13738 | } |
fdd508a6 | 13739 | |
6beb8c23 MR |
13740 | return ret; |
13741 | } | |
13742 | ||
38f3ce3a MR |
13743 | /** |
13744 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13745 | * @plane: drm plane to clean up for | |
13746 | * @fb: old framebuffer that was on plane | |
13747 | * | |
13748 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13749 | * |
13750 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13751 | */ |
13752 | void | |
13753 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13754 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13755 | { |
13756 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13757 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13758 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13759 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13760 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13761 | |
7580d774 ML |
13762 | old_intel_state = to_intel_plane_state(old_state); |
13763 | ||
1ee49399 | 13764 | if (!obj && !old_obj) |
38f3ce3a MR |
13765 | return; |
13766 | ||
1ee49399 ML |
13767 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13768 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 13769 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
13770 | |
13771 | /* prepare_fb aborted? */ | |
13772 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13773 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13774 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13775 | |
13776 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
13777 | } |
13778 | ||
6156a456 CK |
13779 | int |
13780 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13781 | { | |
13782 | int max_scale; | |
13783 | struct drm_device *dev; | |
13784 | struct drm_i915_private *dev_priv; | |
13785 | int crtc_clock, cdclk; | |
13786 | ||
bf8a0af0 | 13787 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13788 | return DRM_PLANE_HELPER_NO_SCALING; |
13789 | ||
13790 | dev = intel_crtc->base.dev; | |
13791 | dev_priv = dev->dev_private; | |
13792 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13793 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13794 | |
54bf1ce6 | 13795 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13796 | return DRM_PLANE_HELPER_NO_SCALING; |
13797 | ||
13798 | /* | |
13799 | * skl max scale is lower of: | |
13800 | * close to 3 but not 3, -1 is for that purpose | |
13801 | * or | |
13802 | * cdclk/crtc_clock | |
13803 | */ | |
13804 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13805 | ||
13806 | return max_scale; | |
13807 | } | |
13808 | ||
465c120c | 13809 | static int |
3c692a41 | 13810 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13811 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13812 | struct intel_plane_state *state) |
13813 | { | |
2b875c22 MR |
13814 | struct drm_crtc *crtc = state->base.crtc; |
13815 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13816 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13817 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13818 | bool can_position = false; | |
465c120c | 13819 | |
693bdc28 VS |
13820 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13821 | /* use scaler when colorkey is not required */ | |
13822 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13823 | min_scale = 1; | |
13824 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13825 | } | |
d8106366 | 13826 | can_position = true; |
6156a456 | 13827 | } |
d8106366 | 13828 | |
061e4b8d ML |
13829 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13830 | &state->dst, &state->clip, | |
da20eabd ML |
13831 | min_scale, max_scale, |
13832 | can_position, true, | |
13833 | &state->visible); | |
14af293f GP |
13834 | } |
13835 | ||
613d2b27 ML |
13836 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13837 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13838 | { |
32b7eeec | 13839 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13841 | struct intel_crtc_state *old_intel_state = |
13842 | to_intel_crtc_state(old_crtc_state); | |
13843 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13844 | |
c34c9ee4 | 13845 | /* Perform vblank evasion around commit operation */ |
62852622 | 13846 | intel_pipe_update_start(intel_crtc); |
0583236e | 13847 | |
bfd16b2a ML |
13848 | if (modeset) |
13849 | return; | |
13850 | ||
13851 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13852 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13853 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13854 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13855 | } |
13856 | ||
613d2b27 ML |
13857 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13858 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13859 | { |
32b7eeec | 13860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13861 | |
62852622 | 13862 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13863 | } |
13864 | ||
cf4c7c12 | 13865 | /** |
4a3b8769 MR |
13866 | * intel_plane_destroy - destroy a plane |
13867 | * @plane: plane to destroy | |
cf4c7c12 | 13868 | * |
4a3b8769 MR |
13869 | * Common destruction function for all types of planes (primary, cursor, |
13870 | * sprite). | |
cf4c7c12 | 13871 | */ |
4a3b8769 | 13872 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13873 | { |
13874 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13875 | drm_plane_cleanup(plane); | |
13876 | kfree(intel_plane); | |
13877 | } | |
13878 | ||
65a3fea0 | 13879 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13880 | .update_plane = drm_atomic_helper_update_plane, |
13881 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13882 | .destroy = intel_plane_destroy, |
c196e1d6 | 13883 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13884 | .atomic_get_property = intel_plane_atomic_get_property, |
13885 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13886 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13887 | .atomic_destroy_state = intel_plane_destroy_state, | |
13888 | ||
465c120c MR |
13889 | }; |
13890 | ||
13891 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13892 | int pipe) | |
13893 | { | |
13894 | struct intel_plane *primary; | |
8e7d688b | 13895 | struct intel_plane_state *state; |
465c120c | 13896 | const uint32_t *intel_primary_formats; |
45e3743a | 13897 | unsigned int num_formats; |
465c120c MR |
13898 | |
13899 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13900 | if (primary == NULL) | |
13901 | return NULL; | |
13902 | ||
8e7d688b MR |
13903 | state = intel_create_plane_state(&primary->base); |
13904 | if (!state) { | |
ea2c67bb MR |
13905 | kfree(primary); |
13906 | return NULL; | |
13907 | } | |
8e7d688b | 13908 | primary->base.state = &state->base; |
ea2c67bb | 13909 | |
465c120c MR |
13910 | primary->can_scale = false; |
13911 | primary->max_downscale = 1; | |
6156a456 CK |
13912 | if (INTEL_INFO(dev)->gen >= 9) { |
13913 | primary->can_scale = true; | |
af99ceda | 13914 | state->scaler_id = -1; |
6156a456 | 13915 | } |
465c120c MR |
13916 | primary->pipe = pipe; |
13917 | primary->plane = pipe; | |
a9ff8714 | 13918 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13919 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
13920 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13921 | primary->plane = !pipe; | |
13922 | ||
6c0fd451 DL |
13923 | if (INTEL_INFO(dev)->gen >= 9) { |
13924 | intel_primary_formats = skl_primary_formats; | |
13925 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13926 | |
13927 | primary->update_plane = skylake_update_primary_plane; | |
13928 | primary->disable_plane = skylake_disable_primary_plane; | |
13929 | } else if (HAS_PCH_SPLIT(dev)) { | |
13930 | intel_primary_formats = i965_primary_formats; | |
13931 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13932 | ||
13933 | primary->update_plane = ironlake_update_primary_plane; | |
13934 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 13935 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
13936 | intel_primary_formats = i965_primary_formats; |
13937 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13938 | |
13939 | primary->update_plane = i9xx_update_primary_plane; | |
13940 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13941 | } else { |
13942 | intel_primary_formats = i8xx_primary_formats; | |
13943 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13944 | |
13945 | primary->update_plane = i9xx_update_primary_plane; | |
13946 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13947 | } |
13948 | ||
13949 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13950 | &intel_plane_funcs, |
465c120c | 13951 | intel_primary_formats, num_formats, |
b0b3b795 | 13952 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 13953 | |
3b7a5119 SJ |
13954 | if (INTEL_INFO(dev)->gen >= 4) |
13955 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13956 | |
ea2c67bb MR |
13957 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13958 | ||
465c120c MR |
13959 | return &primary->base; |
13960 | } | |
13961 | ||
3b7a5119 SJ |
13962 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13963 | { | |
13964 | if (!dev->mode_config.rotation_property) { | |
13965 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13966 | BIT(DRM_ROTATE_180); | |
13967 | ||
13968 | if (INTEL_INFO(dev)->gen >= 9) | |
13969 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13970 | ||
13971 | dev->mode_config.rotation_property = | |
13972 | drm_mode_create_rotation_property(dev, flags); | |
13973 | } | |
13974 | if (dev->mode_config.rotation_property) | |
13975 | drm_object_attach_property(&plane->base.base, | |
13976 | dev->mode_config.rotation_property, | |
13977 | plane->base.state->rotation); | |
13978 | } | |
13979 | ||
3d7d6510 | 13980 | static int |
852e787c | 13981 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13982 | struct intel_crtc_state *crtc_state, |
852e787c | 13983 | struct intel_plane_state *state) |
3d7d6510 | 13984 | { |
061e4b8d | 13985 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13986 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13987 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 13988 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
13989 | unsigned stride; |
13990 | int ret; | |
3d7d6510 | 13991 | |
061e4b8d ML |
13992 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13993 | &state->dst, &state->clip, | |
3d7d6510 MR |
13994 | DRM_PLANE_HELPER_NO_SCALING, |
13995 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13996 | true, true, &state->visible); |
757f9a3e GP |
13997 | if (ret) |
13998 | return ret; | |
13999 | ||
757f9a3e GP |
14000 | /* if we want to turn off the cursor ignore width and height */ |
14001 | if (!obj) | |
da20eabd | 14002 | return 0; |
757f9a3e | 14003 | |
757f9a3e | 14004 | /* Check for which cursor types we support */ |
061e4b8d | 14005 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14006 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14007 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14008 | return -EINVAL; |
14009 | } | |
14010 | ||
ea2c67bb MR |
14011 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14012 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14013 | DRM_DEBUG_KMS("buffer is too small\n"); |
14014 | return -ENOMEM; | |
14015 | } | |
14016 | ||
3a656b54 | 14017 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14018 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14019 | return -EINVAL; |
32b7eeec MR |
14020 | } |
14021 | ||
b29ec92c VS |
14022 | /* |
14023 | * There's something wrong with the cursor on CHV pipe C. | |
14024 | * If it straddles the left edge of the screen then | |
14025 | * moving it away from the edge or disabling it often | |
14026 | * results in a pipe underrun, and often that can lead to | |
14027 | * dead pipe (constant underrun reported, and it scans | |
14028 | * out just a solid color). To recover from that, the | |
14029 | * display power well must be turned off and on again. | |
14030 | * Refuse the put the cursor into that compromised position. | |
14031 | */ | |
14032 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14033 | state->visible && state->base.crtc_x < 0) { | |
14034 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14035 | return -EINVAL; | |
14036 | } | |
14037 | ||
da20eabd | 14038 | return 0; |
852e787c | 14039 | } |
3d7d6510 | 14040 | |
a8ad0d8e ML |
14041 | static void |
14042 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14043 | struct drm_crtc *crtc) |
a8ad0d8e | 14044 | { |
f2858021 ML |
14045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14046 | ||
14047 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14048 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14049 | } |
14050 | ||
f4a2cf29 | 14051 | static void |
55a08b3f ML |
14052 | intel_update_cursor_plane(struct drm_plane *plane, |
14053 | const struct intel_crtc_state *crtc_state, | |
14054 | const struct intel_plane_state *state) | |
852e787c | 14055 | { |
55a08b3f ML |
14056 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14057 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14058 | struct drm_device *dev = plane->dev; |
2b875c22 | 14059 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14060 | uint32_t addr; |
852e787c | 14061 | |
f4a2cf29 | 14062 | if (!obj) |
a912f12f | 14063 | addr = 0; |
f4a2cf29 | 14064 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14065 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14066 | else |
a912f12f | 14067 | addr = obj->phys_handle->busaddr; |
852e787c | 14068 | |
a912f12f | 14069 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14070 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14071 | } |
14072 | ||
3d7d6510 MR |
14073 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14074 | int pipe) | |
14075 | { | |
14076 | struct intel_plane *cursor; | |
8e7d688b | 14077 | struct intel_plane_state *state; |
3d7d6510 MR |
14078 | |
14079 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14080 | if (cursor == NULL) | |
14081 | return NULL; | |
14082 | ||
8e7d688b MR |
14083 | state = intel_create_plane_state(&cursor->base); |
14084 | if (!state) { | |
ea2c67bb MR |
14085 | kfree(cursor); |
14086 | return NULL; | |
14087 | } | |
8e7d688b | 14088 | cursor->base.state = &state->base; |
ea2c67bb | 14089 | |
3d7d6510 MR |
14090 | cursor->can_scale = false; |
14091 | cursor->max_downscale = 1; | |
14092 | cursor->pipe = pipe; | |
14093 | cursor->plane = pipe; | |
a9ff8714 | 14094 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14095 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14096 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14097 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14098 | |
14099 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14100 | &intel_plane_funcs, |
3d7d6510 MR |
14101 | intel_cursor_formats, |
14102 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14103 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14104 | |
14105 | if (INTEL_INFO(dev)->gen >= 4) { | |
14106 | if (!dev->mode_config.rotation_property) | |
14107 | dev->mode_config.rotation_property = | |
14108 | drm_mode_create_rotation_property(dev, | |
14109 | BIT(DRM_ROTATE_0) | | |
14110 | BIT(DRM_ROTATE_180)); | |
14111 | if (dev->mode_config.rotation_property) | |
14112 | drm_object_attach_property(&cursor->base.base, | |
14113 | dev->mode_config.rotation_property, | |
8e7d688b | 14114 | state->base.rotation); |
4398ad45 VS |
14115 | } |
14116 | ||
af99ceda CK |
14117 | if (INTEL_INFO(dev)->gen >=9) |
14118 | state->scaler_id = -1; | |
14119 | ||
ea2c67bb MR |
14120 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14121 | ||
3d7d6510 MR |
14122 | return &cursor->base; |
14123 | } | |
14124 | ||
549e2bfb CK |
14125 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14126 | struct intel_crtc_state *crtc_state) | |
14127 | { | |
14128 | int i; | |
14129 | struct intel_scaler *intel_scaler; | |
14130 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14131 | ||
14132 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14133 | intel_scaler = &scaler_state->scalers[i]; | |
14134 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14135 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14136 | } | |
14137 | ||
14138 | scaler_state->scaler_id = -1; | |
14139 | } | |
14140 | ||
b358d0a6 | 14141 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14142 | { |
fbee40df | 14143 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14144 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14145 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14146 | struct drm_plane *primary = NULL; |
14147 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14148 | int ret; |
79e53945 | 14149 | |
955382f3 | 14150 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14151 | if (intel_crtc == NULL) |
14152 | return; | |
14153 | ||
f5de6e07 ACO |
14154 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14155 | if (!crtc_state) | |
14156 | goto fail; | |
550acefd ACO |
14157 | intel_crtc->config = crtc_state; |
14158 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14159 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14160 | |
549e2bfb CK |
14161 | /* initialize shared scalers */ |
14162 | if (INTEL_INFO(dev)->gen >= 9) { | |
14163 | if (pipe == PIPE_C) | |
14164 | intel_crtc->num_scalers = 1; | |
14165 | else | |
14166 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14167 | ||
14168 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14169 | } | |
14170 | ||
465c120c | 14171 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14172 | if (!primary) |
14173 | goto fail; | |
14174 | ||
14175 | cursor = intel_cursor_plane_create(dev, pipe); | |
14176 | if (!cursor) | |
14177 | goto fail; | |
14178 | ||
465c120c | 14179 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14180 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14181 | if (ret) |
14182 | goto fail; | |
79e53945 | 14183 | |
1f1c2e24 VS |
14184 | /* |
14185 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14186 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14187 | */ |
80824003 JB |
14188 | intel_crtc->pipe = pipe; |
14189 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14190 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14191 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14192 | intel_crtc->plane = !pipe; |
80824003 JB |
14193 | } |
14194 | ||
4b0e333e CW |
14195 | intel_crtc->cursor_base = ~0; |
14196 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14197 | intel_crtc->cursor_size = ~0; |
8d7849db | 14198 | |
852eb00d VS |
14199 | intel_crtc->wm.cxsr_allowed = true; |
14200 | ||
22fd0fab JB |
14201 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14202 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14203 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14204 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14205 | ||
79e53945 | 14206 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14207 | |
8563b1e8 LL |
14208 | intel_color_init(&intel_crtc->base); |
14209 | ||
87b6b101 | 14210 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14211 | return; |
14212 | ||
14213 | fail: | |
14214 | if (primary) | |
14215 | drm_plane_cleanup(primary); | |
14216 | if (cursor) | |
14217 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14218 | kfree(crtc_state); |
3d7d6510 | 14219 | kfree(intel_crtc); |
79e53945 JB |
14220 | } |
14221 | ||
752aa88a JB |
14222 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14223 | { | |
14224 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14225 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14226 | |
51fd371b | 14227 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14228 | |
d3babd3f | 14229 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14230 | return INVALID_PIPE; |
14231 | ||
14232 | return to_intel_crtc(encoder->crtc)->pipe; | |
14233 | } | |
14234 | ||
08d7b3d1 | 14235 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14236 | struct drm_file *file) |
08d7b3d1 | 14237 | { |
08d7b3d1 | 14238 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14239 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14240 | struct intel_crtc *crtc; |
08d7b3d1 | 14241 | |
7707e653 | 14242 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14243 | |
7707e653 | 14244 | if (!drmmode_crtc) { |
08d7b3d1 | 14245 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14246 | return -ENOENT; |
08d7b3d1 CW |
14247 | } |
14248 | ||
7707e653 | 14249 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14250 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14251 | |
c05422d5 | 14252 | return 0; |
08d7b3d1 CW |
14253 | } |
14254 | ||
66a9278e | 14255 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14256 | { |
66a9278e DV |
14257 | struct drm_device *dev = encoder->base.dev; |
14258 | struct intel_encoder *source_encoder; | |
79e53945 | 14259 | int index_mask = 0; |
79e53945 JB |
14260 | int entry = 0; |
14261 | ||
b2784e15 | 14262 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14263 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14264 | index_mask |= (1 << entry); |
14265 | ||
79e53945 JB |
14266 | entry++; |
14267 | } | |
4ef69c7a | 14268 | |
79e53945 JB |
14269 | return index_mask; |
14270 | } | |
14271 | ||
4d302442 CW |
14272 | static bool has_edp_a(struct drm_device *dev) |
14273 | { | |
14274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14275 | ||
14276 | if (!IS_MOBILE(dev)) | |
14277 | return false; | |
14278 | ||
14279 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14280 | return false; | |
14281 | ||
e3589908 | 14282 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14283 | return false; |
14284 | ||
14285 | return true; | |
14286 | } | |
14287 | ||
84b4e042 JB |
14288 | static bool intel_crt_present(struct drm_device *dev) |
14289 | { | |
14290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14291 | ||
884497ed DL |
14292 | if (INTEL_INFO(dev)->gen >= 9) |
14293 | return false; | |
14294 | ||
cf404ce4 | 14295 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14296 | return false; |
14297 | ||
14298 | if (IS_CHERRYVIEW(dev)) | |
14299 | return false; | |
14300 | ||
65e472e4 VS |
14301 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14302 | return false; | |
14303 | ||
70ac54d0 VS |
14304 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14305 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14306 | return false; | |
14307 | ||
e4abb733 | 14308 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14309 | return false; |
14310 | ||
14311 | return true; | |
14312 | } | |
14313 | ||
79e53945 JB |
14314 | static void intel_setup_outputs(struct drm_device *dev) |
14315 | { | |
725e30ad | 14316 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14317 | struct intel_encoder *encoder; |
cb0953d7 | 14318 | bool dpd_is_edp = false; |
79e53945 | 14319 | |
c9093354 | 14320 | intel_lvds_init(dev); |
79e53945 | 14321 | |
84b4e042 | 14322 | if (intel_crt_present(dev)) |
79935fca | 14323 | intel_crt_init(dev); |
cb0953d7 | 14324 | |
c776eb2e VK |
14325 | if (IS_BROXTON(dev)) { |
14326 | /* | |
14327 | * FIXME: Broxton doesn't support port detection via the | |
14328 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14329 | * detect the ports. | |
14330 | */ | |
14331 | intel_ddi_init(dev, PORT_A); | |
14332 | intel_ddi_init(dev, PORT_B); | |
14333 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14334 | |
14335 | intel_dsi_init(dev); | |
c776eb2e | 14336 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14337 | int found; |
14338 | ||
de31facd JB |
14339 | /* |
14340 | * Haswell uses DDI functions to detect digital outputs. | |
14341 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14342 | * it's there. | |
14343 | */ | |
77179400 | 14344 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14345 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14346 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14347 | intel_ddi_init(dev, PORT_A); |
14348 | ||
14349 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14350 | * register */ | |
14351 | found = I915_READ(SFUSE_STRAP); | |
14352 | ||
14353 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14354 | intel_ddi_init(dev, PORT_B); | |
14355 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14356 | intel_ddi_init(dev, PORT_C); | |
14357 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14358 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14359 | /* |
14360 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14361 | */ | |
ef11bdb3 | 14362 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14363 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14364 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14365 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14366 | intel_ddi_init(dev, PORT_E); | |
14367 | ||
0e72a5b5 | 14368 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14369 | int found; |
5d8a7752 | 14370 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14371 | |
14372 | if (has_edp_a(dev)) | |
14373 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14374 | |
dc0fa718 | 14375 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14376 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14377 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14378 | if (!found) |
e2debe91 | 14379 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14380 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14381 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14382 | } |
14383 | ||
dc0fa718 | 14384 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14385 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14386 | |
dc0fa718 | 14387 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14388 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14389 | |
5eb08b69 | 14390 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14391 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14392 | |
270b3042 | 14393 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14394 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14395 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14396 | /* |
14397 | * The DP_DETECTED bit is the latched state of the DDC | |
14398 | * SDA pin at boot. However since eDP doesn't require DDC | |
14399 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14400 | * eDP ports may have been muxed to an alternate function. | |
14401 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14402 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14403 | * detect eDP ports. | |
14404 | */ | |
e66eb81d | 14405 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14406 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14407 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14408 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14409 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14410 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14411 | |
e66eb81d | 14412 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14413 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14414 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14415 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14416 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14417 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14418 | |
9418c1f1 | 14419 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14420 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14421 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14422 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14423 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14424 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14425 | } |
14426 | ||
3cfca973 | 14427 | intel_dsi_init(dev); |
09da55dc | 14428 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14429 | bool found = false; |
7d57382e | 14430 | |
e2debe91 | 14431 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14432 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14433 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14434 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14435 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14436 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14437 | } |
27185ae1 | 14438 | |
3fec3d2f | 14439 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14440 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14441 | } |
13520b05 KH |
14442 | |
14443 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14444 | |
e2debe91 | 14445 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14446 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14447 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14448 | } |
27185ae1 | 14449 | |
e2debe91 | 14450 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14451 | |
3fec3d2f | 14452 | if (IS_G4X(dev)) { |
b01f2c3a | 14453 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14454 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14455 | } |
3fec3d2f | 14456 | if (IS_G4X(dev)) |
ab9d7c30 | 14457 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14458 | } |
27185ae1 | 14459 | |
3fec3d2f | 14460 | if (IS_G4X(dev) && |
e7281eab | 14461 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14462 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14463 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14464 | intel_dvo_init(dev); |
14465 | ||
103a196f | 14466 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14467 | intel_tv_init(dev); |
14468 | ||
0bc12bcb | 14469 | intel_psr_init(dev); |
7c8f8a70 | 14470 | |
b2784e15 | 14471 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14472 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14473 | encoder->base.possible_clones = | |
66a9278e | 14474 | intel_encoder_clones(encoder); |
79e53945 | 14475 | } |
47356eb6 | 14476 | |
dde86e2d | 14477 | intel_init_pch_refclk(dev); |
270b3042 DV |
14478 | |
14479 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14480 | } |
14481 | ||
14482 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14483 | { | |
60a5ca01 | 14484 | struct drm_device *dev = fb->dev; |
79e53945 | 14485 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14486 | |
ef2d633e | 14487 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14488 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14489 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14490 | drm_gem_object_unreference(&intel_fb->obj->base); |
14491 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14492 | kfree(intel_fb); |
14493 | } | |
14494 | ||
14495 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14496 | struct drm_file *file, |
79e53945 JB |
14497 | unsigned int *handle) |
14498 | { | |
14499 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14500 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14501 | |
cc917ab4 CW |
14502 | if (obj->userptr.mm) { |
14503 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14504 | return -EINVAL; | |
14505 | } | |
14506 | ||
05394f39 | 14507 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14508 | } |
14509 | ||
86c98588 RV |
14510 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14511 | struct drm_file *file, | |
14512 | unsigned flags, unsigned color, | |
14513 | struct drm_clip_rect *clips, | |
14514 | unsigned num_clips) | |
14515 | { | |
14516 | struct drm_device *dev = fb->dev; | |
14517 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14518 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14519 | ||
14520 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14521 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14522 | mutex_unlock(&dev->struct_mutex); |
14523 | ||
14524 | return 0; | |
14525 | } | |
14526 | ||
79e53945 JB |
14527 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14528 | .destroy = intel_user_framebuffer_destroy, | |
14529 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14530 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14531 | }; |
14532 | ||
b321803d DL |
14533 | static |
14534 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14535 | uint32_t pixel_format) | |
14536 | { | |
14537 | u32 gen = INTEL_INFO(dev)->gen; | |
14538 | ||
14539 | if (gen >= 9) { | |
ac484963 VS |
14540 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14541 | ||
b321803d DL |
14542 | /* "The stride in bytes must not exceed the of the size of 8K |
14543 | * pixels and 32K bytes." | |
14544 | */ | |
ac484963 | 14545 | return min(8192 * cpp, 32768); |
666a4537 | 14546 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14547 | return 32*1024; |
14548 | } else if (gen >= 4) { | |
14549 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14550 | return 16*1024; | |
14551 | else | |
14552 | return 32*1024; | |
14553 | } else if (gen >= 3) { | |
14554 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14555 | return 8*1024; | |
14556 | else | |
14557 | return 16*1024; | |
14558 | } else { | |
14559 | /* XXX DSPC is limited to 4k tiled */ | |
14560 | return 8*1024; | |
14561 | } | |
14562 | } | |
14563 | ||
b5ea642a DV |
14564 | static int intel_framebuffer_init(struct drm_device *dev, |
14565 | struct intel_framebuffer *intel_fb, | |
14566 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14567 | struct drm_i915_gem_object *obj) | |
79e53945 | 14568 | { |
7b49f948 | 14569 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14570 | unsigned int aligned_height; |
79e53945 | 14571 | int ret; |
b321803d | 14572 | u32 pitch_limit, stride_alignment; |
79e53945 | 14573 | |
dd4916c5 DV |
14574 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14575 | ||
2a80eada DV |
14576 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14577 | /* Enforce that fb modifier and tiling mode match, but only for | |
14578 | * X-tiled. This is needed for FBC. */ | |
14579 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14580 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14581 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14582 | return -EINVAL; | |
14583 | } | |
14584 | } else { | |
14585 | if (obj->tiling_mode == I915_TILING_X) | |
14586 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14587 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14588 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14589 | return -EINVAL; | |
14590 | } | |
14591 | } | |
14592 | ||
9a8f0a12 TU |
14593 | /* Passed in modifier sanity checking. */ |
14594 | switch (mode_cmd->modifier[0]) { | |
14595 | case I915_FORMAT_MOD_Y_TILED: | |
14596 | case I915_FORMAT_MOD_Yf_TILED: | |
14597 | if (INTEL_INFO(dev)->gen < 9) { | |
14598 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14599 | mode_cmd->modifier[0]); | |
14600 | return -EINVAL; | |
14601 | } | |
14602 | case DRM_FORMAT_MOD_NONE: | |
14603 | case I915_FORMAT_MOD_X_TILED: | |
14604 | break; | |
14605 | default: | |
c0f40428 JB |
14606 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14607 | mode_cmd->modifier[0]); | |
57cd6508 | 14608 | return -EINVAL; |
c16ed4be | 14609 | } |
57cd6508 | 14610 | |
7b49f948 VS |
14611 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14612 | mode_cmd->modifier[0], | |
b321803d DL |
14613 | mode_cmd->pixel_format); |
14614 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14615 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14616 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14617 | return -EINVAL; |
c16ed4be | 14618 | } |
57cd6508 | 14619 | |
b321803d DL |
14620 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14621 | mode_cmd->pixel_format); | |
a35cdaa0 | 14622 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14623 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14624 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14625 | "tiled" : "linear", |
a35cdaa0 | 14626 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14627 | return -EINVAL; |
c16ed4be | 14628 | } |
5d7bd705 | 14629 | |
2a80eada | 14630 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14631 | mode_cmd->pitches[0] != obj->stride) { |
14632 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14633 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14634 | return -EINVAL; |
c16ed4be | 14635 | } |
5d7bd705 | 14636 | |
57779d06 | 14637 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14638 | switch (mode_cmd->pixel_format) { |
57779d06 | 14639 | case DRM_FORMAT_C8: |
04b3924d VS |
14640 | case DRM_FORMAT_RGB565: |
14641 | case DRM_FORMAT_XRGB8888: | |
14642 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14643 | break; |
14644 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14645 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14646 | DRM_DEBUG("unsupported pixel format: %s\n", |
14647 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14648 | return -EINVAL; |
c16ed4be | 14649 | } |
57779d06 | 14650 | break; |
57779d06 | 14651 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14652 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14653 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14654 | DRM_DEBUG("unsupported pixel format: %s\n", |
14655 | drm_get_format_name(mode_cmd->pixel_format)); | |
14656 | return -EINVAL; | |
14657 | } | |
14658 | break; | |
14659 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14660 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14661 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14662 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14663 | DRM_DEBUG("unsupported pixel format: %s\n", |
14664 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14665 | return -EINVAL; |
c16ed4be | 14666 | } |
b5626747 | 14667 | break; |
7531208b | 14668 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14669 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14670 | DRM_DEBUG("unsupported pixel format: %s\n", |
14671 | drm_get_format_name(mode_cmd->pixel_format)); | |
14672 | return -EINVAL; | |
14673 | } | |
14674 | break; | |
04b3924d VS |
14675 | case DRM_FORMAT_YUYV: |
14676 | case DRM_FORMAT_UYVY: | |
14677 | case DRM_FORMAT_YVYU: | |
14678 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14679 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14680 | DRM_DEBUG("unsupported pixel format: %s\n", |
14681 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14682 | return -EINVAL; |
c16ed4be | 14683 | } |
57cd6508 CW |
14684 | break; |
14685 | default: | |
4ee62c76 VS |
14686 | DRM_DEBUG("unsupported pixel format: %s\n", |
14687 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14688 | return -EINVAL; |
14689 | } | |
14690 | ||
90f9a336 VS |
14691 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14692 | if (mode_cmd->offsets[0] != 0) | |
14693 | return -EINVAL; | |
14694 | ||
ec2c981e | 14695 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14696 | mode_cmd->pixel_format, |
14697 | mode_cmd->modifier[0]); | |
53155c0a DV |
14698 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14699 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14700 | return -EINVAL; | |
14701 | ||
c7d73f6a DV |
14702 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14703 | intel_fb->obj = obj; | |
14704 | ||
2d7a215f VS |
14705 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
14706 | ||
79e53945 JB |
14707 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14708 | if (ret) { | |
14709 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14710 | return ret; | |
14711 | } | |
14712 | ||
0b05e1e0 VS |
14713 | intel_fb->obj->framebuffer_references++; |
14714 | ||
79e53945 JB |
14715 | return 0; |
14716 | } | |
14717 | ||
79e53945 JB |
14718 | static struct drm_framebuffer * |
14719 | intel_user_framebuffer_create(struct drm_device *dev, | |
14720 | struct drm_file *filp, | |
1eb83451 | 14721 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14722 | { |
dcb1394e | 14723 | struct drm_framebuffer *fb; |
05394f39 | 14724 | struct drm_i915_gem_object *obj; |
76dc3769 | 14725 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14726 | |
308e5bcb | 14727 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14728 | mode_cmd.handles[0])); |
c8725226 | 14729 | if (&obj->base == NULL) |
cce13ff7 | 14730 | return ERR_PTR(-ENOENT); |
79e53945 | 14731 | |
92907cbb | 14732 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14733 | if (IS_ERR(fb)) |
14734 | drm_gem_object_unreference_unlocked(&obj->base); | |
14735 | ||
14736 | return fb; | |
79e53945 JB |
14737 | } |
14738 | ||
0695726e | 14739 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14740 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14741 | { |
14742 | } | |
14743 | #endif | |
14744 | ||
79e53945 | 14745 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14746 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14747 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14748 | .atomic_check = intel_atomic_check, |
14749 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14750 | .atomic_state_alloc = intel_atomic_state_alloc, |
14751 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14752 | }; |
14753 | ||
88212941 ID |
14754 | /** |
14755 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14756 | * @dev_priv: device private | |
14757 | */ | |
14758 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14759 | { |
88212941 | 14760 | if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv)) |
ee9300bb | 14761 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
88212941 | 14762 | else if (IS_CHERRYVIEW(dev_priv)) |
ef9348c8 | 14763 | dev_priv->display.find_dpll = chv_find_best_dpll; |
88212941 | 14764 | else if (IS_VALLEYVIEW(dev_priv)) |
ee9300bb | 14765 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
88212941 | 14766 | else if (IS_PINEVIEW(dev_priv)) |
ee9300bb DV |
14767 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
14768 | else | |
14769 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14770 | ||
88212941 | 14771 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14772 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14773 | dev_priv->display.get_initial_plane_config = |
14774 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14775 | dev_priv->display.crtc_compute_clock = |
14776 | haswell_crtc_compute_clock; | |
14777 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14778 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14779 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14780 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14781 | dev_priv->display.get_initial_plane_config = |
14782 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14783 | dev_priv->display.crtc_compute_clock = |
14784 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14785 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14786 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14787 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14788 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14789 | dev_priv->display.get_initial_plane_config = |
14790 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14791 | dev_priv->display.crtc_compute_clock = |
14792 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14793 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14794 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
88212941 | 14795 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14796 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14797 | dev_priv->display.get_initial_plane_config = |
14798 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14799 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14800 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14801 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14802 | } else { |
0e8ffe1b | 14803 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14804 | dev_priv->display.get_initial_plane_config = |
14805 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14806 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14807 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14808 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14809 | } |
e70236a8 | 14810 | |
e70236a8 | 14811 | /* Returns the core display clock speed */ |
88212941 | 14812 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
14813 | dev_priv->display.get_display_clock_speed = |
14814 | skylake_get_display_clock_speed; | |
88212941 | 14815 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
14816 | dev_priv->display.get_display_clock_speed = |
14817 | broxton_get_display_clock_speed; | |
88212941 | 14818 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
14819 | dev_priv->display.get_display_clock_speed = |
14820 | broadwell_get_display_clock_speed; | |
88212941 | 14821 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
14822 | dev_priv->display.get_display_clock_speed = |
14823 | haswell_get_display_clock_speed; | |
88212941 | 14824 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
14825 | dev_priv->display.get_display_clock_speed = |
14826 | valleyview_get_display_clock_speed; | |
88212941 | 14827 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
14828 | dev_priv->display.get_display_clock_speed = |
14829 | ilk_get_display_clock_speed; | |
88212941 ID |
14830 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
14831 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
14832 | dev_priv->display.get_display_clock_speed = |
14833 | i945_get_display_clock_speed; | |
88212941 | 14834 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
14835 | dev_priv->display.get_display_clock_speed = |
14836 | gm45_get_display_clock_speed; | |
88212941 | 14837 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
14838 | dev_priv->display.get_display_clock_speed = |
14839 | i965gm_get_display_clock_speed; | |
88212941 | 14840 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
14841 | dev_priv->display.get_display_clock_speed = |
14842 | pnv_get_display_clock_speed; | |
88212941 | 14843 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
14844 | dev_priv->display.get_display_clock_speed = |
14845 | g33_get_display_clock_speed; | |
88212941 | 14846 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
14847 | dev_priv->display.get_display_clock_speed = |
14848 | i915_get_display_clock_speed; | |
88212941 | 14849 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
14850 | dev_priv->display.get_display_clock_speed = |
14851 | i9xx_misc_get_display_clock_speed; | |
88212941 | 14852 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
14853 | dev_priv->display.get_display_clock_speed = |
14854 | i915gm_get_display_clock_speed; | |
88212941 | 14855 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
14856 | dev_priv->display.get_display_clock_speed = |
14857 | i865_get_display_clock_speed; | |
88212941 | 14858 | else if (IS_I85X(dev_priv)) |
e70236a8 | 14859 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14860 | i85x_get_display_clock_speed; |
623e01e5 | 14861 | else { /* 830 */ |
88212941 | 14862 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
14863 | dev_priv->display.get_display_clock_speed = |
14864 | i830_get_display_clock_speed; | |
623e01e5 | 14865 | } |
e70236a8 | 14866 | |
88212941 | 14867 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14868 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14869 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14870 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14871 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14872 | /* FIXME: detect B0+ stepping and use auto training */ |
14873 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14874 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14875 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
88212941 | 14876 | if (IS_BROADWELL(dev_priv)) { |
27c329ed ML |
14877 | dev_priv->display.modeset_commit_cdclk = |
14878 | broadwell_modeset_commit_cdclk; | |
14879 | dev_priv->display.modeset_calc_cdclk = | |
14880 | broadwell_modeset_calc_cdclk; | |
14881 | } | |
88212941 | 14882 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
14883 | dev_priv->display.modeset_commit_cdclk = |
14884 | valleyview_modeset_commit_cdclk; | |
14885 | dev_priv->display.modeset_calc_cdclk = | |
14886 | valleyview_modeset_calc_cdclk; | |
88212941 | 14887 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed ML |
14888 | dev_priv->display.modeset_commit_cdclk = |
14889 | broxton_modeset_commit_cdclk; | |
14890 | dev_priv->display.modeset_calc_cdclk = | |
14891 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14892 | } |
8c9f3aaf | 14893 | |
88212941 | 14894 | switch (INTEL_INFO(dev_priv)->gen) { |
8c9f3aaf JB |
14895 | case 2: |
14896 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14897 | break; | |
14898 | ||
14899 | case 3: | |
14900 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14901 | break; | |
14902 | ||
14903 | case 4: | |
14904 | case 5: | |
14905 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14906 | break; | |
14907 | ||
14908 | case 6: | |
14909 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14910 | break; | |
7c9017e5 | 14911 | case 7: |
4e0bbc31 | 14912 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14913 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14914 | break; | |
830c81db | 14915 | case 9: |
ba343e02 TU |
14916 | /* Drop through - unsupported since execlist only. */ |
14917 | default: | |
14918 | /* Default just returns -ENODEV to indicate unsupported */ | |
14919 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14920 | } |
e70236a8 JB |
14921 | } |
14922 | ||
b690e96c JB |
14923 | /* |
14924 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14925 | * resume, or other times. This quirk makes sure that's the case for | |
14926 | * affected systems. | |
14927 | */ | |
0206e353 | 14928 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14929 | { |
14930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14931 | ||
14932 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14933 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14934 | } |
14935 | ||
b6b5d049 VS |
14936 | static void quirk_pipeb_force(struct drm_device *dev) |
14937 | { | |
14938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14939 | ||
14940 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14941 | DRM_INFO("applying pipe b force quirk\n"); | |
14942 | } | |
14943 | ||
435793df KP |
14944 | /* |
14945 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14946 | */ | |
14947 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14948 | { | |
14949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14950 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14951 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14952 | } |
14953 | ||
4dca20ef | 14954 | /* |
5a15ab5b CE |
14955 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14956 | * brightness value | |
4dca20ef CE |
14957 | */ |
14958 | static void quirk_invert_brightness(struct drm_device *dev) | |
14959 | { | |
14960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14961 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14962 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14963 | } |
14964 | ||
9c72cc6f SD |
14965 | /* Some VBT's incorrectly indicate no backlight is present */ |
14966 | static void quirk_backlight_present(struct drm_device *dev) | |
14967 | { | |
14968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14969 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14970 | DRM_INFO("applying backlight present quirk\n"); | |
14971 | } | |
14972 | ||
b690e96c JB |
14973 | struct intel_quirk { |
14974 | int device; | |
14975 | int subsystem_vendor; | |
14976 | int subsystem_device; | |
14977 | void (*hook)(struct drm_device *dev); | |
14978 | }; | |
14979 | ||
5f85f176 EE |
14980 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14981 | struct intel_dmi_quirk { | |
14982 | void (*hook)(struct drm_device *dev); | |
14983 | const struct dmi_system_id (*dmi_id_list)[]; | |
14984 | }; | |
14985 | ||
14986 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14987 | { | |
14988 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14989 | return 1; | |
14990 | } | |
14991 | ||
14992 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14993 | { | |
14994 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14995 | { | |
14996 | .callback = intel_dmi_reverse_brightness, | |
14997 | .ident = "NCR Corporation", | |
14998 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14999 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15000 | }, | |
15001 | }, | |
15002 | { } /* terminating entry */ | |
15003 | }, | |
15004 | .hook = quirk_invert_brightness, | |
15005 | }, | |
15006 | }; | |
15007 | ||
c43b5634 | 15008 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15009 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15010 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15011 | ||
b690e96c JB |
15012 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15013 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15014 | ||
5f080c0f VS |
15015 | /* 830 needs to leave pipe A & dpll A up */ |
15016 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15017 | ||
b6b5d049 VS |
15018 | /* 830 needs to leave pipe B & dpll B up */ |
15019 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15020 | ||
435793df KP |
15021 | /* Lenovo U160 cannot use SSC on LVDS */ |
15022 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15023 | |
15024 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15025 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15026 | |
be505f64 AH |
15027 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15028 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15029 | ||
15030 | /* Acer/eMachines G725 */ | |
15031 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15032 | ||
15033 | /* Acer/eMachines e725 */ | |
15034 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15035 | ||
15036 | /* Acer/Packard Bell NCL20 */ | |
15037 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15038 | ||
15039 | /* Acer Aspire 4736Z */ | |
15040 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15041 | |
15042 | /* Acer Aspire 5336 */ | |
15043 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15044 | |
15045 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15046 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15047 | |
dfb3d47b SD |
15048 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15049 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15050 | ||
b2a9601c | 15051 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15052 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15053 | ||
1b9448b0 JN |
15054 | /* Apple Macbook 4,1 */ |
15055 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15056 | ||
d4967d8c SD |
15057 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15058 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15059 | |
15060 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15061 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15062 | |
15063 | /* Dell Chromebook 11 */ | |
15064 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15065 | |
15066 | /* Dell Chromebook 11 (2015 version) */ | |
15067 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15068 | }; |
15069 | ||
15070 | static void intel_init_quirks(struct drm_device *dev) | |
15071 | { | |
15072 | struct pci_dev *d = dev->pdev; | |
15073 | int i; | |
15074 | ||
15075 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15076 | struct intel_quirk *q = &intel_quirks[i]; | |
15077 | ||
15078 | if (d->device == q->device && | |
15079 | (d->subsystem_vendor == q->subsystem_vendor || | |
15080 | q->subsystem_vendor == PCI_ANY_ID) && | |
15081 | (d->subsystem_device == q->subsystem_device || | |
15082 | q->subsystem_device == PCI_ANY_ID)) | |
15083 | q->hook(dev); | |
15084 | } | |
5f85f176 EE |
15085 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15086 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15087 | intel_dmi_quirks[i].hook(dev); | |
15088 | } | |
b690e96c JB |
15089 | } |
15090 | ||
9cce37f4 JB |
15091 | /* Disable the VGA plane that we never use */ |
15092 | static void i915_disable_vga(struct drm_device *dev) | |
15093 | { | |
15094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15095 | u8 sr1; | |
f0f59a00 | 15096 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15097 | |
2b37c616 | 15098 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15099 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15100 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15101 | sr1 = inb(VGA_SR_DATA); |
15102 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15103 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15104 | udelay(300); | |
15105 | ||
01f5a626 | 15106 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15107 | POSTING_READ(vga_reg); |
15108 | } | |
15109 | ||
f817586c DV |
15110 | void intel_modeset_init_hw(struct drm_device *dev) |
15111 | { | |
1a617b77 ML |
15112 | struct drm_i915_private *dev_priv = dev->dev_private; |
15113 | ||
b6283055 | 15114 | intel_update_cdclk(dev); |
1a617b77 ML |
15115 | |
15116 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15117 | ||
f817586c | 15118 | intel_init_clock_gating(dev); |
8090c6b9 | 15119 | intel_enable_gt_powersave(dev); |
f817586c DV |
15120 | } |
15121 | ||
d93c0372 MR |
15122 | /* |
15123 | * Calculate what we think the watermarks should be for the state we've read | |
15124 | * out of the hardware and then immediately program those watermarks so that | |
15125 | * we ensure the hardware settings match our internal state. | |
15126 | * | |
15127 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15128 | * current state (which was constructed during hardware readout) and running it | |
15129 | * through the atomic check code to calculate new watermark values in the | |
15130 | * state object. | |
15131 | */ | |
15132 | static void sanitize_watermarks(struct drm_device *dev) | |
15133 | { | |
15134 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15135 | struct drm_atomic_state *state; | |
15136 | struct drm_crtc *crtc; | |
15137 | struct drm_crtc_state *cstate; | |
15138 | struct drm_modeset_acquire_ctx ctx; | |
15139 | int ret; | |
15140 | int i; | |
15141 | ||
15142 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15143 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15144 | return; |
15145 | ||
15146 | /* | |
15147 | * We need to hold connection_mutex before calling duplicate_state so | |
15148 | * that the connector loop is protected. | |
15149 | */ | |
15150 | drm_modeset_acquire_init(&ctx, 0); | |
15151 | retry: | |
0cd1262d | 15152 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15153 | if (ret == -EDEADLK) { |
15154 | drm_modeset_backoff(&ctx); | |
15155 | goto retry; | |
15156 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15157 | goto fail; |
d93c0372 MR |
15158 | } |
15159 | ||
15160 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15161 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15162 | goto fail; |
d93c0372 | 15163 | |
ed4a6a7c MR |
15164 | /* |
15165 | * Hardware readout is the only time we don't want to calculate | |
15166 | * intermediate watermarks (since we don't trust the current | |
15167 | * watermarks). | |
15168 | */ | |
15169 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15170 | ||
d93c0372 MR |
15171 | ret = intel_atomic_check(dev, state); |
15172 | if (ret) { | |
15173 | /* | |
15174 | * If we fail here, it means that the hardware appears to be | |
15175 | * programmed in a way that shouldn't be possible, given our | |
15176 | * understanding of watermark requirements. This might mean a | |
15177 | * mistake in the hardware readout code or a mistake in the | |
15178 | * watermark calculations for a given platform. Raise a WARN | |
15179 | * so that this is noticeable. | |
15180 | * | |
15181 | * If this actually happens, we'll have to just leave the | |
15182 | * BIOS-programmed watermarks untouched and hope for the best. | |
15183 | */ | |
15184 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15185 | goto fail; |
d93c0372 MR |
15186 | } |
15187 | ||
15188 | /* Write calculated watermark values back */ | |
15189 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15190 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15191 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15192 | ||
ed4a6a7c MR |
15193 | cs->wm.need_postvbl_update = true; |
15194 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15195 | } |
15196 | ||
15197 | drm_atomic_state_free(state); | |
0cd1262d | 15198 | fail: |
d93c0372 MR |
15199 | drm_modeset_drop_locks(&ctx); |
15200 | drm_modeset_acquire_fini(&ctx); | |
15201 | } | |
15202 | ||
79e53945 JB |
15203 | void intel_modeset_init(struct drm_device *dev) |
15204 | { | |
652c393a | 15205 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15206 | int sprite, ret; |
8cc87b75 | 15207 | enum pipe pipe; |
46f297fb | 15208 | struct intel_crtc *crtc; |
79e53945 JB |
15209 | |
15210 | drm_mode_config_init(dev); | |
15211 | ||
15212 | dev->mode_config.min_width = 0; | |
15213 | dev->mode_config.min_height = 0; | |
15214 | ||
019d96cb DA |
15215 | dev->mode_config.preferred_depth = 24; |
15216 | dev->mode_config.prefer_shadow = 1; | |
15217 | ||
25bab385 TU |
15218 | dev->mode_config.allow_fb_modifiers = true; |
15219 | ||
e6ecefaa | 15220 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15221 | |
b690e96c JB |
15222 | intel_init_quirks(dev); |
15223 | ||
1fa61106 ED |
15224 | intel_init_pm(dev); |
15225 | ||
e3c74757 BW |
15226 | if (INTEL_INFO(dev)->num_pipes == 0) |
15227 | return; | |
15228 | ||
69f92f67 LW |
15229 | /* |
15230 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15231 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15232 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15233 | * indicates as much. | |
15234 | */ | |
15235 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15236 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15237 | DREF_SSC1_ENABLE); | |
15238 | ||
15239 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15240 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15241 | bios_lvds_use_ssc ? "en" : "dis", | |
15242 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15243 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15244 | } | |
15245 | } | |
15246 | ||
a6c45cf0 CW |
15247 | if (IS_GEN2(dev)) { |
15248 | dev->mode_config.max_width = 2048; | |
15249 | dev->mode_config.max_height = 2048; | |
15250 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15251 | dev->mode_config.max_width = 4096; |
15252 | dev->mode_config.max_height = 4096; | |
79e53945 | 15253 | } else { |
a6c45cf0 CW |
15254 | dev->mode_config.max_width = 8192; |
15255 | dev->mode_config.max_height = 8192; | |
79e53945 | 15256 | } |
068be561 | 15257 | |
dc41c154 VS |
15258 | if (IS_845G(dev) || IS_I865G(dev)) { |
15259 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15260 | dev->mode_config.cursor_height = 1023; | |
15261 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15262 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15263 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15264 | } else { | |
15265 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15266 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15267 | } | |
15268 | ||
62106b4f | 15269 | dev->mode_config.fb_base = dev_priv->ggtt.mappable_base; |
79e53945 | 15270 | |
28c97730 | 15271 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15272 | INTEL_INFO(dev)->num_pipes, |
15273 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15274 | |
055e393f | 15275 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15276 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15277 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15278 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15279 | if (ret) |
06da8da2 | 15280 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15281 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15282 | } |
79e53945 JB |
15283 | } |
15284 | ||
bfa7df01 | 15285 | intel_update_czclk(dev_priv); |
e7dc33f3 | 15286 | intel_update_rawclk(dev_priv); |
bfa7df01 VS |
15287 | intel_update_cdclk(dev); |
15288 | ||
e72f9fbf | 15289 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15290 | |
9cce37f4 JB |
15291 | /* Just disable it once at startup */ |
15292 | i915_disable_vga(dev); | |
79e53945 | 15293 | intel_setup_outputs(dev); |
11be49eb | 15294 | |
6e9f798d | 15295 | drm_modeset_lock_all(dev); |
043e9bda | 15296 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15297 | drm_modeset_unlock_all(dev); |
46f297fb | 15298 | |
d3fcc808 | 15299 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15300 | struct intel_initial_plane_config plane_config = {}; |
15301 | ||
46f297fb JB |
15302 | if (!crtc->active) |
15303 | continue; | |
15304 | ||
46f297fb | 15305 | /* |
46f297fb JB |
15306 | * Note that reserving the BIOS fb up front prevents us |
15307 | * from stuffing other stolen allocations like the ring | |
15308 | * on top. This prevents some ugliness at boot time, and | |
15309 | * can even allow for smooth boot transitions if the BIOS | |
15310 | * fb is large enough for the active pipe configuration. | |
15311 | */ | |
eeebeac5 ML |
15312 | dev_priv->display.get_initial_plane_config(crtc, |
15313 | &plane_config); | |
15314 | ||
15315 | /* | |
15316 | * If the fb is shared between multiple heads, we'll | |
15317 | * just get the first one. | |
15318 | */ | |
15319 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15320 | } |
d93c0372 MR |
15321 | |
15322 | /* | |
15323 | * Make sure hardware watermarks really match the state we read out. | |
15324 | * Note that we need to do this after reconstructing the BIOS fb's | |
15325 | * since the watermark calculation done here will use pstate->fb. | |
15326 | */ | |
15327 | sanitize_watermarks(dev); | |
2c7111db CW |
15328 | } |
15329 | ||
7fad798e DV |
15330 | static void intel_enable_pipe_a(struct drm_device *dev) |
15331 | { | |
15332 | struct intel_connector *connector; | |
15333 | struct drm_connector *crt = NULL; | |
15334 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15335 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15336 | |
15337 | /* We can't just switch on the pipe A, we need to set things up with a | |
15338 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15339 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15340 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15341 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15342 | crt = &connector->base; | |
15343 | break; | |
15344 | } | |
15345 | } | |
15346 | ||
15347 | if (!crt) | |
15348 | return; | |
15349 | ||
208bf9fd | 15350 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15351 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15352 | } |
15353 | ||
fa555837 DV |
15354 | static bool |
15355 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15356 | { | |
7eb552ae BW |
15357 | struct drm_device *dev = crtc->base.dev; |
15358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15359 | u32 val; |
fa555837 | 15360 | |
7eb552ae | 15361 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15362 | return true; |
15363 | ||
649636ef | 15364 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15365 | |
15366 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15367 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15368 | return false; | |
15369 | ||
15370 | return true; | |
15371 | } | |
15372 | ||
02e93c35 VS |
15373 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15374 | { | |
15375 | struct drm_device *dev = crtc->base.dev; | |
15376 | struct intel_encoder *encoder; | |
15377 | ||
15378 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15379 | return true; | |
15380 | ||
15381 | return false; | |
15382 | } | |
15383 | ||
dd756198 VS |
15384 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15385 | { | |
15386 | struct drm_device *dev = encoder->base.dev; | |
15387 | struct intel_connector *connector; | |
15388 | ||
15389 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15390 | return true; | |
15391 | ||
15392 | return false; | |
15393 | } | |
15394 | ||
24929352 DV |
15395 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15396 | { | |
15397 | struct drm_device *dev = crtc->base.dev; | |
15398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15399 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15400 | |
24929352 | 15401 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15402 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15403 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15404 | ||
15405 | I915_WRITE(reg, | |
15406 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15407 | } | |
24929352 | 15408 | |
d3eaf884 | 15409 | /* restore vblank interrupts to correct state */ |
9625604c | 15410 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15411 | if (crtc->active) { |
f9cd7b88 VS |
15412 | struct intel_plane *plane; |
15413 | ||
9625604c | 15414 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15415 | |
15416 | /* Disable everything but the primary plane */ | |
15417 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15418 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15419 | continue; | |
15420 | ||
15421 | plane->disable_plane(&plane->base, &crtc->base); | |
15422 | } | |
9625604c | 15423 | } |
d3eaf884 | 15424 | |
24929352 | 15425 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15426 | * disable the crtc (and hence change the state) if it is wrong. Note |
15427 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15428 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15429 | bool plane; |
15430 | ||
24929352 DV |
15431 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15432 | crtc->base.base.id); | |
15433 | ||
15434 | /* Pipe has the wrong plane attached and the plane is active. | |
15435 | * Temporarily change the plane mapping and disable everything | |
15436 | * ... */ | |
15437 | plane = crtc->plane; | |
b70709a6 | 15438 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15439 | crtc->plane = !plane; |
b17d48e2 | 15440 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15441 | crtc->plane = plane; |
24929352 | 15442 | } |
24929352 | 15443 | |
7fad798e DV |
15444 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15445 | crtc->pipe == PIPE_A && !crtc->active) { | |
15446 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15447 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15448 | * call below we restore the pipe to the right state, but leave | |
15449 | * the required bits on. */ | |
15450 | intel_enable_pipe_a(dev); | |
15451 | } | |
15452 | ||
24929352 DV |
15453 | /* Adjust the state of the output pipe according to whether we |
15454 | * have active connectors/encoders. */ | |
842e0307 | 15455 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15456 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15457 | |
a3ed6aad | 15458 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15459 | /* |
15460 | * We start out with underrun reporting disabled to avoid races. | |
15461 | * For correct bookkeeping mark this on active crtcs. | |
15462 | * | |
c5ab3bc0 DV |
15463 | * Also on gmch platforms we dont have any hardware bits to |
15464 | * disable the underrun reporting. Which means we need to start | |
15465 | * out with underrun reporting disabled also on inactive pipes, | |
15466 | * since otherwise we'll complain about the garbage we read when | |
15467 | * e.g. coming up after runtime pm. | |
15468 | * | |
4cc31489 DV |
15469 | * No protection against concurrent access is required - at |
15470 | * worst a fifo underrun happens which also sets this to false. | |
15471 | */ | |
15472 | crtc->cpu_fifo_underrun_disabled = true; | |
15473 | crtc->pch_fifo_underrun_disabled = true; | |
15474 | } | |
24929352 DV |
15475 | } |
15476 | ||
15477 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15478 | { | |
15479 | struct intel_connector *connector; | |
15480 | struct drm_device *dev = encoder->base.dev; | |
15481 | ||
15482 | /* We need to check both for a crtc link (meaning that the | |
15483 | * encoder is active and trying to read from a pipe) and the | |
15484 | * pipe itself being active. */ | |
15485 | bool has_active_crtc = encoder->base.crtc && | |
15486 | to_intel_crtc(encoder->base.crtc)->active; | |
15487 | ||
dd756198 | 15488 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15489 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15490 | encoder->base.base.id, | |
8e329a03 | 15491 | encoder->base.name); |
24929352 DV |
15492 | |
15493 | /* Connector is active, but has no active pipe. This is | |
15494 | * fallout from our resume register restoring. Disable | |
15495 | * the encoder manually again. */ | |
15496 | if (encoder->base.crtc) { | |
15497 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15498 | encoder->base.base.id, | |
8e329a03 | 15499 | encoder->base.name); |
24929352 | 15500 | encoder->disable(encoder); |
a62d1497 VS |
15501 | if (encoder->post_disable) |
15502 | encoder->post_disable(encoder); | |
24929352 | 15503 | } |
7f1950fb | 15504 | encoder->base.crtc = NULL; |
24929352 DV |
15505 | |
15506 | /* Inconsistent output/port/pipe state happens presumably due to | |
15507 | * a bug in one of the get_hw_state functions. Or someplace else | |
15508 | * in our code, like the register restore mess on resume. Clamp | |
15509 | * things to off as a safer default. */ | |
3a3371ff | 15510 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15511 | if (connector->encoder != encoder) |
15512 | continue; | |
7f1950fb EE |
15513 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15514 | connector->base.encoder = NULL; | |
24929352 DV |
15515 | } |
15516 | } | |
15517 | /* Enabled encoders without active connectors will be fixed in | |
15518 | * the crtc fixup. */ | |
15519 | } | |
15520 | ||
04098753 | 15521 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15522 | { |
15523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15524 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15525 | |
04098753 ID |
15526 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15527 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15528 | i915_disable_vga(dev); | |
15529 | } | |
15530 | } | |
15531 | ||
15532 | void i915_redisable_vga(struct drm_device *dev) | |
15533 | { | |
15534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15535 | ||
8dc8a27c PZ |
15536 | /* This function can be called both from intel_modeset_setup_hw_state or |
15537 | * at a very early point in our resume sequence, where the power well | |
15538 | * structures are not yet restored. Since this function is at a very | |
15539 | * paranoid "someone might have enabled VGA while we were not looking" | |
15540 | * level, just check if the power well is enabled instead of trying to | |
15541 | * follow the "don't touch the power well if we don't need it" policy | |
15542 | * the rest of the driver uses. */ | |
6392f847 | 15543 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15544 | return; |
15545 | ||
04098753 | 15546 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15547 | |
15548 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15549 | } |
15550 | ||
f9cd7b88 | 15551 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15552 | { |
f9cd7b88 | 15553 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15554 | |
f9cd7b88 | 15555 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15556 | } |
15557 | ||
f9cd7b88 VS |
15558 | /* FIXME read out full plane state for all planes */ |
15559 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15560 | { |
b26d3ea3 | 15561 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15562 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15563 | to_intel_plane_state(primary->state); |
d032ffa0 | 15564 | |
19b8d387 | 15565 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15566 | primary_get_hw_state(to_intel_plane(primary)); |
15567 | ||
15568 | if (plane_state->visible) | |
15569 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15570 | } |
15571 | ||
30e984df | 15572 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15573 | { |
15574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15575 | enum pipe pipe; | |
24929352 DV |
15576 | struct intel_crtc *crtc; |
15577 | struct intel_encoder *encoder; | |
15578 | struct intel_connector *connector; | |
5358901f | 15579 | int i; |
24929352 | 15580 | |
565602d7 ML |
15581 | dev_priv->active_crtcs = 0; |
15582 | ||
d3fcc808 | 15583 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15584 | struct intel_crtc_state *crtc_state = crtc->config; |
15585 | int pixclk = 0; | |
3b117c8f | 15586 | |
565602d7 ML |
15587 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15588 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15589 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15590 | |
565602d7 ML |
15591 | crtc_state->base.active = crtc_state->base.enable = |
15592 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15593 | ||
15594 | crtc->base.enabled = crtc_state->base.enable; | |
15595 | crtc->active = crtc_state->base.active; | |
15596 | ||
15597 | if (crtc_state->base.active) { | |
15598 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15599 | ||
15600 | if (IS_BROADWELL(dev_priv)) { | |
15601 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15602 | ||
15603 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15604 | if (crtc_state->ips_enabled) | |
15605 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15606 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15607 | IS_CHERRYVIEW(dev_priv) || | |
15608 | IS_BROXTON(dev_priv)) | |
15609 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15610 | else | |
15611 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15612 | } | |
15613 | ||
15614 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15615 | |
f9cd7b88 | 15616 | readout_plane_state(crtc); |
24929352 DV |
15617 | |
15618 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15619 | crtc->base.base.id, | |
15620 | crtc->active ? "enabled" : "disabled"); | |
15621 | } | |
15622 | ||
5358901f DV |
15623 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15624 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15625 | ||
2edd6443 ACO |
15626 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
15627 | &pll->config.hw_state); | |
3e369b76 | 15628 | pll->config.crtc_mask = 0; |
d3fcc808 | 15629 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 15630 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 15631 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15632 | } |
2dd66ebd | 15633 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 15634 | |
1e6f2ddc | 15635 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15636 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
15637 | } |
15638 | ||
b2784e15 | 15639 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15640 | pipe = 0; |
15641 | ||
15642 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15643 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15644 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15645 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15646 | } else { |
15647 | encoder->base.crtc = NULL; | |
15648 | } | |
15649 | ||
6f2bcceb | 15650 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15651 | encoder->base.base.id, |
8e329a03 | 15652 | encoder->base.name, |
24929352 | 15653 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15654 | pipe_name(pipe)); |
24929352 DV |
15655 | } |
15656 | ||
3a3371ff | 15657 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15658 | if (connector->get_hw_state(connector)) { |
15659 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15660 | |
15661 | encoder = connector->encoder; | |
15662 | connector->base.encoder = &encoder->base; | |
15663 | ||
15664 | if (encoder->base.crtc && | |
15665 | encoder->base.crtc->state->active) { | |
15666 | /* | |
15667 | * This has to be done during hardware readout | |
15668 | * because anything calling .crtc_disable may | |
15669 | * rely on the connector_mask being accurate. | |
15670 | */ | |
15671 | encoder->base.crtc->state->connector_mask |= | |
15672 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15673 | encoder->base.crtc->state->encoder_mask |= |
15674 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15675 | } |
15676 | ||
24929352 DV |
15677 | } else { |
15678 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15679 | connector->base.encoder = NULL; | |
15680 | } | |
15681 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15682 | connector->base.base.id, | |
c23cc417 | 15683 | connector->base.name, |
24929352 DV |
15684 | connector->base.encoder ? "enabled" : "disabled"); |
15685 | } | |
7f4c6284 VS |
15686 | |
15687 | for_each_intel_crtc(dev, crtc) { | |
15688 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15689 | ||
15690 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15691 | if (crtc->base.state->active) { | |
15692 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15693 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15694 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15695 | ||
15696 | /* | |
15697 | * The initial mode needs to be set in order to keep | |
15698 | * the atomic core happy. It wants a valid mode if the | |
15699 | * crtc's enabled, so we do the above call. | |
15700 | * | |
15701 | * At this point some state updated by the connectors | |
15702 | * in their ->detect() callback has not run yet, so | |
15703 | * no recalculation can be done yet. | |
15704 | * | |
15705 | * Even if we could do a recalculation and modeset | |
15706 | * right now it would cause a double modeset if | |
15707 | * fbdev or userspace chooses a different initial mode. | |
15708 | * | |
15709 | * If that happens, someone indicated they wanted a | |
15710 | * mode change, which means it's safe to do a full | |
15711 | * recalculation. | |
15712 | */ | |
15713 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15714 | |
15715 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15716 | update_scanline_offset(crtc); | |
7f4c6284 | 15717 | } |
e3b247da VS |
15718 | |
15719 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 15720 | } |
30e984df DV |
15721 | } |
15722 | ||
043e9bda ML |
15723 | /* Scan out the current hw modeset state, |
15724 | * and sanitizes it to the current state | |
15725 | */ | |
15726 | static void | |
15727 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15728 | { |
15729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15730 | enum pipe pipe; | |
30e984df DV |
15731 | struct intel_crtc *crtc; |
15732 | struct intel_encoder *encoder; | |
35c95375 | 15733 | int i; |
30e984df DV |
15734 | |
15735 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15736 | |
15737 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15738 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15739 | intel_sanitize_encoder(encoder); |
15740 | } | |
15741 | ||
055e393f | 15742 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15743 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15744 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15745 | intel_dump_pipe_config(crtc, crtc->config, |
15746 | "[setup_hw_state]"); | |
24929352 | 15747 | } |
9a935856 | 15748 | |
d29b2f9d ACO |
15749 | intel_modeset_update_connector_atomic_state(dev); |
15750 | ||
35c95375 DV |
15751 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15752 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15753 | ||
2dd66ebd | 15754 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15755 | continue; |
15756 | ||
15757 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15758 | ||
2edd6443 | 15759 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15760 | pll->on = false; |
15761 | } | |
15762 | ||
666a4537 | 15763 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15764 | vlv_wm_get_hw_state(dev); |
15765 | else if (IS_GEN9(dev)) | |
3078999f PB |
15766 | skl_wm_get_hw_state(dev); |
15767 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15768 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15769 | |
15770 | for_each_intel_crtc(dev, crtc) { | |
15771 | unsigned long put_domains; | |
15772 | ||
74bff5f9 | 15773 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15774 | if (WARN_ON(put_domains)) |
15775 | modeset_put_power_domains(dev_priv, put_domains); | |
15776 | } | |
15777 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15778 | |
15779 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15780 | } |
7d0bc1ea | 15781 | |
043e9bda ML |
15782 | void intel_display_resume(struct drm_device *dev) |
15783 | { | |
e2c8b870 ML |
15784 | struct drm_i915_private *dev_priv = to_i915(dev); |
15785 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15786 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15787 | int ret; |
e2c8b870 | 15788 | bool setup = false; |
f30da187 | 15789 | |
e2c8b870 | 15790 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15791 | |
ea49c9ac ML |
15792 | /* |
15793 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15794 | * won't be taken. Unfortunately some probed state like | |
15795 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15796 | * it here for now. | |
15797 | */ | |
15798 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15799 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15800 | |
e2c8b870 ML |
15801 | retry: |
15802 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15803 | |
e2c8b870 ML |
15804 | if (ret == 0 && !setup) { |
15805 | setup = true; | |
043e9bda | 15806 | |
e2c8b870 ML |
15807 | intel_modeset_setup_hw_state(dev); |
15808 | i915_redisable_vga(dev); | |
45e2b5f6 | 15809 | } |
8af6cf88 | 15810 | |
e2c8b870 ML |
15811 | if (ret == 0 && state) { |
15812 | struct drm_crtc_state *crtc_state; | |
15813 | struct drm_crtc *crtc; | |
15814 | int i; | |
043e9bda | 15815 | |
e2c8b870 ML |
15816 | state->acquire_ctx = &ctx; |
15817 | ||
15818 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15819 | /* | |
15820 | * Force recalculation even if we restore | |
15821 | * current state. With fast modeset this may not result | |
15822 | * in a modeset when the state is compatible. | |
15823 | */ | |
15824 | crtc_state->mode_changed = true; | |
15825 | } | |
15826 | ||
15827 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15828 | } |
15829 | ||
e2c8b870 ML |
15830 | if (ret == -EDEADLK) { |
15831 | drm_modeset_backoff(&ctx); | |
15832 | goto retry; | |
15833 | } | |
043e9bda | 15834 | |
e2c8b870 ML |
15835 | drm_modeset_drop_locks(&ctx); |
15836 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15837 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15838 | |
e2c8b870 ML |
15839 | if (ret) { |
15840 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15841 | drm_atomic_state_free(state); | |
15842 | } | |
2c7111db CW |
15843 | } |
15844 | ||
15845 | void intel_modeset_gem_init(struct drm_device *dev) | |
15846 | { | |
484b41dd | 15847 | struct drm_crtc *c; |
2ff8fde1 | 15848 | struct drm_i915_gem_object *obj; |
e0d6149b | 15849 | int ret; |
484b41dd | 15850 | |
ae48434c | 15851 | intel_init_gt_powersave(dev); |
ae48434c | 15852 | |
1833b134 | 15853 | intel_modeset_init_hw(dev); |
02e792fb DV |
15854 | |
15855 | intel_setup_overlay(dev); | |
484b41dd JB |
15856 | |
15857 | /* | |
15858 | * Make sure any fbs we allocated at startup are properly | |
15859 | * pinned & fenced. When we do the allocation it's too early | |
15860 | * for this. | |
15861 | */ | |
70e1e0ec | 15862 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15863 | obj = intel_fb_obj(c->primary->fb); |
15864 | if (obj == NULL) | |
484b41dd JB |
15865 | continue; |
15866 | ||
e0d6149b | 15867 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
15868 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
15869 | c->primary->state->rotation); | |
e0d6149b TU |
15870 | mutex_unlock(&dev->struct_mutex); |
15871 | if (ret) { | |
484b41dd JB |
15872 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15873 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15874 | drm_framebuffer_unreference(c->primary->fb); |
15875 | c->primary->fb = NULL; | |
36750f28 | 15876 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15877 | update_state_fb(c->primary); |
36750f28 | 15878 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15879 | } |
15880 | } | |
0962c3c9 VS |
15881 | |
15882 | intel_backlight_register(dev); | |
79e53945 JB |
15883 | } |
15884 | ||
4932e2c3 ID |
15885 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15886 | { | |
15887 | struct drm_connector *connector = &intel_connector->base; | |
15888 | ||
15889 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15890 | drm_connector_unregister(connector); |
4932e2c3 ID |
15891 | } |
15892 | ||
79e53945 JB |
15893 | void intel_modeset_cleanup(struct drm_device *dev) |
15894 | { | |
652c393a | 15895 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15896 | struct intel_connector *connector; |
652c393a | 15897 | |
2eb5252e ID |
15898 | intel_disable_gt_powersave(dev); |
15899 | ||
0962c3c9 VS |
15900 | intel_backlight_unregister(dev); |
15901 | ||
fd0c0642 DV |
15902 | /* |
15903 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15904 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15905 | * experience fancy races otherwise. |
15906 | */ | |
2aeb7d3a | 15907 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15908 | |
fd0c0642 DV |
15909 | /* |
15910 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15911 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15912 | */ | |
f87ea761 | 15913 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15914 | |
723bfd70 JB |
15915 | intel_unregister_dsm_handler(); |
15916 | ||
c937ab3e | 15917 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15918 | |
1630fe75 CW |
15919 | /* flush any delayed tasks or pending work */ |
15920 | flush_scheduled_work(); | |
15921 | ||
db31af1d | 15922 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
15923 | for_each_intel_connector(dev, connector) |
15924 | connector->unregister(connector); | |
d9255d57 | 15925 | |
79e53945 | 15926 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15927 | |
15928 | intel_cleanup_overlay(dev); | |
ae48434c | 15929 | |
ae48434c | 15930 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
15931 | |
15932 | intel_teardown_gmbus(dev); | |
79e53945 JB |
15933 | } |
15934 | ||
f1c79df3 ZW |
15935 | /* |
15936 | * Return which encoder is currently attached for connector. | |
15937 | */ | |
df0e9248 | 15938 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15939 | { |
df0e9248 CW |
15940 | return &intel_attached_encoder(connector)->base; |
15941 | } | |
f1c79df3 | 15942 | |
df0e9248 CW |
15943 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15944 | struct intel_encoder *encoder) | |
15945 | { | |
15946 | connector->encoder = encoder; | |
15947 | drm_mode_connector_attach_encoder(&connector->base, | |
15948 | &encoder->base); | |
79e53945 | 15949 | } |
28d52043 DA |
15950 | |
15951 | /* | |
15952 | * set vga decode state - true == enable VGA decode | |
15953 | */ | |
15954 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15955 | { | |
15956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15957 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15958 | u16 gmch_ctrl; |
15959 | ||
75fa041d CW |
15960 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15961 | DRM_ERROR("failed to read control word\n"); | |
15962 | return -EIO; | |
15963 | } | |
15964 | ||
c0cc8a55 CW |
15965 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15966 | return 0; | |
15967 | ||
28d52043 DA |
15968 | if (state) |
15969 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15970 | else | |
15971 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15972 | |
15973 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15974 | DRM_ERROR("failed to write control word\n"); | |
15975 | return -EIO; | |
15976 | } | |
15977 | ||
28d52043 DA |
15978 | return 0; |
15979 | } | |
c4a1d9e4 | 15980 | |
c4a1d9e4 | 15981 | struct intel_display_error_state { |
ff57f1b0 PZ |
15982 | |
15983 | u32 power_well_driver; | |
15984 | ||
63b66e5b CW |
15985 | int num_transcoders; |
15986 | ||
c4a1d9e4 CW |
15987 | struct intel_cursor_error_state { |
15988 | u32 control; | |
15989 | u32 position; | |
15990 | u32 base; | |
15991 | u32 size; | |
52331309 | 15992 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15993 | |
15994 | struct intel_pipe_error_state { | |
ddf9c536 | 15995 | bool power_domain_on; |
c4a1d9e4 | 15996 | u32 source; |
f301b1e1 | 15997 | u32 stat; |
52331309 | 15998 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15999 | |
16000 | struct intel_plane_error_state { | |
16001 | u32 control; | |
16002 | u32 stride; | |
16003 | u32 size; | |
16004 | u32 pos; | |
16005 | u32 addr; | |
16006 | u32 surface; | |
16007 | u32 tile_offset; | |
52331309 | 16008 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16009 | |
16010 | struct intel_transcoder_error_state { | |
ddf9c536 | 16011 | bool power_domain_on; |
63b66e5b CW |
16012 | enum transcoder cpu_transcoder; |
16013 | ||
16014 | u32 conf; | |
16015 | ||
16016 | u32 htotal; | |
16017 | u32 hblank; | |
16018 | u32 hsync; | |
16019 | u32 vtotal; | |
16020 | u32 vblank; | |
16021 | u32 vsync; | |
16022 | } transcoder[4]; | |
c4a1d9e4 CW |
16023 | }; |
16024 | ||
16025 | struct intel_display_error_state * | |
16026 | intel_display_capture_error_state(struct drm_device *dev) | |
16027 | { | |
fbee40df | 16028 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16029 | struct intel_display_error_state *error; |
63b66e5b CW |
16030 | int transcoders[] = { |
16031 | TRANSCODER_A, | |
16032 | TRANSCODER_B, | |
16033 | TRANSCODER_C, | |
16034 | TRANSCODER_EDP, | |
16035 | }; | |
c4a1d9e4 CW |
16036 | int i; |
16037 | ||
63b66e5b CW |
16038 | if (INTEL_INFO(dev)->num_pipes == 0) |
16039 | return NULL; | |
16040 | ||
9d1cb914 | 16041 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16042 | if (error == NULL) |
16043 | return NULL; | |
16044 | ||
190be112 | 16045 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16046 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16047 | ||
055e393f | 16048 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16049 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16050 | __intel_display_power_is_enabled(dev_priv, |
16051 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16052 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16053 | continue; |
16054 | ||
5efb3e28 VS |
16055 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16056 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16057 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16058 | |
16059 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16060 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16061 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16062 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16063 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16064 | } | |
ca291363 PZ |
16065 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16066 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16067 | if (INTEL_INFO(dev)->gen >= 4) { |
16068 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16069 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16070 | } | |
16071 | ||
c4a1d9e4 | 16072 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16073 | |
3abfce77 | 16074 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16075 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16076 | } |
16077 | ||
4d1de975 | 16078 | /* Note: this does not include DSI transcoders. */ |
63b66e5b CW |
16079 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
16080 | if (HAS_DDI(dev_priv->dev)) | |
16081 | error->num_transcoders++; /* Account for eDP. */ | |
16082 | ||
16083 | for (i = 0; i < error->num_transcoders; i++) { | |
16084 | enum transcoder cpu_transcoder = transcoders[i]; | |
16085 | ||
ddf9c536 | 16086 | error->transcoder[i].power_domain_on = |
f458ebbc | 16087 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16088 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16089 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16090 | continue; |
16091 | ||
63b66e5b CW |
16092 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16093 | ||
16094 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16095 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16096 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16097 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16098 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16099 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16100 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16101 | } |
16102 | ||
16103 | return error; | |
16104 | } | |
16105 | ||
edc3d884 MK |
16106 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16107 | ||
c4a1d9e4 | 16108 | void |
edc3d884 | 16109 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16110 | struct drm_device *dev, |
16111 | struct intel_display_error_state *error) | |
16112 | { | |
055e393f | 16113 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16114 | int i; |
16115 | ||
63b66e5b CW |
16116 | if (!error) |
16117 | return; | |
16118 | ||
edc3d884 | 16119 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16120 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16121 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16122 | error->power_well_driver); |
055e393f | 16123 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16124 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16125 | err_printf(m, " Power: %s\n", |
87ad3212 | 16126 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16127 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16128 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16129 | |
16130 | err_printf(m, "Plane [%d]:\n", i); | |
16131 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16132 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16133 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16134 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16135 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16136 | } |
4b71a570 | 16137 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16138 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16139 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16140 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16141 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16142 | } |
16143 | ||
edc3d884 MK |
16144 | err_printf(m, "Cursor [%d]:\n", i); |
16145 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16146 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16147 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16148 | } |
63b66e5b CW |
16149 | |
16150 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16151 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16152 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16153 | err_printf(m, " Power: %s\n", |
87ad3212 | 16154 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16155 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16156 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16157 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16158 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16159 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16160 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16161 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16162 | } | |
c4a1d9e4 | 16163 | } |