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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
465c120c MR |
75 | }; |
76 | ||
3d7d6510 MR |
77 | /* Cursor formats */ |
78 | static const uint32_t intel_cursor_formats[] = { | |
79 | DRM_FORMAT_ARGB8888, | |
80 | }; | |
81 | ||
6b383a7f | 82 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 83 | |
f1f644dc | 84 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 85 | struct intel_crtc_state *pipe_config); |
18442d08 | 86 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 87 | struct intel_crtc_state *pipe_config); |
f1f644dc | 88 | |
568c634a | 89 | static int intel_set_mode(struct drm_atomic_state *state); |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
97 | struct intel_link_m_n *m_n, |
98 | struct intel_link_m_n *m2_n2); | |
29407aab | 99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
d288f65f | 104 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 105 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
106 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
107 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
108 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
109 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
110 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
111 | int num_connectors); | |
043e9bda | 112 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
e7457a9a | 113 | |
0e32b39c DA |
114 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
115 | { | |
116 | if (!connector->mst_port) | |
117 | return connector->encoder; | |
118 | else | |
119 | return &connector->mst_port->mst_encoders[pipe]->base; | |
120 | } | |
121 | ||
79e53945 | 122 | typedef struct { |
0206e353 | 123 | int min, max; |
79e53945 JB |
124 | } intel_range_t; |
125 | ||
126 | typedef struct { | |
0206e353 AJ |
127 | int dot_limit; |
128 | int p2_slow, p2_fast; | |
79e53945 JB |
129 | } intel_p2_t; |
130 | ||
d4906093 ML |
131 | typedef struct intel_limit intel_limit_t; |
132 | struct intel_limit { | |
0206e353 AJ |
133 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
134 | intel_p2_t p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
d2acd215 DV |
137 | int |
138 | intel_pch_rawclk(struct drm_device *dev) | |
139 | { | |
140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
141 | ||
142 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
143 | ||
144 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
145 | } | |
146 | ||
021357ac CW |
147 | static inline u32 /* units of 100MHz */ |
148 | intel_fdi_link_freq(struct drm_device *dev) | |
149 | { | |
8b99e68c CW |
150 | if (IS_GEN5(dev)) { |
151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
152 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
153 | } else | |
154 | return 27; | |
021357ac CW |
155 | } |
156 | ||
5d536e28 | 157 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 158 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 159 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 160 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
161 | .m = { .min = 96, .max = 140 }, |
162 | .m1 = { .min = 18, .max = 26 }, | |
163 | .m2 = { .min = 6, .max = 16 }, | |
164 | .p = { .min = 4, .max = 128 }, | |
165 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
166 | .p2 = { .dot_limit = 165000, |
167 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
168 | }; |
169 | ||
5d536e28 DV |
170 | static const intel_limit_t intel_limits_i8xx_dvo = { |
171 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 172 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 173 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
174 | .m = { .min = 96, .max = 140 }, |
175 | .m1 = { .min = 18, .max = 26 }, | |
176 | .m2 = { .min = 6, .max = 16 }, | |
177 | .p = { .min = 4, .max = 128 }, | |
178 | .p1 = { .min = 2, .max = 33 }, | |
179 | .p2 = { .dot_limit = 165000, | |
180 | .p2_slow = 4, .p2_fast = 4 }, | |
181 | }; | |
182 | ||
e4b36699 | 183 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 184 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 185 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 186 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
187 | .m = { .min = 96, .max = 140 }, |
188 | .m1 = { .min = 18, .max = 26 }, | |
189 | .m2 = { .min = 6, .max = 16 }, | |
190 | .p = { .min = 4, .max = 128 }, | |
191 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
192 | .p2 = { .dot_limit = 165000, |
193 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 194 | }; |
273e27ca | 195 | |
e4b36699 | 196 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
197 | .dot = { .min = 20000, .max = 400000 }, |
198 | .vco = { .min = 1400000, .max = 2800000 }, | |
199 | .n = { .min = 1, .max = 6 }, | |
200 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
201 | .m1 = { .min = 8, .max = 18 }, |
202 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
203 | .p = { .min = 5, .max = 80 }, |
204 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
205 | .p2 = { .dot_limit = 200000, |
206 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
207 | }; |
208 | ||
209 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
210 | .dot = { .min = 20000, .max = 400000 }, |
211 | .vco = { .min = 1400000, .max = 2800000 }, | |
212 | .n = { .min = 1, .max = 6 }, | |
213 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
214 | .m1 = { .min = 8, .max = 18 }, |
215 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
216 | .p = { .min = 7, .max = 98 }, |
217 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
218 | .p2 = { .dot_limit = 112000, |
219 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
220 | }; |
221 | ||
273e27ca | 222 | |
e4b36699 | 223 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
224 | .dot = { .min = 25000, .max = 270000 }, |
225 | .vco = { .min = 1750000, .max = 3500000}, | |
226 | .n = { .min = 1, .max = 4 }, | |
227 | .m = { .min = 104, .max = 138 }, | |
228 | .m1 = { .min = 17, .max = 23 }, | |
229 | .m2 = { .min = 5, .max = 11 }, | |
230 | .p = { .min = 10, .max = 30 }, | |
231 | .p1 = { .min = 1, .max = 3}, | |
232 | .p2 = { .dot_limit = 270000, | |
233 | .p2_slow = 10, | |
234 | .p2_fast = 10 | |
044c7c41 | 235 | }, |
e4b36699 KP |
236 | }; |
237 | ||
238 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
239 | .dot = { .min = 22000, .max = 400000 }, |
240 | .vco = { .min = 1750000, .max = 3500000}, | |
241 | .n = { .min = 1, .max = 4 }, | |
242 | .m = { .min = 104, .max = 138 }, | |
243 | .m1 = { .min = 16, .max = 23 }, | |
244 | .m2 = { .min = 5, .max = 11 }, | |
245 | .p = { .min = 5, .max = 80 }, | |
246 | .p1 = { .min = 1, .max = 8}, | |
247 | .p2 = { .dot_limit = 165000, | |
248 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
249 | }; |
250 | ||
251 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
252 | .dot = { .min = 20000, .max = 115000 }, |
253 | .vco = { .min = 1750000, .max = 3500000 }, | |
254 | .n = { .min = 1, .max = 3 }, | |
255 | .m = { .min = 104, .max = 138 }, | |
256 | .m1 = { .min = 17, .max = 23 }, | |
257 | .m2 = { .min = 5, .max = 11 }, | |
258 | .p = { .min = 28, .max = 112 }, | |
259 | .p1 = { .min = 2, .max = 8 }, | |
260 | .p2 = { .dot_limit = 0, | |
261 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 262 | }, |
e4b36699 KP |
263 | }; |
264 | ||
265 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
266 | .dot = { .min = 80000, .max = 224000 }, |
267 | .vco = { .min = 1750000, .max = 3500000 }, | |
268 | .n = { .min = 1, .max = 3 }, | |
269 | .m = { .min = 104, .max = 138 }, | |
270 | .m1 = { .min = 17, .max = 23 }, | |
271 | .m2 = { .min = 5, .max = 11 }, | |
272 | .p = { .min = 14, .max = 42 }, | |
273 | .p1 = { .min = 2, .max = 6 }, | |
274 | .p2 = { .dot_limit = 0, | |
275 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 276 | }, |
e4b36699 KP |
277 | }; |
278 | ||
f2b115e6 | 279 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
280 | .dot = { .min = 20000, .max = 400000}, |
281 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 282 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
283 | .n = { .min = 3, .max = 6 }, |
284 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 285 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
286 | .m1 = { .min = 0, .max = 0 }, |
287 | .m2 = { .min = 0, .max = 254 }, | |
288 | .p = { .min = 5, .max = 80 }, | |
289 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
290 | .p2 = { .dot_limit = 200000, |
291 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
292 | }; |
293 | ||
f2b115e6 | 294 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
295 | .dot = { .min = 20000, .max = 400000 }, |
296 | .vco = { .min = 1700000, .max = 3500000 }, | |
297 | .n = { .min = 3, .max = 6 }, | |
298 | .m = { .min = 2, .max = 256 }, | |
299 | .m1 = { .min = 0, .max = 0 }, | |
300 | .m2 = { .min = 0, .max = 254 }, | |
301 | .p = { .min = 7, .max = 112 }, | |
302 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
303 | .p2 = { .dot_limit = 112000, |
304 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
305 | }; |
306 | ||
273e27ca EA |
307 | /* Ironlake / Sandybridge |
308 | * | |
309 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
310 | * the range value for them is (actual_value - 2). | |
311 | */ | |
b91ad0ec | 312 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
313 | .dot = { .min = 25000, .max = 350000 }, |
314 | .vco = { .min = 1760000, .max = 3510000 }, | |
315 | .n = { .min = 1, .max = 5 }, | |
316 | .m = { .min = 79, .max = 127 }, | |
317 | .m1 = { .min = 12, .max = 22 }, | |
318 | .m2 = { .min = 5, .max = 9 }, | |
319 | .p = { .min = 5, .max = 80 }, | |
320 | .p1 = { .min = 1, .max = 8 }, | |
321 | .p2 = { .dot_limit = 225000, | |
322 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
323 | }; |
324 | ||
b91ad0ec | 325 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
326 | .dot = { .min = 25000, .max = 350000 }, |
327 | .vco = { .min = 1760000, .max = 3510000 }, | |
328 | .n = { .min = 1, .max = 3 }, | |
329 | .m = { .min = 79, .max = 118 }, | |
330 | .m1 = { .min = 12, .max = 22 }, | |
331 | .m2 = { .min = 5, .max = 9 }, | |
332 | .p = { .min = 28, .max = 112 }, | |
333 | .p1 = { .min = 2, .max = 8 }, | |
334 | .p2 = { .dot_limit = 225000, | |
335 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
336 | }; |
337 | ||
338 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
339 | .dot = { .min = 25000, .max = 350000 }, |
340 | .vco = { .min = 1760000, .max = 3510000 }, | |
341 | .n = { .min = 1, .max = 3 }, | |
342 | .m = { .min = 79, .max = 127 }, | |
343 | .m1 = { .min = 12, .max = 22 }, | |
344 | .m2 = { .min = 5, .max = 9 }, | |
345 | .p = { .min = 14, .max = 56 }, | |
346 | .p1 = { .min = 2, .max = 8 }, | |
347 | .p2 = { .dot_limit = 225000, | |
348 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
349 | }; |
350 | ||
273e27ca | 351 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 352 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
353 | .dot = { .min = 25000, .max = 350000 }, |
354 | .vco = { .min = 1760000, .max = 3510000 }, | |
355 | .n = { .min = 1, .max = 2 }, | |
356 | .m = { .min = 79, .max = 126 }, | |
357 | .m1 = { .min = 12, .max = 22 }, | |
358 | .m2 = { .min = 5, .max = 9 }, | |
359 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 360 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
361 | .p2 = { .dot_limit = 225000, |
362 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
363 | }; |
364 | ||
365 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
366 | .dot = { .min = 25000, .max = 350000 }, |
367 | .vco = { .min = 1760000, .max = 3510000 }, | |
368 | .n = { .min = 1, .max = 3 }, | |
369 | .m = { .min = 79, .max = 126 }, | |
370 | .m1 = { .min = 12, .max = 22 }, | |
371 | .m2 = { .min = 5, .max = 9 }, | |
372 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 373 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
374 | .p2 = { .dot_limit = 225000, |
375 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
376 | }; |
377 | ||
dc730512 | 378 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
379 | /* |
380 | * These are the data rate limits (measured in fast clocks) | |
381 | * since those are the strictest limits we have. The fast | |
382 | * clock and actual rate limits are more relaxed, so checking | |
383 | * them would make no difference. | |
384 | */ | |
385 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 386 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 387 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
388 | .m1 = { .min = 2, .max = 3 }, |
389 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 390 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 391 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
392 | }; |
393 | ||
ef9348c8 CML |
394 | static const intel_limit_t intel_limits_chv = { |
395 | /* | |
396 | * These are the data rate limits (measured in fast clocks) | |
397 | * since those are the strictest limits we have. The fast | |
398 | * clock and actual rate limits are more relaxed, so checking | |
399 | * them would make no difference. | |
400 | */ | |
401 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 402 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
403 | .n = { .min = 1, .max = 1 }, |
404 | .m1 = { .min = 2, .max = 2 }, | |
405 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
406 | .p1 = { .min = 2, .max = 4 }, | |
407 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
408 | }; | |
409 | ||
5ab7b0b7 ID |
410 | static const intel_limit_t intel_limits_bxt = { |
411 | /* FIXME: find real dot limits */ | |
412 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 413 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
414 | .n = { .min = 1, .max = 1 }, |
415 | .m1 = { .min = 2, .max = 2 }, | |
416 | /* FIXME: find real m2 limits */ | |
417 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
418 | .p1 = { .min = 2, .max = 4 }, | |
419 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
420 | }; | |
421 | ||
cdba954e ACO |
422 | static bool |
423 | needs_modeset(struct drm_crtc_state *state) | |
424 | { | |
425 | return state->mode_changed || state->active_changed; | |
426 | } | |
427 | ||
e0638cdf PZ |
428 | /** |
429 | * Returns whether any output on the specified pipe is of the specified type | |
430 | */ | |
4093561b | 431 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 432 | { |
409ee761 | 433 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
434 | struct intel_encoder *encoder; |
435 | ||
409ee761 | 436 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
437 | if (encoder->type == type) |
438 | return true; | |
439 | ||
440 | return false; | |
441 | } | |
442 | ||
d0737e1d ACO |
443 | /** |
444 | * Returns whether any output on the specified pipe will have the specified | |
445 | * type after a staged modeset is complete, i.e., the same as | |
446 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
447 | * encoder->crtc. | |
448 | */ | |
a93e255f ACO |
449 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
450 | int type) | |
d0737e1d | 451 | { |
a93e255f | 452 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 453 | struct drm_connector *connector; |
a93e255f | 454 | struct drm_connector_state *connector_state; |
d0737e1d | 455 | struct intel_encoder *encoder; |
a93e255f ACO |
456 | int i, num_connectors = 0; |
457 | ||
da3ced29 | 458 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
459 | if (connector_state->crtc != crtc_state->base.crtc) |
460 | continue; | |
461 | ||
462 | num_connectors++; | |
d0737e1d | 463 | |
a93e255f ACO |
464 | encoder = to_intel_encoder(connector_state->best_encoder); |
465 | if (encoder->type == type) | |
d0737e1d | 466 | return true; |
a93e255f ACO |
467 | } |
468 | ||
469 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
470 | |
471 | return false; | |
472 | } | |
473 | ||
a93e255f ACO |
474 | static const intel_limit_t * |
475 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 476 | { |
a93e255f | 477 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 478 | const intel_limit_t *limit; |
b91ad0ec | 479 | |
a93e255f | 480 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 481 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 482 | if (refclk == 100000) |
b91ad0ec ZW |
483 | limit = &intel_limits_ironlake_dual_lvds_100m; |
484 | else | |
485 | limit = &intel_limits_ironlake_dual_lvds; | |
486 | } else { | |
1b894b59 | 487 | if (refclk == 100000) |
b91ad0ec ZW |
488 | limit = &intel_limits_ironlake_single_lvds_100m; |
489 | else | |
490 | limit = &intel_limits_ironlake_single_lvds; | |
491 | } | |
c6bb3538 | 492 | } else |
b91ad0ec | 493 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
494 | |
495 | return limit; | |
496 | } | |
497 | ||
a93e255f ACO |
498 | static const intel_limit_t * |
499 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 500 | { |
a93e255f | 501 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
502 | const intel_limit_t *limit; |
503 | ||
a93e255f | 504 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 505 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 506 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 507 | else |
e4b36699 | 508 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
509 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
510 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 511 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 512 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 513 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 514 | } else /* The option is for other outputs */ |
e4b36699 | 515 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
516 | |
517 | return limit; | |
518 | } | |
519 | ||
a93e255f ACO |
520 | static const intel_limit_t * |
521 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 522 | { |
a93e255f | 523 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
524 | const intel_limit_t *limit; |
525 | ||
5ab7b0b7 ID |
526 | if (IS_BROXTON(dev)) |
527 | limit = &intel_limits_bxt; | |
528 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 529 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 530 | else if (IS_G4X(dev)) { |
a93e255f | 531 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 532 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 533 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 534 | limit = &intel_limits_pineview_lvds; |
2177832f | 535 | else |
f2b115e6 | 536 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
537 | } else if (IS_CHERRYVIEW(dev)) { |
538 | limit = &intel_limits_chv; | |
a0c4da24 | 539 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 540 | limit = &intel_limits_vlv; |
a6c45cf0 | 541 | } else if (!IS_GEN2(dev)) { |
a93e255f | 542 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
543 | limit = &intel_limits_i9xx_lvds; |
544 | else | |
545 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 546 | } else { |
a93e255f | 547 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 548 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 549 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 550 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
551 | else |
552 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
553 | } |
554 | return limit; | |
555 | } | |
556 | ||
dccbea3b ID |
557 | /* |
558 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
559 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
560 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
561 | * The helpers' return value is the rate of the clock that is fed to the | |
562 | * display engine's pipe which can be the above fast dot clock rate or a | |
563 | * divided-down version of it. | |
564 | */ | |
f2b115e6 | 565 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 566 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 567 | { |
2177832f SL |
568 | clock->m = clock->m2 + 2; |
569 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 570 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 571 | return 0; |
fb03ac01 VS |
572 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
573 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
574 | |
575 | return clock->dot; | |
2177832f SL |
576 | } |
577 | ||
7429e9d4 DV |
578 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
579 | { | |
580 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
581 | } | |
582 | ||
dccbea3b | 583 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 584 | { |
7429e9d4 | 585 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 586 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 587 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 588 | return 0; |
fb03ac01 VS |
589 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
590 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
591 | |
592 | return clock->dot; | |
79e53945 JB |
593 | } |
594 | ||
dccbea3b | 595 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
596 | { |
597 | clock->m = clock->m1 * clock->m2; | |
598 | clock->p = clock->p1 * clock->p2; | |
599 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 600 | return 0; |
589eca67 ID |
601 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
602 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
603 | |
604 | return clock->dot / 5; | |
589eca67 ID |
605 | } |
606 | ||
dccbea3b | 607 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
608 | { |
609 | clock->m = clock->m1 * clock->m2; | |
610 | clock->p = clock->p1 * clock->p2; | |
611 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 612 | return 0; |
ef9348c8 CML |
613 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
614 | clock->n << 22); | |
615 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
616 | |
617 | return clock->dot / 5; | |
ef9348c8 CML |
618 | } |
619 | ||
7c04d1d9 | 620 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
621 | /** |
622 | * Returns whether the given set of divisors are valid for a given refclk with | |
623 | * the given connectors. | |
624 | */ | |
625 | ||
1b894b59 CW |
626 | static bool intel_PLL_is_valid(struct drm_device *dev, |
627 | const intel_limit_t *limit, | |
628 | const intel_clock_t *clock) | |
79e53945 | 629 | { |
f01b7962 VS |
630 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
631 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 632 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 633 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 634 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 635 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 636 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 637 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 638 | |
5ab7b0b7 | 639 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
640 | if (clock->m1 <= clock->m2) |
641 | INTELPllInvalid("m1 <= m2\n"); | |
642 | ||
5ab7b0b7 | 643 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
644 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
645 | INTELPllInvalid("p out of range\n"); | |
646 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
647 | INTELPllInvalid("m out of range\n"); | |
648 | } | |
649 | ||
79e53945 | 650 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 651 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
652 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
653 | * connector, etc., rather than just a single range. | |
654 | */ | |
655 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 656 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
657 | |
658 | return true; | |
659 | } | |
660 | ||
3b1429d9 VS |
661 | static int |
662 | i9xx_select_p2_div(const intel_limit_t *limit, | |
663 | const struct intel_crtc_state *crtc_state, | |
664 | int target) | |
79e53945 | 665 | { |
3b1429d9 | 666 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 667 | |
a93e255f | 668 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 669 | /* |
a210b028 DV |
670 | * For LVDS just rely on its current settings for dual-channel. |
671 | * We haven't figured out how to reliably set up different | |
672 | * single/dual channel state, if we even can. | |
79e53945 | 673 | */ |
1974cad0 | 674 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 675 | return limit->p2.p2_fast; |
79e53945 | 676 | else |
3b1429d9 | 677 | return limit->p2.p2_slow; |
79e53945 JB |
678 | } else { |
679 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 680 | return limit->p2.p2_slow; |
79e53945 | 681 | else |
3b1429d9 | 682 | return limit->p2.p2_fast; |
79e53945 | 683 | } |
3b1429d9 VS |
684 | } |
685 | ||
686 | static bool | |
687 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
688 | struct intel_crtc_state *crtc_state, | |
689 | int target, int refclk, intel_clock_t *match_clock, | |
690 | intel_clock_t *best_clock) | |
691 | { | |
692 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
693 | intel_clock_t clock; | |
694 | int err = target; | |
79e53945 | 695 | |
0206e353 | 696 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 697 | |
3b1429d9 VS |
698 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
699 | ||
42158660 ZY |
700 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
701 | clock.m1++) { | |
702 | for (clock.m2 = limit->m2.min; | |
703 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 704 | if (clock.m2 >= clock.m1) |
42158660 ZY |
705 | break; |
706 | for (clock.n = limit->n.min; | |
707 | clock.n <= limit->n.max; clock.n++) { | |
708 | for (clock.p1 = limit->p1.min; | |
709 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
710 | int this_err; |
711 | ||
dccbea3b | 712 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
713 | if (!intel_PLL_is_valid(dev, limit, |
714 | &clock)) | |
715 | continue; | |
716 | if (match_clock && | |
717 | clock.p != match_clock->p) | |
718 | continue; | |
719 | ||
720 | this_err = abs(clock.dot - target); | |
721 | if (this_err < err) { | |
722 | *best_clock = clock; | |
723 | err = this_err; | |
724 | } | |
725 | } | |
726 | } | |
727 | } | |
728 | } | |
729 | ||
730 | return (err != target); | |
731 | } | |
732 | ||
733 | static bool | |
a93e255f ACO |
734 | pnv_find_best_dpll(const intel_limit_t *limit, |
735 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
736 | int target, int refclk, intel_clock_t *match_clock, |
737 | intel_clock_t *best_clock) | |
79e53945 | 738 | { |
3b1429d9 | 739 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 740 | intel_clock_t clock; |
79e53945 JB |
741 | int err = target; |
742 | ||
0206e353 | 743 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 744 | |
3b1429d9 VS |
745 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
746 | ||
42158660 ZY |
747 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
748 | clock.m1++) { | |
749 | for (clock.m2 = limit->m2.min; | |
750 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
751 | for (clock.n = limit->n.min; |
752 | clock.n <= limit->n.max; clock.n++) { | |
753 | for (clock.p1 = limit->p1.min; | |
754 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
755 | int this_err; |
756 | ||
dccbea3b | 757 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
758 | if (!intel_PLL_is_valid(dev, limit, |
759 | &clock)) | |
79e53945 | 760 | continue; |
cec2f356 SP |
761 | if (match_clock && |
762 | clock.p != match_clock->p) | |
763 | continue; | |
79e53945 JB |
764 | |
765 | this_err = abs(clock.dot - target); | |
766 | if (this_err < err) { | |
767 | *best_clock = clock; | |
768 | err = this_err; | |
769 | } | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | ||
775 | return (err != target); | |
776 | } | |
777 | ||
d4906093 | 778 | static bool |
a93e255f ACO |
779 | g4x_find_best_dpll(const intel_limit_t *limit, |
780 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
781 | int target, int refclk, intel_clock_t *match_clock, |
782 | intel_clock_t *best_clock) | |
d4906093 | 783 | { |
3b1429d9 | 784 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
785 | intel_clock_t clock; |
786 | int max_n; | |
3b1429d9 | 787 | bool found = false; |
6ba770dc AJ |
788 | /* approximately equals target * 0.00585 */ |
789 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
790 | |
791 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
792 | |
793 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
794 | ||
d4906093 | 795 | max_n = limit->n.max; |
f77f13e2 | 796 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 797 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 798 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
799 | for (clock.m1 = limit->m1.max; |
800 | clock.m1 >= limit->m1.min; clock.m1--) { | |
801 | for (clock.m2 = limit->m2.max; | |
802 | clock.m2 >= limit->m2.min; clock.m2--) { | |
803 | for (clock.p1 = limit->p1.max; | |
804 | clock.p1 >= limit->p1.min; clock.p1--) { | |
805 | int this_err; | |
806 | ||
dccbea3b | 807 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
808 | if (!intel_PLL_is_valid(dev, limit, |
809 | &clock)) | |
d4906093 | 810 | continue; |
1b894b59 CW |
811 | |
812 | this_err = abs(clock.dot - target); | |
d4906093 ML |
813 | if (this_err < err_most) { |
814 | *best_clock = clock; | |
815 | err_most = this_err; | |
816 | max_n = clock.n; | |
817 | found = true; | |
818 | } | |
819 | } | |
820 | } | |
821 | } | |
822 | } | |
2c07245f ZW |
823 | return found; |
824 | } | |
825 | ||
d5dd62bd ID |
826 | /* |
827 | * Check if the calculated PLL configuration is more optimal compared to the | |
828 | * best configuration and error found so far. Return the calculated error. | |
829 | */ | |
830 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
831 | const intel_clock_t *calculated_clock, | |
832 | const intel_clock_t *best_clock, | |
833 | unsigned int best_error_ppm, | |
834 | unsigned int *error_ppm) | |
835 | { | |
9ca3ba01 ID |
836 | /* |
837 | * For CHV ignore the error and consider only the P value. | |
838 | * Prefer a bigger P value based on HW requirements. | |
839 | */ | |
840 | if (IS_CHERRYVIEW(dev)) { | |
841 | *error_ppm = 0; | |
842 | ||
843 | return calculated_clock->p > best_clock->p; | |
844 | } | |
845 | ||
24be4e46 ID |
846 | if (WARN_ON_ONCE(!target_freq)) |
847 | return false; | |
848 | ||
d5dd62bd ID |
849 | *error_ppm = div_u64(1000000ULL * |
850 | abs(target_freq - calculated_clock->dot), | |
851 | target_freq); | |
852 | /* | |
853 | * Prefer a better P value over a better (smaller) error if the error | |
854 | * is small. Ensure this preference for future configurations too by | |
855 | * setting the error to 0. | |
856 | */ | |
857 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
858 | *error_ppm = 0; | |
859 | ||
860 | return true; | |
861 | } | |
862 | ||
863 | return *error_ppm + 10 < best_error_ppm; | |
864 | } | |
865 | ||
a0c4da24 | 866 | static bool |
a93e255f ACO |
867 | vlv_find_best_dpll(const intel_limit_t *limit, |
868 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
869 | int target, int refclk, intel_clock_t *match_clock, |
870 | intel_clock_t *best_clock) | |
a0c4da24 | 871 | { |
a93e255f | 872 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 873 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 874 | intel_clock_t clock; |
69e4f900 | 875 | unsigned int bestppm = 1000000; |
27e639bf VS |
876 | /* min update 19.2 MHz */ |
877 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 878 | bool found = false; |
a0c4da24 | 879 | |
6b4bf1c4 VS |
880 | target *= 5; /* fast clock */ |
881 | ||
882 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
883 | |
884 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 885 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 886 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 887 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 888 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 889 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 890 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 891 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 892 | unsigned int ppm; |
69e4f900 | 893 | |
6b4bf1c4 VS |
894 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
895 | refclk * clock.m1); | |
896 | ||
dccbea3b | 897 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 898 | |
f01b7962 VS |
899 | if (!intel_PLL_is_valid(dev, limit, |
900 | &clock)) | |
43b0ac53 VS |
901 | continue; |
902 | ||
d5dd62bd ID |
903 | if (!vlv_PLL_is_optimal(dev, target, |
904 | &clock, | |
905 | best_clock, | |
906 | bestppm, &ppm)) | |
907 | continue; | |
6b4bf1c4 | 908 | |
d5dd62bd ID |
909 | *best_clock = clock; |
910 | bestppm = ppm; | |
911 | found = true; | |
a0c4da24 JB |
912 | } |
913 | } | |
914 | } | |
915 | } | |
a0c4da24 | 916 | |
49e497ef | 917 | return found; |
a0c4da24 | 918 | } |
a4fc5ed6 | 919 | |
ef9348c8 | 920 | static bool |
a93e255f ACO |
921 | chv_find_best_dpll(const intel_limit_t *limit, |
922 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
923 | int target, int refclk, intel_clock_t *match_clock, |
924 | intel_clock_t *best_clock) | |
925 | { | |
a93e255f | 926 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 927 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 928 | unsigned int best_error_ppm; |
ef9348c8 CML |
929 | intel_clock_t clock; |
930 | uint64_t m2; | |
931 | int found = false; | |
932 | ||
933 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 934 | best_error_ppm = 1000000; |
ef9348c8 CML |
935 | |
936 | /* | |
937 | * Based on hardware doc, the n always set to 1, and m1 always | |
938 | * set to 2. If requires to support 200Mhz refclk, we need to | |
939 | * revisit this because n may not 1 anymore. | |
940 | */ | |
941 | clock.n = 1, clock.m1 = 2; | |
942 | target *= 5; /* fast clock */ | |
943 | ||
944 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
945 | for (clock.p2 = limit->p2.p2_fast; | |
946 | clock.p2 >= limit->p2.p2_slow; | |
947 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 948 | unsigned int error_ppm; |
ef9348c8 CML |
949 | |
950 | clock.p = clock.p1 * clock.p2; | |
951 | ||
952 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
953 | clock.n) << 22, refclk * clock.m1); | |
954 | ||
955 | if (m2 > INT_MAX/clock.m1) | |
956 | continue; | |
957 | ||
958 | clock.m2 = m2; | |
959 | ||
dccbea3b | 960 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
961 | |
962 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
963 | continue; | |
964 | ||
9ca3ba01 ID |
965 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
966 | best_error_ppm, &error_ppm)) | |
967 | continue; | |
968 | ||
969 | *best_clock = clock; | |
970 | best_error_ppm = error_ppm; | |
971 | found = true; | |
ef9348c8 CML |
972 | } |
973 | } | |
974 | ||
975 | return found; | |
976 | } | |
977 | ||
5ab7b0b7 ID |
978 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
979 | intel_clock_t *best_clock) | |
980 | { | |
981 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
982 | ||
983 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
984 | target_clock, refclk, NULL, best_clock); | |
985 | } | |
986 | ||
20ddf665 VS |
987 | bool intel_crtc_active(struct drm_crtc *crtc) |
988 | { | |
989 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
990 | ||
991 | /* Be paranoid as we can arrive here with only partial | |
992 | * state retrieved from the hardware during setup. | |
993 | * | |
241bfc38 | 994 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
995 | * as Haswell has gained clock readout/fastboot support. |
996 | * | |
66e514c1 | 997 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 998 | * properly reconstruct framebuffers. |
c3d1f436 MR |
999 | * |
1000 | * FIXME: The intel_crtc->active here should be switched to | |
1001 | * crtc->state->active once we have proper CRTC states wired up | |
1002 | * for atomic. | |
20ddf665 | 1003 | */ |
c3d1f436 | 1004 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1005 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1006 | } |
1007 | ||
a5c961d1 PZ |
1008 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1009 | enum pipe pipe) | |
1010 | { | |
1011 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1012 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1013 | ||
6e3c9717 | 1014 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1015 | } |
1016 | ||
fbf49ea2 VS |
1017 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1018 | { | |
1019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1020 | u32 reg = PIPEDSL(pipe); | |
1021 | u32 line1, line2; | |
1022 | u32 line_mask; | |
1023 | ||
1024 | if (IS_GEN2(dev)) | |
1025 | line_mask = DSL_LINEMASK_GEN2; | |
1026 | else | |
1027 | line_mask = DSL_LINEMASK_GEN3; | |
1028 | ||
1029 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1030 | msleep(5); |
fbf49ea2 VS |
1031 | line2 = I915_READ(reg) & line_mask; |
1032 | ||
1033 | return line1 == line2; | |
1034 | } | |
1035 | ||
ab7ad7f6 KP |
1036 | /* |
1037 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1038 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1039 | * |
1040 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1041 | * spinning on the vblank interrupt status bit, since we won't actually | |
1042 | * see an interrupt when the pipe is disabled. | |
1043 | * | |
ab7ad7f6 KP |
1044 | * On Gen4 and above: |
1045 | * wait for the pipe register state bit to turn off | |
1046 | * | |
1047 | * Otherwise: | |
1048 | * wait for the display line value to settle (it usually | |
1049 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1050 | * |
9d0498a2 | 1051 | */ |
575f7ab7 | 1052 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1053 | { |
575f7ab7 | 1054 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1055 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1056 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1057 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1058 | |
1059 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1060 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1061 | |
1062 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1063 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1064 | 100)) | |
284637d9 | 1065 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1066 | } else { |
ab7ad7f6 | 1067 | /* Wait for the display line to settle */ |
fbf49ea2 | 1068 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1069 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1070 | } |
79e53945 JB |
1071 | } |
1072 | ||
b0ea7d37 DL |
1073 | /* |
1074 | * ibx_digital_port_connected - is the specified port connected? | |
1075 | * @dev_priv: i915 private structure | |
1076 | * @port: the port to test | |
1077 | * | |
1078 | * Returns true if @port is connected, false otherwise. | |
1079 | */ | |
1080 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1081 | struct intel_digital_port *port) | |
1082 | { | |
1083 | u32 bit; | |
1084 | ||
c36346e3 | 1085 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1086 | switch (port->port) { |
c36346e3 DL |
1087 | case PORT_B: |
1088 | bit = SDE_PORTB_HOTPLUG; | |
1089 | break; | |
1090 | case PORT_C: | |
1091 | bit = SDE_PORTC_HOTPLUG; | |
1092 | break; | |
1093 | case PORT_D: | |
1094 | bit = SDE_PORTD_HOTPLUG; | |
1095 | break; | |
1096 | default: | |
1097 | return true; | |
1098 | } | |
1099 | } else { | |
eba905b2 | 1100 | switch (port->port) { |
c36346e3 DL |
1101 | case PORT_B: |
1102 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1103 | break; | |
1104 | case PORT_C: | |
1105 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1106 | break; | |
1107 | case PORT_D: | |
1108 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1109 | break; | |
1110 | default: | |
1111 | return true; | |
1112 | } | |
b0ea7d37 DL |
1113 | } |
1114 | ||
1115 | return I915_READ(SDEISR) & bit; | |
1116 | } | |
1117 | ||
b24e7179 JB |
1118 | static const char *state_string(bool enabled) |
1119 | { | |
1120 | return enabled ? "on" : "off"; | |
1121 | } | |
1122 | ||
1123 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1124 | void assert_pll(struct drm_i915_private *dev_priv, |
1125 | enum pipe pipe, bool state) | |
b24e7179 JB |
1126 | { |
1127 | int reg; | |
1128 | u32 val; | |
1129 | bool cur_state; | |
1130 | ||
1131 | reg = DPLL(pipe); | |
1132 | val = I915_READ(reg); | |
1133 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1134 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1135 | "PLL state assertion failure (expected %s, current %s)\n", |
1136 | state_string(state), state_string(cur_state)); | |
1137 | } | |
b24e7179 | 1138 | |
23538ef1 JN |
1139 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1140 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1141 | { | |
1142 | u32 val; | |
1143 | bool cur_state; | |
1144 | ||
a580516d | 1145 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1146 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1147 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1148 | |
1149 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1150 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1151 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1152 | state_string(state), state_string(cur_state)); | |
1153 | } | |
1154 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1155 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1156 | ||
55607e8a | 1157 | struct intel_shared_dpll * |
e2b78267 DV |
1158 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1159 | { | |
1160 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1161 | ||
6e3c9717 | 1162 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1163 | return NULL; |
1164 | ||
6e3c9717 | 1165 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1166 | } |
1167 | ||
040484af | 1168 | /* For ILK+ */ |
55607e8a DV |
1169 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1170 | struct intel_shared_dpll *pll, | |
1171 | bool state) | |
040484af | 1172 | { |
040484af | 1173 | bool cur_state; |
5358901f | 1174 | struct intel_dpll_hw_state hw_state; |
040484af | 1175 | |
92b27b08 | 1176 | if (WARN (!pll, |
46edb027 | 1177 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1178 | return; |
ee7b9f93 | 1179 | |
5358901f | 1180 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1181 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1182 | "%s assertion failure (expected %s, current %s)\n", |
1183 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1184 | } |
040484af JB |
1185 | |
1186 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1187 | enum pipe pipe, bool state) | |
1188 | { | |
1189 | int reg; | |
1190 | u32 val; | |
1191 | bool cur_state; | |
ad80a810 PZ |
1192 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1193 | pipe); | |
040484af | 1194 | |
affa9354 PZ |
1195 | if (HAS_DDI(dev_priv->dev)) { |
1196 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1197 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1198 | val = I915_READ(reg); |
ad80a810 | 1199 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1200 | } else { |
1201 | reg = FDI_TX_CTL(pipe); | |
1202 | val = I915_READ(reg); | |
1203 | cur_state = !!(val & FDI_TX_ENABLE); | |
1204 | } | |
e2c719b7 | 1205 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1206 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1207 | state_string(state), state_string(cur_state)); | |
1208 | } | |
1209 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1210 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1211 | ||
1212 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1213 | enum pipe pipe, bool state) | |
1214 | { | |
1215 | int reg; | |
1216 | u32 val; | |
1217 | bool cur_state; | |
1218 | ||
d63fa0dc PZ |
1219 | reg = FDI_RX_CTL(pipe); |
1220 | val = I915_READ(reg); | |
1221 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1222 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1223 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1224 | state_string(state), state_string(cur_state)); | |
1225 | } | |
1226 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1227 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1228 | ||
1229 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1230 | enum pipe pipe) | |
1231 | { | |
1232 | int reg; | |
1233 | u32 val; | |
1234 | ||
1235 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1236 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1237 | return; |
1238 | ||
bf507ef7 | 1239 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1240 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1241 | return; |
1242 | ||
040484af JB |
1243 | reg = FDI_TX_CTL(pipe); |
1244 | val = I915_READ(reg); | |
e2c719b7 | 1245 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1246 | } |
1247 | ||
55607e8a DV |
1248 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1249 | enum pipe pipe, bool state) | |
040484af JB |
1250 | { |
1251 | int reg; | |
1252 | u32 val; | |
55607e8a | 1253 | bool cur_state; |
040484af JB |
1254 | |
1255 | reg = FDI_RX_CTL(pipe); | |
1256 | val = I915_READ(reg); | |
55607e8a | 1257 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1258 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1259 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1260 | state_string(state), state_string(cur_state)); | |
040484af JB |
1261 | } |
1262 | ||
b680c37a DV |
1263 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1264 | enum pipe pipe) | |
ea0760cf | 1265 | { |
bedd4dba JN |
1266 | struct drm_device *dev = dev_priv->dev; |
1267 | int pp_reg; | |
ea0760cf JB |
1268 | u32 val; |
1269 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1270 | bool locked = true; |
ea0760cf | 1271 | |
bedd4dba JN |
1272 | if (WARN_ON(HAS_DDI(dev))) |
1273 | return; | |
1274 | ||
1275 | if (HAS_PCH_SPLIT(dev)) { | |
1276 | u32 port_sel; | |
1277 | ||
ea0760cf | 1278 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1279 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1280 | ||
1281 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1282 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1283 | panel_pipe = PIPE_B; | |
1284 | /* XXX: else fix for eDP */ | |
1285 | } else if (IS_VALLEYVIEW(dev)) { | |
1286 | /* presumably write lock depends on pipe, not port select */ | |
1287 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1288 | panel_pipe = pipe; | |
ea0760cf JB |
1289 | } else { |
1290 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1291 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1292 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1293 | } |
1294 | ||
1295 | val = I915_READ(pp_reg); | |
1296 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1297 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1298 | locked = false; |
1299 | ||
e2c719b7 | 1300 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1301 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1302 | pipe_name(pipe)); |
ea0760cf JB |
1303 | } |
1304 | ||
93ce0ba6 JN |
1305 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1306 | enum pipe pipe, bool state) | |
1307 | { | |
1308 | struct drm_device *dev = dev_priv->dev; | |
1309 | bool cur_state; | |
1310 | ||
d9d82081 | 1311 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1312 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1313 | else |
5efb3e28 | 1314 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1315 | |
e2c719b7 | 1316 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1317 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1318 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1319 | } | |
1320 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1321 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1322 | ||
b840d907 JB |
1323 | void assert_pipe(struct drm_i915_private *dev_priv, |
1324 | enum pipe pipe, bool state) | |
b24e7179 JB |
1325 | { |
1326 | int reg; | |
1327 | u32 val; | |
63d7bbe9 | 1328 | bool cur_state; |
702e7a56 PZ |
1329 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1330 | pipe); | |
b24e7179 | 1331 | |
b6b5d049 VS |
1332 | /* if we need the pipe quirk it must be always on */ |
1333 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1334 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1335 | state = true; |
1336 | ||
f458ebbc | 1337 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1338 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1339 | cur_state = false; |
1340 | } else { | |
1341 | reg = PIPECONF(cpu_transcoder); | |
1342 | val = I915_READ(reg); | |
1343 | cur_state = !!(val & PIPECONF_ENABLE); | |
1344 | } | |
1345 | ||
e2c719b7 | 1346 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1347 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1348 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1349 | } |
1350 | ||
931872fc CW |
1351 | static void assert_plane(struct drm_i915_private *dev_priv, |
1352 | enum plane plane, bool state) | |
b24e7179 JB |
1353 | { |
1354 | int reg; | |
1355 | u32 val; | |
931872fc | 1356 | bool cur_state; |
b24e7179 JB |
1357 | |
1358 | reg = DSPCNTR(plane); | |
1359 | val = I915_READ(reg); | |
931872fc | 1360 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1361 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1362 | "plane %c assertion failure (expected %s, current %s)\n", |
1363 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1364 | } |
1365 | ||
931872fc CW |
1366 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1367 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1368 | ||
b24e7179 JB |
1369 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1370 | enum pipe pipe) | |
1371 | { | |
653e1026 | 1372 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1373 | int reg, i; |
1374 | u32 val; | |
1375 | int cur_pipe; | |
1376 | ||
653e1026 VS |
1377 | /* Primary planes are fixed to pipes on gen4+ */ |
1378 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1379 | reg = DSPCNTR(pipe); |
1380 | val = I915_READ(reg); | |
e2c719b7 | 1381 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1382 | "plane %c assertion failure, should be disabled but not\n", |
1383 | plane_name(pipe)); | |
19ec1358 | 1384 | return; |
28c05794 | 1385 | } |
19ec1358 | 1386 | |
b24e7179 | 1387 | /* Need to check both planes against the pipe */ |
055e393f | 1388 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1389 | reg = DSPCNTR(i); |
1390 | val = I915_READ(reg); | |
1391 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1392 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1393 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1394 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1395 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1396 | } |
1397 | } | |
1398 | ||
19332d7a JB |
1399 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1400 | enum pipe pipe) | |
1401 | { | |
20674eef | 1402 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1403 | int reg, sprite; |
19332d7a JB |
1404 | u32 val; |
1405 | ||
7feb8b88 | 1406 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1407 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1408 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1409 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1410 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1411 | sprite, pipe_name(pipe)); | |
1412 | } | |
1413 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1414 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1415 | reg = SPCNTR(pipe, sprite); |
20674eef | 1416 | val = I915_READ(reg); |
e2c719b7 | 1417 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1418 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1419 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1420 | } |
1421 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1422 | reg = SPRCTL(pipe); | |
19332d7a | 1423 | val = I915_READ(reg); |
e2c719b7 | 1424 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1425 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1426 | plane_name(pipe), pipe_name(pipe)); |
1427 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1428 | reg = DVSCNTR(pipe); | |
19332d7a | 1429 | val = I915_READ(reg); |
e2c719b7 | 1430 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1431 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1432 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1433 | } |
1434 | } | |
1435 | ||
08c71e5e VS |
1436 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1437 | { | |
e2c719b7 | 1438 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1439 | drm_crtc_vblank_put(crtc); |
1440 | } | |
1441 | ||
89eff4be | 1442 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1443 | { |
1444 | u32 val; | |
1445 | bool enabled; | |
1446 | ||
e2c719b7 | 1447 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1448 | |
92f2584a JB |
1449 | val = I915_READ(PCH_DREF_CONTROL); |
1450 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1451 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1452 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1453 | } |
1454 | ||
ab9412ba DV |
1455 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1456 | enum pipe pipe) | |
92f2584a JB |
1457 | { |
1458 | int reg; | |
1459 | u32 val; | |
1460 | bool enabled; | |
1461 | ||
ab9412ba | 1462 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1463 | val = I915_READ(reg); |
1464 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1465 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1466 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1467 | pipe_name(pipe)); | |
92f2584a JB |
1468 | } |
1469 | ||
4e634389 KP |
1470 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1471 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1472 | { |
1473 | if ((val & DP_PORT_EN) == 0) | |
1474 | return false; | |
1475 | ||
1476 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1477 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1478 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1479 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1480 | return false; | |
44f37d1f CML |
1481 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1482 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1483 | return false; | |
f0575e92 KP |
1484 | } else { |
1485 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1486 | return false; | |
1487 | } | |
1488 | return true; | |
1489 | } | |
1490 | ||
1519b995 KP |
1491 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1492 | enum pipe pipe, u32 val) | |
1493 | { | |
dc0fa718 | 1494 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1495 | return false; |
1496 | ||
1497 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1498 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1499 | return false; |
44f37d1f CML |
1500 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1501 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1502 | return false; | |
1519b995 | 1503 | } else { |
dc0fa718 | 1504 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1505 | return false; |
1506 | } | |
1507 | return true; | |
1508 | } | |
1509 | ||
1510 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1511 | enum pipe pipe, u32 val) | |
1512 | { | |
1513 | if ((val & LVDS_PORT_EN) == 0) | |
1514 | return false; | |
1515 | ||
1516 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1517 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1518 | return false; | |
1519 | } else { | |
1520 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1521 | return false; | |
1522 | } | |
1523 | return true; | |
1524 | } | |
1525 | ||
1526 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1527 | enum pipe pipe, u32 val) | |
1528 | { | |
1529 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1530 | return false; | |
1531 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1532 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1533 | return false; | |
1534 | } else { | |
1535 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1536 | return false; | |
1537 | } | |
1538 | return true; | |
1539 | } | |
1540 | ||
291906f1 | 1541 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1542 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1543 | { |
47a05eca | 1544 | u32 val = I915_READ(reg); |
e2c719b7 | 1545 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1546 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1547 | reg, pipe_name(pipe)); |
de9a35ab | 1548 | |
e2c719b7 | 1549 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1550 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1551 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1552 | } |
1553 | ||
1554 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1555 | enum pipe pipe, int reg) | |
1556 | { | |
47a05eca | 1557 | u32 val = I915_READ(reg); |
e2c719b7 | 1558 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1559 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1560 | reg, pipe_name(pipe)); |
de9a35ab | 1561 | |
e2c719b7 | 1562 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1563 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1564 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1565 | } |
1566 | ||
1567 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1568 | enum pipe pipe) | |
1569 | { | |
1570 | int reg; | |
1571 | u32 val; | |
291906f1 | 1572 | |
f0575e92 KP |
1573 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1574 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1575 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1576 | |
1577 | reg = PCH_ADPA; | |
1578 | val = I915_READ(reg); | |
e2c719b7 | 1579 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1580 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1581 | pipe_name(pipe)); |
291906f1 JB |
1582 | |
1583 | reg = PCH_LVDS; | |
1584 | val = I915_READ(reg); | |
e2c719b7 | 1585 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1586 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1587 | pipe_name(pipe)); |
291906f1 | 1588 | |
e2debe91 PZ |
1589 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1590 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1591 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1592 | } |
1593 | ||
40e9cf64 JB |
1594 | static void intel_init_dpio(struct drm_device *dev) |
1595 | { | |
1596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1597 | ||
1598 | if (!IS_VALLEYVIEW(dev)) | |
1599 | return; | |
1600 | ||
a09caddd CML |
1601 | /* |
1602 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1603 | * CHV x1 PHY (DP/HDMI D) | |
1604 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1605 | */ | |
1606 | if (IS_CHERRYVIEW(dev)) { | |
1607 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1608 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1609 | } else { | |
1610 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1611 | } | |
5382f5f3 JB |
1612 | } |
1613 | ||
d288f65f | 1614 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1615 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1616 | { |
426115cf DV |
1617 | struct drm_device *dev = crtc->base.dev; |
1618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1619 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1620 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1621 | |
426115cf | 1622 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1623 | |
1624 | /* No really, not for ILK+ */ | |
1625 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1626 | ||
1627 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1628 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1629 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1630 | |
426115cf DV |
1631 | I915_WRITE(reg, dpll); |
1632 | POSTING_READ(reg); | |
1633 | udelay(150); | |
1634 | ||
1635 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1636 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1637 | ||
d288f65f | 1638 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1639 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1640 | |
1641 | /* We do this three times for luck */ | |
426115cf | 1642 | I915_WRITE(reg, dpll); |
87442f73 DV |
1643 | POSTING_READ(reg); |
1644 | udelay(150); /* wait for warmup */ | |
426115cf | 1645 | I915_WRITE(reg, dpll); |
87442f73 DV |
1646 | POSTING_READ(reg); |
1647 | udelay(150); /* wait for warmup */ | |
426115cf | 1648 | I915_WRITE(reg, dpll); |
87442f73 DV |
1649 | POSTING_READ(reg); |
1650 | udelay(150); /* wait for warmup */ | |
1651 | } | |
1652 | ||
d288f65f | 1653 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1654 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1655 | { |
1656 | struct drm_device *dev = crtc->base.dev; | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1658 | int pipe = crtc->pipe; | |
1659 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1660 | u32 tmp; |
1661 | ||
1662 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1663 | ||
1664 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1665 | ||
a580516d | 1666 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1667 | |
1668 | /* Enable back the 10bit clock to display controller */ | |
1669 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1670 | tmp |= DPIO_DCLKP_EN; | |
1671 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1672 | ||
54433e91 VS |
1673 | mutex_unlock(&dev_priv->sb_lock); |
1674 | ||
9d556c99 CML |
1675 | /* |
1676 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1677 | */ | |
1678 | udelay(1); | |
1679 | ||
1680 | /* Enable PLL */ | |
d288f65f | 1681 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1682 | |
1683 | /* Check PLL is locked */ | |
a11b0703 | 1684 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1685 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1686 | ||
a11b0703 | 1687 | /* not sure when this should be written */ |
d288f65f | 1688 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1689 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1690 | } |
1691 | ||
1c4e0274 VS |
1692 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1693 | { | |
1694 | struct intel_crtc *crtc; | |
1695 | int count = 0; | |
1696 | ||
1697 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1698 | count += crtc->base.state->active && |
409ee761 | 1699 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1700 | |
1701 | return count; | |
1702 | } | |
1703 | ||
66e3d5c0 | 1704 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1705 | { |
66e3d5c0 DV |
1706 | struct drm_device *dev = crtc->base.dev; |
1707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1708 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1709 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1710 | |
66e3d5c0 | 1711 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1712 | |
63d7bbe9 | 1713 | /* No really, not for ILK+ */ |
3d13ef2e | 1714 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1715 | |
1716 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1717 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1718 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1719 | |
1c4e0274 VS |
1720 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1721 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1722 | /* | |
1723 | * It appears to be important that we don't enable this | |
1724 | * for the current pipe before otherwise configuring the | |
1725 | * PLL. No idea how this should be handled if multiple | |
1726 | * DVO outputs are enabled simultaneosly. | |
1727 | */ | |
1728 | dpll |= DPLL_DVO_2X_MODE; | |
1729 | I915_WRITE(DPLL(!crtc->pipe), | |
1730 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1731 | } | |
66e3d5c0 DV |
1732 | |
1733 | /* Wait for the clocks to stabilize. */ | |
1734 | POSTING_READ(reg); | |
1735 | udelay(150); | |
1736 | ||
1737 | if (INTEL_INFO(dev)->gen >= 4) { | |
1738 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1739 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1740 | } else { |
1741 | /* The pixel multiplier can only be updated once the | |
1742 | * DPLL is enabled and the clocks are stable. | |
1743 | * | |
1744 | * So write it again. | |
1745 | */ | |
1746 | I915_WRITE(reg, dpll); | |
1747 | } | |
63d7bbe9 JB |
1748 | |
1749 | /* We do this three times for luck */ | |
66e3d5c0 | 1750 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1751 | POSTING_READ(reg); |
1752 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1753 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1754 | POSTING_READ(reg); |
1755 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1756 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1757 | POSTING_READ(reg); |
1758 | udelay(150); /* wait for warmup */ | |
1759 | } | |
1760 | ||
1761 | /** | |
50b44a44 | 1762 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1763 | * @dev_priv: i915 private structure |
1764 | * @pipe: pipe PLL to disable | |
1765 | * | |
1766 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1767 | * | |
1768 | * Note! This is for pre-ILK only. | |
1769 | */ | |
1c4e0274 | 1770 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1771 | { |
1c4e0274 VS |
1772 | struct drm_device *dev = crtc->base.dev; |
1773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1774 | enum pipe pipe = crtc->pipe; | |
1775 | ||
1776 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1777 | if (IS_I830(dev) && | |
409ee761 | 1778 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1779 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1780 | I915_WRITE(DPLL(PIPE_B), |
1781 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1782 | I915_WRITE(DPLL(PIPE_A), | |
1783 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1784 | } | |
1785 | ||
b6b5d049 VS |
1786 | /* Don't disable pipe or pipe PLLs if needed */ |
1787 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1788 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1789 | return; |
1790 | ||
1791 | /* Make sure the pipe isn't still relying on us */ | |
1792 | assert_pipe_disabled(dev_priv, pipe); | |
1793 | ||
b8afb911 | 1794 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1795 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1796 | } |
1797 | ||
f6071166 JB |
1798 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1799 | { | |
b8afb911 | 1800 | u32 val; |
f6071166 JB |
1801 | |
1802 | /* Make sure the pipe isn't still relying on us */ | |
1803 | assert_pipe_disabled(dev_priv, pipe); | |
1804 | ||
e5cbfbfb ID |
1805 | /* |
1806 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1807 | * The latter is needed for VGA hotplug / manual detection. | |
1808 | */ | |
b8afb911 | 1809 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1810 | if (pipe == PIPE_B) |
60bfe44f | 1811 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1812 | I915_WRITE(DPLL(pipe), val); |
1813 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1814 | |
1815 | } | |
1816 | ||
1817 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1818 | { | |
d752048d | 1819 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1820 | u32 val; |
1821 | ||
a11b0703 VS |
1822 | /* Make sure the pipe isn't still relying on us */ |
1823 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1824 | |
a11b0703 | 1825 | /* Set PLL en = 0 */ |
60bfe44f VS |
1826 | val = DPLL_SSC_REF_CLK_CHV | |
1827 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1828 | if (pipe != PIPE_A) |
1829 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1830 | I915_WRITE(DPLL(pipe), val); | |
1831 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1832 | |
a580516d | 1833 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1834 | |
1835 | /* Disable 10bit clock to display controller */ | |
1836 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1837 | val &= ~DPIO_DCLKP_EN; | |
1838 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1839 | ||
61407f6d VS |
1840 | /* disable left/right clock distribution */ |
1841 | if (pipe != PIPE_B) { | |
1842 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1843 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1844 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1845 | } else { | |
1846 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1847 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1848 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1849 | } | |
1850 | ||
a580516d | 1851 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1852 | } |
1853 | ||
e4607fcf | 1854 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1855 | struct intel_digital_port *dport, |
1856 | unsigned int expected_mask) | |
89b667f8 JB |
1857 | { |
1858 | u32 port_mask; | |
00fc31b7 | 1859 | int dpll_reg; |
89b667f8 | 1860 | |
e4607fcf CML |
1861 | switch (dport->port) { |
1862 | case PORT_B: | |
89b667f8 | 1863 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1864 | dpll_reg = DPLL(0); |
e4607fcf CML |
1865 | break; |
1866 | case PORT_C: | |
89b667f8 | 1867 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1868 | dpll_reg = DPLL(0); |
9b6de0a1 | 1869 | expected_mask <<= 4; |
00fc31b7 CML |
1870 | break; |
1871 | case PORT_D: | |
1872 | port_mask = DPLL_PORTD_READY_MASK; | |
1873 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1874 | break; |
1875 | default: | |
1876 | BUG(); | |
1877 | } | |
89b667f8 | 1878 | |
9b6de0a1 VS |
1879 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1880 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1881 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1882 | } |
1883 | ||
b14b1055 DV |
1884 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1885 | { | |
1886 | struct drm_device *dev = crtc->base.dev; | |
1887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1888 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1889 | ||
be19f0ff CW |
1890 | if (WARN_ON(pll == NULL)) |
1891 | return; | |
1892 | ||
3e369b76 | 1893 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1894 | if (pll->active == 0) { |
1895 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1896 | WARN_ON(pll->on); | |
1897 | assert_shared_dpll_disabled(dev_priv, pll); | |
1898 | ||
1899 | pll->mode_set(dev_priv, pll); | |
1900 | } | |
1901 | } | |
1902 | ||
92f2584a | 1903 | /** |
85b3894f | 1904 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1905 | * @dev_priv: i915 private structure |
1906 | * @pipe: pipe PLL to enable | |
1907 | * | |
1908 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1909 | * drives the transcoder clock. | |
1910 | */ | |
85b3894f | 1911 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1912 | { |
3d13ef2e DL |
1913 | struct drm_device *dev = crtc->base.dev; |
1914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1915 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1916 | |
87a875bb | 1917 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1918 | return; |
1919 | ||
3e369b76 | 1920 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1921 | return; |
ee7b9f93 | 1922 | |
74dd6928 | 1923 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1924 | pll->name, pll->active, pll->on, |
e2b78267 | 1925 | crtc->base.base.id); |
92f2584a | 1926 | |
cdbd2316 DV |
1927 | if (pll->active++) { |
1928 | WARN_ON(!pll->on); | |
e9d6944e | 1929 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1930 | return; |
1931 | } | |
f4a091c7 | 1932 | WARN_ON(pll->on); |
ee7b9f93 | 1933 | |
bd2bb1b9 PZ |
1934 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1935 | ||
46edb027 | 1936 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1937 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1938 | pll->on = true; |
92f2584a JB |
1939 | } |
1940 | ||
f6daaec2 | 1941 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1942 | { |
3d13ef2e DL |
1943 | struct drm_device *dev = crtc->base.dev; |
1944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1945 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1946 | |
92f2584a | 1947 | /* PCH only available on ILK+ */ |
3d13ef2e | 1948 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
eddfcbcd ML |
1949 | if (pll == NULL) |
1950 | return; | |
92f2584a | 1951 | |
eddfcbcd | 1952 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1953 | return; |
7a419866 | 1954 | |
46edb027 DV |
1955 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1956 | pll->name, pll->active, pll->on, | |
e2b78267 | 1957 | crtc->base.base.id); |
7a419866 | 1958 | |
48da64a8 | 1959 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1960 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1961 | return; |
1962 | } | |
1963 | ||
e9d6944e | 1964 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1965 | WARN_ON(!pll->on); |
cdbd2316 | 1966 | if (--pll->active) |
7a419866 | 1967 | return; |
ee7b9f93 | 1968 | |
46edb027 | 1969 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1970 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1971 | pll->on = false; |
bd2bb1b9 PZ |
1972 | |
1973 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1974 | } |
1975 | ||
b8a4f404 PZ |
1976 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1977 | enum pipe pipe) | |
040484af | 1978 | { |
23670b32 | 1979 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1980 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1981 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1982 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1983 | |
1984 | /* PCH only available on ILK+ */ | |
55522f37 | 1985 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1986 | |
1987 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1988 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1989 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1990 | |
1991 | /* FDI must be feeding us bits for PCH ports */ | |
1992 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1993 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1994 | ||
23670b32 DV |
1995 | if (HAS_PCH_CPT(dev)) { |
1996 | /* Workaround: Set the timing override bit before enabling the | |
1997 | * pch transcoder. */ | |
1998 | reg = TRANS_CHICKEN2(pipe); | |
1999 | val = I915_READ(reg); | |
2000 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2001 | I915_WRITE(reg, val); | |
59c859d6 | 2002 | } |
23670b32 | 2003 | |
ab9412ba | 2004 | reg = PCH_TRANSCONF(pipe); |
040484af | 2005 | val = I915_READ(reg); |
5f7f726d | 2006 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
2007 | |
2008 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2009 | /* | |
c5de7c6f VS |
2010 | * Make the BPC in transcoder be consistent with |
2011 | * that in pipeconf reg. For HDMI we must use 8bpc | |
2012 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 2013 | */ |
dfd07d72 | 2014 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
2015 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
2016 | val |= PIPECONF_8BPC; | |
2017 | else | |
2018 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2019 | } |
5f7f726d PZ |
2020 | |
2021 | val &= ~TRANS_INTERLACE_MASK; | |
2022 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2023 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2024 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2025 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2026 | else | |
2027 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2028 | else |
2029 | val |= TRANS_PROGRESSIVE; | |
2030 | ||
040484af JB |
2031 | I915_WRITE(reg, val | TRANS_ENABLE); |
2032 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2033 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2034 | } |
2035 | ||
8fb033d7 | 2036 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2037 | enum transcoder cpu_transcoder) |
040484af | 2038 | { |
8fb033d7 | 2039 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2040 | |
2041 | /* PCH only available on ILK+ */ | |
55522f37 | 2042 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2043 | |
8fb033d7 | 2044 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2045 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2046 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2047 | |
223a6fdf PZ |
2048 | /* Workaround: set timing override bit. */ |
2049 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2050 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2051 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2052 | ||
25f3ef11 | 2053 | val = TRANS_ENABLE; |
937bb610 | 2054 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2055 | |
9a76b1c6 PZ |
2056 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2057 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2058 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2059 | else |
2060 | val |= TRANS_PROGRESSIVE; | |
2061 | ||
ab9412ba DV |
2062 | I915_WRITE(LPT_TRANSCONF, val); |
2063 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2064 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2065 | } |
2066 | ||
b8a4f404 PZ |
2067 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2068 | enum pipe pipe) | |
040484af | 2069 | { |
23670b32 DV |
2070 | struct drm_device *dev = dev_priv->dev; |
2071 | uint32_t reg, val; | |
040484af JB |
2072 | |
2073 | /* FDI relies on the transcoder */ | |
2074 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2075 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2076 | ||
291906f1 JB |
2077 | /* Ports must be off as well */ |
2078 | assert_pch_ports_disabled(dev_priv, pipe); | |
2079 | ||
ab9412ba | 2080 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2081 | val = I915_READ(reg); |
2082 | val &= ~TRANS_ENABLE; | |
2083 | I915_WRITE(reg, val); | |
2084 | /* wait for PCH transcoder off, transcoder state */ | |
2085 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2086 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2087 | |
2088 | if (!HAS_PCH_IBX(dev)) { | |
2089 | /* Workaround: Clear the timing override chicken bit again. */ | |
2090 | reg = TRANS_CHICKEN2(pipe); | |
2091 | val = I915_READ(reg); | |
2092 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2093 | I915_WRITE(reg, val); | |
2094 | } | |
040484af JB |
2095 | } |
2096 | ||
ab4d966c | 2097 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2098 | { |
8fb033d7 PZ |
2099 | u32 val; |
2100 | ||
ab9412ba | 2101 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2102 | val &= ~TRANS_ENABLE; |
ab9412ba | 2103 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2104 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2105 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2106 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2107 | |
2108 | /* Workaround: clear timing override bit. */ | |
2109 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2110 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2111 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2112 | } |
2113 | ||
b24e7179 | 2114 | /** |
309cfea8 | 2115 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2116 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2117 | * |
0372264a | 2118 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2119 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2120 | */ |
e1fdc473 | 2121 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2122 | { |
0372264a PZ |
2123 | struct drm_device *dev = crtc->base.dev; |
2124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2125 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2126 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2127 | pipe); | |
1a240d4d | 2128 | enum pipe pch_transcoder; |
b24e7179 JB |
2129 | int reg; |
2130 | u32 val; | |
2131 | ||
9e2ee2dd VS |
2132 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2133 | ||
58c6eaa2 | 2134 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2135 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2136 | assert_sprites_disabled(dev_priv, pipe); |
2137 | ||
681e5811 | 2138 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2139 | pch_transcoder = TRANSCODER_A; |
2140 | else | |
2141 | pch_transcoder = pipe; | |
2142 | ||
b24e7179 JB |
2143 | /* |
2144 | * A pipe without a PLL won't actually be able to drive bits from | |
2145 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2146 | * need the check. | |
2147 | */ | |
50360403 | 2148 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2149 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2150 | assert_dsi_pll_enabled(dev_priv); |
2151 | else | |
2152 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2153 | else { |
6e3c9717 | 2154 | if (crtc->config->has_pch_encoder) { |
040484af | 2155 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2156 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2157 | assert_fdi_tx_pll_enabled(dev_priv, |
2158 | (enum pipe) cpu_transcoder); | |
040484af JB |
2159 | } |
2160 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2161 | } | |
b24e7179 | 2162 | |
702e7a56 | 2163 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2164 | val = I915_READ(reg); |
7ad25d48 | 2165 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2166 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2167 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2168 | return; |
7ad25d48 | 2169 | } |
00d70b15 CW |
2170 | |
2171 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2172 | POSTING_READ(reg); |
b24e7179 JB |
2173 | } |
2174 | ||
2175 | /** | |
309cfea8 | 2176 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2177 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2178 | * |
575f7ab7 VS |
2179 | * Disable the pipe of @crtc, making sure that various hardware |
2180 | * specific requirements are met, if applicable, e.g. plane | |
2181 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2182 | * |
2183 | * Will wait until the pipe has shut down before returning. | |
2184 | */ | |
575f7ab7 | 2185 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2186 | { |
575f7ab7 | 2187 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2188 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2189 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2190 | int reg; |
2191 | u32 val; | |
2192 | ||
9e2ee2dd VS |
2193 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2194 | ||
b24e7179 JB |
2195 | /* |
2196 | * Make sure planes won't keep trying to pump pixels to us, | |
2197 | * or we might hang the display. | |
2198 | */ | |
2199 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2200 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2201 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2202 | |
702e7a56 | 2203 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2204 | val = I915_READ(reg); |
00d70b15 CW |
2205 | if ((val & PIPECONF_ENABLE) == 0) |
2206 | return; | |
2207 | ||
67adc644 VS |
2208 | /* |
2209 | * Double wide has implications for planes | |
2210 | * so best keep it disabled when not needed. | |
2211 | */ | |
6e3c9717 | 2212 | if (crtc->config->double_wide) |
67adc644 VS |
2213 | val &= ~PIPECONF_DOUBLE_WIDE; |
2214 | ||
2215 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2216 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2217 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2218 | val &= ~PIPECONF_ENABLE; |
2219 | ||
2220 | I915_WRITE(reg, val); | |
2221 | if ((val & PIPECONF_ENABLE) == 0) | |
2222 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2223 | } |
2224 | ||
693db184 CW |
2225 | static bool need_vtd_wa(struct drm_device *dev) |
2226 | { | |
2227 | #ifdef CONFIG_INTEL_IOMMU | |
2228 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2229 | return true; | |
2230 | #endif | |
2231 | return false; | |
2232 | } | |
2233 | ||
50470bb0 | 2234 | unsigned int |
6761dd31 TU |
2235 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2236 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2237 | { |
6761dd31 TU |
2238 | unsigned int tile_height; |
2239 | uint32_t pixel_bytes; | |
a57ce0b2 | 2240 | |
b5d0e9bf DL |
2241 | switch (fb_format_modifier) { |
2242 | case DRM_FORMAT_MOD_NONE: | |
2243 | tile_height = 1; | |
2244 | break; | |
2245 | case I915_FORMAT_MOD_X_TILED: | |
2246 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2247 | break; | |
2248 | case I915_FORMAT_MOD_Y_TILED: | |
2249 | tile_height = 32; | |
2250 | break; | |
2251 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2252 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2253 | switch (pixel_bytes) { | |
b5d0e9bf | 2254 | default: |
6761dd31 | 2255 | case 1: |
b5d0e9bf DL |
2256 | tile_height = 64; |
2257 | break; | |
6761dd31 TU |
2258 | case 2: |
2259 | case 4: | |
b5d0e9bf DL |
2260 | tile_height = 32; |
2261 | break; | |
6761dd31 | 2262 | case 8: |
b5d0e9bf DL |
2263 | tile_height = 16; |
2264 | break; | |
6761dd31 | 2265 | case 16: |
b5d0e9bf DL |
2266 | WARN_ONCE(1, |
2267 | "128-bit pixels are not supported for display!"); | |
2268 | tile_height = 16; | |
2269 | break; | |
2270 | } | |
2271 | break; | |
2272 | default: | |
2273 | MISSING_CASE(fb_format_modifier); | |
2274 | tile_height = 1; | |
2275 | break; | |
2276 | } | |
091df6cb | 2277 | |
6761dd31 TU |
2278 | return tile_height; |
2279 | } | |
2280 | ||
2281 | unsigned int | |
2282 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2283 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2284 | { | |
2285 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2286 | fb_format_modifier)); | |
a57ce0b2 JB |
2287 | } |
2288 | ||
f64b98cd TU |
2289 | static int |
2290 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2291 | const struct drm_plane_state *plane_state) | |
2292 | { | |
50470bb0 | 2293 | struct intel_rotation_info *info = &view->rotation_info; |
84fe03f7 | 2294 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2295 | |
f64b98cd TU |
2296 | *view = i915_ggtt_view_normal; |
2297 | ||
50470bb0 TU |
2298 | if (!plane_state) |
2299 | return 0; | |
2300 | ||
121920fa | 2301 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2302 | return 0; |
2303 | ||
9abc4648 | 2304 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2305 | |
2306 | info->height = fb->height; | |
2307 | info->pixel_format = fb->pixel_format; | |
2308 | info->pitch = fb->pitches[0]; | |
2309 | info->fb_modifier = fb->modifier[0]; | |
2310 | ||
84fe03f7 TU |
2311 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
2312 | fb->modifier[0]); | |
2313 | tile_pitch = PAGE_SIZE / tile_height; | |
2314 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2315 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2316 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2317 | ||
f64b98cd TU |
2318 | return 0; |
2319 | } | |
2320 | ||
4e9a86b6 VS |
2321 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2322 | { | |
2323 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2324 | return 256 * 1024; | |
985b8bb4 VS |
2325 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
2326 | IS_VALLEYVIEW(dev_priv)) | |
4e9a86b6 VS |
2327 | return 128 * 1024; |
2328 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2329 | return 4 * 1024; | |
2330 | else | |
44c5905e | 2331 | return 0; |
4e9a86b6 VS |
2332 | } |
2333 | ||
127bd2ac | 2334 | int |
850c4cdc TU |
2335 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2336 | struct drm_framebuffer *fb, | |
82bc3b2d | 2337 | const struct drm_plane_state *plane_state, |
91af127f JH |
2338 | struct intel_engine_cs *pipelined, |
2339 | struct drm_i915_gem_request **pipelined_request) | |
6b95a207 | 2340 | { |
850c4cdc | 2341 | struct drm_device *dev = fb->dev; |
ce453d81 | 2342 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2343 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2344 | struct i915_ggtt_view view; |
6b95a207 KH |
2345 | u32 alignment; |
2346 | int ret; | |
2347 | ||
ebcdd39e MR |
2348 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2349 | ||
7b911adc TU |
2350 | switch (fb->modifier[0]) { |
2351 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2352 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2353 | break; |
7b911adc | 2354 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2355 | if (INTEL_INFO(dev)->gen >= 9) |
2356 | alignment = 256 * 1024; | |
2357 | else { | |
2358 | /* pin() will align the object as required by fence */ | |
2359 | alignment = 0; | |
2360 | } | |
6b95a207 | 2361 | break; |
7b911adc | 2362 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2363 | case I915_FORMAT_MOD_Yf_TILED: |
2364 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2365 | "Y tiling bo slipped through, driver bug!\n")) | |
2366 | return -EINVAL; | |
2367 | alignment = 1 * 1024 * 1024; | |
2368 | break; | |
6b95a207 | 2369 | default: |
7b911adc TU |
2370 | MISSING_CASE(fb->modifier[0]); |
2371 | return -EINVAL; | |
6b95a207 KH |
2372 | } |
2373 | ||
f64b98cd TU |
2374 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2375 | if (ret) | |
2376 | return ret; | |
2377 | ||
693db184 CW |
2378 | /* Note that the w/a also requires 64 PTE of padding following the |
2379 | * bo. We currently fill all unused PTE with the shadow page and so | |
2380 | * we should always have valid PTE following the scanout preventing | |
2381 | * the VT-d warning. | |
2382 | */ | |
2383 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2384 | alignment = 256 * 1024; | |
2385 | ||
d6dd6843 PZ |
2386 | /* |
2387 | * Global gtt pte registers are special registers which actually forward | |
2388 | * writes to a chunk of system memory. Which means that there is no risk | |
2389 | * that the register values disappear as soon as we call | |
2390 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2391 | * pin/unpin/fence and not more. | |
2392 | */ | |
2393 | intel_runtime_pm_get(dev_priv); | |
2394 | ||
ce453d81 | 2395 | dev_priv->mm.interruptible = false; |
e6617330 | 2396 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
91af127f | 2397 | pipelined_request, &view); |
48b956c5 | 2398 | if (ret) |
ce453d81 | 2399 | goto err_interruptible; |
6b95a207 KH |
2400 | |
2401 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2402 | * fence, whereas 965+ only requires a fence if using | |
2403 | * framebuffer compression. For simplicity, we always install | |
2404 | * a fence as the cost is not that onerous. | |
2405 | */ | |
06d98131 | 2406 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2407 | if (ret) |
2408 | goto err_unpin; | |
1690e1eb | 2409 | |
9a5a53b3 | 2410 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2411 | |
ce453d81 | 2412 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2413 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2414 | return 0; |
48b956c5 CW |
2415 | |
2416 | err_unpin: | |
f64b98cd | 2417 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2418 | err_interruptible: |
2419 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2420 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2421 | return ret; |
6b95a207 KH |
2422 | } |
2423 | ||
82bc3b2d TU |
2424 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2425 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2426 | { |
82bc3b2d | 2427 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2428 | struct i915_ggtt_view view; |
2429 | int ret; | |
82bc3b2d | 2430 | |
ebcdd39e MR |
2431 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2432 | ||
f64b98cd TU |
2433 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2434 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2435 | ||
1690e1eb | 2436 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2437 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2438 | } |
2439 | ||
c2c75131 DV |
2440 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2441 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2442 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2443 | int *x, int *y, | |
bc752862 CW |
2444 | unsigned int tiling_mode, |
2445 | unsigned int cpp, | |
2446 | unsigned int pitch) | |
c2c75131 | 2447 | { |
bc752862 CW |
2448 | if (tiling_mode != I915_TILING_NONE) { |
2449 | unsigned int tile_rows, tiles; | |
c2c75131 | 2450 | |
bc752862 CW |
2451 | tile_rows = *y / 8; |
2452 | *y %= 8; | |
c2c75131 | 2453 | |
bc752862 CW |
2454 | tiles = *x / (512/cpp); |
2455 | *x %= 512/cpp; | |
2456 | ||
2457 | return tile_rows * pitch * 8 + tiles * 4096; | |
2458 | } else { | |
4e9a86b6 | 2459 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2460 | unsigned int offset; |
2461 | ||
2462 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2463 | *y = (offset & alignment) / pitch; |
2464 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2465 | return offset & ~alignment; | |
bc752862 | 2466 | } |
c2c75131 DV |
2467 | } |
2468 | ||
b35d63fa | 2469 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2470 | { |
2471 | switch (format) { | |
2472 | case DISPPLANE_8BPP: | |
2473 | return DRM_FORMAT_C8; | |
2474 | case DISPPLANE_BGRX555: | |
2475 | return DRM_FORMAT_XRGB1555; | |
2476 | case DISPPLANE_BGRX565: | |
2477 | return DRM_FORMAT_RGB565; | |
2478 | default: | |
2479 | case DISPPLANE_BGRX888: | |
2480 | return DRM_FORMAT_XRGB8888; | |
2481 | case DISPPLANE_RGBX888: | |
2482 | return DRM_FORMAT_XBGR8888; | |
2483 | case DISPPLANE_BGRX101010: | |
2484 | return DRM_FORMAT_XRGB2101010; | |
2485 | case DISPPLANE_RGBX101010: | |
2486 | return DRM_FORMAT_XBGR2101010; | |
2487 | } | |
2488 | } | |
2489 | ||
bc8d7dff DL |
2490 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2491 | { | |
2492 | switch (format) { | |
2493 | case PLANE_CTL_FORMAT_RGB_565: | |
2494 | return DRM_FORMAT_RGB565; | |
2495 | default: | |
2496 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2497 | if (rgb_order) { | |
2498 | if (alpha) | |
2499 | return DRM_FORMAT_ABGR8888; | |
2500 | else | |
2501 | return DRM_FORMAT_XBGR8888; | |
2502 | } else { | |
2503 | if (alpha) | |
2504 | return DRM_FORMAT_ARGB8888; | |
2505 | else | |
2506 | return DRM_FORMAT_XRGB8888; | |
2507 | } | |
2508 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2509 | if (rgb_order) | |
2510 | return DRM_FORMAT_XBGR2101010; | |
2511 | else | |
2512 | return DRM_FORMAT_XRGB2101010; | |
2513 | } | |
2514 | } | |
2515 | ||
5724dbd1 | 2516 | static bool |
f6936e29 DV |
2517 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2518 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2519 | { |
2520 | struct drm_device *dev = crtc->base.dev; | |
2521 | struct drm_i915_gem_object *obj = NULL; | |
2522 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2523 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2524 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2525 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2526 | PAGE_SIZE); | |
2527 | ||
2528 | size_aligned -= base_aligned; | |
46f297fb | 2529 | |
ff2652ea CW |
2530 | if (plane_config->size == 0) |
2531 | return false; | |
2532 | ||
f37b5c2b DV |
2533 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2534 | base_aligned, | |
2535 | base_aligned, | |
2536 | size_aligned); | |
46f297fb | 2537 | if (!obj) |
484b41dd | 2538 | return false; |
46f297fb | 2539 | |
49af449b DL |
2540 | obj->tiling_mode = plane_config->tiling; |
2541 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2542 | obj->stride = fb->pitches[0]; |
46f297fb | 2543 | |
6bf129df DL |
2544 | mode_cmd.pixel_format = fb->pixel_format; |
2545 | mode_cmd.width = fb->width; | |
2546 | mode_cmd.height = fb->height; | |
2547 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2548 | mode_cmd.modifier[0] = fb->modifier[0]; |
2549 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2550 | |
2551 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2552 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2553 | &mode_cmd, obj)) { |
46f297fb JB |
2554 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2555 | goto out_unref_obj; | |
2556 | } | |
46f297fb | 2557 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2558 | |
f6936e29 | 2559 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2560 | return true; |
46f297fb JB |
2561 | |
2562 | out_unref_obj: | |
2563 | drm_gem_object_unreference(&obj->base); | |
2564 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2565 | return false; |
2566 | } | |
2567 | ||
afd65eb4 MR |
2568 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2569 | static void | |
2570 | update_state_fb(struct drm_plane *plane) | |
2571 | { | |
2572 | if (plane->fb == plane->state->fb) | |
2573 | return; | |
2574 | ||
2575 | if (plane->state->fb) | |
2576 | drm_framebuffer_unreference(plane->state->fb); | |
2577 | plane->state->fb = plane->fb; | |
2578 | if (plane->state->fb) | |
2579 | drm_framebuffer_reference(plane->state->fb); | |
2580 | } | |
2581 | ||
5724dbd1 | 2582 | static void |
f6936e29 DV |
2583 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2584 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2585 | { |
2586 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2588 | struct drm_crtc *c; |
2589 | struct intel_crtc *i; | |
2ff8fde1 | 2590 | struct drm_i915_gem_object *obj; |
88595ac9 | 2591 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2592 | struct drm_plane_state *plane_state = primary->state; |
88595ac9 | 2593 | struct drm_framebuffer *fb; |
484b41dd | 2594 | |
2d14030b | 2595 | if (!plane_config->fb) |
484b41dd JB |
2596 | return; |
2597 | ||
f6936e29 | 2598 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2599 | fb = &plane_config->fb->base; |
2600 | goto valid_fb; | |
f55548b5 | 2601 | } |
484b41dd | 2602 | |
2d14030b | 2603 | kfree(plane_config->fb); |
484b41dd JB |
2604 | |
2605 | /* | |
2606 | * Failed to alloc the obj, check to see if we should share | |
2607 | * an fb with another CRTC instead | |
2608 | */ | |
70e1e0ec | 2609 | for_each_crtc(dev, c) { |
484b41dd JB |
2610 | i = to_intel_crtc(c); |
2611 | ||
2612 | if (c == &intel_crtc->base) | |
2613 | continue; | |
2614 | ||
2ff8fde1 MR |
2615 | if (!i->active) |
2616 | continue; | |
2617 | ||
88595ac9 DV |
2618 | fb = c->primary->fb; |
2619 | if (!fb) | |
484b41dd JB |
2620 | continue; |
2621 | ||
88595ac9 | 2622 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2623 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2624 | drm_framebuffer_reference(fb); |
2625 | goto valid_fb; | |
484b41dd JB |
2626 | } |
2627 | } | |
88595ac9 DV |
2628 | |
2629 | return; | |
2630 | ||
2631 | valid_fb: | |
be5651f2 ML |
2632 | plane_state->src_x = plane_state->src_y = 0; |
2633 | plane_state->src_w = fb->width << 16; | |
2634 | plane_state->src_h = fb->height << 16; | |
2635 | ||
2636 | plane_state->crtc_x = plane_state->src_y = 0; | |
2637 | plane_state->crtc_w = fb->width; | |
2638 | plane_state->crtc_h = fb->height; | |
2639 | ||
88595ac9 DV |
2640 | obj = intel_fb_obj(fb); |
2641 | if (obj->tiling_mode != I915_TILING_NONE) | |
2642 | dev_priv->preserve_bios_swizzle = true; | |
2643 | ||
be5651f2 ML |
2644 | drm_framebuffer_reference(fb); |
2645 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2646 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2647 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2648 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2649 | } |
2650 | ||
29b9bde6 DV |
2651 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2652 | struct drm_framebuffer *fb, | |
2653 | int x, int y) | |
81255565 JB |
2654 | { |
2655 | struct drm_device *dev = crtc->dev; | |
2656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2657 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2658 | struct drm_plane *primary = crtc->primary; |
2659 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2660 | struct drm_i915_gem_object *obj; |
81255565 | 2661 | int plane = intel_crtc->plane; |
e506a0c6 | 2662 | unsigned long linear_offset; |
81255565 | 2663 | u32 dspcntr; |
f45651ba | 2664 | u32 reg = DSPCNTR(plane); |
48404c1e | 2665 | int pixel_size; |
f45651ba | 2666 | |
b70709a6 | 2667 | if (!visible || !fb) { |
fdd508a6 VS |
2668 | I915_WRITE(reg, 0); |
2669 | if (INTEL_INFO(dev)->gen >= 4) | |
2670 | I915_WRITE(DSPSURF(plane), 0); | |
2671 | else | |
2672 | I915_WRITE(DSPADDR(plane), 0); | |
2673 | POSTING_READ(reg); | |
2674 | return; | |
2675 | } | |
2676 | ||
c9ba6fad VS |
2677 | obj = intel_fb_obj(fb); |
2678 | if (WARN_ON(obj == NULL)) | |
2679 | return; | |
2680 | ||
2681 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2682 | ||
f45651ba VS |
2683 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2684 | ||
fdd508a6 | 2685 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2686 | |
2687 | if (INTEL_INFO(dev)->gen < 4) { | |
2688 | if (intel_crtc->pipe == PIPE_B) | |
2689 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2690 | ||
2691 | /* pipesrc and dspsize control the size that is scaled from, | |
2692 | * which should always be the user's requested size. | |
2693 | */ | |
2694 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2695 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2696 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2697 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2698 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2699 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2700 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2701 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2702 | I915_WRITE(PRIMPOS(plane), 0); |
2703 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2704 | } |
81255565 | 2705 | |
57779d06 VS |
2706 | switch (fb->pixel_format) { |
2707 | case DRM_FORMAT_C8: | |
81255565 JB |
2708 | dspcntr |= DISPPLANE_8BPP; |
2709 | break; | |
57779d06 | 2710 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2711 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2712 | break; |
57779d06 VS |
2713 | case DRM_FORMAT_RGB565: |
2714 | dspcntr |= DISPPLANE_BGRX565; | |
2715 | break; | |
2716 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2717 | dspcntr |= DISPPLANE_BGRX888; |
2718 | break; | |
2719 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2720 | dspcntr |= DISPPLANE_RGBX888; |
2721 | break; | |
2722 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2723 | dspcntr |= DISPPLANE_BGRX101010; |
2724 | break; | |
2725 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2726 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2727 | break; |
2728 | default: | |
baba133a | 2729 | BUG(); |
81255565 | 2730 | } |
57779d06 | 2731 | |
f45651ba VS |
2732 | if (INTEL_INFO(dev)->gen >= 4 && |
2733 | obj->tiling_mode != I915_TILING_NONE) | |
2734 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2735 | |
de1aa629 VS |
2736 | if (IS_G4X(dev)) |
2737 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2738 | ||
b9897127 | 2739 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2740 | |
c2c75131 DV |
2741 | if (INTEL_INFO(dev)->gen >= 4) { |
2742 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2743 | intel_gen4_compute_page_offset(dev_priv, |
2744 | &x, &y, obj->tiling_mode, | |
b9897127 | 2745 | pixel_size, |
bc752862 | 2746 | fb->pitches[0]); |
c2c75131 DV |
2747 | linear_offset -= intel_crtc->dspaddr_offset; |
2748 | } else { | |
e506a0c6 | 2749 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2750 | } |
e506a0c6 | 2751 | |
8e7d688b | 2752 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2753 | dspcntr |= DISPPLANE_ROTATE_180; |
2754 | ||
6e3c9717 ACO |
2755 | x += (intel_crtc->config->pipe_src_w - 1); |
2756 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2757 | |
2758 | /* Finding the last pixel of the last line of the display | |
2759 | data and adding to linear_offset*/ | |
2760 | linear_offset += | |
6e3c9717 ACO |
2761 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2762 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2763 | } |
2764 | ||
2765 | I915_WRITE(reg, dspcntr); | |
2766 | ||
01f2c773 | 2767 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2768 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2769 | I915_WRITE(DSPSURF(plane), |
2770 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2771 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2772 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2773 | } else |
f343c5f6 | 2774 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2775 | POSTING_READ(reg); |
17638cd6 JB |
2776 | } |
2777 | ||
29b9bde6 DV |
2778 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2779 | struct drm_framebuffer *fb, | |
2780 | int x, int y) | |
17638cd6 JB |
2781 | { |
2782 | struct drm_device *dev = crtc->dev; | |
2783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2784 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2785 | struct drm_plane *primary = crtc->primary; |
2786 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2787 | struct drm_i915_gem_object *obj; |
17638cd6 | 2788 | int plane = intel_crtc->plane; |
e506a0c6 | 2789 | unsigned long linear_offset; |
17638cd6 | 2790 | u32 dspcntr; |
f45651ba | 2791 | u32 reg = DSPCNTR(plane); |
48404c1e | 2792 | int pixel_size; |
f45651ba | 2793 | |
b70709a6 | 2794 | if (!visible || !fb) { |
fdd508a6 VS |
2795 | I915_WRITE(reg, 0); |
2796 | I915_WRITE(DSPSURF(plane), 0); | |
2797 | POSTING_READ(reg); | |
2798 | return; | |
2799 | } | |
2800 | ||
c9ba6fad VS |
2801 | obj = intel_fb_obj(fb); |
2802 | if (WARN_ON(obj == NULL)) | |
2803 | return; | |
2804 | ||
2805 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2806 | ||
f45651ba VS |
2807 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2808 | ||
fdd508a6 | 2809 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2810 | |
2811 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2812 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2813 | |
57779d06 VS |
2814 | switch (fb->pixel_format) { |
2815 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2816 | dspcntr |= DISPPLANE_8BPP; |
2817 | break; | |
57779d06 VS |
2818 | case DRM_FORMAT_RGB565: |
2819 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2820 | break; |
57779d06 | 2821 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2822 | dspcntr |= DISPPLANE_BGRX888; |
2823 | break; | |
2824 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2825 | dspcntr |= DISPPLANE_RGBX888; |
2826 | break; | |
2827 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2828 | dspcntr |= DISPPLANE_BGRX101010; |
2829 | break; | |
2830 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2831 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2832 | break; |
2833 | default: | |
baba133a | 2834 | BUG(); |
17638cd6 JB |
2835 | } |
2836 | ||
2837 | if (obj->tiling_mode != I915_TILING_NONE) | |
2838 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2839 | |
f45651ba | 2840 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2841 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2842 | |
b9897127 | 2843 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2844 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2845 | intel_gen4_compute_page_offset(dev_priv, |
2846 | &x, &y, obj->tiling_mode, | |
b9897127 | 2847 | pixel_size, |
bc752862 | 2848 | fb->pitches[0]); |
c2c75131 | 2849 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2850 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2851 | dspcntr |= DISPPLANE_ROTATE_180; |
2852 | ||
2853 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2854 | x += (intel_crtc->config->pipe_src_w - 1); |
2855 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2856 | |
2857 | /* Finding the last pixel of the last line of the display | |
2858 | data and adding to linear_offset*/ | |
2859 | linear_offset += | |
6e3c9717 ACO |
2860 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2861 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2862 | } |
2863 | } | |
2864 | ||
2865 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2866 | |
01f2c773 | 2867 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2868 | I915_WRITE(DSPSURF(plane), |
2869 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2870 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2871 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2872 | } else { | |
2873 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2874 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2875 | } | |
17638cd6 | 2876 | POSTING_READ(reg); |
17638cd6 JB |
2877 | } |
2878 | ||
b321803d DL |
2879 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2880 | uint32_t pixel_format) | |
2881 | { | |
2882 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2883 | ||
2884 | /* | |
2885 | * The stride is either expressed as a multiple of 64 bytes | |
2886 | * chunks for linear buffers or in number of tiles for tiled | |
2887 | * buffers. | |
2888 | */ | |
2889 | switch (fb_modifier) { | |
2890 | case DRM_FORMAT_MOD_NONE: | |
2891 | return 64; | |
2892 | case I915_FORMAT_MOD_X_TILED: | |
2893 | if (INTEL_INFO(dev)->gen == 2) | |
2894 | return 128; | |
2895 | return 512; | |
2896 | case I915_FORMAT_MOD_Y_TILED: | |
2897 | /* No need to check for old gens and Y tiling since this is | |
2898 | * about the display engine and those will be blocked before | |
2899 | * we get here. | |
2900 | */ | |
2901 | return 128; | |
2902 | case I915_FORMAT_MOD_Yf_TILED: | |
2903 | if (bits_per_pixel == 8) | |
2904 | return 64; | |
2905 | else | |
2906 | return 128; | |
2907 | default: | |
2908 | MISSING_CASE(fb_modifier); | |
2909 | return 64; | |
2910 | } | |
2911 | } | |
2912 | ||
121920fa TU |
2913 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2914 | struct drm_i915_gem_object *obj) | |
2915 | { | |
9abc4648 | 2916 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2917 | |
2918 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2919 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2920 | |
2921 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2922 | } | |
2923 | ||
e435d6e5 ML |
2924 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2925 | { | |
2926 | struct drm_device *dev = intel_crtc->base.dev; | |
2927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2928 | ||
2929 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2930 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2931 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
2932 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2933 | intel_crtc->base.base.id, intel_crtc->pipe, id); | |
2934 | } | |
2935 | ||
a1b2278e CK |
2936 | /* |
2937 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2938 | */ | |
0583236e | 2939 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2940 | { |
a1b2278e CK |
2941 | struct intel_crtc_scaler_state *scaler_state; |
2942 | int i; | |
2943 | ||
a1b2278e CK |
2944 | scaler_state = &intel_crtc->config->scaler_state; |
2945 | ||
2946 | /* loop through and disable scalers that aren't in use */ | |
2947 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2948 | if (!scaler_state->scalers[i].in_use) |
2949 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2950 | } |
2951 | } | |
2952 | ||
6156a456 | 2953 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2954 | { |
6156a456 | 2955 | switch (pixel_format) { |
d161cf7a | 2956 | case DRM_FORMAT_C8: |
c34ce3d1 | 2957 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2958 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2959 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2960 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2961 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2962 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2963 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2964 | /* |
2965 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2966 | * to be already pre-multiplied. We need to add a knob (or a different | |
2967 | * DRM_FORMAT) for user-space to configure that. | |
2968 | */ | |
f75fb42a | 2969 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2970 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2971 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2972 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2973 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2974 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2975 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2976 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2977 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2978 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2979 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2980 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2981 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2982 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2983 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2984 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2985 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2986 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2987 | default: |
4249eeef | 2988 | MISSING_CASE(pixel_format); |
70d21f0e | 2989 | } |
8cfcba41 | 2990 | |
c34ce3d1 | 2991 | return 0; |
6156a456 | 2992 | } |
70d21f0e | 2993 | |
6156a456 CK |
2994 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2995 | { | |
6156a456 | 2996 | switch (fb_modifier) { |
30af77c4 | 2997 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2998 | break; |
30af77c4 | 2999 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3000 | return PLANE_CTL_TILED_X; |
b321803d | 3001 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3002 | return PLANE_CTL_TILED_Y; |
b321803d | 3003 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3004 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3005 | default: |
6156a456 | 3006 | MISSING_CASE(fb_modifier); |
70d21f0e | 3007 | } |
8cfcba41 | 3008 | |
c34ce3d1 | 3009 | return 0; |
6156a456 | 3010 | } |
70d21f0e | 3011 | |
6156a456 CK |
3012 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3013 | { | |
3b7a5119 | 3014 | switch (rotation) { |
6156a456 CK |
3015 | case BIT(DRM_ROTATE_0): |
3016 | break; | |
1e8df167 SJ |
3017 | /* |
3018 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3019 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3020 | */ | |
3b7a5119 | 3021 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3022 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3023 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3024 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3025 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3026 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3027 | default: |
3028 | MISSING_CASE(rotation); | |
3029 | } | |
3030 | ||
c34ce3d1 | 3031 | return 0; |
6156a456 CK |
3032 | } |
3033 | ||
3034 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3035 | struct drm_framebuffer *fb, | |
3036 | int x, int y) | |
3037 | { | |
3038 | struct drm_device *dev = crtc->dev; | |
3039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3040 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3041 | struct drm_plane *plane = crtc->primary; |
3042 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3043 | struct drm_i915_gem_object *obj; |
3044 | int pipe = intel_crtc->pipe; | |
3045 | u32 plane_ctl, stride_div, stride; | |
3046 | u32 tile_height, plane_offset, plane_size; | |
3047 | unsigned int rotation; | |
3048 | int x_offset, y_offset; | |
3049 | unsigned long surf_addr; | |
6156a456 CK |
3050 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3051 | struct intel_plane_state *plane_state; | |
3052 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3053 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3054 | int scaler_id = -1; | |
3055 | ||
6156a456 CK |
3056 | plane_state = to_intel_plane_state(plane->state); |
3057 | ||
b70709a6 | 3058 | if (!visible || !fb) { |
6156a456 CK |
3059 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3060 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3061 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3062 | return; | |
3b7a5119 | 3063 | } |
70d21f0e | 3064 | |
6156a456 CK |
3065 | plane_ctl = PLANE_CTL_ENABLE | |
3066 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3067 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3068 | ||
3069 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3070 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3071 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3072 | ||
3073 | rotation = plane->state->rotation; | |
3074 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3075 | ||
b321803d DL |
3076 | obj = intel_fb_obj(fb); |
3077 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3078 | fb->pixel_format); | |
3b7a5119 SJ |
3079 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3080 | ||
6156a456 CK |
3081 | /* |
3082 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3083 | * update_plane helpers are called from legacy paths. | |
3084 | * Once full atomic crtc is available, below check can be avoided. | |
3085 | */ | |
3086 | if (drm_rect_width(&plane_state->src)) { | |
3087 | scaler_id = plane_state->scaler_id; | |
3088 | src_x = plane_state->src.x1 >> 16; | |
3089 | src_y = plane_state->src.y1 >> 16; | |
3090 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3091 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3092 | dst_x = plane_state->dst.x1; | |
3093 | dst_y = plane_state->dst.y1; | |
3094 | dst_w = drm_rect_width(&plane_state->dst); | |
3095 | dst_h = drm_rect_height(&plane_state->dst); | |
3096 | ||
3097 | WARN_ON(x != src_x || y != src_y); | |
3098 | } else { | |
3099 | src_w = intel_crtc->config->pipe_src_w; | |
3100 | src_h = intel_crtc->config->pipe_src_h; | |
3101 | } | |
3102 | ||
3b7a5119 SJ |
3103 | if (intel_rotation_90_or_270(rotation)) { |
3104 | /* stride = Surface height in tiles */ | |
2614f17d | 3105 | tile_height = intel_tile_height(dev, fb->pixel_format, |
3b7a5119 SJ |
3106 | fb->modifier[0]); |
3107 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3108 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3109 | y_offset = x; |
6156a456 | 3110 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3111 | } else { |
3112 | stride = fb->pitches[0] / stride_div; | |
3113 | x_offset = x; | |
3114 | y_offset = y; | |
6156a456 | 3115 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3116 | } |
3117 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3118 | |
70d21f0e | 3119 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3120 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3121 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3122 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3123 | |
3124 | if (scaler_id >= 0) { | |
3125 | uint32_t ps_ctrl = 0; | |
3126 | ||
3127 | WARN_ON(!dst_w || !dst_h); | |
3128 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3129 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3130 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3131 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3132 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3133 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3134 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3135 | } else { | |
3136 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3137 | } | |
3138 | ||
121920fa | 3139 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3140 | |
3141 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3142 | } | |
3143 | ||
17638cd6 JB |
3144 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3145 | static int | |
3146 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3147 | int x, int y, enum mode_set_atomic state) | |
3148 | { | |
3149 | struct drm_device *dev = crtc->dev; | |
3150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3151 | |
ff2a3117 | 3152 | if (dev_priv->fbc.disable_fbc) |
7733b49b | 3153 | dev_priv->fbc.disable_fbc(dev_priv); |
81255565 | 3154 | |
29b9bde6 DV |
3155 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3156 | ||
3157 | return 0; | |
81255565 JB |
3158 | } |
3159 | ||
7514747d | 3160 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3161 | { |
96a02917 VS |
3162 | struct drm_crtc *crtc; |
3163 | ||
70e1e0ec | 3164 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3165 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3166 | enum plane plane = intel_crtc->plane; | |
3167 | ||
3168 | intel_prepare_page_flip(dev, plane); | |
3169 | intel_finish_page_flip_plane(dev, plane); | |
3170 | } | |
7514747d VS |
3171 | } |
3172 | ||
3173 | static void intel_update_primary_planes(struct drm_device *dev) | |
3174 | { | |
3175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3176 | struct drm_crtc *crtc; | |
96a02917 | 3177 | |
70e1e0ec | 3178 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3179 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3180 | ||
51fd371b | 3181 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3182 | /* |
3183 | * FIXME: Once we have proper support for primary planes (and | |
3184 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3185 | * a NULL crtc->primary->fb. |
947fdaad | 3186 | */ |
f4510a27 | 3187 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3188 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3189 | crtc->primary->fb, |
262ca2b0 MR |
3190 | crtc->x, |
3191 | crtc->y); | |
51fd371b | 3192 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3193 | } |
3194 | } | |
3195 | ||
7514747d VS |
3196 | void intel_prepare_reset(struct drm_device *dev) |
3197 | { | |
3198 | /* no reset support for gen2 */ | |
3199 | if (IS_GEN2(dev)) | |
3200 | return; | |
3201 | ||
3202 | /* reset doesn't touch the display */ | |
3203 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3204 | return; | |
3205 | ||
3206 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3207 | /* |
3208 | * Disabling the crtcs gracefully seems nicer. Also the | |
3209 | * g33 docs say we should at least disable all the planes. | |
3210 | */ | |
6b72d486 | 3211 | intel_display_suspend(dev); |
7514747d VS |
3212 | } |
3213 | ||
3214 | void intel_finish_reset(struct drm_device *dev) | |
3215 | { | |
3216 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3217 | ||
3218 | /* | |
3219 | * Flips in the rings will be nuked by the reset, | |
3220 | * so complete all pending flips so that user space | |
3221 | * will get its events and not get stuck. | |
3222 | */ | |
3223 | intel_complete_page_flips(dev); | |
3224 | ||
3225 | /* no reset support for gen2 */ | |
3226 | if (IS_GEN2(dev)) | |
3227 | return; | |
3228 | ||
3229 | /* reset doesn't touch the display */ | |
3230 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3231 | /* | |
3232 | * Flips in the rings have been nuked by the reset, | |
3233 | * so update the base address of all primary | |
3234 | * planes to the the last fb to make sure we're | |
3235 | * showing the correct fb after a reset. | |
3236 | */ | |
3237 | intel_update_primary_planes(dev); | |
3238 | return; | |
3239 | } | |
3240 | ||
3241 | /* | |
3242 | * The display has been reset as well, | |
3243 | * so need a full re-initialization. | |
3244 | */ | |
3245 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3246 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3247 | ||
3248 | intel_modeset_init_hw(dev); | |
3249 | ||
3250 | spin_lock_irq(&dev_priv->irq_lock); | |
3251 | if (dev_priv->display.hpd_irq_setup) | |
3252 | dev_priv->display.hpd_irq_setup(dev); | |
3253 | spin_unlock_irq(&dev_priv->irq_lock); | |
3254 | ||
043e9bda | 3255 | intel_display_resume(dev); |
7514747d VS |
3256 | |
3257 | intel_hpd_init(dev_priv); | |
3258 | ||
3259 | drm_modeset_unlock_all(dev); | |
3260 | } | |
3261 | ||
2e2f351d | 3262 | static void |
14667a4b CW |
3263 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3264 | { | |
2ff8fde1 | 3265 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3266 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3267 | bool was_interruptible = dev_priv->mm.interruptible; |
3268 | int ret; | |
3269 | ||
14667a4b CW |
3270 | /* Big Hammer, we also need to ensure that any pending |
3271 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3272 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3273 | * framebuffer. Note that we rely on userspace rendering |
3274 | * into the buffer attached to the pipe they are waiting | |
3275 | * on. If not, userspace generates a GPU hang with IPEHR | |
3276 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3277 | * |
3278 | * This should only fail upon a hung GPU, in which case we | |
3279 | * can safely continue. | |
3280 | */ | |
3281 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3282 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3283 | dev_priv->mm.interruptible = was_interruptible; |
3284 | ||
2e2f351d | 3285 | WARN_ON(ret); |
14667a4b CW |
3286 | } |
3287 | ||
7d5e3799 CW |
3288 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3289 | { | |
3290 | struct drm_device *dev = crtc->dev; | |
3291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3293 | bool pending; |
3294 | ||
3295 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3296 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3297 | return false; | |
3298 | ||
5e2d7afc | 3299 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3300 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3301 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3302 | |
3303 | return pending; | |
3304 | } | |
3305 | ||
e30e8f75 GP |
3306 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3307 | { | |
3308 | struct drm_device *dev = crtc->base.dev; | |
3309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3310 | const struct drm_display_mode *adjusted_mode; | |
3311 | ||
3312 | if (!i915.fastboot) | |
3313 | return; | |
3314 | ||
3315 | /* | |
3316 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3317 | * that in compute_mode_changes we check the native mode (not the pfit | |
3318 | * mode) to see if we can flip rather than do a full mode set. In the | |
3319 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3320 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3321 | * sized surface. | |
3322 | * | |
3323 | * To fix this properly, we need to hoist the checks up into | |
3324 | * compute_mode_changes (or above), check the actual pfit state and | |
3325 | * whether the platform allows pfit disable with pipe active, and only | |
3326 | * then update the pipesrc and pfit state, even on the flip path. | |
3327 | */ | |
3328 | ||
6e3c9717 | 3329 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3330 | |
3331 | I915_WRITE(PIPESRC(crtc->pipe), | |
3332 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3333 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3334 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3335 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3336 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3337 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3338 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3339 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3340 | } | |
6e3c9717 ACO |
3341 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3342 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3343 | } |
3344 | ||
5e84e1a4 ZW |
3345 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3346 | { | |
3347 | struct drm_device *dev = crtc->dev; | |
3348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3350 | int pipe = intel_crtc->pipe; | |
3351 | u32 reg, temp; | |
3352 | ||
3353 | /* enable normal train */ | |
3354 | reg = FDI_TX_CTL(pipe); | |
3355 | temp = I915_READ(reg); | |
61e499bf | 3356 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3357 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3358 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3359 | } else { |
3360 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3361 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3362 | } |
5e84e1a4 ZW |
3363 | I915_WRITE(reg, temp); |
3364 | ||
3365 | reg = FDI_RX_CTL(pipe); | |
3366 | temp = I915_READ(reg); | |
3367 | if (HAS_PCH_CPT(dev)) { | |
3368 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3369 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3370 | } else { | |
3371 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3372 | temp |= FDI_LINK_TRAIN_NONE; | |
3373 | } | |
3374 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3375 | ||
3376 | /* wait one idle pattern time */ | |
3377 | POSTING_READ(reg); | |
3378 | udelay(1000); | |
357555c0 JB |
3379 | |
3380 | /* IVB wants error correction enabled */ | |
3381 | if (IS_IVYBRIDGE(dev)) | |
3382 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3383 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3384 | } |
3385 | ||
8db9d77b ZW |
3386 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3387 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3388 | { | |
3389 | struct drm_device *dev = crtc->dev; | |
3390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3392 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3393 | u32 reg, temp, tries; |
8db9d77b | 3394 | |
1c8562f6 | 3395 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3396 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3397 | |
e1a44743 AJ |
3398 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3399 | for train result */ | |
5eddb70b CW |
3400 | reg = FDI_RX_IMR(pipe); |
3401 | temp = I915_READ(reg); | |
e1a44743 AJ |
3402 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3403 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3404 | I915_WRITE(reg, temp); |
3405 | I915_READ(reg); | |
e1a44743 AJ |
3406 | udelay(150); |
3407 | ||
8db9d77b | 3408 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3409 | reg = FDI_TX_CTL(pipe); |
3410 | temp = I915_READ(reg); | |
627eb5a3 | 3411 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3412 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3413 | temp &= ~FDI_LINK_TRAIN_NONE; |
3414 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3415 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3416 | |
5eddb70b CW |
3417 | reg = FDI_RX_CTL(pipe); |
3418 | temp = I915_READ(reg); | |
8db9d77b ZW |
3419 | temp &= ~FDI_LINK_TRAIN_NONE; |
3420 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3421 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3422 | ||
3423 | POSTING_READ(reg); | |
8db9d77b ZW |
3424 | udelay(150); |
3425 | ||
5b2adf89 | 3426 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3427 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3428 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3429 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3430 | |
5eddb70b | 3431 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3432 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3433 | temp = I915_READ(reg); |
8db9d77b ZW |
3434 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3435 | ||
3436 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3437 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3438 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3439 | break; |
3440 | } | |
8db9d77b | 3441 | } |
e1a44743 | 3442 | if (tries == 5) |
5eddb70b | 3443 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3444 | |
3445 | /* Train 2 */ | |
5eddb70b CW |
3446 | reg = FDI_TX_CTL(pipe); |
3447 | temp = I915_READ(reg); | |
8db9d77b ZW |
3448 | temp &= ~FDI_LINK_TRAIN_NONE; |
3449 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3450 | I915_WRITE(reg, temp); |
8db9d77b | 3451 | |
5eddb70b CW |
3452 | reg = FDI_RX_CTL(pipe); |
3453 | temp = I915_READ(reg); | |
8db9d77b ZW |
3454 | temp &= ~FDI_LINK_TRAIN_NONE; |
3455 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3456 | I915_WRITE(reg, temp); |
8db9d77b | 3457 | |
5eddb70b CW |
3458 | POSTING_READ(reg); |
3459 | udelay(150); | |
8db9d77b | 3460 | |
5eddb70b | 3461 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3462 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3463 | temp = I915_READ(reg); |
8db9d77b ZW |
3464 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3465 | ||
3466 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3467 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3468 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3469 | break; | |
3470 | } | |
8db9d77b | 3471 | } |
e1a44743 | 3472 | if (tries == 5) |
5eddb70b | 3473 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3474 | |
3475 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3476 | |
8db9d77b ZW |
3477 | } |
3478 | ||
0206e353 | 3479 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3480 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3481 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3482 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3483 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3484 | }; | |
3485 | ||
3486 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3487 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3488 | { | |
3489 | struct drm_device *dev = crtc->dev; | |
3490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3491 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3492 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3493 | u32 reg, temp, i, retry; |
8db9d77b | 3494 | |
e1a44743 AJ |
3495 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3496 | for train result */ | |
5eddb70b CW |
3497 | reg = FDI_RX_IMR(pipe); |
3498 | temp = I915_READ(reg); | |
e1a44743 AJ |
3499 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3500 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3501 | I915_WRITE(reg, temp); |
3502 | ||
3503 | POSTING_READ(reg); | |
e1a44743 AJ |
3504 | udelay(150); |
3505 | ||
8db9d77b | 3506 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3507 | reg = FDI_TX_CTL(pipe); |
3508 | temp = I915_READ(reg); | |
627eb5a3 | 3509 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3510 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3511 | temp &= ~FDI_LINK_TRAIN_NONE; |
3512 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3513 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3514 | /* SNB-B */ | |
3515 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3516 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3517 | |
d74cf324 DV |
3518 | I915_WRITE(FDI_RX_MISC(pipe), |
3519 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3520 | ||
5eddb70b CW |
3521 | reg = FDI_RX_CTL(pipe); |
3522 | temp = I915_READ(reg); | |
8db9d77b ZW |
3523 | if (HAS_PCH_CPT(dev)) { |
3524 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3525 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3526 | } else { | |
3527 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3528 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3529 | } | |
5eddb70b CW |
3530 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3531 | ||
3532 | POSTING_READ(reg); | |
8db9d77b ZW |
3533 | udelay(150); |
3534 | ||
0206e353 | 3535 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3536 | reg = FDI_TX_CTL(pipe); |
3537 | temp = I915_READ(reg); | |
8db9d77b ZW |
3538 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3539 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3540 | I915_WRITE(reg, temp); |
3541 | ||
3542 | POSTING_READ(reg); | |
8db9d77b ZW |
3543 | udelay(500); |
3544 | ||
fa37d39e SP |
3545 | for (retry = 0; retry < 5; retry++) { |
3546 | reg = FDI_RX_IIR(pipe); | |
3547 | temp = I915_READ(reg); | |
3548 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3549 | if (temp & FDI_RX_BIT_LOCK) { | |
3550 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3551 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3552 | break; | |
3553 | } | |
3554 | udelay(50); | |
8db9d77b | 3555 | } |
fa37d39e SP |
3556 | if (retry < 5) |
3557 | break; | |
8db9d77b ZW |
3558 | } |
3559 | if (i == 4) | |
5eddb70b | 3560 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3561 | |
3562 | /* Train 2 */ | |
5eddb70b CW |
3563 | reg = FDI_TX_CTL(pipe); |
3564 | temp = I915_READ(reg); | |
8db9d77b ZW |
3565 | temp &= ~FDI_LINK_TRAIN_NONE; |
3566 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3567 | if (IS_GEN6(dev)) { | |
3568 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3569 | /* SNB-B */ | |
3570 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3571 | } | |
5eddb70b | 3572 | I915_WRITE(reg, temp); |
8db9d77b | 3573 | |
5eddb70b CW |
3574 | reg = FDI_RX_CTL(pipe); |
3575 | temp = I915_READ(reg); | |
8db9d77b ZW |
3576 | if (HAS_PCH_CPT(dev)) { |
3577 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3578 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3579 | } else { | |
3580 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3581 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3582 | } | |
5eddb70b CW |
3583 | I915_WRITE(reg, temp); |
3584 | ||
3585 | POSTING_READ(reg); | |
8db9d77b ZW |
3586 | udelay(150); |
3587 | ||
0206e353 | 3588 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3589 | reg = FDI_TX_CTL(pipe); |
3590 | temp = I915_READ(reg); | |
8db9d77b ZW |
3591 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3592 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3593 | I915_WRITE(reg, temp); |
3594 | ||
3595 | POSTING_READ(reg); | |
8db9d77b ZW |
3596 | udelay(500); |
3597 | ||
fa37d39e SP |
3598 | for (retry = 0; retry < 5; retry++) { |
3599 | reg = FDI_RX_IIR(pipe); | |
3600 | temp = I915_READ(reg); | |
3601 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3602 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3603 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3604 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3605 | break; | |
3606 | } | |
3607 | udelay(50); | |
8db9d77b | 3608 | } |
fa37d39e SP |
3609 | if (retry < 5) |
3610 | break; | |
8db9d77b ZW |
3611 | } |
3612 | if (i == 4) | |
5eddb70b | 3613 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3614 | |
3615 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3616 | } | |
3617 | ||
357555c0 JB |
3618 | /* Manual link training for Ivy Bridge A0 parts */ |
3619 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3620 | { | |
3621 | struct drm_device *dev = crtc->dev; | |
3622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3624 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3625 | u32 reg, temp, i, j; |
357555c0 JB |
3626 | |
3627 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3628 | for train result */ | |
3629 | reg = FDI_RX_IMR(pipe); | |
3630 | temp = I915_READ(reg); | |
3631 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3632 | temp &= ~FDI_RX_BIT_LOCK; | |
3633 | I915_WRITE(reg, temp); | |
3634 | ||
3635 | POSTING_READ(reg); | |
3636 | udelay(150); | |
3637 | ||
01a415fd DV |
3638 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3639 | I915_READ(FDI_RX_IIR(pipe))); | |
3640 | ||
139ccd3f JB |
3641 | /* Try each vswing and preemphasis setting twice before moving on */ |
3642 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3643 | /* disable first in case we need to retry */ | |
3644 | reg = FDI_TX_CTL(pipe); | |
3645 | temp = I915_READ(reg); | |
3646 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3647 | temp &= ~FDI_TX_ENABLE; | |
3648 | I915_WRITE(reg, temp); | |
357555c0 | 3649 | |
139ccd3f JB |
3650 | reg = FDI_RX_CTL(pipe); |
3651 | temp = I915_READ(reg); | |
3652 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3653 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3654 | temp &= ~FDI_RX_ENABLE; | |
3655 | I915_WRITE(reg, temp); | |
357555c0 | 3656 | |
139ccd3f | 3657 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3658 | reg = FDI_TX_CTL(pipe); |
3659 | temp = I915_READ(reg); | |
139ccd3f | 3660 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3661 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3662 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3663 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3664 | temp |= snb_b_fdi_train_param[j/2]; |
3665 | temp |= FDI_COMPOSITE_SYNC; | |
3666 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3667 | |
139ccd3f JB |
3668 | I915_WRITE(FDI_RX_MISC(pipe), |
3669 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3670 | |
139ccd3f | 3671 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3672 | temp = I915_READ(reg); |
139ccd3f JB |
3673 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3674 | temp |= FDI_COMPOSITE_SYNC; | |
3675 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3676 | |
139ccd3f JB |
3677 | POSTING_READ(reg); |
3678 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3679 | |
139ccd3f JB |
3680 | for (i = 0; i < 4; i++) { |
3681 | reg = FDI_RX_IIR(pipe); | |
3682 | temp = I915_READ(reg); | |
3683 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3684 | |
139ccd3f JB |
3685 | if (temp & FDI_RX_BIT_LOCK || |
3686 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3687 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3688 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3689 | i); | |
3690 | break; | |
3691 | } | |
3692 | udelay(1); /* should be 0.5us */ | |
3693 | } | |
3694 | if (i == 4) { | |
3695 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3696 | continue; | |
3697 | } | |
357555c0 | 3698 | |
139ccd3f | 3699 | /* Train 2 */ |
357555c0 JB |
3700 | reg = FDI_TX_CTL(pipe); |
3701 | temp = I915_READ(reg); | |
139ccd3f JB |
3702 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3703 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3704 | I915_WRITE(reg, temp); | |
3705 | ||
3706 | reg = FDI_RX_CTL(pipe); | |
3707 | temp = I915_READ(reg); | |
3708 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3709 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3710 | I915_WRITE(reg, temp); |
3711 | ||
3712 | POSTING_READ(reg); | |
139ccd3f | 3713 | udelay(2); /* should be 1.5us */ |
357555c0 | 3714 | |
139ccd3f JB |
3715 | for (i = 0; i < 4; i++) { |
3716 | reg = FDI_RX_IIR(pipe); | |
3717 | temp = I915_READ(reg); | |
3718 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3719 | |
139ccd3f JB |
3720 | if (temp & FDI_RX_SYMBOL_LOCK || |
3721 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3722 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3723 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3724 | i); | |
3725 | goto train_done; | |
3726 | } | |
3727 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3728 | } |
139ccd3f JB |
3729 | if (i == 4) |
3730 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3731 | } |
357555c0 | 3732 | |
139ccd3f | 3733 | train_done: |
357555c0 JB |
3734 | DRM_DEBUG_KMS("FDI train done.\n"); |
3735 | } | |
3736 | ||
88cefb6c | 3737 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3738 | { |
88cefb6c | 3739 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3740 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3741 | int pipe = intel_crtc->pipe; |
5eddb70b | 3742 | u32 reg, temp; |
79e53945 | 3743 | |
c64e311e | 3744 | |
c98e9dcf | 3745 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3746 | reg = FDI_RX_CTL(pipe); |
3747 | temp = I915_READ(reg); | |
627eb5a3 | 3748 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3749 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3750 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3751 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3752 | ||
3753 | POSTING_READ(reg); | |
c98e9dcf JB |
3754 | udelay(200); |
3755 | ||
3756 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3757 | temp = I915_READ(reg); |
3758 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3759 | ||
3760 | POSTING_READ(reg); | |
c98e9dcf JB |
3761 | udelay(200); |
3762 | ||
20749730 PZ |
3763 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3764 | reg = FDI_TX_CTL(pipe); | |
3765 | temp = I915_READ(reg); | |
3766 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3767 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3768 | |
20749730 PZ |
3769 | POSTING_READ(reg); |
3770 | udelay(100); | |
6be4a607 | 3771 | } |
0e23b99d JB |
3772 | } |
3773 | ||
88cefb6c DV |
3774 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3775 | { | |
3776 | struct drm_device *dev = intel_crtc->base.dev; | |
3777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3778 | int pipe = intel_crtc->pipe; | |
3779 | u32 reg, temp; | |
3780 | ||
3781 | /* Switch from PCDclk to Rawclk */ | |
3782 | reg = FDI_RX_CTL(pipe); | |
3783 | temp = I915_READ(reg); | |
3784 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3785 | ||
3786 | /* Disable CPU FDI TX PLL */ | |
3787 | reg = FDI_TX_CTL(pipe); | |
3788 | temp = I915_READ(reg); | |
3789 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3790 | ||
3791 | POSTING_READ(reg); | |
3792 | udelay(100); | |
3793 | ||
3794 | reg = FDI_RX_CTL(pipe); | |
3795 | temp = I915_READ(reg); | |
3796 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3797 | ||
3798 | /* Wait for the clocks to turn off. */ | |
3799 | POSTING_READ(reg); | |
3800 | udelay(100); | |
3801 | } | |
3802 | ||
0fc932b8 JB |
3803 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3804 | { | |
3805 | struct drm_device *dev = crtc->dev; | |
3806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3808 | int pipe = intel_crtc->pipe; | |
3809 | u32 reg, temp; | |
3810 | ||
3811 | /* disable CPU FDI tx and PCH FDI rx */ | |
3812 | reg = FDI_TX_CTL(pipe); | |
3813 | temp = I915_READ(reg); | |
3814 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3815 | POSTING_READ(reg); | |
3816 | ||
3817 | reg = FDI_RX_CTL(pipe); | |
3818 | temp = I915_READ(reg); | |
3819 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3820 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3821 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3822 | ||
3823 | POSTING_READ(reg); | |
3824 | udelay(100); | |
3825 | ||
3826 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3827 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3828 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3829 | |
3830 | /* still set train pattern 1 */ | |
3831 | reg = FDI_TX_CTL(pipe); | |
3832 | temp = I915_READ(reg); | |
3833 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3834 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3835 | I915_WRITE(reg, temp); | |
3836 | ||
3837 | reg = FDI_RX_CTL(pipe); | |
3838 | temp = I915_READ(reg); | |
3839 | if (HAS_PCH_CPT(dev)) { | |
3840 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3841 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3842 | } else { | |
3843 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3844 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3845 | } | |
3846 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3847 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3848 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3849 | I915_WRITE(reg, temp); |
3850 | ||
3851 | POSTING_READ(reg); | |
3852 | udelay(100); | |
3853 | } | |
3854 | ||
5dce5b93 CW |
3855 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3856 | { | |
3857 | struct intel_crtc *crtc; | |
3858 | ||
3859 | /* Note that we don't need to be called with mode_config.lock here | |
3860 | * as our list of CRTC objects is static for the lifetime of the | |
3861 | * device and so cannot disappear as we iterate. Similarly, we can | |
3862 | * happily treat the predicates as racy, atomic checks as userspace | |
3863 | * cannot claim and pin a new fb without at least acquring the | |
3864 | * struct_mutex and so serialising with us. | |
3865 | */ | |
d3fcc808 | 3866 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3867 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3868 | continue; | |
3869 | ||
3870 | if (crtc->unpin_work) | |
3871 | intel_wait_for_vblank(dev, crtc->pipe); | |
3872 | ||
3873 | return true; | |
3874 | } | |
3875 | ||
3876 | return false; | |
3877 | } | |
3878 | ||
d6bbafa1 CW |
3879 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3880 | { | |
3881 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3882 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3883 | ||
3884 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3885 | smp_rmb(); | |
3886 | intel_crtc->unpin_work = NULL; | |
3887 | ||
3888 | if (work->event) | |
3889 | drm_send_vblank_event(intel_crtc->base.dev, | |
3890 | intel_crtc->pipe, | |
3891 | work->event); | |
3892 | ||
3893 | drm_crtc_vblank_put(&intel_crtc->base); | |
3894 | ||
3895 | wake_up_all(&dev_priv->pending_flip_queue); | |
3896 | queue_work(dev_priv->wq, &work->work); | |
3897 | ||
3898 | trace_i915_flip_complete(intel_crtc->plane, | |
3899 | work->pending_flip_obj); | |
3900 | } | |
3901 | ||
46a55d30 | 3902 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3903 | { |
0f91128d | 3904 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3905 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3906 | |
2c10d571 | 3907 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3908 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3909 | !intel_crtc_has_pending_flip(crtc), | |
3910 | 60*HZ) == 0)) { | |
3911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3912 | |
5e2d7afc | 3913 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3914 | if (intel_crtc->unpin_work) { |
3915 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3916 | page_flip_completed(intel_crtc); | |
3917 | } | |
5e2d7afc | 3918 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3919 | } |
5bb61643 | 3920 | |
975d568a CW |
3921 | if (crtc->primary->fb) { |
3922 | mutex_lock(&dev->struct_mutex); | |
3923 | intel_finish_fb(crtc->primary->fb); | |
3924 | mutex_unlock(&dev->struct_mutex); | |
3925 | } | |
e6c3a2a6 CW |
3926 | } |
3927 | ||
e615efe4 ED |
3928 | /* Program iCLKIP clock to the desired frequency */ |
3929 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3930 | { | |
3931 | struct drm_device *dev = crtc->dev; | |
3932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3933 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3934 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3935 | u32 temp; | |
3936 | ||
a580516d | 3937 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3938 | |
e615efe4 ED |
3939 | /* It is necessary to ungate the pixclk gate prior to programming |
3940 | * the divisors, and gate it back when it is done. | |
3941 | */ | |
3942 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3943 | ||
3944 | /* Disable SSCCTL */ | |
3945 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3946 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3947 | SBI_SSCCTL_DISABLE, | |
3948 | SBI_ICLK); | |
e615efe4 ED |
3949 | |
3950 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3951 | if (clock == 20000) { |
e615efe4 ED |
3952 | auxdiv = 1; |
3953 | divsel = 0x41; | |
3954 | phaseinc = 0x20; | |
3955 | } else { | |
3956 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3957 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3958 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3959 | * convert the virtual clock precision to KHz here for higher |
3960 | * precision. | |
3961 | */ | |
3962 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3963 | u32 iclk_pi_range = 64; | |
3964 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3965 | ||
12d7ceed | 3966 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3967 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3968 | pi_value = desired_divisor % iclk_pi_range; | |
3969 | ||
3970 | auxdiv = 0; | |
3971 | divsel = msb_divisor_value - 2; | |
3972 | phaseinc = pi_value; | |
3973 | } | |
3974 | ||
3975 | /* This should not happen with any sane values */ | |
3976 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3977 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3978 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3979 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3980 | ||
3981 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3982 | clock, |
e615efe4 ED |
3983 | auxdiv, |
3984 | divsel, | |
3985 | phasedir, | |
3986 | phaseinc); | |
3987 | ||
3988 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3989 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3990 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3991 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3992 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3993 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3994 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3995 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3996 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3997 | |
3998 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3999 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4000 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4001 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4002 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4003 | |
4004 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4005 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4006 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4007 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4008 | |
4009 | /* Wait for initialization time */ | |
4010 | udelay(24); | |
4011 | ||
4012 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 4013 | |
a580516d | 4014 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
4015 | } |
4016 | ||
275f01b2 DV |
4017 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4018 | enum pipe pch_transcoder) | |
4019 | { | |
4020 | struct drm_device *dev = crtc->base.dev; | |
4021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4022 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4023 | |
4024 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4025 | I915_READ(HTOTAL(cpu_transcoder))); | |
4026 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4027 | I915_READ(HBLANK(cpu_transcoder))); | |
4028 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4029 | I915_READ(HSYNC(cpu_transcoder))); | |
4030 | ||
4031 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4032 | I915_READ(VTOTAL(cpu_transcoder))); | |
4033 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4034 | I915_READ(VBLANK(cpu_transcoder))); | |
4035 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4036 | I915_READ(VSYNC(cpu_transcoder))); | |
4037 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4038 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4039 | } | |
4040 | ||
003632d9 | 4041 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4042 | { |
4043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4044 | uint32_t temp; | |
4045 | ||
4046 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4047 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4048 | return; |
4049 | ||
4050 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4051 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4052 | ||
003632d9 ACO |
4053 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4054 | if (enable) | |
4055 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4056 | ||
4057 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4058 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4059 | POSTING_READ(SOUTH_CHICKEN1); | |
4060 | } | |
4061 | ||
4062 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4063 | { | |
4064 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4065 | |
4066 | switch (intel_crtc->pipe) { | |
4067 | case PIPE_A: | |
4068 | break; | |
4069 | case PIPE_B: | |
6e3c9717 | 4070 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4071 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4072 | else |
003632d9 | 4073 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4074 | |
4075 | break; | |
4076 | case PIPE_C: | |
003632d9 | 4077 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4078 | |
4079 | break; | |
4080 | default: | |
4081 | BUG(); | |
4082 | } | |
4083 | } | |
4084 | ||
f67a559d JB |
4085 | /* |
4086 | * Enable PCH resources required for PCH ports: | |
4087 | * - PCH PLLs | |
4088 | * - FDI training & RX/TX | |
4089 | * - update transcoder timings | |
4090 | * - DP transcoding bits | |
4091 | * - transcoder | |
4092 | */ | |
4093 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4094 | { |
4095 | struct drm_device *dev = crtc->dev; | |
4096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4098 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4099 | u32 reg, temp; |
2c07245f | 4100 | |
ab9412ba | 4101 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4102 | |
1fbc0d78 DV |
4103 | if (IS_IVYBRIDGE(dev)) |
4104 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4105 | ||
cd986abb DV |
4106 | /* Write the TU size bits before fdi link training, so that error |
4107 | * detection works. */ | |
4108 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4109 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4110 | ||
c98e9dcf | 4111 | /* For PCH output, training FDI link */ |
674cf967 | 4112 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4113 | |
3ad8a208 DV |
4114 | /* We need to program the right clock selection before writing the pixel |
4115 | * mutliplier into the DPLL. */ | |
303b81e0 | 4116 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4117 | u32 sel; |
4b645f14 | 4118 | |
c98e9dcf | 4119 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4120 | temp |= TRANS_DPLL_ENABLE(pipe); |
4121 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4122 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4123 | temp |= sel; |
4124 | else | |
4125 | temp &= ~sel; | |
c98e9dcf | 4126 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4127 | } |
5eddb70b | 4128 | |
3ad8a208 DV |
4129 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4130 | * transcoder, and we actually should do this to not upset any PCH | |
4131 | * transcoder that already use the clock when we share it. | |
4132 | * | |
4133 | * Note that enable_shared_dpll tries to do the right thing, but | |
4134 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4135 | * the right LVDS enable sequence. */ | |
85b3894f | 4136 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4137 | |
d9b6cb56 JB |
4138 | /* set transcoder timing, panel must allow it */ |
4139 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4140 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4141 | |
303b81e0 | 4142 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4143 | |
c98e9dcf | 4144 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4145 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4146 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4147 | reg = TRANS_DP_CTL(pipe); |
4148 | temp = I915_READ(reg); | |
4149 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4150 | TRANS_DP_SYNC_MASK | |
4151 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4152 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4153 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4154 | |
4155 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4156 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4157 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4158 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4159 | |
4160 | switch (intel_trans_dp_port_sel(crtc)) { | |
4161 | case PCH_DP_B: | |
5eddb70b | 4162 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4163 | break; |
4164 | case PCH_DP_C: | |
5eddb70b | 4165 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4166 | break; |
4167 | case PCH_DP_D: | |
5eddb70b | 4168 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4169 | break; |
4170 | default: | |
e95d41e1 | 4171 | BUG(); |
32f9d658 | 4172 | } |
2c07245f | 4173 | |
5eddb70b | 4174 | I915_WRITE(reg, temp); |
6be4a607 | 4175 | } |
b52eb4dc | 4176 | |
b8a4f404 | 4177 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4178 | } |
4179 | ||
1507e5bd PZ |
4180 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4181 | { | |
4182 | struct drm_device *dev = crtc->dev; | |
4183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4185 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4186 | |
ab9412ba | 4187 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4188 | |
8c52b5e8 | 4189 | lpt_program_iclkip(crtc); |
1507e5bd | 4190 | |
0540e488 | 4191 | /* Set transcoder timing. */ |
275f01b2 | 4192 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4193 | |
937bb610 | 4194 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4195 | } |
4196 | ||
190f68c5 ACO |
4197 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4198 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4199 | { |
e2b78267 | 4200 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4201 | struct intel_shared_dpll *pll; |
de419ab6 | 4202 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4203 | enum intel_dpll_id i; |
ee7b9f93 | 4204 | |
de419ab6 ML |
4205 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4206 | ||
98b6bd99 DV |
4207 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4208 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4209 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4210 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4211 | |
46edb027 DV |
4212 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4213 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4214 | |
de419ab6 | 4215 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4216 | |
98b6bd99 DV |
4217 | goto found; |
4218 | } | |
4219 | ||
bcddf610 S |
4220 | if (IS_BROXTON(dev_priv->dev)) { |
4221 | /* PLL is attached to port in bxt */ | |
4222 | struct intel_encoder *encoder; | |
4223 | struct intel_digital_port *intel_dig_port; | |
4224 | ||
4225 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4226 | if (WARN_ON(!encoder)) | |
4227 | return NULL; | |
4228 | ||
4229 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4230 | /* 1:1 mapping between ports and PLLs */ | |
4231 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4232 | pll = &dev_priv->shared_dplls[i]; | |
4233 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4234 | crtc->base.base.id, pll->name); | |
de419ab6 | 4235 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4236 | |
4237 | goto found; | |
4238 | } | |
4239 | ||
e72f9fbf DV |
4240 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4241 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4242 | |
4243 | /* Only want to check enabled timings first */ | |
de419ab6 | 4244 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4245 | continue; |
4246 | ||
190f68c5 | 4247 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4248 | &shared_dpll[i].hw_state, |
4249 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4250 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4251 | crtc->base.base.id, pll->name, |
de419ab6 | 4252 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4253 | pll->active); |
ee7b9f93 JB |
4254 | goto found; |
4255 | } | |
4256 | } | |
4257 | ||
4258 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4259 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4260 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4261 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4262 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4263 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4264 | goto found; |
4265 | } | |
4266 | } | |
4267 | ||
4268 | return NULL; | |
4269 | ||
4270 | found: | |
de419ab6 ML |
4271 | if (shared_dpll[i].crtc_mask == 0) |
4272 | shared_dpll[i].hw_state = | |
4273 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4274 | |
190f68c5 | 4275 | crtc_state->shared_dpll = i; |
46edb027 DV |
4276 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4277 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4278 | |
de419ab6 | 4279 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4280 | |
ee7b9f93 JB |
4281 | return pll; |
4282 | } | |
4283 | ||
de419ab6 | 4284 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4285 | { |
de419ab6 ML |
4286 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4287 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4288 | struct intel_shared_dpll *pll; |
4289 | enum intel_dpll_id i; | |
4290 | ||
de419ab6 ML |
4291 | if (!to_intel_atomic_state(state)->dpll_set) |
4292 | return; | |
8bd31e67 | 4293 | |
de419ab6 | 4294 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4295 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4296 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4297 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4298 | } |
4299 | } | |
4300 | ||
a1520318 | 4301 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4302 | { |
4303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4304 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4305 | u32 temp; |
4306 | ||
4307 | temp = I915_READ(dslreg); | |
4308 | udelay(500); | |
4309 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4310 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4311 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4312 | } |
4313 | } | |
4314 | ||
86adf9d7 ML |
4315 | static int |
4316 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4317 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4318 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4319 | { |
86adf9d7 ML |
4320 | struct intel_crtc_scaler_state *scaler_state = |
4321 | &crtc_state->scaler_state; | |
4322 | struct intel_crtc *intel_crtc = | |
4323 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4324 | int need_scaling; |
6156a456 CK |
4325 | |
4326 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4327 | (src_h != dst_w || src_w != dst_h): | |
4328 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4329 | |
4330 | /* | |
4331 | * if plane is being disabled or scaler is no more required or force detach | |
4332 | * - free scaler binded to this plane/crtc | |
4333 | * - in order to do this, update crtc->scaler_usage | |
4334 | * | |
4335 | * Here scaler state in crtc_state is set free so that | |
4336 | * scaler can be assigned to other user. Actual register | |
4337 | * update to free the scaler is done in plane/panel-fit programming. | |
4338 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4339 | */ | |
86adf9d7 | 4340 | if (force_detach || !need_scaling) { |
a1b2278e | 4341 | if (*scaler_id >= 0) { |
86adf9d7 | 4342 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4343 | scaler_state->scalers[*scaler_id].in_use = 0; |
4344 | ||
86adf9d7 ML |
4345 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4346 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4347 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4348 | scaler_state->scaler_users); |
4349 | *scaler_id = -1; | |
4350 | } | |
4351 | return 0; | |
4352 | } | |
4353 | ||
4354 | /* range checks */ | |
4355 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4356 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4357 | ||
4358 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4359 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4360 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4361 | "size is out of scaler range\n", |
86adf9d7 | 4362 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4363 | return -EINVAL; |
4364 | } | |
4365 | ||
86adf9d7 ML |
4366 | /* mark this plane as a scaler user in crtc_state */ |
4367 | scaler_state->scaler_users |= (1 << scaler_user); | |
4368 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4369 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4370 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4371 | scaler_state->scaler_users); | |
4372 | ||
4373 | return 0; | |
4374 | } | |
4375 | ||
4376 | /** | |
4377 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4378 | * | |
4379 | * @state: crtc's scaler state | |
86adf9d7 ML |
4380 | * |
4381 | * Return | |
4382 | * 0 - scaler_usage updated successfully | |
4383 | * error - requested scaling cannot be supported or other error condition | |
4384 | */ | |
e435d6e5 | 4385 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4386 | { |
4387 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
4388 | struct drm_display_mode *adjusted_mode = | |
4389 | &state->base.adjusted_mode; | |
4390 | ||
4391 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4392 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4393 | ||
e435d6e5 | 4394 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4395 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4396 | state->pipe_src_w, state->pipe_src_h, | |
8c6cda29 | 4397 | adjusted_mode->hdisplay, adjusted_mode->vdisplay); |
86adf9d7 ML |
4398 | } |
4399 | ||
4400 | /** | |
4401 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4402 | * | |
4403 | * @state: crtc's scaler state | |
86adf9d7 ML |
4404 | * @plane_state: atomic plane state to update |
4405 | * | |
4406 | * Return | |
4407 | * 0 - scaler_usage updated successfully | |
4408 | * error - requested scaling cannot be supported or other error condition | |
4409 | */ | |
da20eabd ML |
4410 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4411 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4412 | { |
4413 | ||
4414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4415 | struct intel_plane *intel_plane = |
4416 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4417 | struct drm_framebuffer *fb = plane_state->base.fb; |
4418 | int ret; | |
4419 | ||
4420 | bool force_detach = !fb || !plane_state->visible; | |
4421 | ||
4422 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4423 | intel_plane->base.base.id, intel_crtc->pipe, | |
4424 | drm_plane_index(&intel_plane->base)); | |
4425 | ||
4426 | ret = skl_update_scaler(crtc_state, force_detach, | |
4427 | drm_plane_index(&intel_plane->base), | |
4428 | &plane_state->scaler_id, | |
4429 | plane_state->base.rotation, | |
4430 | drm_rect_width(&plane_state->src) >> 16, | |
4431 | drm_rect_height(&plane_state->src) >> 16, | |
4432 | drm_rect_width(&plane_state->dst), | |
4433 | drm_rect_height(&plane_state->dst)); | |
4434 | ||
4435 | if (ret || plane_state->scaler_id < 0) | |
4436 | return ret; | |
4437 | ||
a1b2278e | 4438 | /* check colorkey */ |
818ed961 | 4439 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4440 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4441 | intel_plane->base.base.id); |
a1b2278e CK |
4442 | return -EINVAL; |
4443 | } | |
4444 | ||
4445 | /* Check src format */ | |
86adf9d7 ML |
4446 | switch (fb->pixel_format) { |
4447 | case DRM_FORMAT_RGB565: | |
4448 | case DRM_FORMAT_XBGR8888: | |
4449 | case DRM_FORMAT_XRGB8888: | |
4450 | case DRM_FORMAT_ABGR8888: | |
4451 | case DRM_FORMAT_ARGB8888: | |
4452 | case DRM_FORMAT_XRGB2101010: | |
4453 | case DRM_FORMAT_XBGR2101010: | |
4454 | case DRM_FORMAT_YUYV: | |
4455 | case DRM_FORMAT_YVYU: | |
4456 | case DRM_FORMAT_UYVY: | |
4457 | case DRM_FORMAT_VYUY: | |
4458 | break; | |
4459 | default: | |
4460 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4461 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4462 | return -EINVAL; | |
a1b2278e CK |
4463 | } |
4464 | ||
a1b2278e CK |
4465 | return 0; |
4466 | } | |
4467 | ||
e435d6e5 ML |
4468 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4469 | { | |
4470 | int i; | |
4471 | ||
4472 | for (i = 0; i < crtc->num_scalers; i++) | |
4473 | skl_detach_scaler(crtc, i); | |
4474 | } | |
4475 | ||
4476 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4477 | { |
4478 | struct drm_device *dev = crtc->base.dev; | |
4479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4480 | int pipe = crtc->pipe; | |
a1b2278e CK |
4481 | struct intel_crtc_scaler_state *scaler_state = |
4482 | &crtc->config->scaler_state; | |
4483 | ||
4484 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4485 | ||
6e3c9717 | 4486 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4487 | int id; |
4488 | ||
4489 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4490 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4491 | return; | |
4492 | } | |
4493 | ||
4494 | id = scaler_state->scaler_id; | |
4495 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4496 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4497 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4498 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4499 | ||
4500 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4501 | } |
4502 | } | |
4503 | ||
b074cec8 JB |
4504 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4505 | { | |
4506 | struct drm_device *dev = crtc->base.dev; | |
4507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4508 | int pipe = crtc->pipe; | |
4509 | ||
6e3c9717 | 4510 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4511 | /* Force use of hard-coded filter coefficients |
4512 | * as some pre-programmed values are broken, | |
4513 | * e.g. x201. | |
4514 | */ | |
4515 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4516 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4517 | PF_PIPE_SEL_IVB(pipe)); | |
4518 | else | |
4519 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4520 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4521 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4522 | } |
4523 | } | |
4524 | ||
20bc8673 | 4525 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4526 | { |
cea165c3 VS |
4527 | struct drm_device *dev = crtc->base.dev; |
4528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4529 | |
6e3c9717 | 4530 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4531 | return; |
4532 | ||
cea165c3 VS |
4533 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4534 | intel_wait_for_vblank(dev, crtc->pipe); | |
4535 | ||
d77e4531 | 4536 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4537 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4538 | mutex_lock(&dev_priv->rps.hw_lock); |
4539 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4540 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4541 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4542 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4543 | * mailbox." Moreover, the mailbox may return a bogus state, |
4544 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4545 | */ |
4546 | } else { | |
4547 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4548 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4549 | * is essentially intel_wait_for_vblank. If we don't have this | |
4550 | * and don't wait for vblanks until the end of crtc_enable, then | |
4551 | * the HW state readout code will complain that the expected | |
4552 | * IPS_CTL value is not the one we read. */ | |
4553 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4554 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4555 | } | |
d77e4531 PZ |
4556 | } |
4557 | ||
20bc8673 | 4558 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4559 | { |
4560 | struct drm_device *dev = crtc->base.dev; | |
4561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4562 | ||
6e3c9717 | 4563 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4564 | return; |
4565 | ||
4566 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4567 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4568 | mutex_lock(&dev_priv->rps.hw_lock); |
4569 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4570 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4571 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4572 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4573 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4574 | } else { |
2a114cc1 | 4575 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4576 | POSTING_READ(IPS_CTL); |
4577 | } | |
d77e4531 PZ |
4578 | |
4579 | /* We need to wait for a vblank before we can disable the plane. */ | |
4580 | intel_wait_for_vblank(dev, crtc->pipe); | |
4581 | } | |
4582 | ||
4583 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4584 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4585 | { | |
4586 | struct drm_device *dev = crtc->dev; | |
4587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4589 | enum pipe pipe = intel_crtc->pipe; | |
4590 | int palreg = PALETTE(pipe); | |
4591 | int i; | |
4592 | bool reenable_ips = false; | |
4593 | ||
4594 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4595 | if (!crtc->state->active) |
d77e4531 PZ |
4596 | return; |
4597 | ||
50360403 | 4598 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4599 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4600 | assert_dsi_pll_enabled(dev_priv); |
4601 | else | |
4602 | assert_pll_enabled(dev_priv, pipe); | |
4603 | } | |
4604 | ||
4605 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4606 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4607 | palreg = LGC_PALETTE(pipe); |
4608 | ||
4609 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4610 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4611 | */ | |
6e3c9717 | 4612 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4613 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4614 | GAMMA_MODE_MODE_SPLIT)) { | |
4615 | hsw_disable_ips(intel_crtc); | |
4616 | reenable_ips = true; | |
4617 | } | |
4618 | ||
4619 | for (i = 0; i < 256; i++) { | |
4620 | I915_WRITE(palreg + 4 * i, | |
4621 | (intel_crtc->lut_r[i] << 16) | | |
4622 | (intel_crtc->lut_g[i] << 8) | | |
4623 | intel_crtc->lut_b[i]); | |
4624 | } | |
4625 | ||
4626 | if (reenable_ips) | |
4627 | hsw_enable_ips(intel_crtc); | |
4628 | } | |
4629 | ||
7cac945f | 4630 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4631 | { |
7cac945f | 4632 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4633 | struct drm_device *dev = intel_crtc->base.dev; |
4634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4635 | ||
4636 | mutex_lock(&dev->struct_mutex); | |
4637 | dev_priv->mm.interruptible = false; | |
4638 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4639 | dev_priv->mm.interruptible = true; | |
4640 | mutex_unlock(&dev->struct_mutex); | |
4641 | } | |
4642 | ||
4643 | /* Let userspace switch the overlay on again. In most cases userspace | |
4644 | * has to recompute where to put it anyway. | |
4645 | */ | |
4646 | } | |
4647 | ||
87d4300a ML |
4648 | /** |
4649 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4650 | * @crtc: the CRTC whose primary plane was just enabled | |
4651 | * | |
4652 | * Performs potentially sleeping operations that must be done after the primary | |
4653 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4654 | * called due to an explicit primary plane update, or due to an implicit | |
4655 | * re-enable that is caused when a sprite plane is updated to no longer | |
4656 | * completely hide the primary plane. | |
4657 | */ | |
4658 | static void | |
4659 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4660 | { |
4661 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4662 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4664 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4665 | |
87d4300a ML |
4666 | /* |
4667 | * BDW signals flip done immediately if the plane | |
4668 | * is disabled, even if the plane enable is already | |
4669 | * armed to occur at the next vblank :( | |
4670 | */ | |
4671 | if (IS_BROADWELL(dev)) | |
4672 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4673 | |
87d4300a ML |
4674 | /* |
4675 | * FIXME IPS should be fine as long as one plane is | |
4676 | * enabled, but in practice it seems to have problems | |
4677 | * when going from primary only to sprite only and vice | |
4678 | * versa. | |
4679 | */ | |
a5c4d7bc VS |
4680 | hsw_enable_ips(intel_crtc); |
4681 | ||
f99d7069 | 4682 | /* |
87d4300a ML |
4683 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4684 | * So don't enable underrun reporting before at least some planes | |
4685 | * are enabled. | |
4686 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4687 | * but leave the pipe running. | |
f99d7069 | 4688 | */ |
87d4300a ML |
4689 | if (IS_GEN2(dev)) |
4690 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4691 | ||
4692 | /* Underruns don't raise interrupts, so check manually. */ | |
4693 | if (HAS_GMCH_DISPLAY(dev)) | |
4694 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4695 | } |
4696 | ||
87d4300a ML |
4697 | /** |
4698 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4699 | * @crtc: the CRTC whose primary plane is to be disabled | |
4700 | * | |
4701 | * Performs potentially sleeping operations that must be done before the | |
4702 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4703 | * be called due to an explicit primary plane update, or due to an implicit | |
4704 | * disable that is caused when a sprite plane completely hides the primary | |
4705 | * plane. | |
4706 | */ | |
4707 | static void | |
4708 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4709 | { |
4710 | struct drm_device *dev = crtc->dev; | |
4711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4713 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4714 | |
87d4300a ML |
4715 | /* |
4716 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4717 | * So diasble underrun reporting before all the planes get disabled. | |
4718 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4719 | * but leave the pipe running. | |
4720 | */ | |
4721 | if (IS_GEN2(dev)) | |
4722 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4723 | |
87d4300a ML |
4724 | /* |
4725 | * Vblank time updates from the shadow to live plane control register | |
4726 | * are blocked if the memory self-refresh mode is active at that | |
4727 | * moment. So to make sure the plane gets truly disabled, disable | |
4728 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4729 | * will be checked/applied by the HW only at the next frame start | |
4730 | * event which is after the vblank start event, so we need to have a | |
4731 | * wait-for-vblank between disabling the plane and the pipe. | |
4732 | */ | |
262cd2e1 | 4733 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4734 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4735 | dev_priv->wm.vlv.cxsr = false; |
4736 | intel_wait_for_vblank(dev, pipe); | |
4737 | } | |
87d4300a | 4738 | |
87d4300a ML |
4739 | /* |
4740 | * FIXME IPS should be fine as long as one plane is | |
4741 | * enabled, but in practice it seems to have problems | |
4742 | * when going from primary only to sprite only and vice | |
4743 | * versa. | |
4744 | */ | |
a5c4d7bc | 4745 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4746 | } |
4747 | ||
ac21b225 ML |
4748 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4749 | { | |
4750 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
4751 | struct drm_device *dev = crtc->base.dev; | |
7733b49b | 4752 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4753 | struct drm_plane *plane; |
4754 | ||
4755 | if (atomic->wait_vblank) | |
4756 | intel_wait_for_vblank(dev, crtc->pipe); | |
4757 | ||
4758 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4759 | ||
852eb00d VS |
4760 | if (atomic->disable_cxsr) |
4761 | crtc->wm.cxsr_allowed = true; | |
4762 | ||
f015c551 VS |
4763 | if (crtc->atomic.update_wm_post) |
4764 | intel_update_watermarks(&crtc->base); | |
4765 | ||
c80ac854 | 4766 | if (atomic->update_fbc) |
7733b49b | 4767 | intel_fbc_update(dev_priv); |
ac21b225 ML |
4768 | |
4769 | if (atomic->post_enable_primary) | |
4770 | intel_post_enable_primary(&crtc->base); | |
4771 | ||
4772 | drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) | |
4773 | intel_update_sprite_watermarks(plane, &crtc->base, | |
4774 | 0, 0, 0, false, false); | |
4775 | ||
4776 | memset(atomic, 0, sizeof(*atomic)); | |
4777 | } | |
4778 | ||
4779 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4780 | { | |
4781 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4782 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4783 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4784 | struct drm_plane *p; | |
4785 | ||
4786 | /* Track fb's for any planes being disabled */ | |
ac21b225 ML |
4787 | drm_for_each_plane_mask(p, dev, atomic->disabled_planes) { |
4788 | struct intel_plane *plane = to_intel_plane(p); | |
ac21b225 ML |
4789 | |
4790 | mutex_lock(&dev->struct_mutex); | |
a9ff8714 VS |
4791 | i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, |
4792 | plane->frontbuffer_bit); | |
ac21b225 ML |
4793 | mutex_unlock(&dev->struct_mutex); |
4794 | } | |
4795 | ||
4796 | if (atomic->wait_for_flips) | |
4797 | intel_crtc_wait_for_pending_flips(&crtc->base); | |
4798 | ||
c80ac854 | 4799 | if (atomic->disable_fbc) |
25ad93fd | 4800 | intel_fbc_disable_crtc(crtc); |
ac21b225 | 4801 | |
066cf55b RV |
4802 | if (crtc->atomic.disable_ips) |
4803 | hsw_disable_ips(crtc); | |
4804 | ||
ac21b225 ML |
4805 | if (atomic->pre_disable_primary) |
4806 | intel_pre_disable_primary(&crtc->base); | |
852eb00d VS |
4807 | |
4808 | if (atomic->disable_cxsr) { | |
4809 | crtc->wm.cxsr_allowed = false; | |
4810 | intel_set_memory_cxsr(dev_priv, false); | |
4811 | } | |
ac21b225 ML |
4812 | } |
4813 | ||
d032ffa0 | 4814 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4815 | { |
4816 | struct drm_device *dev = crtc->dev; | |
4817 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4818 | struct drm_plane *p; |
87d4300a ML |
4819 | int pipe = intel_crtc->pipe; |
4820 | ||
7cac945f | 4821 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4822 | |
d032ffa0 ML |
4823 | drm_for_each_plane_mask(p, dev, plane_mask) |
4824 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4825 | |
f99d7069 DV |
4826 | /* |
4827 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4828 | * to compute the mask of flip planes precisely. For the time being | |
4829 | * consider this a flip to a NULL plane. | |
4830 | */ | |
4831 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4832 | } |
4833 | ||
f67a559d JB |
4834 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4835 | { | |
4836 | struct drm_device *dev = crtc->dev; | |
4837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4839 | struct intel_encoder *encoder; |
f67a559d | 4840 | int pipe = intel_crtc->pipe; |
f67a559d | 4841 | |
53d9f4e9 | 4842 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4843 | return; |
4844 | ||
6e3c9717 | 4845 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4846 | intel_prepare_shared_dpll(intel_crtc); |
4847 | ||
6e3c9717 | 4848 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4849 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4850 | |
4851 | intel_set_pipe_timings(intel_crtc); | |
4852 | ||
6e3c9717 | 4853 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4854 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4855 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4856 | } |
4857 | ||
4858 | ironlake_set_pipeconf(crtc); | |
4859 | ||
f67a559d | 4860 | intel_crtc->active = true; |
8664281b | 4861 | |
a72e4c9f DV |
4862 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4863 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4864 | |
f6736a1a | 4865 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4866 | if (encoder->pre_enable) |
4867 | encoder->pre_enable(encoder); | |
f67a559d | 4868 | |
6e3c9717 | 4869 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4870 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4871 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4872 | * enabling. */ | |
88cefb6c | 4873 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4874 | } else { |
4875 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4876 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4877 | } | |
f67a559d | 4878 | |
b074cec8 | 4879 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4880 | |
9c54c0dd JB |
4881 | /* |
4882 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4883 | * clocks enabled | |
4884 | */ | |
4885 | intel_crtc_load_lut(crtc); | |
4886 | ||
f37fcc2a | 4887 | intel_update_watermarks(crtc); |
e1fdc473 | 4888 | intel_enable_pipe(intel_crtc); |
f67a559d | 4889 | |
6e3c9717 | 4890 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4891 | ironlake_pch_enable(crtc); |
c98e9dcf | 4892 | |
f9b61ff6 DV |
4893 | assert_vblank_disabled(crtc); |
4894 | drm_crtc_vblank_on(crtc); | |
4895 | ||
fa5c73b1 DV |
4896 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4897 | encoder->enable(encoder); | |
61b77ddd DV |
4898 | |
4899 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4900 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4901 | } |
4902 | ||
42db64ef PZ |
4903 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4904 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4905 | { | |
f5adf94e | 4906 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4907 | } |
4908 | ||
4f771f10 PZ |
4909 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4910 | { | |
4911 | struct drm_device *dev = crtc->dev; | |
4912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4913 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4914 | struct intel_encoder *encoder; | |
99d736a2 ML |
4915 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4916 | struct intel_crtc_state *pipe_config = | |
4917 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4918 | |
53d9f4e9 | 4919 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4920 | return; |
4921 | ||
df8ad70c DV |
4922 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4923 | intel_enable_shared_dpll(intel_crtc); | |
4924 | ||
6e3c9717 | 4925 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4926 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4927 | |
4928 | intel_set_pipe_timings(intel_crtc); | |
4929 | ||
6e3c9717 ACO |
4930 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4931 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4932 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4933 | } |
4934 | ||
6e3c9717 | 4935 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4936 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4937 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4938 | } |
4939 | ||
4940 | haswell_set_pipeconf(crtc); | |
4941 | ||
4942 | intel_set_pipe_csc(crtc); | |
4943 | ||
4f771f10 | 4944 | intel_crtc->active = true; |
8664281b | 4945 | |
a72e4c9f | 4946 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4947 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4948 | if (encoder->pre_enable) | |
4949 | encoder->pre_enable(encoder); | |
4950 | ||
6e3c9717 | 4951 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4952 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4953 | true); | |
4fe9467d ID |
4954 | dev_priv->display.fdi_link_train(crtc); |
4955 | } | |
4956 | ||
1f544388 | 4957 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4958 | |
ff6d9f55 | 4959 | if (INTEL_INFO(dev)->gen == 9) |
e435d6e5 | 4960 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4961 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 4962 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
4963 | else |
4964 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
4965 | |
4966 | /* | |
4967 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4968 | * clocks enabled | |
4969 | */ | |
4970 | intel_crtc_load_lut(crtc); | |
4971 | ||
1f544388 | 4972 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4973 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4974 | |
f37fcc2a | 4975 | intel_update_watermarks(crtc); |
e1fdc473 | 4976 | intel_enable_pipe(intel_crtc); |
42db64ef | 4977 | |
6e3c9717 | 4978 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4979 | lpt_pch_enable(crtc); |
4f771f10 | 4980 | |
6e3c9717 | 4981 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4982 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4983 | ||
f9b61ff6 DV |
4984 | assert_vblank_disabled(crtc); |
4985 | drm_crtc_vblank_on(crtc); | |
4986 | ||
8807e55b | 4987 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4988 | encoder->enable(encoder); |
8807e55b JN |
4989 | intel_opregion_notify_encoder(encoder, true); |
4990 | } | |
4f771f10 | 4991 | |
e4916946 PZ |
4992 | /* If we change the relative order between pipe/planes enabling, we need |
4993 | * to change the workaround. */ | |
99d736a2 ML |
4994 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4995 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4996 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4997 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4998 | } | |
4f771f10 PZ |
4999 | } |
5000 | ||
3f8dce3a DV |
5001 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
5002 | { | |
5003 | struct drm_device *dev = crtc->base.dev; | |
5004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5005 | int pipe = crtc->pipe; | |
5006 | ||
5007 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5008 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 5009 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5010 | I915_WRITE(PF_CTL(pipe), 0); |
5011 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5012 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5013 | } | |
5014 | } | |
5015 | ||
6be4a607 JB |
5016 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5017 | { | |
5018 | struct drm_device *dev = crtc->dev; | |
5019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5021 | struct intel_encoder *encoder; |
6be4a607 | 5022 | int pipe = intel_crtc->pipe; |
5eddb70b | 5023 | u32 reg, temp; |
b52eb4dc | 5024 | |
ea9d758d DV |
5025 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5026 | encoder->disable(encoder); | |
5027 | ||
f9b61ff6 DV |
5028 | drm_crtc_vblank_off(crtc); |
5029 | assert_vblank_disabled(crtc); | |
5030 | ||
6e3c9717 | 5031 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5032 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5033 | |
575f7ab7 | 5034 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5035 | |
3f8dce3a | 5036 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5037 | |
5a74f70a VS |
5038 | if (intel_crtc->config->has_pch_encoder) |
5039 | ironlake_fdi_disable(crtc); | |
5040 | ||
bf49ec8c DV |
5041 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5042 | if (encoder->post_disable) | |
5043 | encoder->post_disable(encoder); | |
2c07245f | 5044 | |
6e3c9717 | 5045 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5046 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5047 | |
d925c59a DV |
5048 | if (HAS_PCH_CPT(dev)) { |
5049 | /* disable TRANS_DP_CTL */ | |
5050 | reg = TRANS_DP_CTL(pipe); | |
5051 | temp = I915_READ(reg); | |
5052 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5053 | TRANS_DP_PORT_SEL_MASK); | |
5054 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5055 | I915_WRITE(reg, temp); | |
5056 | ||
5057 | /* disable DPLL_SEL */ | |
5058 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5059 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5060 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5061 | } |
e3421a18 | 5062 | |
d925c59a DV |
5063 | ironlake_fdi_pll_disable(intel_crtc); |
5064 | } | |
e4ca0612 PJ |
5065 | |
5066 | intel_crtc->active = false; | |
5067 | intel_update_watermarks(crtc); | |
6be4a607 | 5068 | } |
1b3c7a47 | 5069 | |
4f771f10 | 5070 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5071 | { |
4f771f10 PZ |
5072 | struct drm_device *dev = crtc->dev; |
5073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5074 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5075 | struct intel_encoder *encoder; |
6e3c9717 | 5076 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5077 | |
8807e55b JN |
5078 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5079 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5080 | encoder->disable(encoder); |
8807e55b | 5081 | } |
4f771f10 | 5082 | |
f9b61ff6 DV |
5083 | drm_crtc_vblank_off(crtc); |
5084 | assert_vblank_disabled(crtc); | |
5085 | ||
6e3c9717 | 5086 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5087 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5088 | false); | |
575f7ab7 | 5089 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5090 | |
6e3c9717 | 5091 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5092 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5093 | ||
ad80a810 | 5094 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5095 | |
ff6d9f55 | 5096 | if (INTEL_INFO(dev)->gen == 9) |
e435d6e5 | 5097 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5098 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5099 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5100 | else |
5101 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5102 | |
1f544388 | 5103 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5104 | |
6e3c9717 | 5105 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5106 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5107 | intel_ddi_fdi_disable(crtc); |
83616634 | 5108 | } |
4f771f10 | 5109 | |
97b040aa ID |
5110 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5111 | if (encoder->post_disable) | |
5112 | encoder->post_disable(encoder); | |
e4ca0612 PJ |
5113 | |
5114 | intel_crtc->active = false; | |
5115 | intel_update_watermarks(crtc); | |
4f771f10 PZ |
5116 | } |
5117 | ||
2dd24552 JB |
5118 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5119 | { | |
5120 | struct drm_device *dev = crtc->base.dev; | |
5121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5122 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5123 | |
681a8504 | 5124 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5125 | return; |
5126 | ||
2dd24552 | 5127 | /* |
c0b03411 DV |
5128 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5129 | * according to register description and PRM. | |
2dd24552 | 5130 | */ |
c0b03411 DV |
5131 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5132 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5133 | |
b074cec8 JB |
5134 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5135 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5136 | |
5137 | /* Border color in case we don't scale up to the full screen. Black by | |
5138 | * default, change to something else for debugging. */ | |
5139 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5140 | } |
5141 | ||
d05410f9 DA |
5142 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5143 | { | |
5144 | switch (port) { | |
5145 | case PORT_A: | |
5146 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5147 | case PORT_B: | |
5148 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5149 | case PORT_C: | |
5150 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5151 | case PORT_D: | |
5152 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5153 | default: | |
5154 | WARN_ON_ONCE(1); | |
5155 | return POWER_DOMAIN_PORT_OTHER; | |
5156 | } | |
5157 | } | |
5158 | ||
77d22dca ID |
5159 | #define for_each_power_domain(domain, mask) \ |
5160 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5161 | if ((1 << (domain)) & (mask)) | |
5162 | ||
319be8ae ID |
5163 | enum intel_display_power_domain |
5164 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5165 | { | |
5166 | struct drm_device *dev = intel_encoder->base.dev; | |
5167 | struct intel_digital_port *intel_dig_port; | |
5168 | ||
5169 | switch (intel_encoder->type) { | |
5170 | case INTEL_OUTPUT_UNKNOWN: | |
5171 | /* Only DDI platforms should ever use this output type */ | |
5172 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5173 | case INTEL_OUTPUT_DISPLAYPORT: | |
5174 | case INTEL_OUTPUT_HDMI: | |
5175 | case INTEL_OUTPUT_EDP: | |
5176 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5177 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5178 | case INTEL_OUTPUT_DP_MST: |
5179 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5180 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5181 | case INTEL_OUTPUT_ANALOG: |
5182 | return POWER_DOMAIN_PORT_CRT; | |
5183 | case INTEL_OUTPUT_DSI: | |
5184 | return POWER_DOMAIN_PORT_DSI; | |
5185 | default: | |
5186 | return POWER_DOMAIN_PORT_OTHER; | |
5187 | } | |
5188 | } | |
5189 | ||
5190 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5191 | { |
319be8ae ID |
5192 | struct drm_device *dev = crtc->dev; |
5193 | struct intel_encoder *intel_encoder; | |
5194 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5195 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5196 | unsigned long mask; |
5197 | enum transcoder transcoder; | |
5198 | ||
292b990e ML |
5199 | if (!crtc->state->active) |
5200 | return 0; | |
5201 | ||
77d22dca ID |
5202 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
5203 | ||
5204 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5205 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5206 | if (intel_crtc->config->pch_pfit.enabled || |
5207 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5208 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5209 | ||
319be8ae ID |
5210 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5211 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5212 | ||
77d22dca ID |
5213 | return mask; |
5214 | } | |
5215 | ||
292b990e | 5216 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5217 | { |
292b990e ML |
5218 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5220 | enum intel_display_power_domain domain; | |
5221 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5222 | |
292b990e ML |
5223 | old_domains = intel_crtc->enabled_power_domains; |
5224 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5225 | |
292b990e ML |
5226 | domains = new_domains & ~old_domains; |
5227 | ||
5228 | for_each_power_domain(domain, domains) | |
5229 | intel_display_power_get(dev_priv, domain); | |
5230 | ||
5231 | return old_domains & ~new_domains; | |
5232 | } | |
5233 | ||
5234 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5235 | unsigned long domains) | |
5236 | { | |
5237 | enum intel_display_power_domain domain; | |
5238 | ||
5239 | for_each_power_domain(domain, domains) | |
5240 | intel_display_power_put(dev_priv, domain); | |
5241 | } | |
77d22dca | 5242 | |
292b990e ML |
5243 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5244 | { | |
5245 | struct drm_device *dev = state->dev; | |
5246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5247 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5248 | struct drm_crtc_state *crtc_state; | |
5249 | struct drm_crtc *crtc; | |
5250 | int i; | |
77d22dca | 5251 | |
292b990e ML |
5252 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5253 | if (needs_modeset(crtc->state)) | |
5254 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5255 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5256 | } |
5257 | ||
27c329ed ML |
5258 | if (dev_priv->display.modeset_commit_cdclk) { |
5259 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; | |
5260 | ||
5261 | if (cdclk != dev_priv->cdclk_freq && | |
5262 | !WARN_ON(!state->allow_modeset)) | |
5263 | dev_priv->display.modeset_commit_cdclk(state); | |
5264 | } | |
50f6e502 | 5265 | |
292b990e ML |
5266 | for (i = 0; i < I915_MAX_PIPES; i++) |
5267 | if (put_domains[i]) | |
5268 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5269 | } |
5270 | ||
560a7ae4 DL |
5271 | static void intel_update_max_cdclk(struct drm_device *dev) |
5272 | { | |
5273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5274 | ||
5275 | if (IS_SKYLAKE(dev)) { | |
5276 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
5277 | ||
5278 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5279 | dev_priv->max_cdclk_freq = 675000; | |
5280 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5281 | dev_priv->max_cdclk_freq = 540000; | |
5282 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5283 | dev_priv->max_cdclk_freq = 450000; | |
5284 | else | |
5285 | dev_priv->max_cdclk_freq = 337500; | |
5286 | } else if (IS_BROADWELL(dev)) { | |
5287 | /* | |
5288 | * FIXME with extra cooling we can allow | |
5289 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5290 | * How can we know if extra cooling is | |
5291 | * available? PCI ID, VTB, something else? | |
5292 | */ | |
5293 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5294 | dev_priv->max_cdclk_freq = 450000; | |
5295 | else if (IS_BDW_ULX(dev)) | |
5296 | dev_priv->max_cdclk_freq = 450000; | |
5297 | else if (IS_BDW_ULT(dev)) | |
5298 | dev_priv->max_cdclk_freq = 540000; | |
5299 | else | |
5300 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5301 | } else if (IS_CHERRYVIEW(dev)) { |
5302 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5303 | } else if (IS_VALLEYVIEW(dev)) { |
5304 | dev_priv->max_cdclk_freq = 400000; | |
5305 | } else { | |
5306 | /* otherwise assume cdclk is fixed */ | |
5307 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5308 | } | |
5309 | ||
5310 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
5311 | dev_priv->max_cdclk_freq); | |
5312 | } | |
5313 | ||
5314 | static void intel_update_cdclk(struct drm_device *dev) | |
5315 | { | |
5316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5317 | ||
5318 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5319 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5320 | dev_priv->cdclk_freq); | |
5321 | ||
5322 | /* | |
5323 | * Program the gmbus_freq based on the cdclk frequency. | |
5324 | * BSpec erroneously claims we should aim for 4MHz, but | |
5325 | * in fact 1MHz is the correct frequency. | |
5326 | */ | |
5327 | if (IS_VALLEYVIEW(dev)) { | |
5328 | /* | |
5329 | * Program the gmbus_freq based on the cdclk frequency. | |
5330 | * BSpec erroneously claims we should aim for 4MHz, but | |
5331 | * in fact 1MHz is the correct frequency. | |
5332 | */ | |
5333 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5334 | } | |
5335 | ||
5336 | if (dev_priv->max_cdclk_freq == 0) | |
5337 | intel_update_max_cdclk(dev); | |
5338 | } | |
5339 | ||
70d0c574 | 5340 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5341 | { |
5342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5343 | uint32_t divider; | |
5344 | uint32_t ratio; | |
5345 | uint32_t current_freq; | |
5346 | int ret; | |
5347 | ||
5348 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5349 | switch (frequency) { | |
5350 | case 144000: | |
5351 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5352 | ratio = BXT_DE_PLL_RATIO(60); | |
5353 | break; | |
5354 | case 288000: | |
5355 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5356 | ratio = BXT_DE_PLL_RATIO(60); | |
5357 | break; | |
5358 | case 384000: | |
5359 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5360 | ratio = BXT_DE_PLL_RATIO(60); | |
5361 | break; | |
5362 | case 576000: | |
5363 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5364 | ratio = BXT_DE_PLL_RATIO(60); | |
5365 | break; | |
5366 | case 624000: | |
5367 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5368 | ratio = BXT_DE_PLL_RATIO(65); | |
5369 | break; | |
5370 | case 19200: | |
5371 | /* | |
5372 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5373 | * to suppress GCC warning. | |
5374 | */ | |
5375 | ratio = 0; | |
5376 | divider = 0; | |
5377 | break; | |
5378 | default: | |
5379 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5380 | ||
5381 | return; | |
5382 | } | |
5383 | ||
5384 | mutex_lock(&dev_priv->rps.hw_lock); | |
5385 | /* Inform power controller of upcoming frequency change */ | |
5386 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5387 | 0x80000000); | |
5388 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5389 | ||
5390 | if (ret) { | |
5391 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5392 | ret, frequency); | |
5393 | return; | |
5394 | } | |
5395 | ||
5396 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5397 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5398 | current_freq = current_freq * 500 + 1000; | |
5399 | ||
5400 | /* | |
5401 | * DE PLL has to be disabled when | |
5402 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5403 | * - before setting to 624MHz (PLL needs toggling) | |
5404 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5405 | */ | |
5406 | if (frequency == 19200 || frequency == 624000 || | |
5407 | current_freq == 624000) { | |
5408 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5409 | /* Timeout 200us */ | |
5410 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5411 | 1)) | |
5412 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5413 | } | |
5414 | ||
5415 | if (frequency != 19200) { | |
5416 | uint32_t val; | |
5417 | ||
5418 | val = I915_READ(BXT_DE_PLL_CTL); | |
5419 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5420 | val |= ratio; | |
5421 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5422 | ||
5423 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5424 | /* Timeout 200us */ | |
5425 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5426 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5427 | ||
5428 | val = I915_READ(CDCLK_CTL); | |
5429 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5430 | val |= divider; | |
5431 | /* | |
5432 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5433 | * enable otherwise. | |
5434 | */ | |
5435 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5436 | if (frequency >= 500000) | |
5437 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5438 | ||
5439 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5440 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5441 | val |= (frequency - 1000) / 500; | |
5442 | I915_WRITE(CDCLK_CTL, val); | |
5443 | } | |
5444 | ||
5445 | mutex_lock(&dev_priv->rps.hw_lock); | |
5446 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5447 | DIV_ROUND_UP(frequency, 25000)); | |
5448 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5449 | ||
5450 | if (ret) { | |
5451 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5452 | ret, frequency); | |
5453 | return; | |
5454 | } | |
5455 | ||
a47871bd | 5456 | intel_update_cdclk(dev); |
f8437dd1 VK |
5457 | } |
5458 | ||
5459 | void broxton_init_cdclk(struct drm_device *dev) | |
5460 | { | |
5461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5462 | uint32_t val; | |
5463 | ||
5464 | /* | |
5465 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5466 | * or else the reset will hang because there is no PCH to respond. | |
5467 | * Move the handshake programming to initialization sequence. | |
5468 | * Previously was left up to BIOS. | |
5469 | */ | |
5470 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5471 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5472 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5473 | ||
5474 | /* Enable PG1 for cdclk */ | |
5475 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5476 | ||
5477 | /* check if cd clock is enabled */ | |
5478 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5479 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5480 | return; | |
5481 | } | |
5482 | ||
5483 | /* | |
5484 | * FIXME: | |
5485 | * - The initial CDCLK needs to be read from VBT. | |
5486 | * Need to make this change after VBT has changes for BXT. | |
5487 | * - check if setting the max (or any) cdclk freq is really necessary | |
5488 | * here, it belongs to modeset time | |
5489 | */ | |
5490 | broxton_set_cdclk(dev, 624000); | |
5491 | ||
5492 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5493 | POSTING_READ(DBUF_CTL); |
5494 | ||
f8437dd1 VK |
5495 | udelay(10); |
5496 | ||
5497 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5498 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5499 | } | |
5500 | ||
5501 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5502 | { | |
5503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5504 | ||
5505 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5506 | POSTING_READ(DBUF_CTL); |
5507 | ||
f8437dd1 VK |
5508 | udelay(10); |
5509 | ||
5510 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5511 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5512 | ||
5513 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5514 | broxton_set_cdclk(dev, 19200); | |
5515 | ||
5516 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5517 | } | |
5518 | ||
5d96d8af DL |
5519 | static const struct skl_cdclk_entry { |
5520 | unsigned int freq; | |
5521 | unsigned int vco; | |
5522 | } skl_cdclk_frequencies[] = { | |
5523 | { .freq = 308570, .vco = 8640 }, | |
5524 | { .freq = 337500, .vco = 8100 }, | |
5525 | { .freq = 432000, .vco = 8640 }, | |
5526 | { .freq = 450000, .vco = 8100 }, | |
5527 | { .freq = 540000, .vco = 8100 }, | |
5528 | { .freq = 617140, .vco = 8640 }, | |
5529 | { .freq = 675000, .vco = 8100 }, | |
5530 | }; | |
5531 | ||
5532 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5533 | { | |
5534 | return (freq - 1000) / 500; | |
5535 | } | |
5536 | ||
5537 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5538 | { | |
5539 | unsigned int i; | |
5540 | ||
5541 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5542 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5543 | ||
5544 | if (e->freq == freq) | |
5545 | return e->vco; | |
5546 | } | |
5547 | ||
5548 | return 8100; | |
5549 | } | |
5550 | ||
5551 | static void | |
5552 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5553 | { | |
5554 | unsigned int min_freq; | |
5555 | u32 val; | |
5556 | ||
5557 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5558 | val = I915_READ(CDCLK_CTL); | |
5559 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5560 | val |= CDCLK_FREQ_337_308; | |
5561 | ||
5562 | if (required_vco == 8640) | |
5563 | min_freq = 308570; | |
5564 | else | |
5565 | min_freq = 337500; | |
5566 | ||
5567 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5568 | ||
5569 | I915_WRITE(CDCLK_CTL, val); | |
5570 | POSTING_READ(CDCLK_CTL); | |
5571 | ||
5572 | /* | |
5573 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5574 | * taking into account the VCO required to operate the eDP panel at the | |
5575 | * desired frequency. The usual DP link rates operate with a VCO of | |
5576 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5577 | * The modeset code is responsible for the selection of the exact link | |
5578 | * rate later on, with the constraint of choosing a frequency that | |
5579 | * works with required_vco. | |
5580 | */ | |
5581 | val = I915_READ(DPLL_CTRL1); | |
5582 | ||
5583 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5584 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5585 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5586 | if (required_vco == 8640) | |
5587 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5588 | SKL_DPLL0); | |
5589 | else | |
5590 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5591 | SKL_DPLL0); | |
5592 | ||
5593 | I915_WRITE(DPLL_CTRL1, val); | |
5594 | POSTING_READ(DPLL_CTRL1); | |
5595 | ||
5596 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5597 | ||
5598 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5599 | DRM_ERROR("DPLL0 not locked\n"); | |
5600 | } | |
5601 | ||
5602 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5603 | { | |
5604 | int ret; | |
5605 | u32 val; | |
5606 | ||
5607 | /* inform PCU we want to change CDCLK */ | |
5608 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5609 | mutex_lock(&dev_priv->rps.hw_lock); | |
5610 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5611 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5612 | ||
5613 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5614 | } | |
5615 | ||
5616 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5617 | { | |
5618 | unsigned int i; | |
5619 | ||
5620 | for (i = 0; i < 15; i++) { | |
5621 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5622 | return true; | |
5623 | udelay(10); | |
5624 | } | |
5625 | ||
5626 | return false; | |
5627 | } | |
5628 | ||
5629 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5630 | { | |
560a7ae4 | 5631 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5632 | u32 freq_select, pcu_ack; |
5633 | ||
5634 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5635 | ||
5636 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5637 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5638 | return; | |
5639 | } | |
5640 | ||
5641 | /* set CDCLK_CTL */ | |
5642 | switch(freq) { | |
5643 | case 450000: | |
5644 | case 432000: | |
5645 | freq_select = CDCLK_FREQ_450_432; | |
5646 | pcu_ack = 1; | |
5647 | break; | |
5648 | case 540000: | |
5649 | freq_select = CDCLK_FREQ_540; | |
5650 | pcu_ack = 2; | |
5651 | break; | |
5652 | case 308570: | |
5653 | case 337500: | |
5654 | default: | |
5655 | freq_select = CDCLK_FREQ_337_308; | |
5656 | pcu_ack = 0; | |
5657 | break; | |
5658 | case 617140: | |
5659 | case 675000: | |
5660 | freq_select = CDCLK_FREQ_675_617; | |
5661 | pcu_ack = 3; | |
5662 | break; | |
5663 | } | |
5664 | ||
5665 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5666 | POSTING_READ(CDCLK_CTL); | |
5667 | ||
5668 | /* inform PCU of the change */ | |
5669 | mutex_lock(&dev_priv->rps.hw_lock); | |
5670 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5671 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5672 | |
5673 | intel_update_cdclk(dev); | |
5d96d8af DL |
5674 | } |
5675 | ||
5676 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5677 | { | |
5678 | /* disable DBUF power */ | |
5679 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5680 | POSTING_READ(DBUF_CTL); | |
5681 | ||
5682 | udelay(10); | |
5683 | ||
5684 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5685 | DRM_ERROR("DBuf power disable timeout\n"); | |
5686 | ||
5687 | /* disable DPLL0 */ | |
5688 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5689 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5690 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5691 | ||
5692 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5693 | } | |
5694 | ||
5695 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5696 | { | |
5697 | u32 val; | |
5698 | unsigned int required_vco; | |
5699 | ||
5700 | /* enable PCH reset handshake */ | |
5701 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5702 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
5703 | ||
5704 | /* enable PG1 and Misc I/O */ | |
5705 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5706 | ||
5707 | /* DPLL0 already enabed !? */ | |
5708 | if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { | |
5709 | DRM_DEBUG_DRIVER("DPLL0 already running\n"); | |
5710 | return; | |
5711 | } | |
5712 | ||
5713 | /* enable DPLL0 */ | |
5714 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5715 | skl_dpll0_enable(dev_priv, required_vco); | |
5716 | ||
5717 | /* set CDCLK to the frequency the BIOS chose */ | |
5718 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5719 | ||
5720 | /* enable DBUF power */ | |
5721 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5722 | POSTING_READ(DBUF_CTL); | |
5723 | ||
5724 | udelay(10); | |
5725 | ||
5726 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5727 | DRM_ERROR("DBuf power enable timeout\n"); | |
5728 | } | |
5729 | ||
dfcab17e | 5730 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5731 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5732 | { |
586f49dc | 5733 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5734 | |
586f49dc | 5735 | /* Obtain SKU information */ |
a580516d | 5736 | mutex_lock(&dev_priv->sb_lock); |
586f49dc JB |
5737 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
5738 | CCK_FUSE_HPLL_FREQ_MASK; | |
a580516d | 5739 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5740 | |
dfcab17e | 5741 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5742 | } |
5743 | ||
5744 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
5745 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5746 | { | |
5747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5748 | u32 val, cmd; | |
5749 | ||
164dfd28 VK |
5750 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5751 | != dev_priv->cdclk_freq); | |
d60c4473 | 5752 | |
dfcab17e | 5753 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5754 | cmd = 2; |
dfcab17e | 5755 | else if (cdclk == 266667) |
30a970c6 JB |
5756 | cmd = 1; |
5757 | else | |
5758 | cmd = 0; | |
5759 | ||
5760 | mutex_lock(&dev_priv->rps.hw_lock); | |
5761 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5762 | val &= ~DSPFREQGUAR_MASK; | |
5763 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5764 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5765 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5766 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5767 | 50)) { | |
5768 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5769 | } | |
5770 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5771 | ||
54433e91 VS |
5772 | mutex_lock(&dev_priv->sb_lock); |
5773 | ||
dfcab17e | 5774 | if (cdclk == 400000) { |
6bcda4f0 | 5775 | u32 divider; |
30a970c6 | 5776 | |
6bcda4f0 | 5777 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5778 | |
30a970c6 JB |
5779 | /* adjust cdclk divider */ |
5780 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5781 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5782 | val |= divider; |
5783 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5784 | |
5785 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5786 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5787 | 50)) | |
5788 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5789 | } |
5790 | ||
30a970c6 JB |
5791 | /* adjust self-refresh exit latency value */ |
5792 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5793 | val &= ~0x7f; | |
5794 | ||
5795 | /* | |
5796 | * For high bandwidth configs, we set a higher latency in the bunit | |
5797 | * so that the core display fetch happens in time to avoid underruns. | |
5798 | */ | |
dfcab17e | 5799 | if (cdclk == 400000) |
30a970c6 JB |
5800 | val |= 4500 / 250; /* 4.5 usec */ |
5801 | else | |
5802 | val |= 3000 / 250; /* 3.0 usec */ | |
5803 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5804 | |
a580516d | 5805 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5806 | |
b6283055 | 5807 | intel_update_cdclk(dev); |
30a970c6 JB |
5808 | } |
5809 | ||
383c5a6a VS |
5810 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5811 | { | |
5812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5813 | u32 val, cmd; | |
5814 | ||
164dfd28 VK |
5815 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5816 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5817 | |
5818 | switch (cdclk) { | |
383c5a6a VS |
5819 | case 333333: |
5820 | case 320000: | |
383c5a6a | 5821 | case 266667: |
383c5a6a | 5822 | case 200000: |
383c5a6a VS |
5823 | break; |
5824 | default: | |
5f77eeb0 | 5825 | MISSING_CASE(cdclk); |
383c5a6a VS |
5826 | return; |
5827 | } | |
5828 | ||
9d0d3fda VS |
5829 | /* |
5830 | * Specs are full of misinformation, but testing on actual | |
5831 | * hardware has shown that we just need to write the desired | |
5832 | * CCK divider into the Punit register. | |
5833 | */ | |
5834 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5835 | ||
383c5a6a VS |
5836 | mutex_lock(&dev_priv->rps.hw_lock); |
5837 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5838 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5839 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5840 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5841 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5842 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5843 | 50)) { | |
5844 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5845 | } | |
5846 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5847 | ||
b6283055 | 5848 | intel_update_cdclk(dev); |
383c5a6a VS |
5849 | } |
5850 | ||
30a970c6 JB |
5851 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5852 | int max_pixclk) | |
5853 | { | |
6bcda4f0 | 5854 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5855 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5856 | |
30a970c6 JB |
5857 | /* |
5858 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5859 | * 200MHz | |
5860 | * 267MHz | |
29dc7ef3 | 5861 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5862 | * 400MHz (VLV only) |
5863 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5864 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5865 | * |
5866 | * We seem to get an unstable or solid color picture at 200MHz. | |
5867 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5868 | * are off. | |
30a970c6 | 5869 | */ |
6cca3195 VS |
5870 | if (!IS_CHERRYVIEW(dev_priv) && |
5871 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5872 | return 400000; |
6cca3195 | 5873 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5874 | return freq_320; |
e37c67a1 | 5875 | else if (max_pixclk > 0) |
dfcab17e | 5876 | return 266667; |
e37c67a1 VS |
5877 | else |
5878 | return 200000; | |
30a970c6 JB |
5879 | } |
5880 | ||
f8437dd1 VK |
5881 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5882 | int max_pixclk) | |
5883 | { | |
5884 | /* | |
5885 | * FIXME: | |
5886 | * - remove the guardband, it's not needed on BXT | |
5887 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5888 | */ | |
5889 | if (max_pixclk > 576000*9/10) | |
5890 | return 624000; | |
5891 | else if (max_pixclk > 384000*9/10) | |
5892 | return 576000; | |
5893 | else if (max_pixclk > 288000*9/10) | |
5894 | return 384000; | |
5895 | else if (max_pixclk > 144000*9/10) | |
5896 | return 288000; | |
5897 | else | |
5898 | return 144000; | |
5899 | } | |
5900 | ||
a821fc46 ACO |
5901 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5902 | * that's non-NULL, look at current state otherwise. */ | |
5903 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5904 | struct drm_atomic_state *state) | |
30a970c6 | 5905 | { |
30a970c6 | 5906 | struct intel_crtc *intel_crtc; |
304603f4 | 5907 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5908 | int max_pixclk = 0; |
5909 | ||
d3fcc808 | 5910 | for_each_intel_crtc(dev, intel_crtc) { |
27c329ed | 5911 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
304603f4 ACO |
5912 | if (IS_ERR(crtc_state)) |
5913 | return PTR_ERR(crtc_state); | |
5914 | ||
5915 | if (!crtc_state->base.enable) | |
5916 | continue; | |
5917 | ||
5918 | max_pixclk = max(max_pixclk, | |
5919 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5920 | } |
5921 | ||
5922 | return max_pixclk; | |
5923 | } | |
5924 | ||
27c329ed | 5925 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5926 | { |
27c329ed ML |
5927 | struct drm_device *dev = state->dev; |
5928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5929 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
30a970c6 | 5930 | |
304603f4 ACO |
5931 | if (max_pixclk < 0) |
5932 | return max_pixclk; | |
30a970c6 | 5933 | |
27c329ed ML |
5934 | to_intel_atomic_state(state)->cdclk = |
5935 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
0a9ab303 | 5936 | |
27c329ed ML |
5937 | return 0; |
5938 | } | |
304603f4 | 5939 | |
27c329ed ML |
5940 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5941 | { | |
5942 | struct drm_device *dev = state->dev; | |
5943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5944 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
85a96e7a | 5945 | |
27c329ed ML |
5946 | if (max_pixclk < 0) |
5947 | return max_pixclk; | |
85a96e7a | 5948 | |
27c329ed ML |
5949 | to_intel_atomic_state(state)->cdclk = |
5950 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
85a96e7a | 5951 | |
27c329ed | 5952 | return 0; |
30a970c6 JB |
5953 | } |
5954 | ||
1e69cd74 VS |
5955 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5956 | { | |
5957 | unsigned int credits, default_credits; | |
5958 | ||
5959 | if (IS_CHERRYVIEW(dev_priv)) | |
5960 | default_credits = PFI_CREDIT(12); | |
5961 | else | |
5962 | default_credits = PFI_CREDIT(8); | |
5963 | ||
164dfd28 | 5964 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5965 | /* CHV suggested value is 31 or 63 */ |
5966 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5967 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5968 | else |
5969 | credits = PFI_CREDIT(15); | |
5970 | } else { | |
5971 | credits = default_credits; | |
5972 | } | |
5973 | ||
5974 | /* | |
5975 | * WA - write default credits before re-programming | |
5976 | * FIXME: should we also set the resend bit here? | |
5977 | */ | |
5978 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5979 | default_credits); | |
5980 | ||
5981 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5982 | credits | PFI_CREDIT_RESEND); | |
5983 | ||
5984 | /* | |
5985 | * FIXME is this guaranteed to clear | |
5986 | * immediately or should we poll for it? | |
5987 | */ | |
5988 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5989 | } | |
5990 | ||
27c329ed | 5991 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 5992 | { |
a821fc46 | 5993 | struct drm_device *dev = old_state->dev; |
27c329ed | 5994 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
30a970c6 | 5995 | struct drm_i915_private *dev_priv = dev->dev_private; |
30a970c6 | 5996 | |
27c329ed ML |
5997 | /* |
5998 | * FIXME: We can end up here with all power domains off, yet | |
5999 | * with a CDCLK frequency other than the minimum. To account | |
6000 | * for this take the PIPE-A power domain, which covers the HW | |
6001 | * blocks needed for the following programming. This can be | |
6002 | * removed once it's guaranteed that we get here either with | |
6003 | * the minimum CDCLK set, or the required power domains | |
6004 | * enabled. | |
6005 | */ | |
6006 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6007 | |
27c329ed ML |
6008 | if (IS_CHERRYVIEW(dev)) |
6009 | cherryview_set_cdclk(dev, req_cdclk); | |
6010 | else | |
6011 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6012 | |
27c329ed | 6013 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6014 | |
27c329ed | 6015 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6016 | } |
6017 | ||
89b667f8 JB |
6018 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6019 | { | |
6020 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6021 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6023 | struct intel_encoder *encoder; | |
6024 | int pipe = intel_crtc->pipe; | |
23538ef1 | 6025 | bool is_dsi; |
89b667f8 | 6026 | |
53d9f4e9 | 6027 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6028 | return; |
6029 | ||
409ee761 | 6030 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 6031 | |
1ae0d137 VS |
6032 | if (!is_dsi) { |
6033 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6034 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6035 | else |
6e3c9717 | 6036 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6037 | } |
5b18e57c | 6038 | |
6e3c9717 | 6039 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6040 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6041 | |
6042 | intel_set_pipe_timings(intel_crtc); | |
6043 | ||
c14b0485 VS |
6044 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6046 | ||
6047 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6048 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6049 | } | |
6050 | ||
5b18e57c DV |
6051 | i9xx_set_pipeconf(intel_crtc); |
6052 | ||
89b667f8 | 6053 | intel_crtc->active = true; |
89b667f8 | 6054 | |
a72e4c9f | 6055 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6056 | |
89b667f8 JB |
6057 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6058 | if (encoder->pre_pll_enable) | |
6059 | encoder->pre_pll_enable(encoder); | |
6060 | ||
9d556c99 CML |
6061 | if (!is_dsi) { |
6062 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6063 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6064 | else |
6e3c9717 | 6065 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6066 | } |
89b667f8 JB |
6067 | |
6068 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6069 | if (encoder->pre_enable) | |
6070 | encoder->pre_enable(encoder); | |
6071 | ||
2dd24552 JB |
6072 | i9xx_pfit_enable(intel_crtc); |
6073 | ||
63cbb074 VS |
6074 | intel_crtc_load_lut(crtc); |
6075 | ||
e1fdc473 | 6076 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6077 | |
4b3a9526 VS |
6078 | assert_vblank_disabled(crtc); |
6079 | drm_crtc_vblank_on(crtc); | |
6080 | ||
f9b61ff6 DV |
6081 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6082 | encoder->enable(encoder); | |
89b667f8 JB |
6083 | } |
6084 | ||
f13c2ef3 DV |
6085 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6086 | { | |
6087 | struct drm_device *dev = crtc->base.dev; | |
6088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6089 | ||
6e3c9717 ACO |
6090 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6091 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6092 | } |
6093 | ||
0b8765c6 | 6094 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6095 | { |
6096 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6097 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6099 | struct intel_encoder *encoder; |
79e53945 | 6100 | int pipe = intel_crtc->pipe; |
79e53945 | 6101 | |
53d9f4e9 | 6102 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6103 | return; |
6104 | ||
f13c2ef3 DV |
6105 | i9xx_set_pll_dividers(intel_crtc); |
6106 | ||
6e3c9717 | 6107 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6108 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6109 | |
6110 | intel_set_pipe_timings(intel_crtc); | |
6111 | ||
5b18e57c DV |
6112 | i9xx_set_pipeconf(intel_crtc); |
6113 | ||
f7abfe8b | 6114 | intel_crtc->active = true; |
6b383a7f | 6115 | |
4a3436e8 | 6116 | if (!IS_GEN2(dev)) |
a72e4c9f | 6117 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6118 | |
9d6d9f19 MK |
6119 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6120 | if (encoder->pre_enable) | |
6121 | encoder->pre_enable(encoder); | |
6122 | ||
f6736a1a DV |
6123 | i9xx_enable_pll(intel_crtc); |
6124 | ||
2dd24552 JB |
6125 | i9xx_pfit_enable(intel_crtc); |
6126 | ||
63cbb074 VS |
6127 | intel_crtc_load_lut(crtc); |
6128 | ||
f37fcc2a | 6129 | intel_update_watermarks(crtc); |
e1fdc473 | 6130 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6131 | |
4b3a9526 VS |
6132 | assert_vblank_disabled(crtc); |
6133 | drm_crtc_vblank_on(crtc); | |
6134 | ||
f9b61ff6 DV |
6135 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6136 | encoder->enable(encoder); | |
0b8765c6 | 6137 | } |
79e53945 | 6138 | |
87476d63 DV |
6139 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6140 | { | |
6141 | struct drm_device *dev = crtc->base.dev; | |
6142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6143 | |
6e3c9717 | 6144 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6145 | return; |
87476d63 | 6146 | |
328d8e82 | 6147 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6148 | |
328d8e82 DV |
6149 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6150 | I915_READ(PFIT_CONTROL)); | |
6151 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6152 | } |
6153 | ||
0b8765c6 JB |
6154 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6155 | { | |
6156 | struct drm_device *dev = crtc->dev; | |
6157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6159 | struct intel_encoder *encoder; |
0b8765c6 | 6160 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6161 | |
6304cd91 VS |
6162 | /* |
6163 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6164 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6165 | * We also need to wait on all gmch platforms because of the |
6166 | * self-refresh mode constraint explained above. | |
6304cd91 | 6167 | */ |
564ed191 | 6168 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6169 | |
4b3a9526 VS |
6170 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6171 | encoder->disable(encoder); | |
6172 | ||
f9b61ff6 DV |
6173 | drm_crtc_vblank_off(crtc); |
6174 | assert_vblank_disabled(crtc); | |
6175 | ||
575f7ab7 | 6176 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6177 | |
87476d63 | 6178 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6179 | |
89b667f8 JB |
6180 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6181 | if (encoder->post_disable) | |
6182 | encoder->post_disable(encoder); | |
6183 | ||
409ee761 | 6184 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6185 | if (IS_CHERRYVIEW(dev)) |
6186 | chv_disable_pll(dev_priv, pipe); | |
6187 | else if (IS_VALLEYVIEW(dev)) | |
6188 | vlv_disable_pll(dev_priv, pipe); | |
6189 | else | |
1c4e0274 | 6190 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6191 | } |
0b8765c6 | 6192 | |
4a3436e8 | 6193 | if (!IS_GEN2(dev)) |
a72e4c9f | 6194 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
e4ca0612 PJ |
6195 | |
6196 | intel_crtc->active = false; | |
6197 | intel_update_watermarks(crtc); | |
0b8765c6 JB |
6198 | } |
6199 | ||
b17d48e2 ML |
6200 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6201 | { | |
6202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6203 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6204 | enum intel_display_power_domain domain; | |
6205 | unsigned long domains; | |
6206 | ||
6207 | if (!intel_crtc->active) | |
6208 | return; | |
6209 | ||
a539205a ML |
6210 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
6211 | intel_crtc_wait_for_pending_flips(crtc); | |
6212 | intel_pre_disable_primary(crtc); | |
6213 | } | |
6214 | ||
d032ffa0 | 6215 | intel_crtc_disable_planes(crtc, crtc->state->plane_mask); |
b17d48e2 ML |
6216 | dev_priv->display.crtc_disable(crtc); |
6217 | ||
6218 | domains = intel_crtc->enabled_power_domains; | |
6219 | for_each_power_domain(domain, domains) | |
6220 | intel_display_power_put(dev_priv, domain); | |
6221 | intel_crtc->enabled_power_domains = 0; | |
6222 | } | |
6223 | ||
6b72d486 ML |
6224 | /* |
6225 | * turn all crtc's off, but do not adjust state | |
6226 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6227 | */ | |
9716c691 | 6228 | void intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6229 | { |
6b72d486 ML |
6230 | struct drm_crtc *crtc; |
6231 | ||
b17d48e2 ML |
6232 | for_each_crtc(dev, crtc) |
6233 | intel_crtc_disable_noatomic(crtc); | |
ee7b9f93 JB |
6234 | } |
6235 | ||
b04c5bd6 | 6236 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5da76e94 | 6237 | int intel_crtc_control(struct drm_crtc *crtc, bool enable) |
976f8a20 DV |
6238 | { |
6239 | struct drm_device *dev = crtc->dev; | |
5da76e94 ML |
6240 | struct drm_mode_config *config = &dev->mode_config; |
6241 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
0e572fe7 | 6242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5da76e94 ML |
6243 | struct intel_crtc_state *pipe_config; |
6244 | struct drm_atomic_state *state; | |
6245 | int ret; | |
976f8a20 | 6246 | |
1b509259 | 6247 | if (enable == intel_crtc->active) |
5da76e94 | 6248 | return 0; |
0e572fe7 | 6249 | |
1b509259 | 6250 | if (enable && !crtc->state->enable) |
5da76e94 | 6251 | return 0; |
1b509259 | 6252 | |
5da76e94 ML |
6253 | /* this function should be called with drm_modeset_lock_all for now */ |
6254 | if (WARN_ON(!ctx)) | |
6255 | return -EIO; | |
6256 | lockdep_assert_held(&ctx->ww_ctx); | |
1b509259 | 6257 | |
5da76e94 ML |
6258 | state = drm_atomic_state_alloc(dev); |
6259 | if (WARN_ON(!state)) | |
6260 | return -ENOMEM; | |
1b509259 | 6261 | |
5da76e94 ML |
6262 | state->acquire_ctx = ctx; |
6263 | state->allow_modeset = true; | |
6264 | ||
6265 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
6266 | if (IS_ERR(pipe_config)) { | |
6267 | ret = PTR_ERR(pipe_config); | |
6268 | goto err; | |
0e572fe7 | 6269 | } |
5da76e94 ML |
6270 | pipe_config->base.active = enable; |
6271 | ||
6272 | ret = intel_set_mode(state); | |
6273 | if (!ret) | |
6274 | return ret; | |
6275 | ||
6276 | err: | |
6277 | DRM_ERROR("Updating crtc active failed with %i\n", ret); | |
6278 | drm_atomic_state_free(state); | |
6279 | return ret; | |
b04c5bd6 BF |
6280 | } |
6281 | ||
6282 | /** | |
6283 | * Sets the power management mode of the pipe and plane. | |
6284 | */ | |
6285 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6286 | { | |
6287 | struct drm_device *dev = crtc->dev; | |
6288 | struct intel_encoder *intel_encoder; | |
6289 | bool enable = false; | |
6290 | ||
6291 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6292 | enable |= intel_encoder->connectors_active; | |
6293 | ||
6294 | intel_crtc_control(crtc, enable); | |
cdd59983 CW |
6295 | } |
6296 | ||
ea5b213a | 6297 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6298 | { |
4ef69c7a | 6299 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6300 | |
ea5b213a CW |
6301 | drm_encoder_cleanup(encoder); |
6302 | kfree(intel_encoder); | |
7e7d76c3 JB |
6303 | } |
6304 | ||
9237329d | 6305 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6306 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6307 | * state of the entire output pipe. */ | |
9237329d | 6308 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6309 | { |
5ab432ef DV |
6310 | if (mode == DRM_MODE_DPMS_ON) { |
6311 | encoder->connectors_active = true; | |
6312 | ||
b2cabb0e | 6313 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6314 | } else { |
6315 | encoder->connectors_active = false; | |
6316 | ||
b2cabb0e | 6317 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6318 | } |
79e53945 JB |
6319 | } |
6320 | ||
0a91ca29 DV |
6321 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6322 | * internal consistency). */ | |
b980514c | 6323 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6324 | { |
0a91ca29 DV |
6325 | if (connector->get_hw_state(connector)) { |
6326 | struct intel_encoder *encoder = connector->encoder; | |
6327 | struct drm_crtc *crtc; | |
6328 | bool encoder_enabled; | |
6329 | enum pipe pipe; | |
6330 | ||
6331 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6332 | connector->base.base.id, | |
c23cc417 | 6333 | connector->base.name); |
0a91ca29 | 6334 | |
0e32b39c DA |
6335 | /* there is no real hw state for MST connectors */ |
6336 | if (connector->mst_port) | |
6337 | return; | |
6338 | ||
e2c719b7 | 6339 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6340 | "wrong connector dpms state\n"); |
e2c719b7 | 6341 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6342 | "active connector not linked to encoder\n"); |
0a91ca29 | 6343 | |
36cd7444 | 6344 | if (encoder) { |
e2c719b7 | 6345 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6346 | "encoder->connectors_active not set\n"); |
6347 | ||
6348 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6349 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6350 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6351 | return; |
0a91ca29 | 6352 | |
36cd7444 | 6353 | crtc = encoder->base.crtc; |
0a91ca29 | 6354 | |
83d65738 MR |
6355 | I915_STATE_WARN(!crtc->state->enable, |
6356 | "crtc not enabled\n"); | |
e2c719b7 RC |
6357 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6358 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6359 | "encoder active on the wrong pipe\n"); |
6360 | } | |
0a91ca29 | 6361 | } |
79e53945 JB |
6362 | } |
6363 | ||
08d9bc92 ACO |
6364 | int intel_connector_init(struct intel_connector *connector) |
6365 | { | |
6366 | struct drm_connector_state *connector_state; | |
6367 | ||
6368 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6369 | if (!connector_state) | |
6370 | return -ENOMEM; | |
6371 | ||
6372 | connector->base.state = connector_state; | |
6373 | return 0; | |
6374 | } | |
6375 | ||
6376 | struct intel_connector *intel_connector_alloc(void) | |
6377 | { | |
6378 | struct intel_connector *connector; | |
6379 | ||
6380 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6381 | if (!connector) | |
6382 | return NULL; | |
6383 | ||
6384 | if (intel_connector_init(connector) < 0) { | |
6385 | kfree(connector); | |
6386 | return NULL; | |
6387 | } | |
6388 | ||
6389 | return connector; | |
6390 | } | |
6391 | ||
5ab432ef DV |
6392 | /* Even simpler default implementation, if there's really no special case to |
6393 | * consider. */ | |
6394 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6395 | { |
5ab432ef DV |
6396 | /* All the simple cases only support two dpms states. */ |
6397 | if (mode != DRM_MODE_DPMS_ON) | |
6398 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6399 | |
5ab432ef DV |
6400 | if (mode == connector->dpms) |
6401 | return; | |
6402 | ||
6403 | connector->dpms = mode; | |
6404 | ||
6405 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6406 | if (connector->encoder) |
6407 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6408 | |
b980514c | 6409 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6410 | } |
6411 | ||
f0947c37 DV |
6412 | /* Simple connector->get_hw_state implementation for encoders that support only |
6413 | * one connector and no cloning and hence the encoder state determines the state | |
6414 | * of the connector. */ | |
6415 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6416 | { |
24929352 | 6417 | enum pipe pipe = 0; |
f0947c37 | 6418 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6419 | |
f0947c37 | 6420 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6421 | } |
6422 | ||
6d293983 | 6423 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6424 | { |
6d293983 ACO |
6425 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6426 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6427 | |
6428 | return 0; | |
6429 | } | |
6430 | ||
6d293983 | 6431 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6432 | struct intel_crtc_state *pipe_config) |
1857e1da | 6433 | { |
6d293983 ACO |
6434 | struct drm_atomic_state *state = pipe_config->base.state; |
6435 | struct intel_crtc *other_crtc; | |
6436 | struct intel_crtc_state *other_crtc_state; | |
6437 | ||
1857e1da DV |
6438 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6439 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6440 | if (pipe_config->fdi_lanes > 4) { | |
6441 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6442 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6443 | return -EINVAL; |
1857e1da DV |
6444 | } |
6445 | ||
bafb6553 | 6446 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6447 | if (pipe_config->fdi_lanes > 2) { |
6448 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6449 | pipe_config->fdi_lanes); | |
6d293983 | 6450 | return -EINVAL; |
1857e1da | 6451 | } else { |
6d293983 | 6452 | return 0; |
1857e1da DV |
6453 | } |
6454 | } | |
6455 | ||
6456 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6457 | return 0; |
1857e1da DV |
6458 | |
6459 | /* Ivybridge 3 pipe is really complicated */ | |
6460 | switch (pipe) { | |
6461 | case PIPE_A: | |
6d293983 | 6462 | return 0; |
1857e1da | 6463 | case PIPE_B: |
6d293983 ACO |
6464 | if (pipe_config->fdi_lanes <= 2) |
6465 | return 0; | |
6466 | ||
6467 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6468 | other_crtc_state = | |
6469 | intel_atomic_get_crtc_state(state, other_crtc); | |
6470 | if (IS_ERR(other_crtc_state)) | |
6471 | return PTR_ERR(other_crtc_state); | |
6472 | ||
6473 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6474 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6475 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6476 | return -EINVAL; |
1857e1da | 6477 | } |
6d293983 | 6478 | return 0; |
1857e1da | 6479 | case PIPE_C: |
251cc67c VS |
6480 | if (pipe_config->fdi_lanes > 2) { |
6481 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6482 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6483 | return -EINVAL; |
251cc67c | 6484 | } |
6d293983 ACO |
6485 | |
6486 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6487 | other_crtc_state = | |
6488 | intel_atomic_get_crtc_state(state, other_crtc); | |
6489 | if (IS_ERR(other_crtc_state)) | |
6490 | return PTR_ERR(other_crtc_state); | |
6491 | ||
6492 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6493 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6494 | return -EINVAL; |
1857e1da | 6495 | } |
6d293983 | 6496 | return 0; |
1857e1da DV |
6497 | default: |
6498 | BUG(); | |
6499 | } | |
6500 | } | |
6501 | ||
e29c22c0 DV |
6502 | #define RETRY 1 |
6503 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6504 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6505 | { |
1857e1da | 6506 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6507 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6508 | int lane, link_bw, fdi_dotclock, ret; |
6509 | bool needs_recompute = false; | |
877d48d5 | 6510 | |
e29c22c0 | 6511 | retry: |
877d48d5 DV |
6512 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6513 | * each output octet as 10 bits. The actual frequency | |
6514 | * is stored as a divider into a 100MHz clock, and the | |
6515 | * mode pixel clock is stored in units of 1KHz. | |
6516 | * Hence the bw of each lane in terms of the mode signal | |
6517 | * is: | |
6518 | */ | |
6519 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6520 | ||
241bfc38 | 6521 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6522 | |
2bd89a07 | 6523 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6524 | pipe_config->pipe_bpp); |
6525 | ||
6526 | pipe_config->fdi_lanes = lane; | |
6527 | ||
2bd89a07 | 6528 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6529 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6530 | |
6d293983 ACO |
6531 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6532 | intel_crtc->pipe, pipe_config); | |
6533 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6534 | pipe_config->pipe_bpp -= 2*3; |
6535 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6536 | pipe_config->pipe_bpp); | |
6537 | needs_recompute = true; | |
6538 | pipe_config->bw_constrained = true; | |
6539 | ||
6540 | goto retry; | |
6541 | } | |
6542 | ||
6543 | if (needs_recompute) | |
6544 | return RETRY; | |
6545 | ||
6d293983 | 6546 | return ret; |
877d48d5 DV |
6547 | } |
6548 | ||
8cfb3407 VS |
6549 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6550 | struct intel_crtc_state *pipe_config) | |
6551 | { | |
6552 | if (pipe_config->pipe_bpp > 24) | |
6553 | return false; | |
6554 | ||
6555 | /* HSW can handle pixel rate up to cdclk? */ | |
6556 | if (IS_HASWELL(dev_priv->dev)) | |
6557 | return true; | |
6558 | ||
6559 | /* | |
b432e5cf VS |
6560 | * We compare against max which means we must take |
6561 | * the increased cdclk requirement into account when | |
6562 | * calculating the new cdclk. | |
6563 | * | |
6564 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6565 | */ |
6566 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6567 | dev_priv->max_cdclk_freq * 95 / 100; | |
6568 | } | |
6569 | ||
42db64ef | 6570 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6571 | struct intel_crtc_state *pipe_config) |
42db64ef | 6572 | { |
8cfb3407 VS |
6573 | struct drm_device *dev = crtc->base.dev; |
6574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6575 | ||
d330a953 | 6576 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6577 | hsw_crtc_supports_ips(crtc) && |
6578 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6579 | } |
6580 | ||
a43f6e0f | 6581 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6582 | struct intel_crtc_state *pipe_config) |
79e53945 | 6583 | { |
a43f6e0f | 6584 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6585 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6586 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6587 | |
ad3a4479 | 6588 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6589 | if (INTEL_INFO(dev)->gen < 4) { |
44913155 | 6590 | int clock_limit = dev_priv->max_cdclk_freq; |
cf532bb2 VS |
6591 | |
6592 | /* | |
6593 | * Enable pixel doubling when the dot clock | |
6594 | * is > 90% of the (display) core speed. | |
6595 | * | |
b397c96b VS |
6596 | * GDG double wide on either pipe, |
6597 | * otherwise pipe A only. | |
cf532bb2 | 6598 | */ |
b397c96b | 6599 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6600 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6601 | clock_limit *= 2; |
cf532bb2 | 6602 | pipe_config->double_wide = true; |
ad3a4479 VS |
6603 | } |
6604 | ||
241bfc38 | 6605 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6606 | return -EINVAL; |
2c07245f | 6607 | } |
89749350 | 6608 | |
1d1d0e27 VS |
6609 | /* |
6610 | * Pipe horizontal size must be even in: | |
6611 | * - DVO ganged mode | |
6612 | * - LVDS dual channel mode | |
6613 | * - Double wide pipe | |
6614 | */ | |
a93e255f | 6615 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6616 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6617 | pipe_config->pipe_src_w &= ~1; | |
6618 | ||
8693a824 DL |
6619 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6620 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6621 | */ |
6622 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6623 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6624 | return -EINVAL; |
44f46b42 | 6625 | |
f5adf94e | 6626 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6627 | hsw_compute_ips_config(crtc, pipe_config); |
6628 | ||
877d48d5 | 6629 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6630 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6631 | |
cf5a15be | 6632 | return 0; |
79e53945 JB |
6633 | } |
6634 | ||
1652d19e VS |
6635 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6636 | { | |
6637 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6638 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6639 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6640 | uint32_t linkrate; | |
6641 | ||
414355a7 | 6642 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6643 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6644 | |
6645 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6646 | return 540000; | |
6647 | ||
6648 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6649 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6650 | |
71cd8423 DL |
6651 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6652 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6653 | /* vco 8640 */ |
6654 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6655 | case CDCLK_FREQ_450_432: | |
6656 | return 432000; | |
6657 | case CDCLK_FREQ_337_308: | |
6658 | return 308570; | |
6659 | case CDCLK_FREQ_675_617: | |
6660 | return 617140; | |
6661 | default: | |
6662 | WARN(1, "Unknown cd freq selection\n"); | |
6663 | } | |
6664 | } else { | |
6665 | /* vco 8100 */ | |
6666 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6667 | case CDCLK_FREQ_450_432: | |
6668 | return 450000; | |
6669 | case CDCLK_FREQ_337_308: | |
6670 | return 337500; | |
6671 | case CDCLK_FREQ_675_617: | |
6672 | return 675000; | |
6673 | default: | |
6674 | WARN(1, "Unknown cd freq selection\n"); | |
6675 | } | |
6676 | } | |
6677 | ||
6678 | /* error case, do as if DPLL0 isn't enabled */ | |
6679 | return 24000; | |
6680 | } | |
6681 | ||
acd3f3d3 BP |
6682 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6683 | { | |
6684 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6685 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6686 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6687 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6688 | int cdclk; | |
6689 | ||
6690 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6691 | return 19200; | |
6692 | ||
6693 | cdclk = 19200 * pll_ratio / 2; | |
6694 | ||
6695 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6696 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6697 | return cdclk; /* 576MHz or 624MHz */ | |
6698 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6699 | return cdclk * 2 / 3; /* 384MHz */ | |
6700 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6701 | return cdclk / 2; /* 288MHz */ | |
6702 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6703 | return cdclk / 4; /* 144MHz */ | |
6704 | } | |
6705 | ||
6706 | /* error case, do as if DE PLL isn't enabled */ | |
6707 | return 19200; | |
6708 | } | |
6709 | ||
1652d19e VS |
6710 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6711 | { | |
6712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6713 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6714 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6715 | ||
6716 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6717 | return 800000; | |
6718 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6719 | return 450000; | |
6720 | else if (freq == LCPLL_CLK_FREQ_450) | |
6721 | return 450000; | |
6722 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6723 | return 540000; | |
6724 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6725 | return 337500; | |
6726 | else | |
6727 | return 675000; | |
6728 | } | |
6729 | ||
6730 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6731 | { | |
6732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6733 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6734 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6735 | ||
6736 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6737 | return 800000; | |
6738 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6739 | return 450000; | |
6740 | else if (freq == LCPLL_CLK_FREQ_450) | |
6741 | return 450000; | |
6742 | else if (IS_HSW_ULT(dev)) | |
6743 | return 337500; | |
6744 | else | |
6745 | return 540000; | |
79e53945 JB |
6746 | } |
6747 | ||
25eb05fc JB |
6748 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6749 | { | |
d197b7d3 | 6750 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6751 | u32 val; |
6752 | int divider; | |
6753 | ||
6bcda4f0 VS |
6754 | if (dev_priv->hpll_freq == 0) |
6755 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6756 | ||
a580516d | 6757 | mutex_lock(&dev_priv->sb_lock); |
d197b7d3 | 6758 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
a580516d | 6759 | mutex_unlock(&dev_priv->sb_lock); |
d197b7d3 VS |
6760 | |
6761 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6762 | ||
7d007f40 VS |
6763 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6764 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6765 | "cdclk change in progress\n"); | |
6766 | ||
6bcda4f0 | 6767 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6768 | } |
6769 | ||
b37a6434 VS |
6770 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6771 | { | |
6772 | return 450000; | |
6773 | } | |
6774 | ||
e70236a8 JB |
6775 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6776 | { | |
6777 | return 400000; | |
6778 | } | |
79e53945 | 6779 | |
e70236a8 | 6780 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6781 | { |
e907f170 | 6782 | return 333333; |
e70236a8 | 6783 | } |
79e53945 | 6784 | |
e70236a8 JB |
6785 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6786 | { | |
6787 | return 200000; | |
6788 | } | |
79e53945 | 6789 | |
257a7ffc DV |
6790 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6791 | { | |
6792 | u16 gcfgc = 0; | |
6793 | ||
6794 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6795 | ||
6796 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6797 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6798 | return 266667; |
257a7ffc | 6799 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6800 | return 333333; |
257a7ffc | 6801 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6802 | return 444444; |
257a7ffc DV |
6803 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6804 | return 200000; | |
6805 | default: | |
6806 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6807 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6808 | return 133333; |
257a7ffc | 6809 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6810 | return 166667; |
257a7ffc DV |
6811 | } |
6812 | } | |
6813 | ||
e70236a8 JB |
6814 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6815 | { | |
6816 | u16 gcfgc = 0; | |
79e53945 | 6817 | |
e70236a8 JB |
6818 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6819 | ||
6820 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6821 | return 133333; |
e70236a8 JB |
6822 | else { |
6823 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6824 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6825 | return 333333; |
e70236a8 JB |
6826 | default: |
6827 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6828 | return 190000; | |
79e53945 | 6829 | } |
e70236a8 JB |
6830 | } |
6831 | } | |
6832 | ||
6833 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6834 | { | |
e907f170 | 6835 | return 266667; |
e70236a8 JB |
6836 | } |
6837 | ||
1b1d2716 | 6838 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6839 | { |
6840 | u16 hpllcc = 0; | |
1b1d2716 | 6841 | |
65cd2b3f VS |
6842 | /* |
6843 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6844 | * encoding is different :( | |
6845 | * FIXME is this the right way to detect 852GM/852GMV? | |
6846 | */ | |
6847 | if (dev->pdev->revision == 0x1) | |
6848 | return 133333; | |
6849 | ||
1b1d2716 VS |
6850 | pci_bus_read_config_word(dev->pdev->bus, |
6851 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6852 | ||
e70236a8 JB |
6853 | /* Assume that the hardware is in the high speed state. This |
6854 | * should be the default. | |
6855 | */ | |
6856 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6857 | case GC_CLOCK_133_200: | |
1b1d2716 | 6858 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6859 | case GC_CLOCK_100_200: |
6860 | return 200000; | |
6861 | case GC_CLOCK_166_250: | |
6862 | return 250000; | |
6863 | case GC_CLOCK_100_133: | |
e907f170 | 6864 | return 133333; |
1b1d2716 VS |
6865 | case GC_CLOCK_133_266: |
6866 | case GC_CLOCK_133_266_2: | |
6867 | case GC_CLOCK_166_266: | |
6868 | return 266667; | |
e70236a8 | 6869 | } |
79e53945 | 6870 | |
e70236a8 JB |
6871 | /* Shouldn't happen */ |
6872 | return 0; | |
6873 | } | |
79e53945 | 6874 | |
e70236a8 JB |
6875 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6876 | { | |
e907f170 | 6877 | return 133333; |
79e53945 JB |
6878 | } |
6879 | ||
34edce2f VS |
6880 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6881 | { | |
6882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6883 | static const unsigned int blb_vco[8] = { | |
6884 | [0] = 3200000, | |
6885 | [1] = 4000000, | |
6886 | [2] = 5333333, | |
6887 | [3] = 4800000, | |
6888 | [4] = 6400000, | |
6889 | }; | |
6890 | static const unsigned int pnv_vco[8] = { | |
6891 | [0] = 3200000, | |
6892 | [1] = 4000000, | |
6893 | [2] = 5333333, | |
6894 | [3] = 4800000, | |
6895 | [4] = 2666667, | |
6896 | }; | |
6897 | static const unsigned int cl_vco[8] = { | |
6898 | [0] = 3200000, | |
6899 | [1] = 4000000, | |
6900 | [2] = 5333333, | |
6901 | [3] = 6400000, | |
6902 | [4] = 3333333, | |
6903 | [5] = 3566667, | |
6904 | [6] = 4266667, | |
6905 | }; | |
6906 | static const unsigned int elk_vco[8] = { | |
6907 | [0] = 3200000, | |
6908 | [1] = 4000000, | |
6909 | [2] = 5333333, | |
6910 | [3] = 4800000, | |
6911 | }; | |
6912 | static const unsigned int ctg_vco[8] = { | |
6913 | [0] = 3200000, | |
6914 | [1] = 4000000, | |
6915 | [2] = 5333333, | |
6916 | [3] = 6400000, | |
6917 | [4] = 2666667, | |
6918 | [5] = 4266667, | |
6919 | }; | |
6920 | const unsigned int *vco_table; | |
6921 | unsigned int vco; | |
6922 | uint8_t tmp = 0; | |
6923 | ||
6924 | /* FIXME other chipsets? */ | |
6925 | if (IS_GM45(dev)) | |
6926 | vco_table = ctg_vco; | |
6927 | else if (IS_G4X(dev)) | |
6928 | vco_table = elk_vco; | |
6929 | else if (IS_CRESTLINE(dev)) | |
6930 | vco_table = cl_vco; | |
6931 | else if (IS_PINEVIEW(dev)) | |
6932 | vco_table = pnv_vco; | |
6933 | else if (IS_G33(dev)) | |
6934 | vco_table = blb_vco; | |
6935 | else | |
6936 | return 0; | |
6937 | ||
6938 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6939 | ||
6940 | vco = vco_table[tmp & 0x7]; | |
6941 | if (vco == 0) | |
6942 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6943 | else | |
6944 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6945 | ||
6946 | return vco; | |
6947 | } | |
6948 | ||
6949 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6950 | { | |
6951 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6952 | uint16_t tmp = 0; | |
6953 | ||
6954 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6955 | ||
6956 | cdclk_sel = (tmp >> 12) & 0x1; | |
6957 | ||
6958 | switch (vco) { | |
6959 | case 2666667: | |
6960 | case 4000000: | |
6961 | case 5333333: | |
6962 | return cdclk_sel ? 333333 : 222222; | |
6963 | case 3200000: | |
6964 | return cdclk_sel ? 320000 : 228571; | |
6965 | default: | |
6966 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6967 | return 222222; | |
6968 | } | |
6969 | } | |
6970 | ||
6971 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6972 | { | |
6973 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6974 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6975 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6976 | const uint8_t *div_table; | |
6977 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6978 | uint16_t tmp = 0; | |
6979 | ||
6980 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6981 | ||
6982 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6983 | ||
6984 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6985 | goto fail; | |
6986 | ||
6987 | switch (vco) { | |
6988 | case 3200000: | |
6989 | div_table = div_3200; | |
6990 | break; | |
6991 | case 4000000: | |
6992 | div_table = div_4000; | |
6993 | break; | |
6994 | case 5333333: | |
6995 | div_table = div_5333; | |
6996 | break; | |
6997 | default: | |
6998 | goto fail; | |
6999 | } | |
7000 | ||
7001 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7002 | ||
caf4e252 | 7003 | fail: |
34edce2f VS |
7004 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7005 | return 200000; | |
7006 | } | |
7007 | ||
7008 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7009 | { | |
7010 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7011 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7012 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7013 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7014 | const uint8_t *div_table; | |
7015 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7016 | uint16_t tmp = 0; | |
7017 | ||
7018 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7019 | ||
7020 | cdclk_sel = (tmp >> 4) & 0x7; | |
7021 | ||
7022 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7023 | goto fail; | |
7024 | ||
7025 | switch (vco) { | |
7026 | case 3200000: | |
7027 | div_table = div_3200; | |
7028 | break; | |
7029 | case 4000000: | |
7030 | div_table = div_4000; | |
7031 | break; | |
7032 | case 4800000: | |
7033 | div_table = div_4800; | |
7034 | break; | |
7035 | case 5333333: | |
7036 | div_table = div_5333; | |
7037 | break; | |
7038 | default: | |
7039 | goto fail; | |
7040 | } | |
7041 | ||
7042 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7043 | ||
caf4e252 | 7044 | fail: |
34edce2f VS |
7045 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7046 | return 190476; | |
7047 | } | |
7048 | ||
2c07245f | 7049 | static void |
a65851af | 7050 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7051 | { |
a65851af VS |
7052 | while (*num > DATA_LINK_M_N_MASK || |
7053 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7054 | *num >>= 1; |
7055 | *den >>= 1; | |
7056 | } | |
7057 | } | |
7058 | ||
a65851af VS |
7059 | static void compute_m_n(unsigned int m, unsigned int n, |
7060 | uint32_t *ret_m, uint32_t *ret_n) | |
7061 | { | |
7062 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7063 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7064 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7065 | } | |
7066 | ||
e69d0bc1 DV |
7067 | void |
7068 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7069 | int pixel_clock, int link_clock, | |
7070 | struct intel_link_m_n *m_n) | |
2c07245f | 7071 | { |
e69d0bc1 | 7072 | m_n->tu = 64; |
a65851af VS |
7073 | |
7074 | compute_m_n(bits_per_pixel * pixel_clock, | |
7075 | link_clock * nlanes * 8, | |
7076 | &m_n->gmch_m, &m_n->gmch_n); | |
7077 | ||
7078 | compute_m_n(pixel_clock, link_clock, | |
7079 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7080 | } |
7081 | ||
a7615030 CW |
7082 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7083 | { | |
d330a953 JN |
7084 | if (i915.panel_use_ssc >= 0) |
7085 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7086 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7087 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7088 | } |
7089 | ||
a93e255f ACO |
7090 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7091 | int num_connectors) | |
c65d77d8 | 7092 | { |
a93e255f | 7093 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7094 | struct drm_i915_private *dev_priv = dev->dev_private; |
7095 | int refclk; | |
7096 | ||
a93e255f ACO |
7097 | WARN_ON(!crtc_state->base.state); |
7098 | ||
5ab7b0b7 | 7099 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7100 | refclk = 100000; |
a93e255f | 7101 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7102 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7103 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7104 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7105 | } else if (!IS_GEN2(dev)) { |
7106 | refclk = 96000; | |
7107 | } else { | |
7108 | refclk = 48000; | |
7109 | } | |
7110 | ||
7111 | return refclk; | |
7112 | } | |
7113 | ||
7429e9d4 | 7114 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7115 | { |
7df00d7a | 7116 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7117 | } |
f47709a9 | 7118 | |
7429e9d4 DV |
7119 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7120 | { | |
7121 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7122 | } |
7123 | ||
f47709a9 | 7124 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7125 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7126 | intel_clock_t *reduced_clock) |
7127 | { | |
f47709a9 | 7128 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7129 | u32 fp, fp2 = 0; |
7130 | ||
7131 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7132 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7133 | if (reduced_clock) |
7429e9d4 | 7134 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7135 | } else { |
190f68c5 | 7136 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7137 | if (reduced_clock) |
7429e9d4 | 7138 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7139 | } |
7140 | ||
190f68c5 | 7141 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7142 | |
f47709a9 | 7143 | crtc->lowfreq_avail = false; |
a93e255f | 7144 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7145 | reduced_clock) { |
190f68c5 | 7146 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7147 | crtc->lowfreq_avail = true; |
a7516a05 | 7148 | } else { |
190f68c5 | 7149 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7150 | } |
7151 | } | |
7152 | ||
5e69f97f CML |
7153 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7154 | pipe) | |
89b667f8 JB |
7155 | { |
7156 | u32 reg_val; | |
7157 | ||
7158 | /* | |
7159 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7160 | * and set it to a reasonable value instead. | |
7161 | */ | |
ab3c759a | 7162 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7163 | reg_val &= 0xffffff00; |
7164 | reg_val |= 0x00000030; | |
ab3c759a | 7165 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7166 | |
ab3c759a | 7167 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7168 | reg_val &= 0x8cffffff; |
7169 | reg_val = 0x8c000000; | |
ab3c759a | 7170 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7171 | |
ab3c759a | 7172 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7173 | reg_val &= 0xffffff00; |
ab3c759a | 7174 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7175 | |
ab3c759a | 7176 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7177 | reg_val &= 0x00ffffff; |
7178 | reg_val |= 0xb0000000; | |
ab3c759a | 7179 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7180 | } |
7181 | ||
b551842d DV |
7182 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7183 | struct intel_link_m_n *m_n) | |
7184 | { | |
7185 | struct drm_device *dev = crtc->base.dev; | |
7186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7187 | int pipe = crtc->pipe; | |
7188 | ||
e3b95f1e DV |
7189 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7190 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7191 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7192 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7193 | } |
7194 | ||
7195 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7196 | struct intel_link_m_n *m_n, |
7197 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7198 | { |
7199 | struct drm_device *dev = crtc->base.dev; | |
7200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7201 | int pipe = crtc->pipe; | |
6e3c9717 | 7202 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7203 | |
7204 | if (INTEL_INFO(dev)->gen >= 5) { | |
7205 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7206 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7207 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7208 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7209 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7210 | * for gen < 8) and if DRRS is supported (to make sure the | |
7211 | * registers are not unnecessarily accessed). | |
7212 | */ | |
44395bfe | 7213 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7214 | crtc->config->has_drrs) { |
f769cd24 VK |
7215 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7216 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7217 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7218 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7219 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7220 | } | |
b551842d | 7221 | } else { |
e3b95f1e DV |
7222 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7223 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7224 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7225 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7226 | } |
7227 | } | |
7228 | ||
fe3cd48d | 7229 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7230 | { |
fe3cd48d R |
7231 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7232 | ||
7233 | if (m_n == M1_N1) { | |
7234 | dp_m_n = &crtc->config->dp_m_n; | |
7235 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7236 | } else if (m_n == M2_N2) { | |
7237 | ||
7238 | /* | |
7239 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7240 | * needs to be programmed into M1_N1. | |
7241 | */ | |
7242 | dp_m_n = &crtc->config->dp_m2_n2; | |
7243 | } else { | |
7244 | DRM_ERROR("Unsupported divider value\n"); | |
7245 | return; | |
7246 | } | |
7247 | ||
6e3c9717 ACO |
7248 | if (crtc->config->has_pch_encoder) |
7249 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7250 | else |
fe3cd48d | 7251 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7252 | } |
7253 | ||
251ac862 DV |
7254 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7255 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7256 | { |
7257 | u32 dpll, dpll_md; | |
7258 | ||
7259 | /* | |
7260 | * Enable DPIO clock input. We should never disable the reference | |
7261 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7262 | * on it. | |
7263 | */ | |
60bfe44f VS |
7264 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7265 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7266 | /* We should never disable this, set it here for state tracking */ |
7267 | if (crtc->pipe == PIPE_B) | |
7268 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7269 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7270 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7271 | |
d288f65f | 7272 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7273 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7274 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7275 | } |
7276 | ||
d288f65f | 7277 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7278 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7279 | { |
f47709a9 | 7280 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7281 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7282 | int pipe = crtc->pipe; |
bdd4b6a6 | 7283 | u32 mdiv; |
a0c4da24 | 7284 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7285 | u32 coreclk, reg_val; |
a0c4da24 | 7286 | |
a580516d | 7287 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7288 | |
d288f65f VS |
7289 | bestn = pipe_config->dpll.n; |
7290 | bestm1 = pipe_config->dpll.m1; | |
7291 | bestm2 = pipe_config->dpll.m2; | |
7292 | bestp1 = pipe_config->dpll.p1; | |
7293 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7294 | |
89b667f8 JB |
7295 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7296 | ||
7297 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7298 | if (pipe == PIPE_B) |
5e69f97f | 7299 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7300 | |
7301 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7302 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7303 | |
7304 | /* Disable target IRef on PLL */ | |
ab3c759a | 7305 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7306 | reg_val &= 0x00ffffff; |
ab3c759a | 7307 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7308 | |
7309 | /* Disable fast lock */ | |
ab3c759a | 7310 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7311 | |
7312 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7313 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7314 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7315 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7316 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7317 | |
7318 | /* | |
7319 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7320 | * but we don't support that). | |
7321 | * Note: don't use the DAC post divider as it seems unstable. | |
7322 | */ | |
7323 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7324 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7325 | |
a0c4da24 | 7326 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7327 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7328 | |
89b667f8 | 7329 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7330 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7331 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7332 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7333 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7334 | 0x009f0003); |
89b667f8 | 7335 | else |
ab3c759a | 7336 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7337 | 0x00d0000f); |
7338 | ||
681a8504 | 7339 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7340 | /* Use SSC source */ |
bdd4b6a6 | 7341 | if (pipe == PIPE_A) |
ab3c759a | 7342 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7343 | 0x0df40000); |
7344 | else | |
ab3c759a | 7345 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7346 | 0x0df70000); |
7347 | } else { /* HDMI or VGA */ | |
7348 | /* Use bend source */ | |
bdd4b6a6 | 7349 | if (pipe == PIPE_A) |
ab3c759a | 7350 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7351 | 0x0df70000); |
7352 | else | |
ab3c759a | 7353 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7354 | 0x0df40000); |
7355 | } | |
a0c4da24 | 7356 | |
ab3c759a | 7357 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7358 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7359 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7360 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7361 | coreclk |= 0x01000000; |
ab3c759a | 7362 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7363 | |
ab3c759a | 7364 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7365 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7366 | } |
7367 | ||
251ac862 DV |
7368 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7369 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7370 | { |
60bfe44f VS |
7371 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7372 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7373 | DPLL_VCO_ENABLE; |
7374 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7375 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7376 | |
d288f65f VS |
7377 | pipe_config->dpll_hw_state.dpll_md = |
7378 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7379 | } |
7380 | ||
d288f65f | 7381 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7382 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7383 | { |
7384 | struct drm_device *dev = crtc->base.dev; | |
7385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7386 | int pipe = crtc->pipe; | |
7387 | int dpll_reg = DPLL(crtc->pipe); | |
7388 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7389 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7390 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7391 | u32 dpio_val; |
9cbe40c1 | 7392 | int vco; |
9d556c99 | 7393 | |
d288f65f VS |
7394 | bestn = pipe_config->dpll.n; |
7395 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7396 | bestm1 = pipe_config->dpll.m1; | |
7397 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7398 | bestp1 = pipe_config->dpll.p1; | |
7399 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7400 | vco = pipe_config->dpll.vco; |
a945ce7e | 7401 | dpio_val = 0; |
9cbe40c1 | 7402 | loopfilter = 0; |
9d556c99 CML |
7403 | |
7404 | /* | |
7405 | * Enable Refclk and SSC | |
7406 | */ | |
a11b0703 | 7407 | I915_WRITE(dpll_reg, |
d288f65f | 7408 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7409 | |
a580516d | 7410 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7411 | |
9d556c99 CML |
7412 | /* p1 and p2 divider */ |
7413 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7414 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7415 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7416 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7417 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7418 | ||
7419 | /* Feedback post-divider - m2 */ | |
7420 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7421 | ||
7422 | /* Feedback refclk divider - n and m1 */ | |
7423 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7424 | DPIO_CHV_M1_DIV_BY_2 | | |
7425 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7426 | ||
7427 | /* M2 fraction division */ | |
a945ce7e VP |
7428 | if (bestm2_frac) |
7429 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
7430 | |
7431 | /* M2 fraction division enable */ | |
a945ce7e VP |
7432 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7433 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7434 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7435 | if (bestm2_frac) | |
7436 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7437 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7438 | |
de3a0fde VP |
7439 | /* Program digital lock detect threshold */ |
7440 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7441 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7442 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7443 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7444 | if (!bestm2_frac) | |
7445 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7446 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7447 | ||
9d556c99 | 7448 | /* Loop filter */ |
9cbe40c1 VP |
7449 | if (vco == 5400000) { |
7450 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7451 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7452 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7453 | tribuf_calcntr = 0x9; | |
7454 | } else if (vco <= 6200000) { | |
7455 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7456 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7457 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7458 | tribuf_calcntr = 0x9; | |
7459 | } else if (vco <= 6480000) { | |
7460 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7461 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7462 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7463 | tribuf_calcntr = 0x8; | |
7464 | } else { | |
7465 | /* Not supported. Apply the same limits as in the max case */ | |
7466 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7467 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7468 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7469 | tribuf_calcntr = 0; | |
7470 | } | |
9d556c99 CML |
7471 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7472 | ||
968040b2 | 7473 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7474 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7475 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7476 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7477 | ||
9d556c99 CML |
7478 | /* AFC Recal */ |
7479 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7480 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7481 | DPIO_AFC_RECAL); | |
7482 | ||
a580516d | 7483 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7484 | } |
7485 | ||
d288f65f VS |
7486 | /** |
7487 | * vlv_force_pll_on - forcibly enable just the PLL | |
7488 | * @dev_priv: i915 private structure | |
7489 | * @pipe: pipe PLL to enable | |
7490 | * @dpll: PLL configuration | |
7491 | * | |
7492 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7493 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7494 | * be enabled. | |
7495 | */ | |
7496 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7497 | const struct dpll *dpll) | |
7498 | { | |
7499 | struct intel_crtc *crtc = | |
7500 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7501 | struct intel_crtc_state pipe_config = { |
a93e255f | 7502 | .base.crtc = &crtc->base, |
d288f65f VS |
7503 | .pixel_multiplier = 1, |
7504 | .dpll = *dpll, | |
7505 | }; | |
7506 | ||
7507 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7508 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7509 | chv_prepare_pll(crtc, &pipe_config); |
7510 | chv_enable_pll(crtc, &pipe_config); | |
7511 | } else { | |
251ac862 | 7512 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7513 | vlv_prepare_pll(crtc, &pipe_config); |
7514 | vlv_enable_pll(crtc, &pipe_config); | |
7515 | } | |
7516 | } | |
7517 | ||
7518 | /** | |
7519 | * vlv_force_pll_off - forcibly disable just the PLL | |
7520 | * @dev_priv: i915 private structure | |
7521 | * @pipe: pipe PLL to disable | |
7522 | * | |
7523 | * Disable the PLL for @pipe. To be used in cases where we need | |
7524 | * the PLL enabled even when @pipe is not going to be enabled. | |
7525 | */ | |
7526 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7527 | { | |
7528 | if (IS_CHERRYVIEW(dev)) | |
7529 | chv_disable_pll(to_i915(dev), pipe); | |
7530 | else | |
7531 | vlv_disable_pll(to_i915(dev), pipe); | |
7532 | } | |
7533 | ||
251ac862 DV |
7534 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7535 | struct intel_crtc_state *crtc_state, | |
7536 | intel_clock_t *reduced_clock, | |
7537 | int num_connectors) | |
eb1cbe48 | 7538 | { |
f47709a9 | 7539 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7540 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7541 | u32 dpll; |
7542 | bool is_sdvo; | |
190f68c5 | 7543 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7544 | |
190f68c5 | 7545 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7546 | |
a93e255f ACO |
7547 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7548 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7549 | |
7550 | dpll = DPLL_VGA_MODE_DIS; | |
7551 | ||
a93e255f | 7552 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7553 | dpll |= DPLLB_MODE_LVDS; |
7554 | else | |
7555 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7556 | |
ef1b460d | 7557 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7558 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7559 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7560 | } |
198a037f DV |
7561 | |
7562 | if (is_sdvo) | |
4a33e48d | 7563 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7564 | |
190f68c5 | 7565 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7566 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7567 | |
7568 | /* compute bitmask from p1 value */ | |
7569 | if (IS_PINEVIEW(dev)) | |
7570 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7571 | else { | |
7572 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7573 | if (IS_G4X(dev) && reduced_clock) | |
7574 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7575 | } | |
7576 | switch (clock->p2) { | |
7577 | case 5: | |
7578 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7579 | break; | |
7580 | case 7: | |
7581 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7582 | break; | |
7583 | case 10: | |
7584 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7585 | break; | |
7586 | case 14: | |
7587 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7588 | break; | |
7589 | } | |
7590 | if (INTEL_INFO(dev)->gen >= 4) | |
7591 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7592 | ||
190f68c5 | 7593 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7594 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7595 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7596 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7597 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7598 | else | |
7599 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7600 | ||
7601 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7602 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7603 | |
eb1cbe48 | 7604 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7605 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7606 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7607 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7608 | } |
7609 | } | |
7610 | ||
251ac862 DV |
7611 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7612 | struct intel_crtc_state *crtc_state, | |
7613 | intel_clock_t *reduced_clock, | |
7614 | int num_connectors) | |
eb1cbe48 | 7615 | { |
f47709a9 | 7616 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7617 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7618 | u32 dpll; |
190f68c5 | 7619 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7620 | |
190f68c5 | 7621 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7622 | |
eb1cbe48 DV |
7623 | dpll = DPLL_VGA_MODE_DIS; |
7624 | ||
a93e255f | 7625 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7626 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7627 | } else { | |
7628 | if (clock->p1 == 2) | |
7629 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7630 | else | |
7631 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7632 | if (clock->p2 == 4) | |
7633 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7634 | } | |
7635 | ||
a93e255f | 7636 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7637 | dpll |= DPLL_DVO_2X_MODE; |
7638 | ||
a93e255f | 7639 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7640 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7641 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7642 | else | |
7643 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7644 | ||
7645 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7646 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7647 | } |
7648 | ||
8a654f3b | 7649 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7650 | { |
7651 | struct drm_device *dev = intel_crtc->base.dev; | |
7652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7653 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7654 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7655 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7656 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7657 | uint32_t crtc_vtotal, crtc_vblank_end; |
7658 | int vsyncshift = 0; | |
4d8a62ea DV |
7659 | |
7660 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7661 | * the hw state checker will get angry at the mismatch. */ | |
7662 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7663 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7664 | |
609aeaca | 7665 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7666 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7667 | crtc_vtotal -= 1; |
7668 | crtc_vblank_end -= 1; | |
609aeaca | 7669 | |
409ee761 | 7670 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7671 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7672 | else | |
7673 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7674 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7675 | if (vsyncshift < 0) |
7676 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7677 | } |
7678 | ||
7679 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7680 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7681 | |
fe2b8f9d | 7682 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7683 | (adjusted_mode->crtc_hdisplay - 1) | |
7684 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7685 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7686 | (adjusted_mode->crtc_hblank_start - 1) | |
7687 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7688 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7689 | (adjusted_mode->crtc_hsync_start - 1) | |
7690 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7691 | ||
fe2b8f9d | 7692 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7693 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7694 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7695 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7696 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7697 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7698 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7699 | (adjusted_mode->crtc_vsync_start - 1) | |
7700 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7701 | ||
b5e508d4 PZ |
7702 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7703 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7704 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7705 | * bits. */ | |
7706 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7707 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7708 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7709 | ||
b0e77b9c PZ |
7710 | /* pipesrc controls the size that is scaled from, which should |
7711 | * always be the user's requested size. | |
7712 | */ | |
7713 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7714 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7715 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7716 | } |
7717 | ||
1bd1bd80 | 7718 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7719 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7720 | { |
7721 | struct drm_device *dev = crtc->base.dev; | |
7722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7723 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7724 | uint32_t tmp; | |
7725 | ||
7726 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7727 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7728 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7729 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7730 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7731 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7732 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7733 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7734 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7735 | |
7736 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7737 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7738 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7739 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7740 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7741 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7742 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7743 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7744 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7745 | |
7746 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7747 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7748 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7749 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7750 | } |
7751 | ||
7752 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7753 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7754 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7755 | ||
2d112de7 ACO |
7756 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7757 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7758 | } |
7759 | ||
f6a83288 | 7760 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7761 | struct intel_crtc_state *pipe_config) |
babea61d | 7762 | { |
2d112de7 ACO |
7763 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7764 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7765 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7766 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7767 | |
2d112de7 ACO |
7768 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7769 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7770 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7771 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7772 | |
2d112de7 | 7773 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7774 | |
2d112de7 ACO |
7775 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7776 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7777 | } |
7778 | ||
84b046f3 DV |
7779 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7780 | { | |
7781 | struct drm_device *dev = intel_crtc->base.dev; | |
7782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7783 | uint32_t pipeconf; | |
7784 | ||
9f11a9e4 | 7785 | pipeconf = 0; |
84b046f3 | 7786 | |
b6b5d049 VS |
7787 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7788 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7789 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7790 | |
6e3c9717 | 7791 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7792 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7793 | |
ff9ce46e DV |
7794 | /* only g4x and later have fancy bpc/dither controls */ |
7795 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7796 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7797 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7798 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7799 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7800 | |
6e3c9717 | 7801 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7802 | case 18: |
7803 | pipeconf |= PIPECONF_6BPC; | |
7804 | break; | |
7805 | case 24: | |
7806 | pipeconf |= PIPECONF_8BPC; | |
7807 | break; | |
7808 | case 30: | |
7809 | pipeconf |= PIPECONF_10BPC; | |
7810 | break; | |
7811 | default: | |
7812 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7813 | BUG(); | |
84b046f3 DV |
7814 | } |
7815 | } | |
7816 | ||
7817 | if (HAS_PIPE_CXSR(dev)) { | |
7818 | if (intel_crtc->lowfreq_avail) { | |
7819 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7820 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7821 | } else { | |
7822 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7823 | } |
7824 | } | |
7825 | ||
6e3c9717 | 7826 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7827 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7828 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7829 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7830 | else | |
7831 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7832 | } else | |
84b046f3 DV |
7833 | pipeconf |= PIPECONF_PROGRESSIVE; |
7834 | ||
6e3c9717 | 7835 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7836 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7837 | |
84b046f3 DV |
7838 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7839 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7840 | } | |
7841 | ||
190f68c5 ACO |
7842 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7843 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7844 | { |
c7653199 | 7845 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7846 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7847 | int refclk, num_connectors = 0; |
c329a4ec DV |
7848 | intel_clock_t clock; |
7849 | bool ok; | |
7850 | bool is_dsi = false; | |
5eddb70b | 7851 | struct intel_encoder *encoder; |
d4906093 | 7852 | const intel_limit_t *limit; |
55bb9992 | 7853 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7854 | struct drm_connector *connector; |
55bb9992 ACO |
7855 | struct drm_connector_state *connector_state; |
7856 | int i; | |
79e53945 | 7857 | |
dd3cd74a ACO |
7858 | memset(&crtc_state->dpll_hw_state, 0, |
7859 | sizeof(crtc_state->dpll_hw_state)); | |
7860 | ||
da3ced29 | 7861 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7862 | if (connector_state->crtc != &crtc->base) |
7863 | continue; | |
7864 | ||
7865 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7866 | ||
5eddb70b | 7867 | switch (encoder->type) { |
e9fd1c02 JN |
7868 | case INTEL_OUTPUT_DSI: |
7869 | is_dsi = true; | |
7870 | break; | |
6847d71b PZ |
7871 | default: |
7872 | break; | |
79e53945 | 7873 | } |
43565a06 | 7874 | |
c751ce4f | 7875 | num_connectors++; |
79e53945 JB |
7876 | } |
7877 | ||
f2335330 | 7878 | if (is_dsi) |
5b18e57c | 7879 | return 0; |
f2335330 | 7880 | |
190f68c5 | 7881 | if (!crtc_state->clock_set) { |
a93e255f | 7882 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7883 | |
e9fd1c02 JN |
7884 | /* |
7885 | * Returns a set of divisors for the desired target clock with | |
7886 | * the given refclk, or FALSE. The returned values represent | |
7887 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7888 | * 2) / p1 / p2. | |
7889 | */ | |
a93e255f ACO |
7890 | limit = intel_limit(crtc_state, refclk); |
7891 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7892 | crtc_state->port_clock, |
e9fd1c02 | 7893 | refclk, NULL, &clock); |
f2335330 | 7894 | if (!ok) { |
e9fd1c02 JN |
7895 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7896 | return -EINVAL; | |
7897 | } | |
79e53945 | 7898 | |
f2335330 | 7899 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7900 | crtc_state->dpll.n = clock.n; |
7901 | crtc_state->dpll.m1 = clock.m1; | |
7902 | crtc_state->dpll.m2 = clock.m2; | |
7903 | crtc_state->dpll.p1 = clock.p1; | |
7904 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7905 | } |
7026d4ac | 7906 | |
e9fd1c02 | 7907 | if (IS_GEN2(dev)) { |
c329a4ec | 7908 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7909 | num_connectors); |
9d556c99 | 7910 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7911 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7912 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7913 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7914 | } else { |
c329a4ec | 7915 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7916 | num_connectors); |
e9fd1c02 | 7917 | } |
79e53945 | 7918 | |
c8f7a0db | 7919 | return 0; |
f564048e EA |
7920 | } |
7921 | ||
2fa2fe9a | 7922 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7923 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7924 | { |
7925 | struct drm_device *dev = crtc->base.dev; | |
7926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7927 | uint32_t tmp; | |
7928 | ||
dc9e7dec VS |
7929 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7930 | return; | |
7931 | ||
2fa2fe9a | 7932 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7933 | if (!(tmp & PFIT_ENABLE)) |
7934 | return; | |
2fa2fe9a | 7935 | |
06922821 | 7936 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7937 | if (INTEL_INFO(dev)->gen < 4) { |
7938 | if (crtc->pipe != PIPE_B) | |
7939 | return; | |
2fa2fe9a DV |
7940 | } else { |
7941 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7942 | return; | |
7943 | } | |
7944 | ||
06922821 | 7945 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7946 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7947 | if (INTEL_INFO(dev)->gen < 5) | |
7948 | pipe_config->gmch_pfit.lvds_border_bits = | |
7949 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7950 | } | |
7951 | ||
acbec814 | 7952 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7953 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7954 | { |
7955 | struct drm_device *dev = crtc->base.dev; | |
7956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7957 | int pipe = pipe_config->cpu_transcoder; | |
7958 | intel_clock_t clock; | |
7959 | u32 mdiv; | |
662c6ecb | 7960 | int refclk = 100000; |
acbec814 | 7961 | |
f573de5a SK |
7962 | /* In case of MIPI DPLL will not even be used */ |
7963 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7964 | return; | |
7965 | ||
a580516d | 7966 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7967 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7968 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7969 | |
7970 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7971 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7972 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7973 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7974 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7975 | ||
dccbea3b | 7976 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7977 | } |
7978 | ||
5724dbd1 DL |
7979 | static void |
7980 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7981 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7982 | { |
7983 | struct drm_device *dev = crtc->base.dev; | |
7984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7985 | u32 val, base, offset; | |
7986 | int pipe = crtc->pipe, plane = crtc->plane; | |
7987 | int fourcc, pixel_format; | |
6761dd31 | 7988 | unsigned int aligned_height; |
b113d5ee | 7989 | struct drm_framebuffer *fb; |
1b842c89 | 7990 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7991 | |
42a7b088 DL |
7992 | val = I915_READ(DSPCNTR(plane)); |
7993 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7994 | return; | |
7995 | ||
d9806c9f | 7996 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7997 | if (!intel_fb) { |
1ad292b5 JB |
7998 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7999 | return; | |
8000 | } | |
8001 | ||
1b842c89 DL |
8002 | fb = &intel_fb->base; |
8003 | ||
18c5247e DV |
8004 | if (INTEL_INFO(dev)->gen >= 4) { |
8005 | if (val & DISPPLANE_TILED) { | |
49af449b | 8006 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8007 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8008 | } | |
8009 | } | |
1ad292b5 JB |
8010 | |
8011 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8012 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8013 | fb->pixel_format = fourcc; |
8014 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8015 | |
8016 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8017 | if (plane_config->tiling) |
1ad292b5 JB |
8018 | offset = I915_READ(DSPTILEOFF(plane)); |
8019 | else | |
8020 | offset = I915_READ(DSPLINOFF(plane)); | |
8021 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8022 | } else { | |
8023 | base = I915_READ(DSPADDR(plane)); | |
8024 | } | |
8025 | plane_config->base = base; | |
8026 | ||
8027 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8028 | fb->width = ((val >> 16) & 0xfff) + 1; |
8029 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8030 | |
8031 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8032 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8033 | |
b113d5ee | 8034 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8035 | fb->pixel_format, |
8036 | fb->modifier[0]); | |
1ad292b5 | 8037 | |
f37b5c2b | 8038 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8039 | |
2844a921 DL |
8040 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8041 | pipe_name(pipe), plane, fb->width, fb->height, | |
8042 | fb->bits_per_pixel, base, fb->pitches[0], | |
8043 | plane_config->size); | |
1ad292b5 | 8044 | |
2d14030b | 8045 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8046 | } |
8047 | ||
70b23a98 | 8048 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8049 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8050 | { |
8051 | struct drm_device *dev = crtc->base.dev; | |
8052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8053 | int pipe = pipe_config->cpu_transcoder; | |
8054 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8055 | intel_clock_t clock; | |
8056 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
8057 | int refclk = 100000; | |
8058 | ||
a580516d | 8059 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8060 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8061 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8062 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8063 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
a580516d | 8064 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8065 | |
8066 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
8067 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
8068 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
8069 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8070 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8071 | ||
dccbea3b | 8072 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8073 | } |
8074 | ||
0e8ffe1b | 8075 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8076 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8077 | { |
8078 | struct drm_device *dev = crtc->base.dev; | |
8079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8080 | uint32_t tmp; | |
8081 | ||
f458ebbc DV |
8082 | if (!intel_display_power_is_enabled(dev_priv, |
8083 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8084 | return false; |
8085 | ||
e143a21c | 8086 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8087 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8088 | |
0e8ffe1b DV |
8089 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8090 | if (!(tmp & PIPECONF_ENABLE)) | |
8091 | return false; | |
8092 | ||
42571aef VS |
8093 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8094 | switch (tmp & PIPECONF_BPC_MASK) { | |
8095 | case PIPECONF_6BPC: | |
8096 | pipe_config->pipe_bpp = 18; | |
8097 | break; | |
8098 | case PIPECONF_8BPC: | |
8099 | pipe_config->pipe_bpp = 24; | |
8100 | break; | |
8101 | case PIPECONF_10BPC: | |
8102 | pipe_config->pipe_bpp = 30; | |
8103 | break; | |
8104 | default: | |
8105 | break; | |
8106 | } | |
8107 | } | |
8108 | ||
b5a9fa09 DV |
8109 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8110 | pipe_config->limited_color_range = true; | |
8111 | ||
282740f7 VS |
8112 | if (INTEL_INFO(dev)->gen < 4) |
8113 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8114 | ||
1bd1bd80 DV |
8115 | intel_get_pipe_timings(crtc, pipe_config); |
8116 | ||
2fa2fe9a DV |
8117 | i9xx_get_pfit_config(crtc, pipe_config); |
8118 | ||
6c49f241 DV |
8119 | if (INTEL_INFO(dev)->gen >= 4) { |
8120 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8121 | pipe_config->pixel_multiplier = | |
8122 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8123 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8124 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8125 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8126 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8127 | pipe_config->pixel_multiplier = | |
8128 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8129 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8130 | } else { | |
8131 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8132 | * port and will be fixed up in the encoder->get_config | |
8133 | * function. */ | |
8134 | pipe_config->pixel_multiplier = 1; | |
8135 | } | |
8bcc2795 DV |
8136 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8137 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
8138 | /* |
8139 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8140 | * on 830. Filter it out here so that we don't | |
8141 | * report errors due to that. | |
8142 | */ | |
8143 | if (IS_I830(dev)) | |
8144 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8145 | ||
8bcc2795 DV |
8146 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8147 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8148 | } else { |
8149 | /* Mask out read-only status bits. */ | |
8150 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8151 | DPLL_PORTC_READY_MASK | | |
8152 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8153 | } |
6c49f241 | 8154 | |
70b23a98 VS |
8155 | if (IS_CHERRYVIEW(dev)) |
8156 | chv_crtc_clock_get(crtc, pipe_config); | |
8157 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8158 | vlv_crtc_clock_get(crtc, pipe_config); |
8159 | else | |
8160 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8161 | |
0e8ffe1b DV |
8162 | return true; |
8163 | } | |
8164 | ||
dde86e2d | 8165 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8166 | { |
8167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8168 | struct intel_encoder *encoder; |
74cfd7ac | 8169 | u32 val, final; |
13d83a67 | 8170 | bool has_lvds = false; |
199e5d79 | 8171 | bool has_cpu_edp = false; |
199e5d79 | 8172 | bool has_panel = false; |
99eb6a01 KP |
8173 | bool has_ck505 = false; |
8174 | bool can_ssc = false; | |
13d83a67 JB |
8175 | |
8176 | /* We need to take the global config into account */ | |
b2784e15 | 8177 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8178 | switch (encoder->type) { |
8179 | case INTEL_OUTPUT_LVDS: | |
8180 | has_panel = true; | |
8181 | has_lvds = true; | |
8182 | break; | |
8183 | case INTEL_OUTPUT_EDP: | |
8184 | has_panel = true; | |
2de6905f | 8185 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8186 | has_cpu_edp = true; |
8187 | break; | |
6847d71b PZ |
8188 | default: |
8189 | break; | |
13d83a67 JB |
8190 | } |
8191 | } | |
8192 | ||
99eb6a01 | 8193 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8194 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8195 | can_ssc = has_ck505; |
8196 | } else { | |
8197 | has_ck505 = false; | |
8198 | can_ssc = true; | |
8199 | } | |
8200 | ||
2de6905f ID |
8201 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8202 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8203 | |
8204 | /* Ironlake: try to setup display ref clock before DPLL | |
8205 | * enabling. This is only under driver's control after | |
8206 | * PCH B stepping, previous chipset stepping should be | |
8207 | * ignoring this setting. | |
8208 | */ | |
74cfd7ac CW |
8209 | val = I915_READ(PCH_DREF_CONTROL); |
8210 | ||
8211 | /* As we must carefully and slowly disable/enable each source in turn, | |
8212 | * compute the final state we want first and check if we need to | |
8213 | * make any changes at all. | |
8214 | */ | |
8215 | final = val; | |
8216 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8217 | if (has_ck505) | |
8218 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8219 | else | |
8220 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8221 | ||
8222 | final &= ~DREF_SSC_SOURCE_MASK; | |
8223 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8224 | final &= ~DREF_SSC1_ENABLE; | |
8225 | ||
8226 | if (has_panel) { | |
8227 | final |= DREF_SSC_SOURCE_ENABLE; | |
8228 | ||
8229 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8230 | final |= DREF_SSC1_ENABLE; | |
8231 | ||
8232 | if (has_cpu_edp) { | |
8233 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8234 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8235 | else | |
8236 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8237 | } else | |
8238 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8239 | } else { | |
8240 | final |= DREF_SSC_SOURCE_DISABLE; | |
8241 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8242 | } | |
8243 | ||
8244 | if (final == val) | |
8245 | return; | |
8246 | ||
13d83a67 | 8247 | /* Always enable nonspread source */ |
74cfd7ac | 8248 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8249 | |
99eb6a01 | 8250 | if (has_ck505) |
74cfd7ac | 8251 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8252 | else |
74cfd7ac | 8253 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8254 | |
199e5d79 | 8255 | if (has_panel) { |
74cfd7ac CW |
8256 | val &= ~DREF_SSC_SOURCE_MASK; |
8257 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8258 | |
199e5d79 | 8259 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8260 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8261 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8262 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8263 | } else |
74cfd7ac | 8264 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8265 | |
8266 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8267 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8268 | POSTING_READ(PCH_DREF_CONTROL); |
8269 | udelay(200); | |
8270 | ||
74cfd7ac | 8271 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8272 | |
8273 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8274 | if (has_cpu_edp) { |
99eb6a01 | 8275 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8276 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8277 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8278 | } else |
74cfd7ac | 8279 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8280 | } else |
74cfd7ac | 8281 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8282 | |
74cfd7ac | 8283 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8284 | POSTING_READ(PCH_DREF_CONTROL); |
8285 | udelay(200); | |
8286 | } else { | |
8287 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8288 | ||
74cfd7ac | 8289 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8290 | |
8291 | /* Turn off CPU output */ | |
74cfd7ac | 8292 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8293 | |
74cfd7ac | 8294 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8295 | POSTING_READ(PCH_DREF_CONTROL); |
8296 | udelay(200); | |
8297 | ||
8298 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8299 | val &= ~DREF_SSC_SOURCE_MASK; |
8300 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8301 | |
8302 | /* Turn off SSC1 */ | |
74cfd7ac | 8303 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8304 | |
74cfd7ac | 8305 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8306 | POSTING_READ(PCH_DREF_CONTROL); |
8307 | udelay(200); | |
8308 | } | |
74cfd7ac CW |
8309 | |
8310 | BUG_ON(val != final); | |
13d83a67 JB |
8311 | } |
8312 | ||
f31f2d55 | 8313 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8314 | { |
f31f2d55 | 8315 | uint32_t tmp; |
dde86e2d | 8316 | |
0ff066a9 PZ |
8317 | tmp = I915_READ(SOUTH_CHICKEN2); |
8318 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8319 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8320 | |
0ff066a9 PZ |
8321 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8322 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8323 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8324 | |
0ff066a9 PZ |
8325 | tmp = I915_READ(SOUTH_CHICKEN2); |
8326 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8327 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8328 | |
0ff066a9 PZ |
8329 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8330 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8331 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8332 | } |
8333 | ||
8334 | /* WaMPhyProgramming:hsw */ | |
8335 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8336 | { | |
8337 | uint32_t tmp; | |
dde86e2d PZ |
8338 | |
8339 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8340 | tmp &= ~(0xFF << 24); | |
8341 | tmp |= (0x12 << 24); | |
8342 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8343 | ||
dde86e2d PZ |
8344 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8345 | tmp |= (1 << 11); | |
8346 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8347 | ||
8348 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8349 | tmp |= (1 << 11); | |
8350 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8351 | ||
dde86e2d PZ |
8352 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8353 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8354 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8355 | ||
8356 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8357 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8358 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8359 | ||
0ff066a9 PZ |
8360 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8361 | tmp &= ~(7 << 13); | |
8362 | tmp |= (5 << 13); | |
8363 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8364 | |
0ff066a9 PZ |
8365 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8366 | tmp &= ~(7 << 13); | |
8367 | tmp |= (5 << 13); | |
8368 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8369 | |
8370 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8371 | tmp &= ~0xFF; | |
8372 | tmp |= 0x1C; | |
8373 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8374 | ||
8375 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8376 | tmp &= ~0xFF; | |
8377 | tmp |= 0x1C; | |
8378 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8379 | ||
8380 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8381 | tmp &= ~(0xFF << 16); | |
8382 | tmp |= (0x1C << 16); | |
8383 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8384 | ||
8385 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8386 | tmp &= ~(0xFF << 16); | |
8387 | tmp |= (0x1C << 16); | |
8388 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8389 | ||
0ff066a9 PZ |
8390 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8391 | tmp |= (1 << 27); | |
8392 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8393 | |
0ff066a9 PZ |
8394 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8395 | tmp |= (1 << 27); | |
8396 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8397 | |
0ff066a9 PZ |
8398 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8399 | tmp &= ~(0xF << 28); | |
8400 | tmp |= (4 << 28); | |
8401 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8402 | |
0ff066a9 PZ |
8403 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8404 | tmp &= ~(0xF << 28); | |
8405 | tmp |= (4 << 28); | |
8406 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8407 | } |
8408 | ||
2fa86a1f PZ |
8409 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8410 | * Programming" based on the parameters passed: | |
8411 | * - Sequence to enable CLKOUT_DP | |
8412 | * - Sequence to enable CLKOUT_DP without spread | |
8413 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8414 | */ | |
8415 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8416 | bool with_fdi) | |
f31f2d55 PZ |
8417 | { |
8418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8419 | uint32_t reg, tmp; |
8420 | ||
8421 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8422 | with_spread = true; | |
8423 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8424 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8425 | with_fdi = false; | |
f31f2d55 | 8426 | |
a580516d | 8427 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8428 | |
8429 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8430 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8431 | tmp |= SBI_SSCCTL_PATHALT; | |
8432 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8433 | ||
8434 | udelay(24); | |
8435 | ||
2fa86a1f PZ |
8436 | if (with_spread) { |
8437 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8438 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8439 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8440 | |
2fa86a1f PZ |
8441 | if (with_fdi) { |
8442 | lpt_reset_fdi_mphy(dev_priv); | |
8443 | lpt_program_fdi_mphy(dev_priv); | |
8444 | } | |
8445 | } | |
dde86e2d | 8446 | |
2fa86a1f PZ |
8447 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8448 | SBI_GEN0 : SBI_DBUFF0; | |
8449 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8450 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8451 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8452 | |
a580516d | 8453 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8454 | } |
8455 | ||
47701c3b PZ |
8456 | /* Sequence to disable CLKOUT_DP */ |
8457 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8458 | { | |
8459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8460 | uint32_t reg, tmp; | |
8461 | ||
a580516d | 8462 | mutex_lock(&dev_priv->sb_lock); |
47701c3b PZ |
8463 | |
8464 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8465 | SBI_GEN0 : SBI_DBUFF0; | |
8466 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8467 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8468 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8469 | ||
8470 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8471 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8472 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8473 | tmp |= SBI_SSCCTL_PATHALT; | |
8474 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8475 | udelay(32); | |
8476 | } | |
8477 | tmp |= SBI_SSCCTL_DISABLE; | |
8478 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8479 | } | |
8480 | ||
a580516d | 8481 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8482 | } |
8483 | ||
bf8fa3d3 PZ |
8484 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8485 | { | |
bf8fa3d3 PZ |
8486 | struct intel_encoder *encoder; |
8487 | bool has_vga = false; | |
8488 | ||
b2784e15 | 8489 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8490 | switch (encoder->type) { |
8491 | case INTEL_OUTPUT_ANALOG: | |
8492 | has_vga = true; | |
8493 | break; | |
6847d71b PZ |
8494 | default: |
8495 | break; | |
bf8fa3d3 PZ |
8496 | } |
8497 | } | |
8498 | ||
47701c3b PZ |
8499 | if (has_vga) |
8500 | lpt_enable_clkout_dp(dev, true, true); | |
8501 | else | |
8502 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8503 | } |
8504 | ||
dde86e2d PZ |
8505 | /* |
8506 | * Initialize reference clocks when the driver loads | |
8507 | */ | |
8508 | void intel_init_pch_refclk(struct drm_device *dev) | |
8509 | { | |
8510 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8511 | ironlake_init_pch_refclk(dev); | |
8512 | else if (HAS_PCH_LPT(dev)) | |
8513 | lpt_init_pch_refclk(dev); | |
8514 | } | |
8515 | ||
55bb9992 | 8516 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8517 | { |
55bb9992 | 8518 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8519 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8520 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8521 | struct drm_connector *connector; |
55bb9992 | 8522 | struct drm_connector_state *connector_state; |
d9d444cb | 8523 | struct intel_encoder *encoder; |
55bb9992 | 8524 | int num_connectors = 0, i; |
d9d444cb JB |
8525 | bool is_lvds = false; |
8526 | ||
da3ced29 | 8527 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8528 | if (connector_state->crtc != crtc_state->base.crtc) |
8529 | continue; | |
8530 | ||
8531 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8532 | ||
d9d444cb JB |
8533 | switch (encoder->type) { |
8534 | case INTEL_OUTPUT_LVDS: | |
8535 | is_lvds = true; | |
8536 | break; | |
6847d71b PZ |
8537 | default: |
8538 | break; | |
d9d444cb JB |
8539 | } |
8540 | num_connectors++; | |
8541 | } | |
8542 | ||
8543 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8544 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8545 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8546 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8547 | } |
8548 | ||
8549 | return 120000; | |
8550 | } | |
8551 | ||
6ff93609 | 8552 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8553 | { |
c8203565 | 8554 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8556 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8557 | uint32_t val; |
8558 | ||
78114071 | 8559 | val = 0; |
c8203565 | 8560 | |
6e3c9717 | 8561 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8562 | case 18: |
dfd07d72 | 8563 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8564 | break; |
8565 | case 24: | |
dfd07d72 | 8566 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8567 | break; |
8568 | case 30: | |
dfd07d72 | 8569 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8570 | break; |
8571 | case 36: | |
dfd07d72 | 8572 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8573 | break; |
8574 | default: | |
cc769b62 PZ |
8575 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8576 | BUG(); | |
c8203565 PZ |
8577 | } |
8578 | ||
6e3c9717 | 8579 | if (intel_crtc->config->dither) |
c8203565 PZ |
8580 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8581 | ||
6e3c9717 | 8582 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8583 | val |= PIPECONF_INTERLACED_ILK; |
8584 | else | |
8585 | val |= PIPECONF_PROGRESSIVE; | |
8586 | ||
6e3c9717 | 8587 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8588 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8589 | |
c8203565 PZ |
8590 | I915_WRITE(PIPECONF(pipe), val); |
8591 | POSTING_READ(PIPECONF(pipe)); | |
8592 | } | |
8593 | ||
86d3efce VS |
8594 | /* |
8595 | * Set up the pipe CSC unit. | |
8596 | * | |
8597 | * Currently only full range RGB to limited range RGB conversion | |
8598 | * is supported, but eventually this should handle various | |
8599 | * RGB<->YCbCr scenarios as well. | |
8600 | */ | |
50f3b016 | 8601 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8602 | { |
8603 | struct drm_device *dev = crtc->dev; | |
8604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8606 | int pipe = intel_crtc->pipe; | |
8607 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8608 | ||
8609 | /* | |
8610 | * TODO: Check what kind of values actually come out of the pipe | |
8611 | * with these coeff/postoff values and adjust to get the best | |
8612 | * accuracy. Perhaps we even need to take the bpc value into | |
8613 | * consideration. | |
8614 | */ | |
8615 | ||
6e3c9717 | 8616 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8617 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8618 | ||
8619 | /* | |
8620 | * GY/GU and RY/RU should be the other way around according | |
8621 | * to BSpec, but reality doesn't agree. Just set them up in | |
8622 | * a way that results in the correct picture. | |
8623 | */ | |
8624 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8625 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8626 | ||
8627 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8628 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8629 | ||
8630 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8631 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8632 | ||
8633 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8634 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8635 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8636 | ||
8637 | if (INTEL_INFO(dev)->gen > 6) { | |
8638 | uint16_t postoff = 0; | |
8639 | ||
6e3c9717 | 8640 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8641 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8642 | |
8643 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8644 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8645 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8646 | ||
8647 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8648 | } else { | |
8649 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8650 | ||
6e3c9717 | 8651 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8652 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8653 | ||
8654 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8655 | } | |
8656 | } | |
8657 | ||
6ff93609 | 8658 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8659 | { |
756f85cf PZ |
8660 | struct drm_device *dev = crtc->dev; |
8661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8663 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8664 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8665 | uint32_t val; |
8666 | ||
3eff4faa | 8667 | val = 0; |
ee2b0b38 | 8668 | |
6e3c9717 | 8669 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8670 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8671 | ||
6e3c9717 | 8672 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8673 | val |= PIPECONF_INTERLACED_ILK; |
8674 | else | |
8675 | val |= PIPECONF_PROGRESSIVE; | |
8676 | ||
702e7a56 PZ |
8677 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8678 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8679 | |
8680 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8681 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8682 | |
3cdf122c | 8683 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8684 | val = 0; |
8685 | ||
6e3c9717 | 8686 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8687 | case 18: |
8688 | val |= PIPEMISC_DITHER_6_BPC; | |
8689 | break; | |
8690 | case 24: | |
8691 | val |= PIPEMISC_DITHER_8_BPC; | |
8692 | break; | |
8693 | case 30: | |
8694 | val |= PIPEMISC_DITHER_10_BPC; | |
8695 | break; | |
8696 | case 36: | |
8697 | val |= PIPEMISC_DITHER_12_BPC; | |
8698 | break; | |
8699 | default: | |
8700 | /* Case prevented by pipe_config_set_bpp. */ | |
8701 | BUG(); | |
8702 | } | |
8703 | ||
6e3c9717 | 8704 | if (intel_crtc->config->dither) |
756f85cf PZ |
8705 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8706 | ||
8707 | I915_WRITE(PIPEMISC(pipe), val); | |
8708 | } | |
ee2b0b38 PZ |
8709 | } |
8710 | ||
6591c6e4 | 8711 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8712 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8713 | intel_clock_t *clock, |
8714 | bool *has_reduced_clock, | |
8715 | intel_clock_t *reduced_clock) | |
8716 | { | |
8717 | struct drm_device *dev = crtc->dev; | |
8718 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8719 | int refclk; |
d4906093 | 8720 | const intel_limit_t *limit; |
c329a4ec | 8721 | bool ret; |
79e53945 | 8722 | |
55bb9992 | 8723 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8724 | |
d4906093 ML |
8725 | /* |
8726 | * Returns a set of divisors for the desired target clock with the given | |
8727 | * refclk, or FALSE. The returned values represent the clock equation: | |
8728 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8729 | */ | |
a93e255f ACO |
8730 | limit = intel_limit(crtc_state, refclk); |
8731 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8732 | crtc_state->port_clock, |
ee9300bb | 8733 | refclk, NULL, clock); |
6591c6e4 PZ |
8734 | if (!ret) |
8735 | return false; | |
cda4b7d3 | 8736 | |
6591c6e4 PZ |
8737 | return true; |
8738 | } | |
8739 | ||
d4b1931c PZ |
8740 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8741 | { | |
8742 | /* | |
8743 | * Account for spread spectrum to avoid | |
8744 | * oversubscribing the link. Max center spread | |
8745 | * is 2.5%; use 5% for safety's sake. | |
8746 | */ | |
8747 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8748 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8749 | } |
8750 | ||
7429e9d4 | 8751 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8752 | { |
7429e9d4 | 8753 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8754 | } |
8755 | ||
de13a2e3 | 8756 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8757 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8758 | u32 *fp, |
9a7c7890 | 8759 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8760 | { |
de13a2e3 | 8761 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8762 | struct drm_device *dev = crtc->dev; |
8763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8764 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8765 | struct drm_connector *connector; |
55bb9992 ACO |
8766 | struct drm_connector_state *connector_state; |
8767 | struct intel_encoder *encoder; | |
de13a2e3 | 8768 | uint32_t dpll; |
55bb9992 | 8769 | int factor, num_connectors = 0, i; |
09ede541 | 8770 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8771 | |
da3ced29 | 8772 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8773 | if (connector_state->crtc != crtc_state->base.crtc) |
8774 | continue; | |
8775 | ||
8776 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8777 | ||
8778 | switch (encoder->type) { | |
79e53945 JB |
8779 | case INTEL_OUTPUT_LVDS: |
8780 | is_lvds = true; | |
8781 | break; | |
8782 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8783 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8784 | is_sdvo = true; |
79e53945 | 8785 | break; |
6847d71b PZ |
8786 | default: |
8787 | break; | |
79e53945 | 8788 | } |
43565a06 | 8789 | |
c751ce4f | 8790 | num_connectors++; |
79e53945 | 8791 | } |
79e53945 | 8792 | |
c1858123 | 8793 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8794 | factor = 21; |
8795 | if (is_lvds) { | |
8796 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8797 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8798 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8799 | factor = 25; |
190f68c5 | 8800 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8801 | factor = 20; |
c1858123 | 8802 | |
190f68c5 | 8803 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8804 | *fp |= FP_CB_TUNE; |
2c07245f | 8805 | |
9a7c7890 DV |
8806 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8807 | *fp2 |= FP_CB_TUNE; | |
8808 | ||
5eddb70b | 8809 | dpll = 0; |
2c07245f | 8810 | |
a07d6787 EA |
8811 | if (is_lvds) |
8812 | dpll |= DPLLB_MODE_LVDS; | |
8813 | else | |
8814 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8815 | |
190f68c5 | 8816 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8817 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8818 | |
8819 | if (is_sdvo) | |
4a33e48d | 8820 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8821 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8822 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8823 | |
a07d6787 | 8824 | /* compute bitmask from p1 value */ |
190f68c5 | 8825 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8826 | /* also FPA1 */ |
190f68c5 | 8827 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8828 | |
190f68c5 | 8829 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8830 | case 5: |
8831 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8832 | break; | |
8833 | case 7: | |
8834 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8835 | break; | |
8836 | case 10: | |
8837 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8838 | break; | |
8839 | case 14: | |
8840 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8841 | break; | |
79e53945 JB |
8842 | } |
8843 | ||
b4c09f3b | 8844 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8845 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8846 | else |
8847 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8848 | ||
959e16d6 | 8849 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8850 | } |
8851 | ||
190f68c5 ACO |
8852 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8853 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8854 | { |
c7653199 | 8855 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8856 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8857 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8858 | bool ok, has_reduced_clock = false; |
8b47047b | 8859 | bool is_lvds = false; |
e2b78267 | 8860 | struct intel_shared_dpll *pll; |
de13a2e3 | 8861 | |
dd3cd74a ACO |
8862 | memset(&crtc_state->dpll_hw_state, 0, |
8863 | sizeof(crtc_state->dpll_hw_state)); | |
8864 | ||
409ee761 | 8865 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8866 | |
5dc5298b PZ |
8867 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8868 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8869 | |
190f68c5 | 8870 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8871 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8872 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8873 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8874 | return -EINVAL; | |
79e53945 | 8875 | } |
f47709a9 | 8876 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8877 | if (!crtc_state->clock_set) { |
8878 | crtc_state->dpll.n = clock.n; | |
8879 | crtc_state->dpll.m1 = clock.m1; | |
8880 | crtc_state->dpll.m2 = clock.m2; | |
8881 | crtc_state->dpll.p1 = clock.p1; | |
8882 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8883 | } |
79e53945 | 8884 | |
5dc5298b | 8885 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8886 | if (crtc_state->has_pch_encoder) { |
8887 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8888 | if (has_reduced_clock) |
7429e9d4 | 8889 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8890 | |
190f68c5 | 8891 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8892 | &fp, &reduced_clock, |
8893 | has_reduced_clock ? &fp2 : NULL); | |
8894 | ||
190f68c5 ACO |
8895 | crtc_state->dpll_hw_state.dpll = dpll; |
8896 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8897 | if (has_reduced_clock) |
190f68c5 | 8898 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8899 | else |
190f68c5 | 8900 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8901 | |
190f68c5 | 8902 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8903 | if (pll == NULL) { |
84f44ce7 | 8904 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8905 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8906 | return -EINVAL; |
8907 | } | |
3fb37703 | 8908 | } |
79e53945 | 8909 | |
ab585dea | 8910 | if (is_lvds && has_reduced_clock) |
c7653199 | 8911 | crtc->lowfreq_avail = true; |
bcd644e0 | 8912 | else |
c7653199 | 8913 | crtc->lowfreq_avail = false; |
e2b78267 | 8914 | |
c8f7a0db | 8915 | return 0; |
79e53945 JB |
8916 | } |
8917 | ||
eb14cb74 VS |
8918 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8919 | struct intel_link_m_n *m_n) | |
8920 | { | |
8921 | struct drm_device *dev = crtc->base.dev; | |
8922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8923 | enum pipe pipe = crtc->pipe; | |
8924 | ||
8925 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8926 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8927 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8928 | & ~TU_SIZE_MASK; | |
8929 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8930 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8931 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8932 | } | |
8933 | ||
8934 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8935 | enum transcoder transcoder, | |
b95af8be VK |
8936 | struct intel_link_m_n *m_n, |
8937 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8938 | { |
8939 | struct drm_device *dev = crtc->base.dev; | |
8940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8941 | enum pipe pipe = crtc->pipe; |
72419203 | 8942 | |
eb14cb74 VS |
8943 | if (INTEL_INFO(dev)->gen >= 5) { |
8944 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8945 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8946 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8947 | & ~TU_SIZE_MASK; | |
8948 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8949 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8950 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8951 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8952 | * gen < 8) and if DRRS is supported (to make sure the | |
8953 | * registers are not unnecessarily read). | |
8954 | */ | |
8955 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8956 | crtc->config->has_drrs) { |
b95af8be VK |
8957 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8958 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8959 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8960 | & ~TU_SIZE_MASK; | |
8961 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8962 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8963 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8964 | } | |
eb14cb74 VS |
8965 | } else { |
8966 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8967 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8968 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8969 | & ~TU_SIZE_MASK; | |
8970 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8971 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8972 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8973 | } | |
8974 | } | |
8975 | ||
8976 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8977 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8978 | { |
681a8504 | 8979 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8980 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8981 | else | |
8982 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8983 | &pipe_config->dp_m_n, |
8984 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8985 | } |
72419203 | 8986 | |
eb14cb74 | 8987 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8988 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8989 | { |
8990 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8991 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8992 | } |
8993 | ||
bd2e244f | 8994 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8995 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8996 | { |
8997 | struct drm_device *dev = crtc->base.dev; | |
8998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8999 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9000 | uint32_t ps_ctrl = 0; | |
9001 | int id = -1; | |
9002 | int i; | |
bd2e244f | 9003 | |
a1b2278e CK |
9004 | /* find scaler attached to this pipe */ |
9005 | for (i = 0; i < crtc->num_scalers; i++) { | |
9006 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9007 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9008 | id = i; | |
9009 | pipe_config->pch_pfit.enabled = true; | |
9010 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9011 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9012 | break; | |
9013 | } | |
9014 | } | |
bd2e244f | 9015 | |
a1b2278e CK |
9016 | scaler_state->scaler_id = id; |
9017 | if (id >= 0) { | |
9018 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9019 | } else { | |
9020 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9021 | } |
9022 | } | |
9023 | ||
5724dbd1 DL |
9024 | static void |
9025 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9026 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9027 | { |
9028 | struct drm_device *dev = crtc->base.dev; | |
9029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9030 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9031 | int pipe = crtc->pipe; |
9032 | int fourcc, pixel_format; | |
6761dd31 | 9033 | unsigned int aligned_height; |
bc8d7dff | 9034 | struct drm_framebuffer *fb; |
1b842c89 | 9035 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9036 | |
d9806c9f | 9037 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9038 | if (!intel_fb) { |
bc8d7dff DL |
9039 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9040 | return; | |
9041 | } | |
9042 | ||
1b842c89 DL |
9043 | fb = &intel_fb->base; |
9044 | ||
bc8d7dff | 9045 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9046 | if (!(val & PLANE_CTL_ENABLE)) |
9047 | goto error; | |
9048 | ||
bc8d7dff DL |
9049 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9050 | fourcc = skl_format_to_fourcc(pixel_format, | |
9051 | val & PLANE_CTL_ORDER_RGBX, | |
9052 | val & PLANE_CTL_ALPHA_MASK); | |
9053 | fb->pixel_format = fourcc; | |
9054 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9055 | ||
40f46283 DL |
9056 | tiling = val & PLANE_CTL_TILED_MASK; |
9057 | switch (tiling) { | |
9058 | case PLANE_CTL_TILED_LINEAR: | |
9059 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9060 | break; | |
9061 | case PLANE_CTL_TILED_X: | |
9062 | plane_config->tiling = I915_TILING_X; | |
9063 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9064 | break; | |
9065 | case PLANE_CTL_TILED_Y: | |
9066 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9067 | break; | |
9068 | case PLANE_CTL_TILED_YF: | |
9069 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9070 | break; | |
9071 | default: | |
9072 | MISSING_CASE(tiling); | |
9073 | goto error; | |
9074 | } | |
9075 | ||
bc8d7dff DL |
9076 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9077 | plane_config->base = base; | |
9078 | ||
9079 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9080 | ||
9081 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9082 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9083 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9084 | ||
9085 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9086 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9087 | fb->pixel_format); | |
bc8d7dff DL |
9088 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9089 | ||
9090 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9091 | fb->pixel_format, |
9092 | fb->modifier[0]); | |
bc8d7dff | 9093 | |
f37b5c2b | 9094 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9095 | |
9096 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9097 | pipe_name(pipe), fb->width, fb->height, | |
9098 | fb->bits_per_pixel, base, fb->pitches[0], | |
9099 | plane_config->size); | |
9100 | ||
2d14030b | 9101 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9102 | return; |
9103 | ||
9104 | error: | |
9105 | kfree(fb); | |
9106 | } | |
9107 | ||
2fa2fe9a | 9108 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9109 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9110 | { |
9111 | struct drm_device *dev = crtc->base.dev; | |
9112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9113 | uint32_t tmp; | |
9114 | ||
9115 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9116 | ||
9117 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9118 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9119 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9120 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9121 | |
9122 | /* We currently do not free assignements of panel fitters on | |
9123 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9124 | * differentiates them) so just WARN about this case for now. */ | |
9125 | if (IS_GEN7(dev)) { | |
9126 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9127 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9128 | } | |
2fa2fe9a | 9129 | } |
79e53945 JB |
9130 | } |
9131 | ||
5724dbd1 DL |
9132 | static void |
9133 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9134 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9135 | { |
9136 | struct drm_device *dev = crtc->base.dev; | |
9137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9138 | u32 val, base, offset; | |
aeee5a49 | 9139 | int pipe = crtc->pipe; |
4c6baa59 | 9140 | int fourcc, pixel_format; |
6761dd31 | 9141 | unsigned int aligned_height; |
b113d5ee | 9142 | struct drm_framebuffer *fb; |
1b842c89 | 9143 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9144 | |
42a7b088 DL |
9145 | val = I915_READ(DSPCNTR(pipe)); |
9146 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9147 | return; | |
9148 | ||
d9806c9f | 9149 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9150 | if (!intel_fb) { |
4c6baa59 JB |
9151 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9152 | return; | |
9153 | } | |
9154 | ||
1b842c89 DL |
9155 | fb = &intel_fb->base; |
9156 | ||
18c5247e DV |
9157 | if (INTEL_INFO(dev)->gen >= 4) { |
9158 | if (val & DISPPLANE_TILED) { | |
49af449b | 9159 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9160 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9161 | } | |
9162 | } | |
4c6baa59 JB |
9163 | |
9164 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9165 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9166 | fb->pixel_format = fourcc; |
9167 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9168 | |
aeee5a49 | 9169 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9170 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9171 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9172 | } else { |
49af449b | 9173 | if (plane_config->tiling) |
aeee5a49 | 9174 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9175 | else |
aeee5a49 | 9176 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9177 | } |
9178 | plane_config->base = base; | |
9179 | ||
9180 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9181 | fb->width = ((val >> 16) & 0xfff) + 1; |
9182 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9183 | |
9184 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9185 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9186 | |
b113d5ee | 9187 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9188 | fb->pixel_format, |
9189 | fb->modifier[0]); | |
4c6baa59 | 9190 | |
f37b5c2b | 9191 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9192 | |
2844a921 DL |
9193 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9194 | pipe_name(pipe), fb->width, fb->height, | |
9195 | fb->bits_per_pixel, base, fb->pitches[0], | |
9196 | plane_config->size); | |
b113d5ee | 9197 | |
2d14030b | 9198 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9199 | } |
9200 | ||
0e8ffe1b | 9201 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9202 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9203 | { |
9204 | struct drm_device *dev = crtc->base.dev; | |
9205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9206 | uint32_t tmp; | |
9207 | ||
f458ebbc DV |
9208 | if (!intel_display_power_is_enabled(dev_priv, |
9209 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9210 | return false; |
9211 | ||
e143a21c | 9212 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9213 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9214 | |
0e8ffe1b DV |
9215 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9216 | if (!(tmp & PIPECONF_ENABLE)) | |
9217 | return false; | |
9218 | ||
42571aef VS |
9219 | switch (tmp & PIPECONF_BPC_MASK) { |
9220 | case PIPECONF_6BPC: | |
9221 | pipe_config->pipe_bpp = 18; | |
9222 | break; | |
9223 | case PIPECONF_8BPC: | |
9224 | pipe_config->pipe_bpp = 24; | |
9225 | break; | |
9226 | case PIPECONF_10BPC: | |
9227 | pipe_config->pipe_bpp = 30; | |
9228 | break; | |
9229 | case PIPECONF_12BPC: | |
9230 | pipe_config->pipe_bpp = 36; | |
9231 | break; | |
9232 | default: | |
9233 | break; | |
9234 | } | |
9235 | ||
b5a9fa09 DV |
9236 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9237 | pipe_config->limited_color_range = true; | |
9238 | ||
ab9412ba | 9239 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9240 | struct intel_shared_dpll *pll; |
9241 | ||
88adfff1 DV |
9242 | pipe_config->has_pch_encoder = true; |
9243 | ||
627eb5a3 DV |
9244 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9245 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9246 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9247 | |
9248 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9249 | |
c0d43d62 | 9250 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9251 | pipe_config->shared_dpll = |
9252 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9253 | } else { |
9254 | tmp = I915_READ(PCH_DPLL_SEL); | |
9255 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9256 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9257 | else | |
9258 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9259 | } | |
66e985c0 DV |
9260 | |
9261 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9262 | ||
9263 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9264 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9265 | |
9266 | tmp = pipe_config->dpll_hw_state.dpll; | |
9267 | pipe_config->pixel_multiplier = | |
9268 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9269 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9270 | |
9271 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9272 | } else { |
9273 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9274 | } |
9275 | ||
1bd1bd80 DV |
9276 | intel_get_pipe_timings(crtc, pipe_config); |
9277 | ||
2fa2fe9a DV |
9278 | ironlake_get_pfit_config(crtc, pipe_config); |
9279 | ||
0e8ffe1b DV |
9280 | return true; |
9281 | } | |
9282 | ||
be256dc7 PZ |
9283 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9284 | { | |
9285 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9286 | struct intel_crtc *crtc; |
be256dc7 | 9287 | |
d3fcc808 | 9288 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9289 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9290 | pipe_name(crtc->pipe)); |
9291 | ||
e2c719b7 RC |
9292 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9293 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9294 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9295 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9296 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9297 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9298 | "CPU PWM1 enabled\n"); |
c5107b87 | 9299 | if (IS_HASWELL(dev)) |
e2c719b7 | 9300 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9301 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9302 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9303 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9304 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9305 | "Utility pin enabled\n"); |
e2c719b7 | 9306 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9307 | |
9926ada1 PZ |
9308 | /* |
9309 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9310 | * interrupts remain enabled. We used to check for that, but since it's | |
9311 | * gen-specific and since we only disable LCPLL after we fully disable | |
9312 | * the interrupts, the check below should be enough. | |
9313 | */ | |
e2c719b7 | 9314 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9315 | } |
9316 | ||
9ccd5aeb PZ |
9317 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9318 | { | |
9319 | struct drm_device *dev = dev_priv->dev; | |
9320 | ||
9321 | if (IS_HASWELL(dev)) | |
9322 | return I915_READ(D_COMP_HSW); | |
9323 | else | |
9324 | return I915_READ(D_COMP_BDW); | |
9325 | } | |
9326 | ||
3c4c9b81 PZ |
9327 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9328 | { | |
9329 | struct drm_device *dev = dev_priv->dev; | |
9330 | ||
9331 | if (IS_HASWELL(dev)) { | |
9332 | mutex_lock(&dev_priv->rps.hw_lock); | |
9333 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9334 | val)) | |
f475dadf | 9335 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9336 | mutex_unlock(&dev_priv->rps.hw_lock); |
9337 | } else { | |
9ccd5aeb PZ |
9338 | I915_WRITE(D_COMP_BDW, val); |
9339 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9340 | } |
be256dc7 PZ |
9341 | } |
9342 | ||
9343 | /* | |
9344 | * This function implements pieces of two sequences from BSpec: | |
9345 | * - Sequence for display software to disable LCPLL | |
9346 | * - Sequence for display software to allow package C8+ | |
9347 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9348 | * register. Callers should take care of disabling all the display engine | |
9349 | * functions, doing the mode unset, fixing interrupts, etc. | |
9350 | */ | |
6ff58d53 PZ |
9351 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9352 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9353 | { |
9354 | uint32_t val; | |
9355 | ||
9356 | assert_can_disable_lcpll(dev_priv); | |
9357 | ||
9358 | val = I915_READ(LCPLL_CTL); | |
9359 | ||
9360 | if (switch_to_fclk) { | |
9361 | val |= LCPLL_CD_SOURCE_FCLK; | |
9362 | I915_WRITE(LCPLL_CTL, val); | |
9363 | ||
9364 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9365 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9366 | DRM_ERROR("Switching to FCLK failed\n"); | |
9367 | ||
9368 | val = I915_READ(LCPLL_CTL); | |
9369 | } | |
9370 | ||
9371 | val |= LCPLL_PLL_DISABLE; | |
9372 | I915_WRITE(LCPLL_CTL, val); | |
9373 | POSTING_READ(LCPLL_CTL); | |
9374 | ||
9375 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9376 | DRM_ERROR("LCPLL still locked\n"); | |
9377 | ||
9ccd5aeb | 9378 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9379 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9380 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9381 | ndelay(100); |
9382 | ||
9ccd5aeb PZ |
9383 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9384 | 1)) | |
be256dc7 PZ |
9385 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9386 | ||
9387 | if (allow_power_down) { | |
9388 | val = I915_READ(LCPLL_CTL); | |
9389 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9390 | I915_WRITE(LCPLL_CTL, val); | |
9391 | POSTING_READ(LCPLL_CTL); | |
9392 | } | |
9393 | } | |
9394 | ||
9395 | /* | |
9396 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9397 | * source. | |
9398 | */ | |
6ff58d53 | 9399 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9400 | { |
9401 | uint32_t val; | |
9402 | ||
9403 | val = I915_READ(LCPLL_CTL); | |
9404 | ||
9405 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9406 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9407 | return; | |
9408 | ||
a8a8bd54 PZ |
9409 | /* |
9410 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9411 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9412 | */ |
59bad947 | 9413 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9414 | |
be256dc7 PZ |
9415 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9416 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9417 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9418 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9419 | } |
9420 | ||
9ccd5aeb | 9421 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9422 | val |= D_COMP_COMP_FORCE; |
9423 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9424 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9425 | |
9426 | val = I915_READ(LCPLL_CTL); | |
9427 | val &= ~LCPLL_PLL_DISABLE; | |
9428 | I915_WRITE(LCPLL_CTL, val); | |
9429 | ||
9430 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9431 | DRM_ERROR("LCPLL not locked yet\n"); | |
9432 | ||
9433 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9434 | val = I915_READ(LCPLL_CTL); | |
9435 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9436 | I915_WRITE(LCPLL_CTL, val); | |
9437 | ||
9438 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9439 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9440 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9441 | } | |
215733fa | 9442 | |
59bad947 | 9443 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9444 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9445 | } |
9446 | ||
765dab67 PZ |
9447 | /* |
9448 | * Package states C8 and deeper are really deep PC states that can only be | |
9449 | * reached when all the devices on the system allow it, so even if the graphics | |
9450 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9451 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9452 | * | |
9453 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9454 | * well is disabled and most interrupts are disabled, and these are also | |
9455 | * requirements for runtime PM. When these conditions are met, we manually do | |
9456 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9457 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9458 | * hang the machine. | |
9459 | * | |
9460 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9461 | * the state of some registers, so when we come back from PC8+ we need to | |
9462 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9463 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9464 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9465 | * because of the runtime PM support). | |
9466 | * | |
9467 | * For more, read "Display Sequences for Package C8" on the hardware | |
9468 | * documentation. | |
9469 | */ | |
a14cb6fc | 9470 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9471 | { |
c67a470b PZ |
9472 | struct drm_device *dev = dev_priv->dev; |
9473 | uint32_t val; | |
9474 | ||
c67a470b PZ |
9475 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9476 | ||
c67a470b PZ |
9477 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9478 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9479 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9480 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9481 | } | |
9482 | ||
9483 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9484 | hsw_disable_lcpll(dev_priv, true, true); |
9485 | } | |
9486 | ||
a14cb6fc | 9487 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9488 | { |
9489 | struct drm_device *dev = dev_priv->dev; | |
9490 | uint32_t val; | |
9491 | ||
c67a470b PZ |
9492 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9493 | ||
9494 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9495 | lpt_init_pch_refclk(dev); |
9496 | ||
9497 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9498 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9499 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9500 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9501 | } | |
9502 | ||
9503 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9504 | } |
9505 | ||
27c329ed | 9506 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9507 | { |
a821fc46 | 9508 | struct drm_device *dev = old_state->dev; |
27c329ed | 9509 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
f8437dd1 | 9510 | |
27c329ed | 9511 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9512 | } |
9513 | ||
b432e5cf | 9514 | /* compute the max rate for new configuration */ |
27c329ed | 9515 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9516 | { |
b432e5cf | 9517 | struct intel_crtc *intel_crtc; |
27c329ed | 9518 | struct intel_crtc_state *crtc_state; |
b432e5cf | 9519 | int max_pixel_rate = 0; |
b432e5cf | 9520 | |
27c329ed ML |
9521 | for_each_intel_crtc(state->dev, intel_crtc) { |
9522 | int pixel_rate; | |
9523 | ||
9524 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
9525 | if (IS_ERR(crtc_state)) | |
9526 | return PTR_ERR(crtc_state); | |
9527 | ||
9528 | if (!crtc_state->base.enable) | |
b432e5cf VS |
9529 | continue; |
9530 | ||
27c329ed | 9531 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9532 | |
9533 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
27c329ed | 9534 | if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
b432e5cf VS |
9535 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9536 | ||
9537 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9538 | } | |
9539 | ||
9540 | return max_pixel_rate; | |
9541 | } | |
9542 | ||
9543 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9544 | { | |
9545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9546 | uint32_t val, data; | |
9547 | int ret; | |
9548 | ||
9549 | if (WARN((I915_READ(LCPLL_CTL) & | |
9550 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9551 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9552 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9553 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9554 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9555 | return; | |
9556 | ||
9557 | mutex_lock(&dev_priv->rps.hw_lock); | |
9558 | ret = sandybridge_pcode_write(dev_priv, | |
9559 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9560 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9561 | if (ret) { | |
9562 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9563 | return; | |
9564 | } | |
9565 | ||
9566 | val = I915_READ(LCPLL_CTL); | |
9567 | val |= LCPLL_CD_SOURCE_FCLK; | |
9568 | I915_WRITE(LCPLL_CTL, val); | |
9569 | ||
9570 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9571 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9572 | DRM_ERROR("Switching to FCLK failed\n"); | |
9573 | ||
9574 | val = I915_READ(LCPLL_CTL); | |
9575 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9576 | ||
9577 | switch (cdclk) { | |
9578 | case 450000: | |
9579 | val |= LCPLL_CLK_FREQ_450; | |
9580 | data = 0; | |
9581 | break; | |
9582 | case 540000: | |
9583 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9584 | data = 1; | |
9585 | break; | |
9586 | case 337500: | |
9587 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9588 | data = 2; | |
9589 | break; | |
9590 | case 675000: | |
9591 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9592 | data = 3; | |
9593 | break; | |
9594 | default: | |
9595 | WARN(1, "invalid cdclk frequency\n"); | |
9596 | return; | |
9597 | } | |
9598 | ||
9599 | I915_WRITE(LCPLL_CTL, val); | |
9600 | ||
9601 | val = I915_READ(LCPLL_CTL); | |
9602 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9603 | I915_WRITE(LCPLL_CTL, val); | |
9604 | ||
9605 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9606 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9607 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9608 | ||
9609 | mutex_lock(&dev_priv->rps.hw_lock); | |
9610 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9611 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9612 | ||
9613 | intel_update_cdclk(dev); | |
9614 | ||
9615 | WARN(cdclk != dev_priv->cdclk_freq, | |
9616 | "cdclk requested %d kHz but got %d kHz\n", | |
9617 | cdclk, dev_priv->cdclk_freq); | |
9618 | } | |
9619 | ||
27c329ed | 9620 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9621 | { |
27c329ed ML |
9622 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9623 | int max_pixclk = ilk_max_pixel_rate(state); | |
b432e5cf VS |
9624 | int cdclk; |
9625 | ||
9626 | /* | |
9627 | * FIXME should also account for plane ratio | |
9628 | * once 64bpp pixel formats are supported. | |
9629 | */ | |
27c329ed | 9630 | if (max_pixclk > 540000) |
b432e5cf | 9631 | cdclk = 675000; |
27c329ed | 9632 | else if (max_pixclk > 450000) |
b432e5cf | 9633 | cdclk = 540000; |
27c329ed | 9634 | else if (max_pixclk > 337500) |
b432e5cf VS |
9635 | cdclk = 450000; |
9636 | else | |
9637 | cdclk = 337500; | |
9638 | ||
9639 | /* | |
9640 | * FIXME move the cdclk caclulation to | |
9641 | * compute_config() so we can fail gracegully. | |
9642 | */ | |
9643 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9644 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9645 | cdclk, dev_priv->max_cdclk_freq); | |
9646 | cdclk = dev_priv->max_cdclk_freq; | |
9647 | } | |
9648 | ||
27c329ed | 9649 | to_intel_atomic_state(state)->cdclk = cdclk; |
b432e5cf VS |
9650 | |
9651 | return 0; | |
9652 | } | |
9653 | ||
27c329ed | 9654 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9655 | { |
27c329ed ML |
9656 | struct drm_device *dev = old_state->dev; |
9657 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; | |
b432e5cf | 9658 | |
27c329ed | 9659 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9660 | } |
9661 | ||
190f68c5 ACO |
9662 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9663 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9664 | { |
190f68c5 | 9665 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9666 | return -EINVAL; |
716c2e55 | 9667 | |
c7653199 | 9668 | crtc->lowfreq_avail = false; |
644cef34 | 9669 | |
c8f7a0db | 9670 | return 0; |
79e53945 JB |
9671 | } |
9672 | ||
3760b59c S |
9673 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9674 | enum port port, | |
9675 | struct intel_crtc_state *pipe_config) | |
9676 | { | |
9677 | switch (port) { | |
9678 | case PORT_A: | |
9679 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9680 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9681 | break; | |
9682 | case PORT_B: | |
9683 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9684 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9685 | break; | |
9686 | case PORT_C: | |
9687 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9688 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9689 | break; | |
9690 | default: | |
9691 | DRM_ERROR("Incorrect port type\n"); | |
9692 | } | |
9693 | } | |
9694 | ||
96b7dfb7 S |
9695 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9696 | enum port port, | |
5cec258b | 9697 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9698 | { |
3148ade7 | 9699 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9700 | |
9701 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9702 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9703 | ||
9704 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9705 | case SKL_DPLL0: |
9706 | /* | |
9707 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9708 | * of the shared DPLL framework and thus needs to be read out | |
9709 | * separately | |
9710 | */ | |
9711 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9712 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9713 | break; | |
96b7dfb7 S |
9714 | case SKL_DPLL1: |
9715 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9716 | break; | |
9717 | case SKL_DPLL2: | |
9718 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9719 | break; | |
9720 | case SKL_DPLL3: | |
9721 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9722 | break; | |
96b7dfb7 S |
9723 | } |
9724 | } | |
9725 | ||
7d2c8175 DL |
9726 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9727 | enum port port, | |
5cec258b | 9728 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9729 | { |
9730 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9731 | ||
9732 | switch (pipe_config->ddi_pll_sel) { | |
9733 | case PORT_CLK_SEL_WRPLL1: | |
9734 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9735 | break; | |
9736 | case PORT_CLK_SEL_WRPLL2: | |
9737 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9738 | break; | |
9739 | } | |
9740 | } | |
9741 | ||
26804afd | 9742 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9743 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9744 | { |
9745 | struct drm_device *dev = crtc->base.dev; | |
9746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9747 | struct intel_shared_dpll *pll; |
26804afd DV |
9748 | enum port port; |
9749 | uint32_t tmp; | |
9750 | ||
9751 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9752 | ||
9753 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9754 | ||
96b7dfb7 S |
9755 | if (IS_SKYLAKE(dev)) |
9756 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9757 | else if (IS_BROXTON(dev)) |
9758 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9759 | else |
9760 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9761 | |
d452c5b6 DV |
9762 | if (pipe_config->shared_dpll >= 0) { |
9763 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9764 | ||
9765 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9766 | &pipe_config->dpll_hw_state)); | |
9767 | } | |
9768 | ||
26804afd DV |
9769 | /* |
9770 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9771 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9772 | * the PCH transcoder is on. | |
9773 | */ | |
ca370455 DL |
9774 | if (INTEL_INFO(dev)->gen < 9 && |
9775 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9776 | pipe_config->has_pch_encoder = true; |
9777 | ||
9778 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9779 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9780 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9781 | ||
9782 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9783 | } | |
9784 | } | |
9785 | ||
0e8ffe1b | 9786 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9787 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9788 | { |
9789 | struct drm_device *dev = crtc->base.dev; | |
9790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9791 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9792 | uint32_t tmp; |
9793 | ||
f458ebbc | 9794 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9795 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9796 | return false; | |
9797 | ||
e143a21c | 9798 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9799 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9800 | ||
eccb140b DV |
9801 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9802 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9803 | enum pipe trans_edp_pipe; | |
9804 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9805 | default: | |
9806 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9807 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9808 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9809 | trans_edp_pipe = PIPE_A; | |
9810 | break; | |
9811 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9812 | trans_edp_pipe = PIPE_B; | |
9813 | break; | |
9814 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9815 | trans_edp_pipe = PIPE_C; | |
9816 | break; | |
9817 | } | |
9818 | ||
9819 | if (trans_edp_pipe == crtc->pipe) | |
9820 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9821 | } | |
9822 | ||
f458ebbc | 9823 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9824 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9825 | return false; |
9826 | ||
eccb140b | 9827 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9828 | if (!(tmp & PIPECONF_ENABLE)) |
9829 | return false; | |
9830 | ||
26804afd | 9831 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9832 | |
1bd1bd80 DV |
9833 | intel_get_pipe_timings(crtc, pipe_config); |
9834 | ||
a1b2278e CK |
9835 | if (INTEL_INFO(dev)->gen >= 9) { |
9836 | skl_init_scalers(dev, crtc, pipe_config); | |
9837 | } | |
9838 | ||
2fa2fe9a | 9839 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9840 | |
9841 | if (INTEL_INFO(dev)->gen >= 9) { | |
9842 | pipe_config->scaler_state.scaler_id = -1; | |
9843 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9844 | } | |
9845 | ||
bd2e244f | 9846 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9847 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9848 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9849 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9850 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9851 | else |
9852 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
bd2e244f | 9853 | } |
88adfff1 | 9854 | |
e59150dc JB |
9855 | if (IS_HASWELL(dev)) |
9856 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9857 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9858 | |
ebb69c95 CT |
9859 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9860 | pipe_config->pixel_multiplier = | |
9861 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9862 | } else { | |
9863 | pipe_config->pixel_multiplier = 1; | |
9864 | } | |
6c49f241 | 9865 | |
0e8ffe1b DV |
9866 | return true; |
9867 | } | |
9868 | ||
560b85bb CW |
9869 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9870 | { | |
9871 | struct drm_device *dev = crtc->dev; | |
9872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9874 | uint32_t cntl = 0, size = 0; |
560b85bb | 9875 | |
dc41c154 | 9876 | if (base) { |
3dd512fb MR |
9877 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9878 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9879 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9880 | ||
9881 | switch (stride) { | |
9882 | default: | |
9883 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9884 | width, stride); | |
9885 | stride = 256; | |
9886 | /* fallthrough */ | |
9887 | case 256: | |
9888 | case 512: | |
9889 | case 1024: | |
9890 | case 2048: | |
9891 | break; | |
4b0e333e CW |
9892 | } |
9893 | ||
dc41c154 VS |
9894 | cntl |= CURSOR_ENABLE | |
9895 | CURSOR_GAMMA_ENABLE | | |
9896 | CURSOR_FORMAT_ARGB | | |
9897 | CURSOR_STRIDE(stride); | |
9898 | ||
9899 | size = (height << 12) | width; | |
4b0e333e | 9900 | } |
560b85bb | 9901 | |
dc41c154 VS |
9902 | if (intel_crtc->cursor_cntl != 0 && |
9903 | (intel_crtc->cursor_base != base || | |
9904 | intel_crtc->cursor_size != size || | |
9905 | intel_crtc->cursor_cntl != cntl)) { | |
9906 | /* On these chipsets we can only modify the base/size/stride | |
9907 | * whilst the cursor is disabled. | |
9908 | */ | |
9909 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9910 | POSTING_READ(_CURACNTR); |
dc41c154 | 9911 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9912 | } |
560b85bb | 9913 | |
99d1f387 | 9914 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9915 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9916 | intel_crtc->cursor_base = base; |
9917 | } | |
4726e0b0 | 9918 | |
dc41c154 VS |
9919 | if (intel_crtc->cursor_size != size) { |
9920 | I915_WRITE(CURSIZE, size); | |
9921 | intel_crtc->cursor_size = size; | |
4b0e333e | 9922 | } |
560b85bb | 9923 | |
4b0e333e | 9924 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9925 | I915_WRITE(_CURACNTR, cntl); |
9926 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9927 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9928 | } |
560b85bb CW |
9929 | } |
9930 | ||
560b85bb | 9931 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9932 | { |
9933 | struct drm_device *dev = crtc->dev; | |
9934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9936 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9937 | uint32_t cntl; |
9938 | ||
9939 | cntl = 0; | |
9940 | if (base) { | |
9941 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9942 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9943 | case 64: |
9944 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9945 | break; | |
9946 | case 128: | |
9947 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9948 | break; | |
9949 | case 256: | |
9950 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9951 | break; | |
9952 | default: | |
3dd512fb | 9953 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9954 | return; |
65a21cd6 | 9955 | } |
4b0e333e | 9956 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9957 | |
9958 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9959 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9960 | } |
65a21cd6 | 9961 | |
8e7d688b | 9962 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9963 | cntl |= CURSOR_ROTATE_180; |
9964 | ||
4b0e333e CW |
9965 | if (intel_crtc->cursor_cntl != cntl) { |
9966 | I915_WRITE(CURCNTR(pipe), cntl); | |
9967 | POSTING_READ(CURCNTR(pipe)); | |
9968 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9969 | } |
4b0e333e | 9970 | |
65a21cd6 | 9971 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9972 | I915_WRITE(CURBASE(pipe), base); |
9973 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9974 | |
9975 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9976 | } |
9977 | ||
cda4b7d3 | 9978 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9979 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9980 | bool on) | |
cda4b7d3 CW |
9981 | { |
9982 | struct drm_device *dev = crtc->dev; | |
9983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9984 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9985 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9986 | int x = crtc->cursor_x; |
9987 | int y = crtc->cursor_y; | |
d6e4db15 | 9988 | u32 base = 0, pos = 0; |
cda4b7d3 | 9989 | |
d6e4db15 | 9990 | if (on) |
cda4b7d3 | 9991 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9992 | |
6e3c9717 | 9993 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9994 | base = 0; |
9995 | ||
6e3c9717 | 9996 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9997 | base = 0; |
9998 | ||
9999 | if (x < 0) { | |
3dd512fb | 10000 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
10001 | base = 0; |
10002 | ||
10003 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10004 | x = -x; | |
10005 | } | |
10006 | pos |= x << CURSOR_X_SHIFT; | |
10007 | ||
10008 | if (y < 0) { | |
3dd512fb | 10009 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
10010 | base = 0; |
10011 | ||
10012 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10013 | y = -y; | |
10014 | } | |
10015 | pos |= y << CURSOR_Y_SHIFT; | |
10016 | ||
4b0e333e | 10017 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
10018 | return; |
10019 | ||
5efb3e28 VS |
10020 | I915_WRITE(CURPOS(pipe), pos); |
10021 | ||
4398ad45 VS |
10022 | /* ILK+ do this automagically */ |
10023 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10024 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
10025 | base += (intel_crtc->base.cursor->state->crtc_h * |
10026 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
10027 | } |
10028 | ||
8ac54669 | 10029 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
10030 | i845_update_cursor(crtc, base); |
10031 | else | |
10032 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
10033 | } |
10034 | ||
dc41c154 VS |
10035 | static bool cursor_size_ok(struct drm_device *dev, |
10036 | uint32_t width, uint32_t height) | |
10037 | { | |
10038 | if (width == 0 || height == 0) | |
10039 | return false; | |
10040 | ||
10041 | /* | |
10042 | * 845g/865g are special in that they are only limited by | |
10043 | * the width of their cursors, the height is arbitrary up to | |
10044 | * the precision of the register. Everything else requires | |
10045 | * square cursors, limited to a few power-of-two sizes. | |
10046 | */ | |
10047 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10048 | if ((width & 63) != 0) | |
10049 | return false; | |
10050 | ||
10051 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10052 | return false; | |
10053 | ||
10054 | if (height > 1023) | |
10055 | return false; | |
10056 | } else { | |
10057 | switch (width | height) { | |
10058 | case 256: | |
10059 | case 128: | |
10060 | if (IS_GEN2(dev)) | |
10061 | return false; | |
10062 | case 64: | |
10063 | break; | |
10064 | default: | |
10065 | return false; | |
10066 | } | |
10067 | } | |
10068 | ||
10069 | return true; | |
10070 | } | |
10071 | ||
79e53945 | 10072 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10073 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10074 | { |
7203425a | 10075 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10076 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10077 | |
7203425a | 10078 | for (i = start; i < end; i++) { |
79e53945 JB |
10079 | intel_crtc->lut_r[i] = red[i] >> 8; |
10080 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10081 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10082 | } | |
10083 | ||
10084 | intel_crtc_load_lut(crtc); | |
10085 | } | |
10086 | ||
79e53945 JB |
10087 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10088 | static struct drm_display_mode load_detect_mode = { | |
10089 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10090 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10091 | }; | |
10092 | ||
a8bb6818 DV |
10093 | struct drm_framebuffer * |
10094 | __intel_framebuffer_create(struct drm_device *dev, | |
10095 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10096 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10097 | { |
10098 | struct intel_framebuffer *intel_fb; | |
10099 | int ret; | |
10100 | ||
10101 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
10102 | if (!intel_fb) { | |
6ccb81f2 | 10103 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
10104 | return ERR_PTR(-ENOMEM); |
10105 | } | |
10106 | ||
10107 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10108 | if (ret) |
10109 | goto err; | |
d2dff872 CW |
10110 | |
10111 | return &intel_fb->base; | |
dd4916c5 | 10112 | err: |
6ccb81f2 | 10113 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
10114 | kfree(intel_fb); |
10115 | ||
10116 | return ERR_PTR(ret); | |
d2dff872 CW |
10117 | } |
10118 | ||
b5ea642a | 10119 | static struct drm_framebuffer * |
a8bb6818 DV |
10120 | intel_framebuffer_create(struct drm_device *dev, |
10121 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10122 | struct drm_i915_gem_object *obj) | |
10123 | { | |
10124 | struct drm_framebuffer *fb; | |
10125 | int ret; | |
10126 | ||
10127 | ret = i915_mutex_lock_interruptible(dev); | |
10128 | if (ret) | |
10129 | return ERR_PTR(ret); | |
10130 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10131 | mutex_unlock(&dev->struct_mutex); | |
10132 | ||
10133 | return fb; | |
10134 | } | |
10135 | ||
d2dff872 CW |
10136 | static u32 |
10137 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10138 | { | |
10139 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10140 | return ALIGN(pitch, 64); | |
10141 | } | |
10142 | ||
10143 | static u32 | |
10144 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10145 | { | |
10146 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10147 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10148 | } |
10149 | ||
10150 | static struct drm_framebuffer * | |
10151 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10152 | struct drm_display_mode *mode, | |
10153 | int depth, int bpp) | |
10154 | { | |
10155 | struct drm_i915_gem_object *obj; | |
0fed39bd | 10156 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10157 | |
10158 | obj = i915_gem_alloc_object(dev, | |
10159 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10160 | if (obj == NULL) | |
10161 | return ERR_PTR(-ENOMEM); | |
10162 | ||
10163 | mode_cmd.width = mode->hdisplay; | |
10164 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10165 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10166 | bpp); | |
5ca0c34a | 10167 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
10168 | |
10169 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
10170 | } | |
10171 | ||
10172 | static struct drm_framebuffer * | |
10173 | mode_fits_in_fbdev(struct drm_device *dev, | |
10174 | struct drm_display_mode *mode) | |
10175 | { | |
4520f53a | 10176 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
10177 | struct drm_i915_private *dev_priv = dev->dev_private; |
10178 | struct drm_i915_gem_object *obj; | |
10179 | struct drm_framebuffer *fb; | |
10180 | ||
4c0e5528 | 10181 | if (!dev_priv->fbdev) |
d2dff872 CW |
10182 | return NULL; |
10183 | ||
4c0e5528 | 10184 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10185 | return NULL; |
10186 | ||
4c0e5528 DV |
10187 | obj = dev_priv->fbdev->fb->obj; |
10188 | BUG_ON(!obj); | |
10189 | ||
8bcd4553 | 10190 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10191 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10192 | fb->bits_per_pixel)) | |
d2dff872 CW |
10193 | return NULL; |
10194 | ||
01f2c773 | 10195 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10196 | return NULL; |
10197 | ||
10198 | return fb; | |
4520f53a DV |
10199 | #else |
10200 | return NULL; | |
10201 | #endif | |
d2dff872 CW |
10202 | } |
10203 | ||
d3a40d1b ACO |
10204 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10205 | struct drm_crtc *crtc, | |
10206 | struct drm_display_mode *mode, | |
10207 | struct drm_framebuffer *fb, | |
10208 | int x, int y) | |
10209 | { | |
10210 | struct drm_plane_state *plane_state; | |
10211 | int hdisplay, vdisplay; | |
10212 | int ret; | |
10213 | ||
10214 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10215 | if (IS_ERR(plane_state)) | |
10216 | return PTR_ERR(plane_state); | |
10217 | ||
10218 | if (mode) | |
10219 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10220 | else | |
10221 | hdisplay = vdisplay = 0; | |
10222 | ||
10223 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10224 | if (ret) | |
10225 | return ret; | |
10226 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10227 | plane_state->crtc_x = 0; | |
10228 | plane_state->crtc_y = 0; | |
10229 | plane_state->crtc_w = hdisplay; | |
10230 | plane_state->crtc_h = vdisplay; | |
10231 | plane_state->src_x = x << 16; | |
10232 | plane_state->src_y = y << 16; | |
10233 | plane_state->src_w = hdisplay << 16; | |
10234 | plane_state->src_h = vdisplay << 16; | |
10235 | ||
10236 | return 0; | |
10237 | } | |
10238 | ||
d2434ab7 | 10239 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10240 | struct drm_display_mode *mode, |
51fd371b RC |
10241 | struct intel_load_detect_pipe *old, |
10242 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10243 | { |
10244 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10245 | struct intel_encoder *intel_encoder = |
10246 | intel_attached_encoder(connector); | |
79e53945 | 10247 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10248 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10249 | struct drm_crtc *crtc = NULL; |
10250 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10251 | struct drm_framebuffer *fb; |
51fd371b | 10252 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10253 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10254 | struct drm_connector_state *connector_state; |
4be07317 | 10255 | struct intel_crtc_state *crtc_state; |
51fd371b | 10256 | int ret, i = -1; |
79e53945 | 10257 | |
d2dff872 | 10258 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10259 | connector->base.id, connector->name, |
8e329a03 | 10260 | encoder->base.id, encoder->name); |
d2dff872 | 10261 | |
51fd371b RC |
10262 | retry: |
10263 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10264 | if (ret) | |
ad3c558f | 10265 | goto fail; |
6e9f798d | 10266 | |
79e53945 JB |
10267 | /* |
10268 | * Algorithm gets a little messy: | |
7a5e4805 | 10269 | * |
79e53945 JB |
10270 | * - if the connector already has an assigned crtc, use it (but make |
10271 | * sure it's on first) | |
7a5e4805 | 10272 | * |
79e53945 JB |
10273 | * - try to find the first unused crtc that can drive this connector, |
10274 | * and use that if we find one | |
79e53945 JB |
10275 | */ |
10276 | ||
10277 | /* See if we already have a CRTC for this connector */ | |
10278 | if (encoder->crtc) { | |
10279 | crtc = encoder->crtc; | |
8261b191 | 10280 | |
51fd371b | 10281 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10282 | if (ret) |
ad3c558f | 10283 | goto fail; |
4d02e2de | 10284 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10285 | if (ret) |
ad3c558f | 10286 | goto fail; |
7b24056b | 10287 | |
24218aac | 10288 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10289 | old->load_detect_temp = false; |
10290 | ||
10291 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10292 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10293 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10294 | |
7173188d | 10295 | return true; |
79e53945 JB |
10296 | } |
10297 | ||
10298 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10299 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10300 | i++; |
10301 | if (!(encoder->possible_crtcs & (1 << i))) | |
10302 | continue; | |
83d65738 | 10303 | if (possible_crtc->state->enable) |
a459249c | 10304 | continue; |
a459249c VS |
10305 | |
10306 | crtc = possible_crtc; | |
10307 | break; | |
79e53945 JB |
10308 | } |
10309 | ||
10310 | /* | |
10311 | * If we didn't find an unused CRTC, don't use any. | |
10312 | */ | |
10313 | if (!crtc) { | |
7173188d | 10314 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10315 | goto fail; |
79e53945 JB |
10316 | } |
10317 | ||
51fd371b RC |
10318 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10319 | if (ret) | |
ad3c558f | 10320 | goto fail; |
4d02e2de DV |
10321 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10322 | if (ret) | |
ad3c558f | 10323 | goto fail; |
79e53945 JB |
10324 | |
10325 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10326 | old->dpms_mode = connector->dpms; |
8261b191 | 10327 | old->load_detect_temp = true; |
d2dff872 | 10328 | old->release_fb = NULL; |
79e53945 | 10329 | |
83a57153 ACO |
10330 | state = drm_atomic_state_alloc(dev); |
10331 | if (!state) | |
10332 | return false; | |
10333 | ||
10334 | state->acquire_ctx = ctx; | |
10335 | ||
944b0c76 ACO |
10336 | connector_state = drm_atomic_get_connector_state(state, connector); |
10337 | if (IS_ERR(connector_state)) { | |
10338 | ret = PTR_ERR(connector_state); | |
10339 | goto fail; | |
10340 | } | |
10341 | ||
10342 | connector_state->crtc = crtc; | |
10343 | connector_state->best_encoder = &intel_encoder->base; | |
10344 | ||
4be07317 ACO |
10345 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10346 | if (IS_ERR(crtc_state)) { | |
10347 | ret = PTR_ERR(crtc_state); | |
10348 | goto fail; | |
10349 | } | |
10350 | ||
49d6fa21 | 10351 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10352 | |
6492711d CW |
10353 | if (!mode) |
10354 | mode = &load_detect_mode; | |
79e53945 | 10355 | |
d2dff872 CW |
10356 | /* We need a framebuffer large enough to accommodate all accesses |
10357 | * that the plane may generate whilst we perform load detection. | |
10358 | * We can not rely on the fbcon either being present (we get called | |
10359 | * during its initialisation to detect all boot displays, or it may | |
10360 | * not even exist) or that it is large enough to satisfy the | |
10361 | * requested mode. | |
10362 | */ | |
94352cf9 DV |
10363 | fb = mode_fits_in_fbdev(dev, mode); |
10364 | if (fb == NULL) { | |
d2dff872 | 10365 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10366 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10367 | old->release_fb = fb; | |
d2dff872 CW |
10368 | } else |
10369 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10370 | if (IS_ERR(fb)) { |
d2dff872 | 10371 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10372 | goto fail; |
79e53945 | 10373 | } |
79e53945 | 10374 | |
d3a40d1b ACO |
10375 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10376 | if (ret) | |
10377 | goto fail; | |
10378 | ||
8c7b5ccb ACO |
10379 | drm_mode_copy(&crtc_state->base.mode, mode); |
10380 | ||
568c634a | 10381 | if (intel_set_mode(state)) { |
6492711d | 10382 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10383 | if (old->release_fb) |
10384 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10385 | goto fail; |
79e53945 | 10386 | } |
9128b040 | 10387 | crtc->primary->crtc = crtc; |
7173188d | 10388 | |
79e53945 | 10389 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10390 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10391 | return true; |
412b61d8 | 10392 | |
ad3c558f | 10393 | fail: |
e5d958ef ACO |
10394 | drm_atomic_state_free(state); |
10395 | state = NULL; | |
83a57153 | 10396 | |
51fd371b RC |
10397 | if (ret == -EDEADLK) { |
10398 | drm_modeset_backoff(ctx); | |
10399 | goto retry; | |
10400 | } | |
10401 | ||
412b61d8 | 10402 | return false; |
79e53945 JB |
10403 | } |
10404 | ||
d2434ab7 | 10405 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10406 | struct intel_load_detect_pipe *old, |
10407 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10408 | { |
83a57153 | 10409 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10410 | struct intel_encoder *intel_encoder = |
10411 | intel_attached_encoder(connector); | |
4ef69c7a | 10412 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10413 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10415 | struct drm_atomic_state *state; |
944b0c76 | 10416 | struct drm_connector_state *connector_state; |
4be07317 | 10417 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10418 | int ret; |
79e53945 | 10419 | |
d2dff872 | 10420 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10421 | connector->base.id, connector->name, |
8e329a03 | 10422 | encoder->base.id, encoder->name); |
d2dff872 | 10423 | |
8261b191 | 10424 | if (old->load_detect_temp) { |
83a57153 | 10425 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10426 | if (!state) |
10427 | goto fail; | |
83a57153 ACO |
10428 | |
10429 | state->acquire_ctx = ctx; | |
10430 | ||
944b0c76 ACO |
10431 | connector_state = drm_atomic_get_connector_state(state, connector); |
10432 | if (IS_ERR(connector_state)) | |
10433 | goto fail; | |
10434 | ||
4be07317 ACO |
10435 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10436 | if (IS_ERR(crtc_state)) | |
10437 | goto fail; | |
10438 | ||
944b0c76 ACO |
10439 | connector_state->best_encoder = NULL; |
10440 | connector_state->crtc = NULL; | |
10441 | ||
49d6fa21 | 10442 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10443 | |
d3a40d1b ACO |
10444 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10445 | 0, 0); | |
10446 | if (ret) | |
10447 | goto fail; | |
10448 | ||
568c634a | 10449 | ret = intel_set_mode(state); |
2bfb4627 ACO |
10450 | if (ret) |
10451 | goto fail; | |
d2dff872 | 10452 | |
36206361 DV |
10453 | if (old->release_fb) { |
10454 | drm_framebuffer_unregister_private(old->release_fb); | |
10455 | drm_framebuffer_unreference(old->release_fb); | |
10456 | } | |
d2dff872 | 10457 | |
0622a53c | 10458 | return; |
79e53945 JB |
10459 | } |
10460 | ||
c751ce4f | 10461 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10462 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10463 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10464 | |
10465 | return; | |
10466 | fail: | |
10467 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10468 | drm_atomic_state_free(state); | |
79e53945 JB |
10469 | } |
10470 | ||
da4a1efa | 10471 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10472 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10473 | { |
10474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10475 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10476 | ||
10477 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10478 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10479 | else if (HAS_PCH_SPLIT(dev)) |
10480 | return 120000; | |
10481 | else if (!IS_GEN2(dev)) | |
10482 | return 96000; | |
10483 | else | |
10484 | return 48000; | |
10485 | } | |
10486 | ||
79e53945 | 10487 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10488 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10489 | struct intel_crtc_state *pipe_config) |
79e53945 | 10490 | { |
f1f644dc | 10491 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10492 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10493 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10494 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10495 | u32 fp; |
10496 | intel_clock_t clock; | |
dccbea3b | 10497 | int port_clock; |
da4a1efa | 10498 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10499 | |
10500 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10501 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10502 | else |
293623f7 | 10503 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10504 | |
10505 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10506 | if (IS_PINEVIEW(dev)) { |
10507 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10508 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10509 | } else { |
10510 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10511 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10512 | } | |
10513 | ||
a6c45cf0 | 10514 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10515 | if (IS_PINEVIEW(dev)) |
10516 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10517 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10518 | else |
10519 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10520 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10521 | ||
10522 | switch (dpll & DPLL_MODE_MASK) { | |
10523 | case DPLLB_MODE_DAC_SERIAL: | |
10524 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10525 | 5 : 10; | |
10526 | break; | |
10527 | case DPLLB_MODE_LVDS: | |
10528 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10529 | 7 : 14; | |
10530 | break; | |
10531 | default: | |
28c97730 | 10532 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10533 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10534 | return; |
79e53945 JB |
10535 | } |
10536 | ||
ac58c3f0 | 10537 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10538 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10539 | else |
dccbea3b | 10540 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10541 | } else { |
0fb58223 | 10542 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10543 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10544 | |
10545 | if (is_lvds) { | |
10546 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10547 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10548 | |
10549 | if (lvds & LVDS_CLKB_POWER_UP) | |
10550 | clock.p2 = 7; | |
10551 | else | |
10552 | clock.p2 = 14; | |
79e53945 JB |
10553 | } else { |
10554 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10555 | clock.p1 = 2; | |
10556 | else { | |
10557 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10558 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10559 | } | |
10560 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10561 | clock.p2 = 4; | |
10562 | else | |
10563 | clock.p2 = 2; | |
79e53945 | 10564 | } |
da4a1efa | 10565 | |
dccbea3b | 10566 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10567 | } |
10568 | ||
18442d08 VS |
10569 | /* |
10570 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10571 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10572 | * encoder's get_config() function. |
10573 | */ | |
dccbea3b | 10574 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10575 | } |
10576 | ||
6878da05 VS |
10577 | int intel_dotclock_calculate(int link_freq, |
10578 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10579 | { |
f1f644dc JB |
10580 | /* |
10581 | * The calculation for the data clock is: | |
1041a02f | 10582 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10583 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10584 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10585 | * |
10586 | * and the link clock is simpler: | |
1041a02f | 10587 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10588 | */ |
10589 | ||
6878da05 VS |
10590 | if (!m_n->link_n) |
10591 | return 0; | |
f1f644dc | 10592 | |
6878da05 VS |
10593 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10594 | } | |
f1f644dc | 10595 | |
18442d08 | 10596 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10597 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10598 | { |
10599 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10600 | |
18442d08 VS |
10601 | /* read out port_clock from the DPLL */ |
10602 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10603 | |
f1f644dc | 10604 | /* |
18442d08 | 10605 | * This value does not include pixel_multiplier. |
241bfc38 | 10606 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10607 | * agree once we know their relationship in the encoder's |
10608 | * get_config() function. | |
79e53945 | 10609 | */ |
2d112de7 | 10610 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10611 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10612 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10613 | } |
10614 | ||
10615 | /** Returns the currently programmed mode of the given pipe. */ | |
10616 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10617 | struct drm_crtc *crtc) | |
10618 | { | |
548f245b | 10619 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10621 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10622 | struct drm_display_mode *mode; |
5cec258b | 10623 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10624 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10625 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10626 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10627 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10628 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10629 | |
10630 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10631 | if (!mode) | |
10632 | return NULL; | |
10633 | ||
f1f644dc JB |
10634 | /* |
10635 | * Construct a pipe_config sufficient for getting the clock info | |
10636 | * back out of crtc_clock_get. | |
10637 | * | |
10638 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10639 | * to use a real value here instead. | |
10640 | */ | |
293623f7 | 10641 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10642 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10643 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10644 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10645 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10646 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10647 | ||
773ae034 | 10648 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10649 | mode->hdisplay = (htot & 0xffff) + 1; |
10650 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10651 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10652 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10653 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10654 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10655 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10656 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10657 | ||
10658 | drm_mode_set_name(mode); | |
79e53945 JB |
10659 | |
10660 | return mode; | |
10661 | } | |
10662 | ||
f047e395 CW |
10663 | void intel_mark_busy(struct drm_device *dev) |
10664 | { | |
c67a470b PZ |
10665 | struct drm_i915_private *dev_priv = dev->dev_private; |
10666 | ||
f62a0076 CW |
10667 | if (dev_priv->mm.busy) |
10668 | return; | |
10669 | ||
43694d69 | 10670 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10671 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10672 | if (INTEL_INFO(dev)->gen >= 6) |
10673 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10674 | dev_priv->mm.busy = true; |
f047e395 CW |
10675 | } |
10676 | ||
10677 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10678 | { |
c67a470b | 10679 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10680 | |
f62a0076 CW |
10681 | if (!dev_priv->mm.busy) |
10682 | return; | |
10683 | ||
10684 | dev_priv->mm.busy = false; | |
10685 | ||
3d13ef2e | 10686 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10687 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10688 | |
43694d69 | 10689 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10690 | } |
10691 | ||
79e53945 JB |
10692 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10693 | { | |
10694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10695 | struct drm_device *dev = crtc->dev; |
10696 | struct intel_unpin_work *work; | |
67e77c5a | 10697 | |
5e2d7afc | 10698 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10699 | work = intel_crtc->unpin_work; |
10700 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10701 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10702 | |
10703 | if (work) { | |
10704 | cancel_work_sync(&work->work); | |
10705 | kfree(work); | |
10706 | } | |
79e53945 JB |
10707 | |
10708 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10709 | |
79e53945 JB |
10710 | kfree(intel_crtc); |
10711 | } | |
10712 | ||
6b95a207 KH |
10713 | static void intel_unpin_work_fn(struct work_struct *__work) |
10714 | { | |
10715 | struct intel_unpin_work *work = | |
10716 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10717 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10718 | struct drm_device *dev = crtc->base.dev; | |
7733b49b | 10719 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9ff8714 | 10720 | struct drm_plane *primary = crtc->base.primary; |
6b95a207 | 10721 | |
b4a98e57 | 10722 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10723 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10724 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10725 | |
7733b49b | 10726 | intel_fbc_update(dev_priv); |
f06cc1b9 JH |
10727 | |
10728 | if (work->flip_queued_req) | |
146d84f0 | 10729 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10730 | mutex_unlock(&dev->struct_mutex); |
10731 | ||
a9ff8714 | 10732 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10733 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10734 | |
a9ff8714 VS |
10735 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10736 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10737 | |
6b95a207 KH |
10738 | kfree(work); |
10739 | } | |
10740 | ||
1afe3e9d | 10741 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10742 | struct drm_crtc *crtc) |
6b95a207 | 10743 | { |
6b95a207 KH |
10744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10745 | struct intel_unpin_work *work; | |
6b95a207 KH |
10746 | unsigned long flags; |
10747 | ||
10748 | /* Ignore early vblank irqs */ | |
10749 | if (intel_crtc == NULL) | |
10750 | return; | |
10751 | ||
f326038a DV |
10752 | /* |
10753 | * This is called both by irq handlers and the reset code (to complete | |
10754 | * lost pageflips) so needs the full irqsave spinlocks. | |
10755 | */ | |
6b95a207 KH |
10756 | spin_lock_irqsave(&dev->event_lock, flags); |
10757 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10758 | |
10759 | /* Ensure we don't miss a work->pending update ... */ | |
10760 | smp_rmb(); | |
10761 | ||
10762 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10763 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10764 | return; | |
10765 | } | |
10766 | ||
d6bbafa1 | 10767 | page_flip_completed(intel_crtc); |
0af7e4df | 10768 | |
6b95a207 | 10769 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10770 | } |
10771 | ||
1afe3e9d JB |
10772 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10773 | { | |
fbee40df | 10774 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10775 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10776 | ||
49b14a5c | 10777 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10778 | } |
10779 | ||
10780 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10781 | { | |
fbee40df | 10782 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10783 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10784 | ||
49b14a5c | 10785 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10786 | } |
10787 | ||
75f7f3ec VS |
10788 | /* Is 'a' after or equal to 'b'? */ |
10789 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10790 | { | |
10791 | return !((a - b) & 0x80000000); | |
10792 | } | |
10793 | ||
10794 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10795 | { | |
10796 | struct drm_device *dev = crtc->base.dev; | |
10797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10798 | ||
bdfa7542 VS |
10799 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10800 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10801 | return true; | |
10802 | ||
75f7f3ec VS |
10803 | /* |
10804 | * The relevant registers doen't exist on pre-ctg. | |
10805 | * As the flip done interrupt doesn't trigger for mmio | |
10806 | * flips on gmch platforms, a flip count check isn't | |
10807 | * really needed there. But since ctg has the registers, | |
10808 | * include it in the check anyway. | |
10809 | */ | |
10810 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10811 | return true; | |
10812 | ||
10813 | /* | |
10814 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10815 | * used the same base address. In that case the mmio flip might | |
10816 | * have completed, but the CS hasn't even executed the flip yet. | |
10817 | * | |
10818 | * A flip count check isn't enough as the CS might have updated | |
10819 | * the base address just after start of vblank, but before we | |
10820 | * managed to process the interrupt. This means we'd complete the | |
10821 | * CS flip too soon. | |
10822 | * | |
10823 | * Combining both checks should get us a good enough result. It may | |
10824 | * still happen that the CS flip has been executed, but has not | |
10825 | * yet actually completed. But in case the base address is the same | |
10826 | * anyway, we don't really care. | |
10827 | */ | |
10828 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10829 | crtc->unpin_work->gtt_offset && | |
10830 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10831 | crtc->unpin_work->flip_count); | |
10832 | } | |
10833 | ||
6b95a207 KH |
10834 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10835 | { | |
fbee40df | 10836 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10837 | struct intel_crtc *intel_crtc = |
10838 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10839 | unsigned long flags; | |
10840 | ||
f326038a DV |
10841 | |
10842 | /* | |
10843 | * This is called both by irq handlers and the reset code (to complete | |
10844 | * lost pageflips) so needs the full irqsave spinlocks. | |
10845 | * | |
10846 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10847 | * generate a page-flip completion irq, i.e. every modeset |
10848 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10849 | */ | |
6b95a207 | 10850 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10851 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10852 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10853 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10854 | } | |
10855 | ||
eba905b2 | 10856 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10857 | { |
10858 | /* Ensure that the work item is consistent when activating it ... */ | |
10859 | smp_wmb(); | |
10860 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10861 | /* and that it is marked active as soon as the irq could fire. */ | |
10862 | smp_wmb(); | |
10863 | } | |
10864 | ||
8c9f3aaf JB |
10865 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10866 | struct drm_crtc *crtc, | |
10867 | struct drm_framebuffer *fb, | |
ed8d1975 | 10868 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10869 | struct drm_i915_gem_request *req, |
ed8d1975 | 10870 | uint32_t flags) |
8c9f3aaf | 10871 | { |
6258fbe2 | 10872 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10874 | u32 flip_mask; |
10875 | int ret; | |
10876 | ||
5fb9de1a | 10877 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10878 | if (ret) |
4fa62c89 | 10879 | return ret; |
8c9f3aaf JB |
10880 | |
10881 | /* Can't queue multiple flips, so wait for the previous | |
10882 | * one to finish before executing the next. | |
10883 | */ | |
10884 | if (intel_crtc->plane) | |
10885 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10886 | else | |
10887 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10888 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10889 | intel_ring_emit(ring, MI_NOOP); | |
10890 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10891 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10892 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10893 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10894 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10895 | |
10896 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10897 | return 0; |
8c9f3aaf JB |
10898 | } |
10899 | ||
10900 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10901 | struct drm_crtc *crtc, | |
10902 | struct drm_framebuffer *fb, | |
ed8d1975 | 10903 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10904 | struct drm_i915_gem_request *req, |
ed8d1975 | 10905 | uint32_t flags) |
8c9f3aaf | 10906 | { |
6258fbe2 | 10907 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10909 | u32 flip_mask; |
10910 | int ret; | |
10911 | ||
5fb9de1a | 10912 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10913 | if (ret) |
4fa62c89 | 10914 | return ret; |
8c9f3aaf JB |
10915 | |
10916 | if (intel_crtc->plane) | |
10917 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10918 | else | |
10919 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10920 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10921 | intel_ring_emit(ring, MI_NOOP); | |
10922 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10923 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10924 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10925 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10926 | intel_ring_emit(ring, MI_NOOP); |
10927 | ||
e7d841ca | 10928 | intel_mark_page_flip_active(intel_crtc); |
83d4092b | 10929 | return 0; |
8c9f3aaf JB |
10930 | } |
10931 | ||
10932 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10933 | struct drm_crtc *crtc, | |
10934 | struct drm_framebuffer *fb, | |
ed8d1975 | 10935 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10936 | struct drm_i915_gem_request *req, |
ed8d1975 | 10937 | uint32_t flags) |
8c9f3aaf | 10938 | { |
6258fbe2 | 10939 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10940 | struct drm_i915_private *dev_priv = dev->dev_private; |
10941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10942 | uint32_t pf, pipesrc; | |
10943 | int ret; | |
10944 | ||
5fb9de1a | 10945 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10946 | if (ret) |
4fa62c89 | 10947 | return ret; |
8c9f3aaf JB |
10948 | |
10949 | /* i965+ uses the linear or tiled offsets from the | |
10950 | * Display Registers (which do not change across a page-flip) | |
10951 | * so we need only reprogram the base address. | |
10952 | */ | |
6d90c952 DV |
10953 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10954 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10955 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10956 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10957 | obj->tiling_mode); |
8c9f3aaf JB |
10958 | |
10959 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10960 | * untested on non-native modes, so ignore it for now. | |
10961 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10962 | */ | |
10963 | pf = 0; | |
10964 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10965 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10966 | |
10967 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10968 | return 0; |
8c9f3aaf JB |
10969 | } |
10970 | ||
10971 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10972 | struct drm_crtc *crtc, | |
10973 | struct drm_framebuffer *fb, | |
ed8d1975 | 10974 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10975 | struct drm_i915_gem_request *req, |
ed8d1975 | 10976 | uint32_t flags) |
8c9f3aaf | 10977 | { |
6258fbe2 | 10978 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10979 | struct drm_i915_private *dev_priv = dev->dev_private; |
10980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10981 | uint32_t pf, pipesrc; | |
10982 | int ret; | |
10983 | ||
5fb9de1a | 10984 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10985 | if (ret) |
4fa62c89 | 10986 | return ret; |
8c9f3aaf | 10987 | |
6d90c952 DV |
10988 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10989 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10990 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10991 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10992 | |
dc257cf1 DV |
10993 | /* Contrary to the suggestions in the documentation, |
10994 | * "Enable Panel Fitter" does not seem to be required when page | |
10995 | * flipping with a non-native mode, and worse causes a normal | |
10996 | * modeset to fail. | |
10997 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10998 | */ | |
10999 | pf = 0; | |
8c9f3aaf | 11000 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11001 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
11002 | |
11003 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 11004 | return 0; |
8c9f3aaf JB |
11005 | } |
11006 | ||
7c9017e5 JB |
11007 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11008 | struct drm_crtc *crtc, | |
11009 | struct drm_framebuffer *fb, | |
ed8d1975 | 11010 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11011 | struct drm_i915_gem_request *req, |
ed8d1975 | 11012 | uint32_t flags) |
7c9017e5 | 11013 | { |
6258fbe2 | 11014 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11015 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11016 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11017 | int len, ret; |
11018 | ||
eba905b2 | 11019 | switch (intel_crtc->plane) { |
cb05d8de DV |
11020 | case PLANE_A: |
11021 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11022 | break; | |
11023 | case PLANE_B: | |
11024 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11025 | break; | |
11026 | case PLANE_C: | |
11027 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11028 | break; | |
11029 | default: | |
11030 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11031 | return -ENODEV; |
cb05d8de DV |
11032 | } |
11033 | ||
ffe74d75 | 11034 | len = 4; |
f476828a | 11035 | if (ring->id == RCS) { |
ffe74d75 | 11036 | len += 6; |
f476828a DL |
11037 | /* |
11038 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11039 | * 48bits addresses, and we need a NOOP for the batch size to | |
11040 | * stay even. | |
11041 | */ | |
11042 | if (IS_GEN8(dev)) | |
11043 | len += 2; | |
11044 | } | |
ffe74d75 | 11045 | |
f66fab8e VS |
11046 | /* |
11047 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11048 | * "The full packet must be contained within the same cache line." | |
11049 | * | |
11050 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11051 | * cacheline, if we ever start emitting more commands before | |
11052 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11053 | * then do the cacheline alignment, and finally emit the | |
11054 | * MI_DISPLAY_FLIP. | |
11055 | */ | |
bba09b12 | 11056 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11057 | if (ret) |
4fa62c89 | 11058 | return ret; |
f66fab8e | 11059 | |
5fb9de1a | 11060 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11061 | if (ret) |
4fa62c89 | 11062 | return ret; |
7c9017e5 | 11063 | |
ffe74d75 CW |
11064 | /* Unmask the flip-done completion message. Note that the bspec says that |
11065 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11066 | * more than one flip event at any time (or ensure that one flip message | |
11067 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11068 | * Experimentation says that BCS works despite DERRMR masking all | |
11069 | * flip-done completion events and that unmasking all planes at once | |
11070 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11071 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11072 | */ | |
11073 | if (ring->id == RCS) { | |
11074 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11075 | intel_ring_emit(ring, DERRMR); | |
11076 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11077 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11078 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
11079 | if (IS_GEN8(dev)) |
11080 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
11081 | MI_SRM_LRM_GLOBAL_GTT); | |
11082 | else | |
11083 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
11084 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
11085 | intel_ring_emit(ring, DERRMR); |
11086 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
11087 | if (IS_GEN8(dev)) { |
11088 | intel_ring_emit(ring, 0); | |
11089 | intel_ring_emit(ring, MI_NOOP); | |
11090 | } | |
ffe74d75 CW |
11091 | } |
11092 | ||
cb05d8de | 11093 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11094 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11095 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11096 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
11097 | |
11098 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 11099 | return 0; |
7c9017e5 JB |
11100 | } |
11101 | ||
84c33a64 SG |
11102 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11103 | struct drm_i915_gem_object *obj) | |
11104 | { | |
11105 | /* | |
11106 | * This is not being used for older platforms, because | |
11107 | * non-availability of flip done interrupt forces us to use | |
11108 | * CS flips. Older platforms derive flip done using some clever | |
11109 | * tricks involving the flip_pending status bits and vblank irqs. | |
11110 | * So using MMIO flips there would disrupt this mechanism. | |
11111 | */ | |
11112 | ||
8e09bf83 CW |
11113 | if (ring == NULL) |
11114 | return true; | |
11115 | ||
84c33a64 SG |
11116 | if (INTEL_INFO(ring->dev)->gen < 5) |
11117 | return false; | |
11118 | ||
11119 | if (i915.use_mmio_flip < 0) | |
11120 | return false; | |
11121 | else if (i915.use_mmio_flip > 0) | |
11122 | return true; | |
14bf993e OM |
11123 | else if (i915.enable_execlists) |
11124 | return true; | |
84c33a64 | 11125 | else |
b4716185 | 11126 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11127 | } |
11128 | ||
ff944564 DL |
11129 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
11130 | { | |
11131 | struct drm_device *dev = intel_crtc->base.dev; | |
11132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11133 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
11134 | const enum pipe pipe = intel_crtc->pipe; |
11135 | u32 ctl, stride; | |
11136 | ||
11137 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11138 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11139 | switch (fb->modifier[0]) { |
11140 | case DRM_FORMAT_MOD_NONE: | |
11141 | break; | |
11142 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11143 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11144 | break; |
11145 | case I915_FORMAT_MOD_Y_TILED: | |
11146 | ctl |= PLANE_CTL_TILED_Y; | |
11147 | break; | |
11148 | case I915_FORMAT_MOD_Yf_TILED: | |
11149 | ctl |= PLANE_CTL_TILED_YF; | |
11150 | break; | |
11151 | default: | |
11152 | MISSING_CASE(fb->modifier[0]); | |
11153 | } | |
ff944564 DL |
11154 | |
11155 | /* | |
11156 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11157 | * linear buffers or in number of tiles for tiled buffers. | |
11158 | */ | |
2ebef630 TU |
11159 | stride = fb->pitches[0] / |
11160 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11161 | fb->pixel_format); | |
ff944564 DL |
11162 | |
11163 | /* | |
11164 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11165 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11166 | */ | |
11167 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11168 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11169 | ||
11170 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
11171 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11172 | } | |
11173 | ||
11174 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
11175 | { |
11176 | struct drm_device *dev = intel_crtc->base.dev; | |
11177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11178 | struct intel_framebuffer *intel_fb = | |
11179 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11180 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11181 | u32 dspcntr; | |
11182 | u32 reg; | |
11183 | ||
84c33a64 SG |
11184 | reg = DSPCNTR(intel_crtc->plane); |
11185 | dspcntr = I915_READ(reg); | |
11186 | ||
c5d97472 DL |
11187 | if (obj->tiling_mode != I915_TILING_NONE) |
11188 | dspcntr |= DISPPLANE_TILED; | |
11189 | else | |
11190 | dspcntr &= ~DISPPLANE_TILED; | |
11191 | ||
84c33a64 SG |
11192 | I915_WRITE(reg, dspcntr); |
11193 | ||
11194 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
11195 | intel_crtc->unpin_work->gtt_offset); | |
11196 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 11197 | |
ff944564 DL |
11198 | } |
11199 | ||
11200 | /* | |
11201 | * XXX: This is the temporary way to update the plane registers until we get | |
11202 | * around to using the usual plane update functions for MMIO flips | |
11203 | */ | |
11204 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
11205 | { | |
11206 | struct drm_device *dev = intel_crtc->base.dev; | |
11207 | bool atomic_update; | |
11208 | u32 start_vbl_count; | |
11209 | ||
11210 | intel_mark_page_flip_active(intel_crtc); | |
11211 | ||
11212 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
11213 | ||
11214 | if (INTEL_INFO(dev)->gen >= 9) | |
11215 | skl_do_mmio_flip(intel_crtc); | |
11216 | else | |
11217 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11218 | ilk_do_mmio_flip(intel_crtc); | |
11219 | ||
9362c7c5 ACO |
11220 | if (atomic_update) |
11221 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
11222 | } |
11223 | ||
9362c7c5 | 11224 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11225 | { |
b2cfe0ab CW |
11226 | struct intel_mmio_flip *mmio_flip = |
11227 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 11228 | |
eed29a5b DV |
11229 | if (mmio_flip->req) |
11230 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
b2cfe0ab | 11231 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11232 | false, NULL, |
11233 | &mmio_flip->i915->rps.mmioflips)); | |
84c33a64 | 11234 | |
b2cfe0ab CW |
11235 | intel_do_mmio_flip(mmio_flip->crtc); |
11236 | ||
eed29a5b | 11237 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
b2cfe0ab | 11238 | kfree(mmio_flip); |
84c33a64 SG |
11239 | } |
11240 | ||
11241 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11242 | struct drm_crtc *crtc, | |
11243 | struct drm_framebuffer *fb, | |
11244 | struct drm_i915_gem_object *obj, | |
11245 | struct intel_engine_cs *ring, | |
11246 | uint32_t flags) | |
11247 | { | |
b2cfe0ab CW |
11248 | struct intel_mmio_flip *mmio_flip; |
11249 | ||
11250 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11251 | if (mmio_flip == NULL) | |
11252 | return -ENOMEM; | |
84c33a64 | 11253 | |
bcafc4e3 | 11254 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11255 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11256 | mmio_flip->crtc = to_intel_crtc(crtc); |
536f5b5e | 11257 | |
b2cfe0ab CW |
11258 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11259 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11260 | |
84c33a64 SG |
11261 | return 0; |
11262 | } | |
11263 | ||
8c9f3aaf JB |
11264 | static int intel_default_queue_flip(struct drm_device *dev, |
11265 | struct drm_crtc *crtc, | |
11266 | struct drm_framebuffer *fb, | |
ed8d1975 | 11267 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11268 | struct drm_i915_gem_request *req, |
ed8d1975 | 11269 | uint32_t flags) |
8c9f3aaf JB |
11270 | { |
11271 | return -ENODEV; | |
11272 | } | |
11273 | ||
d6bbafa1 CW |
11274 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11275 | struct drm_crtc *crtc) | |
11276 | { | |
11277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11279 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11280 | u32 addr; | |
11281 | ||
11282 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11283 | return true; | |
11284 | ||
11285 | if (!work->enable_stall_check) | |
11286 | return false; | |
11287 | ||
11288 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11289 | if (work->flip_queued_req && |
11290 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11291 | return false; |
11292 | ||
1e3feefd | 11293 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11294 | } |
11295 | ||
1e3feefd | 11296 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11297 | return false; |
11298 | ||
11299 | /* Potential stall - if we see that the flip has happened, | |
11300 | * assume a missed interrupt. */ | |
11301 | if (INTEL_INFO(dev)->gen >= 4) | |
11302 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11303 | else | |
11304 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11305 | ||
11306 | /* There is a potential issue here with a false positive after a flip | |
11307 | * to the same address. We could address this by checking for a | |
11308 | * non-incrementing frame counter. | |
11309 | */ | |
11310 | return addr == work->gtt_offset; | |
11311 | } | |
11312 | ||
11313 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11314 | { | |
11315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11316 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11318 | struct intel_unpin_work *work; |
f326038a | 11319 | |
6c51d46f | 11320 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11321 | |
11322 | if (crtc == NULL) | |
11323 | return; | |
11324 | ||
f326038a | 11325 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11326 | work = intel_crtc->unpin_work; |
11327 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11328 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11329 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11330 | page_flip_completed(intel_crtc); |
6ad790c0 | 11331 | work = NULL; |
d6bbafa1 | 11332 | } |
6ad790c0 CW |
11333 | if (work != NULL && |
11334 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11335 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11336 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11337 | } |
11338 | ||
6b95a207 KH |
11339 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11340 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11341 | struct drm_pending_vblank_event *event, |
11342 | uint32_t page_flip_flags) | |
6b95a207 KH |
11343 | { |
11344 | struct drm_device *dev = crtc->dev; | |
11345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11346 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11347 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11349 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11350 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11351 | struct intel_unpin_work *work; |
a4872ba6 | 11352 | struct intel_engine_cs *ring; |
cf5d8a46 | 11353 | bool mmio_flip; |
91af127f | 11354 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11355 | int ret; |
6b95a207 | 11356 | |
2ff8fde1 MR |
11357 | /* |
11358 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11359 | * check to be safe. In the future we may enable pageflipping from | |
11360 | * a disabled primary plane. | |
11361 | */ | |
11362 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11363 | return -EBUSY; | |
11364 | ||
e6a595d2 | 11365 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11366 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11367 | return -EINVAL; |
11368 | ||
11369 | /* | |
11370 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11371 | * Note that pitch changes could also affect these register. | |
11372 | */ | |
11373 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11374 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11375 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11376 | return -EINVAL; |
11377 | ||
f900db47 CW |
11378 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11379 | goto out_hang; | |
11380 | ||
b14c5679 | 11381 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11382 | if (work == NULL) |
11383 | return -ENOMEM; | |
11384 | ||
6b95a207 | 11385 | work->event = event; |
b4a98e57 | 11386 | work->crtc = crtc; |
ab8d6675 | 11387 | work->old_fb = old_fb; |
6b95a207 KH |
11388 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11389 | ||
87b6b101 | 11390 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11391 | if (ret) |
11392 | goto free_work; | |
11393 | ||
6b95a207 | 11394 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11395 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11396 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11397 | /* Before declaring the flip queue wedged, check if |
11398 | * the hardware completed the operation behind our backs. | |
11399 | */ | |
11400 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11401 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11402 | page_flip_completed(intel_crtc); | |
11403 | } else { | |
11404 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11405 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11406 | |
d6bbafa1 CW |
11407 | drm_crtc_vblank_put(crtc); |
11408 | kfree(work); | |
11409 | return -EBUSY; | |
11410 | } | |
6b95a207 KH |
11411 | } |
11412 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11413 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11414 | |
b4a98e57 CW |
11415 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11416 | flush_workqueue(dev_priv->wq); | |
11417 | ||
75dfca80 | 11418 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11419 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11420 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11421 | |
f4510a27 | 11422 | crtc->primary->fb = fb; |
afd65eb4 | 11423 | update_state_fb(crtc->primary); |
1ed1f968 | 11424 | |
e1f99ce6 | 11425 | work->pending_flip_obj = obj; |
e1f99ce6 | 11426 | |
89ed88ba CW |
11427 | ret = i915_mutex_lock_interruptible(dev); |
11428 | if (ret) | |
11429 | goto cleanup; | |
11430 | ||
b4a98e57 | 11431 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11432 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11433 | |
75f7f3ec | 11434 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11435 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11436 | |
4fa62c89 VS |
11437 | if (IS_VALLEYVIEW(dev)) { |
11438 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11439 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11440 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11441 | ring = NULL; | |
48bf5b2d | 11442 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11443 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11444 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11445 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11446 | if (ring == NULL || ring->id != RCS) |
11447 | ring = &dev_priv->ring[BCS]; | |
11448 | } else { | |
11449 | ring = &dev_priv->ring[RCS]; | |
11450 | } | |
11451 | ||
cf5d8a46 CW |
11452 | mmio_flip = use_mmio_flip(ring, obj); |
11453 | ||
11454 | /* When using CS flips, we want to emit semaphores between rings. | |
11455 | * However, when using mmio flips we will create a task to do the | |
11456 | * synchronisation, so all we want here is to pin the framebuffer | |
11457 | * into the display plane and skip any waits. | |
11458 | */ | |
82bc3b2d | 11459 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 | 11460 | crtc->primary->state, |
91af127f | 11461 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request); |
8c9f3aaf JB |
11462 | if (ret) |
11463 | goto cleanup_pending; | |
6b95a207 | 11464 | |
121920fa TU |
11465 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
11466 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 11467 | |
cf5d8a46 | 11468 | if (mmio_flip) { |
84c33a64 SG |
11469 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11470 | page_flip_flags); | |
d6bbafa1 CW |
11471 | if (ret) |
11472 | goto cleanup_unpin; | |
11473 | ||
f06cc1b9 JH |
11474 | i915_gem_request_assign(&work->flip_queued_req, |
11475 | obj->last_write_req); | |
d6bbafa1 | 11476 | } else { |
6258fbe2 JH |
11477 | if (!request) { |
11478 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11479 | if (ret) | |
11480 | goto cleanup_unpin; | |
11481 | } | |
11482 | ||
11483 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11484 | page_flip_flags); |
11485 | if (ret) | |
11486 | goto cleanup_unpin; | |
11487 | ||
6258fbe2 | 11488 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11489 | } |
11490 | ||
91af127f | 11491 | if (request) |
75289874 | 11492 | i915_add_request_no_flush(request); |
91af127f | 11493 | |
1e3feefd | 11494 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11495 | work->enable_stall_check = true; |
4fa62c89 | 11496 | |
ab8d6675 | 11497 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11498 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11499 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11500 | |
7733b49b | 11501 | intel_fbc_disable(dev_priv); |
a9ff8714 VS |
11502 | intel_frontbuffer_flip_prepare(dev, |
11503 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11504 | |
e5510fac JB |
11505 | trace_i915_flip_request(intel_crtc->plane, obj); |
11506 | ||
6b95a207 | 11507 | return 0; |
96b099fd | 11508 | |
4fa62c89 | 11509 | cleanup_unpin: |
82bc3b2d | 11510 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11511 | cleanup_pending: |
91af127f JH |
11512 | if (request) |
11513 | i915_gem_request_cancel(request); | |
b4a98e57 | 11514 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11515 | mutex_unlock(&dev->struct_mutex); |
11516 | cleanup: | |
f4510a27 | 11517 | crtc->primary->fb = old_fb; |
afd65eb4 | 11518 | update_state_fb(crtc->primary); |
89ed88ba CW |
11519 | |
11520 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11521 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11522 | |
5e2d7afc | 11523 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11524 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11525 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11526 | |
87b6b101 | 11527 | drm_crtc_vblank_put(crtc); |
7317c75e | 11528 | free_work: |
96b099fd CW |
11529 | kfree(work); |
11530 | ||
f900db47 | 11531 | if (ret == -EIO) { |
02e0efb5 ML |
11532 | struct drm_atomic_state *state; |
11533 | struct drm_plane_state *plane_state; | |
11534 | ||
f900db47 | 11535 | out_hang: |
02e0efb5 ML |
11536 | state = drm_atomic_state_alloc(dev); |
11537 | if (!state) | |
11538 | return -ENOMEM; | |
11539 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11540 | ||
11541 | retry: | |
11542 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11543 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11544 | if (!ret) { | |
11545 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11546 | ||
11547 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11548 | if (!ret) | |
11549 | ret = drm_atomic_commit(state); | |
11550 | } | |
11551 | ||
11552 | if (ret == -EDEADLK) { | |
11553 | drm_modeset_backoff(state->acquire_ctx); | |
11554 | drm_atomic_state_clear(state); | |
11555 | goto retry; | |
11556 | } | |
11557 | ||
11558 | if (ret) | |
11559 | drm_atomic_state_free(state); | |
11560 | ||
f0d3dad3 | 11561 | if (ret == 0 && event) { |
5e2d7afc | 11562 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11563 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11564 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11565 | } |
f900db47 | 11566 | } |
96b099fd | 11567 | return ret; |
6b95a207 KH |
11568 | } |
11569 | ||
da20eabd ML |
11570 | |
11571 | /** | |
11572 | * intel_wm_need_update - Check whether watermarks need updating | |
11573 | * @plane: drm plane | |
11574 | * @state: new plane state | |
11575 | * | |
11576 | * Check current plane state versus the new one to determine whether | |
11577 | * watermarks need to be recalculated. | |
11578 | * | |
11579 | * Returns true or false. | |
11580 | */ | |
11581 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11582 | struct drm_plane_state *state) | |
11583 | { | |
11584 | /* Update watermarks on tiling changes. */ | |
11585 | if (!plane->state->fb || !state->fb || | |
11586 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
11587 | plane->state->rotation != state->rotation) | |
11588 | return true; | |
11589 | ||
11590 | if (plane->state->crtc_w != state->crtc_w) | |
11591 | return true; | |
11592 | ||
11593 | return false; | |
11594 | } | |
11595 | ||
11596 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, | |
11597 | struct drm_plane_state *plane_state) | |
11598 | { | |
11599 | struct drm_crtc *crtc = crtc_state->crtc; | |
11600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11601 | struct drm_plane *plane = plane_state->plane; | |
11602 | struct drm_device *dev = crtc->dev; | |
11603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11604 | struct intel_plane_state *old_plane_state = | |
11605 | to_intel_plane_state(plane->state); | |
11606 | int idx = intel_crtc->base.base.id, ret; | |
11607 | int i = drm_plane_index(plane); | |
11608 | bool mode_changed = needs_modeset(crtc_state); | |
11609 | bool was_crtc_enabled = crtc->state->active; | |
11610 | bool is_crtc_enabled = crtc_state->active; | |
11611 | ||
11612 | bool turn_off, turn_on, visible, was_visible; | |
11613 | struct drm_framebuffer *fb = plane_state->fb; | |
11614 | ||
11615 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11616 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11617 | ret = skl_update_scaler_plane( | |
11618 | to_intel_crtc_state(crtc_state), | |
11619 | to_intel_plane_state(plane_state)); | |
11620 | if (ret) | |
11621 | return ret; | |
11622 | } | |
11623 | ||
11624 | /* | |
11625 | * Disabling a plane is always okay; we just need to update | |
11626 | * fb tracking in a special way since cleanup_fb() won't | |
11627 | * get called by the plane helpers. | |
11628 | */ | |
11629 | if (old_plane_state->base.fb && !fb) | |
11630 | intel_crtc->atomic.disabled_planes |= 1 << i; | |
11631 | ||
da20eabd ML |
11632 | was_visible = old_plane_state->visible; |
11633 | visible = to_intel_plane_state(plane_state)->visible; | |
11634 | ||
11635 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11636 | was_visible = false; | |
11637 | ||
11638 | if (!is_crtc_enabled && WARN_ON(visible)) | |
11639 | visible = false; | |
11640 | ||
11641 | if (!was_visible && !visible) | |
11642 | return 0; | |
11643 | ||
11644 | turn_off = was_visible && (!visible || mode_changed); | |
11645 | turn_on = visible && (!was_visible || mode_changed); | |
11646 | ||
11647 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11648 | plane->base.id, fb ? fb->base.id : -1); | |
11649 | ||
11650 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11651 | plane->base.id, was_visible, visible, | |
11652 | turn_off, turn_on, mode_changed); | |
11653 | ||
852eb00d | 11654 | if (turn_on) { |
f015c551 | 11655 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d VS |
11656 | /* must disable cxsr around plane enable/disable */ |
11657 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11658 | intel_crtc->atomic.disable_cxsr = true; | |
11659 | /* to potentially re-enable cxsr */ | |
11660 | intel_crtc->atomic.wait_vblank = true; | |
11661 | intel_crtc->atomic.update_wm_post = true; | |
11662 | } | |
11663 | } else if (turn_off) { | |
f015c551 | 11664 | intel_crtc->atomic.update_wm_post = true; |
852eb00d VS |
11665 | /* must disable cxsr around plane enable/disable */ |
11666 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11667 | if (is_crtc_enabled) | |
11668 | intel_crtc->atomic.wait_vblank = true; | |
11669 | intel_crtc->atomic.disable_cxsr = true; | |
11670 | } | |
11671 | } else if (intel_wm_need_update(plane, plane_state)) { | |
f015c551 | 11672 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d | 11673 | } |
da20eabd | 11674 | |
a9ff8714 VS |
11675 | if (visible) |
11676 | intel_crtc->atomic.fb_bits |= | |
11677 | to_intel_plane(plane)->frontbuffer_bit; | |
11678 | ||
da20eabd ML |
11679 | switch (plane->type) { |
11680 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11681 | intel_crtc->atomic.wait_for_flips = true; |
11682 | intel_crtc->atomic.pre_disable_primary = turn_off; | |
11683 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11684 | ||
066cf55b RV |
11685 | if (turn_off) { |
11686 | /* | |
11687 | * FIXME: Actually if we will still have any other | |
11688 | * plane enabled on the pipe we could let IPS enabled | |
11689 | * still, but for now lets consider that when we make | |
11690 | * primary invisible by setting DSPCNTR to 0 on | |
11691 | * update_primary_plane function IPS needs to be | |
11692 | * disable. | |
11693 | */ | |
11694 | intel_crtc->atomic.disable_ips = true; | |
11695 | ||
da20eabd | 11696 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11697 | } |
da20eabd ML |
11698 | |
11699 | /* | |
11700 | * FBC does not work on some platforms for rotated | |
11701 | * planes, so disable it when rotation is not 0 and | |
11702 | * update it when rotation is set back to 0. | |
11703 | * | |
11704 | * FIXME: This is redundant with the fbc update done in | |
11705 | * the primary plane enable function except that that | |
11706 | * one is done too late. We eventually need to unify | |
11707 | * this. | |
11708 | */ | |
11709 | ||
11710 | if (visible && | |
11711 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11712 | dev_priv->fbc.crtc == intel_crtc && | |
11713 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11714 | intel_crtc->atomic.disable_fbc = true; | |
11715 | ||
11716 | /* | |
11717 | * BDW signals flip done immediately if the plane | |
11718 | * is disabled, even if the plane enable is already | |
11719 | * armed to occur at the next vblank :( | |
11720 | */ | |
11721 | if (turn_on && IS_BROADWELL(dev)) | |
11722 | intel_crtc->atomic.wait_vblank = true; | |
11723 | ||
11724 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11725 | break; | |
11726 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11727 | break; |
11728 | case DRM_PLANE_TYPE_OVERLAY: | |
d032ffa0 | 11729 | if (turn_off && !mode_changed) { |
da20eabd ML |
11730 | intel_crtc->atomic.wait_vblank = true; |
11731 | intel_crtc->atomic.update_sprite_watermarks |= | |
11732 | 1 << i; | |
11733 | } | |
da20eabd ML |
11734 | } |
11735 | return 0; | |
11736 | } | |
11737 | ||
6d3a1ce7 ML |
11738 | static bool encoders_cloneable(const struct intel_encoder *a, |
11739 | const struct intel_encoder *b) | |
11740 | { | |
11741 | /* masks could be asymmetric, so check both ways */ | |
11742 | return a == b || (a->cloneable & (1 << b->type) && | |
11743 | b->cloneable & (1 << a->type)); | |
11744 | } | |
11745 | ||
11746 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11747 | struct intel_crtc *crtc, | |
11748 | struct intel_encoder *encoder) | |
11749 | { | |
11750 | struct intel_encoder *source_encoder; | |
11751 | struct drm_connector *connector; | |
11752 | struct drm_connector_state *connector_state; | |
11753 | int i; | |
11754 | ||
11755 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11756 | if (connector_state->crtc != &crtc->base) | |
11757 | continue; | |
11758 | ||
11759 | source_encoder = | |
11760 | to_intel_encoder(connector_state->best_encoder); | |
11761 | if (!encoders_cloneable(encoder, source_encoder)) | |
11762 | return false; | |
11763 | } | |
11764 | ||
11765 | return true; | |
11766 | } | |
11767 | ||
11768 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11769 | struct intel_crtc *crtc) | |
11770 | { | |
11771 | struct intel_encoder *encoder; | |
11772 | struct drm_connector *connector; | |
11773 | struct drm_connector_state *connector_state; | |
11774 | int i; | |
11775 | ||
11776 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11777 | if (connector_state->crtc != &crtc->base) | |
11778 | continue; | |
11779 | ||
11780 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11781 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11782 | return false; | |
11783 | } | |
11784 | ||
11785 | return true; | |
11786 | } | |
11787 | ||
11788 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11789 | struct drm_crtc_state *crtc_state) | |
11790 | { | |
cf5a15be | 11791 | struct drm_device *dev = crtc->dev; |
ad421372 | 11792 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11794 | struct intel_crtc_state *pipe_config = |
11795 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11796 | struct drm_atomic_state *state = crtc_state->state; |
ad421372 | 11797 | int ret, idx = crtc->base.id; |
6d3a1ce7 ML |
11798 | bool mode_changed = needs_modeset(crtc_state); |
11799 | ||
11800 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11801 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11802 | return -EINVAL; | |
11803 | } | |
11804 | ||
11805 | I915_STATE_WARN(crtc->state->active != intel_crtc->active, | |
11806 | "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n", | |
11807 | idx, crtc->state->active, intel_crtc->active); | |
11808 | ||
852eb00d VS |
11809 | if (mode_changed && !crtc_state->active) |
11810 | intel_crtc->atomic.update_wm_post = true; | |
eddfcbcd | 11811 | |
ad421372 ML |
11812 | if (mode_changed && crtc_state->enable && |
11813 | dev_priv->display.crtc_compute_clock && | |
11814 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11815 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11816 | pipe_config); | |
11817 | if (ret) | |
11818 | return ret; | |
11819 | } | |
11820 | ||
e435d6e5 ML |
11821 | ret = 0; |
11822 | if (INTEL_INFO(dev)->gen >= 9) { | |
11823 | if (mode_changed) | |
11824 | ret = skl_update_scaler_crtc(pipe_config); | |
11825 | ||
11826 | if (!ret) | |
11827 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11828 | pipe_config); | |
11829 | } | |
11830 | ||
11831 | return ret; | |
6d3a1ce7 ML |
11832 | } |
11833 | ||
65b38e0d | 11834 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11835 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11836 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11837 | .atomic_begin = intel_begin_crtc_commit, |
11838 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11839 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11840 | }; |
11841 | ||
d29b2f9d ACO |
11842 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11843 | { | |
11844 | struct intel_connector *connector; | |
11845 | ||
11846 | for_each_intel_connector(dev, connector) { | |
11847 | if (connector->base.encoder) { | |
11848 | connector->base.state->best_encoder = | |
11849 | connector->base.encoder; | |
11850 | connector->base.state->crtc = | |
11851 | connector->base.encoder->crtc; | |
11852 | } else { | |
11853 | connector->base.state->best_encoder = NULL; | |
11854 | connector->base.state->crtc = NULL; | |
11855 | } | |
11856 | } | |
11857 | } | |
11858 | ||
050f7aeb | 11859 | static void |
eba905b2 | 11860 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11861 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11862 | { |
11863 | int bpp = pipe_config->pipe_bpp; | |
11864 | ||
11865 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11866 | connector->base.base.id, | |
c23cc417 | 11867 | connector->base.name); |
050f7aeb DV |
11868 | |
11869 | /* Don't use an invalid EDID bpc value */ | |
11870 | if (connector->base.display_info.bpc && | |
11871 | connector->base.display_info.bpc * 3 < bpp) { | |
11872 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11873 | bpp, connector->base.display_info.bpc*3); | |
11874 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11875 | } | |
11876 | ||
11877 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11878 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11879 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11880 | bpp); | |
11881 | pipe_config->pipe_bpp = 24; | |
11882 | } | |
11883 | } | |
11884 | ||
4e53c2e0 | 11885 | static int |
050f7aeb | 11886 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11887 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11888 | { |
050f7aeb | 11889 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11890 | struct drm_atomic_state *state; |
da3ced29 ACO |
11891 | struct drm_connector *connector; |
11892 | struct drm_connector_state *connector_state; | |
1486017f | 11893 | int bpp, i; |
4e53c2e0 | 11894 | |
d328c9d7 | 11895 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11896 | bpp = 10*3; |
d328c9d7 DV |
11897 | else if (INTEL_INFO(dev)->gen >= 5) |
11898 | bpp = 12*3; | |
11899 | else | |
11900 | bpp = 8*3; | |
11901 | ||
4e53c2e0 | 11902 | |
4e53c2e0 DV |
11903 | pipe_config->pipe_bpp = bpp; |
11904 | ||
1486017f ACO |
11905 | state = pipe_config->base.state; |
11906 | ||
4e53c2e0 | 11907 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11908 | for_each_connector_in_state(state, connector, connector_state, i) { |
11909 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11910 | continue; |
11911 | ||
da3ced29 ACO |
11912 | connected_sink_compute_bpp(to_intel_connector(connector), |
11913 | pipe_config); | |
4e53c2e0 DV |
11914 | } |
11915 | ||
11916 | return bpp; | |
11917 | } | |
11918 | ||
644db711 DV |
11919 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11920 | { | |
11921 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11922 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11923 | mode->crtc_clock, |
644db711 DV |
11924 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11925 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11926 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11927 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11928 | } | |
11929 | ||
c0b03411 | 11930 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11931 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11932 | const char *context) |
11933 | { | |
6a60cd87 CK |
11934 | struct drm_device *dev = crtc->base.dev; |
11935 | struct drm_plane *plane; | |
11936 | struct intel_plane *intel_plane; | |
11937 | struct intel_plane_state *state; | |
11938 | struct drm_framebuffer *fb; | |
11939 | ||
11940 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11941 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11942 | |
11943 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11944 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11945 | pipe_config->pipe_bpp, pipe_config->dither); | |
11946 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11947 | pipe_config->has_pch_encoder, | |
11948 | pipe_config->fdi_lanes, | |
11949 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11950 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11951 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11952 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11953 | pipe_config->has_dp_encoder, | |
11954 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11955 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11956 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11957 | |
11958 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11959 | pipe_config->has_dp_encoder, | |
11960 | pipe_config->dp_m2_n2.gmch_m, | |
11961 | pipe_config->dp_m2_n2.gmch_n, | |
11962 | pipe_config->dp_m2_n2.link_m, | |
11963 | pipe_config->dp_m2_n2.link_n, | |
11964 | pipe_config->dp_m2_n2.tu); | |
11965 | ||
55072d19 DV |
11966 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11967 | pipe_config->has_audio, | |
11968 | pipe_config->has_infoframe); | |
11969 | ||
c0b03411 | 11970 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11971 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11972 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11973 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11974 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11975 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11976 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11977 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11978 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11979 | crtc->num_scalers, | |
11980 | pipe_config->scaler_state.scaler_users, | |
11981 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11982 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11983 | pipe_config->gmch_pfit.control, | |
11984 | pipe_config->gmch_pfit.pgm_ratios, | |
11985 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11986 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11987 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11988 | pipe_config->pch_pfit.size, |
11989 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11990 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11991 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11992 | |
415ff0f6 | 11993 | if (IS_BROXTON(dev)) { |
05712c15 | 11994 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 11995 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 11996 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
11997 | pipe_config->ddi_pll_sel, |
11998 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 11999 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12000 | pipe_config->dpll_hw_state.pll0, |
12001 | pipe_config->dpll_hw_state.pll1, | |
12002 | pipe_config->dpll_hw_state.pll2, | |
12003 | pipe_config->dpll_hw_state.pll3, | |
12004 | pipe_config->dpll_hw_state.pll6, | |
12005 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12006 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12007 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 TU |
12008 | pipe_config->dpll_hw_state.pcsdw12); |
12009 | } else if (IS_SKYLAKE(dev)) { | |
12010 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
12011 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12012 | pipe_config->ddi_pll_sel, | |
12013 | pipe_config->dpll_hw_state.ctrl1, | |
12014 | pipe_config->dpll_hw_state.cfgcr1, | |
12015 | pipe_config->dpll_hw_state.cfgcr2); | |
12016 | } else if (HAS_DDI(dev)) { | |
12017 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
12018 | pipe_config->ddi_pll_sel, | |
12019 | pipe_config->dpll_hw_state.wrpll); | |
12020 | } else { | |
12021 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12022 | "fp0: 0x%x, fp1: 0x%x\n", | |
12023 | pipe_config->dpll_hw_state.dpll, | |
12024 | pipe_config->dpll_hw_state.dpll_md, | |
12025 | pipe_config->dpll_hw_state.fp0, | |
12026 | pipe_config->dpll_hw_state.fp1); | |
12027 | } | |
12028 | ||
6a60cd87 CK |
12029 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12030 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12031 | intel_plane = to_intel_plane(plane); | |
12032 | if (intel_plane->pipe != crtc->pipe) | |
12033 | continue; | |
12034 | ||
12035 | state = to_intel_plane_state(plane->state); | |
12036 | fb = state->base.fb; | |
12037 | if (!fb) { | |
12038 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12039 | "disabled, scaler_id = %d\n", | |
12040 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12041 | plane->base.id, intel_plane->pipe, | |
12042 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12043 | drm_plane_index(plane), state->scaler_id); | |
12044 | continue; | |
12045 | } | |
12046 | ||
12047 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12048 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12049 | plane->base.id, intel_plane->pipe, | |
12050 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12051 | drm_plane_index(plane)); | |
12052 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12053 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12054 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12055 | state->scaler_id, | |
12056 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12057 | drm_rect_width(&state->src) >> 16, | |
12058 | drm_rect_height(&state->src) >> 16, | |
12059 | state->dst.x1, state->dst.y1, | |
12060 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12061 | } | |
c0b03411 DV |
12062 | } |
12063 | ||
5448a00d | 12064 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12065 | { |
5448a00d ACO |
12066 | struct drm_device *dev = state->dev; |
12067 | struct intel_encoder *encoder; | |
da3ced29 | 12068 | struct drm_connector *connector; |
5448a00d | 12069 | struct drm_connector_state *connector_state; |
00f0b378 | 12070 | unsigned int used_ports = 0; |
5448a00d | 12071 | int i; |
00f0b378 VS |
12072 | |
12073 | /* | |
12074 | * Walk the connector list instead of the encoder | |
12075 | * list to detect the problem on ddi platforms | |
12076 | * where there's just one encoder per digital port. | |
12077 | */ | |
da3ced29 | 12078 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12079 | if (!connector_state->best_encoder) |
00f0b378 VS |
12080 | continue; |
12081 | ||
5448a00d ACO |
12082 | encoder = to_intel_encoder(connector_state->best_encoder); |
12083 | ||
12084 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12085 | |
12086 | switch (encoder->type) { | |
12087 | unsigned int port_mask; | |
12088 | case INTEL_OUTPUT_UNKNOWN: | |
12089 | if (WARN_ON(!HAS_DDI(dev))) | |
12090 | break; | |
12091 | case INTEL_OUTPUT_DISPLAYPORT: | |
12092 | case INTEL_OUTPUT_HDMI: | |
12093 | case INTEL_OUTPUT_EDP: | |
12094 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12095 | ||
12096 | /* the same port mustn't appear more than once */ | |
12097 | if (used_ports & port_mask) | |
12098 | return false; | |
12099 | ||
12100 | used_ports |= port_mask; | |
12101 | default: | |
12102 | break; | |
12103 | } | |
12104 | } | |
12105 | ||
12106 | return true; | |
12107 | } | |
12108 | ||
83a57153 ACO |
12109 | static void |
12110 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12111 | { | |
12112 | struct drm_crtc_state tmp_state; | |
663a3640 | 12113 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12114 | struct intel_dpll_hw_state dpll_hw_state; |
12115 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12116 | uint32_t ddi_pll_sel; |
83a57153 | 12117 | |
7546a384 ACO |
12118 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12119 | * kzalloc'd. Code that depends on any field being zero should be | |
12120 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12121 | * only fields that are know to not cause problems are preserved. */ | |
12122 | ||
83a57153 | 12123 | tmp_state = crtc_state->base; |
663a3640 | 12124 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12125 | shared_dpll = crtc_state->shared_dpll; |
12126 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12127 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
4978cc93 | 12128 | |
83a57153 | 12129 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12130 | |
83a57153 | 12131 | crtc_state->base = tmp_state; |
663a3640 | 12132 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12133 | crtc_state->shared_dpll = shared_dpll; |
12134 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12135 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
83a57153 ACO |
12136 | } |
12137 | ||
548ee15b | 12138 | static int |
b8cecdf5 | 12139 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12140 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12141 | { |
b359283a | 12142 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12143 | struct intel_encoder *encoder; |
da3ced29 | 12144 | struct drm_connector *connector; |
0b901879 | 12145 | struct drm_connector_state *connector_state; |
d328c9d7 | 12146 | int base_bpp, ret = -EINVAL; |
0b901879 | 12147 | int i; |
e29c22c0 | 12148 | bool retry = true; |
ee7b9f93 | 12149 | |
83a57153 | 12150 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12151 | |
e143a21c DV |
12152 | pipe_config->cpu_transcoder = |
12153 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12154 | |
2960bc9c ID |
12155 | /* |
12156 | * Sanitize sync polarity flags based on requested ones. If neither | |
12157 | * positive or negative polarity is requested, treat this as meaning | |
12158 | * negative polarity. | |
12159 | */ | |
2d112de7 | 12160 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12161 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12162 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12163 | |
2d112de7 | 12164 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12165 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12166 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12167 | |
050f7aeb DV |
12168 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
12169 | * plane pixel format and any sink constraints into account. Returns the | |
12170 | * source plane bpp so that dithering can be selected on mismatches | |
12171 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
12172 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12173 | pipe_config); | |
12174 | if (base_bpp < 0) | |
4e53c2e0 DV |
12175 | goto fail; |
12176 | ||
e41a56be VS |
12177 | /* |
12178 | * Determine the real pipe dimensions. Note that stereo modes can | |
12179 | * increase the actual pipe size due to the frame doubling and | |
12180 | * insertion of additional space for blanks between the frame. This | |
12181 | * is stored in the crtc timings. We use the requested mode to do this | |
12182 | * computation to clearly distinguish it from the adjusted mode, which | |
12183 | * can be changed by the connectors in the below retry loop. | |
12184 | */ | |
2d112de7 | 12185 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12186 | &pipe_config->pipe_src_w, |
12187 | &pipe_config->pipe_src_h); | |
e41a56be | 12188 | |
e29c22c0 | 12189 | encoder_retry: |
ef1b460d | 12190 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12191 | pipe_config->port_clock = 0; |
ef1b460d | 12192 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12193 | |
135c81b8 | 12194 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12195 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12196 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12197 | |
7758a113 DV |
12198 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12199 | * adjust it according to limitations or connector properties, and also | |
12200 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12201 | */ |
da3ced29 | 12202 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12203 | if (connector_state->crtc != crtc) |
7758a113 | 12204 | continue; |
7ae89233 | 12205 | |
0b901879 ACO |
12206 | encoder = to_intel_encoder(connector_state->best_encoder); |
12207 | ||
efea6e8e DV |
12208 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12209 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12210 | goto fail; |
12211 | } | |
ee7b9f93 | 12212 | } |
47f1c6c9 | 12213 | |
ff9a6750 DV |
12214 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12215 | * done afterwards in case the encoder adjusts the mode. */ | |
12216 | if (!pipe_config->port_clock) | |
2d112de7 | 12217 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12218 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12219 | |
a43f6e0f | 12220 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12221 | if (ret < 0) { |
7758a113 DV |
12222 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12223 | goto fail; | |
ee7b9f93 | 12224 | } |
e29c22c0 DV |
12225 | |
12226 | if (ret == RETRY) { | |
12227 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12228 | ret = -EINVAL; | |
12229 | goto fail; | |
12230 | } | |
12231 | ||
12232 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12233 | retry = false; | |
12234 | goto encoder_retry; | |
12235 | } | |
12236 | ||
d328c9d7 | 12237 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 12238 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12239 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12240 | |
7758a113 | 12241 | fail: |
548ee15b | 12242 | return ret; |
ee7b9f93 | 12243 | } |
47f1c6c9 | 12244 | |
ea9d758d | 12245 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 12246 | { |
ea9d758d | 12247 | struct drm_encoder *encoder; |
f6e5b160 | 12248 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 12249 | |
ea9d758d DV |
12250 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
12251 | if (encoder->crtc == crtc) | |
12252 | return true; | |
12253 | ||
12254 | return false; | |
12255 | } | |
12256 | ||
12257 | static void | |
0a9ab303 | 12258 | intel_modeset_update_state(struct drm_atomic_state *state) |
ea9d758d | 12259 | { |
0a9ab303 | 12260 | struct drm_device *dev = state->dev; |
ea9d758d | 12261 | struct intel_encoder *intel_encoder; |
0a9ab303 ACO |
12262 | struct drm_crtc *crtc; |
12263 | struct drm_crtc_state *crtc_state; | |
ea9d758d | 12264 | struct drm_connector *connector; |
8a75d157 | 12265 | int i; |
ea9d758d | 12266 | |
de419ab6 | 12267 | intel_shared_dpll_commit(state); |
ba41c0de | 12268 | |
b2784e15 | 12269 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
12270 | if (!intel_encoder->base.crtc) |
12271 | continue; | |
12272 | ||
69024de8 ML |
12273 | crtc = intel_encoder->base.crtc; |
12274 | crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); | |
12275 | if (!crtc_state || !needs_modeset(crtc->state)) | |
12276 | continue; | |
ea9d758d | 12277 | |
69024de8 | 12278 | intel_encoder->connectors_active = false; |
ea9d758d DV |
12279 | } |
12280 | ||
3cb480bc | 12281 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
ea9d758d | 12282 | |
7668851f | 12283 | /* Double check state. */ |
8a75d157 | 12284 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
0a9ab303 | 12285 | WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc)); |
3cb480bc ML |
12286 | |
12287 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); | |
fc467a22 ML |
12288 | |
12289 | /* Update hwmode for vblank functions */ | |
12290 | if (crtc->state->active) | |
12291 | crtc->hwmode = crtc->state->adjusted_mode; | |
12292 | else | |
12293 | crtc->hwmode.crtc_clock = 0; | |
ea9d758d DV |
12294 | } |
12295 | ||
12296 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
12297 | if (!connector->encoder || !connector->encoder->crtc) | |
12298 | continue; | |
12299 | ||
69024de8 ML |
12300 | crtc = connector->encoder->crtc; |
12301 | crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); | |
12302 | if (!crtc_state || !needs_modeset(crtc->state)) | |
12303 | continue; | |
ea9d758d | 12304 | |
53d9f4e9 | 12305 | if (crtc->state->active) { |
69024de8 ML |
12306 | struct drm_property *dpms_property = |
12307 | dev->mode_config.dpms_property; | |
68d34720 | 12308 | |
69024de8 ML |
12309 | connector->dpms = DRM_MODE_DPMS_ON; |
12310 | drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON); | |
ea9d758d | 12311 | |
69024de8 ML |
12312 | intel_encoder = to_intel_encoder(connector->encoder); |
12313 | intel_encoder->connectors_active = true; | |
12314 | } else | |
12315 | connector->dpms = DRM_MODE_DPMS_OFF; | |
ea9d758d | 12316 | } |
ea9d758d DV |
12317 | } |
12318 | ||
3bd26263 | 12319 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12320 | { |
3bd26263 | 12321 | int diff; |
f1f644dc JB |
12322 | |
12323 | if (clock1 == clock2) | |
12324 | return true; | |
12325 | ||
12326 | if (!clock1 || !clock2) | |
12327 | return false; | |
12328 | ||
12329 | diff = abs(clock1 - clock2); | |
12330 | ||
12331 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12332 | return true; | |
12333 | ||
12334 | return false; | |
12335 | } | |
12336 | ||
25c5b266 DV |
12337 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12338 | list_for_each_entry((intel_crtc), \ | |
12339 | &(dev)->mode_config.crtc_list, \ | |
12340 | base.head) \ | |
0973f18f | 12341 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12342 | |
cfb23ed6 ML |
12343 | |
12344 | static bool | |
12345 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12346 | unsigned int m2, unsigned int n2, | |
12347 | bool exact) | |
12348 | { | |
12349 | if (m == m2 && n == n2) | |
12350 | return true; | |
12351 | ||
12352 | if (exact || !m || !n || !m2 || !n2) | |
12353 | return false; | |
12354 | ||
12355 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12356 | ||
12357 | if (m > m2) { | |
12358 | while (m > m2) { | |
12359 | m2 <<= 1; | |
12360 | n2 <<= 1; | |
12361 | } | |
12362 | } else if (m < m2) { | |
12363 | while (m < m2) { | |
12364 | m <<= 1; | |
12365 | n <<= 1; | |
12366 | } | |
12367 | } | |
12368 | ||
12369 | return m == m2 && n == n2; | |
12370 | } | |
12371 | ||
12372 | static bool | |
12373 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12374 | struct intel_link_m_n *m2_n2, | |
12375 | bool adjust) | |
12376 | { | |
12377 | if (m_n->tu == m2_n2->tu && | |
12378 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12379 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12380 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12381 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12382 | if (adjust) | |
12383 | *m2_n2 = *m_n; | |
12384 | ||
12385 | return true; | |
12386 | } | |
12387 | ||
12388 | return false; | |
12389 | } | |
12390 | ||
0e8ffe1b | 12391 | static bool |
2fa2fe9a | 12392 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12393 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12394 | struct intel_crtc_state *pipe_config, |
12395 | bool adjust) | |
0e8ffe1b | 12396 | { |
cfb23ed6 ML |
12397 | bool ret = true; |
12398 | ||
12399 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12400 | do { \ | |
12401 | if (!adjust) \ | |
12402 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12403 | else \ | |
12404 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12405 | } while (0) | |
12406 | ||
66e985c0 DV |
12407 | #define PIPE_CONF_CHECK_X(name) \ |
12408 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12409 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12410 | "(expected 0x%08x, found 0x%08x)\n", \ |
12411 | current_config->name, \ | |
12412 | pipe_config->name); \ | |
cfb23ed6 | 12413 | ret = false; \ |
66e985c0 DV |
12414 | } |
12415 | ||
08a24034 DV |
12416 | #define PIPE_CONF_CHECK_I(name) \ |
12417 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12418 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12419 | "(expected %i, found %i)\n", \ |
12420 | current_config->name, \ | |
12421 | pipe_config->name); \ | |
cfb23ed6 ML |
12422 | ret = false; \ |
12423 | } | |
12424 | ||
12425 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12426 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12427 | &pipe_config->name,\ | |
12428 | adjust)) { \ | |
12429 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12430 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12431 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12432 | current_config->name.tu, \ | |
12433 | current_config->name.gmch_m, \ | |
12434 | current_config->name.gmch_n, \ | |
12435 | current_config->name.link_m, \ | |
12436 | current_config->name.link_n, \ | |
12437 | pipe_config->name.tu, \ | |
12438 | pipe_config->name.gmch_m, \ | |
12439 | pipe_config->name.gmch_n, \ | |
12440 | pipe_config->name.link_m, \ | |
12441 | pipe_config->name.link_n); \ | |
12442 | ret = false; \ | |
12443 | } | |
12444 | ||
12445 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12446 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12447 | &pipe_config->name, adjust) && \ | |
12448 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12449 | &pipe_config->name, adjust)) { \ | |
12450 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12451 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12452 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12453 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12454 | current_config->name.tu, \ | |
12455 | current_config->name.gmch_m, \ | |
12456 | current_config->name.gmch_n, \ | |
12457 | current_config->name.link_m, \ | |
12458 | current_config->name.link_n, \ | |
12459 | current_config->alt_name.tu, \ | |
12460 | current_config->alt_name.gmch_m, \ | |
12461 | current_config->alt_name.gmch_n, \ | |
12462 | current_config->alt_name.link_m, \ | |
12463 | current_config->alt_name.link_n, \ | |
12464 | pipe_config->name.tu, \ | |
12465 | pipe_config->name.gmch_m, \ | |
12466 | pipe_config->name.gmch_n, \ | |
12467 | pipe_config->name.link_m, \ | |
12468 | pipe_config->name.link_n); \ | |
12469 | ret = false; \ | |
88adfff1 DV |
12470 | } |
12471 | ||
b95af8be VK |
12472 | /* This is required for BDW+ where there is only one set of registers for |
12473 | * switching between high and low RR. | |
12474 | * This macro can be used whenever a comparison has to be made between one | |
12475 | * hw state and multiple sw state variables. | |
12476 | */ | |
12477 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12478 | if ((current_config->name != pipe_config->name) && \ | |
12479 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12480 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12481 | "(expected %i or %i, found %i)\n", \ |
12482 | current_config->name, \ | |
12483 | current_config->alt_name, \ | |
12484 | pipe_config->name); \ | |
cfb23ed6 | 12485 | ret = false; \ |
b95af8be VK |
12486 | } |
12487 | ||
1bd1bd80 DV |
12488 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12489 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12490 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12491 | "(expected %i, found %i)\n", \ |
12492 | current_config->name & (mask), \ | |
12493 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12494 | ret = false; \ |
1bd1bd80 DV |
12495 | } |
12496 | ||
5e550656 VS |
12497 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12498 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12499 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12500 | "(expected %i, found %i)\n", \ |
12501 | current_config->name, \ | |
12502 | pipe_config->name); \ | |
cfb23ed6 | 12503 | ret = false; \ |
5e550656 VS |
12504 | } |
12505 | ||
bb760063 DV |
12506 | #define PIPE_CONF_QUIRK(quirk) \ |
12507 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12508 | ||
eccb140b DV |
12509 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12510 | ||
08a24034 DV |
12511 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12512 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12513 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12514 | |
eb14cb74 | 12515 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
12516 | |
12517 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12518 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12519 | ||
12520 | PIPE_CONF_CHECK_I(has_drrs); | |
12521 | if (current_config->has_drrs) | |
12522 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12523 | } else | |
12524 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12525 | |
2d112de7 ACO |
12526 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12527 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12528 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12529 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12530 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12531 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12532 | |
2d112de7 ACO |
12533 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12534 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12535 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12536 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12537 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12538 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12539 | |
c93f54cf | 12540 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12541 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12542 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12543 | IS_VALLEYVIEW(dev)) | |
12544 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12545 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12546 | |
9ed109a7 DV |
12547 | PIPE_CONF_CHECK_I(has_audio); |
12548 | ||
2d112de7 | 12549 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12550 | DRM_MODE_FLAG_INTERLACE); |
12551 | ||
bb760063 | 12552 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12553 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12554 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12555 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12556 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12557 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12558 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12559 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12560 | DRM_MODE_FLAG_NVSYNC); |
12561 | } | |
045ac3b5 | 12562 | |
37327abd VS |
12563 | PIPE_CONF_CHECK_I(pipe_src_w); |
12564 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 12565 | |
9953599b DV |
12566 | /* |
12567 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
12568 | * screen. Since we don't yet re-compute the pipe config when moving | |
12569 | * just the lvds port away to another pipe the sw tracking won't match. | |
12570 | * | |
12571 | * Proper atomic modesets with recomputed global state will fix this. | |
12572 | * Until then just don't check gmch state for inherited modes. | |
12573 | */ | |
12574 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
12575 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
12576 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
12577 | if (INTEL_INFO(dev)->gen < 4) | |
12578 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
12579 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
12580 | } | |
12581 | ||
fd4daa9c CW |
12582 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
12583 | if (current_config->pch_pfit.enabled) { | |
12584 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
12585 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
12586 | } | |
2fa2fe9a | 12587 | |
a1b2278e CK |
12588 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12589 | ||
e59150dc JB |
12590 | /* BDW+ don't expose a synchronous way to read the state */ |
12591 | if (IS_HASWELL(dev)) | |
12592 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12593 | |
282740f7 VS |
12594 | PIPE_CONF_CHECK_I(double_wide); |
12595 | ||
26804afd DV |
12596 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12597 | ||
c0d43d62 | 12598 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12599 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12600 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12601 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12602 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12603 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
12604 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12605 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12606 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12607 | |
42571aef VS |
12608 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12609 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12610 | ||
2d112de7 | 12611 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12612 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12613 | |
66e985c0 | 12614 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12615 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12616 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12617 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12618 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12619 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12620 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12621 | |
cfb23ed6 | 12622 | return ret; |
0e8ffe1b DV |
12623 | } |
12624 | ||
08db6652 DL |
12625 | static void check_wm_state(struct drm_device *dev) |
12626 | { | |
12627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12628 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12629 | struct intel_crtc *intel_crtc; | |
12630 | int plane; | |
12631 | ||
12632 | if (INTEL_INFO(dev)->gen < 9) | |
12633 | return; | |
12634 | ||
12635 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12636 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12637 | ||
12638 | for_each_intel_crtc(dev, intel_crtc) { | |
12639 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12640 | const enum pipe pipe = intel_crtc->pipe; | |
12641 | ||
12642 | if (!intel_crtc->active) | |
12643 | continue; | |
12644 | ||
12645 | /* planes */ | |
dd740780 | 12646 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12647 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12648 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12649 | ||
12650 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12651 | continue; | |
12652 | ||
12653 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12654 | "(expected (%u,%u), found (%u,%u))\n", | |
12655 | pipe_name(pipe), plane + 1, | |
12656 | sw_entry->start, sw_entry->end, | |
12657 | hw_entry->start, hw_entry->end); | |
12658 | } | |
12659 | ||
12660 | /* cursor */ | |
12661 | hw_entry = &hw_ddb.cursor[pipe]; | |
12662 | sw_entry = &sw_ddb->cursor[pipe]; | |
12663 | ||
12664 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12665 | continue; | |
12666 | ||
12667 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12668 | "(expected (%u,%u), found (%u,%u))\n", | |
12669 | pipe_name(pipe), | |
12670 | sw_entry->start, sw_entry->end, | |
12671 | hw_entry->start, hw_entry->end); | |
12672 | } | |
12673 | } | |
12674 | ||
91d1b4bd DV |
12675 | static void |
12676 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 12677 | { |
8af6cf88 DV |
12678 | struct intel_connector *connector; |
12679 | ||
3a3371ff | 12680 | for_each_intel_connector(dev, connector) { |
ad3c558f ML |
12681 | struct drm_encoder *encoder = connector->base.encoder; |
12682 | struct drm_connector_state *state = connector->base.state; | |
12683 | ||
8af6cf88 DV |
12684 | /* This also checks the encoder/connector hw state with the |
12685 | * ->get_hw_state callbacks. */ | |
12686 | intel_connector_check_state(connector); | |
12687 | ||
ad3c558f | 12688 | I915_STATE_WARN(state->best_encoder != encoder, |
8af6cf88 DV |
12689 | "connector's staged encoder doesn't match current encoder\n"); |
12690 | } | |
91d1b4bd DV |
12691 | } |
12692 | ||
12693 | static void | |
12694 | check_encoder_state(struct drm_device *dev) | |
12695 | { | |
12696 | struct intel_encoder *encoder; | |
12697 | struct intel_connector *connector; | |
8af6cf88 | 12698 | |
b2784e15 | 12699 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12700 | bool enabled = false; |
12701 | bool active = false; | |
12702 | enum pipe pipe, tracked_pipe; | |
12703 | ||
12704 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12705 | encoder->base.base.id, | |
8e329a03 | 12706 | encoder->base.name); |
8af6cf88 | 12707 | |
e2c719b7 | 12708 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
12709 | "encoder's active_connectors set, but no crtc\n"); |
12710 | ||
3a3371ff | 12711 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
12712 | if (connector->base.encoder != &encoder->base) |
12713 | continue; | |
12714 | enabled = true; | |
12715 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
12716 | active = true; | |
ad3c558f ML |
12717 | |
12718 | I915_STATE_WARN(connector->base.state->crtc != | |
12719 | encoder->base.crtc, | |
12720 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12721 | } |
0e32b39c DA |
12722 | /* |
12723 | * for MST connectors if we unplug the connector is gone | |
12724 | * away but the encoder is still connected to a crtc | |
12725 | * until a modeset happens in response to the hotplug. | |
12726 | */ | |
12727 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
12728 | continue; | |
12729 | ||
e2c719b7 | 12730 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12731 | "encoder's enabled state mismatch " |
12732 | "(expected %i, found %i)\n", | |
12733 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 12734 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
12735 | "active encoder with no crtc\n"); |
12736 | ||
e2c719b7 | 12737 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
12738 | "encoder's computed active state doesn't match tracked active state " |
12739 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
12740 | ||
12741 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 12742 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
12743 | "encoder's hw state doesn't match sw tracking " |
12744 | "(expected %i, found %i)\n", | |
12745 | encoder->connectors_active, active); | |
12746 | ||
12747 | if (!encoder->base.crtc) | |
12748 | continue; | |
12749 | ||
12750 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 12751 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
12752 | "active encoder's pipe doesn't match" |
12753 | "(expected %i, found %i)\n", | |
12754 | tracked_pipe, pipe); | |
12755 | ||
12756 | } | |
91d1b4bd DV |
12757 | } |
12758 | ||
12759 | static void | |
12760 | check_crtc_state(struct drm_device *dev) | |
12761 | { | |
fbee40df | 12762 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12763 | struct intel_crtc *crtc; |
12764 | struct intel_encoder *encoder; | |
5cec258b | 12765 | struct intel_crtc_state pipe_config; |
8af6cf88 | 12766 | |
d3fcc808 | 12767 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
12768 | bool enabled = false; |
12769 | bool active = false; | |
12770 | ||
045ac3b5 JB |
12771 | memset(&pipe_config, 0, sizeof(pipe_config)); |
12772 | ||
8af6cf88 DV |
12773 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12774 | crtc->base.base.id); | |
12775 | ||
83d65738 | 12776 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12777 | "active crtc, but not enabled in sw tracking\n"); |
12778 | ||
b2784e15 | 12779 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12780 | if (encoder->base.crtc != &crtc->base) |
12781 | continue; | |
12782 | enabled = true; | |
12783 | if (encoder->connectors_active) | |
12784 | active = true; | |
12785 | } | |
6c49f241 | 12786 | |
e2c719b7 | 12787 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12788 | "crtc's computed active state doesn't match tracked active state " |
12789 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12790 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12791 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12792 | "(expected %i, found %i)\n", enabled, |
12793 | crtc->base.state->enable); | |
8af6cf88 | 12794 | |
0e8ffe1b DV |
12795 | active = dev_priv->display.get_pipe_config(crtc, |
12796 | &pipe_config); | |
d62cf62a | 12797 | |
b6b5d049 VS |
12798 | /* hw state is inconsistent with the pipe quirk */ |
12799 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12800 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12801 | active = crtc->active; |
12802 | ||
b2784e15 | 12803 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12804 | enum pipe pipe; |
6c49f241 DV |
12805 | if (encoder->base.crtc != &crtc->base) |
12806 | continue; | |
1d37b689 | 12807 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12808 | encoder->get_config(encoder, &pipe_config); |
12809 | } | |
12810 | ||
e2c719b7 | 12811 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12812 | "crtc active state doesn't match with hw state " |
12813 | "(expected %i, found %i)\n", crtc->active, active); | |
12814 | ||
53d9f4e9 ML |
12815 | I915_STATE_WARN(crtc->active != crtc->base.state->active, |
12816 | "transitional active state does not match atomic hw state " | |
12817 | "(expected %i, found %i)\n", crtc->base.state->active, crtc->active); | |
12818 | ||
cfb23ed6 ML |
12819 | if (!active) |
12820 | continue; | |
12821 | ||
12822 | if (!intel_pipe_config_compare(dev, crtc->config, | |
12823 | &pipe_config, false)) { | |
e2c719b7 | 12824 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12825 | intel_dump_pipe_config(crtc, &pipe_config, |
12826 | "[hw state]"); | |
6e3c9717 | 12827 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12828 | "[sw state]"); |
12829 | } | |
8af6cf88 DV |
12830 | } |
12831 | } | |
12832 | ||
91d1b4bd DV |
12833 | static void |
12834 | check_shared_dpll_state(struct drm_device *dev) | |
12835 | { | |
fbee40df | 12836 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12837 | struct intel_crtc *crtc; |
12838 | struct intel_dpll_hw_state dpll_hw_state; | |
12839 | int i; | |
5358901f DV |
12840 | |
12841 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12842 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12843 | int enabled_crtcs = 0, active_crtcs = 0; | |
12844 | bool active; | |
12845 | ||
12846 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12847 | ||
12848 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12849 | ||
12850 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12851 | ||
e2c719b7 | 12852 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12853 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12854 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12855 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12856 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12857 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12858 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12859 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12860 | "pll on state mismatch (expected %i, found %i)\n", |
12861 | pll->on, active); | |
12862 | ||
d3fcc808 | 12863 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12864 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12865 | enabled_crtcs++; |
12866 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12867 | active_crtcs++; | |
12868 | } | |
e2c719b7 | 12869 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12870 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12871 | pll->active, active_crtcs); | |
e2c719b7 | 12872 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12873 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12874 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12875 | |
e2c719b7 | 12876 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12877 | sizeof(dpll_hw_state)), |
12878 | "pll hw state mismatch\n"); | |
5358901f | 12879 | } |
8af6cf88 DV |
12880 | } |
12881 | ||
91d1b4bd DV |
12882 | void |
12883 | intel_modeset_check_state(struct drm_device *dev) | |
12884 | { | |
08db6652 | 12885 | check_wm_state(dev); |
91d1b4bd DV |
12886 | check_connector_state(dev); |
12887 | check_encoder_state(dev); | |
12888 | check_crtc_state(dev); | |
12889 | check_shared_dpll_state(dev); | |
12890 | } | |
12891 | ||
5cec258b | 12892 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12893 | int dotclock) |
12894 | { | |
12895 | /* | |
12896 | * FDI already provided one idea for the dotclock. | |
12897 | * Yell if the encoder disagrees. | |
12898 | */ | |
2d112de7 | 12899 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12900 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12901 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12902 | } |
12903 | ||
80715b2f VS |
12904 | static void update_scanline_offset(struct intel_crtc *crtc) |
12905 | { | |
12906 | struct drm_device *dev = crtc->base.dev; | |
12907 | ||
12908 | /* | |
12909 | * The scanline counter increments at the leading edge of hsync. | |
12910 | * | |
12911 | * On most platforms it starts counting from vtotal-1 on the | |
12912 | * first active line. That means the scanline counter value is | |
12913 | * always one less than what we would expect. Ie. just after | |
12914 | * start of vblank, which also occurs at start of hsync (on the | |
12915 | * last active line), the scanline counter will read vblank_start-1. | |
12916 | * | |
12917 | * On gen2 the scanline counter starts counting from 1 instead | |
12918 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12919 | * to keep the value positive), instead of adding one. | |
12920 | * | |
12921 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12922 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12923 | * there's an extra 1 line difference. So we need to add two instead of | |
12924 | * one to the value. | |
12925 | */ | |
12926 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12927 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12928 | int vtotal; |
12929 | ||
12930 | vtotal = mode->crtc_vtotal; | |
12931 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12932 | vtotal /= 2; | |
12933 | ||
12934 | crtc->scanline_offset = vtotal - 1; | |
12935 | } else if (HAS_DDI(dev) && | |
409ee761 | 12936 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12937 | crtc->scanline_offset = 2; |
12938 | } else | |
12939 | crtc->scanline_offset = 1; | |
12940 | } | |
12941 | ||
ad421372 | 12942 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12943 | { |
225da59b | 12944 | struct drm_device *dev = state->dev; |
ed6739ef | 12945 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12946 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 12947 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12948 | struct intel_crtc_state *intel_crtc_state; |
12949 | struct drm_crtc *crtc; | |
12950 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12951 | int i; |
ed6739ef ACO |
12952 | |
12953 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12954 | return; |
ed6739ef | 12955 | |
0a9ab303 | 12956 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
12957 | int dpll; |
12958 | ||
0a9ab303 | 12959 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 12960 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 12961 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 12962 | |
ad421372 | 12963 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
12964 | continue; |
12965 | ||
ad421372 | 12966 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 12967 | |
ad421372 ML |
12968 | if (!shared_dpll) |
12969 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 12970 | |
ad421372 ML |
12971 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
12972 | } | |
ed6739ef ACO |
12973 | } |
12974 | ||
99d736a2 ML |
12975 | /* |
12976 | * This implements the workaround described in the "notes" section of the mode | |
12977 | * set sequence documentation. When going from no pipes or single pipe to | |
12978 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12979 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12980 | */ | |
12981 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12982 | { | |
12983 | struct drm_crtc_state *crtc_state; | |
12984 | struct intel_crtc *intel_crtc; | |
12985 | struct drm_crtc *crtc; | |
12986 | struct intel_crtc_state *first_crtc_state = NULL; | |
12987 | struct intel_crtc_state *other_crtc_state = NULL; | |
12988 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12989 | int i; | |
12990 | ||
12991 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12992 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12993 | intel_crtc = to_intel_crtc(crtc); | |
12994 | ||
12995 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12996 | continue; | |
12997 | ||
12998 | if (first_crtc_state) { | |
12999 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13000 | break; | |
13001 | } else { | |
13002 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13003 | first_pipe = intel_crtc->pipe; | |
13004 | } | |
13005 | } | |
13006 | ||
13007 | /* No workaround needed? */ | |
13008 | if (!first_crtc_state) | |
13009 | return 0; | |
13010 | ||
13011 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13012 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13013 | struct intel_crtc_state *pipe_config; | |
13014 | ||
13015 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13016 | if (IS_ERR(pipe_config)) | |
13017 | return PTR_ERR(pipe_config); | |
13018 | ||
13019 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13020 | ||
13021 | if (!pipe_config->base.active || | |
13022 | needs_modeset(&pipe_config->base)) | |
13023 | continue; | |
13024 | ||
13025 | /* 2 or more enabled crtcs means no need for w/a */ | |
13026 | if (enabled_pipe != INVALID_PIPE) | |
13027 | return 0; | |
13028 | ||
13029 | enabled_pipe = intel_crtc->pipe; | |
13030 | } | |
13031 | ||
13032 | if (enabled_pipe != INVALID_PIPE) | |
13033 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13034 | else if (other_crtc_state) | |
13035 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13036 | ||
13037 | return 0; | |
13038 | } | |
13039 | ||
27c329ed ML |
13040 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13041 | { | |
13042 | struct drm_crtc *crtc; | |
13043 | struct drm_crtc_state *crtc_state; | |
13044 | int ret = 0; | |
13045 | ||
13046 | /* add all active pipes to the state */ | |
13047 | for_each_crtc(state->dev, crtc) { | |
13048 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13049 | if (IS_ERR(crtc_state)) | |
13050 | return PTR_ERR(crtc_state); | |
13051 | ||
13052 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13053 | continue; | |
13054 | ||
13055 | crtc_state->mode_changed = true; | |
13056 | ||
13057 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13058 | if (ret) | |
13059 | break; | |
13060 | ||
13061 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13062 | if (ret) | |
13063 | break; | |
13064 | } | |
13065 | ||
13066 | return ret; | |
13067 | } | |
13068 | ||
13069 | ||
054518dd | 13070 | /* Code that should eventually be part of atomic_check() */ |
c347a676 | 13071 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
13072 | { |
13073 | struct drm_device *dev = state->dev; | |
27c329ed | 13074 | struct drm_i915_private *dev_priv = dev->dev_private; |
054518dd ACO |
13075 | int ret; |
13076 | ||
b359283a ML |
13077 | if (!check_digital_port_conflicts(state)) { |
13078 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13079 | return -EINVAL; | |
13080 | } | |
13081 | ||
054518dd ACO |
13082 | /* |
13083 | * See if the config requires any additional preparation, e.g. | |
13084 | * to adjust global state with pipes off. We need to do this | |
13085 | * here so we can get the modeset_pipe updated config for the new | |
13086 | * mode set on this crtc. For other crtcs we need to use the | |
13087 | * adjusted_mode bits in the crtc directly. | |
13088 | */ | |
27c329ed ML |
13089 | if (dev_priv->display.modeset_calc_cdclk) { |
13090 | unsigned int cdclk; | |
b432e5cf | 13091 | |
27c329ed ML |
13092 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13093 | ||
13094 | cdclk = to_intel_atomic_state(state)->cdclk; | |
13095 | if (!ret && cdclk != dev_priv->cdclk_freq) | |
13096 | ret = intel_modeset_all_pipes(state); | |
13097 | ||
13098 | if (ret < 0) | |
054518dd | 13099 | return ret; |
27c329ed ML |
13100 | } else |
13101 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; | |
054518dd | 13102 | |
ad421372 | 13103 | intel_modeset_clear_plls(state); |
054518dd | 13104 | |
99d736a2 | 13105 | if (IS_HASWELL(dev)) |
ad421372 | 13106 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13107 | |
ad421372 | 13108 | return 0; |
c347a676 ACO |
13109 | } |
13110 | ||
13111 | static int | |
13112 | intel_modeset_compute_config(struct drm_atomic_state *state) | |
13113 | { | |
13114 | struct drm_crtc *crtc; | |
13115 | struct drm_crtc_state *crtc_state; | |
13116 | int ret, i; | |
61333b60 | 13117 | bool any_ms = false; |
c347a676 ACO |
13118 | |
13119 | ret = drm_atomic_helper_check_modeset(state->dev, state); | |
054518dd ACO |
13120 | if (ret) |
13121 | return ret; | |
13122 | ||
c347a676 | 13123 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13124 | struct intel_crtc_state *pipe_config = |
13125 | to_intel_crtc_state(crtc_state); | |
5c1e3426 | 13126 | bool modeset, recalc = false; |
cfb23ed6 | 13127 | |
61333b60 ML |
13128 | if (!crtc_state->enable) { |
13129 | if (needs_modeset(crtc_state)) | |
13130 | any_ms = true; | |
c347a676 | 13131 | continue; |
61333b60 | 13132 | } |
c347a676 | 13133 | |
cfb23ed6 | 13134 | modeset = needs_modeset(crtc_state); |
5c1e3426 ML |
13135 | /* see comment in intel_modeset_readout_hw_state */ |
13136 | if (!modeset && crtc_state->mode_blob != crtc->state->mode_blob && | |
13137 | pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE) | |
13138 | recalc = true; | |
cfb23ed6 ML |
13139 | |
13140 | if (!modeset && !recalc) | |
13141 | continue; | |
13142 | ||
13143 | if (recalc) { | |
b359283a ML |
13144 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13145 | if (ret) | |
13146 | return ret; | |
13147 | } | |
13148 | ||
cfb23ed6 | 13149 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13150 | if (ret) |
13151 | return ret; | |
13152 | ||
5c1e3426 ML |
13153 | if (recalc && (!i915.fastboot || |
13154 | !intel_pipe_config_compare(state->dev, | |
cfb23ed6 | 13155 | to_intel_crtc_state(crtc->state), |
5c1e3426 | 13156 | pipe_config, true))) { |
cfb23ed6 ML |
13157 | modeset = crtc_state->mode_changed = true; |
13158 | ||
13159 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13160 | if (ret) | |
13161 | return ret; | |
13162 | } | |
61333b60 | 13163 | |
cfb23ed6 | 13164 | any_ms = modeset; |
c347a676 | 13165 | intel_dump_pipe_config(to_intel_crtc(crtc), |
cfb23ed6 ML |
13166 | pipe_config, |
13167 | modeset ? "[modeset]" : "[fastboot]"); | |
c347a676 ACO |
13168 | } |
13169 | ||
61333b60 ML |
13170 | if (any_ms) { |
13171 | ret = intel_modeset_checks(state); | |
13172 | ||
13173 | if (ret) | |
13174 | return ret; | |
27c329ed ML |
13175 | } else |
13176 | to_intel_atomic_state(state)->cdclk = | |
13177 | to_i915(state->dev)->cdclk_freq; | |
c347a676 ACO |
13178 | |
13179 | return drm_atomic_helper_check_planes(state->dev, state); | |
054518dd ACO |
13180 | } |
13181 | ||
c72d969b | 13182 | static int __intel_set_mode(struct drm_atomic_state *state) |
a6778b3c | 13183 | { |
c72d969b | 13184 | struct drm_device *dev = state->dev; |
fbee40df | 13185 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 ACO |
13186 | struct drm_crtc *crtc; |
13187 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 13188 | int ret = 0; |
0a9ab303 | 13189 | int i; |
61333b60 | 13190 | bool any_ms = false; |
a6778b3c | 13191 | |
d4afb8cc ACO |
13192 | ret = drm_atomic_helper_prepare_planes(dev, state); |
13193 | if (ret) | |
13194 | return ret; | |
13195 | ||
1c5e19f8 ML |
13196 | drm_atomic_helper_swap_state(dev, state); |
13197 | ||
0a9ab303 | 13198 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13200 | ||
61333b60 ML |
13201 | if (!needs_modeset(crtc->state)) |
13202 | continue; | |
13203 | ||
13204 | any_ms = true; | |
a539205a | 13205 | intel_pre_plane_update(intel_crtc); |
460da916 | 13206 | |
a539205a ML |
13207 | if (crtc_state->active) { |
13208 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13209 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13210 | intel_crtc->active = false; |
13211 | intel_disable_shared_dpll(intel_crtc); | |
a539205a | 13212 | } |
b8cecdf5 | 13213 | } |
7758a113 | 13214 | |
ea9d758d DV |
13215 | /* Only after disabling all output pipelines that will be changed can we |
13216 | * update the the output configuration. */ | |
0a9ab303 | 13217 | intel_modeset_update_state(state); |
f6e5b160 | 13218 | |
a821fc46 ACO |
13219 | /* The state has been swaped above, so state actually contains the |
13220 | * old state now. */ | |
61333b60 ML |
13221 | if (any_ms) |
13222 | modeset_update_crtc_power_domains(state); | |
47fab737 | 13223 | |
a6778b3c | 13224 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13225 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13226 | if (needs_modeset(crtc->state) && crtc->state->active) { |
13227 | update_scanline_offset(to_intel_crtc(crtc)); | |
13228 | dev_priv->display.crtc_enable(crtc); | |
13229 | } | |
80715b2f | 13230 | |
a539205a | 13231 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
80715b2f | 13232 | } |
a6778b3c | 13233 | |
a6778b3c | 13234 | /* FIXME: add subpixel order */ |
83a57153 | 13235 | |
d4afb8cc ACO |
13236 | drm_atomic_helper_cleanup_planes(dev, state); |
13237 | ||
2bfb4627 ACO |
13238 | drm_atomic_state_free(state); |
13239 | ||
9eb45f22 | 13240 | return 0; |
f6e5b160 CW |
13241 | } |
13242 | ||
568c634a | 13243 | static int intel_set_mode_checked(struct drm_atomic_state *state) |
f30da187 | 13244 | { |
568c634a | 13245 | struct drm_device *dev = state->dev; |
f30da187 DV |
13246 | int ret; |
13247 | ||
568c634a | 13248 | ret = __intel_set_mode(state); |
f30da187 | 13249 | if (ret == 0) |
568c634a | 13250 | intel_modeset_check_state(dev); |
f30da187 DV |
13251 | |
13252 | return ret; | |
13253 | } | |
13254 | ||
568c634a | 13255 | static int intel_set_mode(struct drm_atomic_state *state) |
7f27126e | 13256 | { |
568c634a | 13257 | int ret; |
83a57153 | 13258 | |
568c634a | 13259 | ret = intel_modeset_compute_config(state); |
83a57153 | 13260 | if (ret) |
568c634a | 13261 | return ret; |
7f27126e | 13262 | |
568c634a | 13263 | return intel_set_mode_checked(state); |
7f27126e JB |
13264 | } |
13265 | ||
c0c36b94 CW |
13266 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13267 | { | |
83a57153 ACO |
13268 | struct drm_device *dev = crtc->dev; |
13269 | struct drm_atomic_state *state; | |
e694eb02 | 13270 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13271 | int ret; |
83a57153 ACO |
13272 | |
13273 | state = drm_atomic_state_alloc(dev); | |
13274 | if (!state) { | |
e694eb02 | 13275 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13276 | crtc->base.id); |
13277 | return; | |
13278 | } | |
13279 | ||
e694eb02 | 13280 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13281 | |
e694eb02 ML |
13282 | retry: |
13283 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13284 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13285 | if (!ret) { | |
13286 | if (!crtc_state->active) | |
13287 | goto out; | |
83a57153 | 13288 | |
e694eb02 ML |
13289 | crtc_state->mode_changed = true; |
13290 | ret = intel_set_mode(state); | |
83a57153 ACO |
13291 | } |
13292 | ||
e694eb02 ML |
13293 | if (ret == -EDEADLK) { |
13294 | drm_atomic_state_clear(state); | |
13295 | drm_modeset_backoff(state->acquire_ctx); | |
13296 | goto retry; | |
4ed9fb37 | 13297 | } |
4be07317 | 13298 | |
2bfb4627 | 13299 | if (ret) |
e694eb02 | 13300 | out: |
2bfb4627 | 13301 | drm_atomic_state_free(state); |
c0c36b94 CW |
13302 | } |
13303 | ||
25c5b266 DV |
13304 | #undef for_each_intel_crtc_masked |
13305 | ||
b7885264 ACO |
13306 | static bool intel_connector_in_mode_set(struct intel_connector *connector, |
13307 | struct drm_mode_set *set) | |
13308 | { | |
13309 | int ro; | |
13310 | ||
13311 | for (ro = 0; ro < set->num_connectors; ro++) | |
13312 | if (set->connectors[ro] == &connector->base) | |
13313 | return true; | |
13314 | ||
13315 | return false; | |
13316 | } | |
13317 | ||
2e431051 | 13318 | static int |
9a935856 DV |
13319 | intel_modeset_stage_output_state(struct drm_device *dev, |
13320 | struct drm_mode_set *set, | |
944b0c76 | 13321 | struct drm_atomic_state *state) |
50f56119 | 13322 | { |
9a935856 | 13323 | struct intel_connector *connector; |
d5432a9d | 13324 | struct drm_connector *drm_connector; |
944b0c76 | 13325 | struct drm_connector_state *connector_state; |
d5432a9d ACO |
13326 | struct drm_crtc *crtc; |
13327 | struct drm_crtc_state *crtc_state; | |
13328 | int i, ret; | |
50f56119 | 13329 | |
9abdda74 | 13330 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
13331 | * of connectors. For paranoia, double-check this. */ |
13332 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
13333 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
13334 | ||
3a3371ff | 13335 | for_each_intel_connector(dev, connector) { |
b7885264 ACO |
13336 | bool in_mode_set = intel_connector_in_mode_set(connector, set); |
13337 | ||
d5432a9d ACO |
13338 | if (!in_mode_set && connector->base.state->crtc != set->crtc) |
13339 | continue; | |
13340 | ||
13341 | connector_state = | |
13342 | drm_atomic_get_connector_state(state, &connector->base); | |
13343 | if (IS_ERR(connector_state)) | |
13344 | return PTR_ERR(connector_state); | |
13345 | ||
b7885264 ACO |
13346 | if (in_mode_set) { |
13347 | int pipe = to_intel_crtc(set->crtc)->pipe; | |
d5432a9d ACO |
13348 | connector_state->best_encoder = |
13349 | &intel_find_encoder(connector, pipe)->base; | |
50f56119 DV |
13350 | } |
13351 | ||
d5432a9d | 13352 | if (connector->base.state->crtc != set->crtc) |
b7885264 ACO |
13353 | continue; |
13354 | ||
9a935856 DV |
13355 | /* If we disable the crtc, disable all its connectors. Also, if |
13356 | * the connector is on the changing crtc but not on the new | |
13357 | * connector list, disable it. */ | |
b7885264 | 13358 | if (!set->fb || !in_mode_set) { |
d5432a9d | 13359 | connector_state->best_encoder = NULL; |
9a935856 DV |
13360 | |
13361 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
13362 | connector->base.base.id, | |
c23cc417 | 13363 | connector->base.name); |
9a935856 | 13364 | } |
50f56119 | 13365 | } |
9a935856 | 13366 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 13367 | |
d5432a9d ACO |
13368 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
13369 | connector = to_intel_connector(drm_connector); | |
13370 | ||
13371 | if (!connector_state->best_encoder) { | |
13372 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
13373 | NULL); | |
13374 | if (ret) | |
13375 | return ret; | |
7668851f | 13376 | |
50f56119 | 13377 | continue; |
d5432a9d | 13378 | } |
50f56119 | 13379 | |
d5432a9d ACO |
13380 | if (intel_connector_in_mode_set(connector, set)) { |
13381 | struct drm_crtc *crtc = connector->base.state->crtc; | |
13382 | ||
13383 | /* If this connector was in a previous crtc, add it | |
13384 | * to the state. We might need to disable it. */ | |
13385 | if (crtc) { | |
13386 | crtc_state = | |
13387 | drm_atomic_get_crtc_state(state, crtc); | |
13388 | if (IS_ERR(crtc_state)) | |
13389 | return PTR_ERR(crtc_state); | |
13390 | } | |
13391 | ||
13392 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
13393 | set->crtc); | |
13394 | if (ret) | |
13395 | return ret; | |
13396 | } | |
50f56119 DV |
13397 | |
13398 | /* Make sure the new CRTC will work with the encoder */ | |
d5432a9d ACO |
13399 | if (!drm_encoder_crtc_ok(connector_state->best_encoder, |
13400 | connector_state->crtc)) { | |
5e2b584e | 13401 | return -EINVAL; |
50f56119 | 13402 | } |
944b0c76 | 13403 | |
9a935856 DV |
13404 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
13405 | connector->base.base.id, | |
c23cc417 | 13406 | connector->base.name, |
d5432a9d | 13407 | connector_state->crtc->base.id); |
944b0c76 | 13408 | |
d5432a9d ACO |
13409 | if (connector_state->best_encoder != &connector->encoder->base) |
13410 | connector->encoder = | |
13411 | to_intel_encoder(connector_state->best_encoder); | |
0e32b39c | 13412 | } |
7668851f | 13413 | |
d5432a9d | 13414 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
49d6fa21 ML |
13415 | bool has_connectors; |
13416 | ||
d5432a9d ACO |
13417 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13418 | if (ret) | |
13419 | return ret; | |
4be07317 | 13420 | |
49d6fa21 ML |
13421 | has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc); |
13422 | if (has_connectors != crtc_state->enable) | |
13423 | crtc_state->enable = | |
13424 | crtc_state->active = has_connectors; | |
7668851f VS |
13425 | } |
13426 | ||
8c7b5ccb ACO |
13427 | ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, |
13428 | set->fb, set->x, set->y); | |
13429 | if (ret) | |
13430 | return ret; | |
13431 | ||
13432 | crtc_state = drm_atomic_get_crtc_state(state, set->crtc); | |
13433 | if (IS_ERR(crtc_state)) | |
13434 | return PTR_ERR(crtc_state); | |
13435 | ||
ce52299c MR |
13436 | ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode); |
13437 | if (ret) | |
13438 | return ret; | |
8c7b5ccb ACO |
13439 | |
13440 | if (set->num_connectors) | |
13441 | crtc_state->active = true; | |
13442 | ||
2e431051 DV |
13443 | return 0; |
13444 | } | |
13445 | ||
13446 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
13447 | { | |
13448 | struct drm_device *dev; | |
83a57153 | 13449 | struct drm_atomic_state *state = NULL; |
2e431051 | 13450 | int ret; |
2e431051 | 13451 | |
8d3e375e DV |
13452 | BUG_ON(!set); |
13453 | BUG_ON(!set->crtc); | |
13454 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 13455 | |
7e53f3a4 DV |
13456 | /* Enforce sane interface api - has been abused by the fb helper. */ |
13457 | BUG_ON(!set->mode && set->fb); | |
13458 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 13459 | |
2e431051 DV |
13460 | if (set->fb) { |
13461 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
13462 | set->crtc->base.id, set->fb->base.id, | |
13463 | (int)set->num_connectors, set->x, set->y); | |
13464 | } else { | |
13465 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
13466 | } |
13467 | ||
13468 | dev = set->crtc->dev; | |
13469 | ||
83a57153 | 13470 | state = drm_atomic_state_alloc(dev); |
7cbf41d6 ACO |
13471 | if (!state) |
13472 | return -ENOMEM; | |
83a57153 ACO |
13473 | |
13474 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
13475 | ||
462a425a | 13476 | ret = intel_modeset_stage_output_state(dev, set, state); |
2e431051 | 13477 | if (ret) |
7cbf41d6 | 13478 | goto out; |
2e431051 | 13479 | |
568c634a ACO |
13480 | ret = intel_modeset_compute_config(state); |
13481 | if (ret) | |
7cbf41d6 | 13482 | goto out; |
50f52756 | 13483 | |
1f9954d0 JB |
13484 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
13485 | ||
568c634a | 13486 | ret = intel_set_mode_checked(state); |
2d05eae1 | 13487 | if (ret) { |
bf67dfeb DV |
13488 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
13489 | set->crtc->base.id, ret); | |
2d05eae1 | 13490 | } |
50f56119 | 13491 | |
7cbf41d6 | 13492 | out: |
2bfb4627 ACO |
13493 | if (ret) |
13494 | drm_atomic_state_free(state); | |
50f56119 DV |
13495 | return ret; |
13496 | } | |
f6e5b160 CW |
13497 | |
13498 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 13499 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 13500 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
13501 | .destroy = intel_crtc_destroy, |
13502 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13503 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13504 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13505 | }; |
13506 | ||
5358901f DV |
13507 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13508 | struct intel_shared_dpll *pll, | |
13509 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13510 | { |
5358901f | 13511 | uint32_t val; |
ee7b9f93 | 13512 | |
f458ebbc | 13513 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13514 | return false; |
13515 | ||
5358901f | 13516 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13517 | hw_state->dpll = val; |
13518 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13519 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13520 | |
13521 | return val & DPLL_VCO_ENABLE; | |
13522 | } | |
13523 | ||
15bdd4cf DV |
13524 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13525 | struct intel_shared_dpll *pll) | |
13526 | { | |
3e369b76 ACO |
13527 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13528 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13529 | } |
13530 | ||
e7b903d2 DV |
13531 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13532 | struct intel_shared_dpll *pll) | |
13533 | { | |
e7b903d2 | 13534 | /* PCH refclock must be enabled first */ |
89eff4be | 13535 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13536 | |
3e369b76 | 13537 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13538 | |
13539 | /* Wait for the clocks to stabilize. */ | |
13540 | POSTING_READ(PCH_DPLL(pll->id)); | |
13541 | udelay(150); | |
13542 | ||
13543 | /* The pixel multiplier can only be updated once the | |
13544 | * DPLL is enabled and the clocks are stable. | |
13545 | * | |
13546 | * So write it again. | |
13547 | */ | |
3e369b76 | 13548 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13549 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13550 | udelay(200); |
13551 | } | |
13552 | ||
13553 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13554 | struct intel_shared_dpll *pll) | |
13555 | { | |
13556 | struct drm_device *dev = dev_priv->dev; | |
13557 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13558 | |
13559 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13560 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13561 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13562 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13563 | } |
13564 | ||
15bdd4cf DV |
13565 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13566 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13567 | udelay(200); |
13568 | } | |
13569 | ||
46edb027 DV |
13570 | static char *ibx_pch_dpll_names[] = { |
13571 | "PCH DPLL A", | |
13572 | "PCH DPLL B", | |
13573 | }; | |
13574 | ||
7c74ade1 | 13575 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13576 | { |
e7b903d2 | 13577 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13578 | int i; |
13579 | ||
7c74ade1 | 13580 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13581 | |
e72f9fbf | 13582 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13583 | dev_priv->shared_dplls[i].id = i; |
13584 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13585 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13586 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13587 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13588 | dev_priv->shared_dplls[i].get_hw_state = |
13589 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13590 | } |
13591 | } | |
13592 | ||
7c74ade1 DV |
13593 | static void intel_shared_dpll_init(struct drm_device *dev) |
13594 | { | |
e7b903d2 | 13595 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13596 | |
b6283055 VS |
13597 | intel_update_cdclk(dev); |
13598 | ||
9cd86933 DV |
13599 | if (HAS_DDI(dev)) |
13600 | intel_ddi_pll_init(dev); | |
13601 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13602 | ibx_pch_dpll_init(dev); |
13603 | else | |
13604 | dev_priv->num_shared_dpll = 0; | |
13605 | ||
13606 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13607 | } |
13608 | ||
6beb8c23 MR |
13609 | /** |
13610 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13611 | * @plane: drm plane to prepare for | |
13612 | * @fb: framebuffer to prepare for presentation | |
13613 | * | |
13614 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13615 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13616 | * bits. Some older platforms need special physical address handling for | |
13617 | * cursor planes. | |
13618 | * | |
13619 | * Returns 0 on success, negative error code on failure. | |
13620 | */ | |
13621 | int | |
13622 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13623 | struct drm_framebuffer *fb, |
13624 | const struct drm_plane_state *new_state) | |
465c120c MR |
13625 | { |
13626 | struct drm_device *dev = plane->dev; | |
6beb8c23 | 13627 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 MR |
13628 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
13629 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
6beb8c23 | 13630 | int ret = 0; |
465c120c | 13631 | |
ea2c67bb | 13632 | if (!obj) |
465c120c MR |
13633 | return 0; |
13634 | ||
6beb8c23 | 13635 | mutex_lock(&dev->struct_mutex); |
465c120c | 13636 | |
6beb8c23 MR |
13637 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13638 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13639 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13640 | ret = i915_gem_object_attach_phys(obj, align); | |
13641 | if (ret) | |
13642 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13643 | } else { | |
91af127f | 13644 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); |
6beb8c23 | 13645 | } |
465c120c | 13646 | |
6beb8c23 | 13647 | if (ret == 0) |
a9ff8714 | 13648 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
fdd508a6 | 13649 | |
4c34574f | 13650 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13651 | |
6beb8c23 MR |
13652 | return ret; |
13653 | } | |
13654 | ||
38f3ce3a MR |
13655 | /** |
13656 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13657 | * @plane: drm plane to clean up for | |
13658 | * @fb: old framebuffer that was on plane | |
13659 | * | |
13660 | * Cleans up a framebuffer that has just been removed from a plane. | |
13661 | */ | |
13662 | void | |
13663 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13664 | struct drm_framebuffer *fb, |
13665 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13666 | { |
13667 | struct drm_device *dev = plane->dev; | |
13668 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13669 | ||
13670 | if (WARN_ON(!obj)) | |
13671 | return; | |
13672 | ||
13673 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13674 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13675 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13676 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13677 | mutex_unlock(&dev->struct_mutex); |
13678 | } | |
465c120c MR |
13679 | } |
13680 | ||
6156a456 CK |
13681 | int |
13682 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13683 | { | |
13684 | int max_scale; | |
13685 | struct drm_device *dev; | |
13686 | struct drm_i915_private *dev_priv; | |
13687 | int crtc_clock, cdclk; | |
13688 | ||
13689 | if (!intel_crtc || !crtc_state) | |
13690 | return DRM_PLANE_HELPER_NO_SCALING; | |
13691 | ||
13692 | dev = intel_crtc->base.dev; | |
13693 | dev_priv = dev->dev_private; | |
13694 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13695 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 CK |
13696 | |
13697 | if (!crtc_clock || !cdclk) | |
13698 | return DRM_PLANE_HELPER_NO_SCALING; | |
13699 | ||
13700 | /* | |
13701 | * skl max scale is lower of: | |
13702 | * close to 3 but not 3, -1 is for that purpose | |
13703 | * or | |
13704 | * cdclk/crtc_clock | |
13705 | */ | |
13706 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13707 | ||
13708 | return max_scale; | |
13709 | } | |
13710 | ||
465c120c | 13711 | static int |
3c692a41 | 13712 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13713 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13714 | struct intel_plane_state *state) |
13715 | { | |
2b875c22 MR |
13716 | struct drm_crtc *crtc = state->base.crtc; |
13717 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13718 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13719 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13720 | bool can_position = false; | |
465c120c | 13721 | |
061e4b8d ML |
13722 | /* use scaler when colorkey is not required */ |
13723 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13724 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13725 | min_scale = 1; |
13726 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13727 | can_position = true; |
6156a456 | 13728 | } |
d8106366 | 13729 | |
061e4b8d ML |
13730 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13731 | &state->dst, &state->clip, | |
da20eabd ML |
13732 | min_scale, max_scale, |
13733 | can_position, true, | |
13734 | &state->visible); | |
14af293f GP |
13735 | } |
13736 | ||
13737 | static void | |
13738 | intel_commit_primary_plane(struct drm_plane *plane, | |
13739 | struct intel_plane_state *state) | |
13740 | { | |
2b875c22 MR |
13741 | struct drm_crtc *crtc = state->base.crtc; |
13742 | struct drm_framebuffer *fb = state->base.fb; | |
13743 | struct drm_device *dev = plane->dev; | |
14af293f | 13744 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13745 | struct intel_crtc *intel_crtc; |
14af293f GP |
13746 | struct drm_rect *src = &state->src; |
13747 | ||
ea2c67bb MR |
13748 | crtc = crtc ? crtc : plane->crtc; |
13749 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13750 | |
13751 | plane->fb = fb; | |
9dc806fc MR |
13752 | crtc->x = src->x1 >> 16; |
13753 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13754 | |
a539205a | 13755 | if (!crtc->state->active) |
302d19ac | 13756 | return; |
465c120c | 13757 | |
302d19ac ML |
13758 | if (state->visible) |
13759 | /* FIXME: kill this fastboot hack */ | |
13760 | intel_update_pipe_size(intel_crtc); | |
13761 | ||
13762 | dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y); | |
465c120c MR |
13763 | } |
13764 | ||
a8ad0d8e ML |
13765 | static void |
13766 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13767 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13768 | { |
13769 | struct drm_device *dev = plane->dev; | |
13770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13771 | ||
a8ad0d8e ML |
13772 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13773 | } | |
13774 | ||
32b7eeec | 13775 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13776 | { |
32b7eeec | 13777 | struct drm_device *dev = crtc->dev; |
140fd38d | 13778 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3c692a41 | 13780 | |
a539205a ML |
13781 | if (!needs_modeset(crtc->state)) |
13782 | intel_pre_plane_update(intel_crtc); | |
3c692a41 | 13783 | |
f015c551 | 13784 | if (intel_crtc->atomic.update_wm_pre) |
32b7eeec | 13785 | intel_update_watermarks(crtc); |
3c692a41 | 13786 | |
32b7eeec | 13787 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13788 | |
c34c9ee4 | 13789 | /* Perform vblank evasion around commit operation */ |
a539205a | 13790 | if (crtc->state->active) |
c34c9ee4 MR |
13791 | intel_crtc->atomic.evade = |
13792 | intel_pipe_update_start(intel_crtc, | |
13793 | &intel_crtc->atomic.start_vbl_count); | |
0583236e ML |
13794 | |
13795 | if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9) | |
13796 | skl_detach_scalers(intel_crtc); | |
32b7eeec MR |
13797 | } |
13798 | ||
13799 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13800 | { | |
13801 | struct drm_device *dev = crtc->dev; | |
13802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13803 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
32b7eeec | 13804 | |
c34c9ee4 MR |
13805 | if (intel_crtc->atomic.evade) |
13806 | intel_pipe_update_end(intel_crtc, | |
13807 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13808 | |
140fd38d | 13809 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13810 | |
ac21b225 | 13811 | intel_post_plane_update(intel_crtc); |
3c692a41 GP |
13812 | } |
13813 | ||
cf4c7c12 | 13814 | /** |
4a3b8769 MR |
13815 | * intel_plane_destroy - destroy a plane |
13816 | * @plane: plane to destroy | |
cf4c7c12 | 13817 | * |
4a3b8769 MR |
13818 | * Common destruction function for all types of planes (primary, cursor, |
13819 | * sprite). | |
cf4c7c12 | 13820 | */ |
4a3b8769 | 13821 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13822 | { |
13823 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13824 | drm_plane_cleanup(plane); | |
13825 | kfree(intel_plane); | |
13826 | } | |
13827 | ||
65a3fea0 | 13828 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13829 | .update_plane = drm_atomic_helper_update_plane, |
13830 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13831 | .destroy = intel_plane_destroy, |
c196e1d6 | 13832 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13833 | .atomic_get_property = intel_plane_atomic_get_property, |
13834 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13835 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13836 | .atomic_destroy_state = intel_plane_destroy_state, | |
13837 | ||
465c120c MR |
13838 | }; |
13839 | ||
13840 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13841 | int pipe) | |
13842 | { | |
13843 | struct intel_plane *primary; | |
8e7d688b | 13844 | struct intel_plane_state *state; |
465c120c MR |
13845 | const uint32_t *intel_primary_formats; |
13846 | int num_formats; | |
13847 | ||
13848 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13849 | if (primary == NULL) | |
13850 | return NULL; | |
13851 | ||
8e7d688b MR |
13852 | state = intel_create_plane_state(&primary->base); |
13853 | if (!state) { | |
ea2c67bb MR |
13854 | kfree(primary); |
13855 | return NULL; | |
13856 | } | |
8e7d688b | 13857 | primary->base.state = &state->base; |
ea2c67bb | 13858 | |
465c120c MR |
13859 | primary->can_scale = false; |
13860 | primary->max_downscale = 1; | |
6156a456 CK |
13861 | if (INTEL_INFO(dev)->gen >= 9) { |
13862 | primary->can_scale = true; | |
af99ceda | 13863 | state->scaler_id = -1; |
6156a456 | 13864 | } |
465c120c MR |
13865 | primary->pipe = pipe; |
13866 | primary->plane = pipe; | |
a9ff8714 | 13867 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
13868 | primary->check_plane = intel_check_primary_plane; |
13869 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13870 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
13871 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13872 | primary->plane = !pipe; | |
13873 | ||
6c0fd451 DL |
13874 | if (INTEL_INFO(dev)->gen >= 9) { |
13875 | intel_primary_formats = skl_primary_formats; | |
13876 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13877 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13878 | intel_primary_formats = i965_primary_formats; |
13879 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13880 | } else { |
13881 | intel_primary_formats = i8xx_primary_formats; | |
13882 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13883 | } |
13884 | ||
13885 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13886 | &intel_plane_funcs, |
465c120c MR |
13887 | intel_primary_formats, num_formats, |
13888 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13889 | |
3b7a5119 SJ |
13890 | if (INTEL_INFO(dev)->gen >= 4) |
13891 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13892 | |
ea2c67bb MR |
13893 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13894 | ||
465c120c MR |
13895 | return &primary->base; |
13896 | } | |
13897 | ||
3b7a5119 SJ |
13898 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13899 | { | |
13900 | if (!dev->mode_config.rotation_property) { | |
13901 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13902 | BIT(DRM_ROTATE_180); | |
13903 | ||
13904 | if (INTEL_INFO(dev)->gen >= 9) | |
13905 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13906 | ||
13907 | dev->mode_config.rotation_property = | |
13908 | drm_mode_create_rotation_property(dev, flags); | |
13909 | } | |
13910 | if (dev->mode_config.rotation_property) | |
13911 | drm_object_attach_property(&plane->base.base, | |
13912 | dev->mode_config.rotation_property, | |
13913 | plane->base.state->rotation); | |
13914 | } | |
13915 | ||
3d7d6510 | 13916 | static int |
852e787c | 13917 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13918 | struct intel_crtc_state *crtc_state, |
852e787c | 13919 | struct intel_plane_state *state) |
3d7d6510 | 13920 | { |
061e4b8d | 13921 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13922 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13923 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
757f9a3e GP |
13924 | unsigned stride; |
13925 | int ret; | |
3d7d6510 | 13926 | |
061e4b8d ML |
13927 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13928 | &state->dst, &state->clip, | |
3d7d6510 MR |
13929 | DRM_PLANE_HELPER_NO_SCALING, |
13930 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13931 | true, true, &state->visible); |
757f9a3e GP |
13932 | if (ret) |
13933 | return ret; | |
13934 | ||
757f9a3e GP |
13935 | /* if we want to turn off the cursor ignore width and height */ |
13936 | if (!obj) | |
da20eabd | 13937 | return 0; |
757f9a3e | 13938 | |
757f9a3e | 13939 | /* Check for which cursor types we support */ |
061e4b8d | 13940 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
13941 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13942 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13943 | return -EINVAL; |
13944 | } | |
13945 | ||
ea2c67bb MR |
13946 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13947 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13948 | DRM_DEBUG_KMS("buffer is too small\n"); |
13949 | return -ENOMEM; | |
13950 | } | |
13951 | ||
3a656b54 | 13952 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13953 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13954 | return -EINVAL; |
32b7eeec MR |
13955 | } |
13956 | ||
da20eabd | 13957 | return 0; |
852e787c | 13958 | } |
3d7d6510 | 13959 | |
a8ad0d8e ML |
13960 | static void |
13961 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13962 | struct drm_crtc *crtc) |
a8ad0d8e | 13963 | { |
a8ad0d8e ML |
13964 | intel_crtc_update_cursor(crtc, false); |
13965 | } | |
13966 | ||
f4a2cf29 | 13967 | static void |
852e787c GP |
13968 | intel_commit_cursor_plane(struct drm_plane *plane, |
13969 | struct intel_plane_state *state) | |
13970 | { | |
2b875c22 | 13971 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13972 | struct drm_device *dev = plane->dev; |
13973 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13974 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13975 | uint32_t addr; |
852e787c | 13976 | |
ea2c67bb MR |
13977 | crtc = crtc ? crtc : plane->crtc; |
13978 | intel_crtc = to_intel_crtc(crtc); | |
13979 | ||
2b875c22 | 13980 | plane->fb = state->base.fb; |
ea2c67bb MR |
13981 | crtc->cursor_x = state->base.crtc_x; |
13982 | crtc->cursor_y = state->base.crtc_y; | |
13983 | ||
a912f12f GP |
13984 | if (intel_crtc->cursor_bo == obj) |
13985 | goto update; | |
4ed91096 | 13986 | |
f4a2cf29 | 13987 | if (!obj) |
a912f12f | 13988 | addr = 0; |
f4a2cf29 | 13989 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13990 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13991 | else |
a912f12f | 13992 | addr = obj->phys_handle->busaddr; |
852e787c | 13993 | |
a912f12f GP |
13994 | intel_crtc->cursor_addr = addr; |
13995 | intel_crtc->cursor_bo = obj; | |
852e787c | 13996 | |
302d19ac | 13997 | update: |
a539205a | 13998 | if (crtc->state->active) |
a912f12f | 13999 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
14000 | } |
14001 | ||
3d7d6510 MR |
14002 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14003 | int pipe) | |
14004 | { | |
14005 | struct intel_plane *cursor; | |
8e7d688b | 14006 | struct intel_plane_state *state; |
3d7d6510 MR |
14007 | |
14008 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14009 | if (cursor == NULL) | |
14010 | return NULL; | |
14011 | ||
8e7d688b MR |
14012 | state = intel_create_plane_state(&cursor->base); |
14013 | if (!state) { | |
ea2c67bb MR |
14014 | kfree(cursor); |
14015 | return NULL; | |
14016 | } | |
8e7d688b | 14017 | cursor->base.state = &state->base; |
ea2c67bb | 14018 | |
3d7d6510 MR |
14019 | cursor->can_scale = false; |
14020 | cursor->max_downscale = 1; | |
14021 | cursor->pipe = pipe; | |
14022 | cursor->plane = pipe; | |
a9ff8714 | 14023 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
14024 | cursor->check_plane = intel_check_cursor_plane; |
14025 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 14026 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14027 | |
14028 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14029 | &intel_plane_funcs, |
3d7d6510 MR |
14030 | intel_cursor_formats, |
14031 | ARRAY_SIZE(intel_cursor_formats), | |
14032 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14033 | |
14034 | if (INTEL_INFO(dev)->gen >= 4) { | |
14035 | if (!dev->mode_config.rotation_property) | |
14036 | dev->mode_config.rotation_property = | |
14037 | drm_mode_create_rotation_property(dev, | |
14038 | BIT(DRM_ROTATE_0) | | |
14039 | BIT(DRM_ROTATE_180)); | |
14040 | if (dev->mode_config.rotation_property) | |
14041 | drm_object_attach_property(&cursor->base.base, | |
14042 | dev->mode_config.rotation_property, | |
8e7d688b | 14043 | state->base.rotation); |
4398ad45 VS |
14044 | } |
14045 | ||
af99ceda CK |
14046 | if (INTEL_INFO(dev)->gen >=9) |
14047 | state->scaler_id = -1; | |
14048 | ||
ea2c67bb MR |
14049 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14050 | ||
3d7d6510 MR |
14051 | return &cursor->base; |
14052 | } | |
14053 | ||
549e2bfb CK |
14054 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14055 | struct intel_crtc_state *crtc_state) | |
14056 | { | |
14057 | int i; | |
14058 | struct intel_scaler *intel_scaler; | |
14059 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14060 | ||
14061 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14062 | intel_scaler = &scaler_state->scalers[i]; | |
14063 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14064 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14065 | } | |
14066 | ||
14067 | scaler_state->scaler_id = -1; | |
14068 | } | |
14069 | ||
b358d0a6 | 14070 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14071 | { |
fbee40df | 14072 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14073 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14074 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14075 | struct drm_plane *primary = NULL; |
14076 | struct drm_plane *cursor = NULL; | |
465c120c | 14077 | int i, ret; |
79e53945 | 14078 | |
955382f3 | 14079 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14080 | if (intel_crtc == NULL) |
14081 | return; | |
14082 | ||
f5de6e07 ACO |
14083 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14084 | if (!crtc_state) | |
14085 | goto fail; | |
550acefd ACO |
14086 | intel_crtc->config = crtc_state; |
14087 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14088 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14089 | |
549e2bfb CK |
14090 | /* initialize shared scalers */ |
14091 | if (INTEL_INFO(dev)->gen >= 9) { | |
14092 | if (pipe == PIPE_C) | |
14093 | intel_crtc->num_scalers = 1; | |
14094 | else | |
14095 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14096 | ||
14097 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14098 | } | |
14099 | ||
465c120c | 14100 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14101 | if (!primary) |
14102 | goto fail; | |
14103 | ||
14104 | cursor = intel_cursor_plane_create(dev, pipe); | |
14105 | if (!cursor) | |
14106 | goto fail; | |
14107 | ||
465c120c | 14108 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14109 | cursor, &intel_crtc_funcs); |
14110 | if (ret) | |
14111 | goto fail; | |
79e53945 JB |
14112 | |
14113 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14114 | for (i = 0; i < 256; i++) { |
14115 | intel_crtc->lut_r[i] = i; | |
14116 | intel_crtc->lut_g[i] = i; | |
14117 | intel_crtc->lut_b[i] = i; | |
14118 | } | |
14119 | ||
1f1c2e24 VS |
14120 | /* |
14121 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14122 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14123 | */ |
80824003 JB |
14124 | intel_crtc->pipe = pipe; |
14125 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14126 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14127 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14128 | intel_crtc->plane = !pipe; |
80824003 JB |
14129 | } |
14130 | ||
4b0e333e CW |
14131 | intel_crtc->cursor_base = ~0; |
14132 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14133 | intel_crtc->cursor_size = ~0; |
8d7849db | 14134 | |
852eb00d VS |
14135 | intel_crtc->wm.cxsr_allowed = true; |
14136 | ||
22fd0fab JB |
14137 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14138 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14139 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14140 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14141 | ||
79e53945 | 14142 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14143 | |
14144 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14145 | return; |
14146 | ||
14147 | fail: | |
14148 | if (primary) | |
14149 | drm_plane_cleanup(primary); | |
14150 | if (cursor) | |
14151 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14152 | kfree(crtc_state); |
3d7d6510 | 14153 | kfree(intel_crtc); |
79e53945 JB |
14154 | } |
14155 | ||
752aa88a JB |
14156 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14157 | { | |
14158 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14159 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14160 | |
51fd371b | 14161 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14162 | |
d3babd3f | 14163 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14164 | return INVALID_PIPE; |
14165 | ||
14166 | return to_intel_crtc(encoder->crtc)->pipe; | |
14167 | } | |
14168 | ||
08d7b3d1 | 14169 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14170 | struct drm_file *file) |
08d7b3d1 | 14171 | { |
08d7b3d1 | 14172 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14173 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14174 | struct intel_crtc *crtc; |
08d7b3d1 | 14175 | |
7707e653 | 14176 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14177 | |
7707e653 | 14178 | if (!drmmode_crtc) { |
08d7b3d1 | 14179 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14180 | return -ENOENT; |
08d7b3d1 CW |
14181 | } |
14182 | ||
7707e653 | 14183 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14184 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14185 | |
c05422d5 | 14186 | return 0; |
08d7b3d1 CW |
14187 | } |
14188 | ||
66a9278e | 14189 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14190 | { |
66a9278e DV |
14191 | struct drm_device *dev = encoder->base.dev; |
14192 | struct intel_encoder *source_encoder; | |
79e53945 | 14193 | int index_mask = 0; |
79e53945 JB |
14194 | int entry = 0; |
14195 | ||
b2784e15 | 14196 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14197 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14198 | index_mask |= (1 << entry); |
14199 | ||
79e53945 JB |
14200 | entry++; |
14201 | } | |
4ef69c7a | 14202 | |
79e53945 JB |
14203 | return index_mask; |
14204 | } | |
14205 | ||
4d302442 CW |
14206 | static bool has_edp_a(struct drm_device *dev) |
14207 | { | |
14208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14209 | ||
14210 | if (!IS_MOBILE(dev)) | |
14211 | return false; | |
14212 | ||
14213 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14214 | return false; | |
14215 | ||
e3589908 | 14216 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14217 | return false; |
14218 | ||
14219 | return true; | |
14220 | } | |
14221 | ||
84b4e042 JB |
14222 | static bool intel_crt_present(struct drm_device *dev) |
14223 | { | |
14224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14225 | ||
884497ed DL |
14226 | if (INTEL_INFO(dev)->gen >= 9) |
14227 | return false; | |
14228 | ||
cf404ce4 | 14229 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14230 | return false; |
14231 | ||
14232 | if (IS_CHERRYVIEW(dev)) | |
14233 | return false; | |
14234 | ||
14235 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
14236 | return false; | |
14237 | ||
14238 | return true; | |
14239 | } | |
14240 | ||
79e53945 JB |
14241 | static void intel_setup_outputs(struct drm_device *dev) |
14242 | { | |
725e30ad | 14243 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14244 | struct intel_encoder *encoder; |
cb0953d7 | 14245 | bool dpd_is_edp = false; |
79e53945 | 14246 | |
c9093354 | 14247 | intel_lvds_init(dev); |
79e53945 | 14248 | |
84b4e042 | 14249 | if (intel_crt_present(dev)) |
79935fca | 14250 | intel_crt_init(dev); |
cb0953d7 | 14251 | |
c776eb2e VK |
14252 | if (IS_BROXTON(dev)) { |
14253 | /* | |
14254 | * FIXME: Broxton doesn't support port detection via the | |
14255 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14256 | * detect the ports. | |
14257 | */ | |
14258 | intel_ddi_init(dev, PORT_A); | |
14259 | intel_ddi_init(dev, PORT_B); | |
14260 | intel_ddi_init(dev, PORT_C); | |
14261 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14262 | int found; |
14263 | ||
de31facd JB |
14264 | /* |
14265 | * Haswell uses DDI functions to detect digital outputs. | |
14266 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14267 | * it's there. | |
14268 | */ | |
0e72a5b5 | 14269 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
14270 | /* WaIgnoreDDIAStrap: skl */ |
14271 | if (found || | |
14272 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
14273 | intel_ddi_init(dev, PORT_A); |
14274 | ||
14275 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14276 | * register */ | |
14277 | found = I915_READ(SFUSE_STRAP); | |
14278 | ||
14279 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14280 | intel_ddi_init(dev, PORT_B); | |
14281 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14282 | intel_ddi_init(dev, PORT_C); | |
14283 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14284 | intel_ddi_init(dev, PORT_D); | |
14285 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 14286 | int found; |
5d8a7752 | 14287 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14288 | |
14289 | if (has_edp_a(dev)) | |
14290 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14291 | |
dc0fa718 | 14292 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14293 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 14294 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 14295 | if (!found) |
e2debe91 | 14296 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14297 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14298 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14299 | } |
14300 | ||
dc0fa718 | 14301 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14302 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14303 | |
dc0fa718 | 14304 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14305 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14306 | |
5eb08b69 | 14307 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14308 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14309 | |
270b3042 | 14310 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14311 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14312 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14313 | /* |
14314 | * The DP_DETECTED bit is the latched state of the DDC | |
14315 | * SDA pin at boot. However since eDP doesn't require DDC | |
14316 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14317 | * eDP ports may have been muxed to an alternate function. | |
14318 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14319 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14320 | * detect eDP ports. | |
14321 | */ | |
d2182a66 VS |
14322 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
14323 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
14324 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
14325 | PORT_B); | |
e17ac6db VS |
14326 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
14327 | intel_dp_is_edp(dev, PORT_B)) | |
14328 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 14329 | |
d2182a66 VS |
14330 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
14331 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
14332 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
14333 | PORT_C); | |
e17ac6db VS |
14334 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
14335 | intel_dp_is_edp(dev, PORT_C)) | |
14336 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 14337 | |
9418c1f1 | 14338 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14339 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
14340 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
14341 | PORT_D); | |
e17ac6db VS |
14342 | /* eDP not supported on port D, so don't check VBT */ |
14343 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
14344 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
14345 | } |
14346 | ||
3cfca973 | 14347 | intel_dsi_init(dev); |
09da55dc | 14348 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14349 | bool found = false; |
7d57382e | 14350 | |
e2debe91 | 14351 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14352 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14353 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
3fec3d2f | 14354 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14355 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14356 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14357 | } |
27185ae1 | 14358 | |
3fec3d2f | 14359 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14360 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14361 | } |
13520b05 KH |
14362 | |
14363 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14364 | |
e2debe91 | 14365 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14366 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14367 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14368 | } |
27185ae1 | 14369 | |
e2debe91 | 14370 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14371 | |
3fec3d2f | 14372 | if (IS_G4X(dev)) { |
b01f2c3a | 14373 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14374 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14375 | } |
3fec3d2f | 14376 | if (IS_G4X(dev)) |
ab9d7c30 | 14377 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14378 | } |
27185ae1 | 14379 | |
3fec3d2f | 14380 | if (IS_G4X(dev) && |
e7281eab | 14381 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14382 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14383 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14384 | intel_dvo_init(dev); |
14385 | ||
103a196f | 14386 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14387 | intel_tv_init(dev); |
14388 | ||
0bc12bcb | 14389 | intel_psr_init(dev); |
7c8f8a70 | 14390 | |
b2784e15 | 14391 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14392 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14393 | encoder->base.possible_clones = | |
66a9278e | 14394 | intel_encoder_clones(encoder); |
79e53945 | 14395 | } |
47356eb6 | 14396 | |
dde86e2d | 14397 | intel_init_pch_refclk(dev); |
270b3042 DV |
14398 | |
14399 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14400 | } |
14401 | ||
14402 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14403 | { | |
60a5ca01 | 14404 | struct drm_device *dev = fb->dev; |
79e53945 | 14405 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14406 | |
ef2d633e | 14407 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14408 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14409 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14410 | drm_gem_object_unreference(&intel_fb->obj->base); |
14411 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14412 | kfree(intel_fb); |
14413 | } | |
14414 | ||
14415 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14416 | struct drm_file *file, |
79e53945 JB |
14417 | unsigned int *handle) |
14418 | { | |
14419 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14420 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14421 | |
05394f39 | 14422 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14423 | } |
14424 | ||
86c98588 RV |
14425 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14426 | struct drm_file *file, | |
14427 | unsigned flags, unsigned color, | |
14428 | struct drm_clip_rect *clips, | |
14429 | unsigned num_clips) | |
14430 | { | |
14431 | struct drm_device *dev = fb->dev; | |
14432 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14433 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14434 | ||
14435 | mutex_lock(&dev->struct_mutex); | |
14436 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); | |
14437 | mutex_unlock(&dev->struct_mutex); | |
14438 | ||
14439 | return 0; | |
14440 | } | |
14441 | ||
79e53945 JB |
14442 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14443 | .destroy = intel_user_framebuffer_destroy, | |
14444 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14445 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14446 | }; |
14447 | ||
b321803d DL |
14448 | static |
14449 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14450 | uint32_t pixel_format) | |
14451 | { | |
14452 | u32 gen = INTEL_INFO(dev)->gen; | |
14453 | ||
14454 | if (gen >= 9) { | |
14455 | /* "The stride in bytes must not exceed the of the size of 8K | |
14456 | * pixels and 32K bytes." | |
14457 | */ | |
14458 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14459 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14460 | return 32*1024; | |
14461 | } else if (gen >= 4) { | |
14462 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14463 | return 16*1024; | |
14464 | else | |
14465 | return 32*1024; | |
14466 | } else if (gen >= 3) { | |
14467 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14468 | return 8*1024; | |
14469 | else | |
14470 | return 16*1024; | |
14471 | } else { | |
14472 | /* XXX DSPC is limited to 4k tiled */ | |
14473 | return 8*1024; | |
14474 | } | |
14475 | } | |
14476 | ||
b5ea642a DV |
14477 | static int intel_framebuffer_init(struct drm_device *dev, |
14478 | struct intel_framebuffer *intel_fb, | |
14479 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14480 | struct drm_i915_gem_object *obj) | |
79e53945 | 14481 | { |
6761dd31 | 14482 | unsigned int aligned_height; |
79e53945 | 14483 | int ret; |
b321803d | 14484 | u32 pitch_limit, stride_alignment; |
79e53945 | 14485 | |
dd4916c5 DV |
14486 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14487 | ||
2a80eada DV |
14488 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14489 | /* Enforce that fb modifier and tiling mode match, but only for | |
14490 | * X-tiled. This is needed for FBC. */ | |
14491 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14492 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14493 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14494 | return -EINVAL; | |
14495 | } | |
14496 | } else { | |
14497 | if (obj->tiling_mode == I915_TILING_X) | |
14498 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14499 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14500 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14501 | return -EINVAL; | |
14502 | } | |
14503 | } | |
14504 | ||
9a8f0a12 TU |
14505 | /* Passed in modifier sanity checking. */ |
14506 | switch (mode_cmd->modifier[0]) { | |
14507 | case I915_FORMAT_MOD_Y_TILED: | |
14508 | case I915_FORMAT_MOD_Yf_TILED: | |
14509 | if (INTEL_INFO(dev)->gen < 9) { | |
14510 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14511 | mode_cmd->modifier[0]); | |
14512 | return -EINVAL; | |
14513 | } | |
14514 | case DRM_FORMAT_MOD_NONE: | |
14515 | case I915_FORMAT_MOD_X_TILED: | |
14516 | break; | |
14517 | default: | |
c0f40428 JB |
14518 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14519 | mode_cmd->modifier[0]); | |
57cd6508 | 14520 | return -EINVAL; |
c16ed4be | 14521 | } |
57cd6508 | 14522 | |
b321803d DL |
14523 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14524 | mode_cmd->pixel_format); | |
14525 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14526 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14527 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14528 | return -EINVAL; |
c16ed4be | 14529 | } |
57cd6508 | 14530 | |
b321803d DL |
14531 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14532 | mode_cmd->pixel_format); | |
a35cdaa0 | 14533 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14534 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14535 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14536 | "tiled" : "linear", |
a35cdaa0 | 14537 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14538 | return -EINVAL; |
c16ed4be | 14539 | } |
5d7bd705 | 14540 | |
2a80eada | 14541 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14542 | mode_cmd->pitches[0] != obj->stride) { |
14543 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14544 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14545 | return -EINVAL; |
c16ed4be | 14546 | } |
5d7bd705 | 14547 | |
57779d06 | 14548 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14549 | switch (mode_cmd->pixel_format) { |
57779d06 | 14550 | case DRM_FORMAT_C8: |
04b3924d VS |
14551 | case DRM_FORMAT_RGB565: |
14552 | case DRM_FORMAT_XRGB8888: | |
14553 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14554 | break; |
14555 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14556 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14557 | DRM_DEBUG("unsupported pixel format: %s\n", |
14558 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14559 | return -EINVAL; |
c16ed4be | 14560 | } |
57779d06 | 14561 | break; |
57779d06 | 14562 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14563 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14564 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14565 | drm_get_format_name(mode_cmd->pixel_format)); | |
14566 | return -EINVAL; | |
14567 | } | |
14568 | break; | |
14569 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14570 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14571 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14572 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14573 | DRM_DEBUG("unsupported pixel format: %s\n", |
14574 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14575 | return -EINVAL; |
c16ed4be | 14576 | } |
b5626747 | 14577 | break; |
7531208b DL |
14578 | case DRM_FORMAT_ABGR2101010: |
14579 | if (!IS_VALLEYVIEW(dev)) { | |
14580 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14581 | drm_get_format_name(mode_cmd->pixel_format)); | |
14582 | return -EINVAL; | |
14583 | } | |
14584 | break; | |
04b3924d VS |
14585 | case DRM_FORMAT_YUYV: |
14586 | case DRM_FORMAT_UYVY: | |
14587 | case DRM_FORMAT_YVYU: | |
14588 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14589 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14590 | DRM_DEBUG("unsupported pixel format: %s\n", |
14591 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14592 | return -EINVAL; |
c16ed4be | 14593 | } |
57cd6508 CW |
14594 | break; |
14595 | default: | |
4ee62c76 VS |
14596 | DRM_DEBUG("unsupported pixel format: %s\n", |
14597 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14598 | return -EINVAL; |
14599 | } | |
14600 | ||
90f9a336 VS |
14601 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14602 | if (mode_cmd->offsets[0] != 0) | |
14603 | return -EINVAL; | |
14604 | ||
ec2c981e | 14605 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14606 | mode_cmd->pixel_format, |
14607 | mode_cmd->modifier[0]); | |
53155c0a DV |
14608 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14609 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14610 | return -EINVAL; | |
14611 | ||
c7d73f6a DV |
14612 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14613 | intel_fb->obj = obj; | |
80075d49 | 14614 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14615 | |
79e53945 JB |
14616 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14617 | if (ret) { | |
14618 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14619 | return ret; | |
14620 | } | |
14621 | ||
79e53945 JB |
14622 | return 0; |
14623 | } | |
14624 | ||
79e53945 JB |
14625 | static struct drm_framebuffer * |
14626 | intel_user_framebuffer_create(struct drm_device *dev, | |
14627 | struct drm_file *filp, | |
308e5bcb | 14628 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14629 | { |
05394f39 | 14630 | struct drm_i915_gem_object *obj; |
79e53945 | 14631 | |
308e5bcb JB |
14632 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14633 | mode_cmd->handles[0])); | |
c8725226 | 14634 | if (&obj->base == NULL) |
cce13ff7 | 14635 | return ERR_PTR(-ENOENT); |
79e53945 | 14636 | |
d2dff872 | 14637 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14638 | } |
14639 | ||
4520f53a | 14640 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14641 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14642 | { |
14643 | } | |
14644 | #endif | |
14645 | ||
79e53945 | 14646 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14647 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14648 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14649 | .atomic_check = intel_atomic_check, |
14650 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14651 | .atomic_state_alloc = intel_atomic_state_alloc, |
14652 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14653 | }; |
14654 | ||
e70236a8 JB |
14655 | /* Set up chip specific display functions */ |
14656 | static void intel_init_display(struct drm_device *dev) | |
14657 | { | |
14658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14659 | ||
ee9300bb DV |
14660 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14661 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14662 | else if (IS_CHERRYVIEW(dev)) |
14663 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14664 | else if (IS_VALLEYVIEW(dev)) |
14665 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14666 | else if (IS_PINEVIEW(dev)) | |
14667 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14668 | else | |
14669 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14670 | ||
bc8d7dff DL |
14671 | if (INTEL_INFO(dev)->gen >= 9) { |
14672 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14673 | dev_priv->display.get_initial_plane_config = |
14674 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14675 | dev_priv->display.crtc_compute_clock = |
14676 | haswell_crtc_compute_clock; | |
14677 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14678 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14679 | dev_priv->display.update_primary_plane = |
14680 | skylake_update_primary_plane; | |
14681 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14682 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14683 | dev_priv->display.get_initial_plane_config = |
14684 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14685 | dev_priv->display.crtc_compute_clock = |
14686 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14687 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14688 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14689 | dev_priv->display.update_primary_plane = |
14690 | ironlake_update_primary_plane; | |
09b4ddf9 | 14691 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14692 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14693 | dev_priv->display.get_initial_plane_config = |
14694 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14695 | dev_priv->display.crtc_compute_clock = |
14696 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14697 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14698 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14699 | dev_priv->display.update_primary_plane = |
14700 | ironlake_update_primary_plane; | |
89b667f8 JB |
14701 | } else if (IS_VALLEYVIEW(dev)) { |
14702 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14703 | dev_priv->display.get_initial_plane_config = |
14704 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14705 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14706 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14707 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14708 | dev_priv->display.update_primary_plane = |
14709 | i9xx_update_primary_plane; | |
f564048e | 14710 | } else { |
0e8ffe1b | 14711 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14712 | dev_priv->display.get_initial_plane_config = |
14713 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14714 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14715 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14716 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14717 | dev_priv->display.update_primary_plane = |
14718 | i9xx_update_primary_plane; | |
f564048e | 14719 | } |
e70236a8 | 14720 | |
e70236a8 | 14721 | /* Returns the core display clock speed */ |
1652d19e VS |
14722 | if (IS_SKYLAKE(dev)) |
14723 | dev_priv->display.get_display_clock_speed = | |
14724 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14725 | else if (IS_BROXTON(dev)) |
14726 | dev_priv->display.get_display_clock_speed = | |
14727 | broxton_get_display_clock_speed; | |
1652d19e VS |
14728 | else if (IS_BROADWELL(dev)) |
14729 | dev_priv->display.get_display_clock_speed = | |
14730 | broadwell_get_display_clock_speed; | |
14731 | else if (IS_HASWELL(dev)) | |
14732 | dev_priv->display.get_display_clock_speed = | |
14733 | haswell_get_display_clock_speed; | |
14734 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14735 | dev_priv->display.get_display_clock_speed = |
14736 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14737 | else if (IS_GEN5(dev)) |
14738 | dev_priv->display.get_display_clock_speed = | |
14739 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14740 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14741 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14742 | dev_priv->display.get_display_clock_speed = |
14743 | i945_get_display_clock_speed; | |
34edce2f VS |
14744 | else if (IS_GM45(dev)) |
14745 | dev_priv->display.get_display_clock_speed = | |
14746 | gm45_get_display_clock_speed; | |
14747 | else if (IS_CRESTLINE(dev)) | |
14748 | dev_priv->display.get_display_clock_speed = | |
14749 | i965gm_get_display_clock_speed; | |
14750 | else if (IS_PINEVIEW(dev)) | |
14751 | dev_priv->display.get_display_clock_speed = | |
14752 | pnv_get_display_clock_speed; | |
14753 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14754 | dev_priv->display.get_display_clock_speed = | |
14755 | g33_get_display_clock_speed; | |
e70236a8 JB |
14756 | else if (IS_I915G(dev)) |
14757 | dev_priv->display.get_display_clock_speed = | |
14758 | i915_get_display_clock_speed; | |
257a7ffc | 14759 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14760 | dev_priv->display.get_display_clock_speed = |
14761 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14762 | else if (IS_PINEVIEW(dev)) |
14763 | dev_priv->display.get_display_clock_speed = | |
14764 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14765 | else if (IS_I915GM(dev)) |
14766 | dev_priv->display.get_display_clock_speed = | |
14767 | i915gm_get_display_clock_speed; | |
14768 | else if (IS_I865G(dev)) | |
14769 | dev_priv->display.get_display_clock_speed = | |
14770 | i865_get_display_clock_speed; | |
f0f8a9ce | 14771 | else if (IS_I85X(dev)) |
e70236a8 | 14772 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14773 | i85x_get_display_clock_speed; |
623e01e5 VS |
14774 | else { /* 830 */ |
14775 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14776 | dev_priv->display.get_display_clock_speed = |
14777 | i830_get_display_clock_speed; | |
623e01e5 | 14778 | } |
e70236a8 | 14779 | |
7c10a2b5 | 14780 | if (IS_GEN5(dev)) { |
3bb11b53 | 14781 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14782 | } else if (IS_GEN6(dev)) { |
14783 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14784 | } else if (IS_IVYBRIDGE(dev)) { |
14785 | /* FIXME: detect B0+ stepping and use auto training */ | |
14786 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14787 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14788 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14789 | if (IS_BROADWELL(dev)) { |
14790 | dev_priv->display.modeset_commit_cdclk = | |
14791 | broadwell_modeset_commit_cdclk; | |
14792 | dev_priv->display.modeset_calc_cdclk = | |
14793 | broadwell_modeset_calc_cdclk; | |
14794 | } | |
30a970c6 | 14795 | } else if (IS_VALLEYVIEW(dev)) { |
27c329ed ML |
14796 | dev_priv->display.modeset_commit_cdclk = |
14797 | valleyview_modeset_commit_cdclk; | |
14798 | dev_priv->display.modeset_calc_cdclk = | |
14799 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14800 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14801 | dev_priv->display.modeset_commit_cdclk = |
14802 | broxton_modeset_commit_cdclk; | |
14803 | dev_priv->display.modeset_calc_cdclk = | |
14804 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14805 | } |
8c9f3aaf | 14806 | |
8c9f3aaf JB |
14807 | switch (INTEL_INFO(dev)->gen) { |
14808 | case 2: | |
14809 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14810 | break; | |
14811 | ||
14812 | case 3: | |
14813 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14814 | break; | |
14815 | ||
14816 | case 4: | |
14817 | case 5: | |
14818 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14819 | break; | |
14820 | ||
14821 | case 6: | |
14822 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14823 | break; | |
7c9017e5 | 14824 | case 7: |
4e0bbc31 | 14825 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14826 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14827 | break; | |
830c81db | 14828 | case 9: |
ba343e02 TU |
14829 | /* Drop through - unsupported since execlist only. */ |
14830 | default: | |
14831 | /* Default just returns -ENODEV to indicate unsupported */ | |
14832 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14833 | } |
7bd688cd JN |
14834 | |
14835 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14836 | |
14837 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14838 | } |
14839 | ||
b690e96c JB |
14840 | /* |
14841 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14842 | * resume, or other times. This quirk makes sure that's the case for | |
14843 | * affected systems. | |
14844 | */ | |
0206e353 | 14845 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14846 | { |
14847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14848 | ||
14849 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14850 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14851 | } |
14852 | ||
b6b5d049 VS |
14853 | static void quirk_pipeb_force(struct drm_device *dev) |
14854 | { | |
14855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14856 | ||
14857 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14858 | DRM_INFO("applying pipe b force quirk\n"); | |
14859 | } | |
14860 | ||
435793df KP |
14861 | /* |
14862 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14863 | */ | |
14864 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14865 | { | |
14866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14867 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14868 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14869 | } |
14870 | ||
4dca20ef | 14871 | /* |
5a15ab5b CE |
14872 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14873 | * brightness value | |
4dca20ef CE |
14874 | */ |
14875 | static void quirk_invert_brightness(struct drm_device *dev) | |
14876 | { | |
14877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14878 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14879 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14880 | } |
14881 | ||
9c72cc6f SD |
14882 | /* Some VBT's incorrectly indicate no backlight is present */ |
14883 | static void quirk_backlight_present(struct drm_device *dev) | |
14884 | { | |
14885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14886 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14887 | DRM_INFO("applying backlight present quirk\n"); | |
14888 | } | |
14889 | ||
b690e96c JB |
14890 | struct intel_quirk { |
14891 | int device; | |
14892 | int subsystem_vendor; | |
14893 | int subsystem_device; | |
14894 | void (*hook)(struct drm_device *dev); | |
14895 | }; | |
14896 | ||
5f85f176 EE |
14897 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14898 | struct intel_dmi_quirk { | |
14899 | void (*hook)(struct drm_device *dev); | |
14900 | const struct dmi_system_id (*dmi_id_list)[]; | |
14901 | }; | |
14902 | ||
14903 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14904 | { | |
14905 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14906 | return 1; | |
14907 | } | |
14908 | ||
14909 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14910 | { | |
14911 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14912 | { | |
14913 | .callback = intel_dmi_reverse_brightness, | |
14914 | .ident = "NCR Corporation", | |
14915 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14916 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14917 | }, | |
14918 | }, | |
14919 | { } /* terminating entry */ | |
14920 | }, | |
14921 | .hook = quirk_invert_brightness, | |
14922 | }, | |
14923 | }; | |
14924 | ||
c43b5634 | 14925 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14926 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14927 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14928 | ||
b690e96c JB |
14929 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14930 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14931 | ||
5f080c0f VS |
14932 | /* 830 needs to leave pipe A & dpll A up */ |
14933 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14934 | ||
b6b5d049 VS |
14935 | /* 830 needs to leave pipe B & dpll B up */ |
14936 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14937 | ||
435793df KP |
14938 | /* Lenovo U160 cannot use SSC on LVDS */ |
14939 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14940 | |
14941 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14942 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14943 | |
be505f64 AH |
14944 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14945 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14946 | ||
14947 | /* Acer/eMachines G725 */ | |
14948 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14949 | ||
14950 | /* Acer/eMachines e725 */ | |
14951 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14952 | ||
14953 | /* Acer/Packard Bell NCL20 */ | |
14954 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14955 | ||
14956 | /* Acer Aspire 4736Z */ | |
14957 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14958 | |
14959 | /* Acer Aspire 5336 */ | |
14960 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14961 | |
14962 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14963 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14964 | |
dfb3d47b SD |
14965 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14966 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14967 | ||
b2a9601c | 14968 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14969 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14970 | ||
d4967d8c SD |
14971 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14972 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14973 | |
14974 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14975 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14976 | |
14977 | /* Dell Chromebook 11 */ | |
14978 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14979 | }; |
14980 | ||
14981 | static void intel_init_quirks(struct drm_device *dev) | |
14982 | { | |
14983 | struct pci_dev *d = dev->pdev; | |
14984 | int i; | |
14985 | ||
14986 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14987 | struct intel_quirk *q = &intel_quirks[i]; | |
14988 | ||
14989 | if (d->device == q->device && | |
14990 | (d->subsystem_vendor == q->subsystem_vendor || | |
14991 | q->subsystem_vendor == PCI_ANY_ID) && | |
14992 | (d->subsystem_device == q->subsystem_device || | |
14993 | q->subsystem_device == PCI_ANY_ID)) | |
14994 | q->hook(dev); | |
14995 | } | |
5f85f176 EE |
14996 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14997 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14998 | intel_dmi_quirks[i].hook(dev); | |
14999 | } | |
b690e96c JB |
15000 | } |
15001 | ||
9cce37f4 JB |
15002 | /* Disable the VGA plane that we never use */ |
15003 | static void i915_disable_vga(struct drm_device *dev) | |
15004 | { | |
15005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15006 | u8 sr1; | |
766aa1c4 | 15007 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15008 | |
2b37c616 | 15009 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15010 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15011 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15012 | sr1 = inb(VGA_SR_DATA); |
15013 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15014 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15015 | udelay(300); | |
15016 | ||
01f5a626 | 15017 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15018 | POSTING_READ(vga_reg); |
15019 | } | |
15020 | ||
f817586c DV |
15021 | void intel_modeset_init_hw(struct drm_device *dev) |
15022 | { | |
b6283055 | 15023 | intel_update_cdclk(dev); |
a8f78b58 | 15024 | intel_prepare_ddi(dev); |
f817586c | 15025 | intel_init_clock_gating(dev); |
8090c6b9 | 15026 | intel_enable_gt_powersave(dev); |
f817586c DV |
15027 | } |
15028 | ||
79e53945 JB |
15029 | void intel_modeset_init(struct drm_device *dev) |
15030 | { | |
652c393a | 15031 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15032 | int sprite, ret; |
8cc87b75 | 15033 | enum pipe pipe; |
46f297fb | 15034 | struct intel_crtc *crtc; |
79e53945 JB |
15035 | |
15036 | drm_mode_config_init(dev); | |
15037 | ||
15038 | dev->mode_config.min_width = 0; | |
15039 | dev->mode_config.min_height = 0; | |
15040 | ||
019d96cb DA |
15041 | dev->mode_config.preferred_depth = 24; |
15042 | dev->mode_config.prefer_shadow = 1; | |
15043 | ||
25bab385 TU |
15044 | dev->mode_config.allow_fb_modifiers = true; |
15045 | ||
e6ecefaa | 15046 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15047 | |
b690e96c JB |
15048 | intel_init_quirks(dev); |
15049 | ||
1fa61106 ED |
15050 | intel_init_pm(dev); |
15051 | ||
e3c74757 BW |
15052 | if (INTEL_INFO(dev)->num_pipes == 0) |
15053 | return; | |
15054 | ||
e70236a8 | 15055 | intel_init_display(dev); |
7c10a2b5 | 15056 | intel_init_audio(dev); |
e70236a8 | 15057 | |
a6c45cf0 CW |
15058 | if (IS_GEN2(dev)) { |
15059 | dev->mode_config.max_width = 2048; | |
15060 | dev->mode_config.max_height = 2048; | |
15061 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15062 | dev->mode_config.max_width = 4096; |
15063 | dev->mode_config.max_height = 4096; | |
79e53945 | 15064 | } else { |
a6c45cf0 CW |
15065 | dev->mode_config.max_width = 8192; |
15066 | dev->mode_config.max_height = 8192; | |
79e53945 | 15067 | } |
068be561 | 15068 | |
dc41c154 VS |
15069 | if (IS_845G(dev) || IS_I865G(dev)) { |
15070 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15071 | dev->mode_config.cursor_height = 1023; | |
15072 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15073 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15074 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15075 | } else { | |
15076 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15077 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15078 | } | |
15079 | ||
5d4545ae | 15080 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15081 | |
28c97730 | 15082 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15083 | INTEL_INFO(dev)->num_pipes, |
15084 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15085 | |
055e393f | 15086 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15087 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15088 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15089 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15090 | if (ret) |
06da8da2 | 15091 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15092 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15093 | } |
79e53945 JB |
15094 | } |
15095 | ||
f42bb70d JB |
15096 | intel_init_dpio(dev); |
15097 | ||
e72f9fbf | 15098 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15099 | |
9cce37f4 JB |
15100 | /* Just disable it once at startup */ |
15101 | i915_disable_vga(dev); | |
79e53945 | 15102 | intel_setup_outputs(dev); |
11be49eb CW |
15103 | |
15104 | /* Just in case the BIOS is doing something questionable. */ | |
7733b49b | 15105 | intel_fbc_disable(dev_priv); |
fa9fa083 | 15106 | |
6e9f798d | 15107 | drm_modeset_lock_all(dev); |
043e9bda | 15108 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15109 | drm_modeset_unlock_all(dev); |
46f297fb | 15110 | |
d3fcc808 | 15111 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15112 | struct intel_initial_plane_config plane_config = {}; |
15113 | ||
46f297fb JB |
15114 | if (!crtc->active) |
15115 | continue; | |
15116 | ||
46f297fb | 15117 | /* |
46f297fb JB |
15118 | * Note that reserving the BIOS fb up front prevents us |
15119 | * from stuffing other stolen allocations like the ring | |
15120 | * on top. This prevents some ugliness at boot time, and | |
15121 | * can even allow for smooth boot transitions if the BIOS | |
15122 | * fb is large enough for the active pipe configuration. | |
15123 | */ | |
eeebeac5 ML |
15124 | dev_priv->display.get_initial_plane_config(crtc, |
15125 | &plane_config); | |
15126 | ||
15127 | /* | |
15128 | * If the fb is shared between multiple heads, we'll | |
15129 | * just get the first one. | |
15130 | */ | |
15131 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15132 | } |
2c7111db CW |
15133 | } |
15134 | ||
7fad798e DV |
15135 | static void intel_enable_pipe_a(struct drm_device *dev) |
15136 | { | |
15137 | struct intel_connector *connector; | |
15138 | struct drm_connector *crt = NULL; | |
15139 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15140 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15141 | |
15142 | /* We can't just switch on the pipe A, we need to set things up with a | |
15143 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15144 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15145 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15146 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15147 | crt = &connector->base; | |
15148 | break; | |
15149 | } | |
15150 | } | |
15151 | ||
15152 | if (!crt) | |
15153 | return; | |
15154 | ||
208bf9fd | 15155 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15156 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15157 | } |
15158 | ||
fa555837 DV |
15159 | static bool |
15160 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15161 | { | |
7eb552ae BW |
15162 | struct drm_device *dev = crtc->base.dev; |
15163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
15164 | u32 reg, val; |
15165 | ||
7eb552ae | 15166 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15167 | return true; |
15168 | ||
15169 | reg = DSPCNTR(!crtc->plane); | |
15170 | val = I915_READ(reg); | |
15171 | ||
15172 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15173 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15174 | return false; | |
15175 | ||
15176 | return true; | |
15177 | } | |
15178 | ||
24929352 DV |
15179 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15180 | { | |
15181 | struct drm_device *dev = crtc->base.dev; | |
15182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b17d48e2 | 15183 | struct intel_encoder *encoder; |
fa555837 | 15184 | u32 reg; |
b17d48e2 | 15185 | bool enable; |
24929352 | 15186 | |
24929352 | 15187 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 15188 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
15189 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15190 | ||
d3eaf884 | 15191 | /* restore vblank interrupts to correct state */ |
9625604c | 15192 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15193 | if (crtc->active) { |
3a03dfb0 | 15194 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
d297e103 | 15195 | update_scanline_offset(crtc); |
9625604c DV |
15196 | drm_crtc_vblank_on(&crtc->base); |
15197 | } | |
d3eaf884 | 15198 | |
24929352 | 15199 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15200 | * disable the crtc (and hence change the state) if it is wrong. Note |
15201 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15202 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15203 | bool plane; |
15204 | ||
24929352 DV |
15205 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15206 | crtc->base.base.id); | |
15207 | ||
15208 | /* Pipe has the wrong plane attached and the plane is active. | |
15209 | * Temporarily change the plane mapping and disable everything | |
15210 | * ... */ | |
15211 | plane = crtc->plane; | |
b70709a6 | 15212 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15213 | crtc->plane = !plane; |
b17d48e2 | 15214 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15215 | crtc->plane = plane; |
24929352 | 15216 | } |
24929352 | 15217 | |
7fad798e DV |
15218 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15219 | crtc->pipe == PIPE_A && !crtc->active) { | |
15220 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15221 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15222 | * call below we restore the pipe to the right state, but leave | |
15223 | * the required bits on. */ | |
15224 | intel_enable_pipe_a(dev); | |
15225 | } | |
15226 | ||
24929352 DV |
15227 | /* Adjust the state of the output pipe according to whether we |
15228 | * have active connectors/encoders. */ | |
b17d48e2 ML |
15229 | enable = false; |
15230 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15231 | enable |= encoder->connectors_active; | |
24929352 | 15232 | |
b17d48e2 ML |
15233 | if (!enable) |
15234 | intel_crtc_disable_noatomic(&crtc->base); | |
24929352 | 15235 | |
53d9f4e9 | 15236 | if (crtc->active != crtc->base.state->active) { |
24929352 DV |
15237 | |
15238 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15239 | * functions or because of calls to intel_crtc_disable_noatomic, |
15240 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15241 | * pipe A quirk. */ |
15242 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15243 | crtc->base.base.id, | |
83d65738 | 15244 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15245 | crtc->active ? "enabled" : "disabled"); |
15246 | ||
4be40c98 | 15247 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15248 | crtc->base.state->active = crtc->active; |
24929352 DV |
15249 | crtc->base.enabled = crtc->active; |
15250 | ||
15251 | /* Because we only establish the connector -> encoder -> | |
15252 | * crtc links if something is active, this means the | |
15253 | * crtc is now deactivated. Break the links. connector | |
15254 | * -> encoder links are only establish when things are | |
15255 | * actually up, hence no need to break them. */ | |
15256 | WARN_ON(crtc->active); | |
15257 | ||
15258 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
15259 | WARN_ON(encoder->connectors_active); | |
15260 | encoder->base.crtc = NULL; | |
15261 | } | |
15262 | } | |
c5ab3bc0 | 15263 | |
a3ed6aad | 15264 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15265 | /* |
15266 | * We start out with underrun reporting disabled to avoid races. | |
15267 | * For correct bookkeeping mark this on active crtcs. | |
15268 | * | |
c5ab3bc0 DV |
15269 | * Also on gmch platforms we dont have any hardware bits to |
15270 | * disable the underrun reporting. Which means we need to start | |
15271 | * out with underrun reporting disabled also on inactive pipes, | |
15272 | * since otherwise we'll complain about the garbage we read when | |
15273 | * e.g. coming up after runtime pm. | |
15274 | * | |
4cc31489 DV |
15275 | * No protection against concurrent access is required - at |
15276 | * worst a fifo underrun happens which also sets this to false. | |
15277 | */ | |
15278 | crtc->cpu_fifo_underrun_disabled = true; | |
15279 | crtc->pch_fifo_underrun_disabled = true; | |
15280 | } | |
24929352 DV |
15281 | } |
15282 | ||
15283 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15284 | { | |
15285 | struct intel_connector *connector; | |
15286 | struct drm_device *dev = encoder->base.dev; | |
15287 | ||
15288 | /* We need to check both for a crtc link (meaning that the | |
15289 | * encoder is active and trying to read from a pipe) and the | |
15290 | * pipe itself being active. */ | |
15291 | bool has_active_crtc = encoder->base.crtc && | |
15292 | to_intel_crtc(encoder->base.crtc)->active; | |
15293 | ||
15294 | if (encoder->connectors_active && !has_active_crtc) { | |
15295 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
15296 | encoder->base.base.id, | |
8e329a03 | 15297 | encoder->base.name); |
24929352 DV |
15298 | |
15299 | /* Connector is active, but has no active pipe. This is | |
15300 | * fallout from our resume register restoring. Disable | |
15301 | * the encoder manually again. */ | |
15302 | if (encoder->base.crtc) { | |
15303 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15304 | encoder->base.base.id, | |
8e329a03 | 15305 | encoder->base.name); |
24929352 | 15306 | encoder->disable(encoder); |
a62d1497 VS |
15307 | if (encoder->post_disable) |
15308 | encoder->post_disable(encoder); | |
24929352 | 15309 | } |
7f1950fb EE |
15310 | encoder->base.crtc = NULL; |
15311 | encoder->connectors_active = false; | |
24929352 DV |
15312 | |
15313 | /* Inconsistent output/port/pipe state happens presumably due to | |
15314 | * a bug in one of the get_hw_state functions. Or someplace else | |
15315 | * in our code, like the register restore mess on resume. Clamp | |
15316 | * things to off as a safer default. */ | |
3a3371ff | 15317 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15318 | if (connector->encoder != encoder) |
15319 | continue; | |
7f1950fb EE |
15320 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15321 | connector->base.encoder = NULL; | |
24929352 DV |
15322 | } |
15323 | } | |
15324 | /* Enabled encoders without active connectors will be fixed in | |
15325 | * the crtc fixup. */ | |
15326 | } | |
15327 | ||
04098753 | 15328 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15329 | { |
15330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 15331 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15332 | |
04098753 ID |
15333 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15334 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15335 | i915_disable_vga(dev); | |
15336 | } | |
15337 | } | |
15338 | ||
15339 | void i915_redisable_vga(struct drm_device *dev) | |
15340 | { | |
15341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15342 | ||
8dc8a27c PZ |
15343 | /* This function can be called both from intel_modeset_setup_hw_state or |
15344 | * at a very early point in our resume sequence, where the power well | |
15345 | * structures are not yet restored. Since this function is at a very | |
15346 | * paranoid "someone might have enabled VGA while we were not looking" | |
15347 | * level, just check if the power well is enabled instead of trying to | |
15348 | * follow the "don't touch the power well if we don't need it" policy | |
15349 | * the rest of the driver uses. */ | |
f458ebbc | 15350 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15351 | return; |
15352 | ||
04098753 | 15353 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15354 | } |
15355 | ||
98ec7739 VS |
15356 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
15357 | { | |
15358 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
15359 | ||
d032ffa0 ML |
15360 | return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE); |
15361 | } | |
15362 | ||
15363 | static void readout_plane_state(struct intel_crtc *crtc, | |
15364 | struct intel_crtc_state *crtc_state) | |
15365 | { | |
15366 | struct intel_plane *p; | |
4cf0ebbd | 15367 | struct intel_plane_state *plane_state; |
d032ffa0 ML |
15368 | bool active = crtc_state->base.active; |
15369 | ||
d032ffa0 | 15370 | for_each_intel_plane(crtc->base.dev, p) { |
d032ffa0 ML |
15371 | if (crtc->pipe != p->pipe) |
15372 | continue; | |
15373 | ||
4cf0ebbd | 15374 | plane_state = to_intel_plane_state(p->base.state); |
e435d6e5 | 15375 | |
4cf0ebbd ML |
15376 | if (p->base.type == DRM_PLANE_TYPE_PRIMARY) |
15377 | plane_state->visible = primary_get_hw_state(crtc); | |
15378 | else { | |
15379 | if (active) | |
15380 | p->disable_plane(&p->base, &crtc->base); | |
d032ffa0 | 15381 | |
4cf0ebbd | 15382 | plane_state->visible = false; |
d032ffa0 ML |
15383 | } |
15384 | } | |
98ec7739 VS |
15385 | } |
15386 | ||
30e984df | 15387 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15388 | { |
15389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15390 | enum pipe pipe; | |
24929352 DV |
15391 | struct intel_crtc *crtc; |
15392 | struct intel_encoder *encoder; | |
15393 | struct intel_connector *connector; | |
5358901f | 15394 | int i; |
24929352 | 15395 | |
d3fcc808 | 15396 | for_each_intel_crtc(dev, crtc) { |
b06f8b0d | 15397 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
6e3c9717 | 15398 | memset(crtc->config, 0, sizeof(*crtc->config)); |
f7217905 | 15399 | crtc->config->base.crtc = &crtc->base; |
3b117c8f | 15400 | |
6e3c9717 | 15401 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 15402 | |
0e8ffe1b | 15403 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15404 | crtc->config); |
24929352 | 15405 | |
49d6fa21 | 15406 | crtc->base.state->active = crtc->active; |
24929352 | 15407 | crtc->base.enabled = crtc->active; |
b70709a6 | 15408 | |
5c1e3426 ML |
15409 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
15410 | if (crtc->base.state->active) { | |
15411 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15412 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15413 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15414 | ||
15415 | /* | |
15416 | * The initial mode needs to be set in order to keep | |
15417 | * the atomic core happy. It wants a valid mode if the | |
15418 | * crtc's enabled, so we do the above call. | |
15419 | * | |
15420 | * At this point some state updated by the connectors | |
15421 | * in their ->detect() callback has not run yet, so | |
15422 | * no recalculation can be done yet. | |
15423 | * | |
15424 | * Even if we could do a recalculation and modeset | |
15425 | * right now it would cause a double modeset if | |
15426 | * fbdev or userspace chooses a different initial mode. | |
15427 | * | |
15428 | * So to prevent the double modeset, fail the memcmp | |
15429 | * test in drm_atomic_set_mode_for_crtc to get a new | |
15430 | * mode blob, and compare if the mode blob changed | |
15431 | * when the PIPE_CONFIG_QUIRK_INHERITED_MODE quirk is | |
15432 | * set. | |
15433 | * | |
15434 | * If that happens, someone indicated they wanted a | |
15435 | * mode change, which means it's safe to do a full | |
15436 | * recalculation. | |
15437 | */ | |
15438 | crtc->base.state->mode.private_flags = ~0; | |
15439 | } | |
15440 | ||
15441 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
d032ffa0 | 15442 | readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state)); |
24929352 DV |
15443 | |
15444 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15445 | crtc->base.base.id, | |
15446 | crtc->active ? "enabled" : "disabled"); | |
15447 | } | |
15448 | ||
5358901f DV |
15449 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15450 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15451 | ||
3e369b76 ACO |
15452 | pll->on = pll->get_hw_state(dev_priv, pll, |
15453 | &pll->config.hw_state); | |
5358901f | 15454 | pll->active = 0; |
3e369b76 | 15455 | pll->config.crtc_mask = 0; |
d3fcc808 | 15456 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15457 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15458 | pll->active++; |
3e369b76 | 15459 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15460 | } |
5358901f | 15461 | } |
5358901f | 15462 | |
1e6f2ddc | 15463 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15464 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15465 | |
3e369b76 | 15466 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15467 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15468 | } |
15469 | ||
b2784e15 | 15470 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15471 | pipe = 0; |
15472 | ||
15473 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15474 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15475 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15476 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15477 | } else { |
15478 | encoder->base.crtc = NULL; | |
15479 | } | |
15480 | ||
15481 | encoder->connectors_active = false; | |
6f2bcceb | 15482 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15483 | encoder->base.base.id, |
8e329a03 | 15484 | encoder->base.name, |
24929352 | 15485 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15486 | pipe_name(pipe)); |
24929352 DV |
15487 | } |
15488 | ||
3a3371ff | 15489 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15490 | if (connector->get_hw_state(connector)) { |
15491 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
15492 | connector->encoder->connectors_active = true; | |
15493 | connector->base.encoder = &connector->encoder->base; | |
15494 | } else { | |
15495 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15496 | connector->base.encoder = NULL; | |
15497 | } | |
15498 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15499 | connector->base.base.id, | |
c23cc417 | 15500 | connector->base.name, |
24929352 DV |
15501 | connector->base.encoder ? "enabled" : "disabled"); |
15502 | } | |
30e984df DV |
15503 | } |
15504 | ||
043e9bda ML |
15505 | /* Scan out the current hw modeset state, |
15506 | * and sanitizes it to the current state | |
15507 | */ | |
15508 | static void | |
15509 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15510 | { |
15511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15512 | enum pipe pipe; | |
30e984df DV |
15513 | struct intel_crtc *crtc; |
15514 | struct intel_encoder *encoder; | |
35c95375 | 15515 | int i; |
30e984df DV |
15516 | |
15517 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15518 | |
15519 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15520 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15521 | intel_sanitize_encoder(encoder); |
15522 | } | |
15523 | ||
055e393f | 15524 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15525 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15526 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15527 | intel_dump_pipe_config(crtc, crtc->config, |
15528 | "[setup_hw_state]"); | |
24929352 | 15529 | } |
9a935856 | 15530 | |
d29b2f9d ACO |
15531 | intel_modeset_update_connector_atomic_state(dev); |
15532 | ||
35c95375 DV |
15533 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15534 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15535 | ||
15536 | if (!pll->on || pll->active) | |
15537 | continue; | |
15538 | ||
15539 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15540 | ||
15541 | pll->disable(dev_priv, pll); | |
15542 | pll->on = false; | |
15543 | } | |
15544 | ||
26e1fe4f | 15545 | if (IS_VALLEYVIEW(dev)) |
6eb1a681 VS |
15546 | vlv_wm_get_hw_state(dev); |
15547 | else if (IS_GEN9(dev)) | |
3078999f PB |
15548 | skl_wm_get_hw_state(dev); |
15549 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15550 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15551 | |
15552 | for_each_intel_crtc(dev, crtc) { | |
15553 | unsigned long put_domains; | |
15554 | ||
15555 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15556 | if (WARN_ON(put_domains)) | |
15557 | modeset_put_power_domains(dev_priv, put_domains); | |
15558 | } | |
15559 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15560 | } |
7d0bc1ea | 15561 | |
043e9bda ML |
15562 | void intel_display_resume(struct drm_device *dev) |
15563 | { | |
15564 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15565 | struct intel_connector *conn; | |
15566 | struct intel_plane *plane; | |
15567 | struct drm_crtc *crtc; | |
15568 | int ret; | |
f30da187 | 15569 | |
043e9bda ML |
15570 | if (!state) |
15571 | return; | |
15572 | ||
15573 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15574 | ||
15575 | /* preserve complete old state, including dpll */ | |
15576 | intel_atomic_get_shared_dpll_state(state); | |
15577 | ||
15578 | for_each_crtc(dev, crtc) { | |
15579 | struct drm_crtc_state *crtc_state = | |
15580 | drm_atomic_get_crtc_state(state, crtc); | |
15581 | ||
15582 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15583 | if (ret) | |
15584 | goto err; | |
15585 | ||
15586 | /* force a restore */ | |
15587 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15588 | } |
8af6cf88 | 15589 | |
043e9bda ML |
15590 | for_each_intel_plane(dev, plane) { |
15591 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15592 | if (ret) | |
15593 | goto err; | |
15594 | } | |
15595 | ||
15596 | for_each_intel_connector(dev, conn) { | |
15597 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15598 | if (ret) | |
15599 | goto err; | |
15600 | } | |
15601 | ||
15602 | intel_modeset_setup_hw_state(dev); | |
15603 | ||
15604 | i915_redisable_vga(dev); | |
15605 | ret = intel_set_mode(state); | |
15606 | if (!ret) | |
15607 | return; | |
15608 | ||
15609 | err: | |
15610 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15611 | drm_atomic_state_free(state); | |
2c7111db CW |
15612 | } |
15613 | ||
15614 | void intel_modeset_gem_init(struct drm_device *dev) | |
15615 | { | |
92122789 | 15616 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 15617 | struct drm_crtc *c; |
2ff8fde1 | 15618 | struct drm_i915_gem_object *obj; |
e0d6149b | 15619 | int ret; |
484b41dd | 15620 | |
ae48434c ID |
15621 | mutex_lock(&dev->struct_mutex); |
15622 | intel_init_gt_powersave(dev); | |
15623 | mutex_unlock(&dev->struct_mutex); | |
15624 | ||
92122789 JB |
15625 | /* |
15626 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15627 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15628 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15629 | * indicates as much. | |
15630 | */ | |
15631 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
15632 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15633 | DREF_SSC1_ENABLE); | |
15634 | ||
1833b134 | 15635 | intel_modeset_init_hw(dev); |
02e792fb DV |
15636 | |
15637 | intel_setup_overlay(dev); | |
484b41dd JB |
15638 | |
15639 | /* | |
15640 | * Make sure any fbs we allocated at startup are properly | |
15641 | * pinned & fenced. When we do the allocation it's too early | |
15642 | * for this. | |
15643 | */ | |
70e1e0ec | 15644 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15645 | obj = intel_fb_obj(c->primary->fb); |
15646 | if (obj == NULL) | |
484b41dd JB |
15647 | continue; |
15648 | ||
e0d6149b TU |
15649 | mutex_lock(&dev->struct_mutex); |
15650 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15651 | c->primary->fb, | |
15652 | c->primary->state, | |
91af127f | 15653 | NULL, NULL); |
e0d6149b TU |
15654 | mutex_unlock(&dev->struct_mutex); |
15655 | if (ret) { | |
484b41dd JB |
15656 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15657 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15658 | drm_framebuffer_unreference(c->primary->fb); |
15659 | c->primary->fb = NULL; | |
36750f28 | 15660 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15661 | update_state_fb(c->primary); |
36750f28 | 15662 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15663 | } |
15664 | } | |
0962c3c9 VS |
15665 | |
15666 | intel_backlight_register(dev); | |
79e53945 JB |
15667 | } |
15668 | ||
4932e2c3 ID |
15669 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15670 | { | |
15671 | struct drm_connector *connector = &intel_connector->base; | |
15672 | ||
15673 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15674 | drm_connector_unregister(connector); |
4932e2c3 ID |
15675 | } |
15676 | ||
79e53945 JB |
15677 | void intel_modeset_cleanup(struct drm_device *dev) |
15678 | { | |
652c393a | 15679 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15680 | struct drm_connector *connector; |
652c393a | 15681 | |
2eb5252e ID |
15682 | intel_disable_gt_powersave(dev); |
15683 | ||
0962c3c9 VS |
15684 | intel_backlight_unregister(dev); |
15685 | ||
fd0c0642 DV |
15686 | /* |
15687 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15688 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15689 | * experience fancy races otherwise. |
15690 | */ | |
2aeb7d3a | 15691 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15692 | |
fd0c0642 DV |
15693 | /* |
15694 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15695 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15696 | */ | |
f87ea761 | 15697 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15698 | |
723bfd70 JB |
15699 | intel_unregister_dsm_handler(); |
15700 | ||
7733b49b | 15701 | intel_fbc_disable(dev_priv); |
69341a5e | 15702 | |
1630fe75 CW |
15703 | /* flush any delayed tasks or pending work */ |
15704 | flush_scheduled_work(); | |
15705 | ||
db31af1d JN |
15706 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15707 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15708 | struct intel_connector *intel_connector; |
15709 | ||
15710 | intel_connector = to_intel_connector(connector); | |
15711 | intel_connector->unregister(intel_connector); | |
db31af1d | 15712 | } |
d9255d57 | 15713 | |
79e53945 | 15714 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15715 | |
15716 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15717 | |
15718 | mutex_lock(&dev->struct_mutex); | |
15719 | intel_cleanup_gt_powersave(dev); | |
15720 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15721 | } |
15722 | ||
f1c79df3 ZW |
15723 | /* |
15724 | * Return which encoder is currently attached for connector. | |
15725 | */ | |
df0e9248 | 15726 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15727 | { |
df0e9248 CW |
15728 | return &intel_attached_encoder(connector)->base; |
15729 | } | |
f1c79df3 | 15730 | |
df0e9248 CW |
15731 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15732 | struct intel_encoder *encoder) | |
15733 | { | |
15734 | connector->encoder = encoder; | |
15735 | drm_mode_connector_attach_encoder(&connector->base, | |
15736 | &encoder->base); | |
79e53945 | 15737 | } |
28d52043 DA |
15738 | |
15739 | /* | |
15740 | * set vga decode state - true == enable VGA decode | |
15741 | */ | |
15742 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15743 | { | |
15744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15745 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15746 | u16 gmch_ctrl; |
15747 | ||
75fa041d CW |
15748 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15749 | DRM_ERROR("failed to read control word\n"); | |
15750 | return -EIO; | |
15751 | } | |
15752 | ||
c0cc8a55 CW |
15753 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15754 | return 0; | |
15755 | ||
28d52043 DA |
15756 | if (state) |
15757 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15758 | else | |
15759 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15760 | |
15761 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15762 | DRM_ERROR("failed to write control word\n"); | |
15763 | return -EIO; | |
15764 | } | |
15765 | ||
28d52043 DA |
15766 | return 0; |
15767 | } | |
c4a1d9e4 | 15768 | |
c4a1d9e4 | 15769 | struct intel_display_error_state { |
ff57f1b0 PZ |
15770 | |
15771 | u32 power_well_driver; | |
15772 | ||
63b66e5b CW |
15773 | int num_transcoders; |
15774 | ||
c4a1d9e4 CW |
15775 | struct intel_cursor_error_state { |
15776 | u32 control; | |
15777 | u32 position; | |
15778 | u32 base; | |
15779 | u32 size; | |
52331309 | 15780 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15781 | |
15782 | struct intel_pipe_error_state { | |
ddf9c536 | 15783 | bool power_domain_on; |
c4a1d9e4 | 15784 | u32 source; |
f301b1e1 | 15785 | u32 stat; |
52331309 | 15786 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15787 | |
15788 | struct intel_plane_error_state { | |
15789 | u32 control; | |
15790 | u32 stride; | |
15791 | u32 size; | |
15792 | u32 pos; | |
15793 | u32 addr; | |
15794 | u32 surface; | |
15795 | u32 tile_offset; | |
52331309 | 15796 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15797 | |
15798 | struct intel_transcoder_error_state { | |
ddf9c536 | 15799 | bool power_domain_on; |
63b66e5b CW |
15800 | enum transcoder cpu_transcoder; |
15801 | ||
15802 | u32 conf; | |
15803 | ||
15804 | u32 htotal; | |
15805 | u32 hblank; | |
15806 | u32 hsync; | |
15807 | u32 vtotal; | |
15808 | u32 vblank; | |
15809 | u32 vsync; | |
15810 | } transcoder[4]; | |
c4a1d9e4 CW |
15811 | }; |
15812 | ||
15813 | struct intel_display_error_state * | |
15814 | intel_display_capture_error_state(struct drm_device *dev) | |
15815 | { | |
fbee40df | 15816 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15817 | struct intel_display_error_state *error; |
63b66e5b CW |
15818 | int transcoders[] = { |
15819 | TRANSCODER_A, | |
15820 | TRANSCODER_B, | |
15821 | TRANSCODER_C, | |
15822 | TRANSCODER_EDP, | |
15823 | }; | |
c4a1d9e4 CW |
15824 | int i; |
15825 | ||
63b66e5b CW |
15826 | if (INTEL_INFO(dev)->num_pipes == 0) |
15827 | return NULL; | |
15828 | ||
9d1cb914 | 15829 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15830 | if (error == NULL) |
15831 | return NULL; | |
15832 | ||
190be112 | 15833 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15834 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15835 | ||
055e393f | 15836 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15837 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15838 | __intel_display_power_is_enabled(dev_priv, |
15839 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15840 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15841 | continue; |
15842 | ||
5efb3e28 VS |
15843 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15844 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15845 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15846 | |
15847 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15848 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15849 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15850 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15851 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15852 | } | |
ca291363 PZ |
15853 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15854 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15855 | if (INTEL_INFO(dev)->gen >= 4) { |
15856 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15857 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15858 | } | |
15859 | ||
c4a1d9e4 | 15860 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15861 | |
3abfce77 | 15862 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15863 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15864 | } |
15865 | ||
15866 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15867 | if (HAS_DDI(dev_priv->dev)) | |
15868 | error->num_transcoders++; /* Account for eDP. */ | |
15869 | ||
15870 | for (i = 0; i < error->num_transcoders; i++) { | |
15871 | enum transcoder cpu_transcoder = transcoders[i]; | |
15872 | ||
ddf9c536 | 15873 | error->transcoder[i].power_domain_on = |
f458ebbc | 15874 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15875 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15876 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15877 | continue; |
15878 | ||
63b66e5b CW |
15879 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15880 | ||
15881 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15882 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15883 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15884 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15885 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15886 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15887 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15888 | } |
15889 | ||
15890 | return error; | |
15891 | } | |
15892 | ||
edc3d884 MK |
15893 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15894 | ||
c4a1d9e4 | 15895 | void |
edc3d884 | 15896 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15897 | struct drm_device *dev, |
15898 | struct intel_display_error_state *error) | |
15899 | { | |
055e393f | 15900 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15901 | int i; |
15902 | ||
63b66e5b CW |
15903 | if (!error) |
15904 | return; | |
15905 | ||
edc3d884 | 15906 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15907 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15908 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15909 | error->power_well_driver); |
055e393f | 15910 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15911 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15912 | err_printf(m, " Power: %s\n", |
15913 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15914 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15915 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15916 | |
15917 | err_printf(m, "Plane [%d]:\n", i); | |
15918 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15919 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15920 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15921 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15922 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15923 | } |
4b71a570 | 15924 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15925 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15926 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15927 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15928 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15929 | } |
15930 | ||
edc3d884 MK |
15931 | err_printf(m, "Cursor [%d]:\n", i); |
15932 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15933 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15934 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15935 | } |
63b66e5b CW |
15936 | |
15937 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15938 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15939 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15940 | err_printf(m, " Power: %s\n", |
15941 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15942 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15943 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15944 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15945 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15946 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15947 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15948 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15949 | } | |
c4a1d9e4 | 15950 | } |
e2fcdaa9 VS |
15951 | |
15952 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15953 | { | |
15954 | struct intel_crtc *crtc; | |
15955 | ||
15956 | for_each_intel_crtc(dev, crtc) { | |
15957 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15958 | |
5e2d7afc | 15959 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15960 | |
15961 | work = crtc->unpin_work; | |
15962 | ||
15963 | if (work && work->event && | |
15964 | work->event->base.file_priv == file) { | |
15965 | kfree(work->event); | |
15966 | work->event = NULL; | |
15967 | } | |
15968 | ||
5e2d7afc | 15969 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15970 | } |
15971 | } |