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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
106 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
107 | struct intel_crtc_state *crtc_state); | |
e7457a9a | 108 | |
0e32b39c DA |
109 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
110 | { | |
111 | if (!connector->mst_port) | |
112 | return connector->encoder; | |
113 | else | |
114 | return &connector->mst_port->mst_encoders[pipe]->base; | |
115 | } | |
116 | ||
79e53945 | 117 | typedef struct { |
0206e353 | 118 | int min, max; |
79e53945 JB |
119 | } intel_range_t; |
120 | ||
121 | typedef struct { | |
0206e353 AJ |
122 | int dot_limit; |
123 | int p2_slow, p2_fast; | |
79e53945 JB |
124 | } intel_p2_t; |
125 | ||
d4906093 ML |
126 | typedef struct intel_limit intel_limit_t; |
127 | struct intel_limit { | |
0206e353 AJ |
128 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
129 | intel_p2_t p2; | |
d4906093 | 130 | }; |
79e53945 | 131 | |
d2acd215 DV |
132 | int |
133 | intel_pch_rawclk(struct drm_device *dev) | |
134 | { | |
135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
136 | ||
137 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
138 | ||
139 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
140 | } | |
141 | ||
021357ac CW |
142 | static inline u32 /* units of 100MHz */ |
143 | intel_fdi_link_freq(struct drm_device *dev) | |
144 | { | |
8b99e68c CW |
145 | if (IS_GEN5(dev)) { |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
148 | } else | |
149 | return 27; | |
021357ac CW |
150 | } |
151 | ||
5d536e28 | 152 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 153 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 154 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 155 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
156 | .m = { .min = 96, .max = 140 }, |
157 | .m1 = { .min = 18, .max = 26 }, | |
158 | .m2 = { .min = 6, .max = 16 }, | |
159 | .p = { .min = 4, .max = 128 }, | |
160 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
161 | .p2 = { .dot_limit = 165000, |
162 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
163 | }; |
164 | ||
5d536e28 DV |
165 | static const intel_limit_t intel_limits_i8xx_dvo = { |
166 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 167 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 168 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
169 | .m = { .min = 96, .max = 140 }, |
170 | .m1 = { .min = 18, .max = 26 }, | |
171 | .m2 = { .min = 6, .max = 16 }, | |
172 | .p = { .min = 4, .max = 128 }, | |
173 | .p1 = { .min = 2, .max = 33 }, | |
174 | .p2 = { .dot_limit = 165000, | |
175 | .p2_slow = 4, .p2_fast = 4 }, | |
176 | }; | |
177 | ||
e4b36699 | 178 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 179 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 180 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 181 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
182 | .m = { .min = 96, .max = 140 }, |
183 | .m1 = { .min = 18, .max = 26 }, | |
184 | .m2 = { .min = 6, .max = 16 }, | |
185 | .p = { .min = 4, .max = 128 }, | |
186 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
187 | .p2 = { .dot_limit = 165000, |
188 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 189 | }; |
273e27ca | 190 | |
e4b36699 | 191 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
192 | .dot = { .min = 20000, .max = 400000 }, |
193 | .vco = { .min = 1400000, .max = 2800000 }, | |
194 | .n = { .min = 1, .max = 6 }, | |
195 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
196 | .m1 = { .min = 8, .max = 18 }, |
197 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
198 | .p = { .min = 5, .max = 80 }, |
199 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
200 | .p2 = { .dot_limit = 200000, |
201 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
202 | }; |
203 | ||
204 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
205 | .dot = { .min = 20000, .max = 400000 }, |
206 | .vco = { .min = 1400000, .max = 2800000 }, | |
207 | .n = { .min = 1, .max = 6 }, | |
208 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
209 | .m1 = { .min = 8, .max = 18 }, |
210 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
211 | .p = { .min = 7, .max = 98 }, |
212 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
213 | .p2 = { .dot_limit = 112000, |
214 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
215 | }; |
216 | ||
273e27ca | 217 | |
e4b36699 | 218 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
219 | .dot = { .min = 25000, .max = 270000 }, |
220 | .vco = { .min = 1750000, .max = 3500000}, | |
221 | .n = { .min = 1, .max = 4 }, | |
222 | .m = { .min = 104, .max = 138 }, | |
223 | .m1 = { .min = 17, .max = 23 }, | |
224 | .m2 = { .min = 5, .max = 11 }, | |
225 | .p = { .min = 10, .max = 30 }, | |
226 | .p1 = { .min = 1, .max = 3}, | |
227 | .p2 = { .dot_limit = 270000, | |
228 | .p2_slow = 10, | |
229 | .p2_fast = 10 | |
044c7c41 | 230 | }, |
e4b36699 KP |
231 | }; |
232 | ||
233 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
234 | .dot = { .min = 22000, .max = 400000 }, |
235 | .vco = { .min = 1750000, .max = 3500000}, | |
236 | .n = { .min = 1, .max = 4 }, | |
237 | .m = { .min = 104, .max = 138 }, | |
238 | .m1 = { .min = 16, .max = 23 }, | |
239 | .m2 = { .min = 5, .max = 11 }, | |
240 | .p = { .min = 5, .max = 80 }, | |
241 | .p1 = { .min = 1, .max = 8}, | |
242 | .p2 = { .dot_limit = 165000, | |
243 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
244 | }; |
245 | ||
246 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
247 | .dot = { .min = 20000, .max = 115000 }, |
248 | .vco = { .min = 1750000, .max = 3500000 }, | |
249 | .n = { .min = 1, .max = 3 }, | |
250 | .m = { .min = 104, .max = 138 }, | |
251 | .m1 = { .min = 17, .max = 23 }, | |
252 | .m2 = { .min = 5, .max = 11 }, | |
253 | .p = { .min = 28, .max = 112 }, | |
254 | .p1 = { .min = 2, .max = 8 }, | |
255 | .p2 = { .dot_limit = 0, | |
256 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 257 | }, |
e4b36699 KP |
258 | }; |
259 | ||
260 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
261 | .dot = { .min = 80000, .max = 224000 }, |
262 | .vco = { .min = 1750000, .max = 3500000 }, | |
263 | .n = { .min = 1, .max = 3 }, | |
264 | .m = { .min = 104, .max = 138 }, | |
265 | .m1 = { .min = 17, .max = 23 }, | |
266 | .m2 = { .min = 5, .max = 11 }, | |
267 | .p = { .min = 14, .max = 42 }, | |
268 | .p1 = { .min = 2, .max = 6 }, | |
269 | .p2 = { .dot_limit = 0, | |
270 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 271 | }, |
e4b36699 KP |
272 | }; |
273 | ||
f2b115e6 | 274 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
275 | .dot = { .min = 20000, .max = 400000}, |
276 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 277 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
278 | .n = { .min = 3, .max = 6 }, |
279 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 280 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
281 | .m1 = { .min = 0, .max = 0 }, |
282 | .m2 = { .min = 0, .max = 254 }, | |
283 | .p = { .min = 5, .max = 80 }, | |
284 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
285 | .p2 = { .dot_limit = 200000, |
286 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
287 | }; |
288 | ||
f2b115e6 | 289 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
290 | .dot = { .min = 20000, .max = 400000 }, |
291 | .vco = { .min = 1700000, .max = 3500000 }, | |
292 | .n = { .min = 3, .max = 6 }, | |
293 | .m = { .min = 2, .max = 256 }, | |
294 | .m1 = { .min = 0, .max = 0 }, | |
295 | .m2 = { .min = 0, .max = 254 }, | |
296 | .p = { .min = 7, .max = 112 }, | |
297 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 112000, |
299 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
300 | }; |
301 | ||
273e27ca EA |
302 | /* Ironlake / Sandybridge |
303 | * | |
304 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
305 | * the range value for them is (actual_value - 2). | |
306 | */ | |
b91ad0ec | 307 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
308 | .dot = { .min = 25000, .max = 350000 }, |
309 | .vco = { .min = 1760000, .max = 3510000 }, | |
310 | .n = { .min = 1, .max = 5 }, | |
311 | .m = { .min = 79, .max = 127 }, | |
312 | .m1 = { .min = 12, .max = 22 }, | |
313 | .m2 = { .min = 5, .max = 9 }, | |
314 | .p = { .min = 5, .max = 80 }, | |
315 | .p1 = { .min = 1, .max = 8 }, | |
316 | .p2 = { .dot_limit = 225000, | |
317 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
318 | }; |
319 | ||
b91ad0ec | 320 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 350000 }, |
322 | .vco = { .min = 1760000, .max = 3510000 }, | |
323 | .n = { .min = 1, .max = 3 }, | |
324 | .m = { .min = 79, .max = 118 }, | |
325 | .m1 = { .min = 12, .max = 22 }, | |
326 | .m2 = { .min = 5, .max = 9 }, | |
327 | .p = { .min = 28, .max = 112 }, | |
328 | .p1 = { .min = 2, .max = 8 }, | |
329 | .p2 = { .dot_limit = 225000, | |
330 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
331 | }; |
332 | ||
333 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, | |
336 | .n = { .min = 1, .max = 3 }, | |
337 | .m = { .min = 79, .max = 127 }, | |
338 | .m1 = { .min = 12, .max = 22 }, | |
339 | .m2 = { .min = 5, .max = 9 }, | |
340 | .p = { .min = 14, .max = 56 }, | |
341 | .p1 = { .min = 2, .max = 8 }, | |
342 | .p2 = { .dot_limit = 225000, | |
343 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
344 | }; |
345 | ||
273e27ca | 346 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 347 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 2 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
358 | }; |
359 | ||
360 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
361 | .dot = { .min = 25000, .max = 350000 }, |
362 | .vco = { .min = 1760000, .max = 3510000 }, | |
363 | .n = { .min = 1, .max = 3 }, | |
364 | .m = { .min = 79, .max = 126 }, | |
365 | .m1 = { .min = 12, .max = 22 }, | |
366 | .m2 = { .min = 5, .max = 9 }, | |
367 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 368 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
369 | .p2 = { .dot_limit = 225000, |
370 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
371 | }; |
372 | ||
dc730512 | 373 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
374 | /* |
375 | * These are the data rate limits (measured in fast clocks) | |
376 | * since those are the strictest limits we have. The fast | |
377 | * clock and actual rate limits are more relaxed, so checking | |
378 | * them would make no difference. | |
379 | */ | |
380 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 381 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 382 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
383 | .m1 = { .min = 2, .max = 3 }, |
384 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 385 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 386 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
387 | }; |
388 | ||
ef9348c8 CML |
389 | static const intel_limit_t intel_limits_chv = { |
390 | /* | |
391 | * These are the data rate limits (measured in fast clocks) | |
392 | * since those are the strictest limits we have. The fast | |
393 | * clock and actual rate limits are more relaxed, so checking | |
394 | * them would make no difference. | |
395 | */ | |
396 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 397 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
398 | .n = { .min = 1, .max = 1 }, |
399 | .m1 = { .min = 2, .max = 2 }, | |
400 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
401 | .p1 = { .min = 2, .max = 4 }, | |
402 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
403 | }; | |
404 | ||
6b4bf1c4 VS |
405 | static void vlv_clock(int refclk, intel_clock_t *clock) |
406 | { | |
407 | clock->m = clock->m1 * clock->m2; | |
408 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
409 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
410 | return; | |
fb03ac01 VS |
411 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
412 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
413 | } |
414 | ||
e0638cdf PZ |
415 | /** |
416 | * Returns whether any output on the specified pipe is of the specified type | |
417 | */ | |
4093561b | 418 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 419 | { |
409ee761 | 420 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
421 | struct intel_encoder *encoder; |
422 | ||
409ee761 | 423 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
424 | if (encoder->type == type) |
425 | return true; | |
426 | ||
427 | return false; | |
428 | } | |
429 | ||
d0737e1d ACO |
430 | /** |
431 | * Returns whether any output on the specified pipe will have the specified | |
432 | * type after a staged modeset is complete, i.e., the same as | |
433 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
434 | * encoder->crtc. | |
435 | */ | |
a93e255f ACO |
436 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
437 | int type) | |
d0737e1d | 438 | { |
a93e255f ACO |
439 | struct drm_atomic_state *state = crtc_state->base.state; |
440 | struct drm_connector_state *connector_state; | |
d0737e1d | 441 | struct intel_encoder *encoder; |
a93e255f ACO |
442 | int i, num_connectors = 0; |
443 | ||
444 | for (i = 0; i < state->num_connector; i++) { | |
445 | if (!state->connectors[i]) | |
446 | continue; | |
447 | ||
448 | connector_state = state->connector_states[i]; | |
449 | if (connector_state->crtc != crtc_state->base.crtc) | |
450 | continue; | |
451 | ||
452 | num_connectors++; | |
d0737e1d | 453 | |
a93e255f ACO |
454 | encoder = to_intel_encoder(connector_state->best_encoder); |
455 | if (encoder->type == type) | |
d0737e1d | 456 | return true; |
a93e255f ACO |
457 | } |
458 | ||
459 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
460 | |
461 | return false; | |
462 | } | |
463 | ||
a93e255f ACO |
464 | static const intel_limit_t * |
465 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 466 | { |
a93e255f | 467 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 468 | const intel_limit_t *limit; |
b91ad0ec | 469 | |
a93e255f | 470 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 471 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 472 | if (refclk == 100000) |
b91ad0ec ZW |
473 | limit = &intel_limits_ironlake_dual_lvds_100m; |
474 | else | |
475 | limit = &intel_limits_ironlake_dual_lvds; | |
476 | } else { | |
1b894b59 | 477 | if (refclk == 100000) |
b91ad0ec ZW |
478 | limit = &intel_limits_ironlake_single_lvds_100m; |
479 | else | |
480 | limit = &intel_limits_ironlake_single_lvds; | |
481 | } | |
c6bb3538 | 482 | } else |
b91ad0ec | 483 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
484 | |
485 | return limit; | |
486 | } | |
487 | ||
a93e255f ACO |
488 | static const intel_limit_t * |
489 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 490 | { |
a93e255f | 491 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
492 | const intel_limit_t *limit; |
493 | ||
a93e255f | 494 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 495 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 496 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 497 | else |
e4b36699 | 498 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
499 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
500 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 501 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 502 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 503 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 504 | } else /* The option is for other outputs */ |
e4b36699 | 505 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
506 | |
507 | return limit; | |
508 | } | |
509 | ||
a93e255f ACO |
510 | static const intel_limit_t * |
511 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 512 | { |
a93e255f | 513 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
514 | const intel_limit_t *limit; |
515 | ||
bad720ff | 516 | if (HAS_PCH_SPLIT(dev)) |
a93e255f | 517 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 518 | else if (IS_G4X(dev)) { |
a93e255f | 519 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 520 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 521 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 522 | limit = &intel_limits_pineview_lvds; |
2177832f | 523 | else |
f2b115e6 | 524 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
525 | } else if (IS_CHERRYVIEW(dev)) { |
526 | limit = &intel_limits_chv; | |
a0c4da24 | 527 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 528 | limit = &intel_limits_vlv; |
a6c45cf0 | 529 | } else if (!IS_GEN2(dev)) { |
a93e255f | 530 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
531 | limit = &intel_limits_i9xx_lvds; |
532 | else | |
533 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 534 | } else { |
a93e255f | 535 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 536 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 537 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 538 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
539 | else |
540 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
541 | } |
542 | return limit; | |
543 | } | |
544 | ||
f2b115e6 AJ |
545 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
546 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 547 | { |
2177832f SL |
548 | clock->m = clock->m2 + 2; |
549 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
550 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
551 | return; | |
fb03ac01 VS |
552 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
553 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
554 | } |
555 | ||
7429e9d4 DV |
556 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
557 | { | |
558 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
559 | } | |
560 | ||
ac58c3f0 | 561 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 562 | { |
7429e9d4 | 563 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 564 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
565 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
566 | return; | |
fb03ac01 VS |
567 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
568 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
569 | } |
570 | ||
ef9348c8 CML |
571 | static void chv_clock(int refclk, intel_clock_t *clock) |
572 | { | |
573 | clock->m = clock->m1 * clock->m2; | |
574 | clock->p = clock->p1 * clock->p2; | |
575 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
576 | return; | |
577 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
578 | clock->n << 22); | |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
580 | } | |
581 | ||
7c04d1d9 | 582 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
583 | /** |
584 | * Returns whether the given set of divisors are valid for a given refclk with | |
585 | * the given connectors. | |
586 | */ | |
587 | ||
1b894b59 CW |
588 | static bool intel_PLL_is_valid(struct drm_device *dev, |
589 | const intel_limit_t *limit, | |
590 | const intel_clock_t *clock) | |
79e53945 | 591 | { |
f01b7962 VS |
592 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
593 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 594 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 595 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 596 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 597 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 598 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 599 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
600 | |
601 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
602 | if (clock->m1 <= clock->m2) | |
603 | INTELPllInvalid("m1 <= m2\n"); | |
604 | ||
605 | if (!IS_VALLEYVIEW(dev)) { | |
606 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
607 | INTELPllInvalid("p out of range\n"); | |
608 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
609 | INTELPllInvalid("m out of range\n"); | |
610 | } | |
611 | ||
79e53945 | 612 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 613 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
614 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
615 | * connector, etc., rather than just a single range. | |
616 | */ | |
617 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 618 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
619 | |
620 | return true; | |
621 | } | |
622 | ||
d4906093 | 623 | static bool |
a93e255f ACO |
624 | i9xx_find_best_dpll(const intel_limit_t *limit, |
625 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
626 | int target, int refclk, intel_clock_t *match_clock, |
627 | intel_clock_t *best_clock) | |
79e53945 | 628 | { |
a93e255f | 629 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 630 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 631 | intel_clock_t clock; |
79e53945 JB |
632 | int err = target; |
633 | ||
a93e255f | 634 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 635 | /* |
a210b028 DV |
636 | * For LVDS just rely on its current settings for dual-channel. |
637 | * We haven't figured out how to reliably set up different | |
638 | * single/dual channel state, if we even can. | |
79e53945 | 639 | */ |
1974cad0 | 640 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
641 | clock.p2 = limit->p2.p2_fast; |
642 | else | |
643 | clock.p2 = limit->p2.p2_slow; | |
644 | } else { | |
645 | if (target < limit->p2.dot_limit) | |
646 | clock.p2 = limit->p2.p2_slow; | |
647 | else | |
648 | clock.p2 = limit->p2.p2_fast; | |
649 | } | |
650 | ||
0206e353 | 651 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 652 | |
42158660 ZY |
653 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
654 | clock.m1++) { | |
655 | for (clock.m2 = limit->m2.min; | |
656 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 657 | if (clock.m2 >= clock.m1) |
42158660 ZY |
658 | break; |
659 | for (clock.n = limit->n.min; | |
660 | clock.n <= limit->n.max; clock.n++) { | |
661 | for (clock.p1 = limit->p1.min; | |
662 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
663 | int this_err; |
664 | ||
ac58c3f0 DV |
665 | i9xx_clock(refclk, &clock); |
666 | if (!intel_PLL_is_valid(dev, limit, | |
667 | &clock)) | |
668 | continue; | |
669 | if (match_clock && | |
670 | clock.p != match_clock->p) | |
671 | continue; | |
672 | ||
673 | this_err = abs(clock.dot - target); | |
674 | if (this_err < err) { | |
675 | *best_clock = clock; | |
676 | err = this_err; | |
677 | } | |
678 | } | |
679 | } | |
680 | } | |
681 | } | |
682 | ||
683 | return (err != target); | |
684 | } | |
685 | ||
686 | static bool | |
a93e255f ACO |
687 | pnv_find_best_dpll(const intel_limit_t *limit, |
688 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
689 | int target, int refclk, intel_clock_t *match_clock, |
690 | intel_clock_t *best_clock) | |
79e53945 | 691 | { |
a93e255f | 692 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 693 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 694 | intel_clock_t clock; |
79e53945 JB |
695 | int err = target; |
696 | ||
a93e255f | 697 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 698 | /* |
a210b028 DV |
699 | * For LVDS just rely on its current settings for dual-channel. |
700 | * We haven't figured out how to reliably set up different | |
701 | * single/dual channel state, if we even can. | |
79e53945 | 702 | */ |
1974cad0 | 703 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
704 | clock.p2 = limit->p2.p2_fast; |
705 | else | |
706 | clock.p2 = limit->p2.p2_slow; | |
707 | } else { | |
708 | if (target < limit->p2.dot_limit) | |
709 | clock.p2 = limit->p2.p2_slow; | |
710 | else | |
711 | clock.p2 = limit->p2.p2_fast; | |
712 | } | |
713 | ||
0206e353 | 714 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 715 | |
42158660 ZY |
716 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
717 | clock.m1++) { | |
718 | for (clock.m2 = limit->m2.min; | |
719 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
720 | for (clock.n = limit->n.min; |
721 | clock.n <= limit->n.max; clock.n++) { | |
722 | for (clock.p1 = limit->p1.min; | |
723 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
724 | int this_err; |
725 | ||
ac58c3f0 | 726 | pineview_clock(refclk, &clock); |
1b894b59 CW |
727 | if (!intel_PLL_is_valid(dev, limit, |
728 | &clock)) | |
79e53945 | 729 | continue; |
cec2f356 SP |
730 | if (match_clock && |
731 | clock.p != match_clock->p) | |
732 | continue; | |
79e53945 JB |
733 | |
734 | this_err = abs(clock.dot - target); | |
735 | if (this_err < err) { | |
736 | *best_clock = clock; | |
737 | err = this_err; | |
738 | } | |
739 | } | |
740 | } | |
741 | } | |
742 | } | |
743 | ||
744 | return (err != target); | |
745 | } | |
746 | ||
d4906093 | 747 | static bool |
a93e255f ACO |
748 | g4x_find_best_dpll(const intel_limit_t *limit, |
749 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
750 | int target, int refclk, intel_clock_t *match_clock, |
751 | intel_clock_t *best_clock) | |
d4906093 | 752 | { |
a93e255f | 753 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 754 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
755 | intel_clock_t clock; |
756 | int max_n; | |
757 | bool found; | |
6ba770dc AJ |
758 | /* approximately equals target * 0.00585 */ |
759 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
760 | found = false; |
761 | ||
a93e255f | 762 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 763 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
764 | clock.p2 = limit->p2.p2_fast; |
765 | else | |
766 | clock.p2 = limit->p2.p2_slow; | |
767 | } else { | |
768 | if (target < limit->p2.dot_limit) | |
769 | clock.p2 = limit->p2.p2_slow; | |
770 | else | |
771 | clock.p2 = limit->p2.p2_fast; | |
772 | } | |
773 | ||
774 | memset(best_clock, 0, sizeof(*best_clock)); | |
775 | max_n = limit->n.max; | |
f77f13e2 | 776 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 777 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 778 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
779 | for (clock.m1 = limit->m1.max; |
780 | clock.m1 >= limit->m1.min; clock.m1--) { | |
781 | for (clock.m2 = limit->m2.max; | |
782 | clock.m2 >= limit->m2.min; clock.m2--) { | |
783 | for (clock.p1 = limit->p1.max; | |
784 | clock.p1 >= limit->p1.min; clock.p1--) { | |
785 | int this_err; | |
786 | ||
ac58c3f0 | 787 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
788 | if (!intel_PLL_is_valid(dev, limit, |
789 | &clock)) | |
d4906093 | 790 | continue; |
1b894b59 CW |
791 | |
792 | this_err = abs(clock.dot - target); | |
d4906093 ML |
793 | if (this_err < err_most) { |
794 | *best_clock = clock; | |
795 | err_most = this_err; | |
796 | max_n = clock.n; | |
797 | found = true; | |
798 | } | |
799 | } | |
800 | } | |
801 | } | |
802 | } | |
2c07245f ZW |
803 | return found; |
804 | } | |
805 | ||
d5dd62bd ID |
806 | /* |
807 | * Check if the calculated PLL configuration is more optimal compared to the | |
808 | * best configuration and error found so far. Return the calculated error. | |
809 | */ | |
810 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
811 | const intel_clock_t *calculated_clock, | |
812 | const intel_clock_t *best_clock, | |
813 | unsigned int best_error_ppm, | |
814 | unsigned int *error_ppm) | |
815 | { | |
9ca3ba01 ID |
816 | /* |
817 | * For CHV ignore the error and consider only the P value. | |
818 | * Prefer a bigger P value based on HW requirements. | |
819 | */ | |
820 | if (IS_CHERRYVIEW(dev)) { | |
821 | *error_ppm = 0; | |
822 | ||
823 | return calculated_clock->p > best_clock->p; | |
824 | } | |
825 | ||
24be4e46 ID |
826 | if (WARN_ON_ONCE(!target_freq)) |
827 | return false; | |
828 | ||
d5dd62bd ID |
829 | *error_ppm = div_u64(1000000ULL * |
830 | abs(target_freq - calculated_clock->dot), | |
831 | target_freq); | |
832 | /* | |
833 | * Prefer a better P value over a better (smaller) error if the error | |
834 | * is small. Ensure this preference for future configurations too by | |
835 | * setting the error to 0. | |
836 | */ | |
837 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
838 | *error_ppm = 0; | |
839 | ||
840 | return true; | |
841 | } | |
842 | ||
843 | return *error_ppm + 10 < best_error_ppm; | |
844 | } | |
845 | ||
a0c4da24 | 846 | static bool |
a93e255f ACO |
847 | vlv_find_best_dpll(const intel_limit_t *limit, |
848 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
849 | int target, int refclk, intel_clock_t *match_clock, |
850 | intel_clock_t *best_clock) | |
a0c4da24 | 851 | { |
a93e255f | 852 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 853 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 854 | intel_clock_t clock; |
69e4f900 | 855 | unsigned int bestppm = 1000000; |
27e639bf VS |
856 | /* min update 19.2 MHz */ |
857 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 858 | bool found = false; |
a0c4da24 | 859 | |
6b4bf1c4 VS |
860 | target *= 5; /* fast clock */ |
861 | ||
862 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
863 | |
864 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 865 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 866 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 867 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 868 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 869 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 870 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 871 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 872 | unsigned int ppm; |
69e4f900 | 873 | |
6b4bf1c4 VS |
874 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
875 | refclk * clock.m1); | |
876 | ||
877 | vlv_clock(refclk, &clock); | |
43b0ac53 | 878 | |
f01b7962 VS |
879 | if (!intel_PLL_is_valid(dev, limit, |
880 | &clock)) | |
43b0ac53 VS |
881 | continue; |
882 | ||
d5dd62bd ID |
883 | if (!vlv_PLL_is_optimal(dev, target, |
884 | &clock, | |
885 | best_clock, | |
886 | bestppm, &ppm)) | |
887 | continue; | |
6b4bf1c4 | 888 | |
d5dd62bd ID |
889 | *best_clock = clock; |
890 | bestppm = ppm; | |
891 | found = true; | |
a0c4da24 JB |
892 | } |
893 | } | |
894 | } | |
895 | } | |
a0c4da24 | 896 | |
49e497ef | 897 | return found; |
a0c4da24 | 898 | } |
a4fc5ed6 | 899 | |
ef9348c8 | 900 | static bool |
a93e255f ACO |
901 | chv_find_best_dpll(const intel_limit_t *limit, |
902 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
903 | int target, int refclk, intel_clock_t *match_clock, |
904 | intel_clock_t *best_clock) | |
905 | { | |
a93e255f | 906 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 907 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 908 | unsigned int best_error_ppm; |
ef9348c8 CML |
909 | intel_clock_t clock; |
910 | uint64_t m2; | |
911 | int found = false; | |
912 | ||
913 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 914 | best_error_ppm = 1000000; |
ef9348c8 CML |
915 | |
916 | /* | |
917 | * Based on hardware doc, the n always set to 1, and m1 always | |
918 | * set to 2. If requires to support 200Mhz refclk, we need to | |
919 | * revisit this because n may not 1 anymore. | |
920 | */ | |
921 | clock.n = 1, clock.m1 = 2; | |
922 | target *= 5; /* fast clock */ | |
923 | ||
924 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
925 | for (clock.p2 = limit->p2.p2_fast; | |
926 | clock.p2 >= limit->p2.p2_slow; | |
927 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 928 | unsigned int error_ppm; |
ef9348c8 CML |
929 | |
930 | clock.p = clock.p1 * clock.p2; | |
931 | ||
932 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
933 | clock.n) << 22, refclk * clock.m1); | |
934 | ||
935 | if (m2 > INT_MAX/clock.m1) | |
936 | continue; | |
937 | ||
938 | clock.m2 = m2; | |
939 | ||
940 | chv_clock(refclk, &clock); | |
941 | ||
942 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
943 | continue; | |
944 | ||
9ca3ba01 ID |
945 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
946 | best_error_ppm, &error_ppm)) | |
947 | continue; | |
948 | ||
949 | *best_clock = clock; | |
950 | best_error_ppm = error_ppm; | |
951 | found = true; | |
ef9348c8 CML |
952 | } |
953 | } | |
954 | ||
955 | return found; | |
956 | } | |
957 | ||
20ddf665 VS |
958 | bool intel_crtc_active(struct drm_crtc *crtc) |
959 | { | |
960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
961 | ||
962 | /* Be paranoid as we can arrive here with only partial | |
963 | * state retrieved from the hardware during setup. | |
964 | * | |
241bfc38 | 965 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
966 | * as Haswell has gained clock readout/fastboot support. |
967 | * | |
66e514c1 | 968 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 969 | * properly reconstruct framebuffers. |
c3d1f436 MR |
970 | * |
971 | * FIXME: The intel_crtc->active here should be switched to | |
972 | * crtc->state->active once we have proper CRTC states wired up | |
973 | * for atomic. | |
20ddf665 | 974 | */ |
c3d1f436 | 975 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 976 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
977 | } |
978 | ||
a5c961d1 PZ |
979 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
980 | enum pipe pipe) | |
981 | { | |
982 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
984 | ||
6e3c9717 | 985 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
986 | } |
987 | ||
fbf49ea2 VS |
988 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
989 | { | |
990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
991 | u32 reg = PIPEDSL(pipe); | |
992 | u32 line1, line2; | |
993 | u32 line_mask; | |
994 | ||
995 | if (IS_GEN2(dev)) | |
996 | line_mask = DSL_LINEMASK_GEN2; | |
997 | else | |
998 | line_mask = DSL_LINEMASK_GEN3; | |
999 | ||
1000 | line1 = I915_READ(reg) & line_mask; | |
1001 | mdelay(5); | |
1002 | line2 = I915_READ(reg) & line_mask; | |
1003 | ||
1004 | return line1 == line2; | |
1005 | } | |
1006 | ||
ab7ad7f6 KP |
1007 | /* |
1008 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1009 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1010 | * |
1011 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1012 | * spinning on the vblank interrupt status bit, since we won't actually | |
1013 | * see an interrupt when the pipe is disabled. | |
1014 | * | |
ab7ad7f6 KP |
1015 | * On Gen4 and above: |
1016 | * wait for the pipe register state bit to turn off | |
1017 | * | |
1018 | * Otherwise: | |
1019 | * wait for the display line value to settle (it usually | |
1020 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1021 | * |
9d0498a2 | 1022 | */ |
575f7ab7 | 1023 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1024 | { |
575f7ab7 | 1025 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1026 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1027 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1028 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1029 | |
1030 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1031 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1032 | |
1033 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1034 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1035 | 100)) | |
284637d9 | 1036 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1037 | } else { |
ab7ad7f6 | 1038 | /* Wait for the display line to settle */ |
fbf49ea2 | 1039 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1040 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1041 | } |
79e53945 JB |
1042 | } |
1043 | ||
b0ea7d37 DL |
1044 | /* |
1045 | * ibx_digital_port_connected - is the specified port connected? | |
1046 | * @dev_priv: i915 private structure | |
1047 | * @port: the port to test | |
1048 | * | |
1049 | * Returns true if @port is connected, false otherwise. | |
1050 | */ | |
1051 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1052 | struct intel_digital_port *port) | |
1053 | { | |
1054 | u32 bit; | |
1055 | ||
c36346e3 | 1056 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1057 | switch (port->port) { |
c36346e3 DL |
1058 | case PORT_B: |
1059 | bit = SDE_PORTB_HOTPLUG; | |
1060 | break; | |
1061 | case PORT_C: | |
1062 | bit = SDE_PORTC_HOTPLUG; | |
1063 | break; | |
1064 | case PORT_D: | |
1065 | bit = SDE_PORTD_HOTPLUG; | |
1066 | break; | |
1067 | default: | |
1068 | return true; | |
1069 | } | |
1070 | } else { | |
eba905b2 | 1071 | switch (port->port) { |
c36346e3 DL |
1072 | case PORT_B: |
1073 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1074 | break; | |
1075 | case PORT_C: | |
1076 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1077 | break; | |
1078 | case PORT_D: | |
1079 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1080 | break; | |
1081 | default: | |
1082 | return true; | |
1083 | } | |
b0ea7d37 DL |
1084 | } |
1085 | ||
1086 | return I915_READ(SDEISR) & bit; | |
1087 | } | |
1088 | ||
b24e7179 JB |
1089 | static const char *state_string(bool enabled) |
1090 | { | |
1091 | return enabled ? "on" : "off"; | |
1092 | } | |
1093 | ||
1094 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1095 | void assert_pll(struct drm_i915_private *dev_priv, |
1096 | enum pipe pipe, bool state) | |
b24e7179 JB |
1097 | { |
1098 | int reg; | |
1099 | u32 val; | |
1100 | bool cur_state; | |
1101 | ||
1102 | reg = DPLL(pipe); | |
1103 | val = I915_READ(reg); | |
1104 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1105 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1106 | "PLL state assertion failure (expected %s, current %s)\n", |
1107 | state_string(state), state_string(cur_state)); | |
1108 | } | |
b24e7179 | 1109 | |
23538ef1 JN |
1110 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1111 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1112 | { | |
1113 | u32 val; | |
1114 | bool cur_state; | |
1115 | ||
1116 | mutex_lock(&dev_priv->dpio_lock); | |
1117 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1118 | mutex_unlock(&dev_priv->dpio_lock); | |
1119 | ||
1120 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1121 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1122 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1123 | state_string(state), state_string(cur_state)); | |
1124 | } | |
1125 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1126 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1127 | ||
55607e8a | 1128 | struct intel_shared_dpll * |
e2b78267 DV |
1129 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1130 | { | |
1131 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1132 | ||
6e3c9717 | 1133 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1134 | return NULL; |
1135 | ||
6e3c9717 | 1136 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1137 | } |
1138 | ||
040484af | 1139 | /* For ILK+ */ |
55607e8a DV |
1140 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1141 | struct intel_shared_dpll *pll, | |
1142 | bool state) | |
040484af | 1143 | { |
040484af | 1144 | bool cur_state; |
5358901f | 1145 | struct intel_dpll_hw_state hw_state; |
040484af | 1146 | |
92b27b08 | 1147 | if (WARN (!pll, |
46edb027 | 1148 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1149 | return; |
ee7b9f93 | 1150 | |
5358901f | 1151 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1152 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1153 | "%s assertion failure (expected %s, current %s)\n", |
1154 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1155 | } |
040484af JB |
1156 | |
1157 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1158 | enum pipe pipe, bool state) | |
1159 | { | |
1160 | int reg; | |
1161 | u32 val; | |
1162 | bool cur_state; | |
ad80a810 PZ |
1163 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1164 | pipe); | |
040484af | 1165 | |
affa9354 PZ |
1166 | if (HAS_DDI(dev_priv->dev)) { |
1167 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1168 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1169 | val = I915_READ(reg); |
ad80a810 | 1170 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1171 | } else { |
1172 | reg = FDI_TX_CTL(pipe); | |
1173 | val = I915_READ(reg); | |
1174 | cur_state = !!(val & FDI_TX_ENABLE); | |
1175 | } | |
e2c719b7 | 1176 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1177 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1178 | state_string(state), state_string(cur_state)); | |
1179 | } | |
1180 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1181 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1182 | ||
1183 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1184 | enum pipe pipe, bool state) | |
1185 | { | |
1186 | int reg; | |
1187 | u32 val; | |
1188 | bool cur_state; | |
1189 | ||
d63fa0dc PZ |
1190 | reg = FDI_RX_CTL(pipe); |
1191 | val = I915_READ(reg); | |
1192 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1193 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1194 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1195 | state_string(state), state_string(cur_state)); | |
1196 | } | |
1197 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1198 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1199 | ||
1200 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1201 | enum pipe pipe) | |
1202 | { | |
1203 | int reg; | |
1204 | u32 val; | |
1205 | ||
1206 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1207 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1208 | return; |
1209 | ||
bf507ef7 | 1210 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1211 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1212 | return; |
1213 | ||
040484af JB |
1214 | reg = FDI_TX_CTL(pipe); |
1215 | val = I915_READ(reg); | |
e2c719b7 | 1216 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1217 | } |
1218 | ||
55607e8a DV |
1219 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1220 | enum pipe pipe, bool state) | |
040484af JB |
1221 | { |
1222 | int reg; | |
1223 | u32 val; | |
55607e8a | 1224 | bool cur_state; |
040484af JB |
1225 | |
1226 | reg = FDI_RX_CTL(pipe); | |
1227 | val = I915_READ(reg); | |
55607e8a | 1228 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1229 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1230 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1231 | state_string(state), state_string(cur_state)); | |
040484af JB |
1232 | } |
1233 | ||
b680c37a DV |
1234 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1235 | enum pipe pipe) | |
ea0760cf | 1236 | { |
bedd4dba JN |
1237 | struct drm_device *dev = dev_priv->dev; |
1238 | int pp_reg; | |
ea0760cf JB |
1239 | u32 val; |
1240 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1241 | bool locked = true; |
ea0760cf | 1242 | |
bedd4dba JN |
1243 | if (WARN_ON(HAS_DDI(dev))) |
1244 | return; | |
1245 | ||
1246 | if (HAS_PCH_SPLIT(dev)) { | |
1247 | u32 port_sel; | |
1248 | ||
ea0760cf | 1249 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1250 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1251 | ||
1252 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1253 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1254 | panel_pipe = PIPE_B; | |
1255 | /* XXX: else fix for eDP */ | |
1256 | } else if (IS_VALLEYVIEW(dev)) { | |
1257 | /* presumably write lock depends on pipe, not port select */ | |
1258 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1259 | panel_pipe = pipe; | |
ea0760cf JB |
1260 | } else { |
1261 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1262 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1263 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1264 | } |
1265 | ||
1266 | val = I915_READ(pp_reg); | |
1267 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1268 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1269 | locked = false; |
1270 | ||
e2c719b7 | 1271 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1272 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1273 | pipe_name(pipe)); |
ea0760cf JB |
1274 | } |
1275 | ||
93ce0ba6 JN |
1276 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1277 | enum pipe pipe, bool state) | |
1278 | { | |
1279 | struct drm_device *dev = dev_priv->dev; | |
1280 | bool cur_state; | |
1281 | ||
d9d82081 | 1282 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1283 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1284 | else |
5efb3e28 | 1285 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1286 | |
e2c719b7 | 1287 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1288 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1289 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1290 | } | |
1291 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1292 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1293 | ||
b840d907 JB |
1294 | void assert_pipe(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe, bool state) | |
b24e7179 JB |
1296 | { |
1297 | int reg; | |
1298 | u32 val; | |
63d7bbe9 | 1299 | bool cur_state; |
702e7a56 PZ |
1300 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1301 | pipe); | |
b24e7179 | 1302 | |
b6b5d049 VS |
1303 | /* if we need the pipe quirk it must be always on */ |
1304 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1305 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1306 | state = true; |
1307 | ||
f458ebbc | 1308 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1309 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1310 | cur_state = false; |
1311 | } else { | |
1312 | reg = PIPECONF(cpu_transcoder); | |
1313 | val = I915_READ(reg); | |
1314 | cur_state = !!(val & PIPECONF_ENABLE); | |
1315 | } | |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1318 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1319 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1320 | } |
1321 | ||
931872fc CW |
1322 | static void assert_plane(struct drm_i915_private *dev_priv, |
1323 | enum plane plane, bool state) | |
b24e7179 JB |
1324 | { |
1325 | int reg; | |
1326 | u32 val; | |
931872fc | 1327 | bool cur_state; |
b24e7179 JB |
1328 | |
1329 | reg = DSPCNTR(plane); | |
1330 | val = I915_READ(reg); | |
931872fc | 1331 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1332 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1333 | "plane %c assertion failure (expected %s, current %s)\n", |
1334 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1335 | } |
1336 | ||
931872fc CW |
1337 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1338 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1339 | ||
b24e7179 JB |
1340 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe) | |
1342 | { | |
653e1026 | 1343 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1344 | int reg, i; |
1345 | u32 val; | |
1346 | int cur_pipe; | |
1347 | ||
653e1026 VS |
1348 | /* Primary planes are fixed to pipes on gen4+ */ |
1349 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1350 | reg = DSPCNTR(pipe); |
1351 | val = I915_READ(reg); | |
e2c719b7 | 1352 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1353 | "plane %c assertion failure, should be disabled but not\n", |
1354 | plane_name(pipe)); | |
19ec1358 | 1355 | return; |
28c05794 | 1356 | } |
19ec1358 | 1357 | |
b24e7179 | 1358 | /* Need to check both planes against the pipe */ |
055e393f | 1359 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1360 | reg = DSPCNTR(i); |
1361 | val = I915_READ(reg); | |
1362 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1363 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1364 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1365 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1366 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1367 | } |
1368 | } | |
1369 | ||
19332d7a JB |
1370 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1371 | enum pipe pipe) | |
1372 | { | |
20674eef | 1373 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1374 | int reg, sprite; |
19332d7a JB |
1375 | u32 val; |
1376 | ||
7feb8b88 | 1377 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1378 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1379 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1380 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1381 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1382 | sprite, pipe_name(pipe)); | |
1383 | } | |
1384 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1385 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1386 | reg = SPCNTR(pipe, sprite); |
20674eef | 1387 | val = I915_READ(reg); |
e2c719b7 | 1388 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1389 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1390 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1391 | } |
1392 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1393 | reg = SPRCTL(pipe); | |
19332d7a | 1394 | val = I915_READ(reg); |
e2c719b7 | 1395 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1396 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1397 | plane_name(pipe), pipe_name(pipe)); |
1398 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1399 | reg = DVSCNTR(pipe); | |
19332d7a | 1400 | val = I915_READ(reg); |
e2c719b7 | 1401 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1402 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1403 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1404 | } |
1405 | } | |
1406 | ||
08c71e5e VS |
1407 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1408 | { | |
e2c719b7 | 1409 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1410 | drm_crtc_vblank_put(crtc); |
1411 | } | |
1412 | ||
89eff4be | 1413 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1414 | { |
1415 | u32 val; | |
1416 | bool enabled; | |
1417 | ||
e2c719b7 | 1418 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1419 | |
92f2584a JB |
1420 | val = I915_READ(PCH_DREF_CONTROL); |
1421 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1422 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1423 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1424 | } |
1425 | ||
ab9412ba DV |
1426 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1427 | enum pipe pipe) | |
92f2584a JB |
1428 | { |
1429 | int reg; | |
1430 | u32 val; | |
1431 | bool enabled; | |
1432 | ||
ab9412ba | 1433 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1434 | val = I915_READ(reg); |
1435 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1436 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1437 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1438 | pipe_name(pipe)); | |
92f2584a JB |
1439 | } |
1440 | ||
4e634389 KP |
1441 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1442 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1443 | { |
1444 | if ((val & DP_PORT_EN) == 0) | |
1445 | return false; | |
1446 | ||
1447 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1448 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1449 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1450 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1451 | return false; | |
44f37d1f CML |
1452 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1453 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1454 | return false; | |
f0575e92 KP |
1455 | } else { |
1456 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1457 | return false; | |
1458 | } | |
1459 | return true; | |
1460 | } | |
1461 | ||
1519b995 KP |
1462 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1463 | enum pipe pipe, u32 val) | |
1464 | { | |
dc0fa718 | 1465 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1466 | return false; |
1467 | ||
1468 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1469 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1470 | return false; |
44f37d1f CML |
1471 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1472 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1473 | return false; | |
1519b995 | 1474 | } else { |
dc0fa718 | 1475 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1476 | return false; |
1477 | } | |
1478 | return true; | |
1479 | } | |
1480 | ||
1481 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1482 | enum pipe pipe, u32 val) | |
1483 | { | |
1484 | if ((val & LVDS_PORT_EN) == 0) | |
1485 | return false; | |
1486 | ||
1487 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1488 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1489 | return false; | |
1490 | } else { | |
1491 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1492 | return false; | |
1493 | } | |
1494 | return true; | |
1495 | } | |
1496 | ||
1497 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1498 | enum pipe pipe, u32 val) | |
1499 | { | |
1500 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1501 | return false; | |
1502 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1503 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1504 | return false; | |
1505 | } else { | |
1506 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1507 | return false; | |
1508 | } | |
1509 | return true; | |
1510 | } | |
1511 | ||
291906f1 | 1512 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1513 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1514 | { |
47a05eca | 1515 | u32 val = I915_READ(reg); |
e2c719b7 | 1516 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1517 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1518 | reg, pipe_name(pipe)); |
de9a35ab | 1519 | |
e2c719b7 | 1520 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1521 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1522 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1523 | } |
1524 | ||
1525 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1526 | enum pipe pipe, int reg) | |
1527 | { | |
47a05eca | 1528 | u32 val = I915_READ(reg); |
e2c719b7 | 1529 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1530 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1531 | reg, pipe_name(pipe)); |
de9a35ab | 1532 | |
e2c719b7 | 1533 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1534 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1535 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1536 | } |
1537 | ||
1538 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1539 | enum pipe pipe) | |
1540 | { | |
1541 | int reg; | |
1542 | u32 val; | |
291906f1 | 1543 | |
f0575e92 KP |
1544 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1545 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1546 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1547 | |
1548 | reg = PCH_ADPA; | |
1549 | val = I915_READ(reg); | |
e2c719b7 | 1550 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1551 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1552 | pipe_name(pipe)); |
291906f1 JB |
1553 | |
1554 | reg = PCH_LVDS; | |
1555 | val = I915_READ(reg); | |
e2c719b7 | 1556 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1557 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1558 | pipe_name(pipe)); |
291906f1 | 1559 | |
e2debe91 PZ |
1560 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1561 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1562 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1563 | } |
1564 | ||
40e9cf64 JB |
1565 | static void intel_init_dpio(struct drm_device *dev) |
1566 | { | |
1567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1568 | ||
1569 | if (!IS_VALLEYVIEW(dev)) | |
1570 | return; | |
1571 | ||
a09caddd CML |
1572 | /* |
1573 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1574 | * CHV x1 PHY (DP/HDMI D) | |
1575 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1576 | */ | |
1577 | if (IS_CHERRYVIEW(dev)) { | |
1578 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1579 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1580 | } else { | |
1581 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1582 | } | |
5382f5f3 JB |
1583 | } |
1584 | ||
d288f65f | 1585 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1586 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1587 | { |
426115cf DV |
1588 | struct drm_device *dev = crtc->base.dev; |
1589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1590 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1591 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1592 | |
426115cf | 1593 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1594 | |
1595 | /* No really, not for ILK+ */ | |
1596 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1597 | ||
1598 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1599 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1600 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1601 | |
426115cf DV |
1602 | I915_WRITE(reg, dpll); |
1603 | POSTING_READ(reg); | |
1604 | udelay(150); | |
1605 | ||
1606 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1607 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1608 | ||
d288f65f | 1609 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1610 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1611 | |
1612 | /* We do this three times for luck */ | |
426115cf | 1613 | I915_WRITE(reg, dpll); |
87442f73 DV |
1614 | POSTING_READ(reg); |
1615 | udelay(150); /* wait for warmup */ | |
426115cf | 1616 | I915_WRITE(reg, dpll); |
87442f73 DV |
1617 | POSTING_READ(reg); |
1618 | udelay(150); /* wait for warmup */ | |
426115cf | 1619 | I915_WRITE(reg, dpll); |
87442f73 DV |
1620 | POSTING_READ(reg); |
1621 | udelay(150); /* wait for warmup */ | |
1622 | } | |
1623 | ||
d288f65f | 1624 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1625 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1626 | { |
1627 | struct drm_device *dev = crtc->base.dev; | |
1628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1629 | int pipe = crtc->pipe; | |
1630 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1631 | u32 tmp; |
1632 | ||
1633 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1634 | ||
1635 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1636 | ||
1637 | mutex_lock(&dev_priv->dpio_lock); | |
1638 | ||
1639 | /* Enable back the 10bit clock to display controller */ | |
1640 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1641 | tmp |= DPIO_DCLKP_EN; | |
1642 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1643 | ||
1644 | /* | |
1645 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1646 | */ | |
1647 | udelay(1); | |
1648 | ||
1649 | /* Enable PLL */ | |
d288f65f | 1650 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1651 | |
1652 | /* Check PLL is locked */ | |
a11b0703 | 1653 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1654 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1655 | ||
a11b0703 | 1656 | /* not sure when this should be written */ |
d288f65f | 1657 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1658 | POSTING_READ(DPLL_MD(pipe)); |
1659 | ||
9d556c99 CML |
1660 | mutex_unlock(&dev_priv->dpio_lock); |
1661 | } | |
1662 | ||
1c4e0274 VS |
1663 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1664 | { | |
1665 | struct intel_crtc *crtc; | |
1666 | int count = 0; | |
1667 | ||
1668 | for_each_intel_crtc(dev, crtc) | |
1669 | count += crtc->active && | |
409ee761 | 1670 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1671 | |
1672 | return count; | |
1673 | } | |
1674 | ||
66e3d5c0 | 1675 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1676 | { |
66e3d5c0 DV |
1677 | struct drm_device *dev = crtc->base.dev; |
1678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1679 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1680 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1681 | |
66e3d5c0 | 1682 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1683 | |
63d7bbe9 | 1684 | /* No really, not for ILK+ */ |
3d13ef2e | 1685 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1686 | |
1687 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1688 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1689 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1690 | |
1c4e0274 VS |
1691 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1692 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1693 | /* | |
1694 | * It appears to be important that we don't enable this | |
1695 | * for the current pipe before otherwise configuring the | |
1696 | * PLL. No idea how this should be handled if multiple | |
1697 | * DVO outputs are enabled simultaneosly. | |
1698 | */ | |
1699 | dpll |= DPLL_DVO_2X_MODE; | |
1700 | I915_WRITE(DPLL(!crtc->pipe), | |
1701 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1702 | } | |
66e3d5c0 DV |
1703 | |
1704 | /* Wait for the clocks to stabilize. */ | |
1705 | POSTING_READ(reg); | |
1706 | udelay(150); | |
1707 | ||
1708 | if (INTEL_INFO(dev)->gen >= 4) { | |
1709 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1710 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1711 | } else { |
1712 | /* The pixel multiplier can only be updated once the | |
1713 | * DPLL is enabled and the clocks are stable. | |
1714 | * | |
1715 | * So write it again. | |
1716 | */ | |
1717 | I915_WRITE(reg, dpll); | |
1718 | } | |
63d7bbe9 JB |
1719 | |
1720 | /* We do this three times for luck */ | |
66e3d5c0 | 1721 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1722 | POSTING_READ(reg); |
1723 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1724 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1725 | POSTING_READ(reg); |
1726 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1727 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1728 | POSTING_READ(reg); |
1729 | udelay(150); /* wait for warmup */ | |
1730 | } | |
1731 | ||
1732 | /** | |
50b44a44 | 1733 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1734 | * @dev_priv: i915 private structure |
1735 | * @pipe: pipe PLL to disable | |
1736 | * | |
1737 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1738 | * | |
1739 | * Note! This is for pre-ILK only. | |
1740 | */ | |
1c4e0274 | 1741 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1742 | { |
1c4e0274 VS |
1743 | struct drm_device *dev = crtc->base.dev; |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1745 | enum pipe pipe = crtc->pipe; | |
1746 | ||
1747 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1748 | if (IS_I830(dev) && | |
409ee761 | 1749 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1750 | intel_num_dvo_pipes(dev) == 1) { |
1751 | I915_WRITE(DPLL(PIPE_B), | |
1752 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1753 | I915_WRITE(DPLL(PIPE_A), | |
1754 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1755 | } | |
1756 | ||
b6b5d049 VS |
1757 | /* Don't disable pipe or pipe PLLs if needed */ |
1758 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1759 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1760 | return; |
1761 | ||
1762 | /* Make sure the pipe isn't still relying on us */ | |
1763 | assert_pipe_disabled(dev_priv, pipe); | |
1764 | ||
50b44a44 DV |
1765 | I915_WRITE(DPLL(pipe), 0); |
1766 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1767 | } |
1768 | ||
f6071166 JB |
1769 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1770 | { | |
1771 | u32 val = 0; | |
1772 | ||
1773 | /* Make sure the pipe isn't still relying on us */ | |
1774 | assert_pipe_disabled(dev_priv, pipe); | |
1775 | ||
e5cbfbfb ID |
1776 | /* |
1777 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1778 | * The latter is needed for VGA hotplug / manual detection. | |
1779 | */ | |
f6071166 | 1780 | if (pipe == PIPE_B) |
e5cbfbfb | 1781 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1782 | I915_WRITE(DPLL(pipe), val); |
1783 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1784 | |
1785 | } | |
1786 | ||
1787 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1788 | { | |
d752048d | 1789 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1790 | u32 val; |
1791 | ||
a11b0703 VS |
1792 | /* Make sure the pipe isn't still relying on us */ |
1793 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1794 | |
a11b0703 | 1795 | /* Set PLL en = 0 */ |
d17ec4ce | 1796 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1797 | if (pipe != PIPE_A) |
1798 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1799 | I915_WRITE(DPLL(pipe), val); | |
1800 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1801 | |
1802 | mutex_lock(&dev_priv->dpio_lock); | |
1803 | ||
1804 | /* Disable 10bit clock to display controller */ | |
1805 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1806 | val &= ~DPIO_DCLKP_EN; | |
1807 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1808 | ||
61407f6d VS |
1809 | /* disable left/right clock distribution */ |
1810 | if (pipe != PIPE_B) { | |
1811 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1812 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1813 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1814 | } else { | |
1815 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1816 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1817 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1818 | } | |
1819 | ||
d752048d | 1820 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1821 | } |
1822 | ||
e4607fcf CML |
1823 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1824 | struct intel_digital_port *dport) | |
89b667f8 JB |
1825 | { |
1826 | u32 port_mask; | |
00fc31b7 | 1827 | int dpll_reg; |
89b667f8 | 1828 | |
e4607fcf CML |
1829 | switch (dport->port) { |
1830 | case PORT_B: | |
89b667f8 | 1831 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1832 | dpll_reg = DPLL(0); |
e4607fcf CML |
1833 | break; |
1834 | case PORT_C: | |
89b667f8 | 1835 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1836 | dpll_reg = DPLL(0); |
1837 | break; | |
1838 | case PORT_D: | |
1839 | port_mask = DPLL_PORTD_READY_MASK; | |
1840 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1841 | break; |
1842 | default: | |
1843 | BUG(); | |
1844 | } | |
89b667f8 | 1845 | |
00fc31b7 | 1846 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1847 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1848 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1849 | } |
1850 | ||
b14b1055 DV |
1851 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1852 | { | |
1853 | struct drm_device *dev = crtc->base.dev; | |
1854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1855 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1856 | ||
be19f0ff CW |
1857 | if (WARN_ON(pll == NULL)) |
1858 | return; | |
1859 | ||
3e369b76 | 1860 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1861 | if (pll->active == 0) { |
1862 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1863 | WARN_ON(pll->on); | |
1864 | assert_shared_dpll_disabled(dev_priv, pll); | |
1865 | ||
1866 | pll->mode_set(dev_priv, pll); | |
1867 | } | |
1868 | } | |
1869 | ||
92f2584a | 1870 | /** |
85b3894f | 1871 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1872 | * @dev_priv: i915 private structure |
1873 | * @pipe: pipe PLL to enable | |
1874 | * | |
1875 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1876 | * drives the transcoder clock. | |
1877 | */ | |
85b3894f | 1878 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1879 | { |
3d13ef2e DL |
1880 | struct drm_device *dev = crtc->base.dev; |
1881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1882 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1883 | |
87a875bb | 1884 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1885 | return; |
1886 | ||
3e369b76 | 1887 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1888 | return; |
ee7b9f93 | 1889 | |
74dd6928 | 1890 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1891 | pll->name, pll->active, pll->on, |
e2b78267 | 1892 | crtc->base.base.id); |
92f2584a | 1893 | |
cdbd2316 DV |
1894 | if (pll->active++) { |
1895 | WARN_ON(!pll->on); | |
e9d6944e | 1896 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1897 | return; |
1898 | } | |
f4a091c7 | 1899 | WARN_ON(pll->on); |
ee7b9f93 | 1900 | |
bd2bb1b9 PZ |
1901 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1902 | ||
46edb027 | 1903 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1904 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1905 | pll->on = true; |
92f2584a JB |
1906 | } |
1907 | ||
f6daaec2 | 1908 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1909 | { |
3d13ef2e DL |
1910 | struct drm_device *dev = crtc->base.dev; |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1912 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1913 | |
92f2584a | 1914 | /* PCH only available on ILK+ */ |
3d13ef2e | 1915 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1916 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1917 | return; |
92f2584a | 1918 | |
3e369b76 | 1919 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1920 | return; |
7a419866 | 1921 | |
46edb027 DV |
1922 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1923 | pll->name, pll->active, pll->on, | |
e2b78267 | 1924 | crtc->base.base.id); |
7a419866 | 1925 | |
48da64a8 | 1926 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1927 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1928 | return; |
1929 | } | |
1930 | ||
e9d6944e | 1931 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1932 | WARN_ON(!pll->on); |
cdbd2316 | 1933 | if (--pll->active) |
7a419866 | 1934 | return; |
ee7b9f93 | 1935 | |
46edb027 | 1936 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1937 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1938 | pll->on = false; |
bd2bb1b9 PZ |
1939 | |
1940 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1941 | } |
1942 | ||
b8a4f404 PZ |
1943 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1944 | enum pipe pipe) | |
040484af | 1945 | { |
23670b32 | 1946 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1947 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1949 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1950 | |
1951 | /* PCH only available on ILK+ */ | |
55522f37 | 1952 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1953 | |
1954 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1955 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1956 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1957 | |
1958 | /* FDI must be feeding us bits for PCH ports */ | |
1959 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1960 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1961 | ||
23670b32 DV |
1962 | if (HAS_PCH_CPT(dev)) { |
1963 | /* Workaround: Set the timing override bit before enabling the | |
1964 | * pch transcoder. */ | |
1965 | reg = TRANS_CHICKEN2(pipe); | |
1966 | val = I915_READ(reg); | |
1967 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1968 | I915_WRITE(reg, val); | |
59c859d6 | 1969 | } |
23670b32 | 1970 | |
ab9412ba | 1971 | reg = PCH_TRANSCONF(pipe); |
040484af | 1972 | val = I915_READ(reg); |
5f7f726d | 1973 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1974 | |
1975 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1976 | /* | |
1977 | * make the BPC in transcoder be consistent with | |
1978 | * that in pipeconf reg. | |
1979 | */ | |
dfd07d72 DV |
1980 | val &= ~PIPECONF_BPC_MASK; |
1981 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1982 | } |
5f7f726d PZ |
1983 | |
1984 | val &= ~TRANS_INTERLACE_MASK; | |
1985 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1986 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1987 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1988 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1989 | else | |
1990 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1991 | else |
1992 | val |= TRANS_PROGRESSIVE; | |
1993 | ||
040484af JB |
1994 | I915_WRITE(reg, val | TRANS_ENABLE); |
1995 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1996 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1997 | } |
1998 | ||
8fb033d7 | 1999 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2000 | enum transcoder cpu_transcoder) |
040484af | 2001 | { |
8fb033d7 | 2002 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2003 | |
2004 | /* PCH only available on ILK+ */ | |
55522f37 | 2005 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2006 | |
8fb033d7 | 2007 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2008 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2009 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2010 | |
223a6fdf PZ |
2011 | /* Workaround: set timing override bit. */ |
2012 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2013 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2014 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2015 | ||
25f3ef11 | 2016 | val = TRANS_ENABLE; |
937bb610 | 2017 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2018 | |
9a76b1c6 PZ |
2019 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2020 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2021 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2022 | else |
2023 | val |= TRANS_PROGRESSIVE; | |
2024 | ||
ab9412ba DV |
2025 | I915_WRITE(LPT_TRANSCONF, val); |
2026 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2027 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2028 | } |
2029 | ||
b8a4f404 PZ |
2030 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2031 | enum pipe pipe) | |
040484af | 2032 | { |
23670b32 DV |
2033 | struct drm_device *dev = dev_priv->dev; |
2034 | uint32_t reg, val; | |
040484af JB |
2035 | |
2036 | /* FDI relies on the transcoder */ | |
2037 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2038 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2039 | ||
291906f1 JB |
2040 | /* Ports must be off as well */ |
2041 | assert_pch_ports_disabled(dev_priv, pipe); | |
2042 | ||
ab9412ba | 2043 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2044 | val = I915_READ(reg); |
2045 | val &= ~TRANS_ENABLE; | |
2046 | I915_WRITE(reg, val); | |
2047 | /* wait for PCH transcoder off, transcoder state */ | |
2048 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2049 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2050 | |
2051 | if (!HAS_PCH_IBX(dev)) { | |
2052 | /* Workaround: Clear the timing override chicken bit again. */ | |
2053 | reg = TRANS_CHICKEN2(pipe); | |
2054 | val = I915_READ(reg); | |
2055 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2056 | I915_WRITE(reg, val); | |
2057 | } | |
040484af JB |
2058 | } |
2059 | ||
ab4d966c | 2060 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2061 | { |
8fb033d7 PZ |
2062 | u32 val; |
2063 | ||
ab9412ba | 2064 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2065 | val &= ~TRANS_ENABLE; |
ab9412ba | 2066 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2067 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2068 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2069 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2070 | |
2071 | /* Workaround: clear timing override bit. */ | |
2072 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2073 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2074 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2075 | } |
2076 | ||
b24e7179 | 2077 | /** |
309cfea8 | 2078 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2079 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2080 | * |
0372264a | 2081 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2082 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2083 | */ |
e1fdc473 | 2084 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2085 | { |
0372264a PZ |
2086 | struct drm_device *dev = crtc->base.dev; |
2087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2088 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2089 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2090 | pipe); | |
1a240d4d | 2091 | enum pipe pch_transcoder; |
b24e7179 JB |
2092 | int reg; |
2093 | u32 val; | |
2094 | ||
58c6eaa2 | 2095 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2096 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2097 | assert_sprites_disabled(dev_priv, pipe); |
2098 | ||
681e5811 | 2099 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2100 | pch_transcoder = TRANSCODER_A; |
2101 | else | |
2102 | pch_transcoder = pipe; | |
2103 | ||
b24e7179 JB |
2104 | /* |
2105 | * A pipe without a PLL won't actually be able to drive bits from | |
2106 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2107 | * need the check. | |
2108 | */ | |
2109 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2110 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2111 | assert_dsi_pll_enabled(dev_priv); |
2112 | else | |
2113 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2114 | else { |
6e3c9717 | 2115 | if (crtc->config->has_pch_encoder) { |
040484af | 2116 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2117 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2118 | assert_fdi_tx_pll_enabled(dev_priv, |
2119 | (enum pipe) cpu_transcoder); | |
040484af JB |
2120 | } |
2121 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2122 | } | |
b24e7179 | 2123 | |
702e7a56 | 2124 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2125 | val = I915_READ(reg); |
7ad25d48 | 2126 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2127 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2128 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2129 | return; |
7ad25d48 | 2130 | } |
00d70b15 CW |
2131 | |
2132 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2133 | POSTING_READ(reg); |
b24e7179 JB |
2134 | } |
2135 | ||
2136 | /** | |
309cfea8 | 2137 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2138 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2139 | * |
575f7ab7 VS |
2140 | * Disable the pipe of @crtc, making sure that various hardware |
2141 | * specific requirements are met, if applicable, e.g. plane | |
2142 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2143 | * |
2144 | * Will wait until the pipe has shut down before returning. | |
2145 | */ | |
575f7ab7 | 2146 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2147 | { |
575f7ab7 | 2148 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2149 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2150 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2151 | int reg; |
2152 | u32 val; | |
2153 | ||
2154 | /* | |
2155 | * Make sure planes won't keep trying to pump pixels to us, | |
2156 | * or we might hang the display. | |
2157 | */ | |
2158 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2159 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2160 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2161 | |
702e7a56 | 2162 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2163 | val = I915_READ(reg); |
00d70b15 CW |
2164 | if ((val & PIPECONF_ENABLE) == 0) |
2165 | return; | |
2166 | ||
67adc644 VS |
2167 | /* |
2168 | * Double wide has implications for planes | |
2169 | * so best keep it disabled when not needed. | |
2170 | */ | |
6e3c9717 | 2171 | if (crtc->config->double_wide) |
67adc644 VS |
2172 | val &= ~PIPECONF_DOUBLE_WIDE; |
2173 | ||
2174 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2175 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2176 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2177 | val &= ~PIPECONF_ENABLE; |
2178 | ||
2179 | I915_WRITE(reg, val); | |
2180 | if ((val & PIPECONF_ENABLE) == 0) | |
2181 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2182 | } |
2183 | ||
d74362c9 KP |
2184 | /* |
2185 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2186 | * trigger in order to latch. The display address reg provides this. | |
2187 | */ | |
1dba99f4 VS |
2188 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2189 | enum plane plane) | |
d74362c9 | 2190 | { |
3d13ef2e DL |
2191 | struct drm_device *dev = dev_priv->dev; |
2192 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2193 | |
2194 | I915_WRITE(reg, I915_READ(reg)); | |
2195 | POSTING_READ(reg); | |
d74362c9 KP |
2196 | } |
2197 | ||
b24e7179 | 2198 | /** |
262ca2b0 | 2199 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2200 | * @plane: plane to be enabled |
2201 | * @crtc: crtc for the plane | |
b24e7179 | 2202 | * |
fdd508a6 | 2203 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2204 | */ |
fdd508a6 VS |
2205 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2206 | struct drm_crtc *crtc) | |
b24e7179 | 2207 | { |
fdd508a6 VS |
2208 | struct drm_device *dev = plane->dev; |
2209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2210 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2211 | |
2212 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2213 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2214 | |
98ec7739 VS |
2215 | if (intel_crtc->primary_enabled) |
2216 | return; | |
0037f71c | 2217 | |
4c445e0e | 2218 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2219 | |
fdd508a6 VS |
2220 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2221 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2222 | |
2223 | /* | |
2224 | * BDW signals flip done immediately if the plane | |
2225 | * is disabled, even if the plane enable is already | |
2226 | * armed to occur at the next vblank :( | |
2227 | */ | |
2228 | if (IS_BROADWELL(dev)) | |
2229 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2230 | } |
2231 | ||
b24e7179 | 2232 | /** |
262ca2b0 | 2233 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2234 | * @plane: plane to be disabled |
2235 | * @crtc: crtc for the plane | |
b24e7179 | 2236 | * |
fdd508a6 | 2237 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2238 | */ |
fdd508a6 VS |
2239 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2240 | struct drm_crtc *crtc) | |
b24e7179 | 2241 | { |
fdd508a6 VS |
2242 | struct drm_device *dev = plane->dev; |
2243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2244 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2245 | ||
32b7eeec MR |
2246 | if (WARN_ON(!intel_crtc->active)) |
2247 | return; | |
b24e7179 | 2248 | |
98ec7739 VS |
2249 | if (!intel_crtc->primary_enabled) |
2250 | return; | |
0037f71c | 2251 | |
4c445e0e | 2252 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2253 | |
fdd508a6 VS |
2254 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2255 | crtc->x, crtc->y); | |
b24e7179 JB |
2256 | } |
2257 | ||
693db184 CW |
2258 | static bool need_vtd_wa(struct drm_device *dev) |
2259 | { | |
2260 | #ifdef CONFIG_INTEL_IOMMU | |
2261 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2262 | return true; | |
2263 | #endif | |
2264 | return false; | |
2265 | } | |
2266 | ||
50470bb0 | 2267 | unsigned int |
6761dd31 TU |
2268 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2269 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2270 | { |
6761dd31 TU |
2271 | unsigned int tile_height; |
2272 | uint32_t pixel_bytes; | |
a57ce0b2 | 2273 | |
b5d0e9bf DL |
2274 | switch (fb_format_modifier) { |
2275 | case DRM_FORMAT_MOD_NONE: | |
2276 | tile_height = 1; | |
2277 | break; | |
2278 | case I915_FORMAT_MOD_X_TILED: | |
2279 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2280 | break; | |
2281 | case I915_FORMAT_MOD_Y_TILED: | |
2282 | tile_height = 32; | |
2283 | break; | |
2284 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2285 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2286 | switch (pixel_bytes) { | |
b5d0e9bf | 2287 | default: |
6761dd31 | 2288 | case 1: |
b5d0e9bf DL |
2289 | tile_height = 64; |
2290 | break; | |
6761dd31 TU |
2291 | case 2: |
2292 | case 4: | |
b5d0e9bf DL |
2293 | tile_height = 32; |
2294 | break; | |
6761dd31 | 2295 | case 8: |
b5d0e9bf DL |
2296 | tile_height = 16; |
2297 | break; | |
6761dd31 | 2298 | case 16: |
b5d0e9bf DL |
2299 | WARN_ONCE(1, |
2300 | "128-bit pixels are not supported for display!"); | |
2301 | tile_height = 16; | |
2302 | break; | |
2303 | } | |
2304 | break; | |
2305 | default: | |
2306 | MISSING_CASE(fb_format_modifier); | |
2307 | tile_height = 1; | |
2308 | break; | |
2309 | } | |
091df6cb | 2310 | |
6761dd31 TU |
2311 | return tile_height; |
2312 | } | |
2313 | ||
2314 | unsigned int | |
2315 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2316 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2317 | { | |
2318 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2319 | fb_format_modifier)); | |
a57ce0b2 JB |
2320 | } |
2321 | ||
f64b98cd TU |
2322 | static int |
2323 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2324 | const struct drm_plane_state *plane_state) | |
2325 | { | |
50470bb0 | 2326 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2327 | |
f64b98cd TU |
2328 | *view = i915_ggtt_view_normal; |
2329 | ||
50470bb0 TU |
2330 | if (!plane_state) |
2331 | return 0; | |
2332 | ||
121920fa | 2333 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2334 | return 0; |
2335 | ||
9abc4648 | 2336 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2337 | |
2338 | info->height = fb->height; | |
2339 | info->pixel_format = fb->pixel_format; | |
2340 | info->pitch = fb->pitches[0]; | |
2341 | info->fb_modifier = fb->modifier[0]; | |
2342 | ||
f64b98cd TU |
2343 | return 0; |
2344 | } | |
2345 | ||
127bd2ac | 2346 | int |
850c4cdc TU |
2347 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2348 | struct drm_framebuffer *fb, | |
82bc3b2d | 2349 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2350 | struct intel_engine_cs *pipelined) |
6b95a207 | 2351 | { |
850c4cdc | 2352 | struct drm_device *dev = fb->dev; |
ce453d81 | 2353 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2354 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2355 | struct i915_ggtt_view view; |
6b95a207 KH |
2356 | u32 alignment; |
2357 | int ret; | |
2358 | ||
ebcdd39e MR |
2359 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2360 | ||
7b911adc TU |
2361 | switch (fb->modifier[0]) { |
2362 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2363 | if (INTEL_INFO(dev)->gen >= 9) |
2364 | alignment = 256 * 1024; | |
2365 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2366 | alignment = 128 * 1024; |
a6c45cf0 | 2367 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2368 | alignment = 4 * 1024; |
2369 | else | |
2370 | alignment = 64 * 1024; | |
6b95a207 | 2371 | break; |
7b911adc | 2372 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2373 | if (INTEL_INFO(dev)->gen >= 9) |
2374 | alignment = 256 * 1024; | |
2375 | else { | |
2376 | /* pin() will align the object as required by fence */ | |
2377 | alignment = 0; | |
2378 | } | |
6b95a207 | 2379 | break; |
7b911adc | 2380 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2381 | case I915_FORMAT_MOD_Yf_TILED: |
2382 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2383 | "Y tiling bo slipped through, driver bug!\n")) | |
2384 | return -EINVAL; | |
2385 | alignment = 1 * 1024 * 1024; | |
2386 | break; | |
6b95a207 | 2387 | default: |
7b911adc TU |
2388 | MISSING_CASE(fb->modifier[0]); |
2389 | return -EINVAL; | |
6b95a207 KH |
2390 | } |
2391 | ||
f64b98cd TU |
2392 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2393 | if (ret) | |
2394 | return ret; | |
2395 | ||
693db184 CW |
2396 | /* Note that the w/a also requires 64 PTE of padding following the |
2397 | * bo. We currently fill all unused PTE with the shadow page and so | |
2398 | * we should always have valid PTE following the scanout preventing | |
2399 | * the VT-d warning. | |
2400 | */ | |
2401 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2402 | alignment = 256 * 1024; | |
2403 | ||
d6dd6843 PZ |
2404 | /* |
2405 | * Global gtt pte registers are special registers which actually forward | |
2406 | * writes to a chunk of system memory. Which means that there is no risk | |
2407 | * that the register values disappear as soon as we call | |
2408 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2409 | * pin/unpin/fence and not more. | |
2410 | */ | |
2411 | intel_runtime_pm_get(dev_priv); | |
2412 | ||
ce453d81 | 2413 | dev_priv->mm.interruptible = false; |
e6617330 | 2414 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2415 | &view); |
48b956c5 | 2416 | if (ret) |
ce453d81 | 2417 | goto err_interruptible; |
6b95a207 KH |
2418 | |
2419 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2420 | * fence, whereas 965+ only requires a fence if using | |
2421 | * framebuffer compression. For simplicity, we always install | |
2422 | * a fence as the cost is not that onerous. | |
2423 | */ | |
06d98131 | 2424 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2425 | if (ret) |
2426 | goto err_unpin; | |
1690e1eb | 2427 | |
9a5a53b3 | 2428 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2429 | |
ce453d81 | 2430 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2431 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2432 | return 0; |
48b956c5 CW |
2433 | |
2434 | err_unpin: | |
f64b98cd | 2435 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2436 | err_interruptible: |
2437 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2438 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2439 | return ret; |
6b95a207 KH |
2440 | } |
2441 | ||
82bc3b2d TU |
2442 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2443 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2444 | { |
82bc3b2d | 2445 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2446 | struct i915_ggtt_view view; |
2447 | int ret; | |
82bc3b2d | 2448 | |
ebcdd39e MR |
2449 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2450 | ||
f64b98cd TU |
2451 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2452 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2453 | ||
1690e1eb | 2454 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2455 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2456 | } |
2457 | ||
c2c75131 DV |
2458 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2459 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2460 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2461 | unsigned int tiling_mode, | |
2462 | unsigned int cpp, | |
2463 | unsigned int pitch) | |
c2c75131 | 2464 | { |
bc752862 CW |
2465 | if (tiling_mode != I915_TILING_NONE) { |
2466 | unsigned int tile_rows, tiles; | |
c2c75131 | 2467 | |
bc752862 CW |
2468 | tile_rows = *y / 8; |
2469 | *y %= 8; | |
c2c75131 | 2470 | |
bc752862 CW |
2471 | tiles = *x / (512/cpp); |
2472 | *x %= 512/cpp; | |
2473 | ||
2474 | return tile_rows * pitch * 8 + tiles * 4096; | |
2475 | } else { | |
2476 | unsigned int offset; | |
2477 | ||
2478 | offset = *y * pitch + *x * cpp; | |
2479 | *y = 0; | |
2480 | *x = (offset & 4095) / cpp; | |
2481 | return offset & -4096; | |
2482 | } | |
c2c75131 DV |
2483 | } |
2484 | ||
b35d63fa | 2485 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2486 | { |
2487 | switch (format) { | |
2488 | case DISPPLANE_8BPP: | |
2489 | return DRM_FORMAT_C8; | |
2490 | case DISPPLANE_BGRX555: | |
2491 | return DRM_FORMAT_XRGB1555; | |
2492 | case DISPPLANE_BGRX565: | |
2493 | return DRM_FORMAT_RGB565; | |
2494 | default: | |
2495 | case DISPPLANE_BGRX888: | |
2496 | return DRM_FORMAT_XRGB8888; | |
2497 | case DISPPLANE_RGBX888: | |
2498 | return DRM_FORMAT_XBGR8888; | |
2499 | case DISPPLANE_BGRX101010: | |
2500 | return DRM_FORMAT_XRGB2101010; | |
2501 | case DISPPLANE_RGBX101010: | |
2502 | return DRM_FORMAT_XBGR2101010; | |
2503 | } | |
2504 | } | |
2505 | ||
bc8d7dff DL |
2506 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2507 | { | |
2508 | switch (format) { | |
2509 | case PLANE_CTL_FORMAT_RGB_565: | |
2510 | return DRM_FORMAT_RGB565; | |
2511 | default: | |
2512 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2513 | if (rgb_order) { | |
2514 | if (alpha) | |
2515 | return DRM_FORMAT_ABGR8888; | |
2516 | else | |
2517 | return DRM_FORMAT_XBGR8888; | |
2518 | } else { | |
2519 | if (alpha) | |
2520 | return DRM_FORMAT_ARGB8888; | |
2521 | else | |
2522 | return DRM_FORMAT_XRGB8888; | |
2523 | } | |
2524 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2525 | if (rgb_order) | |
2526 | return DRM_FORMAT_XBGR2101010; | |
2527 | else | |
2528 | return DRM_FORMAT_XRGB2101010; | |
2529 | } | |
2530 | } | |
2531 | ||
5724dbd1 | 2532 | static bool |
f6936e29 DV |
2533 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2534 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2535 | { |
2536 | struct drm_device *dev = crtc->base.dev; | |
2537 | struct drm_i915_gem_object *obj = NULL; | |
2538 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2539 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2540 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2541 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2542 | PAGE_SIZE); | |
2543 | ||
2544 | size_aligned -= base_aligned; | |
46f297fb | 2545 | |
ff2652ea CW |
2546 | if (plane_config->size == 0) |
2547 | return false; | |
2548 | ||
f37b5c2b DV |
2549 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2550 | base_aligned, | |
2551 | base_aligned, | |
2552 | size_aligned); | |
46f297fb | 2553 | if (!obj) |
484b41dd | 2554 | return false; |
46f297fb | 2555 | |
49af449b DL |
2556 | obj->tiling_mode = plane_config->tiling; |
2557 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2558 | obj->stride = fb->pitches[0]; |
46f297fb | 2559 | |
6bf129df DL |
2560 | mode_cmd.pixel_format = fb->pixel_format; |
2561 | mode_cmd.width = fb->width; | |
2562 | mode_cmd.height = fb->height; | |
2563 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2564 | mode_cmd.modifier[0] = fb->modifier[0]; |
2565 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2566 | |
2567 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2568 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2569 | &mode_cmd, obj)) { |
46f297fb JB |
2570 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2571 | goto out_unref_obj; | |
2572 | } | |
46f297fb | 2573 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2574 | |
f6936e29 | 2575 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2576 | return true; |
46f297fb JB |
2577 | |
2578 | out_unref_obj: | |
2579 | drm_gem_object_unreference(&obj->base); | |
2580 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2581 | return false; |
2582 | } | |
2583 | ||
afd65eb4 MR |
2584 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2585 | static void | |
2586 | update_state_fb(struct drm_plane *plane) | |
2587 | { | |
2588 | if (plane->fb == plane->state->fb) | |
2589 | return; | |
2590 | ||
2591 | if (plane->state->fb) | |
2592 | drm_framebuffer_unreference(plane->state->fb); | |
2593 | plane->state->fb = plane->fb; | |
2594 | if (plane->state->fb) | |
2595 | drm_framebuffer_reference(plane->state->fb); | |
2596 | } | |
2597 | ||
5724dbd1 | 2598 | static void |
f6936e29 DV |
2599 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2600 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2601 | { |
2602 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2603 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2604 | struct drm_crtc *c; |
2605 | struct intel_crtc *i; | |
2ff8fde1 | 2606 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2607 | struct drm_plane *primary = intel_crtc->base.primary; |
2608 | struct drm_framebuffer *fb; | |
484b41dd | 2609 | |
2d14030b | 2610 | if (!plane_config->fb) |
484b41dd JB |
2611 | return; |
2612 | ||
f6936e29 | 2613 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2614 | fb = &plane_config->fb->base; |
2615 | goto valid_fb; | |
f55548b5 | 2616 | } |
484b41dd | 2617 | |
2d14030b | 2618 | kfree(plane_config->fb); |
484b41dd JB |
2619 | |
2620 | /* | |
2621 | * Failed to alloc the obj, check to see if we should share | |
2622 | * an fb with another CRTC instead | |
2623 | */ | |
70e1e0ec | 2624 | for_each_crtc(dev, c) { |
484b41dd JB |
2625 | i = to_intel_crtc(c); |
2626 | ||
2627 | if (c == &intel_crtc->base) | |
2628 | continue; | |
2629 | ||
2ff8fde1 MR |
2630 | if (!i->active) |
2631 | continue; | |
2632 | ||
88595ac9 DV |
2633 | fb = c->primary->fb; |
2634 | if (!fb) | |
484b41dd JB |
2635 | continue; |
2636 | ||
88595ac9 | 2637 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2638 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2639 | drm_framebuffer_reference(fb); |
2640 | goto valid_fb; | |
484b41dd JB |
2641 | } |
2642 | } | |
88595ac9 DV |
2643 | |
2644 | return; | |
2645 | ||
2646 | valid_fb: | |
2647 | obj = intel_fb_obj(fb); | |
2648 | if (obj->tiling_mode != I915_TILING_NONE) | |
2649 | dev_priv->preserve_bios_swizzle = true; | |
2650 | ||
2651 | primary->fb = fb; | |
2652 | primary->state->crtc = &intel_crtc->base; | |
2653 | primary->crtc = &intel_crtc->base; | |
2654 | update_state_fb(primary); | |
2655 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2656 | } |
2657 | ||
29b9bde6 DV |
2658 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2659 | struct drm_framebuffer *fb, | |
2660 | int x, int y) | |
81255565 JB |
2661 | { |
2662 | struct drm_device *dev = crtc->dev; | |
2663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2665 | struct drm_i915_gem_object *obj; |
81255565 | 2666 | int plane = intel_crtc->plane; |
e506a0c6 | 2667 | unsigned long linear_offset; |
81255565 | 2668 | u32 dspcntr; |
f45651ba | 2669 | u32 reg = DSPCNTR(plane); |
48404c1e | 2670 | int pixel_size; |
f45651ba | 2671 | |
fdd508a6 VS |
2672 | if (!intel_crtc->primary_enabled) { |
2673 | I915_WRITE(reg, 0); | |
2674 | if (INTEL_INFO(dev)->gen >= 4) | |
2675 | I915_WRITE(DSPSURF(plane), 0); | |
2676 | else | |
2677 | I915_WRITE(DSPADDR(plane), 0); | |
2678 | POSTING_READ(reg); | |
2679 | return; | |
2680 | } | |
2681 | ||
c9ba6fad VS |
2682 | obj = intel_fb_obj(fb); |
2683 | if (WARN_ON(obj == NULL)) | |
2684 | return; | |
2685 | ||
2686 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2687 | ||
f45651ba VS |
2688 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2689 | ||
fdd508a6 | 2690 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2691 | |
2692 | if (INTEL_INFO(dev)->gen < 4) { | |
2693 | if (intel_crtc->pipe == PIPE_B) | |
2694 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2695 | ||
2696 | /* pipesrc and dspsize control the size that is scaled from, | |
2697 | * which should always be the user's requested size. | |
2698 | */ | |
2699 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2700 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2701 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2702 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2703 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2704 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2705 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2706 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2707 | I915_WRITE(PRIMPOS(plane), 0); |
2708 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2709 | } |
81255565 | 2710 | |
57779d06 VS |
2711 | switch (fb->pixel_format) { |
2712 | case DRM_FORMAT_C8: | |
81255565 JB |
2713 | dspcntr |= DISPPLANE_8BPP; |
2714 | break; | |
57779d06 VS |
2715 | case DRM_FORMAT_XRGB1555: |
2716 | case DRM_FORMAT_ARGB1555: | |
2717 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2718 | break; |
57779d06 VS |
2719 | case DRM_FORMAT_RGB565: |
2720 | dspcntr |= DISPPLANE_BGRX565; | |
2721 | break; | |
2722 | case DRM_FORMAT_XRGB8888: | |
2723 | case DRM_FORMAT_ARGB8888: | |
2724 | dspcntr |= DISPPLANE_BGRX888; | |
2725 | break; | |
2726 | case DRM_FORMAT_XBGR8888: | |
2727 | case DRM_FORMAT_ABGR8888: | |
2728 | dspcntr |= DISPPLANE_RGBX888; | |
2729 | break; | |
2730 | case DRM_FORMAT_XRGB2101010: | |
2731 | case DRM_FORMAT_ARGB2101010: | |
2732 | dspcntr |= DISPPLANE_BGRX101010; | |
2733 | break; | |
2734 | case DRM_FORMAT_XBGR2101010: | |
2735 | case DRM_FORMAT_ABGR2101010: | |
2736 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2737 | break; |
2738 | default: | |
baba133a | 2739 | BUG(); |
81255565 | 2740 | } |
57779d06 | 2741 | |
f45651ba VS |
2742 | if (INTEL_INFO(dev)->gen >= 4 && |
2743 | obj->tiling_mode != I915_TILING_NONE) | |
2744 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2745 | |
de1aa629 VS |
2746 | if (IS_G4X(dev)) |
2747 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2748 | ||
b9897127 | 2749 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2750 | |
c2c75131 DV |
2751 | if (INTEL_INFO(dev)->gen >= 4) { |
2752 | intel_crtc->dspaddr_offset = | |
bc752862 | 2753 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2754 | pixel_size, |
bc752862 | 2755 | fb->pitches[0]); |
c2c75131 DV |
2756 | linear_offset -= intel_crtc->dspaddr_offset; |
2757 | } else { | |
e506a0c6 | 2758 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2759 | } |
e506a0c6 | 2760 | |
8e7d688b | 2761 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2762 | dspcntr |= DISPPLANE_ROTATE_180; |
2763 | ||
6e3c9717 ACO |
2764 | x += (intel_crtc->config->pipe_src_w - 1); |
2765 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2766 | |
2767 | /* Finding the last pixel of the last line of the display | |
2768 | data and adding to linear_offset*/ | |
2769 | linear_offset += | |
6e3c9717 ACO |
2770 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2771 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2772 | } |
2773 | ||
2774 | I915_WRITE(reg, dspcntr); | |
2775 | ||
01f2c773 | 2776 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2777 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2778 | I915_WRITE(DSPSURF(plane), |
2779 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2780 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2781 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2782 | } else |
f343c5f6 | 2783 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2784 | POSTING_READ(reg); |
17638cd6 JB |
2785 | } |
2786 | ||
29b9bde6 DV |
2787 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2788 | struct drm_framebuffer *fb, | |
2789 | int x, int y) | |
17638cd6 JB |
2790 | { |
2791 | struct drm_device *dev = crtc->dev; | |
2792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2793 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2794 | struct drm_i915_gem_object *obj; |
17638cd6 | 2795 | int plane = intel_crtc->plane; |
e506a0c6 | 2796 | unsigned long linear_offset; |
17638cd6 | 2797 | u32 dspcntr; |
f45651ba | 2798 | u32 reg = DSPCNTR(plane); |
48404c1e | 2799 | int pixel_size; |
f45651ba | 2800 | |
fdd508a6 VS |
2801 | if (!intel_crtc->primary_enabled) { |
2802 | I915_WRITE(reg, 0); | |
2803 | I915_WRITE(DSPSURF(plane), 0); | |
2804 | POSTING_READ(reg); | |
2805 | return; | |
2806 | } | |
2807 | ||
c9ba6fad VS |
2808 | obj = intel_fb_obj(fb); |
2809 | if (WARN_ON(obj == NULL)) | |
2810 | return; | |
2811 | ||
2812 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2813 | ||
f45651ba VS |
2814 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2815 | ||
fdd508a6 | 2816 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2817 | |
2818 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2819 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2820 | |
57779d06 VS |
2821 | switch (fb->pixel_format) { |
2822 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2823 | dspcntr |= DISPPLANE_8BPP; |
2824 | break; | |
57779d06 VS |
2825 | case DRM_FORMAT_RGB565: |
2826 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2827 | break; |
57779d06 VS |
2828 | case DRM_FORMAT_XRGB8888: |
2829 | case DRM_FORMAT_ARGB8888: | |
2830 | dspcntr |= DISPPLANE_BGRX888; | |
2831 | break; | |
2832 | case DRM_FORMAT_XBGR8888: | |
2833 | case DRM_FORMAT_ABGR8888: | |
2834 | dspcntr |= DISPPLANE_RGBX888; | |
2835 | break; | |
2836 | case DRM_FORMAT_XRGB2101010: | |
2837 | case DRM_FORMAT_ARGB2101010: | |
2838 | dspcntr |= DISPPLANE_BGRX101010; | |
2839 | break; | |
2840 | case DRM_FORMAT_XBGR2101010: | |
2841 | case DRM_FORMAT_ABGR2101010: | |
2842 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2843 | break; |
2844 | default: | |
baba133a | 2845 | BUG(); |
17638cd6 JB |
2846 | } |
2847 | ||
2848 | if (obj->tiling_mode != I915_TILING_NONE) | |
2849 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2850 | |
f45651ba | 2851 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2852 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2853 | |
b9897127 | 2854 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2855 | intel_crtc->dspaddr_offset = |
bc752862 | 2856 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2857 | pixel_size, |
bc752862 | 2858 | fb->pitches[0]); |
c2c75131 | 2859 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2860 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2861 | dspcntr |= DISPPLANE_ROTATE_180; |
2862 | ||
2863 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2864 | x += (intel_crtc->config->pipe_src_w - 1); |
2865 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2866 | |
2867 | /* Finding the last pixel of the last line of the display | |
2868 | data and adding to linear_offset*/ | |
2869 | linear_offset += | |
6e3c9717 ACO |
2870 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2871 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2872 | } |
2873 | } | |
2874 | ||
2875 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2876 | |
01f2c773 | 2877 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2878 | I915_WRITE(DSPSURF(plane), |
2879 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2880 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2881 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2882 | } else { | |
2883 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2884 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2885 | } | |
17638cd6 | 2886 | POSTING_READ(reg); |
17638cd6 JB |
2887 | } |
2888 | ||
b321803d DL |
2889 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2890 | uint32_t pixel_format) | |
2891 | { | |
2892 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2893 | ||
2894 | /* | |
2895 | * The stride is either expressed as a multiple of 64 bytes | |
2896 | * chunks for linear buffers or in number of tiles for tiled | |
2897 | * buffers. | |
2898 | */ | |
2899 | switch (fb_modifier) { | |
2900 | case DRM_FORMAT_MOD_NONE: | |
2901 | return 64; | |
2902 | case I915_FORMAT_MOD_X_TILED: | |
2903 | if (INTEL_INFO(dev)->gen == 2) | |
2904 | return 128; | |
2905 | return 512; | |
2906 | case I915_FORMAT_MOD_Y_TILED: | |
2907 | /* No need to check for old gens and Y tiling since this is | |
2908 | * about the display engine and those will be blocked before | |
2909 | * we get here. | |
2910 | */ | |
2911 | return 128; | |
2912 | case I915_FORMAT_MOD_Yf_TILED: | |
2913 | if (bits_per_pixel == 8) | |
2914 | return 64; | |
2915 | else | |
2916 | return 128; | |
2917 | default: | |
2918 | MISSING_CASE(fb_modifier); | |
2919 | return 64; | |
2920 | } | |
2921 | } | |
2922 | ||
121920fa TU |
2923 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2924 | struct drm_i915_gem_object *obj) | |
2925 | { | |
9abc4648 | 2926 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2927 | |
2928 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2929 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2930 | |
2931 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2932 | } | |
2933 | ||
70d21f0e DL |
2934 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2935 | struct drm_framebuffer *fb, | |
2936 | int x, int y) | |
2937 | { | |
2938 | struct drm_device *dev = crtc->dev; | |
2939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2941 | struct drm_i915_gem_object *obj; |
2942 | int pipe = intel_crtc->pipe; | |
3b7a5119 SJ |
2943 | u32 plane_ctl, stride_div, stride; |
2944 | u32 tile_height, plane_offset, plane_size; | |
2945 | unsigned int rotation; | |
2946 | int x_offset, y_offset; | |
121920fa | 2947 | unsigned long surf_addr; |
3b7a5119 | 2948 | struct drm_plane *plane; |
70d21f0e DL |
2949 | |
2950 | if (!intel_crtc->primary_enabled) { | |
2951 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2952 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2953 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2954 | return; | |
2955 | } | |
2956 | ||
2957 | plane_ctl = PLANE_CTL_ENABLE | | |
2958 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2959 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2960 | ||
2961 | switch (fb->pixel_format) { | |
2962 | case DRM_FORMAT_RGB565: | |
2963 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2964 | break; | |
2965 | case DRM_FORMAT_XRGB8888: | |
2966 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2967 | break; | |
f75fb42a JN |
2968 | case DRM_FORMAT_ARGB8888: |
2969 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2970 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2971 | break; | |
70d21f0e DL |
2972 | case DRM_FORMAT_XBGR8888: |
2973 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2974 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2975 | break; | |
f75fb42a JN |
2976 | case DRM_FORMAT_ABGR8888: |
2977 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2978 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2979 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2980 | break; | |
70d21f0e DL |
2981 | case DRM_FORMAT_XRGB2101010: |
2982 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2983 | break; | |
2984 | case DRM_FORMAT_XBGR2101010: | |
2985 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2986 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2987 | break; | |
2988 | default: | |
2989 | BUG(); | |
2990 | } | |
2991 | ||
30af77c4 DV |
2992 | switch (fb->modifier[0]) { |
2993 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 2994 | break; |
30af77c4 | 2995 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 2996 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
2997 | break; |
2998 | case I915_FORMAT_MOD_Y_TILED: | |
2999 | plane_ctl |= PLANE_CTL_TILED_Y; | |
3000 | break; | |
3001 | case I915_FORMAT_MOD_Yf_TILED: | |
3002 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
3003 | break; |
3004 | default: | |
b321803d | 3005 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
3006 | } |
3007 | ||
3008 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3b7a5119 SJ |
3009 | |
3010 | plane = crtc->primary; | |
3011 | rotation = plane->state->rotation; | |
3012 | switch (rotation) { | |
3013 | case BIT(DRM_ROTATE_90): | |
3014 | plane_ctl |= PLANE_CTL_ROTATE_90; | |
3015 | break; | |
3016 | ||
3017 | case BIT(DRM_ROTATE_180): | |
1447dde0 | 3018 | plane_ctl |= PLANE_CTL_ROTATE_180; |
3b7a5119 SJ |
3019 | break; |
3020 | ||
3021 | case BIT(DRM_ROTATE_270): | |
3022 | plane_ctl |= PLANE_CTL_ROTATE_270; | |
3023 | break; | |
3024 | } | |
70d21f0e | 3025 | |
b321803d DL |
3026 | obj = intel_fb_obj(fb); |
3027 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3028 | fb->pixel_format); | |
3b7a5119 SJ |
3029 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3030 | ||
3031 | if (intel_rotation_90_or_270(rotation)) { | |
3032 | /* stride = Surface height in tiles */ | |
3033 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, | |
3034 | fb->modifier[0]); | |
3035 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
3036 | x_offset = stride * tile_height - y - (plane->state->src_h >> 16); | |
3037 | y_offset = x; | |
3038 | plane_size = ((plane->state->src_w >> 16) - 1) << 16 | | |
3039 | ((plane->state->src_h >> 16) - 1); | |
3040 | } else { | |
3041 | stride = fb->pitches[0] / stride_div; | |
3042 | x_offset = x; | |
3043 | y_offset = y; | |
3044 | plane_size = ((plane->state->src_h >> 16) - 1) << 16 | | |
3045 | ((plane->state->src_w >> 16) - 1); | |
3046 | } | |
3047 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3048 | |
70d21f0e | 3049 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
70d21f0e | 3050 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
3b7a5119 SJ |
3051 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3052 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3053 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
121920fa | 3054 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3055 | |
3056 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3057 | } | |
3058 | ||
17638cd6 JB |
3059 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3060 | static int | |
3061 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3062 | int x, int y, enum mode_set_atomic state) | |
3063 | { | |
3064 | struct drm_device *dev = crtc->dev; | |
3065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3066 | |
6b8e6ed0 CW |
3067 | if (dev_priv->display.disable_fbc) |
3068 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3069 | |
29b9bde6 DV |
3070 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3071 | ||
3072 | return 0; | |
81255565 JB |
3073 | } |
3074 | ||
7514747d | 3075 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3076 | { |
96a02917 VS |
3077 | struct drm_crtc *crtc; |
3078 | ||
70e1e0ec | 3079 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3081 | enum plane plane = intel_crtc->plane; | |
3082 | ||
3083 | intel_prepare_page_flip(dev, plane); | |
3084 | intel_finish_page_flip_plane(dev, plane); | |
3085 | } | |
7514747d VS |
3086 | } |
3087 | ||
3088 | static void intel_update_primary_planes(struct drm_device *dev) | |
3089 | { | |
3090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3091 | struct drm_crtc *crtc; | |
96a02917 | 3092 | |
70e1e0ec | 3093 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3095 | ||
51fd371b | 3096 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3097 | /* |
3098 | * FIXME: Once we have proper support for primary planes (and | |
3099 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3100 | * a NULL crtc->primary->fb. |
947fdaad | 3101 | */ |
f4510a27 | 3102 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3103 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3104 | crtc->primary->fb, |
262ca2b0 MR |
3105 | crtc->x, |
3106 | crtc->y); | |
51fd371b | 3107 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3108 | } |
3109 | } | |
3110 | ||
7514747d VS |
3111 | void intel_prepare_reset(struct drm_device *dev) |
3112 | { | |
f98ce92f VS |
3113 | struct drm_i915_private *dev_priv = to_i915(dev); |
3114 | struct intel_crtc *crtc; | |
3115 | ||
7514747d VS |
3116 | /* no reset support for gen2 */ |
3117 | if (IS_GEN2(dev)) | |
3118 | return; | |
3119 | ||
3120 | /* reset doesn't touch the display */ | |
3121 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3122 | return; | |
3123 | ||
3124 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3125 | |
3126 | /* | |
3127 | * Disabling the crtcs gracefully seems nicer. Also the | |
3128 | * g33 docs say we should at least disable all the planes. | |
3129 | */ | |
3130 | for_each_intel_crtc(dev, crtc) { | |
3131 | if (crtc->active) | |
3132 | dev_priv->display.crtc_disable(&crtc->base); | |
3133 | } | |
7514747d VS |
3134 | } |
3135 | ||
3136 | void intel_finish_reset(struct drm_device *dev) | |
3137 | { | |
3138 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3139 | ||
3140 | /* | |
3141 | * Flips in the rings will be nuked by the reset, | |
3142 | * so complete all pending flips so that user space | |
3143 | * will get its events and not get stuck. | |
3144 | */ | |
3145 | intel_complete_page_flips(dev); | |
3146 | ||
3147 | /* no reset support for gen2 */ | |
3148 | if (IS_GEN2(dev)) | |
3149 | return; | |
3150 | ||
3151 | /* reset doesn't touch the display */ | |
3152 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3153 | /* | |
3154 | * Flips in the rings have been nuked by the reset, | |
3155 | * so update the base address of all primary | |
3156 | * planes to the the last fb to make sure we're | |
3157 | * showing the correct fb after a reset. | |
3158 | */ | |
3159 | intel_update_primary_planes(dev); | |
3160 | return; | |
3161 | } | |
3162 | ||
3163 | /* | |
3164 | * The display has been reset as well, | |
3165 | * so need a full re-initialization. | |
3166 | */ | |
3167 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3168 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3169 | ||
3170 | intel_modeset_init_hw(dev); | |
3171 | ||
3172 | spin_lock_irq(&dev_priv->irq_lock); | |
3173 | if (dev_priv->display.hpd_irq_setup) | |
3174 | dev_priv->display.hpd_irq_setup(dev); | |
3175 | spin_unlock_irq(&dev_priv->irq_lock); | |
3176 | ||
3177 | intel_modeset_setup_hw_state(dev, true); | |
3178 | ||
3179 | intel_hpd_init(dev_priv); | |
3180 | ||
3181 | drm_modeset_unlock_all(dev); | |
3182 | } | |
3183 | ||
14667a4b CW |
3184 | static int |
3185 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3186 | { | |
2ff8fde1 | 3187 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3188 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3189 | bool was_interruptible = dev_priv->mm.interruptible; | |
3190 | int ret; | |
3191 | ||
14667a4b CW |
3192 | /* Big Hammer, we also need to ensure that any pending |
3193 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3194 | * current scanout is retired before unpinning the old | |
3195 | * framebuffer. | |
3196 | * | |
3197 | * This should only fail upon a hung GPU, in which case we | |
3198 | * can safely continue. | |
3199 | */ | |
3200 | dev_priv->mm.interruptible = false; | |
3201 | ret = i915_gem_object_finish_gpu(obj); | |
3202 | dev_priv->mm.interruptible = was_interruptible; | |
3203 | ||
3204 | return ret; | |
3205 | } | |
3206 | ||
7d5e3799 CW |
3207 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3208 | { | |
3209 | struct drm_device *dev = crtc->dev; | |
3210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3211 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3212 | bool pending; |
3213 | ||
3214 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3215 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3216 | return false; | |
3217 | ||
5e2d7afc | 3218 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3219 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3220 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3221 | |
3222 | return pending; | |
3223 | } | |
3224 | ||
e30e8f75 GP |
3225 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3226 | { | |
3227 | struct drm_device *dev = crtc->base.dev; | |
3228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3229 | const struct drm_display_mode *adjusted_mode; | |
3230 | ||
3231 | if (!i915.fastboot) | |
3232 | return; | |
3233 | ||
3234 | /* | |
3235 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3236 | * that in compute_mode_changes we check the native mode (not the pfit | |
3237 | * mode) to see if we can flip rather than do a full mode set. In the | |
3238 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3239 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3240 | * sized surface. | |
3241 | * | |
3242 | * To fix this properly, we need to hoist the checks up into | |
3243 | * compute_mode_changes (or above), check the actual pfit state and | |
3244 | * whether the platform allows pfit disable with pipe active, and only | |
3245 | * then update the pipesrc and pfit state, even on the flip path. | |
3246 | */ | |
3247 | ||
6e3c9717 | 3248 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3249 | |
3250 | I915_WRITE(PIPESRC(crtc->pipe), | |
3251 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3252 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3253 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3254 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3255 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3256 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3257 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3258 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3259 | } | |
6e3c9717 ACO |
3260 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3261 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3262 | } |
3263 | ||
5e84e1a4 ZW |
3264 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3265 | { | |
3266 | struct drm_device *dev = crtc->dev; | |
3267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3269 | int pipe = intel_crtc->pipe; | |
3270 | u32 reg, temp; | |
3271 | ||
3272 | /* enable normal train */ | |
3273 | reg = FDI_TX_CTL(pipe); | |
3274 | temp = I915_READ(reg); | |
61e499bf | 3275 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3276 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3277 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3278 | } else { |
3279 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3280 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3281 | } |
5e84e1a4 ZW |
3282 | I915_WRITE(reg, temp); |
3283 | ||
3284 | reg = FDI_RX_CTL(pipe); | |
3285 | temp = I915_READ(reg); | |
3286 | if (HAS_PCH_CPT(dev)) { | |
3287 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3288 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3289 | } else { | |
3290 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3291 | temp |= FDI_LINK_TRAIN_NONE; | |
3292 | } | |
3293 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3294 | ||
3295 | /* wait one idle pattern time */ | |
3296 | POSTING_READ(reg); | |
3297 | udelay(1000); | |
357555c0 JB |
3298 | |
3299 | /* IVB wants error correction enabled */ | |
3300 | if (IS_IVYBRIDGE(dev)) | |
3301 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3302 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3303 | } |
3304 | ||
8db9d77b ZW |
3305 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3306 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3307 | { | |
3308 | struct drm_device *dev = crtc->dev; | |
3309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3311 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3312 | u32 reg, temp, tries; |
8db9d77b | 3313 | |
1c8562f6 | 3314 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3315 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3316 | |
e1a44743 AJ |
3317 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3318 | for train result */ | |
5eddb70b CW |
3319 | reg = FDI_RX_IMR(pipe); |
3320 | temp = I915_READ(reg); | |
e1a44743 AJ |
3321 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3322 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3323 | I915_WRITE(reg, temp); |
3324 | I915_READ(reg); | |
e1a44743 AJ |
3325 | udelay(150); |
3326 | ||
8db9d77b | 3327 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3328 | reg = FDI_TX_CTL(pipe); |
3329 | temp = I915_READ(reg); | |
627eb5a3 | 3330 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3331 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3332 | temp &= ~FDI_LINK_TRAIN_NONE; |
3333 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3334 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3335 | |
5eddb70b CW |
3336 | reg = FDI_RX_CTL(pipe); |
3337 | temp = I915_READ(reg); | |
8db9d77b ZW |
3338 | temp &= ~FDI_LINK_TRAIN_NONE; |
3339 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3340 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3341 | ||
3342 | POSTING_READ(reg); | |
8db9d77b ZW |
3343 | udelay(150); |
3344 | ||
5b2adf89 | 3345 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3346 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3347 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3348 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3349 | |
5eddb70b | 3350 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3351 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3352 | temp = I915_READ(reg); |
8db9d77b ZW |
3353 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3354 | ||
3355 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3356 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3357 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3358 | break; |
3359 | } | |
8db9d77b | 3360 | } |
e1a44743 | 3361 | if (tries == 5) |
5eddb70b | 3362 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3363 | |
3364 | /* Train 2 */ | |
5eddb70b CW |
3365 | reg = FDI_TX_CTL(pipe); |
3366 | temp = I915_READ(reg); | |
8db9d77b ZW |
3367 | temp &= ~FDI_LINK_TRAIN_NONE; |
3368 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3369 | I915_WRITE(reg, temp); |
8db9d77b | 3370 | |
5eddb70b CW |
3371 | reg = FDI_RX_CTL(pipe); |
3372 | temp = I915_READ(reg); | |
8db9d77b ZW |
3373 | temp &= ~FDI_LINK_TRAIN_NONE; |
3374 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3375 | I915_WRITE(reg, temp); |
8db9d77b | 3376 | |
5eddb70b CW |
3377 | POSTING_READ(reg); |
3378 | udelay(150); | |
8db9d77b | 3379 | |
5eddb70b | 3380 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3381 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3382 | temp = I915_READ(reg); |
8db9d77b ZW |
3383 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3384 | ||
3385 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3386 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3387 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3388 | break; | |
3389 | } | |
8db9d77b | 3390 | } |
e1a44743 | 3391 | if (tries == 5) |
5eddb70b | 3392 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3393 | |
3394 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3395 | |
8db9d77b ZW |
3396 | } |
3397 | ||
0206e353 | 3398 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3399 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3400 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3401 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3402 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3403 | }; | |
3404 | ||
3405 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3406 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3407 | { | |
3408 | struct drm_device *dev = crtc->dev; | |
3409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3411 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3412 | u32 reg, temp, i, retry; |
8db9d77b | 3413 | |
e1a44743 AJ |
3414 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3415 | for train result */ | |
5eddb70b CW |
3416 | reg = FDI_RX_IMR(pipe); |
3417 | temp = I915_READ(reg); | |
e1a44743 AJ |
3418 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3419 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3420 | I915_WRITE(reg, temp); |
3421 | ||
3422 | POSTING_READ(reg); | |
e1a44743 AJ |
3423 | udelay(150); |
3424 | ||
8db9d77b | 3425 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3426 | reg = FDI_TX_CTL(pipe); |
3427 | temp = I915_READ(reg); | |
627eb5a3 | 3428 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3429 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3430 | temp &= ~FDI_LINK_TRAIN_NONE; |
3431 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3432 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3433 | /* SNB-B */ | |
3434 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3435 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3436 | |
d74cf324 DV |
3437 | I915_WRITE(FDI_RX_MISC(pipe), |
3438 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3439 | ||
5eddb70b CW |
3440 | reg = FDI_RX_CTL(pipe); |
3441 | temp = I915_READ(reg); | |
8db9d77b ZW |
3442 | if (HAS_PCH_CPT(dev)) { |
3443 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3444 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3445 | } else { | |
3446 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3447 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3448 | } | |
5eddb70b CW |
3449 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3450 | ||
3451 | POSTING_READ(reg); | |
8db9d77b ZW |
3452 | udelay(150); |
3453 | ||
0206e353 | 3454 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3455 | reg = FDI_TX_CTL(pipe); |
3456 | temp = I915_READ(reg); | |
8db9d77b ZW |
3457 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3458 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3459 | I915_WRITE(reg, temp); |
3460 | ||
3461 | POSTING_READ(reg); | |
8db9d77b ZW |
3462 | udelay(500); |
3463 | ||
fa37d39e SP |
3464 | for (retry = 0; retry < 5; retry++) { |
3465 | reg = FDI_RX_IIR(pipe); | |
3466 | temp = I915_READ(reg); | |
3467 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3468 | if (temp & FDI_RX_BIT_LOCK) { | |
3469 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3470 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3471 | break; | |
3472 | } | |
3473 | udelay(50); | |
8db9d77b | 3474 | } |
fa37d39e SP |
3475 | if (retry < 5) |
3476 | break; | |
8db9d77b ZW |
3477 | } |
3478 | if (i == 4) | |
5eddb70b | 3479 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3480 | |
3481 | /* Train 2 */ | |
5eddb70b CW |
3482 | reg = FDI_TX_CTL(pipe); |
3483 | temp = I915_READ(reg); | |
8db9d77b ZW |
3484 | temp &= ~FDI_LINK_TRAIN_NONE; |
3485 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3486 | if (IS_GEN6(dev)) { | |
3487 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3488 | /* SNB-B */ | |
3489 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3490 | } | |
5eddb70b | 3491 | I915_WRITE(reg, temp); |
8db9d77b | 3492 | |
5eddb70b CW |
3493 | reg = FDI_RX_CTL(pipe); |
3494 | temp = I915_READ(reg); | |
8db9d77b ZW |
3495 | if (HAS_PCH_CPT(dev)) { |
3496 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3497 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3498 | } else { | |
3499 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3500 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3501 | } | |
5eddb70b CW |
3502 | I915_WRITE(reg, temp); |
3503 | ||
3504 | POSTING_READ(reg); | |
8db9d77b ZW |
3505 | udelay(150); |
3506 | ||
0206e353 | 3507 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3508 | reg = FDI_TX_CTL(pipe); |
3509 | temp = I915_READ(reg); | |
8db9d77b ZW |
3510 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3511 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3512 | I915_WRITE(reg, temp); |
3513 | ||
3514 | POSTING_READ(reg); | |
8db9d77b ZW |
3515 | udelay(500); |
3516 | ||
fa37d39e SP |
3517 | for (retry = 0; retry < 5; retry++) { |
3518 | reg = FDI_RX_IIR(pipe); | |
3519 | temp = I915_READ(reg); | |
3520 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3521 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3522 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3523 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3524 | break; | |
3525 | } | |
3526 | udelay(50); | |
8db9d77b | 3527 | } |
fa37d39e SP |
3528 | if (retry < 5) |
3529 | break; | |
8db9d77b ZW |
3530 | } |
3531 | if (i == 4) | |
5eddb70b | 3532 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3533 | |
3534 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3535 | } | |
3536 | ||
357555c0 JB |
3537 | /* Manual link training for Ivy Bridge A0 parts */ |
3538 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3539 | { | |
3540 | struct drm_device *dev = crtc->dev; | |
3541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3542 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3543 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3544 | u32 reg, temp, i, j; |
357555c0 JB |
3545 | |
3546 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3547 | for train result */ | |
3548 | reg = FDI_RX_IMR(pipe); | |
3549 | temp = I915_READ(reg); | |
3550 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3551 | temp &= ~FDI_RX_BIT_LOCK; | |
3552 | I915_WRITE(reg, temp); | |
3553 | ||
3554 | POSTING_READ(reg); | |
3555 | udelay(150); | |
3556 | ||
01a415fd DV |
3557 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3558 | I915_READ(FDI_RX_IIR(pipe))); | |
3559 | ||
139ccd3f JB |
3560 | /* Try each vswing and preemphasis setting twice before moving on */ |
3561 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3562 | /* disable first in case we need to retry */ | |
3563 | reg = FDI_TX_CTL(pipe); | |
3564 | temp = I915_READ(reg); | |
3565 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3566 | temp &= ~FDI_TX_ENABLE; | |
3567 | I915_WRITE(reg, temp); | |
357555c0 | 3568 | |
139ccd3f JB |
3569 | reg = FDI_RX_CTL(pipe); |
3570 | temp = I915_READ(reg); | |
3571 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3572 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3573 | temp &= ~FDI_RX_ENABLE; | |
3574 | I915_WRITE(reg, temp); | |
357555c0 | 3575 | |
139ccd3f | 3576 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3577 | reg = FDI_TX_CTL(pipe); |
3578 | temp = I915_READ(reg); | |
139ccd3f | 3579 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3580 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3581 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3582 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3583 | temp |= snb_b_fdi_train_param[j/2]; |
3584 | temp |= FDI_COMPOSITE_SYNC; | |
3585 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3586 | |
139ccd3f JB |
3587 | I915_WRITE(FDI_RX_MISC(pipe), |
3588 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3589 | |
139ccd3f | 3590 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3591 | temp = I915_READ(reg); |
139ccd3f JB |
3592 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3593 | temp |= FDI_COMPOSITE_SYNC; | |
3594 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3595 | |
139ccd3f JB |
3596 | POSTING_READ(reg); |
3597 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3598 | |
139ccd3f JB |
3599 | for (i = 0; i < 4; i++) { |
3600 | reg = FDI_RX_IIR(pipe); | |
3601 | temp = I915_READ(reg); | |
3602 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3603 | |
139ccd3f JB |
3604 | if (temp & FDI_RX_BIT_LOCK || |
3605 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3606 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3607 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3608 | i); | |
3609 | break; | |
3610 | } | |
3611 | udelay(1); /* should be 0.5us */ | |
3612 | } | |
3613 | if (i == 4) { | |
3614 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3615 | continue; | |
3616 | } | |
357555c0 | 3617 | |
139ccd3f | 3618 | /* Train 2 */ |
357555c0 JB |
3619 | reg = FDI_TX_CTL(pipe); |
3620 | temp = I915_READ(reg); | |
139ccd3f JB |
3621 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3622 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3623 | I915_WRITE(reg, temp); | |
3624 | ||
3625 | reg = FDI_RX_CTL(pipe); | |
3626 | temp = I915_READ(reg); | |
3627 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3628 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3629 | I915_WRITE(reg, temp); |
3630 | ||
3631 | POSTING_READ(reg); | |
139ccd3f | 3632 | udelay(2); /* should be 1.5us */ |
357555c0 | 3633 | |
139ccd3f JB |
3634 | for (i = 0; i < 4; i++) { |
3635 | reg = FDI_RX_IIR(pipe); | |
3636 | temp = I915_READ(reg); | |
3637 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3638 | |
139ccd3f JB |
3639 | if (temp & FDI_RX_SYMBOL_LOCK || |
3640 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3641 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3642 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3643 | i); | |
3644 | goto train_done; | |
3645 | } | |
3646 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3647 | } |
139ccd3f JB |
3648 | if (i == 4) |
3649 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3650 | } |
357555c0 | 3651 | |
139ccd3f | 3652 | train_done: |
357555c0 JB |
3653 | DRM_DEBUG_KMS("FDI train done.\n"); |
3654 | } | |
3655 | ||
88cefb6c | 3656 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3657 | { |
88cefb6c | 3658 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3659 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3660 | int pipe = intel_crtc->pipe; |
5eddb70b | 3661 | u32 reg, temp; |
79e53945 | 3662 | |
c64e311e | 3663 | |
c98e9dcf | 3664 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3665 | reg = FDI_RX_CTL(pipe); |
3666 | temp = I915_READ(reg); | |
627eb5a3 | 3667 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3668 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3669 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3670 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3671 | ||
3672 | POSTING_READ(reg); | |
c98e9dcf JB |
3673 | udelay(200); |
3674 | ||
3675 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3676 | temp = I915_READ(reg); |
3677 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3678 | ||
3679 | POSTING_READ(reg); | |
c98e9dcf JB |
3680 | udelay(200); |
3681 | ||
20749730 PZ |
3682 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3683 | reg = FDI_TX_CTL(pipe); | |
3684 | temp = I915_READ(reg); | |
3685 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3686 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3687 | |
20749730 PZ |
3688 | POSTING_READ(reg); |
3689 | udelay(100); | |
6be4a607 | 3690 | } |
0e23b99d JB |
3691 | } |
3692 | ||
88cefb6c DV |
3693 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3694 | { | |
3695 | struct drm_device *dev = intel_crtc->base.dev; | |
3696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3697 | int pipe = intel_crtc->pipe; | |
3698 | u32 reg, temp; | |
3699 | ||
3700 | /* Switch from PCDclk to Rawclk */ | |
3701 | reg = FDI_RX_CTL(pipe); | |
3702 | temp = I915_READ(reg); | |
3703 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3704 | ||
3705 | /* Disable CPU FDI TX PLL */ | |
3706 | reg = FDI_TX_CTL(pipe); | |
3707 | temp = I915_READ(reg); | |
3708 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3709 | ||
3710 | POSTING_READ(reg); | |
3711 | udelay(100); | |
3712 | ||
3713 | reg = FDI_RX_CTL(pipe); | |
3714 | temp = I915_READ(reg); | |
3715 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3716 | ||
3717 | /* Wait for the clocks to turn off. */ | |
3718 | POSTING_READ(reg); | |
3719 | udelay(100); | |
3720 | } | |
3721 | ||
0fc932b8 JB |
3722 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3723 | { | |
3724 | struct drm_device *dev = crtc->dev; | |
3725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3726 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3727 | int pipe = intel_crtc->pipe; | |
3728 | u32 reg, temp; | |
3729 | ||
3730 | /* disable CPU FDI tx and PCH FDI rx */ | |
3731 | reg = FDI_TX_CTL(pipe); | |
3732 | temp = I915_READ(reg); | |
3733 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3734 | POSTING_READ(reg); | |
3735 | ||
3736 | reg = FDI_RX_CTL(pipe); | |
3737 | temp = I915_READ(reg); | |
3738 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3739 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3740 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3741 | ||
3742 | POSTING_READ(reg); | |
3743 | udelay(100); | |
3744 | ||
3745 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3746 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3747 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3748 | |
3749 | /* still set train pattern 1 */ | |
3750 | reg = FDI_TX_CTL(pipe); | |
3751 | temp = I915_READ(reg); | |
3752 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3753 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3754 | I915_WRITE(reg, temp); | |
3755 | ||
3756 | reg = FDI_RX_CTL(pipe); | |
3757 | temp = I915_READ(reg); | |
3758 | if (HAS_PCH_CPT(dev)) { | |
3759 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3760 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3761 | } else { | |
3762 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3763 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3764 | } | |
3765 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3766 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3767 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3768 | I915_WRITE(reg, temp); |
3769 | ||
3770 | POSTING_READ(reg); | |
3771 | udelay(100); | |
3772 | } | |
3773 | ||
5dce5b93 CW |
3774 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3775 | { | |
3776 | struct intel_crtc *crtc; | |
3777 | ||
3778 | /* Note that we don't need to be called with mode_config.lock here | |
3779 | * as our list of CRTC objects is static for the lifetime of the | |
3780 | * device and so cannot disappear as we iterate. Similarly, we can | |
3781 | * happily treat the predicates as racy, atomic checks as userspace | |
3782 | * cannot claim and pin a new fb without at least acquring the | |
3783 | * struct_mutex and so serialising with us. | |
3784 | */ | |
d3fcc808 | 3785 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3786 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3787 | continue; | |
3788 | ||
3789 | if (crtc->unpin_work) | |
3790 | intel_wait_for_vblank(dev, crtc->pipe); | |
3791 | ||
3792 | return true; | |
3793 | } | |
3794 | ||
3795 | return false; | |
3796 | } | |
3797 | ||
d6bbafa1 CW |
3798 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3799 | { | |
3800 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3801 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3802 | ||
3803 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3804 | smp_rmb(); | |
3805 | intel_crtc->unpin_work = NULL; | |
3806 | ||
3807 | if (work->event) | |
3808 | drm_send_vblank_event(intel_crtc->base.dev, | |
3809 | intel_crtc->pipe, | |
3810 | work->event); | |
3811 | ||
3812 | drm_crtc_vblank_put(&intel_crtc->base); | |
3813 | ||
3814 | wake_up_all(&dev_priv->pending_flip_queue); | |
3815 | queue_work(dev_priv->wq, &work->work); | |
3816 | ||
3817 | trace_i915_flip_complete(intel_crtc->plane, | |
3818 | work->pending_flip_obj); | |
3819 | } | |
3820 | ||
46a55d30 | 3821 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3822 | { |
0f91128d | 3823 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3824 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3825 | |
2c10d571 | 3826 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3827 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3828 | !intel_crtc_has_pending_flip(crtc), | |
3829 | 60*HZ) == 0)) { | |
3830 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3831 | |
5e2d7afc | 3832 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3833 | if (intel_crtc->unpin_work) { |
3834 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3835 | page_flip_completed(intel_crtc); | |
3836 | } | |
5e2d7afc | 3837 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3838 | } |
5bb61643 | 3839 | |
975d568a CW |
3840 | if (crtc->primary->fb) { |
3841 | mutex_lock(&dev->struct_mutex); | |
3842 | intel_finish_fb(crtc->primary->fb); | |
3843 | mutex_unlock(&dev->struct_mutex); | |
3844 | } | |
e6c3a2a6 CW |
3845 | } |
3846 | ||
e615efe4 ED |
3847 | /* Program iCLKIP clock to the desired frequency */ |
3848 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3849 | { | |
3850 | struct drm_device *dev = crtc->dev; | |
3851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3852 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3853 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3854 | u32 temp; | |
3855 | ||
09153000 DV |
3856 | mutex_lock(&dev_priv->dpio_lock); |
3857 | ||
e615efe4 ED |
3858 | /* It is necessary to ungate the pixclk gate prior to programming |
3859 | * the divisors, and gate it back when it is done. | |
3860 | */ | |
3861 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3862 | ||
3863 | /* Disable SSCCTL */ | |
3864 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3865 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3866 | SBI_SSCCTL_DISABLE, | |
3867 | SBI_ICLK); | |
e615efe4 ED |
3868 | |
3869 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3870 | if (clock == 20000) { |
e615efe4 ED |
3871 | auxdiv = 1; |
3872 | divsel = 0x41; | |
3873 | phaseinc = 0x20; | |
3874 | } else { | |
3875 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3876 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3877 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3878 | * convert the virtual clock precision to KHz here for higher |
3879 | * precision. | |
3880 | */ | |
3881 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3882 | u32 iclk_pi_range = 64; | |
3883 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3884 | ||
12d7ceed | 3885 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3886 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3887 | pi_value = desired_divisor % iclk_pi_range; | |
3888 | ||
3889 | auxdiv = 0; | |
3890 | divsel = msb_divisor_value - 2; | |
3891 | phaseinc = pi_value; | |
3892 | } | |
3893 | ||
3894 | /* This should not happen with any sane values */ | |
3895 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3896 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3897 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3898 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3899 | ||
3900 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3901 | clock, |
e615efe4 ED |
3902 | auxdiv, |
3903 | divsel, | |
3904 | phasedir, | |
3905 | phaseinc); | |
3906 | ||
3907 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3908 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3909 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3910 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3911 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3912 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3913 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3914 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3915 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3916 | |
3917 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3918 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3919 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3920 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3921 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3922 | |
3923 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3924 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3925 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3926 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3927 | |
3928 | /* Wait for initialization time */ | |
3929 | udelay(24); | |
3930 | ||
3931 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3932 | |
3933 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3934 | } |
3935 | ||
275f01b2 DV |
3936 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3937 | enum pipe pch_transcoder) | |
3938 | { | |
3939 | struct drm_device *dev = crtc->base.dev; | |
3940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3941 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3942 | |
3943 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3944 | I915_READ(HTOTAL(cpu_transcoder))); | |
3945 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3946 | I915_READ(HBLANK(cpu_transcoder))); | |
3947 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3948 | I915_READ(HSYNC(cpu_transcoder))); | |
3949 | ||
3950 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3951 | I915_READ(VTOTAL(cpu_transcoder))); | |
3952 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3953 | I915_READ(VBLANK(cpu_transcoder))); | |
3954 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3955 | I915_READ(VSYNC(cpu_transcoder))); | |
3956 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3957 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3958 | } | |
3959 | ||
003632d9 | 3960 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
3961 | { |
3962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3963 | uint32_t temp; | |
3964 | ||
3965 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3966 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3967 | return; |
3968 | ||
3969 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3970 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3971 | ||
003632d9 ACO |
3972 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
3973 | if (enable) | |
3974 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3975 | ||
3976 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
3977 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3978 | POSTING_READ(SOUTH_CHICKEN1); | |
3979 | } | |
3980 | ||
3981 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3982 | { | |
3983 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
3984 | |
3985 | switch (intel_crtc->pipe) { | |
3986 | case PIPE_A: | |
3987 | break; | |
3988 | case PIPE_B: | |
6e3c9717 | 3989 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 3990 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 3991 | else |
003632d9 | 3992 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3993 | |
3994 | break; | |
3995 | case PIPE_C: | |
003632d9 | 3996 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3997 | |
3998 | break; | |
3999 | default: | |
4000 | BUG(); | |
4001 | } | |
4002 | } | |
4003 | ||
f67a559d JB |
4004 | /* |
4005 | * Enable PCH resources required for PCH ports: | |
4006 | * - PCH PLLs | |
4007 | * - FDI training & RX/TX | |
4008 | * - update transcoder timings | |
4009 | * - DP transcoding bits | |
4010 | * - transcoder | |
4011 | */ | |
4012 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4013 | { |
4014 | struct drm_device *dev = crtc->dev; | |
4015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4016 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4017 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4018 | u32 reg, temp; |
2c07245f | 4019 | |
ab9412ba | 4020 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4021 | |
1fbc0d78 DV |
4022 | if (IS_IVYBRIDGE(dev)) |
4023 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4024 | ||
cd986abb DV |
4025 | /* Write the TU size bits before fdi link training, so that error |
4026 | * detection works. */ | |
4027 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4028 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4029 | ||
c98e9dcf | 4030 | /* For PCH output, training FDI link */ |
674cf967 | 4031 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4032 | |
3ad8a208 DV |
4033 | /* We need to program the right clock selection before writing the pixel |
4034 | * mutliplier into the DPLL. */ | |
303b81e0 | 4035 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4036 | u32 sel; |
4b645f14 | 4037 | |
c98e9dcf | 4038 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4039 | temp |= TRANS_DPLL_ENABLE(pipe); |
4040 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4041 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4042 | temp |= sel; |
4043 | else | |
4044 | temp &= ~sel; | |
c98e9dcf | 4045 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4046 | } |
5eddb70b | 4047 | |
3ad8a208 DV |
4048 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4049 | * transcoder, and we actually should do this to not upset any PCH | |
4050 | * transcoder that already use the clock when we share it. | |
4051 | * | |
4052 | * Note that enable_shared_dpll tries to do the right thing, but | |
4053 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4054 | * the right LVDS enable sequence. */ | |
85b3894f | 4055 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4056 | |
d9b6cb56 JB |
4057 | /* set transcoder timing, panel must allow it */ |
4058 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4059 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4060 | |
303b81e0 | 4061 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4062 | |
c98e9dcf | 4063 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4064 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4065 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4066 | reg = TRANS_DP_CTL(pipe); |
4067 | temp = I915_READ(reg); | |
4068 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4069 | TRANS_DP_SYNC_MASK | |
4070 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4071 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4072 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4073 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4074 | |
4075 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4076 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4077 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4078 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4079 | |
4080 | switch (intel_trans_dp_port_sel(crtc)) { | |
4081 | case PCH_DP_B: | |
5eddb70b | 4082 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4083 | break; |
4084 | case PCH_DP_C: | |
5eddb70b | 4085 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4086 | break; |
4087 | case PCH_DP_D: | |
5eddb70b | 4088 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4089 | break; |
4090 | default: | |
e95d41e1 | 4091 | BUG(); |
32f9d658 | 4092 | } |
2c07245f | 4093 | |
5eddb70b | 4094 | I915_WRITE(reg, temp); |
6be4a607 | 4095 | } |
b52eb4dc | 4096 | |
b8a4f404 | 4097 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4098 | } |
4099 | ||
1507e5bd PZ |
4100 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4101 | { | |
4102 | struct drm_device *dev = crtc->dev; | |
4103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4104 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4105 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4106 | |
ab9412ba | 4107 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4108 | |
8c52b5e8 | 4109 | lpt_program_iclkip(crtc); |
1507e5bd | 4110 | |
0540e488 | 4111 | /* Set transcoder timing. */ |
275f01b2 | 4112 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4113 | |
937bb610 | 4114 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4115 | } |
4116 | ||
716c2e55 | 4117 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4118 | { |
e2b78267 | 4119 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4120 | |
4121 | if (pll == NULL) | |
4122 | return; | |
4123 | ||
3e369b76 | 4124 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4125 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4126 | return; |
4127 | } | |
4128 | ||
3e369b76 ACO |
4129 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4130 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4131 | WARN_ON(pll->on); |
4132 | WARN_ON(pll->active); | |
4133 | } | |
4134 | ||
6e3c9717 | 4135 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4136 | } |
4137 | ||
190f68c5 ACO |
4138 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4139 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4140 | { |
e2b78267 | 4141 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4142 | struct intel_shared_dpll *pll; |
e2b78267 | 4143 | enum intel_dpll_id i; |
ee7b9f93 | 4144 | |
98b6bd99 DV |
4145 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4146 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4147 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4148 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4149 | |
46edb027 DV |
4150 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4151 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4152 | |
8bd31e67 | 4153 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4154 | |
98b6bd99 DV |
4155 | goto found; |
4156 | } | |
4157 | ||
e72f9fbf DV |
4158 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4159 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4160 | |
4161 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4162 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4163 | continue; |
4164 | ||
190f68c5 | 4165 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4166 | &pll->new_config->hw_state, |
4167 | sizeof(pll->new_config->hw_state)) == 0) { | |
4168 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4169 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4170 | pll->new_config->crtc_mask, |
4171 | pll->active); | |
ee7b9f93 JB |
4172 | goto found; |
4173 | } | |
4174 | } | |
4175 | ||
4176 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4177 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4178 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4179 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4180 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4181 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4182 | goto found; |
4183 | } | |
4184 | } | |
4185 | ||
4186 | return NULL; | |
4187 | ||
4188 | found: | |
8bd31e67 | 4189 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4190 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4191 | |
190f68c5 | 4192 | crtc_state->shared_dpll = i; |
46edb027 DV |
4193 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4194 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4195 | |
8bd31e67 | 4196 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4197 | |
ee7b9f93 JB |
4198 | return pll; |
4199 | } | |
4200 | ||
8bd31e67 ACO |
4201 | /** |
4202 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4203 | * @dev_priv: DRM device | |
4204 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4205 | * | |
4206 | * Starts a new PLL staged config, copying the current config but | |
4207 | * releasing the references of pipes specified in clear_pipes. | |
4208 | */ | |
4209 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4210 | unsigned clear_pipes) | |
4211 | { | |
4212 | struct intel_shared_dpll *pll; | |
4213 | enum intel_dpll_id i; | |
4214 | ||
4215 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4216 | pll = &dev_priv->shared_dplls[i]; | |
4217 | ||
4218 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4219 | GFP_KERNEL); | |
4220 | if (!pll->new_config) | |
4221 | goto cleanup; | |
4222 | ||
4223 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4224 | } | |
4225 | ||
4226 | return 0; | |
4227 | ||
4228 | cleanup: | |
4229 | while (--i >= 0) { | |
4230 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4231 | kfree(pll->new_config); |
8bd31e67 ACO |
4232 | pll->new_config = NULL; |
4233 | } | |
4234 | ||
4235 | return -ENOMEM; | |
4236 | } | |
4237 | ||
4238 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4239 | { | |
4240 | struct intel_shared_dpll *pll; | |
4241 | enum intel_dpll_id i; | |
4242 | ||
4243 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4244 | pll = &dev_priv->shared_dplls[i]; | |
4245 | ||
4246 | WARN_ON(pll->new_config == &pll->config); | |
4247 | ||
4248 | pll->config = *pll->new_config; | |
4249 | kfree(pll->new_config); | |
4250 | pll->new_config = NULL; | |
4251 | } | |
4252 | } | |
4253 | ||
4254 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4255 | { | |
4256 | struct intel_shared_dpll *pll; | |
4257 | enum intel_dpll_id i; | |
4258 | ||
4259 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4260 | pll = &dev_priv->shared_dplls[i]; | |
4261 | ||
4262 | WARN_ON(pll->new_config == &pll->config); | |
4263 | ||
4264 | kfree(pll->new_config); | |
4265 | pll->new_config = NULL; | |
4266 | } | |
4267 | } | |
4268 | ||
a1520318 | 4269 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4270 | { |
4271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4272 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4273 | u32 temp; |
4274 | ||
4275 | temp = I915_READ(dslreg); | |
4276 | udelay(500); | |
4277 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4278 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4279 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4280 | } |
4281 | } | |
4282 | ||
bd2e244f JB |
4283 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4284 | { | |
4285 | struct drm_device *dev = crtc->base.dev; | |
4286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4287 | int pipe = crtc->pipe; | |
4288 | ||
6e3c9717 | 4289 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f | 4290 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); |
6e3c9717 ACO |
4291 | I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4292 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4293 | } |
4294 | } | |
4295 | ||
b074cec8 JB |
4296 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4297 | { | |
4298 | struct drm_device *dev = crtc->base.dev; | |
4299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4300 | int pipe = crtc->pipe; | |
4301 | ||
6e3c9717 | 4302 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4303 | /* Force use of hard-coded filter coefficients |
4304 | * as some pre-programmed values are broken, | |
4305 | * e.g. x201. | |
4306 | */ | |
4307 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4308 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4309 | PF_PIPE_SEL_IVB(pipe)); | |
4310 | else | |
4311 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4312 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4313 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4314 | } |
4315 | } | |
4316 | ||
4a3b8769 | 4317 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4318 | { |
4319 | struct drm_device *dev = crtc->dev; | |
4320 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4321 | struct drm_plane *plane; |
bb53d4ae VS |
4322 | struct intel_plane *intel_plane; |
4323 | ||
af2b653b MR |
4324 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4325 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4326 | if (intel_plane->pipe == pipe) |
4327 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4328 | } |
bb53d4ae VS |
4329 | } |
4330 | ||
0d703d4e MR |
4331 | /* |
4332 | * Disable a plane internally without actually modifying the plane's state. | |
4333 | * This will allow us to easily restore the plane later by just reprogramming | |
4334 | * its state. | |
4335 | */ | |
4336 | static void disable_plane_internal(struct drm_plane *plane) | |
4337 | { | |
4338 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4339 | struct drm_plane_state *state = | |
4340 | plane->funcs->atomic_duplicate_state(plane); | |
4341 | struct intel_plane_state *intel_state = to_intel_plane_state(state); | |
4342 | ||
4343 | intel_state->visible = false; | |
4344 | intel_plane->commit_plane(plane, intel_state); | |
4345 | ||
4346 | intel_plane_destroy_state(plane, state); | |
4347 | } | |
4348 | ||
4a3b8769 | 4349 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4350 | { |
4351 | struct drm_device *dev = crtc->dev; | |
4352 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4353 | struct drm_plane *plane; |
bb53d4ae VS |
4354 | struct intel_plane *intel_plane; |
4355 | ||
af2b653b MR |
4356 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4357 | intel_plane = to_intel_plane(plane); | |
0d703d4e MR |
4358 | if (plane->fb && intel_plane->pipe == pipe) |
4359 | disable_plane_internal(plane); | |
af2b653b | 4360 | } |
bb53d4ae VS |
4361 | } |
4362 | ||
20bc8673 | 4363 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4364 | { |
cea165c3 VS |
4365 | struct drm_device *dev = crtc->base.dev; |
4366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4367 | |
6e3c9717 | 4368 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4369 | return; |
4370 | ||
cea165c3 VS |
4371 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4372 | intel_wait_for_vblank(dev, crtc->pipe); | |
4373 | ||
d77e4531 | 4374 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4375 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4376 | mutex_lock(&dev_priv->rps.hw_lock); |
4377 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4378 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4379 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4380 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4381 | * mailbox." Moreover, the mailbox may return a bogus state, |
4382 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4383 | */ |
4384 | } else { | |
4385 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4386 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4387 | * is essentially intel_wait_for_vblank. If we don't have this | |
4388 | * and don't wait for vblanks until the end of crtc_enable, then | |
4389 | * the HW state readout code will complain that the expected | |
4390 | * IPS_CTL value is not the one we read. */ | |
4391 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4392 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4393 | } | |
d77e4531 PZ |
4394 | } |
4395 | ||
20bc8673 | 4396 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4397 | { |
4398 | struct drm_device *dev = crtc->base.dev; | |
4399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4400 | ||
6e3c9717 | 4401 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4402 | return; |
4403 | ||
4404 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4405 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4406 | mutex_lock(&dev_priv->rps.hw_lock); |
4407 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4408 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4409 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4410 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4411 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4412 | } else { |
2a114cc1 | 4413 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4414 | POSTING_READ(IPS_CTL); |
4415 | } | |
d77e4531 PZ |
4416 | |
4417 | /* We need to wait for a vblank before we can disable the plane. */ | |
4418 | intel_wait_for_vblank(dev, crtc->pipe); | |
4419 | } | |
4420 | ||
4421 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4422 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4423 | { | |
4424 | struct drm_device *dev = crtc->dev; | |
4425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4427 | enum pipe pipe = intel_crtc->pipe; | |
4428 | int palreg = PALETTE(pipe); | |
4429 | int i; | |
4430 | bool reenable_ips = false; | |
4431 | ||
4432 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4433 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4434 | return; |
4435 | ||
4436 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4437 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4438 | assert_dsi_pll_enabled(dev_priv); |
4439 | else | |
4440 | assert_pll_enabled(dev_priv, pipe); | |
4441 | } | |
4442 | ||
4443 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4444 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4445 | palreg = LGC_PALETTE(pipe); |
4446 | ||
4447 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4448 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4449 | */ | |
6e3c9717 | 4450 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4451 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4452 | GAMMA_MODE_MODE_SPLIT)) { | |
4453 | hsw_disable_ips(intel_crtc); | |
4454 | reenable_ips = true; | |
4455 | } | |
4456 | ||
4457 | for (i = 0; i < 256; i++) { | |
4458 | I915_WRITE(palreg + 4 * i, | |
4459 | (intel_crtc->lut_r[i] << 16) | | |
4460 | (intel_crtc->lut_g[i] << 8) | | |
4461 | intel_crtc->lut_b[i]); | |
4462 | } | |
4463 | ||
4464 | if (reenable_ips) | |
4465 | hsw_enable_ips(intel_crtc); | |
4466 | } | |
4467 | ||
d3eedb1a VS |
4468 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4469 | { | |
4470 | if (!enable && intel_crtc->overlay) { | |
4471 | struct drm_device *dev = intel_crtc->base.dev; | |
4472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4473 | ||
4474 | mutex_lock(&dev->struct_mutex); | |
4475 | dev_priv->mm.interruptible = false; | |
4476 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4477 | dev_priv->mm.interruptible = true; | |
4478 | mutex_unlock(&dev->struct_mutex); | |
4479 | } | |
4480 | ||
4481 | /* Let userspace switch the overlay on again. In most cases userspace | |
4482 | * has to recompute where to put it anyway. | |
4483 | */ | |
4484 | } | |
4485 | ||
d3eedb1a | 4486 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4487 | { |
4488 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4490 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4491 | |
fdd508a6 | 4492 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4493 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4494 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4495 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4496 | |
4497 | hsw_enable_ips(intel_crtc); | |
4498 | ||
4499 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4500 | intel_fbc_update(dev); |
a5c4d7bc | 4501 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4502 | |
4503 | /* | |
4504 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4505 | * to compute the mask of flip planes precisely. For the time being | |
4506 | * consider this a flip from a NULL plane. | |
4507 | */ | |
4508 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4509 | } |
4510 | ||
d3eedb1a | 4511 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4512 | { |
4513 | struct drm_device *dev = crtc->dev; | |
4514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4515 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4516 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4517 | |
4518 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4519 | |
e35fef21 | 4520 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4521 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4522 | |
4523 | hsw_disable_ips(intel_crtc); | |
4524 | ||
d3eedb1a | 4525 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4526 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4527 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4528 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4529 | |
f99d7069 DV |
4530 | /* |
4531 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4532 | * to compute the mask of flip planes precisely. For the time being | |
4533 | * consider this a flip to a NULL plane. | |
4534 | */ | |
4535 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4536 | } |
4537 | ||
f67a559d JB |
4538 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4539 | { | |
4540 | struct drm_device *dev = crtc->dev; | |
4541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4542 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4543 | struct intel_encoder *encoder; |
f67a559d | 4544 | int pipe = intel_crtc->pipe; |
f67a559d | 4545 | |
83d65738 | 4546 | WARN_ON(!crtc->state->enable); |
08a48469 | 4547 | |
f67a559d JB |
4548 | if (intel_crtc->active) |
4549 | return; | |
4550 | ||
6e3c9717 | 4551 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4552 | intel_prepare_shared_dpll(intel_crtc); |
4553 | ||
6e3c9717 | 4554 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4555 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4556 | |
4557 | intel_set_pipe_timings(intel_crtc); | |
4558 | ||
6e3c9717 | 4559 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4560 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4561 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4562 | } |
4563 | ||
4564 | ironlake_set_pipeconf(crtc); | |
4565 | ||
f67a559d | 4566 | intel_crtc->active = true; |
8664281b | 4567 | |
a72e4c9f DV |
4568 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4569 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4570 | |
f6736a1a | 4571 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4572 | if (encoder->pre_enable) |
4573 | encoder->pre_enable(encoder); | |
f67a559d | 4574 | |
6e3c9717 | 4575 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4576 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4577 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4578 | * enabling. */ | |
88cefb6c | 4579 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4580 | } else { |
4581 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4582 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4583 | } | |
f67a559d | 4584 | |
b074cec8 | 4585 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4586 | |
9c54c0dd JB |
4587 | /* |
4588 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4589 | * clocks enabled | |
4590 | */ | |
4591 | intel_crtc_load_lut(crtc); | |
4592 | ||
f37fcc2a | 4593 | intel_update_watermarks(crtc); |
e1fdc473 | 4594 | intel_enable_pipe(intel_crtc); |
f67a559d | 4595 | |
6e3c9717 | 4596 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4597 | ironlake_pch_enable(crtc); |
c98e9dcf | 4598 | |
f9b61ff6 DV |
4599 | assert_vblank_disabled(crtc); |
4600 | drm_crtc_vblank_on(crtc); | |
4601 | ||
fa5c73b1 DV |
4602 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4603 | encoder->enable(encoder); | |
61b77ddd DV |
4604 | |
4605 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4606 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4607 | |
d3eedb1a | 4608 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4609 | } |
4610 | ||
42db64ef PZ |
4611 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4612 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4613 | { | |
f5adf94e | 4614 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4615 | } |
4616 | ||
e4916946 PZ |
4617 | /* |
4618 | * This implements the workaround described in the "notes" section of the mode | |
4619 | * set sequence documentation. When going from no pipes or single pipe to | |
4620 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4621 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4622 | */ | |
4623 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4624 | { | |
4625 | struct drm_device *dev = crtc->base.dev; | |
4626 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4627 | ||
4628 | /* We want to get the other_active_crtc only if there's only 1 other | |
4629 | * active crtc. */ | |
d3fcc808 | 4630 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4631 | if (!crtc_it->active || crtc_it == crtc) |
4632 | continue; | |
4633 | ||
4634 | if (other_active_crtc) | |
4635 | return; | |
4636 | ||
4637 | other_active_crtc = crtc_it; | |
4638 | } | |
4639 | if (!other_active_crtc) | |
4640 | return; | |
4641 | ||
4642 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4643 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4644 | } | |
4645 | ||
4f771f10 PZ |
4646 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4647 | { | |
4648 | struct drm_device *dev = crtc->dev; | |
4649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4651 | struct intel_encoder *encoder; | |
4652 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4653 | |
83d65738 | 4654 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4655 | |
4656 | if (intel_crtc->active) | |
4657 | return; | |
4658 | ||
df8ad70c DV |
4659 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4660 | intel_enable_shared_dpll(intel_crtc); | |
4661 | ||
6e3c9717 | 4662 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4663 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4664 | |
4665 | intel_set_pipe_timings(intel_crtc); | |
4666 | ||
6e3c9717 ACO |
4667 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4668 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4669 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4670 | } |
4671 | ||
6e3c9717 | 4672 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4673 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4674 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4675 | } |
4676 | ||
4677 | haswell_set_pipeconf(crtc); | |
4678 | ||
4679 | intel_set_pipe_csc(crtc); | |
4680 | ||
4f771f10 | 4681 | intel_crtc->active = true; |
8664281b | 4682 | |
a72e4c9f | 4683 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4684 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4685 | if (encoder->pre_enable) | |
4686 | encoder->pre_enable(encoder); | |
4687 | ||
6e3c9717 | 4688 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4689 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4690 | true); | |
4fe9467d ID |
4691 | dev_priv->display.fdi_link_train(crtc); |
4692 | } | |
4693 | ||
1f544388 | 4694 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4695 | |
bd2e244f JB |
4696 | if (IS_SKYLAKE(dev)) |
4697 | skylake_pfit_enable(intel_crtc); | |
4698 | else | |
4699 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4700 | |
4701 | /* | |
4702 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4703 | * clocks enabled | |
4704 | */ | |
4705 | intel_crtc_load_lut(crtc); | |
4706 | ||
1f544388 | 4707 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4708 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4709 | |
f37fcc2a | 4710 | intel_update_watermarks(crtc); |
e1fdc473 | 4711 | intel_enable_pipe(intel_crtc); |
42db64ef | 4712 | |
6e3c9717 | 4713 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4714 | lpt_pch_enable(crtc); |
4f771f10 | 4715 | |
6e3c9717 | 4716 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4717 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4718 | ||
f9b61ff6 DV |
4719 | assert_vblank_disabled(crtc); |
4720 | drm_crtc_vblank_on(crtc); | |
4721 | ||
8807e55b | 4722 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4723 | encoder->enable(encoder); |
8807e55b JN |
4724 | intel_opregion_notify_encoder(encoder, true); |
4725 | } | |
4f771f10 | 4726 | |
e4916946 PZ |
4727 | /* If we change the relative order between pipe/planes enabling, we need |
4728 | * to change the workaround. */ | |
4729 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4730 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4731 | } |
4732 | ||
bd2e244f JB |
4733 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4734 | { | |
4735 | struct drm_device *dev = crtc->base.dev; | |
4736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4737 | int pipe = crtc->pipe; | |
4738 | ||
4739 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4740 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4741 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f JB |
4742 | I915_WRITE(PS_CTL(pipe), 0); |
4743 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4744 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4745 | } | |
4746 | } | |
4747 | ||
3f8dce3a DV |
4748 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4749 | { | |
4750 | struct drm_device *dev = crtc->base.dev; | |
4751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4752 | int pipe = crtc->pipe; | |
4753 | ||
4754 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4755 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4756 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4757 | I915_WRITE(PF_CTL(pipe), 0); |
4758 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4759 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4760 | } | |
4761 | } | |
4762 | ||
6be4a607 JB |
4763 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4764 | { | |
4765 | struct drm_device *dev = crtc->dev; | |
4766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4768 | struct intel_encoder *encoder; |
6be4a607 | 4769 | int pipe = intel_crtc->pipe; |
5eddb70b | 4770 | u32 reg, temp; |
b52eb4dc | 4771 | |
f7abfe8b CW |
4772 | if (!intel_crtc->active) |
4773 | return; | |
4774 | ||
d3eedb1a | 4775 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4776 | |
ea9d758d DV |
4777 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4778 | encoder->disable(encoder); | |
4779 | ||
f9b61ff6 DV |
4780 | drm_crtc_vblank_off(crtc); |
4781 | assert_vblank_disabled(crtc); | |
4782 | ||
6e3c9717 | 4783 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4784 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4785 | |
575f7ab7 | 4786 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4787 | |
3f8dce3a | 4788 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4789 | |
bf49ec8c DV |
4790 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4791 | if (encoder->post_disable) | |
4792 | encoder->post_disable(encoder); | |
2c07245f | 4793 | |
6e3c9717 | 4794 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4795 | ironlake_fdi_disable(crtc); |
913d8d11 | 4796 | |
d925c59a | 4797 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4798 | |
d925c59a DV |
4799 | if (HAS_PCH_CPT(dev)) { |
4800 | /* disable TRANS_DP_CTL */ | |
4801 | reg = TRANS_DP_CTL(pipe); | |
4802 | temp = I915_READ(reg); | |
4803 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4804 | TRANS_DP_PORT_SEL_MASK); | |
4805 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4806 | I915_WRITE(reg, temp); | |
4807 | ||
4808 | /* disable DPLL_SEL */ | |
4809 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4810 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4811 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4812 | } |
e3421a18 | 4813 | |
d925c59a | 4814 | /* disable PCH DPLL */ |
e72f9fbf | 4815 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4816 | |
d925c59a DV |
4817 | ironlake_fdi_pll_disable(intel_crtc); |
4818 | } | |
6b383a7f | 4819 | |
f7abfe8b | 4820 | intel_crtc->active = false; |
46ba614c | 4821 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4822 | |
4823 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4824 | intel_fbc_update(dev); |
d1ebd816 | 4825 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4826 | } |
1b3c7a47 | 4827 | |
4f771f10 | 4828 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4829 | { |
4f771f10 PZ |
4830 | struct drm_device *dev = crtc->dev; |
4831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4833 | struct intel_encoder *encoder; |
6e3c9717 | 4834 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 4835 | |
4f771f10 PZ |
4836 | if (!intel_crtc->active) |
4837 | return; | |
4838 | ||
d3eedb1a | 4839 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4840 | |
8807e55b JN |
4841 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4842 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4843 | encoder->disable(encoder); |
8807e55b | 4844 | } |
4f771f10 | 4845 | |
f9b61ff6 DV |
4846 | drm_crtc_vblank_off(crtc); |
4847 | assert_vblank_disabled(crtc); | |
4848 | ||
6e3c9717 | 4849 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
4850 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4851 | false); | |
575f7ab7 | 4852 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4853 | |
6e3c9717 | 4854 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
4855 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4856 | ||
ad80a810 | 4857 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4858 | |
bd2e244f JB |
4859 | if (IS_SKYLAKE(dev)) |
4860 | skylake_pfit_disable(intel_crtc); | |
4861 | else | |
4862 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4863 | |
1f544388 | 4864 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4865 | |
6e3c9717 | 4866 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 4867 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 4868 | intel_ddi_fdi_disable(crtc); |
83616634 | 4869 | } |
4f771f10 | 4870 | |
97b040aa ID |
4871 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4872 | if (encoder->post_disable) | |
4873 | encoder->post_disable(encoder); | |
4874 | ||
4f771f10 | 4875 | intel_crtc->active = false; |
46ba614c | 4876 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4877 | |
4878 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4879 | intel_fbc_update(dev); |
4f771f10 | 4880 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
4881 | |
4882 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4883 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4884 | } |
4885 | ||
ee7b9f93 JB |
4886 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4887 | { | |
4888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4889 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4890 | } |
4891 | ||
6441ab5f | 4892 | |
2dd24552 JB |
4893 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4894 | { | |
4895 | struct drm_device *dev = crtc->base.dev; | |
4896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4897 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 4898 | |
681a8504 | 4899 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
4900 | return; |
4901 | ||
2dd24552 | 4902 | /* |
c0b03411 DV |
4903 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4904 | * according to register description and PRM. | |
2dd24552 | 4905 | */ |
c0b03411 DV |
4906 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4907 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4908 | |
b074cec8 JB |
4909 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4910 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4911 | |
4912 | /* Border color in case we don't scale up to the full screen. Black by | |
4913 | * default, change to something else for debugging. */ | |
4914 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4915 | } |
4916 | ||
d05410f9 DA |
4917 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4918 | { | |
4919 | switch (port) { | |
4920 | case PORT_A: | |
4921 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4922 | case PORT_B: | |
4923 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4924 | case PORT_C: | |
4925 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4926 | case PORT_D: | |
4927 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4928 | default: | |
4929 | WARN_ON_ONCE(1); | |
4930 | return POWER_DOMAIN_PORT_OTHER; | |
4931 | } | |
4932 | } | |
4933 | ||
77d22dca ID |
4934 | #define for_each_power_domain(domain, mask) \ |
4935 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4936 | if ((1 << (domain)) & (mask)) | |
4937 | ||
319be8ae ID |
4938 | enum intel_display_power_domain |
4939 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4940 | { | |
4941 | struct drm_device *dev = intel_encoder->base.dev; | |
4942 | struct intel_digital_port *intel_dig_port; | |
4943 | ||
4944 | switch (intel_encoder->type) { | |
4945 | case INTEL_OUTPUT_UNKNOWN: | |
4946 | /* Only DDI platforms should ever use this output type */ | |
4947 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4948 | case INTEL_OUTPUT_DISPLAYPORT: | |
4949 | case INTEL_OUTPUT_HDMI: | |
4950 | case INTEL_OUTPUT_EDP: | |
4951 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4952 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4953 | case INTEL_OUTPUT_DP_MST: |
4954 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4955 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4956 | case INTEL_OUTPUT_ANALOG: |
4957 | return POWER_DOMAIN_PORT_CRT; | |
4958 | case INTEL_OUTPUT_DSI: | |
4959 | return POWER_DOMAIN_PORT_DSI; | |
4960 | default: | |
4961 | return POWER_DOMAIN_PORT_OTHER; | |
4962 | } | |
4963 | } | |
4964 | ||
4965 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4966 | { |
319be8ae ID |
4967 | struct drm_device *dev = crtc->dev; |
4968 | struct intel_encoder *intel_encoder; | |
4969 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4970 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4971 | unsigned long mask; |
4972 | enum transcoder transcoder; | |
4973 | ||
4974 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4975 | ||
4976 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4977 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
4978 | if (intel_crtc->config->pch_pfit.enabled || |
4979 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
4980 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4981 | ||
319be8ae ID |
4982 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4983 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4984 | ||
77d22dca ID |
4985 | return mask; |
4986 | } | |
4987 | ||
679dacd4 | 4988 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 4989 | { |
679dacd4 | 4990 | struct drm_device *dev = state->dev; |
77d22dca ID |
4991 | struct drm_i915_private *dev_priv = dev->dev_private; |
4992 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4993 | struct intel_crtc *crtc; | |
4994 | ||
4995 | /* | |
4996 | * First get all needed power domains, then put all unneeded, to avoid | |
4997 | * any unnecessary toggling of the power wells. | |
4998 | */ | |
d3fcc808 | 4999 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5000 | enum intel_display_power_domain domain; |
5001 | ||
83d65738 | 5002 | if (!crtc->base.state->enable) |
77d22dca ID |
5003 | continue; |
5004 | ||
319be8ae | 5005 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5006 | |
5007 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5008 | intel_display_power_get(dev_priv, domain); | |
5009 | } | |
5010 | ||
50f6e502 | 5011 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5012 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5013 | |
d3fcc808 | 5014 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5015 | enum intel_display_power_domain domain; |
5016 | ||
5017 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5018 | intel_display_power_put(dev_priv, domain); | |
5019 | ||
5020 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5021 | } | |
5022 | ||
5023 | intel_display_set_init_power(dev_priv, false); | |
5024 | } | |
5025 | ||
dfcab17e | 5026 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5027 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5028 | { |
586f49dc | 5029 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5030 | |
586f49dc JB |
5031 | /* Obtain SKU information */ |
5032 | mutex_lock(&dev_priv->dpio_lock); | |
5033 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5034 | CCK_FUSE_HPLL_FREQ_MASK; | |
5035 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5036 | |
dfcab17e | 5037 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5038 | } |
5039 | ||
f8bf63fd VS |
5040 | static void vlv_update_cdclk(struct drm_device *dev) |
5041 | { | |
5042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5043 | ||
5044 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 5045 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
5046 | dev_priv->vlv_cdclk_freq); |
5047 | ||
5048 | /* | |
5049 | * Program the gmbus_freq based on the cdclk frequency. | |
5050 | * BSpec erroneously claims we should aim for 4MHz, but | |
5051 | * in fact 1MHz is the correct frequency. | |
5052 | */ | |
6be1e3d3 | 5053 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
5054 | } |
5055 | ||
30a970c6 JB |
5056 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5057 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5058 | { | |
5059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5060 | u32 val, cmd; | |
5061 | ||
d197b7d3 | 5062 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 5063 | |
dfcab17e | 5064 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5065 | cmd = 2; |
dfcab17e | 5066 | else if (cdclk == 266667) |
30a970c6 JB |
5067 | cmd = 1; |
5068 | else | |
5069 | cmd = 0; | |
5070 | ||
5071 | mutex_lock(&dev_priv->rps.hw_lock); | |
5072 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5073 | val &= ~DSPFREQGUAR_MASK; | |
5074 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5075 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5076 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5077 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5078 | 50)) { | |
5079 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5080 | } | |
5081 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5082 | ||
dfcab17e | 5083 | if (cdclk == 400000) { |
6bcda4f0 | 5084 | u32 divider; |
30a970c6 | 5085 | |
6bcda4f0 | 5086 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5087 | |
5088 | mutex_lock(&dev_priv->dpio_lock); | |
5089 | /* adjust cdclk divider */ | |
5090 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5091 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5092 | val |= divider; |
5093 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5094 | |
5095 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5096 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5097 | 50)) | |
5098 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5099 | mutex_unlock(&dev_priv->dpio_lock); |
5100 | } | |
5101 | ||
5102 | mutex_lock(&dev_priv->dpio_lock); | |
5103 | /* adjust self-refresh exit latency value */ | |
5104 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5105 | val &= ~0x7f; | |
5106 | ||
5107 | /* | |
5108 | * For high bandwidth configs, we set a higher latency in the bunit | |
5109 | * so that the core display fetch happens in time to avoid underruns. | |
5110 | */ | |
dfcab17e | 5111 | if (cdclk == 400000) |
30a970c6 JB |
5112 | val |= 4500 / 250; /* 4.5 usec */ |
5113 | else | |
5114 | val |= 3000 / 250; /* 3.0 usec */ | |
5115 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5116 | mutex_unlock(&dev_priv->dpio_lock); | |
5117 | ||
f8bf63fd | 5118 | vlv_update_cdclk(dev); |
30a970c6 JB |
5119 | } |
5120 | ||
383c5a6a VS |
5121 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5122 | { | |
5123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5124 | u32 val, cmd; | |
5125 | ||
5126 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
5127 | ||
5128 | switch (cdclk) { | |
383c5a6a VS |
5129 | case 333333: |
5130 | case 320000: | |
383c5a6a | 5131 | case 266667: |
383c5a6a | 5132 | case 200000: |
383c5a6a VS |
5133 | break; |
5134 | default: | |
5f77eeb0 | 5135 | MISSING_CASE(cdclk); |
383c5a6a VS |
5136 | return; |
5137 | } | |
5138 | ||
9d0d3fda VS |
5139 | /* |
5140 | * Specs are full of misinformation, but testing on actual | |
5141 | * hardware has shown that we just need to write the desired | |
5142 | * CCK divider into the Punit register. | |
5143 | */ | |
5144 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5145 | ||
383c5a6a VS |
5146 | mutex_lock(&dev_priv->rps.hw_lock); |
5147 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5148 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5149 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5150 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5151 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5152 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5153 | 50)) { | |
5154 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5155 | } | |
5156 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5157 | ||
5158 | vlv_update_cdclk(dev); | |
5159 | } | |
5160 | ||
30a970c6 JB |
5161 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5162 | int max_pixclk) | |
5163 | { | |
6bcda4f0 | 5164 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5165 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5166 | |
30a970c6 JB |
5167 | /* |
5168 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5169 | * 200MHz | |
5170 | * 267MHz | |
29dc7ef3 | 5171 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5172 | * 400MHz (VLV only) |
5173 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5174 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5175 | * |
5176 | * We seem to get an unstable or solid color picture at 200MHz. | |
5177 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5178 | * are off. | |
30a970c6 | 5179 | */ |
6cca3195 VS |
5180 | if (!IS_CHERRYVIEW(dev_priv) && |
5181 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5182 | return 400000; |
6cca3195 | 5183 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5184 | return freq_320; |
e37c67a1 | 5185 | else if (max_pixclk > 0) |
dfcab17e | 5186 | return 266667; |
e37c67a1 VS |
5187 | else |
5188 | return 200000; | |
30a970c6 JB |
5189 | } |
5190 | ||
2f2d7aa1 | 5191 | /* compute the max pixel clock for new configuration */ |
304603f4 | 5192 | static int intel_mode_max_pixclk(struct drm_atomic_state *state) |
30a970c6 | 5193 | { |
304603f4 | 5194 | struct drm_device *dev = state->dev; |
30a970c6 | 5195 | struct intel_crtc *intel_crtc; |
304603f4 | 5196 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5197 | int max_pixclk = 0; |
5198 | ||
d3fcc808 | 5199 | for_each_intel_crtc(dev, intel_crtc) { |
304603f4 ACO |
5200 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
5201 | if (IS_ERR(crtc_state)) | |
5202 | return PTR_ERR(crtc_state); | |
5203 | ||
5204 | if (!crtc_state->base.enable) | |
5205 | continue; | |
5206 | ||
5207 | max_pixclk = max(max_pixclk, | |
5208 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5209 | } |
5210 | ||
5211 | return max_pixclk; | |
5212 | } | |
5213 | ||
304603f4 | 5214 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, |
2f2d7aa1 | 5215 | unsigned *prepare_pipes) |
30a970c6 | 5216 | { |
304603f4 | 5217 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
30a970c6 | 5218 | struct intel_crtc *intel_crtc; |
304603f4 ACO |
5219 | int max_pixclk = intel_mode_max_pixclk(state); |
5220 | ||
5221 | if (max_pixclk < 0) | |
5222 | return max_pixclk; | |
30a970c6 | 5223 | |
d60c4473 ID |
5224 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
5225 | dev_priv->vlv_cdclk_freq) | |
304603f4 | 5226 | return 0; |
30a970c6 | 5227 | |
2f2d7aa1 | 5228 | /* disable/enable all currently active pipes while we change cdclk */ |
304603f4 | 5229 | for_each_intel_crtc(state->dev, intel_crtc) |
83d65738 | 5230 | if (intel_crtc->base.state->enable) |
30a970c6 | 5231 | *prepare_pipes |= (1 << intel_crtc->pipe); |
304603f4 ACO |
5232 | |
5233 | return 0; | |
30a970c6 JB |
5234 | } |
5235 | ||
1e69cd74 VS |
5236 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5237 | { | |
5238 | unsigned int credits, default_credits; | |
5239 | ||
5240 | if (IS_CHERRYVIEW(dev_priv)) | |
5241 | default_credits = PFI_CREDIT(12); | |
5242 | else | |
5243 | default_credits = PFI_CREDIT(8); | |
5244 | ||
5245 | if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { | |
5246 | /* CHV suggested value is 31 or 63 */ | |
5247 | if (IS_CHERRYVIEW(dev_priv)) | |
5248 | credits = PFI_CREDIT_31; | |
5249 | else | |
5250 | credits = PFI_CREDIT(15); | |
5251 | } else { | |
5252 | credits = default_credits; | |
5253 | } | |
5254 | ||
5255 | /* | |
5256 | * WA - write default credits before re-programming | |
5257 | * FIXME: should we also set the resend bit here? | |
5258 | */ | |
5259 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5260 | default_credits); | |
5261 | ||
5262 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5263 | credits | PFI_CREDIT_RESEND); | |
5264 | ||
5265 | /* | |
5266 | * FIXME is this guaranteed to clear | |
5267 | * immediately or should we poll for it? | |
5268 | */ | |
5269 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5270 | } | |
5271 | ||
679dacd4 | 5272 | static void valleyview_modeset_global_resources(struct drm_atomic_state *state) |
30a970c6 | 5273 | { |
679dacd4 | 5274 | struct drm_device *dev = state->dev; |
30a970c6 | 5275 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 ACO |
5276 | int max_pixclk = intel_mode_max_pixclk(state); |
5277 | int req_cdclk; | |
5278 | ||
5279 | /* The only reason this can fail is if we fail to add the crtc_state | |
5280 | * to the atomic state. But that can't happen since the call to | |
5281 | * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which | |
5282 | * can't have failed otherwise the mode set would be aborted) added all | |
5283 | * the states already. */ | |
5284 | if (WARN_ON(max_pixclk < 0)) | |
5285 | return; | |
5286 | ||
5287 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
30a970c6 | 5288 | |
383c5a6a | 5289 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
5290 | /* |
5291 | * FIXME: We can end up here with all power domains off, yet | |
5292 | * with a CDCLK frequency other than the minimum. To account | |
5293 | * for this take the PIPE-A power domain, which covers the HW | |
5294 | * blocks needed for the following programming. This can be | |
5295 | * removed once it's guaranteed that we get here either with | |
5296 | * the minimum CDCLK set, or the required power domains | |
5297 | * enabled. | |
5298 | */ | |
5299 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5300 | ||
383c5a6a VS |
5301 | if (IS_CHERRYVIEW(dev)) |
5302 | cherryview_set_cdclk(dev, req_cdclk); | |
5303 | else | |
5304 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5305 | |
1e69cd74 VS |
5306 | vlv_program_pfi_credits(dev_priv); |
5307 | ||
738c05c0 | 5308 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5309 | } |
30a970c6 JB |
5310 | } |
5311 | ||
89b667f8 JB |
5312 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5313 | { | |
5314 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5315 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5317 | struct intel_encoder *encoder; | |
5318 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5319 | bool is_dsi; |
89b667f8 | 5320 | |
83d65738 | 5321 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5322 | |
5323 | if (intel_crtc->active) | |
5324 | return; | |
5325 | ||
409ee761 | 5326 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5327 | |
1ae0d137 VS |
5328 | if (!is_dsi) { |
5329 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5330 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5331 | else |
6e3c9717 | 5332 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5333 | } |
5b18e57c | 5334 | |
6e3c9717 | 5335 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5336 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5337 | |
5338 | intel_set_pipe_timings(intel_crtc); | |
5339 | ||
c14b0485 VS |
5340 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5342 | ||
5343 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5344 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5345 | } | |
5346 | ||
5b18e57c DV |
5347 | i9xx_set_pipeconf(intel_crtc); |
5348 | ||
89b667f8 | 5349 | intel_crtc->active = true; |
89b667f8 | 5350 | |
a72e4c9f | 5351 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5352 | |
89b667f8 JB |
5353 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5354 | if (encoder->pre_pll_enable) | |
5355 | encoder->pre_pll_enable(encoder); | |
5356 | ||
9d556c99 CML |
5357 | if (!is_dsi) { |
5358 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5359 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5360 | else |
6e3c9717 | 5361 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5362 | } |
89b667f8 JB |
5363 | |
5364 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5365 | if (encoder->pre_enable) | |
5366 | encoder->pre_enable(encoder); | |
5367 | ||
2dd24552 JB |
5368 | i9xx_pfit_enable(intel_crtc); |
5369 | ||
63cbb074 VS |
5370 | intel_crtc_load_lut(crtc); |
5371 | ||
f37fcc2a | 5372 | intel_update_watermarks(crtc); |
e1fdc473 | 5373 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5374 | |
4b3a9526 VS |
5375 | assert_vblank_disabled(crtc); |
5376 | drm_crtc_vblank_on(crtc); | |
5377 | ||
f9b61ff6 DV |
5378 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5379 | encoder->enable(encoder); | |
5380 | ||
9ab0460b | 5381 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5382 | |
56b80e1f | 5383 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5384 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5385 | } |
5386 | ||
f13c2ef3 DV |
5387 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5388 | { | |
5389 | struct drm_device *dev = crtc->base.dev; | |
5390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5391 | ||
6e3c9717 ACO |
5392 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5393 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5394 | } |
5395 | ||
0b8765c6 | 5396 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5397 | { |
5398 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5399 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5400 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5401 | struct intel_encoder *encoder; |
79e53945 | 5402 | int pipe = intel_crtc->pipe; |
79e53945 | 5403 | |
83d65738 | 5404 | WARN_ON(!crtc->state->enable); |
08a48469 | 5405 | |
f7abfe8b CW |
5406 | if (intel_crtc->active) |
5407 | return; | |
5408 | ||
f13c2ef3 DV |
5409 | i9xx_set_pll_dividers(intel_crtc); |
5410 | ||
6e3c9717 | 5411 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5412 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5413 | |
5414 | intel_set_pipe_timings(intel_crtc); | |
5415 | ||
5b18e57c DV |
5416 | i9xx_set_pipeconf(intel_crtc); |
5417 | ||
f7abfe8b | 5418 | intel_crtc->active = true; |
6b383a7f | 5419 | |
4a3436e8 | 5420 | if (!IS_GEN2(dev)) |
a72e4c9f | 5421 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5422 | |
9d6d9f19 MK |
5423 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5424 | if (encoder->pre_enable) | |
5425 | encoder->pre_enable(encoder); | |
5426 | ||
f6736a1a DV |
5427 | i9xx_enable_pll(intel_crtc); |
5428 | ||
2dd24552 JB |
5429 | i9xx_pfit_enable(intel_crtc); |
5430 | ||
63cbb074 VS |
5431 | intel_crtc_load_lut(crtc); |
5432 | ||
f37fcc2a | 5433 | intel_update_watermarks(crtc); |
e1fdc473 | 5434 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5435 | |
4b3a9526 VS |
5436 | assert_vblank_disabled(crtc); |
5437 | drm_crtc_vblank_on(crtc); | |
5438 | ||
f9b61ff6 DV |
5439 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5440 | encoder->enable(encoder); | |
5441 | ||
9ab0460b | 5442 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5443 | |
4a3436e8 VS |
5444 | /* |
5445 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5446 | * So don't enable underrun reporting before at least some planes | |
5447 | * are enabled. | |
5448 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5449 | * but leave the pipe running. | |
5450 | */ | |
5451 | if (IS_GEN2(dev)) | |
a72e4c9f | 5452 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5453 | |
56b80e1f | 5454 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5455 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5456 | } |
79e53945 | 5457 | |
87476d63 DV |
5458 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5459 | { | |
5460 | struct drm_device *dev = crtc->base.dev; | |
5461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5462 | |
6e3c9717 | 5463 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5464 | return; |
87476d63 | 5465 | |
328d8e82 | 5466 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5467 | |
328d8e82 DV |
5468 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5469 | I915_READ(PFIT_CONTROL)); | |
5470 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5471 | } |
5472 | ||
0b8765c6 JB |
5473 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5474 | { | |
5475 | struct drm_device *dev = crtc->dev; | |
5476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5477 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5478 | struct intel_encoder *encoder; |
0b8765c6 | 5479 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5480 | |
f7abfe8b CW |
5481 | if (!intel_crtc->active) |
5482 | return; | |
5483 | ||
4a3436e8 VS |
5484 | /* |
5485 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5486 | * So diasble underrun reporting before all the planes get disabled. | |
5487 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5488 | * but leave the pipe running. | |
5489 | */ | |
5490 | if (IS_GEN2(dev)) | |
a72e4c9f | 5491 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5492 | |
564ed191 ID |
5493 | /* |
5494 | * Vblank time updates from the shadow to live plane control register | |
5495 | * are blocked if the memory self-refresh mode is active at that | |
5496 | * moment. So to make sure the plane gets truly disabled, disable | |
5497 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5498 | * will be checked/applied by the HW only at the next frame start | |
5499 | * event which is after the vblank start event, so we need to have a | |
5500 | * wait-for-vblank between disabling the plane and the pipe. | |
5501 | */ | |
5502 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5503 | intel_crtc_disable_planes(crtc); |
5504 | ||
6304cd91 VS |
5505 | /* |
5506 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5507 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5508 | * We also need to wait on all gmch platforms because of the |
5509 | * self-refresh mode constraint explained above. | |
6304cd91 | 5510 | */ |
564ed191 | 5511 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5512 | |
4b3a9526 VS |
5513 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5514 | encoder->disable(encoder); | |
5515 | ||
f9b61ff6 DV |
5516 | drm_crtc_vblank_off(crtc); |
5517 | assert_vblank_disabled(crtc); | |
5518 | ||
575f7ab7 | 5519 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5520 | |
87476d63 | 5521 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5522 | |
89b667f8 JB |
5523 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5524 | if (encoder->post_disable) | |
5525 | encoder->post_disable(encoder); | |
5526 | ||
409ee761 | 5527 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5528 | if (IS_CHERRYVIEW(dev)) |
5529 | chv_disable_pll(dev_priv, pipe); | |
5530 | else if (IS_VALLEYVIEW(dev)) | |
5531 | vlv_disable_pll(dev_priv, pipe); | |
5532 | else | |
1c4e0274 | 5533 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5534 | } |
0b8765c6 | 5535 | |
4a3436e8 | 5536 | if (!IS_GEN2(dev)) |
a72e4c9f | 5537 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5538 | |
f7abfe8b | 5539 | intel_crtc->active = false; |
46ba614c | 5540 | intel_update_watermarks(crtc); |
f37fcc2a | 5541 | |
efa9624e | 5542 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5543 | intel_fbc_update(dev); |
efa9624e | 5544 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5545 | } |
5546 | ||
ee7b9f93 JB |
5547 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5548 | { | |
5549 | } | |
5550 | ||
b04c5bd6 BF |
5551 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5552 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5553 | { |
5554 | struct drm_device *dev = crtc->dev; | |
5555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5556 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5557 | enum intel_display_power_domain domain; |
5558 | unsigned long domains; | |
976f8a20 | 5559 | |
0e572fe7 DV |
5560 | if (enable) { |
5561 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5562 | domains = get_crtc_power_domains(crtc); |
5563 | for_each_power_domain(domain, domains) | |
5564 | intel_display_power_get(dev_priv, domain); | |
5565 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5566 | |
5567 | dev_priv->display.crtc_enable(crtc); | |
5568 | } | |
5569 | } else { | |
5570 | if (intel_crtc->active) { | |
5571 | dev_priv->display.crtc_disable(crtc); | |
5572 | ||
e1e9fb84 DV |
5573 | domains = intel_crtc->enabled_power_domains; |
5574 | for_each_power_domain(domain, domains) | |
5575 | intel_display_power_put(dev_priv, domain); | |
5576 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5577 | } |
5578 | } | |
b04c5bd6 BF |
5579 | } |
5580 | ||
5581 | /** | |
5582 | * Sets the power management mode of the pipe and plane. | |
5583 | */ | |
5584 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5585 | { | |
5586 | struct drm_device *dev = crtc->dev; | |
5587 | struct intel_encoder *intel_encoder; | |
5588 | bool enable = false; | |
5589 | ||
5590 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5591 | enable |= intel_encoder->connectors_active; | |
5592 | ||
5593 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5594 | } |
5595 | ||
cdd59983 CW |
5596 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5597 | { | |
cdd59983 | 5598 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5599 | struct drm_connector *connector; |
ee7b9f93 | 5600 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5601 | |
976f8a20 | 5602 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 5603 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
5604 | |
5605 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5606 | dev_priv->display.off(crtc); |
5607 | ||
70a101f8 | 5608 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
5609 | |
5610 | /* Update computed state. */ | |
5611 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5612 | if (!connector->encoder || !connector->encoder->crtc) | |
5613 | continue; | |
5614 | ||
5615 | if (connector->encoder->crtc != crtc) | |
5616 | continue; | |
5617 | ||
5618 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5619 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5620 | } |
5621 | } | |
5622 | ||
ea5b213a | 5623 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5624 | { |
4ef69c7a | 5625 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5626 | |
ea5b213a CW |
5627 | drm_encoder_cleanup(encoder); |
5628 | kfree(intel_encoder); | |
7e7d76c3 JB |
5629 | } |
5630 | ||
9237329d | 5631 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5632 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5633 | * state of the entire output pipe. */ | |
9237329d | 5634 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5635 | { |
5ab432ef DV |
5636 | if (mode == DRM_MODE_DPMS_ON) { |
5637 | encoder->connectors_active = true; | |
5638 | ||
b2cabb0e | 5639 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5640 | } else { |
5641 | encoder->connectors_active = false; | |
5642 | ||
b2cabb0e | 5643 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5644 | } |
79e53945 JB |
5645 | } |
5646 | ||
0a91ca29 DV |
5647 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5648 | * internal consistency). */ | |
b980514c | 5649 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5650 | { |
0a91ca29 DV |
5651 | if (connector->get_hw_state(connector)) { |
5652 | struct intel_encoder *encoder = connector->encoder; | |
5653 | struct drm_crtc *crtc; | |
5654 | bool encoder_enabled; | |
5655 | enum pipe pipe; | |
5656 | ||
5657 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5658 | connector->base.base.id, | |
c23cc417 | 5659 | connector->base.name); |
0a91ca29 | 5660 | |
0e32b39c DA |
5661 | /* there is no real hw state for MST connectors */ |
5662 | if (connector->mst_port) | |
5663 | return; | |
5664 | ||
e2c719b7 | 5665 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 5666 | "wrong connector dpms state\n"); |
e2c719b7 | 5667 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 5668 | "active connector not linked to encoder\n"); |
0a91ca29 | 5669 | |
36cd7444 | 5670 | if (encoder) { |
e2c719b7 | 5671 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
5672 | "encoder->connectors_active not set\n"); |
5673 | ||
5674 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
5675 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
5676 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 5677 | return; |
0a91ca29 | 5678 | |
36cd7444 | 5679 | crtc = encoder->base.crtc; |
0a91ca29 | 5680 | |
83d65738 MR |
5681 | I915_STATE_WARN(!crtc->state->enable, |
5682 | "crtc not enabled\n"); | |
e2c719b7 RC |
5683 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5684 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
5685 | "encoder active on the wrong pipe\n"); |
5686 | } | |
0a91ca29 | 5687 | } |
79e53945 JB |
5688 | } |
5689 | ||
9bdbd0b9 ACO |
5690 | int intel_connector_init(struct intel_connector *connector) |
5691 | { | |
5692 | struct drm_connector_state *connector_state; | |
5693 | ||
5694 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
5695 | if (!connector_state) | |
5696 | return -ENOMEM; | |
5697 | ||
5698 | connector->base.state = connector_state; | |
5699 | return 0; | |
5700 | } | |
5701 | ||
5702 | struct intel_connector *intel_connector_alloc(void) | |
5703 | { | |
5704 | struct intel_connector *connector; | |
5705 | ||
5706 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5707 | if (!connector) | |
5708 | return NULL; | |
5709 | ||
5710 | if (intel_connector_init(connector) < 0) { | |
5711 | kfree(connector); | |
5712 | return NULL; | |
5713 | } | |
5714 | ||
5715 | return connector; | |
5716 | } | |
5717 | ||
5ab432ef DV |
5718 | /* Even simpler default implementation, if there's really no special case to |
5719 | * consider. */ | |
5720 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5721 | { |
5ab432ef DV |
5722 | /* All the simple cases only support two dpms states. */ |
5723 | if (mode != DRM_MODE_DPMS_ON) | |
5724 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5725 | |
5ab432ef DV |
5726 | if (mode == connector->dpms) |
5727 | return; | |
5728 | ||
5729 | connector->dpms = mode; | |
5730 | ||
5731 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5732 | if (connector->encoder) |
5733 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5734 | |
b980514c | 5735 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5736 | } |
5737 | ||
f0947c37 DV |
5738 | /* Simple connector->get_hw_state implementation for encoders that support only |
5739 | * one connector and no cloning and hence the encoder state determines the state | |
5740 | * of the connector. */ | |
5741 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5742 | { |
24929352 | 5743 | enum pipe pipe = 0; |
f0947c37 | 5744 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5745 | |
f0947c37 | 5746 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5747 | } |
5748 | ||
6d293983 | 5749 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 5750 | { |
6d293983 ACO |
5751 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
5752 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
5753 | |
5754 | return 0; | |
5755 | } | |
5756 | ||
6d293983 | 5757 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5758 | struct intel_crtc_state *pipe_config) |
1857e1da | 5759 | { |
6d293983 ACO |
5760 | struct drm_atomic_state *state = pipe_config->base.state; |
5761 | struct intel_crtc *other_crtc; | |
5762 | struct intel_crtc_state *other_crtc_state; | |
5763 | ||
1857e1da DV |
5764 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
5765 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5766 | if (pipe_config->fdi_lanes > 4) { | |
5767 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5768 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5769 | return -EINVAL; |
1857e1da DV |
5770 | } |
5771 | ||
bafb6553 | 5772 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5773 | if (pipe_config->fdi_lanes > 2) { |
5774 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5775 | pipe_config->fdi_lanes); | |
6d293983 | 5776 | return -EINVAL; |
1857e1da | 5777 | } else { |
6d293983 | 5778 | return 0; |
1857e1da DV |
5779 | } |
5780 | } | |
5781 | ||
5782 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 5783 | return 0; |
1857e1da DV |
5784 | |
5785 | /* Ivybridge 3 pipe is really complicated */ | |
5786 | switch (pipe) { | |
5787 | case PIPE_A: | |
6d293983 | 5788 | return 0; |
1857e1da | 5789 | case PIPE_B: |
6d293983 ACO |
5790 | if (pipe_config->fdi_lanes <= 2) |
5791 | return 0; | |
5792 | ||
5793 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
5794 | other_crtc_state = | |
5795 | intel_atomic_get_crtc_state(state, other_crtc); | |
5796 | if (IS_ERR(other_crtc_state)) | |
5797 | return PTR_ERR(other_crtc_state); | |
5798 | ||
5799 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
5800 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5801 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5802 | return -EINVAL; |
1857e1da | 5803 | } |
6d293983 | 5804 | return 0; |
1857e1da | 5805 | case PIPE_C: |
251cc67c VS |
5806 | if (pipe_config->fdi_lanes > 2) { |
5807 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
5808 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5809 | return -EINVAL; |
251cc67c | 5810 | } |
6d293983 ACO |
5811 | |
5812 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
5813 | other_crtc_state = | |
5814 | intel_atomic_get_crtc_state(state, other_crtc); | |
5815 | if (IS_ERR(other_crtc_state)) | |
5816 | return PTR_ERR(other_crtc_state); | |
5817 | ||
5818 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 5819 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 5820 | return -EINVAL; |
1857e1da | 5821 | } |
6d293983 | 5822 | return 0; |
1857e1da DV |
5823 | default: |
5824 | BUG(); | |
5825 | } | |
5826 | } | |
5827 | ||
e29c22c0 DV |
5828 | #define RETRY 1 |
5829 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 5830 | struct intel_crtc_state *pipe_config) |
877d48d5 | 5831 | { |
1857e1da | 5832 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 5833 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
5834 | int lane, link_bw, fdi_dotclock, ret; |
5835 | bool needs_recompute = false; | |
877d48d5 | 5836 | |
e29c22c0 | 5837 | retry: |
877d48d5 DV |
5838 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5839 | * each output octet as 10 bits. The actual frequency | |
5840 | * is stored as a divider into a 100MHz clock, and the | |
5841 | * mode pixel clock is stored in units of 1KHz. | |
5842 | * Hence the bw of each lane in terms of the mode signal | |
5843 | * is: | |
5844 | */ | |
5845 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5846 | ||
241bfc38 | 5847 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5848 | |
2bd89a07 | 5849 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5850 | pipe_config->pipe_bpp); |
5851 | ||
5852 | pipe_config->fdi_lanes = lane; | |
5853 | ||
2bd89a07 | 5854 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5855 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5856 | |
6d293983 ACO |
5857 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5858 | intel_crtc->pipe, pipe_config); | |
5859 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
5860 | pipe_config->pipe_bpp -= 2*3; |
5861 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5862 | pipe_config->pipe_bpp); | |
5863 | needs_recompute = true; | |
5864 | pipe_config->bw_constrained = true; | |
5865 | ||
5866 | goto retry; | |
5867 | } | |
5868 | ||
5869 | if (needs_recompute) | |
5870 | return RETRY; | |
5871 | ||
6d293983 | 5872 | return ret; |
877d48d5 DV |
5873 | } |
5874 | ||
42db64ef | 5875 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 5876 | struct intel_crtc_state *pipe_config) |
42db64ef | 5877 | { |
d330a953 | 5878 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5879 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5880 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5881 | } |
5882 | ||
a43f6e0f | 5883 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 5884 | struct intel_crtc_state *pipe_config) |
79e53945 | 5885 | { |
a43f6e0f | 5886 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5887 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 5888 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 5889 | int ret; |
89749350 | 5890 | |
ad3a4479 | 5891 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5892 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5893 | int clock_limit = |
5894 | dev_priv->display.get_display_clock_speed(dev); | |
5895 | ||
5896 | /* | |
5897 | * Enable pixel doubling when the dot clock | |
5898 | * is > 90% of the (display) core speed. | |
5899 | * | |
b397c96b VS |
5900 | * GDG double wide on either pipe, |
5901 | * otherwise pipe A only. | |
cf532bb2 | 5902 | */ |
b397c96b | 5903 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5904 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5905 | clock_limit *= 2; |
cf532bb2 | 5906 | pipe_config->double_wide = true; |
ad3a4479 VS |
5907 | } |
5908 | ||
241bfc38 | 5909 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5910 | return -EINVAL; |
2c07245f | 5911 | } |
89749350 | 5912 | |
1d1d0e27 VS |
5913 | /* |
5914 | * Pipe horizontal size must be even in: | |
5915 | * - DVO ganged mode | |
5916 | * - LVDS dual channel mode | |
5917 | * - Double wide pipe | |
5918 | */ | |
a93e255f | 5919 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5920 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5921 | pipe_config->pipe_src_w &= ~1; | |
5922 | ||
8693a824 DL |
5923 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5924 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5925 | */ |
5926 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5927 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5928 | return -EINVAL; |
44f46b42 | 5929 | |
bd080ee5 | 5930 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5931 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5932 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5933 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5934 | * for lvds. */ | |
5935 | pipe_config->pipe_bpp = 8*3; | |
5936 | } | |
5937 | ||
f5adf94e | 5938 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5939 | hsw_compute_ips_config(crtc, pipe_config); |
5940 | ||
877d48d5 | 5941 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5942 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5943 | |
d03c93d4 CK |
5944 | /* FIXME: remove below call once atomic mode set is place and all crtc |
5945 | * related checks called from atomic_crtc_check function */ | |
5946 | ret = 0; | |
5947 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
5948 | crtc, pipe_config->base.state); | |
5949 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
5950 | ||
5951 | return ret; | |
79e53945 JB |
5952 | } |
5953 | ||
1652d19e VS |
5954 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
5955 | { | |
5956 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5957 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5958 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5959 | uint32_t linkrate; | |
5960 | ||
5961 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
5962 | WARN(1, "LCPLL1 not enabled\n"); | |
5963 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
5964 | } | |
5965 | ||
5966 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
5967 | return 540000; | |
5968 | ||
5969 | linkrate = (I915_READ(DPLL_CTRL1) & | |
5970 | DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; | |
5971 | ||
5972 | if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || | |
5973 | linkrate == DPLL_CRTL1_LINK_RATE_1080) { | |
5974 | /* vco 8640 */ | |
5975 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
5976 | case CDCLK_FREQ_450_432: | |
5977 | return 432000; | |
5978 | case CDCLK_FREQ_337_308: | |
5979 | return 308570; | |
5980 | case CDCLK_FREQ_675_617: | |
5981 | return 617140; | |
5982 | default: | |
5983 | WARN(1, "Unknown cd freq selection\n"); | |
5984 | } | |
5985 | } else { | |
5986 | /* vco 8100 */ | |
5987 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
5988 | case CDCLK_FREQ_450_432: | |
5989 | return 450000; | |
5990 | case CDCLK_FREQ_337_308: | |
5991 | return 337500; | |
5992 | case CDCLK_FREQ_675_617: | |
5993 | return 675000; | |
5994 | default: | |
5995 | WARN(1, "Unknown cd freq selection\n"); | |
5996 | } | |
5997 | } | |
5998 | ||
5999 | /* error case, do as if DPLL0 isn't enabled */ | |
6000 | return 24000; | |
6001 | } | |
6002 | ||
6003 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6004 | { | |
6005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6006 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6007 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6008 | ||
6009 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6010 | return 800000; | |
6011 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6012 | return 450000; | |
6013 | else if (freq == LCPLL_CLK_FREQ_450) | |
6014 | return 450000; | |
6015 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6016 | return 540000; | |
6017 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6018 | return 337500; | |
6019 | else | |
6020 | return 675000; | |
6021 | } | |
6022 | ||
6023 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6024 | { | |
6025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6026 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6027 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6028 | ||
6029 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6030 | return 800000; | |
6031 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6032 | return 450000; | |
6033 | else if (freq == LCPLL_CLK_FREQ_450) | |
6034 | return 450000; | |
6035 | else if (IS_HSW_ULT(dev)) | |
6036 | return 337500; | |
6037 | else | |
6038 | return 540000; | |
6039 | } | |
6040 | ||
25eb05fc JB |
6041 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6042 | { | |
d197b7d3 | 6043 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6044 | u32 val; |
6045 | int divider; | |
6046 | ||
6bcda4f0 VS |
6047 | if (dev_priv->hpll_freq == 0) |
6048 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6049 | ||
d197b7d3 VS |
6050 | mutex_lock(&dev_priv->dpio_lock); |
6051 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6052 | mutex_unlock(&dev_priv->dpio_lock); | |
6053 | ||
6054 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6055 | ||
7d007f40 VS |
6056 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6057 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6058 | "cdclk change in progress\n"); | |
6059 | ||
6bcda4f0 | 6060 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6061 | } |
6062 | ||
b37a6434 VS |
6063 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6064 | { | |
6065 | return 450000; | |
6066 | } | |
6067 | ||
e70236a8 JB |
6068 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6069 | { | |
6070 | return 400000; | |
6071 | } | |
79e53945 | 6072 | |
e70236a8 | 6073 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6074 | { |
e907f170 | 6075 | return 333333; |
e70236a8 | 6076 | } |
79e53945 | 6077 | |
e70236a8 JB |
6078 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6079 | { | |
6080 | return 200000; | |
6081 | } | |
79e53945 | 6082 | |
257a7ffc DV |
6083 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6084 | { | |
6085 | u16 gcfgc = 0; | |
6086 | ||
6087 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6088 | ||
6089 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6090 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6091 | return 266667; |
257a7ffc | 6092 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6093 | return 333333; |
257a7ffc | 6094 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6095 | return 444444; |
257a7ffc DV |
6096 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6097 | return 200000; | |
6098 | default: | |
6099 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6100 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6101 | return 133333; |
257a7ffc | 6102 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6103 | return 166667; |
257a7ffc DV |
6104 | } |
6105 | } | |
6106 | ||
e70236a8 JB |
6107 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6108 | { | |
6109 | u16 gcfgc = 0; | |
79e53945 | 6110 | |
e70236a8 JB |
6111 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6112 | ||
6113 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6114 | return 133333; |
e70236a8 JB |
6115 | else { |
6116 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6117 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6118 | return 333333; |
e70236a8 JB |
6119 | default: |
6120 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6121 | return 190000; | |
79e53945 | 6122 | } |
e70236a8 JB |
6123 | } |
6124 | } | |
6125 | ||
6126 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6127 | { | |
e907f170 | 6128 | return 266667; |
e70236a8 JB |
6129 | } |
6130 | ||
6131 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6132 | { | |
6133 | u16 hpllcc = 0; | |
6134 | /* Assume that the hardware is in the high speed state. This | |
6135 | * should be the default. | |
6136 | */ | |
6137 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6138 | case GC_CLOCK_133_200: | |
6139 | case GC_CLOCK_100_200: | |
6140 | return 200000; | |
6141 | case GC_CLOCK_166_250: | |
6142 | return 250000; | |
6143 | case GC_CLOCK_100_133: | |
e907f170 | 6144 | return 133333; |
e70236a8 | 6145 | } |
79e53945 | 6146 | |
e70236a8 JB |
6147 | /* Shouldn't happen */ |
6148 | return 0; | |
6149 | } | |
79e53945 | 6150 | |
e70236a8 JB |
6151 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6152 | { | |
e907f170 | 6153 | return 133333; |
79e53945 JB |
6154 | } |
6155 | ||
2c07245f | 6156 | static void |
a65851af | 6157 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6158 | { |
a65851af VS |
6159 | while (*num > DATA_LINK_M_N_MASK || |
6160 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6161 | *num >>= 1; |
6162 | *den >>= 1; | |
6163 | } | |
6164 | } | |
6165 | ||
a65851af VS |
6166 | static void compute_m_n(unsigned int m, unsigned int n, |
6167 | uint32_t *ret_m, uint32_t *ret_n) | |
6168 | { | |
6169 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6170 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6171 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6172 | } | |
6173 | ||
e69d0bc1 DV |
6174 | void |
6175 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6176 | int pixel_clock, int link_clock, | |
6177 | struct intel_link_m_n *m_n) | |
2c07245f | 6178 | { |
e69d0bc1 | 6179 | m_n->tu = 64; |
a65851af VS |
6180 | |
6181 | compute_m_n(bits_per_pixel * pixel_clock, | |
6182 | link_clock * nlanes * 8, | |
6183 | &m_n->gmch_m, &m_n->gmch_n); | |
6184 | ||
6185 | compute_m_n(pixel_clock, link_clock, | |
6186 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6187 | } |
6188 | ||
a7615030 CW |
6189 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6190 | { | |
d330a953 JN |
6191 | if (i915.panel_use_ssc >= 0) |
6192 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6193 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6194 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6195 | } |
6196 | ||
a93e255f ACO |
6197 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6198 | int num_connectors) | |
c65d77d8 | 6199 | { |
a93e255f | 6200 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6201 | struct drm_i915_private *dev_priv = dev->dev_private; |
6202 | int refclk; | |
6203 | ||
a93e255f ACO |
6204 | WARN_ON(!crtc_state->base.state); |
6205 | ||
a0c4da24 | 6206 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 6207 | refclk = 100000; |
a93e255f | 6208 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6209 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6210 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6211 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6212 | } else if (!IS_GEN2(dev)) { |
6213 | refclk = 96000; | |
6214 | } else { | |
6215 | refclk = 48000; | |
6216 | } | |
6217 | ||
6218 | return refclk; | |
6219 | } | |
6220 | ||
7429e9d4 | 6221 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6222 | { |
7df00d7a | 6223 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6224 | } |
f47709a9 | 6225 | |
7429e9d4 DV |
6226 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6227 | { | |
6228 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6229 | } |
6230 | ||
f47709a9 | 6231 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6232 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6233 | intel_clock_t *reduced_clock) |
6234 | { | |
f47709a9 | 6235 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6236 | u32 fp, fp2 = 0; |
6237 | ||
6238 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6239 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6240 | if (reduced_clock) |
7429e9d4 | 6241 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6242 | } else { |
190f68c5 | 6243 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6244 | if (reduced_clock) |
7429e9d4 | 6245 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6246 | } |
6247 | ||
190f68c5 | 6248 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6249 | |
f47709a9 | 6250 | crtc->lowfreq_avail = false; |
a93e255f | 6251 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6252 | reduced_clock) { |
190f68c5 | 6253 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6254 | crtc->lowfreq_avail = true; |
a7516a05 | 6255 | } else { |
190f68c5 | 6256 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6257 | } |
6258 | } | |
6259 | ||
5e69f97f CML |
6260 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6261 | pipe) | |
89b667f8 JB |
6262 | { |
6263 | u32 reg_val; | |
6264 | ||
6265 | /* | |
6266 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6267 | * and set it to a reasonable value instead. | |
6268 | */ | |
ab3c759a | 6269 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6270 | reg_val &= 0xffffff00; |
6271 | reg_val |= 0x00000030; | |
ab3c759a | 6272 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6273 | |
ab3c759a | 6274 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6275 | reg_val &= 0x8cffffff; |
6276 | reg_val = 0x8c000000; | |
ab3c759a | 6277 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6278 | |
ab3c759a | 6279 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6280 | reg_val &= 0xffffff00; |
ab3c759a | 6281 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6282 | |
ab3c759a | 6283 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6284 | reg_val &= 0x00ffffff; |
6285 | reg_val |= 0xb0000000; | |
ab3c759a | 6286 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6287 | } |
6288 | ||
b551842d DV |
6289 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6290 | struct intel_link_m_n *m_n) | |
6291 | { | |
6292 | struct drm_device *dev = crtc->base.dev; | |
6293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6294 | int pipe = crtc->pipe; | |
6295 | ||
e3b95f1e DV |
6296 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6297 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6298 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6299 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6300 | } |
6301 | ||
6302 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6303 | struct intel_link_m_n *m_n, |
6304 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6305 | { |
6306 | struct drm_device *dev = crtc->base.dev; | |
6307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6308 | int pipe = crtc->pipe; | |
6e3c9717 | 6309 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6310 | |
6311 | if (INTEL_INFO(dev)->gen >= 5) { | |
6312 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6313 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6314 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6315 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6316 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6317 | * for gen < 8) and if DRRS is supported (to make sure the | |
6318 | * registers are not unnecessarily accessed). | |
6319 | */ | |
44395bfe | 6320 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6321 | crtc->config->has_drrs) { |
f769cd24 VK |
6322 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6323 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6324 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6325 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6326 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6327 | } | |
b551842d | 6328 | } else { |
e3b95f1e DV |
6329 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6330 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6331 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6332 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6333 | } |
6334 | } | |
6335 | ||
fe3cd48d | 6336 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6337 | { |
fe3cd48d R |
6338 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6339 | ||
6340 | if (m_n == M1_N1) { | |
6341 | dp_m_n = &crtc->config->dp_m_n; | |
6342 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6343 | } else if (m_n == M2_N2) { | |
6344 | ||
6345 | /* | |
6346 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6347 | * needs to be programmed into M1_N1. | |
6348 | */ | |
6349 | dp_m_n = &crtc->config->dp_m2_n2; | |
6350 | } else { | |
6351 | DRM_ERROR("Unsupported divider value\n"); | |
6352 | return; | |
6353 | } | |
6354 | ||
6e3c9717 ACO |
6355 | if (crtc->config->has_pch_encoder) |
6356 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6357 | else |
fe3cd48d | 6358 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6359 | } |
6360 | ||
d288f65f | 6361 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6362 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6363 | { |
6364 | u32 dpll, dpll_md; | |
6365 | ||
6366 | /* | |
6367 | * Enable DPIO clock input. We should never disable the reference | |
6368 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6369 | * on it. | |
6370 | */ | |
6371 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6372 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6373 | /* We should never disable this, set it here for state tracking */ | |
6374 | if (crtc->pipe == PIPE_B) | |
6375 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6376 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6377 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6378 | |
d288f65f | 6379 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6380 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6381 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6382 | } |
6383 | ||
d288f65f | 6384 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6385 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6386 | { |
f47709a9 | 6387 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6388 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6389 | int pipe = crtc->pipe; |
bdd4b6a6 | 6390 | u32 mdiv; |
a0c4da24 | 6391 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6392 | u32 coreclk, reg_val; |
a0c4da24 | 6393 | |
09153000 DV |
6394 | mutex_lock(&dev_priv->dpio_lock); |
6395 | ||
d288f65f VS |
6396 | bestn = pipe_config->dpll.n; |
6397 | bestm1 = pipe_config->dpll.m1; | |
6398 | bestm2 = pipe_config->dpll.m2; | |
6399 | bestp1 = pipe_config->dpll.p1; | |
6400 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6401 | |
89b667f8 JB |
6402 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6403 | ||
6404 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6405 | if (pipe == PIPE_B) |
5e69f97f | 6406 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6407 | |
6408 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6409 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6410 | |
6411 | /* Disable target IRef on PLL */ | |
ab3c759a | 6412 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6413 | reg_val &= 0x00ffffff; |
ab3c759a | 6414 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6415 | |
6416 | /* Disable fast lock */ | |
ab3c759a | 6417 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6418 | |
6419 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6420 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6421 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6422 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6423 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6424 | |
6425 | /* | |
6426 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6427 | * but we don't support that). | |
6428 | * Note: don't use the DAC post divider as it seems unstable. | |
6429 | */ | |
6430 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6431 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6432 | |
a0c4da24 | 6433 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6434 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6435 | |
89b667f8 | 6436 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6437 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6438 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6439 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6440 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6441 | 0x009f0003); |
89b667f8 | 6442 | else |
ab3c759a | 6443 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6444 | 0x00d0000f); |
6445 | ||
681a8504 | 6446 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6447 | /* Use SSC source */ |
bdd4b6a6 | 6448 | if (pipe == PIPE_A) |
ab3c759a | 6449 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6450 | 0x0df40000); |
6451 | else | |
ab3c759a | 6452 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6453 | 0x0df70000); |
6454 | } else { /* HDMI or VGA */ | |
6455 | /* Use bend source */ | |
bdd4b6a6 | 6456 | if (pipe == PIPE_A) |
ab3c759a | 6457 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6458 | 0x0df70000); |
6459 | else | |
ab3c759a | 6460 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6461 | 0x0df40000); |
6462 | } | |
a0c4da24 | 6463 | |
ab3c759a | 6464 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6465 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6466 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6467 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6468 | coreclk |= 0x01000000; |
ab3c759a | 6469 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6470 | |
ab3c759a | 6471 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6472 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6473 | } |
6474 | ||
d288f65f | 6475 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6476 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6477 | { |
d288f65f | 6478 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6479 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6480 | DPLL_VCO_ENABLE; | |
6481 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6482 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6483 | |
d288f65f VS |
6484 | pipe_config->dpll_hw_state.dpll_md = |
6485 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6486 | } |
6487 | ||
d288f65f | 6488 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6489 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6490 | { |
6491 | struct drm_device *dev = crtc->base.dev; | |
6492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6493 | int pipe = crtc->pipe; | |
6494 | int dpll_reg = DPLL(crtc->pipe); | |
6495 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6496 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6497 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6498 | u32 dpio_val; |
9cbe40c1 | 6499 | int vco; |
9d556c99 | 6500 | |
d288f65f VS |
6501 | bestn = pipe_config->dpll.n; |
6502 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6503 | bestm1 = pipe_config->dpll.m1; | |
6504 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6505 | bestp1 = pipe_config->dpll.p1; | |
6506 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6507 | vco = pipe_config->dpll.vco; |
a945ce7e | 6508 | dpio_val = 0; |
9cbe40c1 | 6509 | loopfilter = 0; |
9d556c99 CML |
6510 | |
6511 | /* | |
6512 | * Enable Refclk and SSC | |
6513 | */ | |
a11b0703 | 6514 | I915_WRITE(dpll_reg, |
d288f65f | 6515 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6516 | |
6517 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6518 | |
9d556c99 CML |
6519 | /* p1 and p2 divider */ |
6520 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6521 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6522 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6523 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6524 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6525 | ||
6526 | /* Feedback post-divider - m2 */ | |
6527 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6528 | ||
6529 | /* Feedback refclk divider - n and m1 */ | |
6530 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6531 | DPIO_CHV_M1_DIV_BY_2 | | |
6532 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6533 | ||
6534 | /* M2 fraction division */ | |
a945ce7e VP |
6535 | if (bestm2_frac) |
6536 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6537 | |
6538 | /* M2 fraction division enable */ | |
a945ce7e VP |
6539 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6540 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6541 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6542 | if (bestm2_frac) | |
6543 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6544 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6545 | |
de3a0fde VP |
6546 | /* Program digital lock detect threshold */ |
6547 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6548 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6549 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6550 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6551 | if (!bestm2_frac) | |
6552 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6553 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6554 | ||
9d556c99 | 6555 | /* Loop filter */ |
9cbe40c1 VP |
6556 | if (vco == 5400000) { |
6557 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6558 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6559 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6560 | tribuf_calcntr = 0x9; | |
6561 | } else if (vco <= 6200000) { | |
6562 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6563 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6564 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6565 | tribuf_calcntr = 0x9; | |
6566 | } else if (vco <= 6480000) { | |
6567 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6568 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6569 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6570 | tribuf_calcntr = 0x8; | |
6571 | } else { | |
6572 | /* Not supported. Apply the same limits as in the max case */ | |
6573 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6574 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6575 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6576 | tribuf_calcntr = 0; | |
6577 | } | |
9d556c99 CML |
6578 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6579 | ||
968040b2 | 6580 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6581 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6582 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6583 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6584 | ||
9d556c99 CML |
6585 | /* AFC Recal */ |
6586 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6587 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6588 | DPIO_AFC_RECAL); | |
6589 | ||
6590 | mutex_unlock(&dev_priv->dpio_lock); | |
6591 | } | |
6592 | ||
d288f65f VS |
6593 | /** |
6594 | * vlv_force_pll_on - forcibly enable just the PLL | |
6595 | * @dev_priv: i915 private structure | |
6596 | * @pipe: pipe PLL to enable | |
6597 | * @dpll: PLL configuration | |
6598 | * | |
6599 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6600 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6601 | * be enabled. | |
6602 | */ | |
6603 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6604 | const struct dpll *dpll) | |
6605 | { | |
6606 | struct intel_crtc *crtc = | |
6607 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 6608 | struct intel_crtc_state pipe_config = { |
a93e255f | 6609 | .base.crtc = &crtc->base, |
d288f65f VS |
6610 | .pixel_multiplier = 1, |
6611 | .dpll = *dpll, | |
6612 | }; | |
6613 | ||
6614 | if (IS_CHERRYVIEW(dev)) { | |
6615 | chv_update_pll(crtc, &pipe_config); | |
6616 | chv_prepare_pll(crtc, &pipe_config); | |
6617 | chv_enable_pll(crtc, &pipe_config); | |
6618 | } else { | |
6619 | vlv_update_pll(crtc, &pipe_config); | |
6620 | vlv_prepare_pll(crtc, &pipe_config); | |
6621 | vlv_enable_pll(crtc, &pipe_config); | |
6622 | } | |
6623 | } | |
6624 | ||
6625 | /** | |
6626 | * vlv_force_pll_off - forcibly disable just the PLL | |
6627 | * @dev_priv: i915 private structure | |
6628 | * @pipe: pipe PLL to disable | |
6629 | * | |
6630 | * Disable the PLL for @pipe. To be used in cases where we need | |
6631 | * the PLL enabled even when @pipe is not going to be enabled. | |
6632 | */ | |
6633 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6634 | { | |
6635 | if (IS_CHERRYVIEW(dev)) | |
6636 | chv_disable_pll(to_i915(dev), pipe); | |
6637 | else | |
6638 | vlv_disable_pll(to_i915(dev), pipe); | |
6639 | } | |
6640 | ||
f47709a9 | 6641 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6642 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6643 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6644 | int num_connectors) |
6645 | { | |
f47709a9 | 6646 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6647 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6648 | u32 dpll; |
6649 | bool is_sdvo; | |
190f68c5 | 6650 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6651 | |
190f68c5 | 6652 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6653 | |
a93e255f ACO |
6654 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6655 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6656 | |
6657 | dpll = DPLL_VGA_MODE_DIS; | |
6658 | ||
a93e255f | 6659 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6660 | dpll |= DPLLB_MODE_LVDS; |
6661 | else | |
6662 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6663 | |
ef1b460d | 6664 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 6665 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6666 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6667 | } |
198a037f DV |
6668 | |
6669 | if (is_sdvo) | |
4a33e48d | 6670 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6671 | |
190f68c5 | 6672 | if (crtc_state->has_dp_encoder) |
4a33e48d | 6673 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6674 | |
6675 | /* compute bitmask from p1 value */ | |
6676 | if (IS_PINEVIEW(dev)) | |
6677 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6678 | else { | |
6679 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6680 | if (IS_G4X(dev) && reduced_clock) | |
6681 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6682 | } | |
6683 | switch (clock->p2) { | |
6684 | case 5: | |
6685 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6686 | break; | |
6687 | case 7: | |
6688 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6689 | break; | |
6690 | case 10: | |
6691 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6692 | break; | |
6693 | case 14: | |
6694 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6695 | break; | |
6696 | } | |
6697 | if (INTEL_INFO(dev)->gen >= 4) | |
6698 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6699 | ||
190f68c5 | 6700 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6701 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 6702 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6703 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6704 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6705 | else | |
6706 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6707 | ||
6708 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6709 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6710 | |
eb1cbe48 | 6711 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 6712 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6713 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6714 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6715 | } |
6716 | } | |
6717 | ||
f47709a9 | 6718 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6719 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6720 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6721 | int num_connectors) |
6722 | { | |
f47709a9 | 6723 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6724 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6725 | u32 dpll; |
190f68c5 | 6726 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6727 | |
190f68c5 | 6728 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6729 | |
eb1cbe48 DV |
6730 | dpll = DPLL_VGA_MODE_DIS; |
6731 | ||
a93e255f | 6732 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6733 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6734 | } else { | |
6735 | if (clock->p1 == 2) | |
6736 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6737 | else | |
6738 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6739 | if (clock->p2 == 4) | |
6740 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6741 | } | |
6742 | ||
a93e255f | 6743 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6744 | dpll |= DPLL_DVO_2X_MODE; |
6745 | ||
a93e255f | 6746 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6747 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6748 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6749 | else | |
6750 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6751 | ||
6752 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6753 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6754 | } |
6755 | ||
8a654f3b | 6756 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6757 | { |
6758 | struct drm_device *dev = intel_crtc->base.dev; | |
6759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6760 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 6761 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 6762 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 6763 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6764 | uint32_t crtc_vtotal, crtc_vblank_end; |
6765 | int vsyncshift = 0; | |
4d8a62ea DV |
6766 | |
6767 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6768 | * the hw state checker will get angry at the mismatch. */ | |
6769 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6770 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6771 | |
609aeaca | 6772 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6773 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6774 | crtc_vtotal -= 1; |
6775 | crtc_vblank_end -= 1; | |
609aeaca | 6776 | |
409ee761 | 6777 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6778 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6779 | else | |
6780 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6781 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6782 | if (vsyncshift < 0) |
6783 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6784 | } |
6785 | ||
6786 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6787 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6788 | |
fe2b8f9d | 6789 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6790 | (adjusted_mode->crtc_hdisplay - 1) | |
6791 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6792 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6793 | (adjusted_mode->crtc_hblank_start - 1) | |
6794 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6795 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6796 | (adjusted_mode->crtc_hsync_start - 1) | |
6797 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6798 | ||
fe2b8f9d | 6799 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6800 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6801 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6802 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6803 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6804 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6805 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6806 | (adjusted_mode->crtc_vsync_start - 1) | |
6807 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6808 | ||
b5e508d4 PZ |
6809 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6810 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6811 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6812 | * bits. */ | |
6813 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6814 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6815 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6816 | ||
b0e77b9c PZ |
6817 | /* pipesrc controls the size that is scaled from, which should |
6818 | * always be the user's requested size. | |
6819 | */ | |
6820 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6821 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6822 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6823 | } |
6824 | ||
1bd1bd80 | 6825 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6826 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6827 | { |
6828 | struct drm_device *dev = crtc->base.dev; | |
6829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6830 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6831 | uint32_t tmp; | |
6832 | ||
6833 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6834 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6835 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6836 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6837 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6838 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6839 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6840 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6841 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6842 | |
6843 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6844 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6845 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6846 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6847 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6848 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6849 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6850 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6851 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6852 | |
6853 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6854 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6855 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6856 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
6857 | } |
6858 | ||
6859 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6860 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6861 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6862 | ||
2d112de7 ACO |
6863 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6864 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6865 | } |
6866 | ||
f6a83288 | 6867 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6868 | struct intel_crtc_state *pipe_config) |
babea61d | 6869 | { |
2d112de7 ACO |
6870 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6871 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6872 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6873 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6874 | |
2d112de7 ACO |
6875 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6876 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6877 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6878 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6879 | |
2d112de7 | 6880 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 6881 | |
2d112de7 ACO |
6882 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
6883 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
6884 | } |
6885 | ||
84b046f3 DV |
6886 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6887 | { | |
6888 | struct drm_device *dev = intel_crtc->base.dev; | |
6889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6890 | uint32_t pipeconf; | |
6891 | ||
9f11a9e4 | 6892 | pipeconf = 0; |
84b046f3 | 6893 | |
b6b5d049 VS |
6894 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6895 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6896 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6897 | |
6e3c9717 | 6898 | if (intel_crtc->config->double_wide) |
cf532bb2 | 6899 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 6900 | |
ff9ce46e DV |
6901 | /* only g4x and later have fancy bpc/dither controls */ |
6902 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 6903 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 6904 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 6905 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 6906 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6907 | |
6e3c9717 | 6908 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
6909 | case 18: |
6910 | pipeconf |= PIPECONF_6BPC; | |
6911 | break; | |
6912 | case 24: | |
6913 | pipeconf |= PIPECONF_8BPC; | |
6914 | break; | |
6915 | case 30: | |
6916 | pipeconf |= PIPECONF_10BPC; | |
6917 | break; | |
6918 | default: | |
6919 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6920 | BUG(); | |
84b046f3 DV |
6921 | } |
6922 | } | |
6923 | ||
6924 | if (HAS_PIPE_CXSR(dev)) { | |
6925 | if (intel_crtc->lowfreq_avail) { | |
6926 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6927 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6928 | } else { | |
6929 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6930 | } |
6931 | } | |
6932 | ||
6e3c9717 | 6933 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 6934 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 6935 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6936 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6937 | else | |
6938 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6939 | } else | |
84b046f3 DV |
6940 | pipeconf |= PIPECONF_PROGRESSIVE; |
6941 | ||
6e3c9717 | 6942 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 6943 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 6944 | |
84b046f3 DV |
6945 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6946 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6947 | } | |
6948 | ||
190f68c5 ACO |
6949 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
6950 | struct intel_crtc_state *crtc_state) | |
79e53945 | 6951 | { |
c7653199 | 6952 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6953 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6954 | int refclk, num_connectors = 0; |
652c393a | 6955 | intel_clock_t clock, reduced_clock; |
a16af721 | 6956 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6957 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6958 | struct intel_encoder *encoder; |
d4906093 | 6959 | const intel_limit_t *limit; |
55bb9992 ACO |
6960 | struct drm_atomic_state *state = crtc_state->base.state; |
6961 | struct drm_connector_state *connector_state; | |
6962 | int i; | |
79e53945 | 6963 | |
55bb9992 ACO |
6964 | for (i = 0; i < state->num_connector; i++) { |
6965 | if (!state->connectors[i]) | |
d0737e1d ACO |
6966 | continue; |
6967 | ||
55bb9992 ACO |
6968 | connector_state = state->connector_states[i]; |
6969 | if (connector_state->crtc != &crtc->base) | |
6970 | continue; | |
6971 | ||
6972 | encoder = to_intel_encoder(connector_state->best_encoder); | |
6973 | ||
5eddb70b | 6974 | switch (encoder->type) { |
79e53945 JB |
6975 | case INTEL_OUTPUT_LVDS: |
6976 | is_lvds = true; | |
6977 | break; | |
e9fd1c02 JN |
6978 | case INTEL_OUTPUT_DSI: |
6979 | is_dsi = true; | |
6980 | break; | |
6847d71b PZ |
6981 | default: |
6982 | break; | |
79e53945 | 6983 | } |
43565a06 | 6984 | |
c751ce4f | 6985 | num_connectors++; |
79e53945 JB |
6986 | } |
6987 | ||
f2335330 | 6988 | if (is_dsi) |
5b18e57c | 6989 | return 0; |
f2335330 | 6990 | |
190f68c5 | 6991 | if (!crtc_state->clock_set) { |
a93e255f | 6992 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 6993 | |
e9fd1c02 JN |
6994 | /* |
6995 | * Returns a set of divisors for the desired target clock with | |
6996 | * the given refclk, or FALSE. The returned values represent | |
6997 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6998 | * 2) / p1 / p2. | |
6999 | */ | |
a93e255f ACO |
7000 | limit = intel_limit(crtc_state, refclk); |
7001 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7002 | crtc_state->port_clock, |
e9fd1c02 | 7003 | refclk, NULL, &clock); |
f2335330 | 7004 | if (!ok) { |
e9fd1c02 JN |
7005 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7006 | return -EINVAL; | |
7007 | } | |
79e53945 | 7008 | |
f2335330 JN |
7009 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7010 | /* | |
7011 | * Ensure we match the reduced clock's P to the target | |
7012 | * clock. If the clocks don't match, we can't switch | |
7013 | * the display clock by using the FP0/FP1. In such case | |
7014 | * we will disable the LVDS downclock feature. | |
7015 | */ | |
7016 | has_reduced_clock = | |
a93e255f | 7017 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7018 | dev_priv->lvds_downclock, |
7019 | refclk, &clock, | |
7020 | &reduced_clock); | |
7021 | } | |
7022 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7023 | crtc_state->dpll.n = clock.n; |
7024 | crtc_state->dpll.m1 = clock.m1; | |
7025 | crtc_state->dpll.m2 = clock.m2; | |
7026 | crtc_state->dpll.p1 = clock.p1; | |
7027 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7028 | } |
7026d4ac | 7029 | |
e9fd1c02 | 7030 | if (IS_GEN2(dev)) { |
190f68c5 | 7031 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7032 | has_reduced_clock ? &reduced_clock : NULL, |
7033 | num_connectors); | |
9d556c99 | 7034 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7035 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7036 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7037 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7038 | } else { |
190f68c5 | 7039 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7040 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7041 | num_connectors); |
e9fd1c02 | 7042 | } |
79e53945 | 7043 | |
c8f7a0db | 7044 | return 0; |
f564048e EA |
7045 | } |
7046 | ||
2fa2fe9a | 7047 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7048 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7049 | { |
7050 | struct drm_device *dev = crtc->base.dev; | |
7051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7052 | uint32_t tmp; | |
7053 | ||
dc9e7dec VS |
7054 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7055 | return; | |
7056 | ||
2fa2fe9a | 7057 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7058 | if (!(tmp & PFIT_ENABLE)) |
7059 | return; | |
2fa2fe9a | 7060 | |
06922821 | 7061 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7062 | if (INTEL_INFO(dev)->gen < 4) { |
7063 | if (crtc->pipe != PIPE_B) | |
7064 | return; | |
2fa2fe9a DV |
7065 | } else { |
7066 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7067 | return; | |
7068 | } | |
7069 | ||
06922821 | 7070 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7071 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7072 | if (INTEL_INFO(dev)->gen < 5) | |
7073 | pipe_config->gmch_pfit.lvds_border_bits = | |
7074 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7075 | } | |
7076 | ||
acbec814 | 7077 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7078 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7079 | { |
7080 | struct drm_device *dev = crtc->base.dev; | |
7081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7082 | int pipe = pipe_config->cpu_transcoder; | |
7083 | intel_clock_t clock; | |
7084 | u32 mdiv; | |
662c6ecb | 7085 | int refclk = 100000; |
acbec814 | 7086 | |
f573de5a SK |
7087 | /* In case of MIPI DPLL will not even be used */ |
7088 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7089 | return; | |
7090 | ||
acbec814 | 7091 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7092 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7093 | mutex_unlock(&dev_priv->dpio_lock); |
7094 | ||
7095 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7096 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7097 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7098 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7099 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7100 | ||
f646628b | 7101 | vlv_clock(refclk, &clock); |
acbec814 | 7102 | |
f646628b VS |
7103 | /* clock.dot is the fast clock */ |
7104 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7105 | } |
7106 | ||
5724dbd1 DL |
7107 | static void |
7108 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7109 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7110 | { |
7111 | struct drm_device *dev = crtc->base.dev; | |
7112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7113 | u32 val, base, offset; | |
7114 | int pipe = crtc->pipe, plane = crtc->plane; | |
7115 | int fourcc, pixel_format; | |
6761dd31 | 7116 | unsigned int aligned_height; |
b113d5ee | 7117 | struct drm_framebuffer *fb; |
1b842c89 | 7118 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7119 | |
42a7b088 DL |
7120 | val = I915_READ(DSPCNTR(plane)); |
7121 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7122 | return; | |
7123 | ||
d9806c9f | 7124 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7125 | if (!intel_fb) { |
1ad292b5 JB |
7126 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7127 | return; | |
7128 | } | |
7129 | ||
1b842c89 DL |
7130 | fb = &intel_fb->base; |
7131 | ||
18c5247e DV |
7132 | if (INTEL_INFO(dev)->gen >= 4) { |
7133 | if (val & DISPPLANE_TILED) { | |
49af449b | 7134 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7135 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7136 | } | |
7137 | } | |
1ad292b5 JB |
7138 | |
7139 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7140 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7141 | fb->pixel_format = fourcc; |
7142 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7143 | |
7144 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7145 | if (plane_config->tiling) |
1ad292b5 JB |
7146 | offset = I915_READ(DSPTILEOFF(plane)); |
7147 | else | |
7148 | offset = I915_READ(DSPLINOFF(plane)); | |
7149 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7150 | } else { | |
7151 | base = I915_READ(DSPADDR(plane)); | |
7152 | } | |
7153 | plane_config->base = base; | |
7154 | ||
7155 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7156 | fb->width = ((val >> 16) & 0xfff) + 1; |
7157 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7158 | |
7159 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7160 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7161 | |
b113d5ee | 7162 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7163 | fb->pixel_format, |
7164 | fb->modifier[0]); | |
1ad292b5 | 7165 | |
f37b5c2b | 7166 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7167 | |
2844a921 DL |
7168 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7169 | pipe_name(pipe), plane, fb->width, fb->height, | |
7170 | fb->bits_per_pixel, base, fb->pitches[0], | |
7171 | plane_config->size); | |
1ad292b5 | 7172 | |
2d14030b | 7173 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7174 | } |
7175 | ||
70b23a98 | 7176 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7177 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7178 | { |
7179 | struct drm_device *dev = crtc->base.dev; | |
7180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7181 | int pipe = pipe_config->cpu_transcoder; | |
7182 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7183 | intel_clock_t clock; | |
7184 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7185 | int refclk = 100000; | |
7186 | ||
7187 | mutex_lock(&dev_priv->dpio_lock); | |
7188 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7189 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7190 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7191 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7192 | mutex_unlock(&dev_priv->dpio_lock); | |
7193 | ||
7194 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7195 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7196 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7197 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7198 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7199 | ||
7200 | chv_clock(refclk, &clock); | |
7201 | ||
7202 | /* clock.dot is the fast clock */ | |
7203 | pipe_config->port_clock = clock.dot / 5; | |
7204 | } | |
7205 | ||
0e8ffe1b | 7206 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7207 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7208 | { |
7209 | struct drm_device *dev = crtc->base.dev; | |
7210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7211 | uint32_t tmp; | |
7212 | ||
f458ebbc DV |
7213 | if (!intel_display_power_is_enabled(dev_priv, |
7214 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7215 | return false; |
7216 | ||
e143a21c | 7217 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7218 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7219 | |
0e8ffe1b DV |
7220 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7221 | if (!(tmp & PIPECONF_ENABLE)) | |
7222 | return false; | |
7223 | ||
42571aef VS |
7224 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7225 | switch (tmp & PIPECONF_BPC_MASK) { | |
7226 | case PIPECONF_6BPC: | |
7227 | pipe_config->pipe_bpp = 18; | |
7228 | break; | |
7229 | case PIPECONF_8BPC: | |
7230 | pipe_config->pipe_bpp = 24; | |
7231 | break; | |
7232 | case PIPECONF_10BPC: | |
7233 | pipe_config->pipe_bpp = 30; | |
7234 | break; | |
7235 | default: | |
7236 | break; | |
7237 | } | |
7238 | } | |
7239 | ||
b5a9fa09 DV |
7240 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7241 | pipe_config->limited_color_range = true; | |
7242 | ||
282740f7 VS |
7243 | if (INTEL_INFO(dev)->gen < 4) |
7244 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7245 | ||
1bd1bd80 DV |
7246 | intel_get_pipe_timings(crtc, pipe_config); |
7247 | ||
2fa2fe9a DV |
7248 | i9xx_get_pfit_config(crtc, pipe_config); |
7249 | ||
6c49f241 DV |
7250 | if (INTEL_INFO(dev)->gen >= 4) { |
7251 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7252 | pipe_config->pixel_multiplier = | |
7253 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7254 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7255 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7256 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7257 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7258 | pipe_config->pixel_multiplier = | |
7259 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7260 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7261 | } else { | |
7262 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7263 | * port and will be fixed up in the encoder->get_config | |
7264 | * function. */ | |
7265 | pipe_config->pixel_multiplier = 1; | |
7266 | } | |
8bcc2795 DV |
7267 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7268 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7269 | /* |
7270 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7271 | * on 830. Filter it out here so that we don't | |
7272 | * report errors due to that. | |
7273 | */ | |
7274 | if (IS_I830(dev)) | |
7275 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7276 | ||
8bcc2795 DV |
7277 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7278 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7279 | } else { |
7280 | /* Mask out read-only status bits. */ | |
7281 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7282 | DPLL_PORTC_READY_MASK | | |
7283 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7284 | } |
6c49f241 | 7285 | |
70b23a98 VS |
7286 | if (IS_CHERRYVIEW(dev)) |
7287 | chv_crtc_clock_get(crtc, pipe_config); | |
7288 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7289 | vlv_crtc_clock_get(crtc, pipe_config); |
7290 | else | |
7291 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7292 | |
0e8ffe1b DV |
7293 | return true; |
7294 | } | |
7295 | ||
dde86e2d | 7296 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7297 | { |
7298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7299 | struct intel_encoder *encoder; |
74cfd7ac | 7300 | u32 val, final; |
13d83a67 | 7301 | bool has_lvds = false; |
199e5d79 | 7302 | bool has_cpu_edp = false; |
199e5d79 | 7303 | bool has_panel = false; |
99eb6a01 KP |
7304 | bool has_ck505 = false; |
7305 | bool can_ssc = false; | |
13d83a67 JB |
7306 | |
7307 | /* We need to take the global config into account */ | |
b2784e15 | 7308 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7309 | switch (encoder->type) { |
7310 | case INTEL_OUTPUT_LVDS: | |
7311 | has_panel = true; | |
7312 | has_lvds = true; | |
7313 | break; | |
7314 | case INTEL_OUTPUT_EDP: | |
7315 | has_panel = true; | |
2de6905f | 7316 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7317 | has_cpu_edp = true; |
7318 | break; | |
6847d71b PZ |
7319 | default: |
7320 | break; | |
13d83a67 JB |
7321 | } |
7322 | } | |
7323 | ||
99eb6a01 | 7324 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7325 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7326 | can_ssc = has_ck505; |
7327 | } else { | |
7328 | has_ck505 = false; | |
7329 | can_ssc = true; | |
7330 | } | |
7331 | ||
2de6905f ID |
7332 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7333 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7334 | |
7335 | /* Ironlake: try to setup display ref clock before DPLL | |
7336 | * enabling. This is only under driver's control after | |
7337 | * PCH B stepping, previous chipset stepping should be | |
7338 | * ignoring this setting. | |
7339 | */ | |
74cfd7ac CW |
7340 | val = I915_READ(PCH_DREF_CONTROL); |
7341 | ||
7342 | /* As we must carefully and slowly disable/enable each source in turn, | |
7343 | * compute the final state we want first and check if we need to | |
7344 | * make any changes at all. | |
7345 | */ | |
7346 | final = val; | |
7347 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7348 | if (has_ck505) | |
7349 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7350 | else | |
7351 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7352 | ||
7353 | final &= ~DREF_SSC_SOURCE_MASK; | |
7354 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7355 | final &= ~DREF_SSC1_ENABLE; | |
7356 | ||
7357 | if (has_panel) { | |
7358 | final |= DREF_SSC_SOURCE_ENABLE; | |
7359 | ||
7360 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7361 | final |= DREF_SSC1_ENABLE; | |
7362 | ||
7363 | if (has_cpu_edp) { | |
7364 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7365 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7366 | else | |
7367 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7368 | } else | |
7369 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7370 | } else { | |
7371 | final |= DREF_SSC_SOURCE_DISABLE; | |
7372 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7373 | } | |
7374 | ||
7375 | if (final == val) | |
7376 | return; | |
7377 | ||
13d83a67 | 7378 | /* Always enable nonspread source */ |
74cfd7ac | 7379 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7380 | |
99eb6a01 | 7381 | if (has_ck505) |
74cfd7ac | 7382 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7383 | else |
74cfd7ac | 7384 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7385 | |
199e5d79 | 7386 | if (has_panel) { |
74cfd7ac CW |
7387 | val &= ~DREF_SSC_SOURCE_MASK; |
7388 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7389 | |
199e5d79 | 7390 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7391 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7392 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7393 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7394 | } else |
74cfd7ac | 7395 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7396 | |
7397 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7398 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7399 | POSTING_READ(PCH_DREF_CONTROL); |
7400 | udelay(200); | |
7401 | ||
74cfd7ac | 7402 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7403 | |
7404 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7405 | if (has_cpu_edp) { |
99eb6a01 | 7406 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7407 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7408 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7409 | } else |
74cfd7ac | 7410 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7411 | } else |
74cfd7ac | 7412 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7413 | |
74cfd7ac | 7414 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7415 | POSTING_READ(PCH_DREF_CONTROL); |
7416 | udelay(200); | |
7417 | } else { | |
7418 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7419 | ||
74cfd7ac | 7420 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7421 | |
7422 | /* Turn off CPU output */ | |
74cfd7ac | 7423 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7424 | |
74cfd7ac | 7425 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7426 | POSTING_READ(PCH_DREF_CONTROL); |
7427 | udelay(200); | |
7428 | ||
7429 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7430 | val &= ~DREF_SSC_SOURCE_MASK; |
7431 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7432 | |
7433 | /* Turn off SSC1 */ | |
74cfd7ac | 7434 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7435 | |
74cfd7ac | 7436 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7437 | POSTING_READ(PCH_DREF_CONTROL); |
7438 | udelay(200); | |
7439 | } | |
74cfd7ac CW |
7440 | |
7441 | BUG_ON(val != final); | |
13d83a67 JB |
7442 | } |
7443 | ||
f31f2d55 | 7444 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7445 | { |
f31f2d55 | 7446 | uint32_t tmp; |
dde86e2d | 7447 | |
0ff066a9 PZ |
7448 | tmp = I915_READ(SOUTH_CHICKEN2); |
7449 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7450 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7451 | |
0ff066a9 PZ |
7452 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7453 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7454 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7455 | |
0ff066a9 PZ |
7456 | tmp = I915_READ(SOUTH_CHICKEN2); |
7457 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7458 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7459 | |
0ff066a9 PZ |
7460 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7461 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7462 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7463 | } |
7464 | ||
7465 | /* WaMPhyProgramming:hsw */ | |
7466 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7467 | { | |
7468 | uint32_t tmp; | |
dde86e2d PZ |
7469 | |
7470 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7471 | tmp &= ~(0xFF << 24); | |
7472 | tmp |= (0x12 << 24); | |
7473 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7474 | ||
dde86e2d PZ |
7475 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7476 | tmp |= (1 << 11); | |
7477 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7478 | ||
7479 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7480 | tmp |= (1 << 11); | |
7481 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7482 | ||
dde86e2d PZ |
7483 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7484 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7485 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7486 | ||
7487 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7488 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7489 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7490 | ||
0ff066a9 PZ |
7491 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7492 | tmp &= ~(7 << 13); | |
7493 | tmp |= (5 << 13); | |
7494 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7495 | |
0ff066a9 PZ |
7496 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7497 | tmp &= ~(7 << 13); | |
7498 | tmp |= (5 << 13); | |
7499 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7500 | |
7501 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7502 | tmp &= ~0xFF; | |
7503 | tmp |= 0x1C; | |
7504 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7505 | ||
7506 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7507 | tmp &= ~0xFF; | |
7508 | tmp |= 0x1C; | |
7509 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7510 | ||
7511 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7512 | tmp &= ~(0xFF << 16); | |
7513 | tmp |= (0x1C << 16); | |
7514 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7515 | ||
7516 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7517 | tmp &= ~(0xFF << 16); | |
7518 | tmp |= (0x1C << 16); | |
7519 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7520 | ||
0ff066a9 PZ |
7521 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7522 | tmp |= (1 << 27); | |
7523 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7524 | |
0ff066a9 PZ |
7525 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7526 | tmp |= (1 << 27); | |
7527 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7528 | |
0ff066a9 PZ |
7529 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7530 | tmp &= ~(0xF << 28); | |
7531 | tmp |= (4 << 28); | |
7532 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7533 | |
0ff066a9 PZ |
7534 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7535 | tmp &= ~(0xF << 28); | |
7536 | tmp |= (4 << 28); | |
7537 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7538 | } |
7539 | ||
2fa86a1f PZ |
7540 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7541 | * Programming" based on the parameters passed: | |
7542 | * - Sequence to enable CLKOUT_DP | |
7543 | * - Sequence to enable CLKOUT_DP without spread | |
7544 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7545 | */ | |
7546 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7547 | bool with_fdi) | |
f31f2d55 PZ |
7548 | { |
7549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7550 | uint32_t reg, tmp; |
7551 | ||
7552 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7553 | with_spread = true; | |
7554 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7555 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7556 | with_fdi = false; | |
f31f2d55 PZ |
7557 | |
7558 | mutex_lock(&dev_priv->dpio_lock); | |
7559 | ||
7560 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7561 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7562 | tmp |= SBI_SSCCTL_PATHALT; | |
7563 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7564 | ||
7565 | udelay(24); | |
7566 | ||
2fa86a1f PZ |
7567 | if (with_spread) { |
7568 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7569 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7570 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7571 | |
2fa86a1f PZ |
7572 | if (with_fdi) { |
7573 | lpt_reset_fdi_mphy(dev_priv); | |
7574 | lpt_program_fdi_mphy(dev_priv); | |
7575 | } | |
7576 | } | |
dde86e2d | 7577 | |
2fa86a1f PZ |
7578 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7579 | SBI_GEN0 : SBI_DBUFF0; | |
7580 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7581 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7582 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7583 | |
7584 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7585 | } |
7586 | ||
47701c3b PZ |
7587 | /* Sequence to disable CLKOUT_DP */ |
7588 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7589 | { | |
7590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7591 | uint32_t reg, tmp; | |
7592 | ||
7593 | mutex_lock(&dev_priv->dpio_lock); | |
7594 | ||
7595 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7596 | SBI_GEN0 : SBI_DBUFF0; | |
7597 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7598 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7599 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7600 | ||
7601 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7602 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7603 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7604 | tmp |= SBI_SSCCTL_PATHALT; | |
7605 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7606 | udelay(32); | |
7607 | } | |
7608 | tmp |= SBI_SSCCTL_DISABLE; | |
7609 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7610 | } | |
7611 | ||
7612 | mutex_unlock(&dev_priv->dpio_lock); | |
7613 | } | |
7614 | ||
bf8fa3d3 PZ |
7615 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7616 | { | |
bf8fa3d3 PZ |
7617 | struct intel_encoder *encoder; |
7618 | bool has_vga = false; | |
7619 | ||
b2784e15 | 7620 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7621 | switch (encoder->type) { |
7622 | case INTEL_OUTPUT_ANALOG: | |
7623 | has_vga = true; | |
7624 | break; | |
6847d71b PZ |
7625 | default: |
7626 | break; | |
bf8fa3d3 PZ |
7627 | } |
7628 | } | |
7629 | ||
47701c3b PZ |
7630 | if (has_vga) |
7631 | lpt_enable_clkout_dp(dev, true, true); | |
7632 | else | |
7633 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7634 | } |
7635 | ||
dde86e2d PZ |
7636 | /* |
7637 | * Initialize reference clocks when the driver loads | |
7638 | */ | |
7639 | void intel_init_pch_refclk(struct drm_device *dev) | |
7640 | { | |
7641 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7642 | ironlake_init_pch_refclk(dev); | |
7643 | else if (HAS_PCH_LPT(dev)) | |
7644 | lpt_init_pch_refclk(dev); | |
7645 | } | |
7646 | ||
55bb9992 | 7647 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 7648 | { |
55bb9992 | 7649 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 7650 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 ACO |
7651 | struct drm_atomic_state *state = crtc_state->base.state; |
7652 | struct drm_connector_state *connector_state; | |
d9d444cb | 7653 | struct intel_encoder *encoder; |
55bb9992 | 7654 | int num_connectors = 0, i; |
d9d444cb JB |
7655 | bool is_lvds = false; |
7656 | ||
55bb9992 ACO |
7657 | for (i = 0; i < state->num_connector; i++) { |
7658 | if (!state->connectors[i]) | |
d0737e1d ACO |
7659 | continue; |
7660 | ||
55bb9992 ACO |
7661 | connector_state = state->connector_states[i]; |
7662 | if (connector_state->crtc != crtc_state->base.crtc) | |
7663 | continue; | |
7664 | ||
7665 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7666 | ||
d9d444cb JB |
7667 | switch (encoder->type) { |
7668 | case INTEL_OUTPUT_LVDS: | |
7669 | is_lvds = true; | |
7670 | break; | |
6847d71b PZ |
7671 | default: |
7672 | break; | |
d9d444cb JB |
7673 | } |
7674 | num_connectors++; | |
7675 | } | |
7676 | ||
7677 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7678 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7679 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7680 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7681 | } |
7682 | ||
7683 | return 120000; | |
7684 | } | |
7685 | ||
6ff93609 | 7686 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7687 | { |
c8203565 | 7688 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7690 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7691 | uint32_t val; |
7692 | ||
78114071 | 7693 | val = 0; |
c8203565 | 7694 | |
6e3c9717 | 7695 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7696 | case 18: |
dfd07d72 | 7697 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7698 | break; |
7699 | case 24: | |
dfd07d72 | 7700 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7701 | break; |
7702 | case 30: | |
dfd07d72 | 7703 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7704 | break; |
7705 | case 36: | |
dfd07d72 | 7706 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7707 | break; |
7708 | default: | |
cc769b62 PZ |
7709 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7710 | BUG(); | |
c8203565 PZ |
7711 | } |
7712 | ||
6e3c9717 | 7713 | if (intel_crtc->config->dither) |
c8203565 PZ |
7714 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7715 | ||
6e3c9717 | 7716 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7717 | val |= PIPECONF_INTERLACED_ILK; |
7718 | else | |
7719 | val |= PIPECONF_PROGRESSIVE; | |
7720 | ||
6e3c9717 | 7721 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7722 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7723 | |
c8203565 PZ |
7724 | I915_WRITE(PIPECONF(pipe), val); |
7725 | POSTING_READ(PIPECONF(pipe)); | |
7726 | } | |
7727 | ||
86d3efce VS |
7728 | /* |
7729 | * Set up the pipe CSC unit. | |
7730 | * | |
7731 | * Currently only full range RGB to limited range RGB conversion | |
7732 | * is supported, but eventually this should handle various | |
7733 | * RGB<->YCbCr scenarios as well. | |
7734 | */ | |
50f3b016 | 7735 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7736 | { |
7737 | struct drm_device *dev = crtc->dev; | |
7738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7740 | int pipe = intel_crtc->pipe; | |
7741 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7742 | ||
7743 | /* | |
7744 | * TODO: Check what kind of values actually come out of the pipe | |
7745 | * with these coeff/postoff values and adjust to get the best | |
7746 | * accuracy. Perhaps we even need to take the bpc value into | |
7747 | * consideration. | |
7748 | */ | |
7749 | ||
6e3c9717 | 7750 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7751 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7752 | ||
7753 | /* | |
7754 | * GY/GU and RY/RU should be the other way around according | |
7755 | * to BSpec, but reality doesn't agree. Just set them up in | |
7756 | * a way that results in the correct picture. | |
7757 | */ | |
7758 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7759 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7760 | ||
7761 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7762 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7763 | ||
7764 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7765 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7766 | ||
7767 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7768 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7769 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7770 | ||
7771 | if (INTEL_INFO(dev)->gen > 6) { | |
7772 | uint16_t postoff = 0; | |
7773 | ||
6e3c9717 | 7774 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 7775 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7776 | |
7777 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7778 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7779 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7780 | ||
7781 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7782 | } else { | |
7783 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7784 | ||
6e3c9717 | 7785 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7786 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7787 | ||
7788 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7789 | } | |
7790 | } | |
7791 | ||
6ff93609 | 7792 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7793 | { |
756f85cf PZ |
7794 | struct drm_device *dev = crtc->dev; |
7795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7797 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7798 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
7799 | uint32_t val; |
7800 | ||
3eff4faa | 7801 | val = 0; |
ee2b0b38 | 7802 | |
6e3c9717 | 7803 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7804 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7805 | ||
6e3c9717 | 7806 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7807 | val |= PIPECONF_INTERLACED_ILK; |
7808 | else | |
7809 | val |= PIPECONF_PROGRESSIVE; | |
7810 | ||
702e7a56 PZ |
7811 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7812 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7813 | |
7814 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7815 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7816 | |
3cdf122c | 7817 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7818 | val = 0; |
7819 | ||
6e3c9717 | 7820 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
7821 | case 18: |
7822 | val |= PIPEMISC_DITHER_6_BPC; | |
7823 | break; | |
7824 | case 24: | |
7825 | val |= PIPEMISC_DITHER_8_BPC; | |
7826 | break; | |
7827 | case 30: | |
7828 | val |= PIPEMISC_DITHER_10_BPC; | |
7829 | break; | |
7830 | case 36: | |
7831 | val |= PIPEMISC_DITHER_12_BPC; | |
7832 | break; | |
7833 | default: | |
7834 | /* Case prevented by pipe_config_set_bpp. */ | |
7835 | BUG(); | |
7836 | } | |
7837 | ||
6e3c9717 | 7838 | if (intel_crtc->config->dither) |
756f85cf PZ |
7839 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
7840 | ||
7841 | I915_WRITE(PIPEMISC(pipe), val); | |
7842 | } | |
ee2b0b38 PZ |
7843 | } |
7844 | ||
6591c6e4 | 7845 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 7846 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
7847 | intel_clock_t *clock, |
7848 | bool *has_reduced_clock, | |
7849 | intel_clock_t *reduced_clock) | |
7850 | { | |
7851 | struct drm_device *dev = crtc->dev; | |
7852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 7853 | int refclk; |
d4906093 | 7854 | const intel_limit_t *limit; |
a16af721 | 7855 | bool ret, is_lvds = false; |
79e53945 | 7856 | |
a93e255f | 7857 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 7858 | |
55bb9992 | 7859 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 7860 | |
d4906093 ML |
7861 | /* |
7862 | * Returns a set of divisors for the desired target clock with the given | |
7863 | * refclk, or FALSE. The returned values represent the clock equation: | |
7864 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7865 | */ | |
a93e255f ACO |
7866 | limit = intel_limit(crtc_state, refclk); |
7867 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7868 | crtc_state->port_clock, |
ee9300bb | 7869 | refclk, NULL, clock); |
6591c6e4 PZ |
7870 | if (!ret) |
7871 | return false; | |
cda4b7d3 | 7872 | |
ddc9003c | 7873 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7874 | /* |
7875 | * Ensure we match the reduced clock's P to the target clock. | |
7876 | * If the clocks don't match, we can't switch the display clock | |
7877 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7878 | * downclock feature. | |
7879 | */ | |
ee9300bb | 7880 | *has_reduced_clock = |
a93e255f | 7881 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
7882 | dev_priv->lvds_downclock, |
7883 | refclk, clock, | |
7884 | reduced_clock); | |
652c393a | 7885 | } |
61e9653f | 7886 | |
6591c6e4 PZ |
7887 | return true; |
7888 | } | |
7889 | ||
d4b1931c PZ |
7890 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7891 | { | |
7892 | /* | |
7893 | * Account for spread spectrum to avoid | |
7894 | * oversubscribing the link. Max center spread | |
7895 | * is 2.5%; use 5% for safety's sake. | |
7896 | */ | |
7897 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7898 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7899 | } |
7900 | ||
7429e9d4 | 7901 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7902 | { |
7429e9d4 | 7903 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7904 | } |
7905 | ||
de13a2e3 | 7906 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 7907 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 7908 | u32 *fp, |
9a7c7890 | 7909 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7910 | { |
de13a2e3 | 7911 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7912 | struct drm_device *dev = crtc->dev; |
7913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 ACO |
7914 | struct drm_atomic_state *state = crtc_state->base.state; |
7915 | struct drm_connector_state *connector_state; | |
7916 | struct intel_encoder *encoder; | |
de13a2e3 | 7917 | uint32_t dpll; |
55bb9992 | 7918 | int factor, num_connectors = 0, i; |
09ede541 | 7919 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7920 | |
55bb9992 ACO |
7921 | for (i = 0; i < state->num_connector; i++) { |
7922 | if (!state->connectors[i]) | |
d0737e1d ACO |
7923 | continue; |
7924 | ||
55bb9992 ACO |
7925 | connector_state = state->connector_states[i]; |
7926 | if (connector_state->crtc != crtc_state->base.crtc) | |
7927 | continue; | |
7928 | ||
7929 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7930 | ||
7931 | switch (encoder->type) { | |
79e53945 JB |
7932 | case INTEL_OUTPUT_LVDS: |
7933 | is_lvds = true; | |
7934 | break; | |
7935 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7936 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7937 | is_sdvo = true; |
79e53945 | 7938 | break; |
6847d71b PZ |
7939 | default: |
7940 | break; | |
79e53945 | 7941 | } |
43565a06 | 7942 | |
c751ce4f | 7943 | num_connectors++; |
79e53945 | 7944 | } |
79e53945 | 7945 | |
c1858123 | 7946 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7947 | factor = 21; |
7948 | if (is_lvds) { | |
7949 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7950 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7951 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7952 | factor = 25; |
190f68c5 | 7953 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 7954 | factor = 20; |
c1858123 | 7955 | |
190f68c5 | 7956 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 7957 | *fp |= FP_CB_TUNE; |
2c07245f | 7958 | |
9a7c7890 DV |
7959 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7960 | *fp2 |= FP_CB_TUNE; | |
7961 | ||
5eddb70b | 7962 | dpll = 0; |
2c07245f | 7963 | |
a07d6787 EA |
7964 | if (is_lvds) |
7965 | dpll |= DPLLB_MODE_LVDS; | |
7966 | else | |
7967 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7968 | |
190f68c5 | 7969 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7970 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7971 | |
7972 | if (is_sdvo) | |
4a33e48d | 7973 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 7974 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7975 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7976 | |
a07d6787 | 7977 | /* compute bitmask from p1 value */ |
190f68c5 | 7978 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7979 | /* also FPA1 */ |
190f68c5 | 7980 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7981 | |
190f68c5 | 7982 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
7983 | case 5: |
7984 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7985 | break; | |
7986 | case 7: | |
7987 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7988 | break; | |
7989 | case 10: | |
7990 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7991 | break; | |
7992 | case 14: | |
7993 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7994 | break; | |
79e53945 JB |
7995 | } |
7996 | ||
b4c09f3b | 7997 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7998 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7999 | else |
8000 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8001 | ||
959e16d6 | 8002 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8003 | } |
8004 | ||
190f68c5 ACO |
8005 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8006 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8007 | { |
c7653199 | 8008 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8009 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8010 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8011 | bool ok, has_reduced_clock = false; |
8b47047b | 8012 | bool is_lvds = false; |
e2b78267 | 8013 | struct intel_shared_dpll *pll; |
de13a2e3 | 8014 | |
409ee761 | 8015 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8016 | |
5dc5298b PZ |
8017 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8018 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8019 | |
190f68c5 | 8020 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8021 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8022 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8023 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8024 | return -EINVAL; | |
79e53945 | 8025 | } |
f47709a9 | 8026 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8027 | if (!crtc_state->clock_set) { |
8028 | crtc_state->dpll.n = clock.n; | |
8029 | crtc_state->dpll.m1 = clock.m1; | |
8030 | crtc_state->dpll.m2 = clock.m2; | |
8031 | crtc_state->dpll.p1 = clock.p1; | |
8032 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8033 | } |
79e53945 | 8034 | |
5dc5298b | 8035 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8036 | if (crtc_state->has_pch_encoder) { |
8037 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8038 | if (has_reduced_clock) |
7429e9d4 | 8039 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8040 | |
190f68c5 | 8041 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8042 | &fp, &reduced_clock, |
8043 | has_reduced_clock ? &fp2 : NULL); | |
8044 | ||
190f68c5 ACO |
8045 | crtc_state->dpll_hw_state.dpll = dpll; |
8046 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8047 | if (has_reduced_clock) |
190f68c5 | 8048 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8049 | else |
190f68c5 | 8050 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8051 | |
190f68c5 | 8052 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8053 | if (pll == NULL) { |
84f44ce7 | 8054 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8055 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8056 | return -EINVAL; |
8057 | } | |
3fb37703 | 8058 | } |
79e53945 | 8059 | |
ab585dea | 8060 | if (is_lvds && has_reduced_clock) |
c7653199 | 8061 | crtc->lowfreq_avail = true; |
bcd644e0 | 8062 | else |
c7653199 | 8063 | crtc->lowfreq_avail = false; |
e2b78267 | 8064 | |
c8f7a0db | 8065 | return 0; |
79e53945 JB |
8066 | } |
8067 | ||
eb14cb74 VS |
8068 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8069 | struct intel_link_m_n *m_n) | |
8070 | { | |
8071 | struct drm_device *dev = crtc->base.dev; | |
8072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8073 | enum pipe pipe = crtc->pipe; | |
8074 | ||
8075 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8076 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8077 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8078 | & ~TU_SIZE_MASK; | |
8079 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8080 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8081 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8082 | } | |
8083 | ||
8084 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8085 | enum transcoder transcoder, | |
b95af8be VK |
8086 | struct intel_link_m_n *m_n, |
8087 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8088 | { |
8089 | struct drm_device *dev = crtc->base.dev; | |
8090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8091 | enum pipe pipe = crtc->pipe; |
72419203 | 8092 | |
eb14cb74 VS |
8093 | if (INTEL_INFO(dev)->gen >= 5) { |
8094 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8095 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8096 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8097 | & ~TU_SIZE_MASK; | |
8098 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8099 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8100 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8101 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8102 | * gen < 8) and if DRRS is supported (to make sure the | |
8103 | * registers are not unnecessarily read). | |
8104 | */ | |
8105 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8106 | crtc->config->has_drrs) { |
b95af8be VK |
8107 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8108 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8109 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8110 | & ~TU_SIZE_MASK; | |
8111 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8112 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8113 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8114 | } | |
eb14cb74 VS |
8115 | } else { |
8116 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8117 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8118 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8119 | & ~TU_SIZE_MASK; | |
8120 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8121 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8122 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8123 | } | |
8124 | } | |
8125 | ||
8126 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8127 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8128 | { |
681a8504 | 8129 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8130 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8131 | else | |
8132 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8133 | &pipe_config->dp_m_n, |
8134 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8135 | } |
72419203 | 8136 | |
eb14cb74 | 8137 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8138 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8139 | { |
8140 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8141 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8142 | } |
8143 | ||
bd2e244f | 8144 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8145 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8146 | { |
8147 | struct drm_device *dev = crtc->base.dev; | |
8148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8149 | uint32_t tmp; | |
8150 | ||
8151 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
8152 | ||
8153 | if (tmp & PS_ENABLE) { | |
8154 | pipe_config->pch_pfit.enabled = true; | |
8155 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
8156 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
8157 | } | |
8158 | } | |
8159 | ||
5724dbd1 DL |
8160 | static void |
8161 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8162 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8163 | { |
8164 | struct drm_device *dev = crtc->base.dev; | |
8165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8166 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8167 | int pipe = crtc->pipe; |
8168 | int fourcc, pixel_format; | |
6761dd31 | 8169 | unsigned int aligned_height; |
bc8d7dff | 8170 | struct drm_framebuffer *fb; |
1b842c89 | 8171 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8172 | |
d9806c9f | 8173 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8174 | if (!intel_fb) { |
bc8d7dff DL |
8175 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8176 | return; | |
8177 | } | |
8178 | ||
1b842c89 DL |
8179 | fb = &intel_fb->base; |
8180 | ||
bc8d7dff | 8181 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8182 | if (!(val & PLANE_CTL_ENABLE)) |
8183 | goto error; | |
8184 | ||
bc8d7dff DL |
8185 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8186 | fourcc = skl_format_to_fourcc(pixel_format, | |
8187 | val & PLANE_CTL_ORDER_RGBX, | |
8188 | val & PLANE_CTL_ALPHA_MASK); | |
8189 | fb->pixel_format = fourcc; | |
8190 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8191 | ||
40f46283 DL |
8192 | tiling = val & PLANE_CTL_TILED_MASK; |
8193 | switch (tiling) { | |
8194 | case PLANE_CTL_TILED_LINEAR: | |
8195 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8196 | break; | |
8197 | case PLANE_CTL_TILED_X: | |
8198 | plane_config->tiling = I915_TILING_X; | |
8199 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8200 | break; | |
8201 | case PLANE_CTL_TILED_Y: | |
8202 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8203 | break; | |
8204 | case PLANE_CTL_TILED_YF: | |
8205 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8206 | break; | |
8207 | default: | |
8208 | MISSING_CASE(tiling); | |
8209 | goto error; | |
8210 | } | |
8211 | ||
bc8d7dff DL |
8212 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8213 | plane_config->base = base; | |
8214 | ||
8215 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8216 | ||
8217 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8218 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8219 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8220 | ||
8221 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8222 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8223 | fb->pixel_format); | |
bc8d7dff DL |
8224 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8225 | ||
8226 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8227 | fb->pixel_format, |
8228 | fb->modifier[0]); | |
bc8d7dff | 8229 | |
f37b5c2b | 8230 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8231 | |
8232 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8233 | pipe_name(pipe), fb->width, fb->height, | |
8234 | fb->bits_per_pixel, base, fb->pitches[0], | |
8235 | plane_config->size); | |
8236 | ||
2d14030b | 8237 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8238 | return; |
8239 | ||
8240 | error: | |
8241 | kfree(fb); | |
8242 | } | |
8243 | ||
2fa2fe9a | 8244 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8245 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8246 | { |
8247 | struct drm_device *dev = crtc->base.dev; | |
8248 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8249 | uint32_t tmp; | |
8250 | ||
8251 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8252 | ||
8253 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8254 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8255 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8256 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8257 | |
8258 | /* We currently do not free assignements of panel fitters on | |
8259 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8260 | * differentiates them) so just WARN about this case for now. */ | |
8261 | if (IS_GEN7(dev)) { | |
8262 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8263 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8264 | } | |
2fa2fe9a | 8265 | } |
79e53945 JB |
8266 | } |
8267 | ||
5724dbd1 DL |
8268 | static void |
8269 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8270 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8271 | { |
8272 | struct drm_device *dev = crtc->base.dev; | |
8273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8274 | u32 val, base, offset; | |
aeee5a49 | 8275 | int pipe = crtc->pipe; |
4c6baa59 | 8276 | int fourcc, pixel_format; |
6761dd31 | 8277 | unsigned int aligned_height; |
b113d5ee | 8278 | struct drm_framebuffer *fb; |
1b842c89 | 8279 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8280 | |
42a7b088 DL |
8281 | val = I915_READ(DSPCNTR(pipe)); |
8282 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8283 | return; | |
8284 | ||
d9806c9f | 8285 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8286 | if (!intel_fb) { |
4c6baa59 JB |
8287 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8288 | return; | |
8289 | } | |
8290 | ||
1b842c89 DL |
8291 | fb = &intel_fb->base; |
8292 | ||
18c5247e DV |
8293 | if (INTEL_INFO(dev)->gen >= 4) { |
8294 | if (val & DISPPLANE_TILED) { | |
49af449b | 8295 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8296 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8297 | } | |
8298 | } | |
4c6baa59 JB |
8299 | |
8300 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8301 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8302 | fb->pixel_format = fourcc; |
8303 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8304 | |
aeee5a49 | 8305 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8306 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8307 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8308 | } else { |
49af449b | 8309 | if (plane_config->tiling) |
aeee5a49 | 8310 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8311 | else |
aeee5a49 | 8312 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8313 | } |
8314 | plane_config->base = base; | |
8315 | ||
8316 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8317 | fb->width = ((val >> 16) & 0xfff) + 1; |
8318 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8319 | |
8320 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8321 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8322 | |
b113d5ee | 8323 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8324 | fb->pixel_format, |
8325 | fb->modifier[0]); | |
4c6baa59 | 8326 | |
f37b5c2b | 8327 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8328 | |
2844a921 DL |
8329 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8330 | pipe_name(pipe), fb->width, fb->height, | |
8331 | fb->bits_per_pixel, base, fb->pitches[0], | |
8332 | plane_config->size); | |
b113d5ee | 8333 | |
2d14030b | 8334 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8335 | } |
8336 | ||
0e8ffe1b | 8337 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8338 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8339 | { |
8340 | struct drm_device *dev = crtc->base.dev; | |
8341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8342 | uint32_t tmp; | |
8343 | ||
f458ebbc DV |
8344 | if (!intel_display_power_is_enabled(dev_priv, |
8345 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8346 | return false; |
8347 | ||
e143a21c | 8348 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8349 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8350 | |
0e8ffe1b DV |
8351 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8352 | if (!(tmp & PIPECONF_ENABLE)) | |
8353 | return false; | |
8354 | ||
42571aef VS |
8355 | switch (tmp & PIPECONF_BPC_MASK) { |
8356 | case PIPECONF_6BPC: | |
8357 | pipe_config->pipe_bpp = 18; | |
8358 | break; | |
8359 | case PIPECONF_8BPC: | |
8360 | pipe_config->pipe_bpp = 24; | |
8361 | break; | |
8362 | case PIPECONF_10BPC: | |
8363 | pipe_config->pipe_bpp = 30; | |
8364 | break; | |
8365 | case PIPECONF_12BPC: | |
8366 | pipe_config->pipe_bpp = 36; | |
8367 | break; | |
8368 | default: | |
8369 | break; | |
8370 | } | |
8371 | ||
b5a9fa09 DV |
8372 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8373 | pipe_config->limited_color_range = true; | |
8374 | ||
ab9412ba | 8375 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8376 | struct intel_shared_dpll *pll; |
8377 | ||
88adfff1 DV |
8378 | pipe_config->has_pch_encoder = true; |
8379 | ||
627eb5a3 DV |
8380 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8381 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8382 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8383 | |
8384 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8385 | |
c0d43d62 | 8386 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8387 | pipe_config->shared_dpll = |
8388 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8389 | } else { |
8390 | tmp = I915_READ(PCH_DPLL_SEL); | |
8391 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8392 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8393 | else | |
8394 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8395 | } | |
66e985c0 DV |
8396 | |
8397 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8398 | ||
8399 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8400 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8401 | |
8402 | tmp = pipe_config->dpll_hw_state.dpll; | |
8403 | pipe_config->pixel_multiplier = | |
8404 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8405 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8406 | |
8407 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8408 | } else { |
8409 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8410 | } |
8411 | ||
1bd1bd80 DV |
8412 | intel_get_pipe_timings(crtc, pipe_config); |
8413 | ||
2fa2fe9a DV |
8414 | ironlake_get_pfit_config(crtc, pipe_config); |
8415 | ||
0e8ffe1b DV |
8416 | return true; |
8417 | } | |
8418 | ||
be256dc7 PZ |
8419 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8420 | { | |
8421 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8422 | struct intel_crtc *crtc; |
be256dc7 | 8423 | |
d3fcc808 | 8424 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8425 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8426 | pipe_name(crtc->pipe)); |
8427 | ||
e2c719b7 RC |
8428 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8429 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8430 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8431 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8432 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8433 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8434 | "CPU PWM1 enabled\n"); |
c5107b87 | 8435 | if (IS_HASWELL(dev)) |
e2c719b7 | 8436 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8437 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8438 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8439 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8440 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8441 | "Utility pin enabled\n"); |
e2c719b7 | 8442 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8443 | |
9926ada1 PZ |
8444 | /* |
8445 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8446 | * interrupts remain enabled. We used to check for that, but since it's | |
8447 | * gen-specific and since we only disable LCPLL after we fully disable | |
8448 | * the interrupts, the check below should be enough. | |
8449 | */ | |
e2c719b7 | 8450 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8451 | } |
8452 | ||
9ccd5aeb PZ |
8453 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8454 | { | |
8455 | struct drm_device *dev = dev_priv->dev; | |
8456 | ||
8457 | if (IS_HASWELL(dev)) | |
8458 | return I915_READ(D_COMP_HSW); | |
8459 | else | |
8460 | return I915_READ(D_COMP_BDW); | |
8461 | } | |
8462 | ||
3c4c9b81 PZ |
8463 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8464 | { | |
8465 | struct drm_device *dev = dev_priv->dev; | |
8466 | ||
8467 | if (IS_HASWELL(dev)) { | |
8468 | mutex_lock(&dev_priv->rps.hw_lock); | |
8469 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8470 | val)) | |
f475dadf | 8471 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8472 | mutex_unlock(&dev_priv->rps.hw_lock); |
8473 | } else { | |
9ccd5aeb PZ |
8474 | I915_WRITE(D_COMP_BDW, val); |
8475 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8476 | } |
be256dc7 PZ |
8477 | } |
8478 | ||
8479 | /* | |
8480 | * This function implements pieces of two sequences from BSpec: | |
8481 | * - Sequence for display software to disable LCPLL | |
8482 | * - Sequence for display software to allow package C8+ | |
8483 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8484 | * register. Callers should take care of disabling all the display engine | |
8485 | * functions, doing the mode unset, fixing interrupts, etc. | |
8486 | */ | |
6ff58d53 PZ |
8487 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8488 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8489 | { |
8490 | uint32_t val; | |
8491 | ||
8492 | assert_can_disable_lcpll(dev_priv); | |
8493 | ||
8494 | val = I915_READ(LCPLL_CTL); | |
8495 | ||
8496 | if (switch_to_fclk) { | |
8497 | val |= LCPLL_CD_SOURCE_FCLK; | |
8498 | I915_WRITE(LCPLL_CTL, val); | |
8499 | ||
8500 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8501 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8502 | DRM_ERROR("Switching to FCLK failed\n"); | |
8503 | ||
8504 | val = I915_READ(LCPLL_CTL); | |
8505 | } | |
8506 | ||
8507 | val |= LCPLL_PLL_DISABLE; | |
8508 | I915_WRITE(LCPLL_CTL, val); | |
8509 | POSTING_READ(LCPLL_CTL); | |
8510 | ||
8511 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8512 | DRM_ERROR("LCPLL still locked\n"); | |
8513 | ||
9ccd5aeb | 8514 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8515 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8516 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8517 | ndelay(100); |
8518 | ||
9ccd5aeb PZ |
8519 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8520 | 1)) | |
be256dc7 PZ |
8521 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8522 | ||
8523 | if (allow_power_down) { | |
8524 | val = I915_READ(LCPLL_CTL); | |
8525 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8526 | I915_WRITE(LCPLL_CTL, val); | |
8527 | POSTING_READ(LCPLL_CTL); | |
8528 | } | |
8529 | } | |
8530 | ||
8531 | /* | |
8532 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8533 | * source. | |
8534 | */ | |
6ff58d53 | 8535 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8536 | { |
8537 | uint32_t val; | |
8538 | ||
8539 | val = I915_READ(LCPLL_CTL); | |
8540 | ||
8541 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8542 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8543 | return; | |
8544 | ||
a8a8bd54 PZ |
8545 | /* |
8546 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8547 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8548 | */ |
59bad947 | 8549 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8550 | |
be256dc7 PZ |
8551 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8552 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8553 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8554 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8555 | } |
8556 | ||
9ccd5aeb | 8557 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8558 | val |= D_COMP_COMP_FORCE; |
8559 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8560 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8561 | |
8562 | val = I915_READ(LCPLL_CTL); | |
8563 | val &= ~LCPLL_PLL_DISABLE; | |
8564 | I915_WRITE(LCPLL_CTL, val); | |
8565 | ||
8566 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8567 | DRM_ERROR("LCPLL not locked yet\n"); | |
8568 | ||
8569 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8570 | val = I915_READ(LCPLL_CTL); | |
8571 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8572 | I915_WRITE(LCPLL_CTL, val); | |
8573 | ||
8574 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
8575 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
8576 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
8577 | } | |
215733fa | 8578 | |
59bad947 | 8579 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
8580 | } |
8581 | ||
765dab67 PZ |
8582 | /* |
8583 | * Package states C8 and deeper are really deep PC states that can only be | |
8584 | * reached when all the devices on the system allow it, so even if the graphics | |
8585 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8586 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8587 | * | |
8588 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8589 | * well is disabled and most interrupts are disabled, and these are also | |
8590 | * requirements for runtime PM. When these conditions are met, we manually do | |
8591 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8592 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8593 | * hang the machine. | |
8594 | * | |
8595 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8596 | * the state of some registers, so when we come back from PC8+ we need to | |
8597 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8598 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8599 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8600 | * because of the runtime PM support). | |
8601 | * | |
8602 | * For more, read "Display Sequences for Package C8" on the hardware | |
8603 | * documentation. | |
8604 | */ | |
a14cb6fc | 8605 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8606 | { |
c67a470b PZ |
8607 | struct drm_device *dev = dev_priv->dev; |
8608 | uint32_t val; | |
8609 | ||
c67a470b PZ |
8610 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8611 | ||
c67a470b PZ |
8612 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
8613 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8614 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8615 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8616 | } | |
8617 | ||
8618 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
8619 | hsw_disable_lcpll(dev_priv, true, true); |
8620 | } | |
8621 | ||
a14cb6fc | 8622 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
8623 | { |
8624 | struct drm_device *dev = dev_priv->dev; | |
8625 | uint32_t val; | |
8626 | ||
c67a470b PZ |
8627 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8628 | ||
8629 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
8630 | lpt_init_pch_refclk(dev); |
8631 | ||
8632 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
8633 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8634 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8635 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8636 | } | |
8637 | ||
8638 | intel_prepare_ddi(dev); | |
c67a470b PZ |
8639 | } |
8640 | ||
190f68c5 ACO |
8641 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8642 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8643 | { |
190f68c5 | 8644 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 8645 | return -EINVAL; |
716c2e55 | 8646 | |
c7653199 | 8647 | crtc->lowfreq_avail = false; |
644cef34 | 8648 | |
c8f7a0db | 8649 | return 0; |
79e53945 JB |
8650 | } |
8651 | ||
96b7dfb7 S |
8652 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8653 | enum port port, | |
5cec258b | 8654 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8655 | { |
3148ade7 | 8656 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
8657 | |
8658 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
8659 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
8660 | ||
8661 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
8662 | case SKL_DPLL0: |
8663 | /* | |
8664 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
8665 | * of the shared DPLL framework and thus needs to be read out | |
8666 | * separately | |
8667 | */ | |
8668 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8669 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8670 | break; | |
96b7dfb7 S |
8671 | case SKL_DPLL1: |
8672 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8673 | break; | |
8674 | case SKL_DPLL2: | |
8675 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8676 | break; | |
8677 | case SKL_DPLL3: | |
8678 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8679 | break; | |
96b7dfb7 S |
8680 | } |
8681 | } | |
8682 | ||
7d2c8175 DL |
8683 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8684 | enum port port, | |
5cec258b | 8685 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
8686 | { |
8687 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8688 | ||
8689 | switch (pipe_config->ddi_pll_sel) { | |
8690 | case PORT_CLK_SEL_WRPLL1: | |
8691 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8692 | break; | |
8693 | case PORT_CLK_SEL_WRPLL2: | |
8694 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8695 | break; | |
8696 | } | |
8697 | } | |
8698 | ||
26804afd | 8699 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 8700 | struct intel_crtc_state *pipe_config) |
26804afd DV |
8701 | { |
8702 | struct drm_device *dev = crtc->base.dev; | |
8703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8704 | struct intel_shared_dpll *pll; |
26804afd DV |
8705 | enum port port; |
8706 | uint32_t tmp; | |
8707 | ||
8708 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8709 | ||
8710 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8711 | ||
96b7dfb7 S |
8712 | if (IS_SKYLAKE(dev)) |
8713 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8714 | else | |
8715 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8716 | |
d452c5b6 DV |
8717 | if (pipe_config->shared_dpll >= 0) { |
8718 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8719 | ||
8720 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8721 | &pipe_config->dpll_hw_state)); | |
8722 | } | |
8723 | ||
26804afd DV |
8724 | /* |
8725 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8726 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8727 | * the PCH transcoder is on. | |
8728 | */ | |
ca370455 DL |
8729 | if (INTEL_INFO(dev)->gen < 9 && |
8730 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8731 | pipe_config->has_pch_encoder = true; |
8732 | ||
8733 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8734 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8735 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8736 | ||
8737 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8738 | } | |
8739 | } | |
8740 | ||
0e8ffe1b | 8741 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8742 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8743 | { |
8744 | struct drm_device *dev = crtc->base.dev; | |
8745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8746 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8747 | uint32_t tmp; |
8748 | ||
f458ebbc | 8749 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8750 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8751 | return false; | |
8752 | ||
e143a21c | 8753 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8754 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8755 | ||
eccb140b DV |
8756 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8757 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8758 | enum pipe trans_edp_pipe; | |
8759 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8760 | default: | |
8761 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8762 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8763 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8764 | trans_edp_pipe = PIPE_A; | |
8765 | break; | |
8766 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8767 | trans_edp_pipe = PIPE_B; | |
8768 | break; | |
8769 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8770 | trans_edp_pipe = PIPE_C; | |
8771 | break; | |
8772 | } | |
8773 | ||
8774 | if (trans_edp_pipe == crtc->pipe) | |
8775 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8776 | } | |
8777 | ||
f458ebbc | 8778 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8779 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8780 | return false; |
8781 | ||
eccb140b | 8782 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8783 | if (!(tmp & PIPECONF_ENABLE)) |
8784 | return false; | |
8785 | ||
26804afd | 8786 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8787 | |
1bd1bd80 DV |
8788 | intel_get_pipe_timings(crtc, pipe_config); |
8789 | ||
2fa2fe9a | 8790 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8791 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8792 | if (IS_SKYLAKE(dev)) | |
8793 | skylake_get_pfit_config(crtc, pipe_config); | |
8794 | else | |
8795 | ironlake_get_pfit_config(crtc, pipe_config); | |
8796 | } | |
88adfff1 | 8797 | |
e59150dc JB |
8798 | if (IS_HASWELL(dev)) |
8799 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8800 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8801 | |
ebb69c95 CT |
8802 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8803 | pipe_config->pixel_multiplier = | |
8804 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8805 | } else { | |
8806 | pipe_config->pixel_multiplier = 1; | |
8807 | } | |
6c49f241 | 8808 | |
0e8ffe1b DV |
8809 | return true; |
8810 | } | |
8811 | ||
560b85bb CW |
8812 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8813 | { | |
8814 | struct drm_device *dev = crtc->dev; | |
8815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8817 | uint32_t cntl = 0, size = 0; |
560b85bb | 8818 | |
dc41c154 | 8819 | if (base) { |
3dd512fb MR |
8820 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
8821 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
8822 | unsigned int stride = roundup_pow_of_two(width) * 4; |
8823 | ||
8824 | switch (stride) { | |
8825 | default: | |
8826 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8827 | width, stride); | |
8828 | stride = 256; | |
8829 | /* fallthrough */ | |
8830 | case 256: | |
8831 | case 512: | |
8832 | case 1024: | |
8833 | case 2048: | |
8834 | break; | |
4b0e333e CW |
8835 | } |
8836 | ||
dc41c154 VS |
8837 | cntl |= CURSOR_ENABLE | |
8838 | CURSOR_GAMMA_ENABLE | | |
8839 | CURSOR_FORMAT_ARGB | | |
8840 | CURSOR_STRIDE(stride); | |
8841 | ||
8842 | size = (height << 12) | width; | |
4b0e333e | 8843 | } |
560b85bb | 8844 | |
dc41c154 VS |
8845 | if (intel_crtc->cursor_cntl != 0 && |
8846 | (intel_crtc->cursor_base != base || | |
8847 | intel_crtc->cursor_size != size || | |
8848 | intel_crtc->cursor_cntl != cntl)) { | |
8849 | /* On these chipsets we can only modify the base/size/stride | |
8850 | * whilst the cursor is disabled. | |
8851 | */ | |
8852 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8853 | POSTING_READ(_CURACNTR); |
dc41c154 | 8854 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8855 | } |
560b85bb | 8856 | |
99d1f387 | 8857 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8858 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8859 | intel_crtc->cursor_base = base; |
8860 | } | |
4726e0b0 | 8861 | |
dc41c154 VS |
8862 | if (intel_crtc->cursor_size != size) { |
8863 | I915_WRITE(CURSIZE, size); | |
8864 | intel_crtc->cursor_size = size; | |
4b0e333e | 8865 | } |
560b85bb | 8866 | |
4b0e333e | 8867 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8868 | I915_WRITE(_CURACNTR, cntl); |
8869 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8870 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8871 | } |
560b85bb CW |
8872 | } |
8873 | ||
560b85bb | 8874 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8875 | { |
8876 | struct drm_device *dev = crtc->dev; | |
8877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8879 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8880 | uint32_t cntl; |
8881 | ||
8882 | cntl = 0; | |
8883 | if (base) { | |
8884 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 8885 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
8886 | case 64: |
8887 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8888 | break; | |
8889 | case 128: | |
8890 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8891 | break; | |
8892 | case 256: | |
8893 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8894 | break; | |
8895 | default: | |
3dd512fb | 8896 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 8897 | return; |
65a21cd6 | 8898 | } |
4b0e333e | 8899 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8900 | |
8901 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8902 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8903 | } |
65a21cd6 | 8904 | |
8e7d688b | 8905 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
8906 | cntl |= CURSOR_ROTATE_180; |
8907 | ||
4b0e333e CW |
8908 | if (intel_crtc->cursor_cntl != cntl) { |
8909 | I915_WRITE(CURCNTR(pipe), cntl); | |
8910 | POSTING_READ(CURCNTR(pipe)); | |
8911 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8912 | } |
4b0e333e | 8913 | |
65a21cd6 | 8914 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8915 | I915_WRITE(CURBASE(pipe), base); |
8916 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8917 | |
8918 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8919 | } |
8920 | ||
cda4b7d3 | 8921 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8922 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8923 | bool on) | |
cda4b7d3 CW |
8924 | { |
8925 | struct drm_device *dev = crtc->dev; | |
8926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8928 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8929 | int x = crtc->cursor_x; |
8930 | int y = crtc->cursor_y; | |
d6e4db15 | 8931 | u32 base = 0, pos = 0; |
cda4b7d3 | 8932 | |
d6e4db15 | 8933 | if (on) |
cda4b7d3 | 8934 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8935 | |
6e3c9717 | 8936 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
8937 | base = 0; |
8938 | ||
6e3c9717 | 8939 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
8940 | base = 0; |
8941 | ||
8942 | if (x < 0) { | |
3dd512fb | 8943 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
8944 | base = 0; |
8945 | ||
8946 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8947 | x = -x; | |
8948 | } | |
8949 | pos |= x << CURSOR_X_SHIFT; | |
8950 | ||
8951 | if (y < 0) { | |
3dd512fb | 8952 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
8953 | base = 0; |
8954 | ||
8955 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8956 | y = -y; | |
8957 | } | |
8958 | pos |= y << CURSOR_Y_SHIFT; | |
8959 | ||
4b0e333e | 8960 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8961 | return; |
8962 | ||
5efb3e28 VS |
8963 | I915_WRITE(CURPOS(pipe), pos); |
8964 | ||
4398ad45 VS |
8965 | /* ILK+ do this automagically */ |
8966 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 8967 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
8968 | base += (intel_crtc->base.cursor->state->crtc_h * |
8969 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
8970 | } |
8971 | ||
8ac54669 | 8972 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8973 | i845_update_cursor(crtc, base); |
8974 | else | |
8975 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8976 | } |
8977 | ||
dc41c154 VS |
8978 | static bool cursor_size_ok(struct drm_device *dev, |
8979 | uint32_t width, uint32_t height) | |
8980 | { | |
8981 | if (width == 0 || height == 0) | |
8982 | return false; | |
8983 | ||
8984 | /* | |
8985 | * 845g/865g are special in that they are only limited by | |
8986 | * the width of their cursors, the height is arbitrary up to | |
8987 | * the precision of the register. Everything else requires | |
8988 | * square cursors, limited to a few power-of-two sizes. | |
8989 | */ | |
8990 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8991 | if ((width & 63) != 0) | |
8992 | return false; | |
8993 | ||
8994 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8995 | return false; | |
8996 | ||
8997 | if (height > 1023) | |
8998 | return false; | |
8999 | } else { | |
9000 | switch (width | height) { | |
9001 | case 256: | |
9002 | case 128: | |
9003 | if (IS_GEN2(dev)) | |
9004 | return false; | |
9005 | case 64: | |
9006 | break; | |
9007 | default: | |
9008 | return false; | |
9009 | } | |
9010 | } | |
9011 | ||
9012 | return true; | |
9013 | } | |
9014 | ||
79e53945 | 9015 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9016 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9017 | { |
7203425a | 9018 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9019 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9020 | |
7203425a | 9021 | for (i = start; i < end; i++) { |
79e53945 JB |
9022 | intel_crtc->lut_r[i] = red[i] >> 8; |
9023 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9024 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9025 | } | |
9026 | ||
9027 | intel_crtc_load_lut(crtc); | |
9028 | } | |
9029 | ||
79e53945 JB |
9030 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9031 | static struct drm_display_mode load_detect_mode = { | |
9032 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9033 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9034 | }; | |
9035 | ||
a8bb6818 DV |
9036 | struct drm_framebuffer * |
9037 | __intel_framebuffer_create(struct drm_device *dev, | |
9038 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9039 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9040 | { |
9041 | struct intel_framebuffer *intel_fb; | |
9042 | int ret; | |
9043 | ||
9044 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9045 | if (!intel_fb) { | |
6ccb81f2 | 9046 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9047 | return ERR_PTR(-ENOMEM); |
9048 | } | |
9049 | ||
9050 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9051 | if (ret) |
9052 | goto err; | |
d2dff872 CW |
9053 | |
9054 | return &intel_fb->base; | |
dd4916c5 | 9055 | err: |
6ccb81f2 | 9056 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9057 | kfree(intel_fb); |
9058 | ||
9059 | return ERR_PTR(ret); | |
d2dff872 CW |
9060 | } |
9061 | ||
b5ea642a | 9062 | static struct drm_framebuffer * |
a8bb6818 DV |
9063 | intel_framebuffer_create(struct drm_device *dev, |
9064 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9065 | struct drm_i915_gem_object *obj) | |
9066 | { | |
9067 | struct drm_framebuffer *fb; | |
9068 | int ret; | |
9069 | ||
9070 | ret = i915_mutex_lock_interruptible(dev); | |
9071 | if (ret) | |
9072 | return ERR_PTR(ret); | |
9073 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9074 | mutex_unlock(&dev->struct_mutex); | |
9075 | ||
9076 | return fb; | |
9077 | } | |
9078 | ||
d2dff872 CW |
9079 | static u32 |
9080 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9081 | { | |
9082 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9083 | return ALIGN(pitch, 64); | |
9084 | } | |
9085 | ||
9086 | static u32 | |
9087 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9088 | { | |
9089 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9090 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9091 | } |
9092 | ||
9093 | static struct drm_framebuffer * | |
9094 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9095 | struct drm_display_mode *mode, | |
9096 | int depth, int bpp) | |
9097 | { | |
9098 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9099 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9100 | |
9101 | obj = i915_gem_alloc_object(dev, | |
9102 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9103 | if (obj == NULL) | |
9104 | return ERR_PTR(-ENOMEM); | |
9105 | ||
9106 | mode_cmd.width = mode->hdisplay; | |
9107 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9108 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9109 | bpp); | |
5ca0c34a | 9110 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9111 | |
9112 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9113 | } | |
9114 | ||
9115 | static struct drm_framebuffer * | |
9116 | mode_fits_in_fbdev(struct drm_device *dev, | |
9117 | struct drm_display_mode *mode) | |
9118 | { | |
4520f53a | 9119 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9120 | struct drm_i915_private *dev_priv = dev->dev_private; |
9121 | struct drm_i915_gem_object *obj; | |
9122 | struct drm_framebuffer *fb; | |
9123 | ||
4c0e5528 | 9124 | if (!dev_priv->fbdev) |
d2dff872 CW |
9125 | return NULL; |
9126 | ||
4c0e5528 | 9127 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9128 | return NULL; |
9129 | ||
4c0e5528 DV |
9130 | obj = dev_priv->fbdev->fb->obj; |
9131 | BUG_ON(!obj); | |
9132 | ||
8bcd4553 | 9133 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9134 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9135 | fb->bits_per_pixel)) | |
d2dff872 CW |
9136 | return NULL; |
9137 | ||
01f2c773 | 9138 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9139 | return NULL; |
9140 | ||
9141 | return fb; | |
4520f53a DV |
9142 | #else |
9143 | return NULL; | |
9144 | #endif | |
d2dff872 CW |
9145 | } |
9146 | ||
d2434ab7 | 9147 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9148 | struct drm_display_mode *mode, |
51fd371b RC |
9149 | struct intel_load_detect_pipe *old, |
9150 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9151 | { |
9152 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9153 | struct intel_encoder *intel_encoder = |
9154 | intel_attached_encoder(connector); | |
79e53945 | 9155 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9156 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9157 | struct drm_crtc *crtc = NULL; |
9158 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9159 | struct drm_framebuffer *fb; |
51fd371b | 9160 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9161 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9162 | struct drm_connector_state *connector_state; |
51fd371b | 9163 | int ret, i = -1; |
79e53945 | 9164 | |
d2dff872 | 9165 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9166 | connector->base.id, connector->name, |
8e329a03 | 9167 | encoder->base.id, encoder->name); |
d2dff872 | 9168 | |
51fd371b RC |
9169 | retry: |
9170 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9171 | if (ret) | |
9172 | goto fail_unlock; | |
6e9f798d | 9173 | |
79e53945 JB |
9174 | /* |
9175 | * Algorithm gets a little messy: | |
7a5e4805 | 9176 | * |
79e53945 JB |
9177 | * - if the connector already has an assigned crtc, use it (but make |
9178 | * sure it's on first) | |
7a5e4805 | 9179 | * |
79e53945 JB |
9180 | * - try to find the first unused crtc that can drive this connector, |
9181 | * and use that if we find one | |
79e53945 JB |
9182 | */ |
9183 | ||
9184 | /* See if we already have a CRTC for this connector */ | |
9185 | if (encoder->crtc) { | |
9186 | crtc = encoder->crtc; | |
8261b191 | 9187 | |
51fd371b | 9188 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9189 | if (ret) |
9190 | goto fail_unlock; | |
9191 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9192 | if (ret) |
9193 | goto fail_unlock; | |
7b24056b | 9194 | |
24218aac | 9195 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9196 | old->load_detect_temp = false; |
9197 | ||
9198 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9199 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9200 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9201 | |
7173188d | 9202 | return true; |
79e53945 JB |
9203 | } |
9204 | ||
9205 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9206 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9207 | i++; |
9208 | if (!(encoder->possible_crtcs & (1 << i))) | |
9209 | continue; | |
83d65738 | 9210 | if (possible_crtc->state->enable) |
a459249c VS |
9211 | continue; |
9212 | /* This can occur when applying the pipe A quirk on resume. */ | |
9213 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9214 | continue; | |
9215 | ||
9216 | crtc = possible_crtc; | |
9217 | break; | |
79e53945 JB |
9218 | } |
9219 | ||
9220 | /* | |
9221 | * If we didn't find an unused CRTC, don't use any. | |
9222 | */ | |
9223 | if (!crtc) { | |
7173188d | 9224 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9225 | goto fail_unlock; |
79e53945 JB |
9226 | } |
9227 | ||
51fd371b RC |
9228 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9229 | if (ret) | |
4d02e2de DV |
9230 | goto fail_unlock; |
9231 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9232 | if (ret) | |
51fd371b | 9233 | goto fail_unlock; |
fc303101 DV |
9234 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9235 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9236 | |
9237 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9238 | intel_crtc->new_enabled = true; |
24218aac | 9239 | old->dpms_mode = connector->dpms; |
8261b191 | 9240 | old->load_detect_temp = true; |
d2dff872 | 9241 | old->release_fb = NULL; |
79e53945 | 9242 | |
83a57153 ACO |
9243 | state = drm_atomic_state_alloc(dev); |
9244 | if (!state) | |
9245 | return false; | |
9246 | ||
9247 | state->acquire_ctx = ctx; | |
9248 | ||
944b0c76 ACO |
9249 | connector_state = drm_atomic_get_connector_state(state, connector); |
9250 | if (IS_ERR(connector_state)) { | |
9251 | ret = PTR_ERR(connector_state); | |
9252 | goto fail; | |
9253 | } | |
9254 | ||
9255 | connector_state->crtc = crtc; | |
9256 | connector_state->best_encoder = &intel_encoder->base; | |
9257 | ||
6492711d CW |
9258 | if (!mode) |
9259 | mode = &load_detect_mode; | |
79e53945 | 9260 | |
d2dff872 CW |
9261 | /* We need a framebuffer large enough to accommodate all accesses |
9262 | * that the plane may generate whilst we perform load detection. | |
9263 | * We can not rely on the fbcon either being present (we get called | |
9264 | * during its initialisation to detect all boot displays, or it may | |
9265 | * not even exist) or that it is large enough to satisfy the | |
9266 | * requested mode. | |
9267 | */ | |
94352cf9 DV |
9268 | fb = mode_fits_in_fbdev(dev, mode); |
9269 | if (fb == NULL) { | |
d2dff872 | 9270 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9271 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9272 | old->release_fb = fb; | |
d2dff872 CW |
9273 | } else |
9274 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9275 | if (IS_ERR(fb)) { |
d2dff872 | 9276 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9277 | goto fail; |
79e53945 | 9278 | } |
79e53945 | 9279 | |
83a57153 | 9280 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9281 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9282 | if (old->release_fb) |
9283 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9284 | goto fail; |
79e53945 | 9285 | } |
9128b040 | 9286 | crtc->primary->crtc = crtc; |
7173188d | 9287 | |
79e53945 | 9288 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9289 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9290 | return true; |
412b61d8 VS |
9291 | |
9292 | fail: | |
83d65738 | 9293 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9294 | fail_unlock: |
83a57153 ACO |
9295 | if (state) { |
9296 | drm_atomic_state_free(state); | |
9297 | state = NULL; | |
9298 | } | |
9299 | ||
51fd371b RC |
9300 | if (ret == -EDEADLK) { |
9301 | drm_modeset_backoff(ctx); | |
9302 | goto retry; | |
9303 | } | |
9304 | ||
412b61d8 | 9305 | return false; |
79e53945 JB |
9306 | } |
9307 | ||
d2434ab7 | 9308 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9309 | struct intel_load_detect_pipe *old, |
9310 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9311 | { |
83a57153 | 9312 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9313 | struct intel_encoder *intel_encoder = |
9314 | intel_attached_encoder(connector); | |
4ef69c7a | 9315 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9316 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9318 | struct drm_atomic_state *state; |
944b0c76 | 9319 | struct drm_connector_state *connector_state; |
79e53945 | 9320 | |
d2dff872 | 9321 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9322 | connector->base.id, connector->name, |
8e329a03 | 9323 | encoder->base.id, encoder->name); |
d2dff872 | 9324 | |
8261b191 | 9325 | if (old->load_detect_temp) { |
83a57153 | 9326 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9327 | if (!state) |
9328 | goto fail; | |
83a57153 ACO |
9329 | |
9330 | state->acquire_ctx = ctx; | |
9331 | ||
944b0c76 ACO |
9332 | connector_state = drm_atomic_get_connector_state(state, connector); |
9333 | if (IS_ERR(connector_state)) | |
9334 | goto fail; | |
9335 | ||
fc303101 DV |
9336 | to_intel_connector(connector)->new_encoder = NULL; |
9337 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9338 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9339 | |
9340 | connector_state->best_encoder = NULL; | |
9341 | connector_state->crtc = NULL; | |
9342 | ||
83a57153 ACO |
9343 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9344 | ||
9345 | drm_atomic_state_free(state); | |
d2dff872 | 9346 | |
36206361 DV |
9347 | if (old->release_fb) { |
9348 | drm_framebuffer_unregister_private(old->release_fb); | |
9349 | drm_framebuffer_unreference(old->release_fb); | |
9350 | } | |
d2dff872 | 9351 | |
0622a53c | 9352 | return; |
79e53945 JB |
9353 | } |
9354 | ||
c751ce4f | 9355 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9356 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9357 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9358 | |
9359 | return; | |
9360 | fail: | |
9361 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9362 | drm_atomic_state_free(state); | |
79e53945 JB |
9363 | } |
9364 | ||
da4a1efa | 9365 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9366 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9367 | { |
9368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9369 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9370 | ||
9371 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9372 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9373 | else if (HAS_PCH_SPLIT(dev)) |
9374 | return 120000; | |
9375 | else if (!IS_GEN2(dev)) | |
9376 | return 96000; | |
9377 | else | |
9378 | return 48000; | |
9379 | } | |
9380 | ||
79e53945 | 9381 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9382 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9383 | struct intel_crtc_state *pipe_config) |
79e53945 | 9384 | { |
f1f644dc | 9385 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9386 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9387 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9388 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9389 | u32 fp; |
9390 | intel_clock_t clock; | |
da4a1efa | 9391 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9392 | |
9393 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9394 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9395 | else |
293623f7 | 9396 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9397 | |
9398 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9399 | if (IS_PINEVIEW(dev)) { |
9400 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9401 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9402 | } else { |
9403 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9404 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9405 | } | |
9406 | ||
a6c45cf0 | 9407 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9408 | if (IS_PINEVIEW(dev)) |
9409 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9410 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9411 | else |
9412 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9413 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9414 | ||
9415 | switch (dpll & DPLL_MODE_MASK) { | |
9416 | case DPLLB_MODE_DAC_SERIAL: | |
9417 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9418 | 5 : 10; | |
9419 | break; | |
9420 | case DPLLB_MODE_LVDS: | |
9421 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9422 | 7 : 14; | |
9423 | break; | |
9424 | default: | |
28c97730 | 9425 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9426 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9427 | return; |
79e53945 JB |
9428 | } |
9429 | ||
ac58c3f0 | 9430 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9431 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9432 | else |
da4a1efa | 9433 | i9xx_clock(refclk, &clock); |
79e53945 | 9434 | } else { |
0fb58223 | 9435 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9436 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9437 | |
9438 | if (is_lvds) { | |
9439 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9440 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9441 | |
9442 | if (lvds & LVDS_CLKB_POWER_UP) | |
9443 | clock.p2 = 7; | |
9444 | else | |
9445 | clock.p2 = 14; | |
79e53945 JB |
9446 | } else { |
9447 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9448 | clock.p1 = 2; | |
9449 | else { | |
9450 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9451 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9452 | } | |
9453 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9454 | clock.p2 = 4; | |
9455 | else | |
9456 | clock.p2 = 2; | |
79e53945 | 9457 | } |
da4a1efa VS |
9458 | |
9459 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9460 | } |
9461 | ||
18442d08 VS |
9462 | /* |
9463 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9464 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9465 | * encoder's get_config() function. |
9466 | */ | |
9467 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9468 | } |
9469 | ||
6878da05 VS |
9470 | int intel_dotclock_calculate(int link_freq, |
9471 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9472 | { |
f1f644dc JB |
9473 | /* |
9474 | * The calculation for the data clock is: | |
1041a02f | 9475 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9476 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9477 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9478 | * |
9479 | * and the link clock is simpler: | |
1041a02f | 9480 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9481 | */ |
9482 | ||
6878da05 VS |
9483 | if (!m_n->link_n) |
9484 | return 0; | |
f1f644dc | 9485 | |
6878da05 VS |
9486 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9487 | } | |
f1f644dc | 9488 | |
18442d08 | 9489 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9490 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9491 | { |
9492 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9493 | |
18442d08 VS |
9494 | /* read out port_clock from the DPLL */ |
9495 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9496 | |
f1f644dc | 9497 | /* |
18442d08 | 9498 | * This value does not include pixel_multiplier. |
241bfc38 | 9499 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9500 | * agree once we know their relationship in the encoder's |
9501 | * get_config() function. | |
79e53945 | 9502 | */ |
2d112de7 | 9503 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9504 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9505 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9506 | } |
9507 | ||
9508 | /** Returns the currently programmed mode of the given pipe. */ | |
9509 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9510 | struct drm_crtc *crtc) | |
9511 | { | |
548f245b | 9512 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9514 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9515 | struct drm_display_mode *mode; |
5cec258b | 9516 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9517 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9518 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9519 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9520 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9521 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9522 | |
9523 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9524 | if (!mode) | |
9525 | return NULL; | |
9526 | ||
f1f644dc JB |
9527 | /* |
9528 | * Construct a pipe_config sufficient for getting the clock info | |
9529 | * back out of crtc_clock_get. | |
9530 | * | |
9531 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9532 | * to use a real value here instead. | |
9533 | */ | |
293623f7 | 9534 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9535 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9536 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9537 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9538 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9539 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9540 | ||
773ae034 | 9541 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9542 | mode->hdisplay = (htot & 0xffff) + 1; |
9543 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9544 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9545 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9546 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9547 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9548 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9549 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9550 | ||
9551 | drm_mode_set_name(mode); | |
79e53945 JB |
9552 | |
9553 | return mode; | |
9554 | } | |
9555 | ||
652c393a JB |
9556 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
9557 | { | |
9558 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9559 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9560 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9561 | |
baff296c | 9562 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9563 | return; |
9564 | ||
9565 | if (!dev_priv->lvds_downclock_avail) | |
9566 | return; | |
9567 | ||
9568 | /* | |
9569 | * Since this is called by a timer, we should never get here in | |
9570 | * the manual case. | |
9571 | */ | |
9572 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9573 | int pipe = intel_crtc->pipe; |
9574 | int dpll_reg = DPLL(pipe); | |
9575 | int dpll; | |
f6e5b160 | 9576 | |
44d98a61 | 9577 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9578 | |
8ac5a6d5 | 9579 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9580 | |
dc257cf1 | 9581 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9582 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9583 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9584 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9585 | dpll = I915_READ(dpll_reg); |
9586 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9587 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9588 | } |
9589 | ||
9590 | } | |
9591 | ||
f047e395 CW |
9592 | void intel_mark_busy(struct drm_device *dev) |
9593 | { | |
c67a470b PZ |
9594 | struct drm_i915_private *dev_priv = dev->dev_private; |
9595 | ||
f62a0076 CW |
9596 | if (dev_priv->mm.busy) |
9597 | return; | |
9598 | ||
43694d69 | 9599 | intel_runtime_pm_get(dev_priv); |
c67a470b | 9600 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
9601 | if (INTEL_INFO(dev)->gen >= 6) |
9602 | gen6_rps_busy(dev_priv); | |
f62a0076 | 9603 | dev_priv->mm.busy = true; |
f047e395 CW |
9604 | } |
9605 | ||
9606 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 9607 | { |
c67a470b | 9608 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9609 | struct drm_crtc *crtc; |
652c393a | 9610 | |
f62a0076 CW |
9611 | if (!dev_priv->mm.busy) |
9612 | return; | |
9613 | ||
9614 | dev_priv->mm.busy = false; | |
9615 | ||
70e1e0ec | 9616 | for_each_crtc(dev, crtc) { |
f4510a27 | 9617 | if (!crtc->primary->fb) |
652c393a JB |
9618 | continue; |
9619 | ||
725a5b54 | 9620 | intel_decrease_pllclock(crtc); |
652c393a | 9621 | } |
b29c19b6 | 9622 | |
3d13ef2e | 9623 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9624 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 9625 | |
43694d69 | 9626 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9627 | } |
9628 | ||
f5de6e07 ACO |
9629 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
9630 | struct intel_crtc_state *crtc_state) | |
9631 | { | |
9632 | kfree(crtc->config); | |
9633 | crtc->config = crtc_state; | |
16f3f658 | 9634 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
9635 | } |
9636 | ||
79e53945 JB |
9637 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9638 | { | |
9639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9640 | struct drm_device *dev = crtc->dev; |
9641 | struct intel_unpin_work *work; | |
67e77c5a | 9642 | |
5e2d7afc | 9643 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
9644 | work = intel_crtc->unpin_work; |
9645 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 9646 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
9647 | |
9648 | if (work) { | |
9649 | cancel_work_sync(&work->work); | |
9650 | kfree(work); | |
9651 | } | |
79e53945 | 9652 | |
f5de6e07 | 9653 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 9654 | drm_crtc_cleanup(crtc); |
67e77c5a | 9655 | |
79e53945 JB |
9656 | kfree(intel_crtc); |
9657 | } | |
9658 | ||
6b95a207 KH |
9659 | static void intel_unpin_work_fn(struct work_struct *__work) |
9660 | { | |
9661 | struct intel_unpin_work *work = | |
9662 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9663 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9664 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9665 | |
b4a98e57 | 9666 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 9667 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 9668 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 9669 | |
7ff0ebcc | 9670 | intel_fbc_update(dev); |
f06cc1b9 JH |
9671 | |
9672 | if (work->flip_queued_req) | |
146d84f0 | 9673 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
9674 | mutex_unlock(&dev->struct_mutex); |
9675 | ||
f99d7069 | 9676 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 9677 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 9678 | |
b4a98e57 CW |
9679 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9680 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9681 | ||
6b95a207 KH |
9682 | kfree(work); |
9683 | } | |
9684 | ||
1afe3e9d | 9685 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9686 | struct drm_crtc *crtc) |
6b95a207 | 9687 | { |
6b95a207 KH |
9688 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9689 | struct intel_unpin_work *work; | |
6b95a207 KH |
9690 | unsigned long flags; |
9691 | ||
9692 | /* Ignore early vblank irqs */ | |
9693 | if (intel_crtc == NULL) | |
9694 | return; | |
9695 | ||
f326038a DV |
9696 | /* |
9697 | * This is called both by irq handlers and the reset code (to complete | |
9698 | * lost pageflips) so needs the full irqsave spinlocks. | |
9699 | */ | |
6b95a207 KH |
9700 | spin_lock_irqsave(&dev->event_lock, flags); |
9701 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9702 | |
9703 | /* Ensure we don't miss a work->pending update ... */ | |
9704 | smp_rmb(); | |
9705 | ||
9706 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9707 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9708 | return; | |
9709 | } | |
9710 | ||
d6bbafa1 | 9711 | page_flip_completed(intel_crtc); |
0af7e4df | 9712 | |
6b95a207 | 9713 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9714 | } |
9715 | ||
1afe3e9d JB |
9716 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9717 | { | |
fbee40df | 9718 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9719 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9720 | ||
49b14a5c | 9721 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9722 | } |
9723 | ||
9724 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9725 | { | |
fbee40df | 9726 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9727 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9728 | ||
49b14a5c | 9729 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9730 | } |
9731 | ||
75f7f3ec VS |
9732 | /* Is 'a' after or equal to 'b'? */ |
9733 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9734 | { | |
9735 | return !((a - b) & 0x80000000); | |
9736 | } | |
9737 | ||
9738 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9739 | { | |
9740 | struct drm_device *dev = crtc->base.dev; | |
9741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9742 | ||
bdfa7542 VS |
9743 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9744 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9745 | return true; | |
9746 | ||
75f7f3ec VS |
9747 | /* |
9748 | * The relevant registers doen't exist on pre-ctg. | |
9749 | * As the flip done interrupt doesn't trigger for mmio | |
9750 | * flips on gmch platforms, a flip count check isn't | |
9751 | * really needed there. But since ctg has the registers, | |
9752 | * include it in the check anyway. | |
9753 | */ | |
9754 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9755 | return true; | |
9756 | ||
9757 | /* | |
9758 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9759 | * used the same base address. In that case the mmio flip might | |
9760 | * have completed, but the CS hasn't even executed the flip yet. | |
9761 | * | |
9762 | * A flip count check isn't enough as the CS might have updated | |
9763 | * the base address just after start of vblank, but before we | |
9764 | * managed to process the interrupt. This means we'd complete the | |
9765 | * CS flip too soon. | |
9766 | * | |
9767 | * Combining both checks should get us a good enough result. It may | |
9768 | * still happen that the CS flip has been executed, but has not | |
9769 | * yet actually completed. But in case the base address is the same | |
9770 | * anyway, we don't really care. | |
9771 | */ | |
9772 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9773 | crtc->unpin_work->gtt_offset && | |
9774 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9775 | crtc->unpin_work->flip_count); | |
9776 | } | |
9777 | ||
6b95a207 KH |
9778 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9779 | { | |
fbee40df | 9780 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9781 | struct intel_crtc *intel_crtc = |
9782 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9783 | unsigned long flags; | |
9784 | ||
f326038a DV |
9785 | |
9786 | /* | |
9787 | * This is called both by irq handlers and the reset code (to complete | |
9788 | * lost pageflips) so needs the full irqsave spinlocks. | |
9789 | * | |
9790 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9791 | * generate a page-flip completion irq, i.e. every modeset |
9792 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9793 | */ | |
6b95a207 | 9794 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9795 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9796 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9797 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9798 | } | |
9799 | ||
eba905b2 | 9800 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9801 | { |
9802 | /* Ensure that the work item is consistent when activating it ... */ | |
9803 | smp_wmb(); | |
9804 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9805 | /* and that it is marked active as soon as the irq could fire. */ | |
9806 | smp_wmb(); | |
9807 | } | |
9808 | ||
8c9f3aaf JB |
9809 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9810 | struct drm_crtc *crtc, | |
9811 | struct drm_framebuffer *fb, | |
ed8d1975 | 9812 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9813 | struct intel_engine_cs *ring, |
ed8d1975 | 9814 | uint32_t flags) |
8c9f3aaf | 9815 | { |
8c9f3aaf | 9816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9817 | u32 flip_mask; |
9818 | int ret; | |
9819 | ||
6d90c952 | 9820 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9821 | if (ret) |
4fa62c89 | 9822 | return ret; |
8c9f3aaf JB |
9823 | |
9824 | /* Can't queue multiple flips, so wait for the previous | |
9825 | * one to finish before executing the next. | |
9826 | */ | |
9827 | if (intel_crtc->plane) | |
9828 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9829 | else | |
9830 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9831 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9832 | intel_ring_emit(ring, MI_NOOP); | |
9833 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9834 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9835 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9836 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9837 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9838 | |
9839 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9840 | __intel_ring_advance(ring); |
83d4092b | 9841 | return 0; |
8c9f3aaf JB |
9842 | } |
9843 | ||
9844 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9845 | struct drm_crtc *crtc, | |
9846 | struct drm_framebuffer *fb, | |
ed8d1975 | 9847 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9848 | struct intel_engine_cs *ring, |
ed8d1975 | 9849 | uint32_t flags) |
8c9f3aaf | 9850 | { |
8c9f3aaf | 9851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9852 | u32 flip_mask; |
9853 | int ret; | |
9854 | ||
6d90c952 | 9855 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9856 | if (ret) |
4fa62c89 | 9857 | return ret; |
8c9f3aaf JB |
9858 | |
9859 | if (intel_crtc->plane) | |
9860 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9861 | else | |
9862 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9863 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9864 | intel_ring_emit(ring, MI_NOOP); | |
9865 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9866 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9867 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9868 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9869 | intel_ring_emit(ring, MI_NOOP); |
9870 | ||
e7d841ca | 9871 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9872 | __intel_ring_advance(ring); |
83d4092b | 9873 | return 0; |
8c9f3aaf JB |
9874 | } |
9875 | ||
9876 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9877 | struct drm_crtc *crtc, | |
9878 | struct drm_framebuffer *fb, | |
ed8d1975 | 9879 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9880 | struct intel_engine_cs *ring, |
ed8d1975 | 9881 | uint32_t flags) |
8c9f3aaf JB |
9882 | { |
9883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9885 | uint32_t pf, pipesrc; | |
9886 | int ret; | |
9887 | ||
6d90c952 | 9888 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9889 | if (ret) |
4fa62c89 | 9890 | return ret; |
8c9f3aaf JB |
9891 | |
9892 | /* i965+ uses the linear or tiled offsets from the | |
9893 | * Display Registers (which do not change across a page-flip) | |
9894 | * so we need only reprogram the base address. | |
9895 | */ | |
6d90c952 DV |
9896 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9897 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9898 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9899 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9900 | obj->tiling_mode); |
8c9f3aaf JB |
9901 | |
9902 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9903 | * untested on non-native modes, so ignore it for now. | |
9904 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9905 | */ | |
9906 | pf = 0; | |
9907 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9908 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9909 | |
9910 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9911 | __intel_ring_advance(ring); |
83d4092b | 9912 | return 0; |
8c9f3aaf JB |
9913 | } |
9914 | ||
9915 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9916 | struct drm_crtc *crtc, | |
9917 | struct drm_framebuffer *fb, | |
ed8d1975 | 9918 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9919 | struct intel_engine_cs *ring, |
ed8d1975 | 9920 | uint32_t flags) |
8c9f3aaf JB |
9921 | { |
9922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9924 | uint32_t pf, pipesrc; | |
9925 | int ret; | |
9926 | ||
6d90c952 | 9927 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9928 | if (ret) |
4fa62c89 | 9929 | return ret; |
8c9f3aaf | 9930 | |
6d90c952 DV |
9931 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9932 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9933 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9934 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9935 | |
dc257cf1 DV |
9936 | /* Contrary to the suggestions in the documentation, |
9937 | * "Enable Panel Fitter" does not seem to be required when page | |
9938 | * flipping with a non-native mode, and worse causes a normal | |
9939 | * modeset to fail. | |
9940 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9941 | */ | |
9942 | pf = 0; | |
8c9f3aaf | 9943 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9944 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9945 | |
9946 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9947 | __intel_ring_advance(ring); |
83d4092b | 9948 | return 0; |
8c9f3aaf JB |
9949 | } |
9950 | ||
7c9017e5 JB |
9951 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9952 | struct drm_crtc *crtc, | |
9953 | struct drm_framebuffer *fb, | |
ed8d1975 | 9954 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9955 | struct intel_engine_cs *ring, |
ed8d1975 | 9956 | uint32_t flags) |
7c9017e5 | 9957 | { |
7c9017e5 | 9958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9959 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9960 | int len, ret; |
9961 | ||
eba905b2 | 9962 | switch (intel_crtc->plane) { |
cb05d8de DV |
9963 | case PLANE_A: |
9964 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9965 | break; | |
9966 | case PLANE_B: | |
9967 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9968 | break; | |
9969 | case PLANE_C: | |
9970 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9971 | break; | |
9972 | default: | |
9973 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9974 | return -ENODEV; |
cb05d8de DV |
9975 | } |
9976 | ||
ffe74d75 | 9977 | len = 4; |
f476828a | 9978 | if (ring->id == RCS) { |
ffe74d75 | 9979 | len += 6; |
f476828a DL |
9980 | /* |
9981 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9982 | * 48bits addresses, and we need a NOOP for the batch size to | |
9983 | * stay even. | |
9984 | */ | |
9985 | if (IS_GEN8(dev)) | |
9986 | len += 2; | |
9987 | } | |
ffe74d75 | 9988 | |
f66fab8e VS |
9989 | /* |
9990 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9991 | * "The full packet must be contained within the same cache line." | |
9992 | * | |
9993 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9994 | * cacheline, if we ever start emitting more commands before | |
9995 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9996 | * then do the cacheline alignment, and finally emit the | |
9997 | * MI_DISPLAY_FLIP. | |
9998 | */ | |
9999 | ret = intel_ring_cacheline_align(ring); | |
10000 | if (ret) | |
4fa62c89 | 10001 | return ret; |
f66fab8e | 10002 | |
ffe74d75 | 10003 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10004 | if (ret) |
4fa62c89 | 10005 | return ret; |
7c9017e5 | 10006 | |
ffe74d75 CW |
10007 | /* Unmask the flip-done completion message. Note that the bspec says that |
10008 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10009 | * more than one flip event at any time (or ensure that one flip message | |
10010 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10011 | * Experimentation says that BCS works despite DERRMR masking all | |
10012 | * flip-done completion events and that unmasking all planes at once | |
10013 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10014 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10015 | */ | |
10016 | if (ring->id == RCS) { | |
10017 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10018 | intel_ring_emit(ring, DERRMR); | |
10019 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10020 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10021 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10022 | if (IS_GEN8(dev)) |
10023 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10024 | MI_SRM_LRM_GLOBAL_GTT); | |
10025 | else | |
10026 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10027 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10028 | intel_ring_emit(ring, DERRMR); |
10029 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10030 | if (IS_GEN8(dev)) { |
10031 | intel_ring_emit(ring, 0); | |
10032 | intel_ring_emit(ring, MI_NOOP); | |
10033 | } | |
ffe74d75 CW |
10034 | } |
10035 | ||
cb05d8de | 10036 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10037 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10038 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10039 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10040 | |
10041 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10042 | __intel_ring_advance(ring); |
83d4092b | 10043 | return 0; |
7c9017e5 JB |
10044 | } |
10045 | ||
84c33a64 SG |
10046 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10047 | struct drm_i915_gem_object *obj) | |
10048 | { | |
10049 | /* | |
10050 | * This is not being used for older platforms, because | |
10051 | * non-availability of flip done interrupt forces us to use | |
10052 | * CS flips. Older platforms derive flip done using some clever | |
10053 | * tricks involving the flip_pending status bits and vblank irqs. | |
10054 | * So using MMIO flips there would disrupt this mechanism. | |
10055 | */ | |
10056 | ||
8e09bf83 CW |
10057 | if (ring == NULL) |
10058 | return true; | |
10059 | ||
84c33a64 SG |
10060 | if (INTEL_INFO(ring->dev)->gen < 5) |
10061 | return false; | |
10062 | ||
10063 | if (i915.use_mmio_flip < 0) | |
10064 | return false; | |
10065 | else if (i915.use_mmio_flip > 0) | |
10066 | return true; | |
14bf993e OM |
10067 | else if (i915.enable_execlists) |
10068 | return true; | |
84c33a64 | 10069 | else |
41c52415 | 10070 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10071 | } |
10072 | ||
ff944564 DL |
10073 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10074 | { | |
10075 | struct drm_device *dev = intel_crtc->base.dev; | |
10076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10077 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
10078 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
10079 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10080 | const enum pipe pipe = intel_crtc->pipe; | |
10081 | u32 ctl, stride; | |
10082 | ||
10083 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10084 | ctl &= ~PLANE_CTL_TILED_MASK; | |
10085 | if (obj->tiling_mode == I915_TILING_X) | |
10086 | ctl |= PLANE_CTL_TILED_X; | |
10087 | ||
10088 | /* | |
10089 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10090 | * linear buffers or in number of tiles for tiled buffers. | |
10091 | */ | |
10092 | stride = fb->pitches[0] >> 6; | |
10093 | if (obj->tiling_mode == I915_TILING_X) | |
10094 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
10095 | ||
10096 | /* | |
10097 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10098 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10099 | */ | |
10100 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10101 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10102 | ||
10103 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10104 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10105 | } | |
10106 | ||
10107 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10108 | { |
10109 | struct drm_device *dev = intel_crtc->base.dev; | |
10110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10111 | struct intel_framebuffer *intel_fb = | |
10112 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10113 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10114 | u32 dspcntr; | |
10115 | u32 reg; | |
10116 | ||
84c33a64 SG |
10117 | reg = DSPCNTR(intel_crtc->plane); |
10118 | dspcntr = I915_READ(reg); | |
10119 | ||
c5d97472 DL |
10120 | if (obj->tiling_mode != I915_TILING_NONE) |
10121 | dspcntr |= DISPPLANE_TILED; | |
10122 | else | |
10123 | dspcntr &= ~DISPPLANE_TILED; | |
10124 | ||
84c33a64 SG |
10125 | I915_WRITE(reg, dspcntr); |
10126 | ||
10127 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10128 | intel_crtc->unpin_work->gtt_offset); | |
10129 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10130 | |
ff944564 DL |
10131 | } |
10132 | ||
10133 | /* | |
10134 | * XXX: This is the temporary way to update the plane registers until we get | |
10135 | * around to using the usual plane update functions for MMIO flips | |
10136 | */ | |
10137 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10138 | { | |
10139 | struct drm_device *dev = intel_crtc->base.dev; | |
10140 | bool atomic_update; | |
10141 | u32 start_vbl_count; | |
10142 | ||
10143 | intel_mark_page_flip_active(intel_crtc); | |
10144 | ||
10145 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10146 | ||
10147 | if (INTEL_INFO(dev)->gen >= 9) | |
10148 | skl_do_mmio_flip(intel_crtc); | |
10149 | else | |
10150 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10151 | ilk_do_mmio_flip(intel_crtc); | |
10152 | ||
9362c7c5 ACO |
10153 | if (atomic_update) |
10154 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10155 | } |
10156 | ||
9362c7c5 | 10157 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10158 | { |
cc8c4cc2 | 10159 | struct intel_crtc *crtc = |
9362c7c5 | 10160 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 10161 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 10162 | |
cc8c4cc2 JH |
10163 | mmio_flip = &crtc->mmio_flip; |
10164 | if (mmio_flip->req) | |
9c654818 JH |
10165 | WARN_ON(__i915_wait_request(mmio_flip->req, |
10166 | crtc->reset_counter, | |
10167 | false, NULL, NULL) != 0); | |
84c33a64 | 10168 | |
cc8c4cc2 JH |
10169 | intel_do_mmio_flip(crtc); |
10170 | if (mmio_flip->req) { | |
10171 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 10172 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
10173 | mutex_unlock(&crtc->base.dev->struct_mutex); |
10174 | } | |
84c33a64 SG |
10175 | } |
10176 | ||
10177 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10178 | struct drm_crtc *crtc, | |
10179 | struct drm_framebuffer *fb, | |
10180 | struct drm_i915_gem_object *obj, | |
10181 | struct intel_engine_cs *ring, | |
10182 | uint32_t flags) | |
10183 | { | |
84c33a64 | 10184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 10185 | |
cc8c4cc2 JH |
10186 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
10187 | obj->last_write_req); | |
536f5b5e ACO |
10188 | |
10189 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 10190 | |
84c33a64 SG |
10191 | return 0; |
10192 | } | |
10193 | ||
8c9f3aaf JB |
10194 | static int intel_default_queue_flip(struct drm_device *dev, |
10195 | struct drm_crtc *crtc, | |
10196 | struct drm_framebuffer *fb, | |
ed8d1975 | 10197 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10198 | struct intel_engine_cs *ring, |
ed8d1975 | 10199 | uint32_t flags) |
8c9f3aaf JB |
10200 | { |
10201 | return -ENODEV; | |
10202 | } | |
10203 | ||
d6bbafa1 CW |
10204 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10205 | struct drm_crtc *crtc) | |
10206 | { | |
10207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10209 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10210 | u32 addr; | |
10211 | ||
10212 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10213 | return true; | |
10214 | ||
10215 | if (!work->enable_stall_check) | |
10216 | return false; | |
10217 | ||
10218 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10219 | if (work->flip_queued_req && |
10220 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10221 | return false; |
10222 | ||
1e3feefd | 10223 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10224 | } |
10225 | ||
1e3feefd | 10226 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10227 | return false; |
10228 | ||
10229 | /* Potential stall - if we see that the flip has happened, | |
10230 | * assume a missed interrupt. */ | |
10231 | if (INTEL_INFO(dev)->gen >= 4) | |
10232 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10233 | else | |
10234 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10235 | ||
10236 | /* There is a potential issue here with a false positive after a flip | |
10237 | * to the same address. We could address this by checking for a | |
10238 | * non-incrementing frame counter. | |
10239 | */ | |
10240 | return addr == work->gtt_offset; | |
10241 | } | |
10242 | ||
10243 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10244 | { | |
10245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10246 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10248 | struct intel_unpin_work *work; |
f326038a | 10249 | |
6c51d46f | 10250 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10251 | |
10252 | if (crtc == NULL) | |
10253 | return; | |
10254 | ||
f326038a | 10255 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10256 | work = intel_crtc->unpin_work; |
10257 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10258 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10259 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10260 | page_flip_completed(intel_crtc); |
6ad790c0 | 10261 | work = NULL; |
d6bbafa1 | 10262 | } |
6ad790c0 CW |
10263 | if (work != NULL && |
10264 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10265 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10266 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10267 | } |
10268 | ||
6b95a207 KH |
10269 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10270 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10271 | struct drm_pending_vblank_event *event, |
10272 | uint32_t page_flip_flags) | |
6b95a207 KH |
10273 | { |
10274 | struct drm_device *dev = crtc->dev; | |
10275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10276 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10277 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10279 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10280 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10281 | struct intel_unpin_work *work; |
a4872ba6 | 10282 | struct intel_engine_cs *ring; |
cf5d8a46 | 10283 | bool mmio_flip; |
52e68630 | 10284 | int ret; |
6b95a207 | 10285 | |
2ff8fde1 MR |
10286 | /* |
10287 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10288 | * check to be safe. In the future we may enable pageflipping from | |
10289 | * a disabled primary plane. | |
10290 | */ | |
10291 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10292 | return -EBUSY; | |
10293 | ||
e6a595d2 | 10294 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10295 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10296 | return -EINVAL; |
10297 | ||
10298 | /* | |
10299 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10300 | * Note that pitch changes could also affect these register. | |
10301 | */ | |
10302 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10303 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10304 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10305 | return -EINVAL; |
10306 | ||
f900db47 CW |
10307 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10308 | goto out_hang; | |
10309 | ||
b14c5679 | 10310 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10311 | if (work == NULL) |
10312 | return -ENOMEM; | |
10313 | ||
6b95a207 | 10314 | work->event = event; |
b4a98e57 | 10315 | work->crtc = crtc; |
ab8d6675 | 10316 | work->old_fb = old_fb; |
6b95a207 KH |
10317 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10318 | ||
87b6b101 | 10319 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10320 | if (ret) |
10321 | goto free_work; | |
10322 | ||
6b95a207 | 10323 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10324 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10325 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10326 | /* Before declaring the flip queue wedged, check if |
10327 | * the hardware completed the operation behind our backs. | |
10328 | */ | |
10329 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10330 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10331 | page_flip_completed(intel_crtc); | |
10332 | } else { | |
10333 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10334 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10335 | |
d6bbafa1 CW |
10336 | drm_crtc_vblank_put(crtc); |
10337 | kfree(work); | |
10338 | return -EBUSY; | |
10339 | } | |
6b95a207 KH |
10340 | } |
10341 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10342 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10343 | |
b4a98e57 CW |
10344 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10345 | flush_workqueue(dev_priv->wq); | |
10346 | ||
75dfca80 | 10347 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10348 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10349 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10350 | |
f4510a27 | 10351 | crtc->primary->fb = fb; |
afd65eb4 | 10352 | update_state_fb(crtc->primary); |
1ed1f968 | 10353 | |
e1f99ce6 | 10354 | work->pending_flip_obj = obj; |
e1f99ce6 | 10355 | |
89ed88ba CW |
10356 | ret = i915_mutex_lock_interruptible(dev); |
10357 | if (ret) | |
10358 | goto cleanup; | |
10359 | ||
b4a98e57 | 10360 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10361 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10362 | |
75f7f3ec | 10363 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10364 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10365 | |
4fa62c89 VS |
10366 | if (IS_VALLEYVIEW(dev)) { |
10367 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10368 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10369 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10370 | ring = NULL; | |
48bf5b2d | 10371 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10372 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10373 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10374 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10375 | if (ring == NULL || ring->id != RCS) |
10376 | ring = &dev_priv->ring[BCS]; | |
10377 | } else { | |
10378 | ring = &dev_priv->ring[RCS]; | |
10379 | } | |
10380 | ||
cf5d8a46 CW |
10381 | mmio_flip = use_mmio_flip(ring, obj); |
10382 | ||
10383 | /* When using CS flips, we want to emit semaphores between rings. | |
10384 | * However, when using mmio flips we will create a task to do the | |
10385 | * synchronisation, so all we want here is to pin the framebuffer | |
10386 | * into the display plane and skip any waits. | |
10387 | */ | |
82bc3b2d | 10388 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
10389 | crtc->primary->state, |
10390 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
10391 | if (ret) |
10392 | goto cleanup_pending; | |
6b95a207 | 10393 | |
121920fa TU |
10394 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10395 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10396 | |
cf5d8a46 | 10397 | if (mmio_flip) { |
84c33a64 SG |
10398 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10399 | page_flip_flags); | |
d6bbafa1 CW |
10400 | if (ret) |
10401 | goto cleanup_unpin; | |
10402 | ||
f06cc1b9 JH |
10403 | i915_gem_request_assign(&work->flip_queued_req, |
10404 | obj->last_write_req); | |
d6bbafa1 | 10405 | } else { |
84c33a64 | 10406 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10407 | page_flip_flags); |
10408 | if (ret) | |
10409 | goto cleanup_unpin; | |
10410 | ||
f06cc1b9 JH |
10411 | i915_gem_request_assign(&work->flip_queued_req, |
10412 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10413 | } |
10414 | ||
1e3feefd | 10415 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10416 | work->enable_stall_check = true; |
4fa62c89 | 10417 | |
ab8d6675 | 10418 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10419 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10420 | ||
7ff0ebcc | 10421 | intel_fbc_disable(dev); |
f99d7069 | 10422 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10423 | mutex_unlock(&dev->struct_mutex); |
10424 | ||
e5510fac JB |
10425 | trace_i915_flip_request(intel_crtc->plane, obj); |
10426 | ||
6b95a207 | 10427 | return 0; |
96b099fd | 10428 | |
4fa62c89 | 10429 | cleanup_unpin: |
82bc3b2d | 10430 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10431 | cleanup_pending: |
b4a98e57 | 10432 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10433 | mutex_unlock(&dev->struct_mutex); |
10434 | cleanup: | |
f4510a27 | 10435 | crtc->primary->fb = old_fb; |
afd65eb4 | 10436 | update_state_fb(crtc->primary); |
89ed88ba CW |
10437 | |
10438 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10439 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10440 | |
5e2d7afc | 10441 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10442 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10443 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10444 | |
87b6b101 | 10445 | drm_crtc_vblank_put(crtc); |
7317c75e | 10446 | free_work: |
96b099fd CW |
10447 | kfree(work); |
10448 | ||
f900db47 CW |
10449 | if (ret == -EIO) { |
10450 | out_hang: | |
53a366b9 | 10451 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10452 | if (ret == 0 && event) { |
5e2d7afc | 10453 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10454 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10455 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10456 | } |
f900db47 | 10457 | } |
96b099fd | 10458 | return ret; |
6b95a207 KH |
10459 | } |
10460 | ||
f6e5b160 | 10461 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10462 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10463 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10464 | .atomic_begin = intel_begin_crtc_commit, |
10465 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10466 | }; |
10467 | ||
9a935856 DV |
10468 | /** |
10469 | * intel_modeset_update_staged_output_state | |
10470 | * | |
10471 | * Updates the staged output configuration state, e.g. after we've read out the | |
10472 | * current hw state. | |
10473 | */ | |
10474 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10475 | { |
7668851f | 10476 | struct intel_crtc *crtc; |
9a935856 DV |
10477 | struct intel_encoder *encoder; |
10478 | struct intel_connector *connector; | |
f6e5b160 | 10479 | |
3a3371ff | 10480 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10481 | connector->new_encoder = |
10482 | to_intel_encoder(connector->base.encoder); | |
10483 | } | |
f6e5b160 | 10484 | |
b2784e15 | 10485 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10486 | encoder->new_crtc = |
10487 | to_intel_crtc(encoder->base.crtc); | |
10488 | } | |
7668851f | 10489 | |
d3fcc808 | 10490 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10491 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 10492 | } |
f6e5b160 CW |
10493 | } |
10494 | ||
d29b2f9d ACO |
10495 | /* Transitional helper to copy current connector/encoder state to |
10496 | * connector->state. This is needed so that code that is partially | |
10497 | * converted to atomic does the right thing. | |
10498 | */ | |
10499 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
10500 | { | |
10501 | struct intel_connector *connector; | |
10502 | ||
10503 | for_each_intel_connector(dev, connector) { | |
10504 | if (connector->base.encoder) { | |
10505 | connector->base.state->best_encoder = | |
10506 | connector->base.encoder; | |
10507 | connector->base.state->crtc = | |
10508 | connector->base.encoder->crtc; | |
10509 | } else { | |
10510 | connector->base.state->best_encoder = NULL; | |
10511 | connector->base.state->crtc = NULL; | |
10512 | } | |
10513 | } | |
10514 | } | |
10515 | ||
9a935856 DV |
10516 | /** |
10517 | * intel_modeset_commit_output_state | |
10518 | * | |
10519 | * This function copies the stage display pipe configuration to the real one. | |
10520 | */ | |
10521 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10522 | { | |
7668851f | 10523 | struct intel_crtc *crtc; |
9a935856 DV |
10524 | struct intel_encoder *encoder; |
10525 | struct intel_connector *connector; | |
f6e5b160 | 10526 | |
3a3371ff | 10527 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10528 | connector->base.encoder = &connector->new_encoder->base; |
10529 | } | |
f6e5b160 | 10530 | |
b2784e15 | 10531 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10532 | encoder->base.crtc = &encoder->new_crtc->base; |
10533 | } | |
7668851f | 10534 | |
d3fcc808 | 10535 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10536 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10537 | crtc->base.enabled = crtc->new_enabled; |
10538 | } | |
d29b2f9d ACO |
10539 | |
10540 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
10541 | } |
10542 | ||
050f7aeb | 10543 | static void |
eba905b2 | 10544 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10545 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
10546 | { |
10547 | int bpp = pipe_config->pipe_bpp; | |
10548 | ||
10549 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10550 | connector->base.base.id, | |
c23cc417 | 10551 | connector->base.name); |
050f7aeb DV |
10552 | |
10553 | /* Don't use an invalid EDID bpc value */ | |
10554 | if (connector->base.display_info.bpc && | |
10555 | connector->base.display_info.bpc * 3 < bpp) { | |
10556 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10557 | bpp, connector->base.display_info.bpc*3); | |
10558 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10559 | } | |
10560 | ||
10561 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10562 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10563 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10564 | bpp); | |
10565 | pipe_config->pipe_bpp = 24; | |
10566 | } | |
10567 | } | |
10568 | ||
4e53c2e0 | 10569 | static int |
050f7aeb DV |
10570 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10571 | struct drm_framebuffer *fb, | |
5cec258b | 10572 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10573 | { |
050f7aeb | 10574 | struct drm_device *dev = crtc->base.dev; |
1486017f | 10575 | struct drm_atomic_state *state; |
050f7aeb | 10576 | struct intel_connector *connector; |
1486017f | 10577 | int bpp, i; |
4e53c2e0 | 10578 | |
d42264b1 DV |
10579 | switch (fb->pixel_format) { |
10580 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10581 | bpp = 8*3; /* since we go through a colormap */ |
10582 | break; | |
d42264b1 DV |
10583 | case DRM_FORMAT_XRGB1555: |
10584 | case DRM_FORMAT_ARGB1555: | |
10585 | /* checked in intel_framebuffer_init already */ | |
10586 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10587 | return -EINVAL; | |
10588 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10589 | bpp = 6*3; /* min is 18bpp */ |
10590 | break; | |
d42264b1 DV |
10591 | case DRM_FORMAT_XBGR8888: |
10592 | case DRM_FORMAT_ABGR8888: | |
10593 | /* checked in intel_framebuffer_init already */ | |
10594 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10595 | return -EINVAL; | |
10596 | case DRM_FORMAT_XRGB8888: | |
10597 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10598 | bpp = 8*3; |
10599 | break; | |
d42264b1 DV |
10600 | case DRM_FORMAT_XRGB2101010: |
10601 | case DRM_FORMAT_ARGB2101010: | |
10602 | case DRM_FORMAT_XBGR2101010: | |
10603 | case DRM_FORMAT_ABGR2101010: | |
10604 | /* checked in intel_framebuffer_init already */ | |
10605 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10606 | return -EINVAL; |
4e53c2e0 DV |
10607 | bpp = 10*3; |
10608 | break; | |
baba133a | 10609 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10610 | default: |
10611 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10612 | return -EINVAL; | |
10613 | } | |
10614 | ||
4e53c2e0 DV |
10615 | pipe_config->pipe_bpp = bpp; |
10616 | ||
1486017f ACO |
10617 | state = pipe_config->base.state; |
10618 | ||
4e53c2e0 | 10619 | /* Clamp display bpp to EDID value */ |
1486017f ACO |
10620 | for (i = 0; i < state->num_connector; i++) { |
10621 | if (!state->connectors[i]) | |
10622 | continue; | |
10623 | ||
10624 | connector = to_intel_connector(state->connectors[i]); | |
10625 | if (state->connector_states[i]->crtc != &crtc->base) | |
4e53c2e0 DV |
10626 | continue; |
10627 | ||
050f7aeb | 10628 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10629 | } |
10630 | ||
10631 | return bpp; | |
10632 | } | |
10633 | ||
644db711 DV |
10634 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10635 | { | |
10636 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10637 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10638 | mode->crtc_clock, |
644db711 DV |
10639 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10640 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10641 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10642 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10643 | } | |
10644 | ||
c0b03411 | 10645 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10646 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10647 | const char *context) |
10648 | { | |
6a60cd87 CK |
10649 | struct drm_device *dev = crtc->base.dev; |
10650 | struct drm_plane *plane; | |
10651 | struct intel_plane *intel_plane; | |
10652 | struct intel_plane_state *state; | |
10653 | struct drm_framebuffer *fb; | |
10654 | ||
10655 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
10656 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
10657 | |
10658 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10659 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10660 | pipe_config->pipe_bpp, pipe_config->dither); | |
10661 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10662 | pipe_config->has_pch_encoder, | |
10663 | pipe_config->fdi_lanes, | |
10664 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10665 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10666 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10667 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10668 | pipe_config->has_dp_encoder, | |
10669 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10670 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10671 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10672 | |
10673 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10674 | pipe_config->has_dp_encoder, | |
10675 | pipe_config->dp_m2_n2.gmch_m, | |
10676 | pipe_config->dp_m2_n2.gmch_n, | |
10677 | pipe_config->dp_m2_n2.link_m, | |
10678 | pipe_config->dp_m2_n2.link_n, | |
10679 | pipe_config->dp_m2_n2.tu); | |
10680 | ||
55072d19 DV |
10681 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
10682 | pipe_config->has_audio, | |
10683 | pipe_config->has_infoframe); | |
10684 | ||
c0b03411 | 10685 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10686 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10687 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10688 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10689 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 10690 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10691 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10692 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
6a60cd87 CK |
10693 | DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); |
10694 | DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); | |
10695 | DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
10696 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10697 | pipe_config->gmch_pfit.control, | |
10698 | pipe_config->gmch_pfit.pgm_ratios, | |
10699 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10700 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10701 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10702 | pipe_config->pch_pfit.size, |
10703 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10704 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10705 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 CK |
10706 | |
10707 | DRM_DEBUG_KMS("planes on this crtc\n"); | |
10708 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
10709 | intel_plane = to_intel_plane(plane); | |
10710 | if (intel_plane->pipe != crtc->pipe) | |
10711 | continue; | |
10712 | ||
10713 | state = to_intel_plane_state(plane->state); | |
10714 | fb = state->base.fb; | |
10715 | if (!fb) { | |
10716 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
10717 | "disabled, scaler_id = %d\n", | |
10718 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
10719 | plane->base.id, intel_plane->pipe, | |
10720 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
10721 | drm_plane_index(plane), state->scaler_id); | |
10722 | continue; | |
10723 | } | |
10724 | ||
10725 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
10726 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
10727 | plane->base.id, intel_plane->pipe, | |
10728 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
10729 | drm_plane_index(plane)); | |
10730 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
10731 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
10732 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
10733 | state->scaler_id, | |
10734 | state->src.x1 >> 16, state->src.y1 >> 16, | |
10735 | drm_rect_width(&state->src) >> 16, | |
10736 | drm_rect_height(&state->src) >> 16, | |
10737 | state->dst.x1, state->dst.y1, | |
10738 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
10739 | } | |
c0b03411 DV |
10740 | } |
10741 | ||
bc079e8b VS |
10742 | static bool encoders_cloneable(const struct intel_encoder *a, |
10743 | const struct intel_encoder *b) | |
accfc0c5 | 10744 | { |
bc079e8b VS |
10745 | /* masks could be asymmetric, so check both ways */ |
10746 | return a == b || (a->cloneable & (1 << b->type) && | |
10747 | b->cloneable & (1 << a->type)); | |
10748 | } | |
10749 | ||
98a221da ACO |
10750 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
10751 | struct intel_crtc *crtc, | |
bc079e8b VS |
10752 | struct intel_encoder *encoder) |
10753 | { | |
bc079e8b | 10754 | struct intel_encoder *source_encoder; |
98a221da ACO |
10755 | struct drm_connector_state *connector_state; |
10756 | int i; | |
10757 | ||
10758 | for (i = 0; i < state->num_connector; i++) { | |
10759 | if (!state->connectors[i]) | |
10760 | continue; | |
bc079e8b | 10761 | |
98a221da ACO |
10762 | connector_state = state->connector_states[i]; |
10763 | if (connector_state->crtc != &crtc->base) | |
bc079e8b VS |
10764 | continue; |
10765 | ||
98a221da ACO |
10766 | source_encoder = |
10767 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
10768 | if (!encoders_cloneable(encoder, source_encoder)) |
10769 | return false; | |
10770 | } | |
10771 | ||
10772 | return true; | |
10773 | } | |
10774 | ||
98a221da ACO |
10775 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
10776 | struct intel_crtc *crtc) | |
bc079e8b | 10777 | { |
accfc0c5 | 10778 | struct intel_encoder *encoder; |
98a221da ACO |
10779 | struct drm_connector_state *connector_state; |
10780 | int i; | |
accfc0c5 | 10781 | |
98a221da ACO |
10782 | for (i = 0; i < state->num_connector; i++) { |
10783 | if (!state->connectors[i]) | |
accfc0c5 DV |
10784 | continue; |
10785 | ||
98a221da ACO |
10786 | connector_state = state->connector_states[i]; |
10787 | if (connector_state->crtc != &crtc->base) | |
10788 | continue; | |
10789 | ||
10790 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10791 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 10792 | return false; |
accfc0c5 DV |
10793 | } |
10794 | ||
bc079e8b | 10795 | return true; |
accfc0c5 DV |
10796 | } |
10797 | ||
5448a00d | 10798 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10799 | { |
5448a00d ACO |
10800 | struct drm_device *dev = state->dev; |
10801 | struct intel_encoder *encoder; | |
10802 | struct drm_connector_state *connector_state; | |
00f0b378 | 10803 | unsigned int used_ports = 0; |
5448a00d | 10804 | int i; |
00f0b378 VS |
10805 | |
10806 | /* | |
10807 | * Walk the connector list instead of the encoder | |
10808 | * list to detect the problem on ddi platforms | |
10809 | * where there's just one encoder per digital port. | |
10810 | */ | |
5448a00d ACO |
10811 | for (i = 0; i < state->num_connector; i++) { |
10812 | if (!state->connectors[i]) | |
10813 | continue; | |
00f0b378 | 10814 | |
5448a00d ACO |
10815 | connector_state = state->connector_states[i]; |
10816 | if (!connector_state->best_encoder) | |
00f0b378 VS |
10817 | continue; |
10818 | ||
5448a00d ACO |
10819 | encoder = to_intel_encoder(connector_state->best_encoder); |
10820 | ||
10821 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10822 | |
10823 | switch (encoder->type) { | |
10824 | unsigned int port_mask; | |
10825 | case INTEL_OUTPUT_UNKNOWN: | |
10826 | if (WARN_ON(!HAS_DDI(dev))) | |
10827 | break; | |
10828 | case INTEL_OUTPUT_DISPLAYPORT: | |
10829 | case INTEL_OUTPUT_HDMI: | |
10830 | case INTEL_OUTPUT_EDP: | |
10831 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10832 | ||
10833 | /* the same port mustn't appear more than once */ | |
10834 | if (used_ports & port_mask) | |
10835 | return false; | |
10836 | ||
10837 | used_ports |= port_mask; | |
10838 | default: | |
10839 | break; | |
10840 | } | |
10841 | } | |
10842 | ||
10843 | return true; | |
10844 | } | |
10845 | ||
83a57153 ACO |
10846 | static void |
10847 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10848 | { | |
10849 | struct drm_crtc_state tmp_state; | |
663a3640 | 10850 | struct intel_crtc_scaler_state scaler_state; |
83a57153 | 10851 | |
663a3640 | 10852 | /* Clear only the intel specific part of the crtc state excluding scalers */ |
83a57153 | 10853 | tmp_state = crtc_state->base; |
663a3640 | 10854 | scaler_state = crtc_state->scaler_state; |
83a57153 ACO |
10855 | memset(crtc_state, 0, sizeof *crtc_state); |
10856 | crtc_state->base = tmp_state; | |
663a3640 | 10857 | crtc_state->scaler_state = scaler_state; |
83a57153 ACO |
10858 | } |
10859 | ||
5cec258b | 10860 | static struct intel_crtc_state * |
b8cecdf5 | 10861 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
4e53c2e0 | 10862 | struct drm_framebuffer *fb, |
83a57153 ACO |
10863 | struct drm_display_mode *mode, |
10864 | struct drm_atomic_state *state) | |
ee7b9f93 | 10865 | { |
7758a113 | 10866 | struct intel_encoder *encoder; |
0b901879 ACO |
10867 | struct intel_connector *connector; |
10868 | struct drm_connector_state *connector_state; | |
5cec258b | 10869 | struct intel_crtc_state *pipe_config; |
e29c22c0 | 10870 | int plane_bpp, ret = -EINVAL; |
0b901879 | 10871 | int i; |
e29c22c0 | 10872 | bool retry = true; |
ee7b9f93 | 10873 | |
98a221da | 10874 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 DV |
10875 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10876 | return ERR_PTR(-EINVAL); | |
10877 | } | |
10878 | ||
5448a00d | 10879 | if (!check_digital_port_conflicts(state)) { |
00f0b378 VS |
10880 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
10881 | return ERR_PTR(-EINVAL); | |
10882 | } | |
10883 | ||
83a57153 ACO |
10884 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
10885 | if (IS_ERR(pipe_config)) | |
10886 | return pipe_config; | |
10887 | ||
10888 | clear_intel_crtc_state(pipe_config); | |
7758a113 | 10889 | |
07878248 | 10890 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
10891 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
10892 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 10893 | |
e143a21c DV |
10894 | pipe_config->cpu_transcoder = |
10895 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10896 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10897 | |
2960bc9c ID |
10898 | /* |
10899 | * Sanitize sync polarity flags based on requested ones. If neither | |
10900 | * positive or negative polarity is requested, treat this as meaning | |
10901 | * negative polarity. | |
10902 | */ | |
2d112de7 | 10903 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10904 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10905 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10906 | |
2d112de7 | 10907 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10908 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10909 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10910 | |
050f7aeb DV |
10911 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10912 | * plane pixel format and any sink constraints into account. Returns the | |
10913 | * source plane bpp so that dithering can be selected on mismatches | |
10914 | * after encoders and crtc also have had their say. */ | |
10915 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10916 | fb, pipe_config); | |
4e53c2e0 DV |
10917 | if (plane_bpp < 0) |
10918 | goto fail; | |
10919 | ||
e41a56be VS |
10920 | /* |
10921 | * Determine the real pipe dimensions. Note that stereo modes can | |
10922 | * increase the actual pipe size due to the frame doubling and | |
10923 | * insertion of additional space for blanks between the frame. This | |
10924 | * is stored in the crtc timings. We use the requested mode to do this | |
10925 | * computation to clearly distinguish it from the adjusted mode, which | |
10926 | * can be changed by the connectors in the below retry loop. | |
10927 | */ | |
2d112de7 | 10928 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10929 | &pipe_config->pipe_src_w, |
10930 | &pipe_config->pipe_src_h); | |
e41a56be | 10931 | |
e29c22c0 | 10932 | encoder_retry: |
ef1b460d | 10933 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10934 | pipe_config->port_clock = 0; |
ef1b460d | 10935 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10936 | |
135c81b8 | 10937 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10938 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10939 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10940 | |
7758a113 DV |
10941 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10942 | * adjust it according to limitations or connector properties, and also | |
10943 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10944 | */ |
0b901879 ACO |
10945 | for (i = 0; i < state->num_connector; i++) { |
10946 | connector = to_intel_connector(state->connectors[i]); | |
10947 | if (!connector) | |
10948 | continue; | |
47f1c6c9 | 10949 | |
0b901879 ACO |
10950 | connector_state = state->connector_states[i]; |
10951 | if (connector_state->crtc != crtc) | |
7758a113 | 10952 | continue; |
7ae89233 | 10953 | |
0b901879 ACO |
10954 | encoder = to_intel_encoder(connector_state->best_encoder); |
10955 | ||
efea6e8e DV |
10956 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10957 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10958 | goto fail; |
10959 | } | |
ee7b9f93 | 10960 | } |
47f1c6c9 | 10961 | |
ff9a6750 DV |
10962 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10963 | * done afterwards in case the encoder adjusts the mode. */ | |
10964 | if (!pipe_config->port_clock) | |
2d112de7 | 10965 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10966 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10967 | |
a43f6e0f | 10968 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10969 | if (ret < 0) { |
7758a113 DV |
10970 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10971 | goto fail; | |
ee7b9f93 | 10972 | } |
e29c22c0 DV |
10973 | |
10974 | if (ret == RETRY) { | |
10975 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10976 | ret = -EINVAL; | |
10977 | goto fail; | |
10978 | } | |
10979 | ||
10980 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10981 | retry = false; | |
10982 | goto encoder_retry; | |
10983 | } | |
10984 | ||
4e53c2e0 DV |
10985 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10986 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10987 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10988 | ||
b8cecdf5 | 10989 | return pipe_config; |
7758a113 | 10990 | fail: |
e29c22c0 | 10991 | return ERR_PTR(ret); |
ee7b9f93 | 10992 | } |
47f1c6c9 | 10993 | |
e2e1ed41 DV |
10994 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10995 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10996 | static void | |
10997 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10998 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10999 | { |
11000 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
11001 | struct drm_device *dev = crtc->dev; |
11002 | struct intel_encoder *encoder; | |
11003 | struct intel_connector *connector; | |
11004 | struct drm_crtc *tmp_crtc; | |
79e53945 | 11005 | |
e2e1ed41 | 11006 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 11007 | |
e2e1ed41 DV |
11008 | /* Check which crtcs have changed outputs connected to them, these need |
11009 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
11010 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
11011 | * bit set at most. */ | |
3a3371ff | 11012 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
11013 | if (connector->base.encoder == &connector->new_encoder->base) |
11014 | continue; | |
79e53945 | 11015 | |
e2e1ed41 DV |
11016 | if (connector->base.encoder) { |
11017 | tmp_crtc = connector->base.encoder->crtc; | |
11018 | ||
11019 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11020 | } | |
11021 | ||
11022 | if (connector->new_encoder) | |
11023 | *prepare_pipes |= | |
11024 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
11025 | } |
11026 | ||
b2784e15 | 11027 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
11028 | if (encoder->base.crtc == &encoder->new_crtc->base) |
11029 | continue; | |
11030 | ||
11031 | if (encoder->base.crtc) { | |
11032 | tmp_crtc = encoder->base.crtc; | |
11033 | ||
11034 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11035 | } | |
11036 | ||
11037 | if (encoder->new_crtc) | |
11038 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
11039 | } |
11040 | ||
7668851f | 11041 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 11042 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11043 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 11044 | continue; |
7e7d76c3 | 11045 | |
7668851f | 11046 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 11047 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
11048 | else |
11049 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
11050 | } |
11051 | ||
e2e1ed41 DV |
11052 | |
11053 | /* set_mode is also used to update properties on life display pipes. */ | |
11054 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 11055 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
11056 | *prepare_pipes |= 1 << intel_crtc->pipe; |
11057 | ||
b6c5164d DV |
11058 | /* |
11059 | * For simplicity do a full modeset on any pipe where the output routing | |
11060 | * changed. We could be more clever, but that would require us to be | |
11061 | * more careful with calling the relevant encoder->mode_set functions. | |
11062 | */ | |
e2e1ed41 DV |
11063 | if (*prepare_pipes) |
11064 | *modeset_pipes = *prepare_pipes; | |
11065 | ||
11066 | /* ... and mask these out. */ | |
11067 | *modeset_pipes &= ~(*disable_pipes); | |
11068 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
11069 | |
11070 | /* | |
11071 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
11072 | * obies this rule, but the modeset restore mode of | |
11073 | * intel_modeset_setup_hw_state does not. | |
11074 | */ | |
11075 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
11076 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
11077 | |
11078 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
11079 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 11080 | } |
79e53945 | 11081 | |
ea9d758d | 11082 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11083 | { |
ea9d758d | 11084 | struct drm_encoder *encoder; |
f6e5b160 | 11085 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11086 | |
ea9d758d DV |
11087 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11088 | if (encoder->crtc == crtc) | |
11089 | return true; | |
11090 | ||
11091 | return false; | |
11092 | } | |
11093 | ||
11094 | static void | |
11095 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
11096 | { | |
ba41c0de | 11097 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
11098 | struct intel_encoder *intel_encoder; |
11099 | struct intel_crtc *intel_crtc; | |
11100 | struct drm_connector *connector; | |
11101 | ||
ba41c0de DV |
11102 | intel_shared_dpll_commit(dev_priv); |
11103 | ||
b2784e15 | 11104 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11105 | if (!intel_encoder->base.crtc) |
11106 | continue; | |
11107 | ||
11108 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
11109 | ||
11110 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
11111 | intel_encoder->connectors_active = false; | |
11112 | } | |
11113 | ||
11114 | intel_modeset_commit_output_state(dev); | |
11115 | ||
7668851f | 11116 | /* Double check state. */ |
d3fcc808 | 11117 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11118 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
ea9d758d DV |
11119 | } |
11120 | ||
11121 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11122 | if (!connector->encoder || !connector->encoder->crtc) | |
11123 | continue; | |
11124 | ||
11125 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
11126 | ||
11127 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
11128 | struct drm_property *dpms_property = |
11129 | dev->mode_config.dpms_property; | |
11130 | ||
ea9d758d | 11131 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11132 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11133 | dpms_property, |
11134 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11135 | |
11136 | intel_encoder = to_intel_encoder(connector->encoder); | |
11137 | intel_encoder->connectors_active = true; | |
11138 | } | |
11139 | } | |
11140 | ||
11141 | } | |
11142 | ||
3bd26263 | 11143 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11144 | { |
3bd26263 | 11145 | int diff; |
f1f644dc JB |
11146 | |
11147 | if (clock1 == clock2) | |
11148 | return true; | |
11149 | ||
11150 | if (!clock1 || !clock2) | |
11151 | return false; | |
11152 | ||
11153 | diff = abs(clock1 - clock2); | |
11154 | ||
11155 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11156 | return true; | |
11157 | ||
11158 | return false; | |
11159 | } | |
11160 | ||
25c5b266 DV |
11161 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11162 | list_for_each_entry((intel_crtc), \ | |
11163 | &(dev)->mode_config.crtc_list, \ | |
11164 | base.head) \ | |
0973f18f | 11165 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11166 | |
0e8ffe1b | 11167 | static bool |
2fa2fe9a | 11168 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11169 | struct intel_crtc_state *current_config, |
11170 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11171 | { |
66e985c0 DV |
11172 | #define PIPE_CONF_CHECK_X(name) \ |
11173 | if (current_config->name != pipe_config->name) { \ | |
11174 | DRM_ERROR("mismatch in " #name " " \ | |
11175 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11176 | current_config->name, \ | |
11177 | pipe_config->name); \ | |
11178 | return false; \ | |
11179 | } | |
11180 | ||
08a24034 DV |
11181 | #define PIPE_CONF_CHECK_I(name) \ |
11182 | if (current_config->name != pipe_config->name) { \ | |
11183 | DRM_ERROR("mismatch in " #name " " \ | |
11184 | "(expected %i, found %i)\n", \ | |
11185 | current_config->name, \ | |
11186 | pipe_config->name); \ | |
11187 | return false; \ | |
88adfff1 DV |
11188 | } |
11189 | ||
b95af8be VK |
11190 | /* This is required for BDW+ where there is only one set of registers for |
11191 | * switching between high and low RR. | |
11192 | * This macro can be used whenever a comparison has to be made between one | |
11193 | * hw state and multiple sw state variables. | |
11194 | */ | |
11195 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11196 | if ((current_config->name != pipe_config->name) && \ | |
11197 | (current_config->alt_name != pipe_config->name)) { \ | |
11198 | DRM_ERROR("mismatch in " #name " " \ | |
11199 | "(expected %i or %i, found %i)\n", \ | |
11200 | current_config->name, \ | |
11201 | current_config->alt_name, \ | |
11202 | pipe_config->name); \ | |
11203 | return false; \ | |
11204 | } | |
11205 | ||
1bd1bd80 DV |
11206 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11207 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11208 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11209 | "(expected %i, found %i)\n", \ |
11210 | current_config->name & (mask), \ | |
11211 | pipe_config->name & (mask)); \ | |
11212 | return false; \ | |
11213 | } | |
11214 | ||
5e550656 VS |
11215 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11216 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11217 | DRM_ERROR("mismatch in " #name " " \ | |
11218 | "(expected %i, found %i)\n", \ | |
11219 | current_config->name, \ | |
11220 | pipe_config->name); \ | |
11221 | return false; \ | |
11222 | } | |
11223 | ||
bb760063 DV |
11224 | #define PIPE_CONF_QUIRK(quirk) \ |
11225 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11226 | ||
eccb140b DV |
11227 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11228 | ||
08a24034 DV |
11229 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11230 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11231 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11232 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11233 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11234 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11235 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11236 | |
eb14cb74 | 11237 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11238 | |
11239 | if (INTEL_INFO(dev)->gen < 8) { | |
11240 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11241 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11242 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11243 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11244 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11245 | ||
11246 | if (current_config->has_drrs) { | |
11247 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11248 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11249 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11250 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11251 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11252 | } | |
11253 | } else { | |
11254 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11255 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11256 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11257 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11258 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11259 | } | |
eb14cb74 | 11260 | |
2d112de7 ACO |
11261 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11262 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11263 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11264 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11265 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11266 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11267 | |
2d112de7 ACO |
11268 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11269 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11270 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11271 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11272 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11273 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11274 | |
c93f54cf | 11275 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11276 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11277 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11278 | IS_VALLEYVIEW(dev)) | |
11279 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11280 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11281 | |
9ed109a7 DV |
11282 | PIPE_CONF_CHECK_I(has_audio); |
11283 | ||
2d112de7 | 11284 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11285 | DRM_MODE_FLAG_INTERLACE); |
11286 | ||
bb760063 | 11287 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11288 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11289 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11290 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11291 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11292 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11293 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11294 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11295 | DRM_MODE_FLAG_NVSYNC); |
11296 | } | |
045ac3b5 | 11297 | |
37327abd VS |
11298 | PIPE_CONF_CHECK_I(pipe_src_w); |
11299 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11300 | |
9953599b DV |
11301 | /* |
11302 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11303 | * screen. Since we don't yet re-compute the pipe config when moving | |
11304 | * just the lvds port away to another pipe the sw tracking won't match. | |
11305 | * | |
11306 | * Proper atomic modesets with recomputed global state will fix this. | |
11307 | * Until then just don't check gmch state for inherited modes. | |
11308 | */ | |
11309 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11310 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11311 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11312 | if (INTEL_INFO(dev)->gen < 4) | |
11313 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11314 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11315 | } | |
11316 | ||
fd4daa9c CW |
11317 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11318 | if (current_config->pch_pfit.enabled) { | |
11319 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11320 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11321 | } | |
2fa2fe9a | 11322 | |
e59150dc JB |
11323 | /* BDW+ don't expose a synchronous way to read the state */ |
11324 | if (IS_HASWELL(dev)) | |
11325 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11326 | |
282740f7 VS |
11327 | PIPE_CONF_CHECK_I(double_wide); |
11328 | ||
26804afd DV |
11329 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11330 | ||
c0d43d62 | 11331 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11332 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11333 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11334 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11335 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11336 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11337 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11338 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11339 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11340 | |
42571aef VS |
11341 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11342 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11343 | ||
2d112de7 | 11344 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11345 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11346 | |
66e985c0 | 11347 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11348 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11349 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11350 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11351 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11352 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11353 | |
0e8ffe1b DV |
11354 | return true; |
11355 | } | |
11356 | ||
08db6652 DL |
11357 | static void check_wm_state(struct drm_device *dev) |
11358 | { | |
11359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11360 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11361 | struct intel_crtc *intel_crtc; | |
11362 | int plane; | |
11363 | ||
11364 | if (INTEL_INFO(dev)->gen < 9) | |
11365 | return; | |
11366 | ||
11367 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11368 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11369 | ||
11370 | for_each_intel_crtc(dev, intel_crtc) { | |
11371 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11372 | const enum pipe pipe = intel_crtc->pipe; | |
11373 | ||
11374 | if (!intel_crtc->active) | |
11375 | continue; | |
11376 | ||
11377 | /* planes */ | |
dd740780 | 11378 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11379 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11380 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11381 | ||
11382 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11383 | continue; | |
11384 | ||
11385 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11386 | "(expected (%u,%u), found (%u,%u))\n", | |
11387 | pipe_name(pipe), plane + 1, | |
11388 | sw_entry->start, sw_entry->end, | |
11389 | hw_entry->start, hw_entry->end); | |
11390 | } | |
11391 | ||
11392 | /* cursor */ | |
11393 | hw_entry = &hw_ddb.cursor[pipe]; | |
11394 | sw_entry = &sw_ddb->cursor[pipe]; | |
11395 | ||
11396 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11397 | continue; | |
11398 | ||
11399 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11400 | "(expected (%u,%u), found (%u,%u))\n", | |
11401 | pipe_name(pipe), | |
11402 | sw_entry->start, sw_entry->end, | |
11403 | hw_entry->start, hw_entry->end); | |
11404 | } | |
11405 | } | |
11406 | ||
91d1b4bd DV |
11407 | static void |
11408 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11409 | { |
8af6cf88 DV |
11410 | struct intel_connector *connector; |
11411 | ||
3a3371ff | 11412 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11413 | /* This also checks the encoder/connector hw state with the |
11414 | * ->get_hw_state callbacks. */ | |
11415 | intel_connector_check_state(connector); | |
11416 | ||
e2c719b7 | 11417 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11418 | "connector's staged encoder doesn't match current encoder\n"); |
11419 | } | |
91d1b4bd DV |
11420 | } |
11421 | ||
11422 | static void | |
11423 | check_encoder_state(struct drm_device *dev) | |
11424 | { | |
11425 | struct intel_encoder *encoder; | |
11426 | struct intel_connector *connector; | |
8af6cf88 | 11427 | |
b2784e15 | 11428 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11429 | bool enabled = false; |
11430 | bool active = false; | |
11431 | enum pipe pipe, tracked_pipe; | |
11432 | ||
11433 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11434 | encoder->base.base.id, | |
8e329a03 | 11435 | encoder->base.name); |
8af6cf88 | 11436 | |
e2c719b7 | 11437 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11438 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11439 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11440 | "encoder's active_connectors set, but no crtc\n"); |
11441 | ||
3a3371ff | 11442 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11443 | if (connector->base.encoder != &encoder->base) |
11444 | continue; | |
11445 | enabled = true; | |
11446 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11447 | active = true; | |
11448 | } | |
0e32b39c DA |
11449 | /* |
11450 | * for MST connectors if we unplug the connector is gone | |
11451 | * away but the encoder is still connected to a crtc | |
11452 | * until a modeset happens in response to the hotplug. | |
11453 | */ | |
11454 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11455 | continue; | |
11456 | ||
e2c719b7 | 11457 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11458 | "encoder's enabled state mismatch " |
11459 | "(expected %i, found %i)\n", | |
11460 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11461 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11462 | "active encoder with no crtc\n"); |
11463 | ||
e2c719b7 | 11464 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11465 | "encoder's computed active state doesn't match tracked active state " |
11466 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11467 | ||
11468 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11469 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11470 | "encoder's hw state doesn't match sw tracking " |
11471 | "(expected %i, found %i)\n", | |
11472 | encoder->connectors_active, active); | |
11473 | ||
11474 | if (!encoder->base.crtc) | |
11475 | continue; | |
11476 | ||
11477 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11478 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11479 | "active encoder's pipe doesn't match" |
11480 | "(expected %i, found %i)\n", | |
11481 | tracked_pipe, pipe); | |
11482 | ||
11483 | } | |
91d1b4bd DV |
11484 | } |
11485 | ||
11486 | static void | |
11487 | check_crtc_state(struct drm_device *dev) | |
11488 | { | |
fbee40df | 11489 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11490 | struct intel_crtc *crtc; |
11491 | struct intel_encoder *encoder; | |
5cec258b | 11492 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11493 | |
d3fcc808 | 11494 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11495 | bool enabled = false; |
11496 | bool active = false; | |
11497 | ||
045ac3b5 JB |
11498 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11499 | ||
8af6cf88 DV |
11500 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
11501 | crtc->base.base.id); | |
11502 | ||
83d65738 | 11503 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
11504 | "active crtc, but not enabled in sw tracking\n"); |
11505 | ||
b2784e15 | 11506 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11507 | if (encoder->base.crtc != &crtc->base) |
11508 | continue; | |
11509 | enabled = true; | |
11510 | if (encoder->connectors_active) | |
11511 | active = true; | |
11512 | } | |
6c49f241 | 11513 | |
e2c719b7 | 11514 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
11515 | "crtc's computed active state doesn't match tracked active state " |
11516 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 11517 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 11518 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
11519 | "(expected %i, found %i)\n", enabled, |
11520 | crtc->base.state->enable); | |
8af6cf88 | 11521 | |
0e8ffe1b DV |
11522 | active = dev_priv->display.get_pipe_config(crtc, |
11523 | &pipe_config); | |
d62cf62a | 11524 | |
b6b5d049 VS |
11525 | /* hw state is inconsistent with the pipe quirk */ |
11526 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11527 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
11528 | active = crtc->active; |
11529 | ||
b2784e15 | 11530 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 11531 | enum pipe pipe; |
6c49f241 DV |
11532 | if (encoder->base.crtc != &crtc->base) |
11533 | continue; | |
1d37b689 | 11534 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
11535 | encoder->get_config(encoder, &pipe_config); |
11536 | } | |
11537 | ||
e2c719b7 | 11538 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
11539 | "crtc active state doesn't match with hw state " |
11540 | "(expected %i, found %i)\n", crtc->active, active); | |
11541 | ||
c0b03411 | 11542 | if (active && |
6e3c9717 | 11543 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 11544 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
11545 | intel_dump_pipe_config(crtc, &pipe_config, |
11546 | "[hw state]"); | |
6e3c9717 | 11547 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
11548 | "[sw state]"); |
11549 | } | |
8af6cf88 DV |
11550 | } |
11551 | } | |
11552 | ||
91d1b4bd DV |
11553 | static void |
11554 | check_shared_dpll_state(struct drm_device *dev) | |
11555 | { | |
fbee40df | 11556 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11557 | struct intel_crtc *crtc; |
11558 | struct intel_dpll_hw_state dpll_hw_state; | |
11559 | int i; | |
5358901f DV |
11560 | |
11561 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
11562 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11563 | int enabled_crtcs = 0, active_crtcs = 0; | |
11564 | bool active; | |
11565 | ||
11566 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
11567 | ||
11568 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11569 | ||
11570 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
11571 | ||
e2c719b7 | 11572 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 11573 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 11574 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 11575 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 11576 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 11577 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 11578 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 11579 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
11580 | "pll on state mismatch (expected %i, found %i)\n", |
11581 | pll->on, active); | |
11582 | ||
d3fcc808 | 11583 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11584 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
11585 | enabled_crtcs++; |
11586 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11587 | active_crtcs++; | |
11588 | } | |
e2c719b7 | 11589 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
11590 | "pll active crtcs mismatch (expected %i, found %i)\n", |
11591 | pll->active, active_crtcs); | |
e2c719b7 | 11592 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 11593 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 11594 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 11595 | |
e2c719b7 | 11596 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
11597 | sizeof(dpll_hw_state)), |
11598 | "pll hw state mismatch\n"); | |
5358901f | 11599 | } |
8af6cf88 DV |
11600 | } |
11601 | ||
91d1b4bd DV |
11602 | void |
11603 | intel_modeset_check_state(struct drm_device *dev) | |
11604 | { | |
08db6652 | 11605 | check_wm_state(dev); |
91d1b4bd DV |
11606 | check_connector_state(dev); |
11607 | check_encoder_state(dev); | |
11608 | check_crtc_state(dev); | |
11609 | check_shared_dpll_state(dev); | |
11610 | } | |
11611 | ||
5cec258b | 11612 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
11613 | int dotclock) |
11614 | { | |
11615 | /* | |
11616 | * FDI already provided one idea for the dotclock. | |
11617 | * Yell if the encoder disagrees. | |
11618 | */ | |
2d112de7 | 11619 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11620 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 11621 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
11622 | } |
11623 | ||
80715b2f VS |
11624 | static void update_scanline_offset(struct intel_crtc *crtc) |
11625 | { | |
11626 | struct drm_device *dev = crtc->base.dev; | |
11627 | ||
11628 | /* | |
11629 | * The scanline counter increments at the leading edge of hsync. | |
11630 | * | |
11631 | * On most platforms it starts counting from vtotal-1 on the | |
11632 | * first active line. That means the scanline counter value is | |
11633 | * always one less than what we would expect. Ie. just after | |
11634 | * start of vblank, which also occurs at start of hsync (on the | |
11635 | * last active line), the scanline counter will read vblank_start-1. | |
11636 | * | |
11637 | * On gen2 the scanline counter starts counting from 1 instead | |
11638 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11639 | * to keep the value positive), instead of adding one. | |
11640 | * | |
11641 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11642 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11643 | * there's an extra 1 line difference. So we need to add two instead of | |
11644 | * one to the value. | |
11645 | */ | |
11646 | if (IS_GEN2(dev)) { | |
6e3c9717 | 11647 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11648 | int vtotal; |
11649 | ||
11650 | vtotal = mode->crtc_vtotal; | |
11651 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
11652 | vtotal /= 2; | |
11653 | ||
11654 | crtc->scanline_offset = vtotal - 1; | |
11655 | } else if (HAS_DDI(dev) && | |
409ee761 | 11656 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11657 | crtc->scanline_offset = 2; |
11658 | } else | |
11659 | crtc->scanline_offset = 1; | |
11660 | } | |
11661 | ||
5cec258b | 11662 | static struct intel_crtc_state * |
7f27126e JB |
11663 | intel_modeset_compute_config(struct drm_crtc *crtc, |
11664 | struct drm_display_mode *mode, | |
11665 | struct drm_framebuffer *fb, | |
83a57153 | 11666 | struct drm_atomic_state *state, |
7f27126e JB |
11667 | unsigned *modeset_pipes, |
11668 | unsigned *prepare_pipes, | |
11669 | unsigned *disable_pipes) | |
11670 | { | |
db7542dd | 11671 | struct drm_device *dev = crtc->dev; |
5cec258b | 11672 | struct intel_crtc_state *pipe_config = NULL; |
db7542dd | 11673 | struct intel_crtc *intel_crtc; |
0b901879 ACO |
11674 | int ret = 0; |
11675 | ||
11676 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11677 | if (ret) | |
11678 | return ERR_PTR(ret); | |
7f27126e JB |
11679 | |
11680 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
11681 | prepare_pipes, disable_pipes); | |
11682 | ||
db7542dd ACO |
11683 | for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { |
11684 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11685 | if (IS_ERR(pipe_config)) | |
11686 | return pipe_config; | |
11687 | ||
11688 | pipe_config->base.enable = false; | |
11689 | } | |
7f27126e JB |
11690 | |
11691 | /* | |
11692 | * Note this needs changes when we start tracking multiple modes | |
11693 | * and crtcs. At that point we'll need to compute the whole config | |
11694 | * (i.e. one pipe_config for each crtc) rather than just the one | |
11695 | * for this crtc. | |
11696 | */ | |
db7542dd ACO |
11697 | for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { |
11698 | /* FIXME: For now we still expect modeset_pipes has at most | |
11699 | * one bit set. */ | |
11700 | if (WARN_ON(&intel_crtc->base != crtc)) | |
11701 | continue; | |
83a57153 | 11702 | |
db7542dd ACO |
11703 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); |
11704 | if (IS_ERR(pipe_config)) | |
11705 | return pipe_config; | |
7f27126e | 11706 | |
304603f4 ACO |
11707 | pipe_config->base.enable = true; |
11708 | ||
db7542dd ACO |
11709 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
11710 | "[modeset]"); | |
11711 | } | |
11712 | ||
11713 | return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; | |
7f27126e JB |
11714 | } |
11715 | ||
225da59b | 11716 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, |
ed6739ef ACO |
11717 | unsigned modeset_pipes, |
11718 | unsigned disable_pipes) | |
11719 | { | |
225da59b | 11720 | struct drm_device *dev = state->dev; |
ed6739ef ACO |
11721 | struct drm_i915_private *dev_priv = to_i915(dev); |
11722 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
11723 | struct intel_crtc *intel_crtc; | |
11724 | int ret = 0; | |
11725 | ||
11726 | if (!dev_priv->display.crtc_compute_clock) | |
11727 | return 0; | |
11728 | ||
11729 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
11730 | if (ret) | |
11731 | goto done; | |
11732 | ||
11733 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
225da59b ACO |
11734 | struct intel_crtc_state *crtc_state = |
11735 | intel_atomic_get_crtc_state(state, intel_crtc); | |
11736 | ||
11737 | /* Modeset pipes should have a new state by now */ | |
11738 | if (WARN_ON(IS_ERR(crtc_state))) | |
11739 | continue; | |
11740 | ||
ed6739ef | 11741 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
225da59b | 11742 | crtc_state); |
ed6739ef ACO |
11743 | if (ret) { |
11744 | intel_shared_dpll_abort_config(dev_priv); | |
11745 | goto done; | |
11746 | } | |
11747 | } | |
11748 | ||
11749 | done: | |
11750 | return ret; | |
11751 | } | |
11752 | ||
f30da187 DV |
11753 | static int __intel_set_mode(struct drm_crtc *crtc, |
11754 | struct drm_display_mode *mode, | |
7f27126e | 11755 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 11756 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11757 | unsigned modeset_pipes, |
11758 | unsigned prepare_pipes, | |
11759 | unsigned disable_pipes) | |
a6778b3c DV |
11760 | { |
11761 | struct drm_device *dev = crtc->dev; | |
fbee40df | 11762 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 11763 | struct drm_display_mode *saved_mode; |
304603f4 | 11764 | struct drm_atomic_state *state = pipe_config->base.state; |
83a57153 | 11765 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 11766 | struct intel_crtc *intel_crtc; |
c0c36b94 | 11767 | int ret = 0; |
a6778b3c | 11768 | |
4b4b9238 | 11769 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
11770 | if (!saved_mode) |
11771 | return -ENOMEM; | |
a6778b3c | 11772 | |
83a57153 ACO |
11773 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
11774 | if (!crtc_state_copy) { | |
11775 | ret = -ENOMEM; | |
11776 | goto done; | |
11777 | } | |
11778 | ||
3ac18232 | 11779 | *saved_mode = crtc->mode; |
a6778b3c | 11780 | |
30a970c6 JB |
11781 | /* |
11782 | * See if the config requires any additional preparation, e.g. | |
11783 | * to adjust global state with pipes off. We need to do this | |
11784 | * here so we can get the modeset_pipe updated config for the new | |
11785 | * mode set on this crtc. For other crtcs we need to use the | |
11786 | * adjusted_mode bits in the crtc directly. | |
11787 | */ | |
c164f833 | 11788 | if (IS_VALLEYVIEW(dev)) { |
304603f4 ACO |
11789 | ret = valleyview_modeset_global_pipes(state, &prepare_pipes); |
11790 | if (ret) | |
11791 | goto done; | |
30a970c6 | 11792 | |
c164f833 VS |
11793 | /* may have added more to prepare_pipes than we should */ |
11794 | prepare_pipes &= ~disable_pipes; | |
11795 | } | |
11796 | ||
225da59b | 11797 | ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); |
ed6739ef ACO |
11798 | if (ret) |
11799 | goto done; | |
8bd31e67 | 11800 | |
460da916 DV |
11801 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
11802 | intel_crtc_disable(&intel_crtc->base); | |
11803 | ||
ea9d758d | 11804 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 11805 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
11806 | dev_priv->display.crtc_disable(&intel_crtc->base); |
11807 | } | |
a6778b3c | 11808 | |
6c4c86f5 DV |
11809 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
11810 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
11811 | * |
11812 | * Note we'll need to fix this up when we start tracking multiple | |
11813 | * pipes; here we assume a single modeset_pipe and only track the | |
11814 | * single crtc and mode. | |
f6e5b160 | 11815 | */ |
b8cecdf5 | 11816 | if (modeset_pipes) { |
25c5b266 | 11817 | crtc->mode = *mode; |
b8cecdf5 DV |
11818 | /* mode_set/enable/disable functions rely on a correct pipe |
11819 | * config. */ | |
f5de6e07 | 11820 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
11821 | |
11822 | /* | |
11823 | * Calculate and store various constants which | |
11824 | * are later needed by vblank and swap-completion | |
11825 | * timestamping. They are derived from true hwmode. | |
11826 | */ | |
11827 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 11828 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 11829 | } |
7758a113 | 11830 | |
ea9d758d DV |
11831 | /* Only after disabling all output pipelines that will be changed can we |
11832 | * update the the output configuration. */ | |
11833 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11834 | |
304603f4 | 11835 | modeset_update_crtc_power_domains(state); |
47fab737 | 11836 | |
25c5b266 | 11837 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11838 | struct drm_plane *primary = intel_crtc->base.primary; |
11839 | int vdisplay, hdisplay; | |
4c10794f | 11840 | |
455a6808 | 11841 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
70a101f8 MR |
11842 | ret = drm_plane_helper_update(primary, &intel_crtc->base, |
11843 | fb, 0, 0, | |
11844 | hdisplay, vdisplay, | |
11845 | x << 16, y << 16, | |
11846 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11847 | } |
11848 | ||
11849 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11850 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11851 | update_scanline_offset(intel_crtc); | |
11852 | ||
25c5b266 | 11853 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11854 | } |
a6778b3c | 11855 | |
a6778b3c DV |
11856 | /* FIXME: add subpixel order */ |
11857 | done: | |
83d65738 | 11858 | if (ret && crtc->state->enable) |
3ac18232 | 11859 | crtc->mode = *saved_mode; |
a6778b3c | 11860 | |
83a57153 ACO |
11861 | if (ret == 0 && pipe_config) { |
11862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11863 | ||
11864 | /* The pipe_config will be freed with the atomic state, so | |
11865 | * make a copy. */ | |
11866 | memcpy(crtc_state_copy, intel_crtc->config, | |
11867 | sizeof *crtc_state_copy); | |
11868 | intel_crtc->config = crtc_state_copy; | |
11869 | intel_crtc->base.state = &crtc_state_copy->base; | |
83a57153 ACO |
11870 | } else { |
11871 | kfree(crtc_state_copy); | |
11872 | } | |
11873 | ||
3ac18232 | 11874 | kfree(saved_mode); |
a6778b3c | 11875 | return ret; |
f6e5b160 CW |
11876 | } |
11877 | ||
7f27126e JB |
11878 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11879 | struct drm_display_mode *mode, | |
11880 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 11881 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11882 | unsigned modeset_pipes, |
11883 | unsigned prepare_pipes, | |
11884 | unsigned disable_pipes) | |
f30da187 DV |
11885 | { |
11886 | int ret; | |
11887 | ||
7f27126e JB |
11888 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11889 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11890 | |
11891 | if (ret == 0) | |
11892 | intel_modeset_check_state(crtc->dev); | |
11893 | ||
11894 | return ret; | |
11895 | } | |
11896 | ||
7f27126e JB |
11897 | static int intel_set_mode(struct drm_crtc *crtc, |
11898 | struct drm_display_mode *mode, | |
83a57153 ACO |
11899 | int x, int y, struct drm_framebuffer *fb, |
11900 | struct drm_atomic_state *state) | |
7f27126e | 11901 | { |
5cec258b | 11902 | struct intel_crtc_state *pipe_config; |
7f27126e | 11903 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 11904 | int ret = 0; |
7f27126e | 11905 | |
83a57153 | 11906 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, |
7f27126e JB |
11907 | &modeset_pipes, |
11908 | &prepare_pipes, | |
11909 | &disable_pipes); | |
11910 | ||
83a57153 ACO |
11911 | if (IS_ERR(pipe_config)) { |
11912 | ret = PTR_ERR(pipe_config); | |
11913 | goto out; | |
11914 | } | |
11915 | ||
11916 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11917 | modeset_pipes, prepare_pipes, | |
11918 | disable_pipes); | |
11919 | if (ret) | |
11920 | goto out; | |
7f27126e | 11921 | |
83a57153 ACO |
11922 | out: |
11923 | return ret; | |
7f27126e JB |
11924 | } |
11925 | ||
c0c36b94 CW |
11926 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11927 | { | |
83a57153 ACO |
11928 | struct drm_device *dev = crtc->dev; |
11929 | struct drm_atomic_state *state; | |
11930 | struct intel_encoder *encoder; | |
11931 | struct intel_connector *connector; | |
11932 | struct drm_connector_state *connector_state; | |
11933 | ||
11934 | state = drm_atomic_state_alloc(dev); | |
11935 | if (!state) { | |
11936 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
11937 | crtc->base.id); | |
11938 | return; | |
11939 | } | |
11940 | ||
11941 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
11942 | ||
11943 | /* The force restore path in the HW readout code relies on the staged | |
11944 | * config still keeping the user requested config while the actual | |
11945 | * state has been overwritten by the configuration read from HW. We | |
11946 | * need to copy the staged config to the atomic state, otherwise the | |
11947 | * mode set will just reapply the state the HW is already in. */ | |
11948 | for_each_intel_encoder(dev, encoder) { | |
11949 | if (&encoder->new_crtc->base != crtc) | |
11950 | continue; | |
11951 | ||
11952 | for_each_intel_connector(dev, connector) { | |
11953 | if (connector->new_encoder != encoder) | |
11954 | continue; | |
11955 | ||
11956 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
11957 | if (IS_ERR(connector_state)) { | |
11958 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
11959 | connector->base.base.id, | |
11960 | connector->base.name, | |
11961 | PTR_ERR(connector_state)); | |
11962 | continue; | |
11963 | } | |
11964 | ||
11965 | connector_state->crtc = crtc; | |
11966 | connector_state->best_encoder = &encoder->base; | |
11967 | } | |
11968 | } | |
11969 | ||
11970 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, | |
11971 | state); | |
11972 | ||
11973 | drm_atomic_state_free(state); | |
c0c36b94 CW |
11974 | } |
11975 | ||
25c5b266 DV |
11976 | #undef for_each_intel_crtc_masked |
11977 | ||
d9e55608 DV |
11978 | static void intel_set_config_free(struct intel_set_config *config) |
11979 | { | |
11980 | if (!config) | |
11981 | return; | |
11982 | ||
1aa4b628 DV |
11983 | kfree(config->save_connector_encoders); |
11984 | kfree(config->save_encoder_crtcs); | |
7668851f | 11985 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11986 | kfree(config); |
11987 | } | |
11988 | ||
85f9eb71 DV |
11989 | static int intel_set_config_save_state(struct drm_device *dev, |
11990 | struct intel_set_config *config) | |
11991 | { | |
7668851f | 11992 | struct drm_crtc *crtc; |
85f9eb71 DV |
11993 | struct drm_encoder *encoder; |
11994 | struct drm_connector *connector; | |
11995 | int count; | |
11996 | ||
7668851f VS |
11997 | config->save_crtc_enabled = |
11998 | kcalloc(dev->mode_config.num_crtc, | |
11999 | sizeof(bool), GFP_KERNEL); | |
12000 | if (!config->save_crtc_enabled) | |
12001 | return -ENOMEM; | |
12002 | ||
1aa4b628 DV |
12003 | config->save_encoder_crtcs = |
12004 | kcalloc(dev->mode_config.num_encoder, | |
12005 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
12006 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
12007 | return -ENOMEM; |
12008 | ||
1aa4b628 DV |
12009 | config->save_connector_encoders = |
12010 | kcalloc(dev->mode_config.num_connector, | |
12011 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
12012 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
12013 | return -ENOMEM; |
12014 | ||
12015 | /* Copy data. Note that driver private data is not affected. | |
12016 | * Should anything bad happen only the expected state is | |
12017 | * restored, not the drivers personal bookkeeping. | |
12018 | */ | |
7668851f | 12019 | count = 0; |
70e1e0ec | 12020 | for_each_crtc(dev, crtc) { |
83d65738 | 12021 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
12022 | } |
12023 | ||
85f9eb71 DV |
12024 | count = 0; |
12025 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 12026 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
12027 | } |
12028 | ||
12029 | count = 0; | |
12030 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 12031 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
12032 | } |
12033 | ||
12034 | return 0; | |
12035 | } | |
12036 | ||
12037 | static void intel_set_config_restore_state(struct drm_device *dev, | |
12038 | struct intel_set_config *config) | |
12039 | { | |
7668851f | 12040 | struct intel_crtc *crtc; |
9a935856 DV |
12041 | struct intel_encoder *encoder; |
12042 | struct intel_connector *connector; | |
85f9eb71 DV |
12043 | int count; |
12044 | ||
7668851f | 12045 | count = 0; |
d3fcc808 | 12046 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12047 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
12048 | } | |
12049 | ||
85f9eb71 | 12050 | count = 0; |
b2784e15 | 12051 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
12052 | encoder->new_crtc = |
12053 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
12054 | } |
12055 | ||
12056 | count = 0; | |
3a3371ff | 12057 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12058 | connector->new_encoder = |
12059 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
12060 | } |
12061 | } | |
12062 | ||
e3de42b6 | 12063 | static bool |
2e57f47d | 12064 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
12065 | { |
12066 | int i; | |
12067 | ||
2e57f47d CW |
12068 | if (set->num_connectors == 0) |
12069 | return false; | |
12070 | ||
12071 | if (WARN_ON(set->connectors == NULL)) | |
12072 | return false; | |
12073 | ||
12074 | for (i = 0; i < set->num_connectors; i++) | |
12075 | if (set->connectors[i]->encoder && | |
12076 | set->connectors[i]->encoder->crtc == set->crtc && | |
12077 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
12078 | return true; |
12079 | ||
12080 | return false; | |
12081 | } | |
12082 | ||
5e2b584e DV |
12083 | static void |
12084 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
12085 | struct intel_set_config *config) | |
12086 | { | |
12087 | ||
12088 | /* We should be able to check here if the fb has the same properties | |
12089 | * and then just flip_or_move it */ | |
2e57f47d CW |
12090 | if (is_crtc_connector_off(set)) { |
12091 | config->mode_changed = true; | |
f4510a27 | 12092 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
12093 | /* |
12094 | * If we have no fb, we can only flip as long as the crtc is | |
12095 | * active, otherwise we need a full mode set. The crtc may | |
12096 | * be active if we've only disabled the primary plane, or | |
12097 | * in fastboot situations. | |
12098 | */ | |
f4510a27 | 12099 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
12100 | struct intel_crtc *intel_crtc = |
12101 | to_intel_crtc(set->crtc); | |
12102 | ||
3b150f08 | 12103 | if (intel_crtc->active) { |
319d9827 JB |
12104 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
12105 | config->fb_changed = true; | |
12106 | } else { | |
12107 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
12108 | config->mode_changed = true; | |
12109 | } | |
5e2b584e DV |
12110 | } else if (set->fb == NULL) { |
12111 | config->mode_changed = true; | |
72f4901e | 12112 | } else if (set->fb->pixel_format != |
f4510a27 | 12113 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 12114 | config->mode_changed = true; |
e3de42b6 | 12115 | } else { |
5e2b584e | 12116 | config->fb_changed = true; |
e3de42b6 | 12117 | } |
5e2b584e DV |
12118 | } |
12119 | ||
835c5873 | 12120 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
12121 | config->fb_changed = true; |
12122 | ||
12123 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
12124 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
12125 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
12126 | drm_mode_debug_printmodeline(set->mode); | |
12127 | config->mode_changed = true; | |
12128 | } | |
a1d95703 CW |
12129 | |
12130 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
12131 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
12132 | } |
12133 | ||
2e431051 | 12134 | static int |
9a935856 DV |
12135 | intel_modeset_stage_output_state(struct drm_device *dev, |
12136 | struct drm_mode_set *set, | |
944b0c76 ACO |
12137 | struct intel_set_config *config, |
12138 | struct drm_atomic_state *state) | |
50f56119 | 12139 | { |
9a935856 | 12140 | struct intel_connector *connector; |
944b0c76 | 12141 | struct drm_connector_state *connector_state; |
9a935856 | 12142 | struct intel_encoder *encoder; |
7668851f | 12143 | struct intel_crtc *crtc; |
f3f08572 | 12144 | int ro; |
50f56119 | 12145 | |
9abdda74 | 12146 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12147 | * of connectors. For paranoia, double-check this. */ |
12148 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12149 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12150 | ||
3a3371ff | 12151 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12152 | /* Otherwise traverse passed in connector list and get encoders |
12153 | * for them. */ | |
50f56119 | 12154 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 12155 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 12156 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
12157 | break; |
12158 | } | |
12159 | } | |
12160 | ||
9a935856 DV |
12161 | /* If we disable the crtc, disable all its connectors. Also, if |
12162 | * the connector is on the changing crtc but not on the new | |
12163 | * connector list, disable it. */ | |
12164 | if ((!set->fb || ro == set->num_connectors) && | |
12165 | connector->base.encoder && | |
12166 | connector->base.encoder->crtc == set->crtc) { | |
12167 | connector->new_encoder = NULL; | |
12168 | ||
12169 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12170 | connector->base.base.id, | |
c23cc417 | 12171 | connector->base.name); |
9a935856 DV |
12172 | } |
12173 | ||
12174 | ||
12175 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
12176 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
12177 | connector->base.base.id, | |
12178 | connector->base.name); | |
5e2b584e | 12179 | config->mode_changed = true; |
50f56119 DV |
12180 | } |
12181 | } | |
9a935856 | 12182 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12183 | |
9a935856 | 12184 | /* Update crtc of enabled connectors. */ |
3a3371ff | 12185 | for_each_intel_connector(dev, connector) { |
7668851f VS |
12186 | struct drm_crtc *new_crtc; |
12187 | ||
9a935856 | 12188 | if (!connector->new_encoder) |
50f56119 DV |
12189 | continue; |
12190 | ||
9a935856 | 12191 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
12192 | |
12193 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 12194 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
12195 | new_crtc = set->crtc; |
12196 | } | |
12197 | ||
12198 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
12199 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
12200 | new_crtc)) { | |
5e2b584e | 12201 | return -EINVAL; |
50f56119 | 12202 | } |
0e32b39c | 12203 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 12204 | |
944b0c76 ACO |
12205 | connector_state = |
12206 | drm_atomic_get_connector_state(state, &connector->base); | |
12207 | if (IS_ERR(connector_state)) | |
12208 | return PTR_ERR(connector_state); | |
12209 | ||
12210 | connector_state->crtc = new_crtc; | |
12211 | connector_state->best_encoder = &connector->new_encoder->base; | |
12212 | ||
9a935856 DV |
12213 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12214 | connector->base.base.id, | |
c23cc417 | 12215 | connector->base.name, |
9a935856 DV |
12216 | new_crtc->base.id); |
12217 | } | |
12218 | ||
12219 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 12220 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 12221 | int num_connectors = 0; |
3a3371ff | 12222 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12223 | if (connector->new_encoder == encoder) { |
12224 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 12225 | num_connectors++; |
9a935856 DV |
12226 | } |
12227 | } | |
5a65f358 PZ |
12228 | |
12229 | if (num_connectors == 0) | |
12230 | encoder->new_crtc = NULL; | |
12231 | else if (num_connectors > 1) | |
12232 | return -EINVAL; | |
12233 | ||
9a935856 DV |
12234 | /* Only now check for crtc changes so we don't miss encoders |
12235 | * that will be disabled. */ | |
12236 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
12237 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
12238 | encoder->base.base.id, | |
12239 | encoder->base.name); | |
5e2b584e | 12240 | config->mode_changed = true; |
50f56119 DV |
12241 | } |
12242 | } | |
9a935856 | 12243 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 12244 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
12245 | connector_state = |
12246 | drm_atomic_get_connector_state(state, &connector->base); | |
9d918c15 ACO |
12247 | if (IS_ERR(connector_state)) |
12248 | return PTR_ERR(connector_state); | |
944b0c76 ACO |
12249 | |
12250 | if (connector->new_encoder) { | |
0e32b39c DA |
12251 | if (connector->new_encoder != connector->encoder) |
12252 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
12253 | } else { |
12254 | connector_state->crtc = NULL; | |
f61cccf3 | 12255 | connector_state->best_encoder = NULL; |
944b0c76 | 12256 | } |
0e32b39c | 12257 | } |
d3fcc808 | 12258 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12259 | crtc->new_enabled = false; |
12260 | ||
b2784e15 | 12261 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
12262 | if (encoder->new_crtc == crtc) { |
12263 | crtc->new_enabled = true; | |
12264 | break; | |
12265 | } | |
12266 | } | |
12267 | ||
83d65738 | 12268 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
12269 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
12270 | crtc->base.base.id, | |
7668851f VS |
12271 | crtc->new_enabled ? "en" : "dis"); |
12272 | config->mode_changed = true; | |
12273 | } | |
12274 | } | |
12275 | ||
2e431051 DV |
12276 | return 0; |
12277 | } | |
12278 | ||
7d00a1f5 VS |
12279 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
12280 | { | |
12281 | struct drm_device *dev = crtc->base.dev; | |
12282 | struct intel_encoder *encoder; | |
12283 | struct intel_connector *connector; | |
12284 | ||
12285 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
12286 | pipe_name(crtc->pipe)); | |
12287 | ||
3a3371ff | 12288 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
12289 | if (connector->new_encoder && |
12290 | connector->new_encoder->new_crtc == crtc) | |
12291 | connector->new_encoder = NULL; | |
12292 | } | |
12293 | ||
b2784e15 | 12294 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
12295 | if (encoder->new_crtc == crtc) |
12296 | encoder->new_crtc = NULL; | |
12297 | } | |
12298 | ||
12299 | crtc->new_enabled = false; | |
12300 | } | |
12301 | ||
2e431051 DV |
12302 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12303 | { | |
12304 | struct drm_device *dev; | |
2e431051 | 12305 | struct drm_mode_set save_set; |
83a57153 | 12306 | struct drm_atomic_state *state = NULL; |
2e431051 | 12307 | struct intel_set_config *config; |
5cec258b | 12308 | struct intel_crtc_state *pipe_config; |
50f52756 | 12309 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 12310 | int ret; |
2e431051 | 12311 | |
8d3e375e DV |
12312 | BUG_ON(!set); |
12313 | BUG_ON(!set->crtc); | |
12314 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12315 | |
7e53f3a4 DV |
12316 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12317 | BUG_ON(!set->mode && set->fb); | |
12318 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12319 | |
2e431051 DV |
12320 | if (set->fb) { |
12321 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12322 | set->crtc->base.id, set->fb->base.id, | |
12323 | (int)set->num_connectors, set->x, set->y); | |
12324 | } else { | |
12325 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12326 | } |
12327 | ||
12328 | dev = set->crtc->dev; | |
12329 | ||
12330 | ret = -ENOMEM; | |
12331 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12332 | if (!config) | |
12333 | goto out_config; | |
12334 | ||
12335 | ret = intel_set_config_save_state(dev, config); | |
12336 | if (ret) | |
12337 | goto out_config; | |
12338 | ||
12339 | save_set.crtc = set->crtc; | |
12340 | save_set.mode = &set->crtc->mode; | |
12341 | save_set.x = set->crtc->x; | |
12342 | save_set.y = set->crtc->y; | |
f4510a27 | 12343 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
12344 | |
12345 | /* Compute whether we need a full modeset, only an fb base update or no | |
12346 | * change at all. In the future we might also check whether only the | |
12347 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12348 | * such cases. */ | |
12349 | intel_set_config_compute_mode_changes(set, config); | |
12350 | ||
83a57153 ACO |
12351 | state = drm_atomic_state_alloc(dev); |
12352 | if (!state) { | |
12353 | ret = -ENOMEM; | |
12354 | goto out_config; | |
12355 | } | |
12356 | ||
12357 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12358 | ||
944b0c76 | 12359 | ret = intel_modeset_stage_output_state(dev, set, config, state); |
2e431051 DV |
12360 | if (ret) |
12361 | goto fail; | |
12362 | ||
50f52756 | 12363 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
83a57153 | 12364 | set->fb, state, |
50f52756 JB |
12365 | &modeset_pipes, |
12366 | &prepare_pipes, | |
12367 | &disable_pipes); | |
20664591 | 12368 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12369 | ret = PTR_ERR(pipe_config); |
50f52756 | 12370 | goto fail; |
20664591 | 12371 | } else if (pipe_config) { |
b9950a13 | 12372 | if (pipe_config->has_audio != |
6e3c9717 | 12373 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12374 | config->mode_changed = true; |
12375 | ||
af15d2ce JB |
12376 | /* |
12377 | * Note we have an issue here with infoframes: current code | |
12378 | * only updates them on the full mode set path per hw | |
12379 | * requirements. So here we should be checking for any | |
12380 | * required changes and forcing a mode set. | |
12381 | */ | |
20664591 | 12382 | } |
50f52756 | 12383 | |
1f9954d0 JB |
12384 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12385 | ||
5e2b584e | 12386 | if (config->mode_changed) { |
50f52756 JB |
12387 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12388 | set->x, set->y, set->fb, pipe_config, | |
12389 | modeset_pipes, prepare_pipes, | |
12390 | disable_pipes); | |
5e2b584e | 12391 | } else if (config->fb_changed) { |
3b150f08 | 12392 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
12393 | struct drm_plane *primary = set->crtc->primary; |
12394 | int vdisplay, hdisplay; | |
3b150f08 | 12395 | |
455a6808 | 12396 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12397 | ret = drm_plane_helper_update(primary, set->crtc, set->fb, |
12398 | 0, 0, hdisplay, vdisplay, | |
12399 | set->x << 16, set->y << 16, | |
12400 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12401 | |
12402 | /* | |
12403 | * We need to make sure the primary plane is re-enabled if it | |
12404 | * has previously been turned off. | |
12405 | */ | |
12406 | if (!intel_crtc->primary_enabled && ret == 0) { | |
12407 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 12408 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
12409 | } |
12410 | ||
7ca51a3a JB |
12411 | /* |
12412 | * In the fastboot case this may be our only check of the | |
12413 | * state after boot. It would be better to only do it on | |
12414 | * the first update, but we don't have a nice way of doing that | |
12415 | * (and really, set_config isn't used much for high freq page | |
12416 | * flipping, so increasing its cost here shouldn't be a big | |
12417 | * deal). | |
12418 | */ | |
d330a953 | 12419 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12420 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12421 | } |
12422 | ||
2d05eae1 | 12423 | if (ret) { |
bf67dfeb DV |
12424 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12425 | set->crtc->base.id, ret); | |
50f56119 | 12426 | fail: |
2d05eae1 | 12427 | intel_set_config_restore_state(dev, config); |
50f56119 | 12428 | |
83a57153 ACO |
12429 | drm_atomic_state_clear(state); |
12430 | ||
7d00a1f5 VS |
12431 | /* |
12432 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12433 | * force the pipe off to avoid oopsing in the modeset code | |
12434 | * due to fb==NULL. This should only happen during boot since | |
12435 | * we don't yet reconstruct the FB from the hardware state. | |
12436 | */ | |
12437 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12438 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
12439 | ||
2d05eae1 CW |
12440 | /* Try to restore the config */ |
12441 | if (config->mode_changed && | |
12442 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
12443 | save_set.x, save_set.y, save_set.fb, |
12444 | state)) | |
2d05eae1 CW |
12445 | DRM_ERROR("failed to restore config after modeset failure\n"); |
12446 | } | |
50f56119 | 12447 | |
d9e55608 | 12448 | out_config: |
83a57153 ACO |
12449 | if (state) |
12450 | drm_atomic_state_free(state); | |
12451 | ||
d9e55608 | 12452 | intel_set_config_free(config); |
50f56119 DV |
12453 | return ret; |
12454 | } | |
f6e5b160 CW |
12455 | |
12456 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12457 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12458 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12459 | .destroy = intel_crtc_destroy, |
12460 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12461 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12462 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12463 | }; |
12464 | ||
5358901f DV |
12465 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12466 | struct intel_shared_dpll *pll, | |
12467 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12468 | { |
5358901f | 12469 | uint32_t val; |
ee7b9f93 | 12470 | |
f458ebbc | 12471 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12472 | return false; |
12473 | ||
5358901f | 12474 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12475 | hw_state->dpll = val; |
12476 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12477 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12478 | |
12479 | return val & DPLL_VCO_ENABLE; | |
12480 | } | |
12481 | ||
15bdd4cf DV |
12482 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12483 | struct intel_shared_dpll *pll) | |
12484 | { | |
3e369b76 ACO |
12485 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12486 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12487 | } |
12488 | ||
e7b903d2 DV |
12489 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12490 | struct intel_shared_dpll *pll) | |
12491 | { | |
e7b903d2 | 12492 | /* PCH refclock must be enabled first */ |
89eff4be | 12493 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12494 | |
3e369b76 | 12495 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12496 | |
12497 | /* Wait for the clocks to stabilize. */ | |
12498 | POSTING_READ(PCH_DPLL(pll->id)); | |
12499 | udelay(150); | |
12500 | ||
12501 | /* The pixel multiplier can only be updated once the | |
12502 | * DPLL is enabled and the clocks are stable. | |
12503 | * | |
12504 | * So write it again. | |
12505 | */ | |
3e369b76 | 12506 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12507 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12508 | udelay(200); |
12509 | } | |
12510 | ||
12511 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12512 | struct intel_shared_dpll *pll) | |
12513 | { | |
12514 | struct drm_device *dev = dev_priv->dev; | |
12515 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12516 | |
12517 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12518 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12519 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12520 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12521 | } |
12522 | ||
15bdd4cf DV |
12523 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12524 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12525 | udelay(200); |
12526 | } | |
12527 | ||
46edb027 DV |
12528 | static char *ibx_pch_dpll_names[] = { |
12529 | "PCH DPLL A", | |
12530 | "PCH DPLL B", | |
12531 | }; | |
12532 | ||
7c74ade1 | 12533 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12534 | { |
e7b903d2 | 12535 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12536 | int i; |
12537 | ||
7c74ade1 | 12538 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12539 | |
e72f9fbf | 12540 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12541 | dev_priv->shared_dplls[i].id = i; |
12542 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12543 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12544 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12545 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12546 | dev_priv->shared_dplls[i].get_hw_state = |
12547 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12548 | } |
12549 | } | |
12550 | ||
7c74ade1 DV |
12551 | static void intel_shared_dpll_init(struct drm_device *dev) |
12552 | { | |
e7b903d2 | 12553 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12554 | |
9cd86933 DV |
12555 | if (HAS_DDI(dev)) |
12556 | intel_ddi_pll_init(dev); | |
12557 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12558 | ibx_pch_dpll_init(dev); |
12559 | else | |
12560 | dev_priv->num_shared_dpll = 0; | |
12561 | ||
12562 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12563 | } |
12564 | ||
1fc0a8f7 TU |
12565 | /** |
12566 | * intel_wm_need_update - Check whether watermarks need updating | |
12567 | * @plane: drm plane | |
12568 | * @state: new plane state | |
12569 | * | |
12570 | * Check current plane state versus the new one to determine whether | |
12571 | * watermarks need to be recalculated. | |
12572 | * | |
12573 | * Returns true or false. | |
12574 | */ | |
12575 | bool intel_wm_need_update(struct drm_plane *plane, | |
12576 | struct drm_plane_state *state) | |
12577 | { | |
12578 | /* Update watermarks on tiling changes. */ | |
12579 | if (!plane->state->fb || !state->fb || | |
12580 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
12581 | plane->state->rotation != state->rotation) | |
12582 | return true; | |
12583 | ||
12584 | return false; | |
12585 | } | |
12586 | ||
6beb8c23 MR |
12587 | /** |
12588 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12589 | * @plane: drm plane to prepare for | |
12590 | * @fb: framebuffer to prepare for presentation | |
12591 | * | |
12592 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12593 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12594 | * bits. Some older platforms need special physical address handling for | |
12595 | * cursor planes. | |
12596 | * | |
12597 | * Returns 0 on success, negative error code on failure. | |
12598 | */ | |
12599 | int | |
12600 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12601 | struct drm_framebuffer *fb, |
12602 | const struct drm_plane_state *new_state) | |
465c120c MR |
12603 | { |
12604 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
12605 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12606 | enum pipe pipe = intel_plane->pipe; | |
12607 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12608 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12609 | unsigned frontbuffer_bits = 0; | |
12610 | int ret = 0; | |
465c120c | 12611 | |
ea2c67bb | 12612 | if (!obj) |
465c120c MR |
12613 | return 0; |
12614 | ||
6beb8c23 MR |
12615 | switch (plane->type) { |
12616 | case DRM_PLANE_TYPE_PRIMARY: | |
12617 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12618 | break; | |
12619 | case DRM_PLANE_TYPE_CURSOR: | |
12620 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12621 | break; | |
12622 | case DRM_PLANE_TYPE_OVERLAY: | |
12623 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
12624 | break; | |
12625 | } | |
465c120c | 12626 | |
6beb8c23 | 12627 | mutex_lock(&dev->struct_mutex); |
465c120c | 12628 | |
6beb8c23 MR |
12629 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12630 | INTEL_INFO(dev)->cursor_needs_physical) { | |
12631 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
12632 | ret = i915_gem_object_attach_phys(obj, align); | |
12633 | if (ret) | |
12634 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12635 | } else { | |
82bc3b2d | 12636 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 12637 | } |
465c120c | 12638 | |
6beb8c23 MR |
12639 | if (ret == 0) |
12640 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 12641 | |
4c34574f | 12642 | mutex_unlock(&dev->struct_mutex); |
465c120c | 12643 | |
6beb8c23 MR |
12644 | return ret; |
12645 | } | |
12646 | ||
38f3ce3a MR |
12647 | /** |
12648 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12649 | * @plane: drm plane to clean up for | |
12650 | * @fb: old framebuffer that was on plane | |
12651 | * | |
12652 | * Cleans up a framebuffer that has just been removed from a plane. | |
12653 | */ | |
12654 | void | |
12655 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12656 | struct drm_framebuffer *fb, |
12657 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
12658 | { |
12659 | struct drm_device *dev = plane->dev; | |
12660 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12661 | ||
12662 | if (WARN_ON(!obj)) | |
12663 | return; | |
12664 | ||
12665 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
12666 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
12667 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 12668 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
12669 | mutex_unlock(&dev->struct_mutex); |
12670 | } | |
465c120c MR |
12671 | } |
12672 | ||
12673 | static int | |
3c692a41 GP |
12674 | intel_check_primary_plane(struct drm_plane *plane, |
12675 | struct intel_plane_state *state) | |
12676 | { | |
32b7eeec MR |
12677 | struct drm_device *dev = plane->dev; |
12678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 12679 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12680 | struct intel_crtc *intel_crtc; |
2b875c22 | 12681 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
12682 | struct drm_rect *dest = &state->dst; |
12683 | struct drm_rect *src = &state->src; | |
12684 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 12685 | bool can_position = false; |
465c120c MR |
12686 | int ret; |
12687 | ||
ea2c67bb MR |
12688 | crtc = crtc ? crtc : plane->crtc; |
12689 | intel_crtc = to_intel_crtc(crtc); | |
12690 | ||
d8106366 SJ |
12691 | if (INTEL_INFO(dev)->gen >= 9) |
12692 | can_position = true; | |
12693 | ||
c59cb179 MR |
12694 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
12695 | src, dest, clip, | |
12696 | DRM_PLANE_HELPER_NO_SCALING, | |
12697 | DRM_PLANE_HELPER_NO_SCALING, | |
d8106366 SJ |
12698 | can_position, true, |
12699 | &state->visible); | |
c59cb179 MR |
12700 | if (ret) |
12701 | return ret; | |
465c120c | 12702 | |
32b7eeec MR |
12703 | if (intel_crtc->active) { |
12704 | intel_crtc->atomic.wait_for_flips = true; | |
12705 | ||
12706 | /* | |
12707 | * FBC does not work on some platforms for rotated | |
12708 | * planes, so disable it when rotation is not 0 and | |
12709 | * update it when rotation is set back to 0. | |
12710 | * | |
12711 | * FIXME: This is redundant with the fbc update done in | |
12712 | * the primary plane enable function except that that | |
12713 | * one is done too late. We eventually need to unify | |
12714 | * this. | |
12715 | */ | |
12716 | if (intel_crtc->primary_enabled && | |
12717 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 12718 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 12719 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
12720 | intel_crtc->atomic.disable_fbc = true; |
12721 | } | |
12722 | ||
12723 | if (state->visible) { | |
12724 | /* | |
12725 | * BDW signals flip done immediately if the plane | |
12726 | * is disabled, even if the plane enable is already | |
12727 | * armed to occur at the next vblank :( | |
12728 | */ | |
12729 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
12730 | intel_crtc->atomic.wait_vblank = true; | |
12731 | } | |
12732 | ||
12733 | intel_crtc->atomic.fb_bits |= | |
12734 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
12735 | ||
12736 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 12737 | |
1fc0a8f7 | 12738 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 12739 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
12740 | } |
12741 | ||
14af293f GP |
12742 | return 0; |
12743 | } | |
12744 | ||
12745 | static void | |
12746 | intel_commit_primary_plane(struct drm_plane *plane, | |
12747 | struct intel_plane_state *state) | |
12748 | { | |
2b875c22 MR |
12749 | struct drm_crtc *crtc = state->base.crtc; |
12750 | struct drm_framebuffer *fb = state->base.fb; | |
12751 | struct drm_device *dev = plane->dev; | |
14af293f | 12752 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 12753 | struct intel_crtc *intel_crtc; |
14af293f GP |
12754 | struct drm_rect *src = &state->src; |
12755 | ||
ea2c67bb MR |
12756 | crtc = crtc ? crtc : plane->crtc; |
12757 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
12758 | |
12759 | plane->fb = fb; | |
9dc806fc MR |
12760 | crtc->x = src->x1 >> 16; |
12761 | crtc->y = src->y1 >> 16; | |
ccc759dc | 12762 | |
ccc759dc | 12763 | if (intel_crtc->active) { |
ccc759dc | 12764 | if (state->visible) { |
ccc759dc GP |
12765 | /* FIXME: kill this fastboot hack */ |
12766 | intel_update_pipe_size(intel_crtc); | |
465c120c | 12767 | |
ccc759dc | 12768 | intel_crtc->primary_enabled = true; |
465c120c | 12769 | |
ccc759dc GP |
12770 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
12771 | crtc->x, crtc->y); | |
ccc759dc GP |
12772 | } else { |
12773 | /* | |
12774 | * If clipping results in a non-visible primary plane, | |
12775 | * we'll disable the primary plane. Note that this is | |
12776 | * a bit different than what happens if userspace | |
12777 | * explicitly disables the plane by passing fb=0 | |
12778 | * because plane->fb still gets set and pinned. | |
12779 | */ | |
12780 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 12781 | } |
ccc759dc | 12782 | } |
465c120c MR |
12783 | } |
12784 | ||
32b7eeec | 12785 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 12786 | { |
32b7eeec | 12787 | struct drm_device *dev = crtc->dev; |
140fd38d | 12788 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 12789 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
12790 | struct intel_plane *intel_plane; |
12791 | struct drm_plane *p; | |
12792 | unsigned fb_bits = 0; | |
12793 | ||
12794 | /* Track fb's for any planes being disabled */ | |
12795 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
12796 | intel_plane = to_intel_plane(p); | |
12797 | ||
12798 | if (intel_crtc->atomic.disabled_planes & | |
12799 | (1 << drm_plane_index(p))) { | |
12800 | switch (p->type) { | |
12801 | case DRM_PLANE_TYPE_PRIMARY: | |
12802 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
12803 | break; | |
12804 | case DRM_PLANE_TYPE_CURSOR: | |
12805 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
12806 | break; | |
12807 | case DRM_PLANE_TYPE_OVERLAY: | |
12808 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
12809 | break; | |
12810 | } | |
3c692a41 | 12811 | |
ea2c67bb MR |
12812 | mutex_lock(&dev->struct_mutex); |
12813 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
12814 | mutex_unlock(&dev->struct_mutex); | |
12815 | } | |
12816 | } | |
3c692a41 | 12817 | |
32b7eeec MR |
12818 | if (intel_crtc->atomic.wait_for_flips) |
12819 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 12820 | |
32b7eeec MR |
12821 | if (intel_crtc->atomic.disable_fbc) |
12822 | intel_fbc_disable(dev); | |
3c692a41 | 12823 | |
32b7eeec MR |
12824 | if (intel_crtc->atomic.pre_disable_primary) |
12825 | intel_pre_disable_primary(crtc); | |
3c692a41 | 12826 | |
32b7eeec MR |
12827 | if (intel_crtc->atomic.update_wm) |
12828 | intel_update_watermarks(crtc); | |
3c692a41 | 12829 | |
32b7eeec | 12830 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 12831 | |
c34c9ee4 MR |
12832 | /* Perform vblank evasion around commit operation */ |
12833 | if (intel_crtc->active) | |
12834 | intel_crtc->atomic.evade = | |
12835 | intel_pipe_update_start(intel_crtc, | |
12836 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
12837 | } |
12838 | ||
12839 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
12840 | { | |
12841 | struct drm_device *dev = crtc->dev; | |
12842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12843 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12844 | struct drm_plane *p; | |
12845 | ||
c34c9ee4 MR |
12846 | if (intel_crtc->atomic.evade) |
12847 | intel_pipe_update_end(intel_crtc, | |
12848 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 12849 | |
140fd38d | 12850 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 12851 | |
32b7eeec MR |
12852 | if (intel_crtc->atomic.wait_vblank) |
12853 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
12854 | ||
12855 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
12856 | ||
12857 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 12858 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 12859 | intel_fbc_update(dev); |
ccc759dc | 12860 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 12861 | } |
3c692a41 | 12862 | |
32b7eeec MR |
12863 | if (intel_crtc->atomic.post_enable_primary) |
12864 | intel_post_enable_primary(crtc); | |
3c692a41 | 12865 | |
32b7eeec MR |
12866 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
12867 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
12868 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
12869 | false, false); | |
12870 | ||
12871 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
12872 | } |
12873 | ||
cf4c7c12 | 12874 | /** |
4a3b8769 MR |
12875 | * intel_plane_destroy - destroy a plane |
12876 | * @plane: plane to destroy | |
cf4c7c12 | 12877 | * |
4a3b8769 MR |
12878 | * Common destruction function for all types of planes (primary, cursor, |
12879 | * sprite). | |
cf4c7c12 | 12880 | */ |
4a3b8769 | 12881 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
12882 | { |
12883 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12884 | drm_plane_cleanup(plane); | |
12885 | kfree(intel_plane); | |
12886 | } | |
12887 | ||
65a3fea0 | 12888 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
12889 | .update_plane = drm_atomic_helper_update_plane, |
12890 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 12891 | .destroy = intel_plane_destroy, |
c196e1d6 | 12892 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
12893 | .atomic_get_property = intel_plane_atomic_get_property, |
12894 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12895 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12896 | .atomic_destroy_state = intel_plane_destroy_state, | |
12897 | ||
465c120c MR |
12898 | }; |
12899 | ||
12900 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
12901 | int pipe) | |
12902 | { | |
12903 | struct intel_plane *primary; | |
8e7d688b | 12904 | struct intel_plane_state *state; |
465c120c MR |
12905 | const uint32_t *intel_primary_formats; |
12906 | int num_formats; | |
12907 | ||
12908 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
12909 | if (primary == NULL) | |
12910 | return NULL; | |
12911 | ||
8e7d688b MR |
12912 | state = intel_create_plane_state(&primary->base); |
12913 | if (!state) { | |
ea2c67bb MR |
12914 | kfree(primary); |
12915 | return NULL; | |
12916 | } | |
8e7d688b | 12917 | primary->base.state = &state->base; |
ea2c67bb | 12918 | |
465c120c MR |
12919 | primary->can_scale = false; |
12920 | primary->max_downscale = 1; | |
549e2bfb | 12921 | state->scaler_id = -1; |
465c120c MR |
12922 | primary->pipe = pipe; |
12923 | primary->plane = pipe; | |
c59cb179 MR |
12924 | primary->check_plane = intel_check_primary_plane; |
12925 | primary->commit_plane = intel_commit_primary_plane; | |
08e221fb | 12926 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
12927 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
12928 | primary->plane = !pipe; | |
12929 | ||
12930 | if (INTEL_INFO(dev)->gen <= 3) { | |
12931 | intel_primary_formats = intel_primary_formats_gen2; | |
12932 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
12933 | } else { | |
12934 | intel_primary_formats = intel_primary_formats_gen4; | |
12935 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
12936 | } | |
12937 | ||
12938 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 12939 | &intel_plane_funcs, |
465c120c MR |
12940 | intel_primary_formats, num_formats, |
12941 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 12942 | |
3b7a5119 SJ |
12943 | if (INTEL_INFO(dev)->gen >= 4) |
12944 | intel_create_rotation_property(dev, primary); | |
48404c1e | 12945 | |
ea2c67bb MR |
12946 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12947 | ||
465c120c MR |
12948 | return &primary->base; |
12949 | } | |
12950 | ||
3b7a5119 SJ |
12951 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
12952 | { | |
12953 | if (!dev->mode_config.rotation_property) { | |
12954 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
12955 | BIT(DRM_ROTATE_180); | |
12956 | ||
12957 | if (INTEL_INFO(dev)->gen >= 9) | |
12958 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
12959 | ||
12960 | dev->mode_config.rotation_property = | |
12961 | drm_mode_create_rotation_property(dev, flags); | |
12962 | } | |
12963 | if (dev->mode_config.rotation_property) | |
12964 | drm_object_attach_property(&plane->base.base, | |
12965 | dev->mode_config.rotation_property, | |
12966 | plane->base.state->rotation); | |
12967 | } | |
12968 | ||
3d7d6510 | 12969 | static int |
852e787c GP |
12970 | intel_check_cursor_plane(struct drm_plane *plane, |
12971 | struct intel_plane_state *state) | |
3d7d6510 | 12972 | { |
2b875c22 | 12973 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12974 | struct drm_device *dev = plane->dev; |
2b875c22 | 12975 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12976 | struct drm_rect *dest = &state->dst; |
12977 | struct drm_rect *src = &state->src; | |
12978 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 12979 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 12980 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
12981 | unsigned stride; |
12982 | int ret; | |
3d7d6510 | 12983 | |
ea2c67bb MR |
12984 | crtc = crtc ? crtc : plane->crtc; |
12985 | intel_crtc = to_intel_crtc(crtc); | |
12986 | ||
757f9a3e | 12987 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12988 | src, dest, clip, |
3d7d6510 MR |
12989 | DRM_PLANE_HELPER_NO_SCALING, |
12990 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12991 | true, true, &state->visible); |
757f9a3e GP |
12992 | if (ret) |
12993 | return ret; | |
12994 | ||
12995 | ||
12996 | /* if we want to turn off the cursor ignore width and height */ | |
12997 | if (!obj) | |
32b7eeec | 12998 | goto finish; |
757f9a3e | 12999 | |
757f9a3e | 13000 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13001 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13002 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13003 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13004 | return -EINVAL; |
13005 | } | |
13006 | ||
ea2c67bb MR |
13007 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13008 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13009 | DRM_DEBUG_KMS("buffer is too small\n"); |
13010 | return -ENOMEM; | |
13011 | } | |
13012 | ||
3a656b54 | 13013 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13014 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13015 | ret = -EINVAL; | |
13016 | } | |
757f9a3e | 13017 | |
32b7eeec MR |
13018 | finish: |
13019 | if (intel_crtc->active) { | |
3749f463 | 13020 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13021 | intel_crtc->atomic.update_wm = true; |
13022 | ||
13023 | intel_crtc->atomic.fb_bits |= | |
13024 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13025 | } | |
13026 | ||
757f9a3e | 13027 | return ret; |
852e787c | 13028 | } |
3d7d6510 | 13029 | |
f4a2cf29 | 13030 | static void |
852e787c GP |
13031 | intel_commit_cursor_plane(struct drm_plane *plane, |
13032 | struct intel_plane_state *state) | |
13033 | { | |
2b875c22 | 13034 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13035 | struct drm_device *dev = plane->dev; |
13036 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13037 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13038 | uint32_t addr; |
852e787c | 13039 | |
ea2c67bb MR |
13040 | crtc = crtc ? crtc : plane->crtc; |
13041 | intel_crtc = to_intel_crtc(crtc); | |
13042 | ||
2b875c22 | 13043 | plane->fb = state->base.fb; |
ea2c67bb MR |
13044 | crtc->cursor_x = state->base.crtc_x; |
13045 | crtc->cursor_y = state->base.crtc_y; | |
13046 | ||
a912f12f GP |
13047 | if (intel_crtc->cursor_bo == obj) |
13048 | goto update; | |
4ed91096 | 13049 | |
f4a2cf29 | 13050 | if (!obj) |
a912f12f | 13051 | addr = 0; |
f4a2cf29 | 13052 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13053 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13054 | else |
a912f12f | 13055 | addr = obj->phys_handle->busaddr; |
852e787c | 13056 | |
a912f12f GP |
13057 | intel_crtc->cursor_addr = addr; |
13058 | intel_crtc->cursor_bo = obj; | |
13059 | update: | |
852e787c | 13060 | |
32b7eeec | 13061 | if (intel_crtc->active) |
a912f12f | 13062 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13063 | } |
13064 | ||
3d7d6510 MR |
13065 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13066 | int pipe) | |
13067 | { | |
13068 | struct intel_plane *cursor; | |
8e7d688b | 13069 | struct intel_plane_state *state; |
3d7d6510 MR |
13070 | |
13071 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13072 | if (cursor == NULL) | |
13073 | return NULL; | |
13074 | ||
8e7d688b MR |
13075 | state = intel_create_plane_state(&cursor->base); |
13076 | if (!state) { | |
ea2c67bb MR |
13077 | kfree(cursor); |
13078 | return NULL; | |
13079 | } | |
8e7d688b | 13080 | cursor->base.state = &state->base; |
ea2c67bb | 13081 | |
3d7d6510 MR |
13082 | cursor->can_scale = false; |
13083 | cursor->max_downscale = 1; | |
13084 | cursor->pipe = pipe; | |
13085 | cursor->plane = pipe; | |
549e2bfb | 13086 | state->scaler_id = -1; |
c59cb179 MR |
13087 | cursor->check_plane = intel_check_cursor_plane; |
13088 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
13089 | |
13090 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13091 | &intel_plane_funcs, |
3d7d6510 MR |
13092 | intel_cursor_formats, |
13093 | ARRAY_SIZE(intel_cursor_formats), | |
13094 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13095 | |
13096 | if (INTEL_INFO(dev)->gen >= 4) { | |
13097 | if (!dev->mode_config.rotation_property) | |
13098 | dev->mode_config.rotation_property = | |
13099 | drm_mode_create_rotation_property(dev, | |
13100 | BIT(DRM_ROTATE_0) | | |
13101 | BIT(DRM_ROTATE_180)); | |
13102 | if (dev->mode_config.rotation_property) | |
13103 | drm_object_attach_property(&cursor->base.base, | |
13104 | dev->mode_config.rotation_property, | |
8e7d688b | 13105 | state->base.rotation); |
4398ad45 VS |
13106 | } |
13107 | ||
ea2c67bb MR |
13108 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13109 | ||
3d7d6510 MR |
13110 | return &cursor->base; |
13111 | } | |
13112 | ||
549e2bfb CK |
13113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13114 | struct intel_crtc_state *crtc_state) | |
13115 | { | |
13116 | int i; | |
13117 | struct intel_scaler *intel_scaler; | |
13118 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13119 | ||
13120 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13121 | intel_scaler = &scaler_state->scalers[i]; | |
13122 | intel_scaler->in_use = 0; | |
13123 | intel_scaler->id = i; | |
13124 | ||
13125 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13126 | } | |
13127 | ||
13128 | scaler_state->scaler_id = -1; | |
13129 | } | |
13130 | ||
b358d0a6 | 13131 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13132 | { |
fbee40df | 13133 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13134 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13135 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13136 | struct drm_plane *primary = NULL; |
13137 | struct drm_plane *cursor = NULL; | |
465c120c | 13138 | int i, ret; |
79e53945 | 13139 | |
955382f3 | 13140 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13141 | if (intel_crtc == NULL) |
13142 | return; | |
13143 | ||
f5de6e07 ACO |
13144 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13145 | if (!crtc_state) | |
13146 | goto fail; | |
13147 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 13148 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13149 | |
549e2bfb CK |
13150 | /* initialize shared scalers */ |
13151 | if (INTEL_INFO(dev)->gen >= 9) { | |
13152 | if (pipe == PIPE_C) | |
13153 | intel_crtc->num_scalers = 1; | |
13154 | else | |
13155 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13156 | ||
13157 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13158 | } | |
13159 | ||
465c120c | 13160 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13161 | if (!primary) |
13162 | goto fail; | |
13163 | ||
13164 | cursor = intel_cursor_plane_create(dev, pipe); | |
13165 | if (!cursor) | |
13166 | goto fail; | |
13167 | ||
465c120c | 13168 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13169 | cursor, &intel_crtc_funcs); |
13170 | if (ret) | |
13171 | goto fail; | |
79e53945 JB |
13172 | |
13173 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13174 | for (i = 0; i < 256; i++) { |
13175 | intel_crtc->lut_r[i] = i; | |
13176 | intel_crtc->lut_g[i] = i; | |
13177 | intel_crtc->lut_b[i] = i; | |
13178 | } | |
13179 | ||
1f1c2e24 VS |
13180 | /* |
13181 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13182 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13183 | */ |
80824003 JB |
13184 | intel_crtc->pipe = pipe; |
13185 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13186 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13187 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13188 | intel_crtc->plane = !pipe; |
80824003 JB |
13189 | } |
13190 | ||
4b0e333e CW |
13191 | intel_crtc->cursor_base = ~0; |
13192 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13193 | intel_crtc->cursor_size = ~0; |
8d7849db | 13194 | |
22fd0fab JB |
13195 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13196 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13197 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13198 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13199 | ||
9362c7c5 ACO |
13200 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
13201 | ||
79e53945 | 13202 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13203 | |
13204 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13205 | return; |
13206 | ||
13207 | fail: | |
13208 | if (primary) | |
13209 | drm_plane_cleanup(primary); | |
13210 | if (cursor) | |
13211 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13212 | kfree(crtc_state); |
3d7d6510 | 13213 | kfree(intel_crtc); |
79e53945 JB |
13214 | } |
13215 | ||
752aa88a JB |
13216 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13217 | { | |
13218 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13219 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13220 | |
51fd371b | 13221 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13222 | |
d3babd3f | 13223 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13224 | return INVALID_PIPE; |
13225 | ||
13226 | return to_intel_crtc(encoder->crtc)->pipe; | |
13227 | } | |
13228 | ||
08d7b3d1 | 13229 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13230 | struct drm_file *file) |
08d7b3d1 | 13231 | { |
08d7b3d1 | 13232 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13233 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13234 | struct intel_crtc *crtc; |
08d7b3d1 | 13235 | |
7707e653 | 13236 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13237 | |
7707e653 | 13238 | if (!drmmode_crtc) { |
08d7b3d1 | 13239 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13240 | return -ENOENT; |
08d7b3d1 CW |
13241 | } |
13242 | ||
7707e653 | 13243 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13244 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13245 | |
c05422d5 | 13246 | return 0; |
08d7b3d1 CW |
13247 | } |
13248 | ||
66a9278e | 13249 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13250 | { |
66a9278e DV |
13251 | struct drm_device *dev = encoder->base.dev; |
13252 | struct intel_encoder *source_encoder; | |
79e53945 | 13253 | int index_mask = 0; |
79e53945 JB |
13254 | int entry = 0; |
13255 | ||
b2784e15 | 13256 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13257 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13258 | index_mask |= (1 << entry); |
13259 | ||
79e53945 JB |
13260 | entry++; |
13261 | } | |
4ef69c7a | 13262 | |
79e53945 JB |
13263 | return index_mask; |
13264 | } | |
13265 | ||
4d302442 CW |
13266 | static bool has_edp_a(struct drm_device *dev) |
13267 | { | |
13268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13269 | ||
13270 | if (!IS_MOBILE(dev)) | |
13271 | return false; | |
13272 | ||
13273 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13274 | return false; | |
13275 | ||
e3589908 | 13276 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13277 | return false; |
13278 | ||
13279 | return true; | |
13280 | } | |
13281 | ||
84b4e042 JB |
13282 | static bool intel_crt_present(struct drm_device *dev) |
13283 | { | |
13284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13285 | ||
884497ed DL |
13286 | if (INTEL_INFO(dev)->gen >= 9) |
13287 | return false; | |
13288 | ||
cf404ce4 | 13289 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13290 | return false; |
13291 | ||
13292 | if (IS_CHERRYVIEW(dev)) | |
13293 | return false; | |
13294 | ||
13295 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13296 | return false; | |
13297 | ||
13298 | return true; | |
13299 | } | |
13300 | ||
79e53945 JB |
13301 | static void intel_setup_outputs(struct drm_device *dev) |
13302 | { | |
725e30ad | 13303 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13304 | struct intel_encoder *encoder; |
cb0953d7 | 13305 | bool dpd_is_edp = false; |
79e53945 | 13306 | |
c9093354 | 13307 | intel_lvds_init(dev); |
79e53945 | 13308 | |
84b4e042 | 13309 | if (intel_crt_present(dev)) |
79935fca | 13310 | intel_crt_init(dev); |
cb0953d7 | 13311 | |
affa9354 | 13312 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
13313 | int found; |
13314 | ||
de31facd JB |
13315 | /* |
13316 | * Haswell uses DDI functions to detect digital outputs. | |
13317 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13318 | * it's there. | |
13319 | */ | |
0e72a5b5 | 13320 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13321 | /* WaIgnoreDDIAStrap: skl */ |
13322 | if (found || | |
13323 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13324 | intel_ddi_init(dev, PORT_A); |
13325 | ||
13326 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13327 | * register */ | |
13328 | found = I915_READ(SFUSE_STRAP); | |
13329 | ||
13330 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13331 | intel_ddi_init(dev, PORT_B); | |
13332 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13333 | intel_ddi_init(dev, PORT_C); | |
13334 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13335 | intel_ddi_init(dev, PORT_D); | |
13336 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13337 | int found; |
5d8a7752 | 13338 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13339 | |
13340 | if (has_edp_a(dev)) | |
13341 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13342 | |
dc0fa718 | 13343 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13344 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13345 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13346 | if (!found) |
e2debe91 | 13347 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13348 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13349 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13350 | } |
13351 | ||
dc0fa718 | 13352 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13353 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13354 | |
dc0fa718 | 13355 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13356 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13357 | |
5eb08b69 | 13358 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13359 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13360 | |
270b3042 | 13361 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13362 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13363 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13364 | /* |
13365 | * The DP_DETECTED bit is the latched state of the DDC | |
13366 | * SDA pin at boot. However since eDP doesn't require DDC | |
13367 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13368 | * eDP ports may have been muxed to an alternate function. | |
13369 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13370 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13371 | * detect eDP ports. | |
13372 | */ | |
d2182a66 VS |
13373 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13374 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13375 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13376 | PORT_B); | |
e17ac6db VS |
13377 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13378 | intel_dp_is_edp(dev, PORT_B)) | |
13379 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13380 | |
d2182a66 VS |
13381 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13382 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13383 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13384 | PORT_C); | |
e17ac6db VS |
13385 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13386 | intel_dp_is_edp(dev, PORT_C)) | |
13387 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13388 | |
9418c1f1 | 13389 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13390 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13391 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13392 | PORT_D); | |
e17ac6db VS |
13393 | /* eDP not supported on port D, so don't check VBT */ |
13394 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13395 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13396 | } |
13397 | ||
3cfca973 | 13398 | intel_dsi_init(dev); |
103a196f | 13399 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13400 | bool found = false; |
7d57382e | 13401 | |
e2debe91 | 13402 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13403 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13404 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13405 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13406 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13407 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13408 | } |
27185ae1 | 13409 | |
e7281eab | 13410 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13411 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13412 | } |
13520b05 KH |
13413 | |
13414 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13415 | |
e2debe91 | 13416 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13417 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13418 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13419 | } |
27185ae1 | 13420 | |
e2debe91 | 13421 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13422 | |
b01f2c3a JB |
13423 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13424 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13425 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13426 | } |
e7281eab | 13427 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13428 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13429 | } |
27185ae1 | 13430 | |
b01f2c3a | 13431 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13432 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13433 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13434 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13435 | intel_dvo_init(dev); |
13436 | ||
103a196f | 13437 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13438 | intel_tv_init(dev); |
13439 | ||
0bc12bcb | 13440 | intel_psr_init(dev); |
7c8f8a70 | 13441 | |
b2784e15 | 13442 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13443 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13444 | encoder->base.possible_clones = | |
66a9278e | 13445 | intel_encoder_clones(encoder); |
79e53945 | 13446 | } |
47356eb6 | 13447 | |
dde86e2d | 13448 | intel_init_pch_refclk(dev); |
270b3042 DV |
13449 | |
13450 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13451 | } |
13452 | ||
13453 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13454 | { | |
60a5ca01 | 13455 | struct drm_device *dev = fb->dev; |
79e53945 | 13456 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13457 | |
ef2d633e | 13458 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13459 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13460 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13461 | drm_gem_object_unreference(&intel_fb->obj->base); |
13462 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13463 | kfree(intel_fb); |
13464 | } | |
13465 | ||
13466 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13467 | struct drm_file *file, |
79e53945 JB |
13468 | unsigned int *handle) |
13469 | { | |
13470 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13471 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13472 | |
05394f39 | 13473 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13474 | } |
13475 | ||
13476 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13477 | .destroy = intel_user_framebuffer_destroy, | |
13478 | .create_handle = intel_user_framebuffer_create_handle, | |
13479 | }; | |
13480 | ||
b321803d DL |
13481 | static |
13482 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13483 | uint32_t pixel_format) | |
13484 | { | |
13485 | u32 gen = INTEL_INFO(dev)->gen; | |
13486 | ||
13487 | if (gen >= 9) { | |
13488 | /* "The stride in bytes must not exceed the of the size of 8K | |
13489 | * pixels and 32K bytes." | |
13490 | */ | |
13491 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13492 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13493 | return 32*1024; | |
13494 | } else if (gen >= 4) { | |
13495 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13496 | return 16*1024; | |
13497 | else | |
13498 | return 32*1024; | |
13499 | } else if (gen >= 3) { | |
13500 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13501 | return 8*1024; | |
13502 | else | |
13503 | return 16*1024; | |
13504 | } else { | |
13505 | /* XXX DSPC is limited to 4k tiled */ | |
13506 | return 8*1024; | |
13507 | } | |
13508 | } | |
13509 | ||
b5ea642a DV |
13510 | static int intel_framebuffer_init(struct drm_device *dev, |
13511 | struct intel_framebuffer *intel_fb, | |
13512 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13513 | struct drm_i915_gem_object *obj) | |
79e53945 | 13514 | { |
6761dd31 | 13515 | unsigned int aligned_height; |
79e53945 | 13516 | int ret; |
b321803d | 13517 | u32 pitch_limit, stride_alignment; |
79e53945 | 13518 | |
dd4916c5 DV |
13519 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13520 | ||
2a80eada DV |
13521 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13522 | /* Enforce that fb modifier and tiling mode match, but only for | |
13523 | * X-tiled. This is needed for FBC. */ | |
13524 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13525 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13526 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13527 | return -EINVAL; | |
13528 | } | |
13529 | } else { | |
13530 | if (obj->tiling_mode == I915_TILING_X) | |
13531 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13532 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13533 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13534 | return -EINVAL; | |
13535 | } | |
13536 | } | |
13537 | ||
9a8f0a12 TU |
13538 | /* Passed in modifier sanity checking. */ |
13539 | switch (mode_cmd->modifier[0]) { | |
13540 | case I915_FORMAT_MOD_Y_TILED: | |
13541 | case I915_FORMAT_MOD_Yf_TILED: | |
13542 | if (INTEL_INFO(dev)->gen < 9) { | |
13543 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13544 | mode_cmd->modifier[0]); | |
13545 | return -EINVAL; | |
13546 | } | |
13547 | case DRM_FORMAT_MOD_NONE: | |
13548 | case I915_FORMAT_MOD_X_TILED: | |
13549 | break; | |
13550 | default: | |
c0f40428 JB |
13551 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13552 | mode_cmd->modifier[0]); | |
57cd6508 | 13553 | return -EINVAL; |
c16ed4be | 13554 | } |
57cd6508 | 13555 | |
b321803d DL |
13556 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13557 | mode_cmd->pixel_format); | |
13558 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13559 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13560 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13561 | return -EINVAL; |
c16ed4be | 13562 | } |
57cd6508 | 13563 | |
b321803d DL |
13564 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
13565 | mode_cmd->pixel_format); | |
a35cdaa0 | 13566 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
13567 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
13568 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 13569 | "tiled" : "linear", |
a35cdaa0 | 13570 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 13571 | return -EINVAL; |
c16ed4be | 13572 | } |
5d7bd705 | 13573 | |
2a80eada | 13574 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
13575 | mode_cmd->pitches[0] != obj->stride) { |
13576 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
13577 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 13578 | return -EINVAL; |
c16ed4be | 13579 | } |
5d7bd705 | 13580 | |
57779d06 | 13581 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13582 | switch (mode_cmd->pixel_format) { |
57779d06 | 13583 | case DRM_FORMAT_C8: |
04b3924d VS |
13584 | case DRM_FORMAT_RGB565: |
13585 | case DRM_FORMAT_XRGB8888: | |
13586 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13587 | break; |
13588 | case DRM_FORMAT_XRGB1555: | |
13589 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 13590 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
13591 | DRM_DEBUG("unsupported pixel format: %s\n", |
13592 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13593 | return -EINVAL; |
c16ed4be | 13594 | } |
57779d06 VS |
13595 | break; |
13596 | case DRM_FORMAT_XBGR8888: | |
13597 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
13598 | case DRM_FORMAT_XRGB2101010: |
13599 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
13600 | case DRM_FORMAT_XBGR2101010: |
13601 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 13602 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
13603 | DRM_DEBUG("unsupported pixel format: %s\n", |
13604 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13605 | return -EINVAL; |
c16ed4be | 13606 | } |
b5626747 | 13607 | break; |
04b3924d VS |
13608 | case DRM_FORMAT_YUYV: |
13609 | case DRM_FORMAT_UYVY: | |
13610 | case DRM_FORMAT_YVYU: | |
13611 | case DRM_FORMAT_VYUY: | |
c16ed4be | 13612 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
13613 | DRM_DEBUG("unsupported pixel format: %s\n", |
13614 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13615 | return -EINVAL; |
c16ed4be | 13616 | } |
57cd6508 CW |
13617 | break; |
13618 | default: | |
4ee62c76 VS |
13619 | DRM_DEBUG("unsupported pixel format: %s\n", |
13620 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
13621 | return -EINVAL; |
13622 | } | |
13623 | ||
90f9a336 VS |
13624 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13625 | if (mode_cmd->offsets[0] != 0) | |
13626 | return -EINVAL; | |
13627 | ||
ec2c981e | 13628 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
13629 | mode_cmd->pixel_format, |
13630 | mode_cmd->modifier[0]); | |
53155c0a DV |
13631 | /* FIXME drm helper for size checks (especially planar formats)? */ |
13632 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
13633 | return -EINVAL; | |
13634 | ||
c7d73f6a DV |
13635 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
13636 | intel_fb->obj = obj; | |
80075d49 | 13637 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 13638 | |
79e53945 JB |
13639 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
13640 | if (ret) { | |
13641 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
13642 | return ret; | |
13643 | } | |
13644 | ||
79e53945 JB |
13645 | return 0; |
13646 | } | |
13647 | ||
79e53945 JB |
13648 | static struct drm_framebuffer * |
13649 | intel_user_framebuffer_create(struct drm_device *dev, | |
13650 | struct drm_file *filp, | |
308e5bcb | 13651 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 13652 | { |
05394f39 | 13653 | struct drm_i915_gem_object *obj; |
79e53945 | 13654 | |
308e5bcb JB |
13655 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
13656 | mode_cmd->handles[0])); | |
c8725226 | 13657 | if (&obj->base == NULL) |
cce13ff7 | 13658 | return ERR_PTR(-ENOENT); |
79e53945 | 13659 | |
d2dff872 | 13660 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
13661 | } |
13662 | ||
4520f53a | 13663 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 13664 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
13665 | { |
13666 | } | |
13667 | #endif | |
13668 | ||
79e53945 | 13669 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 13670 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 13671 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
13672 | .atomic_check = intel_atomic_check, |
13673 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
13674 | }; |
13675 | ||
e70236a8 JB |
13676 | /* Set up chip specific display functions */ |
13677 | static void intel_init_display(struct drm_device *dev) | |
13678 | { | |
13679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13680 | ||
ee9300bb DV |
13681 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
13682 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
13683 | else if (IS_CHERRYVIEW(dev)) |
13684 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
13685 | else if (IS_VALLEYVIEW(dev)) |
13686 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
13687 | else if (IS_PINEVIEW(dev)) | |
13688 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
13689 | else | |
13690 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
13691 | ||
bc8d7dff DL |
13692 | if (INTEL_INFO(dev)->gen >= 9) { |
13693 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
13694 | dev_priv->display.get_initial_plane_config = |
13695 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
13696 | dev_priv->display.crtc_compute_clock = |
13697 | haswell_crtc_compute_clock; | |
13698 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
13699 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
13700 | dev_priv->display.off = ironlake_crtc_off; | |
13701 | dev_priv->display.update_primary_plane = | |
13702 | skylake_update_primary_plane; | |
13703 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 13704 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13705 | dev_priv->display.get_initial_plane_config = |
13706 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
13707 | dev_priv->display.crtc_compute_clock = |
13708 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
13709 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
13710 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 13711 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
13712 | dev_priv->display.update_primary_plane = |
13713 | ironlake_update_primary_plane; | |
09b4ddf9 | 13714 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 13715 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
13716 | dev_priv->display.get_initial_plane_config = |
13717 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
13718 | dev_priv->display.crtc_compute_clock = |
13719 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
13720 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
13721 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 13722 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
13723 | dev_priv->display.update_primary_plane = |
13724 | ironlake_update_primary_plane; | |
89b667f8 JB |
13725 | } else if (IS_VALLEYVIEW(dev)) { |
13726 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
13727 | dev_priv->display.get_initial_plane_config = |
13728 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13729 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
13730 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
13731 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
13732 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
13733 | dev_priv->display.update_primary_plane = |
13734 | i9xx_update_primary_plane; | |
f564048e | 13735 | } else { |
0e8ffe1b | 13736 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13737 | dev_priv->display.get_initial_plane_config = |
13738 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13739 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
13740 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
13741 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 13742 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
13743 | dev_priv->display.update_primary_plane = |
13744 | i9xx_update_primary_plane; | |
f564048e | 13745 | } |
e70236a8 | 13746 | |
e70236a8 | 13747 | /* Returns the core display clock speed */ |
1652d19e VS |
13748 | if (IS_SKYLAKE(dev)) |
13749 | dev_priv->display.get_display_clock_speed = | |
13750 | skylake_get_display_clock_speed; | |
13751 | else if (IS_BROADWELL(dev)) | |
13752 | dev_priv->display.get_display_clock_speed = | |
13753 | broadwell_get_display_clock_speed; | |
13754 | else if (IS_HASWELL(dev)) | |
13755 | dev_priv->display.get_display_clock_speed = | |
13756 | haswell_get_display_clock_speed; | |
13757 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
13758 | dev_priv->display.get_display_clock_speed = |
13759 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
13760 | else if (IS_GEN5(dev)) |
13761 | dev_priv->display.get_display_clock_speed = | |
13762 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
13763 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
13764 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
13765 | dev_priv->display.get_display_clock_speed = |
13766 | i945_get_display_clock_speed; | |
13767 | else if (IS_I915G(dev)) | |
13768 | dev_priv->display.get_display_clock_speed = | |
13769 | i915_get_display_clock_speed; | |
257a7ffc | 13770 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
13771 | dev_priv->display.get_display_clock_speed = |
13772 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
13773 | else if (IS_PINEVIEW(dev)) |
13774 | dev_priv->display.get_display_clock_speed = | |
13775 | pnv_get_display_clock_speed; | |
e70236a8 JB |
13776 | else if (IS_I915GM(dev)) |
13777 | dev_priv->display.get_display_clock_speed = | |
13778 | i915gm_get_display_clock_speed; | |
13779 | else if (IS_I865G(dev)) | |
13780 | dev_priv->display.get_display_clock_speed = | |
13781 | i865_get_display_clock_speed; | |
f0f8a9ce | 13782 | else if (IS_I85X(dev)) |
e70236a8 JB |
13783 | dev_priv->display.get_display_clock_speed = |
13784 | i855_get_display_clock_speed; | |
13785 | else /* 852, 830 */ | |
13786 | dev_priv->display.get_display_clock_speed = | |
13787 | i830_get_display_clock_speed; | |
13788 | ||
7c10a2b5 | 13789 | if (IS_GEN5(dev)) { |
3bb11b53 | 13790 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
13791 | } else if (IS_GEN6(dev)) { |
13792 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
13793 | } else if (IS_IVYBRIDGE(dev)) { |
13794 | /* FIXME: detect B0+ stepping and use auto training */ | |
13795 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 13796 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 13797 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
13798 | } else if (IS_VALLEYVIEW(dev)) { |
13799 | dev_priv->display.modeset_global_resources = | |
13800 | valleyview_modeset_global_resources; | |
e70236a8 | 13801 | } |
8c9f3aaf | 13802 | |
8c9f3aaf JB |
13803 | switch (INTEL_INFO(dev)->gen) { |
13804 | case 2: | |
13805 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
13806 | break; | |
13807 | ||
13808 | case 3: | |
13809 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
13810 | break; | |
13811 | ||
13812 | case 4: | |
13813 | case 5: | |
13814 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
13815 | break; | |
13816 | ||
13817 | case 6: | |
13818 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
13819 | break; | |
7c9017e5 | 13820 | case 7: |
4e0bbc31 | 13821 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
13822 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
13823 | break; | |
830c81db | 13824 | case 9: |
ba343e02 TU |
13825 | /* Drop through - unsupported since execlist only. */ |
13826 | default: | |
13827 | /* Default just returns -ENODEV to indicate unsupported */ | |
13828 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 13829 | } |
7bd688cd JN |
13830 | |
13831 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
13832 | |
13833 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
13834 | } |
13835 | ||
b690e96c JB |
13836 | /* |
13837 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
13838 | * resume, or other times. This quirk makes sure that's the case for | |
13839 | * affected systems. | |
13840 | */ | |
0206e353 | 13841 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
13842 | { |
13843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13844 | ||
13845 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 13846 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
13847 | } |
13848 | ||
b6b5d049 VS |
13849 | static void quirk_pipeb_force(struct drm_device *dev) |
13850 | { | |
13851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13852 | ||
13853 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
13854 | DRM_INFO("applying pipe b force quirk\n"); | |
13855 | } | |
13856 | ||
435793df KP |
13857 | /* |
13858 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
13859 | */ | |
13860 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
13861 | { | |
13862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13863 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 13864 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
13865 | } |
13866 | ||
4dca20ef | 13867 | /* |
5a15ab5b CE |
13868 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
13869 | * brightness value | |
4dca20ef CE |
13870 | */ |
13871 | static void quirk_invert_brightness(struct drm_device *dev) | |
13872 | { | |
13873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13874 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 13875 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
13876 | } |
13877 | ||
9c72cc6f SD |
13878 | /* Some VBT's incorrectly indicate no backlight is present */ |
13879 | static void quirk_backlight_present(struct drm_device *dev) | |
13880 | { | |
13881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13882 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
13883 | DRM_INFO("applying backlight present quirk\n"); | |
13884 | } | |
13885 | ||
b690e96c JB |
13886 | struct intel_quirk { |
13887 | int device; | |
13888 | int subsystem_vendor; | |
13889 | int subsystem_device; | |
13890 | void (*hook)(struct drm_device *dev); | |
13891 | }; | |
13892 | ||
5f85f176 EE |
13893 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
13894 | struct intel_dmi_quirk { | |
13895 | void (*hook)(struct drm_device *dev); | |
13896 | const struct dmi_system_id (*dmi_id_list)[]; | |
13897 | }; | |
13898 | ||
13899 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
13900 | { | |
13901 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
13902 | return 1; | |
13903 | } | |
13904 | ||
13905 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
13906 | { | |
13907 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
13908 | { | |
13909 | .callback = intel_dmi_reverse_brightness, | |
13910 | .ident = "NCR Corporation", | |
13911 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
13912 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
13913 | }, | |
13914 | }, | |
13915 | { } /* terminating entry */ | |
13916 | }, | |
13917 | .hook = quirk_invert_brightness, | |
13918 | }, | |
13919 | }; | |
13920 | ||
c43b5634 | 13921 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 13922 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 13923 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 13924 | |
b690e96c JB |
13925 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
13926 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
13927 | ||
b690e96c JB |
13928 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
13929 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
13930 | ||
5f080c0f VS |
13931 | /* 830 needs to leave pipe A & dpll A up */ |
13932 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
13933 | ||
b6b5d049 VS |
13934 | /* 830 needs to leave pipe B & dpll B up */ |
13935 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
13936 | ||
435793df KP |
13937 | /* Lenovo U160 cannot use SSC on LVDS */ |
13938 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
13939 | |
13940 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
13941 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 13942 | |
be505f64 AH |
13943 | /* Acer Aspire 5734Z must invert backlight brightness */ |
13944 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
13945 | ||
13946 | /* Acer/eMachines G725 */ | |
13947 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
13948 | ||
13949 | /* Acer/eMachines e725 */ | |
13950 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
13951 | ||
13952 | /* Acer/Packard Bell NCL20 */ | |
13953 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
13954 | ||
13955 | /* Acer Aspire 4736Z */ | |
13956 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
13957 | |
13958 | /* Acer Aspire 5336 */ | |
13959 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
13960 | |
13961 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
13962 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 13963 | |
dfb3d47b SD |
13964 | /* Acer C720 Chromebook (Core i3 4005U) */ |
13965 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
13966 | ||
b2a9601c | 13967 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
13968 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
13969 | ||
d4967d8c SD |
13970 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
13971 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
13972 | |
13973 | /* HP Chromebook 14 (Celeron 2955U) */ | |
13974 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
13975 | |
13976 | /* Dell Chromebook 11 */ | |
13977 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
13978 | }; |
13979 | ||
13980 | static void intel_init_quirks(struct drm_device *dev) | |
13981 | { | |
13982 | struct pci_dev *d = dev->pdev; | |
13983 | int i; | |
13984 | ||
13985 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
13986 | struct intel_quirk *q = &intel_quirks[i]; | |
13987 | ||
13988 | if (d->device == q->device && | |
13989 | (d->subsystem_vendor == q->subsystem_vendor || | |
13990 | q->subsystem_vendor == PCI_ANY_ID) && | |
13991 | (d->subsystem_device == q->subsystem_device || | |
13992 | q->subsystem_device == PCI_ANY_ID)) | |
13993 | q->hook(dev); | |
13994 | } | |
5f85f176 EE |
13995 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
13996 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
13997 | intel_dmi_quirks[i].hook(dev); | |
13998 | } | |
b690e96c JB |
13999 | } |
14000 | ||
9cce37f4 JB |
14001 | /* Disable the VGA plane that we never use */ |
14002 | static void i915_disable_vga(struct drm_device *dev) | |
14003 | { | |
14004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14005 | u8 sr1; | |
766aa1c4 | 14006 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14007 | |
2b37c616 | 14008 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14009 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14010 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14011 | sr1 = inb(VGA_SR_DATA); |
14012 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14013 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14014 | udelay(300); | |
14015 | ||
01f5a626 | 14016 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14017 | POSTING_READ(vga_reg); |
14018 | } | |
14019 | ||
f817586c DV |
14020 | void intel_modeset_init_hw(struct drm_device *dev) |
14021 | { | |
a8f78b58 ED |
14022 | intel_prepare_ddi(dev); |
14023 | ||
f8bf63fd VS |
14024 | if (IS_VALLEYVIEW(dev)) |
14025 | vlv_update_cdclk(dev); | |
14026 | ||
f817586c DV |
14027 | intel_init_clock_gating(dev); |
14028 | ||
8090c6b9 | 14029 | intel_enable_gt_powersave(dev); |
f817586c DV |
14030 | } |
14031 | ||
79e53945 JB |
14032 | void intel_modeset_init(struct drm_device *dev) |
14033 | { | |
652c393a | 14034 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14035 | int sprite, ret; |
8cc87b75 | 14036 | enum pipe pipe; |
46f297fb | 14037 | struct intel_crtc *crtc; |
79e53945 JB |
14038 | |
14039 | drm_mode_config_init(dev); | |
14040 | ||
14041 | dev->mode_config.min_width = 0; | |
14042 | dev->mode_config.min_height = 0; | |
14043 | ||
019d96cb DA |
14044 | dev->mode_config.preferred_depth = 24; |
14045 | dev->mode_config.prefer_shadow = 1; | |
14046 | ||
25bab385 TU |
14047 | dev->mode_config.allow_fb_modifiers = true; |
14048 | ||
e6ecefaa | 14049 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14050 | |
b690e96c JB |
14051 | intel_init_quirks(dev); |
14052 | ||
1fa61106 ED |
14053 | intel_init_pm(dev); |
14054 | ||
e3c74757 BW |
14055 | if (INTEL_INFO(dev)->num_pipes == 0) |
14056 | return; | |
14057 | ||
e70236a8 | 14058 | intel_init_display(dev); |
7c10a2b5 | 14059 | intel_init_audio(dev); |
e70236a8 | 14060 | |
a6c45cf0 CW |
14061 | if (IS_GEN2(dev)) { |
14062 | dev->mode_config.max_width = 2048; | |
14063 | dev->mode_config.max_height = 2048; | |
14064 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14065 | dev->mode_config.max_width = 4096; |
14066 | dev->mode_config.max_height = 4096; | |
79e53945 | 14067 | } else { |
a6c45cf0 CW |
14068 | dev->mode_config.max_width = 8192; |
14069 | dev->mode_config.max_height = 8192; | |
79e53945 | 14070 | } |
068be561 | 14071 | |
dc41c154 VS |
14072 | if (IS_845G(dev) || IS_I865G(dev)) { |
14073 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14074 | dev->mode_config.cursor_height = 1023; | |
14075 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14076 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14077 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14078 | } else { | |
14079 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14080 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14081 | } | |
14082 | ||
5d4545ae | 14083 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14084 | |
28c97730 | 14085 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14086 | INTEL_INFO(dev)->num_pipes, |
14087 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14088 | |
055e393f | 14089 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14090 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14091 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14092 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14093 | if (ret) |
06da8da2 | 14094 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14095 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14096 | } |
79e53945 JB |
14097 | } |
14098 | ||
f42bb70d JB |
14099 | intel_init_dpio(dev); |
14100 | ||
e72f9fbf | 14101 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14102 | |
9cce37f4 JB |
14103 | /* Just disable it once at startup */ |
14104 | i915_disable_vga(dev); | |
79e53945 | 14105 | intel_setup_outputs(dev); |
11be49eb CW |
14106 | |
14107 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14108 | intel_fbc_disable(dev); |
fa9fa083 | 14109 | |
6e9f798d | 14110 | drm_modeset_lock_all(dev); |
fa9fa083 | 14111 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14112 | drm_modeset_unlock_all(dev); |
46f297fb | 14113 | |
d3fcc808 | 14114 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14115 | if (!crtc->active) |
14116 | continue; | |
14117 | ||
46f297fb | 14118 | /* |
46f297fb JB |
14119 | * Note that reserving the BIOS fb up front prevents us |
14120 | * from stuffing other stolen allocations like the ring | |
14121 | * on top. This prevents some ugliness at boot time, and | |
14122 | * can even allow for smooth boot transitions if the BIOS | |
14123 | * fb is large enough for the active pipe configuration. | |
14124 | */ | |
5724dbd1 DL |
14125 | if (dev_priv->display.get_initial_plane_config) { |
14126 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14127 | &crtc->plane_config); |
14128 | /* | |
14129 | * If the fb is shared between multiple heads, we'll | |
14130 | * just get the first one. | |
14131 | */ | |
f6936e29 | 14132 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14133 | } |
46f297fb | 14134 | } |
2c7111db CW |
14135 | } |
14136 | ||
7fad798e DV |
14137 | static void intel_enable_pipe_a(struct drm_device *dev) |
14138 | { | |
14139 | struct intel_connector *connector; | |
14140 | struct drm_connector *crt = NULL; | |
14141 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14142 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14143 | |
14144 | /* We can't just switch on the pipe A, we need to set things up with a | |
14145 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14146 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14147 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14148 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14149 | crt = &connector->base; | |
14150 | break; | |
14151 | } | |
14152 | } | |
14153 | ||
14154 | if (!crt) | |
14155 | return; | |
14156 | ||
208bf9fd | 14157 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14158 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14159 | } |
14160 | ||
fa555837 DV |
14161 | static bool |
14162 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14163 | { | |
7eb552ae BW |
14164 | struct drm_device *dev = crtc->base.dev; |
14165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14166 | u32 reg, val; |
14167 | ||
7eb552ae | 14168 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14169 | return true; |
14170 | ||
14171 | reg = DSPCNTR(!crtc->plane); | |
14172 | val = I915_READ(reg); | |
14173 | ||
14174 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14175 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14176 | return false; | |
14177 | ||
14178 | return true; | |
14179 | } | |
14180 | ||
24929352 DV |
14181 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14182 | { | |
14183 | struct drm_device *dev = crtc->base.dev; | |
14184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14185 | u32 reg; |
24929352 | 14186 | |
24929352 | 14187 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14188 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14189 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14190 | ||
d3eaf884 | 14191 | /* restore vblank interrupts to correct state */ |
9625604c | 14192 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14193 | if (crtc->active) { |
14194 | update_scanline_offset(crtc); | |
9625604c DV |
14195 | drm_crtc_vblank_on(&crtc->base); |
14196 | } | |
d3eaf884 | 14197 | |
24929352 | 14198 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14199 | * disable the crtc (and hence change the state) if it is wrong. Note |
14200 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14201 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14202 | struct intel_connector *connector; |
14203 | bool plane; | |
14204 | ||
24929352 DV |
14205 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14206 | crtc->base.base.id); | |
14207 | ||
14208 | /* Pipe has the wrong plane attached and the plane is active. | |
14209 | * Temporarily change the plane mapping and disable everything | |
14210 | * ... */ | |
14211 | plane = crtc->plane; | |
14212 | crtc->plane = !plane; | |
9c8958bc | 14213 | crtc->primary_enabled = true; |
24929352 DV |
14214 | dev_priv->display.crtc_disable(&crtc->base); |
14215 | crtc->plane = plane; | |
14216 | ||
14217 | /* ... and break all links. */ | |
3a3371ff | 14218 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14219 | if (connector->encoder->base.crtc != &crtc->base) |
14220 | continue; | |
14221 | ||
7f1950fb EE |
14222 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14223 | connector->base.encoder = NULL; | |
24929352 | 14224 | } |
7f1950fb EE |
14225 | /* multiple connectors may have the same encoder: |
14226 | * handle them and break crtc link separately */ | |
3a3371ff | 14227 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14228 | if (connector->encoder->base.crtc == &crtc->base) { |
14229 | connector->encoder->base.crtc = NULL; | |
14230 | connector->encoder->connectors_active = false; | |
14231 | } | |
24929352 DV |
14232 | |
14233 | WARN_ON(crtc->active); | |
83d65738 | 14234 | crtc->base.state->enable = false; |
24929352 DV |
14235 | crtc->base.enabled = false; |
14236 | } | |
24929352 | 14237 | |
7fad798e DV |
14238 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14239 | crtc->pipe == PIPE_A && !crtc->active) { | |
14240 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14241 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14242 | * call below we restore the pipe to the right state, but leave | |
14243 | * the required bits on. */ | |
14244 | intel_enable_pipe_a(dev); | |
14245 | } | |
14246 | ||
24929352 DV |
14247 | /* Adjust the state of the output pipe according to whether we |
14248 | * have active connectors/encoders. */ | |
14249 | intel_crtc_update_dpms(&crtc->base); | |
14250 | ||
83d65738 | 14251 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14252 | struct intel_encoder *encoder; |
14253 | ||
14254 | /* This can happen either due to bugs in the get_hw_state | |
14255 | * functions or because the pipe is force-enabled due to the | |
14256 | * pipe A quirk. */ | |
14257 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14258 | crtc->base.base.id, | |
83d65738 | 14259 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14260 | crtc->active ? "enabled" : "disabled"); |
14261 | ||
83d65738 | 14262 | crtc->base.state->enable = crtc->active; |
24929352 DV |
14263 | crtc->base.enabled = crtc->active; |
14264 | ||
14265 | /* Because we only establish the connector -> encoder -> | |
14266 | * crtc links if something is active, this means the | |
14267 | * crtc is now deactivated. Break the links. connector | |
14268 | * -> encoder links are only establish when things are | |
14269 | * actually up, hence no need to break them. */ | |
14270 | WARN_ON(crtc->active); | |
14271 | ||
14272 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14273 | WARN_ON(encoder->connectors_active); | |
14274 | encoder->base.crtc = NULL; | |
14275 | } | |
14276 | } | |
c5ab3bc0 | 14277 | |
a3ed6aad | 14278 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14279 | /* |
14280 | * We start out with underrun reporting disabled to avoid races. | |
14281 | * For correct bookkeeping mark this on active crtcs. | |
14282 | * | |
c5ab3bc0 DV |
14283 | * Also on gmch platforms we dont have any hardware bits to |
14284 | * disable the underrun reporting. Which means we need to start | |
14285 | * out with underrun reporting disabled also on inactive pipes, | |
14286 | * since otherwise we'll complain about the garbage we read when | |
14287 | * e.g. coming up after runtime pm. | |
14288 | * | |
4cc31489 DV |
14289 | * No protection against concurrent access is required - at |
14290 | * worst a fifo underrun happens which also sets this to false. | |
14291 | */ | |
14292 | crtc->cpu_fifo_underrun_disabled = true; | |
14293 | crtc->pch_fifo_underrun_disabled = true; | |
14294 | } | |
24929352 DV |
14295 | } |
14296 | ||
14297 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14298 | { | |
14299 | struct intel_connector *connector; | |
14300 | struct drm_device *dev = encoder->base.dev; | |
14301 | ||
14302 | /* We need to check both for a crtc link (meaning that the | |
14303 | * encoder is active and trying to read from a pipe) and the | |
14304 | * pipe itself being active. */ | |
14305 | bool has_active_crtc = encoder->base.crtc && | |
14306 | to_intel_crtc(encoder->base.crtc)->active; | |
14307 | ||
14308 | if (encoder->connectors_active && !has_active_crtc) { | |
14309 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14310 | encoder->base.base.id, | |
8e329a03 | 14311 | encoder->base.name); |
24929352 DV |
14312 | |
14313 | /* Connector is active, but has no active pipe. This is | |
14314 | * fallout from our resume register restoring. Disable | |
14315 | * the encoder manually again. */ | |
14316 | if (encoder->base.crtc) { | |
14317 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14318 | encoder->base.base.id, | |
8e329a03 | 14319 | encoder->base.name); |
24929352 | 14320 | encoder->disable(encoder); |
a62d1497 VS |
14321 | if (encoder->post_disable) |
14322 | encoder->post_disable(encoder); | |
24929352 | 14323 | } |
7f1950fb EE |
14324 | encoder->base.crtc = NULL; |
14325 | encoder->connectors_active = false; | |
24929352 DV |
14326 | |
14327 | /* Inconsistent output/port/pipe state happens presumably due to | |
14328 | * a bug in one of the get_hw_state functions. Or someplace else | |
14329 | * in our code, like the register restore mess on resume. Clamp | |
14330 | * things to off as a safer default. */ | |
3a3371ff | 14331 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14332 | if (connector->encoder != encoder) |
14333 | continue; | |
7f1950fb EE |
14334 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14335 | connector->base.encoder = NULL; | |
24929352 DV |
14336 | } |
14337 | } | |
14338 | /* Enabled encoders without active connectors will be fixed in | |
14339 | * the crtc fixup. */ | |
14340 | } | |
14341 | ||
04098753 | 14342 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14343 | { |
14344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14345 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14346 | |
04098753 ID |
14347 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14348 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14349 | i915_disable_vga(dev); | |
14350 | } | |
14351 | } | |
14352 | ||
14353 | void i915_redisable_vga(struct drm_device *dev) | |
14354 | { | |
14355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14356 | ||
8dc8a27c PZ |
14357 | /* This function can be called both from intel_modeset_setup_hw_state or |
14358 | * at a very early point in our resume sequence, where the power well | |
14359 | * structures are not yet restored. Since this function is at a very | |
14360 | * paranoid "someone might have enabled VGA while we were not looking" | |
14361 | * level, just check if the power well is enabled instead of trying to | |
14362 | * follow the "don't touch the power well if we don't need it" policy | |
14363 | * the rest of the driver uses. */ | |
f458ebbc | 14364 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14365 | return; |
14366 | ||
04098753 | 14367 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14368 | } |
14369 | ||
98ec7739 VS |
14370 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14371 | { | |
14372 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14373 | ||
14374 | if (!crtc->active) | |
14375 | return false; | |
14376 | ||
14377 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14378 | } | |
14379 | ||
30e984df | 14380 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14381 | { |
14382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14383 | enum pipe pipe; | |
24929352 DV |
14384 | struct intel_crtc *crtc; |
14385 | struct intel_encoder *encoder; | |
14386 | struct intel_connector *connector; | |
5358901f | 14387 | int i; |
24929352 | 14388 | |
d3fcc808 | 14389 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 14390 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14391 | |
6e3c9717 | 14392 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14393 | |
0e8ffe1b | 14394 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14395 | crtc->config); |
24929352 | 14396 | |
83d65738 | 14397 | crtc->base.state->enable = crtc->active; |
24929352 | 14398 | crtc->base.enabled = crtc->active; |
98ec7739 | 14399 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
14400 | |
14401 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14402 | crtc->base.base.id, | |
14403 | crtc->active ? "enabled" : "disabled"); | |
14404 | } | |
14405 | ||
5358901f DV |
14406 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14407 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14408 | ||
3e369b76 ACO |
14409 | pll->on = pll->get_hw_state(dev_priv, pll, |
14410 | &pll->config.hw_state); | |
5358901f | 14411 | pll->active = 0; |
3e369b76 | 14412 | pll->config.crtc_mask = 0; |
d3fcc808 | 14413 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14414 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14415 | pll->active++; |
3e369b76 | 14416 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14417 | } |
5358901f | 14418 | } |
5358901f | 14419 | |
1e6f2ddc | 14420 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14421 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14422 | |
3e369b76 | 14423 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14424 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14425 | } |
14426 | ||
b2784e15 | 14427 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14428 | pipe = 0; |
14429 | ||
14430 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14431 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14432 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14433 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14434 | } else { |
14435 | encoder->base.crtc = NULL; | |
14436 | } | |
14437 | ||
14438 | encoder->connectors_active = false; | |
6f2bcceb | 14439 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14440 | encoder->base.base.id, |
8e329a03 | 14441 | encoder->base.name, |
24929352 | 14442 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14443 | pipe_name(pipe)); |
24929352 DV |
14444 | } |
14445 | ||
3a3371ff | 14446 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14447 | if (connector->get_hw_state(connector)) { |
14448 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14449 | connector->encoder->connectors_active = true; | |
14450 | connector->base.encoder = &connector->encoder->base; | |
14451 | } else { | |
14452 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14453 | connector->base.encoder = NULL; | |
14454 | } | |
14455 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14456 | connector->base.base.id, | |
c23cc417 | 14457 | connector->base.name, |
24929352 DV |
14458 | connector->base.encoder ? "enabled" : "disabled"); |
14459 | } | |
30e984df DV |
14460 | } |
14461 | ||
14462 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14463 | * and i915 state tracking structures. */ | |
14464 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14465 | bool force_restore) | |
14466 | { | |
14467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14468 | enum pipe pipe; | |
30e984df DV |
14469 | struct intel_crtc *crtc; |
14470 | struct intel_encoder *encoder; | |
35c95375 | 14471 | int i; |
30e984df DV |
14472 | |
14473 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14474 | |
babea61d JB |
14475 | /* |
14476 | * Now that we have the config, copy it to each CRTC struct | |
14477 | * Note that this could go away if we move to using crtc_config | |
14478 | * checking everywhere. | |
14479 | */ | |
d3fcc808 | 14480 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14481 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14482 | intel_mode_from_pipe_config(&crtc->base.mode, |
14483 | crtc->config); | |
babea61d JB |
14484 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14485 | crtc->base.base.id); | |
14486 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14487 | } | |
14488 | } | |
14489 | ||
24929352 | 14490 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14491 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14492 | intel_sanitize_encoder(encoder); |
14493 | } | |
14494 | ||
055e393f | 14495 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14496 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14497 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14498 | intel_dump_pipe_config(crtc, crtc->config, |
14499 | "[setup_hw_state]"); | |
24929352 | 14500 | } |
9a935856 | 14501 | |
d29b2f9d ACO |
14502 | intel_modeset_update_connector_atomic_state(dev); |
14503 | ||
35c95375 DV |
14504 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14505 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14506 | ||
14507 | if (!pll->on || pll->active) | |
14508 | continue; | |
14509 | ||
14510 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14511 | ||
14512 | pll->disable(dev_priv, pll); | |
14513 | pll->on = false; | |
14514 | } | |
14515 | ||
3078999f PB |
14516 | if (IS_GEN9(dev)) |
14517 | skl_wm_get_hw_state(dev); | |
14518 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14519 | ilk_wm_get_hw_state(dev); |
14520 | ||
45e2b5f6 | 14521 | if (force_restore) { |
7d0bc1ea VS |
14522 | i915_redisable_vga(dev); |
14523 | ||
f30da187 DV |
14524 | /* |
14525 | * We need to use raw interfaces for restoring state to avoid | |
14526 | * checking (bogus) intermediate states. | |
14527 | */ | |
055e393f | 14528 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14529 | struct drm_crtc *crtc = |
14530 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14531 | |
83a57153 | 14532 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14533 | } |
14534 | } else { | |
14535 | intel_modeset_update_staged_output_state(dev); | |
14536 | } | |
8af6cf88 DV |
14537 | |
14538 | intel_modeset_check_state(dev); | |
2c7111db CW |
14539 | } |
14540 | ||
14541 | void intel_modeset_gem_init(struct drm_device *dev) | |
14542 | { | |
92122789 | 14543 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14544 | struct drm_crtc *c; |
2ff8fde1 | 14545 | struct drm_i915_gem_object *obj; |
484b41dd | 14546 | |
ae48434c ID |
14547 | mutex_lock(&dev->struct_mutex); |
14548 | intel_init_gt_powersave(dev); | |
14549 | mutex_unlock(&dev->struct_mutex); | |
14550 | ||
92122789 JB |
14551 | /* |
14552 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14553 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14554 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14555 | * indicates as much. | |
14556 | */ | |
14557 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14558 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14559 | DREF_SSC1_ENABLE); | |
14560 | ||
1833b134 | 14561 | intel_modeset_init_hw(dev); |
02e792fb DV |
14562 | |
14563 | intel_setup_overlay(dev); | |
484b41dd JB |
14564 | |
14565 | /* | |
14566 | * Make sure any fbs we allocated at startup are properly | |
14567 | * pinned & fenced. When we do the allocation it's too early | |
14568 | * for this. | |
14569 | */ | |
14570 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 14571 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
14572 | obj = intel_fb_obj(c->primary->fb); |
14573 | if (obj == NULL) | |
484b41dd JB |
14574 | continue; |
14575 | ||
850c4cdc TU |
14576 | if (intel_pin_and_fence_fb_obj(c->primary, |
14577 | c->primary->fb, | |
82bc3b2d | 14578 | c->primary->state, |
850c4cdc | 14579 | NULL)) { |
484b41dd JB |
14580 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
14581 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
14582 | drm_framebuffer_unreference(c->primary->fb); |
14583 | c->primary->fb = NULL; | |
afd65eb4 | 14584 | update_state_fb(c->primary); |
484b41dd JB |
14585 | } |
14586 | } | |
14587 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
14588 | |
14589 | intel_backlight_register(dev); | |
79e53945 JB |
14590 | } |
14591 | ||
4932e2c3 ID |
14592 | void intel_connector_unregister(struct intel_connector *intel_connector) |
14593 | { | |
14594 | struct drm_connector *connector = &intel_connector->base; | |
14595 | ||
14596 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 14597 | drm_connector_unregister(connector); |
4932e2c3 ID |
14598 | } |
14599 | ||
79e53945 JB |
14600 | void intel_modeset_cleanup(struct drm_device *dev) |
14601 | { | |
652c393a | 14602 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 14603 | struct drm_connector *connector; |
652c393a | 14604 | |
2eb5252e ID |
14605 | intel_disable_gt_powersave(dev); |
14606 | ||
0962c3c9 VS |
14607 | intel_backlight_unregister(dev); |
14608 | ||
fd0c0642 DV |
14609 | /* |
14610 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 14611 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
14612 | * experience fancy races otherwise. |
14613 | */ | |
2aeb7d3a | 14614 | intel_irq_uninstall(dev_priv); |
eb21b92b | 14615 | |
fd0c0642 DV |
14616 | /* |
14617 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
14618 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
14619 | */ | |
f87ea761 | 14620 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 14621 | |
652c393a JB |
14622 | mutex_lock(&dev->struct_mutex); |
14623 | ||
723bfd70 JB |
14624 | intel_unregister_dsm_handler(); |
14625 | ||
7ff0ebcc | 14626 | intel_fbc_disable(dev); |
e70236a8 | 14627 | |
69341a5e KH |
14628 | mutex_unlock(&dev->struct_mutex); |
14629 | ||
1630fe75 CW |
14630 | /* flush any delayed tasks or pending work */ |
14631 | flush_scheduled_work(); | |
14632 | ||
db31af1d JN |
14633 | /* destroy the backlight and sysfs files before encoders/connectors */ |
14634 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
14635 | struct intel_connector *intel_connector; |
14636 | ||
14637 | intel_connector = to_intel_connector(connector); | |
14638 | intel_connector->unregister(intel_connector); | |
db31af1d | 14639 | } |
d9255d57 | 14640 | |
79e53945 | 14641 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
14642 | |
14643 | intel_cleanup_overlay(dev); | |
ae48434c ID |
14644 | |
14645 | mutex_lock(&dev->struct_mutex); | |
14646 | intel_cleanup_gt_powersave(dev); | |
14647 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14648 | } |
14649 | ||
f1c79df3 ZW |
14650 | /* |
14651 | * Return which encoder is currently attached for connector. | |
14652 | */ | |
df0e9248 | 14653 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 14654 | { |
df0e9248 CW |
14655 | return &intel_attached_encoder(connector)->base; |
14656 | } | |
f1c79df3 | 14657 | |
df0e9248 CW |
14658 | void intel_connector_attach_encoder(struct intel_connector *connector, |
14659 | struct intel_encoder *encoder) | |
14660 | { | |
14661 | connector->encoder = encoder; | |
14662 | drm_mode_connector_attach_encoder(&connector->base, | |
14663 | &encoder->base); | |
79e53945 | 14664 | } |
28d52043 DA |
14665 | |
14666 | /* | |
14667 | * set vga decode state - true == enable VGA decode | |
14668 | */ | |
14669 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
14670 | { | |
14671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 14672 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
14673 | u16 gmch_ctrl; |
14674 | ||
75fa041d CW |
14675 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
14676 | DRM_ERROR("failed to read control word\n"); | |
14677 | return -EIO; | |
14678 | } | |
14679 | ||
c0cc8a55 CW |
14680 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
14681 | return 0; | |
14682 | ||
28d52043 DA |
14683 | if (state) |
14684 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
14685 | else | |
14686 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
14687 | |
14688 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
14689 | DRM_ERROR("failed to write control word\n"); | |
14690 | return -EIO; | |
14691 | } | |
14692 | ||
28d52043 DA |
14693 | return 0; |
14694 | } | |
c4a1d9e4 | 14695 | |
c4a1d9e4 | 14696 | struct intel_display_error_state { |
ff57f1b0 PZ |
14697 | |
14698 | u32 power_well_driver; | |
14699 | ||
63b66e5b CW |
14700 | int num_transcoders; |
14701 | ||
c4a1d9e4 CW |
14702 | struct intel_cursor_error_state { |
14703 | u32 control; | |
14704 | u32 position; | |
14705 | u32 base; | |
14706 | u32 size; | |
52331309 | 14707 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14708 | |
14709 | struct intel_pipe_error_state { | |
ddf9c536 | 14710 | bool power_domain_on; |
c4a1d9e4 | 14711 | u32 source; |
f301b1e1 | 14712 | u32 stat; |
52331309 | 14713 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14714 | |
14715 | struct intel_plane_error_state { | |
14716 | u32 control; | |
14717 | u32 stride; | |
14718 | u32 size; | |
14719 | u32 pos; | |
14720 | u32 addr; | |
14721 | u32 surface; | |
14722 | u32 tile_offset; | |
52331309 | 14723 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
14724 | |
14725 | struct intel_transcoder_error_state { | |
ddf9c536 | 14726 | bool power_domain_on; |
63b66e5b CW |
14727 | enum transcoder cpu_transcoder; |
14728 | ||
14729 | u32 conf; | |
14730 | ||
14731 | u32 htotal; | |
14732 | u32 hblank; | |
14733 | u32 hsync; | |
14734 | u32 vtotal; | |
14735 | u32 vblank; | |
14736 | u32 vsync; | |
14737 | } transcoder[4]; | |
c4a1d9e4 CW |
14738 | }; |
14739 | ||
14740 | struct intel_display_error_state * | |
14741 | intel_display_capture_error_state(struct drm_device *dev) | |
14742 | { | |
fbee40df | 14743 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 14744 | struct intel_display_error_state *error; |
63b66e5b CW |
14745 | int transcoders[] = { |
14746 | TRANSCODER_A, | |
14747 | TRANSCODER_B, | |
14748 | TRANSCODER_C, | |
14749 | TRANSCODER_EDP, | |
14750 | }; | |
c4a1d9e4 CW |
14751 | int i; |
14752 | ||
63b66e5b CW |
14753 | if (INTEL_INFO(dev)->num_pipes == 0) |
14754 | return NULL; | |
14755 | ||
9d1cb914 | 14756 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
14757 | if (error == NULL) |
14758 | return NULL; | |
14759 | ||
190be112 | 14760 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
14761 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
14762 | ||
055e393f | 14763 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 14764 | error->pipe[i].power_domain_on = |
f458ebbc DV |
14765 | __intel_display_power_is_enabled(dev_priv, |
14766 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 14767 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
14768 | continue; |
14769 | ||
5efb3e28 VS |
14770 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
14771 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
14772 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
14773 | |
14774 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
14775 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 14776 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 14777 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
14778 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
14779 | } | |
ca291363 PZ |
14780 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
14781 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
14782 | if (INTEL_INFO(dev)->gen >= 4) { |
14783 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
14784 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
14785 | } | |
14786 | ||
c4a1d9e4 | 14787 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 14788 | |
3abfce77 | 14789 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 14790 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
14791 | } |
14792 | ||
14793 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
14794 | if (HAS_DDI(dev_priv->dev)) | |
14795 | error->num_transcoders++; /* Account for eDP. */ | |
14796 | ||
14797 | for (i = 0; i < error->num_transcoders; i++) { | |
14798 | enum transcoder cpu_transcoder = transcoders[i]; | |
14799 | ||
ddf9c536 | 14800 | error->transcoder[i].power_domain_on = |
f458ebbc | 14801 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 14802 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 14803 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
14804 | continue; |
14805 | ||
63b66e5b CW |
14806 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
14807 | ||
14808 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
14809 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
14810 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
14811 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
14812 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
14813 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
14814 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
14815 | } |
14816 | ||
14817 | return error; | |
14818 | } | |
14819 | ||
edc3d884 MK |
14820 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
14821 | ||
c4a1d9e4 | 14822 | void |
edc3d884 | 14823 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
14824 | struct drm_device *dev, |
14825 | struct intel_display_error_state *error) | |
14826 | { | |
055e393f | 14827 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
14828 | int i; |
14829 | ||
63b66e5b CW |
14830 | if (!error) |
14831 | return; | |
14832 | ||
edc3d884 | 14833 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 14834 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 14835 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 14836 | error->power_well_driver); |
055e393f | 14837 | for_each_pipe(dev_priv, i) { |
edc3d884 | 14838 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
14839 | err_printf(m, " Power: %s\n", |
14840 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 14841 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 14842 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
14843 | |
14844 | err_printf(m, "Plane [%d]:\n", i); | |
14845 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
14846 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 14847 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
14848 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
14849 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 14850 | } |
4b71a570 | 14851 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 14852 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 14853 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
14854 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
14855 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
14856 | } |
14857 | ||
edc3d884 MK |
14858 | err_printf(m, "Cursor [%d]:\n", i); |
14859 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
14860 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
14861 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 14862 | } |
63b66e5b CW |
14863 | |
14864 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 14865 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 14866 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
14867 | err_printf(m, " Power: %s\n", |
14868 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
14869 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
14870 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
14871 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
14872 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
14873 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
14874 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
14875 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
14876 | } | |
c4a1d9e4 | 14877 | } |
e2fcdaa9 VS |
14878 | |
14879 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
14880 | { | |
14881 | struct intel_crtc *crtc; | |
14882 | ||
14883 | for_each_intel_crtc(dev, crtc) { | |
14884 | struct intel_unpin_work *work; | |
e2fcdaa9 | 14885 | |
5e2d7afc | 14886 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14887 | |
14888 | work = crtc->unpin_work; | |
14889 | ||
14890 | if (work && work->event && | |
14891 | work->event->base.file_priv == file) { | |
14892 | kfree(work->event); | |
14893 | work->event = NULL; | |
14894 | } | |
14895 | ||
5e2d7afc | 14896 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14897 | } |
14898 | } |