]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_dp.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/skl: Enable runtime PM
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
9dd4ffdf
CML		 44struct dp_link_dpll {
45 int link_bw;
46 struct dpll dpll;
47};
48
49static const struct dp_link_dpll gen4_dpll[] = {
50 { DP_LINK_BW_1_62,
51 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
52 { DP_LINK_BW_2_7,
53 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54};
55
56static const struct dp_link_dpll pch_dpll[] = {
57 { DP_LINK_BW_1_62,
58 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
59 { DP_LINK_BW_2_7,
60 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61};
62
65ce4bf5
CML		 63static const struct dp_link_dpll vlv_dpll[] = {
64 { DP_LINK_BW_1_62,
58f6e632 65 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 66 { DP_LINK_BW_2_7,
67 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68};
69
ef9348c8
CML		 70/*
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
73 */
74static const struct dp_link_dpll chv_dpll[] = {
75 /*
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
79 */
80 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
82 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
83 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
84 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
85 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86};
a8f3ef61 87/* Skylake supports following rates */
f4896f15
VS		 88static const int gen9_rates[] = { 162000, 216000, 270000,
89 324000, 432000, 540000 };
fe51bfb9
VS		 90static const int chv_rates[] = { 162000, 202500, 210000, 216000,
91 243000, 270000, 324000, 405000,
92 420000, 432000, 540000 };
f4896f15 93static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 94
cfcb0fc9
JB		 95/**
96 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
97 * @intel_dp: DP struct
98 *
99 * If a CPU or PCH DP output is attached to an eDP panel, this function
100 * will return true, and false otherwise.
101 */
102static bool is_edp(struct intel_dp *intel_dp)
103{
da63a9f2
PZ		 104 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
105
106 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 107}
108
68b4d824 109static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 110{
68b4d824
ID		 111 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
112
113 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 114}
115
df0e9248
CW		 116static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
117{
fa90ecef 118 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 119}
120
ea5b213a 121static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 122static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 123static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 124static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 125static void vlv_steal_power_sequencer(struct drm_device *dev,
126 enum pipe pipe);
a4fc5ed6 127
ed4e9c1d
VS		 128static int
129intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 130{
7183dc29 131 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 132
133 switch (max_link_bw) {
134 case DP_LINK_BW_1_62:
135 case DP_LINK_BW_2_7:
1db10e28 136 case DP_LINK_BW_5_4:
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
50fec21a 212 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
a4f1289e 230uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 231{
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240}
241
c2af70e2 242static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 331 bool pll_enabled;
961a0db0
VS		 332 uint32_t DP;
333
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe), port_name(intel_dig_port->port)))
337 return;
338
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe), port_name(intel_dig_port->port));
341
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
344 */
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
347 DP |= DP_PORT_WIDTH(1);
348 DP |= DP_LINK_TRAIN_PAT_1;
349
350 if (IS_CHERRYVIEW(dev))
351 DP |= DP_PIPE_SELECT_CHV(pipe);
352 else if (pipe == PIPE_B)
353 DP |= DP_PIPEB_SELECT;
354
d288f65f
VS		 355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
356
357 /*
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
360 */
361 if (!pll_enabled)
362 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
364
961a0db0
VS		 365 /*
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
370 */
371 I915_WRITE(intel_dp->output_reg, DP);
372 POSTING_READ(intel_dp->output_reg);
373
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
375 POSTING_READ(intel_dp->output_reg);
376
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
378 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 379
380 if (!pll_enabled)
381 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 382}
383
bf13e81b
JN		 384static enum pipe
385vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386{
387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 388 struct drm_device *dev = intel_dig_port->base.base.dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 390 struct intel_encoder *encoder;
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 392 enum pipe pipe;
bf13e81b 393
e39b999a 394 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 395
a8c3344e
VS		 396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp));
398
a4a5d2f8
VS		 399 if (intel_dp->pps_pipe != INVALID_PIPE)
400 return intel_dp->pps_pipe;
401
402 /*
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
405 */
406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 base.head) {
408 struct intel_dp *tmp;
409
410 if (encoder->type != INTEL_OUTPUT_EDP)
411 continue;
412
413 tmp = enc_to_intel_dp(&encoder->base);
414
415 if (tmp->pps_pipe != INVALID_PIPE)
416 pipes &= ~(1 << tmp->pps_pipe);
417 }
418
419 /*
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
422 */
423 if (WARN_ON(pipes == 0))
a8c3344e
VS		 424 pipe = PIPE_A;
425 else
426 pipe = ffs(pipes) - 1;
a4a5d2f8 427
a8c3344e
VS		 428 vlv_steal_power_sequencer(dev, pipe);
429 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 430
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp->pps_pipe),
433 port_name(intel_dig_port->port));
434
435 /* init power sequencer on this pipe and port */
36b5f425
VS		 436 intel_dp_init_panel_power_sequencer(dev, intel_dp);
437 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 438
961a0db0
VS		 439 /*
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
442 */
443 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 444
445 return intel_dp->pps_pipe;
446}
447
6491ab27
VS		 448typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
449 enum pipe pipe);
450
451static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
455}
456
457static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
461}
462
463static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return true;
467}
bf13e81b 468
a4a5d2f8 469static enum pipe
6491ab27
VS		 470vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 enum port port,
472 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 473{
474 enum pipe pipe;
bf13e81b 475
bf13e81b
JN		 476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
478 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 479
480 if (port_sel != PANEL_PORT_SELECT_VLV(port))
481 continue;
482
6491ab27
VS		 483 if (!pipe_check(dev_priv, pipe))
484 continue;
485
a4a5d2f8 486 return pipe;
bf13e81b
JN		 487 }
488
a4a5d2f8
VS		 489 return INVALID_PIPE;
490}
491
492static void
493vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 498 enum port port = intel_dig_port->port;
499
500 lockdep_assert_held(&dev_priv->pps_mutex);
501
502 /* try to find a pipe with this port selected */
6491ab27
VS		 503 /* first pick one where the panel is on */
504 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 vlv_pipe_has_pp_on);
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp->pps_pipe == INVALID_PIPE)
508 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
509 vlv_pipe_has_vdd_on);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp->pps_pipe == INVALID_PIPE)
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_any);
a4a5d2f8
VS		 514
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp->pps_pipe == INVALID_PIPE) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
518 port_name(port));
519 return;
bf13e81b
JN		 520 }
521
a4a5d2f8
VS		 522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port), pipe_name(intel_dp->pps_pipe));
524
36b5f425
VS		 525 intel_dp_init_panel_power_sequencer(dev, intel_dp);
526 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 527}
528
773538e8
VS		 529void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530{
531 struct drm_device *dev = dev_priv->dev;
532 struct intel_encoder *encoder;
533
534 if (WARN_ON(!IS_VALLEYVIEW(dev)))
535 return;
536
537 /*
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
545 */
546
547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
548 struct intel_dp *intel_dp;
549
550 if (encoder->type != INTEL_OUTPUT_EDP)
551 continue;
552
553 intel_dp = enc_to_intel_dp(&encoder->base);
554 intel_dp->pps_pipe = INVALID_PIPE;
555 }
bf13e81b
JN		 556}
557
558static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
562 if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_CONTROL;
564 else
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
566}
567
568static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569{
570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571
572 if (HAS_PCH_SPLIT(dev))
573 return PCH_PP_STATUS;
574 else
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
576}
577
01527b31
CT		 578/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580static int edp_notify_handler(struct notifier_block *this, unsigned long code,
581 void *unused)
582{
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
584 edp_notifier);
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 u32 pp_div;
588 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 589
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
591 return 0;
592
773538e8 593 pps_lock(intel_dp);
e39b999a 594
01527b31 595 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
597
01527b31
CT		 598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
602
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
607 }
608
773538e8 609 pps_unlock(intel_dp);
e39b999a 610
01527b31
CT		 611 return 0;
612}
613
4be73780 614static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 617 struct drm_i915_private *dev_priv = dev->dev_private;
618
e39b999a
VS		 619 lockdep_assert_held(&dev_priv->pps_mutex);
620
9a42356b
VS		 621 if (IS_VALLEYVIEW(dev) &&
622 intel_dp->pps_pipe == INVALID_PIPE)
623 return false;
624
bf13e81b 625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 626}
627
4be73780 628static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 629{
30add22d 630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 631 struct drm_i915_private *dev_priv = dev->dev_private;
632
e39b999a
VS		 633 lockdep_assert_held(&dev_priv->pps_mutex);
634
9a42356b
VS		 635 if (IS_VALLEYVIEW(dev) &&
636 intel_dp->pps_pipe == INVALID_PIPE)
637 return false;
638
773538e8 639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 640}
641
9b984dae
KP		 642static void
643intel_dp_check_edp(struct intel_dp *intel_dp)
644{
30add22d 645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 646 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 647
9b984dae
KP		 648 if (!is_edp(intel_dp))
649 return;
453c5420 650
4be73780 651 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 654 I915_READ(_pp_stat_reg(intel_dp)),
655 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 656 }
657}
658
9ee32fea
DV		 659static uint32_t
660intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
661{
662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
663 struct drm_device *dev = intel_dig_port->base.base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 665 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 666 uint32_t status;
667 bool done;
668
ef04f00d 669#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 670 if (has_aux_irq)
b18ac466 671 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 672 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 673 else
674 done = wait_for_atomic(C, 10) == 0;
675 if (!done)
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
677 has_aux_irq);
678#undef C
679
680 return status;
681}
682
ec5b01dd 683static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 684{
174edf1f
PZ		 685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 687
ec5b01dd
DL		 688 /*
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 691 */
ec5b01dd
DL		 692 return index ? 0 : intel_hrawclk(dev) / 2;
693}
694
695static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696{
697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 699 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 700
701 if (index)
702 return 0;
703
704 if (intel_dig_port->port == PORT_A) {
469d4b2a 705 return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
ec5b01dd
DL		 706 } else {
707 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
708 }
709}
710
711static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
712{
713 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
714 struct drm_device *dev = intel_dig_port->base.base.dev;
715 struct drm_i915_private *dev_priv = dev->dev_private;
716
717 if (intel_dig_port->port == PORT_A) {
718 if (index)
719 return 0;
1652d19e 720 return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
2c55c336
JN		 721 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
722 /* Workaround for non-ULT HSW */
bc86625a
CW		 723 switch (index) {
724 case 0: return 63;
725 case 1: return 72;
726 default: return 0;
727 }
ec5b01dd 728 } else {
bc86625a 729 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 730 }
b84a1cf8
RV		 731}
732
ec5b01dd
DL		 733static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
734{
735 return index ? 0 : 100;
736}
737
b6b5e383
DL		 738static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
739{
740 /*
741 * SKL doesn't need us to program the AUX clock divider (Hardware will
742 * derive the clock from CDCLK automatically). We still implement the
743 * get_aux_clock_divider vfunc to plug-in into the existing code.
744 */
745 return index ? 0 : 1;
746}
747
5ed12a19
DL		 748static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
749 bool has_aux_irq,
750 int send_bytes,
751 uint32_t aux_clock_divider)
752{
753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
754 struct drm_device *dev = intel_dig_port->base.base.dev;
755 uint32_t precharge, timeout;
756
757 if (IS_GEN6(dev))
758 precharge = 3;
759 else
760 precharge = 5;
761
762 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
763 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
764 else
765 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
766
767 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 768 DP_AUX_CH_CTL_DONE |
5ed12a19 769 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 770 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 771 timeout |
788d4433 772 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 773 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
774 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 775 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 776}
777
b9ca5fad
DL		 778static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
779 bool has_aux_irq,
780 int send_bytes,
781 uint32_t unused)
782{
783 return DP_AUX_CH_CTL_SEND_BUSY |
784 DP_AUX_CH_CTL_DONE |
785 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
786 DP_AUX_CH_CTL_TIME_OUT_ERROR |
787 DP_AUX_CH_CTL_TIME_OUT_1600us |
788 DP_AUX_CH_CTL_RECEIVE_ERROR |
789 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
790 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
791}
792
b84a1cf8
RV		 793static int
794intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 795 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 796 uint8_t *recv, int recv_size)
797{
798 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
799 struct drm_device *dev = intel_dig_port->base.base.dev;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
802 uint32_t ch_data = ch_ctl + 4;
bc86625a 803 uint32_t aux_clock_divider;
b84a1cf8
RV		 804 int i, ret, recv_bytes;
805 uint32_t status;
5ed12a19 806 int try, clock = 0;
4e6b788c 807 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 808 bool vdd;
809
773538e8 810 pps_lock(intel_dp);
e39b999a 811
72c3500a
VS		 812 /*
813 * We will be called with VDD already enabled for dpcd/edid/oui reads.
814 * In such cases we want to leave VDD enabled and it's up to upper layers
815 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
816 * ourselves.
817 */
1e0560e0 818 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 819
820 /* dp aux is extremely sensitive to irq latency, hence request the
821 * lowest possible wakeup latency and so prevent the cpu from going into
822 * deep sleep states.
823 */
824 pm_qos_update_request(&dev_priv->pm_qos, 0);
825
826 intel_dp_check_edp(intel_dp);
5eb08b69 827
c67a470b
PZ		 828 intel_aux_display_runtime_get(dev_priv);
829
11bee43e
JB		 830 /* Try to wait for any previous AUX channel activity */
831 for (try = 0; try < 3; try++) {
ef04f00d 832 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 833 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
834 break;
835 msleep(1);
836 }
837
838 if (try == 3) {
839 WARN(1, "dp_aux_ch not started status 0x%08x\n",
840 I915_READ(ch_ctl));
9ee32fea
DV		 841 ret = -EBUSY;
842 goto out;
4f7f7b7e
CW		 843 }
844
46a5ae9f
PZ		 845 /* Only 5 data registers! */
846 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
847 ret = -E2BIG;
848 goto out;
849 }
850
ec5b01dd 851 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 852 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
853 has_aux_irq,
854 send_bytes,
855 aux_clock_divider);
5ed12a19 856
bc86625a
CW		 857 /* Must try at least 3 times according to DP spec */
858 for (try = 0; try < 5; try++) {
859 /* Load the send data into the aux channel data registers */
860 for (i = 0; i < send_bytes; i += 4)
861 I915_WRITE(ch_data + i,
a4f1289e
RV		 862 intel_dp_pack_aux(send + i,
863 send_bytes - i));
bc86625a
CW		 864
865 /* Send the command and wait for it to complete */
5ed12a19 866 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 867
868 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
869
870 /* Clear done status and any errors */
871 I915_WRITE(ch_ctl,
872 status |
873 DP_AUX_CH_CTL_DONE |
874 DP_AUX_CH_CTL_TIME_OUT_ERROR |
875 DP_AUX_CH_CTL_RECEIVE_ERROR);
876
74ebf294 877 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 878 continue;
74ebf294
TP		 879
880 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
881 * 400us delay required for errors and timeouts
882 * Timeout errors from the HW already meet this
883 * requirement so skip to next iteration
884 */
885 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
886 usleep_range(400, 500);
bc86625a 887 continue;
74ebf294 888 }
bc86625a
CW		 889 if (status & DP_AUX_CH_CTL_DONE)
890 break;
891 }
4f7f7b7e 892 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 893 break;
894 }
895
a4fc5ed6 896 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 897 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 898 ret = -EBUSY;
899 goto out;
a4fc5ed6
KP		 900 }
901
902 /* Check for timeout or receive error.
903 * Timeouts occur when the sink is not connected
904 */
a5b3da54 905 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 906 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 907 ret = -EIO;
908 goto out;
a5b3da54 909 }
1ae8c0a5
KP		 910
911 /* Timeouts occur when the device isn't connected, so they're
912 * "normal" -- don't fill the kernel log with these */
a5b3da54 913 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 914 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 915 ret = -ETIMEDOUT;
916 goto out;
a4fc5ed6
KP		 917 }
918
919 /* Unload any bytes sent back from the other side */
920 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
921 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 922 if (recv_bytes > recv_size)
923 recv_bytes = recv_size;
0206e353 924
4f7f7b7e 925 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 926 intel_dp_unpack_aux(I915_READ(ch_data + i),
927 recv + i, recv_bytes - i);
a4fc5ed6 928
9ee32fea
DV		 929 ret = recv_bytes;
930out:
931 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 932 intel_aux_display_runtime_put(dev_priv);
9ee32fea 933
884f19e9
JN		 934 if (vdd)
935 edp_panel_vdd_off(intel_dp, false);
936
773538e8 937 pps_unlock(intel_dp);
e39b999a 938
9ee32fea 939 return ret;
a4fc5ed6
KP		 940}
941
a6c8aff0
JN		 942#define BARE_ADDRESS_SIZE 3
943#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 944static ssize_t
945intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 946{
9d1a1031
JN		 947 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
948 uint8_t txbuf[20], rxbuf[20];
949 size_t txsize, rxsize;
a4fc5ed6 950 int ret;
a4fc5ed6 951
d2d9cbbd
VS		 952 txbuf[0] = (msg->request << 4) |
953 ((msg->address >> 16) & 0xf);
954 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 955 txbuf[2] = msg->address & 0xff;
956 txbuf[3] = msg->size - 1;
46a5ae9f 957
9d1a1031
JN		 958 switch (msg->request & ~DP_AUX_I2C_MOT) {
959 case DP_AUX_NATIVE_WRITE:
960 case DP_AUX_I2C_WRITE:
a6c8aff0 961 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 962 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 963
9d1a1031
JN		 964 if (WARN_ON(txsize > 20))
965 return -E2BIG;
a4fc5ed6 966
9d1a1031 967 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 968
9d1a1031
JN		 969 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
970 if (ret > 0) {
971 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 972
a1ddefd8
JN		 973 if (ret > 1) {
974 /* Number of bytes written in a short write. */
975 ret = clamp_t(int, rxbuf[1], 0, msg->size);
976 } else {
977 /* Return payload size. */
978 ret = msg->size;
979 }
9d1a1031
JN		 980 }
981 break;
46a5ae9f 982
9d1a1031
JN		 983 case DP_AUX_NATIVE_READ:
984 case DP_AUX_I2C_READ:
a6c8aff0 985 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 986 rxsize = msg->size + 1;
a4fc5ed6 987
9d1a1031
JN		 988 if (WARN_ON(rxsize > 20))
989 return -E2BIG;
a4fc5ed6 990
9d1a1031
JN		 991 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
992 if (ret > 0) {
993 msg->reply = rxbuf[0] >> 4;
994 /*
995 * Assume happy day, and copy the data. The caller is
996 * expected to check msg->reply before touching it.
997 *
998 * Return payload size.
999 */
1000 ret--;
1001 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1002 }
9d1a1031
JN		 1003 break;
1004
1005 default:
1006 ret = -EINVAL;
1007 break;
a4fc5ed6 1008 }
f51a44b9 1009
9d1a1031 1010 return ret;
a4fc5ed6
KP		 1011}
1012
9d1a1031
JN		 1013static void
1014intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1015{
1016 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1017 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1018 enum port port = intel_dig_port->port;
0b99836f 1019 const char *name = NULL;
ab2c0672
DA		 1020 int ret;
1021
33ad6626
JN		 1022 switch (port) {
1023 case PORT_A:
1024 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1025 name = "DPDDC-A";
ab2c0672 1026 break;
33ad6626
JN		 1027 case PORT_B:
1028 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1029 name = "DPDDC-B";
ab2c0672 1030 break;
33ad6626
JN		 1031 case PORT_C:
1032 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1033 name = "DPDDC-C";
ab2c0672 1034 break;
33ad6626
JN		 1035 case PORT_D:
1036 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1037 name = "DPDDC-D";
33ad6626
JN		 1038 break;
1039 default:
1040 BUG();
ab2c0672
DA		 1041 }
1042
1b1aad75
DL		 1043 /*
1044 * The AUX_CTL register is usually DP_CTL + 0x10.
1045 *
1046 * On Haswell and Broadwell though:
1047 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1048 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1049 *
1050 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1051 */
1052 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1053 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1054
0b99836f 1055 intel_dp->aux.name = name;
9d1a1031
JN		 1056 intel_dp->aux.dev = dev->dev;
1057 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1058
0b99836f
JN		 1059 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1060 connector->base.kdev->kobj.name);
8316f337 1061
4f71d0cb 1062 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1063 if (ret < 0) {
4f71d0cb 1064 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1065 name, ret);
1066 return;
ab2c0672 1067 }
8a5e6aeb 1068
0b99836f
JN		 1069 ret = sysfs_create_link(&connector->base.kdev->kobj,
1070 &intel_dp->aux.ddc.dev.kobj,
1071 intel_dp->aux.ddc.dev.kobj.name);
1072 if (ret < 0) {
1073 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1074 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1075 }
a4fc5ed6
KP		 1076}
1077
80f65de3
ID		 1078static void
1079intel_dp_connector_unregister(struct intel_connector *intel_connector)
1080{
1081 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1082
0e32b39c
DA		 1083 if (!intel_connector->mst_port)
1084 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1085 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1086 intel_connector_unregister(intel_connector);
1087}
1088
5416d871 1089static void
c3346ef6 1090skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
5416d871
DL		 1091{
1092 u32 ctrl1;
1093
1094 pipe_config->ddi_pll_sel = SKL_DPLL0;
1095 pipe_config->dpll_hw_state.cfgcr1 = 0;
1096 pipe_config->dpll_hw_state.cfgcr2 = 0;
1097
1098 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
c3346ef6
SJ		 1099 switch (link_clock / 2) {
1100 case 81000:
5416d871
DL		 1101 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1102 SKL_DPLL0);
1103 break;
c3346ef6 1104 case 135000:
5416d871
DL		 1105 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1106 SKL_DPLL0);
1107 break;
c3346ef6 1108 case 270000:
5416d871
DL		 1109 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1110 SKL_DPLL0);
1111 break;
c3346ef6
SJ		 1112 case 162000:
1113 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
1114 SKL_DPLL0);
1115 break;
1116 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1117 results in CDCLK change. Need to handle the change of CDCLK by
1118 disabling pipes and re-enabling them */
1119 case 108000:
1120 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
1121 SKL_DPLL0);
1122 break;
1123 case 216000:
1124 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
1125 SKL_DPLL0);
1126 break;
1127
5416d871
DL		 1128 }
1129 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1130}
1131
0e50338c 1132static void
5cec258b 1133hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1134{
1135 switch (link_bw) {
1136 case DP_LINK_BW_1_62:
1137 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1138 break;
1139 case DP_LINK_BW_2_7:
1140 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1141 break;
1142 case DP_LINK_BW_5_4:
1143 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1144 break;
1145 }
1146}
1147
fc0f8e25 1148static int
12f6a2e2 1149intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1150{
94ca719e
VS		 1151 if (intel_dp->num_sink_rates) {
1152 *sink_rates = intel_dp->sink_rates;
1153 return intel_dp->num_sink_rates;
fc0f8e25 1154 }
12f6a2e2
VS		 1155
1156 *sink_rates = default_rates;
1157
1158 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1159}
1160
a8f3ef61 1161static int
1db10e28 1162intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
a8f3ef61 1163{
636280ba
VS		 1164 if (INTEL_INFO(dev)->gen >= 9) {
1165 *source_rates = gen9_rates;
1166 return ARRAY_SIZE(gen9_rates);
fe51bfb9
VS		 1167 } else if (IS_CHERRYVIEW(dev)) {
1168 *source_rates = chv_rates;
1169 return ARRAY_SIZE(chv_rates);
a8f3ef61 1170 }
636280ba
VS		 1171
1172 *source_rates = default_rates;
1173
1db10e28
VS		 1174 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1175 /* WaDisableHBR2:skl */
1176 return (DP_LINK_BW_2_7 >> 3) + 1;
1177 else if (INTEL_INFO(dev)->gen >= 8 ||
1178 (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1179 return (DP_LINK_BW_5_4 >> 3) + 1;
1180 else
1181 return (DP_LINK_BW_2_7 >> 3) + 1;
a8f3ef61
SJ		 1182}
1183
c6bb3538
DV		 1184static void
1185intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1186 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1187{
1188 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1189 const struct dp_link_dpll *divisor = NULL;
1190 int i, count = 0;
c6bb3538
DV		 1191
1192 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1193 divisor = gen4_dpll;
1194 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1195 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1196 divisor = pch_dpll;
1197 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1198 } else if (IS_CHERRYVIEW(dev)) {
1199 divisor = chv_dpll;
1200 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1201 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1202 divisor = vlv_dpll;
1203 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1204 }
9dd4ffdf
CML		 1205
1206 if (divisor && count) {
1207 for (i = 0; i < count; i++) {
1208 if (link_bw == divisor[i].link_bw) {
1209 pipe_config->dpll = divisor[i].dpll;
1210 pipe_config->clock_set = true;
1211 break;
1212 }
1213 }
c6bb3538
DV		 1214 }
1215}
1216
2ecae76a
VS		 1217static int intersect_rates(const int *source_rates, int source_len,
1218 const int *sink_rates, int sink_len,
94ca719e 1219 int *common_rates)
a8f3ef61
SJ		 1220{
1221 int i = 0, j = 0, k = 0;
1222
a8f3ef61
SJ		 1223 while (i < source_len && j < sink_len) {
1224 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1225 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1226 return k;
94ca719e 1227 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1228 ++k;
1229 ++i;
1230 ++j;
1231 } else if (source_rates[i] < sink_rates[j]) {
1232 ++i;
1233 } else {
1234 ++j;
1235 }
1236 }
1237 return k;
1238}
1239
94ca719e
VS		 1240static int intel_dp_common_rates(struct intel_dp *intel_dp,
1241 int *common_rates)
2ecae76a
VS		 1242{
1243 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1244 const int *source_rates, *sink_rates;
1245 int source_len, sink_len;
1246
1247 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1248 source_len = intel_dp_source_rates(dev, &source_rates);
1249
1250 return intersect_rates(source_rates, source_len,
1251 sink_rates, sink_len,
94ca719e 1252 common_rates);
2ecae76a
VS		 1253}
1254
0336400e
VS		 1255static void snprintf_int_array(char *str, size_t len,
1256 const int *array, int nelem)
1257{
1258 int i;
1259
1260 str[0] = '\0';
1261
1262 for (i = 0; i < nelem; i++) {
1263 int r = snprintf(str, len, "%d,", array[i]);
1264 if (r >= len)
1265 return;
1266 str += r;
1267 len -= r;
1268 }
1269}
1270
1271static void intel_dp_print_rates(struct intel_dp *intel_dp)
1272{
1273 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1274 const int *source_rates, *sink_rates;
94ca719e
VS		 1275 int source_len, sink_len, common_len;
1276 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1277 char str[128]; /* FIXME: too big for stack? */
1278
1279 if ((drm_debug & DRM_UT_KMS) == 0)
1280 return;
1281
1282 source_len = intel_dp_source_rates(dev, &source_rates);
1283 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1284 DRM_DEBUG_KMS("source rates: %s\n", str);
1285
1286 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1287 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1288 DRM_DEBUG_KMS("sink rates: %s\n", str);
1289
94ca719e
VS		 1290 common_len = intel_dp_common_rates(intel_dp, common_rates);
1291 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1292 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1293}
1294
f4896f15 1295static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1296{
1297 int i = 0;
1298
1299 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1300 if (find == rates[i])
1301 break;
1302
1303 return i;
1304}
1305
50fec21a
VS		 1306int
1307intel_dp_max_link_rate(struct intel_dp *intel_dp)
1308{
1309 int rates[DP_MAX_SUPPORTED_RATES] = {};
1310 int len;
1311
94ca719e 1312 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1313 if (WARN_ON(len <= 0))
1314 return 162000;
1315
1316 return rates[rate_to_index(0, rates) - 1];
1317}
1318
ed4e9c1d
VS		 1319int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1320{
94ca719e 1321 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1322}
1323
00c09d70 1324bool
5bfe2ac0 1325intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1326 struct intel_crtc_state *pipe_config)
a4fc5ed6 1327{
5bfe2ac0 1328 struct drm_device *dev = encoder->base.dev;
36008365 1329 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1330 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1332 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1333 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1334 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1335 int lane_count, clock;
56071a20 1336 int min_lane_count = 1;
eeb6324d 1337 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1338 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1339 int min_clock = 0;
a8f3ef61 1340 int max_clock;
083f9560 1341 int bpp, mode_rate;
ff9a6750 1342 int link_avail, link_clock;
94ca719e
VS		 1343 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1344 int common_len;
a8f3ef61 1345
94ca719e 1346 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1347
1348 /* No common link rates between source and sink */
94ca719e 1349 WARN_ON(common_len <= 0);
a8f3ef61 1350
94ca719e 1351 max_clock = common_len - 1;
a4fc5ed6 1352
bc7d38a4 1353 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1354 pipe_config->has_pch_encoder = true;
1355
03afc4a2 1356 pipe_config->has_dp_encoder = true;
f769cd24 1357 pipe_config->has_drrs = false;
9ed109a7 1358 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1359
dd06f90e
JN		 1360 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1361 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1362 adjusted_mode);
a1b2278e
CK		 1363
1364 if (INTEL_INFO(dev)->gen >= 9) {
1365 int ret;
1366 ret = skl_update_scaler_users(intel_crtc, pipe_config, NULL, NULL, 0);
1367 if (ret)
1368 return ret;
1369 }
1370
2dd24552
JB		 1371 if (!HAS_PCH_SPLIT(dev))
1372 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1373 intel_connector->panel.fitting_mode);
1374 else
b074cec8
JB		 1375 intel_pch_panel_fitting(intel_crtc, pipe_config,
1376 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1377 }
1378
cb1793ce 1379 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1380 return false;
1381
083f9560 1382 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1383 "max bw %d pixel clock %iKHz\n",
94ca719e 1384 max_lane_count, common_rates[max_clock],
241bfc38 1385 adjusted_mode->crtc_clock);
083f9560 1386
36008365
DV		 1387 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1388 * bpc in between. */
3e7ca985 1389 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1390 if (is_edp(intel_dp)) {
1391 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1392 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1393 dev_priv->vbt.edp_bpp);
1394 bpp = dev_priv->vbt.edp_bpp;
1395 }
1396
344c5bbc
JN		 1397 /*
1398 * Use the maximum clock and number of lanes the eDP panel
1399 * advertizes being capable of. The panels are generally
1400 * designed to support only a single clock and lane
1401 * configuration, and typically these values correspond to the
1402 * native resolution of the panel.
1403 */
1404 min_lane_count = max_lane_count;
1405 min_clock = max_clock;
7984211e 1406 }
657445fe 1407
36008365 1408 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1409 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1410 bpp);
36008365 1411
c6930992 1412 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1413 for (lane_count = min_lane_count;
1414 lane_count <= max_lane_count;
1415 lane_count <<= 1) {
1416
94ca719e 1417 link_clock = common_rates[clock];
36008365
DV		 1418 link_avail = intel_dp_max_data_rate(link_clock,
1419 lane_count);
1420
1421 if (mode_rate <= link_avail) {
1422 goto found;
1423 }
1424 }
1425 }
1426 }
c4867936 1427
36008365 1428 return false;
3685a8f3 1429
36008365 1430found:
55bc60db
VS		 1431 if (intel_dp->color_range_auto) {
1432 /*
1433 * See:
1434 * CEA-861-E - 5.1 Default Encoding Parameters
1435 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1436 */
18316c8c 1437 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1438 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1439 else
1440 intel_dp->color_range = 0;
1441 }
1442
3685a8f3 1443 if (intel_dp->color_range)
50f3b016 1444 pipe_config->limited_color_range = true;
a4fc5ed6 1445
36008365 1446 intel_dp->lane_count = lane_count;
a8f3ef61 1447
94ca719e 1448 if (intel_dp->num_sink_rates) {
bc27b7d3 1449 intel_dp->link_bw = 0;
a8f3ef61 1450 intel_dp->rate_select =
94ca719e 1451 intel_dp_rate_select(intel_dp, common_rates[clock]);
bc27b7d3
VS		 1452 } else {
1453 intel_dp->link_bw =
94ca719e 1454 drm_dp_link_rate_to_bw_code(common_rates[clock]);
bc27b7d3 1455 intel_dp->rate_select = 0;
a8f3ef61
SJ		 1456 }
1457
657445fe 1458 pipe_config->pipe_bpp = bpp;
94ca719e 1459 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1460
36008365
DV		 1461 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1462 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1463 pipe_config->port_clock, bpp);
36008365
DV		 1464 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1465 mode_rate, link_avail);
a4fc5ed6 1466
03afc4a2 1467 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1468 adjusted_mode->crtc_clock,
1469 pipe_config->port_clock,
03afc4a2 1470 &pipe_config->dp_m_n);
9d1a455b 1471
439d7ac0 1472 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1473 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1474 pipe_config->has_drrs = true;
439d7ac0
PB		 1475 intel_link_compute_m_n(bpp, lane_count,
1476 intel_connector->panel.downclock_mode->clock,
1477 pipe_config->port_clock,
1478 &pipe_config->dp_m2_n2);
1479 }
1480
5416d871 1481 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
94ca719e 1482 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
977bb38d
S		 1483 else if (IS_BROXTON(dev))
1484 /* handled in ddi */;
5416d871 1485 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1486 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1487 else
1488 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1489
03afc4a2 1490 return true;
a4fc5ed6
KP		 1491}
1492
7c62a164 1493static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1494{
7c62a164
DV		 1495 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1496 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1497 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 u32 dpa_ctl;
1500
6e3c9717
ACO		 1501 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1502 crtc->config->port_clock);
ea9b6006
DV		 1503 dpa_ctl = I915_READ(DP_A);
1504 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1505
6e3c9717 1506 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1507 /* For a long time we've carried around a ILK-DevA w/a for the
1508 * 160MHz clock. If we're really unlucky, it's still required.
1509 */
1510 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1511 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1512 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1513 } else {
1514 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1515 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1516 }
1ce17038 1517
ea9b6006
DV		 1518 I915_WRITE(DP_A, dpa_ctl);
1519
1520 POSTING_READ(DP_A);
1521 udelay(500);
1522}
1523
8ac33ed3 1524static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1525{
b934223d 1526 struct drm_device *dev = encoder->base.dev;
417e822d 1527 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1528 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1529 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1530 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1531 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1532
417e822d 1533 /*
1a2eb460 1534 * There are four kinds of DP registers:
417e822d
KP		 1535 *
1536 * IBX PCH
1a2eb460
KP		 1537 * SNB CPU
1538 * IVB CPU
417e822d
KP		 1539 * CPT PCH
1540 *
1541 * IBX PCH and CPU are the same for almost everything,
1542 * except that the CPU DP PLL is configured in this
1543 * register
1544 *
1545 * CPT PCH is quite different, having many bits moved
1546 * to the TRANS_DP_CTL register instead. That
1547 * configuration happens (oddly) in ironlake_pch_enable
1548 */
9c9e7927 1549
417e822d
KP		 1550 /* Preserve the BIOS-computed detected bit. This is
1551 * supposed to be read-only.
1552 */
1553 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1554
417e822d 1555 /* Handle DP bits in common between all three register formats */
417e822d 1556 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1557 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1558
6e3c9717 1559 if (crtc->config->has_audio)
ea5b213a 1560 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1561
417e822d 1562 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1563
bc7d38a4 1564 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1565 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1566 intel_dp->DP |= DP_SYNC_HS_HIGH;
1567 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1568 intel_dp->DP |= DP_SYNC_VS_HIGH;
1569 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1570
6aba5b6c 1571 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1572 intel_dp->DP |= DP_ENHANCED_FRAMING;
1573
7c62a164 1574 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1575 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1576 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1577 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1578
1579 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1580 intel_dp->DP |= DP_SYNC_HS_HIGH;
1581 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1582 intel_dp->DP |= DP_SYNC_VS_HIGH;
1583 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1584
6aba5b6c 1585 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1586 intel_dp->DP |= DP_ENHANCED_FRAMING;
1587
44f37d1f
CML		 1588 if (!IS_CHERRYVIEW(dev)) {
1589 if (crtc->pipe == 1)
1590 intel_dp->DP |= DP_PIPEB_SELECT;
1591 } else {
1592 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1593 }
417e822d
KP		 1594 } else {
1595 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1596 }
a4fc5ed6
KP		 1597}
1598
ffd6749d
PZ		 1599#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1600#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1601
1a5ef5b7
PZ		 1602#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1603#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1604
ffd6749d
PZ		 1605#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1606#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1607
4be73780 1608static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1609 u32 mask,
1610 u32 value)
bd943159 1611{
30add22d 1612 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1613 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1614 u32 pp_stat_reg, pp_ctrl_reg;
1615
e39b999a
VS		 1616 lockdep_assert_held(&dev_priv->pps_mutex);
1617
bf13e81b
JN		 1618 pp_stat_reg = _pp_stat_reg(intel_dp);
1619 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1620
99ea7127 1621 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1622 mask, value,
1623 I915_READ(pp_stat_reg),
1624 I915_READ(pp_ctrl_reg));
32ce697c 1625
453c5420 1626 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1627 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1628 I915_READ(pp_stat_reg),
1629 I915_READ(pp_ctrl_reg));
32ce697c 1630 }
54c136d4
CW		 1631
1632 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1633}
32ce697c 1634
4be73780 1635static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1636{
1637 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1638 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1639}
1640
4be73780 1641static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1642{
1643 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1644 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1645}
1646
4be73780 1647static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1648{
1649 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1650
1651 /* When we disable the VDD override bit last we have to do the manual
1652 * wait. */
1653 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1654 intel_dp->panel_power_cycle_delay);
1655
4be73780 1656 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1657}
1658
4be73780 1659static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1660{
1661 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1662 intel_dp->backlight_on_delay);
1663}
1664
4be73780 1665static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1666{
1667 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1668 intel_dp->backlight_off_delay);
1669}
99ea7127 1670
832dd3c1
KP		 1671/* Read the current pp_control value, unlocking the register if it
1672 * is locked
1673 */
1674
453c5420 1675static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1676{
453c5420
JB		 1677 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 u32 control;
832dd3c1 1680
e39b999a
VS		 1681 lockdep_assert_held(&dev_priv->pps_mutex);
1682
bf13e81b 1683 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1684 control &= ~PANEL_UNLOCK_MASK;
1685 control |= PANEL_UNLOCK_REGS;
1686 return control;
bd943159
KP		 1687}
1688
951468f3
VS		 1689/*
1690 * Must be paired with edp_panel_vdd_off().
1691 * Must hold pps_mutex around the whole on/off sequence.
1692 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1693 */
1e0560e0 1694static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1695{
30add22d 1696 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1698 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1699 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1700 enum intel_display_power_domain power_domain;
5d613501 1701 u32 pp;
453c5420 1702 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1703 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1704
e39b999a
VS		 1705 lockdep_assert_held(&dev_priv->pps_mutex);
1706
97af61f5 1707 if (!is_edp(intel_dp))
adddaaf4 1708 return false;
bd943159 1709
2c623c11 1710 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1711 intel_dp->want_panel_vdd = true;
99ea7127 1712
4be73780 1713 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1714 return need_to_disable;
b0665d57 1715
4e6e1a54
ID		 1716 power_domain = intel_display_port_power_domain(intel_encoder);
1717 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1718
3936fcf4
VS		 1719 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1720 port_name(intel_dig_port->port));
bd943159 1721
4be73780
DV		 1722 if (!edp_have_panel_power(intel_dp))
1723 wait_panel_power_cycle(intel_dp);
99ea7127 1724
453c5420 1725 pp = ironlake_get_pp_control(intel_dp);
5d613501 1726 pp |= EDP_FORCE_VDD;
ebf33b18 1727
bf13e81b
JN		 1728 pp_stat_reg = _pp_stat_reg(intel_dp);
1729 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1730
1731 I915_WRITE(pp_ctrl_reg, pp);
1732 POSTING_READ(pp_ctrl_reg);
1733 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1734 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1735 /*
1736 * If the panel wasn't on, delay before accessing aux channel
1737 */
4be73780 1738 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1739 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1740 port_name(intel_dig_port->port));
f01eca2e 1741 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1742 }
adddaaf4
JN		 1743
1744 return need_to_disable;
1745}
1746
951468f3
VS		 1747/*
1748 * Must be paired with intel_edp_panel_vdd_off() or
1749 * intel_edp_panel_off().
1750 * Nested calls to these functions are not allowed since
1751 * we drop the lock. Caller must use some higher level
1752 * locking to prevent nested calls from other threads.
1753 */
b80d6c78 1754void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1755{
c695b6b6 1756 bool vdd;
adddaaf4 1757
c695b6b6
VS		 1758 if (!is_edp(intel_dp))
1759 return;
1760
773538e8 1761 pps_lock(intel_dp);
c695b6b6 1762 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1763 pps_unlock(intel_dp);
c695b6b6 1764
e2c719b7 1765 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1766 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1767}
1768
4be73780 1769static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1770{
30add22d 1771 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1772 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1773 struct intel_digital_port *intel_dig_port =
1774 dp_to_dig_port(intel_dp);
1775 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1776 enum intel_display_power_domain power_domain;
5d613501 1777 u32 pp;
453c5420 1778 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1779
e39b999a 1780 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1781
15e899a0 1782 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1783
15e899a0 1784 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1785 return;
b0665d57 1786
3936fcf4
VS		 1787 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1788 port_name(intel_dig_port->port));
bd943159 1789
be2c9196
VS		 1790 pp = ironlake_get_pp_control(intel_dp);
1791 pp &= ~EDP_FORCE_VDD;
453c5420 1792
be2c9196
VS		 1793 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1794 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1795
be2c9196
VS		 1796 I915_WRITE(pp_ctrl_reg, pp);
1797 POSTING_READ(pp_ctrl_reg);
90791a5c 1798
be2c9196
VS		 1799 /* Make sure sequencer is idle before allowing subsequent activity */
1800 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1801 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1802
be2c9196
VS		 1803 if ((pp & POWER_TARGET_ON) == 0)
1804 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1805
be2c9196
VS		 1806 power_domain = intel_display_port_power_domain(intel_encoder);
1807 intel_display_power_put(dev_priv, power_domain);
bd943159 1808}
5d613501 1809
4be73780 1810static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1811{
1812 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1813 struct intel_dp, panel_vdd_work);
bd943159 1814
773538e8 1815 pps_lock(intel_dp);
15e899a0
VS		 1816 if (!intel_dp->want_panel_vdd)
1817 edp_panel_vdd_off_sync(intel_dp);
773538e8 1818 pps_unlock(intel_dp);
bd943159
KP		 1819}
1820
aba86890
ID		 1821static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1822{
1823 unsigned long delay;
1824
1825 /*
1826 * Queue the timer to fire a long time from now (relative to the power
1827 * down delay) to keep the panel power up across a sequence of
1828 * operations.
1829 */
1830 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1831 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1832}
1833
951468f3
VS		 1834/*
1835 * Must be paired with edp_panel_vdd_on().
1836 * Must hold pps_mutex around the whole on/off sequence.
1837 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1838 */
4be73780 1839static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1840{
e39b999a
VS		 1841 struct drm_i915_private *dev_priv =
1842 intel_dp_to_dev(intel_dp)->dev_private;
1843
1844 lockdep_assert_held(&dev_priv->pps_mutex);
1845
97af61f5
KP		 1846 if (!is_edp(intel_dp))
1847 return;
5d613501 1848
e2c719b7 1849 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1850 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1851
bd943159
KP		 1852 intel_dp->want_panel_vdd = false;
1853
aba86890 1854 if (sync)
4be73780 1855 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1856 else
1857 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1858}
1859
9f0fb5be 1860static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1861{
30add22d 1862 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1863 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1864 u32 pp;
453c5420 1865 u32 pp_ctrl_reg;
9934c132 1866
9f0fb5be
VS		 1867 lockdep_assert_held(&dev_priv->pps_mutex);
1868
97af61f5 1869 if (!is_edp(intel_dp))
bd943159 1870 return;
99ea7127 1871
3936fcf4
VS		 1872 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1873 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1874
e7a89ace
VS		 1875 if (WARN(edp_have_panel_power(intel_dp),
1876 "eDP port %c panel power already on\n",
1877 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1878 return;
9934c132 1879
4be73780 1880 wait_panel_power_cycle(intel_dp);
37c6c9b0 1881
bf13e81b 1882 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1883 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1884 if (IS_GEN5(dev)) {
1885 /* ILK workaround: disable reset around power sequence */
1886 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1887 I915_WRITE(pp_ctrl_reg, pp);
1888 POSTING_READ(pp_ctrl_reg);
05ce1a49 1889 }
37c6c9b0 1890
1c0ae80a 1891 pp |= POWER_TARGET_ON;
99ea7127
KP		 1892 if (!IS_GEN5(dev))
1893 pp |= PANEL_POWER_RESET;
1894
453c5420
JB		 1895 I915_WRITE(pp_ctrl_reg, pp);
1896 POSTING_READ(pp_ctrl_reg);
9934c132 1897
4be73780 1898 wait_panel_on(intel_dp);
dce56b3c 1899 intel_dp->last_power_on = jiffies;
9934c132 1900
05ce1a49
KP		 1901 if (IS_GEN5(dev)) {
1902 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1903 I915_WRITE(pp_ctrl_reg, pp);
1904 POSTING_READ(pp_ctrl_reg);
05ce1a49 1905 }
9f0fb5be 1906}
e39b999a 1907
9f0fb5be
VS		 1908void intel_edp_panel_on(struct intel_dp *intel_dp)
1909{
1910 if (!is_edp(intel_dp))
1911 return;
1912
1913 pps_lock(intel_dp);
1914 edp_panel_on(intel_dp);
773538e8 1915 pps_unlock(intel_dp);
9934c132
JB		 1916}
1917
9f0fb5be
VS		 1918
1919static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1920{
4e6e1a54
ID		 1921 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1922 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1923 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1924 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1925 enum intel_display_power_domain power_domain;
99ea7127 1926 u32 pp;
453c5420 1927 u32 pp_ctrl_reg;
9934c132 1928
9f0fb5be
VS		 1929 lockdep_assert_held(&dev_priv->pps_mutex);
1930
97af61f5
KP		 1931 if (!is_edp(intel_dp))
1932 return;
37c6c9b0 1933
3936fcf4
VS		 1934 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1935 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1936
3936fcf4
VS		 1937 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1938 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1939
453c5420 1940 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1941 /* We need to switch off panel power _and_ force vdd, for otherwise some
1942 * panels get very unhappy and cease to work. */
b3064154
PJ		 1943 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1944 EDP_BLC_ENABLE);
453c5420 1945
bf13e81b 1946 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1947
849e39f5
PZ		 1948 intel_dp->want_panel_vdd = false;
1949
453c5420
JB		 1950 I915_WRITE(pp_ctrl_reg, pp);
1951 POSTING_READ(pp_ctrl_reg);
9934c132 1952
dce56b3c 1953 intel_dp->last_power_cycle = jiffies;
4be73780 1954 wait_panel_off(intel_dp);
849e39f5
PZ		 1955
1956 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1957 power_domain = intel_display_port_power_domain(intel_encoder);
1958 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1959}
e39b999a 1960
9f0fb5be
VS		 1961void intel_edp_panel_off(struct intel_dp *intel_dp)
1962{
1963 if (!is_edp(intel_dp))
1964 return;
e39b999a 1965
9f0fb5be
VS		 1966 pps_lock(intel_dp);
1967 edp_panel_off(intel_dp);
773538e8 1968 pps_unlock(intel_dp);
9934c132
JB		 1969}
1970
1250d107
JN		 1971/* Enable backlight in the panel power control. */
1972static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1973{
da63a9f2
PZ		 1974 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1975 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 u32 pp;
453c5420 1978 u32 pp_ctrl_reg;
32f9d658 1979
01cb9ea6
JB		 1980 /*
1981 * If we enable the backlight right away following a panel power
1982 * on, we may see slight flicker as the panel syncs with the eDP
1983 * link. So delay a bit to make sure the image is solid before
1984 * allowing it to appear.
1985 */
4be73780 1986 wait_backlight_on(intel_dp);
e39b999a 1987
773538e8 1988 pps_lock(intel_dp);
e39b999a 1989
453c5420 1990 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1991 pp |= EDP_BLC_ENABLE;
453c5420 1992
bf13e81b 1993 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1994
1995 I915_WRITE(pp_ctrl_reg, pp);
1996 POSTING_READ(pp_ctrl_reg);
e39b999a 1997
773538e8 1998 pps_unlock(intel_dp);
32f9d658
ZW		 1999}
2000
1250d107
JN		 2001/* Enable backlight PWM and backlight PP control. */
2002void intel_edp_backlight_on(struct intel_dp *intel_dp)
2003{
2004 if (!is_edp(intel_dp))
2005 return;
2006
2007 DRM_DEBUG_KMS("\n");
2008
2009 intel_panel_enable_backlight(intel_dp->attached_connector);
2010 _intel_edp_backlight_on(intel_dp);
2011}
2012
2013/* Disable backlight in the panel power control. */
2014static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2015{
30add22d 2016 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2017 struct drm_i915_private *dev_priv = dev->dev_private;
2018 u32 pp;
453c5420 2019 u32 pp_ctrl_reg;
32f9d658 2020
f01eca2e
KP		 2021 if (!is_edp(intel_dp))
2022 return;
2023
773538e8 2024 pps_lock(intel_dp);
e39b999a 2025
453c5420 2026 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2027 pp &= ~EDP_BLC_ENABLE;
453c5420 2028
bf13e81b 2029 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2030
2031 I915_WRITE(pp_ctrl_reg, pp);
2032 POSTING_READ(pp_ctrl_reg);
f7d2323c 2033
773538e8 2034 pps_unlock(intel_dp);
e39b999a
VS		 2035
2036 intel_dp->last_backlight_off = jiffies;
f7d2323c 2037 edp_wait_backlight_off(intel_dp);
1250d107 2038}
f7d2323c 2039
1250d107
JN		 2040/* Disable backlight PP control and backlight PWM. */
2041void intel_edp_backlight_off(struct intel_dp *intel_dp)
2042{
2043 if (!is_edp(intel_dp))
2044 return;
2045
2046 DRM_DEBUG_KMS("\n");
f7d2323c 2047
1250d107 2048 _intel_edp_backlight_off(intel_dp);
f7d2323c 2049 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2050}
a4fc5ed6 2051
73580fb7
JN		 2052/*
2053 * Hook for controlling the panel power control backlight through the bl_power
2054 * sysfs attribute. Take care to handle multiple calls.
2055 */
2056static void intel_edp_backlight_power(struct intel_connector *connector,
2057 bool enable)
2058{
2059 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2060 bool is_enabled;
2061
773538e8 2062 pps_lock(intel_dp);
e39b999a 2063 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2064 pps_unlock(intel_dp);
73580fb7
JN		 2065
2066 if (is_enabled == enable)
2067 return;
2068
23ba9373
JN		 2069 DRM_DEBUG_KMS("panel power control backlight %s\n",
2070 enable ? "enable" : "disable");
73580fb7
JN		 2071
2072 if (enable)
2073 _intel_edp_backlight_on(intel_dp);
2074 else
2075 _intel_edp_backlight_off(intel_dp);
2076}
2077
2bd2ad64 2078static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2079{
da63a9f2
PZ		 2080 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2081 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2082 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 u32 dpa_ctl;
2085
2bd2ad64
DV		 2086 assert_pipe_disabled(dev_priv,
2087 to_intel_crtc(crtc)->pipe);
2088
d240f20f
JB		 2089 DRM_DEBUG_KMS("\n");
2090 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2091 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2092 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2093
2094 /* We don't adjust intel_dp->DP while tearing down the link, to
2095 * facilitate link retraining (e.g. after hotplug). Hence clear all
2096 * enable bits here to ensure that we don't enable too much. */
2097 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2098 intel_dp->DP |= DP_PLL_ENABLE;
2099 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2100 POSTING_READ(DP_A);
2101 udelay(200);
d240f20f
JB		 2102}
2103
2bd2ad64 2104static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2105{
da63a9f2
PZ		 2106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2107 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2108 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 u32 dpa_ctl;
2111
2bd2ad64
DV		 2112 assert_pipe_disabled(dev_priv,
2113 to_intel_crtc(crtc)->pipe);
2114
d240f20f 2115 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2116 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2117 "dp pll off, should be on\n");
2118 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2119
2120 /* We can't rely on the value tracked for the DP register in
2121 * intel_dp->DP because link_down must not change that (otherwise link
2122 * re-training will fail. */
298b0b39 2123 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2124 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2125 POSTING_READ(DP_A);
d240f20f
JB		 2126 udelay(200);
2127}
2128
c7ad3810 2129/* If the sink supports it, try to set the power state appropriately */
c19b0669 2130void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2131{
2132 int ret, i;
2133
2134 /* Should have a valid DPCD by this point */
2135 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2136 return;
2137
2138 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2139 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2140 DP_SET_POWER_D3);
c7ad3810
JB		 2141 } else {
2142 /*
2143 * When turning on, we need to retry for 1ms to give the sink
2144 * time to wake up.
2145 */
2146 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2147 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2148 DP_SET_POWER_D0);
c7ad3810
JB		 2149 if (ret == 1)
2150 break;
2151 msleep(1);
2152 }
2153 }
f9cac721
JN		 2154
2155 if (ret != 1)
2156 DRM_DEBUG_KMS("failed to %s sink power state\n",
2157 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2158}
2159
19d8fe15
DV		 2160static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2161 enum pipe *pipe)
d240f20f 2162{
19d8fe15 2163 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2164 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2165 struct drm_device *dev = encoder->base.dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2167 enum intel_display_power_domain power_domain;
2168 u32 tmp;
2169
2170 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2171 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2172 return false;
2173
2174 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2175
2176 if (!(tmp & DP_PORT_EN))
2177 return false;
2178
bc7d38a4 2179 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 2180 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 2181 } else if (IS_CHERRYVIEW(dev)) {
2182 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 2183 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 2184 *pipe = PORT_TO_PIPE(tmp);
2185 } else {
2186 u32 trans_sel;
2187 u32 trans_dp;
2188 int i;
2189
2190 switch (intel_dp->output_reg) {
2191 case PCH_DP_B:
2192 trans_sel = TRANS_DP_PORT_SEL_B;
2193 break;
2194 case PCH_DP_C:
2195 trans_sel = TRANS_DP_PORT_SEL_C;
2196 break;
2197 case PCH_DP_D:
2198 trans_sel = TRANS_DP_PORT_SEL_D;
2199 break;
2200 default:
2201 return true;
2202 }
2203
055e393f 2204 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2205 trans_dp = I915_READ(TRANS_DP_CTL(i));
2206 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2207 *pipe = i;
2208 return true;
2209 }
2210 }
19d8fe15 2211
4a0833ec
DV		 2212 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2213 intel_dp->output_reg);
2214 }
d240f20f 2215
19d8fe15
DV		 2216 return true;
2217}
d240f20f 2218
045ac3b5 2219static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2220 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2221{
2222 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2223 u32 tmp, flags = 0;
63000ef6
XZ		 2224 struct drm_device *dev = encoder->base.dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 enum port port = dp_to_dig_port(intel_dp)->port;
2227 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2228 int dotclock;
045ac3b5 2229
9ed109a7
DV		 2230 tmp = I915_READ(intel_dp->output_reg);
2231 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2232 pipe_config->has_audio = true;
2233
63000ef6 2234 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2235 if (tmp & DP_SYNC_HS_HIGH)
2236 flags |= DRM_MODE_FLAG_PHSYNC;
2237 else
2238 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2239
63000ef6
XZ		 2240 if (tmp & DP_SYNC_VS_HIGH)
2241 flags |= DRM_MODE_FLAG_PVSYNC;
2242 else
2243 flags |= DRM_MODE_FLAG_NVSYNC;
2244 } else {
2245 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2246 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2247 flags |= DRM_MODE_FLAG_PHSYNC;
2248 else
2249 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2250
63000ef6
XZ		 2251 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2252 flags |= DRM_MODE_FLAG_PVSYNC;
2253 else
2254 flags |= DRM_MODE_FLAG_NVSYNC;
2255 }
045ac3b5 2256
2d112de7 2257 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2258
8c875fca
VS		 2259 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2260 tmp & DP_COLOR_RANGE_16_235)
2261 pipe_config->limited_color_range = true;
2262
eb14cb74
VS		 2263 pipe_config->has_dp_encoder = true;
2264
2265 intel_dp_get_m_n(crtc, pipe_config);
2266
18442d08 2267 if (port == PORT_A) {
f1f644dc
JB		 2268 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2269 pipe_config->port_clock = 162000;
2270 else
2271 pipe_config->port_clock = 270000;
2272 }
18442d08
VS		 2273
2274 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2275 &pipe_config->dp_m_n);
2276
2277 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2278 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2279
2d112de7 2280 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2281
c6cd2ee2
JN		 2282 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2283 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2284 /*
2285 * This is a big fat ugly hack.
2286 *
2287 * Some machines in UEFI boot mode provide us a VBT that has 18
2288 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2289 * unknown we fail to light up. Yet the same BIOS boots up with
2290 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2291 * max, not what it tells us to use.
2292 *
2293 * Note: This will still be broken if the eDP panel is not lit
2294 * up by the BIOS, and thus we can't get the mode at module
2295 * load.
2296 */
2297 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2298 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2299 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2300 }
045ac3b5
JB		 2301}
2302
e8cb4558 2303static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2304{
e8cb4558 2305 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2306 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2307 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2308
6e3c9717 2309 if (crtc->config->has_audio)
495a5bb8 2310 intel_audio_codec_disable(encoder);
6cb49835 2311
b32c6f48
RV		 2312 if (HAS_PSR(dev) && !HAS_DDI(dev))
2313 intel_psr_disable(intel_dp);
2314
6cb49835
DV		 2315 /* Make sure the panel is off before trying to change the mode. But also
2316 * ensure that we have vdd while we switch off the panel. */
24f3e092 2317 intel_edp_panel_vdd_on(intel_dp);
4be73780 2318 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2319 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2320 intel_edp_panel_off(intel_dp);
3739850b 2321
08aff3fe
VS		 2322 /* disable the port before the pipe on g4x */
2323 if (INTEL_INFO(dev)->gen < 5)
3739850b 2324 intel_dp_link_down(intel_dp);
d240f20f
JB		 2325}
2326
08aff3fe 2327static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2328{
2bd2ad64 2329 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2330 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2331
49277c31 2332 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2333 if (port == PORT_A)
2334 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2335}
2336
2337static void vlv_post_disable_dp(struct intel_encoder *encoder)
2338{
2339 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2340
2341 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2342}
2343
580d3811
VS		 2344static void chv_post_disable_dp(struct intel_encoder *encoder)
2345{
2346 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2347 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2348 struct drm_device *dev = encoder->base.dev;
2349 struct drm_i915_private *dev_priv = dev->dev_private;
2350 struct intel_crtc *intel_crtc =
2351 to_intel_crtc(encoder->base.crtc);
2352 enum dpio_channel ch = vlv_dport_to_channel(dport);
2353 enum pipe pipe = intel_crtc->pipe;
2354 u32 val;
2355
2356 intel_dp_link_down(intel_dp);
2357
2358 mutex_lock(&dev_priv->dpio_lock);
2359
2360 /* Propagate soft reset to data lane reset */
97fd4d5c 2361 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2362 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2363 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2364
97fd4d5c
VS		 2365 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2366 val |= CHV_PCS_REQ_SOFTRESET_EN;
2367 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2368
2369 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2370 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2371 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2372
2373 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2374 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2375 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2376
2377 mutex_unlock(&dev_priv->dpio_lock);
2378}
2379
7b13b58a
VS		 2380static void
2381_intel_dp_set_link_train(struct intel_dp *intel_dp,
2382 uint32_t *DP,
2383 uint8_t dp_train_pat)
2384{
2385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2386 struct drm_device *dev = intel_dig_port->base.base.dev;
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 enum port port = intel_dig_port->port;
2389
2390 if (HAS_DDI(dev)) {
2391 uint32_t temp = I915_READ(DP_TP_CTL(port));
2392
2393 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2394 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2395 else
2396 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2397
2398 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2399 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2400 case DP_TRAINING_PATTERN_DISABLE:
2401 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2402
2403 break;
2404 case DP_TRAINING_PATTERN_1:
2405 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2406 break;
2407 case DP_TRAINING_PATTERN_2:
2408 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2409 break;
2410 case DP_TRAINING_PATTERN_3:
2411 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2412 break;
2413 }
2414 I915_WRITE(DP_TP_CTL(port), temp);
2415
2416 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2417 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2418
2419 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2420 case DP_TRAINING_PATTERN_DISABLE:
2421 *DP |= DP_LINK_TRAIN_OFF_CPT;
2422 break;
2423 case DP_TRAINING_PATTERN_1:
2424 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2425 break;
2426 case DP_TRAINING_PATTERN_2:
2427 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2428 break;
2429 case DP_TRAINING_PATTERN_3:
2430 DRM_ERROR("DP training pattern 3 not supported\n");
2431 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2432 break;
2433 }
2434
2435 } else {
2436 if (IS_CHERRYVIEW(dev))
2437 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2438 else
2439 *DP &= ~DP_LINK_TRAIN_MASK;
2440
2441 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2442 case DP_TRAINING_PATTERN_DISABLE:
2443 *DP |= DP_LINK_TRAIN_OFF;
2444 break;
2445 case DP_TRAINING_PATTERN_1:
2446 *DP |= DP_LINK_TRAIN_PAT_1;
2447 break;
2448 case DP_TRAINING_PATTERN_2:
2449 *DP |= DP_LINK_TRAIN_PAT_2;
2450 break;
2451 case DP_TRAINING_PATTERN_3:
2452 if (IS_CHERRYVIEW(dev)) {
2453 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2454 } else {
2455 DRM_ERROR("DP training pattern 3 not supported\n");
2456 *DP |= DP_LINK_TRAIN_PAT_2;
2457 }
2458 break;
2459 }
2460 }
2461}
2462
2463static void intel_dp_enable_port(struct intel_dp *intel_dp)
2464{
2465 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467
7b13b58a
VS		 2468 /* enable with pattern 1 (as per spec) */
2469 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2470 DP_TRAINING_PATTERN_1);
2471
2472 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2473 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2474
2475 /*
2476 * Magic for VLV/CHV. We _must_ first set up the register
2477 * without actually enabling the port, and then do another
2478 * write to enable the port. Otherwise link training will
2479 * fail when the power sequencer is freshly used for this port.
2480 */
2481 intel_dp->DP |= DP_PORT_EN;
2482
2483 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2484 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2485}
2486
e8cb4558 2487static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2488{
e8cb4558
DV		 2489 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2490 struct drm_device *dev = encoder->base.dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2492 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2493 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2494
0c33d8d7
DV		 2495 if (WARN_ON(dp_reg & DP_PORT_EN))
2496 return;
5d613501 2497
093e3f13
VS		 2498 pps_lock(intel_dp);
2499
2500 if (IS_VALLEYVIEW(dev))
2501 vlv_init_panel_power_sequencer(intel_dp);
2502
7b13b58a 2503 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2504
2505 edp_panel_vdd_on(intel_dp);
2506 edp_panel_on(intel_dp);
2507 edp_panel_vdd_off(intel_dp, true);
2508
2509 pps_unlock(intel_dp);
2510
61234fa5
VS		 2511 if (IS_VALLEYVIEW(dev))
2512 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2513
f01eca2e 2514 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2515 intel_dp_start_link_train(intel_dp);
33a34e4e 2516 intel_dp_complete_link_train(intel_dp);
3ab9c637 2517 intel_dp_stop_link_train(intel_dp);
c1dec79a 2518
6e3c9717 2519 if (crtc->config->has_audio) {
c1dec79a
JN		 2520 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2521 pipe_name(crtc->pipe));
2522 intel_audio_codec_enable(encoder);
2523 }
ab1f90f9 2524}
89b667f8 2525
ecff4f3b
JN		 2526static void g4x_enable_dp(struct intel_encoder *encoder)
2527{
828f5c6e
JN		 2528 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2529
ecff4f3b 2530 intel_enable_dp(encoder);
4be73780 2531 intel_edp_backlight_on(intel_dp);
ab1f90f9 2532}
89b667f8 2533
ab1f90f9
JN		 2534static void vlv_enable_dp(struct intel_encoder *encoder)
2535{
828f5c6e
JN		 2536 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2537
4be73780 2538 intel_edp_backlight_on(intel_dp);
b32c6f48 2539 intel_psr_enable(intel_dp);
d240f20f
JB		 2540}
2541
ecff4f3b 2542static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2543{
2544 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2545 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2546
8ac33ed3
DV		 2547 intel_dp_prepare(encoder);
2548
d41f1efb
DV		 2549 /* Only ilk+ has port A */
2550 if (dport->port == PORT_A) {
2551 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2552 ironlake_edp_pll_on(intel_dp);
d41f1efb 2553 }
ab1f90f9
JN		 2554}
2555
83b84597
VS		 2556static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2557{
2558 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2559 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2560 enum pipe pipe = intel_dp->pps_pipe;
2561 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2562
2563 edp_panel_vdd_off_sync(intel_dp);
2564
2565 /*
2566 * VLV seems to get confused when multiple power seqeuencers
2567 * have the same port selected (even if only one has power/vdd
2568 * enabled). The failure manifests as vlv_wait_port_ready() failing
2569 * CHV on the other hand doesn't seem to mind having the same port
2570 * selected in multiple power seqeuencers, but let's clear the
2571 * port select always when logically disconnecting a power sequencer
2572 * from a port.
2573 */
2574 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2575 pipe_name(pipe), port_name(intel_dig_port->port));
2576 I915_WRITE(pp_on_reg, 0);
2577 POSTING_READ(pp_on_reg);
2578
2579 intel_dp->pps_pipe = INVALID_PIPE;
2580}
2581
a4a5d2f8
VS		 2582static void vlv_steal_power_sequencer(struct drm_device *dev,
2583 enum pipe pipe)
2584{
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct intel_encoder *encoder;
2587
2588 lockdep_assert_held(&dev_priv->pps_mutex);
2589
ac3c12e4
VS		 2590 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2591 return;
2592
a4a5d2f8
VS		 2593 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2594 base.head) {
2595 struct intel_dp *intel_dp;
773538e8 2596 enum port port;
a4a5d2f8
VS		 2597
2598 if (encoder->type != INTEL_OUTPUT_EDP)
2599 continue;
2600
2601 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2602 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2603
2604 if (intel_dp->pps_pipe != pipe)
2605 continue;
2606
2607 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2608 pipe_name(pipe), port_name(port));
a4a5d2f8 2609
034e43c6
VS		 2610 WARN(encoder->connectors_active,
2611 "stealing pipe %c power sequencer from active eDP port %c\n",
2612 pipe_name(pipe), port_name(port));
a4a5d2f8 2613
a4a5d2f8 2614 /* make sure vdd is off before we steal it */
83b84597 2615 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2616 }
2617}
2618
2619static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2620{
2621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2622 struct intel_encoder *encoder = &intel_dig_port->base;
2623 struct drm_device *dev = encoder->base.dev;
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2626
2627 lockdep_assert_held(&dev_priv->pps_mutex);
2628
093e3f13
VS		 2629 if (!is_edp(intel_dp))
2630 return;
2631
a4a5d2f8
VS		 2632 if (intel_dp->pps_pipe == crtc->pipe)
2633 return;
2634
2635 /*
2636 * If another power sequencer was being used on this
2637 * port previously make sure to turn off vdd there while
2638 * we still have control of it.
2639 */
2640 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2641 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2642
2643 /*
2644 * We may be stealing the power
2645 * sequencer from another port.
2646 */
2647 vlv_steal_power_sequencer(dev, crtc->pipe);
2648
2649 /* now it's all ours */
2650 intel_dp->pps_pipe = crtc->pipe;
2651
2652 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2653 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2654
2655 /* init power sequencer on this pipe and port */
36b5f425
VS		 2656 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2657 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2658}
2659
ab1f90f9 2660static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2661{
2bd2ad64 2662 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2663 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2664 struct drm_device *dev = encoder->base.dev;
89b667f8 2665 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2666 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2667 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2668 int pipe = intel_crtc->pipe;
2669 u32 val;
a4fc5ed6 2670
ab1f90f9 2671 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2672
ab3c759a 2673 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2674 val = 0;
2675 if (pipe)
2676 val |= (1<<21);
2677 else
2678 val &= ~(1<<21);
2679 val |= 0x001000c4;
ab3c759a
CML		 2680 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2681 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2682 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2683
ab1f90f9
JN		 2684 mutex_unlock(&dev_priv->dpio_lock);
2685
2686 intel_enable_dp(encoder);
89b667f8
JB		 2687}
2688
ecff4f3b 2689static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2690{
2691 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2692 struct drm_device *dev = encoder->base.dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2694 struct intel_crtc *intel_crtc =
2695 to_intel_crtc(encoder->base.crtc);
e4607fcf 2696 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2697 int pipe = intel_crtc->pipe;
89b667f8 2698
8ac33ed3
DV		 2699 intel_dp_prepare(encoder);
2700
89b667f8 2701 /* Program Tx lane resets to default */
0980a60f 2702 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2703 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2704 DPIO_PCS_TX_LANE2_RESET |
2705 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2706 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2707 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2708 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2709 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2710 DPIO_PCS_CLK_SOFT_RESET);
2711
2712 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2713 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2714 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2715 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2716 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2717}
2718
e4a1d846
CML		 2719static void chv_pre_enable_dp(struct intel_encoder *encoder)
2720{
2721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2722 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2723 struct drm_device *dev = encoder->base.dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2725 struct intel_crtc *intel_crtc =
2726 to_intel_crtc(encoder->base.crtc);
2727 enum dpio_channel ch = vlv_dport_to_channel(dport);
2728 int pipe = intel_crtc->pipe;
2729 int data, i;
949c1d43 2730 u32 val;
e4a1d846 2731
e4a1d846 2732 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2733
570e2a74
VS		 2734 /* allow hardware to manage TX FIFO reset source */
2735 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2736 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2737 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2738
2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2740 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2741 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2742
949c1d43 2743 /* Deassert soft data lane reset*/
97fd4d5c 2744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2745 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2746 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2747
2748 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2749 val |= CHV_PCS_REQ_SOFTRESET_EN;
2750 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2751
2752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2753 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2754 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2755
97fd4d5c 2756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2757 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2758 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2759
2760 /* Program Tx lane latency optimal setting*/
e4a1d846 2761 for (i = 0; i < 4; i++) {
e4a1d846
CML		 2762 /* Set the upar bit */
2763 data = (i == 1) ? 0x0 : 0x1;
2764 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2765 data << DPIO_UPAR_SHIFT);
2766 }
2767
2768 /* Data lane stagger programming */
2769 /* FIXME: Fix up value only after power analysis */
2770
2771 mutex_unlock(&dev_priv->dpio_lock);
2772
e4a1d846 2773 intel_enable_dp(encoder);
e4a1d846
CML		 2774}
2775
9197c88b
VS		 2776static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2777{
2778 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2779 struct drm_device *dev = encoder->base.dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc =
2782 to_intel_crtc(encoder->base.crtc);
2783 enum dpio_channel ch = vlv_dport_to_channel(dport);
2784 enum pipe pipe = intel_crtc->pipe;
2785 u32 val;
2786
625695f8
VS		 2787 intel_dp_prepare(encoder);
2788
9197c88b
VS		 2789 mutex_lock(&dev_priv->dpio_lock);
2790
b9e5ac3c
VS		 2791 /* program left/right clock distribution */
2792 if (pipe != PIPE_B) {
2793 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2794 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2795 if (ch == DPIO_CH0)
2796 val |= CHV_BUFLEFTENA1_FORCE;
2797 if (ch == DPIO_CH1)
2798 val |= CHV_BUFRIGHTENA1_FORCE;
2799 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2800 } else {
2801 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2802 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2803 if (ch == DPIO_CH0)
2804 val |= CHV_BUFLEFTENA2_FORCE;
2805 if (ch == DPIO_CH1)
2806 val |= CHV_BUFRIGHTENA2_FORCE;
2807 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2808 }
2809
9197c88b
VS		 2810 /* program clock channel usage */
2811 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2812 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2813 if (pipe != PIPE_B)
2814 val &= ~CHV_PCS_USEDCLKCHANNEL;
2815 else
2816 val |= CHV_PCS_USEDCLKCHANNEL;
2817 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2818
2819 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2820 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2821 if (pipe != PIPE_B)
2822 val &= ~CHV_PCS_USEDCLKCHANNEL;
2823 else
2824 val |= CHV_PCS_USEDCLKCHANNEL;
2825 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2826
2827 /*
2828 * This a a bit weird since generally CL
2829 * matches the pipe, but here we need to
2830 * pick the CL based on the port.
2831 */
2832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2833 if (pipe != PIPE_B)
2834 val &= ~CHV_CMN_USEDCLKCHANNEL;
2835 else
2836 val |= CHV_CMN_USEDCLKCHANNEL;
2837 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2838
2839 mutex_unlock(&dev_priv->dpio_lock);
2840}
2841
a4fc5ed6 2842/*
df0c237d
JB		 2843 * Native read with retry for link status and receiver capability reads for
2844 * cases where the sink may still be asleep.
9d1a1031
JN		 2845 *
2846 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2847 * supposed to retry 3 times per the spec.
a4fc5ed6 2848 */
9d1a1031
JN		 2849static ssize_t
2850intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2851 void *buffer, size_t size)
a4fc5ed6 2852{
9d1a1031
JN		 2853 ssize_t ret;
2854 int i;
61da5fab 2855
f6a19066
VS		 2856 /*
2857 * Sometime we just get the same incorrect byte repeated
2858 * over the entire buffer. Doing just one throw away read
2859 * initially seems to "solve" it.
2860 */
2861 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2862
61da5fab 2863 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2864 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2865 if (ret == size)
2866 return ret;
61da5fab
JB		 2867 msleep(1);
2868 }
a4fc5ed6 2869
9d1a1031 2870 return ret;
a4fc5ed6
KP		 2871}
2872
2873/*
2874 * Fetch AUX CH registers 0x202 - 0x207 which contain
2875 * link status information
2876 */
2877static bool
93f62dad 2878intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2879{
9d1a1031
JN		 2880 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2881 DP_LANE0_1_STATUS,
2882 link_status,
2883 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2884}
2885
1100244e 2886/* These are source-specific values. */
a4fc5ed6 2887static uint8_t
1a2eb460 2888intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2889{
30add22d 2890 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2891 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2892 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2893
9314726b
VK		 2894 if (IS_BROXTON(dev))
2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2896 else if (INTEL_INFO(dev)->gen >= 9) {
7ad14a29
SJ		 2897 if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
2898 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2900 } else if (IS_VALLEYVIEW(dev))
bd60018a 2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2902 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2903 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2904 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2905 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2906 else
bd60018a 2907 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2908}
2909
2910static uint8_t
2911intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2912{
30add22d 2913 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2914 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2915
5a9d1f1a
DL		 2916 if (INTEL_INFO(dev)->gen >= 9) {
2917 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2919 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2923 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2925 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2926 default:
2927 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2928 }
2929 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2930 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2932 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2938 default:
bd60018a 2939 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2940 }
e2fa6fba
P		 2941 } else if (IS_VALLEYVIEW(dev)) {
2942 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2944 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2946 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2948 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2950 default:
bd60018a 2951 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2952 }
bc7d38a4 2953 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2954 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2956 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2960 default:
bd60018a 2961 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2962 }
2963 } else {
2964 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2968 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2970 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2972 default:
bd60018a 2973 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2974 }
a4fc5ed6
KP		 2975 }
2976}
2977
5829975c 2978static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 2979{
2980 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2983 struct intel_crtc *intel_crtc =
2984 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2985 unsigned long demph_reg_value, preemph_reg_value,
2986 uniqtranscale_reg_value;
2987 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2988 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2989 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2990
2991 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2992 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2993 preemph_reg_value = 0x0004000;
2994 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2996 demph_reg_value = 0x2B405555;
2997 uniqtranscale_reg_value = 0x552AB83A;
2998 break;
bd60018a 2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3000 demph_reg_value = 0x2B404040;
3001 uniqtranscale_reg_value = 0x5548B83A;
3002 break;
bd60018a 3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3004 demph_reg_value = 0x2B245555;
3005 uniqtranscale_reg_value = 0x5560B83A;
3006 break;
bd60018a 3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3008 demph_reg_value = 0x2B405555;
3009 uniqtranscale_reg_value = 0x5598DA3A;
3010 break;
3011 default:
3012 return 0;
3013 }
3014 break;
bd60018a 3015 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3016 preemph_reg_value = 0x0002000;
3017 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3019 demph_reg_value = 0x2B404040;
3020 uniqtranscale_reg_value = 0x5552B83A;
3021 break;
bd60018a 3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3023 demph_reg_value = 0x2B404848;
3024 uniqtranscale_reg_value = 0x5580B83A;
3025 break;
bd60018a 3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3027 demph_reg_value = 0x2B404040;
3028 uniqtranscale_reg_value = 0x55ADDA3A;
3029 break;
3030 default:
3031 return 0;
3032 }
3033 break;
bd60018a 3034 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3035 preemph_reg_value = 0x0000000;
3036 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3038 demph_reg_value = 0x2B305555;
3039 uniqtranscale_reg_value = 0x5570B83A;
3040 break;
bd60018a 3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3042 demph_reg_value = 0x2B2B4040;
3043 uniqtranscale_reg_value = 0x55ADDA3A;
3044 break;
3045 default:
3046 return 0;
3047 }
3048 break;
bd60018a 3049 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3050 preemph_reg_value = 0x0006000;
3051 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3053 demph_reg_value = 0x1B405555;
3054 uniqtranscale_reg_value = 0x55ADDA3A;
3055 break;
3056 default:
3057 return 0;
3058 }
3059 break;
3060 default:
3061 return 0;
3062 }
3063
0980a60f 3064 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3065 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3066 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3067 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3068 uniqtranscale_reg_value);
ab3c759a
CML		 3069 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3070 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3071 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3072 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3073 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3074
3075 return 0;
3076}
3077
5829975c 3078static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3079{
3080 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3083 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3084 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3085 uint8_t train_set = intel_dp->train_set[0];
3086 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3087 enum pipe pipe = intel_crtc->pipe;
3088 int i;
e4a1d846
CML		 3089
3090 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3091 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3092 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3094 deemph_reg_value = 128;
3095 margin_reg_value = 52;
3096 break;
bd60018a 3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3098 deemph_reg_value = 128;
3099 margin_reg_value = 77;
3100 break;
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3102 deemph_reg_value = 128;
3103 margin_reg_value = 102;
3104 break;
bd60018a 3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3106 deemph_reg_value = 128;
3107 margin_reg_value = 154;
3108 /* FIXME extra to set for 1200 */
3109 break;
3110 default:
3111 return 0;
3112 }
3113 break;
bd60018a 3114 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3115 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3117 deemph_reg_value = 85;
3118 margin_reg_value = 78;
3119 break;
bd60018a 3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3121 deemph_reg_value = 85;
3122 margin_reg_value = 116;
3123 break;
bd60018a 3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3125 deemph_reg_value = 85;
3126 margin_reg_value = 154;
3127 break;
3128 default:
3129 return 0;
3130 }
3131 break;
bd60018a 3132 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3133 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3135 deemph_reg_value = 64;
3136 margin_reg_value = 104;
3137 break;
bd60018a 3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3139 deemph_reg_value = 64;
3140 margin_reg_value = 154;
3141 break;
3142 default:
3143 return 0;
3144 }
3145 break;
bd60018a 3146 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3147 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3149 deemph_reg_value = 43;
3150 margin_reg_value = 154;
3151 break;
3152 default:
3153 return 0;
3154 }
3155 break;
3156 default:
3157 return 0;
3158 }
3159
3160 mutex_lock(&dev_priv->dpio_lock);
3161
3162 /* Clear calc init */
1966e59e
VS		 3163 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3164 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3165 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3166 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3167 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3168
3169 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3170 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3171 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3172 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3173 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3174
a02ef3c7
VS		 3175 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3176 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3177 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3178 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3179
3180 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3181 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3182 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3183 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3184
e4a1d846 3185 /* Program swing deemph */
f72df8db
VS		 3186 for (i = 0; i < 4; i++) {
3187 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3188 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3189 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3190 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3191 }
e4a1d846
CML		 3192
3193 /* Program swing margin */
f72df8db
VS		 3194 for (i = 0; i < 4; i++) {
3195 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3196 val &= ~DPIO_SWING_MARGIN000_MASK;
3197 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3198 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3199 }
e4a1d846
CML		 3200
3201 /* Disable unique transition scale */
f72df8db
VS		 3202 for (i = 0; i < 4; i++) {
3203 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3204 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3205 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3206 }
e4a1d846
CML		 3207
3208 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3209 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3210 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3211 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3212
3213 /*
3214 * The document said it needs to set bit 27 for ch0 and bit 26
3215 * for ch1. Might be a typo in the doc.
3216 * For now, for this unique transition scale selection, set bit
3217 * 27 for ch0 and ch1.
3218 */
f72df8db
VS		 3219 for (i = 0; i < 4; i++) {
3220 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3221 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3222 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3223 }
e4a1d846 3224
f72df8db
VS		 3225 for (i = 0; i < 4; i++) {
3226 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3227 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3228 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3229 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3230 }
e4a1d846
CML		 3231 }
3232
3233 /* Start swing calculation */
1966e59e
VS		 3234 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3235 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3236 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3237
3238 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3239 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3240 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3241
3242 /* LRC Bypass */
3243 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3244 val |= DPIO_LRC_BYPASS;
3245 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3246
3247 mutex_unlock(&dev_priv->dpio_lock);
3248
3249 return 0;
3250}
3251
a4fc5ed6 3252static void
0301b3ac
JN		 3253intel_get_adjust_train(struct intel_dp *intel_dp,
3254 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3255{
3256 uint8_t v = 0;
3257 uint8_t p = 0;
3258 int lane;
1a2eb460
KP		 3259 uint8_t voltage_max;
3260 uint8_t preemph_max;
a4fc5ed6 3261
33a34e4e 3262 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3263 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3264 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3265
3266 if (this_v > v)
3267 v = this_v;
3268 if (this_p > p)
3269 p = this_p;
3270 }
3271
1a2eb460 3272 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3273 if (v >= voltage_max)
3274 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3275
1a2eb460
KP		 3276 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3277 if (p >= preemph_max)
3278 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3279
3280 for (lane = 0; lane < 4; lane++)
33a34e4e 3281 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3282}
3283
3284static uint32_t
5829975c 3285gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3286{
3cf2efb1 3287 uint32_t signal_levels = 0;
a4fc5ed6 3288
3cf2efb1 3289 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3291 default:
3292 signal_levels |= DP_VOLTAGE_0_4;
3293 break;
bd60018a 3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3295 signal_levels |= DP_VOLTAGE_0_6;
3296 break;
bd60018a 3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3298 signal_levels |= DP_VOLTAGE_0_8;
3299 break;
bd60018a 3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3301 signal_levels |= DP_VOLTAGE_1_2;
3302 break;
3303 }
3cf2efb1 3304 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3305 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3306 default:
3307 signal_levels |= DP_PRE_EMPHASIS_0;
3308 break;
bd60018a 3309 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3310 signal_levels |= DP_PRE_EMPHASIS_3_5;
3311 break;
bd60018a 3312 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3313 signal_levels |= DP_PRE_EMPHASIS_6;
3314 break;
bd60018a 3315 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3316 signal_levels |= DP_PRE_EMPHASIS_9_5;
3317 break;
3318 }
3319 return signal_levels;
3320}
3321
e3421a18
ZW		 3322/* Gen6's DP voltage swing and pre-emphasis control */
3323static uint32_t
5829975c 3324gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3325{
3c5a62b5
YL		 3326 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3327 DP_TRAIN_PRE_EMPHASIS_MASK);
3328 switch (signal_levels) {
bd60018a
SJ		 3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3331 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3333 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3336 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3339 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3342 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3343 default:
3c5a62b5
YL		 3344 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3345 "0x%x\n", signal_levels);
3346 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3347 }
3348}
3349
1a2eb460
KP		 3350/* Gen7's DP voltage swing and pre-emphasis control */
3351static uint32_t
5829975c 3352gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3353{
3354 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3355 DP_TRAIN_PRE_EMPHASIS_MASK);
3356 switch (signal_levels) {
bd60018a 3357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3358 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3360 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3361 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3362 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3363
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3365 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3367 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3368
bd60018a 3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3370 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3372 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3373
3374 default:
3375 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3376 "0x%x\n", signal_levels);
3377 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3378 }
3379}
3380
d6c0d722
PZ		 3381/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3382static uint32_t
5829975c 3383hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3384{
d6c0d722
PZ		 3385 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3386 DP_TRAIN_PRE_EMPHASIS_MASK);
3387 switch (signal_levels) {
bd60018a 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3389 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3391 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3392 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3393 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3395 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3396
bd60018a 3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3398 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3400 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3402 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3403
bd60018a 3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3405 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3407 return DDI_BUF_TRANS_SELECT(8);
7ad14a29
SJ		 3408
3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3410 return DDI_BUF_TRANS_SELECT(9);
d6c0d722
PZ		 3411 default:
3412 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3413 "0x%x\n", signal_levels);
c5fe6a06 3414 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3415 }
a4fc5ed6
KP		 3416}
3417
5829975c 3418static void bxt_signal_levels(struct intel_dp *intel_dp)
96fb9f9b
VK		 3419{
3420 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3421 enum port port = dport->port;
3422 struct drm_device *dev = dport->base.base.dev;
3423 struct intel_encoder *encoder = &dport->base;
3424 uint8_t train_set = intel_dp->train_set[0];
3425 uint32_t level = 0;
3426
3427 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3428 DP_TRAIN_PRE_EMPHASIS_MASK);
3429 switch (signal_levels) {
3430 default:
3431 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3433 level = 0;
3434 break;
3435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3436 level = 1;
3437 break;
3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3439 level = 2;
3440 break;
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3442 level = 3;
3443 break;
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3445 level = 4;
3446 break;
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3448 level = 5;
3449 break;
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3451 level = 6;
3452 break;
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3454 level = 7;
3455 break;
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3457 level = 8;
3458 break;
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3460 level = 9;
3461 break;
3462 }
3463
3464 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
3465}
3466
f0a3424e
PZ		 3467/* Properly updates "DP" with the correct signal levels. */
3468static void
3469intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3470{
3471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3472 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3473 struct drm_device *dev = intel_dig_port->base.base.dev;
3474 uint32_t signal_levels, mask;
3475 uint8_t train_set = intel_dp->train_set[0];
3476
96fb9f9b
VK		 3477 if (IS_BROXTON(dev)) {
3478 signal_levels = 0;
5829975c 3479 bxt_signal_levels(intel_dp);
96fb9f9b
VK		 3480 mask = 0;
3481 } else if (HAS_DDI(dev)) {
5829975c 3482 signal_levels = hsw_signal_levels(train_set);
f0a3424e 3483 mask = DDI_BUF_EMP_MASK;
e4a1d846 3484 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3485 signal_levels = chv_signal_levels(intel_dp);
e4a1d846 3486 mask = 0;
e2fa6fba 3487 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3488 signal_levels = vlv_signal_levels(intel_dp);
e2fa6fba 3489 mask = 0;
bc7d38a4 3490 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3491 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3492 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3493 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3494 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3495 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3496 } else {
5829975c 3497 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3498 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3499 }
3500
96fb9f9b
VK		 3501 if (mask)
3502 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3503
3504 DRM_DEBUG_KMS("Using vswing level %d\n",
3505 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3506 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3507 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3508 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e
PZ		 3509
3510 *DP = (*DP & ~mask) | signal_levels;
3511}
3512
a4fc5ed6 3513static bool
ea5b213a 3514intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3515 uint32_t *DP,
58e10eb9 3516 uint8_t dp_train_pat)
a4fc5ed6 3517{
174edf1f
PZ		 3518 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3519 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3520 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3521 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3522 int ret, len;
a4fc5ed6 3523
7b13b58a 3524 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3525
70aff66c 3526 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3527 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3528
2cdfe6c8
JN		 3529 buf[0] = dp_train_pat;
3530 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3531 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3532 /* don't write DP_TRAINING_LANEx_SET on disable */
3533 len = 1;
3534 } else {
3535 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3536 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3537 len = intel_dp->lane_count + 1;
47ea7542 3538 }
a4fc5ed6 3539
9d1a1031
JN		 3540 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3541 buf, len);
2cdfe6c8
JN		 3542
3543 return ret == len;
a4fc5ed6
KP		 3544}
3545
70aff66c
JN		 3546static bool
3547intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3548 uint8_t dp_train_pat)
3549{
953d22e8 3550 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3551 intel_dp_set_signal_levels(intel_dp, DP);
3552 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3553}
3554
3555static bool
3556intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3557 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3558{
3559 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3560 struct drm_device *dev = intel_dig_port->base.base.dev;
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 int ret;
3563
3564 intel_get_adjust_train(intel_dp, link_status);
3565 intel_dp_set_signal_levels(intel_dp, DP);
3566
3567 I915_WRITE(intel_dp->output_reg, *DP);
3568 POSTING_READ(intel_dp->output_reg);
3569
9d1a1031
JN		 3570 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3571 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3572
3573 return ret == intel_dp->lane_count;
3574}
3575
3ab9c637
ID		 3576static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3577{
3578 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3579 struct drm_device *dev = intel_dig_port->base.base.dev;
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 enum port port = intel_dig_port->port;
3582 uint32_t val;
3583
3584 if (!HAS_DDI(dev))
3585 return;
3586
3587 val = I915_READ(DP_TP_CTL(port));
3588 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3589 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3590 I915_WRITE(DP_TP_CTL(port), val);
3591
3592 /*
3593 * On PORT_A we can have only eDP in SST mode. There the only reason
3594 * we need to set idle transmission mode is to work around a HW issue
3595 * where we enable the pipe while not in idle link-training mode.
3596 * In this case there is requirement to wait for a minimum number of
3597 * idle patterns to be sent.
3598 */
3599 if (port == PORT_A)
3600 return;
3601
3602 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3603 1))
3604 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3605}
3606
33a34e4e 3607/* Enable corresponding port and start training pattern 1 */
c19b0669 3608void
33a34e4e 3609intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3610{
da63a9f2 3611 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3612 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3613 int i;
3614 uint8_t voltage;
cdb0e95b 3615 int voltage_tries, loop_tries;
ea5b213a 3616 uint32_t DP = intel_dp->DP;
6aba5b6c 3617 uint8_t link_config[2];
a4fc5ed6 3618
affa9354 3619 if (HAS_DDI(dev))
c19b0669
PZ		 3620 intel_ddi_prepare_link_retrain(encoder);
3621
3cf2efb1 3622 /* Write the link configuration data */
6aba5b6c
JN		 3623 link_config[0] = intel_dp->link_bw;
3624 link_config[1] = intel_dp->lane_count;
3625 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3626 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3627 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
94ca719e 3628 if (intel_dp->num_sink_rates)
a8f3ef61
SJ		 3629 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3630 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3631
3632 link_config[0] = 0;
3633 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3634 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3635
3636 DP |= DP_PORT_EN;
1a2eb460 3637
70aff66c
JN		 3638 /* clock recovery */
3639 if (!intel_dp_reset_link_train(intel_dp, &DP,
3640 DP_TRAINING_PATTERN_1 |
3641 DP_LINK_SCRAMBLING_DISABLE)) {
3642 DRM_ERROR("failed to enable link training\n");
3643 return;
3644 }
3645
a4fc5ed6 3646 voltage = 0xff;
cdb0e95b
KP		 3647 voltage_tries = 0;
3648 loop_tries = 0;
a4fc5ed6 3649 for (;;) {
70aff66c 3650 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3651
a7c9655f 3652 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3653 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3654 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3655 break;
93f62dad 3656 }
a4fc5ed6 3657
01916270 3658 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3659 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3660 break;
3661 }
3662
3663 /* Check to see if we've tried the max voltage */
3664 for (i = 0; i < intel_dp->lane_count; i++)
3665 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3666 break;
3b4f819d 3667 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3668 ++loop_tries;
3669 if (loop_tries == 5) {
3def84b3 3670 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3671 break;
3672 }
70aff66c
JN		 3673 intel_dp_reset_link_train(intel_dp, &DP,
3674 DP_TRAINING_PATTERN_1 |
3675 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3676 voltage_tries = 0;
3677 continue;
3678 }
a4fc5ed6 3679
3cf2efb1 3680 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3681 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3682 ++voltage_tries;
b06fbda3 3683 if (voltage_tries == 5) {
3def84b3 3684 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3685 break;
3686 }
3687 } else
3688 voltage_tries = 0;
3689 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3690
70aff66c
JN		 3691 /* Update training set as requested by target */
3692 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3693 DRM_ERROR("failed to update link training\n");
3694 break;
3695 }
a4fc5ed6
KP		 3696 }
3697
33a34e4e
JB		 3698 intel_dp->DP = DP;
3699}
3700
c19b0669 3701void
33a34e4e
JB		 3702intel_dp_complete_link_train(struct intel_dp *intel_dp)
3703{
33a34e4e 3704 bool channel_eq = false;
37f80975 3705 int tries, cr_tries;
33a34e4e 3706 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3707 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3708
3709 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3710 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3711 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3712
a4fc5ed6 3713 /* channel equalization */
70aff66c 3714 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3715 training_pattern |
70aff66c
JN		 3716 DP_LINK_SCRAMBLING_DISABLE)) {
3717 DRM_ERROR("failed to start channel equalization\n");
3718 return;
3719 }
3720
a4fc5ed6 3721 tries = 0;
37f80975 3722 cr_tries = 0;
a4fc5ed6
KP		 3723 channel_eq = false;
3724 for (;;) {
70aff66c 3725 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3726
37f80975
JB		 3727 if (cr_tries > 5) {
3728 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3729 break;
3730 }
3731
a7c9655f 3732 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3733 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3734 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3735 break;
70aff66c 3736 }
a4fc5ed6 3737
37f80975 3738 /* Make sure clock is still ok */
01916270 3739 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3740 intel_dp_start_link_train(intel_dp);
70aff66c 3741 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3742 training_pattern |
70aff66c 3743 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3744 cr_tries++;
3745 continue;
3746 }
3747
1ffdff13 3748 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3749 channel_eq = true;
3750 break;
3751 }
a4fc5ed6 3752
37f80975
JB		 3753 /* Try 5 times, then try clock recovery if that fails */
3754 if (tries > 5) {
37f80975 3755 intel_dp_start_link_train(intel_dp);
70aff66c 3756 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3757 training_pattern |
70aff66c 3758 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3759 tries = 0;
3760 cr_tries++;
3761 continue;
3762 }
a4fc5ed6 3763
70aff66c
JN		 3764 /* Update training set as requested by target */
3765 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3766 DRM_ERROR("failed to update link training\n");
3767 break;
3768 }
3cf2efb1 3769 ++tries;
869184a6 3770 }
3cf2efb1 3771
3ab9c637
ID		 3772 intel_dp_set_idle_link_train(intel_dp);
3773
3774 intel_dp->DP = DP;
3775
d6c0d722 3776 if (channel_eq)
07f42258 3777 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3778
3ab9c637
ID		 3779}
3780
3781void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3782{
70aff66c 3783 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3784 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3785}
3786
3787static void
ea5b213a 3788intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3789{
da63a9f2 3790 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3791 enum port port = intel_dig_port->port;
da63a9f2 3792 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3793 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3794 uint32_t DP = intel_dp->DP;
a4fc5ed6 3795
bc76e320 3796 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3797 return;
3798
0c33d8d7 3799 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3800 return;
3801
28c97730 3802 DRM_DEBUG_KMS("\n");
32f9d658 3803
bc7d38a4 3804 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3805 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3806 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3807 } else {
aad3d14d
VS		 3808 if (IS_CHERRYVIEW(dev))
3809 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3810 else
3811 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3812 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3813 }
fe255d00 3814 POSTING_READ(intel_dp->output_reg);
5eb08b69 3815
493a7081 3816 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3817 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
5bddd17f
EA		 3818 /* Hardware workaround: leaving our transcoder select
3819 * set to transcoder B while it's off will prevent the
3820 * corresponding HDMI output on transcoder A.
3821 *
3822 * Combine this with another hardware workaround:
3823 * transcoder select bit can only be cleared while the
3824 * port is enabled.
3825 */
3826 DP &= ~DP_PIPEB_SELECT;
3827 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3828 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3829 }
3830
832afda6 3831 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3832 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3833 POSTING_READ(intel_dp->output_reg);
f01eca2e 3834 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3835}
3836
26d61aad
KP		 3837static bool
3838intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3839{
a031d709
RV		 3840 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3841 struct drm_device *dev = dig_port->base.base.dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3843 uint8_t rev;
a031d709 3844
9d1a1031
JN		 3845 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3846 sizeof(intel_dp->dpcd)) < 0)
edb39244 3847 return false; /* aux transfer failed */
92fd8fd1 3848
a8e98153 3849 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3850
edb39244
AJ		 3851 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3852 return false; /* DPCD not present */
3853
2293bb5c
SK		 3854 /* Check if the panel supports PSR */
3855 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3856 if (is_edp(intel_dp)) {
9d1a1031
JN		 3857 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3858 intel_dp->psr_dpcd,
3859 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3860 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3861 dev_priv->psr.sink_support = true;
50003939 3862 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3863 }
474d1ec4
SJ		 3864
3865 if (INTEL_INFO(dev)->gen >= 9 &&
3866 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3867 uint8_t frame_sync_cap;
3868
3869 dev_priv->psr.sink_support = true;
3870 intel_dp_dpcd_read_wake(&intel_dp->aux,
3871 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3872 &frame_sync_cap, 1);
3873 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3874 /* PSR2 needs frame sync as well */
3875 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3876 DRM_DEBUG_KMS("PSR2 %s on sink",
3877 dev_priv->psr.psr2_support ? "supported" : "not supported");
3878 }
50003939
JN		 3879 }
3880
7809a611 3881 /* Training Pattern 3 support, both source and sink */
06ea66b6 3882 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3883 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3884 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3885 intel_dp->use_tps3 = true;
f8d8a672 3886 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3887 } else
3888 intel_dp->use_tps3 = false;
3889
fc0f8e25
SJ		 3890 /* Intermediate frequency support */
3891 if (is_edp(intel_dp) &&
3892 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3893 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3894 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3895 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3896 int i;
3897
fc0f8e25
SJ		 3898 intel_dp_dpcd_read_wake(&intel_dp->aux,
3899 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3900 sink_rates,
3901 sizeof(sink_rates));
ea2d8a42 3902
94ca719e
VS		 3903 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3904 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3905
3906 if (val == 0)
3907 break;
3908
94ca719e 3909 intel_dp->sink_rates[i] = val * 200;
ea2d8a42 3910 }
94ca719e 3911 intel_dp->num_sink_rates = i;
fc0f8e25 3912 }
0336400e
VS		 3913
3914 intel_dp_print_rates(intel_dp);
3915
edb39244
AJ		 3916 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3917 DP_DWN_STRM_PORT_PRESENT))
3918 return true; /* native DP sink */
3919
3920 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3921 return true; /* no per-port downstream info */
3922
9d1a1031
JN		 3923 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3924 intel_dp->downstream_ports,
3925 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3926 return false; /* downstream port status fetch failed */
3927
3928 return true;
92fd8fd1
KP		 3929}
3930
0d198328
AJ		 3931static void
3932intel_dp_probe_oui(struct intel_dp *intel_dp)
3933{
3934 u8 buf[3];
3935
3936 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3937 return;
3938
9d1a1031 3939 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3940 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3941 buf[0], buf[1], buf[2]);
3942
9d1a1031 3943 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3944 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3945 buf[0], buf[1], buf[2]);
3946}
3947
0e32b39c
DA		 3948static bool
3949intel_dp_probe_mst(struct intel_dp *intel_dp)
3950{
3951 u8 buf[1];
3952
3953 if (!intel_dp->can_mst)
3954 return false;
3955
3956 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3957 return false;
3958
0e32b39c
DA		 3959 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3960 if (buf[0] & DP_MST_CAP) {
3961 DRM_DEBUG_KMS("Sink is MST capable\n");
3962 intel_dp->is_mst = true;
3963 } else {
3964 DRM_DEBUG_KMS("Sink is not MST capable\n");
3965 intel_dp->is_mst = false;
3966 }
3967 }
0e32b39c
DA		 3968
3969 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3970 return intel_dp->is_mst;
3971}
3972
d2e216d0
RV		 3973int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3974{
3975 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3976 struct drm_device *dev = intel_dig_port->base.base.dev;
3977 struct intel_crtc *intel_crtc =
3978 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3979 u8 buf;
3980 int test_crc_count;
3981 int attempts = 6;
d2e216d0 3982
ad9dc91b 3983 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3984 return -EIO;
d2e216d0 3985
ad9dc91b 3986 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3987 return -ENOTTY;
3988
1dda5f93
RV		 3989 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3990 return -EIO;
3991
9d1a1031 3992 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3993 buf | DP_TEST_SINK_START) < 0)
bda0381e 3994 return -EIO;
d2e216d0 3995
1dda5f93 3996 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3997 return -EIO;
ad9dc91b 3998 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3999
ad9dc91b 4000 do {
1dda5f93
RV		 4001 if (drm_dp_dpcd_readb(&intel_dp->aux,
4002 DP_TEST_SINK_MISC, &buf) < 0)
4003 return -EIO;
ad9dc91b
RV		 4004 intel_wait_for_vblank(dev, intel_crtc->pipe);
4005 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4006
4007 if (attempts == 0) {
90bd1f46
DV		 4008 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4009 return -ETIMEDOUT;
ad9dc91b 4010 }
d2e216d0 4011
9d1a1031 4012 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 4013 return -EIO;
d2e216d0 4014
1dda5f93
RV		 4015 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4016 return -EIO;
4017 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4018 buf & ~DP_TEST_SINK_START) < 0)
4019 return -EIO;
ce31d9f4 4020
d2e216d0
RV		 4021 return 0;
4022}
4023
a60f0e38
JB		 4024static bool
4025intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4026{
9d1a1031
JN		 4027 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4028 DP_DEVICE_SERVICE_IRQ_VECTOR,
4029 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4030}
4031
0e32b39c
DA		 4032static bool
4033intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4034{
4035 int ret;
4036
4037 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4038 DP_SINK_COUNT_ESI,
4039 sink_irq_vector, 14);
4040 if (ret != 14)
4041 return false;
4042
4043 return true;
4044}
4045
c5d5ab7a
TP		 4046static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4047{
4048 uint8_t test_result = DP_TEST_ACK;
4049 return test_result;
4050}
4051
4052static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4053{
4054 uint8_t test_result = DP_TEST_NAK;
4055 return test_result;
4056}
4057
4058static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4059{
c5d5ab7a
TP		 4060 uint8_t test_result = DP_TEST_NAK;
4061 return test_result;
4062}
4063
4064static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4065{
c5d5ab7a
TP		 4066 uint8_t test_result = DP_TEST_NAK;
4067 return test_result;
4068}
4069
4070static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4071{
4072 uint8_t response = DP_TEST_NAK;
4073 uint8_t rxdata = 0;
4074 int status = 0;
4075
4076 intel_dp->compliance_test_type = 0;
4077 intel_dp->aux.i2c_nack_count = 0;
4078 intel_dp->aux.i2c_defer_count = 0;
4079
4080 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4081 if (status <= 0) {
4082 DRM_DEBUG_KMS("Could not read test request from sink\n");
4083 goto update_status;
4084 }
4085
4086 switch (rxdata) {
4087 case DP_TEST_LINK_TRAINING:
4088 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4089 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4090 response = intel_dp_autotest_link_training(intel_dp);
4091 break;
4092 case DP_TEST_LINK_VIDEO_PATTERN:
4093 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4094 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4095 response = intel_dp_autotest_video_pattern(intel_dp);
4096 break;
4097 case DP_TEST_LINK_EDID_READ:
4098 DRM_DEBUG_KMS("EDID test requested\n");
4099 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4100 response = intel_dp_autotest_edid(intel_dp);
4101 break;
4102 case DP_TEST_LINK_PHY_TEST_PATTERN:
4103 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4104 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4105 response = intel_dp_autotest_phy_pattern(intel_dp);
4106 break;
4107 default:
4108 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4109 break;
4110 }
4111
4112update_status:
4113 status = drm_dp_dpcd_write(&intel_dp->aux,
4114 DP_TEST_RESPONSE,
4115 &response, 1);
4116 if (status <= 0)
4117 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4118}
4119
0e32b39c
DA		 4120static int
4121intel_dp_check_mst_status(struct intel_dp *intel_dp)
4122{
4123 bool bret;
4124
4125 if (intel_dp->is_mst) {
4126 u8 esi[16] = { 0 };
4127 int ret = 0;
4128 int retry;
4129 bool handled;
4130 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4131go_again:
4132 if (bret == true) {
4133
4134 /* check link status - esi[10] = 0x200c */
4135 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4136 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4137 intel_dp_start_link_train(intel_dp);
4138 intel_dp_complete_link_train(intel_dp);
4139 intel_dp_stop_link_train(intel_dp);
4140 }
4141
6f34cc39 4142 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4143 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4144
4145 if (handled) {
4146 for (retry = 0; retry < 3; retry++) {
4147 int wret;
4148 wret = drm_dp_dpcd_write(&intel_dp->aux,
4149 DP_SINK_COUNT_ESI+1,
4150 &esi[1], 3);
4151 if (wret == 3) {
4152 break;
4153 }
4154 }
4155
4156 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4157 if (bret == true) {
6f34cc39 4158 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4159 goto go_again;
4160 }
4161 } else
4162 ret = 0;
4163
4164 return ret;
4165 } else {
4166 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4167 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4168 intel_dp->is_mst = false;
4169 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4170 /* send a hotplug event */
4171 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4172 }
4173 }
4174 return -EINVAL;
4175}
4176
a4fc5ed6
KP		 4177/*
4178 * According to DP spec
4179 * 5.1.2:
4180 * 1. Read DPCD
4181 * 2. Configure link according to Receiver Capabilities
4182 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4183 * 4. Check link status on receipt of hot-plug interrupt
4184 */
a5146200 4185static void
ea5b213a 4186intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4187{
5b215bcf 4188 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4189 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4190 u8 sink_irq_vector;
93f62dad 4191 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4192
5b215bcf
DA		 4193 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4194
da63a9f2 4195 if (!intel_encoder->connectors_active)
d2b996ac 4196 return;
59cd09e1 4197
da63a9f2 4198 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4199 return;
4200
1a125d8a
ID		 4201 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4202 return;
4203
92fd8fd1 4204 /* Try to read receiver status if the link appears to be up */
93f62dad 4205 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4206 return;
4207 }
4208
92fd8fd1 4209 /* Now read the DPCD to see if it's actually running */
26d61aad 4210 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4211 return;
4212 }
4213
a60f0e38
JB		 4214 /* Try to read the source of the interrupt */
4215 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4216 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4217 /* Clear interrupt source */
9d1a1031
JN		 4218 drm_dp_dpcd_writeb(&intel_dp->aux,
4219 DP_DEVICE_SERVICE_IRQ_VECTOR,
4220 sink_irq_vector);
a60f0e38
JB		 4221
4222 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4223 intel_dp_handle_test_request(intel_dp);
4224 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4225 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4226 }
4227
1ffdff13 4228 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4229 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4230 intel_encoder->base.name);
33a34e4e
JB		 4231 intel_dp_start_link_train(intel_dp);
4232 intel_dp_complete_link_train(intel_dp);
3ab9c637 4233 intel_dp_stop_link_train(intel_dp);
33a34e4e 4234 }
a4fc5ed6 4235}
a4fc5ed6 4236
caf9ab24 4237/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4238static enum drm_connector_status
26d61aad 4239intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4240{
caf9ab24 4241 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4242 uint8_t type;
4243
4244 if (!intel_dp_get_dpcd(intel_dp))
4245 return connector_status_disconnected;
4246
4247 /* if there's no downstream port, we're done */
4248 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4249 return connector_status_connected;
caf9ab24
AJ		 4250
4251 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4252 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4253 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4254 uint8_t reg;
9d1a1031
JN		 4255
4256 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4257 &reg, 1) < 0)
caf9ab24 4258 return connector_status_unknown;
9d1a1031 4259
23235177
AJ		 4260 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4261 : connector_status_disconnected;
caf9ab24
AJ		 4262 }
4263
4264 /* If no HPD, poke DDC gently */
0b99836f 4265 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4266 return connector_status_connected;
caf9ab24
AJ		 4267
4268 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4269 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4270 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4271 if (type == DP_DS_PORT_TYPE_VGA ||
4272 type == DP_DS_PORT_TYPE_NON_EDID)
4273 return connector_status_unknown;
4274 } else {
4275 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4276 DP_DWN_STRM_PORT_TYPE_MASK;
4277 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4278 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4279 return connector_status_unknown;
4280 }
caf9ab24
AJ		 4281
4282 /* Anything else is out of spec, warn and ignore */
4283 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4284 return connector_status_disconnected;
71ba9000
AJ		 4285}
4286
d410b56d
CW		 4287static enum drm_connector_status
4288edp_detect(struct intel_dp *intel_dp)
4289{
4290 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4291 enum drm_connector_status status;
4292
4293 status = intel_panel_detect(dev);
4294 if (status == connector_status_unknown)
4295 status = connector_status_connected;
4296
4297 return status;
4298}
4299
5eb08b69 4300static enum drm_connector_status
a9756bb5 4301ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4302{
30add22d 4303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4306
1b469639
DL		 4307 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4308 return connector_status_disconnected;
4309
26d61aad 4310 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4311}
4312
2a592bec
DA		 4313static int g4x_digital_port_connected(struct drm_device *dev,
4314 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4315{
a4fc5ed6 4316 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4317 uint32_t bit;
5eb08b69 4318
232a6ee9
TP		 4319 if (IS_VALLEYVIEW(dev)) {
4320 switch (intel_dig_port->port) {
4321 case PORT_B:
4322 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4323 break;
4324 case PORT_C:
4325 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4326 break;
4327 case PORT_D:
4328 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4329 break;
4330 default:
2a592bec 4331 return -EINVAL;
232a6ee9
TP		 4332 }
4333 } else {
4334 switch (intel_dig_port->port) {
4335 case PORT_B:
4336 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4337 break;
4338 case PORT_C:
4339 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4340 break;
4341 case PORT_D:
4342 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4343 break;
4344 default:
2a592bec 4345 return -EINVAL;
232a6ee9 4346 }
a4fc5ed6
KP		 4347 }
4348
10f76a38 4349 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4350 return 0;
4351 return 1;
4352}
4353
4354static enum drm_connector_status
4355g4x_dp_detect(struct intel_dp *intel_dp)
4356{
4357 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4359 int ret;
4360
4361 /* Can't disconnect eDP, but you can close the lid... */
4362 if (is_edp(intel_dp)) {
4363 enum drm_connector_status status;
4364
4365 status = intel_panel_detect(dev);
4366 if (status == connector_status_unknown)
4367 status = connector_status_connected;
4368 return status;
4369 }
4370
4371 ret = g4x_digital_port_connected(dev, intel_dig_port);
4372 if (ret == -EINVAL)
4373 return connector_status_unknown;
4374 else if (ret == 0)
a4fc5ed6
KP		 4375 return connector_status_disconnected;
4376
26d61aad 4377 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4378}
4379
8c241fef 4380static struct edid *
beb60608 4381intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4382{
beb60608 4383 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4384
9cd300e0
JN		 4385 /* use cached edid if we have one */
4386 if (intel_connector->edid) {
9cd300e0
JN		 4387 /* invalid edid */
4388 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4389 return NULL;
4390
55e9edeb 4391 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4392 } else
4393 return drm_get_edid(&intel_connector->base,
4394 &intel_dp->aux.ddc);
4395}
8c241fef 4396
beb60608
CW		 4397static void
4398intel_dp_set_edid(struct intel_dp *intel_dp)
4399{
4400 struct intel_connector *intel_connector = intel_dp->attached_connector;
4401 struct edid *edid;
8c241fef 4402
beb60608
CW		 4403 edid = intel_dp_get_edid(intel_dp);
4404 intel_connector->detect_edid = edid;
4405
4406 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4407 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4408 else
4409 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4410}
4411
beb60608
CW		 4412static void
4413intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4414{
beb60608 4415 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4416
beb60608
CW		 4417 kfree(intel_connector->detect_edid);
4418 intel_connector->detect_edid = NULL;
9cd300e0 4419
beb60608
CW		 4420 intel_dp->has_audio = false;
4421}
d6f24d0f 4422
beb60608
CW		 4423static enum intel_display_power_domain
4424intel_dp_power_get(struct intel_dp *dp)
4425{
4426 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4427 enum intel_display_power_domain power_domain;
4428
4429 power_domain = intel_display_port_power_domain(encoder);
4430 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4431
4432 return power_domain;
4433}
d6f24d0f 4434
beb60608
CW		 4435static void
4436intel_dp_power_put(struct intel_dp *dp,
4437 enum intel_display_power_domain power_domain)
4438{
4439 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4440 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4441}
4442
a9756bb5
ZW		 4443static enum drm_connector_status
4444intel_dp_detect(struct drm_connector *connector, bool force)
4445{
4446 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4447 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4448 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4449 struct drm_device *dev = connector->dev;
a9756bb5 4450 enum drm_connector_status status;
671dedd2 4451 enum intel_display_power_domain power_domain;
0e32b39c 4452 bool ret;
a9756bb5 4453
164c8598 4454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4455 connector->base.id, connector->name);
beb60608 4456 intel_dp_unset_edid(intel_dp);
164c8598 4457
0e32b39c
DA		 4458 if (intel_dp->is_mst) {
4459 /* MST devices are disconnected from a monitor POV */
4460 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4461 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4462 return connector_status_disconnected;
0e32b39c
DA		 4463 }
4464
beb60608 4465 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4466
d410b56d
CW		 4467 /* Can't disconnect eDP, but you can close the lid... */
4468 if (is_edp(intel_dp))
4469 status = edp_detect(intel_dp);
4470 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4471 status = ironlake_dp_detect(intel_dp);
4472 else
4473 status = g4x_dp_detect(intel_dp);
4474 if (status != connector_status_connected)
c8c8fb33 4475 goto out;
a9756bb5 4476
0d198328
AJ		 4477 intel_dp_probe_oui(intel_dp);
4478
0e32b39c
DA		 4479 ret = intel_dp_probe_mst(intel_dp);
4480 if (ret) {
4481 /* if we are in MST mode then this connector
4482 won't appear connected or have anything with EDID on it */
4483 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4484 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4485 status = connector_status_disconnected;
4486 goto out;
4487 }
4488
beb60608 4489 intel_dp_set_edid(intel_dp);
a9756bb5 4490
d63885da
PZ		 4491 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4492 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4493 status = connector_status_connected;
4494
4495out:
beb60608 4496 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4497 return status;
a4fc5ed6
KP		 4498}
4499
beb60608
CW		 4500static void
4501intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4502{
df0e9248 4503 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4504 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4505 enum intel_display_power_domain power_domain;
a4fc5ed6 4506
beb60608
CW		 4507 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4508 connector->base.id, connector->name);
4509 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4510
beb60608
CW		 4511 if (connector->status != connector_status_connected)
4512 return;
671dedd2 4513
beb60608
CW		 4514 power_domain = intel_dp_power_get(intel_dp);
4515
4516 intel_dp_set_edid(intel_dp);
4517
4518 intel_dp_power_put(intel_dp, power_domain);
4519
4520 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4521 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4522}
4523
4524static int intel_dp_get_modes(struct drm_connector *connector)
4525{
4526 struct intel_connector *intel_connector = to_intel_connector(connector);
4527 struct edid *edid;
4528
4529 edid = intel_connector->detect_edid;
4530 if (edid) {
4531 int ret = intel_connector_update_modes(connector, edid);
4532 if (ret)
4533 return ret;
4534 }
32f9d658 4535
f8779fda 4536 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4537 if (is_edp(intel_attached_dp(connector)) &&
4538 intel_connector->panel.fixed_mode) {
f8779fda 4539 struct drm_display_mode *mode;
beb60608
CW		 4540
4541 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4542 intel_connector->panel.fixed_mode);
f8779fda 4543 if (mode) {
32f9d658
ZW		 4544 drm_mode_probed_add(connector, mode);
4545 return 1;
4546 }
4547 }
beb60608 4548
32f9d658 4549 return 0;
a4fc5ed6
KP		 4550}
4551
1aad7ac0
CW		 4552static bool
4553intel_dp_detect_audio(struct drm_connector *connector)
4554{
1aad7ac0 4555 bool has_audio = false;
beb60608 4556 struct edid *edid;
1aad7ac0 4557
beb60608
CW		 4558 edid = to_intel_connector(connector)->detect_edid;
4559 if (edid)
1aad7ac0 4560 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4561
1aad7ac0
CW		 4562 return has_audio;
4563}
4564
f684960e
CW		 4565static int
4566intel_dp_set_property(struct drm_connector *connector,
4567 struct drm_property *property,
4568 uint64_t val)
4569{
e953fd7b 4570 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4571 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4572 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4573 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4574 int ret;
4575
662595df 4576 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4577 if (ret)
4578 return ret;
4579
3f43c48d 4580 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4581 int i = val;
4582 bool has_audio;
4583
4584 if (i == intel_dp->force_audio)
f684960e
CW		 4585 return 0;
4586
1aad7ac0 4587 intel_dp->force_audio = i;
f684960e 4588
c3e5f67b 4589 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4590 has_audio = intel_dp_detect_audio(connector);
4591 else
c3e5f67b 4592 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4593
4594 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4595 return 0;
4596
1aad7ac0 4597 intel_dp->has_audio = has_audio;
f684960e
CW		 4598 goto done;
4599 }
4600
e953fd7b 4601 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4602 bool old_auto = intel_dp->color_range_auto;
4603 uint32_t old_range = intel_dp->color_range;
4604
55bc60db
VS		 4605 switch (val) {
4606 case INTEL_BROADCAST_RGB_AUTO:
4607 intel_dp->color_range_auto = true;
4608 break;
4609 case INTEL_BROADCAST_RGB_FULL:
4610 intel_dp->color_range_auto = false;
4611 intel_dp->color_range = 0;
4612 break;
4613 case INTEL_BROADCAST_RGB_LIMITED:
4614 intel_dp->color_range_auto = false;
4615 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4616 break;
4617 default:
4618 return -EINVAL;
4619 }
ae4edb80
DV		 4620
4621 if (old_auto == intel_dp->color_range_auto &&
4622 old_range == intel_dp->color_range)
4623 return 0;
4624
e953fd7b
CW		 4625 goto done;
4626 }
4627
53b41837
YN		 4628 if (is_edp(intel_dp) &&
4629 property == connector->dev->mode_config.scaling_mode_property) {
4630 if (val == DRM_MODE_SCALE_NONE) {
4631 DRM_DEBUG_KMS("no scaling not supported\n");
4632 return -EINVAL;
4633 }
4634
4635 if (intel_connector->panel.fitting_mode == val) {
4636 /* the eDP scaling property is not changed */
4637 return 0;
4638 }
4639 intel_connector->panel.fitting_mode = val;
4640
4641 goto done;
4642 }
4643
f684960e
CW		 4644 return -EINVAL;
4645
4646done:
c0c36b94
CW		 4647 if (intel_encoder->base.crtc)
4648 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4649
4650 return 0;
4651}
4652
a4fc5ed6 4653static void
73845adf 4654intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4655{
1d508706 4656 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4657
10e972d3 4658 kfree(intel_connector->detect_edid);
beb60608 4659
9cd300e0
JN		 4660 if (!IS_ERR_OR_NULL(intel_connector->edid))
4661 kfree(intel_connector->edid);
4662
acd8db10
PZ		 4663 /* Can't call is_edp() since the encoder may have been destroyed
4664 * already. */
4665 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4666 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4667
a4fc5ed6 4668 drm_connector_cleanup(connector);
55f78c43 4669 kfree(connector);
a4fc5ed6
KP		 4670}
4671
00c09d70 4672void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4673{
da63a9f2
PZ		 4674 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4675 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4676
4f71d0cb 4677 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4678 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4679 if (is_edp(intel_dp)) {
4680 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4681 /*
4682 * vdd might still be enabled do to the delayed vdd off.
4683 * Make sure vdd is actually turned off here.
4684 */
773538e8 4685 pps_lock(intel_dp);
4be73780 4686 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4687 pps_unlock(intel_dp);
4688
01527b31
CT		 4689 if (intel_dp->edp_notifier.notifier_call) {
4690 unregister_reboot_notifier(&intel_dp->edp_notifier);
4691 intel_dp->edp_notifier.notifier_call = NULL;
4692 }
bd943159 4693 }
c8bd0e49 4694 drm_encoder_cleanup(encoder);
da63a9f2 4695 kfree(intel_dig_port);
24d05927
DV		 4696}
4697
07f9cd0b
ID		 4698static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4699{
4700 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4701
4702 if (!is_edp(intel_dp))
4703 return;
4704
951468f3
VS		 4705 /*
4706 * vdd might still be enabled do to the delayed vdd off.
4707 * Make sure vdd is actually turned off here.
4708 */
afa4e53a 4709 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4710 pps_lock(intel_dp);
07f9cd0b 4711 edp_panel_vdd_off_sync(intel_dp);
773538e8 4712 pps_unlock(intel_dp);
07f9cd0b
ID		 4713}
4714
49e6bc51
VS		 4715static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4716{
4717 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4718 struct drm_device *dev = intel_dig_port->base.base.dev;
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4720 enum intel_display_power_domain power_domain;
4721
4722 lockdep_assert_held(&dev_priv->pps_mutex);
4723
4724 if (!edp_have_panel_vdd(intel_dp))
4725 return;
4726
4727 /*
4728 * The VDD bit needs a power domain reference, so if the bit is
4729 * already enabled when we boot or resume, grab this reference and
4730 * schedule a vdd off, so we don't hold on to the reference
4731 * indefinitely.
4732 */
4733 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4734 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4735 intel_display_power_get(dev_priv, power_domain);
4736
4737 edp_panel_vdd_schedule_off(intel_dp);
4738}
4739
6d93c0c4
ID		 4740static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4741{
49e6bc51
VS		 4742 struct intel_dp *intel_dp;
4743
4744 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4745 return;
4746
4747 intel_dp = enc_to_intel_dp(encoder);
4748
4749 pps_lock(intel_dp);
4750
4751 /*
4752 * Read out the current power sequencer assignment,
4753 * in case the BIOS did something with it.
4754 */
4755 if (IS_VALLEYVIEW(encoder->dev))
4756 vlv_initial_power_sequencer_setup(intel_dp);
4757
4758 intel_edp_panel_vdd_sanitize(intel_dp);
4759
4760 pps_unlock(intel_dp);
6d93c0c4
ID		 4761}
4762
a4fc5ed6 4763static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4764 .dpms = intel_connector_dpms,
a4fc5ed6 4765 .detect = intel_dp_detect,
beb60608 4766 .force = intel_dp_force,
a4fc5ed6 4767 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4768 .set_property = intel_dp_set_property,
2545e4a6 4769 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4770 .destroy = intel_dp_connector_destroy,
c6f95f27 4771 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4772 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4773};
4774
4775static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4776 .get_modes = intel_dp_get_modes,
4777 .mode_valid = intel_dp_mode_valid,
df0e9248 4778 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4779};
4780
a4fc5ed6 4781static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4782 .reset = intel_dp_encoder_reset,
24d05927 4783 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4784};
4785
0e32b39c 4786void
21d40d37 4787intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4788{
0e32b39c 4789 return;
c8110e52 4790}
6207937d 4791
b2c5c181 4792enum irqreturn
13cf5504
DA		 4793intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4794{
4795 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4796 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4797 struct drm_device *dev = intel_dig_port->base.base.dev;
4798 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4799 enum intel_display_power_domain power_domain;
b2c5c181 4800 enum irqreturn ret = IRQ_NONE;
1c767b33 4801
0e32b39c
DA		 4802 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4803 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4804
7a7f84cc
VS		 4805 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4806 /*
4807 * vdd off can generate a long pulse on eDP which
4808 * would require vdd on to handle it, and thus we
4809 * would end up in an endless cycle of
4810 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4811 */
4812 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4813 port_name(intel_dig_port->port));
a8b3d52f 4814 return IRQ_HANDLED;
7a7f84cc
VS		 4815 }
4816
26fbb774
VS		 4817 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4818 port_name(intel_dig_port->port),
0e32b39c 4819 long_hpd ? "long" : "short");
13cf5504 4820
1c767b33
ID		 4821 power_domain = intel_display_port_power_domain(intel_encoder);
4822 intel_display_power_get(dev_priv, power_domain);
4823
0e32b39c 4824 if (long_hpd) {
2a592bec
DA		 4825
4826 if (HAS_PCH_SPLIT(dev)) {
4827 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4828 goto mst_fail;
4829 } else {
4830 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4831 goto mst_fail;
4832 }
0e32b39c
DA		 4833
4834 if (!intel_dp_get_dpcd(intel_dp)) {
4835 goto mst_fail;
4836 }
4837
4838 intel_dp_probe_oui(intel_dp);
4839
4840 if (!intel_dp_probe_mst(intel_dp))
4841 goto mst_fail;
4842
4843 } else {
4844 if (intel_dp->is_mst) {
1c767b33 4845 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4846 goto mst_fail;
4847 }
4848
4849 if (!intel_dp->is_mst) {
4850 /*
4851 * we'll check the link status via the normal hot plug path later -
4852 * but for short hpds we should check it now
4853 */
5b215bcf 4854 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4855 intel_dp_check_link_status(intel_dp);
5b215bcf 4856 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4857 }
4858 }
b2c5c181
DV		 4859
4860 ret = IRQ_HANDLED;
4861
1c767b33 4862 goto put_power;
0e32b39c
DA		 4863mst_fail:
4864 /* if we were in MST mode, and device is not there get out of MST mode */
4865 if (intel_dp->is_mst) {
4866 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4867 intel_dp->is_mst = false;
4868 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4869 }
1c767b33
ID		 4870put_power:
4871 intel_display_power_put(dev_priv, power_domain);
4872
4873 return ret;
13cf5504
DA		 4874}
4875
e3421a18
ZW		 4876/* Return which DP Port should be selected for Transcoder DP control */
4877int
0206e353 4878intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4879{
4880 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4881 struct intel_encoder *intel_encoder;
4882 struct intel_dp *intel_dp;
e3421a18 4883
fa90ecef
PZ		 4884 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4885 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4886
fa90ecef
PZ		 4887 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4888 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4889 return intel_dp->output_reg;
e3421a18 4890 }
ea5b213a 4891
e3421a18
ZW		 4892 return -1;
4893}
4894
36e83a18 4895/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4896bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4897{
4898 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4899 union child_device_config *p_child;
36e83a18 4900 int i;
5d8a7752
VS		 4901 static const short port_mapping[] = {
4902 [PORT_B] = PORT_IDPB,
4903 [PORT_C] = PORT_IDPC,
4904 [PORT_D] = PORT_IDPD,
4905 };
36e83a18 4906
3b32a35b
VS		 4907 if (port == PORT_A)
4908 return true;
4909
41aa3448 4910 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4911 return false;
4912
41aa3448
RV		 4913 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4914 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4915
5d8a7752 4916 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4917 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4918 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4919 return true;
4920 }
4921 return false;
4922}
4923
0e32b39c 4924void
f684960e
CW		 4925intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4926{
53b41837
YN		 4927 struct intel_connector *intel_connector = to_intel_connector(connector);
4928
3f43c48d 4929 intel_attach_force_audio_property(connector);
e953fd7b 4930 intel_attach_broadcast_rgb_property(connector);
55bc60db 4931 intel_dp->color_range_auto = true;
53b41837
YN		 4932
4933 if (is_edp(intel_dp)) {
4934 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4935 drm_object_attach_property(
4936 &connector->base,
53b41837 4937 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4938 DRM_MODE_SCALE_ASPECT);
4939 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4940 }
f684960e
CW		 4941}
4942
dada1a9f
ID		 4943static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4944{
4945 intel_dp->last_power_cycle = jiffies;
4946 intel_dp->last_power_on = jiffies;
4947 intel_dp->last_backlight_off = jiffies;
4948}
4949
67a54566
DV		 4950static void
4951intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4952 struct intel_dp *intel_dp)
67a54566
DV		 4953{
4954 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4955 struct edp_power_seq cur, vbt, spec,
4956 *final = &intel_dp->pps_delays;
67a54566 4957 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4958 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4959
e39b999a
VS		 4960 lockdep_assert_held(&dev_priv->pps_mutex);
4961
81ddbc69
VS		 4962 /* already initialized? */
4963 if (final->t11_t12 != 0)
4964 return;
4965
453c5420 4966 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4967 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4968 pp_on_reg = PCH_PP_ON_DELAYS;
4969 pp_off_reg = PCH_PP_OFF_DELAYS;
4970 pp_div_reg = PCH_PP_DIVISOR;
4971 } else {
bf13e81b
JN		 4972 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4973
4974 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4975 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4976 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4977 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4978 }
67a54566
DV		 4979
4980 /* Workaround: Need to write PP_CONTROL with the unlock key as
4981 * the very first thing. */
453c5420 4982 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4983 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4984
453c5420
JB		 4985 pp_on = I915_READ(pp_on_reg);
4986 pp_off = I915_READ(pp_off_reg);
4987 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4988
4989 /* Pull timing values out of registers */
4990 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4991 PANEL_POWER_UP_DELAY_SHIFT;
4992
4993 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4994 PANEL_LIGHT_ON_DELAY_SHIFT;
4995
4996 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4997 PANEL_LIGHT_OFF_DELAY_SHIFT;
4998
4999 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5000 PANEL_POWER_DOWN_DELAY_SHIFT;
5001
5002 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5003 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5004
5005 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5006 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5007
41aa3448 5008 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5009
5010 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5011 * our hw here, which are all in 100usec. */
5012 spec.t1_t3 = 210 * 10;
5013 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5014 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5015 spec.t10 = 500 * 10;
5016 /* This one is special and actually in units of 100ms, but zero
5017 * based in the hw (so we need to add 100 ms). But the sw vbt
5018 * table multiplies it with 1000 to make it in units of 100usec,
5019 * too. */
5020 spec.t11_t12 = (510 + 100) * 10;
5021
5022 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5023 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5024
5025 /* Use the max of the register settings and vbt. If both are
5026 * unset, fall back to the spec limits. */
36b5f425 5027#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5028 spec.field : \
5029 max(cur.field, vbt.field))
5030 assign_final(t1_t3);
5031 assign_final(t8);
5032 assign_final(t9);
5033 assign_final(t10);
5034 assign_final(t11_t12);
5035#undef assign_final
5036
36b5f425 5037#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5038 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5039 intel_dp->backlight_on_delay = get_delay(t8);
5040 intel_dp->backlight_off_delay = get_delay(t9);
5041 intel_dp->panel_power_down_delay = get_delay(t10);
5042 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5043#undef get_delay
5044
f30d26e4
JN		 5045 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5046 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5047 intel_dp->panel_power_cycle_delay);
5048
5049 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5050 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5051}
5052
5053static void
5054intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5055 struct intel_dp *intel_dp)
f30d26e4
JN		 5056{
5057 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5058 u32 pp_on, pp_off, pp_div, port_sel = 0;
5059 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5060 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 5061 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5062 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5063
e39b999a 5064 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 5065
5066 if (HAS_PCH_SPLIT(dev)) {
5067 pp_on_reg = PCH_PP_ON_DELAYS;
5068 pp_off_reg = PCH_PP_OFF_DELAYS;
5069 pp_div_reg = PCH_PP_DIVISOR;
5070 } else {
bf13e81b
JN		 5071 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5072
5073 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5074 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5075 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5076 }
5077
b2f19d1a
PZ		 5078 /*
5079 * And finally store the new values in the power sequencer. The
5080 * backlight delays are set to 1 because we do manual waits on them. For
5081 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5082 * we'll end up waiting for the backlight off delay twice: once when we
5083 * do the manual sleep, and once when we disable the panel and wait for
5084 * the PP_STATUS bit to become zero.
5085 */
f30d26e4 5086 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5087 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5088 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5089 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5090 /* Compute the divisor for the pp clock, simply match the Bspec
5091 * formula. */
453c5420 5092 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 5093 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 5094 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5095
5096 /* Haswell doesn't have any port selection bits for the panel
5097 * power sequencer any more. */
bc7d38a4 5098 if (IS_VALLEYVIEW(dev)) {
ad933b56 5099 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5100 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5101 if (port == PORT_A)
a24c144c 5102 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5103 else
a24c144c 5104 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5105 }
5106
453c5420
JB		 5107 pp_on |= port_sel;
5108
5109 I915_WRITE(pp_on_reg, pp_on);
5110 I915_WRITE(pp_off_reg, pp_off);
5111 I915_WRITE(pp_div_reg, pp_div);
67a54566 5112
67a54566 5113 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5114 I915_READ(pp_on_reg),
5115 I915_READ(pp_off_reg),
5116 I915_READ(pp_div_reg));
f684960e
CW		 5117}
5118
b33a2815
VK		 5119/**
5120 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5121 * @dev: DRM device
5122 * @refresh_rate: RR to be programmed
5123 *
5124 * This function gets called when refresh rate (RR) has to be changed from
5125 * one frequency to another. Switches can be between high and low RR
5126 * supported by the panel or to any other RR based on media playback (in
5127 * this case, RR value needs to be passed from user space).
5128 *
5129 * The caller of this function needs to take a lock on dev_priv->drrs.
5130 */
96178eeb 5131static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5132{
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 struct intel_encoder *encoder;
96178eeb
VK		 5135 struct intel_digital_port *dig_port = NULL;
5136 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5137 struct intel_crtc_state *config = NULL;
439d7ac0 5138 struct intel_crtc *intel_crtc = NULL;
439d7ac0 5139 u32 reg, val;
96178eeb 5140 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5141
5142 if (refresh_rate <= 0) {
5143 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5144 return;
5145 }
5146
96178eeb
VK		 5147 if (intel_dp == NULL) {
5148 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5149 return;
5150 }
5151
1fcc9d1c 5152 /*
e4d59f6b
RV		 5153 * FIXME: This needs proper synchronization with psr state for some
5154 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5155 */
439d7ac0 5156
96178eeb
VK		 5157 dig_port = dp_to_dig_port(intel_dp);
5158 encoder = &dig_port->base;
723f9aab 5159 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5160
5161 if (!intel_crtc) {
5162 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5163 return;
5164 }
5165
6e3c9717 5166 config = intel_crtc->config;
439d7ac0 5167
96178eeb 5168 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5169 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5170 return;
5171 }
5172
96178eeb
VK		 5173 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5174 refresh_rate)
439d7ac0
PB		 5175 index = DRRS_LOW_RR;
5176
96178eeb 5177 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5178 DRM_DEBUG_KMS(
5179 "DRRS requested for previously set RR...ignoring\n");
5180 return;
5181 }
5182
5183 if (!intel_crtc->active) {
5184 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5185 return;
5186 }
5187
44395bfe 5188 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5189 switch (index) {
5190 case DRRS_HIGH_RR:
5191 intel_dp_set_m_n(intel_crtc, M1_N1);
5192 break;
5193 case DRRS_LOW_RR:
5194 intel_dp_set_m_n(intel_crtc, M2_N2);
5195 break;
5196 case DRRS_MAX_RR:
5197 default:
5198 DRM_ERROR("Unsupported refreshrate type\n");
5199 }
5200 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 5201 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 5202 val = I915_READ(reg);
a4c30b1d 5203
439d7ac0 5204 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5205 if (IS_VALLEYVIEW(dev))
5206 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5207 else
5208 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5209 } else {
6fa7aec1
VK		 5210 if (IS_VALLEYVIEW(dev))
5211 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5212 else
5213 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5214 }
5215 I915_WRITE(reg, val);
5216 }
5217
4e9ac947
VK		 5218 dev_priv->drrs.refresh_rate_type = index;
5219
5220 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5221}
5222
b33a2815
VK		 5223/**
5224 * intel_edp_drrs_enable - init drrs struct if supported
5225 * @intel_dp: DP struct
5226 *
5227 * Initializes frontbuffer_bits and drrs.dp
5228 */
c395578e
VK		 5229void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5230{
5231 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5232 struct drm_i915_private *dev_priv = dev->dev_private;
5233 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5234 struct drm_crtc *crtc = dig_port->base.base.crtc;
5235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236
5237 if (!intel_crtc->config->has_drrs) {
5238 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5239 return;
5240 }
5241
5242 mutex_lock(&dev_priv->drrs.mutex);
5243 if (WARN_ON(dev_priv->drrs.dp)) {
5244 DRM_ERROR("DRRS already enabled\n");
5245 goto unlock;
5246 }
5247
5248 dev_priv->drrs.busy_frontbuffer_bits = 0;
5249
5250 dev_priv->drrs.dp = intel_dp;
5251
5252unlock:
5253 mutex_unlock(&dev_priv->drrs.mutex);
5254}
5255
b33a2815
VK		 5256/**
5257 * intel_edp_drrs_disable - Disable DRRS
5258 * @intel_dp: DP struct
5259 *
5260 */
c395578e
VK		 5261void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5262{
5263 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5266 struct drm_crtc *crtc = dig_port->base.base.crtc;
5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268
5269 if (!intel_crtc->config->has_drrs)
5270 return;
5271
5272 mutex_lock(&dev_priv->drrs.mutex);
5273 if (!dev_priv->drrs.dp) {
5274 mutex_unlock(&dev_priv->drrs.mutex);
5275 return;
5276 }
5277
5278 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5279 intel_dp_set_drrs_state(dev_priv->dev,
5280 intel_dp->attached_connector->panel.
5281 fixed_mode->vrefresh);
5282
5283 dev_priv->drrs.dp = NULL;
5284 mutex_unlock(&dev_priv->drrs.mutex);
5285
5286 cancel_delayed_work_sync(&dev_priv->drrs.work);
5287}
5288
4e9ac947
VK		 5289static void intel_edp_drrs_downclock_work(struct work_struct *work)
5290{
5291 struct drm_i915_private *dev_priv =
5292 container_of(work, typeof(*dev_priv), drrs.work.work);
5293 struct intel_dp *intel_dp;
5294
5295 mutex_lock(&dev_priv->drrs.mutex);
5296
5297 intel_dp = dev_priv->drrs.dp;
5298
5299 if (!intel_dp)
5300 goto unlock;
5301
439d7ac0 5302 /*
4e9ac947
VK		 5303 * The delayed work can race with an invalidate hence we need to
5304 * recheck.
439d7ac0
PB		 5305 */
5306
4e9ac947
VK		 5307 if (dev_priv->drrs.busy_frontbuffer_bits)
5308 goto unlock;
439d7ac0 5309
4e9ac947
VK		 5310 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5311 intel_dp_set_drrs_state(dev_priv->dev,
5312 intel_dp->attached_connector->panel.
5313 downclock_mode->vrefresh);
439d7ac0 5314
4e9ac947 5315unlock:
4e9ac947 5316 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5317}
5318
b33a2815
VK		 5319/**
5320 * intel_edp_drrs_invalidate - Invalidate DRRS
5321 * @dev: DRM device
5322 * @frontbuffer_bits: frontbuffer plane tracking bits
5323 *
5324 * When there is a disturbance on screen (due to cursor movement/time
5325 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5326 * high RR.
5327 *
5328 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5329 */
a93fad0f
VK		 5330void intel_edp_drrs_invalidate(struct drm_device *dev,
5331 unsigned frontbuffer_bits)
5332{
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 struct drm_crtc *crtc;
5335 enum pipe pipe;
5336
9da7d693 5337 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5338 return;
5339
88f933a8 5340 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5341
a93fad0f 5342 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5343 if (!dev_priv->drrs.dp) {
5344 mutex_unlock(&dev_priv->drrs.mutex);
5345 return;
5346 }
5347
a93fad0f
VK		 5348 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5349 pipe = to_intel_crtc(crtc)->pipe;
5350
5351 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
a93fad0f
VK		 5352 intel_dp_set_drrs_state(dev_priv->dev,
5353 dev_priv->drrs.dp->attached_connector->panel.
5354 fixed_mode->vrefresh);
5355 }
5356
5357 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5358
5359 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5360 mutex_unlock(&dev_priv->drrs.mutex);
5361}
5362
b33a2815
VK		 5363/**
5364 * intel_edp_drrs_flush - Flush DRRS
5365 * @dev: DRM device
5366 * @frontbuffer_bits: frontbuffer plane tracking bits
5367 *
5368 * When there is no movement on screen, DRRS work can be scheduled.
5369 * This DRRS work is responsible for setting relevant registers after a
5370 * timeout of 1 second.
5371 *
5372 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5373 */
a93fad0f
VK		 5374void intel_edp_drrs_flush(struct drm_device *dev,
5375 unsigned frontbuffer_bits)
5376{
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 struct drm_crtc *crtc;
5379 enum pipe pipe;
5380
9da7d693 5381 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5382 return;
5383
88f933a8 5384 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5385
a93fad0f 5386 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5387 if (!dev_priv->drrs.dp) {
5388 mutex_unlock(&dev_priv->drrs.mutex);
5389 return;
5390 }
5391
a93fad0f
VK		 5392 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5393 pipe = to_intel_crtc(crtc)->pipe;
5394 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5395
a93fad0f
VK		 5396 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5397 !dev_priv->drrs.busy_frontbuffer_bits)
5398 schedule_delayed_work(&dev_priv->drrs.work,
5399 msecs_to_jiffies(1000));
5400 mutex_unlock(&dev_priv->drrs.mutex);
5401}
5402
b33a2815
VK		 5403/**
5404 * DOC: Display Refresh Rate Switching (DRRS)
5405 *
5406 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5407 * which enables swtching between low and high refresh rates,
5408 * dynamically, based on the usage scenario. This feature is applicable
5409 * for internal panels.
5410 *
5411 * Indication that the panel supports DRRS is given by the panel EDID, which
5412 * would list multiple refresh rates for one resolution.
5413 *
5414 * DRRS is of 2 types - static and seamless.
5415 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5416 * (may appear as a blink on screen) and is used in dock-undock scenario.
5417 * Seamless DRRS involves changing RR without any visual effect to the user
5418 * and can be used during normal system usage. This is done by programming
5419 * certain registers.
5420 *
5421 * Support for static/seamless DRRS may be indicated in the VBT based on
5422 * inputs from the panel spec.
5423 *
5424 * DRRS saves power by switching to low RR based on usage scenarios.
5425 *
5426 * eDP DRRS:-
5427 * The implementation is based on frontbuffer tracking implementation.
5428 * When there is a disturbance on the screen triggered by user activity or a
5429 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5430 * When there is no movement on screen, after a timeout of 1 second, a switch
5431 * to low RR is made.
5432 * For integration with frontbuffer tracking code,
5433 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5434 *
5435 * DRRS can be further extended to support other internal panels and also
5436 * the scenario of video playback wherein RR is set based on the rate
5437 * requested by userspace.
5438 */
5439
5440/**
5441 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5442 * @intel_connector: eDP connector
5443 * @fixed_mode: preferred mode of panel
5444 *
5445 * This function is called only once at driver load to initialize basic
5446 * DRRS stuff.
5447 *
5448 * Returns:
5449 * Downclock mode if panel supports it, else return NULL.
5450 * DRRS support is determined by the presence of downclock mode (apart
5451 * from VBT setting).
5452 */
4f9db5b5 5453static struct drm_display_mode *
96178eeb
VK		 5454intel_dp_drrs_init(struct intel_connector *intel_connector,
5455 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5456{
5457 struct drm_connector *connector = &intel_connector->base;
96178eeb 5458 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 struct drm_display_mode *downclock_mode = NULL;
5461
9da7d693
DV		 5462 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5463 mutex_init(&dev_priv->drrs.mutex);
5464
4f9db5b5
PB		 5465 if (INTEL_INFO(dev)->gen <= 6) {
5466 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5467 return NULL;
5468 }
5469
5470 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5471 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5472 return NULL;
5473 }
5474
5475 downclock_mode = intel_find_panel_downclock
5476 (dev, fixed_mode, connector);
5477
5478 if (!downclock_mode) {
a1d26342 5479 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5480 return NULL;
5481 }
5482
96178eeb 5483 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5484
96178eeb 5485 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5486 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5487 return downclock_mode;
5488}
5489
ed92f0b2 5490static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5491 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5492{
5493 struct drm_connector *connector = &intel_connector->base;
5494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5495 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5496 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5499 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5500 bool has_dpcd;
5501 struct drm_display_mode *scan;
5502 struct edid *edid;
6517d273 5503 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5504
5505 if (!is_edp(intel_dp))
5506 return true;
5507
49e6bc51
VS		 5508 pps_lock(intel_dp);
5509 intel_edp_panel_vdd_sanitize(intel_dp);
5510 pps_unlock(intel_dp);
63635217 5511
ed92f0b2 5512 /* Cache DPCD and EDID for edp. */
ed92f0b2 5513 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5514
5515 if (has_dpcd) {
5516 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5517 dev_priv->no_aux_handshake =
5518 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5519 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5520 } else {
5521 /* if this fails, presume the device is a ghost */
5522 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5523 return false;
5524 }
5525
5526 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5527 pps_lock(intel_dp);
36b5f425 5528 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5529 pps_unlock(intel_dp);
ed92f0b2 5530
060c8778 5531 mutex_lock(&dev->mode_config.mutex);
0b99836f 5532 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5533 if (edid) {
5534 if (drm_add_edid_modes(connector, edid)) {
5535 drm_mode_connector_update_edid_property(connector,
5536 edid);
5537 drm_edid_to_eld(connector, edid);
5538 } else {
5539 kfree(edid);
5540 edid = ERR_PTR(-EINVAL);
5541 }
5542 } else {
5543 edid = ERR_PTR(-ENOENT);
5544 }
5545 intel_connector->edid = edid;
5546
5547 /* prefer fixed mode from EDID if available */
5548 list_for_each_entry(scan, &connector->probed_modes, head) {
5549 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5550 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5551 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5552 intel_connector, fixed_mode);
ed92f0b2
PZ		 5553 break;
5554 }
5555 }
5556
5557 /* fallback to VBT if available for eDP */
5558 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5559 fixed_mode = drm_mode_duplicate(dev,
5560 dev_priv->vbt.lfp_lvds_vbt_mode);
5561 if (fixed_mode)
5562 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5563 }
060c8778 5564 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5565
01527b31
CT		 5566 if (IS_VALLEYVIEW(dev)) {
5567 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5568 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5569
5570 /*
5571 * Figure out the current pipe for the initial backlight setup.
5572 * If the current pipe isn't valid, try the PPS pipe, and if that
5573 * fails just assume pipe A.
5574 */
5575 if (IS_CHERRYVIEW(dev))
5576 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5577 else
5578 pipe = PORT_TO_PIPE(intel_dp->DP);
5579
5580 if (pipe != PIPE_A && pipe != PIPE_B)
5581 pipe = intel_dp->pps_pipe;
5582
5583 if (pipe != PIPE_A && pipe != PIPE_B)
5584 pipe = PIPE_A;
5585
5586 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5587 pipe_name(pipe));
01527b31
CT		 5588 }
5589
4f9db5b5 5590 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5591 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5592 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5593
5594 return true;
5595}
5596
16c25533 5597bool
f0fec3f2
PZ		 5598intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5599 struct intel_connector *intel_connector)
a4fc5ed6 5600{
f0fec3f2
PZ		 5601 struct drm_connector *connector = &intel_connector->base;
5602 struct intel_dp *intel_dp = &intel_dig_port->dp;
5603 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5604 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5605 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5606 enum port port = intel_dig_port->port;
0b99836f 5607 int type;
a4fc5ed6 5608
a4a5d2f8
VS		 5609 intel_dp->pps_pipe = INVALID_PIPE;
5610
ec5b01dd 5611 /* intel_dp vfuncs */
b6b5e383
DL		 5612 if (INTEL_INFO(dev)->gen >= 9)
5613 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5614 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5615 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5616 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5617 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5618 else if (HAS_PCH_SPLIT(dev))
5619 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5620 else
5621 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5622
b9ca5fad
DL		 5623 if (INTEL_INFO(dev)->gen >= 9)
5624 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5625 else
5626 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5627
0767935e
DV		 5628 /* Preserve the current hw state. */
5629 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5630 intel_dp->attached_connector = intel_connector;
3d3dc149 5631
3b32a35b 5632 if (intel_dp_is_edp(dev, port))
b329530c 5633 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5634 else
5635 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5636
f7d24902
ID		 5637 /*
5638 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5639 * for DP the encoder type can be set by the caller to
5640 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5641 */
5642 if (type == DRM_MODE_CONNECTOR_eDP)
5643 intel_encoder->type = INTEL_OUTPUT_EDP;
5644
c17ed5b5
VS		 5645 /* eDP only on port B and/or C on vlv/chv */
5646 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5647 port != PORT_B && port != PORT_C))
5648 return false;
5649
e7281eab
ID		 5650 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5651 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5652 port_name(port));
5653
b329530c 5654 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5655 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5656
a4fc5ed6
KP		 5657 connector->interlace_allowed = true;
5658 connector->doublescan_allowed = 0;
5659
f0fec3f2 5660 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5661 edp_panel_vdd_work);
a4fc5ed6 5662
df0e9248 5663 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5664 drm_connector_register(connector);
a4fc5ed6 5665
affa9354 5666 if (HAS_DDI(dev))
bcbc889b
PZ		 5667 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5668 else
5669 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5670 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5671
0b99836f 5672 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5673 switch (port) {
5674 case PORT_A:
1d843f9d 5675 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5676 break;
5677 case PORT_B:
1d843f9d 5678 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5679 break;
5680 case PORT_C:
1d843f9d 5681 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5682 break;
5683 case PORT_D:
1d843f9d 5684 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5685 break;
5686 default:
ad1c0b19 5687 BUG();
5eb08b69
ZW		 5688 }
5689
dada1a9f 5690 if (is_edp(intel_dp)) {
773538e8 5691 pps_lock(intel_dp);
1e74a324
VS		 5692 intel_dp_init_panel_power_timestamps(intel_dp);
5693 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5694 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5695 else
36b5f425 5696 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5697 pps_unlock(intel_dp);
dada1a9f 5698 }
0095e6dc 5699
9d1a1031 5700 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5701
0e32b39c 5702 /* init MST on ports that can support it */
c86ea3d0 5703 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5704 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5705 intel_dp_mst_encoder_init(intel_dig_port,
5706 intel_connector->base.base.id);
0e32b39c
DA		 5707 }
5708 }
5709
36b5f425 5710 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5711 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5712 if (is_edp(intel_dp)) {
5713 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5714 /*
5715 * vdd might still be enabled do to the delayed vdd off.
5716 * Make sure vdd is actually turned off here.
5717 */
773538e8 5718 pps_lock(intel_dp);
4be73780 5719 edp_panel_vdd_off_sync(intel_dp);
773538e8 5720 pps_unlock(intel_dp);
15b1d171 5721 }
34ea3d38 5722 drm_connector_unregister(connector);
b2f246a8 5723 drm_connector_cleanup(connector);
16c25533 5724 return false;
b2f246a8 5725 }
32f9d658 5726
f684960e
CW		 5727 intel_dp_add_properties(intel_dp, connector);
5728
a4fc5ed6
KP		 5729 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5730 * 0xd. Failure to do so will result in spurious interrupts being
5731 * generated on the port when a cable is not attached.
5732 */
5733 if (IS_G4X(dev) && !IS_GM45(dev)) {
5734 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5735 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5736 }
16c25533 5737
aa7471d2
JN		 5738 i915_debugfs_connector_add(connector);
5739
16c25533 5740 return true;
a4fc5ed6 5741}
f0fec3f2
PZ		 5742
5743void
5744intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5745{
13cf5504 5746 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5747 struct intel_digital_port *intel_dig_port;
5748 struct intel_encoder *intel_encoder;
5749 struct drm_encoder *encoder;
5750 struct intel_connector *intel_connector;
5751
b14c5679 5752 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5753 if (!intel_dig_port)
5754 return;
5755
08d9bc92 5756 intel_connector = intel_connector_alloc();
f0fec3f2
PZ		 5757 if (!intel_connector) {
5758 kfree(intel_dig_port);
5759 return;
5760 }
5761
5762 intel_encoder = &intel_dig_port->base;
5763 encoder = &intel_encoder->base;
5764
5765 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5766 DRM_MODE_ENCODER_TMDS);
5767
5bfe2ac0 5768 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5769 intel_encoder->disable = intel_disable_dp;
00c09d70 5770 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5771 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5772 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5773 if (IS_CHERRYVIEW(dev)) {
9197c88b 5774 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5775 intel_encoder->pre_enable = chv_pre_enable_dp;
5776 intel_encoder->enable = vlv_enable_dp;
580d3811 5777 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5778 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5779 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5780 intel_encoder->pre_enable = vlv_pre_enable_dp;
5781 intel_encoder->enable = vlv_enable_dp;
49277c31 5782 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5783 } else {
ecff4f3b
JN		 5784 intel_encoder->pre_enable = g4x_pre_enable_dp;
5785 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5786 if (INTEL_INFO(dev)->gen >= 5)
5787 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5788 }
f0fec3f2 5789
174edf1f 5790 intel_dig_port->port = port;
f0fec3f2
PZ		 5791 intel_dig_port->dp.output_reg = output_reg;
5792
00c09d70 5793 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5794 if (IS_CHERRYVIEW(dev)) {
5795 if (port == PORT_D)
5796 intel_encoder->crtc_mask = 1 << 2;
5797 else
5798 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5799 } else {
5800 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5801 }
bc079e8b 5802 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5803 intel_encoder->hot_plug = intel_dp_hot_plug;
5804
13cf5504
DA		 5805 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5806 dev_priv->hpd_irq_port[port] = intel_dig_port;
5807
15b1d171
PZ		 5808 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5809 drm_encoder_cleanup(encoder);
5810 kfree(intel_dig_port);
b2f246a8 5811 kfree(intel_connector);
15b1d171 5812 }
f0fec3f2 5813}
0e32b39c
DA		 5814
5815void intel_dp_mst_suspend(struct drm_device *dev)
5816{
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5818 int i;
5819
5820 /* disable MST */
5821 for (i = 0; i < I915_MAX_PORTS; i++) {
5822 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5823 if (!intel_dig_port)
5824 continue;
5825
5826 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5827 if (!intel_dig_port->dp.can_mst)
5828 continue;
5829 if (intel_dig_port->dp.is_mst)
5830 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5831 }
5832 }
5833}
5834
5835void intel_dp_mst_resume(struct drm_device *dev)
5836{
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 int i;
5839
5840 for (i = 0; i < I915_MAX_PORTS; i++) {
5841 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5842 if (!intel_dig_port)
5843 continue;
5844 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5845 int ret;
5846
5847 if (!intel_dig_port->dp.can_mst)
5848 continue;
5849
5850 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5851 if (ret != 0) {
5852 intel_dp_check_mst_status(&intel_dig_port->dp);
5853 }
5854 }
5855 }
5856}
ubuntu-bionic-kernel mirror