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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
a4fc5ed6 KP |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "drm_crtc.h" | |
34 | #include "drm_crtc_helper.h" | |
d6f24d0f | 35 | #include "drm_edid.h" |
a4fc5ed6 KP |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
ab2c0672 | 39 | #include "drm_dp_helper.h" |
a4fc5ed6 | 40 | |
a2006cf5 | 41 | #define DP_RECEIVER_CAP_SIZE 0xf |
a4fc5ed6 KP |
42 | #define DP_LINK_STATUS_SIZE 6 |
43 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
44 | ||
45 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
46 | ||
ea5b213a CW |
47 | struct intel_dp { |
48 | struct intel_encoder base; | |
a4fc5ed6 KP |
49 | uint32_t output_reg; |
50 | uint32_t DP; | |
51 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 52 | bool has_audio; |
c3e5f67b | 53 | enum hdmi_force_audio force_audio; |
e953fd7b | 54 | uint32_t color_range; |
d2b996ac | 55 | int dpms_mode; |
a4fc5ed6 KP |
56 | uint8_t link_bw; |
57 | uint8_t lane_count; | |
a2006cf5 | 58 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
a4fc5ed6 KP |
59 | struct i2c_adapter adapter; |
60 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 61 | bool is_pch_edp; |
33a34e4e | 62 | uint8_t train_set[4]; |
f01eca2e KP |
63 | int panel_power_up_delay; |
64 | int panel_power_down_delay; | |
65 | int panel_power_cycle_delay; | |
66 | int backlight_on_delay; | |
67 | int backlight_off_delay; | |
d15456de | 68 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
bd943159 KP |
69 | struct delayed_work panel_vdd_work; |
70 | bool want_panel_vdd; | |
d6f24d0f JB |
71 | struct edid *edid; /* cached EDID for eDP */ |
72 | int edid_mode_count; | |
a4fc5ed6 KP |
73 | }; |
74 | ||
cfcb0fc9 JB |
75 | /** |
76 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
77 | * @intel_dp: DP struct | |
78 | * | |
79 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
80 | * will return true, and false otherwise. | |
81 | */ | |
82 | static bool is_edp(struct intel_dp *intel_dp) | |
83 | { | |
84 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
85 | } | |
86 | ||
87 | /** | |
88 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
89 | * @intel_dp: DP struct | |
90 | * | |
91 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
92 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
93 | * may need FDI resources for a given DP output or not. | |
94 | */ | |
95 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
96 | { | |
97 | return intel_dp->is_pch_edp; | |
98 | } | |
99 | ||
1c95822a AJ |
100 | /** |
101 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? | |
102 | * @intel_dp: DP struct | |
103 | * | |
104 | * Returns true if the given DP struct corresponds to a CPU eDP port. | |
105 | */ | |
106 | static bool is_cpu_edp(struct intel_dp *intel_dp) | |
107 | { | |
108 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); | |
109 | } | |
110 | ||
ea5b213a CW |
111 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
112 | { | |
4ef69c7a | 113 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 114 | } |
a4fc5ed6 | 115 | |
df0e9248 CW |
116 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
117 | { | |
118 | return container_of(intel_attached_encoder(connector), | |
119 | struct intel_dp, base); | |
120 | } | |
121 | ||
814948ad JB |
122 | /** |
123 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
124 | * @encoder: DRM encoder | |
125 | * | |
126 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
127 | * by intel_display.c. | |
128 | */ | |
129 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
130 | { | |
131 | struct intel_dp *intel_dp; | |
132 | ||
133 | if (!encoder) | |
134 | return false; | |
135 | ||
136 | intel_dp = enc_to_intel_dp(encoder); | |
137 | ||
138 | return is_pch_edp(intel_dp); | |
139 | } | |
140 | ||
33a34e4e JB |
141 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
142 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 143 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 144 | |
32f9d658 | 145 | void |
0206e353 | 146 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
ea5b213a | 147 | int *lane_num, int *link_bw) |
32f9d658 | 148 | { |
ea5b213a | 149 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 150 | |
ea5b213a CW |
151 | *lane_num = intel_dp->lane_count; |
152 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 153 | *link_bw = 162000; |
ea5b213a | 154 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
155 | *link_bw = 270000; |
156 | } | |
157 | ||
94bf2ced DV |
158 | int |
159 | intel_edp_target_clock(struct intel_encoder *intel_encoder, | |
160 | struct drm_display_mode *mode) | |
161 | { | |
162 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); | |
163 | ||
164 | if (intel_dp->panel_fixed_mode) | |
165 | return intel_dp->panel_fixed_mode->clock; | |
166 | else | |
167 | return mode->clock; | |
168 | } | |
169 | ||
a4fc5ed6 | 170 | static int |
ea5b213a | 171 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 172 | { |
9a10f401 KP |
173 | int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; |
174 | switch (max_lane_count) { | |
175 | case 1: case 2: case 4: | |
176 | break; | |
177 | default: | |
178 | max_lane_count = 4; | |
a4fc5ed6 KP |
179 | } |
180 | return max_lane_count; | |
181 | } | |
182 | ||
183 | static int | |
ea5b213a | 184 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 185 | { |
7183dc29 | 186 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
187 | |
188 | switch (max_link_bw) { | |
189 | case DP_LINK_BW_1_62: | |
190 | case DP_LINK_BW_2_7: | |
191 | break; | |
192 | default: | |
193 | max_link_bw = DP_LINK_BW_1_62; | |
194 | break; | |
195 | } | |
196 | return max_link_bw; | |
197 | } | |
198 | ||
199 | static int | |
200 | intel_dp_link_clock(uint8_t link_bw) | |
201 | { | |
202 | if (link_bw == DP_LINK_BW_2_7) | |
203 | return 270000; | |
204 | else | |
205 | return 162000; | |
206 | } | |
207 | ||
cd9dde44 AJ |
208 | /* |
209 | * The units on the numbers in the next two are... bizarre. Examples will | |
210 | * make it clearer; this one parallels an example in the eDP spec. | |
211 | * | |
212 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
213 | * | |
214 | * 270000 * 1 * 8 / 10 == 216000 | |
215 | * | |
216 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
217 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
218 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
219 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
220 | * | |
221 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
222 | * get the result in decakilobits instead of kilobits. | |
223 | */ | |
224 | ||
a4fc5ed6 | 225 | static int |
c898261c | 226 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 227 | { |
cd9dde44 | 228 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
229 | } |
230 | ||
fe27d53e DA |
231 | static int |
232 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
233 | { | |
234 | return (max_link_clock * max_lanes * 8) / 10; | |
235 | } | |
236 | ||
c4867936 DV |
237 | static bool |
238 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, | |
239 | struct drm_display_mode *mode, | |
cb1793ce | 240 | bool adjust_mode) |
c4867936 DV |
241 | { |
242 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); | |
243 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
244 | int max_rate, mode_rate; | |
245 | ||
246 | mode_rate = intel_dp_link_required(mode->clock, 24); | |
247 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
248 | ||
249 | if (mode_rate > max_rate) { | |
250 | mode_rate = intel_dp_link_required(mode->clock, 18); | |
251 | if (mode_rate > max_rate) | |
252 | return false; | |
253 | ||
cb1793ce DV |
254 | if (adjust_mode) |
255 | mode->private_flags | |
c4867936 DV |
256 | |= INTEL_MODE_DP_FORCE_6BPC; |
257 | ||
258 | return true; | |
259 | } | |
260 | ||
261 | return true; | |
262 | } | |
263 | ||
a4fc5ed6 KP |
264 | static int |
265 | intel_dp_mode_valid(struct drm_connector *connector, | |
266 | struct drm_display_mode *mode) | |
267 | { | |
df0e9248 | 268 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
a4fc5ed6 | 269 | |
d15456de KP |
270 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
271 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) | |
7de56f43 ZY |
272 | return MODE_PANEL; |
273 | ||
d15456de | 274 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
7de56f43 ZY |
275 | return MODE_PANEL; |
276 | } | |
277 | ||
cb1793ce | 278 | if (!intel_dp_adjust_dithering(intel_dp, mode, false)) |
c4867936 | 279 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
280 | |
281 | if (mode->clock < 10000) | |
282 | return MODE_CLOCK_LOW; | |
283 | ||
0af78a2b DV |
284 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
285 | return MODE_H_ILLEGAL; | |
286 | ||
a4fc5ed6 KP |
287 | return MODE_OK; |
288 | } | |
289 | ||
290 | static uint32_t | |
291 | pack_aux(uint8_t *src, int src_bytes) | |
292 | { | |
293 | int i; | |
294 | uint32_t v = 0; | |
295 | ||
296 | if (src_bytes > 4) | |
297 | src_bytes = 4; | |
298 | for (i = 0; i < src_bytes; i++) | |
299 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
300 | return v; | |
301 | } | |
302 | ||
303 | static void | |
304 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
305 | { | |
306 | int i; | |
307 | if (dst_bytes > 4) | |
308 | dst_bytes = 4; | |
309 | for (i = 0; i < dst_bytes; i++) | |
310 | dst[i] = src >> ((3-i) * 8); | |
311 | } | |
312 | ||
fb0f8fbf KP |
313 | /* hrawclock is 1/4 the FSB frequency */ |
314 | static int | |
315 | intel_hrawclk(struct drm_device *dev) | |
316 | { | |
317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
318 | uint32_t clkcfg; | |
319 | ||
320 | clkcfg = I915_READ(CLKCFG); | |
321 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
322 | case CLKCFG_FSB_400: | |
323 | return 100; | |
324 | case CLKCFG_FSB_533: | |
325 | return 133; | |
326 | case CLKCFG_FSB_667: | |
327 | return 166; | |
328 | case CLKCFG_FSB_800: | |
329 | return 200; | |
330 | case CLKCFG_FSB_1067: | |
331 | return 266; | |
332 | case CLKCFG_FSB_1333: | |
333 | return 333; | |
334 | /* these two are just a guess; one of them might be right */ | |
335 | case CLKCFG_FSB_1600: | |
336 | case CLKCFG_FSB_1600_ALT: | |
337 | return 400; | |
338 | default: | |
339 | return 133; | |
340 | } | |
341 | } | |
342 | ||
ebf33b18 KP |
343 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
344 | { | |
345 | struct drm_device *dev = intel_dp->base.base.dev; | |
346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
347 | ||
348 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; | |
349 | } | |
350 | ||
351 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
352 | { | |
353 | struct drm_device *dev = intel_dp->base.base.dev; | |
354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
355 | ||
356 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; | |
357 | } | |
358 | ||
9b984dae KP |
359 | static void |
360 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
361 | { | |
362 | struct drm_device *dev = intel_dp->base.base.dev; | |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 364 | |
9b984dae KP |
365 | if (!is_edp(intel_dp)) |
366 | return; | |
ebf33b18 | 367 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
368 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
369 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
ebf33b18 | 370 | I915_READ(PCH_PP_STATUS), |
9b984dae KP |
371 | I915_READ(PCH_PP_CONTROL)); |
372 | } | |
373 | } | |
374 | ||
a4fc5ed6 | 375 | static int |
ea5b213a | 376 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
377 | uint8_t *send, int send_bytes, |
378 | uint8_t *recv, int recv_size) | |
379 | { | |
ea5b213a | 380 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 381 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
382 | struct drm_i915_private *dev_priv = dev->dev_private; |
383 | uint32_t ch_ctl = output_reg + 0x10; | |
384 | uint32_t ch_data = ch_ctl + 4; | |
385 | int i; | |
386 | int recv_bytes; | |
a4fc5ed6 | 387 | uint32_t status; |
fb0f8fbf | 388 | uint32_t aux_clock_divider; |
6b4e0a93 | 389 | int try, precharge; |
a4fc5ed6 | 390 | |
9b984dae | 391 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 392 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
393 | * and would like to run at 2MHz. So, take the |
394 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
395 | * |
396 | * Note that PCH attached eDP panels should use a 125MHz input | |
397 | * clock divider. | |
a4fc5ed6 | 398 | */ |
1c95822a | 399 | if (is_cpu_edp(intel_dp)) { |
1a2eb460 KP |
400 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
401 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ | |
e3421a18 ZW |
402 | else |
403 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
404 | } else if (HAS_PCH_SPLIT(dev)) | |
6919132e | 405 | aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
406 | else |
407 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
408 | ||
6b4e0a93 DV |
409 | if (IS_GEN6(dev)) |
410 | precharge = 3; | |
411 | else | |
412 | precharge = 5; | |
413 | ||
11bee43e JB |
414 | /* Try to wait for any previous AUX channel activity */ |
415 | for (try = 0; try < 3; try++) { | |
416 | status = I915_READ(ch_ctl); | |
417 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
418 | break; | |
419 | msleep(1); | |
420 | } | |
421 | ||
422 | if (try == 3) { | |
423 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
424 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
425 | return -EBUSY; |
426 | } | |
427 | ||
fb0f8fbf KP |
428 | /* Must try at least 3 times according to DP spec */ |
429 | for (try = 0; try < 5; try++) { | |
430 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
431 | for (i = 0; i < send_bytes; i += 4) |
432 | I915_WRITE(ch_data + i, | |
433 | pack_aux(send + i, send_bytes - i)); | |
0206e353 | 434 | |
fb0f8fbf | 435 | /* Send the command and wait for it to complete */ |
4f7f7b7e CW |
436 | I915_WRITE(ch_ctl, |
437 | DP_AUX_CH_CTL_SEND_BUSY | | |
438 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
439 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
440 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
441 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
442 | DP_AUX_CH_CTL_DONE | | |
443 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
444 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 445 | for (;;) { |
fb0f8fbf KP |
446 | status = I915_READ(ch_ctl); |
447 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
448 | break; | |
4f7f7b7e | 449 | udelay(100); |
fb0f8fbf | 450 | } |
0206e353 | 451 | |
fb0f8fbf | 452 | /* Clear done status and any errors */ |
4f7f7b7e CW |
453 | I915_WRITE(ch_ctl, |
454 | status | | |
455 | DP_AUX_CH_CTL_DONE | | |
456 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
457 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
d7e96fea AJ |
458 | |
459 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
460 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
461 | continue; | |
4f7f7b7e | 462 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
463 | break; |
464 | } | |
465 | ||
a4fc5ed6 | 466 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 467 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 468 | return -EBUSY; |
a4fc5ed6 KP |
469 | } |
470 | ||
471 | /* Check for timeout or receive error. | |
472 | * Timeouts occur when the sink is not connected | |
473 | */ | |
a5b3da54 | 474 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 475 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
476 | return -EIO; |
477 | } | |
1ae8c0a5 KP |
478 | |
479 | /* Timeouts occur when the device isn't connected, so they're | |
480 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 481 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 482 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 483 | return -ETIMEDOUT; |
a4fc5ed6 KP |
484 | } |
485 | ||
486 | /* Unload any bytes sent back from the other side */ | |
487 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
488 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
489 | if (recv_bytes > recv_size) |
490 | recv_bytes = recv_size; | |
0206e353 | 491 | |
4f7f7b7e CW |
492 | for (i = 0; i < recv_bytes; i += 4) |
493 | unpack_aux(I915_READ(ch_data + i), | |
494 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
495 | |
496 | return recv_bytes; | |
497 | } | |
498 | ||
499 | /* Write data to the aux channel in native mode */ | |
500 | static int | |
ea5b213a | 501 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
502 | uint16_t address, uint8_t *send, int send_bytes) |
503 | { | |
504 | int ret; | |
505 | uint8_t msg[20]; | |
506 | int msg_bytes; | |
507 | uint8_t ack; | |
508 | ||
9b984dae | 509 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
510 | if (send_bytes > 16) |
511 | return -1; | |
512 | msg[0] = AUX_NATIVE_WRITE << 4; | |
513 | msg[1] = address >> 8; | |
eebc863e | 514 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
515 | msg[3] = send_bytes - 1; |
516 | memcpy(&msg[4], send, send_bytes); | |
517 | msg_bytes = send_bytes + 4; | |
518 | for (;;) { | |
ea5b213a | 519 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
520 | if (ret < 0) |
521 | return ret; | |
522 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
523 | break; | |
524 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
525 | udelay(100); | |
526 | else | |
a5b3da54 | 527 | return -EIO; |
a4fc5ed6 KP |
528 | } |
529 | return send_bytes; | |
530 | } | |
531 | ||
532 | /* Write a single byte to the aux channel in native mode */ | |
533 | static int | |
ea5b213a | 534 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
535 | uint16_t address, uint8_t byte) |
536 | { | |
ea5b213a | 537 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
538 | } |
539 | ||
540 | /* read bytes from a native aux channel */ | |
541 | static int | |
ea5b213a | 542 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
543 | uint16_t address, uint8_t *recv, int recv_bytes) |
544 | { | |
545 | uint8_t msg[4]; | |
546 | int msg_bytes; | |
547 | uint8_t reply[20]; | |
548 | int reply_bytes; | |
549 | uint8_t ack; | |
550 | int ret; | |
551 | ||
9b984dae | 552 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
553 | msg[0] = AUX_NATIVE_READ << 4; |
554 | msg[1] = address >> 8; | |
555 | msg[2] = address & 0xff; | |
556 | msg[3] = recv_bytes - 1; | |
557 | ||
558 | msg_bytes = 4; | |
559 | reply_bytes = recv_bytes + 1; | |
560 | ||
561 | for (;;) { | |
ea5b213a | 562 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 563 | reply, reply_bytes); |
a5b3da54 KP |
564 | if (ret == 0) |
565 | return -EPROTO; | |
566 | if (ret < 0) | |
a4fc5ed6 KP |
567 | return ret; |
568 | ack = reply[0]; | |
569 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
570 | memcpy(recv, reply + 1, ret - 1); | |
571 | return ret - 1; | |
572 | } | |
573 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
574 | udelay(100); | |
575 | else | |
a5b3da54 | 576 | return -EIO; |
a4fc5ed6 KP |
577 | } |
578 | } | |
579 | ||
580 | static int | |
ab2c0672 DA |
581 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
582 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 583 | { |
ab2c0672 | 584 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
585 | struct intel_dp *intel_dp = container_of(adapter, |
586 | struct intel_dp, | |
587 | adapter); | |
ab2c0672 DA |
588 | uint16_t address = algo_data->address; |
589 | uint8_t msg[5]; | |
590 | uint8_t reply[2]; | |
8316f337 | 591 | unsigned retry; |
ab2c0672 DA |
592 | int msg_bytes; |
593 | int reply_bytes; | |
594 | int ret; | |
595 | ||
9b984dae | 596 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
597 | /* Set up the command byte */ |
598 | if (mode & MODE_I2C_READ) | |
599 | msg[0] = AUX_I2C_READ << 4; | |
600 | else | |
601 | msg[0] = AUX_I2C_WRITE << 4; | |
602 | ||
603 | if (!(mode & MODE_I2C_STOP)) | |
604 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 605 | |
ab2c0672 DA |
606 | msg[1] = address >> 8; |
607 | msg[2] = address; | |
608 | ||
609 | switch (mode) { | |
610 | case MODE_I2C_WRITE: | |
611 | msg[3] = 0; | |
612 | msg[4] = write_byte; | |
613 | msg_bytes = 5; | |
614 | reply_bytes = 1; | |
615 | break; | |
616 | case MODE_I2C_READ: | |
617 | msg[3] = 0; | |
618 | msg_bytes = 4; | |
619 | reply_bytes = 2; | |
620 | break; | |
621 | default: | |
622 | msg_bytes = 3; | |
623 | reply_bytes = 1; | |
624 | break; | |
625 | } | |
626 | ||
8316f337 DF |
627 | for (retry = 0; retry < 5; retry++) { |
628 | ret = intel_dp_aux_ch(intel_dp, | |
629 | msg, msg_bytes, | |
630 | reply, reply_bytes); | |
ab2c0672 | 631 | if (ret < 0) { |
3ff99164 | 632 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
633 | return ret; |
634 | } | |
8316f337 DF |
635 | |
636 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
637 | case AUX_NATIVE_REPLY_ACK: | |
638 | /* I2C-over-AUX Reply field is only valid | |
639 | * when paired with AUX ACK. | |
640 | */ | |
641 | break; | |
642 | case AUX_NATIVE_REPLY_NACK: | |
643 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
644 | return -EREMOTEIO; | |
645 | case AUX_NATIVE_REPLY_DEFER: | |
646 | udelay(100); | |
647 | continue; | |
648 | default: | |
649 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
650 | reply[0]); | |
651 | return -EREMOTEIO; | |
652 | } | |
653 | ||
ab2c0672 DA |
654 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
655 | case AUX_I2C_REPLY_ACK: | |
656 | if (mode == MODE_I2C_READ) { | |
657 | *read_byte = reply[1]; | |
658 | } | |
659 | return reply_bytes - 1; | |
660 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 661 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
662 | return -EREMOTEIO; |
663 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 664 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
665 | udelay(100); |
666 | break; | |
667 | default: | |
8316f337 | 668 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
669 | return -EREMOTEIO; |
670 | } | |
671 | } | |
8316f337 DF |
672 | |
673 | DRM_ERROR("too many retries, giving up\n"); | |
674 | return -EREMOTEIO; | |
a4fc5ed6 KP |
675 | } |
676 | ||
0b5c541b | 677 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
bd943159 | 678 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
0b5c541b | 679 | |
a4fc5ed6 | 680 | static int |
ea5b213a | 681 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 682 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 683 | { |
0b5c541b KP |
684 | int ret; |
685 | ||
d54e9d28 | 686 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
687 | intel_dp->algo.running = false; |
688 | intel_dp->algo.address = 0; | |
689 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
690 | ||
0206e353 | 691 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
692 | intel_dp->adapter.owner = THIS_MODULE; |
693 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 694 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
695 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
696 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
697 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
698 | ||
0b5c541b KP |
699 | ironlake_edp_panel_vdd_on(intel_dp); |
700 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 701 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 702 | return ret; |
a4fc5ed6 KP |
703 | } |
704 | ||
705 | static bool | |
e811f5ae LP |
706 | intel_dp_mode_fixup(struct drm_encoder *encoder, |
707 | const struct drm_display_mode *mode, | |
a4fc5ed6 KP |
708 | struct drm_display_mode *adjusted_mode) |
709 | { | |
0d3a1bee | 710 | struct drm_device *dev = encoder->dev; |
ea5b213a | 711 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 712 | int lane_count, clock; |
ea5b213a CW |
713 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
714 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
083f9560 | 715 | int bpp, mode_rate; |
a4fc5ed6 KP |
716 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
717 | ||
d15456de KP |
718 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
719 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); | |
1d8e1c75 CW |
720 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
721 | mode, adjusted_mode); | |
0d3a1bee ZY |
722 | } |
723 | ||
cb1793ce | 724 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
725 | return false; |
726 | ||
083f9560 DV |
727 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
728 | "max bw %02x pixel clock %iKHz\n", | |
71244653 | 729 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
083f9560 | 730 | |
cb1793ce | 731 | if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) |
c4867936 DV |
732 | return false; |
733 | ||
734 | bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; | |
71244653 | 735 | mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); |
c4867936 | 736 | |
2514bc51 JB |
737 | for (clock = 0; clock <= max_clock; clock++) { |
738 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { | |
fe27d53e | 739 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 740 | |
083f9560 | 741 | if (mode_rate <= link_avail) { |
ea5b213a CW |
742 | intel_dp->link_bw = bws[clock]; |
743 | intel_dp->lane_count = lane_count; | |
744 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
083f9560 DV |
745 | DRM_DEBUG_KMS("DP link bw %02x lane " |
746 | "count %d clock %d bpp %d\n", | |
ea5b213a | 747 | intel_dp->link_bw, intel_dp->lane_count, |
083f9560 DV |
748 | adjusted_mode->clock, bpp); |
749 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", | |
750 | mode_rate, link_avail); | |
a4fc5ed6 KP |
751 | return true; |
752 | } | |
753 | } | |
754 | } | |
fe27d53e | 755 | |
a4fc5ed6 KP |
756 | return false; |
757 | } | |
758 | ||
759 | struct intel_dp_m_n { | |
760 | uint32_t tu; | |
761 | uint32_t gmch_m; | |
762 | uint32_t gmch_n; | |
763 | uint32_t link_m; | |
764 | uint32_t link_n; | |
765 | }; | |
766 | ||
767 | static void | |
768 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
769 | { | |
770 | while (*num > 0xffffff || *den > 0xffffff) { | |
771 | *num >>= 1; | |
772 | *den >>= 1; | |
773 | } | |
774 | } | |
775 | ||
776 | static void | |
36e83a18 | 777 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
778 | int nlanes, |
779 | int pixel_clock, | |
780 | int link_clock, | |
781 | struct intel_dp_m_n *m_n) | |
782 | { | |
783 | m_n->tu = 64; | |
36e83a18 | 784 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
785 | m_n->gmch_n = link_clock * nlanes; |
786 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
787 | m_n->link_m = pixel_clock; | |
788 | m_n->link_n = link_clock; | |
789 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
790 | } | |
791 | ||
792 | void | |
793 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
794 | struct drm_display_mode *adjusted_mode) | |
795 | { | |
796 | struct drm_device *dev = crtc->dev; | |
6c2b7c12 | 797 | struct intel_encoder *encoder; |
a4fc5ed6 KP |
798 | struct drm_i915_private *dev_priv = dev->dev_private; |
799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 800 | int lane_count = 4; |
a4fc5ed6 | 801 | struct intel_dp_m_n m_n; |
9db4a9c7 | 802 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
803 | |
804 | /* | |
21d40d37 | 805 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 806 | */ |
6c2b7c12 DV |
807 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
808 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
a4fc5ed6 | 809 | |
9a10f401 KP |
810 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
811 | intel_dp->base.type == INTEL_OUTPUT_EDP) | |
812 | { | |
ea5b213a | 813 | lane_count = intel_dp->lane_count; |
51190667 | 814 | break; |
a4fc5ed6 KP |
815 | } |
816 | } | |
817 | ||
818 | /* | |
819 | * Compute the GMCH and Link ratios. The '3' here is | |
820 | * the number of bytes_per_pixel post-LUT, which we always | |
821 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
822 | */ | |
858fa035 | 823 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
824 | mode->clock, adjusted_mode->clock, &m_n); |
825 | ||
c619eed4 | 826 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
827 | I915_WRITE(TRANSDATA_M1(pipe), |
828 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
829 | m_n.gmch_m); | |
830 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
831 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
832 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 833 | } else { |
9db4a9c7 JB |
834 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
835 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
836 | m_n.gmch_m); | |
837 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
838 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
839 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
840 | } |
841 | } | |
842 | ||
f01eca2e KP |
843 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
844 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
845 | ||
a4fc5ed6 KP |
846 | static void |
847 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
848 | struct drm_display_mode *adjusted_mode) | |
849 | { | |
e3421a18 | 850 | struct drm_device *dev = encoder->dev; |
417e822d | 851 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 852 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 853 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
854 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
855 | ||
f01eca2e KP |
856 | /* Turn on the eDP PLL if needed */ |
857 | if (is_edp(intel_dp)) { | |
858 | if (!is_pch_edp(intel_dp)) | |
859 | ironlake_edp_pll_on(encoder); | |
860 | else | |
861 | ironlake_edp_pll_off(encoder); | |
862 | } | |
863 | ||
417e822d | 864 | /* |
1a2eb460 | 865 | * There are four kinds of DP registers: |
417e822d KP |
866 | * |
867 | * IBX PCH | |
1a2eb460 KP |
868 | * SNB CPU |
869 | * IVB CPU | |
417e822d KP |
870 | * CPT PCH |
871 | * | |
872 | * IBX PCH and CPU are the same for almost everything, | |
873 | * except that the CPU DP PLL is configured in this | |
874 | * register | |
875 | * | |
876 | * CPT PCH is quite different, having many bits moved | |
877 | * to the TRANS_DP_CTL register instead. That | |
878 | * configuration happens (oddly) in ironlake_pch_enable | |
879 | */ | |
9c9e7927 | 880 | |
417e822d KP |
881 | /* Preserve the BIOS-computed detected bit. This is |
882 | * supposed to be read-only. | |
883 | */ | |
884 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
885 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 886 | |
417e822d KP |
887 | /* Handle DP bits in common between all three register formats */ |
888 | ||
889 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 890 | |
ea5b213a | 891 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 892 | case 1: |
ea5b213a | 893 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
894 | break; |
895 | case 2: | |
ea5b213a | 896 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
897 | break; |
898 | case 4: | |
ea5b213a | 899 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
900 | break; |
901 | } | |
e0dac65e WF |
902 | if (intel_dp->has_audio) { |
903 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
904 | pipe_name(intel_crtc->pipe)); | |
ea5b213a | 905 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
e0dac65e WF |
906 | intel_write_eld(encoder, adjusted_mode); |
907 | } | |
ea5b213a CW |
908 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
909 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
910 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 911 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 | 912 | /* |
9962c925 | 913 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 914 | */ |
7183dc29 JB |
915 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
916 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a | 917 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
a4fc5ed6 KP |
918 | } |
919 | ||
417e822d | 920 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 921 | |
1a2eb460 KP |
922 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { |
923 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
924 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
925 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
926 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
927 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
928 | ||
929 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
930 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
931 | ||
932 | intel_dp->DP |= intel_crtc->pipe << 29; | |
933 | ||
934 | /* don't miss out required setting for eDP */ | |
935 | intel_dp->DP |= DP_PLL_ENABLE; | |
936 | if (adjusted_mode->clock < 200000) | |
937 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | |
938 | else | |
939 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
940 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { | |
417e822d KP |
941 | intel_dp->DP |= intel_dp->color_range; |
942 | ||
943 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
944 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
945 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
946 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
947 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
948 | ||
949 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
950 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
951 | ||
952 | if (intel_crtc->pipe == 1) | |
953 | intel_dp->DP |= DP_PIPEB_SELECT; | |
954 | ||
955 | if (is_cpu_edp(intel_dp)) { | |
956 | /* don't miss out required setting for eDP */ | |
957 | intel_dp->DP |= DP_PLL_ENABLE; | |
958 | if (adjusted_mode->clock < 200000) | |
959 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | |
960 | else | |
961 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
962 | } | |
963 | } else { | |
964 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 965 | } |
a4fc5ed6 KP |
966 | } |
967 | ||
99ea7127 KP |
968 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
969 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
970 | ||
971 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) | |
972 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
973 | ||
974 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) | |
975 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
976 | ||
977 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, | |
978 | u32 mask, | |
979 | u32 value) | |
bd943159 | 980 | { |
99ea7127 KP |
981 | struct drm_device *dev = intel_dp->base.base.dev; |
982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
32ce697c | 983 | |
99ea7127 KP |
984 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
985 | mask, value, | |
986 | I915_READ(PCH_PP_STATUS), | |
987 | I915_READ(PCH_PP_CONTROL)); | |
32ce697c | 988 | |
99ea7127 KP |
989 | if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { |
990 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", | |
991 | I915_READ(PCH_PP_STATUS), | |
992 | I915_READ(PCH_PP_CONTROL)); | |
32ce697c | 993 | } |
99ea7127 | 994 | } |
32ce697c | 995 | |
99ea7127 KP |
996 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
997 | { | |
998 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
999 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); | |
bd943159 KP |
1000 | } |
1001 | ||
99ea7127 KP |
1002 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
1003 | { | |
1004 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
1005 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); | |
1006 | } | |
1007 | ||
1008 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) | |
1009 | { | |
1010 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
1011 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); | |
1012 | } | |
1013 | ||
1014 | ||
832dd3c1 KP |
1015 | /* Read the current pp_control value, unlocking the register if it |
1016 | * is locked | |
1017 | */ | |
1018 | ||
1019 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) | |
1020 | { | |
1021 | u32 control = I915_READ(PCH_PP_CONTROL); | |
1022 | ||
1023 | control &= ~PANEL_UNLOCK_MASK; | |
1024 | control |= PANEL_UNLOCK_REGS; | |
1025 | return control; | |
bd943159 KP |
1026 | } |
1027 | ||
5d613501 JB |
1028 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1029 | { | |
1030 | struct drm_device *dev = intel_dp->base.base.dev; | |
1031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1032 | u32 pp; | |
1033 | ||
97af61f5 KP |
1034 | if (!is_edp(intel_dp)) |
1035 | return; | |
f01eca2e | 1036 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 1037 | |
bd943159 KP |
1038 | WARN(intel_dp->want_panel_vdd, |
1039 | "eDP VDD already requested on\n"); | |
1040 | ||
1041 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1042 | |
bd943159 KP |
1043 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
1044 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
1045 | return; | |
1046 | } | |
1047 | ||
99ea7127 KP |
1048 | if (!ironlake_edp_have_panel_power(intel_dp)) |
1049 | ironlake_wait_panel_power_cycle(intel_dp); | |
1050 | ||
832dd3c1 | 1051 | pp = ironlake_get_pp_control(dev_priv); |
5d613501 JB |
1052 | pp |= EDP_FORCE_VDD; |
1053 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1054 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
1055 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
1056 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
ebf33b18 KP |
1057 | |
1058 | /* | |
1059 | * If the panel wasn't on, delay before accessing aux channel | |
1060 | */ | |
1061 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 1062 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1063 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1064 | } |
5d613501 JB |
1065 | } |
1066 | ||
bd943159 | 1067 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 JB |
1068 | { |
1069 | struct drm_device *dev = intel_dp->base.base.dev; | |
1070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1071 | u32 pp; | |
1072 | ||
bd943159 | 1073 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
832dd3c1 | 1074 | pp = ironlake_get_pp_control(dev_priv); |
bd943159 KP |
1075 | pp &= ~EDP_FORCE_VDD; |
1076 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1077 | POSTING_READ(PCH_PP_CONTROL); | |
1078 | ||
1079 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
1080 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", | |
1081 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
99ea7127 KP |
1082 | |
1083 | msleep(intel_dp->panel_power_down_delay); | |
bd943159 KP |
1084 | } |
1085 | } | |
5d613501 | 1086 | |
bd943159 KP |
1087 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1088 | { | |
1089 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1090 | struct intel_dp, panel_vdd_work); | |
1091 | struct drm_device *dev = intel_dp->base.base.dev; | |
1092 | ||
627f7675 | 1093 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 1094 | ironlake_panel_vdd_off_sync(intel_dp); |
627f7675 | 1095 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1096 | } |
1097 | ||
1098 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) | |
1099 | { | |
97af61f5 KP |
1100 | if (!is_edp(intel_dp)) |
1101 | return; | |
5d613501 | 1102 | |
bd943159 KP |
1103 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
1104 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
f2e8b18a | 1105 | |
bd943159 KP |
1106 | intel_dp->want_panel_vdd = false; |
1107 | ||
1108 | if (sync) { | |
1109 | ironlake_panel_vdd_off_sync(intel_dp); | |
1110 | } else { | |
1111 | /* | |
1112 | * Queue the timer to fire a long | |
1113 | * time from now (relative to the power down delay) | |
1114 | * to keep the panel power up across a sequence of operations | |
1115 | */ | |
1116 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1117 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1118 | } | |
5d613501 JB |
1119 | } |
1120 | ||
86a3073e | 1121 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1122 | { |
01cb9ea6 | 1123 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1124 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1125 | u32 pp; |
9934c132 | 1126 | |
97af61f5 | 1127 | if (!is_edp(intel_dp)) |
bd943159 | 1128 | return; |
99ea7127 KP |
1129 | |
1130 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1131 | ||
1132 | if (ironlake_edp_have_panel_power(intel_dp)) { | |
1133 | DRM_DEBUG_KMS("eDP power already on\n"); | |
7d639f35 | 1134 | return; |
99ea7127 | 1135 | } |
9934c132 | 1136 | |
99ea7127 | 1137 | ironlake_wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1138 | |
99ea7127 | 1139 | pp = ironlake_get_pp_control(dev_priv); |
05ce1a49 KP |
1140 | if (IS_GEN5(dev)) { |
1141 | /* ILK workaround: disable reset around power sequence */ | |
1142 | pp &= ~PANEL_POWER_RESET; | |
1143 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1144 | POSTING_READ(PCH_PP_CONTROL); | |
1145 | } | |
37c6c9b0 | 1146 | |
1c0ae80a | 1147 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1148 | if (!IS_GEN5(dev)) |
1149 | pp |= PANEL_POWER_RESET; | |
1150 | ||
9934c132 | 1151 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 1152 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 1153 | |
99ea7127 | 1154 | ironlake_wait_panel_on(intel_dp); |
9934c132 | 1155 | |
05ce1a49 KP |
1156 | if (IS_GEN5(dev)) { |
1157 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1158 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1159 | POSTING_READ(PCH_PP_CONTROL); | |
1160 | } | |
9934c132 JB |
1161 | } |
1162 | ||
99ea7127 | 1163 | static void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1164 | { |
99ea7127 | 1165 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1166 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1167 | u32 pp; |
9934c132 | 1168 | |
97af61f5 KP |
1169 | if (!is_edp(intel_dp)) |
1170 | return; | |
37c6c9b0 | 1171 | |
99ea7127 | 1172 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1173 | |
6cb49835 | 1174 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
37c6c9b0 | 1175 | |
99ea7127 | 1176 | pp = ironlake_get_pp_control(dev_priv); |
35a38556 DV |
1177 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1178 | * panels get very unhappy and cease to work. */ | |
1179 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); | |
99ea7127 KP |
1180 | I915_WRITE(PCH_PP_CONTROL, pp); |
1181 | POSTING_READ(PCH_PP_CONTROL); | |
9934c132 | 1182 | |
35a38556 DV |
1183 | intel_dp->want_panel_vdd = false; |
1184 | ||
99ea7127 | 1185 | ironlake_wait_panel_off(intel_dp); |
9934c132 JB |
1186 | } |
1187 | ||
86a3073e | 1188 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1189 | { |
f01eca2e | 1190 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1191 | struct drm_i915_private *dev_priv = dev->dev_private; |
1192 | u32 pp; | |
1193 | ||
f01eca2e KP |
1194 | if (!is_edp(intel_dp)) |
1195 | return; | |
1196 | ||
28c97730 | 1197 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1198 | /* |
1199 | * If we enable the backlight right away following a panel power | |
1200 | * on, we may see slight flicker as the panel syncs with the eDP | |
1201 | * link. So delay a bit to make sure the image is solid before | |
1202 | * allowing it to appear. | |
1203 | */ | |
f01eca2e | 1204 | msleep(intel_dp->backlight_on_delay); |
832dd3c1 | 1205 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1206 | pp |= EDP_BLC_ENABLE; |
1207 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 1208 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
1209 | } |
1210 | ||
86a3073e | 1211 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1212 | { |
f01eca2e | 1213 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1214 | struct drm_i915_private *dev_priv = dev->dev_private; |
1215 | u32 pp; | |
1216 | ||
f01eca2e KP |
1217 | if (!is_edp(intel_dp)) |
1218 | return; | |
1219 | ||
28c97730 | 1220 | DRM_DEBUG_KMS("\n"); |
832dd3c1 | 1221 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1222 | pp &= ~EDP_BLC_ENABLE; |
1223 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1224 | POSTING_READ(PCH_PP_CONTROL); |
1225 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1226 | } |
a4fc5ed6 | 1227 | |
d240f20f JB |
1228 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1229 | { | |
1230 | struct drm_device *dev = encoder->dev; | |
1231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1232 | u32 dpa_ctl; | |
1233 | ||
1234 | DRM_DEBUG_KMS("\n"); | |
1235 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1236 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1237 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1238 | POSTING_READ(DP_A); |
1239 | udelay(200); | |
d240f20f JB |
1240 | } |
1241 | ||
1242 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1243 | { | |
1244 | struct drm_device *dev = encoder->dev; | |
1245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1246 | u32 dpa_ctl; | |
1247 | ||
1248 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1249 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1250 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1251 | POSTING_READ(DP_A); |
d240f20f JB |
1252 | udelay(200); |
1253 | } | |
1254 | ||
c7ad3810 JB |
1255 | /* If the sink supports it, try to set the power state appropriately */ |
1256 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1257 | { | |
1258 | int ret, i; | |
1259 | ||
1260 | /* Should have a valid DPCD by this point */ | |
1261 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1262 | return; | |
1263 | ||
1264 | if (mode != DRM_MODE_DPMS_ON) { | |
1265 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1266 | DP_SET_POWER_D3); | |
1267 | if (ret != 1) | |
1268 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1269 | } else { | |
1270 | /* | |
1271 | * When turning on, we need to retry for 1ms to give the sink | |
1272 | * time to wake up. | |
1273 | */ | |
1274 | for (i = 0; i < 3; i++) { | |
1275 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1276 | DP_SET_POWER, | |
1277 | DP_SET_POWER_D0); | |
1278 | if (ret == 1) | |
1279 | break; | |
1280 | msleep(1); | |
1281 | } | |
1282 | } | |
1283 | } | |
1284 | ||
d240f20f JB |
1285 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1286 | { | |
1287 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1288 | |
6cb49835 DV |
1289 | |
1290 | /* Make sure the panel is off before trying to change the mode. But also | |
1291 | * ensure that we have vdd while we switch off the panel. */ | |
1292 | ironlake_edp_panel_vdd_on(intel_dp); | |
21264c63 | 1293 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1294 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
35a38556 | 1295 | ironlake_edp_panel_off(intel_dp); |
21264c63 | 1296 | intel_dp_link_down(intel_dp); |
d240f20f JB |
1297 | } |
1298 | ||
1299 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1300 | { | |
1301 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d4270e57 JB |
1302 | struct drm_device *dev = encoder->dev; |
1303 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); | |
5d613501 | 1304 | |
97af61f5 | 1305 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1306 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1307 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1308 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1309 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1310 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1311 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1312 | |
1313 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d4270e57 JB |
1314 | |
1315 | if (HAS_PCH_CPT(dev)) | |
1316 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
d240f20f JB |
1317 | } |
1318 | ||
a4fc5ed6 KP |
1319 | static void |
1320 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1321 | { | |
ea5b213a | 1322 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1323 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1324 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1325 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1326 | |
1327 | if (mode != DRM_MODE_DPMS_ON) { | |
6cb49835 DV |
1328 | /* Switching the panel off requires vdd. */ |
1329 | ironlake_edp_panel_vdd_on(intel_dp); | |
21264c63 | 1330 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1331 | intel_dp_sink_dpms(intel_dp, mode); |
35a38556 | 1332 | ironlake_edp_panel_off(intel_dp); |
736085bc | 1333 | intel_dp_link_down(intel_dp); |
21264c63 KP |
1334 | |
1335 | if (is_cpu_edp(intel_dp)) | |
1336 | ironlake_edp_pll_off(encoder); | |
a4fc5ed6 | 1337 | } else { |
21264c63 KP |
1338 | if (is_cpu_edp(intel_dp)) |
1339 | ironlake_edp_pll_on(encoder); | |
1340 | ||
97af61f5 | 1341 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1342 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1343 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1344 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1345 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1346 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1347 | intel_dp_complete_link_train(intel_dp); |
bee7eb2d | 1348 | } else |
bd943159 KP |
1349 | ironlake_edp_panel_vdd_off(intel_dp, false); |
1350 | ironlake_edp_backlight_on(intel_dp); | |
a4fc5ed6 | 1351 | } |
d2b996ac | 1352 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1353 | } |
1354 | ||
1355 | /* | |
df0c237d JB |
1356 | * Native read with retry for link status and receiver capability reads for |
1357 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1358 | */ |
1359 | static bool | |
df0c237d JB |
1360 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1361 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1362 | { |
61da5fab JB |
1363 | int ret, i; |
1364 | ||
df0c237d JB |
1365 | /* |
1366 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1367 | * but we're also supposed to retry 3 times per the spec. | |
1368 | */ | |
61da5fab | 1369 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1370 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1371 | recv_bytes); | |
1372 | if (ret == recv_bytes) | |
61da5fab JB |
1373 | return true; |
1374 | msleep(1); | |
1375 | } | |
a4fc5ed6 | 1376 | |
61da5fab | 1377 | return false; |
a4fc5ed6 KP |
1378 | } |
1379 | ||
1380 | /* | |
1381 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1382 | * link status information | |
1383 | */ | |
1384 | static bool | |
93f62dad | 1385 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1386 | { |
df0c237d JB |
1387 | return intel_dp_aux_native_read_retry(intel_dp, |
1388 | DP_LANE0_1_STATUS, | |
93f62dad | 1389 | link_status, |
df0c237d | 1390 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
1391 | } |
1392 | ||
1393 | static uint8_t | |
1394 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1395 | int r) | |
1396 | { | |
1397 | return link_status[r - DP_LANE0_1_STATUS]; | |
1398 | } | |
1399 | ||
a4fc5ed6 | 1400 | static uint8_t |
93f62dad | 1401 | intel_get_adjust_request_voltage(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1402 | int lane) |
1403 | { | |
a4fc5ed6 KP |
1404 | int s = ((lane & 1) ? |
1405 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1406 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
93f62dad | 1407 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1408 | |
1409 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1410 | } | |
1411 | ||
1412 | static uint8_t | |
93f62dad | 1413 | intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1414 | int lane) |
1415 | { | |
a4fc5ed6 KP |
1416 | int s = ((lane & 1) ? |
1417 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1418 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
93f62dad | 1419 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1420 | |
1421 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1422 | } | |
1423 | ||
1424 | ||
1425 | #if 0 | |
1426 | static char *voltage_names[] = { | |
1427 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1428 | }; | |
1429 | static char *pre_emph_names[] = { | |
1430 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1431 | }; | |
1432 | static char *link_train_names[] = { | |
1433 | "pattern 1", "pattern 2", "idle", "off" | |
1434 | }; | |
1435 | #endif | |
1436 | ||
1437 | /* | |
1438 | * These are source-specific values; current Intel hardware supports | |
1439 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1440 | */ | |
a4fc5ed6 KP |
1441 | |
1442 | static uint8_t | |
1a2eb460 | 1443 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 1444 | { |
1a2eb460 KP |
1445 | struct drm_device *dev = intel_dp->base.base.dev; |
1446 | ||
1447 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) | |
1448 | return DP_TRAIN_VOLTAGE_SWING_800; | |
1449 | else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) | |
1450 | return DP_TRAIN_VOLTAGE_SWING_1200; | |
1451 | else | |
1452 | return DP_TRAIN_VOLTAGE_SWING_800; | |
1453 | } | |
1454 | ||
1455 | static uint8_t | |
1456 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
1457 | { | |
1458 | struct drm_device *dev = intel_dp->base.base.dev; | |
1459 | ||
1460 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { | |
1461 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1462 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1463 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1464 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1465 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1466 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1467 | default: | |
1468 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1469 | } | |
1470 | } else { | |
1471 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1472 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1473 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1474 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1475 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1476 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1477 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1478 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1479 | default: | |
1480 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1481 | } | |
a4fc5ed6 KP |
1482 | } |
1483 | } | |
1484 | ||
1485 | static void | |
93f62dad | 1486 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 KP |
1487 | { |
1488 | uint8_t v = 0; | |
1489 | uint8_t p = 0; | |
1490 | int lane; | |
93f62dad | 1491 | uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); |
1a2eb460 KP |
1492 | uint8_t voltage_max; |
1493 | uint8_t preemph_max; | |
a4fc5ed6 | 1494 | |
33a34e4e | 1495 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad KP |
1496 | uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); |
1497 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); | |
a4fc5ed6 KP |
1498 | |
1499 | if (this_v > v) | |
1500 | v = this_v; | |
1501 | if (this_p > p) | |
1502 | p = this_p; | |
1503 | } | |
1504 | ||
1a2eb460 | 1505 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
1506 | if (v >= voltage_max) |
1507 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 1508 | |
1a2eb460 KP |
1509 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
1510 | if (p >= preemph_max) | |
1511 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
1512 | |
1513 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1514 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1515 | } |
1516 | ||
1517 | static uint32_t | |
93f62dad | 1518 | intel_dp_signal_levels(uint8_t train_set) |
a4fc5ed6 | 1519 | { |
3cf2efb1 | 1520 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1521 | |
3cf2efb1 | 1522 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1523 | case DP_TRAIN_VOLTAGE_SWING_400: |
1524 | default: | |
1525 | signal_levels |= DP_VOLTAGE_0_4; | |
1526 | break; | |
1527 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1528 | signal_levels |= DP_VOLTAGE_0_6; | |
1529 | break; | |
1530 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1531 | signal_levels |= DP_VOLTAGE_0_8; | |
1532 | break; | |
1533 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1534 | signal_levels |= DP_VOLTAGE_1_2; | |
1535 | break; | |
1536 | } | |
3cf2efb1 | 1537 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1538 | case DP_TRAIN_PRE_EMPHASIS_0: |
1539 | default: | |
1540 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1541 | break; | |
1542 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1543 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1544 | break; | |
1545 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1546 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1547 | break; | |
1548 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1549 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1550 | break; | |
1551 | } | |
1552 | return signal_levels; | |
1553 | } | |
1554 | ||
e3421a18 ZW |
1555 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1556 | static uint32_t | |
1557 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1558 | { | |
3c5a62b5 YL |
1559 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1560 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1561 | switch (signal_levels) { | |
e3421a18 | 1562 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1563 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1564 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1565 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1566 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1567 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1568 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1569 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1570 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1571 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1572 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1573 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1574 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1575 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1576 | default: |
3c5a62b5 YL |
1577 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1578 | "0x%x\n", signal_levels); | |
1579 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1580 | } |
1581 | } | |
1582 | ||
1a2eb460 KP |
1583 | /* Gen7's DP voltage swing and pre-emphasis control */ |
1584 | static uint32_t | |
1585 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
1586 | { | |
1587 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
1588 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1589 | switch (signal_levels) { | |
1590 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1591 | return EDP_LINK_TRAIN_400MV_0DB_IVB; | |
1592 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1593 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; | |
1594 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1595 | return EDP_LINK_TRAIN_400MV_6DB_IVB; | |
1596 | ||
1597 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
1598 | return EDP_LINK_TRAIN_600MV_0DB_IVB; | |
1599 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1600 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; | |
1601 | ||
1602 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
1603 | return EDP_LINK_TRAIN_800MV_0DB_IVB; | |
1604 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1605 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; | |
1606 | ||
1607 | default: | |
1608 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
1609 | "0x%x\n", signal_levels); | |
1610 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
1611 | } | |
1612 | } | |
1613 | ||
a4fc5ed6 KP |
1614 | static uint8_t |
1615 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1616 | int lane) | |
1617 | { | |
a4fc5ed6 | 1618 | int s = (lane & 1) * 4; |
93f62dad | 1619 | uint8_t l = link_status[lane>>1]; |
a4fc5ed6 KP |
1620 | |
1621 | return (l >> s) & 0xf; | |
1622 | } | |
1623 | ||
1624 | /* Check for clock recovery is done on all channels */ | |
1625 | static bool | |
1626 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1627 | { | |
1628 | int lane; | |
1629 | uint8_t lane_status; | |
1630 | ||
1631 | for (lane = 0; lane < lane_count; lane++) { | |
1632 | lane_status = intel_get_lane_status(link_status, lane); | |
1633 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1634 | return false; | |
1635 | } | |
1636 | return true; | |
1637 | } | |
1638 | ||
1639 | /* Check to see if channel eq is done on all channels */ | |
1640 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1641 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1642 | DP_LANE_SYMBOL_LOCKED) | |
1643 | static bool | |
93f62dad | 1644 | intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 KP |
1645 | { |
1646 | uint8_t lane_align; | |
1647 | uint8_t lane_status; | |
1648 | int lane; | |
1649 | ||
93f62dad | 1650 | lane_align = intel_dp_link_status(link_status, |
a4fc5ed6 KP |
1651 | DP_LANE_ALIGN_STATUS_UPDATED); |
1652 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1653 | return false; | |
33a34e4e | 1654 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad | 1655 | lane_status = intel_get_lane_status(link_status, lane); |
a4fc5ed6 KP |
1656 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1657 | return false; | |
1658 | } | |
1659 | return true; | |
1660 | } | |
1661 | ||
1662 | static bool | |
ea5b213a | 1663 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1664 | uint32_t dp_reg_value, |
58e10eb9 | 1665 | uint8_t dp_train_pat) |
a4fc5ed6 | 1666 | { |
4ef69c7a | 1667 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1668 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1669 | int ret; |
1670 | ||
ea5b213a CW |
1671 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1672 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1673 | |
ea5b213a | 1674 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1675 | DP_TRAINING_PATTERN_SET, |
1676 | dp_train_pat); | |
1677 | ||
ea5b213a | 1678 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 | 1679 | DP_TRAINING_LANE0_SET, |
b34f1f09 KP |
1680 | intel_dp->train_set, |
1681 | intel_dp->lane_count); | |
1682 | if (ret != intel_dp->lane_count) | |
a4fc5ed6 KP |
1683 | return false; |
1684 | ||
1685 | return true; | |
1686 | } | |
1687 | ||
33a34e4e | 1688 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1689 | static void |
33a34e4e | 1690 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1691 | { |
4ef69c7a | 1692 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1693 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1694 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1695 | int i; |
1696 | uint8_t voltage; | |
1697 | bool clock_recovery = false; | |
cdb0e95b | 1698 | int voltage_tries, loop_tries; |
e3421a18 | 1699 | u32 reg; |
ea5b213a | 1700 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1701 | |
e8519464 AJ |
1702 | /* |
1703 | * On CPT we have to enable the port in training pattern 1, which | |
1704 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1705 | * the port and wait for it to become active. | |
1706 | */ | |
1707 | if (!HAS_PCH_CPT(dev)) { | |
1708 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1709 | POSTING_READ(intel_dp->output_reg); | |
1710 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1711 | } | |
a4fc5ed6 | 1712 | |
3cf2efb1 CW |
1713 | /* Write the link configuration data */ |
1714 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1715 | intel_dp->link_configuration, | |
1716 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1717 | |
1718 | DP |= DP_PORT_EN; | |
1a2eb460 KP |
1719 | |
1720 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) | |
e3421a18 ZW |
1721 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1722 | else | |
1723 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1724 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 | 1725 | voltage = 0xff; |
cdb0e95b KP |
1726 | voltage_tries = 0; |
1727 | loop_tries = 0; | |
a4fc5ed6 KP |
1728 | clock_recovery = false; |
1729 | for (;;) { | |
33a34e4e | 1730 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
93f62dad | 1731 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1732 | uint32_t signal_levels; |
417e822d | 1733 | |
1a2eb460 KP |
1734 | |
1735 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { | |
1736 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); | |
1737 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; | |
1738 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { | |
33a34e4e | 1739 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1740 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1741 | } else { | |
93f62dad KP |
1742 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
1743 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); | |
e3421a18 ZW |
1744 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1745 | } | |
a4fc5ed6 | 1746 | |
1a2eb460 | 1747 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) |
e3421a18 ZW |
1748 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1749 | else | |
1750 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1751 | ||
ea5b213a | 1752 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1753 | DP_TRAINING_PATTERN_1 | |
1754 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1755 | break; |
a4fc5ed6 KP |
1756 | /* Set training pattern 1 */ |
1757 | ||
3cf2efb1 | 1758 | udelay(100); |
93f62dad KP |
1759 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1760 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 1761 | break; |
93f62dad | 1762 | } |
a4fc5ed6 | 1763 | |
93f62dad KP |
1764 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1765 | DRM_DEBUG_KMS("clock recovery OK\n"); | |
3cf2efb1 CW |
1766 | clock_recovery = true; |
1767 | break; | |
1768 | } | |
1769 | ||
1770 | /* Check to see if we've tried the max voltage */ | |
1771 | for (i = 0; i < intel_dp->lane_count; i++) | |
1772 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1773 | break; |
0d710688 | 1774 | if (i == intel_dp->lane_count && voltage_tries == 5) { |
cdb0e95b KP |
1775 | ++loop_tries; |
1776 | if (loop_tries == 5) { | |
1777 | DRM_DEBUG_KMS("too many full retries, give up\n"); | |
1778 | break; | |
1779 | } | |
1780 | memset(intel_dp->train_set, 0, 4); | |
1781 | voltage_tries = 0; | |
1782 | continue; | |
1783 | } | |
a4fc5ed6 | 1784 | |
3cf2efb1 CW |
1785 | /* Check to see if we've tried the same voltage 5 times */ |
1786 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
cdb0e95b KP |
1787 | ++voltage_tries; |
1788 | if (voltage_tries == 5) { | |
1789 | DRM_DEBUG_KMS("too many voltage retries, give up\n"); | |
a4fc5ed6 | 1790 | break; |
cdb0e95b | 1791 | } |
3cf2efb1 | 1792 | } else |
cdb0e95b | 1793 | voltage_tries = 0; |
3cf2efb1 | 1794 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
a4fc5ed6 | 1795 | |
3cf2efb1 | 1796 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1797 | intel_get_adjust_train(intel_dp, link_status); |
a4fc5ed6 KP |
1798 | } |
1799 | ||
33a34e4e JB |
1800 | intel_dp->DP = DP; |
1801 | } | |
1802 | ||
1803 | static void | |
1804 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1805 | { | |
4ef69c7a | 1806 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1807 | struct drm_i915_private *dev_priv = dev->dev_private; |
1808 | bool channel_eq = false; | |
37f80975 | 1809 | int tries, cr_tries; |
33a34e4e JB |
1810 | u32 reg; |
1811 | uint32_t DP = intel_dp->DP; | |
1812 | ||
a4fc5ed6 KP |
1813 | /* channel equalization */ |
1814 | tries = 0; | |
37f80975 | 1815 | cr_tries = 0; |
a4fc5ed6 KP |
1816 | channel_eq = false; |
1817 | for (;;) { | |
33a34e4e | 1818 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1819 | uint32_t signal_levels; |
93f62dad | 1820 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1821 | |
37f80975 JB |
1822 | if (cr_tries > 5) { |
1823 | DRM_ERROR("failed to train DP, aborting\n"); | |
1824 | intel_dp_link_down(intel_dp); | |
1825 | break; | |
1826 | } | |
1827 | ||
1a2eb460 KP |
1828 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { |
1829 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); | |
1830 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; | |
1831 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { | |
33a34e4e | 1832 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1833 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1834 | } else { | |
93f62dad | 1835 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1836 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1837 | } | |
1838 | ||
1a2eb460 | 1839 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) |
e3421a18 ZW |
1840 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1841 | else | |
1842 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1843 | |
1844 | /* channel eq pattern */ | |
ea5b213a | 1845 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1846 | DP_TRAINING_PATTERN_2 | |
1847 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1848 | break; |
1849 | ||
3cf2efb1 | 1850 | udelay(400); |
93f62dad | 1851 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 | 1852 | break; |
a4fc5ed6 | 1853 | |
37f80975 | 1854 | /* Make sure clock is still ok */ |
93f62dad | 1855 | if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 JB |
1856 | intel_dp_start_link_train(intel_dp); |
1857 | cr_tries++; | |
1858 | continue; | |
1859 | } | |
1860 | ||
93f62dad | 1861 | if (intel_channel_eq_ok(intel_dp, link_status)) { |
3cf2efb1 CW |
1862 | channel_eq = true; |
1863 | break; | |
1864 | } | |
a4fc5ed6 | 1865 | |
37f80975 JB |
1866 | /* Try 5 times, then try clock recovery if that fails */ |
1867 | if (tries > 5) { | |
1868 | intel_dp_link_down(intel_dp); | |
1869 | intel_dp_start_link_train(intel_dp); | |
1870 | tries = 0; | |
1871 | cr_tries++; | |
1872 | continue; | |
1873 | } | |
a4fc5ed6 | 1874 | |
3cf2efb1 | 1875 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1876 | intel_get_adjust_train(intel_dp, link_status); |
3cf2efb1 | 1877 | ++tries; |
869184a6 | 1878 | } |
3cf2efb1 | 1879 | |
1a2eb460 | 1880 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) |
e3421a18 ZW |
1881 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1882 | else | |
1883 | reg = DP | DP_LINK_TRAIN_OFF; | |
1884 | ||
ea5b213a CW |
1885 | I915_WRITE(intel_dp->output_reg, reg); |
1886 | POSTING_READ(intel_dp->output_reg); | |
1887 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1888 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1889 | } | |
1890 | ||
1891 | static void | |
ea5b213a | 1892 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1893 | { |
4ef69c7a | 1894 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1895 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1896 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1897 | |
1b39d6f3 CW |
1898 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1899 | return; | |
1900 | ||
28c97730 | 1901 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1902 | |
cfcb0fc9 | 1903 | if (is_edp(intel_dp)) { |
32f9d658 | 1904 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1905 | I915_WRITE(intel_dp->output_reg, DP); |
1906 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1907 | udelay(100); |
1908 | } | |
1909 | ||
1a2eb460 | 1910 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
e3421a18 | 1911 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1912 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1913 | } else { |
1914 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1915 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1916 | } |
fe255d00 | 1917 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1918 | |
fe255d00 | 1919 | msleep(17); |
5eb08b69 | 1920 | |
417e822d | 1921 | if (is_edp(intel_dp)) { |
1a2eb460 | 1922 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) |
417e822d KP |
1923 | DP |= DP_LINK_TRAIN_OFF_CPT; |
1924 | else | |
1925 | DP |= DP_LINK_TRAIN_OFF; | |
1926 | } | |
5bddd17f | 1927 | |
493a7081 | 1928 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 1929 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
31acbcc4 CW |
1930 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1931 | ||
5bddd17f EA |
1932 | /* Hardware workaround: leaving our transcoder select |
1933 | * set to transcoder B while it's off will prevent the | |
1934 | * corresponding HDMI output on transcoder A. | |
1935 | * | |
1936 | * Combine this with another hardware workaround: | |
1937 | * transcoder select bit can only be cleared while the | |
1938 | * port is enabled. | |
1939 | */ | |
1940 | DP &= ~DP_PIPEB_SELECT; | |
1941 | I915_WRITE(intel_dp->output_reg, DP); | |
1942 | ||
1943 | /* Changes to enable or select take place the vblank | |
1944 | * after being written. | |
1945 | */ | |
31acbcc4 CW |
1946 | if (crtc == NULL) { |
1947 | /* We can arrive here never having been attached | |
1948 | * to a CRTC, for instance, due to inheriting | |
1949 | * random state from the BIOS. | |
1950 | * | |
1951 | * If the pipe is not running, play safe and | |
1952 | * wait for the clocks to stabilise before | |
1953 | * continuing. | |
1954 | */ | |
1955 | POSTING_READ(intel_dp->output_reg); | |
1956 | msleep(50); | |
1957 | } else | |
1958 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1959 | } |
1960 | ||
832afda6 | 1961 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
1962 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1963 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1964 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1965 | } |
1966 | ||
26d61aad KP |
1967 | static bool |
1968 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1969 | { |
92fd8fd1 | 1970 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
0206e353 | 1971 | sizeof(intel_dp->dpcd)) && |
92fd8fd1 | 1972 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { |
26d61aad | 1973 | return true; |
92fd8fd1 KP |
1974 | } |
1975 | ||
26d61aad | 1976 | return false; |
92fd8fd1 KP |
1977 | } |
1978 | ||
0d198328 AJ |
1979 | static void |
1980 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
1981 | { | |
1982 | u8 buf[3]; | |
1983 | ||
1984 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
1985 | return; | |
1986 | ||
351cfc34 DV |
1987 | ironlake_edp_panel_vdd_on(intel_dp); |
1988 | ||
0d198328 AJ |
1989 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
1990 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
1991 | buf[0], buf[1], buf[2]); | |
1992 | ||
1993 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) | |
1994 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
1995 | buf[0], buf[1], buf[2]); | |
351cfc34 DV |
1996 | |
1997 | ironlake_edp_panel_vdd_off(intel_dp, false); | |
0d198328 AJ |
1998 | } |
1999 | ||
a60f0e38 JB |
2000 | static bool |
2001 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
2002 | { | |
2003 | int ret; | |
2004 | ||
2005 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
2006 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2007 | sink_irq_vector, 1); | |
2008 | if (!ret) | |
2009 | return false; | |
2010 | ||
2011 | return true; | |
2012 | } | |
2013 | ||
2014 | static void | |
2015 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
2016 | { | |
2017 | /* NAK by default */ | |
2018 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); | |
2019 | } | |
2020 | ||
a4fc5ed6 KP |
2021 | /* |
2022 | * According to DP spec | |
2023 | * 5.1.2: | |
2024 | * 1. Read DPCD | |
2025 | * 2. Configure link according to Receiver Capabilities | |
2026 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
2027 | * 4. Check link status on receipt of hot-plug interrupt | |
2028 | */ | |
2029 | ||
2030 | static void | |
ea5b213a | 2031 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 2032 | { |
a60f0e38 | 2033 | u8 sink_irq_vector; |
93f62dad | 2034 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 2035 | |
d2b996ac KP |
2036 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
2037 | return; | |
59cd09e1 | 2038 | |
4ef69c7a | 2039 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
2040 | return; |
2041 | ||
92fd8fd1 | 2042 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 2043 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
ea5b213a | 2044 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
2045 | return; |
2046 | } | |
2047 | ||
92fd8fd1 | 2048 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 2049 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
2050 | intel_dp_link_down(intel_dp); |
2051 | return; | |
2052 | } | |
2053 | ||
a60f0e38 JB |
2054 | /* Try to read the source of the interrupt */ |
2055 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
2056 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
2057 | /* Clear interrupt source */ | |
2058 | intel_dp_aux_native_write_1(intel_dp, | |
2059 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2060 | sink_irq_vector); | |
2061 | ||
2062 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
2063 | intel_dp_handle_test_request(intel_dp); | |
2064 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
2065 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
2066 | } | |
2067 | ||
93f62dad | 2068 | if (!intel_channel_eq_ok(intel_dp, link_status)) { |
92fd8fd1 KP |
2069 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
2070 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
2071 | intel_dp_start_link_train(intel_dp); |
2072 | intel_dp_complete_link_train(intel_dp); | |
2073 | } | |
a4fc5ed6 | 2074 | } |
a4fc5ed6 | 2075 | |
71ba9000 | 2076 | static enum drm_connector_status |
26d61aad | 2077 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 2078 | { |
26d61aad KP |
2079 | if (intel_dp_get_dpcd(intel_dp)) |
2080 | return connector_status_connected; | |
2081 | return connector_status_disconnected; | |
71ba9000 AJ |
2082 | } |
2083 | ||
5eb08b69 | 2084 | static enum drm_connector_status |
a9756bb5 | 2085 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 2086 | { |
5eb08b69 ZW |
2087 | enum drm_connector_status status; |
2088 | ||
fe16d949 CW |
2089 | /* Can't disconnect eDP, but you can close the lid... */ |
2090 | if (is_edp(intel_dp)) { | |
2091 | status = intel_panel_detect(intel_dp->base.base.dev); | |
2092 | if (status == connector_status_unknown) | |
2093 | status = connector_status_connected; | |
2094 | return status; | |
2095 | } | |
01cb9ea6 | 2096 | |
26d61aad | 2097 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
2098 | } |
2099 | ||
a4fc5ed6 | 2100 | static enum drm_connector_status |
a9756bb5 | 2101 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 2102 | { |
4ef69c7a | 2103 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 2104 | struct drm_i915_private *dev_priv = dev->dev_private; |
10f76a38 | 2105 | uint32_t bit; |
5eb08b69 | 2106 | |
ea5b213a | 2107 | switch (intel_dp->output_reg) { |
a4fc5ed6 | 2108 | case DP_B: |
10f76a38 | 2109 | bit = DPB_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 KP |
2110 | break; |
2111 | case DP_C: | |
10f76a38 | 2112 | bit = DPC_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 KP |
2113 | break; |
2114 | case DP_D: | |
10f76a38 | 2115 | bit = DPD_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 KP |
2116 | break; |
2117 | default: | |
2118 | return connector_status_unknown; | |
2119 | } | |
2120 | ||
10f76a38 | 2121 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
a4fc5ed6 KP |
2122 | return connector_status_disconnected; |
2123 | ||
26d61aad | 2124 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
2125 | } |
2126 | ||
8c241fef KP |
2127 | static struct edid * |
2128 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
2129 | { | |
2130 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2131 | struct edid *edid; | |
d6f24d0f JB |
2132 | int size; |
2133 | ||
2134 | if (is_edp(intel_dp)) { | |
2135 | if (!intel_dp->edid) | |
2136 | return NULL; | |
2137 | ||
2138 | size = (intel_dp->edid->extensions + 1) * EDID_LENGTH; | |
2139 | edid = kmalloc(size, GFP_KERNEL); | |
2140 | if (!edid) | |
2141 | return NULL; | |
2142 | ||
2143 | memcpy(edid, intel_dp->edid, size); | |
2144 | return edid; | |
2145 | } | |
8c241fef | 2146 | |
8c241fef | 2147 | edid = drm_get_edid(connector, adapter); |
8c241fef KP |
2148 | return edid; |
2149 | } | |
2150 | ||
2151 | static int | |
2152 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
2153 | { | |
2154 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2155 | int ret; | |
2156 | ||
d6f24d0f JB |
2157 | if (is_edp(intel_dp)) { |
2158 | drm_mode_connector_update_edid_property(connector, | |
2159 | intel_dp->edid); | |
2160 | ret = drm_add_edid_modes(connector, intel_dp->edid); | |
2161 | drm_edid_to_eld(connector, | |
2162 | intel_dp->edid); | |
2163 | connector->display_info.raw_edid = NULL; | |
2164 | return intel_dp->edid_mode_count; | |
2165 | } | |
2166 | ||
8c241fef | 2167 | ret = intel_ddc_get_modes(connector, adapter); |
8c241fef KP |
2168 | return ret; |
2169 | } | |
2170 | ||
2171 | ||
a9756bb5 ZW |
2172 | /** |
2173 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
2174 | * | |
2175 | * \return true if DP port is connected. | |
2176 | * \return false if DP port is disconnected. | |
2177 | */ | |
2178 | static enum drm_connector_status | |
2179 | intel_dp_detect(struct drm_connector *connector, bool force) | |
2180 | { | |
2181 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2182 | struct drm_device *dev = intel_dp->base.base.dev; | |
2183 | enum drm_connector_status status; | |
2184 | struct edid *edid = NULL; | |
2185 | ||
2186 | intel_dp->has_audio = false; | |
2187 | ||
2188 | if (HAS_PCH_SPLIT(dev)) | |
2189 | status = ironlake_dp_detect(intel_dp); | |
2190 | else | |
2191 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 2192 | |
ac66ae83 AJ |
2193 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
2194 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
2195 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
2196 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 2197 | |
a9756bb5 ZW |
2198 | if (status != connector_status_connected) |
2199 | return status; | |
2200 | ||
0d198328 AJ |
2201 | intel_dp_probe_oui(intel_dp); |
2202 | ||
c3e5f67b DV |
2203 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
2204 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | |
f684960e | 2205 | } else { |
8c241fef | 2206 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
2207 | if (edid) { |
2208 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
2209 | connector->display_info.raw_edid = NULL; | |
2210 | kfree(edid); | |
2211 | } | |
a9756bb5 ZW |
2212 | } |
2213 | ||
2214 | return connector_status_connected; | |
a4fc5ed6 KP |
2215 | } |
2216 | ||
2217 | static int intel_dp_get_modes(struct drm_connector *connector) | |
2218 | { | |
df0e9248 | 2219 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 2220 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
2221 | struct drm_i915_private *dev_priv = dev->dev_private; |
2222 | int ret; | |
a4fc5ed6 KP |
2223 | |
2224 | /* We should parse the EDID data and find out if it has an audio sink | |
2225 | */ | |
2226 | ||
8c241fef | 2227 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 2228 | if (ret) { |
d15456de | 2229 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
b9efc480 ZY |
2230 | struct drm_display_mode *newmode; |
2231 | list_for_each_entry(newmode, &connector->probed_modes, | |
2232 | head) { | |
d15456de KP |
2233 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
2234 | intel_dp->panel_fixed_mode = | |
b9efc480 ZY |
2235 | drm_mode_duplicate(dev, newmode); |
2236 | break; | |
2237 | } | |
2238 | } | |
2239 | } | |
32f9d658 | 2240 | return ret; |
b9efc480 | 2241 | } |
32f9d658 ZW |
2242 | |
2243 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 2244 | if (is_edp(intel_dp)) { |
47f0eb22 | 2245 | /* initialize panel mode from VBT if available for eDP */ |
d15456de KP |
2246 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
2247 | intel_dp->panel_fixed_mode = | |
47f0eb22 | 2248 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
d15456de KP |
2249 | if (intel_dp->panel_fixed_mode) { |
2250 | intel_dp->panel_fixed_mode->type |= | |
47f0eb22 KP |
2251 | DRM_MODE_TYPE_PREFERRED; |
2252 | } | |
2253 | } | |
d15456de | 2254 | if (intel_dp->panel_fixed_mode) { |
32f9d658 | 2255 | struct drm_display_mode *mode; |
d15456de | 2256 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
32f9d658 ZW |
2257 | drm_mode_probed_add(connector, mode); |
2258 | return 1; | |
2259 | } | |
2260 | } | |
2261 | return 0; | |
a4fc5ed6 KP |
2262 | } |
2263 | ||
1aad7ac0 CW |
2264 | static bool |
2265 | intel_dp_detect_audio(struct drm_connector *connector) | |
2266 | { | |
2267 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2268 | struct edid *edid; | |
2269 | bool has_audio = false; | |
2270 | ||
8c241fef | 2271 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
2272 | if (edid) { |
2273 | has_audio = drm_detect_monitor_audio(edid); | |
2274 | ||
2275 | connector->display_info.raw_edid = NULL; | |
2276 | kfree(edid); | |
2277 | } | |
2278 | ||
2279 | return has_audio; | |
2280 | } | |
2281 | ||
f684960e CW |
2282 | static int |
2283 | intel_dp_set_property(struct drm_connector *connector, | |
2284 | struct drm_property *property, | |
2285 | uint64_t val) | |
2286 | { | |
e953fd7b | 2287 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
2288 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2289 | int ret; | |
2290 | ||
2291 | ret = drm_connector_property_set_value(connector, property, val); | |
2292 | if (ret) | |
2293 | return ret; | |
2294 | ||
3f43c48d | 2295 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2296 | int i = val; |
2297 | bool has_audio; | |
2298 | ||
2299 | if (i == intel_dp->force_audio) | |
f684960e CW |
2300 | return 0; |
2301 | ||
1aad7ac0 | 2302 | intel_dp->force_audio = i; |
f684960e | 2303 | |
c3e5f67b | 2304 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
2305 | has_audio = intel_dp_detect_audio(connector); |
2306 | else | |
c3e5f67b | 2307 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
2308 | |
2309 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2310 | return 0; |
2311 | ||
1aad7ac0 | 2312 | intel_dp->has_audio = has_audio; |
f684960e CW |
2313 | goto done; |
2314 | } | |
2315 | ||
e953fd7b CW |
2316 | if (property == dev_priv->broadcast_rgb_property) { |
2317 | if (val == !!intel_dp->color_range) | |
2318 | return 0; | |
2319 | ||
2320 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
2321 | goto done; | |
2322 | } | |
2323 | ||
f684960e CW |
2324 | return -EINVAL; |
2325 | ||
2326 | done: | |
2327 | if (intel_dp->base.base.crtc) { | |
2328 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
2329 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
2330 | crtc->x, crtc->y, | |
2331 | crtc->fb); | |
2332 | } | |
2333 | ||
2334 | return 0; | |
2335 | } | |
2336 | ||
a4fc5ed6 | 2337 | static void |
0206e353 | 2338 | intel_dp_destroy(struct drm_connector *connector) |
a4fc5ed6 | 2339 | { |
aaa6fd2a MG |
2340 | struct drm_device *dev = connector->dev; |
2341 | ||
2342 | if (intel_dpd_is_edp(dev)) | |
2343 | intel_panel_destroy_backlight(dev); | |
2344 | ||
a4fc5ed6 KP |
2345 | drm_sysfs_connector_remove(connector); |
2346 | drm_connector_cleanup(connector); | |
55f78c43 | 2347 | kfree(connector); |
a4fc5ed6 KP |
2348 | } |
2349 | ||
24d05927 DV |
2350 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2351 | { | |
2352 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2353 | ||
2354 | i2c_del_adapter(&intel_dp->adapter); | |
2355 | drm_encoder_cleanup(encoder); | |
bd943159 | 2356 | if (is_edp(intel_dp)) { |
d6f24d0f | 2357 | kfree(intel_dp->edid); |
bd943159 KP |
2358 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
2359 | ironlake_panel_vdd_off_sync(intel_dp); | |
2360 | } | |
24d05927 DV |
2361 | kfree(intel_dp); |
2362 | } | |
2363 | ||
a4fc5ed6 KP |
2364 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
2365 | .dpms = intel_dp_dpms, | |
2366 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 2367 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 2368 | .mode_set = intel_dp_mode_set, |
d240f20f | 2369 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
2370 | }; |
2371 | ||
2372 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2373 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
2374 | .detect = intel_dp_detect, |
2375 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2376 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2377 | .destroy = intel_dp_destroy, |
2378 | }; | |
2379 | ||
2380 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2381 | .get_modes = intel_dp_get_modes, | |
2382 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2383 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2384 | }; |
2385 | ||
a4fc5ed6 | 2386 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2387 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2388 | }; |
2389 | ||
995b6762 | 2390 | static void |
21d40d37 | 2391 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2392 | { |
ea5b213a | 2393 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2394 | |
885a5014 | 2395 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2396 | } |
6207937d | 2397 | |
e3421a18 ZW |
2398 | /* Return which DP Port should be selected for Transcoder DP control */ |
2399 | int | |
0206e353 | 2400 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
2401 | { |
2402 | struct drm_device *dev = crtc->dev; | |
6c2b7c12 | 2403 | struct intel_encoder *encoder; |
e3421a18 | 2404 | |
6c2b7c12 DV |
2405 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
2406 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
e3421a18 | 2407 | |
417e822d KP |
2408 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
2409 | intel_dp->base.type == INTEL_OUTPUT_EDP) | |
ea5b213a | 2410 | return intel_dp->output_reg; |
e3421a18 | 2411 | } |
ea5b213a | 2412 | |
e3421a18 ZW |
2413 | return -1; |
2414 | } | |
2415 | ||
36e83a18 | 2416 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2417 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2418 | { |
2419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2420 | struct child_device_config *p_child; | |
2421 | int i; | |
2422 | ||
2423 | if (!dev_priv->child_dev_num) | |
2424 | return false; | |
2425 | ||
2426 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2427 | p_child = dev_priv->child_dev + i; | |
2428 | ||
2429 | if (p_child->dvo_port == PORT_IDPD && | |
2430 | p_child->device_type == DEVICE_TYPE_eDP) | |
2431 | return true; | |
2432 | } | |
2433 | return false; | |
2434 | } | |
2435 | ||
f684960e CW |
2436 | static void |
2437 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2438 | { | |
3f43c48d | 2439 | intel_attach_force_audio_property(connector); |
e953fd7b | 2440 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2441 | } |
2442 | ||
a4fc5ed6 KP |
2443 | void |
2444 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2445 | { | |
2446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2447 | struct drm_connector *connector; | |
ea5b213a | 2448 | struct intel_dp *intel_dp; |
21d40d37 | 2449 | struct intel_encoder *intel_encoder; |
55f78c43 | 2450 | struct intel_connector *intel_connector; |
5eb08b69 | 2451 | const char *name = NULL; |
b329530c | 2452 | int type; |
a4fc5ed6 | 2453 | |
ea5b213a CW |
2454 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2455 | if (!intel_dp) | |
a4fc5ed6 KP |
2456 | return; |
2457 | ||
3d3dc149 | 2458 | intel_dp->output_reg = output_reg; |
d2b996ac | 2459 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2460 | |
55f78c43 ZW |
2461 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2462 | if (!intel_connector) { | |
ea5b213a | 2463 | kfree(intel_dp); |
55f78c43 ZW |
2464 | return; |
2465 | } | |
ea5b213a | 2466 | intel_encoder = &intel_dp->base; |
55f78c43 | 2467 | |
ea5b213a | 2468 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2469 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2470 | intel_dp->is_pch_edp = true; |
b329530c | 2471 | |
cfcb0fc9 | 2472 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2473 | type = DRM_MODE_CONNECTOR_eDP; |
2474 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2475 | } else { | |
2476 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2477 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2478 | } | |
2479 | ||
55f78c43 | 2480 | connector = &intel_connector->base; |
b329530c | 2481 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2482 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2483 | ||
eb1f8e4f DA |
2484 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2485 | ||
652af9d7 | 2486 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2487 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2488 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2489 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2490 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2491 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2492 | |
bd943159 | 2493 | if (is_edp(intel_dp)) { |
21d40d37 | 2494 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
bd943159 KP |
2495 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2496 | ironlake_panel_vdd_work); | |
2497 | } | |
6251ec0a | 2498 | |
27f8227b | 2499 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
ee7b9f93 | 2500 | |
a4fc5ed6 KP |
2501 | connector->interlace_allowed = true; |
2502 | connector->doublescan_allowed = 0; | |
2503 | ||
4ef69c7a | 2504 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2505 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2506 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2507 | |
df0e9248 | 2508 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2509 | drm_sysfs_connector_add(connector); |
2510 | ||
2511 | /* Set up the DDC bus. */ | |
5eb08b69 | 2512 | switch (output_reg) { |
32f9d658 ZW |
2513 | case DP_A: |
2514 | name = "DPDDC-A"; | |
2515 | break; | |
5eb08b69 ZW |
2516 | case DP_B: |
2517 | case PCH_DP_B: | |
b01f2c3a | 2518 | dev_priv->hotplug_supported_mask |= |
78d56d78 | 2519 | DPB_HOTPLUG_INT_STATUS; |
5eb08b69 ZW |
2520 | name = "DPDDC-B"; |
2521 | break; | |
2522 | case DP_C: | |
2523 | case PCH_DP_C: | |
b01f2c3a | 2524 | dev_priv->hotplug_supported_mask |= |
78d56d78 | 2525 | DPC_HOTPLUG_INT_STATUS; |
5eb08b69 ZW |
2526 | name = "DPDDC-C"; |
2527 | break; | |
2528 | case DP_D: | |
2529 | case PCH_DP_D: | |
b01f2c3a | 2530 | dev_priv->hotplug_supported_mask |= |
78d56d78 | 2531 | DPD_HOTPLUG_INT_STATUS; |
5eb08b69 ZW |
2532 | name = "DPDDC-D"; |
2533 | break; | |
2534 | } | |
2535 | ||
d6f24d0f JB |
2536 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2537 | ||
89667383 JB |
2538 | /* Cache some DPCD data in the eDP case */ |
2539 | if (is_edp(intel_dp)) { | |
59f3e272 | 2540 | bool ret; |
f01eca2e KP |
2541 | struct edp_power_seq cur, vbt; |
2542 | u32 pp_on, pp_off, pp_div; | |
d6f24d0f | 2543 | struct edid *edid; |
5d613501 JB |
2544 | |
2545 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2546 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2547 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2548 | |
bfa3384a JB |
2549 | if (!pp_on || !pp_off || !pp_div) { |
2550 | DRM_INFO("bad panel power sequencing delays, disabling panel\n"); | |
2551 | intel_dp_encoder_destroy(&intel_dp->base.base); | |
2552 | intel_dp_destroy(&intel_connector->base); | |
2553 | return; | |
2554 | } | |
2555 | ||
f01eca2e KP |
2556 | /* Pull timing values out of registers */ |
2557 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2558 | PANEL_POWER_UP_DELAY_SHIFT; | |
2559 | ||
2560 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2561 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
f2e8b18a | 2562 | |
f01eca2e KP |
2563 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
2564 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2565 | ||
2566 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2567 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2568 | ||
2569 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2570 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2571 | ||
2572 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2573 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2574 | ||
2575 | vbt = dev_priv->edp.pps; | |
2576 | ||
2577 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2578 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2579 | ||
2580 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2581 | ||
2582 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2583 | intel_dp->backlight_on_delay = get_delay(t8); | |
2584 | intel_dp->backlight_off_delay = get_delay(t9); | |
2585 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2586 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2587 | ||
2588 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2589 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2590 | intel_dp->panel_power_cycle_delay); | |
2591 | ||
2592 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2593 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 JB |
2594 | |
2595 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2596 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 2597 | ironlake_edp_panel_vdd_off(intel_dp, false); |
99ea7127 | 2598 | |
59f3e272 | 2599 | if (ret) { |
7183dc29 JB |
2600 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2601 | dev_priv->no_aux_handshake = | |
2602 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2603 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2604 | } else { | |
3d3dc149 | 2605 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2606 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2607 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2608 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2609 | return; |
89667383 | 2610 | } |
89667383 | 2611 | |
d6f24d0f JB |
2612 | ironlake_edp_panel_vdd_on(intel_dp); |
2613 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
2614 | if (edid) { | |
2615 | drm_mode_connector_update_edid_property(connector, | |
2616 | edid); | |
2617 | intel_dp->edid_mode_count = | |
2618 | drm_add_edid_modes(connector, edid); | |
2619 | drm_edid_to_eld(connector, edid); | |
2620 | intel_dp->edid = edid; | |
2621 | } | |
2622 | ironlake_edp_panel_vdd_off(intel_dp, false); | |
2623 | } | |
552fb0b7 | 2624 | |
21d40d37 | 2625 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2626 | |
4d926461 | 2627 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2628 | dev_priv->int_edp_connector = connector; |
2629 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2630 | } |
2631 | ||
f684960e CW |
2632 | intel_dp_add_properties(intel_dp, connector); |
2633 | ||
a4fc5ed6 KP |
2634 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2635 | * 0xd. Failure to do so will result in spurious interrupts being | |
2636 | * generated on the port when a cable is not attached. | |
2637 | */ | |
2638 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2639 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2640 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2641 | } | |
2642 | } |