]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/gpu/drm/i915/intel_dp.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/lvds: move fitting mode from intel_lvds_connector to intel_panel
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
50 return intel_dp->base.type == INTEL_OUTPUT_EDP;
51}
52
53/**
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
56 *
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
60 */
61static bool is_pch_edp(struct intel_dp *intel_dp)
62{
63 return intel_dp->is_pch_edp;
64}
65
1c95822a
AJ		 66/**
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
69 *
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
71 */
72static bool is_cpu_edp(struct intel_dp *intel_dp)
73{
74 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
75}
76
df0e9248
CW		 77static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
78{
79 return container_of(intel_attached_encoder(connector),
80 struct intel_dp, base);
81}
82
814948ad
JB		 83/**
84 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
85 * @encoder: DRM encoder
86 *
87 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
88 * by intel_display.c.
89 */
90bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
91{
92 struct intel_dp *intel_dp;
93
94 if (!encoder)
95 return false;
96
97 intel_dp = enc_to_intel_dp(encoder);
98
99 return is_pch_edp(intel_dp);
100}
101
ea5b213a 102static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 103
32f9d658 104void
0206e353 105intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 106 int *lane_num, int *link_bw)
32f9d658 107{
ea5b213a 108 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 109
ea5b213a 110 *lane_num = intel_dp->lane_count;
3b5c662e 111 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 112}
113
94bf2ced
DV		 114int
115intel_edp_target_clock(struct intel_encoder *intel_encoder,
116 struct drm_display_mode *mode)
117{
118 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
dd06f90e 119 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 120
dd06f90e
JN		 121 if (intel_connector->panel.fixed_mode)
122 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 123 else
124 return mode->clock;
125}
126
a4fc5ed6 127static int
ea5b213a 128intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 129{
7183dc29 130 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 131
132 switch (max_link_bw) {
133 case DP_LINK_BW_1_62:
134 case DP_LINK_BW_2_7:
135 break;
136 default:
137 max_link_bw = DP_LINK_BW_1_62;
138 break;
139 }
140 return max_link_bw;
141}
142
143static int
144intel_dp_link_clock(uint8_t link_bw)
145{
146 if (link_bw == DP_LINK_BW_2_7)
147 return 270000;
148 else
149 return 162000;
150}
151
cd9dde44
AJ		 152/*
153 * The units on the numbers in the next two are... bizarre. Examples will
154 * make it clearer; this one parallels an example in the eDP spec.
155 *
156 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
157 *
158 * 270000 * 1 * 8 / 10 == 216000
159 *
160 * The actual data capacity of that configuration is 2.16Gbit/s, so the
161 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
162 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
163 * 119000. At 18bpp that's 2142000 kilobits per second.
164 *
165 * Thus the strange-looking division by 10 in intel_dp_link_required, to
166 * get the result in decakilobits instead of kilobits.
167 */
168
a4fc5ed6 169static int
c898261c 170intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 171{
cd9dde44 172 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 173}
174
fe27d53e
DA		 175static int
176intel_dp_max_data_rate(int max_link_clock, int max_lanes)
177{
178 return (max_link_clock * max_lanes * 8) / 10;
179}
180
c4867936
DV		 181static bool
182intel_dp_adjust_dithering(struct intel_dp *intel_dp,
183 struct drm_display_mode *mode,
cb1793ce 184 bool adjust_mode)
c4867936
DV		 185{
186 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
295 struct drm_device *dev = intel_dp->base.base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
303 struct drm_device *dev = intel_dp->base.base.dev;
304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
312 struct drm_device *dev = intel_dp->base.base.dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
a4fc5ed6 325static int
ea5b213a 326intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 327 uint8_t *send, int send_bytes,
328 uint8_t *recv, int recv_size)
329{
ea5b213a 330 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 331 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 332 struct drm_i915_private *dev_priv = dev->dev_private;
333 uint32_t ch_ctl = output_reg + 0x10;
334 uint32_t ch_data = ch_ctl + 4;
335 int i;
336 int recv_bytes;
a4fc5ed6 337 uint32_t status;
fb0f8fbf 338 uint32_t aux_clock_divider;
6b4e0a93 339 int try, precharge;
a4fc5ed6 340
750eb99e
PZ		 341 if (IS_HASWELL(dev)) {
342 switch (intel_dp->port) {
343 case PORT_A:
344 ch_ctl = DPA_AUX_CH_CTL;
345 ch_data = DPA_AUX_CH_DATA1;
346 break;
347 case PORT_B:
348 ch_ctl = PCH_DPB_AUX_CH_CTL;
349 ch_data = PCH_DPB_AUX_CH_DATA1;
350 break;
351 case PORT_C:
352 ch_ctl = PCH_DPC_AUX_CH_CTL;
353 ch_data = PCH_DPC_AUX_CH_DATA1;
354 break;
355 case PORT_D:
356 ch_ctl = PCH_DPD_AUX_CH_CTL;
357 ch_data = PCH_DPD_AUX_CH_DATA1;
358 break;
359 default:
360 BUG();
361 }
362 }
363
9b984dae 364 intel_dp_check_edp(intel_dp);
a4fc5ed6 365 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 368 *
369 * Note that PCH attached eDP panels should use a 125MHz input
370 * clock divider.
a4fc5ed6 371 */
1c95822a 372 if (is_cpu_edp(intel_dp)) {
b8fc2f6a
PZ		 373 if (IS_HASWELL(dev))
374 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
375 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 376 aux_clock_divider = 100;
377 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 378 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 379 else
380 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
381 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 382 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 383 else
384 aux_clock_divider = intel_hrawclk(dev) / 2;
385
6b4e0a93
DV		 386 if (IS_GEN6(dev))
387 precharge = 3;
388 else
389 precharge = 5;
390
11bee43e
JB		 391 /* Try to wait for any previous AUX channel activity */
392 for (try = 0; try < 3; try++) {
393 status = I915_READ(ch_ctl);
394 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
395 break;
396 msleep(1);
397 }
398
399 if (try == 3) {
400 WARN(1, "dp_aux_ch not started status 0x%08x\n",
401 I915_READ(ch_ctl));
4f7f7b7e
CW		 402 return -EBUSY;
403 }
404
fb0f8fbf
KP		 405 /* Must try at least 3 times according to DP spec */
406 for (try = 0; try < 5; try++) {
407 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 408 for (i = 0; i < send_bytes; i += 4)
409 I915_WRITE(ch_data + i,
410 pack_aux(send + i, send_bytes - i));
0206e353 411
fb0f8fbf 412 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 413 I915_WRITE(ch_ctl,
414 DP_AUX_CH_CTL_SEND_BUSY |
415 DP_AUX_CH_CTL_TIME_OUT_400us |
416 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
417 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
418 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
419 DP_AUX_CH_CTL_DONE |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR |
421 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 422 for (;;) {
fb0f8fbf
KP		 423 status = I915_READ(ch_ctl);
424 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
425 break;
4f7f7b7e 426 udelay(100);
fb0f8fbf 427 }
0206e353 428
fb0f8fbf 429 /* Clear done status and any errors */
4f7f7b7e
CW		 430 I915_WRITE(ch_ctl,
431 status |
432 DP_AUX_CH_CTL_DONE |
433 DP_AUX_CH_CTL_TIME_OUT_ERROR |
434 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 435
436 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR))
438 continue;
4f7f7b7e 439 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 440 break;
441 }
442
a4fc5ed6 443 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 444 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 445 return -EBUSY;
a4fc5ed6
KP		 446 }
447
448 /* Check for timeout or receive error.
449 * Timeouts occur when the sink is not connected
450 */
a5b3da54 451 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 452 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 453 return -EIO;
454 }
1ae8c0a5
KP		 455
456 /* Timeouts occur when the device isn't connected, so they're
457 * "normal" -- don't fill the kernel log with these */
a5b3da54 458 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 459 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 460 return -ETIMEDOUT;
a4fc5ed6
KP		 461 }
462
463 /* Unload any bytes sent back from the other side */
464 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
465 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 466 if (recv_bytes > recv_size)
467 recv_bytes = recv_size;
0206e353 468
4f7f7b7e
CW		 469 for (i = 0; i < recv_bytes; i += 4)
470 unpack_aux(I915_READ(ch_data + i),
471 recv + i, recv_bytes - i);
a4fc5ed6
KP		 472
473 return recv_bytes;
474}
475
476/* Write data to the aux channel in native mode */
477static int
ea5b213a 478intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 479 uint16_t address, uint8_t *send, int send_bytes)
480{
481 int ret;
482 uint8_t msg[20];
483 int msg_bytes;
484 uint8_t ack;
485
9b984dae 486 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 487 if (send_bytes > 16)
488 return -1;
489 msg[0] = AUX_NATIVE_WRITE << 4;
490 msg[1] = address >> 8;
eebc863e 491 msg[2] = address & 0xff;
a4fc5ed6
KP		 492 msg[3] = send_bytes - 1;
493 memcpy(&msg[4], send, send_bytes);
494 msg_bytes = send_bytes + 4;
495 for (;;) {
ea5b213a 496 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 497 if (ret < 0)
498 return ret;
499 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
500 break;
501 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
502 udelay(100);
503 else
a5b3da54 504 return -EIO;
a4fc5ed6
KP		 505 }
506 return send_bytes;
507}
508
509/* Write a single byte to the aux channel in native mode */
510static int
ea5b213a 511intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 512 uint16_t address, uint8_t byte)
513{
ea5b213a 514 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 515}
516
517/* read bytes from a native aux channel */
518static int
ea5b213a 519intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 520 uint16_t address, uint8_t *recv, int recv_bytes)
521{
522 uint8_t msg[4];
523 int msg_bytes;
524 uint8_t reply[20];
525 int reply_bytes;
526 uint8_t ack;
527 int ret;
528
9b984dae 529 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 530 msg[0] = AUX_NATIVE_READ << 4;
531 msg[1] = address >> 8;
532 msg[2] = address & 0xff;
533 msg[3] = recv_bytes - 1;
534
535 msg_bytes = 4;
536 reply_bytes = recv_bytes + 1;
537
538 for (;;) {
ea5b213a 539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 540 reply, reply_bytes);
a5b3da54
KP		 541 if (ret == 0)
542 return -EPROTO;
543 if (ret < 0)
a4fc5ed6
KP		 544 return ret;
545 ack = reply[0];
546 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
547 memcpy(recv, reply + 1, ret - 1);
548 return ret - 1;
549 }
550 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
551 udelay(100);
552 else
a5b3da54 553 return -EIO;
a4fc5ed6
KP		 554 }
555}
556
557static int
ab2c0672
DA		 558intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
559 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 560{
ab2c0672 561 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 562 struct intel_dp *intel_dp = container_of(adapter,
563 struct intel_dp,
564 adapter);
ab2c0672
DA		 565 uint16_t address = algo_data->address;
566 uint8_t msg[5];
567 uint8_t reply[2];
8316f337 568 unsigned retry;
ab2c0672
DA		 569 int msg_bytes;
570 int reply_bytes;
571 int ret;
572
9b984dae 573 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 574 /* Set up the command byte */
575 if (mode & MODE_I2C_READ)
576 msg[0] = AUX_I2C_READ << 4;
577 else
578 msg[0] = AUX_I2C_WRITE << 4;
579
580 if (!(mode & MODE_I2C_STOP))
581 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 582
ab2c0672
DA		 583 msg[1] = address >> 8;
584 msg[2] = address;
585
586 switch (mode) {
587 case MODE_I2C_WRITE:
588 msg[3] = 0;
589 msg[4] = write_byte;
590 msg_bytes = 5;
591 reply_bytes = 1;
592 break;
593 case MODE_I2C_READ:
594 msg[3] = 0;
595 msg_bytes = 4;
596 reply_bytes = 2;
597 break;
598 default:
599 msg_bytes = 3;
600 reply_bytes = 1;
601 break;
602 }
603
8316f337
DF		 604 for (retry = 0; retry < 5; retry++) {
605 ret = intel_dp_aux_ch(intel_dp,
606 msg, msg_bytes,
607 reply, reply_bytes);
ab2c0672 608 if (ret < 0) {
3ff99164 609 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 610 return ret;
611 }
8316f337
DF		 612
613 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
614 case AUX_NATIVE_REPLY_ACK:
615 /* I2C-over-AUX Reply field is only valid
616 * when paired with AUX ACK.
617 */
618 break;
619 case AUX_NATIVE_REPLY_NACK:
620 DRM_DEBUG_KMS("aux_ch native nack\n");
621 return -EREMOTEIO;
622 case AUX_NATIVE_REPLY_DEFER:
623 udelay(100);
624 continue;
625 default:
626 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
627 reply[0]);
628 return -EREMOTEIO;
629 }
630
ab2c0672
DA		 631 switch (reply[0] & AUX_I2C_REPLY_MASK) {
632 case AUX_I2C_REPLY_ACK:
633 if (mode == MODE_I2C_READ) {
634 *read_byte = reply[1];
635 }
636 return reply_bytes - 1;
637 case AUX_I2C_REPLY_NACK:
8316f337 638 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 639 return -EREMOTEIO;
640 case AUX_I2C_REPLY_DEFER:
8316f337 641 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 642 udelay(100);
643 break;
644 default:
8316f337 645 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 646 return -EREMOTEIO;
647 }
648 }
8316f337
DF		 649
650 DRM_ERROR("too many retries, giving up\n");
651 return -EREMOTEIO;
a4fc5ed6
KP		 652}
653
654static int
ea5b213a 655intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 656 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 657{
0b5c541b
KP		 658 int ret;
659
d54e9d28 660 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 661 intel_dp->algo.running = false;
662 intel_dp->algo.address = 0;
663 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
664
0206e353 665 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 666 intel_dp->adapter.owner = THIS_MODULE;
667 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 668 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 669 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
670 intel_dp->adapter.algo_data = &intel_dp->algo;
671 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
672
0b5c541b
KP		 673 ironlake_edp_panel_vdd_on(intel_dp);
674 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 675 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 676 return ret;
a4fc5ed6
KP		 677}
678
679static bool
e811f5ae
LP		 680intel_dp_mode_fixup(struct drm_encoder *encoder,
681 const struct drm_display_mode *mode,
a4fc5ed6
KP		 682 struct drm_display_mode *adjusted_mode)
683{
0d3a1bee 684 struct drm_device *dev = encoder->dev;
ea5b213a 685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 686 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 687 int lane_count, clock;
397fe157 688 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 689 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 690 int bpp, mode_rate;
a4fc5ed6
KP		 691 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
692
dd06f90e
JN		 693 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
694 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
695 adjusted_mode);
1d8e1c75
CW		 696 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
697 mode, adjusted_mode);
0d3a1bee
ZY		 698 }
699
cb1793ce 700 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 701 return false;
702
083f9560
DV		 703 DRM_DEBUG_KMS("DP link computation with max lane count %i "
704 "max bw %02x pixel clock %iKHz\n",
71244653 705 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 706
cb1793ce 707 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 708 return false;
709
710 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 711 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 712
2514bc51
JB		 713 for (clock = 0; clock <= max_clock; clock++) {
714 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 715 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 716
083f9560 717 if (mode_rate <= link_avail) {
ea5b213a
CW		 718 intel_dp->link_bw = bws[clock];
719 intel_dp->lane_count = lane_count;
720 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 721 DRM_DEBUG_KMS("DP link bw %02x lane "
722 "count %d clock %d bpp %d\n",
ea5b213a 723 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 724 adjusted_mode->clock, bpp);
725 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
726 mode_rate, link_avail);
a4fc5ed6
KP		 727 return true;
728 }
729 }
730 }
fe27d53e 731
a4fc5ed6
KP		 732 return false;
733}
734
735struct intel_dp_m_n {
736 uint32_t tu;
737 uint32_t gmch_m;
738 uint32_t gmch_n;
739 uint32_t link_m;
740 uint32_t link_n;
741};
742
743static void
744intel_reduce_ratio(uint32_t *num, uint32_t *den)
745{
746 while (*num > 0xffffff || *den > 0xffffff) {
747 *num >>= 1;
748 *den >>= 1;
749 }
750}
751
752static void
36e83a18 753intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 754 int nlanes,
755 int pixel_clock,
756 int link_clock,
757 struct intel_dp_m_n *m_n)
758{
759 m_n->tu = 64;
36e83a18 760 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 761 m_n->gmch_n = link_clock * nlanes;
762 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
763 m_n->link_m = pixel_clock;
764 m_n->link_n = link_clock;
765 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
766}
767
768void
769intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
770 struct drm_display_mode *adjusted_mode)
771{
772 struct drm_device *dev = crtc->dev;
6c2b7c12 773 struct intel_encoder *encoder;
a4fc5ed6
KP		 774 struct drm_i915_private *dev_priv = dev->dev_private;
775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 776 int lane_count = 4;
a4fc5ed6 777 struct intel_dp_m_n m_n;
9db4a9c7 778 int pipe = intel_crtc->pipe;
afe2fcf5 779 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 780
781 /*
21d40d37 782 * Find the lane count in the intel_encoder private
a4fc5ed6 783 */
6c2b7c12
DV		 784 for_each_encoder_on_crtc(dev, crtc, encoder) {
785 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 786
9a10f401
KP		 787 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
788 intel_dp->base.type == INTEL_OUTPUT_EDP)
789 {
ea5b213a 790 lane_count = intel_dp->lane_count;
51190667 791 break;
a4fc5ed6
KP		 792 }
793 }
794
795 /*
796 * Compute the GMCH and Link ratios. The '3' here is
797 * the number of bytes_per_pixel post-LUT, which we always
798 * set up for 8-bits of R/G/B, or 3 bytes total.
799 */
858fa035 800 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 801 mode->clock, adjusted_mode->clock, &m_n);
802
1eb8dfec 803 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 804 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
805 TU_SIZE(m_n.tu) | m_n.gmch_m);
806 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
807 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
808 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 809 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 810 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 811 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
812 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
813 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 814 } else if (IS_VALLEYVIEW(dev)) {
815 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
816 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
817 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
818 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 819 } else {
9db4a9c7 820 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 821 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 822 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
823 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
824 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 825 }
826}
827
247d89f6
PZ		 828void intel_dp_init_link_config(struct intel_dp *intel_dp)
829{
830 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
831 intel_dp->link_configuration[0] = intel_dp->link_bw;
832 intel_dp->link_configuration[1] = intel_dp->lane_count;
833 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
834 /*
835 * Check for DPCD version > 1.1 and enhanced framing support
836 */
837 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
838 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
839 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
840 }
841}
842
a4fc5ed6
KP		 843static void
844intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
845 struct drm_display_mode *adjusted_mode)
846{
e3421a18 847 struct drm_device *dev = encoder->dev;
417e822d 848 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 849 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 850 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
852
417e822d 853 /*
1a2eb460 854 * There are four kinds of DP registers:
417e822d
KP		 855 *
856 * IBX PCH
1a2eb460
KP		 857 * SNB CPU
858 * IVB CPU
417e822d
KP		 859 * CPT PCH
860 *
861 * IBX PCH and CPU are the same for almost everything,
862 * except that the CPU DP PLL is configured in this
863 * register
864 *
865 * CPT PCH is quite different, having many bits moved
866 * to the TRANS_DP_CTL register instead. That
867 * configuration happens (oddly) in ironlake_pch_enable
868 */
9c9e7927 869
417e822d
KP		 870 /* Preserve the BIOS-computed detected bit. This is
871 * supposed to be read-only.
872 */
873 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 874
417e822d 875 /* Handle DP bits in common between all three register formats */
417e822d 876 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 877
ea5b213a 878 switch (intel_dp->lane_count) {
a4fc5ed6 879 case 1:
ea5b213a 880 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 881 break;
882 case 2:
ea5b213a 883 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 884 break;
885 case 4:
ea5b213a 886 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 887 break;
888 }
e0dac65e
WF		 889 if (intel_dp->has_audio) {
890 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
891 pipe_name(intel_crtc->pipe));
ea5b213a 892 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 893 intel_write_eld(encoder, adjusted_mode);
894 }
247d89f6
PZ		 895
896 intel_dp_init_link_config(intel_dp);
a4fc5ed6 897
417e822d 898 /* Split out the IBX/CPU vs CPT settings */
32f9d658 899
19c03924 900 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 901 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
902 intel_dp->DP |= DP_SYNC_HS_HIGH;
903 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
904 intel_dp->DP |= DP_SYNC_VS_HIGH;
905 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
906
907 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
908 intel_dp->DP |= DP_ENHANCED_FRAMING;
909
910 intel_dp->DP |= intel_crtc->pipe << 29;
911
912 /* don't miss out required setting for eDP */
1a2eb460
KP		 913 if (adjusted_mode->clock < 200000)
914 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
915 else
916 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
917 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 918 intel_dp->DP |= intel_dp->color_range;
919
920 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
921 intel_dp->DP |= DP_SYNC_HS_HIGH;
922 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
923 intel_dp->DP |= DP_SYNC_VS_HIGH;
924 intel_dp->DP |= DP_LINK_TRAIN_OFF;
925
926 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
927 intel_dp->DP |= DP_ENHANCED_FRAMING;
928
929 if (intel_crtc->pipe == 1)
930 intel_dp->DP |= DP_PIPEB_SELECT;
931
932 if (is_cpu_edp(intel_dp)) {
933 /* don't miss out required setting for eDP */
417e822d
KP		 934 if (adjusted_mode->clock < 200000)
935 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
936 else
937 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
938 }
939 } else {
940 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 941 }
a4fc5ed6
KP		 942}
943
99ea7127
KP		 944#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
945#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
946
947#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
948#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
949
950#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
951#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
952
953static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
954 u32 mask,
955 u32 value)
bd943159 956{
99ea7127
KP		 957 struct drm_device *dev = intel_dp->base.base.dev;
958 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 959
99ea7127
KP		 960 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
961 mask, value,
962 I915_READ(PCH_PP_STATUS),
963 I915_READ(PCH_PP_CONTROL));
32ce697c 964
99ea7127
KP		 965 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
966 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
967 I915_READ(PCH_PP_STATUS),
968 I915_READ(PCH_PP_CONTROL));
32ce697c 969 }
99ea7127 970}
32ce697c 971
99ea7127
KP		 972static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
973{
974 DRM_DEBUG_KMS("Wait for panel power on\n");
975 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 976}
977
99ea7127
KP		 978static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
979{
980 DRM_DEBUG_KMS("Wait for panel power off time\n");
981 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
982}
983
984static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
985{
986 DRM_DEBUG_KMS("Wait for panel power cycle\n");
987 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
988}
989
990
832dd3c1
KP		 991/* Read the current pp_control value, unlocking the register if it
992 * is locked
993 */
994
995static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
996{
997 u32 control = I915_READ(PCH_PP_CONTROL);
998
999 control &= ~PANEL_UNLOCK_MASK;
1000 control |= PANEL_UNLOCK_REGS;
1001 return control;
bd943159
KP		 1002}
1003
82a4d9c0 1004void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501
JB		 1005{
1006 struct drm_device *dev = intel_dp->base.base.dev;
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 u32 pp;
1009
97af61f5
KP		 1010 if (!is_edp(intel_dp))
1011 return;
f01eca2e 1012 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1013
bd943159
KP		 1014 WARN(intel_dp->want_panel_vdd,
1015 "eDP VDD already requested on\n");
1016
1017 intel_dp->want_panel_vdd = true;
99ea7127 1018
bd943159
KP		 1019 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1020 DRM_DEBUG_KMS("eDP VDD already on\n");
1021 return;
1022 }
1023
99ea7127
KP		 1024 if (!ironlake_edp_have_panel_power(intel_dp))
1025 ironlake_wait_panel_power_cycle(intel_dp);
1026
832dd3c1 1027 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1028 pp |= EDP_FORCE_VDD;
1029 I915_WRITE(PCH_PP_CONTROL, pp);
1030 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1031 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1032 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1033
1034 /*
1035 * If the panel wasn't on, delay before accessing aux channel
1036 */
1037 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1038 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1039 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1040 }
5d613501
JB		 1041}
1042
bd943159 1043static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1044{
1045 struct drm_device *dev = intel_dp->base.base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 u32 pp;
1048
bd943159 1049 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1050 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1051 pp &= ~EDP_FORCE_VDD;
1052 I915_WRITE(PCH_PP_CONTROL, pp);
1053 POSTING_READ(PCH_PP_CONTROL);
1054
1055 /* Make sure sequencer is idle before allowing subsequent activity */
1056 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1057 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1058
1059 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1060 }
1061}
5d613501 1062
bd943159
KP		 1063static void ironlake_panel_vdd_work(struct work_struct *__work)
1064{
1065 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1066 struct intel_dp, panel_vdd_work);
1067 struct drm_device *dev = intel_dp->base.base.dev;
1068
627f7675 1069 mutex_lock(&dev->mode_config.mutex);
bd943159 1070 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1071 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1072}
1073
82a4d9c0 1074void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1075{
97af61f5
KP		 1076 if (!is_edp(intel_dp))
1077 return;
5d613501 1078
bd943159
KP		 1079 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1080 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1081
bd943159
KP		 1082 intel_dp->want_panel_vdd = false;
1083
1084 if (sync) {
1085 ironlake_panel_vdd_off_sync(intel_dp);
1086 } else {
1087 /*
1088 * Queue the timer to fire a long
1089 * time from now (relative to the power down delay)
1090 * to keep the panel power up across a sequence of operations
1091 */
1092 schedule_delayed_work(&intel_dp->panel_vdd_work,
1093 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1094 }
5d613501
JB		 1095}
1096
82a4d9c0 1097void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1098{
01cb9ea6 1099 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1100 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1101 u32 pp;
9934c132 1102
97af61f5 1103 if (!is_edp(intel_dp))
bd943159 1104 return;
99ea7127
KP		 1105
1106 DRM_DEBUG_KMS("Turn eDP power on\n");
1107
1108 if (ironlake_edp_have_panel_power(intel_dp)) {
1109 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1110 return;
99ea7127 1111 }
9934c132 1112
99ea7127 1113 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1114
99ea7127 1115 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1116 if (IS_GEN5(dev)) {
1117 /* ILK workaround: disable reset around power sequence */
1118 pp &= ~PANEL_POWER_RESET;
1119 I915_WRITE(PCH_PP_CONTROL, pp);
1120 POSTING_READ(PCH_PP_CONTROL);
1121 }
37c6c9b0 1122
1c0ae80a 1123 pp |= POWER_TARGET_ON;
99ea7127
KP		 1124 if (!IS_GEN5(dev))
1125 pp |= PANEL_POWER_RESET;
1126
9934c132 1127 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1128 POSTING_READ(PCH_PP_CONTROL);
9934c132 1129
99ea7127 1130 ironlake_wait_panel_on(intel_dp);
9934c132 1131
05ce1a49
KP		 1132 if (IS_GEN5(dev)) {
1133 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1134 I915_WRITE(PCH_PP_CONTROL, pp);
1135 POSTING_READ(PCH_PP_CONTROL);
1136 }
9934c132
JB		 1137}
1138
82a4d9c0 1139void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1140{
99ea7127 1141 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1142 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1143 u32 pp;
9934c132 1144
97af61f5
KP		 1145 if (!is_edp(intel_dp))
1146 return;
37c6c9b0 1147
99ea7127 1148 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1149
6cb49835 1150 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1151
99ea7127 1152 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1153 /* We need to switch off panel power _and_ force vdd, for otherwise some
1154 * panels get very unhappy and cease to work. */
1155 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1156 I915_WRITE(PCH_PP_CONTROL, pp);
1157 POSTING_READ(PCH_PP_CONTROL);
9934c132 1158
35a38556
DV		 1159 intel_dp->want_panel_vdd = false;
1160
99ea7127 1161 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1162}
1163
d6c50ff8 1164void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1165{
f01eca2e 1166 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 1167 struct drm_i915_private *dev_priv = dev->dev_private;
035aa3de 1168 int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
32f9d658
ZW		 1169 u32 pp;
1170
f01eca2e
KP		 1171 if (!is_edp(intel_dp))
1172 return;
1173
28c97730 1174 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1175 /*
1176 * If we enable the backlight right away following a panel power
1177 * on, we may see slight flicker as the panel syncs with the eDP
1178 * link. So delay a bit to make sure the image is solid before
1179 * allowing it to appear.
1180 */
f01eca2e 1181 msleep(intel_dp->backlight_on_delay);
832dd3c1 1182 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1183 pp |= EDP_BLC_ENABLE;
1184 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1185 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1186
1187 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1188}
1189
d6c50ff8 1190void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1191{
f01eca2e 1192 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1193 struct drm_i915_private *dev_priv = dev->dev_private;
1194 u32 pp;
1195
f01eca2e
KP		 1196 if (!is_edp(intel_dp))
1197 return;
1198
035aa3de
DV		 1199 intel_panel_disable_backlight(dev);
1200
28c97730 1201 DRM_DEBUG_KMS("\n");
832dd3c1 1202 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1203 pp &= ~EDP_BLC_ENABLE;
1204 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1205 POSTING_READ(PCH_PP_CONTROL);
1206 msleep(intel_dp->backlight_off_delay);
32f9d658 1207}
a4fc5ed6 1208
2bd2ad64 1209static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1210{
2bd2ad64
DV		 1211 struct drm_device *dev = intel_dp->base.base.dev;
1212 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 u32 dpa_ctl;
1215
2bd2ad64
DV		 1216 assert_pipe_disabled(dev_priv,
1217 to_intel_crtc(crtc)->pipe);
1218
d240f20f
JB		 1219 DRM_DEBUG_KMS("\n");
1220 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1221 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1222 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1223
1224 /* We don't adjust intel_dp->DP while tearing down the link, to
1225 * facilitate link retraining (e.g. after hotplug). Hence clear all
1226 * enable bits here to ensure that we don't enable too much. */
1227 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1228 intel_dp->DP |= DP_PLL_ENABLE;
1229 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1230 POSTING_READ(DP_A);
1231 udelay(200);
d240f20f
JB		 1232}
1233
2bd2ad64 1234static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1235{
2bd2ad64
DV		 1236 struct drm_device *dev = intel_dp->base.base.dev;
1237 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 u32 dpa_ctl;
1240
2bd2ad64
DV		 1241 assert_pipe_disabled(dev_priv,
1242 to_intel_crtc(crtc)->pipe);
1243
d240f20f 1244 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1245 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1246 "dp pll off, should be on\n");
1247 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1248
1249 /* We can't rely on the value tracked for the DP register in
1250 * intel_dp->DP because link_down must not change that (otherwise link
1251 * re-training will fail. */
298b0b39 1252 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1253 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1254 POSTING_READ(DP_A);
d240f20f
JB		 1255 udelay(200);
1256}
1257
c7ad3810 1258/* If the sink supports it, try to set the power state appropriately */
c19b0669 1259void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1260{
1261 int ret, i;
1262
1263 /* Should have a valid DPCD by this point */
1264 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1265 return;
1266
1267 if (mode != DRM_MODE_DPMS_ON) {
1268 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1269 DP_SET_POWER_D3);
1270 if (ret != 1)
1271 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1272 } else {
1273 /*
1274 * When turning on, we need to retry for 1ms to give the sink
1275 * time to wake up.
1276 */
1277 for (i = 0; i < 3; i++) {
1278 ret = intel_dp_aux_native_write_1(intel_dp,
1279 DP_SET_POWER,
1280 DP_SET_POWER_D0);
1281 if (ret == 1)
1282 break;
1283 msleep(1);
1284 }
1285 }
1286}
1287
19d8fe15
DV		 1288static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1289 enum pipe *pipe)
d240f20f 1290{
19d8fe15
DV		 1291 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1292 struct drm_device *dev = encoder->base.dev;
1293 struct drm_i915_private *dev_priv = dev->dev_private;
1294 u32 tmp = I915_READ(intel_dp->output_reg);
1295
1296 if (!(tmp & DP_PORT_EN))
1297 return false;
1298
1299 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1300 *pipe = PORT_TO_PIPE_CPT(tmp);
1301 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1302 *pipe = PORT_TO_PIPE(tmp);
1303 } else {
1304 u32 trans_sel;
1305 u32 trans_dp;
1306 int i;
1307
1308 switch (intel_dp->output_reg) {
1309 case PCH_DP_B:
1310 trans_sel = TRANS_DP_PORT_SEL_B;
1311 break;
1312 case PCH_DP_C:
1313 trans_sel = TRANS_DP_PORT_SEL_C;
1314 break;
1315 case PCH_DP_D:
1316 trans_sel = TRANS_DP_PORT_SEL_D;
1317 break;
1318 default:
1319 return true;
1320 }
1321
1322 for_each_pipe(i) {
1323 trans_dp = I915_READ(TRANS_DP_CTL(i));
1324 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1325 *pipe = i;
1326 return true;
1327 }
1328 }
1329 }
1330
1331 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1332
19d8fe15
DV		 1333 return true;
1334}
1335
e8cb4558 1336static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1337{
e8cb4558 1338 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1339
1340 /* Make sure the panel is off before trying to change the mode. But also
1341 * ensure that we have vdd while we switch off the panel. */
1342 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1343 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1344 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1345 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1346
1347 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1348 if (!is_cpu_edp(intel_dp))
1349 intel_dp_link_down(intel_dp);
d240f20f
JB		 1350}
1351
2bd2ad64
DV		 1352static void intel_post_disable_dp(struct intel_encoder *encoder)
1353{
1354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1355
3739850b
DV		 1356 if (is_cpu_edp(intel_dp)) {
1357 intel_dp_link_down(intel_dp);
2bd2ad64 1358 ironlake_edp_pll_off(intel_dp);
3739850b 1359 }
2bd2ad64
DV		 1360}
1361
e8cb4558 1362static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1363{
e8cb4558
DV		 1364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1365 struct drm_device *dev = encoder->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1368
0c33d8d7
DV		 1369 if (WARN_ON(dp_reg & DP_PORT_EN))
1370 return;
1371
97af61f5 1372 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1373 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1374 intel_dp_start_link_train(intel_dp);
1375 ironlake_edp_panel_on(intel_dp);
1376 ironlake_edp_panel_vdd_off(intel_dp, true);
1377 intel_dp_complete_link_train(intel_dp);
f01eca2e 1378 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1379}
1380
2bd2ad64 1381static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1382{
2bd2ad64 1383 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1384
2bd2ad64
DV		 1385 if (is_cpu_edp(intel_dp))
1386 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1387}
1388
1389/*
df0c237d
JB		 1390 * Native read with retry for link status and receiver capability reads for
1391 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1392 */
1393static bool
df0c237d
JB		 1394intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1395 uint8_t *recv, int recv_bytes)
a4fc5ed6 1396{
61da5fab
JB		 1397 int ret, i;
1398
df0c237d
JB		 1399 /*
1400 * Sinks are *supposed* to come up within 1ms from an off state,
1401 * but we're also supposed to retry 3 times per the spec.
1402 */
61da5fab 1403 for (i = 0; i < 3; i++) {
df0c237d
JB		 1404 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1405 recv_bytes);
1406 if (ret == recv_bytes)
61da5fab
JB		 1407 return true;
1408 msleep(1);
1409 }
a4fc5ed6 1410
61da5fab 1411 return false;
a4fc5ed6
KP		 1412}
1413
1414/*
1415 * Fetch AUX CH registers 0x202 - 0x207 which contain
1416 * link status information
1417 */
1418static bool
93f62dad 1419intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1420{
df0c237d
JB		 1421 return intel_dp_aux_native_read_retry(intel_dp,
1422 DP_LANE0_1_STATUS,
93f62dad 1423 link_status,
df0c237d 1424 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1425}
1426
a4fc5ed6
KP		 1427#if 0
1428static char *voltage_names[] = {
1429 "0.4V", "0.6V", "0.8V", "1.2V"
1430};
1431static char *pre_emph_names[] = {
1432 "0dB", "3.5dB", "6dB", "9.5dB"
1433};
1434static char *link_train_names[] = {
1435 "pattern 1", "pattern 2", "idle", "off"
1436};
1437#endif
1438
1439/*
1440 * These are source-specific values; current Intel hardware supports
1441 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1442 */
a4fc5ed6
KP		 1443
1444static uint8_t
1a2eb460 1445intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1446{
1a2eb460
KP		 1447 struct drm_device *dev = intel_dp->base.base.dev;
1448
1449 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1450 return DP_TRAIN_VOLTAGE_SWING_800;
1451 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1452 return DP_TRAIN_VOLTAGE_SWING_1200;
1453 else
1454 return DP_TRAIN_VOLTAGE_SWING_800;
1455}
1456
1457static uint8_t
1458intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1459{
1460 struct drm_device *dev = intel_dp->base.base.dev;
1461
d6c0d722
PZ		 1462 if (IS_HASWELL(dev)) {
1463 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1464 case DP_TRAIN_VOLTAGE_SWING_400:
1465 return DP_TRAIN_PRE_EMPHASIS_9_5;
1466 case DP_TRAIN_VOLTAGE_SWING_600:
1467 return DP_TRAIN_PRE_EMPHASIS_6;
1468 case DP_TRAIN_VOLTAGE_SWING_800:
1469 return DP_TRAIN_PRE_EMPHASIS_3_5;
1470 case DP_TRAIN_VOLTAGE_SWING_1200:
1471 default:
1472 return DP_TRAIN_PRE_EMPHASIS_0;
1473 }
1474 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1475 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1476 case DP_TRAIN_VOLTAGE_SWING_400:
1477 return DP_TRAIN_PRE_EMPHASIS_6;
1478 case DP_TRAIN_VOLTAGE_SWING_600:
1479 case DP_TRAIN_VOLTAGE_SWING_800:
1480 return DP_TRAIN_PRE_EMPHASIS_3_5;
1481 default:
1482 return DP_TRAIN_PRE_EMPHASIS_0;
1483 }
1484 } else {
1485 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1486 case DP_TRAIN_VOLTAGE_SWING_400:
1487 return DP_TRAIN_PRE_EMPHASIS_6;
1488 case DP_TRAIN_VOLTAGE_SWING_600:
1489 return DP_TRAIN_PRE_EMPHASIS_6;
1490 case DP_TRAIN_VOLTAGE_SWING_800:
1491 return DP_TRAIN_PRE_EMPHASIS_3_5;
1492 case DP_TRAIN_VOLTAGE_SWING_1200:
1493 default:
1494 return DP_TRAIN_PRE_EMPHASIS_0;
1495 }
a4fc5ed6
KP		 1496 }
1497}
1498
1499static void
93f62dad 1500intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1501{
1502 uint8_t v = 0;
1503 uint8_t p = 0;
1504 int lane;
1a2eb460
KP		 1505 uint8_t voltage_max;
1506 uint8_t preemph_max;
a4fc5ed6 1507
33a34e4e 1508 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1509 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1510 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1511
1512 if (this_v > v)
1513 v = this_v;
1514 if (this_p > p)
1515 p = this_p;
1516 }
1517
1a2eb460 1518 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1519 if (v >= voltage_max)
1520 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1521
1a2eb460
KP		 1522 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1523 if (p >= preemph_max)
1524 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1525
1526 for (lane = 0; lane < 4; lane++)
33a34e4e 1527 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1528}
1529
1530static uint32_t
93f62dad 1531intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1532{
3cf2efb1 1533 uint32_t signal_levels = 0;
a4fc5ed6 1534
3cf2efb1 1535 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1536 case DP_TRAIN_VOLTAGE_SWING_400:
1537 default:
1538 signal_levels |= DP_VOLTAGE_0_4;
1539 break;
1540 case DP_TRAIN_VOLTAGE_SWING_600:
1541 signal_levels |= DP_VOLTAGE_0_6;
1542 break;
1543 case DP_TRAIN_VOLTAGE_SWING_800:
1544 signal_levels |= DP_VOLTAGE_0_8;
1545 break;
1546 case DP_TRAIN_VOLTAGE_SWING_1200:
1547 signal_levels |= DP_VOLTAGE_1_2;
1548 break;
1549 }
3cf2efb1 1550 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1551 case DP_TRAIN_PRE_EMPHASIS_0:
1552 default:
1553 signal_levels |= DP_PRE_EMPHASIS_0;
1554 break;
1555 case DP_TRAIN_PRE_EMPHASIS_3_5:
1556 signal_levels |= DP_PRE_EMPHASIS_3_5;
1557 break;
1558 case DP_TRAIN_PRE_EMPHASIS_6:
1559 signal_levels |= DP_PRE_EMPHASIS_6;
1560 break;
1561 case DP_TRAIN_PRE_EMPHASIS_9_5:
1562 signal_levels |= DP_PRE_EMPHASIS_9_5;
1563 break;
1564 }
1565 return signal_levels;
1566}
1567
e3421a18
ZW		 1568/* Gen6's DP voltage swing and pre-emphasis control */
1569static uint32_t
1570intel_gen6_edp_signal_levels(uint8_t train_set)
1571{
3c5a62b5
YL		 1572 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1573 DP_TRAIN_PRE_EMPHASIS_MASK);
1574 switch (signal_levels) {
e3421a18 1575 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1576 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1577 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1578 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1579 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1580 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1581 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1582 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1583 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1584 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1585 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1586 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1587 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1588 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1589 default:
3c5a62b5
YL		 1590 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1591 "0x%x\n", signal_levels);
1592 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1593 }
1594}
1595
1a2eb460
KP		 1596/* Gen7's DP voltage swing and pre-emphasis control */
1597static uint32_t
1598intel_gen7_edp_signal_levels(uint8_t train_set)
1599{
1600 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1601 DP_TRAIN_PRE_EMPHASIS_MASK);
1602 switch (signal_levels) {
1603 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1604 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1605 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1606 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1607 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1608 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1609
1610 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1611 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1612 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1613 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1614
1615 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1616 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1617 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1618 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1619
1620 default:
1621 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1622 "0x%x\n", signal_levels);
1623 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1624 }
1625}
1626
d6c0d722
PZ		 1627/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1628static uint32_t
1629intel_dp_signal_levels_hsw(uint8_t train_set)
1630{
1631 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1632 DP_TRAIN_PRE_EMPHASIS_MASK);
1633 switch (signal_levels) {
1634 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1635 return DDI_BUF_EMP_400MV_0DB_HSW;
1636 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1637 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1638 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1639 return DDI_BUF_EMP_400MV_6DB_HSW;
1640 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1641 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1642
1643 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1644 return DDI_BUF_EMP_600MV_0DB_HSW;
1645 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1646 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1647 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1648 return DDI_BUF_EMP_600MV_6DB_HSW;
1649
1650 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1651 return DDI_BUF_EMP_800MV_0DB_HSW;
1652 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1653 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1654 default:
1655 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1656 "0x%x\n", signal_levels);
1657 return DDI_BUF_EMP_400MV_0DB_HSW;
1658 }
1659}
1660
a4fc5ed6 1661static bool
ea5b213a 1662intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1663 uint32_t dp_reg_value,
58e10eb9 1664 uint8_t dp_train_pat)
a4fc5ed6 1665{
4ef69c7a 1666 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1667 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1668 int ret;
d6c0d722 1669 uint32_t temp;
a4fc5ed6 1670
d6c0d722
PZ		 1671 if (IS_HASWELL(dev)) {
1672 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1673
1674 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1675 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1676 else
1677 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1678
1679 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1680 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1681 case DP_TRAINING_PATTERN_DISABLE:
1682 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1683 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1684
1685 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1686 DP_TP_STATUS_IDLE_DONE), 1))
1687 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1688
1689 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1690 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1691
1692 break;
1693 case DP_TRAINING_PATTERN_1:
1694 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1695 break;
1696 case DP_TRAINING_PATTERN_2:
1697 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1698 break;
1699 case DP_TRAINING_PATTERN_3:
1700 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1701 break;
1702 }
1703 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1704
1705 } else if (HAS_PCH_CPT(dev) &&
1706 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1707 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1708
1709 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1710 case DP_TRAINING_PATTERN_DISABLE:
1711 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1712 break;
1713 case DP_TRAINING_PATTERN_1:
1714 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1715 break;
1716 case DP_TRAINING_PATTERN_2:
1717 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1718 break;
1719 case DP_TRAINING_PATTERN_3:
1720 DRM_ERROR("DP training pattern 3 not supported\n");
1721 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1722 break;
1723 }
1724
1725 } else {
1726 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1727
1728 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1729 case DP_TRAINING_PATTERN_DISABLE:
1730 dp_reg_value |= DP_LINK_TRAIN_OFF;
1731 break;
1732 case DP_TRAINING_PATTERN_1:
1733 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1734 break;
1735 case DP_TRAINING_PATTERN_2:
1736 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1737 break;
1738 case DP_TRAINING_PATTERN_3:
1739 DRM_ERROR("DP training pattern 3 not supported\n");
1740 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1741 break;
1742 }
1743 }
1744
ea5b213a
CW		 1745 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1746 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1747
ea5b213a 1748 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1749 DP_TRAINING_PATTERN_SET,
1750 dp_train_pat);
1751
47ea7542
PZ		 1752 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1753 DP_TRAINING_PATTERN_DISABLE) {
1754 ret = intel_dp_aux_native_write(intel_dp,
1755 DP_TRAINING_LANE0_SET,
1756 intel_dp->train_set,
1757 intel_dp->lane_count);
1758 if (ret != intel_dp->lane_count)
1759 return false;
1760 }
a4fc5ed6
KP		 1761
1762 return true;
1763}
1764
33a34e4e 1765/* Enable corresponding port and start training pattern 1 */
c19b0669 1766void
33a34e4e 1767intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1768{
c19b0669
PZ		 1769 struct drm_encoder *encoder = &intel_dp->base.base;
1770 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1771 int i;
1772 uint8_t voltage;
1773 bool clock_recovery = false;
cdb0e95b 1774 int voltage_tries, loop_tries;
ea5b213a 1775 uint32_t DP = intel_dp->DP;
a4fc5ed6 1776
c19b0669
PZ		 1777 if (IS_HASWELL(dev))
1778 intel_ddi_prepare_link_retrain(encoder);
1779
3cf2efb1
CW		 1780 /* Write the link configuration data */
1781 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1782 intel_dp->link_configuration,
1783 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1784
1785 DP |= DP_PORT_EN;
1a2eb460 1786
33a34e4e 1787 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1788 voltage = 0xff;
cdb0e95b
KP		 1789 voltage_tries = 0;
1790 loop_tries = 0;
a4fc5ed6
KP		 1791 clock_recovery = false;
1792 for (;;) {
33a34e4e 1793 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1794 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1795 uint32_t signal_levels;
417e822d 1796
d6c0d722
PZ		 1797 if (IS_HASWELL(dev)) {
1798 signal_levels = intel_dp_signal_levels_hsw(
1799 intel_dp->train_set[0]);
1800 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1801 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1802 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1803 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1804 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1805 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1806 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1807 } else {
93f62dad 1808 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1809 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1810 }
d6c0d722
PZ		 1811 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1812 signal_levels);
a4fc5ed6 1813
a7c9655f 1814 /* Set training pattern 1 */
47ea7542 1815 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1816 DP_TRAINING_PATTERN_1 |
1817 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1818 break;
a4fc5ed6 1819
a7c9655f 1820 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1821 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1822 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1823 break;
93f62dad 1824 }
a4fc5ed6 1825
01916270 1826 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1827 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1828 clock_recovery = true;
1829 break;
1830 }
1831
1832 /* Check to see if we've tried the max voltage */
1833 for (i = 0; i < intel_dp->lane_count; i++)
1834 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1835 break;
0d710688 1836 if (i == intel_dp->lane_count && voltage_tries == 5) {
24773670 1837 if (++loop_tries == 5) {
cdb0e95b
KP		 1838 DRM_DEBUG_KMS("too many full retries, give up\n");
1839 break;
1840 }
1841 memset(intel_dp->train_set, 0, 4);
1842 voltage_tries = 0;
1843 continue;
1844 }
a4fc5ed6 1845
3cf2efb1 1846 /* Check to see if we've tried the same voltage 5 times */
24773670
CW		 1847 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1848 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
cdb0e95b 1849 voltage_tries = 0;
24773670
CW		 1850 } else
1851 ++voltage_tries;
a4fc5ed6 1852
3cf2efb1 1853 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1854 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1855 }
1856
33a34e4e
JB		 1857 intel_dp->DP = DP;
1858}
1859
c19b0669 1860void
33a34e4e
JB		 1861intel_dp_complete_link_train(struct intel_dp *intel_dp)
1862{
4ef69c7a 1863 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1864 bool channel_eq = false;
37f80975 1865 int tries, cr_tries;
33a34e4e
JB		 1866 uint32_t DP = intel_dp->DP;
1867
a4fc5ed6
KP		 1868 /* channel equalization */
1869 tries = 0;
37f80975 1870 cr_tries = 0;
a4fc5ed6
KP		 1871 channel_eq = false;
1872 for (;;) {
33a34e4e 1873 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1874 uint32_t signal_levels;
93f62dad 1875 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1876
37f80975
JB		 1877 if (cr_tries > 5) {
1878 DRM_ERROR("failed to train DP, aborting\n");
1879 intel_dp_link_down(intel_dp);
1880 break;
1881 }
1882
d6c0d722
PZ		 1883 if (IS_HASWELL(dev)) {
1884 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1885 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1886 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1887 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1888 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1889 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1890 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1891 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1892 } else {
93f62dad 1893 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1894 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1895 }
1896
a4fc5ed6 1897 /* channel eq pattern */
47ea7542 1898 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1899 DP_TRAINING_PATTERN_2 |
1900 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1901 break;
1902
a7c9655f 1903 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1904 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1905 break;
a4fc5ed6 1906
37f80975 1907 /* Make sure clock is still ok */
01916270 1908 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1909 intel_dp_start_link_train(intel_dp);
1910 cr_tries++;
1911 continue;
1912 }
1913
1ffdff13 1914 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1915 channel_eq = true;
1916 break;
1917 }
a4fc5ed6 1918
37f80975
JB		 1919 /* Try 5 times, then try clock recovery if that fails */
1920 if (tries > 5) {
1921 intel_dp_link_down(intel_dp);
1922 intel_dp_start_link_train(intel_dp);
1923 tries = 0;
1924 cr_tries++;
1925 continue;
1926 }
a4fc5ed6 1927
3cf2efb1 1928 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1929 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1930 ++tries;
869184a6 1931 }
3cf2efb1 1932
d6c0d722
PZ		 1933 if (channel_eq)
1934 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1935
47ea7542 1936 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1937}
1938
1939static void
ea5b213a 1940intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1941{
4ef69c7a 1942 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1943 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1944 uint32_t DP = intel_dp->DP;
a4fc5ed6 1945
c19b0669
PZ		 1946 /*
1947 * DDI code has a strict mode set sequence and we should try to respect
1948 * it, otherwise we might hang the machine in many different ways. So we
1949 * really should be disabling the port only on a complete crtc_disable
1950 * sequence. This function is just called under two conditions on DDI
1951 * code:
1952 * - Link train failed while doing crtc_enable, and on this case we
1953 * really should respect the mode set sequence and wait for a
1954 * crtc_disable.
1955 * - Someone turned the monitor off and intel_dp_check_link_status
1956 * called us. We don't need to disable the whole port on this case, so
1957 * when someone turns the monitor on again,
1958 * intel_ddi_prepare_link_retrain will take care of redoing the link
1959 * train.
1960 */
1961 if (IS_HASWELL(dev))
1962 return;
1963
0c33d8d7 1964 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1965 return;
1966
28c97730 1967 DRM_DEBUG_KMS("\n");
32f9d658 1968
1a2eb460 1969 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1970 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1971 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1972 } else {
1973 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1974 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1975 }
fe255d00 1976 POSTING_READ(intel_dp->output_reg);
5eb08b69 1977
fe255d00 1978 msleep(17);
5eb08b69 1979
493a7081 1980 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1981 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1982 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1983
5bddd17f
EA		 1984 /* Hardware workaround: leaving our transcoder select
1985 * set to transcoder B while it's off will prevent the
1986 * corresponding HDMI output on transcoder A.
1987 *
1988 * Combine this with another hardware workaround:
1989 * transcoder select bit can only be cleared while the
1990 * port is enabled.
1991 */
1992 DP &= ~DP_PIPEB_SELECT;
1993 I915_WRITE(intel_dp->output_reg, DP);
1994
1995 /* Changes to enable or select take place the vblank
1996 * after being written.
1997 */
31acbcc4
CW		 1998 if (crtc == NULL) {
1999 /* We can arrive here never having been attached
2000 * to a CRTC, for instance, due to inheriting
2001 * random state from the BIOS.
2002 *
2003 * If the pipe is not running, play safe and
2004 * wait for the clocks to stabilise before
2005 * continuing.
2006 */
2007 POSTING_READ(intel_dp->output_reg);
2008 msleep(50);
2009 } else
2010 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2011 }
2012
832afda6 2013 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2014 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2015 POSTING_READ(intel_dp->output_reg);
f01eca2e 2016 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2017}
2018
26d61aad
KP		 2019static bool
2020intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2021{
92fd8fd1 2022 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2023 sizeof(intel_dp->dpcd)) == 0)
2024 return false; /* aux transfer failed */
92fd8fd1 2025
b091cd92
AJ		 2026 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2027 return false; /* DPCD not present */
2028
2029 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2030 DP_DWN_STRM_PORT_PRESENT))
2031 return true; /* native DP sink */
2032
2033 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2034 return true; /* no per-port downstream info */
2035
2036 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2037 intel_dp->downstream_ports,
2038 DP_MAX_DOWNSTREAM_PORTS) == 0)
2039 return false; /* downstream port status fetch failed */
2040
2041 return true;
92fd8fd1
KP		 2042}
2043
0d198328
AJ		 2044static void
2045intel_dp_probe_oui(struct intel_dp *intel_dp)
2046{
2047 u8 buf[3];
2048
2049 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2050 return;
2051
351cfc34
DV		 2052 ironlake_edp_panel_vdd_on(intel_dp);
2053
0d198328
AJ		 2054 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2055 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2056 buf[0], buf[1], buf[2]);
2057
2058 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2059 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2060 buf[0], buf[1], buf[2]);
351cfc34
DV		 2061
2062 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2063}
2064
a60f0e38
JB		 2065static bool
2066intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2067{
2068 int ret;
2069
2070 ret = intel_dp_aux_native_read_retry(intel_dp,
2071 DP_DEVICE_SERVICE_IRQ_VECTOR,
2072 sink_irq_vector, 1);
2073 if (!ret)
2074 return false;
2075
2076 return true;
2077}
2078
2079static void
2080intel_dp_handle_test_request(struct intel_dp *intel_dp)
2081{
2082 /* NAK by default */
9324cf7f 2083 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2084}
2085
a4fc5ed6
KP		 2086/*
2087 * According to DP spec
2088 * 5.1.2:
2089 * 1. Read DPCD
2090 * 2. Configure link according to Receiver Capabilities
2091 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2092 * 4. Check link status on receipt of hot-plug interrupt
2093 */
2094
2095static void
ea5b213a 2096intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2097{
a60f0e38 2098 u8 sink_irq_vector;
93f62dad 2099 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2100
24e804ba 2101 if (!intel_dp->base.connectors_active)
d2b996ac 2102 return;
59cd09e1 2103
24e804ba 2104 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2105 return;
2106
92fd8fd1 2107 /* Try to read receiver status if the link appears to be up */
93f62dad 2108 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2109 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2110 return;
2111 }
2112
92fd8fd1 2113 /* Now read the DPCD to see if it's actually running */
26d61aad 2114 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2115 intel_dp_link_down(intel_dp);
2116 return;
2117 }
2118
a60f0e38
JB		 2119 /* Try to read the source of the interrupt */
2120 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2121 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2122 /* Clear interrupt source */
2123 intel_dp_aux_native_write_1(intel_dp,
2124 DP_DEVICE_SERVICE_IRQ_VECTOR,
2125 sink_irq_vector);
2126
2127 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2128 intel_dp_handle_test_request(intel_dp);
2129 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2130 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2131 }
2132
1ffdff13 2133 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1
KP		 2134 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2135 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2136 intel_dp_start_link_train(intel_dp);
2137 intel_dp_complete_link_train(intel_dp);
2138 }
a4fc5ed6 2139}
a4fc5ed6 2140
07d3dc18 2141/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2142static enum drm_connector_status
26d61aad 2143intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2144{
07d3dc18
AJ		 2145 uint8_t *dpcd = intel_dp->dpcd;
2146 bool hpd;
2147 uint8_t type;
2148
2149 if (!intel_dp_get_dpcd(intel_dp))
2150 return connector_status_disconnected;
2151
2152 /* if there's no downstream port, we're done */
2153 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2154 return connector_status_connected;
2155
2156 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2157 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2158 if (hpd) {
da131a46 2159 uint8_t reg;
07d3dc18 2160 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2161 &reg, 1))
07d3dc18 2162 return connector_status_unknown;
da131a46
AJ		 2163 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2164 : connector_status_disconnected;
07d3dc18
AJ		 2165 }
2166
2167 /* If no HPD, poke DDC gently */
2168 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2169 return connector_status_connected;
07d3dc18
AJ		 2170
2171 /* Well we tried, say unknown for unreliable port types */
2172 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2173 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2174 return connector_status_unknown;
2175
2176 /* Anything else is out of spec, warn and ignore */
2177 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2178 return connector_status_disconnected;
71ba9000
AJ		 2179}
2180
5eb08b69 2181static enum drm_connector_status
a9756bb5 2182ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2183{
5eb08b69
ZW		 2184 enum drm_connector_status status;
2185
fe16d949
CW		 2186 /* Can't disconnect eDP, but you can close the lid... */
2187 if (is_edp(intel_dp)) {
2188 status = intel_panel_detect(intel_dp->base.base.dev);
2189 if (status == connector_status_unknown)
2190 status = connector_status_connected;
2191 return status;
2192 }
01cb9ea6 2193
26d61aad 2194 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2195}
2196
a4fc5ed6 2197static enum drm_connector_status
a9756bb5 2198g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2199{
4ef69c7a 2200 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2201 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2202 uint32_t bit;
5eb08b69 2203
ea5b213a 2204 switch (intel_dp->output_reg) {
a4fc5ed6 2205 case DP_B:
10f76a38 2206 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2207 break;
2208 case DP_C:
10f76a38 2209 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2210 break;
2211 case DP_D:
10f76a38 2212 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2213 break;
2214 default:
2215 return connector_status_unknown;
2216 }
2217
10f76a38 2218 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2219 return connector_status_disconnected;
2220
26d61aad 2221 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2222}
2223
8c241fef
KP		 2224static struct edid *
2225intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2226{
9cd300e0 2227 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2228
9cd300e0
JN		 2229 /* use cached edid if we have one */
2230 if (intel_connector->edid) {
2231 struct edid *edid;
2232 int size;
2233
2234 /* invalid edid */
2235 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2236 return NULL;
2237
9cd300e0 2238 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2239 edid = kmalloc(size, GFP_KERNEL);
2240 if (!edid)
2241 return NULL;
2242
9cd300e0 2243 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2244 return edid;
2245 }
8c241fef 2246
9cd300e0 2247 return drm_get_edid(connector, adapter);
8c241fef
KP		 2248}
2249
2250static int
2251intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2252{
9cd300e0 2253 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2254
9cd300e0
JN		 2255 /* use cached edid if we have one */
2256 if (intel_connector->edid) {
2257 /* invalid edid */
2258 if (IS_ERR(intel_connector->edid))
2259 return 0;
2260
2261 return intel_connector_update_modes(connector,
2262 intel_connector->edid);
d6f24d0f
JB		 2263 }
2264
9cd300e0 2265 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2266}
2267
2268
a9756bb5
ZW		 2269/**
2270 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2271 *
2272 * \return true if DP port is connected.
2273 * \return false if DP port is disconnected.
2274 */
2275static enum drm_connector_status
2276intel_dp_detect(struct drm_connector *connector, bool force)
2277{
2278 struct intel_dp *intel_dp = intel_attached_dp(connector);
2279 struct drm_device *dev = intel_dp->base.base.dev;
2280 enum drm_connector_status status;
2281 struct edid *edid = NULL;
898076ed 2282 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
a9756bb5
ZW		 2283
2284 intel_dp->has_audio = false;
2285
2286 if (HAS_PCH_SPLIT(dev))
2287 status = ironlake_dp_detect(intel_dp);
2288 else
2289 status = g4x_dp_detect(intel_dp);
1b9be9d0 2290
898076ed
JN		 2291 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2292 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2293 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
1b9be9d0 2294
a9756bb5
ZW		 2295 if (status != connector_status_connected)
2296 return status;
2297
0d198328
AJ		 2298 intel_dp_probe_oui(intel_dp);
2299
c3e5f67b
DV		 2300 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2301 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2302 } else {
8c241fef 2303 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2304 if (edid) {
2305 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2306 kfree(edid);
2307 }
a9756bb5
ZW		 2308 }
2309
2310 return connector_status_connected;
a4fc5ed6
KP		 2311}
2312
2313static int intel_dp_get_modes(struct drm_connector *connector)
2314{
df0e9248 2315 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2316 struct intel_connector *intel_connector = to_intel_connector(connector);
4ef69c7a 2317 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 2318 int ret;
a4fc5ed6
KP		 2319
2320 /* We should parse the EDID data and find out if it has an audio sink
2321 */
2322
8c241fef 2323 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2324 if (ret)
32f9d658
ZW		 2325 return ret;
2326
f8779fda 2327 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2328 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2329 struct drm_display_mode *mode;
dd06f90e
JN		 2330 mode = drm_mode_duplicate(dev,
2331 intel_connector->panel.fixed_mode);
f8779fda 2332 if (mode) {
32f9d658
ZW		 2333 drm_mode_probed_add(connector, mode);
2334 return 1;
2335 }
2336 }
2337 return 0;
a4fc5ed6
KP		 2338}
2339
1aad7ac0
CW		 2340static bool
2341intel_dp_detect_audio(struct drm_connector *connector)
2342{
2343 struct intel_dp *intel_dp = intel_attached_dp(connector);
2344 struct edid *edid;
2345 bool has_audio = false;
2346
8c241fef 2347 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2348 if (edid) {
2349 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2350 kfree(edid);
2351 }
2352
2353 return has_audio;
2354}
2355
f684960e
CW		 2356static int
2357intel_dp_set_property(struct drm_connector *connector,
2358 struct drm_property *property,
2359 uint64_t val)
2360{
e953fd7b 2361 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2362 struct intel_dp *intel_dp = intel_attached_dp(connector);
2363 int ret;
2364
2365 ret = drm_connector_property_set_value(connector, property, val);
2366 if (ret)
2367 return ret;
2368
3f43c48d 2369 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2370 int i = val;
2371 bool has_audio;
2372
2373 if (i == intel_dp->force_audio)
f684960e
CW		 2374 return 0;
2375
1aad7ac0 2376 intel_dp->force_audio = i;
f684960e 2377
c3e5f67b 2378 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2379 has_audio = intel_dp_detect_audio(connector);
2380 else
c3e5f67b 2381 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2382
2383 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2384 return 0;
2385
1aad7ac0 2386 intel_dp->has_audio = has_audio;
f684960e
CW		 2387 goto done;
2388 }
2389
e953fd7b
CW		 2390 if (property == dev_priv->broadcast_rgb_property) {
2391 if (val == !!intel_dp->color_range)
2392 return 0;
2393
2394 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2395 goto done;
2396 }
2397
f684960e
CW		 2398 return -EINVAL;
2399
2400done:
2401 if (intel_dp->base.base.crtc) {
2402 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2403 intel_set_mode(crtc, &crtc->mode,
2404 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2405 }
2406
2407 return 0;
2408}
2409
a4fc5ed6 2410static void
0206e353 2411intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2412{
aaa6fd2a 2413 struct drm_device *dev = connector->dev;
be3cd5e3 2414 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2415 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2416
9cd300e0
JN		 2417 if (!IS_ERR_OR_NULL(intel_connector->edid))
2418 kfree(intel_connector->edid);
2419
1d508706 2420 if (is_edp(intel_dp)) {
aaa6fd2a 2421 intel_panel_destroy_backlight(dev);
1d508706
JN		 2422 intel_panel_fini(&intel_connector->panel);
2423 }
aaa6fd2a 2424
a4fc5ed6
KP		 2425 drm_sysfs_connector_remove(connector);
2426 drm_connector_cleanup(connector);
55f78c43 2427 kfree(connector);
a4fc5ed6
KP		 2428}
2429
24d05927
DV		 2430static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2431{
2432 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2433
2434 i2c_del_adapter(&intel_dp->adapter);
2435 drm_encoder_cleanup(encoder);
bd943159
KP		 2436 if (is_edp(intel_dp)) {
2437 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2438 ironlake_panel_vdd_off_sync(intel_dp);
2439 }
24d05927
DV		 2440 kfree(intel_dp);
2441}
2442
a4fc5ed6 2443static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2444 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2445 .mode_set = intel_dp_mode_set,
1f703855 2446 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2447};
2448
a7902ac5
PZ		 2449static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2450 .mode_fixup = intel_dp_mode_fixup,
2451 .mode_set = intel_ddi_mode_set,
2452 .disable = intel_encoder_noop,
2453};
2454
a4fc5ed6 2455static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2456 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2457 .detect = intel_dp_detect,
2458 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2459 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2460 .destroy = intel_dp_destroy,
2461};
2462
2463static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2464 .get_modes = intel_dp_get_modes,
2465 .mode_valid = intel_dp_mode_valid,
df0e9248 2466 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2467};
2468
a4fc5ed6 2469static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2470 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2471};
2472
995b6762 2473static void
21d40d37 2474intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2475{
ea5b213a 2476 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2477
885a5014 2478 intel_dp_check_link_status(intel_dp);
c8110e52 2479}
6207937d 2480
e3421a18
ZW		 2481/* Return which DP Port should be selected for Transcoder DP control */
2482int
0206e353 2483intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2484{
2485 struct drm_device *dev = crtc->dev;
6c2b7c12 2486 struct intel_encoder *encoder;
e3421a18 2487
6c2b7c12
DV		 2488 for_each_encoder_on_crtc(dev, crtc, encoder) {
2489 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2490
417e822d
KP		 2491 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2492 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2493 return intel_dp->output_reg;
e3421a18 2494 }
ea5b213a 2495
e3421a18
ZW		 2496 return -1;
2497}
2498
36e83a18 2499/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2500bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2501{
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 struct child_device_config *p_child;
2504 int i;
2505
2506 if (!dev_priv->child_dev_num)
2507 return false;
2508
2509 for (i = 0; i < dev_priv->child_dev_num; i++) {
2510 p_child = dev_priv->child_dev + i;
2511
2512 if (p_child->dvo_port == PORT_IDPD &&
2513 p_child->device_type == DEVICE_TYPE_eDP)
2514 return true;
2515 }
2516 return false;
2517}
2518
f684960e
CW		 2519static void
2520intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2521{
3f43c48d 2522 intel_attach_force_audio_property(connector);
e953fd7b 2523 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2524}
2525
67a54566
DV		 2526static void
2527intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2528 struct intel_dp *intel_dp)
2529{
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 struct edp_power_seq cur, vbt, spec, final;
2532 u32 pp_on, pp_off, pp_div, pp;
2533
2534 /* Workaround: Need to write PP_CONTROL with the unlock key as
2535 * the very first thing. */
2536 pp = ironlake_get_pp_control(dev_priv);
2537 I915_WRITE(PCH_PP_CONTROL, pp);
2538
2539 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2540 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2541 pp_div = I915_READ(PCH_PP_DIVISOR);
2542
2543 /* Pull timing values out of registers */
2544 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2545 PANEL_POWER_UP_DELAY_SHIFT;
2546
2547 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2548 PANEL_LIGHT_ON_DELAY_SHIFT;
2549
2550 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2551 PANEL_LIGHT_OFF_DELAY_SHIFT;
2552
2553 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2554 PANEL_POWER_DOWN_DELAY_SHIFT;
2555
2556 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2557 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2558
2559 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2560 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2561
2562 vbt = dev_priv->edp.pps;
2563
2564 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2565 * our hw here, which are all in 100usec. */
2566 spec.t1_t3 = 210 * 10;
2567 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2568 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2569 spec.t10 = 500 * 10;
2570 /* This one is special and actually in units of 100ms, but zero
2571 * based in the hw (so we need to add 100 ms). But the sw vbt
2572 * table multiplies it with 1000 to make it in units of 100usec,
2573 * too. */
2574 spec.t11_t12 = (510 + 100) * 10;
2575
2576 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2577 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2578
2579 /* Use the max of the register settings and vbt. If both are
2580 * unset, fall back to the spec limits. */
2581#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2582 spec.field : \
2583 max(cur.field, vbt.field))
2584 assign_final(t1_t3);
2585 assign_final(t8);
2586 assign_final(t9);
2587 assign_final(t10);
2588 assign_final(t11_t12);
2589#undef assign_final
2590
2591#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2592 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2593 intel_dp->backlight_on_delay = get_delay(t8);
2594 intel_dp->backlight_off_delay = get_delay(t9);
2595 intel_dp->panel_power_down_delay = get_delay(t10);
2596 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2597#undef get_delay
2598
2599 /* And finally store the new values in the power sequencer. */
2600 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2601 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2602 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2603 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2604 /* Compute the divisor for the pp clock, simply match the Bspec
2605 * formula. */
2606 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2607 << PP_REFERENCE_DIVIDER_SHIFT;
2608 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2609 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2610
2611 /* Haswell doesn't have any port selection bits for the panel
2612 * power sequencer any more. */
2613 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2614 if (is_cpu_edp(intel_dp))
2615 pp_on |= PANEL_POWER_PORT_DP_A;
2616 else
2617 pp_on |= PANEL_POWER_PORT_DP_D;
2618 }
2619
2620 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2621 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2622 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2623
2624
2625 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2626 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2627 intel_dp->panel_power_cycle_delay);
2628
2629 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2630 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2631
2632 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2633 I915_READ(PCH_PP_ON_DELAYS),
2634 I915_READ(PCH_PP_OFF_DELAYS),
2635 I915_READ(PCH_PP_DIVISOR));
2636}
2637
a4fc5ed6 2638void
ab9d7c30 2639intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2640{
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct drm_connector *connector;
ea5b213a 2643 struct intel_dp *intel_dp;
21d40d37 2644 struct intel_encoder *intel_encoder;
55f78c43 2645 struct intel_connector *intel_connector;
f8779fda 2646 struct drm_display_mode *fixed_mode = NULL;
5eb08b69 2647 const char *name = NULL;
b329530c 2648 int type;
a4fc5ed6 2649
ea5b213a
CW		 2650 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2651 if (!intel_dp)
a4fc5ed6
KP		 2652 return;
2653
3d3dc149 2654 intel_dp->output_reg = output_reg;
ab9d7c30 2655 intel_dp->port = port;
0767935e
DV		 2656 /* Preserve the current hw state. */
2657 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2658
55f78c43
ZW		 2659 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2660 if (!intel_connector) {
ea5b213a 2661 kfree(intel_dp);
55f78c43
ZW		 2662 return;
2663 }
ea5b213a 2664 intel_encoder = &intel_dp->base;
dd06f90e 2665 intel_dp->attached_connector = intel_connector;
55f78c43 2666
ea5b213a 2667 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2668 if (intel_dpd_is_edp(dev))
ea5b213a 2669 intel_dp->is_pch_edp = true;
b329530c 2670
19c03924
GB		 2671 /*
2672 * FIXME : We need to initialize built-in panels before external panels.
2673 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2674 */
2675 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2676 type = DRM_MODE_CONNECTOR_eDP;
2677 intel_encoder->type = INTEL_OUTPUT_EDP;
2678 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2679 type = DRM_MODE_CONNECTOR_eDP;
2680 intel_encoder->type = INTEL_OUTPUT_EDP;
2681 } else {
2682 type = DRM_MODE_CONNECTOR_DisplayPort;
2683 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2684 }
2685
55f78c43 2686 connector = &intel_connector->base;
b329530c 2687 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2688 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2689
eb1f8e4f
DA		 2690 connector->polled = DRM_CONNECTOR_POLL_HPD;
2691
66a9278e 2692 intel_encoder->cloneable = false;
f8aed700 2693
66a9278e
DV		 2694 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2695 ironlake_panel_vdd_work);
6251ec0a 2696
27f8227b 2697 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2698
a4fc5ed6
KP		 2699 connector->interlace_allowed = true;
2700 connector->doublescan_allowed = 0;
2701
4ef69c7a 2702 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2703 DRM_MODE_ENCODER_TMDS);
a7902ac5
PZ		 2704
2705 if (IS_HASWELL(dev))
2706 drm_encoder_helper_add(&intel_encoder->base,
2707 &intel_dp_helper_funcs_hsw);
2708 else
2709 drm_encoder_helper_add(&intel_encoder->base,
2710 &intel_dp_helper_funcs);
a4fc5ed6 2711
df0e9248 2712 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2713 drm_sysfs_connector_add(connector);
2714
a7902ac5
PZ		 2715 if (IS_HASWELL(dev)) {
2716 intel_encoder->enable = intel_enable_ddi;
2717 intel_encoder->pre_enable = intel_ddi_pre_enable;
2718 intel_encoder->disable = intel_disable_ddi;
2719 intel_encoder->post_disable = intel_ddi_post_disable;
2720 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2721 } else {
2722 intel_encoder->enable = intel_enable_dp;
2723 intel_encoder->pre_enable = intel_pre_enable_dp;
2724 intel_encoder->disable = intel_disable_dp;
2725 intel_encoder->post_disable = intel_post_disable_dp;
2726 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2727 }
19d8fe15 2728 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2729
a4fc5ed6 2730 /* Set up the DDC bus. */
ab9d7c30
PZ		 2731 switch (port) {
2732 case PORT_A:
2733 name = "DPDDC-A";
2734 break;
2735 case PORT_B:
2736 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2737 name = "DPDDC-B";
2738 break;
2739 case PORT_C:
2740 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2741 name = "DPDDC-C";
2742 break;
2743 case PORT_D:
2744 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2745 name = "DPDDC-D";
2746 break;
2747 default:
2748 WARN(1, "Invalid port %c\n", port_name(port));
2749 break;
5eb08b69
ZW		 2750 }
2751
67a54566
DV		 2752 if (is_edp(intel_dp))
2753 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2754
2755 intel_dp_i2c_init(intel_dp, intel_connector, name);
2756
67a54566 2757 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2758 if (is_edp(intel_dp)) {
2759 bool ret;
f8779fda 2760 struct drm_display_mode *scan;
c1f05264 2761 struct edid *edid;
5d613501
JB		 2762
2763 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2764 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2765 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2766
59f3e272 2767 if (ret) {
7183dc29
JB		 2768 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2769 dev_priv->no_aux_handshake =
2770 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2771 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2772 } else {
3d3dc149 2773 /* if this fails, presume the device is a ghost */
48898b03 2774 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2775 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2776 intel_dp_destroy(&intel_connector->base);
3d3dc149 2777 return;
89667383 2778 }
89667383 2779
d6f24d0f
JB		 2780 ironlake_edp_panel_vdd_on(intel_dp);
2781 edid = drm_get_edid(connector, &intel_dp->adapter);
2782 if (edid) {
9cd300e0
JN		 2783 if (drm_add_edid_modes(connector, edid)) {
2784 drm_mode_connector_update_edid_property(connector, edid);
2785 drm_edid_to_eld(connector, edid);
2786 } else {
2787 kfree(edid);
2788 edid = ERR_PTR(-EINVAL);
2789 }
2790 } else {
2791 edid = ERR_PTR(-ENOENT);
d6f24d0f 2792 }
9cd300e0 2793 intel_connector->edid = edid;
f8779fda
JN		 2794
2795 /* prefer fixed mode from EDID if available */
2796 list_for_each_entry(scan, &connector->probed_modes, head) {
2797 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2798 fixed_mode = drm_mode_duplicate(dev, scan);
2799 break;
2800 }
2801 }
2802
2803 /* fallback to VBT if available for eDP */
2804 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2805 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2806 if (fixed_mode)
2807 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2808 }
f8779fda 2809
d6f24d0f
JB		 2810 ironlake_edp_panel_vdd_off(intel_dp, false);
2811 }
552fb0b7 2812
21d40d37 2813 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2814
1d508706 2815 if (is_edp(intel_dp)) {
dd06f90e 2816 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2817 intel_panel_setup_backlight(connector);
1d508706 2818 }
32f9d658 2819
f684960e
CW		 2820 intel_dp_add_properties(intel_dp, connector);
2821
a4fc5ed6
KP		 2822 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2823 * 0xd. Failure to do so will result in spurious interrupts being
2824 * generated on the port when a cable is not attached.
2825 */
2826 if (IS_G4X(dev) && !IS_GM45(dev)) {
2827 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2828 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2829 }
2830}
ubuntu-zesty-kernel mirror