]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_dp.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Set aux clk to 100MHz for Valleyview
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6 39
b091cd92 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
cfcb0fc9
JB		 44/**
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
47 *
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
50 */
51static bool is_edp(struct intel_dp *intel_dp)
52{
53 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54}
55
56/**
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
59 *
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
63 */
64static bool is_pch_edp(struct intel_dp *intel_dp)
65{
66 return intel_dp->is_pch_edp;
67}
68
1c95822a
AJ		 69/**
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
72 *
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 */
75static bool is_cpu_edp(struct intel_dp *intel_dp)
76{
77 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78}
79
ea5b213a
CW		 80static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
81{
4ef69c7a 82 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 83}
a4fc5ed6 84
df0e9248
CW		 85static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
86{
87 return container_of(intel_attached_encoder(connector),
88 struct intel_dp, base);
89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
33a34e4e
JB		 110static void intel_dp_start_link_train(struct intel_dp *intel_dp);
111static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 112static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 113
32f9d658 114void
0206e353 115intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 116 int *lane_num, int *link_bw)
32f9d658 117{
ea5b213a 118 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 119
ea5b213a
CW		 120 *lane_num = intel_dp->lane_count;
121 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 122 *link_bw = 162000;
ea5b213a 123 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 124 *link_bw = 270000;
125}
126
94bf2ced
DV		 127int
128intel_edp_target_clock(struct intel_encoder *intel_encoder,
129 struct drm_display_mode *mode)
130{
131 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
132
133 if (intel_dp->panel_fixed_mode)
134 return intel_dp->panel_fixed_mode->clock;
135 else
136 return mode->clock;
137}
138
a4fc5ed6 139static int
ea5b213a 140intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 141{
9a10f401
KP		 142 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) {
144 case 1: case 2: case 4:
145 break;
146 default:
147 max_lane_count = 4;
a4fc5ed6
KP		 148 }
149 return max_lane_count;
150}
151
152static int
ea5b213a 153intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 154{
7183dc29 155 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 156
157 switch (max_link_bw) {
158 case DP_LINK_BW_1_62:
159 case DP_LINK_BW_2_7:
160 break;
161 default:
162 max_link_bw = DP_LINK_BW_1_62;
163 break;
164 }
165 return max_link_bw;
166}
167
168static int
169intel_dp_link_clock(uint8_t link_bw)
170{
171 if (link_bw == DP_LINK_BW_2_7)
172 return 270000;
173 else
174 return 162000;
175}
176
cd9dde44
AJ		 177/*
178 * The units on the numbers in the next two are... bizarre. Examples will
179 * make it clearer; this one parallels an example in the eDP spec.
180 *
181 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
182 *
183 * 270000 * 1 * 8 / 10 == 216000
184 *
185 * The actual data capacity of that configuration is 2.16Gbit/s, so the
186 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
187 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
188 * 119000. At 18bpp that's 2142000 kilobits per second.
189 *
190 * Thus the strange-looking division by 10 in intel_dp_link_required, to
191 * get the result in decakilobits instead of kilobits.
192 */
193
a4fc5ed6 194static int
c898261c 195intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 196{
cd9dde44 197 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 198}
199
fe27d53e
DA		 200static int
201intel_dp_max_data_rate(int max_link_clock, int max_lanes)
202{
203 return (max_link_clock * max_lanes * 8) / 10;
204}
205
c4867936
DV		 206static bool
207intel_dp_adjust_dithering(struct intel_dp *intel_dp,
208 struct drm_display_mode *mode,
cb1793ce 209 bool adjust_mode)
c4867936
DV		 210{
211 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
212 int max_lanes = intel_dp_max_lane_count(intel_dp);
213 int max_rate, mode_rate;
214
215 mode_rate = intel_dp_link_required(mode->clock, 24);
216 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
217
218 if (mode_rate > max_rate) {
219 mode_rate = intel_dp_link_required(mode->clock, 18);
220 if (mode_rate > max_rate)
221 return false;
222
cb1793ce
DV		 223 if (adjust_mode)
224 mode->private_flags
c4867936
DV		 225 |= INTEL_MODE_DP_FORCE_6BPC;
226
227 return true;
228 }
229
230 return true;
231}
232
a4fc5ed6
KP		 233static int
234intel_dp_mode_valid(struct drm_connector *connector,
235 struct drm_display_mode *mode)
236{
df0e9248 237 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 238
d15456de
KP		 239 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
240 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 241 return MODE_PANEL;
242
d15456de 243 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 244 return MODE_PANEL;
245 }
246
cb1793ce 247 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 248 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 249
250 if (mode->clock < 10000)
251 return MODE_CLOCK_LOW;
252
0af78a2b
DV		 253 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
254 return MODE_H_ILLEGAL;
255
a4fc5ed6
KP		 256 return MODE_OK;
257}
258
259static uint32_t
260pack_aux(uint8_t *src, int src_bytes)
261{
262 int i;
263 uint32_t v = 0;
264
265 if (src_bytes > 4)
266 src_bytes = 4;
267 for (i = 0; i < src_bytes; i++)
268 v |= ((uint32_t) src[i]) << ((3-i) * 8);
269 return v;
270}
271
272static void
273unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
274{
275 int i;
276 if (dst_bytes > 4)
277 dst_bytes = 4;
278 for (i = 0; i < dst_bytes; i++)
279 dst[i] = src >> ((3-i) * 8);
280}
281
fb0f8fbf
KP		 282/* hrawclock is 1/4 the FSB frequency */
283static int
284intel_hrawclk(struct drm_device *dev)
285{
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 uint32_t clkcfg;
288
9473c8f4
VP		 289 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
290 if (IS_VALLEYVIEW(dev))
291 return 200;
292
fb0f8fbf
KP		 293 clkcfg = I915_READ(CLKCFG);
294 switch (clkcfg & CLKCFG_FSB_MASK) {
295 case CLKCFG_FSB_400:
296 return 100;
297 case CLKCFG_FSB_533:
298 return 133;
299 case CLKCFG_FSB_667:
300 return 166;
301 case CLKCFG_FSB_800:
302 return 200;
303 case CLKCFG_FSB_1067:
304 return 266;
305 case CLKCFG_FSB_1333:
306 return 333;
307 /* these two are just a guess; one of them might be right */
308 case CLKCFG_FSB_1600:
309 case CLKCFG_FSB_1600_ALT:
310 return 400;
311 default:
312 return 133;
313 }
314}
315
ebf33b18
KP		 316static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
317{
318 struct drm_device *dev = intel_dp->base.base.dev;
319 struct drm_i915_private *dev_priv = dev->dev_private;
320
321 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
322}
323
324static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
325{
326 struct drm_device *dev = intel_dp->base.base.dev;
327 struct drm_i915_private *dev_priv = dev->dev_private;
328
329 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
330}
331
9b984dae
KP		 332static void
333intel_dp_check_edp(struct intel_dp *intel_dp)
334{
335 struct drm_device *dev = intel_dp->base.base.dev;
336 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 337
9b984dae
KP		 338 if (!is_edp(intel_dp))
339 return;
ebf33b18 340 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 341 WARN(1, "eDP powered off while attempting aux channel communication.\n");
342 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 343 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 344 I915_READ(PCH_PP_CONTROL));
345 }
346}
347
a4fc5ed6 348static int
ea5b213a 349intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 350 uint8_t *send, int send_bytes,
351 uint8_t *recv, int recv_size)
352{
ea5b213a 353 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 354 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 355 struct drm_i915_private *dev_priv = dev->dev_private;
356 uint32_t ch_ctl = output_reg + 0x10;
357 uint32_t ch_data = ch_ctl + 4;
358 int i;
359 int recv_bytes;
a4fc5ed6 360 uint32_t status;
fb0f8fbf 361 uint32_t aux_clock_divider;
6b4e0a93 362 int try, precharge;
a4fc5ed6 363
9b984dae 364 intel_dp_check_edp(intel_dp);
a4fc5ed6 365 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 368 *
369 * Note that PCH attached eDP panels should use a 125MHz input
370 * clock divider.
a4fc5ed6 371 */
1c95822a 372 if (is_cpu_edp(intel_dp)) {
9473c8f4
VP		 373 if (IS_VALLEYVIEW(dev))
374 aux_clock_divider = 100;
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 376 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 377 else
378 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
379 } else if (HAS_PCH_SPLIT(dev))
6919132e 380 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 381 else
382 aux_clock_divider = intel_hrawclk(dev) / 2;
383
6b4e0a93
DV		 384 if (IS_GEN6(dev))
385 precharge = 3;
386 else
387 precharge = 5;
388
11bee43e
JB		 389 /* Try to wait for any previous AUX channel activity */
390 for (try = 0; try < 3; try++) {
391 status = I915_READ(ch_ctl);
392 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
393 break;
394 msleep(1);
395 }
396
397 if (try == 3) {
398 WARN(1, "dp_aux_ch not started status 0x%08x\n",
399 I915_READ(ch_ctl));
4f7f7b7e
CW		 400 return -EBUSY;
401 }
402
fb0f8fbf
KP		 403 /* Must try at least 3 times according to DP spec */
404 for (try = 0; try < 5; try++) {
405 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 406 for (i = 0; i < send_bytes; i += 4)
407 I915_WRITE(ch_data + i,
408 pack_aux(send + i, send_bytes - i));
0206e353 409
fb0f8fbf 410 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 411 I915_WRITE(ch_ctl,
412 DP_AUX_CH_CTL_SEND_BUSY |
413 DP_AUX_CH_CTL_TIME_OUT_400us |
414 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
415 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
416 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
417 DP_AUX_CH_CTL_DONE |
418 DP_AUX_CH_CTL_TIME_OUT_ERROR |
419 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 420 for (;;) {
fb0f8fbf
KP		 421 status = I915_READ(ch_ctl);
422 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
423 break;
4f7f7b7e 424 udelay(100);
fb0f8fbf 425 }
0206e353 426
fb0f8fbf 427 /* Clear done status and any errors */
4f7f7b7e
CW		 428 I915_WRITE(ch_ctl,
429 status |
430 DP_AUX_CH_CTL_DONE |
431 DP_AUX_CH_CTL_TIME_OUT_ERROR |
432 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 433
434 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
435 DP_AUX_CH_CTL_RECEIVE_ERROR))
436 continue;
4f7f7b7e 437 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 438 break;
439 }
440
a4fc5ed6 441 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 442 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 443 return -EBUSY;
a4fc5ed6
KP		 444 }
445
446 /* Check for timeout or receive error.
447 * Timeouts occur when the sink is not connected
448 */
a5b3da54 449 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 450 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 451 return -EIO;
452 }
1ae8c0a5
KP		 453
454 /* Timeouts occur when the device isn't connected, so they're
455 * "normal" -- don't fill the kernel log with these */
a5b3da54 456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 458 return -ETIMEDOUT;
a4fc5ed6
KP		 459 }
460
461 /* Unload any bytes sent back from the other side */
462 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
463 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 464 if (recv_bytes > recv_size)
465 recv_bytes = recv_size;
0206e353 466
4f7f7b7e
CW		 467 for (i = 0; i < recv_bytes; i += 4)
468 unpack_aux(I915_READ(ch_data + i),
469 recv + i, recv_bytes - i);
a4fc5ed6
KP		 470
471 return recv_bytes;
472}
473
474/* Write data to the aux channel in native mode */
475static int
ea5b213a 476intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 477 uint16_t address, uint8_t *send, int send_bytes)
478{
479 int ret;
480 uint8_t msg[20];
481 int msg_bytes;
482 uint8_t ack;
483
9b984dae 484 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 485 if (send_bytes > 16)
486 return -1;
487 msg[0] = AUX_NATIVE_WRITE << 4;
488 msg[1] = address >> 8;
eebc863e 489 msg[2] = address & 0xff;
a4fc5ed6
KP		 490 msg[3] = send_bytes - 1;
491 memcpy(&msg[4], send, send_bytes);
492 msg_bytes = send_bytes + 4;
493 for (;;) {
ea5b213a 494 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 495 if (ret < 0)
496 return ret;
497 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
498 break;
499 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
500 udelay(100);
501 else
a5b3da54 502 return -EIO;
a4fc5ed6
KP		 503 }
504 return send_bytes;
505}
506
507/* Write a single byte to the aux channel in native mode */
508static int
ea5b213a 509intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 510 uint16_t address, uint8_t byte)
511{
ea5b213a 512 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 513}
514
515/* read bytes from a native aux channel */
516static int
ea5b213a 517intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 518 uint16_t address, uint8_t *recv, int recv_bytes)
519{
520 uint8_t msg[4];
521 int msg_bytes;
522 uint8_t reply[20];
523 int reply_bytes;
524 uint8_t ack;
525 int ret;
526
9b984dae 527 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 528 msg[0] = AUX_NATIVE_READ << 4;
529 msg[1] = address >> 8;
530 msg[2] = address & 0xff;
531 msg[3] = recv_bytes - 1;
532
533 msg_bytes = 4;
534 reply_bytes = recv_bytes + 1;
535
536 for (;;) {
ea5b213a 537 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 538 reply, reply_bytes);
a5b3da54
KP		 539 if (ret == 0)
540 return -EPROTO;
541 if (ret < 0)
a4fc5ed6
KP		 542 return ret;
543 ack = reply[0];
544 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
545 memcpy(recv, reply + 1, ret - 1);
546 return ret - 1;
547 }
548 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
549 udelay(100);
550 else
a5b3da54 551 return -EIO;
a4fc5ed6
KP		 552 }
553}
554
555static int
ab2c0672
DA		 556intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
557 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 558{
ab2c0672 559 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 560 struct intel_dp *intel_dp = container_of(adapter,
561 struct intel_dp,
562 adapter);
ab2c0672
DA		 563 uint16_t address = algo_data->address;
564 uint8_t msg[5];
565 uint8_t reply[2];
8316f337 566 unsigned retry;
ab2c0672
DA		 567 int msg_bytes;
568 int reply_bytes;
569 int ret;
570
9b984dae 571 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 572 /* Set up the command byte */
573 if (mode & MODE_I2C_READ)
574 msg[0] = AUX_I2C_READ << 4;
575 else
576 msg[0] = AUX_I2C_WRITE << 4;
577
578 if (!(mode & MODE_I2C_STOP))
579 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 580
ab2c0672
DA		 581 msg[1] = address >> 8;
582 msg[2] = address;
583
584 switch (mode) {
585 case MODE_I2C_WRITE:
586 msg[3] = 0;
587 msg[4] = write_byte;
588 msg_bytes = 5;
589 reply_bytes = 1;
590 break;
591 case MODE_I2C_READ:
592 msg[3] = 0;
593 msg_bytes = 4;
594 reply_bytes = 2;
595 break;
596 default:
597 msg_bytes = 3;
598 reply_bytes = 1;
599 break;
600 }
601
8316f337
DF		 602 for (retry = 0; retry < 5; retry++) {
603 ret = intel_dp_aux_ch(intel_dp,
604 msg, msg_bytes,
605 reply, reply_bytes);
ab2c0672 606 if (ret < 0) {
3ff99164 607 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 608 return ret;
609 }
8316f337
DF		 610
611 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
612 case AUX_NATIVE_REPLY_ACK:
613 /* I2C-over-AUX Reply field is only valid
614 * when paired with AUX ACK.
615 */
616 break;
617 case AUX_NATIVE_REPLY_NACK:
618 DRM_DEBUG_KMS("aux_ch native nack\n");
619 return -EREMOTEIO;
620 case AUX_NATIVE_REPLY_DEFER:
621 udelay(100);
622 continue;
623 default:
624 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
625 reply[0]);
626 return -EREMOTEIO;
627 }
628
ab2c0672
DA		 629 switch (reply[0] & AUX_I2C_REPLY_MASK) {
630 case AUX_I2C_REPLY_ACK:
631 if (mode == MODE_I2C_READ) {
632 *read_byte = reply[1];
633 }
634 return reply_bytes - 1;
635 case AUX_I2C_REPLY_NACK:
8316f337 636 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 637 return -EREMOTEIO;
638 case AUX_I2C_REPLY_DEFER:
8316f337 639 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 640 udelay(100);
641 break;
642 default:
8316f337 643 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 644 return -EREMOTEIO;
645 }
646 }
8316f337
DF		 647
648 DRM_ERROR("too many retries, giving up\n");
649 return -EREMOTEIO;
a4fc5ed6
KP		 650}
651
0b5c541b 652static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 653static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 654
a4fc5ed6 655static int
ea5b213a 656intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 657 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 658{
0b5c541b
KP		 659 int ret;
660
d54e9d28 661 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 662 intel_dp->algo.running = false;
663 intel_dp->algo.address = 0;
664 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
665
0206e353 666 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 667 intel_dp->adapter.owner = THIS_MODULE;
668 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 669 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 670 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
671 intel_dp->adapter.algo_data = &intel_dp->algo;
672 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
673
0b5c541b
KP		 674 ironlake_edp_panel_vdd_on(intel_dp);
675 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 676 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 677 return ret;
a4fc5ed6
KP		 678}
679
680static bool
e811f5ae
LP		 681intel_dp_mode_fixup(struct drm_encoder *encoder,
682 const struct drm_display_mode *mode,
a4fc5ed6
KP		 683 struct drm_display_mode *adjusted_mode)
684{
0d3a1bee 685 struct drm_device *dev = encoder->dev;
ea5b213a 686 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 687 int lane_count, clock;
ea5b213a
CW		 688 int max_lane_count = intel_dp_max_lane_count(intel_dp);
689 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 690 int bpp, mode_rate;
a4fc5ed6
KP		 691 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
692
d15456de
KP		 693 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
694 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 695 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
696 mode, adjusted_mode);
0d3a1bee
ZY		 697 }
698
cb1793ce 699 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 700 return false;
701
083f9560
DV		 702 DRM_DEBUG_KMS("DP link computation with max lane count %i "
703 "max bw %02x pixel clock %iKHz\n",
71244653 704 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 705
cb1793ce 706 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 707 return false;
708
709 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 710 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 711
2514bc51
JB		 712 for (clock = 0; clock <= max_clock; clock++) {
713 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 714 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 715
083f9560 716 if (mode_rate <= link_avail) {
ea5b213a
CW		 717 intel_dp->link_bw = bws[clock];
718 intel_dp->lane_count = lane_count;
719 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 720 DRM_DEBUG_KMS("DP link bw %02x lane "
721 "count %d clock %d bpp %d\n",
ea5b213a 722 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 723 adjusted_mode->clock, bpp);
724 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
725 mode_rate, link_avail);
a4fc5ed6
KP		 726 return true;
727 }
728 }
729 }
fe27d53e 730
a4fc5ed6
KP		 731 return false;
732}
733
734struct intel_dp_m_n {
735 uint32_t tu;
736 uint32_t gmch_m;
737 uint32_t gmch_n;
738 uint32_t link_m;
739 uint32_t link_n;
740};
741
742static void
743intel_reduce_ratio(uint32_t *num, uint32_t *den)
744{
745 while (*num > 0xffffff || *den > 0xffffff) {
746 *num >>= 1;
747 *den >>= 1;
748 }
749}
750
751static void
36e83a18 752intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 753 int nlanes,
754 int pixel_clock,
755 int link_clock,
756 struct intel_dp_m_n *m_n)
757{
758 m_n->tu = 64;
36e83a18 759 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 760 m_n->gmch_n = link_clock * nlanes;
761 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
762 m_n->link_m = pixel_clock;
763 m_n->link_n = link_clock;
764 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
765}
766
767void
768intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
769 struct drm_display_mode *adjusted_mode)
770{
771 struct drm_device *dev = crtc->dev;
6c2b7c12 772 struct intel_encoder *encoder;
a4fc5ed6
KP		 773 struct drm_i915_private *dev_priv = dev->dev_private;
774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 775 int lane_count = 4;
a4fc5ed6 776 struct intel_dp_m_n m_n;
9db4a9c7 777 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 778
779 /*
21d40d37 780 * Find the lane count in the intel_encoder private
a4fc5ed6 781 */
6c2b7c12
DV		 782 for_each_encoder_on_crtc(dev, crtc, encoder) {
783 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 784
9a10f401
KP		 785 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
786 intel_dp->base.type == INTEL_OUTPUT_EDP)
787 {
ea5b213a 788 lane_count = intel_dp->lane_count;
51190667 789 break;
a4fc5ed6
KP		 790 }
791 }
792
793 /*
794 * Compute the GMCH and Link ratios. The '3' here is
795 * the number of bytes_per_pixel post-LUT, which we always
796 * set up for 8-bits of R/G/B, or 3 bytes total.
797 */
858fa035 798 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 799 mode->clock, adjusted_mode->clock, &m_n);
800
c619eed4 801 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 802 I915_WRITE(TRANSDATA_M1(pipe),
803 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
804 m_n.gmch_m);
805 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
806 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
807 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 808 } else {
9db4a9c7
JB		 809 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
810 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
811 m_n.gmch_m);
812 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
813 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
814 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 815 }
816}
817
818static void
819intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
820 struct drm_display_mode *adjusted_mode)
821{
e3421a18 822 struct drm_device *dev = encoder->dev;
417e822d 823 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 824 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 825 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
827
417e822d 828 /*
1a2eb460 829 * There are four kinds of DP registers:
417e822d
KP		 830 *
831 * IBX PCH
1a2eb460
KP		 832 * SNB CPU
833 * IVB CPU
417e822d
KP		 834 * CPT PCH
835 *
836 * IBX PCH and CPU are the same for almost everything,
837 * except that the CPU DP PLL is configured in this
838 * register
839 *
840 * CPT PCH is quite different, having many bits moved
841 * to the TRANS_DP_CTL register instead. That
842 * configuration happens (oddly) in ironlake_pch_enable
843 */
9c9e7927 844
417e822d
KP		 845 /* Preserve the BIOS-computed detected bit. This is
846 * supposed to be read-only.
847 */
848 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 849
417e822d 850 /* Handle DP bits in common between all three register formats */
417e822d 851 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 852
ea5b213a 853 switch (intel_dp->lane_count) {
a4fc5ed6 854 case 1:
ea5b213a 855 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 856 break;
857 case 2:
ea5b213a 858 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 859 break;
860 case 4:
ea5b213a 861 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 862 break;
863 }
e0dac65e
WF		 864 if (intel_dp->has_audio) {
865 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
866 pipe_name(intel_crtc->pipe));
ea5b213a 867 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 868 intel_write_eld(encoder, adjusted_mode);
869 }
ea5b213a
CW		 870 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
871 intel_dp->link_configuration[0] = intel_dp->link_bw;
872 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 873 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 874 /*
9962c925 875 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 876 */
7183dc29
JB		 877 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
878 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 879 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 880 }
881
417e822d 882 /* Split out the IBX/CPU vs CPT settings */
32f9d658 883
1a2eb460
KP		 884 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
885 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
886 intel_dp->DP |= DP_SYNC_HS_HIGH;
887 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
888 intel_dp->DP |= DP_SYNC_VS_HIGH;
889 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
890
891 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
892 intel_dp->DP |= DP_ENHANCED_FRAMING;
893
894 intel_dp->DP |= intel_crtc->pipe << 29;
895
896 /* don't miss out required setting for eDP */
1a2eb460
KP		 897 if (adjusted_mode->clock < 200000)
898 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
899 else
900 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
901 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 902 intel_dp->DP |= intel_dp->color_range;
903
904 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
905 intel_dp->DP |= DP_SYNC_HS_HIGH;
906 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
907 intel_dp->DP |= DP_SYNC_VS_HIGH;
908 intel_dp->DP |= DP_LINK_TRAIN_OFF;
909
910 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
911 intel_dp->DP |= DP_ENHANCED_FRAMING;
912
913 if (intel_crtc->pipe == 1)
914 intel_dp->DP |= DP_PIPEB_SELECT;
915
916 if (is_cpu_edp(intel_dp)) {
917 /* don't miss out required setting for eDP */
417e822d
KP		 918 if (adjusted_mode->clock < 200000)
919 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
920 else
921 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
922 }
923 } else {
924 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 925 }
a4fc5ed6
KP		 926}
927
99ea7127
KP		 928#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
929#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
930
931#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
932#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
933
934#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
935#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
936
937static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
938 u32 mask,
939 u32 value)
bd943159 940{
99ea7127
KP		 941 struct drm_device *dev = intel_dp->base.base.dev;
942 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 943
99ea7127
KP		 944 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
945 mask, value,
946 I915_READ(PCH_PP_STATUS),
947 I915_READ(PCH_PP_CONTROL));
32ce697c 948
99ea7127
KP		 949 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
950 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
951 I915_READ(PCH_PP_STATUS),
952 I915_READ(PCH_PP_CONTROL));
32ce697c 953 }
99ea7127 954}
32ce697c 955
99ea7127
KP		 956static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
957{
958 DRM_DEBUG_KMS("Wait for panel power on\n");
959 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 960}
961
99ea7127
KP		 962static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
963{
964 DRM_DEBUG_KMS("Wait for panel power off time\n");
965 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
966}
967
968static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
969{
970 DRM_DEBUG_KMS("Wait for panel power cycle\n");
971 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
972}
973
974
832dd3c1
KP		 975/* Read the current pp_control value, unlocking the register if it
976 * is locked
977 */
978
979static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
980{
981 u32 control = I915_READ(PCH_PP_CONTROL);
982
983 control &= ~PANEL_UNLOCK_MASK;
984 control |= PANEL_UNLOCK_REGS;
985 return control;
bd943159
KP		 986}
987
5d613501
JB		 988static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
989{
990 struct drm_device *dev = intel_dp->base.base.dev;
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 u32 pp;
993
97af61f5
KP		 994 if (!is_edp(intel_dp))
995 return;
f01eca2e 996 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 997
bd943159
KP		 998 WARN(intel_dp->want_panel_vdd,
999 "eDP VDD already requested on\n");
1000
1001 intel_dp->want_panel_vdd = true;
99ea7127 1002
bd943159
KP		 1003 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1004 DRM_DEBUG_KMS("eDP VDD already on\n");
1005 return;
1006 }
1007
99ea7127
KP		 1008 if (!ironlake_edp_have_panel_power(intel_dp))
1009 ironlake_wait_panel_power_cycle(intel_dp);
1010
832dd3c1 1011 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1012 pp |= EDP_FORCE_VDD;
1013 I915_WRITE(PCH_PP_CONTROL, pp);
1014 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1015 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1016 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1017
1018 /*
1019 * If the panel wasn't on, delay before accessing aux channel
1020 */
1021 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1022 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1023 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1024 }
5d613501
JB		 1025}
1026
bd943159 1027static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1028{
1029 struct drm_device *dev = intel_dp->base.base.dev;
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 u32 pp;
1032
bd943159 1033 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1034 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1035 pp &= ~EDP_FORCE_VDD;
1036 I915_WRITE(PCH_PP_CONTROL, pp);
1037 POSTING_READ(PCH_PP_CONTROL);
1038
1039 /* Make sure sequencer is idle before allowing subsequent activity */
1040 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1041 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1042
1043 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1044 }
1045}
5d613501 1046
bd943159
KP		 1047static void ironlake_panel_vdd_work(struct work_struct *__work)
1048{
1049 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1050 struct intel_dp, panel_vdd_work);
1051 struct drm_device *dev = intel_dp->base.base.dev;
1052
627f7675 1053 mutex_lock(&dev->mode_config.mutex);
bd943159 1054 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1055 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1056}
1057
1058static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1059{
97af61f5
KP		 1060 if (!is_edp(intel_dp))
1061 return;
5d613501 1062
bd943159
KP		 1063 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1064 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1065
bd943159
KP		 1066 intel_dp->want_panel_vdd = false;
1067
1068 if (sync) {
1069 ironlake_panel_vdd_off_sync(intel_dp);
1070 } else {
1071 /*
1072 * Queue the timer to fire a long
1073 * time from now (relative to the power down delay)
1074 * to keep the panel power up across a sequence of operations
1075 */
1076 schedule_delayed_work(&intel_dp->panel_vdd_work,
1077 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1078 }
5d613501
JB		 1079}
1080
86a3073e 1081static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1082{
01cb9ea6 1083 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1084 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1085 u32 pp;
9934c132 1086
97af61f5 1087 if (!is_edp(intel_dp))
bd943159 1088 return;
99ea7127
KP		 1089
1090 DRM_DEBUG_KMS("Turn eDP power on\n");
1091
1092 if (ironlake_edp_have_panel_power(intel_dp)) {
1093 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1094 return;
99ea7127 1095 }
9934c132 1096
99ea7127 1097 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1098
99ea7127 1099 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1100 if (IS_GEN5(dev)) {
1101 /* ILK workaround: disable reset around power sequence */
1102 pp &= ~PANEL_POWER_RESET;
1103 I915_WRITE(PCH_PP_CONTROL, pp);
1104 POSTING_READ(PCH_PP_CONTROL);
1105 }
37c6c9b0 1106
1c0ae80a 1107 pp |= POWER_TARGET_ON;
99ea7127
KP		 1108 if (!IS_GEN5(dev))
1109 pp |= PANEL_POWER_RESET;
1110
9934c132 1111 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1112 POSTING_READ(PCH_PP_CONTROL);
9934c132 1113
99ea7127 1114 ironlake_wait_panel_on(intel_dp);
9934c132 1115
05ce1a49
KP		 1116 if (IS_GEN5(dev)) {
1117 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1118 I915_WRITE(PCH_PP_CONTROL, pp);
1119 POSTING_READ(PCH_PP_CONTROL);
1120 }
9934c132
JB		 1121}
1122
99ea7127 1123static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1124{
99ea7127 1125 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1126 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1127 u32 pp;
9934c132 1128
97af61f5
KP		 1129 if (!is_edp(intel_dp))
1130 return;
37c6c9b0 1131
99ea7127 1132 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1133
6cb49835 1134 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1135
99ea7127 1136 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1137 /* We need to switch off panel power _and_ force vdd, for otherwise some
1138 * panels get very unhappy and cease to work. */
1139 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1140 I915_WRITE(PCH_PP_CONTROL, pp);
1141 POSTING_READ(PCH_PP_CONTROL);
9934c132 1142
35a38556
DV		 1143 intel_dp->want_panel_vdd = false;
1144
99ea7127 1145 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1146}
1147
86a3073e 1148static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1149{
f01eca2e 1150 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 u32 pp;
1153
f01eca2e
KP		 1154 if (!is_edp(intel_dp))
1155 return;
1156
28c97730 1157 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1158 /*
1159 * If we enable the backlight right away following a panel power
1160 * on, we may see slight flicker as the panel syncs with the eDP
1161 * link. So delay a bit to make sure the image is solid before
1162 * allowing it to appear.
1163 */
f01eca2e 1164 msleep(intel_dp->backlight_on_delay);
832dd3c1 1165 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1166 pp |= EDP_BLC_ENABLE;
1167 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1168 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1169}
1170
86a3073e 1171static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1172{
f01eca2e 1173 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1174 struct drm_i915_private *dev_priv = dev->dev_private;
1175 u32 pp;
1176
f01eca2e
KP		 1177 if (!is_edp(intel_dp))
1178 return;
1179
28c97730 1180 DRM_DEBUG_KMS("\n");
832dd3c1 1181 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1182 pp &= ~EDP_BLC_ENABLE;
1183 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1184 POSTING_READ(PCH_PP_CONTROL);
1185 msleep(intel_dp->backlight_off_delay);
32f9d658 1186}
a4fc5ed6 1187
2bd2ad64 1188static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1189{
2bd2ad64
DV		 1190 struct drm_device *dev = intel_dp->base.base.dev;
1191 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 u32 dpa_ctl;
1194
2bd2ad64
DV		 1195 assert_pipe_disabled(dev_priv,
1196 to_intel_crtc(crtc)->pipe);
1197
d240f20f
JB		 1198 DRM_DEBUG_KMS("\n");
1199 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1200 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1201 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1202
1203 /* We don't adjust intel_dp->DP while tearing down the link, to
1204 * facilitate link retraining (e.g. after hotplug). Hence clear all
1205 * enable bits here to ensure that we don't enable too much. */
1206 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1207 intel_dp->DP |= DP_PLL_ENABLE;
1208 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1209 POSTING_READ(DP_A);
1210 udelay(200);
d240f20f
JB		 1211}
1212
2bd2ad64 1213static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1214{
2bd2ad64
DV		 1215 struct drm_device *dev = intel_dp->base.base.dev;
1216 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 u32 dpa_ctl;
1219
2bd2ad64
DV		 1220 assert_pipe_disabled(dev_priv,
1221 to_intel_crtc(crtc)->pipe);
1222
d240f20f 1223 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1224 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1225 "dp pll off, should be on\n");
1226 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1227
1228 /* We can't rely on the value tracked for the DP register in
1229 * intel_dp->DP because link_down must not change that (otherwise link
1230 * re-training will fail. */
298b0b39 1231 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1232 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1233 POSTING_READ(DP_A);
d240f20f
JB		 1234 udelay(200);
1235}
1236
c7ad3810
JB		 1237/* If the sink supports it, try to set the power state appropriately */
1238static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1239{
1240 int ret, i;
1241
1242 /* Should have a valid DPCD by this point */
1243 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1244 return;
1245
1246 if (mode != DRM_MODE_DPMS_ON) {
1247 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1248 DP_SET_POWER_D3);
1249 if (ret != 1)
1250 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1251 } else {
1252 /*
1253 * When turning on, we need to retry for 1ms to give the sink
1254 * time to wake up.
1255 */
1256 for (i = 0; i < 3; i++) {
1257 ret = intel_dp_aux_native_write_1(intel_dp,
1258 DP_SET_POWER,
1259 DP_SET_POWER_D0);
1260 if (ret == 1)
1261 break;
1262 msleep(1);
1263 }
1264 }
1265}
1266
19d8fe15
DV		 1267static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1268 enum pipe *pipe)
d240f20f 1269{
19d8fe15
DV		 1270 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1271 struct drm_device *dev = encoder->base.dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 u32 tmp = I915_READ(intel_dp->output_reg);
1274
1275 if (!(tmp & DP_PORT_EN))
1276 return false;
1277
1278 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1279 *pipe = PORT_TO_PIPE_CPT(tmp);
1280 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1281 *pipe = PORT_TO_PIPE(tmp);
1282 } else {
1283 u32 trans_sel;
1284 u32 trans_dp;
1285 int i;
1286
1287 switch (intel_dp->output_reg) {
1288 case PCH_DP_B:
1289 trans_sel = TRANS_DP_PORT_SEL_B;
1290 break;
1291 case PCH_DP_C:
1292 trans_sel = TRANS_DP_PORT_SEL_C;
1293 break;
1294 case PCH_DP_D:
1295 trans_sel = TRANS_DP_PORT_SEL_D;
1296 break;
1297 default:
1298 return true;
1299 }
1300
1301 for_each_pipe(i) {
1302 trans_dp = I915_READ(TRANS_DP_CTL(i));
1303 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1304 *pipe = i;
1305 return true;
1306 }
1307 }
1308 }
1309
1310 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1311
19d8fe15
DV		 1312 return true;
1313}
1314
e8cb4558 1315static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1316{
e8cb4558 1317 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1318
1319 /* Make sure the panel is off before trying to change the mode. But also
1320 * ensure that we have vdd while we switch off the panel. */
1321 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1322 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1323 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1324 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1325
1326 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1327 if (!is_cpu_edp(intel_dp))
1328 intel_dp_link_down(intel_dp);
d240f20f
JB		 1329}
1330
2bd2ad64
DV		 1331static void intel_post_disable_dp(struct intel_encoder *encoder)
1332{
1333 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1334
3739850b
DV		 1335 if (is_cpu_edp(intel_dp)) {
1336 intel_dp_link_down(intel_dp);
2bd2ad64 1337 ironlake_edp_pll_off(intel_dp);
3739850b 1338 }
2bd2ad64
DV		 1339}
1340
e8cb4558 1341static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1342{
e8cb4558
DV		 1343 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1344 struct drm_device *dev = encoder->base.dev;
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1347
0c33d8d7
DV		 1348 if (WARN_ON(dp_reg & DP_PORT_EN))
1349 return;
1350
97af61f5 1351 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1352 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1353 intel_dp_start_link_train(intel_dp);
1354 ironlake_edp_panel_on(intel_dp);
1355 ironlake_edp_panel_vdd_off(intel_dp, true);
1356 intel_dp_complete_link_train(intel_dp);
f01eca2e 1357 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1358}
1359
2bd2ad64 1360static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1361{
2bd2ad64 1362 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1363
2bd2ad64
DV		 1364 if (is_cpu_edp(intel_dp))
1365 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1366}
1367
1368/*
df0c237d
JB		 1369 * Native read with retry for link status and receiver capability reads for
1370 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1371 */
1372static bool
df0c237d
JB		 1373intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1374 uint8_t *recv, int recv_bytes)
a4fc5ed6 1375{
61da5fab
JB		 1376 int ret, i;
1377
df0c237d
JB		 1378 /*
1379 * Sinks are *supposed* to come up within 1ms from an off state,
1380 * but we're also supposed to retry 3 times per the spec.
1381 */
61da5fab 1382 for (i = 0; i < 3; i++) {
df0c237d
JB		 1383 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1384 recv_bytes);
1385 if (ret == recv_bytes)
61da5fab
JB		 1386 return true;
1387 msleep(1);
1388 }
a4fc5ed6 1389
61da5fab 1390 return false;
a4fc5ed6
KP		 1391}
1392
1393/*
1394 * Fetch AUX CH registers 0x202 - 0x207 which contain
1395 * link status information
1396 */
1397static bool
93f62dad 1398intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1399{
df0c237d
JB		 1400 return intel_dp_aux_native_read_retry(intel_dp,
1401 DP_LANE0_1_STATUS,
93f62dad 1402 link_status,
df0c237d 1403 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1404}
1405
1406static uint8_t
1407intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1408 int r)
1409{
1410 return link_status[r - DP_LANE0_1_STATUS];
1411}
1412
a4fc5ed6 1413static uint8_t
93f62dad 1414intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1415 int lane)
1416{
a4fc5ed6
KP		 1417 int s = ((lane & 1) ?
1418 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1419 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1420 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1421
1422 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1423}
1424
1425static uint8_t
93f62dad 1426intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1427 int lane)
1428{
a4fc5ed6
KP		 1429 int s = ((lane & 1) ?
1430 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1431 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1432 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1433
1434 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1435}
1436
1437
1438#if 0
1439static char *voltage_names[] = {
1440 "0.4V", "0.6V", "0.8V", "1.2V"
1441};
1442static char *pre_emph_names[] = {
1443 "0dB", "3.5dB", "6dB", "9.5dB"
1444};
1445static char *link_train_names[] = {
1446 "pattern 1", "pattern 2", "idle", "off"
1447};
1448#endif
1449
1450/*
1451 * These are source-specific values; current Intel hardware supports
1452 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1453 */
a4fc5ed6
KP		 1454
1455static uint8_t
1a2eb460 1456intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1457{
1a2eb460
KP		 1458 struct drm_device *dev = intel_dp->base.base.dev;
1459
1460 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1461 return DP_TRAIN_VOLTAGE_SWING_800;
1462 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1463 return DP_TRAIN_VOLTAGE_SWING_1200;
1464 else
1465 return DP_TRAIN_VOLTAGE_SWING_800;
1466}
1467
1468static uint8_t
1469intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1470{
1471 struct drm_device *dev = intel_dp->base.base.dev;
1472
1473 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1474 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1475 case DP_TRAIN_VOLTAGE_SWING_400:
1476 return DP_TRAIN_PRE_EMPHASIS_6;
1477 case DP_TRAIN_VOLTAGE_SWING_600:
1478 case DP_TRAIN_VOLTAGE_SWING_800:
1479 return DP_TRAIN_PRE_EMPHASIS_3_5;
1480 default:
1481 return DP_TRAIN_PRE_EMPHASIS_0;
1482 }
1483 } else {
1484 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1485 case DP_TRAIN_VOLTAGE_SWING_400:
1486 return DP_TRAIN_PRE_EMPHASIS_6;
1487 case DP_TRAIN_VOLTAGE_SWING_600:
1488 return DP_TRAIN_PRE_EMPHASIS_6;
1489 case DP_TRAIN_VOLTAGE_SWING_800:
1490 return DP_TRAIN_PRE_EMPHASIS_3_5;
1491 case DP_TRAIN_VOLTAGE_SWING_1200:
1492 default:
1493 return DP_TRAIN_PRE_EMPHASIS_0;
1494 }
a4fc5ed6
KP		 1495 }
1496}
1497
1498static void
93f62dad 1499intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1500{
1501 uint8_t v = 0;
1502 uint8_t p = 0;
1503 int lane;
93f62dad 1504 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1505 uint8_t voltage_max;
1506 uint8_t preemph_max;
a4fc5ed6 1507
33a34e4e 1508 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1509 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1510 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1511
1512 if (this_v > v)
1513 v = this_v;
1514 if (this_p > p)
1515 p = this_p;
1516 }
1517
1a2eb460 1518 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1519 if (v >= voltage_max)
1520 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1521
1a2eb460
KP		 1522 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1523 if (p >= preemph_max)
1524 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1525
1526 for (lane = 0; lane < 4; lane++)
33a34e4e 1527 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1528}
1529
1530static uint32_t
93f62dad 1531intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1532{
3cf2efb1 1533 uint32_t signal_levels = 0;
a4fc5ed6 1534
3cf2efb1 1535 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1536 case DP_TRAIN_VOLTAGE_SWING_400:
1537 default:
1538 signal_levels |= DP_VOLTAGE_0_4;
1539 break;
1540 case DP_TRAIN_VOLTAGE_SWING_600:
1541 signal_levels |= DP_VOLTAGE_0_6;
1542 break;
1543 case DP_TRAIN_VOLTAGE_SWING_800:
1544 signal_levels |= DP_VOLTAGE_0_8;
1545 break;
1546 case DP_TRAIN_VOLTAGE_SWING_1200:
1547 signal_levels |= DP_VOLTAGE_1_2;
1548 break;
1549 }
3cf2efb1 1550 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1551 case DP_TRAIN_PRE_EMPHASIS_0:
1552 default:
1553 signal_levels |= DP_PRE_EMPHASIS_0;
1554 break;
1555 case DP_TRAIN_PRE_EMPHASIS_3_5:
1556 signal_levels |= DP_PRE_EMPHASIS_3_5;
1557 break;
1558 case DP_TRAIN_PRE_EMPHASIS_6:
1559 signal_levels |= DP_PRE_EMPHASIS_6;
1560 break;
1561 case DP_TRAIN_PRE_EMPHASIS_9_5:
1562 signal_levels |= DP_PRE_EMPHASIS_9_5;
1563 break;
1564 }
1565 return signal_levels;
1566}
1567
e3421a18
ZW		 1568/* Gen6's DP voltage swing and pre-emphasis control */
1569static uint32_t
1570intel_gen6_edp_signal_levels(uint8_t train_set)
1571{
3c5a62b5
YL		 1572 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1573 DP_TRAIN_PRE_EMPHASIS_MASK);
1574 switch (signal_levels) {
e3421a18 1575 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1576 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1577 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1578 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1579 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1580 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1581 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1582 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1583 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1584 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1585 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1586 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1587 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1588 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1589 default:
3c5a62b5
YL		 1590 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1591 "0x%x\n", signal_levels);
1592 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1593 }
1594}
1595
1a2eb460
KP		 1596/* Gen7's DP voltage swing and pre-emphasis control */
1597static uint32_t
1598intel_gen7_edp_signal_levels(uint8_t train_set)
1599{
1600 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1601 DP_TRAIN_PRE_EMPHASIS_MASK);
1602 switch (signal_levels) {
1603 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1604 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1605 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1606 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1607 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1608 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1609
1610 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1611 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1612 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1613 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1614
1615 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1616 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1617 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1618 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1619
1620 default:
1621 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1622 "0x%x\n", signal_levels);
1623 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1624 }
1625}
1626
a4fc5ed6
KP		 1627static uint8_t
1628intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1629 int lane)
1630{
a4fc5ed6 1631 int s = (lane & 1) * 4;
93f62dad 1632 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1633
1634 return (l >> s) & 0xf;
1635}
1636
1637/* Check for clock recovery is done on all channels */
1638static bool
1639intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1640{
1641 int lane;
1642 uint8_t lane_status;
1643
1644 for (lane = 0; lane < lane_count; lane++) {
1645 lane_status = intel_get_lane_status(link_status, lane);
1646 if ((lane_status & DP_LANE_CR_DONE) == 0)
1647 return false;
1648 }
1649 return true;
1650}
1651
1652/* Check to see if channel eq is done on all channels */
1653#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1654 DP_LANE_CHANNEL_EQ_DONE|\
1655 DP_LANE_SYMBOL_LOCKED)
1656static bool
93f62dad 1657intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1658{
1659 uint8_t lane_align;
1660 uint8_t lane_status;
1661 int lane;
1662
93f62dad 1663 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1664 DP_LANE_ALIGN_STATUS_UPDATED);
1665 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1666 return false;
33a34e4e 1667 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1668 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1669 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1670 return false;
1671 }
1672 return true;
1673}
1674
1675static bool
ea5b213a 1676intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1677 uint32_t dp_reg_value,
58e10eb9 1678 uint8_t dp_train_pat)
a4fc5ed6 1679{
4ef69c7a 1680 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1681 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1682 int ret;
1683
47ea7542
PZ		 1684 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1685 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1686
1687 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1688 case DP_TRAINING_PATTERN_DISABLE:
1689 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1690 break;
1691 case DP_TRAINING_PATTERN_1:
1692 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1693 break;
1694 case DP_TRAINING_PATTERN_2:
1695 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1696 break;
1697 case DP_TRAINING_PATTERN_3:
1698 DRM_ERROR("DP training pattern 3 not supported\n");
1699 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1700 break;
1701 }
1702
1703 } else {
1704 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1705
1706 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1707 case DP_TRAINING_PATTERN_DISABLE:
1708 dp_reg_value |= DP_LINK_TRAIN_OFF;
1709 break;
1710 case DP_TRAINING_PATTERN_1:
1711 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1712 break;
1713 case DP_TRAINING_PATTERN_2:
1714 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1715 break;
1716 case DP_TRAINING_PATTERN_3:
1717 DRM_ERROR("DP training pattern 3 not supported\n");
1718 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1719 break;
1720 }
1721 }
1722
ea5b213a
CW		 1723 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1724 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1725
ea5b213a 1726 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1727 DP_TRAINING_PATTERN_SET,
1728 dp_train_pat);
1729
47ea7542
PZ		 1730 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1731 DP_TRAINING_PATTERN_DISABLE) {
1732 ret = intel_dp_aux_native_write(intel_dp,
1733 DP_TRAINING_LANE0_SET,
1734 intel_dp->train_set,
1735 intel_dp->lane_count);
1736 if (ret != intel_dp->lane_count)
1737 return false;
1738 }
a4fc5ed6
KP		 1739
1740 return true;
1741}
1742
33a34e4e 1743/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1744static void
33a34e4e 1745intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1746{
4ef69c7a 1747 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 1748 int i;
1749 uint8_t voltage;
1750 bool clock_recovery = false;
cdb0e95b 1751 int voltage_tries, loop_tries;
ea5b213a 1752 uint32_t DP = intel_dp->DP;
a4fc5ed6 1753
3cf2efb1
CW		 1754 /* Write the link configuration data */
1755 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1756 intel_dp->link_configuration,
1757 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1758
1759 DP |= DP_PORT_EN;
1a2eb460 1760
33a34e4e 1761 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1762 voltage = 0xff;
cdb0e95b
KP		 1763 voltage_tries = 0;
1764 loop_tries = 0;
a4fc5ed6
KP		 1765 clock_recovery = false;
1766 for (;;) {
33a34e4e 1767 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1768 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1769 uint32_t signal_levels;
417e822d 1770
1a2eb460
KP		 1771
1772 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1773 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1774 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1775 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1776 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1777 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1778 } else {
93f62dad
KP		 1779 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1780 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1781 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1782 }
a4fc5ed6 1783
47ea7542 1784 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1785 DP_TRAINING_PATTERN_1 |
1786 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1787 break;
a4fc5ed6
KP		 1788 /* Set training pattern 1 */
1789
3cf2efb1 1790 udelay(100);
93f62dad
KP		 1791 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1792 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1793 break;
93f62dad 1794 }
a4fc5ed6 1795
93f62dad
KP		 1796 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1797 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1798 clock_recovery = true;
1799 break;
1800 }
1801
1802 /* Check to see if we've tried the max voltage */
1803 for (i = 0; i < intel_dp->lane_count; i++)
1804 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1805 break;
0d710688 1806 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1807 ++loop_tries;
1808 if (loop_tries == 5) {
1809 DRM_DEBUG_KMS("too many full retries, give up\n");
1810 break;
1811 }
1812 memset(intel_dp->train_set, 0, 4);
1813 voltage_tries = 0;
1814 continue;
1815 }
a4fc5ed6 1816
3cf2efb1
CW		 1817 /* Check to see if we've tried the same voltage 5 times */
1818 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1819 ++voltage_tries;
1820 if (voltage_tries == 5) {
1821 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1822 break;
cdb0e95b 1823 }
3cf2efb1 1824 } else
cdb0e95b 1825 voltage_tries = 0;
3cf2efb1 1826 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1827
3cf2efb1 1828 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1829 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1830 }
1831
33a34e4e
JB		 1832 intel_dp->DP = DP;
1833}
1834
1835static void
1836intel_dp_complete_link_train(struct intel_dp *intel_dp)
1837{
4ef69c7a 1838 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1839 bool channel_eq = false;
37f80975 1840 int tries, cr_tries;
33a34e4e
JB		 1841 uint32_t DP = intel_dp->DP;
1842
a4fc5ed6
KP		 1843 /* channel equalization */
1844 tries = 0;
37f80975 1845 cr_tries = 0;
a4fc5ed6
KP		 1846 channel_eq = false;
1847 for (;;) {
33a34e4e 1848 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1849 uint32_t signal_levels;
93f62dad 1850 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1851
37f80975
JB		 1852 if (cr_tries > 5) {
1853 DRM_ERROR("failed to train DP, aborting\n");
1854 intel_dp_link_down(intel_dp);
1855 break;
1856 }
1857
1a2eb460
KP		 1858 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1859 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1860 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1861 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1862 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1863 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1864 } else {
93f62dad 1865 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1866 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1867 }
1868
a4fc5ed6 1869 /* channel eq pattern */
47ea7542 1870 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1871 DP_TRAINING_PATTERN_2 |
1872 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1873 break;
1874
3cf2efb1 1875 udelay(400);
93f62dad 1876 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1877 break;
a4fc5ed6 1878
37f80975 1879 /* Make sure clock is still ok */
93f62dad 1880 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1881 intel_dp_start_link_train(intel_dp);
1882 cr_tries++;
1883 continue;
1884 }
1885
93f62dad 1886 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1887 channel_eq = true;
1888 break;
1889 }
a4fc5ed6 1890
37f80975
JB		 1891 /* Try 5 times, then try clock recovery if that fails */
1892 if (tries > 5) {
1893 intel_dp_link_down(intel_dp);
1894 intel_dp_start_link_train(intel_dp);
1895 tries = 0;
1896 cr_tries++;
1897 continue;
1898 }
a4fc5ed6 1899
3cf2efb1 1900 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1901 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1902 ++tries;
869184a6 1903 }
3cf2efb1 1904
47ea7542 1905 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1906}
1907
1908static void
ea5b213a 1909intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1910{
4ef69c7a 1911 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1912 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1913 uint32_t DP = intel_dp->DP;
a4fc5ed6 1914
0c33d8d7 1915 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1916 return;
1917
28c97730 1918 DRM_DEBUG_KMS("\n");
32f9d658 1919
1a2eb460 1920 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1921 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1922 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1923 } else {
1924 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1925 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1926 }
fe255d00 1927 POSTING_READ(intel_dp->output_reg);
5eb08b69 1928
fe255d00 1929 msleep(17);
5eb08b69 1930
493a7081 1931 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1932 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1933 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1934
5bddd17f
EA		 1935 /* Hardware workaround: leaving our transcoder select
1936 * set to transcoder B while it's off will prevent the
1937 * corresponding HDMI output on transcoder A.
1938 *
1939 * Combine this with another hardware workaround:
1940 * transcoder select bit can only be cleared while the
1941 * port is enabled.
1942 */
1943 DP &= ~DP_PIPEB_SELECT;
1944 I915_WRITE(intel_dp->output_reg, DP);
1945
1946 /* Changes to enable or select take place the vblank
1947 * after being written.
1948 */
31acbcc4
CW		 1949 if (crtc == NULL) {
1950 /* We can arrive here never having been attached
1951 * to a CRTC, for instance, due to inheriting
1952 * random state from the BIOS.
1953 *
1954 * If the pipe is not running, play safe and
1955 * wait for the clocks to stabilise before
1956 * continuing.
1957 */
1958 POSTING_READ(intel_dp->output_reg);
1959 msleep(50);
1960 } else
1961 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1962 }
1963
832afda6 1964 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1965 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1966 POSTING_READ(intel_dp->output_reg);
f01eca2e 1967 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1968}
1969
26d61aad
KP		 1970static bool
1971intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1972{
92fd8fd1 1973 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 1974 sizeof(intel_dp->dpcd)) == 0)
1975 return false; /* aux transfer failed */
92fd8fd1 1976
b091cd92
AJ		 1977 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1978 return false; /* DPCD not present */
1979
1980 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1981 DP_DWN_STRM_PORT_PRESENT))
1982 return true; /* native DP sink */
1983
1984 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
1985 return true; /* no per-port downstream info */
1986
1987 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
1988 intel_dp->downstream_ports,
1989 DP_MAX_DOWNSTREAM_PORTS) == 0)
1990 return false; /* downstream port status fetch failed */
1991
1992 return true;
92fd8fd1
KP		 1993}
1994
0d198328
AJ		 1995static void
1996intel_dp_probe_oui(struct intel_dp *intel_dp)
1997{
1998 u8 buf[3];
1999
2000 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2001 return;
2002
351cfc34
DV		 2003 ironlake_edp_panel_vdd_on(intel_dp);
2004
0d198328
AJ		 2005 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2006 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2007 buf[0], buf[1], buf[2]);
2008
2009 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2010 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2011 buf[0], buf[1], buf[2]);
351cfc34
DV		 2012
2013 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2014}
2015
a60f0e38
JB		 2016static bool
2017intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2018{
2019 int ret;
2020
2021 ret = intel_dp_aux_native_read_retry(intel_dp,
2022 DP_DEVICE_SERVICE_IRQ_VECTOR,
2023 sink_irq_vector, 1);
2024 if (!ret)
2025 return false;
2026
2027 return true;
2028}
2029
2030static void
2031intel_dp_handle_test_request(struct intel_dp *intel_dp)
2032{
2033 /* NAK by default */
2034 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2035}
2036
a4fc5ed6
KP		 2037/*
2038 * According to DP spec
2039 * 5.1.2:
2040 * 1. Read DPCD
2041 * 2. Configure link according to Receiver Capabilities
2042 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2043 * 4. Check link status on receipt of hot-plug interrupt
2044 */
2045
2046static void
ea5b213a 2047intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2048{
a60f0e38 2049 u8 sink_irq_vector;
93f62dad 2050 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2051
24e804ba 2052 if (!intel_dp->base.connectors_active)
d2b996ac 2053 return;
59cd09e1 2054
24e804ba 2055 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2056 return;
2057
92fd8fd1 2058 /* Try to read receiver status if the link appears to be up */
93f62dad 2059 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2060 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2061 return;
2062 }
2063
92fd8fd1 2064 /* Now read the DPCD to see if it's actually running */
26d61aad 2065 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2066 intel_dp_link_down(intel_dp);
2067 return;
2068 }
2069
a60f0e38
JB		 2070 /* Try to read the source of the interrupt */
2071 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2072 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2073 /* Clear interrupt source */
2074 intel_dp_aux_native_write_1(intel_dp,
2075 DP_DEVICE_SERVICE_IRQ_VECTOR,
2076 sink_irq_vector);
2077
2078 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2079 intel_dp_handle_test_request(intel_dp);
2080 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2081 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2082 }
2083
93f62dad 2084 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2085 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2086 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2087 intel_dp_start_link_train(intel_dp);
2088 intel_dp_complete_link_train(intel_dp);
2089 }
a4fc5ed6 2090}
a4fc5ed6 2091
07d3dc18 2092/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2093static enum drm_connector_status
26d61aad 2094intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2095{
07d3dc18
AJ		 2096 uint8_t *dpcd = intel_dp->dpcd;
2097 bool hpd;
2098 uint8_t type;
2099
2100 if (!intel_dp_get_dpcd(intel_dp))
2101 return connector_status_disconnected;
2102
2103 /* if there's no downstream port, we're done */
2104 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2105 return connector_status_connected;
2106
2107 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2108 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2109 if (hpd) {
da131a46 2110 uint8_t reg;
07d3dc18 2111 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2112 &reg, 1))
07d3dc18 2113 return connector_status_unknown;
da131a46
AJ		 2114 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2115 : connector_status_disconnected;
07d3dc18
AJ		 2116 }
2117
2118 /* If no HPD, poke DDC gently */
2119 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2120 return connector_status_connected;
07d3dc18
AJ		 2121
2122 /* Well we tried, say unknown for unreliable port types */
2123 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2124 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2125 return connector_status_unknown;
2126
2127 /* Anything else is out of spec, warn and ignore */
2128 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2129 return connector_status_disconnected;
71ba9000
AJ		 2130}
2131
5eb08b69 2132static enum drm_connector_status
a9756bb5 2133ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2134{
5eb08b69
ZW		 2135 enum drm_connector_status status;
2136
fe16d949
CW		 2137 /* Can't disconnect eDP, but you can close the lid... */
2138 if (is_edp(intel_dp)) {
2139 status = intel_panel_detect(intel_dp->base.base.dev);
2140 if (status == connector_status_unknown)
2141 status = connector_status_connected;
2142 return status;
2143 }
01cb9ea6 2144
26d61aad 2145 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2146}
2147
a4fc5ed6 2148static enum drm_connector_status
a9756bb5 2149g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2150{
4ef69c7a 2151 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2152 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2153 uint32_t bit;
5eb08b69 2154
ea5b213a 2155 switch (intel_dp->output_reg) {
a4fc5ed6 2156 case DP_B:
10f76a38 2157 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2158 break;
2159 case DP_C:
10f76a38 2160 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2161 break;
2162 case DP_D:
10f76a38 2163 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2164 break;
2165 default:
2166 return connector_status_unknown;
2167 }
2168
10f76a38 2169 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2170 return connector_status_disconnected;
2171
26d61aad 2172 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2173}
2174
8c241fef
KP		 2175static struct edid *
2176intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2177{
2178 struct intel_dp *intel_dp = intel_attached_dp(connector);
2179 struct edid *edid;
d6f24d0f
JB		 2180 int size;
2181
2182 if (is_edp(intel_dp)) {
2183 if (!intel_dp->edid)
2184 return NULL;
2185
2186 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2187 edid = kmalloc(size, GFP_KERNEL);
2188 if (!edid)
2189 return NULL;
2190
2191 memcpy(edid, intel_dp->edid, size);
2192 return edid;
2193 }
8c241fef 2194
8c241fef 2195 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2196 return edid;
2197}
2198
2199static int
2200intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2201{
2202 struct intel_dp *intel_dp = intel_attached_dp(connector);
2203 int ret;
2204
d6f24d0f
JB		 2205 if (is_edp(intel_dp)) {
2206 drm_mode_connector_update_edid_property(connector,
2207 intel_dp->edid);
2208 ret = drm_add_edid_modes(connector, intel_dp->edid);
2209 drm_edid_to_eld(connector,
2210 intel_dp->edid);
d6f24d0f
JB		 2211 return intel_dp->edid_mode_count;
2212 }
2213
8c241fef 2214 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2215 return ret;
2216}
2217
2218
a9756bb5
ZW		 2219/**
2220 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2221 *
2222 * \return true if DP port is connected.
2223 * \return false if DP port is disconnected.
2224 */
2225static enum drm_connector_status
2226intel_dp_detect(struct drm_connector *connector, bool force)
2227{
2228 struct intel_dp *intel_dp = intel_attached_dp(connector);
2229 struct drm_device *dev = intel_dp->base.base.dev;
2230 enum drm_connector_status status;
2231 struct edid *edid = NULL;
2232
2233 intel_dp->has_audio = false;
2234
2235 if (HAS_PCH_SPLIT(dev))
2236 status = ironlake_dp_detect(intel_dp);
2237 else
2238 status = g4x_dp_detect(intel_dp);
1b9be9d0 2239
ac66ae83
AJ		 2240 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2241 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2242 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2243 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2244
a9756bb5
ZW		 2245 if (status != connector_status_connected)
2246 return status;
2247
0d198328
AJ		 2248 intel_dp_probe_oui(intel_dp);
2249
c3e5f67b
DV		 2250 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2251 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2252 } else {
8c241fef 2253 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2254 if (edid) {
2255 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2256 kfree(edid);
2257 }
a9756bb5
ZW		 2258 }
2259
2260 return connector_status_connected;
a4fc5ed6
KP		 2261}
2262
2263static int intel_dp_get_modes(struct drm_connector *connector)
2264{
df0e9248 2265 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2266 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 int ret;
a4fc5ed6
KP		 2269
2270 /* We should parse the EDID data and find out if it has an audio sink
2271 */
2272
8c241fef 2273 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2274 if (ret) {
d15456de 2275 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2276 struct drm_display_mode *newmode;
2277 list_for_each_entry(newmode, &connector->probed_modes,
2278 head) {
d15456de
KP		 2279 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2280 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2281 drm_mode_duplicate(dev, newmode);
2282 break;
2283 }
2284 }
2285 }
32f9d658 2286 return ret;
b9efc480 2287 }
32f9d658
ZW		 2288
2289 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2290 if (is_edp(intel_dp)) {
47f0eb22 2291 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2292 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2293 intel_dp->panel_fixed_mode =
47f0eb22 2294 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2295 if (intel_dp->panel_fixed_mode) {
2296 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2297 DRM_MODE_TYPE_PREFERRED;
2298 }
2299 }
d15456de 2300 if (intel_dp->panel_fixed_mode) {
32f9d658 2301 struct drm_display_mode *mode;
d15456de 2302 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2303 drm_mode_probed_add(connector, mode);
2304 return 1;
2305 }
2306 }
2307 return 0;
a4fc5ed6
KP		 2308}
2309
1aad7ac0
CW		 2310static bool
2311intel_dp_detect_audio(struct drm_connector *connector)
2312{
2313 struct intel_dp *intel_dp = intel_attached_dp(connector);
2314 struct edid *edid;
2315 bool has_audio = false;
2316
8c241fef 2317 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2318 if (edid) {
2319 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2320 kfree(edid);
2321 }
2322
2323 return has_audio;
2324}
2325
f684960e
CW		 2326static int
2327intel_dp_set_property(struct drm_connector *connector,
2328 struct drm_property *property,
2329 uint64_t val)
2330{
e953fd7b 2331 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2332 struct intel_dp *intel_dp = intel_attached_dp(connector);
2333 int ret;
2334
2335 ret = drm_connector_property_set_value(connector, property, val);
2336 if (ret)
2337 return ret;
2338
3f43c48d 2339 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2340 int i = val;
2341 bool has_audio;
2342
2343 if (i == intel_dp->force_audio)
f684960e
CW		 2344 return 0;
2345
1aad7ac0 2346 intel_dp->force_audio = i;
f684960e 2347
c3e5f67b 2348 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2349 has_audio = intel_dp_detect_audio(connector);
2350 else
c3e5f67b 2351 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2352
2353 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2354 return 0;
2355
1aad7ac0 2356 intel_dp->has_audio = has_audio;
f684960e
CW		 2357 goto done;
2358 }
2359
e953fd7b
CW		 2360 if (property == dev_priv->broadcast_rgb_property) {
2361 if (val == !!intel_dp->color_range)
2362 return 0;
2363
2364 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2365 goto done;
2366 }
2367
f684960e
CW		 2368 return -EINVAL;
2369
2370done:
2371 if (intel_dp->base.base.crtc) {
2372 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2373 intel_set_mode(crtc, &crtc->mode,
2374 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2375 }
2376
2377 return 0;
2378}
2379
a4fc5ed6 2380static void
0206e353 2381intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2382{
aaa6fd2a
MG		 2383 struct drm_device *dev = connector->dev;
2384
2385 if (intel_dpd_is_edp(dev))
2386 intel_panel_destroy_backlight(dev);
2387
a4fc5ed6
KP		 2388 drm_sysfs_connector_remove(connector);
2389 drm_connector_cleanup(connector);
55f78c43 2390 kfree(connector);
a4fc5ed6
KP		 2391}
2392
24d05927
DV		 2393static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2394{
2395 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2396
2397 i2c_del_adapter(&intel_dp->adapter);
2398 drm_encoder_cleanup(encoder);
bd943159 2399 if (is_edp(intel_dp)) {
d6f24d0f 2400 kfree(intel_dp->edid);
bd943159
KP		 2401 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2402 ironlake_panel_vdd_off_sync(intel_dp);
2403 }
24d05927
DV		 2404 kfree(intel_dp);
2405}
2406
a4fc5ed6 2407static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2408 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2409 .mode_set = intel_dp_mode_set,
1f703855 2410 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2411};
2412
2413static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2414 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2415 .detect = intel_dp_detect,
2416 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2417 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2418 .destroy = intel_dp_destroy,
2419};
2420
2421static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2422 .get_modes = intel_dp_get_modes,
2423 .mode_valid = intel_dp_mode_valid,
df0e9248 2424 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2425};
2426
a4fc5ed6 2427static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2428 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2429};
2430
995b6762 2431static void
21d40d37 2432intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2433{
ea5b213a 2434 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2435
885a5014 2436 intel_dp_check_link_status(intel_dp);
c8110e52 2437}
6207937d 2438
e3421a18
ZW		 2439/* Return which DP Port should be selected for Transcoder DP control */
2440int
0206e353 2441intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2442{
2443 struct drm_device *dev = crtc->dev;
6c2b7c12 2444 struct intel_encoder *encoder;
e3421a18 2445
6c2b7c12
DV		 2446 for_each_encoder_on_crtc(dev, crtc, encoder) {
2447 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2448
417e822d
KP		 2449 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2450 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2451 return intel_dp->output_reg;
e3421a18 2452 }
ea5b213a 2453
e3421a18
ZW		 2454 return -1;
2455}
2456
36e83a18 2457/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2458bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2459{
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct child_device_config *p_child;
2462 int i;
2463
2464 if (!dev_priv->child_dev_num)
2465 return false;
2466
2467 for (i = 0; i < dev_priv->child_dev_num; i++) {
2468 p_child = dev_priv->child_dev + i;
2469
2470 if (p_child->dvo_port == PORT_IDPD &&
2471 p_child->device_type == DEVICE_TYPE_eDP)
2472 return true;
2473 }
2474 return false;
2475}
2476
f684960e
CW		 2477static void
2478intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2479{
3f43c48d 2480 intel_attach_force_audio_property(connector);
e953fd7b 2481 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2482}
2483
a4fc5ed6 2484void
ab9d7c30 2485intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2486{
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2488 struct drm_connector *connector;
ea5b213a 2489 struct intel_dp *intel_dp;
21d40d37 2490 struct intel_encoder *intel_encoder;
55f78c43 2491 struct intel_connector *intel_connector;
5eb08b69 2492 const char *name = NULL;
b329530c 2493 int type;
a4fc5ed6 2494
ea5b213a
CW		 2495 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2496 if (!intel_dp)
a4fc5ed6
KP		 2497 return;
2498
3d3dc149 2499 intel_dp->output_reg = output_reg;
ab9d7c30 2500 intel_dp->port = port;
0767935e
DV		 2501 /* Preserve the current hw state. */
2502 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2503
55f78c43
ZW		 2504 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2505 if (!intel_connector) {
ea5b213a 2506 kfree(intel_dp);
55f78c43
ZW		 2507 return;
2508 }
ea5b213a 2509 intel_encoder = &intel_dp->base;
55f78c43 2510
ea5b213a 2511 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2512 if (intel_dpd_is_edp(dev))
ea5b213a 2513 intel_dp->is_pch_edp = true;
b329530c 2514
cfcb0fc9 2515 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2516 type = DRM_MODE_CONNECTOR_eDP;
2517 intel_encoder->type = INTEL_OUTPUT_EDP;
2518 } else {
2519 type = DRM_MODE_CONNECTOR_DisplayPort;
2520 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2521 }
2522
55f78c43 2523 connector = &intel_connector->base;
b329530c 2524 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2525 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2526
eb1f8e4f
DA		 2527 connector->polled = DRM_CONNECTOR_POLL_HPD;
2528
66a9278e 2529 intel_encoder->cloneable = false;
f8aed700 2530
66a9278e
DV		 2531 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2532 ironlake_panel_vdd_work);
6251ec0a 2533
27f8227b 2534 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2535
a4fc5ed6
KP		 2536 connector->interlace_allowed = true;
2537 connector->doublescan_allowed = 0;
2538
4ef69c7a 2539 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2540 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2541 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2542
df0e9248 2543 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2544 drm_sysfs_connector_add(connector);
2545
e8cb4558 2546 intel_encoder->enable = intel_enable_dp;
2bd2ad64 2547 intel_encoder->pre_enable = intel_pre_enable_dp;
e8cb4558 2548 intel_encoder->disable = intel_disable_dp;
2bd2ad64 2549 intel_encoder->post_disable = intel_post_disable_dp;
19d8fe15
DV		 2550 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2551 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2552
a4fc5ed6 2553 /* Set up the DDC bus. */
ab9d7c30
PZ		 2554 switch (port) {
2555 case PORT_A:
2556 name = "DPDDC-A";
2557 break;
2558 case PORT_B:
2559 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2560 name = "DPDDC-B";
2561 break;
2562 case PORT_C:
2563 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2564 name = "DPDDC-C";
2565 break;
2566 case PORT_D:
2567 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2568 name = "DPDDC-D";
2569 break;
2570 default:
2571 WARN(1, "Invalid port %c\n", port_name(port));
2572 break;
5eb08b69
ZW		 2573 }
2574
89667383
JB		 2575 /* Cache some DPCD data in the eDP case */
2576 if (is_edp(intel_dp)) {
f01eca2e
KP		 2577 struct edp_power_seq cur, vbt;
2578 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2579
2580 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2581 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2582 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2583
bfa3384a
JB		 2584 if (!pp_on || !pp_off || !pp_div) {
2585 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2586 intel_dp_encoder_destroy(&intel_dp->base.base);
2587 intel_dp_destroy(&intel_connector->base);
2588 return;
2589 }
2590
f01eca2e
KP		 2591 /* Pull timing values out of registers */
2592 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2593 PANEL_POWER_UP_DELAY_SHIFT;
2594
2595 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2596 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2597
f01eca2e
KP		 2598 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2599 PANEL_LIGHT_OFF_DELAY_SHIFT;
2600
2601 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2602 PANEL_POWER_DOWN_DELAY_SHIFT;
2603
2604 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2605 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2606
2607 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2608 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2609
2610 vbt = dev_priv->edp.pps;
2611
2612 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2613 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2614
2615#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2616
2617 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2618 intel_dp->backlight_on_delay = get_delay(t8);
2619 intel_dp->backlight_off_delay = get_delay(t9);
2620 intel_dp->panel_power_down_delay = get_delay(t10);
2621 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2622
2623 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2624 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2625 intel_dp->panel_power_cycle_delay);
2626
2627 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2628 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
c1f05264
DA		 2629 }
2630
2631 intel_dp_i2c_init(intel_dp, intel_connector, name);
2632
2633 if (is_edp(intel_dp)) {
2634 bool ret;
2635 struct edid *edid;
5d613501
JB		 2636
2637 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2638 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2639 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2640
59f3e272 2641 if (ret) {
7183dc29
JB		 2642 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2643 dev_priv->no_aux_handshake =
2644 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2645 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2646 } else {
3d3dc149 2647 /* if this fails, presume the device is a ghost */
48898b03 2648 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2649 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2650 intel_dp_destroy(&intel_connector->base);
3d3dc149 2651 return;
89667383 2652 }
89667383 2653
d6f24d0f
JB		 2654 ironlake_edp_panel_vdd_on(intel_dp);
2655 edid = drm_get_edid(connector, &intel_dp->adapter);
2656 if (edid) {
2657 drm_mode_connector_update_edid_property(connector,
2658 edid);
2659 intel_dp->edid_mode_count =
2660 drm_add_edid_modes(connector, edid);
2661 drm_edid_to_eld(connector, edid);
2662 intel_dp->edid = edid;
2663 }
2664 ironlake_edp_panel_vdd_off(intel_dp, false);
2665 }
552fb0b7 2666
21d40d37 2667 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2668
4d926461 2669 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2670 dev_priv->int_edp_connector = connector;
2671 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2672 }
2673
f684960e
CW		 2674 intel_dp_add_properties(intel_dp, connector);
2675
a4fc5ed6
KP		 2676 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2677 * 0xd. Failure to do so will result in spurious interrupts being
2678 * generated on the port when a cable is not attached.
2679 */
2680 if (IS_G4X(dev) && !IS_GM45(dev)) {
2681 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2682 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2683 }
2684}
ubuntu-bionic-kernel mirror