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drm/i915: fix up a raw 64bit divide
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include "drmP.h"
30#include "drm.h"
31#include "drm_crtc.h"
32#include "drm_crtc_helper.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
36#include "intel_dp.h"
37
38#define DP_LINK_STATUS_SIZE 6
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41#define DP_LINK_CONFIGURATION_SIZE 9
42
43struct intel_dp_priv {
44 uint32_t output_reg;
45 uint32_t DP;
46 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
47 uint32_t save_DP;
48 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
49 bool has_audio;
c8110e52 50 int dpms_mode;
a4fc5ed6
KP		 51 uint8_t link_bw;
52 uint8_t lane_count;
53 uint8_t dpcd[4];
54 struct intel_output *intel_output;
55 struct i2c_adapter adapter;
56 struct i2c_algo_dp_aux_data algo;
57};
58
59static void
60intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
61 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
62
63static void
64intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
65
66static int
67intel_dp_max_lane_count(struct intel_output *intel_output)
68{
69 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
70 int max_lane_count = 4;
71
72 if (dp_priv->dpcd[0] >= 0x11) {
73 max_lane_count = dp_priv->dpcd[2] & 0x1f;
74 switch (max_lane_count) {
75 case 1: case 2: case 4:
76 break;
77 default:
78 max_lane_count = 4;
79 }
80 }
81 return max_lane_count;
82}
83
84static int
85intel_dp_max_link_bw(struct intel_output *intel_output)
86{
87 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
88 int max_link_bw = dp_priv->dpcd[1];
89
90 switch (max_link_bw) {
91 case DP_LINK_BW_1_62:
92 case DP_LINK_BW_2_7:
93 break;
94 default:
95 max_link_bw = DP_LINK_BW_1_62;
96 break;
97 }
98 return max_link_bw;
99}
100
101static int
102intel_dp_link_clock(uint8_t link_bw)
103{
104 if (link_bw == DP_LINK_BW_2_7)
105 return 270000;
106 else
107 return 162000;
108}
109
110/* I think this is a fiction */
111static int
112intel_dp_link_required(int pixel_clock)
113{
114 return pixel_clock * 3;
115}
116
117static int
118intel_dp_mode_valid(struct drm_connector *connector,
119 struct drm_display_mode *mode)
120{
121 struct intel_output *intel_output = to_intel_output(connector);
122 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
123 int max_lanes = intel_dp_max_lane_count(intel_output);
124
125 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
126 return MODE_CLOCK_HIGH;
127
128 if (mode->clock < 10000)
129 return MODE_CLOCK_LOW;
130
131 return MODE_OK;
132}
133
134static uint32_t
135pack_aux(uint8_t *src, int src_bytes)
136{
137 int i;
138 uint32_t v = 0;
139
140 if (src_bytes > 4)
141 src_bytes = 4;
142 for (i = 0; i < src_bytes; i++)
143 v |= ((uint32_t) src[i]) << ((3-i) * 8);
144 return v;
145}
146
147static void
148unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
149{
150 int i;
151 if (dst_bytes > 4)
152 dst_bytes = 4;
153 for (i = 0; i < dst_bytes; i++)
154 dst[i] = src >> ((3-i) * 8);
155}
156
fb0f8fbf
KP		 157/* hrawclock is 1/4 the FSB frequency */
158static int
159intel_hrawclk(struct drm_device *dev)
160{
161 struct drm_i915_private *dev_priv = dev->dev_private;
162 uint32_t clkcfg;
163
164 clkcfg = I915_READ(CLKCFG);
165 switch (clkcfg & CLKCFG_FSB_MASK) {
166 case CLKCFG_FSB_400:
167 return 100;
168 case CLKCFG_FSB_533:
169 return 133;
170 case CLKCFG_FSB_667:
171 return 166;
172 case CLKCFG_FSB_800:
173 return 200;
174 case CLKCFG_FSB_1067:
175 return 266;
176 case CLKCFG_FSB_1333:
177 return 333;
178 /* these two are just a guess; one of them might be right */
179 case CLKCFG_FSB_1600:
180 case CLKCFG_FSB_1600_ALT:
181 return 400;
182 default:
183 return 133;
184 }
185}
186
a4fc5ed6
KP		 187static int
188intel_dp_aux_ch(struct intel_output *intel_output,
189 uint8_t *send, int send_bytes,
190 uint8_t *recv, int recv_size)
191{
192 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
193 uint32_t output_reg = dp_priv->output_reg;
194 struct drm_device *dev = intel_output->base.dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 uint32_t ch_ctl = output_reg + 0x10;
197 uint32_t ch_data = ch_ctl + 4;
198 int i;
199 int recv_bytes;
200 uint32_t ctl;
201 uint32_t status;
fb0f8fbf
KP		 202 uint32_t aux_clock_divider;
203 int try;
a4fc5ed6
KP		 204
205 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 206 * and would like to run at 2MHz. So, take the
207 * hrawclk value and divide by 2 and use that
a4fc5ed6 208 */
fb0f8fbf
KP		 209 aux_clock_divider = intel_hrawclk(dev) / 2;
210 /* Must try at least 3 times according to DP spec */
211 for (try = 0; try < 5; try++) {
212 /* Load the send data into the aux channel data registers */
213 for (i = 0; i < send_bytes; i += 4) {
214 uint32_t d = pack_aux(send + i, send_bytes - i);;
215
216 I915_WRITE(ch_data + i, d);
217 }
218
219 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
220 DP_AUX_CH_CTL_TIME_OUT_400us |
221 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
222 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
223 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
224 DP_AUX_CH_CTL_DONE |
225 DP_AUX_CH_CTL_TIME_OUT_ERROR |
226 DP_AUX_CH_CTL_RECEIVE_ERROR);
227
228 /* Send the command and wait for it to complete */
229 I915_WRITE(ch_ctl, ctl);
230 (void) I915_READ(ch_ctl);
231 for (;;) {
232 udelay(100);
233 status = I915_READ(ch_ctl);
234 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
235 break;
236 }
237
238 /* Clear done status and any errors */
239 I915_WRITE(ch_ctl, (ctl |
240 DP_AUX_CH_CTL_DONE |
241 DP_AUX_CH_CTL_TIME_OUT_ERROR |
242 DP_AUX_CH_CTL_RECEIVE_ERROR));
243 (void) I915_READ(ch_ctl);
244 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 245 break;
246 }
247
a4fc5ed6
KP		 248 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
249 printk(KERN_ERR "dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 250 return -EBUSY;
a4fc5ed6
KP		 251 }
252
253 /* Check for timeout or receive error.
254 * Timeouts occur when the sink is not connected
255 */
a5b3da54
KP		 256 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
257 printk(KERN_ERR "dp_aux_ch receive error status 0x%08x\n", status);
258 return -EIO;
259 }
260 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
261 printk(KERN_ERR "dp_aux_ch timeout status 0x%08x\n", status);
262 return -ETIMEDOUT;
a4fc5ed6
KP		 263 }
264
265 /* Unload any bytes sent back from the other side */
266 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
267 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
268
269 if (recv_bytes > recv_size)
270 recv_bytes = recv_size;
271
272 for (i = 0; i < recv_bytes; i += 4) {
273 uint32_t d = I915_READ(ch_data + i);
274
275 unpack_aux(d, recv + i, recv_bytes - i);
276 }
277
278 return recv_bytes;
279}
280
281/* Write data to the aux channel in native mode */
282static int
283intel_dp_aux_native_write(struct intel_output *intel_output,
284 uint16_t address, uint8_t *send, int send_bytes)
285{
286 int ret;
287 uint8_t msg[20];
288 int msg_bytes;
289 uint8_t ack;
290
291 if (send_bytes > 16)
292 return -1;
293 msg[0] = AUX_NATIVE_WRITE << 4;
294 msg[1] = address >> 8;
295 msg[2] = address;
296 msg[3] = send_bytes - 1;
297 memcpy(&msg[4], send, send_bytes);
298 msg_bytes = send_bytes + 4;
299 for (;;) {
300 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
301 if (ret < 0)
302 return ret;
303 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
304 break;
305 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
306 udelay(100);
307 else
a5b3da54 308 return -EIO;
a4fc5ed6
KP		 309 }
310 return send_bytes;
311}
312
313/* Write a single byte to the aux channel in native mode */
314static int
315intel_dp_aux_native_write_1(struct intel_output *intel_output,
316 uint16_t address, uint8_t byte)
317{
318 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
319}
320
321/* read bytes from a native aux channel */
322static int
323intel_dp_aux_native_read(struct intel_output *intel_output,
324 uint16_t address, uint8_t *recv, int recv_bytes)
325{
326 uint8_t msg[4];
327 int msg_bytes;
328 uint8_t reply[20];
329 int reply_bytes;
330 uint8_t ack;
331 int ret;
332
333 msg[0] = AUX_NATIVE_READ << 4;
334 msg[1] = address >> 8;
335 msg[2] = address & 0xff;
336 msg[3] = recv_bytes - 1;
337
338 msg_bytes = 4;
339 reply_bytes = recv_bytes + 1;
340
341 for (;;) {
342 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
343 reply, reply_bytes);
a5b3da54
KP		 344 if (ret == 0)
345 return -EPROTO;
346 if (ret < 0)
a4fc5ed6
KP		 347 return ret;
348 ack = reply[0];
349 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
350 memcpy(recv, reply + 1, ret - 1);
351 return ret - 1;
352 }
353 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
354 udelay(100);
355 else
a5b3da54 356 return -EIO;
a4fc5ed6
KP		 357 }
358}
359
360static int
361intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
362 uint8_t *send, int send_bytes,
363 uint8_t *recv, int recv_bytes)
364{
365 struct intel_dp_priv *dp_priv = container_of(adapter,
366 struct intel_dp_priv,
367 adapter);
368 struct intel_output *intel_output = dp_priv->intel_output;
369
370 return intel_dp_aux_ch(intel_output,
371 send, send_bytes, recv, recv_bytes);
372}
373
374static int
375intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
376{
377 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
378
379 DRM_ERROR("i2c_init %s\n", name);
380 dp_priv->algo.running = false;
381 dp_priv->algo.address = 0;
382 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
383
384 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
385 dp_priv->adapter.owner = THIS_MODULE;
386 dp_priv->adapter.class = I2C_CLASS_DDC;
387 strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
388 dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
389 dp_priv->adapter.algo_data = &dp_priv->algo;
390 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
391
392 return i2c_dp_aux_add_bus(&dp_priv->adapter);
393}
394
395static bool
396intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
397 struct drm_display_mode *adjusted_mode)
398{
399 struct intel_output *intel_output = enc_to_intel_output(encoder);
400 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
401 int lane_count, clock;
402 int max_lane_count = intel_dp_max_lane_count(intel_output);
403 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
404 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
405
406 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
407 for (clock = 0; clock <= max_clock; clock++) {
408 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
409
410 if (intel_dp_link_required(mode->clock) <= link_avail) {
411 dp_priv->link_bw = bws[clock];
412 dp_priv->lane_count = lane_count;
413 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
414 printk(KERN_ERR "link bw %02x lane count %d clock %d\n",
415 dp_priv->link_bw, dp_priv->lane_count,
416 adjusted_mode->clock);
417 return true;
418 }
419 }
420 }
421 return false;
422}
423
424struct intel_dp_m_n {
425 uint32_t tu;
426 uint32_t gmch_m;
427 uint32_t gmch_n;
428 uint32_t link_m;
429 uint32_t link_n;
430};
431
432static void
433intel_reduce_ratio(uint32_t *num, uint32_t *den)
434{
435 while (*num > 0xffffff || *den > 0xffffff) {
436 *num >>= 1;
437 *den >>= 1;
438 }
439}
440
441static void
442intel_dp_compute_m_n(int bytes_per_pixel,
443 int nlanes,
444 int pixel_clock,
445 int link_clock,
446 struct intel_dp_m_n *m_n)
447{
448 m_n->tu = 64;
449 m_n->gmch_m = pixel_clock * bytes_per_pixel;
450 m_n->gmch_n = link_clock * nlanes;
451 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
452 m_n->link_m = pixel_clock;
453 m_n->link_n = link_clock;
454 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
455}
456
457void
458intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
459 struct drm_display_mode *adjusted_mode)
460{
461 struct drm_device *dev = crtc->dev;
462 struct drm_mode_config *mode_config = &dev->mode_config;
463 struct drm_connector *connector;
464 struct drm_i915_private *dev_priv = dev->dev_private;
465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
466 int lane_count = 4;
467 struct intel_dp_m_n m_n;
468
469 /*
470 * Find the lane count in the intel_output private
471 */
472 list_for_each_entry(connector, &mode_config->connector_list, head) {
473 struct intel_output *intel_output = to_intel_output(connector);
474 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
475
476 if (!connector->encoder || connector->encoder->crtc != crtc)
477 continue;
478
479 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
480 lane_count = dp_priv->lane_count;
481 break;
482 }
483 }
484
485 /*
486 * Compute the GMCH and Link ratios. The '3' here is
487 * the number of bytes_per_pixel post-LUT, which we always
488 * set up for 8-bits of R/G/B, or 3 bytes total.
489 */
490 intel_dp_compute_m_n(3, lane_count,
491 mode->clock, adjusted_mode->clock, &m_n);
492
493 if (intel_crtc->pipe == 0) {
494 I915_WRITE(PIPEA_GMCH_DATA_M,
495 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
496 m_n.gmch_m);
497 I915_WRITE(PIPEA_GMCH_DATA_N,
498 m_n.gmch_n);
499 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
500 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
501 } else {
502 I915_WRITE(PIPEB_GMCH_DATA_M,
503 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
504 m_n.gmch_m);
505 I915_WRITE(PIPEB_GMCH_DATA_N,
506 m_n.gmch_n);
507 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
508 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
509 }
510}
511
512static void
513intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
514 struct drm_display_mode *adjusted_mode)
515{
516 struct intel_output *intel_output = enc_to_intel_output(encoder);
517 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
518 struct drm_crtc *crtc = intel_output->enc.crtc;
519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
520
521 dp_priv->DP = (DP_LINK_TRAIN_OFF |
522 DP_VOLTAGE_0_4 |
523 DP_PRE_EMPHASIS_0 |
524 DP_SYNC_VS_HIGH |
525 DP_SYNC_HS_HIGH);
526
527 switch (dp_priv->lane_count) {
528 case 1:
529 dp_priv->DP |= DP_PORT_WIDTH_1;
530 break;
531 case 2:
532 dp_priv->DP |= DP_PORT_WIDTH_2;
533 break;
534 case 4:
535 dp_priv->DP |= DP_PORT_WIDTH_4;
536 break;
537 }
538 if (dp_priv->has_audio)
539 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
540
541 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
542 dp_priv->link_configuration[0] = dp_priv->link_bw;
543 dp_priv->link_configuration[1] = dp_priv->lane_count;
544
545 /*
546 * Check for DPCD version > 1.1,
547 * enable enahanced frame stuff in that case
548 */
549 if (dp_priv->dpcd[0] >= 0x11) {
550 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
551 dp_priv->DP |= DP_ENHANCED_FRAMING;
552 }
553
554 if (intel_crtc->pipe == 1)
555 dp_priv->DP |= DP_PIPEB_SELECT;
556}
557
558
559static void
560intel_dp_dpms(struct drm_encoder *encoder, int mode)
561{
562 struct intel_output *intel_output = enc_to_intel_output(encoder);
563 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
564 struct drm_device *dev = intel_output->base.dev;
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
567
568 if (mode != DRM_MODE_DPMS_ON) {
569 if (dp_reg & DP_PORT_EN)
570 intel_dp_link_down(intel_output, dp_priv->DP);
571 } else {
572 if (!(dp_reg & DP_PORT_EN))
573 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
574 }
c8110e52 575 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 576}
577
578/*
579 * Fetch AUX CH registers 0x202 - 0x207 which contain
580 * link status information
581 */
582static bool
583intel_dp_get_link_status(struct intel_output *intel_output,
584 uint8_t link_status[DP_LINK_STATUS_SIZE])
585{
586 int ret;
587
588 ret = intel_dp_aux_native_read(intel_output,
589 DP_LANE0_1_STATUS,
590 link_status, DP_LINK_STATUS_SIZE);
591 if (ret != DP_LINK_STATUS_SIZE)
592 return false;
593 return true;
594}
595
596static uint8_t
597intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
598 int r)
599{
600 return link_status[r - DP_LANE0_1_STATUS];
601}
602
603static void
604intel_dp_save(struct drm_connector *connector)
605{
606 struct intel_output *intel_output = to_intel_output(connector);
607 struct drm_device *dev = intel_output->base.dev;
608 struct drm_i915_private *dev_priv = dev->dev_private;
609 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
610
611 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
612 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
613 dp_priv->save_link_configuration,
614 sizeof (dp_priv->save_link_configuration));
615}
616
617static uint8_t
618intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
619 int lane)
620{
621 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
622 int s = ((lane & 1) ?
623 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
624 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
625 uint8_t l = intel_dp_link_status(link_status, i);
626
627 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
628}
629
630static uint8_t
631intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
632 int lane)
633{
634 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
635 int s = ((lane & 1) ?
636 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
637 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
638 uint8_t l = intel_dp_link_status(link_status, i);
639
640 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
641}
642
643
644#if 0
645static char *voltage_names[] = {
646 "0.4V", "0.6V", "0.8V", "1.2V"
647};
648static char *pre_emph_names[] = {
649 "0dB", "3.5dB", "6dB", "9.5dB"
650};
651static char *link_train_names[] = {
652 "pattern 1", "pattern 2", "idle", "off"
653};
654#endif
655
656/*
657 * These are source-specific values; current Intel hardware supports
658 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
659 */
660#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
661
662static uint8_t
663intel_dp_pre_emphasis_max(uint8_t voltage_swing)
664{
665 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
666 case DP_TRAIN_VOLTAGE_SWING_400:
667 return DP_TRAIN_PRE_EMPHASIS_6;
668 case DP_TRAIN_VOLTAGE_SWING_600:
669 return DP_TRAIN_PRE_EMPHASIS_6;
670 case DP_TRAIN_VOLTAGE_SWING_800:
671 return DP_TRAIN_PRE_EMPHASIS_3_5;
672 case DP_TRAIN_VOLTAGE_SWING_1200:
673 default:
674 return DP_TRAIN_PRE_EMPHASIS_0;
675 }
676}
677
678static void
679intel_get_adjust_train(struct intel_output *intel_output,
680 uint8_t link_status[DP_LINK_STATUS_SIZE],
681 int lane_count,
682 uint8_t train_set[4])
683{
684 uint8_t v = 0;
685 uint8_t p = 0;
686 int lane;
687
688 for (lane = 0; lane < lane_count; lane++) {
689 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
690 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
691
692 if (this_v > v)
693 v = this_v;
694 if (this_p > p)
695 p = this_p;
696 }
697
698 if (v >= I830_DP_VOLTAGE_MAX)
699 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
700
701 if (p >= intel_dp_pre_emphasis_max(v))
702 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
703
704 for (lane = 0; lane < 4; lane++)
705 train_set[lane] = v | p;
706}
707
708static uint32_t
709intel_dp_signal_levels(uint8_t train_set, int lane_count)
710{
711 uint32_t signal_levels = 0;
712
713 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
714 case DP_TRAIN_VOLTAGE_SWING_400:
715 default:
716 signal_levels |= DP_VOLTAGE_0_4;
717 break;
718 case DP_TRAIN_VOLTAGE_SWING_600:
719 signal_levels |= DP_VOLTAGE_0_6;
720 break;
721 case DP_TRAIN_VOLTAGE_SWING_800:
722 signal_levels |= DP_VOLTAGE_0_8;
723 break;
724 case DP_TRAIN_VOLTAGE_SWING_1200:
725 signal_levels |= DP_VOLTAGE_1_2;
726 break;
727 }
728 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
729 case DP_TRAIN_PRE_EMPHASIS_0:
730 default:
731 signal_levels |= DP_PRE_EMPHASIS_0;
732 break;
733 case DP_TRAIN_PRE_EMPHASIS_3_5:
734 signal_levels |= DP_PRE_EMPHASIS_3_5;
735 break;
736 case DP_TRAIN_PRE_EMPHASIS_6:
737 signal_levels |= DP_PRE_EMPHASIS_6;
738 break;
739 case DP_TRAIN_PRE_EMPHASIS_9_5:
740 signal_levels |= DP_PRE_EMPHASIS_9_5;
741 break;
742 }
743 return signal_levels;
744}
745
746static uint8_t
747intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
748 int lane)
749{
750 int i = DP_LANE0_1_STATUS + (lane >> 1);
751 int s = (lane & 1) * 4;
752 uint8_t l = intel_dp_link_status(link_status, i);
753
754 return (l >> s) & 0xf;
755}
756
757/* Check for clock recovery is done on all channels */
758static bool
759intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
760{
761 int lane;
762 uint8_t lane_status;
763
764 for (lane = 0; lane < lane_count; lane++) {
765 lane_status = intel_get_lane_status(link_status, lane);
766 if ((lane_status & DP_LANE_CR_DONE) == 0)
767 return false;
768 }
769 return true;
770}
771
772/* Check to see if channel eq is done on all channels */
773#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
774 DP_LANE_CHANNEL_EQ_DONE|\
775 DP_LANE_SYMBOL_LOCKED)
776static bool
777intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
778{
779 uint8_t lane_align;
780 uint8_t lane_status;
781 int lane;
782
783 lane_align = intel_dp_link_status(link_status,
784 DP_LANE_ALIGN_STATUS_UPDATED);
785 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
786 return false;
787 for (lane = 0; lane < lane_count; lane++) {
788 lane_status = intel_get_lane_status(link_status, lane);
789 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
790 return false;
791 }
792 return true;
793}
794
795static bool
796intel_dp_set_link_train(struct intel_output *intel_output,
797 uint32_t dp_reg_value,
798 uint8_t dp_train_pat,
799 uint8_t train_set[4],
800 bool first)
801{
802 struct drm_device *dev = intel_output->base.dev;
803 struct drm_i915_private *dev_priv = dev->dev_private;
804 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
805 int ret;
806
807 I915_WRITE(dp_priv->output_reg, dp_reg_value);
808 POSTING_READ(dp_priv->output_reg);
809 if (first)
810 intel_wait_for_vblank(dev);
811
812 intel_dp_aux_native_write_1(intel_output,
813 DP_TRAINING_PATTERN_SET,
814 dp_train_pat);
815
816 ret = intel_dp_aux_native_write(intel_output,
817 DP_TRAINING_LANE0_SET, train_set, 4);
818 if (ret != 4)
819 return false;
820
821 return true;
822}
823
824static void
825intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
826 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
827{
828 struct drm_device *dev = intel_output->base.dev;
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
831 uint8_t train_set[4];
832 uint8_t link_status[DP_LINK_STATUS_SIZE];
833 int i;
834 uint8_t voltage;
835 bool clock_recovery = false;
836 bool channel_eq = false;
837 bool first = true;
838 int tries;
839
840 /* Write the link configuration data */
841 intel_dp_aux_native_write(intel_output, 0x100,
842 link_configuration, DP_LINK_CONFIGURATION_SIZE);
843
844 DP |= DP_PORT_EN;
845 DP &= ~DP_LINK_TRAIN_MASK;
846 memset(train_set, 0, 4);
847 voltage = 0xff;
848 tries = 0;
849 clock_recovery = false;
850 for (;;) {
851 /* Use train_set[0] to set the voltage and pre emphasis values */
852 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
853 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
854
855 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
856 DP_TRAINING_PATTERN_1, train_set, first))
857 break;
858 first = false;
859 /* Set training pattern 1 */
860
861 udelay(100);
862 if (!intel_dp_get_link_status(intel_output, link_status))
863 break;
864
865 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
866 clock_recovery = true;
867 break;
868 }
869
870 /* Check to see if we've tried the max voltage */
871 for (i = 0; i < dp_priv->lane_count; i++)
872 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
873 break;
874 if (i == dp_priv->lane_count)
875 break;
876
877 /* Check to see if we've tried the same voltage 5 times */
878 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
879 ++tries;
880 if (tries == 5)
881 break;
882 } else
883 tries = 0;
884 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
885
886 /* Compute new train_set as requested by target */
887 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
888 }
889
890 /* channel equalization */
891 tries = 0;
892 channel_eq = false;
893 for (;;) {
894 /* Use train_set[0] to set the voltage and pre emphasis values */
895 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
896 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
897
898 /* channel eq pattern */
899 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
900 DP_TRAINING_PATTERN_2, train_set,
901 false))
902 break;
903
904 udelay(400);
905 if (!intel_dp_get_link_status(intel_output, link_status))
906 break;
907
908 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
909 channel_eq = true;
910 break;
911 }
912
913 /* Try 5 times */
914 if (tries > 5)
915 break;
916
917 /* Compute new train_set as requested by target */
918 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
919 ++tries;
920 }
921
922 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
923 POSTING_READ(dp_priv->output_reg);
924 intel_dp_aux_native_write_1(intel_output,
925 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
926}
927
928static void
929intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
930{
931 struct drm_device *dev = intel_output->base.dev;
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
934
935 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
936 POSTING_READ(dp_priv->output_reg);
937}
938
939static void
940intel_dp_restore(struct drm_connector *connector)
941{
942 struct intel_output *intel_output = to_intel_output(connector);
943 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
944
945 if (dp_priv->save_DP & DP_PORT_EN)
946 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
947 else
948 intel_dp_link_down(intel_output, dp_priv->save_DP);
949}
950
a4fc5ed6
KP		 951/*
952 * According to DP spec
953 * 5.1.2:
954 * 1. Read DPCD
955 * 2. Configure link according to Receiver Capabilities
956 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
957 * 4. Check link status on receipt of hot-plug interrupt
958 */
959
960static void
961intel_dp_check_link_status(struct intel_output *intel_output)
962{
963 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
964 uint8_t link_status[DP_LINK_STATUS_SIZE];
965
966 if (!intel_output->enc.crtc)
967 return;
968
969 if (!intel_dp_get_link_status(intel_output, link_status)) {
970 intel_dp_link_down(intel_output, dp_priv->DP);
971 return;
972 }
973
974 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
975 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
976}
a4fc5ed6
KP		 977
978/**
979 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
980 *
981 * \return true if DP port is connected.
982 * \return false if DP port is disconnected.
983 */
984static enum drm_connector_status
985intel_dp_detect(struct drm_connector *connector)
986{
987 struct intel_output *intel_output = to_intel_output(connector);
988 struct drm_device *dev = intel_output->base.dev;
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
991 uint32_t temp, bit;
992 enum drm_connector_status status;
993
994 dp_priv->has_audio = false;
995
996 temp = I915_READ(PORT_HOTPLUG_EN);
997
998 I915_WRITE(PORT_HOTPLUG_EN,
999 temp |
1000 DPB_HOTPLUG_INT_EN |
1001 DPC_HOTPLUG_INT_EN |
1002 DPD_HOTPLUG_INT_EN);
1003
1004 POSTING_READ(PORT_HOTPLUG_EN);
1005
1006 switch (dp_priv->output_reg) {
1007 case DP_B:
1008 bit = DPB_HOTPLUG_INT_STATUS;
1009 break;
1010 case DP_C:
1011 bit = DPC_HOTPLUG_INT_STATUS;
1012 break;
1013 case DP_D:
1014 bit = DPD_HOTPLUG_INT_STATUS;
1015 break;
1016 default:
1017 return connector_status_unknown;
1018 }
1019
1020 temp = I915_READ(PORT_HOTPLUG_STAT);
1021
1022 if ((temp & bit) == 0)
1023 return connector_status_disconnected;
1024
1025 status = connector_status_disconnected;
1026 if (intel_dp_aux_native_read(intel_output,
1027 0x000, dp_priv->dpcd,
1028 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1029 {
1030 if (dp_priv->dpcd[0] != 0)
1031 status = connector_status_connected;
1032 }
1033 return status;
1034}
1035
1036static int intel_dp_get_modes(struct drm_connector *connector)
1037{
1038 struct intel_output *intel_output = to_intel_output(connector);
1039
1040 /* We should parse the EDID data and find out if it has an audio sink
1041 */
1042
1043 return intel_ddc_get_modes(intel_output);
1044}
1045
1046static void
1047intel_dp_destroy (struct drm_connector *connector)
1048{
1049 struct intel_output *intel_output = to_intel_output(connector);
1050
1051 if (intel_output->i2c_bus)
1052 intel_i2c_destroy(intel_output->i2c_bus);
1053 drm_sysfs_connector_remove(connector);
1054 drm_connector_cleanup(connector);
1055 kfree(intel_output);
1056}
1057
1058static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1059 .dpms = intel_dp_dpms,
1060 .mode_fixup = intel_dp_mode_fixup,
1061 .prepare = intel_encoder_prepare,
1062 .mode_set = intel_dp_mode_set,
1063 .commit = intel_encoder_commit,
1064};
1065
1066static const struct drm_connector_funcs intel_dp_connector_funcs = {
1067 .dpms = drm_helper_connector_dpms,
1068 .save = intel_dp_save,
1069 .restore = intel_dp_restore,
1070 .detect = intel_dp_detect,
1071 .fill_modes = drm_helper_probe_single_connector_modes,
1072 .destroy = intel_dp_destroy,
1073};
1074
1075static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1076 .get_modes = intel_dp_get_modes,
1077 .mode_valid = intel_dp_mode_valid,
1078 .best_encoder = intel_best_encoder,
1079};
1080
1081static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1082{
1083 drm_encoder_cleanup(encoder);
1084}
1085
1086static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1087 .destroy = intel_dp_enc_destroy,
1088};
1089
c8110e52
KP		 1090void
1091intel_dp_hot_plug(struct intel_output *intel_output)
1092{
1093 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1094
1095 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1096 intel_dp_check_link_status(intel_output);
1097}
1098
a4fc5ed6
KP		 1099void
1100intel_dp_init(struct drm_device *dev, int output_reg)
1101{
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 struct drm_connector *connector;
1104 struct intel_output *intel_output;
1105 struct intel_dp_priv *dp_priv;
1106
1107 intel_output = kcalloc(sizeof(struct intel_output) +
1108 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1109 if (!intel_output)
1110 return;
1111
1112 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1113
1114 connector = &intel_output->base;
1115 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1116 DRM_MODE_CONNECTOR_DisplayPort);
1117 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1118
1119 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1120
1121 connector->interlace_allowed = true;
1122 connector->doublescan_allowed = 0;
1123
1124 dp_priv->intel_output = intel_output;
1125 dp_priv->output_reg = output_reg;
1126 dp_priv->has_audio = false;
c8110e52 1127 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6
KP		 1128 intel_output->dev_priv = dp_priv;
1129
1130 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1131 DRM_MODE_ENCODER_TMDS);
1132 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1133
1134 drm_mode_connector_attach_encoder(&intel_output->base,
1135 &intel_output->enc);
1136 drm_sysfs_connector_add(connector);
1137
1138 /* Set up the DDC bus. */
1139 intel_dp_i2c_init(intel_output,
1140 (output_reg == DP_B) ? "DPDDC-B" :
1141 (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
1142 intel_output->ddc_bus = &dp_priv->adapter;
c8110e52 1143 intel_output->hot_plug = intel_dp_hot_plug;
a4fc5ed6
KP		 1144
1145 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1146 * 0xd. Failure to do so will result in spurious interrupts being
1147 * generated on the port when a cable is not attached.
1148 */
1149 if (IS_G4X(dev) && !IS_GM45(dev)) {
1150 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1151 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1152 }
1153}
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