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drm/i915: fix SDEIMR assertion when disabling LCPLL
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 56{
68b4d824
ID		 57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 60}
61
df0e9248
CW		 62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
fa90ecef 64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 65}
66
ea5b213a 67static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 68
a4fc5ed6 69static int
ea5b213a 70intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 71{
7183dc29 72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
d4eead50
ID		 78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
80 break;
a4fc5ed6 81 default:
d4eead50
ID		 82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
83 max_link_bw);
a4fc5ed6
KP		 84 max_link_bw = DP_LINK_BW_1_62;
85 break;
86 }
87 return max_link_bw;
88}
89
cd9dde44
AJ		 90/*
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
93 *
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
95 *
96 * 270000 * 1 * 8 / 10 == 216000
97 *
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
102 *
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
105 */
106
a4fc5ed6 107static int
c898261c 108intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 109{
cd9dde44 110 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 111}
112
fe27d53e
DA		 113static int
114intel_dp_max_data_rate(int max_link_clock, int max_lanes)
115{
116 return (max_link_clock * max_lanes * 8) / 10;
117}
118
a4fc5ed6
KP		 119static int
120intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
122{
df0e9248 123 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 128
dd06f90e
JN		 129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 131 return MODE_PANEL;
132
dd06f90e 133 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 134 return MODE_PANEL;
03afc4a2
DV		 135
136 target_clock = fixed_mode->clock;
7de56f43
ZY		 137 }
138
36008365
DV		 139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
141
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
144
145 if (mode_rate > max_rate)
c4867936 146 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 147
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
150
0af78a2b
DV		 151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
153
a4fc5ed6
KP		 154 return MODE_OK;
155}
156
157static uint32_t
158pack_aux(uint8_t *src, int src_bytes)
159{
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168}
169
170static void
171unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172{
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178}
179
fb0f8fbf
KP		 180/* hrawclock is 1/4 the FSB frequency */
181static int
182intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
9473c8f4
VP		 187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
fb0f8fbf
KP		 191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
ebf33b18
KP		 214static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
215{
30add22d 216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 217 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 218 u32 pp_stat_reg;
ebf33b18 219
453c5420
JB		 220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 222}
223
224static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
225{
30add22d 226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 227 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 228 u32 pp_ctrl_reg;
ebf33b18 229
453c5420
JB		 230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 232}
233
9b984dae
KP		 234static void
235intel_dp_check_edp(struct intel_dp *intel_dp)
236{
30add22d 237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 238 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 239 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 240
9b984dae
KP		 241 if (!is_edp(intel_dp))
242 return;
453c5420
JB		 243
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
246
ebf33b18 247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
9b984dae
KP		 252 }
253}
254
9ee32fea
DV		 255static uint32_t
256intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
257{
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 262 uint32_t status;
263 bool done;
264
ef04f00d 265#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 266 if (has_aux_irq)
b18ac466 267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 268 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 269 else
270 done = wait_for_atomic(C, 10) == 0;
271 if (!done)
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
273 has_aux_irq);
274#undef C
275
276 return status;
277}
278
bc86625a
CW		 279static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
280 int index)
a4fc5ed6 281{
174edf1f
PZ		 282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 284 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 285
a4fc5ed6 286 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 287 * and would like to run at 2MHz. So, take the
288 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 289 *
290 * Note that PCH attached eDP panels should use a 125MHz input
291 * clock divider.
a4fc5ed6 292 */
a62d0834 293 if (IS_VALLEYVIEW(dev)) {
bc86625a 294 return index ? 0 : 100;
a62d0834 295 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 296 if (index)
297 return 0;
affa9354 298 if (HAS_DDI(dev))
bc86625a 299 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 300 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 301 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 302 else
b84a1cf8 303 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 304 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
305 /* Workaround for non-ULT HSW */
bc86625a
CW		 306 switch (index) {
307 case 0: return 63;
308 case 1: return 72;
309 default: return 0;
310 }
2c55c336 311 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 312 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 313 } else {
bc86625a 314 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 315 }
b84a1cf8
RV		 316}
317
318static int
319intel_dp_aux_ch(struct intel_dp *intel_dp,
320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
322{
323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = intel_dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
327 uint32_t ch_data = ch_ctl + 4;
bc86625a 328 uint32_t aux_clock_divider;
b84a1cf8
RV		 329 int i, ret, recv_bytes;
330 uint32_t status;
bc86625a 331 int try, precharge, clock = 0;
b84a1cf8
RV		 332 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
333
334 /* dp aux is extremely sensitive to irq latency, hence request the
335 * lowest possible wakeup latency and so prevent the cpu from going into
336 * deep sleep states.
337 */
338 pm_qos_update_request(&dev_priv->pm_qos, 0);
339
340 intel_dp_check_edp(intel_dp);
5eb08b69 341
6b4e0a93
DV		 342 if (IS_GEN6(dev))
343 precharge = 3;
344 else
345 precharge = 5;
346
11bee43e
JB		 347 /* Try to wait for any previous AUX channel activity */
348 for (try = 0; try < 3; try++) {
ef04f00d 349 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 350 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
351 break;
352 msleep(1);
353 }
354
355 if (try == 3) {
356 WARN(1, "dp_aux_ch not started status 0x%08x\n",
357 I915_READ(ch_ctl));
9ee32fea
DV		 358 ret = -EBUSY;
359 goto out;
4f7f7b7e
CW		 360 }
361
bc86625a
CW		 362 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
363 /* Must try at least 3 times according to DP spec */
364 for (try = 0; try < 5; try++) {
365 /* Load the send data into the aux channel data registers */
366 for (i = 0; i < send_bytes; i += 4)
367 I915_WRITE(ch_data + i,
368 pack_aux(send + i, send_bytes - i));
369
370 /* Send the command and wait for it to complete */
371 I915_WRITE(ch_ctl,
372 DP_AUX_CH_CTL_SEND_BUSY |
373 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
374 DP_AUX_CH_CTL_TIME_OUT_400us |
375 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
376 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
377 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
378 DP_AUX_CH_CTL_DONE |
379 DP_AUX_CH_CTL_TIME_OUT_ERROR |
380 DP_AUX_CH_CTL_RECEIVE_ERROR);
381
382 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
383
384 /* Clear done status and any errors */
385 I915_WRITE(ch_ctl,
386 status |
387 DP_AUX_CH_CTL_DONE |
388 DP_AUX_CH_CTL_TIME_OUT_ERROR |
389 DP_AUX_CH_CTL_RECEIVE_ERROR);
390
391 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
392 DP_AUX_CH_CTL_RECEIVE_ERROR))
393 continue;
394 if (status & DP_AUX_CH_CTL_DONE)
395 break;
396 }
4f7f7b7e 397 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 398 break;
399 }
400
a4fc5ed6 401 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 402 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 403 ret = -EBUSY;
404 goto out;
a4fc5ed6
KP		 405 }
406
407 /* Check for timeout or receive error.
408 * Timeouts occur when the sink is not connected
409 */
a5b3da54 410 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 411 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 412 ret = -EIO;
413 goto out;
a5b3da54 414 }
1ae8c0a5
KP		 415
416 /* Timeouts occur when the device isn't connected, so they're
417 * "normal" -- don't fill the kernel log with these */
a5b3da54 418 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 419 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 420 ret = -ETIMEDOUT;
421 goto out;
a4fc5ed6
KP		 422 }
423
424 /* Unload any bytes sent back from the other side */
425 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
426 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 427 if (recv_bytes > recv_size)
428 recv_bytes = recv_size;
0206e353 429
4f7f7b7e
CW		 430 for (i = 0; i < recv_bytes; i += 4)
431 unpack_aux(I915_READ(ch_data + i),
432 recv + i, recv_bytes - i);
a4fc5ed6 433
9ee32fea
DV		 434 ret = recv_bytes;
435out:
436 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
437
438 return ret;
a4fc5ed6
KP		 439}
440
441/* Write data to the aux channel in native mode */
442static int
ea5b213a 443intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 444 uint16_t address, uint8_t *send, int send_bytes)
445{
446 int ret;
447 uint8_t msg[20];
448 int msg_bytes;
449 uint8_t ack;
450
9b984dae 451 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 452 if (send_bytes > 16)
453 return -1;
454 msg[0] = AUX_NATIVE_WRITE << 4;
455 msg[1] = address >> 8;
eebc863e 456 msg[2] = address & 0xff;
a4fc5ed6
KP		 457 msg[3] = send_bytes - 1;
458 memcpy(&msg[4], send, send_bytes);
459 msg_bytes = send_bytes + 4;
460 for (;;) {
ea5b213a 461 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 462 if (ret < 0)
463 return ret;
464 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
465 break;
466 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
467 udelay(100);
468 else
a5b3da54 469 return -EIO;
a4fc5ed6
KP		 470 }
471 return send_bytes;
472}
473
474/* Write a single byte to the aux channel in native mode */
475static int
ea5b213a 476intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 477 uint16_t address, uint8_t byte)
478{
ea5b213a 479 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 480}
481
482/* read bytes from a native aux channel */
483static int
ea5b213a 484intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 485 uint16_t address, uint8_t *recv, int recv_bytes)
486{
487 uint8_t msg[4];
488 int msg_bytes;
489 uint8_t reply[20];
490 int reply_bytes;
491 uint8_t ack;
492 int ret;
493
9b984dae 494 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 495 msg[0] = AUX_NATIVE_READ << 4;
496 msg[1] = address >> 8;
497 msg[2] = address & 0xff;
498 msg[3] = recv_bytes - 1;
499
500 msg_bytes = 4;
501 reply_bytes = recv_bytes + 1;
502
503 for (;;) {
ea5b213a 504 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 505 reply, reply_bytes);
a5b3da54
KP		 506 if (ret == 0)
507 return -EPROTO;
508 if (ret < 0)
a4fc5ed6
KP		 509 return ret;
510 ack = reply[0];
511 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
512 memcpy(recv, reply + 1, ret - 1);
513 return ret - 1;
514 }
515 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
516 udelay(100);
517 else
a5b3da54 518 return -EIO;
a4fc5ed6
KP		 519 }
520}
521
522static int
ab2c0672
DA		 523intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
524 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 525{
ab2c0672 526 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 527 struct intel_dp *intel_dp = container_of(adapter,
528 struct intel_dp,
529 adapter);
ab2c0672
DA		 530 uint16_t address = algo_data->address;
531 uint8_t msg[5];
532 uint8_t reply[2];
8316f337 533 unsigned retry;
ab2c0672
DA		 534 int msg_bytes;
535 int reply_bytes;
536 int ret;
537
9b984dae 538 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 539 /* Set up the command byte */
540 if (mode & MODE_I2C_READ)
541 msg[0] = AUX_I2C_READ << 4;
542 else
543 msg[0] = AUX_I2C_WRITE << 4;
544
545 if (!(mode & MODE_I2C_STOP))
546 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 547
ab2c0672
DA		 548 msg[1] = address >> 8;
549 msg[2] = address;
550
551 switch (mode) {
552 case MODE_I2C_WRITE:
553 msg[3] = 0;
554 msg[4] = write_byte;
555 msg_bytes = 5;
556 reply_bytes = 1;
557 break;
558 case MODE_I2C_READ:
559 msg[3] = 0;
560 msg_bytes = 4;
561 reply_bytes = 2;
562 break;
563 default:
564 msg_bytes = 3;
565 reply_bytes = 1;
566 break;
567 }
568
8316f337
DF		 569 for (retry = 0; retry < 5; retry++) {
570 ret = intel_dp_aux_ch(intel_dp,
571 msg, msg_bytes,
572 reply, reply_bytes);
ab2c0672 573 if (ret < 0) {
3ff99164 574 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 575 return ret;
576 }
8316f337
DF		 577
578 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
579 case AUX_NATIVE_REPLY_ACK:
580 /* I2C-over-AUX Reply field is only valid
581 * when paired with AUX ACK.
582 */
583 break;
584 case AUX_NATIVE_REPLY_NACK:
585 DRM_DEBUG_KMS("aux_ch native nack\n");
586 return -EREMOTEIO;
587 case AUX_NATIVE_REPLY_DEFER:
588 udelay(100);
589 continue;
590 default:
591 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
592 reply[0]);
593 return -EREMOTEIO;
594 }
595
ab2c0672
DA		 596 switch (reply[0] & AUX_I2C_REPLY_MASK) {
597 case AUX_I2C_REPLY_ACK:
598 if (mode == MODE_I2C_READ) {
599 *read_byte = reply[1];
600 }
601 return reply_bytes - 1;
602 case AUX_I2C_REPLY_NACK:
8316f337 603 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 604 return -EREMOTEIO;
605 case AUX_I2C_REPLY_DEFER:
8316f337 606 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 607 udelay(100);
608 break;
609 default:
8316f337 610 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 611 return -EREMOTEIO;
612 }
613 }
8316f337
DF		 614
615 DRM_ERROR("too many retries, giving up\n");
616 return -EREMOTEIO;
a4fc5ed6
KP		 617}
618
619static int
ea5b213a 620intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 621 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 622{
0b5c541b
KP		 623 int ret;
624
d54e9d28 625 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 626 intel_dp->algo.running = false;
627 intel_dp->algo.address = 0;
628 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
629
0206e353 630 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 631 intel_dp->adapter.owner = THIS_MODULE;
632 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 633 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 634 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
635 intel_dp->adapter.algo_data = &intel_dp->algo;
636 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
637
0b5c541b
KP		 638 ironlake_edp_panel_vdd_on(intel_dp);
639 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 640 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 641 return ret;
a4fc5ed6
KP		 642}
643
c6bb3538
DV		 644static void
645intel_dp_set_clock(struct intel_encoder *encoder,
646 struct intel_crtc_config *pipe_config, int link_bw)
647{
648 struct drm_device *dev = encoder->base.dev;
649
650 if (IS_G4X(dev)) {
651 if (link_bw == DP_LINK_BW_1_62) {
652 pipe_config->dpll.p1 = 2;
653 pipe_config->dpll.p2 = 10;
654 pipe_config->dpll.n = 2;
655 pipe_config->dpll.m1 = 23;
656 pipe_config->dpll.m2 = 8;
657 } else {
658 pipe_config->dpll.p1 = 1;
659 pipe_config->dpll.p2 = 10;
660 pipe_config->dpll.n = 1;
661 pipe_config->dpll.m1 = 14;
662 pipe_config->dpll.m2 = 2;
663 }
664 pipe_config->clock_set = true;
665 } else if (IS_HASWELL(dev)) {
666 /* Haswell has special-purpose DP DDI clocks. */
667 } else if (HAS_PCH_SPLIT(dev)) {
668 if (link_bw == DP_LINK_BW_1_62) {
669 pipe_config->dpll.n = 1;
670 pipe_config->dpll.p1 = 2;
671 pipe_config->dpll.p2 = 10;
672 pipe_config->dpll.m1 = 12;
673 pipe_config->dpll.m2 = 9;
674 } else {
675 pipe_config->dpll.n = 2;
676 pipe_config->dpll.p1 = 1;
677 pipe_config->dpll.p2 = 10;
678 pipe_config->dpll.m1 = 14;
679 pipe_config->dpll.m2 = 8;
680 }
681 pipe_config->clock_set = true;
682 } else if (IS_VALLEYVIEW(dev)) {
683 /* FIXME: Need to figure out optimized DP clocks for vlv. */
684 }
685}
686
00c09d70 687bool
5bfe2ac0
DV		 688intel_dp_compute_config(struct intel_encoder *encoder,
689 struct intel_crtc_config *pipe_config)
a4fc5ed6 690{
5bfe2ac0 691 struct drm_device *dev = encoder->base.dev;
36008365 692 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 693 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 694 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 695 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 696 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 697 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 698 int lane_count, clock;
397fe157 699 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 700 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 701 int bpp, mode_rate;
a4fc5ed6 702 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 703 int link_avail, link_clock;
a4fc5ed6 704
bc7d38a4 705 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 706 pipe_config->has_pch_encoder = true;
707
03afc4a2 708 pipe_config->has_dp_encoder = true;
a4fc5ed6 709
dd06f90e
JN		 710 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
711 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
712 adjusted_mode);
2dd24552
JB		 713 if (!HAS_PCH_SPLIT(dev))
714 intel_gmch_panel_fitting(intel_crtc, pipe_config,
715 intel_connector->panel.fitting_mode);
716 else
b074cec8
JB		 717 intel_pch_panel_fitting(intel_crtc, pipe_config,
718 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 719 }
720
cb1793ce 721 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 722 return false;
723
083f9560
DV		 724 DRM_DEBUG_KMS("DP link computation with max lane count %i "
725 "max bw %02x pixel clock %iKHz\n",
71244653 726 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 727
36008365
DV		 728 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
729 * bpc in between. */
3e7ca985 730 bpp = pipe_config->pipe_bpp;
7984211e
ID		 731 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
732 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
733 dev_priv->vbt.edp_bpp);
e1b73cba 734 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 735 }
657445fe 736
36008365 737 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 738 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 739
740 for (clock = 0; clock <= max_clock; clock++) {
741 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
742 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
743 link_avail = intel_dp_max_data_rate(link_clock,
744 lane_count);
745
746 if (mode_rate <= link_avail) {
747 goto found;
748 }
749 }
750 }
751 }
c4867936 752
36008365 753 return false;
3685a8f3 754
36008365 755found:
55bc60db
VS		 756 if (intel_dp->color_range_auto) {
757 /*
758 * See:
759 * CEA-861-E - 5.1 Default Encoding Parameters
760 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
761 */
18316c8c 762 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 763 intel_dp->color_range = DP_COLOR_RANGE_16_235;
764 else
765 intel_dp->color_range = 0;
766 }
767
3685a8f3 768 if (intel_dp->color_range)
50f3b016 769 pipe_config->limited_color_range = true;
a4fc5ed6 770
36008365
DV		 771 intel_dp->link_bw = bws[clock];
772 intel_dp->lane_count = lane_count;
657445fe 773 pipe_config->pipe_bpp = bpp;
ff9a6750 774 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 775
36008365
DV		 776 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
777 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 778 pipe_config->port_clock, bpp);
36008365
DV		 779 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
780 mode_rate, link_avail);
a4fc5ed6 781
03afc4a2 782 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 783 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 784 &pipe_config->dp_m_n);
9d1a455b 785
c6bb3538
DV		 786 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
787
03afc4a2 788 return true;
a4fc5ed6
KP		 789}
790
247d89f6
PZ		 791void intel_dp_init_link_config(struct intel_dp *intel_dp)
792{
793 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
794 intel_dp->link_configuration[0] = intel_dp->link_bw;
795 intel_dp->link_configuration[1] = intel_dp->lane_count;
796 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
797 /*
798 * Check for DPCD version > 1.1 and enhanced framing support
799 */
800 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
801 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
802 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
803 }
804}
805
7c62a164 806static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 807{
7c62a164
DV		 808 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
809 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
810 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 dpa_ctl;
813
ff9a6750 814 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 815 dpa_ctl = I915_READ(DP_A);
816 dpa_ctl &= ~DP_PLL_FREQ_MASK;
817
ff9a6750 818 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 819 /* For a long time we've carried around a ILK-DevA w/a for the
820 * 160MHz clock. If we're really unlucky, it's still required.
821 */
822 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 823 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 824 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 825 } else {
826 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 827 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 828 }
1ce17038 829
ea9b6006
DV		 830 I915_WRITE(DP_A, dpa_ctl);
831
832 POSTING_READ(DP_A);
833 udelay(500);
834}
835
b934223d 836static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 837{
b934223d 838 struct drm_device *dev = encoder->base.dev;
417e822d 839 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 840 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 841 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 842 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
843 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 844
417e822d 845 /*
1a2eb460 846 * There are four kinds of DP registers:
417e822d
KP		 847 *
848 * IBX PCH
1a2eb460
KP		 849 * SNB CPU
850 * IVB CPU
417e822d
KP		 851 * CPT PCH
852 *
853 * IBX PCH and CPU are the same for almost everything,
854 * except that the CPU DP PLL is configured in this
855 * register
856 *
857 * CPT PCH is quite different, having many bits moved
858 * to the TRANS_DP_CTL register instead. That
859 * configuration happens (oddly) in ironlake_pch_enable
860 */
9c9e7927 861
417e822d
KP		 862 /* Preserve the BIOS-computed detected bit. This is
863 * supposed to be read-only.
864 */
865 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 866
417e822d 867 /* Handle DP bits in common between all three register formats */
417e822d 868 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 869 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 870
e0dac65e
WF		 871 if (intel_dp->has_audio) {
872 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 873 pipe_name(crtc->pipe));
ea5b213a 874 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 875 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 876 }
247d89f6
PZ		 877
878 intel_dp_init_link_config(intel_dp);
a4fc5ed6 879
417e822d 880 /* Split out the IBX/CPU vs CPT settings */
32f9d658 881
bc7d38a4 882 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 883 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
884 intel_dp->DP |= DP_SYNC_HS_HIGH;
885 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
886 intel_dp->DP |= DP_SYNC_VS_HIGH;
887 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
888
889 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
890 intel_dp->DP |= DP_ENHANCED_FRAMING;
891
7c62a164 892 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 893 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 894 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 895 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 896
897 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
898 intel_dp->DP |= DP_SYNC_HS_HIGH;
899 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
900 intel_dp->DP |= DP_SYNC_VS_HIGH;
901 intel_dp->DP |= DP_LINK_TRAIN_OFF;
902
903 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
904 intel_dp->DP |= DP_ENHANCED_FRAMING;
905
7c62a164 906 if (crtc->pipe == 1)
417e822d 907 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 908 } else {
909 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 910 }
ea9b6006 911
bc7d38a4 912 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 913 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 914}
915
99ea7127
KP		 916#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
917#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
918
919#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
920#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
921
922#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
923#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
924
925static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
926 u32 mask,
927 u32 value)
bd943159 928{
30add22d 929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 930 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 931 u32 pp_stat_reg, pp_ctrl_reg;
932
933 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
934 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 935
99ea7127 936 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 937 mask, value,
938 I915_READ(pp_stat_reg),
939 I915_READ(pp_ctrl_reg));
32ce697c 940
453c5420 941 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 942 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 943 I915_READ(pp_stat_reg),
944 I915_READ(pp_ctrl_reg));
32ce697c 945 }
99ea7127 946}
32ce697c 947
99ea7127
KP		 948static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
949{
950 DRM_DEBUG_KMS("Wait for panel power on\n");
951 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 952}
953
99ea7127
KP		 954static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
955{
956 DRM_DEBUG_KMS("Wait for panel power off time\n");
957 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
958}
959
960static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
961{
962 DRM_DEBUG_KMS("Wait for panel power cycle\n");
963 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
964}
965
966
832dd3c1
KP		 967/* Read the current pp_control value, unlocking the register if it
968 * is locked
969 */
970
453c5420 971static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 972{
453c5420
JB		 973 struct drm_device *dev = intel_dp_to_dev(intel_dp);
974 struct drm_i915_private *dev_priv = dev->dev_private;
975 u32 control;
976 u32 pp_ctrl_reg;
977
978 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
979 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 980
981 control &= ~PANEL_UNLOCK_MASK;
982 control |= PANEL_UNLOCK_REGS;
983 return control;
bd943159
KP		 984}
985
82a4d9c0 986void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 987{
30add22d 988 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 989 struct drm_i915_private *dev_priv = dev->dev_private;
990 u32 pp;
453c5420 991 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 992
97af61f5
KP		 993 if (!is_edp(intel_dp))
994 return;
f01eca2e 995 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 996
bd943159
KP		 997 WARN(intel_dp->want_panel_vdd,
998 "eDP VDD already requested on\n");
999
1000 intel_dp->want_panel_vdd = true;
99ea7127 1001
bd943159
KP		 1002 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1003 DRM_DEBUG_KMS("eDP VDD already on\n");
1004 return;
1005 }
1006
99ea7127
KP		 1007 if (!ironlake_edp_have_panel_power(intel_dp))
1008 ironlake_wait_panel_power_cycle(intel_dp);
1009
453c5420 1010 pp = ironlake_get_pp_control(intel_dp);
5d613501 1011 pp |= EDP_FORCE_VDD;
ebf33b18 1012
453c5420
JB		 1013 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1014 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1015
1016 I915_WRITE(pp_ctrl_reg, pp);
1017 POSTING_READ(pp_ctrl_reg);
1018 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1019 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1020 /*
1021 * If the panel wasn't on, delay before accessing aux channel
1022 */
1023 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1024 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1025 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1026 }
5d613501
JB		 1027}
1028
bd943159 1029static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1030{
30add22d 1031 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 u32 pp;
453c5420 1034 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1035
a0e99e68
DV		 1036 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1037
bd943159 1038 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1039 pp = ironlake_get_pp_control(intel_dp);
bd943159 1040 pp &= ~EDP_FORCE_VDD;
bd943159 1041
453c5420
JB		 1042 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1043 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1044
1045 I915_WRITE(pp_ctrl_reg, pp);
1046 POSTING_READ(pp_ctrl_reg);
99ea7127 1047
453c5420
JB		 1048 /* Make sure sequencer is idle before allowing subsequent activity */
1049 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1050 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1051 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1052 }
1053}
5d613501 1054
bd943159
KP		 1055static void ironlake_panel_vdd_work(struct work_struct *__work)
1056{
1057 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1058 struct intel_dp, panel_vdd_work);
30add22d 1059 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1060
627f7675 1061 mutex_lock(&dev->mode_config.mutex);
bd943159 1062 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1063 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1064}
1065
82a4d9c0 1066void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1067{
97af61f5
KP		 1068 if (!is_edp(intel_dp))
1069 return;
5d613501 1070
bd943159
KP		 1071 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1072 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1073
bd943159
KP		 1074 intel_dp->want_panel_vdd = false;
1075
1076 if (sync) {
1077 ironlake_panel_vdd_off_sync(intel_dp);
1078 } else {
1079 /*
1080 * Queue the timer to fire a long
1081 * time from now (relative to the power down delay)
1082 * to keep the panel power up across a sequence of operations
1083 */
1084 schedule_delayed_work(&intel_dp->panel_vdd_work,
1085 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1086 }
5d613501
JB		 1087}
1088
82a4d9c0 1089void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1090{
30add22d 1091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1092 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1093 u32 pp;
453c5420 1094 u32 pp_ctrl_reg;
9934c132 1095
97af61f5 1096 if (!is_edp(intel_dp))
bd943159 1097 return;
99ea7127
KP		 1098
1099 DRM_DEBUG_KMS("Turn eDP power on\n");
1100
1101 if (ironlake_edp_have_panel_power(intel_dp)) {
1102 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1103 return;
99ea7127 1104 }
9934c132 1105
99ea7127 1106 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1107
453c5420 1108 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1109 if (IS_GEN5(dev)) {
1110 /* ILK workaround: disable reset around power sequence */
1111 pp &= ~PANEL_POWER_RESET;
1112 I915_WRITE(PCH_PP_CONTROL, pp);
1113 POSTING_READ(PCH_PP_CONTROL);
1114 }
37c6c9b0 1115
1c0ae80a 1116 pp |= POWER_TARGET_ON;
99ea7127
KP		 1117 if (!IS_GEN5(dev))
1118 pp |= PANEL_POWER_RESET;
1119
453c5420
JB		 1120 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1121
1122 I915_WRITE(pp_ctrl_reg, pp);
1123 POSTING_READ(pp_ctrl_reg);
9934c132 1124
99ea7127 1125 ironlake_wait_panel_on(intel_dp);
9934c132 1126
05ce1a49
KP		 1127 if (IS_GEN5(dev)) {
1128 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1129 I915_WRITE(PCH_PP_CONTROL, pp);
1130 POSTING_READ(PCH_PP_CONTROL);
1131 }
9934c132
JB		 1132}
1133
82a4d9c0 1134void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1135{
30add22d 1136 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1137 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1138 u32 pp;
453c5420 1139 u32 pp_ctrl_reg;
9934c132 1140
97af61f5
KP		 1141 if (!is_edp(intel_dp))
1142 return;
37c6c9b0 1143
99ea7127 1144 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1145
6cb49835 1146 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1147
453c5420 1148 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1149 /* We need to switch off panel power _and_ force vdd, for otherwise some
1150 * panels get very unhappy and cease to work. */
1151 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1152
1153 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1154
1155 I915_WRITE(pp_ctrl_reg, pp);
1156 POSTING_READ(pp_ctrl_reg);
9934c132 1157
35a38556
DV		 1158 intel_dp->want_panel_vdd = false;
1159
99ea7127 1160 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1161}
1162
d6c50ff8 1163void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1164{
da63a9f2
PZ		 1165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1166 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1167 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1168 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1169 u32 pp;
453c5420 1170 u32 pp_ctrl_reg;
32f9d658 1171
f01eca2e
KP		 1172 if (!is_edp(intel_dp))
1173 return;
1174
28c97730 1175 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1176 /*
1177 * If we enable the backlight right away following a panel power
1178 * on, we may see slight flicker as the panel syncs with the eDP
1179 * link. So delay a bit to make sure the image is solid before
1180 * allowing it to appear.
1181 */
f01eca2e 1182 msleep(intel_dp->backlight_on_delay);
453c5420 1183 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1184 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1185
1186 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1187
1188 I915_WRITE(pp_ctrl_reg, pp);
1189 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1190
1191 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1192}
1193
d6c50ff8 1194void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1195{
30add22d 1196 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u32 pp;
453c5420 1199 u32 pp_ctrl_reg;
32f9d658 1200
f01eca2e
KP		 1201 if (!is_edp(intel_dp))
1202 return;
1203
035aa3de
DV		 1204 intel_panel_disable_backlight(dev);
1205
28c97730 1206 DRM_DEBUG_KMS("\n");
453c5420 1207 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1208 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1209
1210 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1211
1212 I915_WRITE(pp_ctrl_reg, pp);
1213 POSTING_READ(pp_ctrl_reg);
f01eca2e 1214 msleep(intel_dp->backlight_off_delay);
32f9d658 1215}
a4fc5ed6 1216
2bd2ad64 1217static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1218{
da63a9f2
PZ		 1219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1220 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1221 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 u32 dpa_ctl;
1224
2bd2ad64
DV		 1225 assert_pipe_disabled(dev_priv,
1226 to_intel_crtc(crtc)->pipe);
1227
d240f20f
JB		 1228 DRM_DEBUG_KMS("\n");
1229 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1230 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1231 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1232
1233 /* We don't adjust intel_dp->DP while tearing down the link, to
1234 * facilitate link retraining (e.g. after hotplug). Hence clear all
1235 * enable bits here to ensure that we don't enable too much. */
1236 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1237 intel_dp->DP |= DP_PLL_ENABLE;
1238 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1239 POSTING_READ(DP_A);
1240 udelay(200);
d240f20f
JB		 1241}
1242
2bd2ad64 1243static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1244{
da63a9f2
PZ		 1245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1246 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1247 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 u32 dpa_ctl;
1250
2bd2ad64
DV		 1251 assert_pipe_disabled(dev_priv,
1252 to_intel_crtc(crtc)->pipe);
1253
d240f20f 1254 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1255 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1256 "dp pll off, should be on\n");
1257 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1258
1259 /* We can't rely on the value tracked for the DP register in
1260 * intel_dp->DP because link_down must not change that (otherwise link
1261 * re-training will fail. */
298b0b39 1262 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1263 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1264 POSTING_READ(DP_A);
d240f20f
JB		 1265 udelay(200);
1266}
1267
c7ad3810 1268/* If the sink supports it, try to set the power state appropriately */
c19b0669 1269void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1270{
1271 int ret, i;
1272
1273 /* Should have a valid DPCD by this point */
1274 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1275 return;
1276
1277 if (mode != DRM_MODE_DPMS_ON) {
1278 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1279 DP_SET_POWER_D3);
1280 if (ret != 1)
1281 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1282 } else {
1283 /*
1284 * When turning on, we need to retry for 1ms to give the sink
1285 * time to wake up.
1286 */
1287 for (i = 0; i < 3; i++) {
1288 ret = intel_dp_aux_native_write_1(intel_dp,
1289 DP_SET_POWER,
1290 DP_SET_POWER_D0);
1291 if (ret == 1)
1292 break;
1293 msleep(1);
1294 }
1295 }
1296}
1297
19d8fe15
DV		 1298static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1299 enum pipe *pipe)
d240f20f 1300{
19d8fe15 1301 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1302 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1303 struct drm_device *dev = encoder->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 u32 tmp = I915_READ(intel_dp->output_reg);
1306
1307 if (!(tmp & DP_PORT_EN))
1308 return false;
1309
bc7d38a4 1310 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1311 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1312 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1313 *pipe = PORT_TO_PIPE(tmp);
1314 } else {
1315 u32 trans_sel;
1316 u32 trans_dp;
1317 int i;
1318
1319 switch (intel_dp->output_reg) {
1320 case PCH_DP_B:
1321 trans_sel = TRANS_DP_PORT_SEL_B;
1322 break;
1323 case PCH_DP_C:
1324 trans_sel = TRANS_DP_PORT_SEL_C;
1325 break;
1326 case PCH_DP_D:
1327 trans_sel = TRANS_DP_PORT_SEL_D;
1328 break;
1329 default:
1330 return true;
1331 }
1332
1333 for_each_pipe(i) {
1334 trans_dp = I915_READ(TRANS_DP_CTL(i));
1335 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1336 *pipe = i;
1337 return true;
1338 }
1339 }
19d8fe15 1340
4a0833ec
DV		 1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342 intel_dp->output_reg);
1343 }
d240f20f 1344
19d8fe15
DV		 1345 return true;
1346}
d240f20f 1347
045ac3b5
JB		 1348static void intel_dp_get_config(struct intel_encoder *encoder,
1349 struct intel_crtc_config *pipe_config)
1350{
1351 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1352 u32 tmp, flags = 0;
63000ef6
XZ		 1353 struct drm_device *dev = encoder->base.dev;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 enum port port = dp_to_dig_port(intel_dp)->port;
1356 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 1357
63000ef6
XZ		 1358 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1359 tmp = I915_READ(intel_dp->output_reg);
1360 if (tmp & DP_SYNC_HS_HIGH)
1361 flags |= DRM_MODE_FLAG_PHSYNC;
1362 else
1363 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1364
63000ef6
XZ		 1365 if (tmp & DP_SYNC_VS_HIGH)
1366 flags |= DRM_MODE_FLAG_PVSYNC;
1367 else
1368 flags |= DRM_MODE_FLAG_NVSYNC;
1369 } else {
1370 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1371 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1372 flags |= DRM_MODE_FLAG_PHSYNC;
1373 else
1374 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1375
63000ef6
XZ		 1376 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1377 flags |= DRM_MODE_FLAG_PVSYNC;
1378 else
1379 flags |= DRM_MODE_FLAG_NVSYNC;
1380 }
045ac3b5
JB		 1381
1382 pipe_config->adjusted_mode.flags |= flags;
f1f644dc
JB		 1383
1384 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1385 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1386 pipe_config->port_clock = 162000;
1387 else
1388 pipe_config->port_clock = 270000;
1389 }
045ac3b5
JB		 1390}
1391
2293bb5c
SK		 1392static bool is_edp_psr(struct intel_dp *intel_dp)
1393{
1394 return is_edp(intel_dp) &&
1395 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1396}
1397
2b28bb1b
RV		 1398static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1399{
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401
1402 if (!IS_HASWELL(dev))
1403 return false;
1404
1405 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1406}
1407
1408static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1409 struct edp_vsc_psr *vsc_psr)
1410{
1411 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1412 struct drm_device *dev = dig_port->base.base.dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1415 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1416 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1417 uint32_t *data = (uint32_t *) vsc_psr;
1418 unsigned int i;
1419
1420 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1421 the video DIP being updated before program video DIP data buffer
1422 registers for DIP being updated. */
1423 I915_WRITE(ctl_reg, 0);
1424 POSTING_READ(ctl_reg);
1425
1426 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1427 if (i < sizeof(struct edp_vsc_psr))
1428 I915_WRITE(data_reg + i, *data++);
1429 else
1430 I915_WRITE(data_reg + i, 0);
1431 }
1432
1433 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1434 POSTING_READ(ctl_reg);
1435}
1436
1437static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1438{
1439 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 struct edp_vsc_psr psr_vsc;
1442
1443 if (intel_dp->psr_setup_done)
1444 return;
1445
1446 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1447 memset(&psr_vsc, 0, sizeof(psr_vsc));
1448 psr_vsc.sdp_header.HB0 = 0;
1449 psr_vsc.sdp_header.HB1 = 0x7;
1450 psr_vsc.sdp_header.HB2 = 0x2;
1451 psr_vsc.sdp_header.HB3 = 0x8;
1452 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1453
1454 /* Avoid continuous PSR exit by masking memup and hpd */
1455 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1456 EDP_PSR_DEBUG_MASK_HPD);
1457
1458 intel_dp->psr_setup_done = true;
1459}
1460
1461static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1462{
1463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1464 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1465 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1466 int precharge = 0x3;
1467 int msg_size = 5; /* Header(4) + Message(1) */
1468
1469 /* Enable PSR in sink */
1470 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1471 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1472 DP_PSR_ENABLE &
1473 ~DP_PSR_MAIN_LINK_ACTIVE);
1474 else
1475 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1476 DP_PSR_ENABLE |
1477 DP_PSR_MAIN_LINK_ACTIVE);
1478
1479 /* Setup AUX registers */
1480 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1481 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1482 I915_WRITE(EDP_PSR_AUX_CTL,
1483 DP_AUX_CH_CTL_TIME_OUT_400us |
1484 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1485 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1486 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1487}
1488
1489static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1490{
1491 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 uint32_t max_sleep_time = 0x1f;
1494 uint32_t idle_frames = 1;
1495 uint32_t val = 0x0;
1496
1497 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1498 val |= EDP_PSR_LINK_STANDBY;
1499 val |= EDP_PSR_TP2_TP3_TIME_0us;
1500 val |= EDP_PSR_TP1_TIME_0us;
1501 val |= EDP_PSR_SKIP_AUX_EXIT;
1502 } else
1503 val |= EDP_PSR_LINK_DISABLE;
1504
1505 I915_WRITE(EDP_PSR_CTL, val |
1506 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1507 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1508 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1509 EDP_PSR_ENABLE);
1510}
1511
3f51e471
RV		 1512static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1513{
1514 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1515 struct drm_device *dev = dig_port->base.base.dev;
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 struct drm_crtc *crtc = dig_port->base.base.crtc;
1518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1520 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1521
1522 if (!IS_HASWELL(dev)) {
1523 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1524 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1525 return false;
1526 }
1527
1528 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1529 (dig_port->port != PORT_A)) {
1530 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1531 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1532 return false;
1533 }
1534
1535 if (!is_edp_psr(intel_dp)) {
1536 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1537 dev_priv->no_psr_reason = PSR_NO_SINK;
1538 return false;
1539 }
1540
105b7c11
RV		 1541 if (!i915_enable_psr) {
1542 DRM_DEBUG_KMS("PSR disable by flag\n");
1543 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1544 return false;
1545 }
1546
cd234b0b
CW		 1547 crtc = dig_port->base.base.crtc;
1548 if (crtc == NULL) {
1549 DRM_DEBUG_KMS("crtc not active for PSR\n");
1550 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1551 return false;
1552 }
1553
1554 intel_crtc = to_intel_crtc(crtc);
3f51e471
RV		 1555 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1556 DRM_DEBUG_KMS("crtc not active for PSR\n");
1557 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1558 return false;
1559 }
1560
cd234b0b 1561 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1562 if (obj->tiling_mode != I915_TILING_X ||
1563 obj->fence_reg == I915_FENCE_REG_NONE) {
1564 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1565 dev_priv->no_psr_reason = PSR_NOT_TILED;
1566 return false;
1567 }
1568
1569 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1570 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1571 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1572 return false;
1573 }
1574
1575 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1576 S3D_ENABLE) {
1577 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1578 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1579 return false;
1580 }
1581
1582 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1583 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1584 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1585 return false;
1586 }
1587
1588 return true;
1589}
1590
3d739d92 1591static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1592{
1593 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1594
3f51e471
RV		 1595 if (!intel_edp_psr_match_conditions(intel_dp) ||
1596 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1597 return;
1598
1599 /* Setup PSR once */
1600 intel_edp_psr_setup(intel_dp);
1601
1602 /* Enable PSR on the panel */
1603 intel_edp_psr_enable_sink(intel_dp);
1604
1605 /* Enable PSR on the host */
1606 intel_edp_psr_enable_source(intel_dp);
1607}
1608
3d739d92
RV		 1609void intel_edp_psr_enable(struct intel_dp *intel_dp)
1610{
1611 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1612
1613 if (intel_edp_psr_match_conditions(intel_dp) &&
1614 !intel_edp_is_psr_enabled(dev))
1615 intel_edp_psr_do_enable(intel_dp);
1616}
1617
2b28bb1b
RV		 1618void intel_edp_psr_disable(struct intel_dp *intel_dp)
1619{
1620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622
1623 if (!intel_edp_is_psr_enabled(dev))
1624 return;
1625
1626 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1627
1628 /* Wait till PSR is idle */
1629 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1630 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1631 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1632}
1633
3d739d92
RV		 1634void intel_edp_psr_update(struct drm_device *dev)
1635{
1636 struct intel_encoder *encoder;
1637 struct intel_dp *intel_dp = NULL;
1638
1639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1640 if (encoder->type == INTEL_OUTPUT_EDP) {
1641 intel_dp = enc_to_intel_dp(&encoder->base);
1642
1643 if (!is_edp_psr(intel_dp))
1644 return;
1645
1646 if (!intel_edp_psr_match_conditions(intel_dp))
1647 intel_edp_psr_disable(intel_dp);
1648 else
1649 if (!intel_edp_is_psr_enabled(dev))
1650 intel_edp_psr_do_enable(intel_dp);
1651 }
1652}
1653
e8cb4558 1654static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1655{
e8cb4558 1656 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1657 enum port port = dp_to_dig_port(intel_dp)->port;
1658 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1659
1660 /* Make sure the panel is off before trying to change the mode. But also
1661 * ensure that we have vdd while we switch off the panel. */
1662 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1663 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1664 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1665 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1666
1667 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1668 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1669 intel_dp_link_down(intel_dp);
d240f20f
JB		 1670}
1671
2bd2ad64 1672static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1673{
2bd2ad64 1674 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1675 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1676 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1677
982a3866 1678 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1679 intel_dp_link_down(intel_dp);
b2634017
JB		 1680 if (!IS_VALLEYVIEW(dev))
1681 ironlake_edp_pll_off(intel_dp);
3739850b 1682 }
2bd2ad64
DV		 1683}
1684
e8cb4558 1685static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1686{
e8cb4558
DV		 1687 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1688 struct drm_device *dev = encoder->base.dev;
1689 struct drm_i915_private *dev_priv = dev->dev_private;
1690 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1691
0c33d8d7
DV		 1692 if (WARN_ON(dp_reg & DP_PORT_EN))
1693 return;
5d613501 1694
97af61f5 1695 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1696 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1697 intel_dp_start_link_train(intel_dp);
97af61f5 1698 ironlake_edp_panel_on(intel_dp);
bd943159 1699 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1700 intel_dp_complete_link_train(intel_dp);
3ab9c637 1701 intel_dp_stop_link_train(intel_dp);
f01eca2e 1702 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1703}
89b667f8 1704
ab1f90f9
JN		 1705static void vlv_enable_dp(struct intel_encoder *encoder)
1706{
d240f20f
JB		 1707}
1708
2bd2ad64 1709static void intel_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1710{
1711 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1712 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1713
1714 if (dport->port == PORT_A)
1715 ironlake_edp_pll_on(intel_dp);
1716}
1717
1718static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1719{
2bd2ad64 1720 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1721 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1722 struct drm_device *dev = encoder->base.dev;
89b667f8 1723 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1724 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1725 int port = vlv_dport_to_channel(dport);
1726 int pipe = intel_crtc->pipe;
1727 u32 val;
a4fc5ed6 1728
ab1f90f9 1729 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1730
ab1f90f9
JN		 1731 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1732 val = 0;
1733 if (pipe)
1734 val |= (1<<21);
1735 else
1736 val &= ~(1<<21);
1737 val |= 0x001000c4;
1738 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1739 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1740 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1741
ab1f90f9
JN		 1742 mutex_unlock(&dev_priv->dpio_lock);
1743
1744 intel_enable_dp(encoder);
1745
1746 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1747}
1748
1749static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1750{
1751 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1752 struct drm_device *dev = encoder->base.dev;
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 int port = vlv_dport_to_channel(dport);
1755
1756 if (!IS_VALLEYVIEW(dev))
1757 return;
1758
89b667f8 1759 /* Program Tx lane resets to default */
0980a60f 1760 mutex_lock(&dev_priv->dpio_lock);
ae99258f 1761 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1762 DPIO_PCS_TX_LANE2_RESET |
1763 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1764 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1765 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1766 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1767 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1768 DPIO_PCS_CLK_SOFT_RESET);
1769
1770 /* Fix up inter-pair skew failure */
ae99258f
JN		 1771 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1772 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1773 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1774 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1775}
1776
1777/*
df0c237d
JB		 1778 * Native read with retry for link status and receiver capability reads for
1779 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1780 */
1781static bool
df0c237d
JB		 1782intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1783 uint8_t *recv, int recv_bytes)
a4fc5ed6 1784{
61da5fab
JB		 1785 int ret, i;
1786
df0c237d
JB		 1787 /*
1788 * Sinks are *supposed* to come up within 1ms from an off state,
1789 * but we're also supposed to retry 3 times per the spec.
1790 */
61da5fab 1791 for (i = 0; i < 3; i++) {
df0c237d
JB		 1792 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1793 recv_bytes);
1794 if (ret == recv_bytes)
61da5fab
JB		 1795 return true;
1796 msleep(1);
1797 }
a4fc5ed6 1798
61da5fab 1799 return false;
a4fc5ed6
KP		 1800}
1801
1802/*
1803 * Fetch AUX CH registers 0x202 - 0x207 which contain
1804 * link status information
1805 */
1806static bool
93f62dad 1807intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1808{
df0c237d
JB		 1809 return intel_dp_aux_native_read_retry(intel_dp,
1810 DP_LANE0_1_STATUS,
93f62dad 1811 link_status,
df0c237d 1812 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1813}
1814
a4fc5ed6
KP		 1815#if 0
1816static char *voltage_names[] = {
1817 "0.4V", "0.6V", "0.8V", "1.2V"
1818};
1819static char *pre_emph_names[] = {
1820 "0dB", "3.5dB", "6dB", "9.5dB"
1821};
1822static char *link_train_names[] = {
1823 "pattern 1", "pattern 2", "idle", "off"
1824};
1825#endif
1826
1827/*
1828 * These are source-specific values; current Intel hardware supports
1829 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1830 */
a4fc5ed6
KP		 1831
1832static uint8_t
1a2eb460 1833intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1834{
30add22d 1835 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1836 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1837
e2fa6fba
P		 1838 if (IS_VALLEYVIEW(dev))
1839 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1840 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1841 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1842 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1843 return DP_TRAIN_VOLTAGE_SWING_1200;
1844 else
1845 return DP_TRAIN_VOLTAGE_SWING_800;
1846}
1847
1848static uint8_t
1849intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1850{
30add22d 1851 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1852 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1853
22b8bf17 1854 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1855 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1856 case DP_TRAIN_VOLTAGE_SWING_400:
1857 return DP_TRAIN_PRE_EMPHASIS_9_5;
1858 case DP_TRAIN_VOLTAGE_SWING_600:
1859 return DP_TRAIN_PRE_EMPHASIS_6;
1860 case DP_TRAIN_VOLTAGE_SWING_800:
1861 return DP_TRAIN_PRE_EMPHASIS_3_5;
1862 case DP_TRAIN_VOLTAGE_SWING_1200:
1863 default:
1864 return DP_TRAIN_PRE_EMPHASIS_0;
1865 }
e2fa6fba
P		 1866 } else if (IS_VALLEYVIEW(dev)) {
1867 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1868 case DP_TRAIN_VOLTAGE_SWING_400:
1869 return DP_TRAIN_PRE_EMPHASIS_9_5;
1870 case DP_TRAIN_VOLTAGE_SWING_600:
1871 return DP_TRAIN_PRE_EMPHASIS_6;
1872 case DP_TRAIN_VOLTAGE_SWING_800:
1873 return DP_TRAIN_PRE_EMPHASIS_3_5;
1874 case DP_TRAIN_VOLTAGE_SWING_1200:
1875 default:
1876 return DP_TRAIN_PRE_EMPHASIS_0;
1877 }
bc7d38a4 1878 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1879 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1880 case DP_TRAIN_VOLTAGE_SWING_400:
1881 return DP_TRAIN_PRE_EMPHASIS_6;
1882 case DP_TRAIN_VOLTAGE_SWING_600:
1883 case DP_TRAIN_VOLTAGE_SWING_800:
1884 return DP_TRAIN_PRE_EMPHASIS_3_5;
1885 default:
1886 return DP_TRAIN_PRE_EMPHASIS_0;
1887 }
1888 } else {
1889 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1890 case DP_TRAIN_VOLTAGE_SWING_400:
1891 return DP_TRAIN_PRE_EMPHASIS_6;
1892 case DP_TRAIN_VOLTAGE_SWING_600:
1893 return DP_TRAIN_PRE_EMPHASIS_6;
1894 case DP_TRAIN_VOLTAGE_SWING_800:
1895 return DP_TRAIN_PRE_EMPHASIS_3_5;
1896 case DP_TRAIN_VOLTAGE_SWING_1200:
1897 default:
1898 return DP_TRAIN_PRE_EMPHASIS_0;
1899 }
a4fc5ed6
KP		 1900 }
1901}
1902
e2fa6fba
P		 1903static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1904{
1905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1908 unsigned long demph_reg_value, preemph_reg_value,
1909 uniqtranscale_reg_value;
1910 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1911 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1912
1913 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1914 case DP_TRAIN_PRE_EMPHASIS_0:
1915 preemph_reg_value = 0x0004000;
1916 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1917 case DP_TRAIN_VOLTAGE_SWING_400:
1918 demph_reg_value = 0x2B405555;
1919 uniqtranscale_reg_value = 0x552AB83A;
1920 break;
1921 case DP_TRAIN_VOLTAGE_SWING_600:
1922 demph_reg_value = 0x2B404040;
1923 uniqtranscale_reg_value = 0x5548B83A;
1924 break;
1925 case DP_TRAIN_VOLTAGE_SWING_800:
1926 demph_reg_value = 0x2B245555;
1927 uniqtranscale_reg_value = 0x5560B83A;
1928 break;
1929 case DP_TRAIN_VOLTAGE_SWING_1200:
1930 demph_reg_value = 0x2B405555;
1931 uniqtranscale_reg_value = 0x5598DA3A;
1932 break;
1933 default:
1934 return 0;
1935 }
1936 break;
1937 case DP_TRAIN_PRE_EMPHASIS_3_5:
1938 preemph_reg_value = 0x0002000;
1939 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1940 case DP_TRAIN_VOLTAGE_SWING_400:
1941 demph_reg_value = 0x2B404040;
1942 uniqtranscale_reg_value = 0x5552B83A;
1943 break;
1944 case DP_TRAIN_VOLTAGE_SWING_600:
1945 demph_reg_value = 0x2B404848;
1946 uniqtranscale_reg_value = 0x5580B83A;
1947 break;
1948 case DP_TRAIN_VOLTAGE_SWING_800:
1949 demph_reg_value = 0x2B404040;
1950 uniqtranscale_reg_value = 0x55ADDA3A;
1951 break;
1952 default:
1953 return 0;
1954 }
1955 break;
1956 case DP_TRAIN_PRE_EMPHASIS_6:
1957 preemph_reg_value = 0x0000000;
1958 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1959 case DP_TRAIN_VOLTAGE_SWING_400:
1960 demph_reg_value = 0x2B305555;
1961 uniqtranscale_reg_value = 0x5570B83A;
1962 break;
1963 case DP_TRAIN_VOLTAGE_SWING_600:
1964 demph_reg_value = 0x2B2B4040;
1965 uniqtranscale_reg_value = 0x55ADDA3A;
1966 break;
1967 default:
1968 return 0;
1969 }
1970 break;
1971 case DP_TRAIN_PRE_EMPHASIS_9_5:
1972 preemph_reg_value = 0x0006000;
1973 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1974 case DP_TRAIN_VOLTAGE_SWING_400:
1975 demph_reg_value = 0x1B405555;
1976 uniqtranscale_reg_value = 0x55ADDA3A;
1977 break;
1978 default:
1979 return 0;
1980 }
1981 break;
1982 default:
1983 return 0;
1984 }
1985
0980a60f 1986 mutex_lock(&dev_priv->dpio_lock);
ae99258f
JN		 1987 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1988 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1989 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 1990 uniqtranscale_reg_value);
ae99258f
JN		 1991 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1992 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1993 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1994 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 1995 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 1996
1997 return 0;
1998}
1999
a4fc5ed6 2000static void
93f62dad 2001intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2002{
2003 uint8_t v = 0;
2004 uint8_t p = 0;
2005 int lane;
1a2eb460
KP		 2006 uint8_t voltage_max;
2007 uint8_t preemph_max;
a4fc5ed6 2008
33a34e4e 2009 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2010 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2011 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2012
2013 if (this_v > v)
2014 v = this_v;
2015 if (this_p > p)
2016 p = this_p;
2017 }
2018
1a2eb460 2019 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2020 if (v >= voltage_max)
2021 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2022
1a2eb460
KP		 2023 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2024 if (p >= preemph_max)
2025 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2026
2027 for (lane = 0; lane < 4; lane++)
33a34e4e 2028 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2029}
2030
2031static uint32_t
f0a3424e 2032intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2033{
3cf2efb1 2034 uint32_t signal_levels = 0;
a4fc5ed6 2035
3cf2efb1 2036 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2037 case DP_TRAIN_VOLTAGE_SWING_400:
2038 default:
2039 signal_levels |= DP_VOLTAGE_0_4;
2040 break;
2041 case DP_TRAIN_VOLTAGE_SWING_600:
2042 signal_levels |= DP_VOLTAGE_0_6;
2043 break;
2044 case DP_TRAIN_VOLTAGE_SWING_800:
2045 signal_levels |= DP_VOLTAGE_0_8;
2046 break;
2047 case DP_TRAIN_VOLTAGE_SWING_1200:
2048 signal_levels |= DP_VOLTAGE_1_2;
2049 break;
2050 }
3cf2efb1 2051 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2052 case DP_TRAIN_PRE_EMPHASIS_0:
2053 default:
2054 signal_levels |= DP_PRE_EMPHASIS_0;
2055 break;
2056 case DP_TRAIN_PRE_EMPHASIS_3_5:
2057 signal_levels |= DP_PRE_EMPHASIS_3_5;
2058 break;
2059 case DP_TRAIN_PRE_EMPHASIS_6:
2060 signal_levels |= DP_PRE_EMPHASIS_6;
2061 break;
2062 case DP_TRAIN_PRE_EMPHASIS_9_5:
2063 signal_levels |= DP_PRE_EMPHASIS_9_5;
2064 break;
2065 }
2066 return signal_levels;
2067}
2068
e3421a18
ZW		 2069/* Gen6's DP voltage swing and pre-emphasis control */
2070static uint32_t
2071intel_gen6_edp_signal_levels(uint8_t train_set)
2072{
3c5a62b5
YL		 2073 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2074 DP_TRAIN_PRE_EMPHASIS_MASK);
2075 switch (signal_levels) {
e3421a18 2076 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2077 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2078 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2079 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2080 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2081 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2082 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2083 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2084 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2085 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2086 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2087 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2088 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2089 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2090 default:
3c5a62b5
YL		 2091 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2092 "0x%x\n", signal_levels);
2093 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2094 }
2095}
2096
1a2eb460
KP		 2097/* Gen7's DP voltage swing and pre-emphasis control */
2098static uint32_t
2099intel_gen7_edp_signal_levels(uint8_t train_set)
2100{
2101 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2102 DP_TRAIN_PRE_EMPHASIS_MASK);
2103 switch (signal_levels) {
2104 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2105 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2106 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2107 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2108 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2109 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2110
2111 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2112 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2113 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2114 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2115
2116 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2117 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2118 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2119 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2120
2121 default:
2122 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2123 "0x%x\n", signal_levels);
2124 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2125 }
2126}
2127
d6c0d722
PZ		 2128/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2129static uint32_t
f0a3424e 2130intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2131{
d6c0d722
PZ		 2132 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2133 DP_TRAIN_PRE_EMPHASIS_MASK);
2134 switch (signal_levels) {
2135 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2136 return DDI_BUF_EMP_400MV_0DB_HSW;
2137 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2138 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2139 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2140 return DDI_BUF_EMP_400MV_6DB_HSW;
2141 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2142 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2143
d6c0d722
PZ		 2144 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2145 return DDI_BUF_EMP_600MV_0DB_HSW;
2146 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2147 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2148 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2149 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2150
d6c0d722
PZ		 2151 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2152 return DDI_BUF_EMP_800MV_0DB_HSW;
2153 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2154 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2155 default:
2156 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2157 "0x%x\n", signal_levels);
2158 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2159 }
a4fc5ed6
KP		 2160}
2161
f0a3424e
PZ		 2162/* Properly updates "DP" with the correct signal levels. */
2163static void
2164intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2165{
2166 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2167 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2168 struct drm_device *dev = intel_dig_port->base.base.dev;
2169 uint32_t signal_levels, mask;
2170 uint8_t train_set = intel_dp->train_set[0];
2171
22b8bf17 2172 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2173 signal_levels = intel_hsw_signal_levels(train_set);
2174 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2175 } else if (IS_VALLEYVIEW(dev)) {
2176 signal_levels = intel_vlv_signal_levels(intel_dp);
2177 mask = 0;
bc7d38a4 2178 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2179 signal_levels = intel_gen7_edp_signal_levels(train_set);
2180 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2181 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2182 signal_levels = intel_gen6_edp_signal_levels(train_set);
2183 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2184 } else {
2185 signal_levels = intel_gen4_signal_levels(train_set);
2186 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2187 }
2188
2189 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2190
2191 *DP = (*DP & ~mask) | signal_levels;
2192}
2193
a4fc5ed6 2194static bool
ea5b213a 2195intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2196 uint32_t dp_reg_value,
58e10eb9 2197 uint8_t dp_train_pat)
a4fc5ed6 2198{
174edf1f
PZ		 2199 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2200 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2201 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2202 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2203 int ret;
2204
22b8bf17 2205 if (HAS_DDI(dev)) {
3ab9c637 2206 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2207
2208 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2209 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2210 else
2211 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2212
2213 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2214 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2215 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2216 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2217
2218 break;
2219 case DP_TRAINING_PATTERN_1:
2220 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2221 break;
2222 case DP_TRAINING_PATTERN_2:
2223 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2224 break;
2225 case DP_TRAINING_PATTERN_3:
2226 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2227 break;
2228 }
174edf1f 2229 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2230
bc7d38a4 2231 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2232 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2233
2234 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2235 case DP_TRAINING_PATTERN_DISABLE:
2236 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2237 break;
2238 case DP_TRAINING_PATTERN_1:
2239 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2240 break;
2241 case DP_TRAINING_PATTERN_2:
2242 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2243 break;
2244 case DP_TRAINING_PATTERN_3:
2245 DRM_ERROR("DP training pattern 3 not supported\n");
2246 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2247 break;
2248 }
2249
2250 } else {
2251 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2252
2253 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2254 case DP_TRAINING_PATTERN_DISABLE:
2255 dp_reg_value |= DP_LINK_TRAIN_OFF;
2256 break;
2257 case DP_TRAINING_PATTERN_1:
2258 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2259 break;
2260 case DP_TRAINING_PATTERN_2:
2261 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2262 break;
2263 case DP_TRAINING_PATTERN_3:
2264 DRM_ERROR("DP training pattern 3 not supported\n");
2265 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2266 break;
2267 }
2268 }
2269
ea5b213a
CW		 2270 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2271 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2272
ea5b213a 2273 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2274 DP_TRAINING_PATTERN_SET,
2275 dp_train_pat);
2276
47ea7542
PZ		 2277 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2278 DP_TRAINING_PATTERN_DISABLE) {
2279 ret = intel_dp_aux_native_write(intel_dp,
2280 DP_TRAINING_LANE0_SET,
2281 intel_dp->train_set,
2282 intel_dp->lane_count);
2283 if (ret != intel_dp->lane_count)
2284 return false;
2285 }
a4fc5ed6
KP		 2286
2287 return true;
2288}
2289
3ab9c637
ID		 2290static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2291{
2292 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2293 struct drm_device *dev = intel_dig_port->base.base.dev;
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 enum port port = intel_dig_port->port;
2296 uint32_t val;
2297
2298 if (!HAS_DDI(dev))
2299 return;
2300
2301 val = I915_READ(DP_TP_CTL(port));
2302 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2303 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2304 I915_WRITE(DP_TP_CTL(port), val);
2305
2306 /*
2307 * On PORT_A we can have only eDP in SST mode. There the only reason
2308 * we need to set idle transmission mode is to work around a HW issue
2309 * where we enable the pipe while not in idle link-training mode.
2310 * In this case there is requirement to wait for a minimum number of
2311 * idle patterns to be sent.
2312 */
2313 if (port == PORT_A)
2314 return;
2315
2316 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2317 1))
2318 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2319}
2320
33a34e4e 2321/* Enable corresponding port and start training pattern 1 */
c19b0669 2322void
33a34e4e 2323intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2324{
da63a9f2 2325 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2326 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2327 int i;
2328 uint8_t voltage;
cdb0e95b 2329 int voltage_tries, loop_tries;
ea5b213a 2330 uint32_t DP = intel_dp->DP;
a4fc5ed6 2331
affa9354 2332 if (HAS_DDI(dev))
c19b0669
PZ		 2333 intel_ddi_prepare_link_retrain(encoder);
2334
3cf2efb1
CW		 2335 /* Write the link configuration data */
2336 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2337 intel_dp->link_configuration,
2338 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2339
2340 DP |= DP_PORT_EN;
1a2eb460 2341
33a34e4e 2342 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2343 voltage = 0xff;
cdb0e95b
KP		 2344 voltage_tries = 0;
2345 loop_tries = 0;
a4fc5ed6 2346 for (;;) {
33a34e4e 2347 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2348 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2349
2350 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2351
a7c9655f 2352 /* Set training pattern 1 */
47ea7542 2353 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2354 DP_TRAINING_PATTERN_1 |
2355 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2356 break;
a4fc5ed6 2357
a7c9655f 2358 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2359 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2360 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2361 break;
93f62dad 2362 }
a4fc5ed6 2363
01916270 2364 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2365 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2366 break;
2367 }
2368
2369 /* Check to see if we've tried the max voltage */
2370 for (i = 0; i < intel_dp->lane_count; i++)
2371 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2372 break;
3b4f819d 2373 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2374 ++loop_tries;
2375 if (loop_tries == 5) {
cdb0e95b
KP		 2376 DRM_DEBUG_KMS("too many full retries, give up\n");
2377 break;
2378 }
2379 memset(intel_dp->train_set, 0, 4);
2380 voltage_tries = 0;
2381 continue;
2382 }
a4fc5ed6 2383
3cf2efb1 2384 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2385 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2386 ++voltage_tries;
b06fbda3
DV		 2387 if (voltage_tries == 5) {
2388 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2389 break;
2390 }
2391 } else
2392 voltage_tries = 0;
2393 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2394
3cf2efb1 2395 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2396 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2397 }
2398
33a34e4e
JB		 2399 intel_dp->DP = DP;
2400}
2401
c19b0669 2402void
33a34e4e
JB		 2403intel_dp_complete_link_train(struct intel_dp *intel_dp)
2404{
33a34e4e 2405 bool channel_eq = false;
37f80975 2406 int tries, cr_tries;
33a34e4e
JB		 2407 uint32_t DP = intel_dp->DP;
2408
a4fc5ed6
KP		 2409 /* channel equalization */
2410 tries = 0;
37f80975 2411 cr_tries = 0;
a4fc5ed6
KP		 2412 channel_eq = false;
2413 for (;;) {
93f62dad 2414 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2415
37f80975
JB		 2416 if (cr_tries > 5) {
2417 DRM_ERROR("failed to train DP, aborting\n");
2418 intel_dp_link_down(intel_dp);
2419 break;
2420 }
2421
f0a3424e 2422 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2423
a4fc5ed6 2424 /* channel eq pattern */
47ea7542 2425 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2426 DP_TRAINING_PATTERN_2 |
2427 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2428 break;
2429
a7c9655f 2430 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2431 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2432 break;
a4fc5ed6 2433
37f80975 2434 /* Make sure clock is still ok */
01916270 2435 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2436 intel_dp_start_link_train(intel_dp);
2437 cr_tries++;
2438 continue;
2439 }
2440
1ffdff13 2441 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2442 channel_eq = true;
2443 break;
2444 }
a4fc5ed6 2445
37f80975
JB		 2446 /* Try 5 times, then try clock recovery if that fails */
2447 if (tries > 5) {
2448 intel_dp_link_down(intel_dp);
2449 intel_dp_start_link_train(intel_dp);
2450 tries = 0;
2451 cr_tries++;
2452 continue;
2453 }
a4fc5ed6 2454
3cf2efb1 2455 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2456 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2457 ++tries;
869184a6 2458 }
3cf2efb1 2459
3ab9c637
ID		 2460 intel_dp_set_idle_link_train(intel_dp);
2461
2462 intel_dp->DP = DP;
2463
d6c0d722 2464 if (channel_eq)
07f42258 2465 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2466
3ab9c637
ID		 2467}
2468
2469void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2470{
2471 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2472 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2473}
2474
2475static void
ea5b213a 2476intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2477{
da63a9f2 2478 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2479 enum port port = intel_dig_port->port;
da63a9f2 2480 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2481 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2482 struct intel_crtc *intel_crtc =
2483 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2484 uint32_t DP = intel_dp->DP;
a4fc5ed6 2485
c19b0669
PZ		 2486 /*
2487 * DDI code has a strict mode set sequence and we should try to respect
2488 * it, otherwise we might hang the machine in many different ways. So we
2489 * really should be disabling the port only on a complete crtc_disable
2490 * sequence. This function is just called under two conditions on DDI
2491 * code:
2492 * - Link train failed while doing crtc_enable, and on this case we
2493 * really should respect the mode set sequence and wait for a
2494 * crtc_disable.
2495 * - Someone turned the monitor off and intel_dp_check_link_status
2496 * called us. We don't need to disable the whole port on this case, so
2497 * when someone turns the monitor on again,
2498 * intel_ddi_prepare_link_retrain will take care of redoing the link
2499 * train.
2500 */
affa9354 2501 if (HAS_DDI(dev))
c19b0669
PZ		 2502 return;
2503
0c33d8d7 2504 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2505 return;
2506
28c97730 2507 DRM_DEBUG_KMS("\n");
32f9d658 2508
bc7d38a4 2509 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2510 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2511 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2512 } else {
2513 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2514 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2515 }
fe255d00 2516 POSTING_READ(intel_dp->output_reg);
5eb08b69 2517
ab527efc
DV		 2518 /* We don't really know why we're doing this */
2519 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2520
493a7081 2521 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2522 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2523 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2524
5bddd17f
EA		 2525 /* Hardware workaround: leaving our transcoder select
2526 * set to transcoder B while it's off will prevent the
2527 * corresponding HDMI output on transcoder A.
2528 *
2529 * Combine this with another hardware workaround:
2530 * transcoder select bit can only be cleared while the
2531 * port is enabled.
2532 */
2533 DP &= ~DP_PIPEB_SELECT;
2534 I915_WRITE(intel_dp->output_reg, DP);
2535
2536 /* Changes to enable or select take place the vblank
2537 * after being written.
2538 */
ff50afe9
DV		 2539 if (WARN_ON(crtc == NULL)) {
2540 /* We should never try to disable a port without a crtc
2541 * attached. For paranoia keep the code around for a
2542 * bit. */
31acbcc4
CW		 2543 POSTING_READ(intel_dp->output_reg);
2544 msleep(50);
2545 } else
ab527efc 2546 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2547 }
2548
832afda6 2549 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2550 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2551 POSTING_READ(intel_dp->output_reg);
f01eca2e 2552 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2553}
2554
26d61aad
KP		 2555static bool
2556intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2557{
577c7a50
DL		 2558 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2559
92fd8fd1 2560 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2561 sizeof(intel_dp->dpcd)) == 0)
2562 return false; /* aux transfer failed */
92fd8fd1 2563
577c7a50
DL		 2564 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2565 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2566 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2567
edb39244
AJ		 2568 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2569 return false; /* DPCD not present */
2570
2293bb5c
SK		 2571 /* Check if the panel supports PSR */
2572 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2573 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2574 intel_dp->psr_dpcd,
2575 sizeof(intel_dp->psr_dpcd));
2576 if (is_edp_psr(intel_dp))
2577 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
edb39244
AJ		 2578 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2579 DP_DWN_STRM_PORT_PRESENT))
2580 return true; /* native DP sink */
2581
2582 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2583 return true; /* no per-port downstream info */
2584
2585 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2586 intel_dp->downstream_ports,
2587 DP_MAX_DOWNSTREAM_PORTS) == 0)
2588 return false; /* downstream port status fetch failed */
2589
2590 return true;
92fd8fd1
KP		 2591}
2592
0d198328
AJ		 2593static void
2594intel_dp_probe_oui(struct intel_dp *intel_dp)
2595{
2596 u8 buf[3];
2597
2598 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2599 return;
2600
351cfc34
DV		 2601 ironlake_edp_panel_vdd_on(intel_dp);
2602
0d198328
AJ		 2603 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2604 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2605 buf[0], buf[1], buf[2]);
2606
2607 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2608 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2609 buf[0], buf[1], buf[2]);
351cfc34
DV		 2610
2611 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2612}
2613
a60f0e38
JB		 2614static bool
2615intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2616{
2617 int ret;
2618
2619 ret = intel_dp_aux_native_read_retry(intel_dp,
2620 DP_DEVICE_SERVICE_IRQ_VECTOR,
2621 sink_irq_vector, 1);
2622 if (!ret)
2623 return false;
2624
2625 return true;
2626}
2627
2628static void
2629intel_dp_handle_test_request(struct intel_dp *intel_dp)
2630{
2631 /* NAK by default */
9324cf7f 2632 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2633}
2634
a4fc5ed6
KP		 2635/*
2636 * According to DP spec
2637 * 5.1.2:
2638 * 1. Read DPCD
2639 * 2. Configure link according to Receiver Capabilities
2640 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2641 * 4. Check link status on receipt of hot-plug interrupt
2642 */
2643
00c09d70 2644void
ea5b213a 2645intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2646{
da63a9f2 2647 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2648 u8 sink_irq_vector;
93f62dad 2649 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2650
da63a9f2 2651 if (!intel_encoder->connectors_active)
d2b996ac 2652 return;
59cd09e1 2653
da63a9f2 2654 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2655 return;
2656
92fd8fd1 2657 /* Try to read receiver status if the link appears to be up */
93f62dad 2658 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2659 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2660 return;
2661 }
2662
92fd8fd1 2663 /* Now read the DPCD to see if it's actually running */
26d61aad 2664 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2665 intel_dp_link_down(intel_dp);
2666 return;
2667 }
2668
a60f0e38
JB		 2669 /* Try to read the source of the interrupt */
2670 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2671 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2672 /* Clear interrupt source */
2673 intel_dp_aux_native_write_1(intel_dp,
2674 DP_DEVICE_SERVICE_IRQ_VECTOR,
2675 sink_irq_vector);
2676
2677 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2678 intel_dp_handle_test_request(intel_dp);
2679 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2680 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2681 }
2682
1ffdff13 2683 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2684 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2685 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2686 intel_dp_start_link_train(intel_dp);
2687 intel_dp_complete_link_train(intel_dp);
3ab9c637 2688 intel_dp_stop_link_train(intel_dp);
33a34e4e 2689 }
a4fc5ed6 2690}
a4fc5ed6 2691
caf9ab24 2692/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2693static enum drm_connector_status
26d61aad 2694intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2695{
caf9ab24
AJ		 2696 uint8_t *dpcd = intel_dp->dpcd;
2697 bool hpd;
2698 uint8_t type;
2699
2700 if (!intel_dp_get_dpcd(intel_dp))
2701 return connector_status_disconnected;
2702
2703 /* if there's no downstream port, we're done */
2704 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2705 return connector_status_connected;
caf9ab24
AJ		 2706
2707 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2708 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2709 if (hpd) {
23235177 2710 uint8_t reg;
caf9ab24 2711 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2712 &reg, 1))
caf9ab24 2713 return connector_status_unknown;
23235177
AJ		 2714 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2715 : connector_status_disconnected;
caf9ab24
AJ		 2716 }
2717
2718 /* If no HPD, poke DDC gently */
2719 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2720 return connector_status_connected;
caf9ab24
AJ		 2721
2722 /* Well we tried, say unknown for unreliable port types */
2723 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2724 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2725 return connector_status_unknown;
2726
2727 /* Anything else is out of spec, warn and ignore */
2728 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2729 return connector_status_disconnected;
71ba9000
AJ		 2730}
2731
5eb08b69 2732static enum drm_connector_status
a9756bb5 2733ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2734{
30add22d 2735 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2738 enum drm_connector_status status;
2739
fe16d949
CW		 2740 /* Can't disconnect eDP, but you can close the lid... */
2741 if (is_edp(intel_dp)) {
30add22d 2742 status = intel_panel_detect(dev);
fe16d949
CW		 2743 if (status == connector_status_unknown)
2744 status = connector_status_connected;
2745 return status;
2746 }
01cb9ea6 2747
1b469639
DL		 2748 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2749 return connector_status_disconnected;
2750
26d61aad 2751 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2752}
2753
a4fc5ed6 2754static enum drm_connector_status
a9756bb5 2755g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2756{
30add22d 2757 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2758 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2760 uint32_t bit;
5eb08b69 2761
35aad75f
JB		 2762 /* Can't disconnect eDP, but you can close the lid... */
2763 if (is_edp(intel_dp)) {
2764 enum drm_connector_status status;
2765
2766 status = intel_panel_detect(dev);
2767 if (status == connector_status_unknown)
2768 status = connector_status_connected;
2769 return status;
2770 }
2771
34f2be46
VS		 2772 switch (intel_dig_port->port) {
2773 case PORT_B:
26739f12 2774 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2775 break;
34f2be46 2776 case PORT_C:
26739f12 2777 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2778 break;
34f2be46 2779 case PORT_D:
26739f12 2780 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2781 break;
2782 default:
2783 return connector_status_unknown;
2784 }
2785
10f76a38 2786 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2787 return connector_status_disconnected;
2788
26d61aad 2789 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2790}
2791
8c241fef
KP		 2792static struct edid *
2793intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2794{
9cd300e0 2795 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2796
9cd300e0
JN		 2797 /* use cached edid if we have one */
2798 if (intel_connector->edid) {
2799 struct edid *edid;
2800 int size;
2801
2802 /* invalid edid */
2803 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2804 return NULL;
2805
9cd300e0 2806 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2807 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2808 if (!edid)
2809 return NULL;
2810
d6f24d0f
JB		 2811 return edid;
2812 }
8c241fef 2813
9cd300e0 2814 return drm_get_edid(connector, adapter);
8c241fef
KP		 2815}
2816
2817static int
2818intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2819{
9cd300e0 2820 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2821
9cd300e0
JN		 2822 /* use cached edid if we have one */
2823 if (intel_connector->edid) {
2824 /* invalid edid */
2825 if (IS_ERR(intel_connector->edid))
2826 return 0;
2827
2828 return intel_connector_update_modes(connector,
2829 intel_connector->edid);
d6f24d0f
JB		 2830 }
2831
9cd300e0 2832 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2833}
2834
a9756bb5
ZW		 2835static enum drm_connector_status
2836intel_dp_detect(struct drm_connector *connector, bool force)
2837{
2838 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2839 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2840 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2841 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2842 enum drm_connector_status status;
2843 struct edid *edid = NULL;
2844
164c8598
CW		 2845 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2846 connector->base.id, drm_get_connector_name(connector));
2847
a9756bb5
ZW		 2848 intel_dp->has_audio = false;
2849
2850 if (HAS_PCH_SPLIT(dev))
2851 status = ironlake_dp_detect(intel_dp);
2852 else
2853 status = g4x_dp_detect(intel_dp);
1b9be9d0 2854
a9756bb5
ZW		 2855 if (status != connector_status_connected)
2856 return status;
2857
0d198328
AJ		 2858 intel_dp_probe_oui(intel_dp);
2859
c3e5f67b
DV		 2860 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2861 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2862 } else {
8c241fef 2863 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2864 if (edid) {
2865 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2866 kfree(edid);
2867 }
a9756bb5
ZW		 2868 }
2869
d63885da
PZ		 2870 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2871 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2872 return connector_status_connected;
a4fc5ed6
KP		 2873}
2874
2875static int intel_dp_get_modes(struct drm_connector *connector)
2876{
df0e9248 2877 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2878 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2879 struct drm_device *dev = connector->dev;
32f9d658 2880 int ret;
a4fc5ed6
KP		 2881
2882 /* We should parse the EDID data and find out if it has an audio sink
2883 */
2884
8c241fef 2885 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2886 if (ret)
32f9d658
ZW		 2887 return ret;
2888
f8779fda 2889 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2890 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2891 struct drm_display_mode *mode;
dd06f90e
JN		 2892 mode = drm_mode_duplicate(dev,
2893 intel_connector->panel.fixed_mode);
f8779fda 2894 if (mode) {
32f9d658
ZW		 2895 drm_mode_probed_add(connector, mode);
2896 return 1;
2897 }
2898 }
2899 return 0;
a4fc5ed6
KP		 2900}
2901
1aad7ac0
CW		 2902static bool
2903intel_dp_detect_audio(struct drm_connector *connector)
2904{
2905 struct intel_dp *intel_dp = intel_attached_dp(connector);
2906 struct edid *edid;
2907 bool has_audio = false;
2908
8c241fef 2909 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2910 if (edid) {
2911 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2912 kfree(edid);
2913 }
2914
2915 return has_audio;
2916}
2917
f684960e
CW		 2918static int
2919intel_dp_set_property(struct drm_connector *connector,
2920 struct drm_property *property,
2921 uint64_t val)
2922{
e953fd7b 2923 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2924 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2925 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2926 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2927 int ret;
2928
662595df 2929 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2930 if (ret)
2931 return ret;
2932
3f43c48d 2933 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2934 int i = val;
2935 bool has_audio;
2936
2937 if (i == intel_dp->force_audio)
f684960e
CW		 2938 return 0;
2939
1aad7ac0 2940 intel_dp->force_audio = i;
f684960e 2941
c3e5f67b 2942 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2943 has_audio = intel_dp_detect_audio(connector);
2944 else
c3e5f67b 2945 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2946
2947 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2948 return 0;
2949
1aad7ac0 2950 intel_dp->has_audio = has_audio;
f684960e
CW		 2951 goto done;
2952 }
2953
e953fd7b 2954 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2955 bool old_auto = intel_dp->color_range_auto;
2956 uint32_t old_range = intel_dp->color_range;
2957
55bc60db
VS		 2958 switch (val) {
2959 case INTEL_BROADCAST_RGB_AUTO:
2960 intel_dp->color_range_auto = true;
2961 break;
2962 case INTEL_BROADCAST_RGB_FULL:
2963 intel_dp->color_range_auto = false;
2964 intel_dp->color_range = 0;
2965 break;
2966 case INTEL_BROADCAST_RGB_LIMITED:
2967 intel_dp->color_range_auto = false;
2968 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2969 break;
2970 default:
2971 return -EINVAL;
2972 }
ae4edb80
DV		 2973
2974 if (old_auto == intel_dp->color_range_auto &&
2975 old_range == intel_dp->color_range)
2976 return 0;
2977
e953fd7b
CW		 2978 goto done;
2979 }
2980
53b41837
YN		 2981 if (is_edp(intel_dp) &&
2982 property == connector->dev->mode_config.scaling_mode_property) {
2983 if (val == DRM_MODE_SCALE_NONE) {
2984 DRM_DEBUG_KMS("no scaling not supported\n");
2985 return -EINVAL;
2986 }
2987
2988 if (intel_connector->panel.fitting_mode == val) {
2989 /* the eDP scaling property is not changed */
2990 return 0;
2991 }
2992 intel_connector->panel.fitting_mode = val;
2993
2994 goto done;
2995 }
2996
f684960e
CW		 2997 return -EINVAL;
2998
2999done:
c0c36b94
CW		 3000 if (intel_encoder->base.crtc)
3001 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3002
3003 return 0;
3004}
3005
a4fc5ed6 3006static void
73845adf 3007intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3008{
1d508706 3009 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3010
9cd300e0
JN		 3011 if (!IS_ERR_OR_NULL(intel_connector->edid))
3012 kfree(intel_connector->edid);
3013
acd8db10
PZ		 3014 /* Can't call is_edp() since the encoder may have been destroyed
3015 * already. */
3016 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3017 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3018
a4fc5ed6
KP		 3019 drm_sysfs_connector_remove(connector);
3020 drm_connector_cleanup(connector);
55f78c43 3021 kfree(connector);
a4fc5ed6
KP		 3022}
3023
00c09d70 3024void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3025{
da63a9f2
PZ		 3026 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3027 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3029
3030 i2c_del_adapter(&intel_dp->adapter);
3031 drm_encoder_cleanup(encoder);
bd943159
KP		 3032 if (is_edp(intel_dp)) {
3033 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3034 mutex_lock(&dev->mode_config.mutex);
bd943159 3035 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3036 mutex_unlock(&dev->mode_config.mutex);
bd943159 3037 }
da63a9f2 3038 kfree(intel_dig_port);
24d05927
DV		 3039}
3040
a4fc5ed6 3041static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3042 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3043 .detect = intel_dp_detect,
3044 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3045 .set_property = intel_dp_set_property,
73845adf 3046 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3047};
3048
3049static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3050 .get_modes = intel_dp_get_modes,
3051 .mode_valid = intel_dp_mode_valid,
df0e9248 3052 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3053};
3054
a4fc5ed6 3055static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3056 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3057};
3058
995b6762 3059static void
21d40d37 3060intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3061{
fa90ecef 3062 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3063
885a5014 3064 intel_dp_check_link_status(intel_dp);
c8110e52 3065}
6207937d 3066
e3421a18
ZW		 3067/* Return which DP Port should be selected for Transcoder DP control */
3068int
0206e353 3069intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3070{
3071 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3072 struct intel_encoder *intel_encoder;
3073 struct intel_dp *intel_dp;
e3421a18 3074
fa90ecef
PZ		 3075 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3076 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3077
fa90ecef
PZ		 3078 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3079 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3080 return intel_dp->output_reg;
e3421a18 3081 }
ea5b213a 3082
e3421a18
ZW		 3083 return -1;
3084}
3085
36e83a18 3086/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3087bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3088{
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090 struct child_device_config *p_child;
3091 int i;
3092
41aa3448 3093 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3094 return false;
3095
41aa3448
RV		 3096 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3097 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 3098
3099 if (p_child->dvo_port == PORT_IDPD &&
3100 p_child->device_type == DEVICE_TYPE_eDP)
3101 return true;
3102 }
3103 return false;
3104}
3105
f684960e
CW		 3106static void
3107intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3108{
53b41837
YN		 3109 struct intel_connector *intel_connector = to_intel_connector(connector);
3110
3f43c48d 3111 intel_attach_force_audio_property(connector);
e953fd7b 3112 intel_attach_broadcast_rgb_property(connector);
55bc60db 3113 intel_dp->color_range_auto = true;
53b41837
YN		 3114
3115 if (is_edp(intel_dp)) {
3116 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3117 drm_object_attach_property(
3118 &connector->base,
53b41837 3119 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3120 DRM_MODE_SCALE_ASPECT);
3121 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3122 }
f684960e
CW		 3123}
3124
67a54566
DV		 3125static void
3126intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3127 struct intel_dp *intel_dp,
3128 struct edp_power_seq *out)
67a54566
DV		 3129{
3130 struct drm_i915_private *dev_priv = dev->dev_private;
3131 struct edp_power_seq cur, vbt, spec, final;
3132 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 3133 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3134
3135 if (HAS_PCH_SPLIT(dev)) {
3136 pp_control_reg = PCH_PP_CONTROL;
3137 pp_on_reg = PCH_PP_ON_DELAYS;
3138 pp_off_reg = PCH_PP_OFF_DELAYS;
3139 pp_div_reg = PCH_PP_DIVISOR;
3140 } else {
3141 pp_control_reg = PIPEA_PP_CONTROL;
3142 pp_on_reg = PIPEA_PP_ON_DELAYS;
3143 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3144 pp_div_reg = PIPEA_PP_DIVISOR;
3145 }
67a54566
DV		 3146
3147 /* Workaround: Need to write PP_CONTROL with the unlock key as
3148 * the very first thing. */
453c5420
JB		 3149 pp = ironlake_get_pp_control(intel_dp);
3150 I915_WRITE(pp_control_reg, pp);
67a54566 3151
453c5420
JB		 3152 pp_on = I915_READ(pp_on_reg);
3153 pp_off = I915_READ(pp_off_reg);
3154 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3155
3156 /* Pull timing values out of registers */
3157 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3158 PANEL_POWER_UP_DELAY_SHIFT;
3159
3160 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3161 PANEL_LIGHT_ON_DELAY_SHIFT;
3162
3163 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3164 PANEL_LIGHT_OFF_DELAY_SHIFT;
3165
3166 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3167 PANEL_POWER_DOWN_DELAY_SHIFT;
3168
3169 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3170 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3171
3172 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3173 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3174
41aa3448 3175 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3176
3177 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3178 * our hw here, which are all in 100usec. */
3179 spec.t1_t3 = 210 * 10;
3180 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3181 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3182 spec.t10 = 500 * 10;
3183 /* This one is special and actually in units of 100ms, but zero
3184 * based in the hw (so we need to add 100 ms). But the sw vbt
3185 * table multiplies it with 1000 to make it in units of 100usec,
3186 * too. */
3187 spec.t11_t12 = (510 + 100) * 10;
3188
3189 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3190 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3191
3192 /* Use the max of the register settings and vbt. If both are
3193 * unset, fall back to the spec limits. */
3194#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3195 spec.field : \
3196 max(cur.field, vbt.field))
3197 assign_final(t1_t3);
3198 assign_final(t8);
3199 assign_final(t9);
3200 assign_final(t10);
3201 assign_final(t11_t12);
3202#undef assign_final
3203
3204#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3205 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3206 intel_dp->backlight_on_delay = get_delay(t8);
3207 intel_dp->backlight_off_delay = get_delay(t9);
3208 intel_dp->panel_power_down_delay = get_delay(t10);
3209 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3210#undef get_delay
3211
f30d26e4
JN		 3212 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3213 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3214 intel_dp->panel_power_cycle_delay);
3215
3216 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3217 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3218
3219 if (out)
3220 *out = final;
3221}
3222
3223static void
3224intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3225 struct intel_dp *intel_dp,
3226 struct edp_power_seq *seq)
3227{
3228 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3229 u32 pp_on, pp_off, pp_div, port_sel = 0;
3230 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3231 int pp_on_reg, pp_off_reg, pp_div_reg;
3232
3233 if (HAS_PCH_SPLIT(dev)) {
3234 pp_on_reg = PCH_PP_ON_DELAYS;
3235 pp_off_reg = PCH_PP_OFF_DELAYS;
3236 pp_div_reg = PCH_PP_DIVISOR;
3237 } else {
3238 pp_on_reg = PIPEA_PP_ON_DELAYS;
3239 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3240 pp_div_reg = PIPEA_PP_DIVISOR;
3241 }
3242
67a54566 3243 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3244 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3245 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3246 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3247 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3248 /* Compute the divisor for the pp clock, simply match the Bspec
3249 * formula. */
453c5420 3250 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3251 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3252 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3253
3254 /* Haswell doesn't have any port selection bits for the panel
3255 * power sequencer any more. */
bc7d38a4
ID		 3256 if (IS_VALLEYVIEW(dev)) {
3257 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3258 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3259 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 3260 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 3261 else
453c5420 3262 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 3263 }
3264
453c5420
JB		 3265 pp_on |= port_sel;
3266
3267 I915_WRITE(pp_on_reg, pp_on);
3268 I915_WRITE(pp_off_reg, pp_off);
3269 I915_WRITE(pp_div_reg, pp_div);
67a54566 3270
67a54566 3271 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3272 I915_READ(pp_on_reg),
3273 I915_READ(pp_off_reg),
3274 I915_READ(pp_div_reg));
f684960e
CW		 3275}
3276
ed92f0b2
PZ		 3277static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3278 struct intel_connector *intel_connector)
3279{
3280 struct drm_connector *connector = &intel_connector->base;
3281 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3282 struct drm_device *dev = intel_dig_port->base.base.dev;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 struct drm_display_mode *fixed_mode = NULL;
3285 struct edp_power_seq power_seq = { 0 };
3286 bool has_dpcd;
3287 struct drm_display_mode *scan;
3288 struct edid *edid;
3289
3290 if (!is_edp(intel_dp))
3291 return true;
3292
3293 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3294
3295 /* Cache DPCD and EDID for edp. */
3296 ironlake_edp_panel_vdd_on(intel_dp);
3297 has_dpcd = intel_dp_get_dpcd(intel_dp);
3298 ironlake_edp_panel_vdd_off(intel_dp, false);
3299
3300 if (has_dpcd) {
3301 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3302 dev_priv->no_aux_handshake =
3303 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3304 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3305 } else {
3306 /* if this fails, presume the device is a ghost */
3307 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3308 return false;
3309 }
3310
3311 /* We now know it's not a ghost, init power sequence regs. */
3312 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3313 &power_seq);
3314
3315 ironlake_edp_panel_vdd_on(intel_dp);
3316 edid = drm_get_edid(connector, &intel_dp->adapter);
3317 if (edid) {
3318 if (drm_add_edid_modes(connector, edid)) {
3319 drm_mode_connector_update_edid_property(connector,
3320 edid);
3321 drm_edid_to_eld(connector, edid);
3322 } else {
3323 kfree(edid);
3324 edid = ERR_PTR(-EINVAL);
3325 }
3326 } else {
3327 edid = ERR_PTR(-ENOENT);
3328 }
3329 intel_connector->edid = edid;
3330
3331 /* prefer fixed mode from EDID if available */
3332 list_for_each_entry(scan, &connector->probed_modes, head) {
3333 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3334 fixed_mode = drm_mode_duplicate(dev, scan);
3335 break;
3336 }
3337 }
3338
3339 /* fallback to VBT if available for eDP */
3340 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3341 fixed_mode = drm_mode_duplicate(dev,
3342 dev_priv->vbt.lfp_lvds_vbt_mode);
3343 if (fixed_mode)
3344 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3345 }
3346
3347 ironlake_edp_panel_vdd_off(intel_dp, false);
3348
3349 intel_panel_init(&intel_connector->panel, fixed_mode);
3350 intel_panel_setup_backlight(connector);
3351
3352 return true;
3353}
3354
16c25533 3355bool
f0fec3f2
PZ		 3356intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3357 struct intel_connector *intel_connector)
a4fc5ed6 3358{
f0fec3f2
PZ		 3359 struct drm_connector *connector = &intel_connector->base;
3360 struct intel_dp *intel_dp = &intel_dig_port->dp;
3361 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3362 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3363 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3364 enum port port = intel_dig_port->port;
5eb08b69 3365 const char *name = NULL;
b2a14755 3366 int type, error;
a4fc5ed6 3367
0767935e
DV		 3368 /* Preserve the current hw state. */
3369 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3370 intel_dp->attached_connector = intel_connector;
3d3dc149 3371
f7d24902 3372 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3373 /*
3374 * FIXME : We need to initialize built-in panels before external panels.
3375 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3376 */
f7d24902
ID		 3377 switch (port) {
3378 case PORT_A:
b329530c 3379 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3380 break;
3381 case PORT_C:
3382 if (IS_VALLEYVIEW(dev))
3383 type = DRM_MODE_CONNECTOR_eDP;
3384 break;
3385 case PORT_D:
3386 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3387 type = DRM_MODE_CONNECTOR_eDP;
3388 break;
3389 default: /* silence GCC warning */
3390 break;
b329530c
AJ		 3391 }
3392
f7d24902
ID		 3393 /*
3394 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3395 * for DP the encoder type can be set by the caller to
3396 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3397 */
3398 if (type == DRM_MODE_CONNECTOR_eDP)
3399 intel_encoder->type = INTEL_OUTPUT_EDP;
3400
e7281eab
ID		 3401 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3402 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3403 port_name(port));
3404
b329530c 3405 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3406 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3407
a4fc5ed6
KP		 3408 connector->interlace_allowed = true;
3409 connector->doublescan_allowed = 0;
3410
f0fec3f2
PZ		 3411 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3412 ironlake_panel_vdd_work);
a4fc5ed6 3413
df0e9248 3414 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3415 drm_sysfs_connector_add(connector);
3416
affa9354 3417 if (HAS_DDI(dev))
bcbc889b
PZ		 3418 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3419 else
3420 intel_connector->get_hw_state = intel_connector_get_hw_state;
3421
9ed35ab1
PZ		 3422 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3423 if (HAS_DDI(dev)) {
3424 switch (intel_dig_port->port) {
3425 case PORT_A:
3426 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3427 break;
3428 case PORT_B:
3429 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3430 break;
3431 case PORT_C:
3432 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3433 break;
3434 case PORT_D:
3435 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3436 break;
3437 default:
3438 BUG();
3439 }
3440 }
e8cb4558 3441
a4fc5ed6 3442 /* Set up the DDC bus. */
ab9d7c30
PZ		 3443 switch (port) {
3444 case PORT_A:
1d843f9d 3445 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3446 name = "DPDDC-A";
3447 break;
3448 case PORT_B:
1d843f9d 3449 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3450 name = "DPDDC-B";
3451 break;
3452 case PORT_C:
1d843f9d 3453 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3454 name = "DPDDC-C";
3455 break;
3456 case PORT_D:
1d843f9d 3457 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3458 name = "DPDDC-D";
3459 break;
3460 default:
ad1c0b19 3461 BUG();
5eb08b69
ZW		 3462 }
3463
b2a14755
PZ		 3464 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3465 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3466 error, port_name(port));
c1f05264 3467
2b28bb1b
RV		 3468 intel_dp->psr_setup_done = false;
3469
b2f246a8 3470 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3471 i2c_del_adapter(&intel_dp->adapter);
3472 if (is_edp(intel_dp)) {
3473 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3474 mutex_lock(&dev->mode_config.mutex);
3475 ironlake_panel_vdd_off_sync(intel_dp);
3476 mutex_unlock(&dev->mode_config.mutex);
3477 }
b2f246a8
PZ		 3478 drm_sysfs_connector_remove(connector);
3479 drm_connector_cleanup(connector);
16c25533 3480 return false;
b2f246a8 3481 }
32f9d658 3482
f684960e
CW		 3483 intel_dp_add_properties(intel_dp, connector);
3484
a4fc5ed6
KP		 3485 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3486 * 0xd. Failure to do so will result in spurious interrupts being
3487 * generated on the port when a cable is not attached.
3488 */
3489 if (IS_G4X(dev) && !IS_GM45(dev)) {
3490 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3491 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3492 }
16c25533
PZ		 3493
3494 return true;
a4fc5ed6 3495}
f0fec3f2
PZ		 3496
3497void
3498intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3499{
3500 struct intel_digital_port *intel_dig_port;
3501 struct intel_encoder *intel_encoder;
3502 struct drm_encoder *encoder;
3503 struct intel_connector *intel_connector;
3504
3505 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3506 if (!intel_dig_port)
3507 return;
3508
3509 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3510 if (!intel_connector) {
3511 kfree(intel_dig_port);
3512 return;
3513 }
3514
3515 intel_encoder = &intel_dig_port->base;
3516 encoder = &intel_encoder->base;
3517
3518 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3519 DRM_MODE_ENCODER_TMDS);
3520
5bfe2ac0 3521 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3522 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3523 intel_encoder->disable = intel_disable_dp;
3524 intel_encoder->post_disable = intel_post_disable_dp;
3525 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3526 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3527 if (IS_VALLEYVIEW(dev)) {
89b667f8 3528 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
ab1f90f9
JN		 3529 intel_encoder->pre_enable = vlv_pre_enable_dp;
3530 intel_encoder->enable = vlv_enable_dp;
3531 } else {
3532 intel_encoder->pre_enable = intel_pre_enable_dp;
3533 intel_encoder->enable = intel_enable_dp;
3534 }
f0fec3f2 3535
174edf1f 3536 intel_dig_port->port = port;
f0fec3f2
PZ		 3537 intel_dig_port->dp.output_reg = output_reg;
3538
00c09d70 3539 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3540 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3541 intel_encoder->cloneable = false;
3542 intel_encoder->hot_plug = intel_dp_hot_plug;
3543
15b1d171
PZ		 3544 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3545 drm_encoder_cleanup(encoder);
3546 kfree(intel_dig_port);
b2f246a8 3547 kfree(intel_connector);
15b1d171 3548 }
f0fec3f2 3549}
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