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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
b6b5e383
DL		 664static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
665{
666 /*
667 * SKL doesn't need us to program the AUX clock divider (Hardware will
668 * derive the clock from CDCLK automatically). We still implement the
669 * get_aux_clock_divider vfunc to plug-in into the existing code.
670 */
671 return index ? 0 : 1;
672}
673
5ed12a19
DL		 674static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
675 bool has_aux_irq,
676 int send_bytes,
677 uint32_t aux_clock_divider)
678{
679 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
680 struct drm_device *dev = intel_dig_port->base.base.dev;
681 uint32_t precharge, timeout;
682
683 if (IS_GEN6(dev))
684 precharge = 3;
685 else
686 precharge = 5;
687
688 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
689 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
690 else
691 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
692
693 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 694 DP_AUX_CH_CTL_DONE |
5ed12a19 695 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 696 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 697 timeout |
788d4433 698 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 699 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
700 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 701 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 702}
703
b9ca5fad
DL		 704static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
705 bool has_aux_irq,
706 int send_bytes,
707 uint32_t unused)
708{
709 return DP_AUX_CH_CTL_SEND_BUSY |
710 DP_AUX_CH_CTL_DONE |
711 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
712 DP_AUX_CH_CTL_TIME_OUT_ERROR |
713 DP_AUX_CH_CTL_TIME_OUT_1600us |
714 DP_AUX_CH_CTL_RECEIVE_ERROR |
715 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
716 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
717}
718
b84a1cf8
RV		 719static int
720intel_dp_aux_ch(struct intel_dp *intel_dp,
721 uint8_t *send, int send_bytes,
722 uint8_t *recv, int recv_size)
723{
724 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
725 struct drm_device *dev = intel_dig_port->base.base.dev;
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
728 uint32_t ch_data = ch_ctl + 4;
bc86625a 729 uint32_t aux_clock_divider;
b84a1cf8
RV		 730 int i, ret, recv_bytes;
731 uint32_t status;
5ed12a19 732 int try, clock = 0;
4e6b788c 733 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 734 bool vdd;
735
773538e8 736 pps_lock(intel_dp);
e39b999a 737
72c3500a
VS		 738 /*
739 * We will be called with VDD already enabled for dpcd/edid/oui reads.
740 * In such cases we want to leave VDD enabled and it's up to upper layers
741 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
742 * ourselves.
743 */
1e0560e0 744 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 745
746 /* dp aux is extremely sensitive to irq latency, hence request the
747 * lowest possible wakeup latency and so prevent the cpu from going into
748 * deep sleep states.
749 */
750 pm_qos_update_request(&dev_priv->pm_qos, 0);
751
752 intel_dp_check_edp(intel_dp);
5eb08b69 753
c67a470b
PZ		 754 intel_aux_display_runtime_get(dev_priv);
755
11bee43e
JB		 756 /* Try to wait for any previous AUX channel activity */
757 for (try = 0; try < 3; try++) {
ef04f00d 758 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 759 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
760 break;
761 msleep(1);
762 }
763
764 if (try == 3) {
765 WARN(1, "dp_aux_ch not started status 0x%08x\n",
766 I915_READ(ch_ctl));
9ee32fea
DV		 767 ret = -EBUSY;
768 goto out;
4f7f7b7e
CW		 769 }
770
46a5ae9f
PZ		 771 /* Only 5 data registers! */
772 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
773 ret = -E2BIG;
774 goto out;
775 }
776
ec5b01dd 777 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 778 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
779 has_aux_irq,
780 send_bytes,
781 aux_clock_divider);
5ed12a19 782
bc86625a
CW		 783 /* Must try at least 3 times according to DP spec */
784 for (try = 0; try < 5; try++) {
785 /* Load the send data into the aux channel data registers */
786 for (i = 0; i < send_bytes; i += 4)
787 I915_WRITE(ch_data + i,
788 pack_aux(send + i, send_bytes - i));
789
790 /* Send the command and wait for it to complete */
5ed12a19 791 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 792
793 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
794
795 /* Clear done status and any errors */
796 I915_WRITE(ch_ctl,
797 status |
798 DP_AUX_CH_CTL_DONE |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR |
800 DP_AUX_CH_CTL_RECEIVE_ERROR);
801
802 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
803 DP_AUX_CH_CTL_RECEIVE_ERROR))
804 continue;
805 if (status & DP_AUX_CH_CTL_DONE)
806 break;
807 }
4f7f7b7e 808 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 809 break;
810 }
811
a4fc5ed6 812 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 813 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 814 ret = -EBUSY;
815 goto out;
a4fc5ed6
KP		 816 }
817
818 /* Check for timeout or receive error.
819 * Timeouts occur when the sink is not connected
820 */
a5b3da54 821 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 822 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 823 ret = -EIO;
824 goto out;
a5b3da54 825 }
1ae8c0a5
KP		 826
827 /* Timeouts occur when the device isn't connected, so they're
828 * "normal" -- don't fill the kernel log with these */
a5b3da54 829 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 830 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 831 ret = -ETIMEDOUT;
832 goto out;
a4fc5ed6
KP		 833 }
834
835 /* Unload any bytes sent back from the other side */
836 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
837 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 838 if (recv_bytes > recv_size)
839 recv_bytes = recv_size;
0206e353 840
4f7f7b7e
CW		 841 for (i = 0; i < recv_bytes; i += 4)
842 unpack_aux(I915_READ(ch_data + i),
843 recv + i, recv_bytes - i);
a4fc5ed6 844
9ee32fea
DV		 845 ret = recv_bytes;
846out:
847 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 848 intel_aux_display_runtime_put(dev_priv);
9ee32fea 849
884f19e9
JN		 850 if (vdd)
851 edp_panel_vdd_off(intel_dp, false);
852
773538e8 853 pps_unlock(intel_dp);
e39b999a 854
9ee32fea 855 return ret;
a4fc5ed6
KP		 856}
857
a6c8aff0
JN		 858#define BARE_ADDRESS_SIZE 3
859#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 860static ssize_t
861intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 862{
9d1a1031
JN		 863 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
864 uint8_t txbuf[20], rxbuf[20];
865 size_t txsize, rxsize;
a4fc5ed6 866 int ret;
a4fc5ed6 867
9d1a1031
JN		 868 txbuf[0] = msg->request << 4;
869 txbuf[1] = msg->address >> 8;
870 txbuf[2] = msg->address & 0xff;
871 txbuf[3] = msg->size - 1;
46a5ae9f 872
9d1a1031
JN		 873 switch (msg->request & ~DP_AUX_I2C_MOT) {
874 case DP_AUX_NATIVE_WRITE:
875 case DP_AUX_I2C_WRITE:
a6c8aff0 876 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 877 rxsize = 1;
f51a44b9 878
9d1a1031
JN		 879 if (WARN_ON(txsize > 20))
880 return -E2BIG;
a4fc5ed6 881
9d1a1031 882 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 883
9d1a1031
JN		 884 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
885 if (ret > 0) {
886 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 887
9d1a1031
JN		 888 /* Return payload size. */
889 ret = msg->size;
890 }
891 break;
46a5ae9f 892
9d1a1031
JN		 893 case DP_AUX_NATIVE_READ:
894 case DP_AUX_I2C_READ:
a6c8aff0 895 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 896 rxsize = msg->size + 1;
a4fc5ed6 897
9d1a1031
JN		 898 if (WARN_ON(rxsize > 20))
899 return -E2BIG;
a4fc5ed6 900
9d1a1031
JN		 901 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
902 if (ret > 0) {
903 msg->reply = rxbuf[0] >> 4;
904 /*
905 * Assume happy day, and copy the data. The caller is
906 * expected to check msg->reply before touching it.
907 *
908 * Return payload size.
909 */
910 ret--;
911 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 912 }
9d1a1031
JN		 913 break;
914
915 default:
916 ret = -EINVAL;
917 break;
a4fc5ed6 918 }
f51a44b9 919
9d1a1031 920 return ret;
a4fc5ed6
KP		 921}
922
9d1a1031
JN		 923static void
924intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
925{
926 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
928 enum port port = intel_dig_port->port;
0b99836f 929 const char *name = NULL;
ab2c0672
DA		 930 int ret;
931
33ad6626
JN		 932 switch (port) {
933 case PORT_A:
934 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 935 name = "DPDDC-A";
ab2c0672 936 break;
33ad6626
JN		 937 case PORT_B:
938 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 939 name = "DPDDC-B";
ab2c0672 940 break;
33ad6626
JN		 941 case PORT_C:
942 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 943 name = "DPDDC-C";
ab2c0672 944 break;
33ad6626
JN		 945 case PORT_D:
946 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 947 name = "DPDDC-D";
33ad6626
JN		 948 break;
949 default:
950 BUG();
ab2c0672
DA		 951 }
952
1b1aad75
DL		 953 /*
954 * The AUX_CTL register is usually DP_CTL + 0x10.
955 *
956 * On Haswell and Broadwell though:
957 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
958 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
959 *
960 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
961 */
962 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 963 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 964
0b99836f 965 intel_dp->aux.name = name;
9d1a1031
JN		 966 intel_dp->aux.dev = dev->dev;
967 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 968
0b99836f
JN		 969 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
970 connector->base.kdev->kobj.name);
8316f337 971
4f71d0cb 972 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 973 if (ret < 0) {
4f71d0cb 974 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 975 name, ret);
976 return;
ab2c0672 977 }
8a5e6aeb 978
0b99836f
JN		 979 ret = sysfs_create_link(&connector->base.kdev->kobj,
980 &intel_dp->aux.ddc.dev.kobj,
981 intel_dp->aux.ddc.dev.kobj.name);
982 if (ret < 0) {
983 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 984 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 985 }
a4fc5ed6
KP		 986}
987
80f65de3
ID		 988static void
989intel_dp_connector_unregister(struct intel_connector *intel_connector)
990{
991 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
992
0e32b39c
DA		 993 if (!intel_connector->mst_port)
994 sysfs_remove_link(&intel_connector->base.kdev->kobj,
995 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 996 intel_connector_unregister(intel_connector);
997}
998
0e50338c
DV		 999static void
1000hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1001{
1002 switch (link_bw) {
1003 case DP_LINK_BW_1_62:
1004 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1005 break;
1006 case DP_LINK_BW_2_7:
1007 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1008 break;
1009 case DP_LINK_BW_5_4:
1010 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1011 break;
1012 }
1013}
1014
c6bb3538
DV		 1015static void
1016intel_dp_set_clock(struct intel_encoder *encoder,
1017 struct intel_crtc_config *pipe_config, int link_bw)
1018{
1019 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1020 const struct dp_link_dpll *divisor = NULL;
1021 int i, count = 0;
c6bb3538
DV		 1022
1023 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1024 divisor = gen4_dpll;
1025 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1026 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1027 divisor = pch_dpll;
1028 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1029 } else if (IS_CHERRYVIEW(dev)) {
1030 divisor = chv_dpll;
1031 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1032 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1033 divisor = vlv_dpll;
1034 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1035 }
9dd4ffdf
CML		 1036
1037 if (divisor && count) {
1038 for (i = 0; i < count; i++) {
1039 if (link_bw == divisor[i].link_bw) {
1040 pipe_config->dpll = divisor[i].dpll;
1041 pipe_config->clock_set = true;
1042 break;
1043 }
1044 }
c6bb3538
DV		 1045 }
1046}
1047
00c09d70 1048bool
5bfe2ac0
DV		 1049intel_dp_compute_config(struct intel_encoder *encoder,
1050 struct intel_crtc_config *pipe_config)
a4fc5ed6 1051{
5bfe2ac0 1052 struct drm_device *dev = encoder->base.dev;
36008365 1053 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1054 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1055 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1056 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1057 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1058 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1059 int lane_count, clock;
56071a20 1060 int min_lane_count = 1;
eeb6324d 1061 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1062 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1063 int min_clock = 0;
06ea66b6 1064 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1065 int bpp, mode_rate;
06ea66b6 1066 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1067 int link_avail, link_clock;
a4fc5ed6 1068
bc7d38a4 1069 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1070 pipe_config->has_pch_encoder = true;
1071
03afc4a2 1072 pipe_config->has_dp_encoder = true;
f769cd24 1073 pipe_config->has_drrs = false;
9ed109a7 1074 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1075
dd06f90e
JN		 1076 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1077 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1078 adjusted_mode);
2dd24552
JB		 1079 if (!HAS_PCH_SPLIT(dev))
1080 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1081 intel_connector->panel.fitting_mode);
1082 else
b074cec8
JB		 1083 intel_pch_panel_fitting(intel_crtc, pipe_config,
1084 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1085 }
1086
cb1793ce 1087 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1088 return false;
1089
083f9560
DV		 1090 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1091 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1092 max_lane_count, bws[max_clock],
1093 adjusted_mode->crtc_clock);
083f9560 1094
36008365
DV		 1095 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1096 * bpc in between. */
3e7ca985 1097 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1098 if (is_edp(intel_dp)) {
1099 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1100 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1101 dev_priv->vbt.edp_bpp);
1102 bpp = dev_priv->vbt.edp_bpp;
1103 }
1104
344c5bbc
JN		 1105 /*
1106 * Use the maximum clock and number of lanes the eDP panel
1107 * advertizes being capable of. The panels are generally
1108 * designed to support only a single clock and lane
1109 * configuration, and typically these values correspond to the
1110 * native resolution of the panel.
1111 */
1112 min_lane_count = max_lane_count;
1113 min_clock = max_clock;
7984211e 1114 }
657445fe 1115
36008365 1116 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1117 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1118 bpp);
36008365 1119
c6930992
DA		 1120 for (clock = min_clock; clock <= max_clock; clock++) {
1121 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1122 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1123 link_avail = intel_dp_max_data_rate(link_clock,
1124 lane_count);
1125
1126 if (mode_rate <= link_avail) {
1127 goto found;
1128 }
1129 }
1130 }
1131 }
c4867936 1132
36008365 1133 return false;
3685a8f3 1134
36008365 1135found:
55bc60db
VS		 1136 if (intel_dp->color_range_auto) {
1137 /*
1138 * See:
1139 * CEA-861-E - 5.1 Default Encoding Parameters
1140 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1141 */
18316c8c 1142 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1143 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1144 else
1145 intel_dp->color_range = 0;
1146 }
1147
3685a8f3 1148 if (intel_dp->color_range)
50f3b016 1149 pipe_config->limited_color_range = true;
a4fc5ed6 1150
36008365
DV		 1151 intel_dp->link_bw = bws[clock];
1152 intel_dp->lane_count = lane_count;
657445fe 1153 pipe_config->pipe_bpp = bpp;
ff9a6750 1154 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1155
36008365
DV		 1156 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1157 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1158 pipe_config->port_clock, bpp);
36008365
DV		 1159 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1160 mode_rate, link_avail);
a4fc5ed6 1161
03afc4a2 1162 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1163 adjusted_mode->crtc_clock,
1164 pipe_config->port_clock,
03afc4a2 1165 &pipe_config->dp_m_n);
9d1a455b 1166
439d7ac0
PB		 1167 if (intel_connector->panel.downclock_mode != NULL &&
1168 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1169 pipe_config->has_drrs = true;
439d7ac0
PB		 1170 intel_link_compute_m_n(bpp, lane_count,
1171 intel_connector->panel.downclock_mode->clock,
1172 pipe_config->port_clock,
1173 &pipe_config->dp_m2_n2);
1174 }
1175
ea155f32 1176 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1177 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1178 else
1179 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1180
03afc4a2 1181 return true;
a4fc5ed6
KP		 1182}
1183
7c62a164 1184static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1185{
7c62a164
DV		 1186 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1187 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1188 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 u32 dpa_ctl;
1191
ff9a6750 1192 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1193 dpa_ctl = I915_READ(DP_A);
1194 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1195
ff9a6750 1196 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1197 /* For a long time we've carried around a ILK-DevA w/a for the
1198 * 160MHz clock. If we're really unlucky, it's still required.
1199 */
1200 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1201 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1202 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1203 } else {
1204 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1205 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1206 }
1ce17038 1207
ea9b6006
DV		 1208 I915_WRITE(DP_A, dpa_ctl);
1209
1210 POSTING_READ(DP_A);
1211 udelay(500);
1212}
1213
8ac33ed3 1214static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1215{
b934223d 1216 struct drm_device *dev = encoder->base.dev;
417e822d 1217 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1218 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1219 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1220 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1221 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1222
417e822d 1223 /*
1a2eb460 1224 * There are four kinds of DP registers:
417e822d
KP		 1225 *
1226 * IBX PCH
1a2eb460
KP		 1227 * SNB CPU
1228 * IVB CPU
417e822d
KP		 1229 * CPT PCH
1230 *
1231 * IBX PCH and CPU are the same for almost everything,
1232 * except that the CPU DP PLL is configured in this
1233 * register
1234 *
1235 * CPT PCH is quite different, having many bits moved
1236 * to the TRANS_DP_CTL register instead. That
1237 * configuration happens (oddly) in ironlake_pch_enable
1238 */
9c9e7927 1239
417e822d
KP		 1240 /* Preserve the BIOS-computed detected bit. This is
1241 * supposed to be read-only.
1242 */
1243 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1244
417e822d 1245 /* Handle DP bits in common between all three register formats */
417e822d 1246 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1247 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1248
9ed109a7 1249 if (crtc->config.has_audio) {
e0dac65e 1250 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1251 pipe_name(crtc->pipe));
ea5b213a 1252 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1253 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1254 }
247d89f6 1255
417e822d 1256 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1257
bc7d38a4 1258 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1259 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1260 intel_dp->DP |= DP_SYNC_HS_HIGH;
1261 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1262 intel_dp->DP |= DP_SYNC_VS_HIGH;
1263 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1264
6aba5b6c 1265 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1266 intel_dp->DP |= DP_ENHANCED_FRAMING;
1267
7c62a164 1268 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1269 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1270 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1271 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1272
1273 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1274 intel_dp->DP |= DP_SYNC_HS_HIGH;
1275 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1276 intel_dp->DP |= DP_SYNC_VS_HIGH;
1277 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1278
6aba5b6c 1279 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1280 intel_dp->DP |= DP_ENHANCED_FRAMING;
1281
44f37d1f
CML		 1282 if (!IS_CHERRYVIEW(dev)) {
1283 if (crtc->pipe == 1)
1284 intel_dp->DP |= DP_PIPEB_SELECT;
1285 } else {
1286 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1287 }
417e822d
KP		 1288 } else {
1289 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1290 }
a4fc5ed6
KP		 1291}
1292
ffd6749d
PZ		 1293#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1294#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1295
1a5ef5b7
PZ		 1296#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1297#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1298
ffd6749d
PZ		 1299#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1300#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1301
4be73780 1302static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1303 u32 mask,
1304 u32 value)
bd943159 1305{
30add22d 1306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1307 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1308 u32 pp_stat_reg, pp_ctrl_reg;
1309
e39b999a
VS		 1310 lockdep_assert_held(&dev_priv->pps_mutex);
1311
bf13e81b
JN		 1312 pp_stat_reg = _pp_stat_reg(intel_dp);
1313 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1314
99ea7127 1315 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1316 mask, value,
1317 I915_READ(pp_stat_reg),
1318 I915_READ(pp_ctrl_reg));
32ce697c 1319
453c5420 1320 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1321 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1322 I915_READ(pp_stat_reg),
1323 I915_READ(pp_ctrl_reg));
32ce697c 1324 }
54c136d4
CW		 1325
1326 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1327}
32ce697c 1328
4be73780 1329static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1330{
1331 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1332 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1333}
1334
4be73780 1335static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1336{
1337 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1338 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1339}
1340
4be73780 1341static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1342{
1343 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1344
1345 /* When we disable the VDD override bit last we have to do the manual
1346 * wait. */
1347 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1348 intel_dp->panel_power_cycle_delay);
1349
4be73780 1350 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1351}
1352
4be73780 1353static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1354{
1355 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1356 intel_dp->backlight_on_delay);
1357}
1358
4be73780 1359static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1360{
1361 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1362 intel_dp->backlight_off_delay);
1363}
99ea7127 1364
832dd3c1
KP		 1365/* Read the current pp_control value, unlocking the register if it
1366 * is locked
1367 */
1368
453c5420 1369static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1370{
453c5420
JB		 1371 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373 u32 control;
832dd3c1 1374
e39b999a
VS		 1375 lockdep_assert_held(&dev_priv->pps_mutex);
1376
bf13e81b 1377 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1378 control &= ~PANEL_UNLOCK_MASK;
1379 control |= PANEL_UNLOCK_REGS;
1380 return control;
bd943159
KP		 1381}
1382
951468f3
VS		 1383/*
1384 * Must be paired with edp_panel_vdd_off().
1385 * Must hold pps_mutex around the whole on/off sequence.
1386 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1387 */
1e0560e0 1388static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1389{
30add22d 1390 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1392 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1393 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1394 enum intel_display_power_domain power_domain;
5d613501 1395 u32 pp;
453c5420 1396 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1397 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1398
e39b999a
VS		 1399 lockdep_assert_held(&dev_priv->pps_mutex);
1400
97af61f5 1401 if (!is_edp(intel_dp))
adddaaf4 1402 return false;
bd943159
KP		 1403
1404 intel_dp->want_panel_vdd = true;
99ea7127 1405
4be73780 1406 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1407 return need_to_disable;
b0665d57 1408
4e6e1a54
ID		 1409 power_domain = intel_display_port_power_domain(intel_encoder);
1410 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1411
b0665d57 1412 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1413
4be73780
DV		 1414 if (!edp_have_panel_power(intel_dp))
1415 wait_panel_power_cycle(intel_dp);
99ea7127 1416
453c5420 1417 pp = ironlake_get_pp_control(intel_dp);
5d613501 1418 pp |= EDP_FORCE_VDD;
ebf33b18 1419
bf13e81b
JN		 1420 pp_stat_reg = _pp_stat_reg(intel_dp);
1421 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1422
1423 I915_WRITE(pp_ctrl_reg, pp);
1424 POSTING_READ(pp_ctrl_reg);
1425 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1426 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1427 /*
1428 * If the panel wasn't on, delay before accessing aux channel
1429 */
4be73780 1430 if (!edp_have_panel_power(intel_dp)) {
bd943159 1431 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1432 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1433 }
adddaaf4
JN		 1434
1435 return need_to_disable;
1436}
1437
951468f3
VS		 1438/*
1439 * Must be paired with intel_edp_panel_vdd_off() or
1440 * intel_edp_panel_off().
1441 * Nested calls to these functions are not allowed since
1442 * we drop the lock. Caller must use some higher level
1443 * locking to prevent nested calls from other threads.
1444 */
b80d6c78 1445void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1446{
c695b6b6 1447 bool vdd;
adddaaf4 1448
c695b6b6
VS		 1449 if (!is_edp(intel_dp))
1450 return;
1451
773538e8 1452 pps_lock(intel_dp);
c695b6b6 1453 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1454 pps_unlock(intel_dp);
c695b6b6
VS		 1455
1456 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1457}
1458
4be73780 1459static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1460{
30add22d 1461 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1462 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1463 struct intel_digital_port *intel_dig_port =
1464 dp_to_dig_port(intel_dp);
1465 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1466 enum intel_display_power_domain power_domain;
5d613501 1467 u32 pp;
453c5420 1468 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1469
e39b999a 1470 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1471
15e899a0 1472 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1473
15e899a0 1474 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1475 return;
b0665d57 1476
be2c9196 1477 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1478
be2c9196
VS		 1479 pp = ironlake_get_pp_control(intel_dp);
1480 pp &= ~EDP_FORCE_VDD;
453c5420 1481
be2c9196
VS		 1482 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1483 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1484
be2c9196
VS		 1485 I915_WRITE(pp_ctrl_reg, pp);
1486 POSTING_READ(pp_ctrl_reg);
99ea7127 1487
be2c9196
VS		 1488 /* Make sure sequencer is idle before allowing subsequent activity */
1489 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1490 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1491
be2c9196
VS		 1492 if ((pp & POWER_TARGET_ON) == 0)
1493 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1494
be2c9196
VS		 1495 power_domain = intel_display_port_power_domain(intel_encoder);
1496 intel_display_power_put(dev_priv, power_domain);
bd943159 1497}
5d613501 1498
4be73780 1499static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1500{
1501 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1502 struct intel_dp, panel_vdd_work);
bd943159 1503
773538e8 1504 pps_lock(intel_dp);
15e899a0
VS		 1505 if (!intel_dp->want_panel_vdd)
1506 edp_panel_vdd_off_sync(intel_dp);
773538e8 1507 pps_unlock(intel_dp);
bd943159
KP		 1508}
1509
aba86890
ID		 1510static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1511{
1512 unsigned long delay;
1513
1514 /*
1515 * Queue the timer to fire a long time from now (relative to the power
1516 * down delay) to keep the panel power up across a sequence of
1517 * operations.
1518 */
1519 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1520 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1521}
1522
951468f3
VS		 1523/*
1524 * Must be paired with edp_panel_vdd_on().
1525 * Must hold pps_mutex around the whole on/off sequence.
1526 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1527 */
4be73780 1528static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1529{
e39b999a
VS		 1530 struct drm_i915_private *dev_priv =
1531 intel_dp_to_dev(intel_dp)->dev_private;
1532
1533 lockdep_assert_held(&dev_priv->pps_mutex);
1534
97af61f5
KP		 1535 if (!is_edp(intel_dp))
1536 return;
5d613501 1537
bd943159 1538 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1539
bd943159
KP		 1540 intel_dp->want_panel_vdd = false;
1541
aba86890 1542 if (sync)
4be73780 1543 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1544 else
1545 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1546}
1547
951468f3
VS		 1548/*
1549 * Must be paired with intel_edp_panel_vdd_on().
1550 * Nested calls to these functions are not allowed since
1551 * we drop the lock. Caller must use some higher level
1552 * locking to prevent nested calls from other threads.
1553 */
1e0560e0
VS		 1554static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1555{
e39b999a
VS		 1556 if (!is_edp(intel_dp))
1557 return;
1558
773538e8 1559 pps_lock(intel_dp);
1e0560e0 1560 edp_panel_vdd_off(intel_dp, sync);
773538e8 1561 pps_unlock(intel_dp);
1e0560e0
VS		 1562}
1563
4be73780 1564void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1565{
30add22d 1566 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1567 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1568 u32 pp;
453c5420 1569 u32 pp_ctrl_reg;
9934c132 1570
97af61f5 1571 if (!is_edp(intel_dp))
bd943159 1572 return;
99ea7127
KP		 1573
1574 DRM_DEBUG_KMS("Turn eDP power on\n");
1575
773538e8 1576 pps_lock(intel_dp);
e39b999a 1577
4be73780 1578 if (edp_have_panel_power(intel_dp)) {
99ea7127 1579 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1580 goto out;
99ea7127 1581 }
9934c132 1582
4be73780 1583 wait_panel_power_cycle(intel_dp);
37c6c9b0 1584
bf13e81b 1585 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1586 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1587 if (IS_GEN5(dev)) {
1588 /* ILK workaround: disable reset around power sequence */
1589 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1590 I915_WRITE(pp_ctrl_reg, pp);
1591 POSTING_READ(pp_ctrl_reg);
05ce1a49 1592 }
37c6c9b0 1593
1c0ae80a 1594 pp |= POWER_TARGET_ON;
99ea7127
KP		 1595 if (!IS_GEN5(dev))
1596 pp |= PANEL_POWER_RESET;
1597
453c5420
JB		 1598 I915_WRITE(pp_ctrl_reg, pp);
1599 POSTING_READ(pp_ctrl_reg);
9934c132 1600
4be73780 1601 wait_panel_on(intel_dp);
dce56b3c 1602 intel_dp->last_power_on = jiffies;
9934c132 1603
05ce1a49
KP		 1604 if (IS_GEN5(dev)) {
1605 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1606 I915_WRITE(pp_ctrl_reg, pp);
1607 POSTING_READ(pp_ctrl_reg);
05ce1a49 1608 }
e39b999a
VS		 1609
1610 out:
773538e8 1611 pps_unlock(intel_dp);
9934c132
JB		 1612}
1613
4be73780 1614void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1615{
4e6e1a54
ID		 1616 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1617 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1619 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1620 enum intel_display_power_domain power_domain;
99ea7127 1621 u32 pp;
453c5420 1622 u32 pp_ctrl_reg;
9934c132 1623
97af61f5
KP		 1624 if (!is_edp(intel_dp))
1625 return;
37c6c9b0 1626
99ea7127 1627 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1628
773538e8 1629 pps_lock(intel_dp);
e39b999a 1630
24f3e092
JN		 1631 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1632
453c5420 1633 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1634 /* We need to switch off panel power _and_ force vdd, for otherwise some
1635 * panels get very unhappy and cease to work. */
b3064154
PJ		 1636 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1637 EDP_BLC_ENABLE);
453c5420 1638
bf13e81b 1639 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1640
849e39f5
PZ		 1641 intel_dp->want_panel_vdd = false;
1642
453c5420
JB		 1643 I915_WRITE(pp_ctrl_reg, pp);
1644 POSTING_READ(pp_ctrl_reg);
9934c132 1645
dce56b3c 1646 intel_dp->last_power_cycle = jiffies;
4be73780 1647 wait_panel_off(intel_dp);
849e39f5
PZ		 1648
1649 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1650 power_domain = intel_display_port_power_domain(intel_encoder);
1651 intel_display_power_put(dev_priv, power_domain);
e39b999a 1652
773538e8 1653 pps_unlock(intel_dp);
9934c132
JB		 1654}
1655
1250d107
JN		 1656/* Enable backlight in the panel power control. */
1657static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1658{
da63a9f2
PZ		 1659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1660 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 u32 pp;
453c5420 1663 u32 pp_ctrl_reg;
32f9d658 1664
01cb9ea6
JB		 1665 /*
1666 * If we enable the backlight right away following a panel power
1667 * on, we may see slight flicker as the panel syncs with the eDP
1668 * link. So delay a bit to make sure the image is solid before
1669 * allowing it to appear.
1670 */
4be73780 1671 wait_backlight_on(intel_dp);
e39b999a 1672
773538e8 1673 pps_lock(intel_dp);
e39b999a 1674
453c5420 1675 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1676 pp |= EDP_BLC_ENABLE;
453c5420 1677
bf13e81b 1678 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1679
1680 I915_WRITE(pp_ctrl_reg, pp);
1681 POSTING_READ(pp_ctrl_reg);
e39b999a 1682
773538e8 1683 pps_unlock(intel_dp);
32f9d658
ZW		 1684}
1685
1250d107
JN		 1686/* Enable backlight PWM and backlight PP control. */
1687void intel_edp_backlight_on(struct intel_dp *intel_dp)
1688{
1689 if (!is_edp(intel_dp))
1690 return;
1691
1692 DRM_DEBUG_KMS("\n");
1693
1694 intel_panel_enable_backlight(intel_dp->attached_connector);
1695 _intel_edp_backlight_on(intel_dp);
1696}
1697
1698/* Disable backlight in the panel power control. */
1699static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1700{
30add22d 1701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703 u32 pp;
453c5420 1704 u32 pp_ctrl_reg;
32f9d658 1705
f01eca2e
KP		 1706 if (!is_edp(intel_dp))
1707 return;
1708
773538e8 1709 pps_lock(intel_dp);
e39b999a 1710
453c5420 1711 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1712 pp &= ~EDP_BLC_ENABLE;
453c5420 1713
bf13e81b 1714 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1715
1716 I915_WRITE(pp_ctrl_reg, pp);
1717 POSTING_READ(pp_ctrl_reg);
f7d2323c 1718
773538e8 1719 pps_unlock(intel_dp);
e39b999a
VS		 1720
1721 intel_dp->last_backlight_off = jiffies;
f7d2323c 1722 edp_wait_backlight_off(intel_dp);
1250d107 1723}
f7d2323c 1724
1250d107
JN		 1725/* Disable backlight PP control and backlight PWM. */
1726void intel_edp_backlight_off(struct intel_dp *intel_dp)
1727{
1728 if (!is_edp(intel_dp))
1729 return;
1730
1731 DRM_DEBUG_KMS("\n");
f7d2323c 1732
1250d107 1733 _intel_edp_backlight_off(intel_dp);
f7d2323c 1734 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1735}
a4fc5ed6 1736
73580fb7
JN		 1737/*
1738 * Hook for controlling the panel power control backlight through the bl_power
1739 * sysfs attribute. Take care to handle multiple calls.
1740 */
1741static void intel_edp_backlight_power(struct intel_connector *connector,
1742 bool enable)
1743{
1744 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1745 bool is_enabled;
1746
773538e8 1747 pps_lock(intel_dp);
e39b999a 1748 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1749 pps_unlock(intel_dp);
73580fb7
JN		 1750
1751 if (is_enabled == enable)
1752 return;
1753
23ba9373
JN		 1754 DRM_DEBUG_KMS("panel power control backlight %s\n",
1755 enable ? "enable" : "disable");
73580fb7
JN		 1756
1757 if (enable)
1758 _intel_edp_backlight_on(intel_dp);
1759 else
1760 _intel_edp_backlight_off(intel_dp);
1761}
1762
2bd2ad64 1763static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1764{
da63a9f2
PZ		 1765 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1766 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1767 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 u32 dpa_ctl;
1770
2bd2ad64
DV		 1771 assert_pipe_disabled(dev_priv,
1772 to_intel_crtc(crtc)->pipe);
1773
d240f20f
JB		 1774 DRM_DEBUG_KMS("\n");
1775 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1776 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1777 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1778
1779 /* We don't adjust intel_dp->DP while tearing down the link, to
1780 * facilitate link retraining (e.g. after hotplug). Hence clear all
1781 * enable bits here to ensure that we don't enable too much. */
1782 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1783 intel_dp->DP |= DP_PLL_ENABLE;
1784 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1785 POSTING_READ(DP_A);
1786 udelay(200);
d240f20f
JB		 1787}
1788
2bd2ad64 1789static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1790{
da63a9f2
PZ		 1791 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1792 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1793 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1794 struct drm_i915_private *dev_priv = dev->dev_private;
1795 u32 dpa_ctl;
1796
2bd2ad64
DV		 1797 assert_pipe_disabled(dev_priv,
1798 to_intel_crtc(crtc)->pipe);
1799
d240f20f 1800 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1801 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1802 "dp pll off, should be on\n");
1803 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1804
1805 /* We can't rely on the value tracked for the DP register in
1806 * intel_dp->DP because link_down must not change that (otherwise link
1807 * re-training will fail. */
298b0b39 1808 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1809 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1810 POSTING_READ(DP_A);
d240f20f
JB		 1811 udelay(200);
1812}
1813
c7ad3810 1814/* If the sink supports it, try to set the power state appropriately */
c19b0669 1815void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1816{
1817 int ret, i;
1818
1819 /* Should have a valid DPCD by this point */
1820 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1821 return;
1822
1823 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1824 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1825 DP_SET_POWER_D3);
c7ad3810
JB		 1826 } else {
1827 /*
1828 * When turning on, we need to retry for 1ms to give the sink
1829 * time to wake up.
1830 */
1831 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1832 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1833 DP_SET_POWER_D0);
c7ad3810
JB		 1834 if (ret == 1)
1835 break;
1836 msleep(1);
1837 }
1838 }
f9cac721
JN		 1839
1840 if (ret != 1)
1841 DRM_DEBUG_KMS("failed to %s sink power state\n",
1842 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1843}
1844
19d8fe15
DV		 1845static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1846 enum pipe *pipe)
d240f20f 1847{
19d8fe15 1848 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1849 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1850 struct drm_device *dev = encoder->base.dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1852 enum intel_display_power_domain power_domain;
1853 u32 tmp;
1854
1855 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1856 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1857 return false;
1858
1859 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1860
1861 if (!(tmp & DP_PORT_EN))
1862 return false;
1863
bc7d38a4 1864 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1865 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1866 } else if (IS_CHERRYVIEW(dev)) {
1867 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1869 *pipe = PORT_TO_PIPE(tmp);
1870 } else {
1871 u32 trans_sel;
1872 u32 trans_dp;
1873 int i;
1874
1875 switch (intel_dp->output_reg) {
1876 case PCH_DP_B:
1877 trans_sel = TRANS_DP_PORT_SEL_B;
1878 break;
1879 case PCH_DP_C:
1880 trans_sel = TRANS_DP_PORT_SEL_C;
1881 break;
1882 case PCH_DP_D:
1883 trans_sel = TRANS_DP_PORT_SEL_D;
1884 break;
1885 default:
1886 return true;
1887 }
1888
055e393f 1889 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1890 trans_dp = I915_READ(TRANS_DP_CTL(i));
1891 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1892 *pipe = i;
1893 return true;
1894 }
1895 }
19d8fe15 1896
4a0833ec
DV		 1897 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1898 intel_dp->output_reg);
1899 }
d240f20f 1900
19d8fe15
DV		 1901 return true;
1902}
d240f20f 1903
045ac3b5
JB		 1904static void intel_dp_get_config(struct intel_encoder *encoder,
1905 struct intel_crtc_config *pipe_config)
1906{
1907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1908 u32 tmp, flags = 0;
63000ef6
XZ		 1909 struct drm_device *dev = encoder->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 enum port port = dp_to_dig_port(intel_dp)->port;
1912 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1913 int dotclock;
045ac3b5 1914
9ed109a7
DV		 1915 tmp = I915_READ(intel_dp->output_reg);
1916 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1917 pipe_config->has_audio = true;
1918
63000ef6 1919 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1920 if (tmp & DP_SYNC_HS_HIGH)
1921 flags |= DRM_MODE_FLAG_PHSYNC;
1922 else
1923 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1924
63000ef6
XZ		 1925 if (tmp & DP_SYNC_VS_HIGH)
1926 flags |= DRM_MODE_FLAG_PVSYNC;
1927 else
1928 flags |= DRM_MODE_FLAG_NVSYNC;
1929 } else {
1930 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1931 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1932 flags |= DRM_MODE_FLAG_PHSYNC;
1933 else
1934 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1935
63000ef6
XZ		 1936 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1937 flags |= DRM_MODE_FLAG_PVSYNC;
1938 else
1939 flags |= DRM_MODE_FLAG_NVSYNC;
1940 }
045ac3b5
JB		 1941
1942 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1943
eb14cb74
VS		 1944 pipe_config->has_dp_encoder = true;
1945
1946 intel_dp_get_m_n(crtc, pipe_config);
1947
18442d08 1948 if (port == PORT_A) {
f1f644dc
JB		 1949 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1950 pipe_config->port_clock = 162000;
1951 else
1952 pipe_config->port_clock = 270000;
1953 }
18442d08
VS		 1954
1955 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1956 &pipe_config->dp_m_n);
1957
1958 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1959 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1960
241bfc38 1961 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1962
c6cd2ee2
JN		 1963 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1964 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1965 /*
1966 * This is a big fat ugly hack.
1967 *
1968 * Some machines in UEFI boot mode provide us a VBT that has 18
1969 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1970 * unknown we fail to light up. Yet the same BIOS boots up with
1971 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1972 * max, not what it tells us to use.
1973 *
1974 * Note: This will still be broken if the eDP panel is not lit
1975 * up by the BIOS, and thus we can't get the mode at module
1976 * load.
1977 */
1978 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1979 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1980 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1981 }
045ac3b5
JB		 1982}
1983
34eb7579 1984static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1985{
34eb7579 1986 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1987}
1988
2b28bb1b
RV		 1989static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1990{
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992
18b5992c 1993 if (!HAS_PSR(dev))
2b28bb1b
RV		 1994 return false;
1995
18b5992c 1996 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1997}
1998
1999static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2000 struct edp_vsc_psr *vsc_psr)
2001{
2002 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2003 struct drm_device *dev = dig_port->base.base.dev;
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2006 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2007 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2008 uint32_t *data = (uint32_t *) vsc_psr;
2009 unsigned int i;
2010
2011 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2012 the video DIP being updated before program video DIP data buffer
2013 registers for DIP being updated. */
2014 I915_WRITE(ctl_reg, 0);
2015 POSTING_READ(ctl_reg);
2016
2017 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2018 if (i < sizeof(struct edp_vsc_psr))
2019 I915_WRITE(data_reg + i, *data++);
2020 else
2021 I915_WRITE(data_reg + i, 0);
2022 }
2023
2024 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2025 POSTING_READ(ctl_reg);
2026}
2027
ba80f4d4 2028static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2029{
2b28bb1b
RV		 2030 struct edp_vsc_psr psr_vsc;
2031
2b28bb1b
RV		 2032 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2033 memset(&psr_vsc, 0, sizeof(psr_vsc));
2034 psr_vsc.sdp_header.HB0 = 0;
2035 psr_vsc.sdp_header.HB1 = 0x7;
2036 psr_vsc.sdp_header.HB2 = 0x2;
2037 psr_vsc.sdp_header.HB3 = 0x8;
2038 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2039}
2040
2041static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2042{
0e0ae652
RV		 2043 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2044 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2045 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2046 uint32_t aux_clock_divider;
2b28bb1b
RV		 2047 int precharge = 0x3;
2048 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2049 bool only_standby = false;
2b28bb1b 2050
ec5b01dd
DL		 2051 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2052
0e0ae652
RV		 2053 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2054 only_standby = true;
2055
2b28bb1b 2056 /* Enable PSR in sink */
0e0ae652 2057 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2058 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2059 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2060 else
9d1a1031
JN		 2061 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2062 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2063
2064 /* Setup AUX registers */
18b5992c
BW		 2065 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2066 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2067 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2068 DP_AUX_CH_CTL_TIME_OUT_400us |
2069 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2070 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2071 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2072}
2073
2074static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2075{
0e0ae652
RV		 2076 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2077 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 uint32_t max_sleep_time = 0x1f;
2080 uint32_t idle_frames = 1;
2081 uint32_t val = 0x0;
ed8546ac 2082 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2083 bool only_standby = false;
2084
2085 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2086 only_standby = true;
2b28bb1b 2087
0e0ae652 2088 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2089 val |= EDP_PSR_LINK_STANDBY;
2090 val |= EDP_PSR_TP2_TP3_TIME_0us;
2091 val |= EDP_PSR_TP1_TIME_0us;
2092 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2093 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2094 } else
2095 val |= EDP_PSR_LINK_DISABLE;
2096
18b5992c 2097 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2098 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2099 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2100 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2101 EDP_PSR_ENABLE);
2102}
2103
3f51e471
RV		 2104static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2105{
2106 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2107 struct drm_device *dev = dig_port->base.base.dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 struct drm_crtc *crtc = dig_port->base.base.crtc;
2110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2111
f0355c4a 2112 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2113 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2114 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2115
a031d709
RV		 2116 dev_priv->psr.source_ok = false;
2117
9ca15301 2118 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2119 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2120 return false;
2121 }
2122
d330a953 2123 if (!i915.enable_psr) {
105b7c11 2124 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2125 return false;
2126 }
2127
4c8c7000
RV		 2128 /* Below limitations aren't valid for Broadwell */
2129 if (IS_BROADWELL(dev))
2130 goto out;
2131
3f51e471
RV		 2132 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2133 S3D_ENABLE) {
2134 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2135 return false;
2136 }
2137
ca73b4f0 2138 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2139 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2140 return false;
2141 }
2142
4c8c7000 2143 out:
a031d709 2144 dev_priv->psr.source_ok = true;
3f51e471
RV		 2145 return true;
2146}
2147
3d739d92 2148static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2149{
7c8f8a70
RV		 2150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2151 struct drm_device *dev = intel_dig_port->base.base.dev;
2152 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2153
3638379c
DV		 2154 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2155 WARN_ON(dev_priv->psr.active);
f0355c4a 2156 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2157
7ca5a41f 2158 /* Enable/Re-enable PSR on the host */
2b28bb1b 2159 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2160
7c8f8a70 2161 dev_priv->psr.active = true;
2b28bb1b
RV		 2162}
2163
3d739d92
RV		 2164void intel_edp_psr_enable(struct intel_dp *intel_dp)
2165{
2166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2167 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2168
4704c573
RV		 2169 if (!HAS_PSR(dev)) {
2170 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2171 return;
2172 }
2173
34eb7579
RV		 2174 if (!is_edp_psr(intel_dp)) {
2175 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2176 return;
2177 }
2178
f0355c4a 2179 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2180 if (dev_priv->psr.enabled) {
2181 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2182 goto unlock;
109fc2ad
DV		 2183 }
2184
0aa48783
RV		 2185 if (!intel_edp_psr_match_conditions(intel_dp))
2186 goto unlock;
2187
9ca15301
DV		 2188 dev_priv->psr.busy_frontbuffer_bits = 0;
2189
ba80f4d4
RV		 2190 intel_edp_psr_setup_vsc(intel_dp);
2191
2192 /* Avoid continuous PSR exit by masking memup and hpd */
2193 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2194 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2195
7ca5a41f
RV		 2196 /* Enable PSR on the panel */
2197 intel_edp_psr_enable_sink(intel_dp);
2198
0aa48783
RV		 2199 dev_priv->psr.enabled = intel_dp;
2200unlock:
f0355c4a 2201 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2202}
2203
2b28bb1b
RV		 2204void intel_edp_psr_disable(struct intel_dp *intel_dp)
2205{
2206 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208
f0355c4a
DV		 2209 mutex_lock(&dev_priv->psr.lock);
2210 if (!dev_priv->psr.enabled) {
2211 mutex_unlock(&dev_priv->psr.lock);
2212 return;
2213 }
2214
3638379c
DV		 2215 if (dev_priv->psr.active) {
2216 I915_WRITE(EDP_PSR_CTL(dev),
2217 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2218
2219 /* Wait till PSR is idle */
2220 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2221 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2222 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2223
3638379c
DV		 2224 dev_priv->psr.active = false;
2225 } else {
2226 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2227 }
7c8f8a70 2228
2807cf69 2229 dev_priv->psr.enabled = NULL;
f0355c4a 2230 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2231
2232 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2233}
2234
f02a326e 2235static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2236{
2237 struct drm_i915_private *dev_priv =
2238 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2239 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2240
8d7f4fe9
RV		 2241 /* We have to make sure PSR is ready for re-enable
2242 * otherwise it keeps disabled until next full enable/disable cycle.
2243 * PSR might take some time to get fully disabled
2244 * and be ready for re-enable.
2245 */
2246 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2247 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2248 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2249 return;
2250 }
2251
f0355c4a
DV		 2252 mutex_lock(&dev_priv->psr.lock);
2253 intel_dp = dev_priv->psr.enabled;
2254
2807cf69 2255 if (!intel_dp)
f0355c4a 2256 goto unlock;
2807cf69 2257
9ca15301
DV		 2258 /*
2259 * The delayed work can race with an invalidate hence we need to
2260 * recheck. Since psr_flush first clears this and then reschedules we
2261 * won't ever miss a flush when bailing out here.
2262 */
2263 if (dev_priv->psr.busy_frontbuffer_bits)
2264 goto unlock;
2265
2266 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2267unlock:
2268 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2269}
2270
9ca15301 2271static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2272{
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274
3638379c
DV		 2275 if (dev_priv->psr.active) {
2276 u32 val = I915_READ(EDP_PSR_CTL(dev));
2277
2278 WARN_ON(!(val & EDP_PSR_ENABLE));
2279
2280 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2281
2282 dev_priv->psr.active = false;
2283 }
7c8f8a70 2284
9ca15301
DV		 2285}
2286
2287void intel_edp_psr_invalidate(struct drm_device *dev,
2288 unsigned frontbuffer_bits)
2289{
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct drm_crtc *crtc;
2292 enum pipe pipe;
2293
9ca15301
DV		 2294 mutex_lock(&dev_priv->psr.lock);
2295 if (!dev_priv->psr.enabled) {
2296 mutex_unlock(&dev_priv->psr.lock);
2297 return;
2298 }
2299
2300 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2301 pipe = to_intel_crtc(crtc)->pipe;
2302
2303 intel_edp_psr_do_exit(dev);
2304
2305 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2306
2307 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2308 mutex_unlock(&dev_priv->psr.lock);
2309}
2310
2311void intel_edp_psr_flush(struct drm_device *dev,
2312 unsigned frontbuffer_bits)
2313{
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct drm_crtc *crtc;
2316 enum pipe pipe;
2317
9ca15301
DV		 2318 mutex_lock(&dev_priv->psr.lock);
2319 if (!dev_priv->psr.enabled) {
2320 mutex_unlock(&dev_priv->psr.lock);
2321 return;
2322 }
2323
2324 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2325 pipe = to_intel_crtc(crtc)->pipe;
2326 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2327
2328 /*
2329 * On Haswell sprite plane updates don't result in a psr invalidating
2330 * signal in the hardware. Which means we need to manually fake this in
2331 * software for all flushes, not just when we've seen a preceding
2332 * invalidation through frontbuffer rendering.
2333 */
2334 if (IS_HASWELL(dev) &&
2335 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2336 intel_edp_psr_do_exit(dev);
2337
2338 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2339 schedule_delayed_work(&dev_priv->psr.work,
2340 msecs_to_jiffies(100));
f0355c4a 2341 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2342}
2343
2344void intel_edp_psr_init(struct drm_device *dev)
2345{
2346 struct drm_i915_private *dev_priv = dev->dev_private;
2347
7c8f8a70 2348 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2349 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2350}
2351
e8cb4558 2352static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2353{
e8cb4558 2354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2355 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2356
2357 /* Make sure the panel is off before trying to change the mode. But also
2358 * ensure that we have vdd while we switch off the panel. */
24f3e092 2359 intel_edp_panel_vdd_on(intel_dp);
4be73780 2360 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2361 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2362 intel_edp_panel_off(intel_dp);
3739850b 2363
08aff3fe
VS		 2364 /* disable the port before the pipe on g4x */
2365 if (INTEL_INFO(dev)->gen < 5)
3739850b 2366 intel_dp_link_down(intel_dp);
d240f20f
JB		 2367}
2368
08aff3fe 2369static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2370{
2bd2ad64 2371 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2372 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2373
49277c31 2374 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2375 if (port == PORT_A)
2376 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2377}
2378
2379static void vlv_post_disable_dp(struct intel_encoder *encoder)
2380{
2381 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2382
2383 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2384}
2385
580d3811
VS		 2386static void chv_post_disable_dp(struct intel_encoder *encoder)
2387{
2388 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2389 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2390 struct drm_device *dev = encoder->base.dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc =
2393 to_intel_crtc(encoder->base.crtc);
2394 enum dpio_channel ch = vlv_dport_to_channel(dport);
2395 enum pipe pipe = intel_crtc->pipe;
2396 u32 val;
2397
2398 intel_dp_link_down(intel_dp);
2399
2400 mutex_lock(&dev_priv->dpio_lock);
2401
2402 /* Propagate soft reset to data lane reset */
97fd4d5c 2403 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2404 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2405 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2406
97fd4d5c
VS		 2407 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2408 val |= CHV_PCS_REQ_SOFTRESET_EN;
2409 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2410
2411 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2412 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2413 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2414
2415 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2416 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2417 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2418
2419 mutex_unlock(&dev_priv->dpio_lock);
2420}
2421
7b13b58a
VS		 2422static void
2423_intel_dp_set_link_train(struct intel_dp *intel_dp,
2424 uint32_t *DP,
2425 uint8_t dp_train_pat)
2426{
2427 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2428 struct drm_device *dev = intel_dig_port->base.base.dev;
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 enum port port = intel_dig_port->port;
2431
2432 if (HAS_DDI(dev)) {
2433 uint32_t temp = I915_READ(DP_TP_CTL(port));
2434
2435 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2436 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2437 else
2438 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2439
2440 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2441 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2442 case DP_TRAINING_PATTERN_DISABLE:
2443 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2444
2445 break;
2446 case DP_TRAINING_PATTERN_1:
2447 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2448 break;
2449 case DP_TRAINING_PATTERN_2:
2450 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2451 break;
2452 case DP_TRAINING_PATTERN_3:
2453 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2454 break;
2455 }
2456 I915_WRITE(DP_TP_CTL(port), temp);
2457
2458 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2459 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2460
2461 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2462 case DP_TRAINING_PATTERN_DISABLE:
2463 *DP |= DP_LINK_TRAIN_OFF_CPT;
2464 break;
2465 case DP_TRAINING_PATTERN_1:
2466 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2467 break;
2468 case DP_TRAINING_PATTERN_2:
2469 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2470 break;
2471 case DP_TRAINING_PATTERN_3:
2472 DRM_ERROR("DP training pattern 3 not supported\n");
2473 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2474 break;
2475 }
2476
2477 } else {
2478 if (IS_CHERRYVIEW(dev))
2479 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2480 else
2481 *DP &= ~DP_LINK_TRAIN_MASK;
2482
2483 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2484 case DP_TRAINING_PATTERN_DISABLE:
2485 *DP |= DP_LINK_TRAIN_OFF;
2486 break;
2487 case DP_TRAINING_PATTERN_1:
2488 *DP |= DP_LINK_TRAIN_PAT_1;
2489 break;
2490 case DP_TRAINING_PATTERN_2:
2491 *DP |= DP_LINK_TRAIN_PAT_2;
2492 break;
2493 case DP_TRAINING_PATTERN_3:
2494 if (IS_CHERRYVIEW(dev)) {
2495 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2496 } else {
2497 DRM_ERROR("DP training pattern 3 not supported\n");
2498 *DP |= DP_LINK_TRAIN_PAT_2;
2499 }
2500 break;
2501 }
2502 }
2503}
2504
2505static void intel_dp_enable_port(struct intel_dp *intel_dp)
2506{
2507 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509
2510 intel_dp->DP |= DP_PORT_EN;
2511
2512 /* enable with pattern 1 (as per spec) */
2513 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2514 DP_TRAINING_PATTERN_1);
2515
2516 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2517 POSTING_READ(intel_dp->output_reg);
2518}
2519
e8cb4558 2520static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2521{
e8cb4558
DV		 2522 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2523 struct drm_device *dev = encoder->base.dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2526
0c33d8d7
DV		 2527 if (WARN_ON(dp_reg & DP_PORT_EN))
2528 return;
5d613501 2529
7b13b58a 2530 intel_dp_enable_port(intel_dp);
24f3e092 2531 intel_edp_panel_vdd_on(intel_dp);
4be73780 2532 intel_edp_panel_on(intel_dp);
1e0560e0 2533 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2534 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2535 intel_dp_start_link_train(intel_dp);
33a34e4e 2536 intel_dp_complete_link_train(intel_dp);
3ab9c637 2537 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2538}
89b667f8 2539
ecff4f3b
JN		 2540static void g4x_enable_dp(struct intel_encoder *encoder)
2541{
828f5c6e
JN		 2542 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2543
ecff4f3b 2544 intel_enable_dp(encoder);
4be73780 2545 intel_edp_backlight_on(intel_dp);
ab1f90f9 2546}
89b667f8 2547
ab1f90f9
JN		 2548static void vlv_enable_dp(struct intel_encoder *encoder)
2549{
828f5c6e
JN		 2550 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2551
4be73780 2552 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2553}
2554
ecff4f3b 2555static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2556{
2557 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2558 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2559
8ac33ed3
DV		 2560 intel_dp_prepare(encoder);
2561
d41f1efb
DV		 2562 /* Only ilk+ has port A */
2563 if (dport->port == PORT_A) {
2564 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2565 ironlake_edp_pll_on(intel_dp);
d41f1efb 2566 }
ab1f90f9
JN		 2567}
2568
a4a5d2f8
VS		 2569static void vlv_steal_power_sequencer(struct drm_device *dev,
2570 enum pipe pipe)
2571{
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573 struct intel_encoder *encoder;
2574
2575 lockdep_assert_held(&dev_priv->pps_mutex);
2576
2577 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2578 base.head) {
2579 struct intel_dp *intel_dp;
773538e8 2580 enum port port;
a4a5d2f8
VS		 2581
2582 if (encoder->type != INTEL_OUTPUT_EDP)
2583 continue;
2584
2585 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2586 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2587
2588 if (intel_dp->pps_pipe != pipe)
2589 continue;
2590
2591 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2592 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2593
2594 /* make sure vdd is off before we steal it */
2595 edp_panel_vdd_off_sync(intel_dp);
2596
2597 intel_dp->pps_pipe = INVALID_PIPE;
2598 }
2599}
2600
2601static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2602{
2603 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2604 struct intel_encoder *encoder = &intel_dig_port->base;
2605 struct drm_device *dev = encoder->base.dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2608 struct edp_power_seq power_seq;
2609
2610 lockdep_assert_held(&dev_priv->pps_mutex);
2611
2612 if (intel_dp->pps_pipe == crtc->pipe)
2613 return;
2614
2615 /*
2616 * If another power sequencer was being used on this
2617 * port previously make sure to turn off vdd there while
2618 * we still have control of it.
2619 */
2620 if (intel_dp->pps_pipe != INVALID_PIPE)
2621 edp_panel_vdd_off_sync(intel_dp);
2622
2623 /*
2624 * We may be stealing the power
2625 * sequencer from another port.
2626 */
2627 vlv_steal_power_sequencer(dev, crtc->pipe);
2628
2629 /* now it's all ours */
2630 intel_dp->pps_pipe = crtc->pipe;
2631
2632 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2633 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2634
2635 /* init power sequencer on this pipe and port */
2636 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2637 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2638 &power_seq);
2639}
2640
ab1f90f9 2641static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2642{
2bd2ad64 2643 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2644 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2645 struct drm_device *dev = encoder->base.dev;
89b667f8 2646 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2647 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2648 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2649 int pipe = intel_crtc->pipe;
2650 u32 val;
a4fc5ed6 2651
ab1f90f9 2652 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2653
ab3c759a 2654 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2655 val = 0;
2656 if (pipe)
2657 val |= (1<<21);
2658 else
2659 val &= ~(1<<21);
2660 val |= 0x001000c4;
ab3c759a
CML		 2661 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2662 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2663 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2664
ab1f90f9
JN		 2665 mutex_unlock(&dev_priv->dpio_lock);
2666
2cac613b 2667 if (is_edp(intel_dp)) {
773538e8 2668 pps_lock(intel_dp);
a4a5d2f8 2669 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2670 pps_unlock(intel_dp);
2cac613b 2671 }
bf13e81b 2672
ab1f90f9
JN		 2673 intel_enable_dp(encoder);
2674
e4607fcf 2675 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2676}
2677
ecff4f3b 2678static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2679{
2680 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2681 struct drm_device *dev = encoder->base.dev;
2682 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2683 struct intel_crtc *intel_crtc =
2684 to_intel_crtc(encoder->base.crtc);
e4607fcf 2685 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2686 int pipe = intel_crtc->pipe;
89b667f8 2687
8ac33ed3
DV		 2688 intel_dp_prepare(encoder);
2689
89b667f8 2690 /* Program Tx lane resets to default */
0980a60f 2691 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2692 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2693 DPIO_PCS_TX_LANE2_RESET |
2694 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2695 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2696 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2697 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2698 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2699 DPIO_PCS_CLK_SOFT_RESET);
2700
2701 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2702 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2703 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2704 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2705 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2706}
2707
e4a1d846
CML		 2708static void chv_pre_enable_dp(struct intel_encoder *encoder)
2709{
2710 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2711 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2712 struct drm_device *dev = encoder->base.dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2714 struct intel_crtc *intel_crtc =
2715 to_intel_crtc(encoder->base.crtc);
2716 enum dpio_channel ch = vlv_dport_to_channel(dport);
2717 int pipe = intel_crtc->pipe;
2718 int data, i;
949c1d43 2719 u32 val;
e4a1d846 2720
e4a1d846 2721 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2722
2723 /* Deassert soft data lane reset*/
97fd4d5c 2724 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2725 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2726 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2727
2728 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2729 val |= CHV_PCS_REQ_SOFTRESET_EN;
2730 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2731
2732 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2733 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2734 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2735
97fd4d5c 2736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2737 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2738 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2739
2740 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2741 for (i = 0; i < 4; i++) {
2742 /* Set the latency optimal bit */
2743 data = (i == 1) ? 0x0 : 0x6;
2744 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2745 data << DPIO_FRC_LATENCY_SHFIT);
2746
2747 /* Set the upar bit */
2748 data = (i == 1) ? 0x0 : 0x1;
2749 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2750 data << DPIO_UPAR_SHIFT);
2751 }
2752
2753 /* Data lane stagger programming */
2754 /* FIXME: Fix up value only after power analysis */
2755
2756 mutex_unlock(&dev_priv->dpio_lock);
2757
2758 if (is_edp(intel_dp)) {
773538e8 2759 pps_lock(intel_dp);
a4a5d2f8 2760 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2761 pps_unlock(intel_dp);
e4a1d846
CML		 2762 }
2763
2764 intel_enable_dp(encoder);
2765
2766 vlv_wait_port_ready(dev_priv, dport);
2767}
2768
9197c88b
VS		 2769static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2770{
2771 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2772 struct drm_device *dev = encoder->base.dev;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct intel_crtc *intel_crtc =
2775 to_intel_crtc(encoder->base.crtc);
2776 enum dpio_channel ch = vlv_dport_to_channel(dport);
2777 enum pipe pipe = intel_crtc->pipe;
2778 u32 val;
2779
625695f8
VS		 2780 intel_dp_prepare(encoder);
2781
9197c88b
VS		 2782 mutex_lock(&dev_priv->dpio_lock);
2783
b9e5ac3c
VS		 2784 /* program left/right clock distribution */
2785 if (pipe != PIPE_B) {
2786 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2787 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2788 if (ch == DPIO_CH0)
2789 val |= CHV_BUFLEFTENA1_FORCE;
2790 if (ch == DPIO_CH1)
2791 val |= CHV_BUFRIGHTENA1_FORCE;
2792 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2793 } else {
2794 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2795 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2796 if (ch == DPIO_CH0)
2797 val |= CHV_BUFLEFTENA2_FORCE;
2798 if (ch == DPIO_CH1)
2799 val |= CHV_BUFRIGHTENA2_FORCE;
2800 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2801 }
2802
9197c88b
VS		 2803 /* program clock channel usage */
2804 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2805 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2806 if (pipe != PIPE_B)
2807 val &= ~CHV_PCS_USEDCLKCHANNEL;
2808 else
2809 val |= CHV_PCS_USEDCLKCHANNEL;
2810 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2811
2812 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2813 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2814 if (pipe != PIPE_B)
2815 val &= ~CHV_PCS_USEDCLKCHANNEL;
2816 else
2817 val |= CHV_PCS_USEDCLKCHANNEL;
2818 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2819
2820 /*
2821 * This a a bit weird since generally CL
2822 * matches the pipe, but here we need to
2823 * pick the CL based on the port.
2824 */
2825 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2826 if (pipe != PIPE_B)
2827 val &= ~CHV_CMN_USEDCLKCHANNEL;
2828 else
2829 val |= CHV_CMN_USEDCLKCHANNEL;
2830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2831
2832 mutex_unlock(&dev_priv->dpio_lock);
2833}
2834
a4fc5ed6 2835/*
df0c237d
JB		 2836 * Native read with retry for link status and receiver capability reads for
2837 * cases where the sink may still be asleep.
9d1a1031
JN		 2838 *
2839 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2840 * supposed to retry 3 times per the spec.
a4fc5ed6 2841 */
9d1a1031
JN		 2842static ssize_t
2843intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2844 void *buffer, size_t size)
a4fc5ed6 2845{
9d1a1031
JN		 2846 ssize_t ret;
2847 int i;
61da5fab 2848
61da5fab 2849 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2850 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2851 if (ret == size)
2852 return ret;
61da5fab
JB		 2853 msleep(1);
2854 }
a4fc5ed6 2855
9d1a1031 2856 return ret;
a4fc5ed6
KP		 2857}
2858
2859/*
2860 * Fetch AUX CH registers 0x202 - 0x207 which contain
2861 * link status information
2862 */
2863static bool
93f62dad 2864intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2865{
9d1a1031
JN		 2866 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2867 DP_LANE0_1_STATUS,
2868 link_status,
2869 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2870}
2871
1100244e 2872/* These are source-specific values. */
a4fc5ed6 2873static uint8_t
1a2eb460 2874intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2875{
30add22d 2876 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2877 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2878
5a9d1f1a
DL		 2879 if (INTEL_INFO(dev)->gen >= 9)
2880 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2881 else if (IS_VALLEYVIEW(dev))
bd60018a 2882 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2883 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2884 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2885 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2886 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2887 else
bd60018a 2888 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2889}
2890
2891static uint8_t
2892intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2893{
30add22d 2894 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2895 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2896
5a9d1f1a
DL		 2897 if (INTEL_INFO(dev)->gen >= 9) {
2898 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2900 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2902 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2903 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2904 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2905 default:
2906 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2907 }
2908 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2909 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2911 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2913 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2915 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2917 default:
bd60018a 2918 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2919 }
e2fa6fba
P		 2920 } else if (IS_VALLEYVIEW(dev)) {
2921 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2923 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2925 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2927 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2929 default:
bd60018a 2930 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2931 }
bc7d38a4 2932 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2933 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2935 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2939 default:
bd60018a 2940 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2941 }
2942 } else {
2943 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2945 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2951 default:
bd60018a 2952 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2953 }
a4fc5ed6
KP		 2954 }
2955}
2956
e2fa6fba
P		 2957static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2958{
2959 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2962 struct intel_crtc *intel_crtc =
2963 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2964 unsigned long demph_reg_value, preemph_reg_value,
2965 uniqtranscale_reg_value;
2966 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2967 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2968 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2969
2970 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2971 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2972 preemph_reg_value = 0x0004000;
2973 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2975 demph_reg_value = 0x2B405555;
2976 uniqtranscale_reg_value = 0x552AB83A;
2977 break;
bd60018a 2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2979 demph_reg_value = 0x2B404040;
2980 uniqtranscale_reg_value = 0x5548B83A;
2981 break;
bd60018a 2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2983 demph_reg_value = 0x2B245555;
2984 uniqtranscale_reg_value = 0x5560B83A;
2985 break;
bd60018a 2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2987 demph_reg_value = 0x2B405555;
2988 uniqtranscale_reg_value = 0x5598DA3A;
2989 break;
2990 default:
2991 return 0;
2992 }
2993 break;
bd60018a 2994 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2995 preemph_reg_value = 0x0002000;
2996 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2998 demph_reg_value = 0x2B404040;
2999 uniqtranscale_reg_value = 0x5552B83A;
3000 break;
bd60018a 3001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3002 demph_reg_value = 0x2B404848;
3003 uniqtranscale_reg_value = 0x5580B83A;
3004 break;
bd60018a 3005 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3006 demph_reg_value = 0x2B404040;
3007 uniqtranscale_reg_value = 0x55ADDA3A;
3008 break;
3009 default:
3010 return 0;
3011 }
3012 break;
bd60018a 3013 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3014 preemph_reg_value = 0x0000000;
3015 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3017 demph_reg_value = 0x2B305555;
3018 uniqtranscale_reg_value = 0x5570B83A;
3019 break;
bd60018a 3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3021 demph_reg_value = 0x2B2B4040;
3022 uniqtranscale_reg_value = 0x55ADDA3A;
3023 break;
3024 default:
3025 return 0;
3026 }
3027 break;
bd60018a 3028 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3029 preemph_reg_value = 0x0006000;
3030 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3032 demph_reg_value = 0x1B405555;
3033 uniqtranscale_reg_value = 0x55ADDA3A;
3034 break;
3035 default:
3036 return 0;
3037 }
3038 break;
3039 default:
3040 return 0;
3041 }
3042
0980a60f 3043 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3044 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3045 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3046 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3047 uniqtranscale_reg_value);
ab3c759a
CML		 3048 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3049 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3050 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3051 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3052 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3053
3054 return 0;
3055}
3056
e4a1d846
CML		 3057static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3058{
3059 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3060 struct drm_i915_private *dev_priv = dev->dev_private;
3061 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3062 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3063 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3064 uint8_t train_set = intel_dp->train_set[0];
3065 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3066 enum pipe pipe = intel_crtc->pipe;
3067 int i;
e4a1d846
CML		 3068
3069 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3070 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3071 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3073 deemph_reg_value = 128;
3074 margin_reg_value = 52;
3075 break;
bd60018a 3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3077 deemph_reg_value = 128;
3078 margin_reg_value = 77;
3079 break;
bd60018a 3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3081 deemph_reg_value = 128;
3082 margin_reg_value = 102;
3083 break;
bd60018a 3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3085 deemph_reg_value = 128;
3086 margin_reg_value = 154;
3087 /* FIXME extra to set for 1200 */
3088 break;
3089 default:
3090 return 0;
3091 }
3092 break;
bd60018a 3093 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3094 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3096 deemph_reg_value = 85;
3097 margin_reg_value = 78;
3098 break;
bd60018a 3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3100 deemph_reg_value = 85;
3101 margin_reg_value = 116;
3102 break;
bd60018a 3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3104 deemph_reg_value = 85;
3105 margin_reg_value = 154;
3106 break;
3107 default:
3108 return 0;
3109 }
3110 break;
bd60018a 3111 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3112 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3114 deemph_reg_value = 64;
3115 margin_reg_value = 104;
3116 break;
bd60018a 3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3118 deemph_reg_value = 64;
3119 margin_reg_value = 154;
3120 break;
3121 default:
3122 return 0;
3123 }
3124 break;
bd60018a 3125 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3126 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3128 deemph_reg_value = 43;
3129 margin_reg_value = 154;
3130 break;
3131 default:
3132 return 0;
3133 }
3134 break;
3135 default:
3136 return 0;
3137 }
3138
3139 mutex_lock(&dev_priv->dpio_lock);
3140
3141 /* Clear calc init */
1966e59e
VS		 3142 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3143 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3144 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3145
3146 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3147 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3148 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3149
3150 /* Program swing deemph */
f72df8db
VS		 3151 for (i = 0; i < 4; i++) {
3152 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3153 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3154 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3155 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3156 }
e4a1d846
CML		 3157
3158 /* Program swing margin */
f72df8db
VS		 3159 for (i = 0; i < 4; i++) {
3160 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3161 val &= ~DPIO_SWING_MARGIN000_MASK;
3162 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3163 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3164 }
e4a1d846
CML		 3165
3166 /* Disable unique transition scale */
f72df8db
VS		 3167 for (i = 0; i < 4; i++) {
3168 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3169 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3170 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3171 }
e4a1d846
CML		 3172
3173 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3174 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3175 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3176 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3177
3178 /*
3179 * The document said it needs to set bit 27 for ch0 and bit 26
3180 * for ch1. Might be a typo in the doc.
3181 * For now, for this unique transition scale selection, set bit
3182 * 27 for ch0 and ch1.
3183 */
f72df8db
VS		 3184 for (i = 0; i < 4; i++) {
3185 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3186 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3187 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3188 }
e4a1d846 3189
f72df8db
VS		 3190 for (i = 0; i < 4; i++) {
3191 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3192 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3193 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3194 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3195 }
e4a1d846
CML		 3196 }
3197
3198 /* Start swing calculation */
1966e59e
VS		 3199 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3200 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3201 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3202
3203 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3204 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3205 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3206
3207 /* LRC Bypass */
3208 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3209 val |= DPIO_LRC_BYPASS;
3210 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3211
3212 mutex_unlock(&dev_priv->dpio_lock);
3213
3214 return 0;
3215}
3216
a4fc5ed6 3217static void
0301b3ac
JN		 3218intel_get_adjust_train(struct intel_dp *intel_dp,
3219 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3220{
3221 uint8_t v = 0;
3222 uint8_t p = 0;
3223 int lane;
1a2eb460
KP		 3224 uint8_t voltage_max;
3225 uint8_t preemph_max;
a4fc5ed6 3226
33a34e4e 3227 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3228 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3229 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3230
3231 if (this_v > v)
3232 v = this_v;
3233 if (this_p > p)
3234 p = this_p;
3235 }
3236
1a2eb460 3237 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3238 if (v >= voltage_max)
3239 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3240
1a2eb460
KP		 3241 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3242 if (p >= preemph_max)
3243 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3244
3245 for (lane = 0; lane < 4; lane++)
33a34e4e 3246 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3247}
3248
3249static uint32_t
f0a3424e 3250intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3251{
3cf2efb1 3252 uint32_t signal_levels = 0;
a4fc5ed6 3253
3cf2efb1 3254 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3256 default:
3257 signal_levels |= DP_VOLTAGE_0_4;
3258 break;
bd60018a 3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3260 signal_levels |= DP_VOLTAGE_0_6;
3261 break;
bd60018a 3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3263 signal_levels |= DP_VOLTAGE_0_8;
3264 break;
bd60018a 3265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3266 signal_levels |= DP_VOLTAGE_1_2;
3267 break;
3268 }
3cf2efb1 3269 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3270 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3271 default:
3272 signal_levels |= DP_PRE_EMPHASIS_0;
3273 break;
bd60018a 3274 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3275 signal_levels |= DP_PRE_EMPHASIS_3_5;
3276 break;
bd60018a 3277 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3278 signal_levels |= DP_PRE_EMPHASIS_6;
3279 break;
bd60018a 3280 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3281 signal_levels |= DP_PRE_EMPHASIS_9_5;
3282 break;
3283 }
3284 return signal_levels;
3285}
3286
e3421a18
ZW		 3287/* Gen6's DP voltage swing and pre-emphasis control */
3288static uint32_t
3289intel_gen6_edp_signal_levels(uint8_t train_set)
3290{
3c5a62b5
YL		 3291 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3292 DP_TRAIN_PRE_EMPHASIS_MASK);
3293 switch (signal_levels) {
bd60018a
SJ		 3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3296 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3298 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3301 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3304 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3307 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3308 default:
3c5a62b5
YL		 3309 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3310 "0x%x\n", signal_levels);
3311 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3312 }
3313}
3314
1a2eb460
KP		 3315/* Gen7's DP voltage swing and pre-emphasis control */
3316static uint32_t
3317intel_gen7_edp_signal_levels(uint8_t train_set)
3318{
3319 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3320 DP_TRAIN_PRE_EMPHASIS_MASK);
3321 switch (signal_levels) {
bd60018a 3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3323 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3325 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3327 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3328
bd60018a 3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3330 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3332 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3333
bd60018a 3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3335 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3337 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3338
3339 default:
3340 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3341 "0x%x\n", signal_levels);
3342 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3343 }
3344}
3345
d6c0d722
PZ		 3346/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3347static uint32_t
f0a3424e 3348intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3349{
d6c0d722
PZ		 3350 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3351 DP_TRAIN_PRE_EMPHASIS_MASK);
3352 switch (signal_levels) {
bd60018a 3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3354 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3355 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3356 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3358 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3360 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3361
bd60018a 3362 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3363 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3365 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3367 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3368
bd60018a 3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3370 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3372 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3373 default:
3374 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3375 "0x%x\n", signal_levels);
c5fe6a06 3376 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3377 }
a4fc5ed6
KP		 3378}
3379
f0a3424e
PZ		 3380/* Properly updates "DP" with the correct signal levels. */
3381static void
3382intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3383{
3384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3385 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3386 struct drm_device *dev = intel_dig_port->base.base.dev;
3387 uint32_t signal_levels, mask;
3388 uint8_t train_set = intel_dp->train_set[0];
3389
5a9d1f1a 3390 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3391 signal_levels = intel_hsw_signal_levels(train_set);
3392 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3393 } else if (IS_CHERRYVIEW(dev)) {
3394 signal_levels = intel_chv_signal_levels(intel_dp);
3395 mask = 0;
e2fa6fba
P		 3396 } else if (IS_VALLEYVIEW(dev)) {
3397 signal_levels = intel_vlv_signal_levels(intel_dp);
3398 mask = 0;
bc7d38a4 3399 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3400 signal_levels = intel_gen7_edp_signal_levels(train_set);
3401 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3402 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3403 signal_levels = intel_gen6_edp_signal_levels(train_set);
3404 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3405 } else {
3406 signal_levels = intel_gen4_signal_levels(train_set);
3407 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3408 }
3409
3410 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3411
3412 *DP = (*DP & ~mask) | signal_levels;
3413}
3414
a4fc5ed6 3415static bool
ea5b213a 3416intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3417 uint32_t *DP,
58e10eb9 3418 uint8_t dp_train_pat)
a4fc5ed6 3419{
174edf1f
PZ		 3420 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3421 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3422 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3423 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3424 int ret, len;
a4fc5ed6 3425
7b13b58a 3426 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3427
70aff66c 3428 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3429 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3430
2cdfe6c8
JN		 3431 buf[0] = dp_train_pat;
3432 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3433 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3434 /* don't write DP_TRAINING_LANEx_SET on disable */
3435 len = 1;
3436 } else {
3437 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3438 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3439 len = intel_dp->lane_count + 1;
47ea7542 3440 }
a4fc5ed6 3441
9d1a1031
JN		 3442 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3443 buf, len);
2cdfe6c8
JN		 3444
3445 return ret == len;
a4fc5ed6
KP		 3446}
3447
70aff66c
JN		 3448static bool
3449intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3450 uint8_t dp_train_pat)
3451{
953d22e8 3452 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3453 intel_dp_set_signal_levels(intel_dp, DP);
3454 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3455}
3456
3457static bool
3458intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3459 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3460{
3461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3462 struct drm_device *dev = intel_dig_port->base.base.dev;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 int ret;
3465
3466 intel_get_adjust_train(intel_dp, link_status);
3467 intel_dp_set_signal_levels(intel_dp, DP);
3468
3469 I915_WRITE(intel_dp->output_reg, *DP);
3470 POSTING_READ(intel_dp->output_reg);
3471
9d1a1031
JN		 3472 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3473 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3474
3475 return ret == intel_dp->lane_count;
3476}
3477
3ab9c637
ID		 3478static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3479{
3480 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3481 struct drm_device *dev = intel_dig_port->base.base.dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 enum port port = intel_dig_port->port;
3484 uint32_t val;
3485
3486 if (!HAS_DDI(dev))
3487 return;
3488
3489 val = I915_READ(DP_TP_CTL(port));
3490 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3491 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3492 I915_WRITE(DP_TP_CTL(port), val);
3493
3494 /*
3495 * On PORT_A we can have only eDP in SST mode. There the only reason
3496 * we need to set idle transmission mode is to work around a HW issue
3497 * where we enable the pipe while not in idle link-training mode.
3498 * In this case there is requirement to wait for a minimum number of
3499 * idle patterns to be sent.
3500 */
3501 if (port == PORT_A)
3502 return;
3503
3504 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3505 1))
3506 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3507}
3508
33a34e4e 3509/* Enable corresponding port and start training pattern 1 */
c19b0669 3510void
33a34e4e 3511intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3512{
da63a9f2 3513 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3514 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3515 int i;
3516 uint8_t voltage;
cdb0e95b 3517 int voltage_tries, loop_tries;
ea5b213a 3518 uint32_t DP = intel_dp->DP;
6aba5b6c 3519 uint8_t link_config[2];
a4fc5ed6 3520
affa9354 3521 if (HAS_DDI(dev))
c19b0669
PZ		 3522 intel_ddi_prepare_link_retrain(encoder);
3523
3cf2efb1 3524 /* Write the link configuration data */
6aba5b6c
JN		 3525 link_config[0] = intel_dp->link_bw;
3526 link_config[1] = intel_dp->lane_count;
3527 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3528 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3529 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3530
3531 link_config[0] = 0;
3532 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3533 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3534
3535 DP |= DP_PORT_EN;
1a2eb460 3536
70aff66c
JN		 3537 /* clock recovery */
3538 if (!intel_dp_reset_link_train(intel_dp, &DP,
3539 DP_TRAINING_PATTERN_1 |
3540 DP_LINK_SCRAMBLING_DISABLE)) {
3541 DRM_ERROR("failed to enable link training\n");
3542 return;
3543 }
3544
a4fc5ed6 3545 voltage = 0xff;
cdb0e95b
KP		 3546 voltage_tries = 0;
3547 loop_tries = 0;
a4fc5ed6 3548 for (;;) {
70aff66c 3549 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3550
a7c9655f 3551 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3552 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3553 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3554 break;
93f62dad 3555 }
a4fc5ed6 3556
01916270 3557 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3558 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3559 break;
3560 }
3561
3562 /* Check to see if we've tried the max voltage */
3563 for (i = 0; i < intel_dp->lane_count; i++)
3564 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3565 break;
3b4f819d 3566 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3567 ++loop_tries;
3568 if (loop_tries == 5) {
3def84b3 3569 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3570 break;
3571 }
70aff66c
JN		 3572 intel_dp_reset_link_train(intel_dp, &DP,
3573 DP_TRAINING_PATTERN_1 |
3574 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3575 voltage_tries = 0;
3576 continue;
3577 }
a4fc5ed6 3578
3cf2efb1 3579 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3580 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3581 ++voltage_tries;
b06fbda3 3582 if (voltage_tries == 5) {
3def84b3 3583 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3584 break;
3585 }
3586 } else
3587 voltage_tries = 0;
3588 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3589
70aff66c
JN		 3590 /* Update training set as requested by target */
3591 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3592 DRM_ERROR("failed to update link training\n");
3593 break;
3594 }
a4fc5ed6
KP		 3595 }
3596
33a34e4e
JB		 3597 intel_dp->DP = DP;
3598}
3599
c19b0669 3600void
33a34e4e
JB		 3601intel_dp_complete_link_train(struct intel_dp *intel_dp)
3602{
33a34e4e 3603 bool channel_eq = false;
37f80975 3604 int tries, cr_tries;
33a34e4e 3605 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3606 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3607
3608 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3609 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3610 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3611
a4fc5ed6 3612 /* channel equalization */
70aff66c 3613 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3614 training_pattern |
70aff66c
JN		 3615 DP_LINK_SCRAMBLING_DISABLE)) {
3616 DRM_ERROR("failed to start channel equalization\n");
3617 return;
3618 }
3619
a4fc5ed6 3620 tries = 0;
37f80975 3621 cr_tries = 0;
a4fc5ed6
KP		 3622 channel_eq = false;
3623 for (;;) {
70aff66c 3624 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3625
37f80975
JB		 3626 if (cr_tries > 5) {
3627 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3628 break;
3629 }
3630
a7c9655f 3631 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3632 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3633 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3634 break;
70aff66c 3635 }
a4fc5ed6 3636
37f80975 3637 /* Make sure clock is still ok */
01916270 3638 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3639 intel_dp_start_link_train(intel_dp);
70aff66c 3640 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3641 training_pattern |
70aff66c 3642 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3643 cr_tries++;
3644 continue;
3645 }
3646
1ffdff13 3647 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3648 channel_eq = true;
3649 break;
3650 }
a4fc5ed6 3651
37f80975
JB		 3652 /* Try 5 times, then try clock recovery if that fails */
3653 if (tries > 5) {
3654 intel_dp_link_down(intel_dp);
3655 intel_dp_start_link_train(intel_dp);
70aff66c 3656 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3657 training_pattern |
70aff66c 3658 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3659 tries = 0;
3660 cr_tries++;
3661 continue;
3662 }
a4fc5ed6 3663
70aff66c
JN		 3664 /* Update training set as requested by target */
3665 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3666 DRM_ERROR("failed to update link training\n");
3667 break;
3668 }
3cf2efb1 3669 ++tries;
869184a6 3670 }
3cf2efb1 3671
3ab9c637
ID		 3672 intel_dp_set_idle_link_train(intel_dp);
3673
3674 intel_dp->DP = DP;
3675
d6c0d722 3676 if (channel_eq)
07f42258 3677 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3678
3ab9c637
ID		 3679}
3680
3681void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3682{
70aff66c 3683 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3684 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3685}
3686
3687static void
ea5b213a 3688intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3689{
da63a9f2 3690 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3691 enum port port = intel_dig_port->port;
da63a9f2 3692 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3693 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3694 struct intel_crtc *intel_crtc =
3695 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3696 uint32_t DP = intel_dp->DP;
a4fc5ed6 3697
bc76e320 3698 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3699 return;
3700
0c33d8d7 3701 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3702 return;
3703
28c97730 3704 DRM_DEBUG_KMS("\n");
32f9d658 3705
bc7d38a4 3706 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3707 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3708 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3709 } else {
aad3d14d
VS		 3710 if (IS_CHERRYVIEW(dev))
3711 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3712 else
3713 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3714 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3715 }
fe255d00 3716 POSTING_READ(intel_dp->output_reg);
5eb08b69 3717
493a7081 3718 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3719 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3720 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3721
5bddd17f
EA		 3722 /* Hardware workaround: leaving our transcoder select
3723 * set to transcoder B while it's off will prevent the
3724 * corresponding HDMI output on transcoder A.
3725 *
3726 * Combine this with another hardware workaround:
3727 * transcoder select bit can only be cleared while the
3728 * port is enabled.
3729 */
3730 DP &= ~DP_PIPEB_SELECT;
3731 I915_WRITE(intel_dp->output_reg, DP);
3732
3733 /* Changes to enable or select take place the vblank
3734 * after being written.
3735 */
ff50afe9
DV		 3736 if (WARN_ON(crtc == NULL)) {
3737 /* We should never try to disable a port without a crtc
3738 * attached. For paranoia keep the code around for a
3739 * bit. */
31acbcc4
CW		 3740 POSTING_READ(intel_dp->output_reg);
3741 msleep(50);
3742 } else
ab527efc 3743 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3744 }
3745
832afda6 3746 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3747 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3748 POSTING_READ(intel_dp->output_reg);
f01eca2e 3749 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3750}
3751
26d61aad
KP		 3752static bool
3753intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3754{
a031d709
RV		 3755 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3756 struct drm_device *dev = dig_port->base.base.dev;
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758
9d1a1031
JN		 3759 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3760 sizeof(intel_dp->dpcd)) < 0)
edb39244 3761 return false; /* aux transfer failed */
92fd8fd1 3762
a8e98153 3763 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3764
edb39244
AJ		 3765 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3766 return false; /* DPCD not present */
3767
2293bb5c
SK		 3768 /* Check if the panel supports PSR */
3769 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3770 if (is_edp(intel_dp)) {
9d1a1031
JN		 3771 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3772 intel_dp->psr_dpcd,
3773 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3774 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3775 dev_priv->psr.sink_support = true;
50003939 3776 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3777 }
50003939
JN		 3778 }
3779
06ea66b6
TP		 3780 /* Training Pattern 3 support */
3781 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3782 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3783 intel_dp->use_tps3 = true;
f8d8a672 3784 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3785 } else
3786 intel_dp->use_tps3 = false;
3787
edb39244
AJ		 3788 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3789 DP_DWN_STRM_PORT_PRESENT))
3790 return true; /* native DP sink */
3791
3792 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3793 return true; /* no per-port downstream info */
3794
9d1a1031
JN		 3795 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3796 intel_dp->downstream_ports,
3797 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3798 return false; /* downstream port status fetch failed */
3799
3800 return true;
92fd8fd1
KP		 3801}
3802
0d198328
AJ		 3803static void
3804intel_dp_probe_oui(struct intel_dp *intel_dp)
3805{
3806 u8 buf[3];
3807
3808 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3809 return;
3810
24f3e092 3811 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3812
9d1a1031 3813 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3814 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3815 buf[0], buf[1], buf[2]);
3816
9d1a1031 3817 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3818 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3819 buf[0], buf[1], buf[2]);
351cfc34 3820
1e0560e0 3821 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3822}
3823
0e32b39c
DA		 3824static bool
3825intel_dp_probe_mst(struct intel_dp *intel_dp)
3826{
3827 u8 buf[1];
3828
3829 if (!intel_dp->can_mst)
3830 return false;
3831
3832 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3833 return false;
3834
d337a341 3835 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3836 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3837 if (buf[0] & DP_MST_CAP) {
3838 DRM_DEBUG_KMS("Sink is MST capable\n");
3839 intel_dp->is_mst = true;
3840 } else {
3841 DRM_DEBUG_KMS("Sink is not MST capable\n");
3842 intel_dp->is_mst = false;
3843 }
3844 }
1e0560e0 3845 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3846
3847 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3848 return intel_dp->is_mst;
3849}
3850
d2e216d0
RV		 3851int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3852{
3853 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3854 struct drm_device *dev = intel_dig_port->base.base.dev;
3855 struct intel_crtc *intel_crtc =
3856 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3857 u8 buf;
3858 int test_crc_count;
3859 int attempts = 6;
d2e216d0 3860
ad9dc91b 3861 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3862 return -EIO;
d2e216d0 3863
ad9dc91b 3864 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3865 return -ENOTTY;
3866
ce31d9f4 3867 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf);
9d1a1031 3868 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3869 buf | DP_TEST_SINK_START) < 0)
bda0381e 3870 return -EIO;
d2e216d0 3871
ad9dc91b
RV		 3872 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf);
3873 test_crc_count = buf & DP_TEST_COUNT_MASK;
3874
3875 do {
3876 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf);
3877 intel_wait_for_vblank(dev, intel_crtc->pipe);
3878 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3879
3880 if (attempts == 0) {
3881 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3882 return -EIO;
3883 }
d2e216d0 3884
9d1a1031 3885 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3886 return -EIO;
d2e216d0 3887
ce31d9f4
RV		 3888 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf);
3889 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3890 buf & ~DP_TEST_SINK_START);
3891
d2e216d0
RV		 3892 return 0;
3893}
3894
a60f0e38
JB		 3895static bool
3896intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3897{
9d1a1031
JN		 3898 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3899 DP_DEVICE_SERVICE_IRQ_VECTOR,
3900 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3901}
3902
0e32b39c
DA		 3903static bool
3904intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3905{
3906 int ret;
3907
3908 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3909 DP_SINK_COUNT_ESI,
3910 sink_irq_vector, 14);
3911 if (ret != 14)
3912 return false;
3913
3914 return true;
3915}
3916
a60f0e38
JB		 3917static void
3918intel_dp_handle_test_request(struct intel_dp *intel_dp)
3919{
3920 /* NAK by default */
9d1a1031 3921 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3922}
3923
0e32b39c
DA		 3924static int
3925intel_dp_check_mst_status(struct intel_dp *intel_dp)
3926{
3927 bool bret;
3928
3929 if (intel_dp->is_mst) {
3930 u8 esi[16] = { 0 };
3931 int ret = 0;
3932 int retry;
3933 bool handled;
3934 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3935go_again:
3936 if (bret == true) {
3937
3938 /* check link status - esi[10] = 0x200c */
3939 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3940 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3941 intel_dp_start_link_train(intel_dp);
3942 intel_dp_complete_link_train(intel_dp);
3943 intel_dp_stop_link_train(intel_dp);
3944 }
3945
3946 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3947 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3948
3949 if (handled) {
3950 for (retry = 0; retry < 3; retry++) {
3951 int wret;
3952 wret = drm_dp_dpcd_write(&intel_dp->aux,
3953 DP_SINK_COUNT_ESI+1,
3954 &esi[1], 3);
3955 if (wret == 3) {
3956 break;
3957 }
3958 }
3959
3960 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3961 if (bret == true) {
3962 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3963 goto go_again;
3964 }
3965 } else
3966 ret = 0;
3967
3968 return ret;
3969 } else {
3970 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3971 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3972 intel_dp->is_mst = false;
3973 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3974 /* send a hotplug event */
3975 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3976 }
3977 }
3978 return -EINVAL;
3979}
3980
a4fc5ed6
KP		 3981/*
3982 * According to DP spec
3983 * 5.1.2:
3984 * 1. Read DPCD
3985 * 2. Configure link according to Receiver Capabilities
3986 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3987 * 4. Check link status on receipt of hot-plug interrupt
3988 */
00c09d70 3989void
ea5b213a 3990intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3991{
5b215bcf 3992 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3993 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3994 u8 sink_irq_vector;
93f62dad 3995 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3996
5b215bcf
DA		 3997 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3998
da63a9f2 3999 if (!intel_encoder->connectors_active)
d2b996ac 4000 return;
59cd09e1 4001
da63a9f2 4002 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4003 return;
4004
1a125d8a
ID		 4005 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4006 return;
4007
92fd8fd1 4008 /* Try to read receiver status if the link appears to be up */
93f62dad 4009 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4010 return;
4011 }
4012
92fd8fd1 4013 /* Now read the DPCD to see if it's actually running */
26d61aad 4014 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4015 return;
4016 }
4017
a60f0e38
JB		 4018 /* Try to read the source of the interrupt */
4019 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4020 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4021 /* Clear interrupt source */
9d1a1031
JN		 4022 drm_dp_dpcd_writeb(&intel_dp->aux,
4023 DP_DEVICE_SERVICE_IRQ_VECTOR,
4024 sink_irq_vector);
a60f0e38
JB		 4025
4026 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4027 intel_dp_handle_test_request(intel_dp);
4028 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4029 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4030 }
4031
1ffdff13 4032 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4033 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4034 intel_encoder->base.name);
33a34e4e
JB		 4035 intel_dp_start_link_train(intel_dp);
4036 intel_dp_complete_link_train(intel_dp);
3ab9c637 4037 intel_dp_stop_link_train(intel_dp);
33a34e4e 4038 }
a4fc5ed6 4039}
a4fc5ed6 4040
caf9ab24 4041/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4042static enum drm_connector_status
26d61aad 4043intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4044{
caf9ab24 4045 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4046 uint8_t type;
4047
4048 if (!intel_dp_get_dpcd(intel_dp))
4049 return connector_status_disconnected;
4050
4051 /* if there's no downstream port, we're done */
4052 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4053 return connector_status_connected;
caf9ab24
AJ		 4054
4055 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4056 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4057 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4058 uint8_t reg;
9d1a1031
JN		 4059
4060 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4061 &reg, 1) < 0)
caf9ab24 4062 return connector_status_unknown;
9d1a1031 4063
23235177
AJ		 4064 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4065 : connector_status_disconnected;
caf9ab24
AJ		 4066 }
4067
4068 /* If no HPD, poke DDC gently */
0b99836f 4069 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4070 return connector_status_connected;
caf9ab24
AJ		 4071
4072 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4073 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4074 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4075 if (type == DP_DS_PORT_TYPE_VGA ||
4076 type == DP_DS_PORT_TYPE_NON_EDID)
4077 return connector_status_unknown;
4078 } else {
4079 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4080 DP_DWN_STRM_PORT_TYPE_MASK;
4081 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4082 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4083 return connector_status_unknown;
4084 }
caf9ab24
AJ		 4085
4086 /* Anything else is out of spec, warn and ignore */
4087 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4088 return connector_status_disconnected;
71ba9000
AJ		 4089}
4090
d410b56d
CW		 4091static enum drm_connector_status
4092edp_detect(struct intel_dp *intel_dp)
4093{
4094 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4095 enum drm_connector_status status;
4096
4097 status = intel_panel_detect(dev);
4098 if (status == connector_status_unknown)
4099 status = connector_status_connected;
4100
4101 return status;
4102}
4103
5eb08b69 4104static enum drm_connector_status
a9756bb5 4105ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4106{
30add22d 4107 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4110
1b469639
DL		 4111 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4112 return connector_status_disconnected;
4113
26d61aad 4114 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4115}
4116
2a592bec
DA		 4117static int g4x_digital_port_connected(struct drm_device *dev,
4118 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4119{
a4fc5ed6 4120 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4121 uint32_t bit;
5eb08b69 4122
232a6ee9
TP		 4123 if (IS_VALLEYVIEW(dev)) {
4124 switch (intel_dig_port->port) {
4125 case PORT_B:
4126 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4127 break;
4128 case PORT_C:
4129 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4130 break;
4131 case PORT_D:
4132 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4133 break;
4134 default:
2a592bec 4135 return -EINVAL;
232a6ee9
TP		 4136 }
4137 } else {
4138 switch (intel_dig_port->port) {
4139 case PORT_B:
4140 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4141 break;
4142 case PORT_C:
4143 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4144 break;
4145 case PORT_D:
4146 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4147 break;
4148 default:
2a592bec 4149 return -EINVAL;
232a6ee9 4150 }
a4fc5ed6
KP		 4151 }
4152
10f76a38 4153 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4154 return 0;
4155 return 1;
4156}
4157
4158static enum drm_connector_status
4159g4x_dp_detect(struct intel_dp *intel_dp)
4160{
4161 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4162 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4163 int ret;
4164
4165 /* Can't disconnect eDP, but you can close the lid... */
4166 if (is_edp(intel_dp)) {
4167 enum drm_connector_status status;
4168
4169 status = intel_panel_detect(dev);
4170 if (status == connector_status_unknown)
4171 status = connector_status_connected;
4172 return status;
4173 }
4174
4175 ret = g4x_digital_port_connected(dev, intel_dig_port);
4176 if (ret == -EINVAL)
4177 return connector_status_unknown;
4178 else if (ret == 0)
a4fc5ed6
KP		 4179 return connector_status_disconnected;
4180
26d61aad 4181 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4182}
4183
8c241fef 4184static struct edid *
beb60608 4185intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4186{
beb60608 4187 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4188
9cd300e0
JN		 4189 /* use cached edid if we have one */
4190 if (intel_connector->edid) {
9cd300e0
JN		 4191 /* invalid edid */
4192 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4193 return NULL;
4194
55e9edeb 4195 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4196 } else
4197 return drm_get_edid(&intel_connector->base,
4198 &intel_dp->aux.ddc);
4199}
8c241fef 4200
beb60608
CW		 4201static void
4202intel_dp_set_edid(struct intel_dp *intel_dp)
4203{
4204 struct intel_connector *intel_connector = intel_dp->attached_connector;
4205 struct edid *edid;
8c241fef 4206
beb60608
CW		 4207 edid = intel_dp_get_edid(intel_dp);
4208 intel_connector->detect_edid = edid;
4209
4210 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4211 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4212 else
4213 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4214}
4215
beb60608
CW		 4216static void
4217intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4218{
beb60608 4219 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4220
beb60608
CW		 4221 kfree(intel_connector->detect_edid);
4222 intel_connector->detect_edid = NULL;
9cd300e0 4223
beb60608
CW		 4224 intel_dp->has_audio = false;
4225}
d6f24d0f 4226
beb60608
CW		 4227static enum intel_display_power_domain
4228intel_dp_power_get(struct intel_dp *dp)
4229{
4230 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4231 enum intel_display_power_domain power_domain;
4232
4233 power_domain = intel_display_port_power_domain(encoder);
4234 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4235
4236 return power_domain;
4237}
d6f24d0f 4238
beb60608
CW		 4239static void
4240intel_dp_power_put(struct intel_dp *dp,
4241 enum intel_display_power_domain power_domain)
4242{
4243 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4244 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4245}
4246
a9756bb5
ZW		 4247static enum drm_connector_status
4248intel_dp_detect(struct drm_connector *connector, bool force)
4249{
4250 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4251 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4252 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4253 struct drm_device *dev = connector->dev;
a9756bb5 4254 enum drm_connector_status status;
671dedd2 4255 enum intel_display_power_domain power_domain;
0e32b39c 4256 bool ret;
a9756bb5 4257
164c8598 4258 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4259 connector->base.id, connector->name);
beb60608 4260 intel_dp_unset_edid(intel_dp);
164c8598 4261
0e32b39c
DA		 4262 if (intel_dp->is_mst) {
4263 /* MST devices are disconnected from a monitor POV */
4264 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4265 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4266 return connector_status_disconnected;
0e32b39c
DA		 4267 }
4268
beb60608 4269 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4270
d410b56d
CW		 4271 /* Can't disconnect eDP, but you can close the lid... */
4272 if (is_edp(intel_dp))
4273 status = edp_detect(intel_dp);
4274 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4275 status = ironlake_dp_detect(intel_dp);
4276 else
4277 status = g4x_dp_detect(intel_dp);
4278 if (status != connector_status_connected)
c8c8fb33 4279 goto out;
a9756bb5 4280
0d198328
AJ		 4281 intel_dp_probe_oui(intel_dp);
4282
0e32b39c
DA		 4283 ret = intel_dp_probe_mst(intel_dp);
4284 if (ret) {
4285 /* if we are in MST mode then this connector
4286 won't appear connected or have anything with EDID on it */
4287 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4288 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4289 status = connector_status_disconnected;
4290 goto out;
4291 }
4292
beb60608 4293 intel_dp_set_edid(intel_dp);
a9756bb5 4294
d63885da
PZ		 4295 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4296 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4297 status = connector_status_connected;
4298
4299out:
beb60608 4300 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4301 return status;
a4fc5ed6
KP		 4302}
4303
beb60608
CW		 4304static void
4305intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4306{
df0e9248 4307 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4308 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4309 enum intel_display_power_domain power_domain;
a4fc5ed6 4310
beb60608
CW		 4311 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4312 connector->base.id, connector->name);
4313 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4314
beb60608
CW		 4315 if (connector->status != connector_status_connected)
4316 return;
671dedd2 4317
beb60608
CW		 4318 power_domain = intel_dp_power_get(intel_dp);
4319
4320 intel_dp_set_edid(intel_dp);
4321
4322 intel_dp_power_put(intel_dp, power_domain);
4323
4324 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4325 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4326}
4327
4328static int intel_dp_get_modes(struct drm_connector *connector)
4329{
4330 struct intel_connector *intel_connector = to_intel_connector(connector);
4331 struct edid *edid;
4332
4333 edid = intel_connector->detect_edid;
4334 if (edid) {
4335 int ret = intel_connector_update_modes(connector, edid);
4336 if (ret)
4337 return ret;
4338 }
32f9d658 4339
f8779fda 4340 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4341 if (is_edp(intel_attached_dp(connector)) &&
4342 intel_connector->panel.fixed_mode) {
f8779fda 4343 struct drm_display_mode *mode;
beb60608
CW		 4344
4345 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4346 intel_connector->panel.fixed_mode);
f8779fda 4347 if (mode) {
32f9d658
ZW		 4348 drm_mode_probed_add(connector, mode);
4349 return 1;
4350 }
4351 }
beb60608 4352
32f9d658 4353 return 0;
a4fc5ed6
KP		 4354}
4355
1aad7ac0
CW		 4356static bool
4357intel_dp_detect_audio(struct drm_connector *connector)
4358{
1aad7ac0 4359 bool has_audio = false;
beb60608 4360 struct edid *edid;
1aad7ac0 4361
beb60608
CW		 4362 edid = to_intel_connector(connector)->detect_edid;
4363 if (edid)
1aad7ac0 4364 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4365
1aad7ac0
CW		 4366 return has_audio;
4367}
4368
f684960e
CW		 4369static int
4370intel_dp_set_property(struct drm_connector *connector,
4371 struct drm_property *property,
4372 uint64_t val)
4373{
e953fd7b 4374 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4375 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4376 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4377 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4378 int ret;
4379
662595df 4380 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4381 if (ret)
4382 return ret;
4383
3f43c48d 4384 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4385 int i = val;
4386 bool has_audio;
4387
4388 if (i == intel_dp->force_audio)
f684960e
CW		 4389 return 0;
4390
1aad7ac0 4391 intel_dp->force_audio = i;
f684960e 4392
c3e5f67b 4393 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4394 has_audio = intel_dp_detect_audio(connector);
4395 else
c3e5f67b 4396 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4397
4398 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4399 return 0;
4400
1aad7ac0 4401 intel_dp->has_audio = has_audio;
f684960e
CW		 4402 goto done;
4403 }
4404
e953fd7b 4405 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4406 bool old_auto = intel_dp->color_range_auto;
4407 uint32_t old_range = intel_dp->color_range;
4408
55bc60db
VS		 4409 switch (val) {
4410 case INTEL_BROADCAST_RGB_AUTO:
4411 intel_dp->color_range_auto = true;
4412 break;
4413 case INTEL_BROADCAST_RGB_FULL:
4414 intel_dp->color_range_auto = false;
4415 intel_dp->color_range = 0;
4416 break;
4417 case INTEL_BROADCAST_RGB_LIMITED:
4418 intel_dp->color_range_auto = false;
4419 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4420 break;
4421 default:
4422 return -EINVAL;
4423 }
ae4edb80
DV		 4424
4425 if (old_auto == intel_dp->color_range_auto &&
4426 old_range == intel_dp->color_range)
4427 return 0;
4428
e953fd7b
CW		 4429 goto done;
4430 }
4431
53b41837
YN		 4432 if (is_edp(intel_dp) &&
4433 property == connector->dev->mode_config.scaling_mode_property) {
4434 if (val == DRM_MODE_SCALE_NONE) {
4435 DRM_DEBUG_KMS("no scaling not supported\n");
4436 return -EINVAL;
4437 }
4438
4439 if (intel_connector->panel.fitting_mode == val) {
4440 /* the eDP scaling property is not changed */
4441 return 0;
4442 }
4443 intel_connector->panel.fitting_mode = val;
4444
4445 goto done;
4446 }
4447
f684960e
CW		 4448 return -EINVAL;
4449
4450done:
c0c36b94
CW		 4451 if (intel_encoder->base.crtc)
4452 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4453
4454 return 0;
4455}
4456
a4fc5ed6 4457static void
73845adf 4458intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4459{
1d508706 4460 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4461
10e972d3 4462 kfree(intel_connector->detect_edid);
beb60608 4463
9cd300e0
JN		 4464 if (!IS_ERR_OR_NULL(intel_connector->edid))
4465 kfree(intel_connector->edid);
4466
acd8db10
PZ		 4467 /* Can't call is_edp() since the encoder may have been destroyed
4468 * already. */
4469 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4470 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4471
a4fc5ed6 4472 drm_connector_cleanup(connector);
55f78c43 4473 kfree(connector);
a4fc5ed6
KP		 4474}
4475
00c09d70 4476void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4477{
da63a9f2
PZ		 4478 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4479 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4480
4f71d0cb 4481 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4482 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4483 drm_encoder_cleanup(encoder);
bd943159
KP		 4484 if (is_edp(intel_dp)) {
4485 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4486 /*
4487 * vdd might still be enabled do to the delayed vdd off.
4488 * Make sure vdd is actually turned off here.
4489 */
773538e8 4490 pps_lock(intel_dp);
4be73780 4491 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4492 pps_unlock(intel_dp);
4493
01527b31
CT		 4494 if (intel_dp->edp_notifier.notifier_call) {
4495 unregister_reboot_notifier(&intel_dp->edp_notifier);
4496 intel_dp->edp_notifier.notifier_call = NULL;
4497 }
bd943159 4498 }
da63a9f2 4499 kfree(intel_dig_port);
24d05927
DV		 4500}
4501
07f9cd0b
ID		 4502static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4503{
4504 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4505
4506 if (!is_edp(intel_dp))
4507 return;
4508
951468f3
VS		 4509 /*
4510 * vdd might still be enabled do to the delayed vdd off.
4511 * Make sure vdd is actually turned off here.
4512 */
773538e8 4513 pps_lock(intel_dp);
07f9cd0b 4514 edp_panel_vdd_off_sync(intel_dp);
773538e8 4515 pps_unlock(intel_dp);
07f9cd0b
ID		 4516}
4517
6d93c0c4
ID		 4518static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4519{
4520 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4521}
4522
a4fc5ed6 4523static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4524 .dpms = intel_connector_dpms,
a4fc5ed6 4525 .detect = intel_dp_detect,
beb60608 4526 .force = intel_dp_force,
a4fc5ed6 4527 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4528 .set_property = intel_dp_set_property,
73845adf 4529 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4530};
4531
4532static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4533 .get_modes = intel_dp_get_modes,
4534 .mode_valid = intel_dp_mode_valid,
df0e9248 4535 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4536};
4537
a4fc5ed6 4538static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4539 .reset = intel_dp_encoder_reset,
24d05927 4540 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4541};
4542
0e32b39c 4543void
21d40d37 4544intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4545{
0e32b39c 4546 return;
c8110e52 4547}
6207937d 4548
13cf5504
DA		 4549bool
4550intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4551{
4552 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4553 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4554 struct drm_device *dev = intel_dig_port->base.base.dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4556 enum intel_display_power_domain power_domain;
4557 bool ret = true;
4558
0e32b39c
DA		 4559 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4560 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4561
26fbb774
VS		 4562 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4563 port_name(intel_dig_port->port),
0e32b39c 4564 long_hpd ? "long" : "short");
13cf5504 4565
1c767b33
ID		 4566 power_domain = intel_display_port_power_domain(intel_encoder);
4567 intel_display_power_get(dev_priv, power_domain);
4568
0e32b39c 4569 if (long_hpd) {
2a592bec
DA		 4570
4571 if (HAS_PCH_SPLIT(dev)) {
4572 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4573 goto mst_fail;
4574 } else {
4575 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4576 goto mst_fail;
4577 }
0e32b39c
DA		 4578
4579 if (!intel_dp_get_dpcd(intel_dp)) {
4580 goto mst_fail;
4581 }
4582
4583 intel_dp_probe_oui(intel_dp);
4584
4585 if (!intel_dp_probe_mst(intel_dp))
4586 goto mst_fail;
4587
4588 } else {
4589 if (intel_dp->is_mst) {
1c767b33 4590 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4591 goto mst_fail;
4592 }
4593
4594 if (!intel_dp->is_mst) {
4595 /*
4596 * we'll check the link status via the normal hot plug path later -
4597 * but for short hpds we should check it now
4598 */
5b215bcf 4599 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4600 intel_dp_check_link_status(intel_dp);
5b215bcf 4601 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4602 }
4603 }
1c767b33
ID		 4604 ret = false;
4605 goto put_power;
0e32b39c
DA		 4606mst_fail:
4607 /* if we were in MST mode, and device is not there get out of MST mode */
4608 if (intel_dp->is_mst) {
4609 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4610 intel_dp->is_mst = false;
4611 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4612 }
1c767b33
ID		 4613put_power:
4614 intel_display_power_put(dev_priv, power_domain);
4615
4616 return ret;
13cf5504
DA		 4617}
4618
e3421a18
ZW		 4619/* Return which DP Port should be selected for Transcoder DP control */
4620int
0206e353 4621intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4622{
4623 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4624 struct intel_encoder *intel_encoder;
4625 struct intel_dp *intel_dp;
e3421a18 4626
fa90ecef
PZ		 4627 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4628 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4629
fa90ecef
PZ		 4630 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4631 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4632 return intel_dp->output_reg;
e3421a18 4633 }
ea5b213a 4634
e3421a18
ZW		 4635 return -1;
4636}
4637
36e83a18 4638/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4639bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4640{
4641 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4642 union child_device_config *p_child;
36e83a18 4643 int i;
5d8a7752
VS		 4644 static const short port_mapping[] = {
4645 [PORT_B] = PORT_IDPB,
4646 [PORT_C] = PORT_IDPC,
4647 [PORT_D] = PORT_IDPD,
4648 };
36e83a18 4649
3b32a35b
VS		 4650 if (port == PORT_A)
4651 return true;
4652
41aa3448 4653 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4654 return false;
4655
41aa3448
RV		 4656 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4657 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4658
5d8a7752 4659 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4660 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4661 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4662 return true;
4663 }
4664 return false;
4665}
4666
0e32b39c 4667void
f684960e
CW		 4668intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4669{
53b41837
YN		 4670 struct intel_connector *intel_connector = to_intel_connector(connector);
4671
3f43c48d 4672 intel_attach_force_audio_property(connector);
e953fd7b 4673 intel_attach_broadcast_rgb_property(connector);
55bc60db 4674 intel_dp->color_range_auto = true;
53b41837
YN		 4675
4676 if (is_edp(intel_dp)) {
4677 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4678 drm_object_attach_property(
4679 &connector->base,
53b41837 4680 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4681 DRM_MODE_SCALE_ASPECT);
4682 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4683 }
f684960e
CW		 4684}
4685
dada1a9f
ID		 4686static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4687{
4688 intel_dp->last_power_cycle = jiffies;
4689 intel_dp->last_power_on = jiffies;
4690 intel_dp->last_backlight_off = jiffies;
4691}
4692
67a54566
DV		 4693static void
4694intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4695 struct intel_dp *intel_dp,
4696 struct edp_power_seq *out)
67a54566
DV		 4697{
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 struct edp_power_seq cur, vbt, spec, final;
4700 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4701 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4702
e39b999a
VS		 4703 lockdep_assert_held(&dev_priv->pps_mutex);
4704
453c5420 4705 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4706 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4707 pp_on_reg = PCH_PP_ON_DELAYS;
4708 pp_off_reg = PCH_PP_OFF_DELAYS;
4709 pp_div_reg = PCH_PP_DIVISOR;
4710 } else {
bf13e81b
JN		 4711 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4712
4713 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4714 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4715 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4716 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4717 }
67a54566
DV		 4718
4719 /* Workaround: Need to write PP_CONTROL with the unlock key as
4720 * the very first thing. */
453c5420 4721 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4722 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4723
453c5420
JB		 4724 pp_on = I915_READ(pp_on_reg);
4725 pp_off = I915_READ(pp_off_reg);
4726 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4727
4728 /* Pull timing values out of registers */
4729 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4730 PANEL_POWER_UP_DELAY_SHIFT;
4731
4732 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4733 PANEL_LIGHT_ON_DELAY_SHIFT;
4734
4735 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4736 PANEL_LIGHT_OFF_DELAY_SHIFT;
4737
4738 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4739 PANEL_POWER_DOWN_DELAY_SHIFT;
4740
4741 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4742 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4743
4744 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4745 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4746
41aa3448 4747 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4748
4749 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4750 * our hw here, which are all in 100usec. */
4751 spec.t1_t3 = 210 * 10;
4752 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4753 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4754 spec.t10 = 500 * 10;
4755 /* This one is special and actually in units of 100ms, but zero
4756 * based in the hw (so we need to add 100 ms). But the sw vbt
4757 * table multiplies it with 1000 to make it in units of 100usec,
4758 * too. */
4759 spec.t11_t12 = (510 + 100) * 10;
4760
4761 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4762 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4763
4764 /* Use the max of the register settings and vbt. If both are
4765 * unset, fall back to the spec limits. */
4766#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4767 spec.field : \
4768 max(cur.field, vbt.field))
4769 assign_final(t1_t3);
4770 assign_final(t8);
4771 assign_final(t9);
4772 assign_final(t10);
4773 assign_final(t11_t12);
4774#undef assign_final
4775
4776#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4777 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4778 intel_dp->backlight_on_delay = get_delay(t8);
4779 intel_dp->backlight_off_delay = get_delay(t9);
4780 intel_dp->panel_power_down_delay = get_delay(t10);
4781 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4782#undef get_delay
4783
f30d26e4
JN		 4784 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4785 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4786 intel_dp->panel_power_cycle_delay);
4787
4788 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4789 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4790
4791 if (out)
4792 *out = final;
4793}
4794
4795static void
4796intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4797 struct intel_dp *intel_dp,
4798 struct edp_power_seq *seq)
4799{
4800 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4801 u32 pp_on, pp_off, pp_div, port_sel = 0;
4802 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4803 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4804 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4805
e39b999a 4806 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4807
4808 if (HAS_PCH_SPLIT(dev)) {
4809 pp_on_reg = PCH_PP_ON_DELAYS;
4810 pp_off_reg = PCH_PP_OFF_DELAYS;
4811 pp_div_reg = PCH_PP_DIVISOR;
4812 } else {
bf13e81b
JN		 4813 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4814
4815 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4816 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4817 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4818 }
4819
b2f19d1a
PZ		 4820 /*
4821 * And finally store the new values in the power sequencer. The
4822 * backlight delays are set to 1 because we do manual waits on them. For
4823 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4824 * we'll end up waiting for the backlight off delay twice: once when we
4825 * do the manual sleep, and once when we disable the panel and wait for
4826 * the PP_STATUS bit to become zero.
4827 */
f30d26e4 4828 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4829 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4830 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4831 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4832 /* Compute the divisor for the pp clock, simply match the Bspec
4833 * formula. */
453c5420 4834 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4835 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4836 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4837
4838 /* Haswell doesn't have any port selection bits for the panel
4839 * power sequencer any more. */
bc7d38a4 4840 if (IS_VALLEYVIEW(dev)) {
ad933b56 4841 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4842 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4843 if (port == PORT_A)
a24c144c 4844 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4845 else
a24c144c 4846 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4847 }
4848
453c5420
JB		 4849 pp_on |= port_sel;
4850
4851 I915_WRITE(pp_on_reg, pp_on);
4852 I915_WRITE(pp_off_reg, pp_off);
4853 I915_WRITE(pp_div_reg, pp_div);
67a54566 4854
67a54566 4855 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4856 I915_READ(pp_on_reg),
4857 I915_READ(pp_off_reg),
4858 I915_READ(pp_div_reg));
f684960e
CW		 4859}
4860
439d7ac0
PB		 4861void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4862{
4863 struct drm_i915_private *dev_priv = dev->dev_private;
4864 struct intel_encoder *encoder;
4865 struct intel_dp *intel_dp = NULL;
4866 struct intel_crtc_config *config = NULL;
4867 struct intel_crtc *intel_crtc = NULL;
4868 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4869 u32 reg, val;
4870 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4871
4872 if (refresh_rate <= 0) {
4873 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4874 return;
4875 }
4876
4877 if (intel_connector == NULL) {
4878 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4879 return;
4880 }
4881
1fcc9d1c
DV		 4882 /*
4883 * FIXME: This needs proper synchronization with psr state. But really
4884 * hard to tell without seeing the user of this function of this code.
4885 * Check locking and ordering once that lands.
4886 */
439d7ac0
PB		 4887 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4888 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4889 return;
4890 }
4891
4892 encoder = intel_attached_encoder(&intel_connector->base);
4893 intel_dp = enc_to_intel_dp(&encoder->base);
4894 intel_crtc = encoder->new_crtc;
4895
4896 if (!intel_crtc) {
4897 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4898 return;
4899 }
4900
4901 config = &intel_crtc->config;
4902
4903 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4904 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4905 return;
4906 }
4907
4908 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4909 index = DRRS_LOW_RR;
4910
4911 if (index == intel_dp->drrs_state.refresh_rate_type) {
4912 DRM_DEBUG_KMS(
4913 "DRRS requested for previously set RR...ignoring\n");
4914 return;
4915 }
4916
4917 if (!intel_crtc->active) {
4918 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4919 return;
4920 }
4921
4922 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4923 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4924 val = I915_READ(reg);
4925 if (index > DRRS_HIGH_RR) {
4926 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4927 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4928 } else {
4929 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4930 }
4931 I915_WRITE(reg, val);
4932 }
4933
4934 /*
4935 * mutex taken to ensure that there is no race between differnt
4936 * drrs calls trying to update refresh rate. This scenario may occur
4937 * in future when idleness detection based DRRS in kernel and
4938 * possible calls from user space to set differnt RR are made.
4939 */
4940
4941 mutex_lock(&intel_dp->drrs_state.mutex);
4942
4943 intel_dp->drrs_state.refresh_rate_type = index;
4944
4945 mutex_unlock(&intel_dp->drrs_state.mutex);
4946
4947 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4948}
4949
4f9db5b5
PB		 4950static struct drm_display_mode *
4951intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4952 struct intel_connector *intel_connector,
4953 struct drm_display_mode *fixed_mode)
4954{
4955 struct drm_connector *connector = &intel_connector->base;
4956 struct intel_dp *intel_dp = &intel_dig_port->dp;
4957 struct drm_device *dev = intel_dig_port->base.base.dev;
4958 struct drm_i915_private *dev_priv = dev->dev_private;
4959 struct drm_display_mode *downclock_mode = NULL;
4960
4961 if (INTEL_INFO(dev)->gen <= 6) {
4962 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4963 return NULL;
4964 }
4965
4966 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4967 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4968 return NULL;
4969 }
4970
4971 downclock_mode = intel_find_panel_downclock
4972 (dev, fixed_mode, connector);
4973
4974 if (!downclock_mode) {
4079b8d1 4975 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4976 return NULL;
4977 }
4978
439d7ac0
PB		 4979 dev_priv->drrs.connector = intel_connector;
4980
4981 mutex_init(&intel_dp->drrs_state.mutex);
4982
4f9db5b5
PB		 4983 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4984
4985 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4986 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4987 return downclock_mode;
4988}
4989
aba86890
ID		 4990void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4991{
4992 struct drm_device *dev = intel_encoder->base.dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 struct intel_dp *intel_dp;
4995 enum intel_display_power_domain power_domain;
4996
4997 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4998 return;
4999
5000 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5001
5002 pps_lock(intel_dp);
5003
aba86890 5004 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5005 goto out;
aba86890
ID		 5006 /*
5007 * The VDD bit needs a power domain reference, so if the bit is
5008 * already enabled when we boot or resume, grab this reference and
5009 * schedule a vdd off, so we don't hold on to the reference
5010 * indefinitely.
5011 */
5012 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5013 power_domain = intel_display_port_power_domain(intel_encoder);
5014 intel_display_power_get(dev_priv, power_domain);
5015
5016 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5017 out:
773538e8 5018 pps_unlock(intel_dp);
aba86890
ID		 5019}
5020
ed92f0b2 5021static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 5022 struct intel_connector *intel_connector,
5023 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 5024{
5025 struct drm_connector *connector = &intel_connector->base;
5026 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5027 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5028 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5031 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5032 bool has_dpcd;
5033 struct drm_display_mode *scan;
5034 struct edid *edid;
5035
4f9db5b5
PB		 5036 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5037
ed92f0b2
PZ		 5038 if (!is_edp(intel_dp))
5039 return true;
5040
aba86890 5041 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5042
ed92f0b2 5043 /* Cache DPCD and EDID for edp. */
24f3e092 5044 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 5045 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 5046 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 5047
5048 if (has_dpcd) {
5049 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5050 dev_priv->no_aux_handshake =
5051 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5052 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5053 } else {
5054 /* if this fails, presume the device is a ghost */
5055 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5056 return false;
5057 }
5058
5059 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5060 pps_lock(intel_dp);
0095e6dc 5061 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 5062 pps_unlock(intel_dp);
ed92f0b2 5063
060c8778 5064 mutex_lock(&dev->mode_config.mutex);
0b99836f 5065 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5066 if (edid) {
5067 if (drm_add_edid_modes(connector, edid)) {
5068 drm_mode_connector_update_edid_property(connector,
5069 edid);
5070 drm_edid_to_eld(connector, edid);
5071 } else {
5072 kfree(edid);
5073 edid = ERR_PTR(-EINVAL);
5074 }
5075 } else {
5076 edid = ERR_PTR(-ENOENT);
5077 }
5078 intel_connector->edid = edid;
5079
5080 /* prefer fixed mode from EDID if available */
5081 list_for_each_entry(scan, &connector->probed_modes, head) {
5082 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5083 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5084 downclock_mode = intel_dp_drrs_init(
5085 intel_dig_port,
5086 intel_connector, fixed_mode);
ed92f0b2
PZ		 5087 break;
5088 }
5089 }
5090
5091 /* fallback to VBT if available for eDP */
5092 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5093 fixed_mode = drm_mode_duplicate(dev,
5094 dev_priv->vbt.lfp_lvds_vbt_mode);
5095 if (fixed_mode)
5096 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5097 }
060c8778 5098 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5099
01527b31
CT		 5100 if (IS_VALLEYVIEW(dev)) {
5101 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5102 register_reboot_notifier(&intel_dp->edp_notifier);
5103 }
5104
4f9db5b5 5105 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5106 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5107 intel_panel_setup_backlight(connector);
5108
5109 return true;
5110}
5111
16c25533 5112bool
f0fec3f2
PZ		 5113intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5114 struct intel_connector *intel_connector)
a4fc5ed6 5115{
f0fec3f2
PZ		 5116 struct drm_connector *connector = &intel_connector->base;
5117 struct intel_dp *intel_dp = &intel_dig_port->dp;
5118 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5119 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5120 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5121 enum port port = intel_dig_port->port;
0095e6dc 5122 struct edp_power_seq power_seq = { 0 };
0b99836f 5123 int type;
a4fc5ed6 5124
a4a5d2f8
VS		 5125 intel_dp->pps_pipe = INVALID_PIPE;
5126
ec5b01dd 5127 /* intel_dp vfuncs */
b6b5e383
DL		 5128 if (INTEL_INFO(dev)->gen >= 9)
5129 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5130 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5131 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5132 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5133 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5134 else if (HAS_PCH_SPLIT(dev))
5135 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5136 else
5137 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5138
b9ca5fad
DL		 5139 if (INTEL_INFO(dev)->gen >= 9)
5140 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5141 else
5142 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5143
0767935e
DV		 5144 /* Preserve the current hw state. */
5145 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5146 intel_dp->attached_connector = intel_connector;
3d3dc149 5147
3b32a35b 5148 if (intel_dp_is_edp(dev, port))
b329530c 5149 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5150 else
5151 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5152
f7d24902
ID		 5153 /*
5154 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5155 * for DP the encoder type can be set by the caller to
5156 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5157 */
5158 if (type == DRM_MODE_CONNECTOR_eDP)
5159 intel_encoder->type = INTEL_OUTPUT_EDP;
5160
e7281eab
ID		 5161 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5162 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5163 port_name(port));
5164
b329530c 5165 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5166 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5167
a4fc5ed6
KP		 5168 connector->interlace_allowed = true;
5169 connector->doublescan_allowed = 0;
5170
f0fec3f2 5171 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5172 edp_panel_vdd_work);
a4fc5ed6 5173
df0e9248 5174 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5175 drm_connector_register(connector);
a4fc5ed6 5176
affa9354 5177 if (HAS_DDI(dev))
bcbc889b
PZ		 5178 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5179 else
5180 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5181 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5182
0b99836f 5183 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5184 switch (port) {
5185 case PORT_A:
1d843f9d 5186 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5187 break;
5188 case PORT_B:
1d843f9d 5189 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5190 break;
5191 case PORT_C:
1d843f9d 5192 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5193 break;
5194 case PORT_D:
1d843f9d 5195 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5196 break;
5197 default:
ad1c0b19 5198 BUG();
5eb08b69
ZW		 5199 }
5200
dada1a9f 5201 if (is_edp(intel_dp)) {
773538e8 5202 pps_lock(intel_dp);
a4a5d2f8
VS		 5203 if (IS_VALLEYVIEW(dev)) {
5204 vlv_initial_power_sequencer_setup(intel_dp);
5205 } else {
5206 intel_dp_init_panel_power_timestamps(intel_dp);
5207 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5208 &power_seq);
5209 }
773538e8 5210 pps_unlock(intel_dp);
dada1a9f 5211 }
0095e6dc 5212
9d1a1031 5213 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5214
0e32b39c
DA		 5215 /* init MST on ports that can support it */
5216 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5217 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5218 intel_dp_mst_encoder_init(intel_dig_port,
5219 intel_connector->base.base.id);
0e32b39c
DA		 5220 }
5221 }
5222
0095e6dc 5223 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5224 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5225 if (is_edp(intel_dp)) {
5226 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5227 /*
5228 * vdd might still be enabled do to the delayed vdd off.
5229 * Make sure vdd is actually turned off here.
5230 */
773538e8 5231 pps_lock(intel_dp);
4be73780 5232 edp_panel_vdd_off_sync(intel_dp);
773538e8 5233 pps_unlock(intel_dp);
15b1d171 5234 }
34ea3d38 5235 drm_connector_unregister(connector);
b2f246a8 5236 drm_connector_cleanup(connector);
16c25533 5237 return false;
b2f246a8 5238 }
32f9d658 5239
f684960e
CW		 5240 intel_dp_add_properties(intel_dp, connector);
5241
a4fc5ed6
KP		 5242 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5243 * 0xd. Failure to do so will result in spurious interrupts being
5244 * generated on the port when a cable is not attached.
5245 */
5246 if (IS_G4X(dev) && !IS_GM45(dev)) {
5247 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5248 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5249 }
16c25533
PZ		 5250
5251 return true;
a4fc5ed6 5252}
f0fec3f2
PZ		 5253
5254void
5255intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5256{
13cf5504 5257 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5258 struct intel_digital_port *intel_dig_port;
5259 struct intel_encoder *intel_encoder;
5260 struct drm_encoder *encoder;
5261 struct intel_connector *intel_connector;
5262
b14c5679 5263 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5264 if (!intel_dig_port)
5265 return;
5266
b14c5679 5267 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5268 if (!intel_connector) {
5269 kfree(intel_dig_port);
5270 return;
5271 }
5272
5273 intel_encoder = &intel_dig_port->base;
5274 encoder = &intel_encoder->base;
5275
5276 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5277 DRM_MODE_ENCODER_TMDS);
5278
5bfe2ac0 5279 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5280 intel_encoder->disable = intel_disable_dp;
00c09d70 5281 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5282 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5283 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5284 if (IS_CHERRYVIEW(dev)) {
9197c88b 5285 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5286 intel_encoder->pre_enable = chv_pre_enable_dp;
5287 intel_encoder->enable = vlv_enable_dp;
580d3811 5288 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5289 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5290 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5291 intel_encoder->pre_enable = vlv_pre_enable_dp;
5292 intel_encoder->enable = vlv_enable_dp;
49277c31 5293 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5294 } else {
ecff4f3b
JN		 5295 intel_encoder->pre_enable = g4x_pre_enable_dp;
5296 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5297 if (INTEL_INFO(dev)->gen >= 5)
5298 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5299 }
f0fec3f2 5300
174edf1f 5301 intel_dig_port->port = port;
f0fec3f2
PZ		 5302 intel_dig_port->dp.output_reg = output_reg;
5303
00c09d70 5304 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5305 if (IS_CHERRYVIEW(dev)) {
5306 if (port == PORT_D)
5307 intel_encoder->crtc_mask = 1 << 2;
5308 else
5309 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5310 } else {
5311 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5312 }
bc079e8b 5313 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5314 intel_encoder->hot_plug = intel_dp_hot_plug;
5315
13cf5504
DA		 5316 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5317 dev_priv->hpd_irq_port[port] = intel_dig_port;
5318
15b1d171
PZ		 5319 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5320 drm_encoder_cleanup(encoder);
5321 kfree(intel_dig_port);
b2f246a8 5322 kfree(intel_connector);
15b1d171 5323 }
f0fec3f2 5324}
0e32b39c
DA		 5325
5326void intel_dp_mst_suspend(struct drm_device *dev)
5327{
5328 struct drm_i915_private *dev_priv = dev->dev_private;
5329 int i;
5330
5331 /* disable MST */
5332 for (i = 0; i < I915_MAX_PORTS; i++) {
5333 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5334 if (!intel_dig_port)
5335 continue;
5336
5337 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5338 if (!intel_dig_port->dp.can_mst)
5339 continue;
5340 if (intel_dig_port->dp.is_mst)
5341 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5342 }
5343 }
5344}
5345
5346void intel_dp_mst_resume(struct drm_device *dev)
5347{
5348 struct drm_i915_private *dev_priv = dev->dev_private;
5349 int i;
5350
5351 for (i = 0; i < I915_MAX_PORTS; i++) {
5352 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5353 if (!intel_dig_port)
5354 continue;
5355 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5356 int ret;
5357
5358 if (!intel_dig_port->dp.can_mst)
5359 continue;
5360
5361 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5362 if (ret != 0) {
5363 intel_dp_check_mst_status(&intel_dig_port->dp);
5364 }
5365 }
5366 }
5367}
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