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drm/i915/skl: Read sink supported rates from edp panel
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
9dd4ffdf
CML		 44struct dp_link_dpll {
45 int link_bw;
46 struct dpll dpll;
47};
48
49static const struct dp_link_dpll gen4_dpll[] = {
50 { DP_LINK_BW_1_62,
51 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
52 { DP_LINK_BW_2_7,
53 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54};
55
56static const struct dp_link_dpll pch_dpll[] = {
57 { DP_LINK_BW_1_62,
58 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
59 { DP_LINK_BW_2_7,
60 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61};
62
65ce4bf5
CML		 63static const struct dp_link_dpll vlv_dpll[] = {
64 { DP_LINK_BW_1_62,
58f6e632 65 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 66 { DP_LINK_BW_2_7,
67 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68};
69
ef9348c8
CML		 70/*
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
73 */
74static const struct dp_link_dpll chv_dpll[] = {
75 /*
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
79 */
80 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
82 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
83 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
84 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
85 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86};
87
cfcb0fc9
JB		 88/**
89 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
90 * @intel_dp: DP struct
91 *
92 * If a CPU or PCH DP output is attached to an eDP panel, this function
93 * will return true, and false otherwise.
94 */
95static bool is_edp(struct intel_dp *intel_dp)
96{
da63a9f2
PZ		 97 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
98
99 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 100}
101
68b4d824 102static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 103{
68b4d824
ID		 104 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
105
106 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 107}
108
df0e9248
CW		 109static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
110{
fa90ecef 111 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 112}
113
ea5b213a 114static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 115static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 116static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 117static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 118static void vlv_steal_power_sequencer(struct drm_device *dev,
119 enum pipe pipe);
a4fc5ed6 120
0e32b39c 121int
ea5b213a 122intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 123{
7183dc29 124 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 125 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 126
127 switch (max_link_bw) {
128 case DP_LINK_BW_1_62:
129 case DP_LINK_BW_2_7:
130 break;
d4eead50 131 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 132 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
133 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 134 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
135 max_link_bw = DP_LINK_BW_5_4;
136 else
137 max_link_bw = DP_LINK_BW_2_7;
d4eead50 138 break;
a4fc5ed6 139 default:
d4eead50
ID		 140 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
141 max_link_bw);
a4fc5ed6
KP		 142 max_link_bw = DP_LINK_BW_1_62;
143 break;
144 }
145 return max_link_bw;
146}
147
eeb6324d
PZ		 148static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
149{
150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
151 struct drm_device *dev = intel_dig_port->base.base.dev;
152 u8 source_max, sink_max;
153
154 source_max = 4;
155 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
156 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
157 source_max = 2;
158
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 202
dd06f90e
JN		 203 if (is_edp(intel_dp) && fixed_mode) {
204 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 205 return MODE_PANEL;
206
dd06f90e 207 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 208 return MODE_PANEL;
03afc4a2
DV		 209
210 target_clock = fixed_mode->clock;
7de56f43
ZY		 211 }
212
36008365 213 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 214 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 215
216 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
217 mode_rate = intel_dp_link_required(target_clock, 18);
218
219 if (mode_rate > max_rate)
c4867936 220 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 221
222 if (mode->clock < 10000)
223 return MODE_CLOCK_LOW;
224
0af78a2b
DV		 225 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
226 return MODE_H_ILLEGAL;
227
a4fc5ed6
KP		 228 return MODE_OK;
229}
230
a4f1289e 231uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 232{
233 int i;
234 uint32_t v = 0;
235
236 if (src_bytes > 4)
237 src_bytes = 4;
238 for (i = 0; i < src_bytes; i++)
239 v |= ((uint32_t) src[i]) << ((3-i) * 8);
240 return v;
241}
242
c2af70e2 243static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 244{
245 int i;
246 if (dst_bytes > 4)
247 dst_bytes = 4;
248 for (i = 0; i < dst_bytes; i++)
249 dst[i] = src >> ((3-i) * 8);
250}
251
fb0f8fbf
KP		 252/* hrawclock is 1/4 the FSB frequency */
253static int
254intel_hrawclk(struct drm_device *dev)
255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 uint32_t clkcfg;
258
9473c8f4
VP		 259 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
260 if (IS_VALLEYVIEW(dev))
261 return 200;
262
fb0f8fbf
KP		 263 clkcfg = I915_READ(CLKCFG);
264 switch (clkcfg & CLKCFG_FSB_MASK) {
265 case CLKCFG_FSB_400:
266 return 100;
267 case CLKCFG_FSB_533:
268 return 133;
269 case CLKCFG_FSB_667:
270 return 166;
271 case CLKCFG_FSB_800:
272 return 200;
273 case CLKCFG_FSB_1067:
274 return 266;
275 case CLKCFG_FSB_1333:
276 return 333;
277 /* these two are just a guess; one of them might be right */
278 case CLKCFG_FSB_1600:
279 case CLKCFG_FSB_1600_ALT:
280 return 400;
281 default:
282 return 133;
283 }
284}
285
bf13e81b
JN		 286static void
287intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 288 struct intel_dp *intel_dp);
bf13e81b
JN		 289static void
290intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 291 struct intel_dp *intel_dp);
bf13e81b 292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
961a0db0
VS		 325static void
326vlv_power_sequencer_kick(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 332 bool pll_enabled;
961a0db0
VS		 333 uint32_t DP;
334
335 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
336 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
337 pipe_name(pipe), port_name(intel_dig_port->port)))
338 return;
339
340 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
341 pipe_name(pipe), port_name(intel_dig_port->port));
342
343 /* Preserve the BIOS-computed detected bit. This is
344 * supposed to be read-only.
345 */
346 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
347 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
348 DP |= DP_PORT_WIDTH(1);
349 DP |= DP_LINK_TRAIN_PAT_1;
350
351 if (IS_CHERRYVIEW(dev))
352 DP |= DP_PIPE_SELECT_CHV(pipe);
353 else if (pipe == PIPE_B)
354 DP |= DP_PIPEB_SELECT;
355
d288f65f
VS		 356 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
357
358 /*
359 * The DPLL for the pipe must be enabled for this to work.
360 * So enable temporarily it if it's not already enabled.
361 */
362 if (!pll_enabled)
363 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
364 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
365
961a0db0
VS		 366 /*
367 * Similar magic as in intel_dp_enable_port().
368 * We _must_ do this port enable + disable trick
369 * to make this power seqeuencer lock onto the port.
370 * Otherwise even VDD force bit won't work.
371 */
372 I915_WRITE(intel_dp->output_reg, DP);
373 POSTING_READ(intel_dp->output_reg);
374
375 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
376 POSTING_READ(intel_dp->output_reg);
377
378 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
379 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 380
381 if (!pll_enabled)
382 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 383}
384
bf13e81b
JN		 385static enum pipe
386vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
387{
388 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 389 struct drm_device *dev = intel_dig_port->base.base.dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 391 struct intel_encoder *encoder;
392 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 393 enum pipe pipe;
bf13e81b 394
e39b999a 395 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 396
a8c3344e
VS		 397 /* We should never land here with regular DP ports */
398 WARN_ON(!is_edp(intel_dp));
399
a4a5d2f8
VS		 400 if (intel_dp->pps_pipe != INVALID_PIPE)
401 return intel_dp->pps_pipe;
402
403 /*
404 * We don't have power sequencer currently.
405 * Pick one that's not used by other ports.
406 */
407 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
408 base.head) {
409 struct intel_dp *tmp;
410
411 if (encoder->type != INTEL_OUTPUT_EDP)
412 continue;
413
414 tmp = enc_to_intel_dp(&encoder->base);
415
416 if (tmp->pps_pipe != INVALID_PIPE)
417 pipes &= ~(1 << tmp->pps_pipe);
418 }
419
420 /*
421 * Didn't find one. This should not happen since there
422 * are two power sequencers and up to two eDP ports.
423 */
424 if (WARN_ON(pipes == 0))
a8c3344e
VS		 425 pipe = PIPE_A;
426 else
427 pipe = ffs(pipes) - 1;
a4a5d2f8 428
a8c3344e
VS		 429 vlv_steal_power_sequencer(dev, pipe);
430 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 431
432 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
433 pipe_name(intel_dp->pps_pipe),
434 port_name(intel_dig_port->port));
435
436 /* init power sequencer on this pipe and port */
36b5f425
VS		 437 intel_dp_init_panel_power_sequencer(dev, intel_dp);
438 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 439
961a0db0
VS		 440 /*
441 * Even vdd force doesn't work until we've made
442 * the power sequencer lock in on the port.
443 */
444 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 445
446 return intel_dp->pps_pipe;
447}
448
6491ab27
VS		 449typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
450 enum pipe pipe);
451
452static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
453 enum pipe pipe)
454{
455 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
456}
457
458static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
459 enum pipe pipe)
460{
461 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
462}
463
464static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
465 enum pipe pipe)
466{
467 return true;
468}
bf13e81b 469
a4a5d2f8 470static enum pipe
6491ab27
VS		 471vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
472 enum port port,
473 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 474{
475 enum pipe pipe;
bf13e81b 476
bf13e81b
JN		 477 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
478 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
479 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 480
481 if (port_sel != PANEL_PORT_SELECT_VLV(port))
482 continue;
483
6491ab27
VS		 484 if (!pipe_check(dev_priv, pipe))
485 continue;
486
a4a5d2f8 487 return pipe;
bf13e81b
JN		 488 }
489
a4a5d2f8
VS		 490 return INVALID_PIPE;
491}
492
493static void
494vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
495{
496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
497 struct drm_device *dev = intel_dig_port->base.base.dev;
498 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 499 enum port port = intel_dig_port->port;
500
501 lockdep_assert_held(&dev_priv->pps_mutex);
502
503 /* try to find a pipe with this port selected */
6491ab27
VS		 504 /* first pick one where the panel is on */
505 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
506 vlv_pipe_has_pp_on);
507 /* didn't find one? pick one where vdd is on */
508 if (intel_dp->pps_pipe == INVALID_PIPE)
509 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
510 vlv_pipe_has_vdd_on);
511 /* didn't find one? pick one with just the correct port */
512 if (intel_dp->pps_pipe == INVALID_PIPE)
513 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
514 vlv_pipe_any);
a4a5d2f8
VS		 515
516 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
517 if (intel_dp->pps_pipe == INVALID_PIPE) {
518 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
519 port_name(port));
520 return;
bf13e81b
JN		 521 }
522
a4a5d2f8
VS		 523 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
524 port_name(port), pipe_name(intel_dp->pps_pipe));
525
36b5f425
VS		 526 intel_dp_init_panel_power_sequencer(dev, intel_dp);
527 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 528}
529
773538e8
VS		 530void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
531{
532 struct drm_device *dev = dev_priv->dev;
533 struct intel_encoder *encoder;
534
535 if (WARN_ON(!IS_VALLEYVIEW(dev)))
536 return;
537
538 /*
539 * We can't grab pps_mutex here due to deadlock with power_domain
540 * mutex when power_domain functions are called while holding pps_mutex.
541 * That also means that in order to use pps_pipe the code needs to
542 * hold both a power domain reference and pps_mutex, and the power domain
543 * reference get/put must be done while _not_ holding pps_mutex.
544 * pps_{lock,unlock}() do these steps in the correct order, so one
545 * should use them always.
546 */
547
548 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
549 struct intel_dp *intel_dp;
550
551 if (encoder->type != INTEL_OUTPUT_EDP)
552 continue;
553
554 intel_dp = enc_to_intel_dp(&encoder->base);
555 intel_dp->pps_pipe = INVALID_PIPE;
556 }
bf13e81b
JN		 557}
558
559static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
560{
561 struct drm_device *dev = intel_dp_to_dev(intel_dp);
562
563 if (HAS_PCH_SPLIT(dev))
564 return PCH_PP_CONTROL;
565 else
566 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
567}
568
569static u32 _pp_stat_reg(struct intel_dp *intel_dp)
570{
571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
572
573 if (HAS_PCH_SPLIT(dev))
574 return PCH_PP_STATUS;
575 else
576 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
577}
578
01527b31
CT		 579/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
580 This function only applicable when panel PM state is not to be tracked */
581static int edp_notify_handler(struct notifier_block *this, unsigned long code,
582 void *unused)
583{
584 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
585 edp_notifier);
586 struct drm_device *dev = intel_dp_to_dev(intel_dp);
587 struct drm_i915_private *dev_priv = dev->dev_private;
588 u32 pp_div;
589 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 590
591 if (!is_edp(intel_dp) || code != SYS_RESTART)
592 return 0;
593
773538e8 594 pps_lock(intel_dp);
e39b999a 595
01527b31 596 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 597 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
598
01527b31
CT		 599 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
600 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
601 pp_div = I915_READ(pp_div_reg);
602 pp_div &= PP_REFERENCE_DIVIDER_MASK;
603
604 /* 0x1F write to PP_DIV_REG sets max cycle delay */
605 I915_WRITE(pp_div_reg, pp_div | 0x1F);
606 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
607 msleep(intel_dp->panel_power_cycle_delay);
608 }
609
773538e8 610 pps_unlock(intel_dp);
e39b999a 611
01527b31
CT		 612 return 0;
613}
614
4be73780 615static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 616{
30add22d 617 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 618 struct drm_i915_private *dev_priv = dev->dev_private;
619
e39b999a
VS		 620 lockdep_assert_held(&dev_priv->pps_mutex);
621
9a42356b
VS		 622 if (IS_VALLEYVIEW(dev) &&
623 intel_dp->pps_pipe == INVALID_PIPE)
624 return false;
625
bf13e81b 626 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 627}
628
4be73780 629static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 630{
30add22d 631 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 632 struct drm_i915_private *dev_priv = dev->dev_private;
633
e39b999a
VS		 634 lockdep_assert_held(&dev_priv->pps_mutex);
635
9a42356b
VS		 636 if (IS_VALLEYVIEW(dev) &&
637 intel_dp->pps_pipe == INVALID_PIPE)
638 return false;
639
773538e8 640 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 641}
642
9b984dae
KP		 643static void
644intel_dp_check_edp(struct intel_dp *intel_dp)
645{
30add22d 646 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 647 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 648
9b984dae
KP		 649 if (!is_edp(intel_dp))
650 return;
453c5420 651
4be73780 652 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 653 WARN(1, "eDP powered off while attempting aux channel communication.\n");
654 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 655 I915_READ(_pp_stat_reg(intel_dp)),
656 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 657 }
658}
659
9ee32fea
DV		 660static uint32_t
661intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
662{
663 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
664 struct drm_device *dev = intel_dig_port->base.base.dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 666 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 667 uint32_t status;
668 bool done;
669
ef04f00d 670#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 671 if (has_aux_irq)
b18ac466 672 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 673 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 674 else
675 done = wait_for_atomic(C, 10) == 0;
676 if (!done)
677 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
678 has_aux_irq);
679#undef C
680
681 return status;
682}
683
ec5b01dd 684static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 685{
174edf1f
PZ		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 688
ec5b01dd
DL		 689 /*
690 * The clock divider is based off the hrawclk, and would like to run at
691 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 692 */
ec5b01dd
DL		 693 return index ? 0 : intel_hrawclk(dev) / 2;
694}
695
696static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
697{
698 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
699 struct drm_device *dev = intel_dig_port->base.base.dev;
700
701 if (index)
702 return 0;
703
704 if (intel_dig_port->port == PORT_A) {
705 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 706 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 707 else
b84a1cf8 708 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 709 } else {
710 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
711 }
712}
713
714static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
715{
716 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
717 struct drm_device *dev = intel_dig_port->base.base.dev;
718 struct drm_i915_private *dev_priv = dev->dev_private;
719
720 if (intel_dig_port->port == PORT_A) {
721 if (index)
722 return 0;
723 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 724 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
725 /* Workaround for non-ULT HSW */
bc86625a
CW		 726 switch (index) {
727 case 0: return 63;
728 case 1: return 72;
729 default: return 0;
730 }
ec5b01dd 731 } else {
bc86625a 732 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 733 }
b84a1cf8
RV		 734}
735
ec5b01dd
DL		 736static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
737{
738 return index ? 0 : 100;
739}
740
b6b5e383
DL		 741static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
742{
743 /*
744 * SKL doesn't need us to program the AUX clock divider (Hardware will
745 * derive the clock from CDCLK automatically). We still implement the
746 * get_aux_clock_divider vfunc to plug-in into the existing code.
747 */
748 return index ? 0 : 1;
749}
750
5ed12a19
DL		 751static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
752 bool has_aux_irq,
753 int send_bytes,
754 uint32_t aux_clock_divider)
755{
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
757 struct drm_device *dev = intel_dig_port->base.base.dev;
758 uint32_t precharge, timeout;
759
760 if (IS_GEN6(dev))
761 precharge = 3;
762 else
763 precharge = 5;
764
765 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
766 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
767 else
768 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
769
770 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 771 DP_AUX_CH_CTL_DONE |
5ed12a19 772 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 773 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 774 timeout |
788d4433 775 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 776 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
777 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 778 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 779}
780
b9ca5fad
DL		 781static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
782 bool has_aux_irq,
783 int send_bytes,
784 uint32_t unused)
785{
786 return DP_AUX_CH_CTL_SEND_BUSY |
787 DP_AUX_CH_CTL_DONE |
788 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
789 DP_AUX_CH_CTL_TIME_OUT_ERROR |
790 DP_AUX_CH_CTL_TIME_OUT_1600us |
791 DP_AUX_CH_CTL_RECEIVE_ERROR |
792 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
793 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
794}
795
b84a1cf8
RV		 796static int
797intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 798 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 799 uint8_t *recv, int recv_size)
800{
801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
802 struct drm_device *dev = intel_dig_port->base.base.dev;
803 struct drm_i915_private *dev_priv = dev->dev_private;
804 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
805 uint32_t ch_data = ch_ctl + 4;
bc86625a 806 uint32_t aux_clock_divider;
b84a1cf8
RV		 807 int i, ret, recv_bytes;
808 uint32_t status;
5ed12a19 809 int try, clock = 0;
4e6b788c 810 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 811 bool vdd;
812
773538e8 813 pps_lock(intel_dp);
e39b999a 814
72c3500a
VS		 815 /*
816 * We will be called with VDD already enabled for dpcd/edid/oui reads.
817 * In such cases we want to leave VDD enabled and it's up to upper layers
818 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
819 * ourselves.
820 */
1e0560e0 821 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 822
823 /* dp aux is extremely sensitive to irq latency, hence request the
824 * lowest possible wakeup latency and so prevent the cpu from going into
825 * deep sleep states.
826 */
827 pm_qos_update_request(&dev_priv->pm_qos, 0);
828
829 intel_dp_check_edp(intel_dp);
5eb08b69 830
c67a470b
PZ		 831 intel_aux_display_runtime_get(dev_priv);
832
11bee43e
JB		 833 /* Try to wait for any previous AUX channel activity */
834 for (try = 0; try < 3; try++) {
ef04f00d 835 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 836 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
837 break;
838 msleep(1);
839 }
840
841 if (try == 3) {
842 WARN(1, "dp_aux_ch not started status 0x%08x\n",
843 I915_READ(ch_ctl));
9ee32fea
DV		 844 ret = -EBUSY;
845 goto out;
4f7f7b7e
CW		 846 }
847
46a5ae9f
PZ		 848 /* Only 5 data registers! */
849 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
850 ret = -E2BIG;
851 goto out;
852 }
853
ec5b01dd 854 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 855 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
856 has_aux_irq,
857 send_bytes,
858 aux_clock_divider);
5ed12a19 859
bc86625a
CW		 860 /* Must try at least 3 times according to DP spec */
861 for (try = 0; try < 5; try++) {
862 /* Load the send data into the aux channel data registers */
863 for (i = 0; i < send_bytes; i += 4)
864 I915_WRITE(ch_data + i,
a4f1289e
RV		 865 intel_dp_pack_aux(send + i,
866 send_bytes - i));
bc86625a
CW		 867
868 /* Send the command and wait for it to complete */
5ed12a19 869 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 870
871 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
872
873 /* Clear done status and any errors */
874 I915_WRITE(ch_ctl,
875 status |
876 DP_AUX_CH_CTL_DONE |
877 DP_AUX_CH_CTL_TIME_OUT_ERROR |
878 DP_AUX_CH_CTL_RECEIVE_ERROR);
879
880 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
881 DP_AUX_CH_CTL_RECEIVE_ERROR))
882 continue;
883 if (status & DP_AUX_CH_CTL_DONE)
884 break;
885 }
4f7f7b7e 886 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 887 break;
888 }
889
a4fc5ed6 890 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 891 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 892 ret = -EBUSY;
893 goto out;
a4fc5ed6
KP		 894 }
895
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
898 */
a5b3da54 899 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 901 ret = -EIO;
902 goto out;
a5b3da54 903 }
1ae8c0a5
KP		 904
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
a5b3da54 907 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 909 ret = -ETIMEDOUT;
910 goto out;
a4fc5ed6
KP		 911 }
912
913 /* Unload any bytes sent back from the other side */
914 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 916 if (recv_bytes > recv_size)
917 recv_bytes = recv_size;
0206e353 918
4f7f7b7e 919 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 920 intel_dp_unpack_aux(I915_READ(ch_data + i),
921 recv + i, recv_bytes - i);
a4fc5ed6 922
9ee32fea
DV		 923 ret = recv_bytes;
924out:
925 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 926 intel_aux_display_runtime_put(dev_priv);
9ee32fea 927
884f19e9
JN		 928 if (vdd)
929 edp_panel_vdd_off(intel_dp, false);
930
773538e8 931 pps_unlock(intel_dp);
e39b999a 932
9ee32fea 933 return ret;
a4fc5ed6
KP		 934}
935
a6c8aff0
JN		 936#define BARE_ADDRESS_SIZE 3
937#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 938static ssize_t
939intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 940{
9d1a1031
JN		 941 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
942 uint8_t txbuf[20], rxbuf[20];
943 size_t txsize, rxsize;
a4fc5ed6 944 int ret;
a4fc5ed6 945
9d1a1031
JN		 946 txbuf[0] = msg->request << 4;
947 txbuf[1] = msg->address >> 8;
948 txbuf[2] = msg->address & 0xff;
949 txbuf[3] = msg->size - 1;
46a5ae9f 950
9d1a1031
JN		 951 switch (msg->request & ~DP_AUX_I2C_MOT) {
952 case DP_AUX_NATIVE_WRITE:
953 case DP_AUX_I2C_WRITE:
a6c8aff0 954 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 955 rxsize = 1;
f51a44b9 956
9d1a1031
JN		 957 if (WARN_ON(txsize > 20))
958 return -E2BIG;
a4fc5ed6 959
9d1a1031 960 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 961
9d1a1031
JN		 962 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
963 if (ret > 0) {
964 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 965
9d1a1031
JN		 966 /* Return payload size. */
967 ret = msg->size;
968 }
969 break;
46a5ae9f 970
9d1a1031
JN		 971 case DP_AUX_NATIVE_READ:
972 case DP_AUX_I2C_READ:
a6c8aff0 973 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 974 rxsize = msg->size + 1;
a4fc5ed6 975
9d1a1031
JN		 976 if (WARN_ON(rxsize > 20))
977 return -E2BIG;
a4fc5ed6 978
9d1a1031
JN		 979 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
980 if (ret > 0) {
981 msg->reply = rxbuf[0] >> 4;
982 /*
983 * Assume happy day, and copy the data. The caller is
984 * expected to check msg->reply before touching it.
985 *
986 * Return payload size.
987 */
988 ret--;
989 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 990 }
9d1a1031
JN		 991 break;
992
993 default:
994 ret = -EINVAL;
995 break;
a4fc5ed6 996 }
f51a44b9 997
9d1a1031 998 return ret;
a4fc5ed6
KP		 999}
1000
9d1a1031
JN		 1001static void
1002intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1003{
1004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1005 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1006 enum port port = intel_dig_port->port;
0b99836f 1007 const char *name = NULL;
ab2c0672
DA		 1008 int ret;
1009
33ad6626
JN		 1010 switch (port) {
1011 case PORT_A:
1012 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1013 name = "DPDDC-A";
ab2c0672 1014 break;
33ad6626
JN		 1015 case PORT_B:
1016 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1017 name = "DPDDC-B";
ab2c0672 1018 break;
33ad6626
JN		 1019 case PORT_C:
1020 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1021 name = "DPDDC-C";
ab2c0672 1022 break;
33ad6626
JN		 1023 case PORT_D:
1024 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1025 name = "DPDDC-D";
33ad6626
JN		 1026 break;
1027 default:
1028 BUG();
ab2c0672
DA		 1029 }
1030
1b1aad75
DL		 1031 /*
1032 * The AUX_CTL register is usually DP_CTL + 0x10.
1033 *
1034 * On Haswell and Broadwell though:
1035 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1036 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1037 *
1038 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1039 */
1040 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1041 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1042
0b99836f 1043 intel_dp->aux.name = name;
9d1a1031
JN		 1044 intel_dp->aux.dev = dev->dev;
1045 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1046
0b99836f
JN		 1047 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1048 connector->base.kdev->kobj.name);
8316f337 1049
4f71d0cb 1050 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1051 if (ret < 0) {
4f71d0cb 1052 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1053 name, ret);
1054 return;
ab2c0672 1055 }
8a5e6aeb 1056
0b99836f
JN		 1057 ret = sysfs_create_link(&connector->base.kdev->kobj,
1058 &intel_dp->aux.ddc.dev.kobj,
1059 intel_dp->aux.ddc.dev.kobj.name);
1060 if (ret < 0) {
1061 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1062 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1063 }
a4fc5ed6
KP		 1064}
1065
80f65de3
ID		 1066static void
1067intel_dp_connector_unregister(struct intel_connector *intel_connector)
1068{
1069 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1070
0e32b39c
DA		 1071 if (!intel_connector->mst_port)
1072 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1073 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1074 intel_connector_unregister(intel_connector);
1075}
1076
5416d871 1077static void
5cec258b 1078skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
5416d871
DL		 1079{
1080 u32 ctrl1;
1081
1082 pipe_config->ddi_pll_sel = SKL_DPLL0;
1083 pipe_config->dpll_hw_state.cfgcr1 = 0;
1084 pipe_config->dpll_hw_state.cfgcr2 = 0;
1085
1086 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1087 switch (link_bw) {
1088 case DP_LINK_BW_1_62:
1089 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1090 SKL_DPLL0);
1091 break;
1092 case DP_LINK_BW_2_7:
1093 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1094 SKL_DPLL0);
1095 break;
1096 case DP_LINK_BW_5_4:
1097 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1098 SKL_DPLL0);
1099 break;
1100 }
1101 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1102}
1103
0e50338c 1104static void
5cec258b 1105hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1106{
1107 switch (link_bw) {
1108 case DP_LINK_BW_1_62:
1109 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1110 break;
1111 case DP_LINK_BW_2_7:
1112 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1113 break;
1114 case DP_LINK_BW_5_4:
1115 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1116 break;
1117 }
1118}
1119
fc0f8e25
SJ		 1120static int
1121intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
1122{
1123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1124 int i = 0;
1125 uint16_t val;
1126
1127 if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
1128 /*
1129 * Receiver supports only main-link rate selection by
1130 * link rate table method, so read link rates from
1131 * supported_link_rates
1132 */
1133 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
1134 val = le16_to_cpu(intel_dp->supported_rates[i]);
1135 if (val == 0)
1136 break;
1137
1138 sink_rates[i] = val * 200;
1139 }
1140
1141 if (i <= 0)
1142 DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
1143 }
1144 return i;
1145}
1146
c6bb3538
DV		 1147static void
1148intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1149 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1150{
1151 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1152 const struct dp_link_dpll *divisor = NULL;
1153 int i, count = 0;
c6bb3538
DV		 1154
1155 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1156 divisor = gen4_dpll;
1157 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1158 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1159 divisor = pch_dpll;
1160 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1161 } else if (IS_CHERRYVIEW(dev)) {
1162 divisor = chv_dpll;
1163 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1164 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1165 divisor = vlv_dpll;
1166 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1167 }
9dd4ffdf
CML		 1168
1169 if (divisor && count) {
1170 for (i = 0; i < count; i++) {
1171 if (link_bw == divisor[i].link_bw) {
1172 pipe_config->dpll = divisor[i].dpll;
1173 pipe_config->clock_set = true;
1174 break;
1175 }
1176 }
c6bb3538
DV		 1177 }
1178}
1179
00c09d70 1180bool
5bfe2ac0 1181intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1182 struct intel_crtc_state *pipe_config)
a4fc5ed6 1183{
5bfe2ac0 1184 struct drm_device *dev = encoder->base.dev;
36008365 1185 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1186 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1187 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1188 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1189 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1190 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1191 int lane_count, clock;
56071a20 1192 int min_lane_count = 1;
eeb6324d 1193 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1194 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1195 int min_clock = 0;
06ea66b6 1196 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1197 int bpp, mode_rate;
06ea66b6 1198 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1199 int link_avail, link_clock;
a4fc5ed6 1200
bc7d38a4 1201 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1202 pipe_config->has_pch_encoder = true;
1203
03afc4a2 1204 pipe_config->has_dp_encoder = true;
f769cd24 1205 pipe_config->has_drrs = false;
9ed109a7 1206 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1207
dd06f90e
JN		 1208 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1209 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1210 adjusted_mode);
2dd24552
JB		 1211 if (!HAS_PCH_SPLIT(dev))
1212 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1213 intel_connector->panel.fitting_mode);
1214 else
b074cec8
JB		 1215 intel_pch_panel_fitting(intel_crtc, pipe_config,
1216 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1217 }
1218
cb1793ce 1219 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1220 return false;
1221
083f9560
DV		 1222 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1223 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1224 max_lane_count, bws[max_clock],
1225 adjusted_mode->crtc_clock);
083f9560 1226
36008365
DV		 1227 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1228 * bpc in between. */
3e7ca985 1229 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1230 if (is_edp(intel_dp)) {
1231 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1232 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1233 dev_priv->vbt.edp_bpp);
1234 bpp = dev_priv->vbt.edp_bpp;
1235 }
1236
344c5bbc
JN		 1237 /*
1238 * Use the maximum clock and number of lanes the eDP panel
1239 * advertizes being capable of. The panels are generally
1240 * designed to support only a single clock and lane
1241 * configuration, and typically these values correspond to the
1242 * native resolution of the panel.
1243 */
1244 min_lane_count = max_lane_count;
1245 min_clock = max_clock;
7984211e 1246 }
657445fe 1247
36008365 1248 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1249 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1250 bpp);
36008365 1251
c6930992
DA		 1252 for (clock = min_clock; clock <= max_clock; clock++) {
1253 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1254 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1255 link_avail = intel_dp_max_data_rate(link_clock,
1256 lane_count);
1257
1258 if (mode_rate <= link_avail) {
1259 goto found;
1260 }
1261 }
1262 }
1263 }
c4867936 1264
36008365 1265 return false;
3685a8f3 1266
36008365 1267found:
55bc60db
VS		 1268 if (intel_dp->color_range_auto) {
1269 /*
1270 * See:
1271 * CEA-861-E - 5.1 Default Encoding Parameters
1272 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1273 */
18316c8c 1274 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1275 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1276 else
1277 intel_dp->color_range = 0;
1278 }
1279
3685a8f3 1280 if (intel_dp->color_range)
50f3b016 1281 pipe_config->limited_color_range = true;
a4fc5ed6 1282
36008365
DV		 1283 intel_dp->link_bw = bws[clock];
1284 intel_dp->lane_count = lane_count;
657445fe 1285 pipe_config->pipe_bpp = bpp;
ff9a6750 1286 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1287
36008365
DV		 1288 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1289 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1290 pipe_config->port_clock, bpp);
36008365
DV		 1291 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1292 mode_rate, link_avail);
a4fc5ed6 1293
03afc4a2 1294 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1295 adjusted_mode->crtc_clock,
1296 pipe_config->port_clock,
03afc4a2 1297 &pipe_config->dp_m_n);
9d1a455b 1298
439d7ac0 1299 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1300 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1301 pipe_config->has_drrs = true;
439d7ac0
PB		 1302 intel_link_compute_m_n(bpp, lane_count,
1303 intel_connector->panel.downclock_mode->clock,
1304 pipe_config->port_clock,
1305 &pipe_config->dp_m2_n2);
1306 }
1307
5416d871
DL		 1308 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1309 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1310 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1311 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1312 else
1313 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1314
03afc4a2 1315 return true;
a4fc5ed6
KP		 1316}
1317
7c62a164 1318static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1319{
7c62a164
DV		 1320 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1321 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1322 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1323 struct drm_i915_private *dev_priv = dev->dev_private;
1324 u32 dpa_ctl;
1325
6e3c9717
ACO		 1326 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1327 crtc->config->port_clock);
ea9b6006
DV		 1328 dpa_ctl = I915_READ(DP_A);
1329 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1330
6e3c9717 1331 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1332 /* For a long time we've carried around a ILK-DevA w/a for the
1333 * 160MHz clock. If we're really unlucky, it's still required.
1334 */
1335 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1336 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1337 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1338 } else {
1339 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1340 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1341 }
1ce17038 1342
ea9b6006
DV		 1343 I915_WRITE(DP_A, dpa_ctl);
1344
1345 POSTING_READ(DP_A);
1346 udelay(500);
1347}
1348
8ac33ed3 1349static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1350{
b934223d 1351 struct drm_device *dev = encoder->base.dev;
417e822d 1352 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1354 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1355 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1356 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1357
417e822d 1358 /*
1a2eb460 1359 * There are four kinds of DP registers:
417e822d
KP		 1360 *
1361 * IBX PCH
1a2eb460
KP		 1362 * SNB CPU
1363 * IVB CPU
417e822d
KP		 1364 * CPT PCH
1365 *
1366 * IBX PCH and CPU are the same for almost everything,
1367 * except that the CPU DP PLL is configured in this
1368 * register
1369 *
1370 * CPT PCH is quite different, having many bits moved
1371 * to the TRANS_DP_CTL register instead. That
1372 * configuration happens (oddly) in ironlake_pch_enable
1373 */
9c9e7927 1374
417e822d
KP		 1375 /* Preserve the BIOS-computed detected bit. This is
1376 * supposed to be read-only.
1377 */
1378 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1379
417e822d 1380 /* Handle DP bits in common between all three register formats */
417e822d 1381 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1382 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1383
6e3c9717 1384 if (crtc->config->has_audio)
ea5b213a 1385 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1386
417e822d 1387 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1388
bc7d38a4 1389 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1390 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1391 intel_dp->DP |= DP_SYNC_HS_HIGH;
1392 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1393 intel_dp->DP |= DP_SYNC_VS_HIGH;
1394 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1395
6aba5b6c 1396 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1397 intel_dp->DP |= DP_ENHANCED_FRAMING;
1398
7c62a164 1399 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1400 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1401 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1402 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1403
1404 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1405 intel_dp->DP |= DP_SYNC_HS_HIGH;
1406 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1407 intel_dp->DP |= DP_SYNC_VS_HIGH;
1408 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1409
6aba5b6c 1410 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1411 intel_dp->DP |= DP_ENHANCED_FRAMING;
1412
44f37d1f
CML		 1413 if (!IS_CHERRYVIEW(dev)) {
1414 if (crtc->pipe == 1)
1415 intel_dp->DP |= DP_PIPEB_SELECT;
1416 } else {
1417 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1418 }
417e822d
KP		 1419 } else {
1420 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1421 }
a4fc5ed6
KP		 1422}
1423
ffd6749d
PZ		 1424#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1425#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1426
1a5ef5b7
PZ		 1427#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1428#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1429
ffd6749d
PZ		 1430#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1431#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1432
4be73780 1433static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1434 u32 mask,
1435 u32 value)
bd943159 1436{
30add22d 1437 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1438 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1439 u32 pp_stat_reg, pp_ctrl_reg;
1440
e39b999a
VS		 1441 lockdep_assert_held(&dev_priv->pps_mutex);
1442
bf13e81b
JN		 1443 pp_stat_reg = _pp_stat_reg(intel_dp);
1444 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1445
99ea7127 1446 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1447 mask, value,
1448 I915_READ(pp_stat_reg),
1449 I915_READ(pp_ctrl_reg));
32ce697c 1450
453c5420 1451 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1452 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1453 I915_READ(pp_stat_reg),
1454 I915_READ(pp_ctrl_reg));
32ce697c 1455 }
54c136d4
CW		 1456
1457 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1458}
32ce697c 1459
4be73780 1460static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1461{
1462 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1463 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1464}
1465
4be73780 1466static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1467{
1468 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1469 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1470}
1471
4be73780 1472static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1473{
1474 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1475
1476 /* When we disable the VDD override bit last we have to do the manual
1477 * wait. */
1478 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1479 intel_dp->panel_power_cycle_delay);
1480
4be73780 1481 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1482}
1483
4be73780 1484static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1485{
1486 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1487 intel_dp->backlight_on_delay);
1488}
1489
4be73780 1490static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1491{
1492 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1493 intel_dp->backlight_off_delay);
1494}
99ea7127 1495
832dd3c1
KP		 1496/* Read the current pp_control value, unlocking the register if it
1497 * is locked
1498 */
1499
453c5420 1500static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1501{
453c5420
JB		 1502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 u32 control;
832dd3c1 1505
e39b999a
VS		 1506 lockdep_assert_held(&dev_priv->pps_mutex);
1507
bf13e81b 1508 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1509 control &= ~PANEL_UNLOCK_MASK;
1510 control |= PANEL_UNLOCK_REGS;
1511 return control;
bd943159
KP		 1512}
1513
951468f3
VS		 1514/*
1515 * Must be paired with edp_panel_vdd_off().
1516 * Must hold pps_mutex around the whole on/off sequence.
1517 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1518 */
1e0560e0 1519static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1520{
30add22d 1521 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1522 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1523 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1524 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1525 enum intel_display_power_domain power_domain;
5d613501 1526 u32 pp;
453c5420 1527 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1528 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1529
e39b999a
VS		 1530 lockdep_assert_held(&dev_priv->pps_mutex);
1531
97af61f5 1532 if (!is_edp(intel_dp))
adddaaf4 1533 return false;
bd943159 1534
2c623c11 1535 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1536 intel_dp->want_panel_vdd = true;
99ea7127 1537
4be73780 1538 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1539 return need_to_disable;
b0665d57 1540
4e6e1a54
ID		 1541 power_domain = intel_display_port_power_domain(intel_encoder);
1542 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1543
3936fcf4
VS		 1544 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1545 port_name(intel_dig_port->port));
bd943159 1546
4be73780
DV		 1547 if (!edp_have_panel_power(intel_dp))
1548 wait_panel_power_cycle(intel_dp);
99ea7127 1549
453c5420 1550 pp = ironlake_get_pp_control(intel_dp);
5d613501 1551 pp |= EDP_FORCE_VDD;
ebf33b18 1552
bf13e81b
JN		 1553 pp_stat_reg = _pp_stat_reg(intel_dp);
1554 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1555
1556 I915_WRITE(pp_ctrl_reg, pp);
1557 POSTING_READ(pp_ctrl_reg);
1558 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1559 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1560 /*
1561 * If the panel wasn't on, delay before accessing aux channel
1562 */
4be73780 1563 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1564 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1565 port_name(intel_dig_port->port));
f01eca2e 1566 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1567 }
adddaaf4
JN		 1568
1569 return need_to_disable;
1570}
1571
951468f3
VS		 1572/*
1573 * Must be paired with intel_edp_panel_vdd_off() or
1574 * intel_edp_panel_off().
1575 * Nested calls to these functions are not allowed since
1576 * we drop the lock. Caller must use some higher level
1577 * locking to prevent nested calls from other threads.
1578 */
b80d6c78 1579void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1580{
c695b6b6 1581 bool vdd;
adddaaf4 1582
c695b6b6
VS		 1583 if (!is_edp(intel_dp))
1584 return;
1585
773538e8 1586 pps_lock(intel_dp);
c695b6b6 1587 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1588 pps_unlock(intel_dp);
c695b6b6 1589
e2c719b7 1590 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1591 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1592}
1593
4be73780 1594static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1595{
30add22d 1596 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1597 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1598 struct intel_digital_port *intel_dig_port =
1599 dp_to_dig_port(intel_dp);
1600 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1601 enum intel_display_power_domain power_domain;
5d613501 1602 u32 pp;
453c5420 1603 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1604
e39b999a 1605 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1606
15e899a0 1607 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1608
15e899a0 1609 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1610 return;
b0665d57 1611
3936fcf4
VS		 1612 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1613 port_name(intel_dig_port->port));
bd943159 1614
be2c9196
VS		 1615 pp = ironlake_get_pp_control(intel_dp);
1616 pp &= ~EDP_FORCE_VDD;
453c5420 1617
be2c9196
VS		 1618 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1619 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1620
be2c9196
VS		 1621 I915_WRITE(pp_ctrl_reg, pp);
1622 POSTING_READ(pp_ctrl_reg);
90791a5c 1623
be2c9196
VS		 1624 /* Make sure sequencer is idle before allowing subsequent activity */
1625 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1626 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1627
be2c9196
VS		 1628 if ((pp & POWER_TARGET_ON) == 0)
1629 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1630
be2c9196
VS		 1631 power_domain = intel_display_port_power_domain(intel_encoder);
1632 intel_display_power_put(dev_priv, power_domain);
bd943159 1633}
5d613501 1634
4be73780 1635static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1636{
1637 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1638 struct intel_dp, panel_vdd_work);
bd943159 1639
773538e8 1640 pps_lock(intel_dp);
15e899a0
VS		 1641 if (!intel_dp->want_panel_vdd)
1642 edp_panel_vdd_off_sync(intel_dp);
773538e8 1643 pps_unlock(intel_dp);
bd943159
KP		 1644}
1645
aba86890
ID		 1646static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1647{
1648 unsigned long delay;
1649
1650 /*
1651 * Queue the timer to fire a long time from now (relative to the power
1652 * down delay) to keep the panel power up across a sequence of
1653 * operations.
1654 */
1655 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1656 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1657}
1658
951468f3
VS		 1659/*
1660 * Must be paired with edp_panel_vdd_on().
1661 * Must hold pps_mutex around the whole on/off sequence.
1662 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1663 */
4be73780 1664static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1665{
e39b999a
VS		 1666 struct drm_i915_private *dev_priv =
1667 intel_dp_to_dev(intel_dp)->dev_private;
1668
1669 lockdep_assert_held(&dev_priv->pps_mutex);
1670
97af61f5
KP		 1671 if (!is_edp(intel_dp))
1672 return;
5d613501 1673
e2c719b7 1674 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1675 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1676
bd943159
KP		 1677 intel_dp->want_panel_vdd = false;
1678
aba86890 1679 if (sync)
4be73780 1680 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1681 else
1682 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1683}
1684
9f0fb5be 1685static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1686{
30add22d 1687 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1688 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1689 u32 pp;
453c5420 1690 u32 pp_ctrl_reg;
9934c132 1691
9f0fb5be
VS		 1692 lockdep_assert_held(&dev_priv->pps_mutex);
1693
97af61f5 1694 if (!is_edp(intel_dp))
bd943159 1695 return;
99ea7127 1696
3936fcf4
VS		 1697 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1698 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1699
e7a89ace
VS		 1700 if (WARN(edp_have_panel_power(intel_dp),
1701 "eDP port %c panel power already on\n",
1702 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1703 return;
9934c132 1704
4be73780 1705 wait_panel_power_cycle(intel_dp);
37c6c9b0 1706
bf13e81b 1707 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1708 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1709 if (IS_GEN5(dev)) {
1710 /* ILK workaround: disable reset around power sequence */
1711 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1712 I915_WRITE(pp_ctrl_reg, pp);
1713 POSTING_READ(pp_ctrl_reg);
05ce1a49 1714 }
37c6c9b0 1715
1c0ae80a 1716 pp |= POWER_TARGET_ON;
99ea7127
KP		 1717 if (!IS_GEN5(dev))
1718 pp |= PANEL_POWER_RESET;
1719
453c5420
JB		 1720 I915_WRITE(pp_ctrl_reg, pp);
1721 POSTING_READ(pp_ctrl_reg);
9934c132 1722
4be73780 1723 wait_panel_on(intel_dp);
dce56b3c 1724 intel_dp->last_power_on = jiffies;
9934c132 1725
05ce1a49
KP		 1726 if (IS_GEN5(dev)) {
1727 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1728 I915_WRITE(pp_ctrl_reg, pp);
1729 POSTING_READ(pp_ctrl_reg);
05ce1a49 1730 }
9f0fb5be 1731}
e39b999a 1732
9f0fb5be
VS		 1733void intel_edp_panel_on(struct intel_dp *intel_dp)
1734{
1735 if (!is_edp(intel_dp))
1736 return;
1737
1738 pps_lock(intel_dp);
1739 edp_panel_on(intel_dp);
773538e8 1740 pps_unlock(intel_dp);
9934c132
JB		 1741}
1742
9f0fb5be
VS		 1743
1744static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1745{
4e6e1a54
ID		 1746 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1747 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1748 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1749 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1750 enum intel_display_power_domain power_domain;
99ea7127 1751 u32 pp;
453c5420 1752 u32 pp_ctrl_reg;
9934c132 1753
9f0fb5be
VS		 1754 lockdep_assert_held(&dev_priv->pps_mutex);
1755
97af61f5
KP		 1756 if (!is_edp(intel_dp))
1757 return;
37c6c9b0 1758
3936fcf4
VS		 1759 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1760 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1761
3936fcf4
VS		 1762 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1763 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1764
453c5420 1765 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1766 /* We need to switch off panel power _and_ force vdd, for otherwise some
1767 * panels get very unhappy and cease to work. */
b3064154
PJ		 1768 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1769 EDP_BLC_ENABLE);
453c5420 1770
bf13e81b 1771 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1772
849e39f5
PZ		 1773 intel_dp->want_panel_vdd = false;
1774
453c5420
JB		 1775 I915_WRITE(pp_ctrl_reg, pp);
1776 POSTING_READ(pp_ctrl_reg);
9934c132 1777
dce56b3c 1778 intel_dp->last_power_cycle = jiffies;
4be73780 1779 wait_panel_off(intel_dp);
849e39f5
PZ		 1780
1781 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1782 power_domain = intel_display_port_power_domain(intel_encoder);
1783 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1784}
e39b999a 1785
9f0fb5be
VS		 1786void intel_edp_panel_off(struct intel_dp *intel_dp)
1787{
1788 if (!is_edp(intel_dp))
1789 return;
e39b999a 1790
9f0fb5be
VS		 1791 pps_lock(intel_dp);
1792 edp_panel_off(intel_dp);
773538e8 1793 pps_unlock(intel_dp);
9934c132
JB		 1794}
1795
1250d107
JN		 1796/* Enable backlight in the panel power control. */
1797static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1798{
da63a9f2
PZ		 1799 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1800 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1801 struct drm_i915_private *dev_priv = dev->dev_private;
1802 u32 pp;
453c5420 1803 u32 pp_ctrl_reg;
32f9d658 1804
01cb9ea6
JB		 1805 /*
1806 * If we enable the backlight right away following a panel power
1807 * on, we may see slight flicker as the panel syncs with the eDP
1808 * link. So delay a bit to make sure the image is solid before
1809 * allowing it to appear.
1810 */
4be73780 1811 wait_backlight_on(intel_dp);
e39b999a 1812
773538e8 1813 pps_lock(intel_dp);
e39b999a 1814
453c5420 1815 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1816 pp |= EDP_BLC_ENABLE;
453c5420 1817
bf13e81b 1818 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1819
1820 I915_WRITE(pp_ctrl_reg, pp);
1821 POSTING_READ(pp_ctrl_reg);
e39b999a 1822
773538e8 1823 pps_unlock(intel_dp);
32f9d658
ZW		 1824}
1825
1250d107
JN		 1826/* Enable backlight PWM and backlight PP control. */
1827void intel_edp_backlight_on(struct intel_dp *intel_dp)
1828{
1829 if (!is_edp(intel_dp))
1830 return;
1831
1832 DRM_DEBUG_KMS("\n");
1833
1834 intel_panel_enable_backlight(intel_dp->attached_connector);
1835 _intel_edp_backlight_on(intel_dp);
1836}
1837
1838/* Disable backlight in the panel power control. */
1839static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1840{
30add22d 1841 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 u32 pp;
453c5420 1844 u32 pp_ctrl_reg;
32f9d658 1845
f01eca2e
KP		 1846 if (!is_edp(intel_dp))
1847 return;
1848
773538e8 1849 pps_lock(intel_dp);
e39b999a 1850
453c5420 1851 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1852 pp &= ~EDP_BLC_ENABLE;
453c5420 1853
bf13e81b 1854 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1855
1856 I915_WRITE(pp_ctrl_reg, pp);
1857 POSTING_READ(pp_ctrl_reg);
f7d2323c 1858
773538e8 1859 pps_unlock(intel_dp);
e39b999a
VS		 1860
1861 intel_dp->last_backlight_off = jiffies;
f7d2323c 1862 edp_wait_backlight_off(intel_dp);
1250d107 1863}
f7d2323c 1864
1250d107
JN		 1865/* Disable backlight PP control and backlight PWM. */
1866void intel_edp_backlight_off(struct intel_dp *intel_dp)
1867{
1868 if (!is_edp(intel_dp))
1869 return;
1870
1871 DRM_DEBUG_KMS("\n");
f7d2323c 1872
1250d107 1873 _intel_edp_backlight_off(intel_dp);
f7d2323c 1874 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1875}
a4fc5ed6 1876
73580fb7
JN		 1877/*
1878 * Hook for controlling the panel power control backlight through the bl_power
1879 * sysfs attribute. Take care to handle multiple calls.
1880 */
1881static void intel_edp_backlight_power(struct intel_connector *connector,
1882 bool enable)
1883{
1884 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1885 bool is_enabled;
1886
773538e8 1887 pps_lock(intel_dp);
e39b999a 1888 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1889 pps_unlock(intel_dp);
73580fb7
JN		 1890
1891 if (is_enabled == enable)
1892 return;
1893
23ba9373
JN		 1894 DRM_DEBUG_KMS("panel power control backlight %s\n",
1895 enable ? "enable" : "disable");
73580fb7
JN		 1896
1897 if (enable)
1898 _intel_edp_backlight_on(intel_dp);
1899 else
1900 _intel_edp_backlight_off(intel_dp);
1901}
1902
2bd2ad64 1903static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1904{
da63a9f2
PZ		 1905 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1906 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1907 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1908 struct drm_i915_private *dev_priv = dev->dev_private;
1909 u32 dpa_ctl;
1910
2bd2ad64
DV		 1911 assert_pipe_disabled(dev_priv,
1912 to_intel_crtc(crtc)->pipe);
1913
d240f20f
JB		 1914 DRM_DEBUG_KMS("\n");
1915 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1916 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1917 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1918
1919 /* We don't adjust intel_dp->DP while tearing down the link, to
1920 * facilitate link retraining (e.g. after hotplug). Hence clear all
1921 * enable bits here to ensure that we don't enable too much. */
1922 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1923 intel_dp->DP |= DP_PLL_ENABLE;
1924 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1925 POSTING_READ(DP_A);
1926 udelay(200);
d240f20f
JB		 1927}
1928
2bd2ad64 1929static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1930{
da63a9f2
PZ		 1931 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1932 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1933 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1934 struct drm_i915_private *dev_priv = dev->dev_private;
1935 u32 dpa_ctl;
1936
2bd2ad64
DV		 1937 assert_pipe_disabled(dev_priv,
1938 to_intel_crtc(crtc)->pipe);
1939
d240f20f 1940 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1941 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1942 "dp pll off, should be on\n");
1943 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1944
1945 /* We can't rely on the value tracked for the DP register in
1946 * intel_dp->DP because link_down must not change that (otherwise link
1947 * re-training will fail. */
298b0b39 1948 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1949 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1950 POSTING_READ(DP_A);
d240f20f
JB		 1951 udelay(200);
1952}
1953
c7ad3810 1954/* If the sink supports it, try to set the power state appropriately */
c19b0669 1955void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1956{
1957 int ret, i;
1958
1959 /* Should have a valid DPCD by this point */
1960 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1961 return;
1962
1963 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1964 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1965 DP_SET_POWER_D3);
c7ad3810
JB		 1966 } else {
1967 /*
1968 * When turning on, we need to retry for 1ms to give the sink
1969 * time to wake up.
1970 */
1971 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1972 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1973 DP_SET_POWER_D0);
c7ad3810
JB		 1974 if (ret == 1)
1975 break;
1976 msleep(1);
1977 }
1978 }
f9cac721
JN		 1979
1980 if (ret != 1)
1981 DRM_DEBUG_KMS("failed to %s sink power state\n",
1982 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1983}
1984
19d8fe15
DV		 1985static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1986 enum pipe *pipe)
d240f20f 1987{
19d8fe15 1988 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1989 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1990 struct drm_device *dev = encoder->base.dev;
1991 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1992 enum intel_display_power_domain power_domain;
1993 u32 tmp;
1994
1995 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1996 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1997 return false;
1998
1999 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2000
2001 if (!(tmp & DP_PORT_EN))
2002 return false;
2003
bc7d38a4 2004 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 2005 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 2006 } else if (IS_CHERRYVIEW(dev)) {
2007 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 2008 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 2009 *pipe = PORT_TO_PIPE(tmp);
2010 } else {
2011 u32 trans_sel;
2012 u32 trans_dp;
2013 int i;
2014
2015 switch (intel_dp->output_reg) {
2016 case PCH_DP_B:
2017 trans_sel = TRANS_DP_PORT_SEL_B;
2018 break;
2019 case PCH_DP_C:
2020 trans_sel = TRANS_DP_PORT_SEL_C;
2021 break;
2022 case PCH_DP_D:
2023 trans_sel = TRANS_DP_PORT_SEL_D;
2024 break;
2025 default:
2026 return true;
2027 }
2028
055e393f 2029 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2030 trans_dp = I915_READ(TRANS_DP_CTL(i));
2031 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2032 *pipe = i;
2033 return true;
2034 }
2035 }
19d8fe15 2036
4a0833ec
DV		 2037 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2038 intel_dp->output_reg);
2039 }
d240f20f 2040
19d8fe15
DV		 2041 return true;
2042}
d240f20f 2043
045ac3b5 2044static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2045 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2046{
2047 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2048 u32 tmp, flags = 0;
63000ef6
XZ		 2049 struct drm_device *dev = encoder->base.dev;
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 enum port port = dp_to_dig_port(intel_dp)->port;
2052 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2053 int dotclock;
045ac3b5 2054
9ed109a7
DV		 2055 tmp = I915_READ(intel_dp->output_reg);
2056 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2057 pipe_config->has_audio = true;
2058
63000ef6 2059 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2060 if (tmp & DP_SYNC_HS_HIGH)
2061 flags |= DRM_MODE_FLAG_PHSYNC;
2062 else
2063 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2064
63000ef6
XZ		 2065 if (tmp & DP_SYNC_VS_HIGH)
2066 flags |= DRM_MODE_FLAG_PVSYNC;
2067 else
2068 flags |= DRM_MODE_FLAG_NVSYNC;
2069 } else {
2070 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2071 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2072 flags |= DRM_MODE_FLAG_PHSYNC;
2073 else
2074 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2075
63000ef6
XZ		 2076 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2077 flags |= DRM_MODE_FLAG_PVSYNC;
2078 else
2079 flags |= DRM_MODE_FLAG_NVSYNC;
2080 }
045ac3b5 2081
2d112de7 2082 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2083
8c875fca
VS		 2084 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2085 tmp & DP_COLOR_RANGE_16_235)
2086 pipe_config->limited_color_range = true;
2087
eb14cb74
VS		 2088 pipe_config->has_dp_encoder = true;
2089
2090 intel_dp_get_m_n(crtc, pipe_config);
2091
18442d08 2092 if (port == PORT_A) {
f1f644dc
JB		 2093 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2094 pipe_config->port_clock = 162000;
2095 else
2096 pipe_config->port_clock = 270000;
2097 }
18442d08
VS		 2098
2099 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2100 &pipe_config->dp_m_n);
2101
2102 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2103 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2104
2d112de7 2105 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2106
c6cd2ee2
JN		 2107 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2108 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2109 /*
2110 * This is a big fat ugly hack.
2111 *
2112 * Some machines in UEFI boot mode provide us a VBT that has 18
2113 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2114 * unknown we fail to light up. Yet the same BIOS boots up with
2115 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2116 * max, not what it tells us to use.
2117 *
2118 * Note: This will still be broken if the eDP panel is not lit
2119 * up by the BIOS, and thus we can't get the mode at module
2120 * load.
2121 */
2122 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2123 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2124 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2125 }
045ac3b5
JB		 2126}
2127
e8cb4558 2128static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2129{
e8cb4558 2130 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2131 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2132 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2133
6e3c9717 2134 if (crtc->config->has_audio)
495a5bb8 2135 intel_audio_codec_disable(encoder);
6cb49835 2136
b32c6f48
RV		 2137 if (HAS_PSR(dev) && !HAS_DDI(dev))
2138 intel_psr_disable(intel_dp);
2139
6cb49835
DV		 2140 /* Make sure the panel is off before trying to change the mode. But also
2141 * ensure that we have vdd while we switch off the panel. */
24f3e092 2142 intel_edp_panel_vdd_on(intel_dp);
4be73780 2143 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2144 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2145 intel_edp_panel_off(intel_dp);
3739850b 2146
08aff3fe
VS		 2147 /* disable the port before the pipe on g4x */
2148 if (INTEL_INFO(dev)->gen < 5)
3739850b 2149 intel_dp_link_down(intel_dp);
d240f20f
JB		 2150}
2151
08aff3fe 2152static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2153{
2bd2ad64 2154 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2155 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2156
49277c31 2157 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2158 if (port == PORT_A)
2159 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2160}
2161
2162static void vlv_post_disable_dp(struct intel_encoder *encoder)
2163{
2164 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2165
2166 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2167}
2168
580d3811
VS		 2169static void chv_post_disable_dp(struct intel_encoder *encoder)
2170{
2171 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2172 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2173 struct drm_device *dev = encoder->base.dev;
2174 struct drm_i915_private *dev_priv = dev->dev_private;
2175 struct intel_crtc *intel_crtc =
2176 to_intel_crtc(encoder->base.crtc);
2177 enum dpio_channel ch = vlv_dport_to_channel(dport);
2178 enum pipe pipe = intel_crtc->pipe;
2179 u32 val;
2180
2181 intel_dp_link_down(intel_dp);
2182
2183 mutex_lock(&dev_priv->dpio_lock);
2184
2185 /* Propagate soft reset to data lane reset */
97fd4d5c 2186 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2187 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2188 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2189
97fd4d5c
VS		 2190 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2191 val |= CHV_PCS_REQ_SOFTRESET_EN;
2192 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2193
2194 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2195 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2196 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2197
2198 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2199 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2200 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2201
2202 mutex_unlock(&dev_priv->dpio_lock);
2203}
2204
7b13b58a
VS		 2205static void
2206_intel_dp_set_link_train(struct intel_dp *intel_dp,
2207 uint32_t *DP,
2208 uint8_t dp_train_pat)
2209{
2210 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2211 struct drm_device *dev = intel_dig_port->base.base.dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 enum port port = intel_dig_port->port;
2214
2215 if (HAS_DDI(dev)) {
2216 uint32_t temp = I915_READ(DP_TP_CTL(port));
2217
2218 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2219 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2220 else
2221 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2222
2223 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2224 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2225 case DP_TRAINING_PATTERN_DISABLE:
2226 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2227
2228 break;
2229 case DP_TRAINING_PATTERN_1:
2230 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2231 break;
2232 case DP_TRAINING_PATTERN_2:
2233 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2234 break;
2235 case DP_TRAINING_PATTERN_3:
2236 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2237 break;
2238 }
2239 I915_WRITE(DP_TP_CTL(port), temp);
2240
2241 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2242 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2243
2244 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2245 case DP_TRAINING_PATTERN_DISABLE:
2246 *DP |= DP_LINK_TRAIN_OFF_CPT;
2247 break;
2248 case DP_TRAINING_PATTERN_1:
2249 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2250 break;
2251 case DP_TRAINING_PATTERN_2:
2252 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2253 break;
2254 case DP_TRAINING_PATTERN_3:
2255 DRM_ERROR("DP training pattern 3 not supported\n");
2256 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2257 break;
2258 }
2259
2260 } else {
2261 if (IS_CHERRYVIEW(dev))
2262 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2263 else
2264 *DP &= ~DP_LINK_TRAIN_MASK;
2265
2266 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2267 case DP_TRAINING_PATTERN_DISABLE:
2268 *DP |= DP_LINK_TRAIN_OFF;
2269 break;
2270 case DP_TRAINING_PATTERN_1:
2271 *DP |= DP_LINK_TRAIN_PAT_1;
2272 break;
2273 case DP_TRAINING_PATTERN_2:
2274 *DP |= DP_LINK_TRAIN_PAT_2;
2275 break;
2276 case DP_TRAINING_PATTERN_3:
2277 if (IS_CHERRYVIEW(dev)) {
2278 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2279 } else {
2280 DRM_ERROR("DP training pattern 3 not supported\n");
2281 *DP |= DP_LINK_TRAIN_PAT_2;
2282 }
2283 break;
2284 }
2285 }
2286}
2287
2288static void intel_dp_enable_port(struct intel_dp *intel_dp)
2289{
2290 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292
7b13b58a
VS		 2293 /* enable with pattern 1 (as per spec) */
2294 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2295 DP_TRAINING_PATTERN_1);
2296
2297 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2298 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2299
2300 /*
2301 * Magic for VLV/CHV. We _must_ first set up the register
2302 * without actually enabling the port, and then do another
2303 * write to enable the port. Otherwise link training will
2304 * fail when the power sequencer is freshly used for this port.
2305 */
2306 intel_dp->DP |= DP_PORT_EN;
2307
2308 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2309 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2310}
2311
e8cb4558 2312static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2313{
e8cb4558
DV		 2314 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2315 struct drm_device *dev = encoder->base.dev;
2316 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2317 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2318 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2319
0c33d8d7
DV		 2320 if (WARN_ON(dp_reg & DP_PORT_EN))
2321 return;
5d613501 2322
093e3f13
VS		 2323 pps_lock(intel_dp);
2324
2325 if (IS_VALLEYVIEW(dev))
2326 vlv_init_panel_power_sequencer(intel_dp);
2327
7b13b58a 2328 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2329
2330 edp_panel_vdd_on(intel_dp);
2331 edp_panel_on(intel_dp);
2332 edp_panel_vdd_off(intel_dp, true);
2333
2334 pps_unlock(intel_dp);
2335
61234fa5
VS		 2336 if (IS_VALLEYVIEW(dev))
2337 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2338
f01eca2e 2339 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2340 intel_dp_start_link_train(intel_dp);
33a34e4e 2341 intel_dp_complete_link_train(intel_dp);
3ab9c637 2342 intel_dp_stop_link_train(intel_dp);
c1dec79a 2343
6e3c9717 2344 if (crtc->config->has_audio) {
c1dec79a
JN		 2345 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2346 pipe_name(crtc->pipe));
2347 intel_audio_codec_enable(encoder);
2348 }
ab1f90f9 2349}
89b667f8 2350
ecff4f3b
JN		 2351static void g4x_enable_dp(struct intel_encoder *encoder)
2352{
828f5c6e
JN		 2353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2354
ecff4f3b 2355 intel_enable_dp(encoder);
4be73780 2356 intel_edp_backlight_on(intel_dp);
ab1f90f9 2357}
89b667f8 2358
ab1f90f9
JN		 2359static void vlv_enable_dp(struct intel_encoder *encoder)
2360{
828f5c6e
JN		 2361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2362
4be73780 2363 intel_edp_backlight_on(intel_dp);
b32c6f48 2364 intel_psr_enable(intel_dp);
d240f20f
JB		 2365}
2366
ecff4f3b 2367static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2368{
2369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2370 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2371
8ac33ed3
DV		 2372 intel_dp_prepare(encoder);
2373
d41f1efb
DV		 2374 /* Only ilk+ has port A */
2375 if (dport->port == PORT_A) {
2376 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2377 ironlake_edp_pll_on(intel_dp);
d41f1efb 2378 }
ab1f90f9
JN		 2379}
2380
83b84597
VS		 2381static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2382{
2383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2384 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2385 enum pipe pipe = intel_dp->pps_pipe;
2386 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2387
2388 edp_panel_vdd_off_sync(intel_dp);
2389
2390 /*
2391 * VLV seems to get confused when multiple power seqeuencers
2392 * have the same port selected (even if only one has power/vdd
2393 * enabled). The failure manifests as vlv_wait_port_ready() failing
2394 * CHV on the other hand doesn't seem to mind having the same port
2395 * selected in multiple power seqeuencers, but let's clear the
2396 * port select always when logically disconnecting a power sequencer
2397 * from a port.
2398 */
2399 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2400 pipe_name(pipe), port_name(intel_dig_port->port));
2401 I915_WRITE(pp_on_reg, 0);
2402 POSTING_READ(pp_on_reg);
2403
2404 intel_dp->pps_pipe = INVALID_PIPE;
2405}
2406
a4a5d2f8
VS		 2407static void vlv_steal_power_sequencer(struct drm_device *dev,
2408 enum pipe pipe)
2409{
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_encoder *encoder;
2412
2413 lockdep_assert_held(&dev_priv->pps_mutex);
2414
ac3c12e4
VS		 2415 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2416 return;
2417
a4a5d2f8
VS		 2418 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2419 base.head) {
2420 struct intel_dp *intel_dp;
773538e8 2421 enum port port;
a4a5d2f8
VS		 2422
2423 if (encoder->type != INTEL_OUTPUT_EDP)
2424 continue;
2425
2426 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2427 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2428
2429 if (intel_dp->pps_pipe != pipe)
2430 continue;
2431
2432 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2433 pipe_name(pipe), port_name(port));
a4a5d2f8 2434
034e43c6
VS		 2435 WARN(encoder->connectors_active,
2436 "stealing pipe %c power sequencer from active eDP port %c\n",
2437 pipe_name(pipe), port_name(port));
a4a5d2f8 2438
a4a5d2f8 2439 /* make sure vdd is off before we steal it */
83b84597 2440 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2441 }
2442}
2443
2444static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2445{
2446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2447 struct intel_encoder *encoder = &intel_dig_port->base;
2448 struct drm_device *dev = encoder->base.dev;
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2451
2452 lockdep_assert_held(&dev_priv->pps_mutex);
2453
093e3f13
VS		 2454 if (!is_edp(intel_dp))
2455 return;
2456
a4a5d2f8
VS		 2457 if (intel_dp->pps_pipe == crtc->pipe)
2458 return;
2459
2460 /*
2461 * If another power sequencer was being used on this
2462 * port previously make sure to turn off vdd there while
2463 * we still have control of it.
2464 */
2465 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2466 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2467
2468 /*
2469 * We may be stealing the power
2470 * sequencer from another port.
2471 */
2472 vlv_steal_power_sequencer(dev, crtc->pipe);
2473
2474 /* now it's all ours */
2475 intel_dp->pps_pipe = crtc->pipe;
2476
2477 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2478 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2479
2480 /* init power sequencer on this pipe and port */
36b5f425
VS		 2481 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2482 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2483}
2484
ab1f90f9 2485static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2486{
2bd2ad64 2487 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2488 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2489 struct drm_device *dev = encoder->base.dev;
89b667f8 2490 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2491 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2492 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2493 int pipe = intel_crtc->pipe;
2494 u32 val;
a4fc5ed6 2495
ab1f90f9 2496 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2497
ab3c759a 2498 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2499 val = 0;
2500 if (pipe)
2501 val |= (1<<21);
2502 else
2503 val &= ~(1<<21);
2504 val |= 0x001000c4;
ab3c759a
CML		 2505 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2506 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2507 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2508
ab1f90f9
JN		 2509 mutex_unlock(&dev_priv->dpio_lock);
2510
2511 intel_enable_dp(encoder);
89b667f8
JB		 2512}
2513
ecff4f3b 2514static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2515{
2516 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2517 struct drm_device *dev = encoder->base.dev;
2518 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2519 struct intel_crtc *intel_crtc =
2520 to_intel_crtc(encoder->base.crtc);
e4607fcf 2521 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2522 int pipe = intel_crtc->pipe;
89b667f8 2523
8ac33ed3
DV		 2524 intel_dp_prepare(encoder);
2525
89b667f8 2526 /* Program Tx lane resets to default */
0980a60f 2527 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2528 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2529 DPIO_PCS_TX_LANE2_RESET |
2530 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2531 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2532 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2533 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2534 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2535 DPIO_PCS_CLK_SOFT_RESET);
2536
2537 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2538 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2539 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2540 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2541 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2542}
2543
e4a1d846
CML		 2544static void chv_pre_enable_dp(struct intel_encoder *encoder)
2545{
2546 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2547 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2548 struct drm_device *dev = encoder->base.dev;
2549 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2550 struct intel_crtc *intel_crtc =
2551 to_intel_crtc(encoder->base.crtc);
2552 enum dpio_channel ch = vlv_dport_to_channel(dport);
2553 int pipe = intel_crtc->pipe;
2554 int data, i;
949c1d43 2555 u32 val;
e4a1d846 2556
e4a1d846 2557 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2558
570e2a74
VS		 2559 /* allow hardware to manage TX FIFO reset source */
2560 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2561 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2562 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2563
2564 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2565 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2566 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2567
949c1d43 2568 /* Deassert soft data lane reset*/
97fd4d5c 2569 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2570 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2571 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2572
2573 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2574 val |= CHV_PCS_REQ_SOFTRESET_EN;
2575 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2576
2577 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2578 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2579 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2580
97fd4d5c 2581 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2582 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2583 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2584
2585 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2586 for (i = 0; i < 4; i++) {
2587 /* Set the latency optimal bit */
2588 data = (i == 1) ? 0x0 : 0x6;
2589 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2590 data << DPIO_FRC_LATENCY_SHFIT);
2591
2592 /* Set the upar bit */
2593 data = (i == 1) ? 0x0 : 0x1;
2594 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2595 data << DPIO_UPAR_SHIFT);
2596 }
2597
2598 /* Data lane stagger programming */
2599 /* FIXME: Fix up value only after power analysis */
2600
2601 mutex_unlock(&dev_priv->dpio_lock);
2602
e4a1d846 2603 intel_enable_dp(encoder);
e4a1d846
CML		 2604}
2605
9197c88b
VS		 2606static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2607{
2608 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2609 struct drm_device *dev = encoder->base.dev;
2610 struct drm_i915_private *dev_priv = dev->dev_private;
2611 struct intel_crtc *intel_crtc =
2612 to_intel_crtc(encoder->base.crtc);
2613 enum dpio_channel ch = vlv_dport_to_channel(dport);
2614 enum pipe pipe = intel_crtc->pipe;
2615 u32 val;
2616
625695f8
VS		 2617 intel_dp_prepare(encoder);
2618
9197c88b
VS		 2619 mutex_lock(&dev_priv->dpio_lock);
2620
b9e5ac3c
VS		 2621 /* program left/right clock distribution */
2622 if (pipe != PIPE_B) {
2623 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2624 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2625 if (ch == DPIO_CH0)
2626 val |= CHV_BUFLEFTENA1_FORCE;
2627 if (ch == DPIO_CH1)
2628 val |= CHV_BUFRIGHTENA1_FORCE;
2629 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2630 } else {
2631 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2632 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2633 if (ch == DPIO_CH0)
2634 val |= CHV_BUFLEFTENA2_FORCE;
2635 if (ch == DPIO_CH1)
2636 val |= CHV_BUFRIGHTENA2_FORCE;
2637 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2638 }
2639
9197c88b
VS		 2640 /* program clock channel usage */
2641 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2642 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2643 if (pipe != PIPE_B)
2644 val &= ~CHV_PCS_USEDCLKCHANNEL;
2645 else
2646 val |= CHV_PCS_USEDCLKCHANNEL;
2647 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2648
2649 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2650 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2651 if (pipe != PIPE_B)
2652 val &= ~CHV_PCS_USEDCLKCHANNEL;
2653 else
2654 val |= CHV_PCS_USEDCLKCHANNEL;
2655 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2656
2657 /*
2658 * This a a bit weird since generally CL
2659 * matches the pipe, but here we need to
2660 * pick the CL based on the port.
2661 */
2662 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2663 if (pipe != PIPE_B)
2664 val &= ~CHV_CMN_USEDCLKCHANNEL;
2665 else
2666 val |= CHV_CMN_USEDCLKCHANNEL;
2667 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2668
2669 mutex_unlock(&dev_priv->dpio_lock);
2670}
2671
a4fc5ed6 2672/*
df0c237d
JB		 2673 * Native read with retry for link status and receiver capability reads for
2674 * cases where the sink may still be asleep.
9d1a1031
JN		 2675 *
2676 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2677 * supposed to retry 3 times per the spec.
a4fc5ed6 2678 */
9d1a1031
JN		 2679static ssize_t
2680intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2681 void *buffer, size_t size)
a4fc5ed6 2682{
9d1a1031
JN		 2683 ssize_t ret;
2684 int i;
61da5fab 2685
f6a19066
VS		 2686 /*
2687 * Sometime we just get the same incorrect byte repeated
2688 * over the entire buffer. Doing just one throw away read
2689 * initially seems to "solve" it.
2690 */
2691 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2692
61da5fab 2693 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2694 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2695 if (ret == size)
2696 return ret;
61da5fab
JB		 2697 msleep(1);
2698 }
a4fc5ed6 2699
9d1a1031 2700 return ret;
a4fc5ed6
KP		 2701}
2702
2703/*
2704 * Fetch AUX CH registers 0x202 - 0x207 which contain
2705 * link status information
2706 */
2707static bool
93f62dad 2708intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2709{
9d1a1031
JN		 2710 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2711 DP_LANE0_1_STATUS,
2712 link_status,
2713 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2714}
2715
1100244e 2716/* These are source-specific values. */
a4fc5ed6 2717static uint8_t
1a2eb460 2718intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2719{
30add22d 2720 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2721 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2722 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2723
7ad14a29
SJ		 2724 if (INTEL_INFO(dev)->gen >= 9) {
2725 if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
2726 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2727 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2728 } else if (IS_VALLEYVIEW(dev))
bd60018a 2729 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2730 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2731 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2732 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2733 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2734 else
bd60018a 2735 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2736}
2737
2738static uint8_t
2739intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2740{
30add22d 2741 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2742 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2743
5a9d1f1a
DL		 2744 if (INTEL_INFO(dev)->gen >= 9) {
2745 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2746 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2747 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2748 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2749 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2750 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2751 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2752 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2753 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2754 default:
2755 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2756 }
2757 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2758 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2759 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2760 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2761 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2762 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2763 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2764 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2765 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2766 default:
bd60018a 2767 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2768 }
e2fa6fba
P		 2769 } else if (IS_VALLEYVIEW(dev)) {
2770 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2771 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2772 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2773 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2774 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2775 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2776 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2777 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2778 default:
bd60018a 2779 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2780 }
bc7d38a4 2781 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2782 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2783 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2784 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2785 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2786 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2787 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2788 default:
bd60018a 2789 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2790 }
2791 } else {
2792 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2793 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2794 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2795 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2796 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2797 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2798 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2799 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2800 default:
bd60018a 2801 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2802 }
a4fc5ed6
KP		 2803 }
2804}
2805
e2fa6fba
P		 2806static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2807{
2808 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2811 struct intel_crtc *intel_crtc =
2812 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2813 unsigned long demph_reg_value, preemph_reg_value,
2814 uniqtranscale_reg_value;
2815 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2816 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2817 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2818
2819 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2820 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2821 preemph_reg_value = 0x0004000;
2822 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2823 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2824 demph_reg_value = 0x2B405555;
2825 uniqtranscale_reg_value = 0x552AB83A;
2826 break;
bd60018a 2827 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2828 demph_reg_value = 0x2B404040;
2829 uniqtranscale_reg_value = 0x5548B83A;
2830 break;
bd60018a 2831 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2832 demph_reg_value = 0x2B245555;
2833 uniqtranscale_reg_value = 0x5560B83A;
2834 break;
bd60018a 2835 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2836 demph_reg_value = 0x2B405555;
2837 uniqtranscale_reg_value = 0x5598DA3A;
2838 break;
2839 default:
2840 return 0;
2841 }
2842 break;
bd60018a 2843 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2844 preemph_reg_value = 0x0002000;
2845 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2846 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2847 demph_reg_value = 0x2B404040;
2848 uniqtranscale_reg_value = 0x5552B83A;
2849 break;
bd60018a 2850 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2851 demph_reg_value = 0x2B404848;
2852 uniqtranscale_reg_value = 0x5580B83A;
2853 break;
bd60018a 2854 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2855 demph_reg_value = 0x2B404040;
2856 uniqtranscale_reg_value = 0x55ADDA3A;
2857 break;
2858 default:
2859 return 0;
2860 }
2861 break;
bd60018a 2862 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2863 preemph_reg_value = 0x0000000;
2864 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2866 demph_reg_value = 0x2B305555;
2867 uniqtranscale_reg_value = 0x5570B83A;
2868 break;
bd60018a 2869 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2870 demph_reg_value = 0x2B2B4040;
2871 uniqtranscale_reg_value = 0x55ADDA3A;
2872 break;
2873 default:
2874 return 0;
2875 }
2876 break;
bd60018a 2877 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2878 preemph_reg_value = 0x0006000;
2879 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2880 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2881 demph_reg_value = 0x1B405555;
2882 uniqtranscale_reg_value = 0x55ADDA3A;
2883 break;
2884 default:
2885 return 0;
2886 }
2887 break;
2888 default:
2889 return 0;
2890 }
2891
0980a60f 2892 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2893 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2894 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2895 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2896 uniqtranscale_reg_value);
ab3c759a
CML		 2897 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2898 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2899 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2900 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2901 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2902
2903 return 0;
2904}
2905
e4a1d846
CML		 2906static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2907{
2908 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2911 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2912 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2913 uint8_t train_set = intel_dp->train_set[0];
2914 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2915 enum pipe pipe = intel_crtc->pipe;
2916 int i;
e4a1d846
CML		 2917
2918 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2919 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2920 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2922 deemph_reg_value = 128;
2923 margin_reg_value = 52;
2924 break;
bd60018a 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2926 deemph_reg_value = 128;
2927 margin_reg_value = 77;
2928 break;
bd60018a 2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2930 deemph_reg_value = 128;
2931 margin_reg_value = 102;
2932 break;
bd60018a 2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2934 deemph_reg_value = 128;
2935 margin_reg_value = 154;
2936 /* FIXME extra to set for 1200 */
2937 break;
2938 default:
2939 return 0;
2940 }
2941 break;
bd60018a 2942 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2943 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2945 deemph_reg_value = 85;
2946 margin_reg_value = 78;
2947 break;
bd60018a 2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2949 deemph_reg_value = 85;
2950 margin_reg_value = 116;
2951 break;
bd60018a 2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2953 deemph_reg_value = 85;
2954 margin_reg_value = 154;
2955 break;
2956 default:
2957 return 0;
2958 }
2959 break;
bd60018a 2960 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2961 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2963 deemph_reg_value = 64;
2964 margin_reg_value = 104;
2965 break;
bd60018a 2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2967 deemph_reg_value = 64;
2968 margin_reg_value = 154;
2969 break;
2970 default:
2971 return 0;
2972 }
2973 break;
bd60018a 2974 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2975 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2977 deemph_reg_value = 43;
2978 margin_reg_value = 154;
2979 break;
2980 default:
2981 return 0;
2982 }
2983 break;
2984 default:
2985 return 0;
2986 }
2987
2988 mutex_lock(&dev_priv->dpio_lock);
2989
2990 /* Clear calc init */
1966e59e
VS		 2991 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2992 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2993 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2994 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 2995 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2996
2997 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2998 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2999 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3000 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3001 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3002
a02ef3c7
VS		 3003 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3004 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3005 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3006 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3007
3008 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3009 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3010 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3011 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3012
e4a1d846 3013 /* Program swing deemph */
f72df8db
VS		 3014 for (i = 0; i < 4; i++) {
3015 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3016 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3017 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3018 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3019 }
e4a1d846
CML		 3020
3021 /* Program swing margin */
f72df8db
VS		 3022 for (i = 0; i < 4; i++) {
3023 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3024 val &= ~DPIO_SWING_MARGIN000_MASK;
3025 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3026 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3027 }
e4a1d846
CML		 3028
3029 /* Disable unique transition scale */
f72df8db
VS		 3030 for (i = 0; i < 4; i++) {
3031 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3032 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3033 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3034 }
e4a1d846
CML		 3035
3036 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3037 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3038 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3039 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3040
3041 /*
3042 * The document said it needs to set bit 27 for ch0 and bit 26
3043 * for ch1. Might be a typo in the doc.
3044 * For now, for this unique transition scale selection, set bit
3045 * 27 for ch0 and ch1.
3046 */
f72df8db
VS		 3047 for (i = 0; i < 4; i++) {
3048 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3049 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3050 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3051 }
e4a1d846 3052
f72df8db
VS		 3053 for (i = 0; i < 4; i++) {
3054 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3055 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3056 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3057 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3058 }
e4a1d846
CML		 3059 }
3060
3061 /* Start swing calculation */
1966e59e
VS		 3062 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3063 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3064 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3065
3066 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3067 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3068 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3069
3070 /* LRC Bypass */
3071 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3072 val |= DPIO_LRC_BYPASS;
3073 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3074
3075 mutex_unlock(&dev_priv->dpio_lock);
3076
3077 return 0;
3078}
3079
a4fc5ed6 3080static void
0301b3ac
JN		 3081intel_get_adjust_train(struct intel_dp *intel_dp,
3082 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3083{
3084 uint8_t v = 0;
3085 uint8_t p = 0;
3086 int lane;
1a2eb460
KP		 3087 uint8_t voltage_max;
3088 uint8_t preemph_max;
a4fc5ed6 3089
33a34e4e 3090 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3091 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3092 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3093
3094 if (this_v > v)
3095 v = this_v;
3096 if (this_p > p)
3097 p = this_p;
3098 }
3099
1a2eb460 3100 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3101 if (v >= voltage_max)
3102 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3103
1a2eb460
KP		 3104 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3105 if (p >= preemph_max)
3106 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3107
3108 for (lane = 0; lane < 4; lane++)
33a34e4e 3109 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3110}
3111
3112static uint32_t
f0a3424e 3113intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3114{
3cf2efb1 3115 uint32_t signal_levels = 0;
a4fc5ed6 3116
3cf2efb1 3117 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3119 default:
3120 signal_levels |= DP_VOLTAGE_0_4;
3121 break;
bd60018a 3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3123 signal_levels |= DP_VOLTAGE_0_6;
3124 break;
bd60018a 3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3126 signal_levels |= DP_VOLTAGE_0_8;
3127 break;
bd60018a 3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3129 signal_levels |= DP_VOLTAGE_1_2;
3130 break;
3131 }
3cf2efb1 3132 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3133 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3134 default:
3135 signal_levels |= DP_PRE_EMPHASIS_0;
3136 break;
bd60018a 3137 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3138 signal_levels |= DP_PRE_EMPHASIS_3_5;
3139 break;
bd60018a 3140 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3141 signal_levels |= DP_PRE_EMPHASIS_6;
3142 break;
bd60018a 3143 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3144 signal_levels |= DP_PRE_EMPHASIS_9_5;
3145 break;
3146 }
3147 return signal_levels;
3148}
3149
e3421a18
ZW		 3150/* Gen6's DP voltage swing and pre-emphasis control */
3151static uint32_t
3152intel_gen6_edp_signal_levels(uint8_t train_set)
3153{
3c5a62b5
YL		 3154 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3155 DP_TRAIN_PRE_EMPHASIS_MASK);
3156 switch (signal_levels) {
bd60018a
SJ		 3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3159 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3161 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3164 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3167 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3169 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3170 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3171 default:
3c5a62b5
YL		 3172 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3173 "0x%x\n", signal_levels);
3174 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3175 }
3176}
3177
1a2eb460
KP		 3178/* Gen7's DP voltage swing and pre-emphasis control */
3179static uint32_t
3180intel_gen7_edp_signal_levels(uint8_t train_set)
3181{
3182 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3183 DP_TRAIN_PRE_EMPHASIS_MASK);
3184 switch (signal_levels) {
bd60018a 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3186 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3188 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3190 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3191
bd60018a 3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3193 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3195 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3196
bd60018a 3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3198 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3200 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3201
3202 default:
3203 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3204 "0x%x\n", signal_levels);
3205 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3206 }
3207}
3208
d6c0d722
PZ		 3209/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3210static uint32_t
f0a3424e 3211intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3212{
d6c0d722
PZ		 3213 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3214 DP_TRAIN_PRE_EMPHASIS_MASK);
3215 switch (signal_levels) {
bd60018a 3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3217 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3219 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3221 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3223 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3224
bd60018a 3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3226 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3228 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3230 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3231
bd60018a 3232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3233 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3235 return DDI_BUF_TRANS_SELECT(8);
7ad14a29
SJ		 3236
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3238 return DDI_BUF_TRANS_SELECT(9);
d6c0d722
PZ		 3239 default:
3240 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3241 "0x%x\n", signal_levels);
c5fe6a06 3242 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3243 }
a4fc5ed6
KP		 3244}
3245
f0a3424e
PZ		 3246/* Properly updates "DP" with the correct signal levels. */
3247static void
3248intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3249{
3250 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3251 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3252 struct drm_device *dev = intel_dig_port->base.base.dev;
3253 uint32_t signal_levels, mask;
3254 uint8_t train_set = intel_dp->train_set[0];
3255
5a9d1f1a 3256 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3257 signal_levels = intel_hsw_signal_levels(train_set);
3258 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3259 } else if (IS_CHERRYVIEW(dev)) {
3260 signal_levels = intel_chv_signal_levels(intel_dp);
3261 mask = 0;
e2fa6fba
P		 3262 } else if (IS_VALLEYVIEW(dev)) {
3263 signal_levels = intel_vlv_signal_levels(intel_dp);
3264 mask = 0;
bc7d38a4 3265 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3266 signal_levels = intel_gen7_edp_signal_levels(train_set);
3267 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3268 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3269 signal_levels = intel_gen6_edp_signal_levels(train_set);
3270 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3271 } else {
3272 signal_levels = intel_gen4_signal_levels(train_set);
3273 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3274 }
3275
3276 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3277
3278 *DP = (*DP & ~mask) | signal_levels;
3279}
3280
a4fc5ed6 3281static bool
ea5b213a 3282intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3283 uint32_t *DP,
58e10eb9 3284 uint8_t dp_train_pat)
a4fc5ed6 3285{
174edf1f
PZ		 3286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3287 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3288 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3289 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3290 int ret, len;
a4fc5ed6 3291
7b13b58a 3292 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3293
70aff66c 3294 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3295 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3296
2cdfe6c8
JN		 3297 buf[0] = dp_train_pat;
3298 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3299 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3300 /* don't write DP_TRAINING_LANEx_SET on disable */
3301 len = 1;
3302 } else {
3303 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3304 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3305 len = intel_dp->lane_count + 1;
47ea7542 3306 }
a4fc5ed6 3307
9d1a1031
JN		 3308 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3309 buf, len);
2cdfe6c8
JN		 3310
3311 return ret == len;
a4fc5ed6
KP		 3312}
3313
70aff66c
JN		 3314static bool
3315intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3316 uint8_t dp_train_pat)
3317{
953d22e8 3318 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3319 intel_dp_set_signal_levels(intel_dp, DP);
3320 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3321}
3322
3323static bool
3324intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3325 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3326{
3327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3328 struct drm_device *dev = intel_dig_port->base.base.dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 int ret;
3331
3332 intel_get_adjust_train(intel_dp, link_status);
3333 intel_dp_set_signal_levels(intel_dp, DP);
3334
3335 I915_WRITE(intel_dp->output_reg, *DP);
3336 POSTING_READ(intel_dp->output_reg);
3337
9d1a1031
JN		 3338 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3339 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3340
3341 return ret == intel_dp->lane_count;
3342}
3343
3ab9c637
ID		 3344static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3345{
3346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3347 struct drm_device *dev = intel_dig_port->base.base.dev;
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 enum port port = intel_dig_port->port;
3350 uint32_t val;
3351
3352 if (!HAS_DDI(dev))
3353 return;
3354
3355 val = I915_READ(DP_TP_CTL(port));
3356 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3357 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3358 I915_WRITE(DP_TP_CTL(port), val);
3359
3360 /*
3361 * On PORT_A we can have only eDP in SST mode. There the only reason
3362 * we need to set idle transmission mode is to work around a HW issue
3363 * where we enable the pipe while not in idle link-training mode.
3364 * In this case there is requirement to wait for a minimum number of
3365 * idle patterns to be sent.
3366 */
3367 if (port == PORT_A)
3368 return;
3369
3370 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3371 1))
3372 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3373}
3374
33a34e4e 3375/* Enable corresponding port and start training pattern 1 */
c19b0669 3376void
33a34e4e 3377intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3378{
da63a9f2 3379 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3380 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3381 int i;
3382 uint8_t voltage;
cdb0e95b 3383 int voltage_tries, loop_tries;
ea5b213a 3384 uint32_t DP = intel_dp->DP;
6aba5b6c 3385 uint8_t link_config[2];
a4fc5ed6 3386
affa9354 3387 if (HAS_DDI(dev))
c19b0669
PZ		 3388 intel_ddi_prepare_link_retrain(encoder);
3389
3cf2efb1 3390 /* Write the link configuration data */
6aba5b6c
JN		 3391 link_config[0] = intel_dp->link_bw;
3392 link_config[1] = intel_dp->lane_count;
3393 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3394 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3395 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3396
3397 link_config[0] = 0;
3398 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3399 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3400
3401 DP |= DP_PORT_EN;
1a2eb460 3402
70aff66c
JN		 3403 /* clock recovery */
3404 if (!intel_dp_reset_link_train(intel_dp, &DP,
3405 DP_TRAINING_PATTERN_1 |
3406 DP_LINK_SCRAMBLING_DISABLE)) {
3407 DRM_ERROR("failed to enable link training\n");
3408 return;
3409 }
3410
a4fc5ed6 3411 voltage = 0xff;
cdb0e95b
KP		 3412 voltage_tries = 0;
3413 loop_tries = 0;
a4fc5ed6 3414 for (;;) {
70aff66c 3415 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3416
a7c9655f 3417 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3418 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3419 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3420 break;
93f62dad 3421 }
a4fc5ed6 3422
01916270 3423 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3424 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3425 break;
3426 }
3427
3428 /* Check to see if we've tried the max voltage */
3429 for (i = 0; i < intel_dp->lane_count; i++)
3430 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3431 break;
3b4f819d 3432 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3433 ++loop_tries;
3434 if (loop_tries == 5) {
3def84b3 3435 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3436 break;
3437 }
70aff66c
JN		 3438 intel_dp_reset_link_train(intel_dp, &DP,
3439 DP_TRAINING_PATTERN_1 |
3440 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3441 voltage_tries = 0;
3442 continue;
3443 }
a4fc5ed6 3444
3cf2efb1 3445 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3446 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3447 ++voltage_tries;
b06fbda3 3448 if (voltage_tries == 5) {
3def84b3 3449 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3450 break;
3451 }
3452 } else
3453 voltage_tries = 0;
3454 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3455
70aff66c
JN		 3456 /* Update training set as requested by target */
3457 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3458 DRM_ERROR("failed to update link training\n");
3459 break;
3460 }
a4fc5ed6
KP		 3461 }
3462
33a34e4e
JB		 3463 intel_dp->DP = DP;
3464}
3465
c19b0669 3466void
33a34e4e
JB		 3467intel_dp_complete_link_train(struct intel_dp *intel_dp)
3468{
33a34e4e 3469 bool channel_eq = false;
37f80975 3470 int tries, cr_tries;
33a34e4e 3471 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3472 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3473
3474 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3475 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3476 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3477
a4fc5ed6 3478 /* channel equalization */
70aff66c 3479 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3480 training_pattern |
70aff66c
JN		 3481 DP_LINK_SCRAMBLING_DISABLE)) {
3482 DRM_ERROR("failed to start channel equalization\n");
3483 return;
3484 }
3485
a4fc5ed6 3486 tries = 0;
37f80975 3487 cr_tries = 0;
a4fc5ed6
KP		 3488 channel_eq = false;
3489 for (;;) {
70aff66c 3490 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3491
37f80975
JB		 3492 if (cr_tries > 5) {
3493 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3494 break;
3495 }
3496
a7c9655f 3497 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3498 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3499 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3500 break;
70aff66c 3501 }
a4fc5ed6 3502
37f80975 3503 /* Make sure clock is still ok */
01916270 3504 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3505 intel_dp_start_link_train(intel_dp);
70aff66c 3506 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3507 training_pattern |
70aff66c 3508 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3509 cr_tries++;
3510 continue;
3511 }
3512
1ffdff13 3513 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3514 channel_eq = true;
3515 break;
3516 }
a4fc5ed6 3517
37f80975
JB		 3518 /* Try 5 times, then try clock recovery if that fails */
3519 if (tries > 5) {
37f80975 3520 intel_dp_start_link_train(intel_dp);
70aff66c 3521 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3522 training_pattern |
70aff66c 3523 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3524 tries = 0;
3525 cr_tries++;
3526 continue;
3527 }
a4fc5ed6 3528
70aff66c
JN		 3529 /* Update training set as requested by target */
3530 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3531 DRM_ERROR("failed to update link training\n");
3532 break;
3533 }
3cf2efb1 3534 ++tries;
869184a6 3535 }
3cf2efb1 3536
3ab9c637
ID		 3537 intel_dp_set_idle_link_train(intel_dp);
3538
3539 intel_dp->DP = DP;
3540
d6c0d722 3541 if (channel_eq)
07f42258 3542 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3543
3ab9c637
ID		 3544}
3545
3546void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3547{
70aff66c 3548 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3549 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3550}
3551
3552static void
ea5b213a 3553intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3554{
da63a9f2 3555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3556 enum port port = intel_dig_port->port;
da63a9f2 3557 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3558 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3559 uint32_t DP = intel_dp->DP;
a4fc5ed6 3560
bc76e320 3561 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3562 return;
3563
0c33d8d7 3564 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3565 return;
3566
28c97730 3567 DRM_DEBUG_KMS("\n");
32f9d658 3568
bc7d38a4 3569 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3570 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3571 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3572 } else {
aad3d14d
VS		 3573 if (IS_CHERRYVIEW(dev))
3574 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3575 else
3576 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3577 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3578 }
fe255d00 3579 POSTING_READ(intel_dp->output_reg);
5eb08b69 3580
493a7081 3581 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3582 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
5bddd17f
EA		 3583 /* Hardware workaround: leaving our transcoder select
3584 * set to transcoder B while it's off will prevent the
3585 * corresponding HDMI output on transcoder A.
3586 *
3587 * Combine this with another hardware workaround:
3588 * transcoder select bit can only be cleared while the
3589 * port is enabled.
3590 */
3591 DP &= ~DP_PIPEB_SELECT;
3592 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3593 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3594 }
3595
832afda6 3596 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3597 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3598 POSTING_READ(intel_dp->output_reg);
f01eca2e 3599 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3600}
3601
26d61aad
KP		 3602static bool
3603intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3604{
a031d709
RV		 3605 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3606 struct drm_device *dev = dig_port->base.base.dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3608 uint8_t rev;
a031d709 3609
9d1a1031
JN		 3610 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3611 sizeof(intel_dp->dpcd)) < 0)
edb39244 3612 return false; /* aux transfer failed */
92fd8fd1 3613
a8e98153 3614 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3615
edb39244
AJ		 3616 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3617 return false; /* DPCD not present */
3618
2293bb5c
SK		 3619 /* Check if the panel supports PSR */
3620 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3621 if (is_edp(intel_dp)) {
9d1a1031
JN		 3622 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3623 intel_dp->psr_dpcd,
3624 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3625 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3626 dev_priv->psr.sink_support = true;
50003939 3627 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3628 }
50003939
JN		 3629 }
3630
7809a611 3631 /* Training Pattern 3 support, both source and sink */
06ea66b6 3632 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3633 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3634 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3635 intel_dp->use_tps3 = true;
f8d8a672 3636 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3637 } else
3638 intel_dp->use_tps3 = false;
3639
fc0f8e25
SJ		 3640 /* Intermediate frequency support */
3641 if (is_edp(intel_dp) &&
3642 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3643 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3644 (rev >= 0x03)) { /* eDp v1.4 or higher */
3645 intel_dp_dpcd_read_wake(&intel_dp->aux,
3646 DP_SUPPORTED_LINK_RATES,
3647 intel_dp->supported_rates,
3648 sizeof(intel_dp->supported_rates));
3649 }
edb39244
AJ		 3650 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3651 DP_DWN_STRM_PORT_PRESENT))
3652 return true; /* native DP sink */
3653
3654 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3655 return true; /* no per-port downstream info */
3656
9d1a1031
JN		 3657 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3658 intel_dp->downstream_ports,
3659 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3660 return false; /* downstream port status fetch failed */
3661
3662 return true;
92fd8fd1
KP		 3663}
3664
0d198328
AJ		 3665static void
3666intel_dp_probe_oui(struct intel_dp *intel_dp)
3667{
3668 u8 buf[3];
3669
3670 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3671 return;
3672
9d1a1031 3673 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3674 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3675 buf[0], buf[1], buf[2]);
3676
9d1a1031 3677 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3678 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3679 buf[0], buf[1], buf[2]);
3680}
3681
0e32b39c
DA		 3682static bool
3683intel_dp_probe_mst(struct intel_dp *intel_dp)
3684{
3685 u8 buf[1];
3686
3687 if (!intel_dp->can_mst)
3688 return false;
3689
3690 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3691 return false;
3692
0e32b39c
DA		 3693 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3694 if (buf[0] & DP_MST_CAP) {
3695 DRM_DEBUG_KMS("Sink is MST capable\n");
3696 intel_dp->is_mst = true;
3697 } else {
3698 DRM_DEBUG_KMS("Sink is not MST capable\n");
3699 intel_dp->is_mst = false;
3700 }
3701 }
0e32b39c
DA		 3702
3703 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3704 return intel_dp->is_mst;
3705}
3706
d2e216d0
RV		 3707int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3708{
3709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3710 struct drm_device *dev = intel_dig_port->base.base.dev;
3711 struct intel_crtc *intel_crtc =
3712 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3713 u8 buf;
3714 int test_crc_count;
3715 int attempts = 6;
d2e216d0 3716
ad9dc91b 3717 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3718 return -EIO;
d2e216d0 3719
ad9dc91b 3720 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3721 return -ENOTTY;
3722
1dda5f93
RV		 3723 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3724 return -EIO;
3725
9d1a1031 3726 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3727 buf | DP_TEST_SINK_START) < 0)
bda0381e 3728 return -EIO;
d2e216d0 3729
1dda5f93 3730 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3731 return -EIO;
ad9dc91b 3732 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3733
ad9dc91b 3734 do {
1dda5f93
RV		 3735 if (drm_dp_dpcd_readb(&intel_dp->aux,
3736 DP_TEST_SINK_MISC, &buf) < 0)
3737 return -EIO;
ad9dc91b
RV		 3738 intel_wait_for_vblank(dev, intel_crtc->pipe);
3739 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3740
3741 if (attempts == 0) {
90bd1f46
DV		 3742 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3743 return -ETIMEDOUT;
ad9dc91b 3744 }
d2e216d0 3745
9d1a1031 3746 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3747 return -EIO;
d2e216d0 3748
1dda5f93
RV		 3749 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3750 return -EIO;
3751 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3752 buf & ~DP_TEST_SINK_START) < 0)
3753 return -EIO;
ce31d9f4 3754
d2e216d0
RV		 3755 return 0;
3756}
3757
a60f0e38
JB		 3758static bool
3759intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3760{
9d1a1031
JN		 3761 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3762 DP_DEVICE_SERVICE_IRQ_VECTOR,
3763 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3764}
3765
0e32b39c
DA		 3766static bool
3767intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3768{
3769 int ret;
3770
3771 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3772 DP_SINK_COUNT_ESI,
3773 sink_irq_vector, 14);
3774 if (ret != 14)
3775 return false;
3776
3777 return true;
3778}
3779
a60f0e38
JB		 3780static void
3781intel_dp_handle_test_request(struct intel_dp *intel_dp)
3782{
3783 /* NAK by default */
9d1a1031 3784 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3785}
3786
0e32b39c
DA		 3787static int
3788intel_dp_check_mst_status(struct intel_dp *intel_dp)
3789{
3790 bool bret;
3791
3792 if (intel_dp->is_mst) {
3793 u8 esi[16] = { 0 };
3794 int ret = 0;
3795 int retry;
3796 bool handled;
3797 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3798go_again:
3799 if (bret == true) {
3800
3801 /* check link status - esi[10] = 0x200c */
3802 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3803 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3804 intel_dp_start_link_train(intel_dp);
3805 intel_dp_complete_link_train(intel_dp);
3806 intel_dp_stop_link_train(intel_dp);
3807 }
3808
6f34cc39 3809 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3810 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3811
3812 if (handled) {
3813 for (retry = 0; retry < 3; retry++) {
3814 int wret;
3815 wret = drm_dp_dpcd_write(&intel_dp->aux,
3816 DP_SINK_COUNT_ESI+1,
3817 &esi[1], 3);
3818 if (wret == 3) {
3819 break;
3820 }
3821 }
3822
3823 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3824 if (bret == true) {
6f34cc39 3825 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3826 goto go_again;
3827 }
3828 } else
3829 ret = 0;
3830
3831 return ret;
3832 } else {
3833 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3834 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3835 intel_dp->is_mst = false;
3836 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3837 /* send a hotplug event */
3838 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3839 }
3840 }
3841 return -EINVAL;
3842}
3843
a4fc5ed6
KP		 3844/*
3845 * According to DP spec
3846 * 5.1.2:
3847 * 1. Read DPCD
3848 * 2. Configure link according to Receiver Capabilities
3849 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3850 * 4. Check link status on receipt of hot-plug interrupt
3851 */
a5146200 3852static void
ea5b213a 3853intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3854{
5b215bcf 3855 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3856 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3857 u8 sink_irq_vector;
93f62dad 3858 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3859
5b215bcf
DA		 3860 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3861
da63a9f2 3862 if (!intel_encoder->connectors_active)
d2b996ac 3863 return;
59cd09e1 3864
da63a9f2 3865 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3866 return;
3867
1a125d8a
ID		 3868 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3869 return;
3870
92fd8fd1 3871 /* Try to read receiver status if the link appears to be up */
93f62dad 3872 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3873 return;
3874 }
3875
92fd8fd1 3876 /* Now read the DPCD to see if it's actually running */
26d61aad 3877 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3878 return;
3879 }
3880
a60f0e38
JB		 3881 /* Try to read the source of the interrupt */
3882 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3883 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3884 /* Clear interrupt source */
9d1a1031
JN		 3885 drm_dp_dpcd_writeb(&intel_dp->aux,
3886 DP_DEVICE_SERVICE_IRQ_VECTOR,
3887 sink_irq_vector);
a60f0e38
JB		 3888
3889 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3890 intel_dp_handle_test_request(intel_dp);
3891 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3892 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3893 }
3894
1ffdff13 3895 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3896 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3897 intel_encoder->base.name);
33a34e4e
JB		 3898 intel_dp_start_link_train(intel_dp);
3899 intel_dp_complete_link_train(intel_dp);
3ab9c637 3900 intel_dp_stop_link_train(intel_dp);
33a34e4e 3901 }
a4fc5ed6 3902}
a4fc5ed6 3903
caf9ab24 3904/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3905static enum drm_connector_status
26d61aad 3906intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3907{
caf9ab24 3908 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3909 uint8_t type;
3910
3911 if (!intel_dp_get_dpcd(intel_dp))
3912 return connector_status_disconnected;
3913
3914 /* if there's no downstream port, we're done */
3915 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3916 return connector_status_connected;
caf9ab24
AJ		 3917
3918 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3919 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3920 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3921 uint8_t reg;
9d1a1031
JN		 3922
3923 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3924 &reg, 1) < 0)
caf9ab24 3925 return connector_status_unknown;
9d1a1031 3926
23235177
AJ		 3927 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3928 : connector_status_disconnected;
caf9ab24
AJ		 3929 }
3930
3931 /* If no HPD, poke DDC gently */
0b99836f 3932 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3933 return connector_status_connected;
caf9ab24
AJ		 3934
3935 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3936 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3937 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3938 if (type == DP_DS_PORT_TYPE_VGA ||
3939 type == DP_DS_PORT_TYPE_NON_EDID)
3940 return connector_status_unknown;
3941 } else {
3942 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3943 DP_DWN_STRM_PORT_TYPE_MASK;
3944 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3945 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3946 return connector_status_unknown;
3947 }
caf9ab24
AJ		 3948
3949 /* Anything else is out of spec, warn and ignore */
3950 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3951 return connector_status_disconnected;
71ba9000
AJ		 3952}
3953
d410b56d
CW		 3954static enum drm_connector_status
3955edp_detect(struct intel_dp *intel_dp)
3956{
3957 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3958 enum drm_connector_status status;
3959
3960 status = intel_panel_detect(dev);
3961 if (status == connector_status_unknown)
3962 status = connector_status_connected;
3963
3964 return status;
3965}
3966
5eb08b69 3967static enum drm_connector_status
a9756bb5 3968ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3969{
30add22d 3970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3971 struct drm_i915_private *dev_priv = dev->dev_private;
3972 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3973
1b469639
DL		 3974 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3975 return connector_status_disconnected;
3976
26d61aad 3977 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3978}
3979
2a592bec
DA		 3980static int g4x_digital_port_connected(struct drm_device *dev,
3981 struct intel_digital_port *intel_dig_port)
a4fc5ed6 3982{
a4fc5ed6 3983 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 3984 uint32_t bit;
5eb08b69 3985
232a6ee9
TP		 3986 if (IS_VALLEYVIEW(dev)) {
3987 switch (intel_dig_port->port) {
3988 case PORT_B:
3989 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3990 break;
3991 case PORT_C:
3992 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3993 break;
3994 case PORT_D:
3995 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3996 break;
3997 default:
2a592bec 3998 return -EINVAL;
232a6ee9
TP		 3999 }
4000 } else {
4001 switch (intel_dig_port->port) {
4002 case PORT_B:
4003 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4004 break;
4005 case PORT_C:
4006 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4007 break;
4008 case PORT_D:
4009 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4010 break;
4011 default:
2a592bec 4012 return -EINVAL;
232a6ee9 4013 }
a4fc5ed6
KP		 4014 }
4015
10f76a38 4016 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4017 return 0;
4018 return 1;
4019}
4020
4021static enum drm_connector_status
4022g4x_dp_detect(struct intel_dp *intel_dp)
4023{
4024 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4025 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4026 int ret;
4027
4028 /* Can't disconnect eDP, but you can close the lid... */
4029 if (is_edp(intel_dp)) {
4030 enum drm_connector_status status;
4031
4032 status = intel_panel_detect(dev);
4033 if (status == connector_status_unknown)
4034 status = connector_status_connected;
4035 return status;
4036 }
4037
4038 ret = g4x_digital_port_connected(dev, intel_dig_port);
4039 if (ret == -EINVAL)
4040 return connector_status_unknown;
4041 else if (ret == 0)
a4fc5ed6
KP		 4042 return connector_status_disconnected;
4043
26d61aad 4044 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4045}
4046
8c241fef 4047static struct edid *
beb60608 4048intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4049{
beb60608 4050 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4051
9cd300e0
JN		 4052 /* use cached edid if we have one */
4053 if (intel_connector->edid) {
9cd300e0
JN		 4054 /* invalid edid */
4055 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4056 return NULL;
4057
55e9edeb 4058 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4059 } else
4060 return drm_get_edid(&intel_connector->base,
4061 &intel_dp->aux.ddc);
4062}
8c241fef 4063
beb60608
CW		 4064static void
4065intel_dp_set_edid(struct intel_dp *intel_dp)
4066{
4067 struct intel_connector *intel_connector = intel_dp->attached_connector;
4068 struct edid *edid;
8c241fef 4069
beb60608
CW		 4070 edid = intel_dp_get_edid(intel_dp);
4071 intel_connector->detect_edid = edid;
4072
4073 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4074 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4075 else
4076 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4077}
4078
beb60608
CW		 4079static void
4080intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4081{
beb60608 4082 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4083
beb60608
CW		 4084 kfree(intel_connector->detect_edid);
4085 intel_connector->detect_edid = NULL;
9cd300e0 4086
beb60608
CW		 4087 intel_dp->has_audio = false;
4088}
d6f24d0f 4089
beb60608
CW		 4090static enum intel_display_power_domain
4091intel_dp_power_get(struct intel_dp *dp)
4092{
4093 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4094 enum intel_display_power_domain power_domain;
4095
4096 power_domain = intel_display_port_power_domain(encoder);
4097 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4098
4099 return power_domain;
4100}
d6f24d0f 4101
beb60608
CW		 4102static void
4103intel_dp_power_put(struct intel_dp *dp,
4104 enum intel_display_power_domain power_domain)
4105{
4106 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4107 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4108}
4109
a9756bb5
ZW		 4110static enum drm_connector_status
4111intel_dp_detect(struct drm_connector *connector, bool force)
4112{
4113 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4114 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4115 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4116 struct drm_device *dev = connector->dev;
a9756bb5 4117 enum drm_connector_status status;
671dedd2 4118 enum intel_display_power_domain power_domain;
0e32b39c 4119 bool ret;
a9756bb5 4120
164c8598 4121 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4122 connector->base.id, connector->name);
beb60608 4123 intel_dp_unset_edid(intel_dp);
164c8598 4124
0e32b39c
DA		 4125 if (intel_dp->is_mst) {
4126 /* MST devices are disconnected from a monitor POV */
4127 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4128 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4129 return connector_status_disconnected;
0e32b39c
DA		 4130 }
4131
beb60608 4132 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4133
d410b56d
CW		 4134 /* Can't disconnect eDP, but you can close the lid... */
4135 if (is_edp(intel_dp))
4136 status = edp_detect(intel_dp);
4137 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4138 status = ironlake_dp_detect(intel_dp);
4139 else
4140 status = g4x_dp_detect(intel_dp);
4141 if (status != connector_status_connected)
c8c8fb33 4142 goto out;
a9756bb5 4143
0d198328
AJ		 4144 intel_dp_probe_oui(intel_dp);
4145
0e32b39c
DA		 4146 ret = intel_dp_probe_mst(intel_dp);
4147 if (ret) {
4148 /* if we are in MST mode then this connector
4149 won't appear connected or have anything with EDID on it */
4150 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4151 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4152 status = connector_status_disconnected;
4153 goto out;
4154 }
4155
beb60608 4156 intel_dp_set_edid(intel_dp);
a9756bb5 4157
d63885da
PZ		 4158 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4159 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4160 status = connector_status_connected;
4161
4162out:
beb60608 4163 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4164 return status;
a4fc5ed6
KP		 4165}
4166
beb60608
CW		 4167static void
4168intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4169{
df0e9248 4170 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4171 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4172 enum intel_display_power_domain power_domain;
a4fc5ed6 4173
beb60608
CW		 4174 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4175 connector->base.id, connector->name);
4176 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4177
beb60608
CW		 4178 if (connector->status != connector_status_connected)
4179 return;
671dedd2 4180
beb60608
CW		 4181 power_domain = intel_dp_power_get(intel_dp);
4182
4183 intel_dp_set_edid(intel_dp);
4184
4185 intel_dp_power_put(intel_dp, power_domain);
4186
4187 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4188 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4189}
4190
4191static int intel_dp_get_modes(struct drm_connector *connector)
4192{
4193 struct intel_connector *intel_connector = to_intel_connector(connector);
4194 struct edid *edid;
4195
4196 edid = intel_connector->detect_edid;
4197 if (edid) {
4198 int ret = intel_connector_update_modes(connector, edid);
4199 if (ret)
4200 return ret;
4201 }
32f9d658 4202
f8779fda 4203 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4204 if (is_edp(intel_attached_dp(connector)) &&
4205 intel_connector->panel.fixed_mode) {
f8779fda 4206 struct drm_display_mode *mode;
beb60608
CW		 4207
4208 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4209 intel_connector->panel.fixed_mode);
f8779fda 4210 if (mode) {
32f9d658
ZW		 4211 drm_mode_probed_add(connector, mode);
4212 return 1;
4213 }
4214 }
beb60608 4215
32f9d658 4216 return 0;
a4fc5ed6
KP		 4217}
4218
1aad7ac0
CW		 4219static bool
4220intel_dp_detect_audio(struct drm_connector *connector)
4221{
1aad7ac0 4222 bool has_audio = false;
beb60608 4223 struct edid *edid;
1aad7ac0 4224
beb60608
CW		 4225 edid = to_intel_connector(connector)->detect_edid;
4226 if (edid)
1aad7ac0 4227 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4228
1aad7ac0
CW		 4229 return has_audio;
4230}
4231
f684960e
CW		 4232static int
4233intel_dp_set_property(struct drm_connector *connector,
4234 struct drm_property *property,
4235 uint64_t val)
4236{
e953fd7b 4237 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4238 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4239 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4240 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4241 int ret;
4242
662595df 4243 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4244 if (ret)
4245 return ret;
4246
3f43c48d 4247 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4248 int i = val;
4249 bool has_audio;
4250
4251 if (i == intel_dp->force_audio)
f684960e
CW		 4252 return 0;
4253
1aad7ac0 4254 intel_dp->force_audio = i;
f684960e 4255
c3e5f67b 4256 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4257 has_audio = intel_dp_detect_audio(connector);
4258 else
c3e5f67b 4259 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4260
4261 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4262 return 0;
4263
1aad7ac0 4264 intel_dp->has_audio = has_audio;
f684960e
CW		 4265 goto done;
4266 }
4267
e953fd7b 4268 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4269 bool old_auto = intel_dp->color_range_auto;
4270 uint32_t old_range = intel_dp->color_range;
4271
55bc60db
VS		 4272 switch (val) {
4273 case INTEL_BROADCAST_RGB_AUTO:
4274 intel_dp->color_range_auto = true;
4275 break;
4276 case INTEL_BROADCAST_RGB_FULL:
4277 intel_dp->color_range_auto = false;
4278 intel_dp->color_range = 0;
4279 break;
4280 case INTEL_BROADCAST_RGB_LIMITED:
4281 intel_dp->color_range_auto = false;
4282 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4283 break;
4284 default:
4285 return -EINVAL;
4286 }
ae4edb80
DV		 4287
4288 if (old_auto == intel_dp->color_range_auto &&
4289 old_range == intel_dp->color_range)
4290 return 0;
4291
e953fd7b
CW		 4292 goto done;
4293 }
4294
53b41837
YN		 4295 if (is_edp(intel_dp) &&
4296 property == connector->dev->mode_config.scaling_mode_property) {
4297 if (val == DRM_MODE_SCALE_NONE) {
4298 DRM_DEBUG_KMS("no scaling not supported\n");
4299 return -EINVAL;
4300 }
4301
4302 if (intel_connector->panel.fitting_mode == val) {
4303 /* the eDP scaling property is not changed */
4304 return 0;
4305 }
4306 intel_connector->panel.fitting_mode = val;
4307
4308 goto done;
4309 }
4310
f684960e
CW		 4311 return -EINVAL;
4312
4313done:
c0c36b94
CW		 4314 if (intel_encoder->base.crtc)
4315 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4316
4317 return 0;
4318}
4319
a4fc5ed6 4320static void
73845adf 4321intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4322{
1d508706 4323 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4324
10e972d3 4325 kfree(intel_connector->detect_edid);
beb60608 4326
9cd300e0
JN		 4327 if (!IS_ERR_OR_NULL(intel_connector->edid))
4328 kfree(intel_connector->edid);
4329
acd8db10
PZ		 4330 /* Can't call is_edp() since the encoder may have been destroyed
4331 * already. */
4332 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4333 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4334
a4fc5ed6 4335 drm_connector_cleanup(connector);
55f78c43 4336 kfree(connector);
a4fc5ed6
KP		 4337}
4338
00c09d70 4339void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4340{
da63a9f2
PZ		 4341 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4342 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4343
4f71d0cb 4344 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4345 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4346 if (is_edp(intel_dp)) {
4347 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4348 /*
4349 * vdd might still be enabled do to the delayed vdd off.
4350 * Make sure vdd is actually turned off here.
4351 */
773538e8 4352 pps_lock(intel_dp);
4be73780 4353 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4354 pps_unlock(intel_dp);
4355
01527b31
CT		 4356 if (intel_dp->edp_notifier.notifier_call) {
4357 unregister_reboot_notifier(&intel_dp->edp_notifier);
4358 intel_dp->edp_notifier.notifier_call = NULL;
4359 }
bd943159 4360 }
c8bd0e49 4361 drm_encoder_cleanup(encoder);
da63a9f2 4362 kfree(intel_dig_port);
24d05927
DV		 4363}
4364
07f9cd0b
ID		 4365static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4366{
4367 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4368
4369 if (!is_edp(intel_dp))
4370 return;
4371
951468f3
VS		 4372 /*
4373 * vdd might still be enabled do to the delayed vdd off.
4374 * Make sure vdd is actually turned off here.
4375 */
afa4e53a 4376 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4377 pps_lock(intel_dp);
07f9cd0b 4378 edp_panel_vdd_off_sync(intel_dp);
773538e8 4379 pps_unlock(intel_dp);
07f9cd0b
ID		 4380}
4381
49e6bc51
VS		 4382static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4383{
4384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4385 struct drm_device *dev = intel_dig_port->base.base.dev;
4386 struct drm_i915_private *dev_priv = dev->dev_private;
4387 enum intel_display_power_domain power_domain;
4388
4389 lockdep_assert_held(&dev_priv->pps_mutex);
4390
4391 if (!edp_have_panel_vdd(intel_dp))
4392 return;
4393
4394 /*
4395 * The VDD bit needs a power domain reference, so if the bit is
4396 * already enabled when we boot or resume, grab this reference and
4397 * schedule a vdd off, so we don't hold on to the reference
4398 * indefinitely.
4399 */
4400 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4401 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4402 intel_display_power_get(dev_priv, power_domain);
4403
4404 edp_panel_vdd_schedule_off(intel_dp);
4405}
4406
6d93c0c4
ID		 4407static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4408{
49e6bc51
VS		 4409 struct intel_dp *intel_dp;
4410
4411 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4412 return;
4413
4414 intel_dp = enc_to_intel_dp(encoder);
4415
4416 pps_lock(intel_dp);
4417
4418 /*
4419 * Read out the current power sequencer assignment,
4420 * in case the BIOS did something with it.
4421 */
4422 if (IS_VALLEYVIEW(encoder->dev))
4423 vlv_initial_power_sequencer_setup(intel_dp);
4424
4425 intel_edp_panel_vdd_sanitize(intel_dp);
4426
4427 pps_unlock(intel_dp);
6d93c0c4
ID		 4428}
4429
a4fc5ed6 4430static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4431 .dpms = intel_connector_dpms,
a4fc5ed6 4432 .detect = intel_dp_detect,
beb60608 4433 .force = intel_dp_force,
a4fc5ed6 4434 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4435 .set_property = intel_dp_set_property,
2545e4a6 4436 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4437 .destroy = intel_dp_connector_destroy,
c6f95f27 4438 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
a4fc5ed6
KP		 4439};
4440
4441static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4442 .get_modes = intel_dp_get_modes,
4443 .mode_valid = intel_dp_mode_valid,
df0e9248 4444 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4445};
4446
a4fc5ed6 4447static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4448 .reset = intel_dp_encoder_reset,
24d05927 4449 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4450};
4451
0e32b39c 4452void
21d40d37 4453intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4454{
0e32b39c 4455 return;
c8110e52 4456}
6207937d 4457
b2c5c181 4458enum irqreturn
13cf5504
DA		 4459intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4460{
4461 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4462 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4463 struct drm_device *dev = intel_dig_port->base.base.dev;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4465 enum intel_display_power_domain power_domain;
b2c5c181 4466 enum irqreturn ret = IRQ_NONE;
1c767b33 4467
0e32b39c
DA		 4468 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4469 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4470
7a7f84cc
VS		 4471 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4472 /*
4473 * vdd off can generate a long pulse on eDP which
4474 * would require vdd on to handle it, and thus we
4475 * would end up in an endless cycle of
4476 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4477 */
4478 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4479 port_name(intel_dig_port->port));
a8b3d52f 4480 return IRQ_HANDLED;
7a7f84cc
VS		 4481 }
4482
26fbb774
VS		 4483 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4484 port_name(intel_dig_port->port),
0e32b39c 4485 long_hpd ? "long" : "short");
13cf5504 4486
1c767b33
ID		 4487 power_domain = intel_display_port_power_domain(intel_encoder);
4488 intel_display_power_get(dev_priv, power_domain);
4489
0e32b39c 4490 if (long_hpd) {
2a592bec
DA		 4491
4492 if (HAS_PCH_SPLIT(dev)) {
4493 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4494 goto mst_fail;
4495 } else {
4496 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4497 goto mst_fail;
4498 }
0e32b39c
DA		 4499
4500 if (!intel_dp_get_dpcd(intel_dp)) {
4501 goto mst_fail;
4502 }
4503
4504 intel_dp_probe_oui(intel_dp);
4505
4506 if (!intel_dp_probe_mst(intel_dp))
4507 goto mst_fail;
4508
4509 } else {
4510 if (intel_dp->is_mst) {
1c767b33 4511 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4512 goto mst_fail;
4513 }
4514
4515 if (!intel_dp->is_mst) {
4516 /*
4517 * we'll check the link status via the normal hot plug path later -
4518 * but for short hpds we should check it now
4519 */
5b215bcf 4520 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4521 intel_dp_check_link_status(intel_dp);
5b215bcf 4522 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4523 }
4524 }
b2c5c181
DV		 4525
4526 ret = IRQ_HANDLED;
4527
1c767b33 4528 goto put_power;
0e32b39c
DA		 4529mst_fail:
4530 /* if we were in MST mode, and device is not there get out of MST mode */
4531 if (intel_dp->is_mst) {
4532 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4533 intel_dp->is_mst = false;
4534 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4535 }
1c767b33
ID		 4536put_power:
4537 intel_display_power_put(dev_priv, power_domain);
4538
4539 return ret;
13cf5504
DA		 4540}
4541
e3421a18
ZW		 4542/* Return which DP Port should be selected for Transcoder DP control */
4543int
0206e353 4544intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4545{
4546 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4547 struct intel_encoder *intel_encoder;
4548 struct intel_dp *intel_dp;
e3421a18 4549
fa90ecef
PZ		 4550 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4551 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4552
fa90ecef
PZ		 4553 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4554 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4555 return intel_dp->output_reg;
e3421a18 4556 }
ea5b213a 4557
e3421a18
ZW		 4558 return -1;
4559}
4560
36e83a18 4561/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4562bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4563{
4564 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4565 union child_device_config *p_child;
36e83a18 4566 int i;
5d8a7752
VS		 4567 static const short port_mapping[] = {
4568 [PORT_B] = PORT_IDPB,
4569 [PORT_C] = PORT_IDPC,
4570 [PORT_D] = PORT_IDPD,
4571 };
36e83a18 4572
3b32a35b
VS		 4573 if (port == PORT_A)
4574 return true;
4575
41aa3448 4576 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4577 return false;
4578
41aa3448
RV		 4579 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4580 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4581
5d8a7752 4582 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4583 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4584 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4585 return true;
4586 }
4587 return false;
4588}
4589
0e32b39c 4590void
f684960e
CW		 4591intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4592{
53b41837
YN		 4593 struct intel_connector *intel_connector = to_intel_connector(connector);
4594
3f43c48d 4595 intel_attach_force_audio_property(connector);
e953fd7b 4596 intel_attach_broadcast_rgb_property(connector);
55bc60db 4597 intel_dp->color_range_auto = true;
53b41837
YN		 4598
4599 if (is_edp(intel_dp)) {
4600 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4601 drm_object_attach_property(
4602 &connector->base,
53b41837 4603 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4604 DRM_MODE_SCALE_ASPECT);
4605 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4606 }
f684960e
CW		 4607}
4608
dada1a9f
ID		 4609static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4610{
4611 intel_dp->last_power_cycle = jiffies;
4612 intel_dp->last_power_on = jiffies;
4613 intel_dp->last_backlight_off = jiffies;
4614}
4615
67a54566
DV		 4616static void
4617intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4618 struct intel_dp *intel_dp)
67a54566
DV		 4619{
4620 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4621 struct edp_power_seq cur, vbt, spec,
4622 *final = &intel_dp->pps_delays;
67a54566 4623 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4624 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4625
e39b999a
VS		 4626 lockdep_assert_held(&dev_priv->pps_mutex);
4627
81ddbc69
VS		 4628 /* already initialized? */
4629 if (final->t11_t12 != 0)
4630 return;
4631
453c5420 4632 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4633 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4634 pp_on_reg = PCH_PP_ON_DELAYS;
4635 pp_off_reg = PCH_PP_OFF_DELAYS;
4636 pp_div_reg = PCH_PP_DIVISOR;
4637 } else {
bf13e81b
JN		 4638 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4639
4640 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4641 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4642 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4643 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4644 }
67a54566
DV		 4645
4646 /* Workaround: Need to write PP_CONTROL with the unlock key as
4647 * the very first thing. */
453c5420 4648 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4649 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4650
453c5420
JB		 4651 pp_on = I915_READ(pp_on_reg);
4652 pp_off = I915_READ(pp_off_reg);
4653 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4654
4655 /* Pull timing values out of registers */
4656 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4657 PANEL_POWER_UP_DELAY_SHIFT;
4658
4659 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4660 PANEL_LIGHT_ON_DELAY_SHIFT;
4661
4662 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4663 PANEL_LIGHT_OFF_DELAY_SHIFT;
4664
4665 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4666 PANEL_POWER_DOWN_DELAY_SHIFT;
4667
4668 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4669 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4670
4671 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4672 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4673
41aa3448 4674 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4675
4676 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4677 * our hw here, which are all in 100usec. */
4678 spec.t1_t3 = 210 * 10;
4679 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4680 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4681 spec.t10 = 500 * 10;
4682 /* This one is special and actually in units of 100ms, but zero
4683 * based in the hw (so we need to add 100 ms). But the sw vbt
4684 * table multiplies it with 1000 to make it in units of 100usec,
4685 * too. */
4686 spec.t11_t12 = (510 + 100) * 10;
4687
4688 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4689 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4690
4691 /* Use the max of the register settings and vbt. If both are
4692 * unset, fall back to the spec limits. */
36b5f425 4693#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4694 spec.field : \
4695 max(cur.field, vbt.field))
4696 assign_final(t1_t3);
4697 assign_final(t8);
4698 assign_final(t9);
4699 assign_final(t10);
4700 assign_final(t11_t12);
4701#undef assign_final
4702
36b5f425 4703#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4704 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4705 intel_dp->backlight_on_delay = get_delay(t8);
4706 intel_dp->backlight_off_delay = get_delay(t9);
4707 intel_dp->panel_power_down_delay = get_delay(t10);
4708 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4709#undef get_delay
4710
f30d26e4
JN		 4711 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4712 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4713 intel_dp->panel_power_cycle_delay);
4714
4715 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4716 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4717}
4718
4719static void
4720intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4721 struct intel_dp *intel_dp)
f30d26e4
JN		 4722{
4723 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4724 u32 pp_on, pp_off, pp_div, port_sel = 0;
4725 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4726 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4727 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4728 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4729
e39b999a 4730 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4731
4732 if (HAS_PCH_SPLIT(dev)) {
4733 pp_on_reg = PCH_PP_ON_DELAYS;
4734 pp_off_reg = PCH_PP_OFF_DELAYS;
4735 pp_div_reg = PCH_PP_DIVISOR;
4736 } else {
bf13e81b
JN		 4737 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4738
4739 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4740 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4741 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4742 }
4743
b2f19d1a
PZ		 4744 /*
4745 * And finally store the new values in the power sequencer. The
4746 * backlight delays are set to 1 because we do manual waits on them. For
4747 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4748 * we'll end up waiting for the backlight off delay twice: once when we
4749 * do the manual sleep, and once when we disable the panel and wait for
4750 * the PP_STATUS bit to become zero.
4751 */
f30d26e4 4752 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4753 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4754 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4755 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4756 /* Compute the divisor for the pp clock, simply match the Bspec
4757 * formula. */
453c5420 4758 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4759 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4760 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4761
4762 /* Haswell doesn't have any port selection bits for the panel
4763 * power sequencer any more. */
bc7d38a4 4764 if (IS_VALLEYVIEW(dev)) {
ad933b56 4765 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4766 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4767 if (port == PORT_A)
a24c144c 4768 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4769 else
a24c144c 4770 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4771 }
4772
453c5420
JB		 4773 pp_on |= port_sel;
4774
4775 I915_WRITE(pp_on_reg, pp_on);
4776 I915_WRITE(pp_off_reg, pp_off);
4777 I915_WRITE(pp_div_reg, pp_div);
67a54566 4778
67a54566 4779 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4780 I915_READ(pp_on_reg),
4781 I915_READ(pp_off_reg),
4782 I915_READ(pp_div_reg));
f684960e
CW		 4783}
4784
b33a2815
VK		 4785/**
4786 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4787 * @dev: DRM device
4788 * @refresh_rate: RR to be programmed
4789 *
4790 * This function gets called when refresh rate (RR) has to be changed from
4791 * one frequency to another. Switches can be between high and low RR
4792 * supported by the panel or to any other RR based on media playback (in
4793 * this case, RR value needs to be passed from user space).
4794 *
4795 * The caller of this function needs to take a lock on dev_priv->drrs.
4796 */
96178eeb 4797static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4798{
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 struct intel_encoder *encoder;
96178eeb
VK		 4801 struct intel_digital_port *dig_port = NULL;
4802 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 4803 struct intel_crtc_state *config = NULL;
439d7ac0 4804 struct intel_crtc *intel_crtc = NULL;
439d7ac0 4805 u32 reg, val;
96178eeb 4806 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 4807
4808 if (refresh_rate <= 0) {
4809 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4810 return;
4811 }
4812
96178eeb
VK		 4813 if (intel_dp == NULL) {
4814 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 4815 return;
4816 }
4817
1fcc9d1c 4818 /*
e4d59f6b
RV		 4819 * FIXME: This needs proper synchronization with psr state for some
4820 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 4821 */
439d7ac0 4822
96178eeb
VK		 4823 dig_port = dp_to_dig_port(intel_dp);
4824 encoder = &dig_port->base;
439d7ac0
PB		 4825 intel_crtc = encoder->new_crtc;
4826
4827 if (!intel_crtc) {
4828 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4829 return;
4830 }
4831
6e3c9717 4832 config = intel_crtc->config;
439d7ac0 4833
96178eeb 4834 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 4835 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4836 return;
4837 }
4838
96178eeb
VK		 4839 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4840 refresh_rate)
439d7ac0
PB		 4841 index = DRRS_LOW_RR;
4842
96178eeb 4843 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 4844 DRM_DEBUG_KMS(
4845 "DRRS requested for previously set RR...ignoring\n");
4846 return;
4847 }
4848
4849 if (!intel_crtc->active) {
4850 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4851 return;
4852 }
4853
44395bfe 4854 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 4855 switch (index) {
4856 case DRRS_HIGH_RR:
4857 intel_dp_set_m_n(intel_crtc, M1_N1);
4858 break;
4859 case DRRS_LOW_RR:
4860 intel_dp_set_m_n(intel_crtc, M2_N2);
4861 break;
4862 case DRRS_MAX_RR:
4863 default:
4864 DRM_ERROR("Unsupported refreshrate type\n");
4865 }
4866 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 4867 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 4868 val = I915_READ(reg);
a4c30b1d 4869
439d7ac0 4870 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 4871 if (IS_VALLEYVIEW(dev))
4872 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4873 else
4874 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 4875 } else {
6fa7aec1
VK		 4876 if (IS_VALLEYVIEW(dev))
4877 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4878 else
4879 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 4880 }
4881 I915_WRITE(reg, val);
4882 }
4883
4e9ac947
VK		 4884 dev_priv->drrs.refresh_rate_type = index;
4885
4886 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4887}
4888
b33a2815
VK		 4889/**
4890 * intel_edp_drrs_enable - init drrs struct if supported
4891 * @intel_dp: DP struct
4892 *
4893 * Initializes frontbuffer_bits and drrs.dp
4894 */
c395578e
VK		 4895void intel_edp_drrs_enable(struct intel_dp *intel_dp)
4896{
4897 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4899 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4900 struct drm_crtc *crtc = dig_port->base.base.crtc;
4901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4902
4903 if (!intel_crtc->config->has_drrs) {
4904 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4905 return;
4906 }
4907
4908 mutex_lock(&dev_priv->drrs.mutex);
4909 if (WARN_ON(dev_priv->drrs.dp)) {
4910 DRM_ERROR("DRRS already enabled\n");
4911 goto unlock;
4912 }
4913
4914 dev_priv->drrs.busy_frontbuffer_bits = 0;
4915
4916 dev_priv->drrs.dp = intel_dp;
4917
4918unlock:
4919 mutex_unlock(&dev_priv->drrs.mutex);
4920}
4921
b33a2815
VK		 4922/**
4923 * intel_edp_drrs_disable - Disable DRRS
4924 * @intel_dp: DP struct
4925 *
4926 */
c395578e
VK		 4927void intel_edp_drrs_disable(struct intel_dp *intel_dp)
4928{
4929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4932 struct drm_crtc *crtc = dig_port->base.base.crtc;
4933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4934
4935 if (!intel_crtc->config->has_drrs)
4936 return;
4937
4938 mutex_lock(&dev_priv->drrs.mutex);
4939 if (!dev_priv->drrs.dp) {
4940 mutex_unlock(&dev_priv->drrs.mutex);
4941 return;
4942 }
4943
4944 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4945 intel_dp_set_drrs_state(dev_priv->dev,
4946 intel_dp->attached_connector->panel.
4947 fixed_mode->vrefresh);
4948
4949 dev_priv->drrs.dp = NULL;
4950 mutex_unlock(&dev_priv->drrs.mutex);
4951
4952 cancel_delayed_work_sync(&dev_priv->drrs.work);
4953}
4954
4e9ac947
VK		 4955static void intel_edp_drrs_downclock_work(struct work_struct *work)
4956{
4957 struct drm_i915_private *dev_priv =
4958 container_of(work, typeof(*dev_priv), drrs.work.work);
4959 struct intel_dp *intel_dp;
4960
4961 mutex_lock(&dev_priv->drrs.mutex);
4962
4963 intel_dp = dev_priv->drrs.dp;
4964
4965 if (!intel_dp)
4966 goto unlock;
4967
439d7ac0 4968 /*
4e9ac947
VK		 4969 * The delayed work can race with an invalidate hence we need to
4970 * recheck.
439d7ac0
PB		 4971 */
4972
4e9ac947
VK		 4973 if (dev_priv->drrs.busy_frontbuffer_bits)
4974 goto unlock;
439d7ac0 4975
4e9ac947
VK		 4976 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
4977 intel_dp_set_drrs_state(dev_priv->dev,
4978 intel_dp->attached_connector->panel.
4979 downclock_mode->vrefresh);
439d7ac0 4980
4e9ac947 4981unlock:
439d7ac0 4982
4e9ac947 4983 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 4984}
4985
b33a2815
VK		 4986/**
4987 * intel_edp_drrs_invalidate - Invalidate DRRS
4988 * @dev: DRM device
4989 * @frontbuffer_bits: frontbuffer plane tracking bits
4990 *
4991 * When there is a disturbance on screen (due to cursor movement/time
4992 * update etc), DRRS needs to be invalidated, i.e. need to switch to
4993 * high RR.
4994 *
4995 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4996 */
a93fad0f
VK		 4997void intel_edp_drrs_invalidate(struct drm_device *dev,
4998 unsigned frontbuffer_bits)
4999{
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 struct drm_crtc *crtc;
5002 enum pipe pipe;
5003
5004 if (!dev_priv->drrs.dp)
5005 return;
5006
3954e733
R		 5007 cancel_delayed_work_sync(&dev_priv->drrs.work);
5008
a93fad0f
VK		 5009 mutex_lock(&dev_priv->drrs.mutex);
5010 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5011 pipe = to_intel_crtc(crtc)->pipe;
5012
5013 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
a93fad0f
VK		 5014 intel_dp_set_drrs_state(dev_priv->dev,
5015 dev_priv->drrs.dp->attached_connector->panel.
5016 fixed_mode->vrefresh);
5017 }
5018
5019 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5020
5021 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5022 mutex_unlock(&dev_priv->drrs.mutex);
5023}
5024
b33a2815
VK		 5025/**
5026 * intel_edp_drrs_flush - Flush DRRS
5027 * @dev: DRM device
5028 * @frontbuffer_bits: frontbuffer plane tracking bits
5029 *
5030 * When there is no movement on screen, DRRS work can be scheduled.
5031 * This DRRS work is responsible for setting relevant registers after a
5032 * timeout of 1 second.
5033 *
5034 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5035 */
a93fad0f
VK		 5036void intel_edp_drrs_flush(struct drm_device *dev,
5037 unsigned frontbuffer_bits)
5038{
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 struct drm_crtc *crtc;
5041 enum pipe pipe;
5042
5043 if (!dev_priv->drrs.dp)
5044 return;
5045
3954e733
R		 5046 cancel_delayed_work_sync(&dev_priv->drrs.work);
5047
a93fad0f
VK		 5048 mutex_lock(&dev_priv->drrs.mutex);
5049 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5050 pipe = to_intel_crtc(crtc)->pipe;
5051 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5052
a93fad0f
VK		 5053 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5054 !dev_priv->drrs.busy_frontbuffer_bits)
5055 schedule_delayed_work(&dev_priv->drrs.work,
5056 msecs_to_jiffies(1000));
5057 mutex_unlock(&dev_priv->drrs.mutex);
5058}
5059
b33a2815
VK		 5060/**
5061 * DOC: Display Refresh Rate Switching (DRRS)
5062 *
5063 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5064 * which enables swtching between low and high refresh rates,
5065 * dynamically, based on the usage scenario. This feature is applicable
5066 * for internal panels.
5067 *
5068 * Indication that the panel supports DRRS is given by the panel EDID, which
5069 * would list multiple refresh rates for one resolution.
5070 *
5071 * DRRS is of 2 types - static and seamless.
5072 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5073 * (may appear as a blink on screen) and is used in dock-undock scenario.
5074 * Seamless DRRS involves changing RR without any visual effect to the user
5075 * and can be used during normal system usage. This is done by programming
5076 * certain registers.
5077 *
5078 * Support for static/seamless DRRS may be indicated in the VBT based on
5079 * inputs from the panel spec.
5080 *
5081 * DRRS saves power by switching to low RR based on usage scenarios.
5082 *
5083 * eDP DRRS:-
5084 * The implementation is based on frontbuffer tracking implementation.
5085 * When there is a disturbance on the screen triggered by user activity or a
5086 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5087 * When there is no movement on screen, after a timeout of 1 second, a switch
5088 * to low RR is made.
5089 * For integration with frontbuffer tracking code,
5090 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5091 *
5092 * DRRS can be further extended to support other internal panels and also
5093 * the scenario of video playback wherein RR is set based on the rate
5094 * requested by userspace.
5095 */
5096
5097/**
5098 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5099 * @intel_connector: eDP connector
5100 * @fixed_mode: preferred mode of panel
5101 *
5102 * This function is called only once at driver load to initialize basic
5103 * DRRS stuff.
5104 *
5105 * Returns:
5106 * Downclock mode if panel supports it, else return NULL.
5107 * DRRS support is determined by the presence of downclock mode (apart
5108 * from VBT setting).
5109 */
4f9db5b5 5110static struct drm_display_mode *
96178eeb
VK		 5111intel_dp_drrs_init(struct intel_connector *intel_connector,
5112 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5113{
5114 struct drm_connector *connector = &intel_connector->base;
96178eeb 5115 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5116 struct drm_i915_private *dev_priv = dev->dev_private;
5117 struct drm_display_mode *downclock_mode = NULL;
5118
5119 if (INTEL_INFO(dev)->gen <= 6) {
5120 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5121 return NULL;
5122 }
5123
5124 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5125 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5126 return NULL;
5127 }
5128
5129 downclock_mode = intel_find_panel_downclock
5130 (dev, fixed_mode, connector);
5131
5132 if (!downclock_mode) {
a1d26342 5133 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5134 return NULL;
5135 }
5136
4e9ac947
VK		 5137 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5138
96178eeb 5139 mutex_init(&dev_priv->drrs.mutex);
439d7ac0 5140
96178eeb 5141 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5142
96178eeb 5143 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5144 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5145 return downclock_mode;
5146}
5147
ed92f0b2 5148static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5149 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5150{
5151 struct drm_connector *connector = &intel_connector->base;
5152 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5153 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5154 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5155 struct drm_i915_private *dev_priv = dev->dev_private;
5156 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5157 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5158 bool has_dpcd;
5159 struct drm_display_mode *scan;
5160 struct edid *edid;
6517d273 5161 enum pipe pipe = INVALID_PIPE;
ed92f0b2 5162
96178eeb 5163 dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
4f9db5b5 5164
ed92f0b2
PZ		 5165 if (!is_edp(intel_dp))
5166 return true;
5167
49e6bc51
VS		 5168 pps_lock(intel_dp);
5169 intel_edp_panel_vdd_sanitize(intel_dp);
5170 pps_unlock(intel_dp);
63635217 5171
ed92f0b2 5172 /* Cache DPCD and EDID for edp. */
ed92f0b2 5173 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5174
5175 if (has_dpcd) {
5176 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5177 dev_priv->no_aux_handshake =
5178 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5179 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5180 } else {
5181 /* if this fails, presume the device is a ghost */
5182 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5183 return false;
5184 }
5185
5186 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5187 pps_lock(intel_dp);
36b5f425 5188 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5189 pps_unlock(intel_dp);
ed92f0b2 5190
060c8778 5191 mutex_lock(&dev->mode_config.mutex);
0b99836f 5192 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5193 if (edid) {
5194 if (drm_add_edid_modes(connector, edid)) {
5195 drm_mode_connector_update_edid_property(connector,
5196 edid);
5197 drm_edid_to_eld(connector, edid);
5198 } else {
5199 kfree(edid);
5200 edid = ERR_PTR(-EINVAL);
5201 }
5202 } else {
5203 edid = ERR_PTR(-ENOENT);
5204 }
5205 intel_connector->edid = edid;
5206
5207 /* prefer fixed mode from EDID if available */
5208 list_for_each_entry(scan, &connector->probed_modes, head) {
5209 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5210 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5211 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5212 intel_connector, fixed_mode);
ed92f0b2
PZ		 5213 break;
5214 }
5215 }
5216
5217 /* fallback to VBT if available for eDP */
5218 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5219 fixed_mode = drm_mode_duplicate(dev,
5220 dev_priv->vbt.lfp_lvds_vbt_mode);
5221 if (fixed_mode)
5222 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5223 }
060c8778 5224 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5225
01527b31
CT		 5226 if (IS_VALLEYVIEW(dev)) {
5227 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5228 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5229
5230 /*
5231 * Figure out the current pipe for the initial backlight setup.
5232 * If the current pipe isn't valid, try the PPS pipe, and if that
5233 * fails just assume pipe A.
5234 */
5235 if (IS_CHERRYVIEW(dev))
5236 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5237 else
5238 pipe = PORT_TO_PIPE(intel_dp->DP);
5239
5240 if (pipe != PIPE_A && pipe != PIPE_B)
5241 pipe = intel_dp->pps_pipe;
5242
5243 if (pipe != PIPE_A && pipe != PIPE_B)
5244 pipe = PIPE_A;
5245
5246 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5247 pipe_name(pipe));
01527b31
CT		 5248 }
5249
4f9db5b5 5250 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5251 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5252 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5253
5254 return true;
5255}
5256
16c25533 5257bool
f0fec3f2
PZ		 5258intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5259 struct intel_connector *intel_connector)
a4fc5ed6 5260{
f0fec3f2
PZ		 5261 struct drm_connector *connector = &intel_connector->base;
5262 struct intel_dp *intel_dp = &intel_dig_port->dp;
5263 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5264 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5265 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5266 enum port port = intel_dig_port->port;
0b99836f 5267 int type;
a4fc5ed6 5268
a4a5d2f8
VS		 5269 intel_dp->pps_pipe = INVALID_PIPE;
5270
ec5b01dd 5271 /* intel_dp vfuncs */
b6b5e383
DL		 5272 if (INTEL_INFO(dev)->gen >= 9)
5273 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5274 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5275 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5276 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5277 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5278 else if (HAS_PCH_SPLIT(dev))
5279 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5280 else
5281 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5282
b9ca5fad
DL		 5283 if (INTEL_INFO(dev)->gen >= 9)
5284 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5285 else
5286 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5287
0767935e
DV		 5288 /* Preserve the current hw state. */
5289 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5290 intel_dp->attached_connector = intel_connector;
3d3dc149 5291
3b32a35b 5292 if (intel_dp_is_edp(dev, port))
b329530c 5293 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5294 else
5295 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5296
f7d24902
ID		 5297 /*
5298 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5299 * for DP the encoder type can be set by the caller to
5300 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5301 */
5302 if (type == DRM_MODE_CONNECTOR_eDP)
5303 intel_encoder->type = INTEL_OUTPUT_EDP;
5304
c17ed5b5
VS		 5305 /* eDP only on port B and/or C on vlv/chv */
5306 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5307 port != PORT_B && port != PORT_C))
5308 return false;
5309
e7281eab
ID		 5310 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5311 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5312 port_name(port));
5313
b329530c 5314 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5315 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5316
a4fc5ed6
KP		 5317 connector->interlace_allowed = true;
5318 connector->doublescan_allowed = 0;
5319
f0fec3f2 5320 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5321 edp_panel_vdd_work);
a4fc5ed6 5322
df0e9248 5323 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5324 drm_connector_register(connector);
a4fc5ed6 5325
affa9354 5326 if (HAS_DDI(dev))
bcbc889b
PZ		 5327 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5328 else
5329 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5330 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5331
0b99836f 5332 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5333 switch (port) {
5334 case PORT_A:
1d843f9d 5335 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5336 break;
5337 case PORT_B:
1d843f9d 5338 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5339 break;
5340 case PORT_C:
1d843f9d 5341 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5342 break;
5343 case PORT_D:
1d843f9d 5344 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5345 break;
5346 default:
ad1c0b19 5347 BUG();
5eb08b69
ZW		 5348 }
5349
dada1a9f 5350 if (is_edp(intel_dp)) {
773538e8 5351 pps_lock(intel_dp);
1e74a324
VS		 5352 intel_dp_init_panel_power_timestamps(intel_dp);
5353 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5354 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5355 else
36b5f425 5356 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5357 pps_unlock(intel_dp);
dada1a9f 5358 }
0095e6dc 5359
9d1a1031 5360 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5361
0e32b39c 5362 /* init MST on ports that can support it */
c86ea3d0 5363 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5364 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5365 intel_dp_mst_encoder_init(intel_dig_port,
5366 intel_connector->base.base.id);
0e32b39c
DA		 5367 }
5368 }
5369
36b5f425 5370 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5371 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5372 if (is_edp(intel_dp)) {
5373 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5374 /*
5375 * vdd might still be enabled do to the delayed vdd off.
5376 * Make sure vdd is actually turned off here.
5377 */
773538e8 5378 pps_lock(intel_dp);
4be73780 5379 edp_panel_vdd_off_sync(intel_dp);
773538e8 5380 pps_unlock(intel_dp);
15b1d171 5381 }
34ea3d38 5382 drm_connector_unregister(connector);
b2f246a8 5383 drm_connector_cleanup(connector);
16c25533 5384 return false;
b2f246a8 5385 }
32f9d658 5386
f684960e
CW		 5387 intel_dp_add_properties(intel_dp, connector);
5388
a4fc5ed6
KP		 5389 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5390 * 0xd. Failure to do so will result in spurious interrupts being
5391 * generated on the port when a cable is not attached.
5392 */
5393 if (IS_G4X(dev) && !IS_GM45(dev)) {
5394 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5395 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5396 }
16c25533
PZ		 5397
5398 return true;
a4fc5ed6 5399}
f0fec3f2
PZ		 5400
5401void
5402intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5403{
13cf5504 5404 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5405 struct intel_digital_port *intel_dig_port;
5406 struct intel_encoder *intel_encoder;
5407 struct drm_encoder *encoder;
5408 struct intel_connector *intel_connector;
5409
b14c5679 5410 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5411 if (!intel_dig_port)
5412 return;
5413
b14c5679 5414 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5415 if (!intel_connector) {
5416 kfree(intel_dig_port);
5417 return;
5418 }
5419
5420 intel_encoder = &intel_dig_port->base;
5421 encoder = &intel_encoder->base;
5422
5423 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5424 DRM_MODE_ENCODER_TMDS);
5425
5bfe2ac0 5426 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5427 intel_encoder->disable = intel_disable_dp;
00c09d70 5428 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5429 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5430 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5431 if (IS_CHERRYVIEW(dev)) {
9197c88b 5432 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5433 intel_encoder->pre_enable = chv_pre_enable_dp;
5434 intel_encoder->enable = vlv_enable_dp;
580d3811 5435 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5436 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5437 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5438 intel_encoder->pre_enable = vlv_pre_enable_dp;
5439 intel_encoder->enable = vlv_enable_dp;
49277c31 5440 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5441 } else {
ecff4f3b
JN		 5442 intel_encoder->pre_enable = g4x_pre_enable_dp;
5443 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5444 if (INTEL_INFO(dev)->gen >= 5)
5445 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5446 }
f0fec3f2 5447
174edf1f 5448 intel_dig_port->port = port;
f0fec3f2
PZ		 5449 intel_dig_port->dp.output_reg = output_reg;
5450
00c09d70 5451 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5452 if (IS_CHERRYVIEW(dev)) {
5453 if (port == PORT_D)
5454 intel_encoder->crtc_mask = 1 << 2;
5455 else
5456 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5457 } else {
5458 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5459 }
bc079e8b 5460 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5461 intel_encoder->hot_plug = intel_dp_hot_plug;
5462
13cf5504
DA		 5463 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5464 dev_priv->hpd_irq_port[port] = intel_dig_port;
5465
15b1d171
PZ		 5466 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5467 drm_encoder_cleanup(encoder);
5468 kfree(intel_dig_port);
b2f246a8 5469 kfree(intel_connector);
15b1d171 5470 }
f0fec3f2 5471}
0e32b39c
DA		 5472
5473void intel_dp_mst_suspend(struct drm_device *dev)
5474{
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 int i;
5477
5478 /* disable MST */
5479 for (i = 0; i < I915_MAX_PORTS; i++) {
5480 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5481 if (!intel_dig_port)
5482 continue;
5483
5484 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5485 if (!intel_dig_port->dp.can_mst)
5486 continue;
5487 if (intel_dig_port->dp.is_mst)
5488 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5489 }
5490 }
5491}
5492
5493void intel_dp_mst_resume(struct drm_device *dev)
5494{
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 int i;
5497
5498 for (i = 0; i < I915_MAX_PORTS; i++) {
5499 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5500 if (!intel_dig_port)
5501 continue;
5502 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5503 int ret;
5504
5505 if (!intel_dig_port->dp.can_mst)
5506 continue;
5507
5508 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5509 if (ret != 0) {
5510 intel_dp_check_mst_status(&intel_dig_port->dp);
5511 }
5512 }
5513 }
5514}
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