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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
760285e7 | 31 | #include <drm/i915_drm.h> |
80824003 | 32 | #include "i915_drv.h" |
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_crtc_helper.h> | |
35 | #include <drm/drm_fb_helper.h> | |
b1ba124d | 36 | #include <drm/drm_dp_dual_mode_helper.h> |
0e32b39c | 37 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 38 | #include <drm/drm_rect.h> |
10f81c19 | 39 | #include <drm/drm_atomic.h> |
913d8d11 | 40 | |
1d5bfac9 DV |
41 | /** |
42 | * _wait_for - magic (register) wait macro | |
43 | * | |
44 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
45 | * contexts. Note that it's important that we check the condition again after | |
46 | * having timed out, since the timeout could be due to preemption or similar and | |
47 | * we've never had a chance to check the condition before the timeout. | |
0351b939 TU |
48 | * |
49 | * TODO: When modesetting has fully transitioned to atomic, the below | |
50 | * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts | |
51 | * added. | |
1d5bfac9 | 52 | */ |
3f177625 TU |
53 | #define _wait_for(COND, US, W) ({ \ |
54 | unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ | |
913d8d11 | 55 | int ret__ = 0; \ |
0206e353 | 56 | while (!(COND)) { \ |
913d8d11 | 57 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
58 | if (!(COND)) \ |
59 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
60 | break; \ |
61 | } \ | |
9848de08 | 62 | if ((W) && drm_can_sleep()) { \ |
3f177625 | 63 | usleep_range((W), (W)*2); \ |
0cc2764c BW |
64 | } else { \ |
65 | cpu_relax(); \ | |
66 | } \ | |
913d8d11 CW |
67 | } \ |
68 | ret__; \ | |
69 | }) | |
70 | ||
3f177625 TU |
71 | #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) |
72 | #define wait_for_us(COND, US) _wait_for((COND), (US), 1) | |
73 | ||
0351b939 TU |
74 | /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ |
75 | #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) | |
76 | # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic()) | |
77 | #else | |
78 | # define _WAIT_FOR_ATOMIC_CHECK do { } while (0) | |
79 | #endif | |
80 | ||
81 | #define _wait_for_atomic(COND, US) ({ \ | |
82 | unsigned long end__; \ | |
83 | int ret__ = 0; \ | |
84 | _WAIT_FOR_ATOMIC_CHECK; \ | |
85 | BUILD_BUG_ON((US) > 50000); \ | |
86 | end__ = (local_clock() >> 10) + (US) + 1; \ | |
87 | while (!(COND)) { \ | |
88 | if (time_after((unsigned long)(local_clock() >> 10), end__)) { \ | |
89 | /* Unlike the regular wait_for(), this atomic variant \ | |
90 | * cannot be preempted (and we'll just ignore the issue\ | |
91 | * of irq interruptions) and so we know that no time \ | |
92 | * has passed since the last check of COND and can \ | |
93 | * immediately report the timeout. \ | |
94 | */ \ | |
95 | ret__ = -ETIMEDOUT; \ | |
96 | break; \ | |
97 | } \ | |
98 | cpu_relax(); \ | |
99 | } \ | |
100 | ret__; \ | |
101 | }) | |
102 | ||
103 | #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000) | |
104 | #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US)) | |
481b6af3 | 105 | |
49938ac4 JN |
106 | #define KHz(x) (1000 * (x)) |
107 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 108 | |
79e53945 JB |
109 | /* |
110 | * Display related stuff | |
111 | */ | |
112 | ||
113 | /* store information about an Ixxx DVO */ | |
114 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
115 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
116 | #define MAX_OUTPUTS 6 | |
117 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 | 118 | |
4726e0b0 SK |
119 | /* Maximum cursor sizes */ |
120 | #define GEN2_CURSOR_WIDTH 64 | |
121 | #define GEN2_CURSOR_HEIGHT 64 | |
068be561 DL |
122 | #define MAX_CURSOR_WIDTH 256 |
123 | #define MAX_CURSOR_HEIGHT 256 | |
4726e0b0 | 124 | |
79e53945 JB |
125 | #define INTEL_I2C_BUS_DVO 1 |
126 | #define INTEL_I2C_BUS_SDVO 2 | |
127 | ||
128 | /* these are outputs from the chip - integrated only | |
129 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
130 | enum intel_output_type { |
131 | INTEL_OUTPUT_UNUSED = 0, | |
132 | INTEL_OUTPUT_ANALOG = 1, | |
133 | INTEL_OUTPUT_DVO = 2, | |
134 | INTEL_OUTPUT_SDVO = 3, | |
135 | INTEL_OUTPUT_LVDS = 4, | |
136 | INTEL_OUTPUT_TVOUT = 5, | |
137 | INTEL_OUTPUT_HDMI = 6, | |
138 | INTEL_OUTPUT_DISPLAYPORT = 7, | |
139 | INTEL_OUTPUT_EDP = 8, | |
140 | INTEL_OUTPUT_DSI = 9, | |
141 | INTEL_OUTPUT_UNKNOWN = 10, | |
142 | INTEL_OUTPUT_DP_MST = 11, | |
143 | }; | |
79e53945 JB |
144 | |
145 | #define INTEL_DVO_CHIP_NONE 0 | |
146 | #define INTEL_DVO_CHIP_LVDS 1 | |
147 | #define INTEL_DVO_CHIP_TMDS 2 | |
148 | #define INTEL_DVO_CHIP_TVOUT 4 | |
149 | ||
dfba2e2d SK |
150 | #define INTEL_DSI_VIDEO_MODE 0 |
151 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 152 | |
79e53945 JB |
153 | struct intel_framebuffer { |
154 | struct drm_framebuffer base; | |
05394f39 | 155 | struct drm_i915_gem_object *obj; |
2d7a215f | 156 | struct intel_rotation_info rot_info; |
79e53945 JB |
157 | }; |
158 | ||
37811fcc CW |
159 | struct intel_fbdev { |
160 | struct drm_fb_helper helper; | |
8bcd4553 | 161 | struct intel_framebuffer *fb; |
d978ef14 | 162 | int preferred_bpp; |
37811fcc | 163 | }; |
79e53945 | 164 | |
21d40d37 | 165 | struct intel_encoder { |
4ef69c7a | 166 | struct drm_encoder base; |
9a935856 | 167 | |
6847d71b | 168 | enum intel_output_type type; |
bc079e8b | 169 | unsigned int cloneable; |
21d40d37 | 170 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 | 171 | bool (*compute_config)(struct intel_encoder *, |
5cec258b | 172 | struct intel_crtc_state *); |
dafd226c | 173 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 174 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 175 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 176 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 177 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 178 | void (*post_disable)(struct intel_encoder *); |
d6db995f | 179 | void (*post_pll_disable)(struct intel_encoder *); |
f0947c37 DV |
180 | /* Read out the current hw state of this connector, returning true if |
181 | * the encoder is active. If the encoder is enabled it also set the pipe | |
182 | * it is connected to in the pipe parameter. */ | |
183 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 184 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 185 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
186 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
187 | * be set correctly before calling this function. */ | |
045ac3b5 | 188 | void (*get_config)(struct intel_encoder *, |
5cec258b | 189 | struct intel_crtc_state *pipe_config); |
07f9cd0b ID |
190 | /* |
191 | * Called during system suspend after all pending requests for the | |
192 | * encoder are flushed (for example for DP AUX transactions) and | |
193 | * device interrupts are disabled. | |
194 | */ | |
195 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 196 | int crtc_mask; |
1d843f9d | 197 | enum hpd_pin hpd_pin; |
79e53945 JB |
198 | }; |
199 | ||
1d508706 | 200 | struct intel_panel { |
dd06f90e | 201 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 202 | struct drm_display_mode *downclock_mode; |
4d891523 | 203 | int fitting_mode; |
58c68779 JN |
204 | |
205 | /* backlight */ | |
206 | struct { | |
c91c9f32 | 207 | bool present; |
58c68779 | 208 | u32 level; |
6dda730e | 209 | u32 min; |
7bd688cd | 210 | u32 max; |
58c68779 | 211 | bool enabled; |
636baebf JN |
212 | bool combination_mode; /* gen 2/4 only */ |
213 | bool active_low_pwm; | |
b029e66f SK |
214 | |
215 | /* PWM chip */ | |
022e4e52 SK |
216 | bool util_pin_active_low; /* bxt+ */ |
217 | u8 controller; /* bxt+ only */ | |
b029e66f SK |
218 | struct pwm_device *pwm; |
219 | ||
58c68779 | 220 | struct backlight_device *device; |
ab656bb9 | 221 | |
5507faeb JN |
222 | /* Connector and platform specific backlight functions */ |
223 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
224 | uint32_t (*get)(struct intel_connector *connector); | |
225 | void (*set)(struct intel_connector *connector, uint32_t level); | |
226 | void (*disable)(struct intel_connector *connector); | |
227 | void (*enable)(struct intel_connector *connector); | |
228 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, | |
229 | uint32_t hz); | |
230 | void (*power)(struct intel_connector *, bool enable); | |
231 | } backlight; | |
1d508706 JN |
232 | }; |
233 | ||
5daa55eb ZW |
234 | struct intel_connector { |
235 | struct drm_connector base; | |
9a935856 DV |
236 | /* |
237 | * The fixed encoder this connector is connected to. | |
238 | */ | |
df0e9248 | 239 | struct intel_encoder *encoder; |
9a935856 | 240 | |
f0947c37 DV |
241 | /* Reads out the current hw, returning true if the connector is enabled |
242 | * and active (i.e. dpms ON state). */ | |
243 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 | 244 | |
4932e2c3 ID |
245 | /* |
246 | * Removes all interfaces through which the connector is accessible | |
247 | * - like sysfs, debugfs entries -, so that no new operations can be | |
248 | * started on the connector. Also makes sure all currently pending | |
249 | * operations finish before returing. | |
250 | */ | |
251 | void (*unregister)(struct intel_connector *); | |
252 | ||
1d508706 JN |
253 | /* Panel info for eDP and LVDS */ |
254 | struct intel_panel panel; | |
9cd300e0 JN |
255 | |
256 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
257 | struct edid *edid; | |
beb60608 | 258 | struct edid *detect_edid; |
821450c6 EE |
259 | |
260 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
261 | state of connector->polled in case hotplug storm detection changes it */ | |
262 | u8 polled; | |
0e32b39c DA |
263 | |
264 | void *port; /* store this opaque as its illegal to dereference it */ | |
265 | ||
266 | struct intel_dp *mst_port; | |
5daa55eb ZW |
267 | }; |
268 | ||
9e2c8475 | 269 | struct dpll { |
80ad9206 VS |
270 | /* given values */ |
271 | int n; | |
272 | int m1, m2; | |
273 | int p1, p2; | |
274 | /* derived values */ | |
275 | int dot; | |
276 | int vco; | |
277 | int m; | |
278 | int p; | |
9e2c8475 | 279 | }; |
80ad9206 | 280 | |
de419ab6 ML |
281 | struct intel_atomic_state { |
282 | struct drm_atomic_state base; | |
283 | ||
27c329ed | 284 | unsigned int cdclk; |
565602d7 | 285 | |
1a617b77 ML |
286 | /* |
287 | * Calculated device cdclk, can be different from cdclk | |
288 | * only when all crtc's are DPMS off. | |
289 | */ | |
290 | unsigned int dev_cdclk; | |
291 | ||
565602d7 ML |
292 | bool dpll_set, modeset; |
293 | ||
294 | unsigned int active_crtcs; | |
295 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
296 | ||
de419ab6 | 297 | struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; |
aa363136 | 298 | struct intel_wm_config wm_config; |
ed4a6a7c MR |
299 | |
300 | /* | |
301 | * Current watermarks can't be trusted during hardware readout, so | |
302 | * don't bother calculating intermediate watermarks. | |
303 | */ | |
304 | bool skip_intermediate_wm; | |
de419ab6 ML |
305 | }; |
306 | ||
eeca778a | 307 | struct intel_plane_state { |
2b875c22 | 308 | struct drm_plane_state base; |
eeca778a GP |
309 | struct drm_rect src; |
310 | struct drm_rect dst; | |
311 | struct drm_rect clip; | |
eeca778a | 312 | bool visible; |
32b7eeec | 313 | |
be41e336 CK |
314 | /* |
315 | * scaler_id | |
316 | * = -1 : not using a scaler | |
317 | * >= 0 : using a scalers | |
318 | * | |
319 | * plane requiring a scaler: | |
320 | * - During check_plane, its bit is set in | |
321 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 322 | * update_scaler_plane. |
be41e336 CK |
323 | * - scaler_id indicates the scaler it got assigned. |
324 | * | |
325 | * plane doesn't require a scaler: | |
326 | * - this can happen when scaling is no more required or plane simply | |
327 | * got disabled. | |
328 | * - During check_plane, corresponding bit is reset in | |
329 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 330 | * update_scaler_plane. |
be41e336 CK |
331 | */ |
332 | int scaler_id; | |
818ed961 ML |
333 | |
334 | struct drm_intel_sprite_colorkey ckey; | |
7580d774 ML |
335 | |
336 | /* async flip related structures */ | |
337 | struct drm_i915_gem_request *wait_req; | |
eeca778a GP |
338 | }; |
339 | ||
5724dbd1 | 340 | struct intel_initial_plane_config { |
2d14030b | 341 | struct intel_framebuffer *fb; |
49af449b | 342 | unsigned int tiling; |
46f297fb JB |
343 | int size; |
344 | u32 base; | |
345 | }; | |
346 | ||
be41e336 CK |
347 | #define SKL_MIN_SRC_W 8 |
348 | #define SKL_MAX_SRC_W 4096 | |
349 | #define SKL_MIN_SRC_H 8 | |
6156a456 | 350 | #define SKL_MAX_SRC_H 4096 |
be41e336 CK |
351 | #define SKL_MIN_DST_W 8 |
352 | #define SKL_MAX_DST_W 4096 | |
353 | #define SKL_MIN_DST_H 8 | |
6156a456 | 354 | #define SKL_MAX_DST_H 4096 |
be41e336 CK |
355 | |
356 | struct intel_scaler { | |
be41e336 CK |
357 | int in_use; |
358 | uint32_t mode; | |
359 | }; | |
360 | ||
361 | struct intel_crtc_scaler_state { | |
362 | #define SKL_NUM_SCALERS 2 | |
363 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
364 | ||
365 | /* | |
366 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
367 | * | |
368 | * If a bit is set, a user is using a scaler. | |
369 | * Here user can be a plane or crtc as defined below: | |
370 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
371 | * bit 31 - crtc | |
372 | * | |
373 | * Instead of creating a new index to cover planes and crtc, using | |
374 | * existing drm_plane_index for planes which is well less than 31 | |
375 | * planes and bit 31 for crtc. This should be fine to cover all | |
376 | * our platforms. | |
377 | * | |
378 | * intel_atomic_setup_scalers will setup available scalers to users | |
379 | * requesting scalers. It will gracefully fail if request exceeds | |
380 | * avilability. | |
381 | */ | |
382 | #define SKL_CRTC_INDEX 31 | |
383 | unsigned scaler_users; | |
384 | ||
385 | /* scaler used by crtc for panel fitting purpose */ | |
386 | int scaler_id; | |
387 | }; | |
388 | ||
1ed51de9 DV |
389 | /* drm_mode->private_flags */ |
390 | #define I915_MODE_FLAG_INHERITED 1 | |
391 | ||
4e0963c7 MR |
392 | struct intel_pipe_wm { |
393 | struct intel_wm_level wm[5]; | |
71f0a626 | 394 | struct intel_wm_level raw_wm[5]; |
4e0963c7 MR |
395 | uint32_t linetime; |
396 | bool fbc_wm_enabled; | |
397 | bool pipe_enabled; | |
398 | bool sprites_enabled; | |
399 | bool sprites_scaled; | |
400 | }; | |
401 | ||
402 | struct skl_pipe_wm { | |
403 | struct skl_wm_level wm[8]; | |
404 | struct skl_wm_level trans_wm; | |
405 | uint32_t linetime; | |
406 | }; | |
407 | ||
e8f1f02e MR |
408 | struct intel_crtc_wm_state { |
409 | union { | |
410 | struct { | |
411 | /* | |
412 | * Intermediate watermarks; these can be | |
413 | * programmed immediately since they satisfy | |
414 | * both the current configuration we're | |
415 | * switching away from and the new | |
416 | * configuration we're switching to. | |
417 | */ | |
418 | struct intel_pipe_wm intermediate; | |
419 | ||
420 | /* | |
421 | * Optimal watermarks, programmed post-vblank | |
422 | * when this state is committed. | |
423 | */ | |
424 | struct intel_pipe_wm optimal; | |
425 | } ilk; | |
426 | ||
427 | struct { | |
428 | /* gen9+ only needs 1-step wm programming */ | |
429 | struct skl_pipe_wm optimal; | |
430 | } skl; | |
431 | }; | |
432 | ||
433 | /* | |
434 | * Platforms with two-step watermark programming will need to | |
435 | * update watermark programming post-vblank to switch from the | |
436 | * safe intermediate watermarks to the optimal final | |
437 | * watermarks. | |
438 | */ | |
439 | bool need_postvbl_update; | |
440 | }; | |
441 | ||
5cec258b | 442 | struct intel_crtc_state { |
2d112de7 ACO |
443 | struct drm_crtc_state base; |
444 | ||
bb760063 DV |
445 | /** |
446 | * quirks - bitfield with hw state readout quirks | |
447 | * | |
448 | * For various reasons the hw state readout code might not be able to | |
449 | * completely faithfully read out the current state. These cases are | |
450 | * tracked with quirk flags so that fastboot and state checker can act | |
451 | * accordingly. | |
452 | */ | |
9953599b | 453 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 DV |
454 | unsigned long quirks; |
455 | ||
cd202f69 | 456 | unsigned fb_bits; /* framebuffers to flip */ |
ab1d3a0e ML |
457 | bool update_pipe; /* can a fast modeset be performed? */ |
458 | bool disable_cxsr; | |
caed361d | 459 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
e8861675 | 460 | bool fb_changed; /* fb on any of the planes is changed */ |
bfd16b2a | 461 | |
37327abd VS |
462 | /* Pipe source size (ie. panel fitter input size) |
463 | * All planes will be positioned inside this space, | |
464 | * and get clipped at the edges. */ | |
465 | int pipe_src_w, pipe_src_h; | |
466 | ||
5bfe2ac0 DV |
467 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
468 | * between pch encoders and cpu encoders. */ | |
469 | bool has_pch_encoder; | |
50f3b016 | 470 | |
e43823ec JB |
471 | /* Are we sending infoframes on the attached port */ |
472 | bool has_infoframe; | |
473 | ||
3b117c8f | 474 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
4d1de975 JN |
475 | * pipe on Haswell and later (where we have a special eDP transcoder) |
476 | * and Broxton (where we have special DSI transcoders). */ | |
3b117c8f DV |
477 | enum transcoder cpu_transcoder; |
478 | ||
50f3b016 DV |
479 | /* |
480 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
481 | * range fed into the crtcs. | |
482 | */ | |
483 | bool limited_color_range; | |
484 | ||
03afc4a2 DV |
485 | /* DP has a bunch of special case unfortunately, so mark the pipe |
486 | * accordingly. */ | |
487 | bool has_dp_encoder; | |
d8b32247 | 488 | |
a65347ba JN |
489 | /* DSI has special cases */ |
490 | bool has_dsi_encoder; | |
491 | ||
6897b4b5 DV |
492 | /* Whether we should send NULL infoframes. Required for audio. */ |
493 | bool has_hdmi_sink; | |
494 | ||
9ed109a7 DV |
495 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
496 | * has_dp_encoder is set. */ | |
497 | bool has_audio; | |
498 | ||
d8b32247 DV |
499 | /* |
500 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
501 | * plane bpp. | |
502 | */ | |
965e0c48 | 503 | bool dither; |
f47709a9 DV |
504 | |
505 | /* Controls for the clock computation, to override various stages. */ | |
506 | bool clock_set; | |
507 | ||
09ede541 DV |
508 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
509 | * work correctly, we need to track this at runtime.*/ | |
510 | bool sdvo_tv_clock; | |
511 | ||
e29c22c0 DV |
512 | /* |
513 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
514 | * required. This is set in the 2nd loop of calling encoder's | |
515 | * ->compute_config if the first pick doesn't work out. | |
516 | */ | |
517 | bool bw_constrained; | |
518 | ||
f47709a9 DV |
519 | /* Settings for the intel dpll used on pretty much everything but |
520 | * haswell. */ | |
80ad9206 | 521 | struct dpll dpll; |
f47709a9 | 522 | |
8106ddbd ACO |
523 | /* Selected dpll when shared or NULL. */ |
524 | struct intel_shared_dpll *shared_dpll; | |
a43f6e0f | 525 | |
96b7dfb7 S |
526 | /* |
527 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. | |
528 | * - enum skl_dpll on SKL | |
529 | */ | |
de7cfc63 DV |
530 | uint32_t ddi_pll_sel; |
531 | ||
66e985c0 DV |
532 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
533 | struct intel_dpll_hw_state dpll_hw_state; | |
534 | ||
47eacbab VS |
535 | /* DSI PLL registers */ |
536 | struct { | |
537 | u32 ctrl, div; | |
538 | } dsi_pll; | |
539 | ||
965e0c48 | 540 | int pipe_bpp; |
6cf86a5e | 541 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 542 | |
439d7ac0 PB |
543 | /* m2_n2 for eDP downclock */ |
544 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 545 | bool has_drrs; |
439d7ac0 | 546 | |
ff9a6750 DV |
547 | /* |
548 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
549 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
550 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 551 | */ |
ff9a6750 DV |
552 | int port_clock; |
553 | ||
6cc5f341 DV |
554 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
555 | unsigned pixel_multiplier; | |
2dd24552 | 556 | |
90a6b7b0 VS |
557 | uint8_t lane_count; |
558 | ||
2dd24552 | 559 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
560 | struct { |
561 | u32 control; | |
562 | u32 pgm_ratios; | |
68fc8742 | 563 | u32 lvds_border_bits; |
b074cec8 JB |
564 | } gmch_pfit; |
565 | ||
566 | /* Panel fitter placement and size for Ironlake+ */ | |
567 | struct { | |
568 | u32 pos; | |
569 | u32 size; | |
fd4daa9c | 570 | bool enabled; |
fabf6e51 | 571 | bool force_thru; |
b074cec8 | 572 | } pch_pfit; |
33d29b14 | 573 | |
ca3a0ff8 | 574 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 575 | int fdi_lanes; |
ca3a0ff8 | 576 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
577 | |
578 | bool ips_enabled; | |
cf532bb2 | 579 | |
f51be2e0 PZ |
580 | bool enable_fbc; |
581 | ||
cf532bb2 | 582 | bool double_wide; |
0e32b39c DA |
583 | |
584 | bool dp_encoder_is_mst; | |
585 | int pbn; | |
be41e336 CK |
586 | |
587 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
588 | |
589 | /* w/a for waiting 2 vblanks during crtc enable */ | |
590 | enum pipe hsw_workaround_pipe; | |
d21fbe87 MR |
591 | |
592 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
593 | bool disable_lp_wm; | |
4e0963c7 | 594 | |
e8f1f02e | 595 | struct intel_crtc_wm_state wm; |
05dc698c LL |
596 | |
597 | /* Gamma mode programmed on the pipe */ | |
598 | uint32_t gamma_mode; | |
b8cecdf5 DV |
599 | }; |
600 | ||
262cd2e1 VS |
601 | struct vlv_wm_state { |
602 | struct vlv_pipe_wm wm[3]; | |
603 | struct vlv_sr_wm sr[3]; | |
604 | uint8_t num_active_planes; | |
605 | uint8_t num_levels; | |
606 | uint8_t level; | |
607 | bool cxsr; | |
608 | }; | |
609 | ||
84c33a64 | 610 | struct intel_mmio_flip { |
9362c7c5 | 611 | struct work_struct work; |
bcafc4e3 | 612 | struct drm_i915_private *i915; |
eed29a5b | 613 | struct drm_i915_gem_request *req; |
b2cfe0ab | 614 | struct intel_crtc *crtc; |
86efe24a | 615 | unsigned int rotation; |
84c33a64 SG |
616 | }; |
617 | ||
79e53945 JB |
618 | struct intel_crtc { |
619 | struct drm_crtc base; | |
80824003 JB |
620 | enum pipe pipe; |
621 | enum plane plane; | |
79e53945 | 622 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
623 | /* |
624 | * Whether the crtc and the connected output pipeline is active. Implies | |
625 | * that crtc->enabled is set, i.e. the current mode configuration has | |
626 | * some outputs connected to this crtc. | |
08a48469 DV |
627 | */ |
628 | bool active; | |
6efdf354 | 629 | unsigned long enabled_power_domains; |
652c393a | 630 | bool lowfreq_avail; |
02e792fb | 631 | struct intel_overlay *overlay; |
6b95a207 | 632 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 633 | |
b4a98e57 CW |
634 | atomic_t unpin_work_count; |
635 | ||
e506a0c6 DV |
636 | /* Display surface base address adjustement for pageflips. Note that on |
637 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
638 | * handled in the hw itself (with the TILEOFF register). */ | |
54ea9da8 | 639 | u32 dspaddr_offset; |
2db3366b PZ |
640 | int adjusted_x; |
641 | int adjusted_y; | |
e506a0c6 | 642 | |
cda4b7d3 | 643 | uint32_t cursor_addr; |
4b0e333e | 644 | uint32_t cursor_cntl; |
dc41c154 | 645 | uint32_t cursor_size; |
4b0e333e | 646 | uint32_t cursor_base; |
4b645f14 | 647 | |
6e3c9717 | 648 | struct intel_crtc_state *config; |
b8cecdf5 | 649 | |
10d83730 VS |
650 | /* reset counter value when the last flip was submitted */ |
651 | unsigned int reset_counter; | |
8664281b PZ |
652 | |
653 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
654 | bool cpu_fifo_underrun_disabled; | |
655 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
656 | |
657 | /* per-pipe watermark state */ | |
658 | struct { | |
659 | /* watermarks currently being used */ | |
4e0963c7 MR |
660 | union { |
661 | struct intel_pipe_wm ilk; | |
662 | struct skl_pipe_wm skl; | |
663 | } active; | |
ed4a6a7c | 664 | |
852eb00d VS |
665 | /* allow CxSR on this pipe */ |
666 | bool cxsr_allowed; | |
0b2ae6d7 | 667 | } wm; |
8d7849db | 668 | |
80715b2f | 669 | int scanline_offset; |
32b7eeec | 670 | |
eb120ef6 JB |
671 | struct { |
672 | unsigned start_vbl_count; | |
673 | ktime_t start_vbl_time; | |
674 | int min_vbl, max_vbl; | |
675 | int scanline_start; | |
676 | } debug; | |
85a62bf9 | 677 | |
be41e336 CK |
678 | /* scalers available on this crtc */ |
679 | int num_scalers; | |
262cd2e1 VS |
680 | |
681 | struct vlv_wm_state wm_state; | |
79e53945 JB |
682 | }; |
683 | ||
c35426d2 VS |
684 | struct intel_plane_wm_parameters { |
685 | uint32_t horiz_pixels; | |
ed57cb8a | 686 | uint32_t vert_pixels; |
2cd601c6 CK |
687 | /* |
688 | * For packed pixel formats: | |
689 | * bytes_per_pixel - holds bytes per pixel | |
690 | * For planar pixel formats: | |
691 | * bytes_per_pixel - holds bytes per pixel for uv-plane | |
692 | * y_bytes_per_pixel - holds bytes per pixel for y-plane | |
693 | */ | |
c35426d2 | 694 | uint8_t bytes_per_pixel; |
2cd601c6 | 695 | uint8_t y_bytes_per_pixel; |
c35426d2 VS |
696 | bool enabled; |
697 | bool scaled; | |
0fda6568 | 698 | u64 tiling; |
1fc0a8f7 | 699 | unsigned int rotation; |
6eb1a681 | 700 | uint16_t fifo_size; |
c35426d2 VS |
701 | }; |
702 | ||
b840d907 JB |
703 | struct intel_plane { |
704 | struct drm_plane base; | |
7f1f3851 | 705 | int plane; |
b840d907 | 706 | enum pipe pipe; |
2d354c34 | 707 | bool can_scale; |
b840d907 | 708 | int max_downscale; |
a9ff8714 | 709 | uint32_t frontbuffer_bit; |
526682e9 PZ |
710 | |
711 | /* Since we need to change the watermarks before/after | |
712 | * enabling/disabling the planes, we need to store the parameters here | |
713 | * as the other pieces of the struct may not reflect the values we want | |
714 | * for the watermark calculations. Currently only Haswell uses this. | |
715 | */ | |
c35426d2 | 716 | struct intel_plane_wm_parameters wm; |
526682e9 | 717 | |
8e7d688b MR |
718 | /* |
719 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
720 | * new plane properties). New runtime state should now be placed in | |
2fde1391 | 721 | * the intel_plane_state structure and accessed via plane_state. |
8e7d688b MR |
722 | */ |
723 | ||
b840d907 | 724 | void (*update_plane)(struct drm_plane *plane, |
2fde1391 ML |
725 | const struct intel_crtc_state *crtc_state, |
726 | const struct intel_plane_state *plane_state); | |
b39d53f6 | 727 | void (*disable_plane)(struct drm_plane *plane, |
7fabf5ef | 728 | struct drm_crtc *crtc); |
c59cb179 | 729 | int (*check_plane)(struct drm_plane *plane, |
061e4b8d | 730 | struct intel_crtc_state *crtc_state, |
c59cb179 | 731 | struct intel_plane_state *state); |
b840d907 JB |
732 | }; |
733 | ||
b445e3b0 ED |
734 | struct intel_watermark_params { |
735 | unsigned long fifo_size; | |
736 | unsigned long max_wm; | |
737 | unsigned long default_wm; | |
738 | unsigned long guard_size; | |
739 | unsigned long cacheline_size; | |
740 | }; | |
741 | ||
742 | struct cxsr_latency { | |
743 | int is_desktop; | |
744 | int is_ddr3; | |
745 | unsigned long fsb_freq; | |
746 | unsigned long mem_freq; | |
747 | unsigned long display_sr; | |
748 | unsigned long display_hpll_disable; | |
749 | unsigned long cursor_sr; | |
750 | unsigned long cursor_hpll_disable; | |
751 | }; | |
752 | ||
de419ab6 | 753 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 754 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 755 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 756 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 757 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 758 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 759 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 760 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
155e6369 | 761 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
79e53945 | 762 | |
f5bbfca3 | 763 | struct intel_hdmi { |
f0f59a00 | 764 | i915_reg_t hdmi_reg; |
f5bbfca3 | 765 | int ddc_bus; |
b1ba124d VS |
766 | struct { |
767 | enum drm_dp_dual_mode_type type; | |
768 | int max_tmds_clock; | |
769 | } dp_dual_mode; | |
0f2a2a75 | 770 | bool limited_color_range; |
55bc60db | 771 | bool color_range_auto; |
f5bbfca3 ED |
772 | bool has_hdmi_sink; |
773 | bool has_audio; | |
774 | enum hdmi_force_audio force_audio; | |
abedc077 | 775 | bool rgb_quant_range_selectable; |
94a11ddc | 776 | enum hdmi_picture_aspect aspect_ratio; |
d8b4c43a | 777 | struct intel_connector *attached_connector; |
f5bbfca3 | 778 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a | 779 | enum hdmi_infoframe_type type, |
fff63867 | 780 | const void *frame, ssize_t len); |
687f4d06 | 781 | void (*set_infoframes)(struct drm_encoder *encoder, |
6897b4b5 | 782 | bool enable, |
7c5f93b0 | 783 | const struct drm_display_mode *adjusted_mode); |
cda0aaaf VS |
784 | bool (*infoframe_enabled)(struct drm_encoder *encoder, |
785 | const struct intel_crtc_state *pipe_config); | |
f5bbfca3 ED |
786 | }; |
787 | ||
0e32b39c | 788 | struct intel_dp_mst_encoder; |
b091cd92 | 789 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 790 | |
fe3cd48d R |
791 | /* |
792 | * enum link_m_n_set: | |
793 | * When platform provides two set of M_N registers for dp, we can | |
794 | * program them and switch between them incase of DRRS. | |
795 | * But When only one such register is provided, we have to program the | |
796 | * required divider value on that registers itself based on the DRRS state. | |
797 | * | |
798 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
799 | * dp_m2_n2 on M2_N2 registers (If supported) | |
800 | * | |
801 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
802 | * M2_N2 registers are not supported | |
803 | */ | |
804 | ||
805 | enum link_m_n_set { | |
806 | /* Sets the m1_n1 and m2_n2 */ | |
807 | M1_N1 = 0, | |
808 | M2_N2 | |
809 | }; | |
810 | ||
54d63ca6 | 811 | struct intel_dp { |
f0f59a00 VS |
812 | i915_reg_t output_reg; |
813 | i915_reg_t aux_ch_ctl_reg; | |
814 | i915_reg_t aux_ch_data_reg[5]; | |
54d63ca6 | 815 | uint32_t DP; |
901c2daf VS |
816 | int link_rate; |
817 | uint8_t lane_count; | |
30d9aa42 | 818 | uint8_t sink_count; |
54d63ca6 | 819 | bool has_audio; |
7d23e3c3 | 820 | bool detect_done; |
54d63ca6 | 821 | enum hdmi_force_audio force_audio; |
0f2a2a75 | 822 | bool limited_color_range; |
55bc60db | 823 | bool color_range_auto; |
54d63ca6 | 824 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
2293bb5c | 825 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 826 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
86ee27b5 | 827 | uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; |
94ca719e VS |
828 | /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ |
829 | uint8_t num_sink_rates; | |
830 | int sink_rates[DP_MAX_SUPPORTED_RATES]; | |
9d1a1031 | 831 | struct drm_dp_aux aux; |
54d63ca6 SK |
832 | uint8_t train_set[4]; |
833 | int panel_power_up_delay; | |
834 | int panel_power_down_delay; | |
835 | int panel_power_cycle_delay; | |
836 | int backlight_on_delay; | |
837 | int backlight_off_delay; | |
54d63ca6 SK |
838 | struct delayed_work panel_vdd_work; |
839 | bool want_panel_vdd; | |
dce56b3c PZ |
840 | unsigned long last_power_on; |
841 | unsigned long last_backlight_off; | |
d28d4731 | 842 | ktime_t panel_power_off_time; |
5d42f82a | 843 | |
01527b31 CT |
844 | struct notifier_block edp_notifier; |
845 | ||
a4a5d2f8 VS |
846 | /* |
847 | * Pipe whose power sequencer is currently locked into | |
848 | * this port. Only relevant on VLV/CHV. | |
849 | */ | |
850 | enum pipe pps_pipe; | |
36b5f425 | 851 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 852 | |
0e32b39c DA |
853 | bool can_mst; /* this port supports mst */ |
854 | bool is_mst; | |
855 | int active_mst_links; | |
856 | /* connector directly attached - won't be use for modeset in mst world */ | |
dd06f90e | 857 | struct intel_connector *attached_connector; |
ec5b01dd | 858 | |
0e32b39c DA |
859 | /* mst connector list */ |
860 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
861 | struct drm_dp_mst_topology_mgr mst_mgr; | |
862 | ||
ec5b01dd | 863 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
864 | /* |
865 | * This function returns the value we have to program the AUX_CTL | |
866 | * register with to kick off an AUX transaction. | |
867 | */ | |
868 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
869 | bool has_aux_irq, | |
870 | int send_bytes, | |
871 | uint32_t aux_clock_divider); | |
ad64217b ACO |
872 | |
873 | /* This is called before a link training is starterd */ | |
874 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
875 | ||
4e96c977 | 876 | bool train_set_valid; |
c5d5ab7a TP |
877 | |
878 | /* Displayport compliance testing */ | |
879 | unsigned long compliance_test_type; | |
559be30c TP |
880 | unsigned long compliance_test_data; |
881 | bool compliance_test_active; | |
54d63ca6 SK |
882 | }; |
883 | ||
da63a9f2 PZ |
884 | struct intel_digital_port { |
885 | struct intel_encoder base; | |
174edf1f | 886 | enum port port; |
bcf53de4 | 887 | u32 saved_port_bits; |
da63a9f2 PZ |
888 | struct intel_dp dp; |
889 | struct intel_hdmi hdmi; | |
b2c5c181 | 890 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
b0b33846 | 891 | bool release_cl2_override; |
ccb1a831 | 892 | uint8_t max_lanes; |
cae666ce TI |
893 | /* for communication with audio component; protected by av_mutex */ |
894 | const struct drm_connector *audio_connector; | |
da63a9f2 PZ |
895 | }; |
896 | ||
0e32b39c DA |
897 | struct intel_dp_mst_encoder { |
898 | struct intel_encoder base; | |
899 | enum pipe pipe; | |
900 | struct intel_digital_port *primary; | |
901 | void *port; /* store this opaque as its illegal to dereference it */ | |
902 | }; | |
903 | ||
65d64cc5 | 904 | static inline enum dpio_channel |
89b667f8 JB |
905 | vlv_dport_to_channel(struct intel_digital_port *dport) |
906 | { | |
907 | switch (dport->port) { | |
908 | case PORT_B: | |
00fc31b7 | 909 | case PORT_D: |
e4607fcf | 910 | return DPIO_CH0; |
89b667f8 | 911 | case PORT_C: |
e4607fcf | 912 | return DPIO_CH1; |
89b667f8 JB |
913 | default: |
914 | BUG(); | |
915 | } | |
916 | } | |
917 | ||
65d64cc5 VS |
918 | static inline enum dpio_phy |
919 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
920 | { | |
921 | switch (dport->port) { | |
922 | case PORT_B: | |
923 | case PORT_C: | |
924 | return DPIO_PHY0; | |
925 | case PORT_D: | |
926 | return DPIO_PHY1; | |
927 | default: | |
928 | BUG(); | |
929 | } | |
930 | } | |
931 | ||
932 | static inline enum dpio_channel | |
eb69b0e5 CML |
933 | vlv_pipe_to_channel(enum pipe pipe) |
934 | { | |
935 | switch (pipe) { | |
936 | case PIPE_A: | |
937 | case PIPE_C: | |
938 | return DPIO_CH0; | |
939 | case PIPE_B: | |
940 | return DPIO_CH1; | |
941 | default: | |
942 | BUG(); | |
943 | } | |
944 | } | |
945 | ||
f875c15a CW |
946 | static inline struct drm_crtc * |
947 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
948 | { | |
949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
950 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
951 | } | |
952 | ||
417ae147 CW |
953 | static inline struct drm_crtc * |
954 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
955 | { | |
956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
957 | return dev_priv->plane_to_crtc_mapping[plane]; | |
958 | } | |
959 | ||
4e5359cd SF |
960 | struct intel_unpin_work { |
961 | struct work_struct work; | |
b4a98e57 | 962 | struct drm_crtc *crtc; |
ab8d6675 | 963 | struct drm_framebuffer *old_fb; |
05394f39 | 964 | struct drm_i915_gem_object *pending_flip_obj; |
4e5359cd | 965 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
966 | atomic_t pending; |
967 | #define INTEL_FLIP_INACTIVE 0 | |
968 | #define INTEL_FLIP_PENDING 1 | |
969 | #define INTEL_FLIP_COMPLETE 2 | |
75f7f3ec VS |
970 | u32 flip_count; |
971 | u32 gtt_offset; | |
f06cc1b9 | 972 | struct drm_i915_gem_request *flip_queued_req; |
66f59c5c VS |
973 | u32 flip_queued_vblank; |
974 | u32 flip_ready_vblank; | |
4e5359cd SF |
975 | bool enable_stall_check; |
976 | }; | |
977 | ||
5f1aae65 | 978 | struct intel_load_detect_pipe { |
edde3617 | 979 | struct drm_atomic_state *restore_state; |
5f1aae65 | 980 | }; |
79e53945 | 981 | |
5f1aae65 PZ |
982 | static inline struct intel_encoder * |
983 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
984 | { |
985 | return to_intel_connector(connector)->encoder; | |
986 | } | |
987 | ||
da63a9f2 PZ |
988 | static inline struct intel_digital_port * |
989 | enc_to_dig_port(struct drm_encoder *encoder) | |
990 | { | |
991 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
992 | } |
993 | ||
0e32b39c DA |
994 | static inline struct intel_dp_mst_encoder * |
995 | enc_to_mst(struct drm_encoder *encoder) | |
996 | { | |
997 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
998 | } | |
999 | ||
9ff8c9ba ID |
1000 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
1001 | { | |
1002 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
1003 | } |
1004 | ||
1005 | static inline struct intel_digital_port * | |
1006 | dp_to_dig_port(struct intel_dp *intel_dp) | |
1007 | { | |
1008 | return container_of(intel_dp, struct intel_digital_port, dp); | |
1009 | } | |
1010 | ||
1011 | static inline struct intel_digital_port * | |
1012 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
1013 | { | |
1014 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
1015 | } |
1016 | ||
6af31a65 DL |
1017 | /* |
1018 | * Returns the number of planes for this pipe, ie the number of sprites + 1 | |
1019 | * (primary plane). This doesn't count the cursor plane then. | |
1020 | */ | |
1021 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) | |
1022 | { | |
1023 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; | |
1024 | } | |
5f1aae65 | 1025 | |
47339cd9 | 1026 | /* intel_fifo_underrun.c */ |
a72e4c9f | 1027 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 1028 | enum pipe pipe, bool enable); |
a72e4c9f | 1029 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 PZ |
1030 | enum transcoder pch_transcoder, |
1031 | bool enable); | |
1f7247c0 DV |
1032 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
1033 | enum pipe pipe); | |
1034 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
1035 | enum transcoder pch_transcoder); | |
aca7b684 VS |
1036 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
1037 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
1038 | |
1039 | /* i915_irq.c */ | |
480c8033 DV |
1040 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
1041 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
1042 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
1043 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
dc97997a | 1044 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
91d14251 TU |
1045 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); |
1046 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); | |
59d02a1f | 1047 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); |
b963291c DV |
1048 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
1049 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
1050 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
1051 | { | |
1052 | /* | |
1053 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
1054 | * this is the only thing we need to check. | |
1055 | */ | |
2aeb7d3a | 1056 | return dev_priv->pm.irqs_enabled; |
9df7575f JB |
1057 | } |
1058 | ||
a225f079 | 1059 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
4c6c03be DL |
1060 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
1061 | unsigned int pipe_mask); | |
aae8ba84 VS |
1062 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
1063 | unsigned int pipe_mask); | |
5f1aae65 | 1064 | |
5f1aae65 | 1065 | /* intel_crt.c */ |
87440425 | 1066 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
1067 | |
1068 | ||
1069 | /* intel_ddi.c */ | |
e404ba8d VS |
1070 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
1071 | const struct intel_crtc_state *pipe_config); | |
6a7e4f99 | 1072 | void intel_prepare_ddi_buffer(struct intel_encoder *encoder); |
87440425 PZ |
1073 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
1074 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
1075 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
1076 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
87440425 PZ |
1077 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
1078 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
1079 | enum transcoder cpu_transcoder); | |
1080 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
1081 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
190f68c5 ACO |
1082 | bool intel_ddi_pll_select(struct intel_crtc *crtc, |
1083 | struct intel_crtc_state *crtc_state); | |
87440425 | 1084 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
ad64217b | 1085 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
87440425 PZ |
1086 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
1087 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
1088 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
5cec258b | 1089 | struct intel_crtc_state *pipe_config); |
bcddf610 S |
1090 | struct intel_encoder * |
1091 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); | |
5f1aae65 | 1092 | |
44905a27 | 1093 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
0e32b39c | 1094 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1095 | struct intel_crtc_state *pipe_config); |
0e32b39c | 1096 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
f8896f5d | 1097 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
5f1aae65 | 1098 | |
b680c37a | 1099 | /* intel_frontbuffer.c */ |
f99d7069 | 1100 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
a4001f1b | 1101 | enum fb_op_origin origin); |
f99d7069 DV |
1102 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
1103 | unsigned frontbuffer_bits); | |
1104 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
1105 | unsigned frontbuffer_bits); | |
f99d7069 | 1106 | void intel_frontbuffer_flip(struct drm_device *dev, |
fdbff928 | 1107 | unsigned frontbuffer_bits); |
6761dd31 TU |
1108 | unsigned int intel_fb_align_height(struct drm_device *dev, |
1109 | unsigned int height, | |
1110 | uint32_t pixel_format, | |
1111 | uint64_t fb_format_modifier); | |
de152b62 RV |
1112 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, |
1113 | enum fb_op_origin origin); | |
7b49f948 VS |
1114 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
1115 | uint64_t fb_modifier, uint32_t pixel_format); | |
b680c37a | 1116 | |
7c10a2b5 | 1117 | /* intel_audio.c */ |
88212941 | 1118 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv); |
69bfe1a9 JN |
1119 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
1120 | void intel_audio_codec_disable(struct intel_encoder *encoder); | |
58fddc28 ID |
1121 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
1122 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); | |
7c10a2b5 | 1123 | |
b680c37a | 1124 | /* intel_display.c */ |
19ab4ed3 | 1125 | void intel_update_rawclk(struct drm_i915_private *dev_priv); |
c30fec65 VS |
1126 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
1127 | const char *name, u32 reg, int ref_freq); | |
65a3fea0 | 1128 | extern const struct drm_plane_funcs intel_plane_funcs; |
88212941 | 1129 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
1663b9d6 | 1130 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
b680c37a | 1131 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
7d993739 TU |
1132 | void intel_mark_busy(struct drm_i915_private *dev_priv); |
1133 | void intel_mark_idle(struct drm_i915_private *dev_priv); | |
87440425 | 1134 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
70e0bd74 | 1135 | int intel_display_suspend(struct drm_device *dev); |
87440425 | 1136 | void intel_encoder_destroy(struct drm_encoder *encoder); |
08d9bc92 ACO |
1137 | int intel_connector_init(struct intel_connector *); |
1138 | struct intel_connector *intel_connector_alloc(void); | |
87440425 | 1139 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
87440425 PZ |
1140 | void intel_connector_attach_encoder(struct intel_connector *connector, |
1141 | struct intel_encoder *encoder); | |
1142 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
1143 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
1144 | struct drm_crtc *crtc); | |
752aa88a | 1145 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
1146 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
1147 | struct drm_file *file_priv); | |
87440425 PZ |
1148 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1149 | enum pipe pipe); | |
4093561b | 1150 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
4f905cf9 DV |
1151 | static inline void |
1152 | intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
1153 | { | |
1154 | drm_wait_one_vblank(dev, pipe); | |
1155 | } | |
0c241d5b VS |
1156 | static inline void |
1157 | intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe) | |
1158 | { | |
1159 | const struct intel_crtc *crtc = | |
1160 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
1161 | ||
1162 | if (crtc->active) | |
1163 | intel_wait_for_vblank(dev, pipe); | |
1164 | } | |
87440425 | 1165 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1166 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1167 | struct intel_digital_port *dport, |
1168 | unsigned int expected_mask); | |
87440425 PZ |
1169 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
1170 | struct drm_display_mode *mode, | |
51fd371b RC |
1171 | struct intel_load_detect_pipe *old, |
1172 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1173 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1174 | struct intel_load_detect_pipe *old, |
1175 | struct drm_modeset_acquire_ctx *ctx); | |
3465c580 VS |
1176 | int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
1177 | unsigned int rotation); | |
fb4b8ce1 | 1178 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation); |
a8bb6818 DV |
1179 | struct drm_framebuffer * |
1180 | __intel_framebuffer_create(struct drm_device *dev, | |
87440425 PZ |
1181 | struct drm_mode_fb_cmd2 *mode_cmd, |
1182 | struct drm_i915_gem_object *obj); | |
91d14251 TU |
1183 | void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane); |
1184 | void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe); | |
1185 | void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane); | |
1186 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe); | |
6beb8c23 | 1187 | int intel_prepare_plane_fb(struct drm_plane *plane, |
d136dfee | 1188 | const struct drm_plane_state *new_state); |
38f3ce3a | 1189 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
d136dfee | 1190 | const struct drm_plane_state *old_state); |
a98b3431 MR |
1191 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1192 | const struct drm_plane_state *state, | |
1193 | struct drm_property *property, | |
1194 | uint64_t *val); | |
1195 | int intel_plane_atomic_set_property(struct drm_plane *plane, | |
1196 | struct drm_plane_state *state, | |
1197 | struct drm_property *property, | |
1198 | uint64_t val); | |
da20eabd ML |
1199 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
1200 | struct drm_plane_state *plane_state); | |
716c2e55 | 1201 | |
832be82f VS |
1202 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
1203 | uint64_t fb_modifier, unsigned int cpp); | |
50470bb0 | 1204 | |
121920fa TU |
1205 | static inline bool |
1206 | intel_rotation_90_or_270(unsigned int rotation) | |
1207 | { | |
1208 | return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); | |
1209 | } | |
1210 | ||
3b7a5119 SJ |
1211 | void intel_create_rotation_property(struct drm_device *dev, |
1212 | struct intel_plane *plane); | |
1213 | ||
7abd4b35 ACO |
1214 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1215 | enum pipe pipe); | |
1216 | ||
3f36b937 TU |
1217 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
1218 | const struct dpll *dpll); | |
d288f65f | 1219 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); |
8802e5b6 | 1220 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
d288f65f | 1221 | |
716c2e55 | 1222 | /* modesetting asserts */ |
b680c37a DV |
1223 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1224 | enum pipe pipe); | |
55607e8a DV |
1225 | void assert_pll(struct drm_i915_private *dev_priv, |
1226 | enum pipe pipe, bool state); | |
1227 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1228 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
8563b1e8 LL |
1229 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
1230 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1231 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
55607e8a DV |
1232 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe, bool state); | |
1234 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1235 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1236 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1237 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1238 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
4f2d9934 VS |
1239 | u32 intel_compute_tile_offset(int *x, int *y, |
1240 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
1241 | unsigned int pitch, |
1242 | unsigned int rotation); | |
c033666a CW |
1243 | void intel_prepare_reset(struct drm_i915_private *dev_priv); |
1244 | void intel_finish_reset(struct drm_i915_private *dev_priv); | |
a14cb6fc PZ |
1245 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1246 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
c6c4696f ID |
1247 | void broxton_init_cdclk(struct drm_i915_private *dev_priv); |
1248 | void broxton_uninit_cdclk(struct drm_i915_private *dev_priv); | |
adc7f04b | 1249 | bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv); |
c6c4696f ID |
1250 | void broxton_ddi_phy_init(struct drm_i915_private *dev_priv); |
1251 | void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv); | |
adc7f04b | 1252 | void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv); |
da2f41d1 | 1253 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); |
664326f8 SK |
1254 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
1255 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
f62c79b3 | 1256 | void gen9_enable_dc5(struct drm_i915_private *dev_priv); |
5d96d8af | 1257 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
c73666f3 | 1258 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5d96d8af | 1259 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); |
0a9d2bed AM |
1260 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
1261 | void skl_disable_dc6(struct drm_i915_private *dev_priv); | |
87440425 | 1262 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1263 | struct intel_crtc_state *pipe_config); |
fe3cd48d | 1264 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
87440425 | 1265 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
5ab7b0b7 | 1266 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 ACO |
1267 | struct dpll *best_clock); |
1268 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); | |
dccbea3b | 1269 | |
87440425 | 1270 | bool intel_crtc_active(struct drm_crtc *crtc); |
20bc8673 VS |
1271 | void hsw_enable_ips(struct intel_crtc *crtc); |
1272 | void hsw_disable_ips(struct intel_crtc *crtc); | |
319be8ae ID |
1273 | enum intel_display_power_domain |
1274 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); | |
25f78f58 VS |
1275 | enum intel_display_power_domain |
1276 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); | |
f6a83288 | 1277 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1278 | struct intel_crtc_state *pipe_config); |
86adf9d7 | 1279 | |
e435d6e5 | 1280 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
6156a456 | 1281 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); |
8ea30864 | 1282 | |
44eb0cb9 MK |
1283 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
1284 | struct drm_i915_gem_object *obj, | |
1285 | unsigned int plane); | |
dedf278c | 1286 | |
6156a456 CK |
1287 | u32 skl_plane_ctl_format(uint32_t pixel_format); |
1288 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier); | |
1289 | u32 skl_plane_ctl_rotation(unsigned int rotation); | |
121920fa | 1290 | |
eb805623 | 1291 | /* intel_csr.c */ |
f4448375 | 1292 | void intel_csr_ucode_init(struct drm_i915_private *); |
2abc525b | 1293 | void intel_csr_load_program(struct drm_i915_private *); |
f4448375 | 1294 | void intel_csr_ucode_fini(struct drm_i915_private *); |
f74ed08d ID |
1295 | void intel_csr_ucode_suspend(struct drm_i915_private *); |
1296 | void intel_csr_ucode_resume(struct drm_i915_private *); | |
eb805623 | 1297 | |
5f1aae65 | 1298 | /* intel_dp.c */ |
f0f59a00 | 1299 | void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port); |
87440425 PZ |
1300 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1301 | struct intel_connector *intel_connector); | |
901c2daf VS |
1302 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1303 | const struct intel_crtc_state *pipe_config); | |
87440425 | 1304 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
87440425 PZ |
1305 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
1306 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
bf93ba67 ID |
1307 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
1308 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); | |
87440425 | 1309 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
d2e216d0 | 1310 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
87440425 | 1311 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
5cec258b | 1312 | struct intel_crtc_state *pipe_config); |
5d8a7752 | 1313 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
b2c5c181 DV |
1314 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1315 | bool long_hpd); | |
4be73780 DV |
1316 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
1317 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
24f3e092 | 1318 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
1319 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1320 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
0e32b39c DA |
1321 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
1322 | void intel_dp_mst_suspend(struct drm_device *dev); | |
1323 | void intel_dp_mst_resume(struct drm_device *dev); | |
50fec21a | 1324 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
ed4e9c1d | 1325 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
0e32b39c | 1326 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
773538e8 | 1327 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0bc12bcb | 1328 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
4a3b8769 | 1329 | void intel_plane_destroy(struct drm_plane *plane); |
c395578e VK |
1330 | void intel_edp_drrs_enable(struct intel_dp *intel_dp); |
1331 | void intel_edp_drrs_disable(struct intel_dp *intel_dp); | |
a93fad0f VK |
1332 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
1333 | unsigned frontbuffer_bits); | |
1334 | void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); | |
237ed86c SJ |
1335 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
1336 | struct intel_digital_port *port); | |
0bc12bcb | 1337 | |
94223d04 ACO |
1338 | void |
1339 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, | |
1340 | uint8_t dp_train_pat); | |
1341 | void | |
1342 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); | |
1343 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); | |
1344 | uint8_t | |
1345 | intel_dp_voltage_max(struct intel_dp *intel_dp); | |
1346 | uint8_t | |
1347 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); | |
1348 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, | |
1349 | uint8_t *link_bw, uint8_t *rate_select); | |
e588fa18 | 1350 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
94223d04 ACO |
1351 | bool |
1352 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); | |
1353 | ||
419b1b7a ACO |
1354 | static inline unsigned int intel_dp_unused_lane_mask(int lane_count) |
1355 | { | |
1356 | return ~((1 << lane_count) - 1) & 0xf; | |
1357 | } | |
1358 | ||
e7156c83 YA |
1359 | /* intel_dp_aux_backlight.c */ |
1360 | int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); | |
1361 | ||
0e32b39c DA |
1362 | /* intel_dp_mst.c */ |
1363 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1364 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
5f1aae65 | 1365 | /* intel_dsi.c */ |
4328633d | 1366 | void intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
1367 | |
1368 | ||
1369 | /* intel_dvo.c */ | |
87440425 | 1370 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
1371 | |
1372 | ||
0632fef6 | 1373 | /* legacy fbdev emulation in intel_fbdev.c */ |
0695726e | 1374 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4520f53a | 1375 | extern int intel_fbdev_init(struct drm_device *dev); |
e00bf696 | 1376 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
4520f53a | 1377 | extern void intel_fbdev_fini(struct drm_device *dev); |
82e3b8c1 | 1378 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 DV |
1379 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1380 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
1381 | #else |
1382 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1383 | { | |
1384 | return 0; | |
1385 | } | |
5f1aae65 | 1386 | |
e00bf696 | 1387 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
4520f53a DV |
1388 | { |
1389 | } | |
1390 | ||
1391 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
1392 | { | |
1393 | } | |
1394 | ||
82e3b8c1 | 1395 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a DV |
1396 | { |
1397 | } | |
1398 | ||
0632fef6 | 1399 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
1400 | { |
1401 | } | |
1402 | #endif | |
5f1aae65 | 1403 | |
7ff0ebcc | 1404 | /* intel_fbc.c */ |
f51be2e0 PZ |
1405 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
1406 | struct drm_atomic_state *state); | |
0e631adc | 1407 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
1eb52238 PZ |
1408 | void intel_fbc_pre_update(struct intel_crtc *crtc); |
1409 | void intel_fbc_post_update(struct intel_crtc *crtc); | |
7ff0ebcc | 1410 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
010cf73d | 1411 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
d029bcad | 1412 | void intel_fbc_enable(struct intel_crtc *crtc); |
c937ab3e PZ |
1413 | void intel_fbc_disable(struct intel_crtc *crtc); |
1414 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); | |
dbef0f15 PZ |
1415 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1416 | unsigned int frontbuffer_bits, | |
1417 | enum fb_op_origin origin); | |
1418 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1419 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
7733b49b | 1420 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
7ff0ebcc | 1421 | |
5f1aae65 | 1422 | /* intel_hdmi.c */ |
f0f59a00 | 1423 | void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port); |
87440425 PZ |
1424 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1425 | struct intel_connector *intel_connector); | |
1426 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1427 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
5cec258b | 1428 | struct intel_crtc_state *pipe_config); |
b2ccb822 | 1429 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); |
5f1aae65 PZ |
1430 | |
1431 | ||
1432 | /* intel_lvds.c */ | |
87440425 PZ |
1433 | void intel_lvds_init(struct drm_device *dev); |
1434 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
1435 | |
1436 | ||
1437 | /* intel_modes.c */ | |
1438 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 1439 | struct edid *edid); |
5f1aae65 | 1440 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
1441 | void intel_attach_force_audio_property(struct drm_connector *connector); |
1442 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
7949dd47 | 1443 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); |
5f1aae65 PZ |
1444 | |
1445 | ||
1446 | /* intel_overlay.c */ | |
1ee8da6d CW |
1447 | void intel_setup_overlay(struct drm_i915_private *dev_priv); |
1448 | void intel_cleanup_overlay(struct drm_i915_private *dev_priv); | |
87440425 | 1449 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
1ee8da6d CW |
1450 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, |
1451 | struct drm_file *file_priv); | |
1452 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, | |
1453 | struct drm_file *file_priv); | |
1362b776 | 1454 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
5f1aae65 PZ |
1455 | |
1456 | ||
1457 | /* intel_panel.c */ | |
87440425 | 1458 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1459 | struct drm_display_mode *fixed_mode, |
1460 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
1461 | void intel_panel_fini(struct intel_panel *panel); |
1462 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1463 | struct drm_display_mode *adjusted_mode); | |
1464 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1465 | struct intel_crtc_state *pipe_config, |
87440425 PZ |
1466 | int fitting_mode); |
1467 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1468 | struct intel_crtc_state *pipe_config, |
87440425 | 1469 | int fitting_mode); |
6dda730e JN |
1470 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1471 | u32 level, u32 max); | |
6517d273 | 1472 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
752aa88a JB |
1473 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1474 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 1475 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
87440425 | 1476 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
ec9ed197 VK |
1477 | extern struct drm_display_mode *intel_find_panel_downclock( |
1478 | struct drm_device *dev, | |
1479 | struct drm_display_mode *fixed_mode, | |
1480 | struct drm_connector *connector); | |
0962c3c9 VS |
1481 | void intel_backlight_register(struct drm_device *dev); |
1482 | void intel_backlight_unregister(struct drm_device *dev); | |
1483 | ||
5f1aae65 | 1484 | |
0bc12bcb | 1485 | /* intel_psr.c */ |
0bc12bcb RV |
1486 | void intel_psr_enable(struct intel_dp *intel_dp); |
1487 | void intel_psr_disable(struct intel_dp *intel_dp); | |
1488 | void intel_psr_invalidate(struct drm_device *dev, | |
20c8838b | 1489 | unsigned frontbuffer_bits); |
0bc12bcb | 1490 | void intel_psr_flush(struct drm_device *dev, |
169de131 RV |
1491 | unsigned frontbuffer_bits, |
1492 | enum fb_op_origin origin); | |
0bc12bcb | 1493 | void intel_psr_init(struct drm_device *dev); |
20c8838b DV |
1494 | void intel_psr_single_frame_update(struct drm_device *dev, |
1495 | unsigned frontbuffer_bits); | |
0bc12bcb | 1496 | |
9c065a7d DV |
1497 | /* intel_runtime_pm.c */ |
1498 | int intel_power_domains_init(struct drm_i915_private *); | |
f458ebbc | 1499 | void intel_power_domains_fini(struct drm_i915_private *); |
73dfc227 ID |
1500 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
1501 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv); | |
d7d7c9ee ID |
1502 | void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
1503 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv); | |
f458ebbc | 1504 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
9895ad03 DS |
1505 | const char * |
1506 | intel_display_power_domain_str(enum intel_display_power_domain domain); | |
9c065a7d | 1507 | |
f458ebbc DV |
1508 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
1509 | enum intel_display_power_domain domain); | |
1510 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1511 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1512 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1513 | enum intel_display_power_domain domain); | |
09731280 ID |
1514 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
1515 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1516 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1517 | enum intel_display_power_domain domain); | |
da5827c3 ID |
1518 | |
1519 | static inline void | |
1520 | assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) | |
1521 | { | |
1522 | WARN_ONCE(dev_priv->pm.suspended, | |
1523 | "Device suspended during HW access\n"); | |
1524 | } | |
1525 | ||
1526 | static inline void | |
1527 | assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) | |
1528 | { | |
1529 | assert_rpm_device_not_suspended(dev_priv); | |
becd9ca2 DV |
1530 | /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes |
1531 | * too much noise. */ | |
1532 | if (!atomic_read(&dev_priv->pm.wakeref_count)) | |
1533 | DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access"); | |
da5827c3 ID |
1534 | } |
1535 | ||
2b19efeb ID |
1536 | static inline int |
1537 | assert_rpm_atomic_begin(struct drm_i915_private *dev_priv) | |
1538 | { | |
1539 | int seq = atomic_read(&dev_priv->pm.atomic_seq); | |
1540 | ||
1541 | assert_rpm_wakelock_held(dev_priv); | |
1542 | ||
1543 | return seq; | |
1544 | } | |
1545 | ||
1546 | static inline void | |
1547 | assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq) | |
1548 | { | |
1549 | WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq, | |
1550 | "HW access outside of RPM atomic section\n"); | |
1551 | } | |
1552 | ||
1f814dac ID |
1553 | /** |
1554 | * disable_rpm_wakeref_asserts - disable the RPM assert checks | |
1555 | * @dev_priv: i915 device instance | |
1556 | * | |
1557 | * This function disable asserts that check if we hold an RPM wakelock | |
1558 | * reference, while keeping the device-not-suspended checks still enabled. | |
1559 | * It's meant to be used only in special circumstances where our rule about | |
1560 | * the wakelock refcount wrt. the device power state doesn't hold. According | |
1561 | * to this rule at any point where we access the HW or want to keep the HW in | |
1562 | * an active state we must hold an RPM wakelock reference acquired via one of | |
1563 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots | |
1564 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the | |
1565 | * forcewake release timer, and the GPU RPS and hangcheck works. All other | |
1566 | * users should avoid using this function. | |
1567 | * | |
1568 | * Any calls to this function must have a symmetric call to | |
1569 | * enable_rpm_wakeref_asserts(). | |
1570 | */ | |
1571 | static inline void | |
1572 | disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
1573 | { | |
1574 | atomic_inc(&dev_priv->pm.wakeref_count); | |
1575 | } | |
1576 | ||
1577 | /** | |
1578 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks | |
1579 | * @dev_priv: i915 device instance | |
1580 | * | |
1581 | * This function re-enables the RPM assert checks after disabling them with | |
1582 | * disable_rpm_wakeref_asserts. It's meant to be used only in special | |
1583 | * circumstances otherwise its use should be avoided. | |
1584 | * | |
1585 | * Any calls to this function must have a symmetric call to | |
1586 | * disable_rpm_wakeref_asserts(). | |
1587 | */ | |
1588 | static inline void | |
1589 | enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
1590 | { | |
1591 | atomic_dec(&dev_priv->pm.wakeref_count); | |
1592 | } | |
1593 | ||
1594 | /* TODO: convert users of these to rely instead on proper RPM refcounting */ | |
1595 | #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ | |
1596 | disable_rpm_wakeref_asserts(dev_priv) | |
1597 | ||
1598 | #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ | |
1599 | enable_rpm_wakeref_asserts(dev_priv) | |
1600 | ||
9c065a7d | 1601 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
09731280 | 1602 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); |
9c065a7d DV |
1603 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
1604 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
1605 | ||
d9bc89d9 DV |
1606 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
1607 | ||
e0fce78f VS |
1608 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1609 | bool override, unsigned int mask); | |
b0b33846 VS |
1610 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1611 | enum dpio_channel ch, bool override); | |
e0fce78f VS |
1612 | |
1613 | ||
5f1aae65 | 1614 | /* intel_pm.c */ |
87440425 PZ |
1615 | void intel_init_clock_gating(struct drm_device *dev); |
1616 | void intel_suspend_hw(struct drm_device *dev); | |
546c81fd | 1617 | int ilk_wm_max_level(const struct drm_device *dev); |
87440425 | 1618 | void intel_update_watermarks(struct drm_crtc *crtc); |
87440425 | 1619 | void intel_init_pm(struct drm_device *dev); |
bb400da9 | 1620 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); |
f742a552 | 1621 | void intel_pm_setup(struct drm_device *dev); |
87440425 PZ |
1622 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
1623 | void intel_gpu_ips_teardown(void); | |
dc97997a CW |
1624 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv); |
1625 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); | |
1626 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); | |
1627 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); | |
1628 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); | |
1629 | void intel_reset_gt_powersave(struct drm_i915_private *dev_priv); | |
1630 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv); | |
43cf3bf0 CW |
1631 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
1632 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
076e29f2 | 1633 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
1854d5ca | 1634 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
1635 | struct intel_rps_client *rps, |
1636 | unsigned long submitted); | |
91d14251 | 1637 | void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req); |
6eb1a681 | 1638 | void vlv_wm_get_hw_state(struct drm_device *dev); |
243e6a44 | 1639 | void ilk_wm_get_hw_state(struct drm_device *dev); |
3078999f | 1640 | void skl_wm_get_hw_state(struct drm_device *dev); |
08db6652 DL |
1641 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
1642 | struct skl_ddb_allocation *ddb /* out */); | |
8cfb3407 | 1643 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); |
ed4a6a7c | 1644 | bool ilk_disable_lp_wm(struct drm_device *dev); |
dc97997a CW |
1645 | int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); |
1646 | static inline int intel_enable_rc6(void) | |
1647 | { | |
1648 | return i915.enable_rc6; | |
1649 | } | |
72662e10 | 1650 | |
5f1aae65 | 1651 | /* intel_sdvo.c */ |
f0f59a00 VS |
1652 | bool intel_sdvo_init(struct drm_device *dev, |
1653 | i915_reg_t reg, enum port port); | |
96a02917 | 1654 | |
2b28bb1b | 1655 | |
5f1aae65 | 1656 | /* intel_sprite.c */ |
87440425 | 1657 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
87440425 PZ |
1658 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
1659 | struct drm_file *file_priv); | |
34e0adbb ML |
1660 | void intel_pipe_update_start(struct intel_crtc *crtc); |
1661 | void intel_pipe_update_end(struct intel_crtc *crtc); | |
5f1aae65 PZ |
1662 | |
1663 | /* intel_tv.c */ | |
87440425 | 1664 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 1665 | |
ea2c67bb | 1666 | /* intel_atomic.c */ |
2545e4a6 MR |
1667 | int intel_connector_atomic_get_property(struct drm_connector *connector, |
1668 | const struct drm_connector_state *state, | |
1669 | struct drm_property *property, | |
1670 | uint64_t *val); | |
1356837e MR |
1671 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
1672 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
1673 | struct drm_crtc_state *state); | |
de419ab6 ML |
1674 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
1675 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
1676 | struct intel_shared_dpll_config * | |
1677 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); | |
1678 | ||
10f81c19 ACO |
1679 | static inline struct intel_crtc_state * |
1680 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
1681 | struct intel_crtc *crtc) | |
1682 | { | |
1683 | struct drm_crtc_state *crtc_state; | |
1684 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
1685 | if (IS_ERR(crtc_state)) | |
0b6cc188 | 1686 | return ERR_CAST(crtc_state); |
10f81c19 ACO |
1687 | |
1688 | return to_intel_crtc_state(crtc_state); | |
1689 | } | |
e3bddded ML |
1690 | |
1691 | static inline struct intel_plane_state * | |
1692 | intel_atomic_get_existing_plane_state(struct drm_atomic_state *state, | |
1693 | struct intel_plane *plane) | |
1694 | { | |
1695 | struct drm_plane_state *plane_state; | |
1696 | ||
1697 | plane_state = drm_atomic_get_existing_plane_state(state, &plane->base); | |
1698 | ||
1699 | return to_intel_plane_state(plane_state); | |
1700 | } | |
1701 | ||
d03c93d4 CK |
1702 | int intel_atomic_setup_scalers(struct drm_device *dev, |
1703 | struct intel_crtc *intel_crtc, | |
1704 | struct intel_crtc_state *crtc_state); | |
5ee67f1c MR |
1705 | |
1706 | /* intel_atomic_plane.c */ | |
8e7d688b | 1707 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
ea2c67bb MR |
1708 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
1709 | void intel_plane_destroy_state(struct drm_plane *plane, | |
1710 | struct drm_plane_state *state); | |
1711 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
1712 | ||
8563b1e8 LL |
1713 | /* intel_color.c */ |
1714 | void intel_color_init(struct drm_crtc *crtc); | |
82cf435b | 1715 | int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); |
b95c5321 ML |
1716 | void intel_color_set_csc(struct drm_crtc_state *crtc_state); |
1717 | void intel_color_load_luts(struct drm_crtc_state *crtc_state); | |
8563b1e8 | 1718 | |
79e53945 | 1719 | #endif /* __INTEL_DRV_H__ */ |