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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
760285e7 | 31 | #include <drm/i915_drm.h> |
80824003 | 32 | #include "i915_drv.h" |
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_crtc_helper.h> | |
35 | #include <drm/drm_fb_helper.h> | |
0e32b39c | 36 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 37 | #include <drm/drm_rect.h> |
913d8d11 | 38 | |
2e541625 AE |
39 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
40 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) | |
41 | ||
1d5bfac9 DV |
42 | /** |
43 | * _wait_for - magic (register) wait macro | |
44 | * | |
45 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
46 | * contexts. Note that it's important that we check the condition again after | |
47 | * having timed out, since the timeout could be due to preemption or similar and | |
48 | * we've never had a chance to check the condition before the timeout. | |
49 | */ | |
481b6af3 | 50 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 51 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 52 | int ret__ = 0; \ |
0206e353 | 53 | while (!(COND)) { \ |
913d8d11 | 54 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
55 | if (!(COND)) \ |
56 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
57 | break; \ |
58 | } \ | |
0cc2764c BW |
59 | if (W && drm_can_sleep()) { \ |
60 | msleep(W); \ | |
61 | } else { \ | |
62 | cpu_relax(); \ | |
63 | } \ | |
913d8d11 CW |
64 | } \ |
65 | ret__; \ | |
66 | }) | |
67 | ||
481b6af3 CW |
68 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
69 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
70 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
71 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 72 | |
49938ac4 JN |
73 | #define KHz(x) (1000 * (x)) |
74 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 75 | |
79e53945 JB |
76 | /* |
77 | * Display related stuff | |
78 | */ | |
79 | ||
80 | /* store information about an Ixxx DVO */ | |
81 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
82 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
83 | #define MAX_OUTPUTS 6 | |
84 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 | 85 | |
4726e0b0 SK |
86 | /* Maximum cursor sizes */ |
87 | #define GEN2_CURSOR_WIDTH 64 | |
88 | #define GEN2_CURSOR_HEIGHT 64 | |
068be561 DL |
89 | #define MAX_CURSOR_WIDTH 256 |
90 | #define MAX_CURSOR_HEIGHT 256 | |
4726e0b0 | 91 | |
79e53945 JB |
92 | #define INTEL_I2C_BUS_DVO 1 |
93 | #define INTEL_I2C_BUS_SDVO 2 | |
94 | ||
95 | /* these are outputs from the chip - integrated only | |
96 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
97 | enum intel_output_type { |
98 | INTEL_OUTPUT_UNUSED = 0, | |
99 | INTEL_OUTPUT_ANALOG = 1, | |
100 | INTEL_OUTPUT_DVO = 2, | |
101 | INTEL_OUTPUT_SDVO = 3, | |
102 | INTEL_OUTPUT_LVDS = 4, | |
103 | INTEL_OUTPUT_TVOUT = 5, | |
104 | INTEL_OUTPUT_HDMI = 6, | |
105 | INTEL_OUTPUT_DISPLAYPORT = 7, | |
106 | INTEL_OUTPUT_EDP = 8, | |
107 | INTEL_OUTPUT_DSI = 9, | |
108 | INTEL_OUTPUT_UNKNOWN = 10, | |
109 | INTEL_OUTPUT_DP_MST = 11, | |
110 | }; | |
79e53945 JB |
111 | |
112 | #define INTEL_DVO_CHIP_NONE 0 | |
113 | #define INTEL_DVO_CHIP_LVDS 1 | |
114 | #define INTEL_DVO_CHIP_TMDS 2 | |
115 | #define INTEL_DVO_CHIP_TVOUT 4 | |
116 | ||
dfba2e2d SK |
117 | #define INTEL_DSI_VIDEO_MODE 0 |
118 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 119 | |
79e53945 JB |
120 | struct intel_framebuffer { |
121 | struct drm_framebuffer base; | |
05394f39 | 122 | struct drm_i915_gem_object *obj; |
79e53945 JB |
123 | }; |
124 | ||
37811fcc CW |
125 | struct intel_fbdev { |
126 | struct drm_fb_helper helper; | |
8bcd4553 | 127 | struct intel_framebuffer *fb; |
37811fcc CW |
128 | struct list_head fbdev_list; |
129 | struct drm_display_mode *our_mode; | |
d978ef14 | 130 | int preferred_bpp; |
37811fcc | 131 | }; |
79e53945 | 132 | |
21d40d37 | 133 | struct intel_encoder { |
4ef69c7a | 134 | struct drm_encoder base; |
9a935856 DV |
135 | /* |
136 | * The new crtc this encoder will be driven from. Only differs from | |
137 | * base->crtc while a modeset is in progress. | |
138 | */ | |
139 | struct intel_crtc *new_crtc; | |
140 | ||
6847d71b | 141 | enum intel_output_type type; |
bc079e8b | 142 | unsigned int cloneable; |
5ab432ef | 143 | bool connectors_active; |
21d40d37 | 144 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
145 | bool (*compute_config)(struct intel_encoder *, |
146 | struct intel_crtc_config *); | |
dafd226c | 147 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 148 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 149 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 150 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 151 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 152 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
153 | /* Read out the current hw state of this connector, returning true if |
154 | * the encoder is active. If the encoder is enabled it also set the pipe | |
155 | * it is connected to in the pipe parameter. */ | |
156 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 157 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 158 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
159 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
160 | * be set correctly before calling this function. */ | |
045ac3b5 JB |
161 | void (*get_config)(struct intel_encoder *, |
162 | struct intel_crtc_config *pipe_config); | |
07f9cd0b ID |
163 | /* |
164 | * Called during system suspend after all pending requests for the | |
165 | * encoder are flushed (for example for DP AUX transactions) and | |
166 | * device interrupts are disabled. | |
167 | */ | |
168 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 169 | int crtc_mask; |
1d843f9d | 170 | enum hpd_pin hpd_pin; |
79e53945 JB |
171 | }; |
172 | ||
1d508706 | 173 | struct intel_panel { |
dd06f90e | 174 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 175 | struct drm_display_mode *downclock_mode; |
4d891523 | 176 | int fitting_mode; |
58c68779 JN |
177 | |
178 | /* backlight */ | |
179 | struct { | |
c91c9f32 | 180 | bool present; |
58c68779 | 181 | u32 level; |
6dda730e | 182 | u32 min; |
7bd688cd | 183 | u32 max; |
58c68779 | 184 | bool enabled; |
636baebf JN |
185 | bool combination_mode; /* gen 2/4 only */ |
186 | bool active_low_pwm; | |
58c68779 JN |
187 | struct backlight_device *device; |
188 | } backlight; | |
ab656bb9 JN |
189 | |
190 | void (*backlight_power)(struct intel_connector *, bool enable); | |
1d508706 JN |
191 | }; |
192 | ||
5daa55eb ZW |
193 | struct intel_connector { |
194 | struct drm_connector base; | |
9a935856 DV |
195 | /* |
196 | * The fixed encoder this connector is connected to. | |
197 | */ | |
df0e9248 | 198 | struct intel_encoder *encoder; |
9a935856 DV |
199 | |
200 | /* | |
201 | * The new encoder this connector will be driven. Only differs from | |
202 | * encoder while a modeset is in progress. | |
203 | */ | |
204 | struct intel_encoder *new_encoder; | |
205 | ||
f0947c37 DV |
206 | /* Reads out the current hw, returning true if the connector is enabled |
207 | * and active (i.e. dpms ON state). */ | |
208 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 | 209 | |
4932e2c3 ID |
210 | /* |
211 | * Removes all interfaces through which the connector is accessible | |
212 | * - like sysfs, debugfs entries -, so that no new operations can be | |
213 | * started on the connector. Also makes sure all currently pending | |
214 | * operations finish before returing. | |
215 | */ | |
216 | void (*unregister)(struct intel_connector *); | |
217 | ||
1d508706 JN |
218 | /* Panel info for eDP and LVDS */ |
219 | struct intel_panel panel; | |
9cd300e0 JN |
220 | |
221 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
222 | struct edid *edid; | |
beb60608 | 223 | struct edid *detect_edid; |
821450c6 EE |
224 | |
225 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
226 | state of connector->polled in case hotplug storm detection changes it */ | |
227 | u8 polled; | |
0e32b39c DA |
228 | |
229 | void *port; /* store this opaque as its illegal to dereference it */ | |
230 | ||
231 | struct intel_dp *mst_port; | |
5daa55eb ZW |
232 | }; |
233 | ||
80ad9206 VS |
234 | typedef struct dpll { |
235 | /* given values */ | |
236 | int n; | |
237 | int m1, m2; | |
238 | int p1, p2; | |
239 | /* derived values */ | |
240 | int dot; | |
241 | int vco; | |
242 | int m; | |
243 | int p; | |
244 | } intel_clock_t; | |
245 | ||
eeca778a GP |
246 | struct intel_plane_state { |
247 | struct drm_crtc *crtc; | |
248 | struct drm_framebuffer *fb; | |
249 | struct drm_rect src; | |
250 | struct drm_rect dst; | |
251 | struct drm_rect clip; | |
252 | struct drm_rect orig_src; | |
253 | struct drm_rect orig_dst; | |
254 | bool visible; | |
255 | }; | |
256 | ||
46f297fb | 257 | struct intel_plane_config { |
46f297fb JB |
258 | bool tiled; |
259 | int size; | |
260 | u32 base; | |
261 | }; | |
262 | ||
b8cecdf5 | 263 | struct intel_crtc_config { |
bb760063 DV |
264 | /** |
265 | * quirks - bitfield with hw state readout quirks | |
266 | * | |
267 | * For various reasons the hw state readout code might not be able to | |
268 | * completely faithfully read out the current state. These cases are | |
269 | * tracked with quirk flags so that fastboot and state checker can act | |
270 | * accordingly. | |
271 | */ | |
9953599b DV |
272 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
273 | #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ | |
bb760063 DV |
274 | unsigned long quirks; |
275 | ||
5113bc9b VS |
276 | /* User requested mode, only valid as a starting point to |
277 | * compute adjusted_mode, except in the case of (S)DVO where | |
278 | * it's also for the output timings of the (S)DVO chip. | |
279 | * adjusted_mode will then correspond to the S(DVO) chip's | |
280 | * preferred input timings. */ | |
b8cecdf5 | 281 | struct drm_display_mode requested_mode; |
3c52f4eb | 282 | /* Actual pipe timings ie. what we program into the pipe timing |
241bfc38 | 283 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
b8cecdf5 | 284 | struct drm_display_mode adjusted_mode; |
37327abd VS |
285 | |
286 | /* Pipe source size (ie. panel fitter input size) | |
287 | * All planes will be positioned inside this space, | |
288 | * and get clipped at the edges. */ | |
289 | int pipe_src_w, pipe_src_h; | |
290 | ||
5bfe2ac0 DV |
291 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
292 | * between pch encoders and cpu encoders. */ | |
293 | bool has_pch_encoder; | |
50f3b016 | 294 | |
e43823ec JB |
295 | /* Are we sending infoframes on the attached port */ |
296 | bool has_infoframe; | |
297 | ||
3b117c8f DV |
298 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
299 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
300 | enum transcoder cpu_transcoder; | |
301 | ||
50f3b016 DV |
302 | /* |
303 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
304 | * range fed into the crtcs. | |
305 | */ | |
306 | bool limited_color_range; | |
307 | ||
03afc4a2 DV |
308 | /* DP has a bunch of special case unfortunately, so mark the pipe |
309 | * accordingly. */ | |
310 | bool has_dp_encoder; | |
d8b32247 | 311 | |
6897b4b5 DV |
312 | /* Whether we should send NULL infoframes. Required for audio. */ |
313 | bool has_hdmi_sink; | |
314 | ||
9ed109a7 DV |
315 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
316 | * has_dp_encoder is set. */ | |
317 | bool has_audio; | |
318 | ||
d8b32247 DV |
319 | /* |
320 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
321 | * plane bpp. | |
322 | */ | |
965e0c48 | 323 | bool dither; |
f47709a9 DV |
324 | |
325 | /* Controls for the clock computation, to override various stages. */ | |
326 | bool clock_set; | |
327 | ||
09ede541 DV |
328 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
329 | * work correctly, we need to track this at runtime.*/ | |
330 | bool sdvo_tv_clock; | |
331 | ||
e29c22c0 DV |
332 | /* |
333 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
334 | * required. This is set in the 2nd loop of calling encoder's | |
335 | * ->compute_config if the first pick doesn't work out. | |
336 | */ | |
337 | bool bw_constrained; | |
338 | ||
f47709a9 DV |
339 | /* Settings for the intel dpll used on pretty much everything but |
340 | * haswell. */ | |
80ad9206 | 341 | struct dpll dpll; |
f47709a9 | 342 | |
a43f6e0f DV |
343 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
344 | enum intel_dpll_id shared_dpll; | |
345 | ||
96b7dfb7 S |
346 | /* |
347 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. | |
348 | * - enum skl_dpll on SKL | |
349 | */ | |
de7cfc63 DV |
350 | uint32_t ddi_pll_sel; |
351 | ||
66e985c0 DV |
352 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
353 | struct intel_dpll_hw_state dpll_hw_state; | |
354 | ||
965e0c48 | 355 | int pipe_bpp; |
6cf86a5e | 356 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 357 | |
439d7ac0 PB |
358 | /* m2_n2 for eDP downclock */ |
359 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 360 | bool has_drrs; |
439d7ac0 | 361 | |
ff9a6750 DV |
362 | /* |
363 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
364 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
365 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 366 | */ |
ff9a6750 DV |
367 | int port_clock; |
368 | ||
6cc5f341 DV |
369 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
370 | unsigned pixel_multiplier; | |
2dd24552 JB |
371 | |
372 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
373 | struct { |
374 | u32 control; | |
375 | u32 pgm_ratios; | |
68fc8742 | 376 | u32 lvds_border_bits; |
b074cec8 JB |
377 | } gmch_pfit; |
378 | ||
379 | /* Panel fitter placement and size for Ironlake+ */ | |
380 | struct { | |
381 | u32 pos; | |
382 | u32 size; | |
fd4daa9c | 383 | bool enabled; |
fabf6e51 | 384 | bool force_thru; |
b074cec8 | 385 | } pch_pfit; |
33d29b14 | 386 | |
ca3a0ff8 | 387 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 388 | int fdi_lanes; |
ca3a0ff8 | 389 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
390 | |
391 | bool ips_enabled; | |
cf532bb2 VS |
392 | |
393 | bool double_wide; | |
0e32b39c DA |
394 | |
395 | bool dp_encoder_is_mst; | |
396 | int pbn; | |
b8cecdf5 DV |
397 | }; |
398 | ||
0b2ae6d7 VS |
399 | struct intel_pipe_wm { |
400 | struct intel_wm_level wm[5]; | |
401 | uint32_t linetime; | |
402 | bool fbc_wm_enabled; | |
2a44b76b VS |
403 | bool pipe_enabled; |
404 | bool sprites_enabled; | |
405 | bool sprites_scaled; | |
0b2ae6d7 VS |
406 | }; |
407 | ||
84c33a64 SG |
408 | struct intel_mmio_flip { |
409 | u32 seqno; | |
536f5b5e | 410 | struct intel_engine_cs *ring; |
9362c7c5 | 411 | struct work_struct work; |
84c33a64 SG |
412 | }; |
413 | ||
2ac96d2a PB |
414 | struct skl_pipe_wm { |
415 | struct skl_wm_level wm[8]; | |
416 | struct skl_wm_level trans_wm; | |
417 | uint32_t linetime; | |
418 | }; | |
419 | ||
79e53945 JB |
420 | struct intel_crtc { |
421 | struct drm_crtc base; | |
80824003 JB |
422 | enum pipe pipe; |
423 | enum plane plane; | |
79e53945 | 424 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
425 | /* |
426 | * Whether the crtc and the connected output pipeline is active. Implies | |
427 | * that crtc->enabled is set, i.e. the current mode configuration has | |
428 | * some outputs connected to this crtc. | |
08a48469 DV |
429 | */ |
430 | bool active; | |
6efdf354 | 431 | unsigned long enabled_power_domains; |
4c445e0e | 432 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
652c393a | 433 | bool lowfreq_avail; |
02e792fb | 434 | struct intel_overlay *overlay; |
6b95a207 | 435 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 436 | |
b4a98e57 CW |
437 | atomic_t unpin_work_count; |
438 | ||
e506a0c6 DV |
439 | /* Display surface base address adjustement for pageflips. Note that on |
440 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
441 | * handled in the hw itself (with the TILEOFF register). */ | |
442 | unsigned long dspaddr_offset; | |
443 | ||
05394f39 | 444 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 | 445 | uint32_t cursor_addr; |
cda4b7d3 | 446 | int16_t cursor_width, cursor_height; |
4b0e333e | 447 | uint32_t cursor_cntl; |
dc41c154 | 448 | uint32_t cursor_size; |
4b0e333e | 449 | uint32_t cursor_base; |
4b645f14 | 450 | |
46f297fb | 451 | struct intel_plane_config plane_config; |
b8cecdf5 | 452 | struct intel_crtc_config config; |
50741abc | 453 | struct intel_crtc_config *new_config; |
7668851f | 454 | bool new_enabled; |
b8cecdf5 | 455 | |
10d83730 VS |
456 | /* reset counter value when the last flip was submitted */ |
457 | unsigned int reset_counter; | |
8664281b PZ |
458 | |
459 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
460 | bool cpu_fifo_underrun_disabled; | |
461 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
462 | |
463 | /* per-pipe watermark state */ | |
464 | struct { | |
465 | /* watermarks currently being used */ | |
466 | struct intel_pipe_wm active; | |
2ac96d2a PB |
467 | /* SKL wm values currently in use */ |
468 | struct skl_pipe_wm skl_active; | |
0b2ae6d7 | 469 | } wm; |
8d7849db | 470 | |
80715b2f | 471 | int scanline_offset; |
84c33a64 | 472 | struct intel_mmio_flip mmio_flip; |
79e53945 JB |
473 | }; |
474 | ||
c35426d2 VS |
475 | struct intel_plane_wm_parameters { |
476 | uint32_t horiz_pixels; | |
ed57cb8a | 477 | uint32_t vert_pixels; |
c35426d2 VS |
478 | uint8_t bytes_per_pixel; |
479 | bool enabled; | |
480 | bool scaled; | |
481 | }; | |
482 | ||
b840d907 JB |
483 | struct intel_plane { |
484 | struct drm_plane base; | |
7f1f3851 | 485 | int plane; |
b840d907 JB |
486 | enum pipe pipe; |
487 | struct drm_i915_gem_object *obj; | |
2d354c34 | 488 | bool can_scale; |
b840d907 | 489 | int max_downscale; |
5e1bac2f JB |
490 | int crtc_x, crtc_y; |
491 | unsigned int crtc_w, crtc_h; | |
492 | uint32_t src_x, src_y; | |
493 | uint32_t src_w, src_h; | |
76eebda7 | 494 | unsigned int rotation; |
526682e9 PZ |
495 | |
496 | /* Since we need to change the watermarks before/after | |
497 | * enabling/disabling the planes, we need to store the parameters here | |
498 | * as the other pieces of the struct may not reflect the values we want | |
499 | * for the watermark calculations. Currently only Haswell uses this. | |
500 | */ | |
c35426d2 | 501 | struct intel_plane_wm_parameters wm; |
526682e9 | 502 | |
b840d907 | 503 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 504 | struct drm_crtc *crtc, |
b840d907 JB |
505 | struct drm_framebuffer *fb, |
506 | struct drm_i915_gem_object *obj, | |
507 | int crtc_x, int crtc_y, | |
508 | unsigned int crtc_w, unsigned int crtc_h, | |
509 | uint32_t x, uint32_t y, | |
510 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 VS |
511 | void (*disable_plane)(struct drm_plane *plane, |
512 | struct drm_crtc *crtc); | |
8ea30864 JB |
513 | int (*update_colorkey)(struct drm_plane *plane, |
514 | struct drm_intel_sprite_colorkey *key); | |
515 | void (*get_colorkey)(struct drm_plane *plane, | |
516 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
517 | }; |
518 | ||
b445e3b0 ED |
519 | struct intel_watermark_params { |
520 | unsigned long fifo_size; | |
521 | unsigned long max_wm; | |
522 | unsigned long default_wm; | |
523 | unsigned long guard_size; | |
524 | unsigned long cacheline_size; | |
525 | }; | |
526 | ||
527 | struct cxsr_latency { | |
528 | int is_desktop; | |
529 | int is_ddr3; | |
530 | unsigned long fsb_freq; | |
531 | unsigned long mem_freq; | |
532 | unsigned long display_sr; | |
533 | unsigned long display_hpll_disable; | |
534 | unsigned long cursor_sr; | |
535 | unsigned long cursor_hpll_disable; | |
536 | }; | |
537 | ||
79e53945 | 538 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 539 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 540 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 541 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 542 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
155e6369 | 543 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
79e53945 | 544 | |
f5bbfca3 | 545 | struct intel_hdmi { |
b242b7f7 | 546 | u32 hdmi_reg; |
f5bbfca3 | 547 | int ddc_bus; |
f5bbfca3 | 548 | uint32_t color_range; |
55bc60db | 549 | bool color_range_auto; |
f5bbfca3 ED |
550 | bool has_hdmi_sink; |
551 | bool has_audio; | |
552 | enum hdmi_force_audio force_audio; | |
abedc077 | 553 | bool rgb_quant_range_selectable; |
94a11ddc | 554 | enum hdmi_picture_aspect aspect_ratio; |
f5bbfca3 | 555 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a | 556 | enum hdmi_infoframe_type type, |
fff63867 | 557 | const void *frame, ssize_t len); |
687f4d06 | 558 | void (*set_infoframes)(struct drm_encoder *encoder, |
6897b4b5 | 559 | bool enable, |
687f4d06 | 560 | struct drm_display_mode *adjusted_mode); |
e43823ec | 561 | bool (*infoframe_enabled)(struct drm_encoder *encoder); |
f5bbfca3 ED |
562 | }; |
563 | ||
0e32b39c | 564 | struct intel_dp_mst_encoder; |
b091cd92 | 565 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 566 | |
4f9db5b5 PB |
567 | /** |
568 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
569 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
570 | * parsing for same resolution. | |
571 | */ | |
572 | enum edp_drrs_refresh_rate_type { | |
573 | DRRS_HIGH_RR, | |
574 | DRRS_LOW_RR, | |
575 | DRRS_MAX_RR, /* RR count */ | |
576 | }; | |
577 | ||
54d63ca6 | 578 | struct intel_dp { |
54d63ca6 | 579 | uint32_t output_reg; |
9ed35ab1 | 580 | uint32_t aux_ch_ctl_reg; |
54d63ca6 | 581 | uint32_t DP; |
54d63ca6 SK |
582 | bool has_audio; |
583 | enum hdmi_force_audio force_audio; | |
584 | uint32_t color_range; | |
55bc60db | 585 | bool color_range_auto; |
54d63ca6 SK |
586 | uint8_t link_bw; |
587 | uint8_t lane_count; | |
588 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
2293bb5c | 589 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 590 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
9d1a1031 | 591 | struct drm_dp_aux aux; |
54d63ca6 SK |
592 | uint8_t train_set[4]; |
593 | int panel_power_up_delay; | |
594 | int panel_power_down_delay; | |
595 | int panel_power_cycle_delay; | |
596 | int backlight_on_delay; | |
597 | int backlight_off_delay; | |
54d63ca6 SK |
598 | struct delayed_work panel_vdd_work; |
599 | bool want_panel_vdd; | |
dce56b3c PZ |
600 | unsigned long last_power_cycle; |
601 | unsigned long last_power_on; | |
602 | unsigned long last_backlight_off; | |
5d42f82a | 603 | |
01527b31 CT |
604 | struct notifier_block edp_notifier; |
605 | ||
a4a5d2f8 VS |
606 | /* |
607 | * Pipe whose power sequencer is currently locked into | |
608 | * this port. Only relevant on VLV/CHV. | |
609 | */ | |
610 | enum pipe pps_pipe; | |
36b5f425 | 611 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 612 | |
06ea66b6 | 613 | bool use_tps3; |
0e32b39c DA |
614 | bool can_mst; /* this port supports mst */ |
615 | bool is_mst; | |
616 | int active_mst_links; | |
617 | /* connector directly attached - won't be use for modeset in mst world */ | |
dd06f90e | 618 | struct intel_connector *attached_connector; |
ec5b01dd | 619 | |
0e32b39c DA |
620 | /* mst connector list */ |
621 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
622 | struct drm_dp_mst_topology_mgr mst_mgr; | |
623 | ||
ec5b01dd | 624 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
625 | /* |
626 | * This function returns the value we have to program the AUX_CTL | |
627 | * register with to kick off an AUX transaction. | |
628 | */ | |
629 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
630 | bool has_aux_irq, | |
631 | int send_bytes, | |
632 | uint32_t aux_clock_divider); | |
4f9db5b5 PB |
633 | struct { |
634 | enum drrs_support_type type; | |
635 | enum edp_drrs_refresh_rate_type refresh_rate_type; | |
439d7ac0 | 636 | struct mutex mutex; |
4f9db5b5 PB |
637 | } drrs_state; |
638 | ||
54d63ca6 SK |
639 | }; |
640 | ||
da63a9f2 PZ |
641 | struct intel_digital_port { |
642 | struct intel_encoder base; | |
174edf1f | 643 | enum port port; |
bcf53de4 | 644 | u32 saved_port_bits; |
da63a9f2 PZ |
645 | struct intel_dp dp; |
646 | struct intel_hdmi hdmi; | |
13cf5504 | 647 | bool (*hpd_pulse)(struct intel_digital_port *, bool); |
da63a9f2 PZ |
648 | }; |
649 | ||
0e32b39c DA |
650 | struct intel_dp_mst_encoder { |
651 | struct intel_encoder base; | |
652 | enum pipe pipe; | |
653 | struct intel_digital_port *primary; | |
654 | void *port; /* store this opaque as its illegal to dereference it */ | |
655 | }; | |
656 | ||
89b667f8 JB |
657 | static inline int |
658 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
659 | { | |
660 | switch (dport->port) { | |
661 | case PORT_B: | |
00fc31b7 | 662 | case PORT_D: |
e4607fcf | 663 | return DPIO_CH0; |
89b667f8 | 664 | case PORT_C: |
e4607fcf | 665 | return DPIO_CH1; |
89b667f8 JB |
666 | default: |
667 | BUG(); | |
668 | } | |
669 | } | |
670 | ||
eb69b0e5 CML |
671 | static inline int |
672 | vlv_pipe_to_channel(enum pipe pipe) | |
673 | { | |
674 | switch (pipe) { | |
675 | case PIPE_A: | |
676 | case PIPE_C: | |
677 | return DPIO_CH0; | |
678 | case PIPE_B: | |
679 | return DPIO_CH1; | |
680 | default: | |
681 | BUG(); | |
682 | } | |
683 | } | |
684 | ||
f875c15a CW |
685 | static inline struct drm_crtc * |
686 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
687 | { | |
688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
689 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
690 | } | |
691 | ||
417ae147 CW |
692 | static inline struct drm_crtc * |
693 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
694 | { | |
695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
696 | return dev_priv->plane_to_crtc_mapping[plane]; | |
697 | } | |
698 | ||
4e5359cd SF |
699 | struct intel_unpin_work { |
700 | struct work_struct work; | |
b4a98e57 | 701 | struct drm_crtc *crtc; |
05394f39 CW |
702 | struct drm_i915_gem_object *old_fb_obj; |
703 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 704 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
705 | atomic_t pending; |
706 | #define INTEL_FLIP_INACTIVE 0 | |
707 | #define INTEL_FLIP_PENDING 1 | |
708 | #define INTEL_FLIP_COMPLETE 2 | |
75f7f3ec VS |
709 | u32 flip_count; |
710 | u32 gtt_offset; | |
d6bbafa1 CW |
711 | struct intel_engine_cs *flip_queued_ring; |
712 | u32 flip_queued_seqno; | |
713 | int flip_queued_vblank; | |
714 | int flip_ready_vblank; | |
4e5359cd SF |
715 | bool enable_stall_check; |
716 | }; | |
717 | ||
d9e55608 | 718 | struct intel_set_config { |
1aa4b628 DV |
719 | struct drm_encoder **save_connector_encoders; |
720 | struct drm_crtc **save_encoder_crtcs; | |
7668851f | 721 | bool *save_crtc_enabled; |
5e2b584e DV |
722 | |
723 | bool fb_changed; | |
724 | bool mode_changed; | |
d9e55608 DV |
725 | }; |
726 | ||
5f1aae65 PZ |
727 | struct intel_load_detect_pipe { |
728 | struct drm_framebuffer *release_fb; | |
729 | bool load_detect_temp; | |
730 | int dpms_mode; | |
731 | }; | |
79e53945 | 732 | |
5f1aae65 PZ |
733 | static inline struct intel_encoder * |
734 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
735 | { |
736 | return to_intel_connector(connector)->encoder; | |
737 | } | |
738 | ||
da63a9f2 PZ |
739 | static inline struct intel_digital_port * |
740 | enc_to_dig_port(struct drm_encoder *encoder) | |
741 | { | |
742 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
743 | } |
744 | ||
0e32b39c DA |
745 | static inline struct intel_dp_mst_encoder * |
746 | enc_to_mst(struct drm_encoder *encoder) | |
747 | { | |
748 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
749 | } | |
750 | ||
9ff8c9ba ID |
751 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
752 | { | |
753 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
754 | } |
755 | ||
756 | static inline struct intel_digital_port * | |
757 | dp_to_dig_port(struct intel_dp *intel_dp) | |
758 | { | |
759 | return container_of(intel_dp, struct intel_digital_port, dp); | |
760 | } | |
761 | ||
762 | static inline struct intel_digital_port * | |
763 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
764 | { | |
765 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
766 | } |
767 | ||
6af31a65 DL |
768 | /* |
769 | * Returns the number of planes for this pipe, ie the number of sprites + 1 | |
770 | * (primary plane). This doesn't count the cursor plane then. | |
771 | */ | |
772 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) | |
773 | { | |
774 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; | |
775 | } | |
5f1aae65 | 776 | |
47339cd9 | 777 | /* intel_fifo_underrun.c */ |
a72e4c9f | 778 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 779 | enum pipe pipe, bool enable); |
a72e4c9f | 780 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 PZ |
781 | enum transcoder pch_transcoder, |
782 | bool enable); | |
1f7247c0 DV |
783 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
784 | enum pipe pipe); | |
785 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
786 | enum transcoder pch_transcoder); | |
a72e4c9f | 787 | void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv); |
47339cd9 DV |
788 | |
789 | /* i915_irq.c */ | |
480c8033 DV |
790 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
791 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
792 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
793 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
3cc134e3 | 794 | void gen6_reset_rps_interrupts(struct drm_device *dev); |
b900b949 ID |
795 | void gen6_enable_rps_interrupts(struct drm_device *dev); |
796 | void gen6_disable_rps_interrupts(struct drm_device *dev); | |
b963291c DV |
797 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
798 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
799 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
800 | { | |
801 | /* | |
802 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
803 | * this is the only thing we need to check. | |
804 | */ | |
2aeb7d3a | 805 | return dev_priv->pm.irqs_enabled; |
9df7575f JB |
806 | } |
807 | ||
a225f079 | 808 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
d49bdb0e | 809 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); |
5f1aae65 | 810 | |
5f1aae65 | 811 | /* intel_crt.c */ |
87440425 | 812 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
813 | |
814 | ||
815 | /* intel_ddi.c */ | |
87440425 PZ |
816 | void intel_prepare_ddi(struct drm_device *dev); |
817 | void hsw_fdi_link_train(struct drm_crtc *crtc); | |
818 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
819 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
820 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
821 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); | |
822 | void intel_ddi_pll_init(struct drm_device *dev); | |
823 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); | |
824 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
825 | enum transcoder cpu_transcoder); | |
826 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
827 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
566b734a | 828 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
87440425 PZ |
829 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
830 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); | |
831 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
832 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
833 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
834 | struct intel_crtc_config *pipe_config); | |
5f1aae65 | 835 | |
44905a27 | 836 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
0e32b39c DA |
837 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
838 | struct intel_crtc_config *pipe_config); | |
839 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); | |
5f1aae65 | 840 | |
b680c37a | 841 | /* intel_frontbuffer.c */ |
f99d7069 DV |
842 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
843 | struct intel_engine_cs *ring); | |
844 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
845 | unsigned frontbuffer_bits); | |
846 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
847 | unsigned frontbuffer_bits); | |
848 | void intel_frontbuffer_flush(struct drm_device *dev, | |
849 | unsigned frontbuffer_bits); | |
850 | /** | |
5c323b2a | 851 | * intel_frontbuffer_flip - synchronous frontbuffer flip |
f99d7069 DV |
852 | * @dev: DRM device |
853 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
854 | * | |
855 | * This function gets called after scheduling a flip on @obj. This is for | |
856 | * synchronous plane updates which will happen on the next vblank and which will | |
857 | * not get delayed by pending gpu rendering. | |
858 | * | |
859 | * Can be called without any locks held. | |
860 | */ | |
861 | static inline | |
862 | void intel_frontbuffer_flip(struct drm_device *dev, | |
863 | unsigned frontbuffer_bits) | |
864 | { | |
865 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
866 | } | |
867 | ||
868 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); | |
b680c37a DV |
869 | |
870 | ||
7c10a2b5 JN |
871 | /* intel_audio.c */ |
872 | void intel_init_audio(struct drm_device *dev); | |
69bfe1a9 JN |
873 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
874 | void intel_audio_codec_disable(struct intel_encoder *encoder); | |
7c10a2b5 | 875 | |
b680c37a DV |
876 | /* intel_display.c */ |
877 | const char *intel_output_name(int output); | |
878 | bool intel_has_pending_fb_unpin(struct drm_device *dev); | |
879 | int intel_pch_rawclk(struct drm_device *dev); | |
880 | void intel_mark_busy(struct drm_device *dev); | |
87440425 PZ |
881 | void intel_mark_idle(struct drm_device *dev); |
882 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
b04c5bd6 | 883 | void intel_crtc_control(struct drm_crtc *crtc, bool enable); |
87440425 PZ |
884 | void intel_crtc_update_dpms(struct drm_crtc *crtc); |
885 | void intel_encoder_destroy(struct drm_encoder *encoder); | |
886 | void intel_connector_dpms(struct drm_connector *, int mode); | |
887 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
888 | void intel_modeset_check_state(struct drm_device *dev); | |
b0ea7d37 DL |
889 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
890 | struct intel_digital_port *port); | |
87440425 PZ |
891 | void intel_connector_attach_encoder(struct intel_connector *connector, |
892 | struct intel_encoder *encoder); | |
893 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
894 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
895 | struct drm_crtc *crtc); | |
752aa88a | 896 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
897 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
898 | struct drm_file *file_priv); | |
87440425 PZ |
899 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
900 | enum pipe pipe); | |
4093561b | 901 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
4f905cf9 DV |
902 | static inline void |
903 | intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
904 | { | |
905 | drm_wait_one_vblank(dev, pipe); | |
906 | } | |
87440425 | 907 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf CML |
908 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
909 | struct intel_digital_port *dport); | |
87440425 PZ |
910 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
911 | struct drm_display_mode *mode, | |
51fd371b RC |
912 | struct intel_load_detect_pipe *old, |
913 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 914 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 915 | struct intel_load_detect_pipe *old); |
850c4cdc TU |
916 | int intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
917 | struct drm_framebuffer *fb, | |
a4872ba6 | 918 | struct intel_engine_cs *pipelined); |
87440425 | 919 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
a8bb6818 DV |
920 | struct drm_framebuffer * |
921 | __intel_framebuffer_create(struct drm_device *dev, | |
87440425 PZ |
922 | struct drm_mode_fb_cmd2 *mode_cmd, |
923 | struct drm_i915_gem_object *obj); | |
87440425 PZ |
924 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
925 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
926 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
d6bbafa1 | 927 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
716c2e55 DV |
928 | |
929 | /* shared dpll functions */ | |
5f1aae65 | 930 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
55607e8a DV |
931 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
932 | struct intel_shared_dpll *pll, | |
933 | bool state); | |
934 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
935 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
716c2e55 DV |
936 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); |
937 | void intel_put_shared_dpll(struct intel_crtc *crtc); | |
938 | ||
d288f65f VS |
939 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
940 | const struct dpll *dpll); | |
941 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); | |
942 | ||
716c2e55 | 943 | /* modesetting asserts */ |
b680c37a DV |
944 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
945 | enum pipe pipe); | |
55607e8a DV |
946 | void assert_pll(struct drm_i915_private *dev_priv, |
947 | enum pipe pipe, bool state); | |
948 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
949 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
950 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
951 | enum pipe pipe, bool state); | |
952 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
953 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 954 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
955 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
956 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
87440425 PZ |
957 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
958 | unsigned int tiling_mode, | |
959 | unsigned int bpp, | |
960 | unsigned int pitch); | |
7514747d VS |
961 | void intel_prepare_reset(struct drm_device *dev); |
962 | void intel_finish_reset(struct drm_device *dev); | |
a14cb6fc PZ |
963 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
964 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
87440425 PZ |
965 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
966 | struct intel_crtc_config *pipe_config); | |
f769cd24 | 967 | void intel_dp_set_m_n(struct intel_crtc *crtc); |
87440425 PZ |
968 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
969 | void | |
5f1aae65 PZ |
970 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
971 | int dotclock); | |
87440425 | 972 | bool intel_crtc_active(struct drm_crtc *crtc); |
20bc8673 VS |
973 | void hsw_enable_ips(struct intel_crtc *crtc); |
974 | void hsw_disable_ips(struct intel_crtc *crtc); | |
319be8ae ID |
975 | enum intel_display_power_domain |
976 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); | |
f6a83288 DV |
977 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
978 | struct intel_crtc_config *pipe_config); | |
46f297fb | 979 | int intel_format_to_fourcc(int format); |
46a55d30 | 980 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
e2fcdaa9 | 981 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); |
8ea30864 | 982 | |
5f1aae65 | 983 | /* intel_dp.c */ |
87440425 PZ |
984 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
985 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |
986 | struct intel_connector *intel_connector); | |
87440425 PZ |
987 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
988 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
989 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); | |
990 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
991 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
992 | void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
d2e216d0 | 993 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
87440425 PZ |
994 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
995 | struct intel_crtc_config *pipe_config); | |
5d8a7752 | 996 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
13cf5504 DA |
997 | bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
998 | bool long_hpd); | |
4be73780 DV |
999 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
1000 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
24f3e092 | 1001 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
1002 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1003 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
439d7ac0 | 1004 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); |
0e32b39c DA |
1005 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
1006 | void intel_dp_mst_suspend(struct drm_device *dev); | |
1007 | void intel_dp_mst_resume(struct drm_device *dev); | |
1008 | int intel_dp_max_link_bw(struct intel_dp *intel_dp); | |
1009 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); | |
773538e8 | 1010 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0bc12bcb RV |
1011 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
1012 | void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes); | |
1013 | ||
0e32b39c DA |
1014 | /* intel_dp_mst.c */ |
1015 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1016 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
5f1aae65 | 1017 | /* intel_dsi.c */ |
4328633d | 1018 | void intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
1019 | |
1020 | ||
1021 | /* intel_dvo.c */ | |
87440425 | 1022 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
1023 | |
1024 | ||
0632fef6 | 1025 | /* legacy fbdev emulation in intel_fbdev.c */ |
4520f53a DV |
1026 | #ifdef CONFIG_DRM_I915_FBDEV |
1027 | extern int intel_fbdev_init(struct drm_device *dev); | |
d1d70677 | 1028 | extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); |
4520f53a | 1029 | extern void intel_fbdev_fini(struct drm_device *dev); |
82e3b8c1 | 1030 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 DV |
1031 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1032 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
1033 | #else |
1034 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1035 | { | |
1036 | return 0; | |
1037 | } | |
5f1aae65 | 1038 | |
d1d70677 | 1039 | static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) |
4520f53a DV |
1040 | { |
1041 | } | |
1042 | ||
1043 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
1044 | { | |
1045 | } | |
1046 | ||
82e3b8c1 | 1047 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a DV |
1048 | { |
1049 | } | |
1050 | ||
0632fef6 | 1051 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
1052 | { |
1053 | } | |
1054 | #endif | |
5f1aae65 PZ |
1055 | |
1056 | /* intel_hdmi.c */ | |
87440425 PZ |
1057 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
1058 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |
1059 | struct intel_connector *intel_connector); | |
1060 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1061 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
1062 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
1063 | |
1064 | ||
1065 | /* intel_lvds.c */ | |
87440425 PZ |
1066 | void intel_lvds_init(struct drm_device *dev); |
1067 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
1068 | |
1069 | ||
1070 | /* intel_modes.c */ | |
1071 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 1072 | struct edid *edid); |
5f1aae65 | 1073 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
1074 | void intel_attach_force_audio_property(struct drm_connector *connector); |
1075 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
5f1aae65 PZ |
1076 | |
1077 | ||
1078 | /* intel_overlay.c */ | |
87440425 PZ |
1079 | void intel_setup_overlay(struct drm_device *dev); |
1080 | void intel_cleanup_overlay(struct drm_device *dev); | |
1081 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
1082 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
1083 | struct drm_file *file_priv); | |
1084 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
1085 | struct drm_file *file_priv); | |
5f1aae65 PZ |
1086 | |
1087 | ||
1088 | /* intel_panel.c */ | |
87440425 | 1089 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1090 | struct drm_display_mode *fixed_mode, |
1091 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
1092 | void intel_panel_fini(struct intel_panel *panel); |
1093 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1094 | struct drm_display_mode *adjusted_mode); | |
1095 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
1096 | struct intel_crtc_config *pipe_config, | |
1097 | int fitting_mode); | |
1098 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
1099 | struct intel_crtc_config *pipe_config, | |
1100 | int fitting_mode); | |
6dda730e JN |
1101 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1102 | u32 level, u32 max); | |
6517d273 | 1103 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
752aa88a JB |
1104 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1105 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 1106 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
7bd688cd | 1107 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
87440425 | 1108 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
ec9ed197 VK |
1109 | extern struct drm_display_mode *intel_find_panel_downclock( |
1110 | struct drm_device *dev, | |
1111 | struct drm_display_mode *fixed_mode, | |
1112 | struct drm_connector *connector); | |
0962c3c9 VS |
1113 | void intel_backlight_register(struct drm_device *dev); |
1114 | void intel_backlight_unregister(struct drm_device *dev); | |
1115 | ||
5f1aae65 | 1116 | |
0bc12bcb | 1117 | /* intel_psr.c */ |
0bc12bcb RV |
1118 | void intel_psr_enable(struct intel_dp *intel_dp); |
1119 | void intel_psr_disable(struct intel_dp *intel_dp); | |
1120 | void intel_psr_invalidate(struct drm_device *dev, | |
1121 | unsigned frontbuffer_bits); | |
1122 | void intel_psr_flush(struct drm_device *dev, | |
1123 | unsigned frontbuffer_bits); | |
1124 | void intel_psr_init(struct drm_device *dev); | |
1125 | ||
9c065a7d DV |
1126 | /* intel_runtime_pm.c */ |
1127 | int intel_power_domains_init(struct drm_i915_private *); | |
f458ebbc | 1128 | void intel_power_domains_fini(struct drm_i915_private *); |
9c065a7d | 1129 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
f458ebbc | 1130 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
9c065a7d | 1131 | |
f458ebbc DV |
1132 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
1133 | enum intel_display_power_domain domain); | |
1134 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1135 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1136 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1137 | enum intel_display_power_domain domain); | |
1138 | void intel_display_power_put(struct drm_i915_private *dev_priv, | |
1139 | enum intel_display_power_domain domain); | |
1140 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); | |
1141 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
1142 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); | |
1143 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); | |
1144 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
1145 | ||
d9bc89d9 DV |
1146 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
1147 | ||
5f1aae65 | 1148 | /* intel_pm.c */ |
87440425 PZ |
1149 | void intel_init_clock_gating(struct drm_device *dev); |
1150 | void intel_suspend_hw(struct drm_device *dev); | |
546c81fd | 1151 | int ilk_wm_max_level(const struct drm_device *dev); |
87440425 PZ |
1152 | void intel_update_watermarks(struct drm_crtc *crtc); |
1153 | void intel_update_sprite_watermarks(struct drm_plane *plane, | |
1154 | struct drm_crtc *crtc, | |
ed57cb8a DL |
1155 | uint32_t sprite_width, |
1156 | uint32_t sprite_height, | |
1157 | int pixel_size, | |
87440425 PZ |
1158 | bool enabled, bool scaled); |
1159 | void intel_init_pm(struct drm_device *dev); | |
f742a552 | 1160 | void intel_pm_setup(struct drm_device *dev); |
87440425 PZ |
1161 | bool intel_fbc_enabled(struct drm_device *dev); |
1162 | void intel_update_fbc(struct drm_device *dev); | |
1163 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
1164 | void intel_gpu_ips_teardown(void); | |
ae48434c ID |
1165 | void intel_init_gt_powersave(struct drm_device *dev); |
1166 | void intel_cleanup_gt_powersave(struct drm_device *dev); | |
87440425 PZ |
1167 | void intel_enable_gt_powersave(struct drm_device *dev); |
1168 | void intel_disable_gt_powersave(struct drm_device *dev); | |
156c7ca0 | 1169 | void intel_suspend_gt_powersave(struct drm_device *dev); |
c6df39b5 | 1170 | void intel_reset_gt_powersave(struct drm_device *dev); |
87440425 | 1171 | void ironlake_teardown_rc6(struct drm_device *dev); |
c67a470b | 1172 | void gen6_update_ring_freq(struct drm_device *dev); |
076e29f2 DV |
1173 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
1174 | void gen6_rps_boost(struct drm_i915_private *dev_priv); | |
243e6a44 | 1175 | void ilk_wm_get_hw_state(struct drm_device *dev); |
3078999f | 1176 | void skl_wm_get_hw_state(struct drm_device *dev); |
08db6652 DL |
1177 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
1178 | struct skl_ddb_allocation *ddb /* out */); | |
d2011dc8 | 1179 | |
72662e10 | 1180 | |
5f1aae65 | 1181 | /* intel_sdvo.c */ |
87440425 | 1182 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
96a02917 | 1183 | |
2b28bb1b | 1184 | |
5f1aae65 | 1185 | /* intel_sprite.c */ |
87440425 | 1186 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
1dba99f4 | 1187 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
87440425 | 1188 | enum plane plane); |
48404c1e SJ |
1189 | int intel_plane_set_property(struct drm_plane *plane, |
1190 | struct drm_property *prop, | |
1191 | uint64_t val); | |
e57465f3 | 1192 | int intel_plane_restore(struct drm_plane *plane); |
87440425 PZ |
1193 | void intel_plane_disable(struct drm_plane *plane); |
1194 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
1195 | struct drm_file *file_priv); | |
1196 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
1197 | struct drm_file *file_priv); | |
9362c7c5 ACO |
1198 | bool intel_pipe_update_start(struct intel_crtc *crtc, |
1199 | uint32_t *start_vbl_count); | |
1200 | void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); | |
5f1aae65 PZ |
1201 | |
1202 | /* intel_tv.c */ | |
87440425 | 1203 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 1204 | |
79e53945 | 1205 | #endif /* __INTEL_DRV_H__ */ |