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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
31 | /* | |
32 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". | |
33 | * These expanded contexts enable a number of new abilities, especially | |
34 | * "Execlists" (also implemented in this file). | |
35 | * | |
36 | * Execlists are the new method by which, on gen8+ hardware, workloads are | |
37 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
38 | */ | |
39 | ||
40 | #include <drm/drmP.h> | |
41 | #include <drm/i915_drm.h> | |
42 | #include "i915_drv.h" | |
127f1003 | 43 | |
8c857917 OM |
44 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
45 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
46 | ||
47 | #define GEN8_LR_CONTEXT_ALIGN 4096 | |
48 | ||
8670d6f9 OM |
49 | #define RING_ELSP(ring) ((ring)->mmio_base+0x230) |
50 | #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) | |
51 | ||
52 | #define CTX_LRI_HEADER_0 0x01 | |
53 | #define CTX_CONTEXT_CONTROL 0x02 | |
54 | #define CTX_RING_HEAD 0x04 | |
55 | #define CTX_RING_TAIL 0x06 | |
56 | #define CTX_RING_BUFFER_START 0x08 | |
57 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
58 | #define CTX_BB_HEAD_U 0x0c | |
59 | #define CTX_BB_HEAD_L 0x0e | |
60 | #define CTX_BB_STATE 0x10 | |
61 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
62 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
63 | #define CTX_SECOND_BB_STATE 0x16 | |
64 | #define CTX_BB_PER_CTX_PTR 0x18 | |
65 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
66 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
67 | #define CTX_LRI_HEADER_1 0x21 | |
68 | #define CTX_CTX_TIMESTAMP 0x22 | |
69 | #define CTX_PDP3_UDW 0x24 | |
70 | #define CTX_PDP3_LDW 0x26 | |
71 | #define CTX_PDP2_UDW 0x28 | |
72 | #define CTX_PDP2_LDW 0x2a | |
73 | #define CTX_PDP1_UDW 0x2c | |
74 | #define CTX_PDP1_LDW 0x2e | |
75 | #define CTX_PDP0_UDW 0x30 | |
76 | #define CTX_PDP0_LDW 0x32 | |
77 | #define CTX_LRI_HEADER_2 0x41 | |
78 | #define CTX_R_PWR_CLK_STATE 0x42 | |
79 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
80 | ||
127f1003 OM |
81 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
82 | { | |
bd84b1e9 DV |
83 | WARN_ON(i915.enable_ppgtt == -1); |
84 | ||
127f1003 OM |
85 | if (enable_execlists == 0) |
86 | return 0; | |
87 | ||
88 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev)) | |
89 | return 1; | |
90 | ||
91 | return 0; | |
92 | } | |
ede7d42b | 93 | |
454afebd OM |
94 | int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
95 | struct intel_engine_cs *ring, | |
96 | struct intel_context *ctx, | |
97 | struct drm_i915_gem_execbuffer2 *args, | |
98 | struct list_head *vmas, | |
99 | struct drm_i915_gem_object *batch_obj, | |
100 | u64 exec_start, u32 flags) | |
101 | { | |
102 | /* TODO */ | |
103 | return 0; | |
104 | } | |
105 | ||
106 | void intel_logical_ring_stop(struct intel_engine_cs *ring) | |
107 | { | |
108 | /* TODO */ | |
109 | } | |
110 | ||
82e104cc OM |
111 | void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) |
112 | { | |
113 | intel_logical_ring_advance(ringbuf); | |
114 | ||
115 | if (intel_ring_stopped(ringbuf->ring)) | |
116 | return; | |
117 | ||
118 | /* TODO: how to submit a context to the ELSP is not here yet */ | |
119 | } | |
120 | ||
121 | static int logical_ring_alloc_seqno(struct intel_engine_cs *ring) | |
122 | { | |
123 | if (ring->outstanding_lazy_seqno) | |
124 | return 0; | |
125 | ||
126 | if (ring->preallocated_lazy_request == NULL) { | |
127 | struct drm_i915_gem_request *request; | |
128 | ||
129 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
130 | if (request == NULL) | |
131 | return -ENOMEM; | |
132 | ||
133 | ring->preallocated_lazy_request = request; | |
134 | } | |
135 | ||
136 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); | |
137 | } | |
138 | ||
139 | static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, | |
140 | int bytes) | |
141 | { | |
142 | struct intel_engine_cs *ring = ringbuf->ring; | |
143 | struct drm_i915_gem_request *request; | |
144 | u32 seqno = 0; | |
145 | int ret; | |
146 | ||
147 | if (ringbuf->last_retired_head != -1) { | |
148 | ringbuf->head = ringbuf->last_retired_head; | |
149 | ringbuf->last_retired_head = -1; | |
150 | ||
151 | ringbuf->space = intel_ring_space(ringbuf); | |
152 | if (ringbuf->space >= bytes) | |
153 | return 0; | |
154 | } | |
155 | ||
156 | list_for_each_entry(request, &ring->request_list, list) { | |
157 | if (__intel_ring_space(request->tail, ringbuf->tail, | |
158 | ringbuf->size) >= bytes) { | |
159 | seqno = request->seqno; | |
160 | break; | |
161 | } | |
162 | } | |
163 | ||
164 | if (seqno == 0) | |
165 | return -ENOSPC; | |
166 | ||
167 | ret = i915_wait_seqno(ring, seqno); | |
168 | if (ret) | |
169 | return ret; | |
170 | ||
171 | /* TODO: make sure we update the right ringbuffer's last_retired_head | |
172 | * when retiring requests */ | |
173 | i915_gem_retire_requests_ring(ring); | |
174 | ringbuf->head = ringbuf->last_retired_head; | |
175 | ringbuf->last_retired_head = -1; | |
176 | ||
177 | ringbuf->space = intel_ring_space(ringbuf); | |
178 | return 0; | |
179 | } | |
180 | ||
181 | static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, | |
182 | int bytes) | |
183 | { | |
184 | struct intel_engine_cs *ring = ringbuf->ring; | |
185 | struct drm_device *dev = ring->dev; | |
186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
187 | unsigned long end; | |
188 | int ret; | |
189 | ||
190 | ret = logical_ring_wait_request(ringbuf, bytes); | |
191 | if (ret != -ENOSPC) | |
192 | return ret; | |
193 | ||
194 | /* Force the context submission in case we have been skipping it */ | |
195 | intel_logical_ring_advance_and_submit(ringbuf); | |
196 | ||
197 | /* With GEM the hangcheck timer should kick us out of the loop, | |
198 | * leaving it early runs the risk of corrupting GEM state (due | |
199 | * to running on almost untested codepaths). But on resume | |
200 | * timers don't work yet, so prevent a complete hang in that | |
201 | * case by choosing an insanely large timeout. */ | |
202 | end = jiffies + 60 * HZ; | |
203 | ||
204 | do { | |
205 | ringbuf->head = I915_READ_HEAD(ring); | |
206 | ringbuf->space = intel_ring_space(ringbuf); | |
207 | if (ringbuf->space >= bytes) { | |
208 | ret = 0; | |
209 | break; | |
210 | } | |
211 | ||
212 | msleep(1); | |
213 | ||
214 | if (dev_priv->mm.interruptible && signal_pending(current)) { | |
215 | ret = -ERESTARTSYS; | |
216 | break; | |
217 | } | |
218 | ||
219 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
220 | dev_priv->mm.interruptible); | |
221 | if (ret) | |
222 | break; | |
223 | ||
224 | if (time_after(jiffies, end)) { | |
225 | ret = -EBUSY; | |
226 | break; | |
227 | } | |
228 | } while (1); | |
229 | ||
230 | return ret; | |
231 | } | |
232 | ||
233 | static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) | |
234 | { | |
235 | uint32_t __iomem *virt; | |
236 | int rem = ringbuf->size - ringbuf->tail; | |
237 | ||
238 | if (ringbuf->space < rem) { | |
239 | int ret = logical_ring_wait_for_space(ringbuf, rem); | |
240 | ||
241 | if (ret) | |
242 | return ret; | |
243 | } | |
244 | ||
245 | virt = ringbuf->virtual_start + ringbuf->tail; | |
246 | rem /= 4; | |
247 | while (rem--) | |
248 | iowrite32(MI_NOOP, virt++); | |
249 | ||
250 | ringbuf->tail = 0; | |
251 | ringbuf->space = intel_ring_space(ringbuf); | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
256 | static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) | |
257 | { | |
258 | int ret; | |
259 | ||
260 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { | |
261 | ret = logical_ring_wrap_buffer(ringbuf); | |
262 | if (unlikely(ret)) | |
263 | return ret; | |
264 | } | |
265 | ||
266 | if (unlikely(ringbuf->space < bytes)) { | |
267 | ret = logical_ring_wait_for_space(ringbuf, bytes); | |
268 | if (unlikely(ret)) | |
269 | return ret; | |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) | |
276 | { | |
277 | struct intel_engine_cs *ring = ringbuf->ring; | |
278 | struct drm_device *dev = ring->dev; | |
279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
280 | int ret; | |
281 | ||
282 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
283 | dev_priv->mm.interruptible); | |
284 | if (ret) | |
285 | return ret; | |
286 | ||
287 | ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); | |
288 | if (ret) | |
289 | return ret; | |
290 | ||
291 | /* Preallocate the olr before touching the ring */ | |
292 | ret = logical_ring_alloc_seqno(ring); | |
293 | if (ret) | |
294 | return ret; | |
295 | ||
296 | ringbuf->space -= num_dwords * sizeof(uint32_t); | |
297 | return 0; | |
298 | } | |
299 | ||
9b1136d5 OM |
300 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
301 | { | |
302 | struct drm_device *dev = ring->dev; | |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
304 | ||
305 | I915_WRITE(RING_MODE_GEN7(ring), | |
306 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
307 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
308 | POSTING_READ(RING_MODE_GEN7(ring)); | |
309 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); | |
310 | ||
311 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
317 | { | |
318 | struct drm_device *dev = ring->dev; | |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
320 | int ret; | |
321 | ||
322 | ret = gen8_init_common_ring(ring); | |
323 | if (ret) | |
324 | return ret; | |
325 | ||
326 | /* We need to disable the AsyncFlip performance optimisations in order | |
327 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
328 | * programmed to '1' on all products. | |
329 | * | |
330 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
331 | */ | |
332 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
333 | ||
334 | ret = intel_init_pipe_control(ring); | |
335 | if (ret) | |
336 | return ret; | |
337 | ||
338 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
339 | ||
340 | return ret; | |
341 | } | |
342 | ||
4712274c OM |
343 | static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
344 | u32 invalidate_domains, | |
345 | u32 unused) | |
346 | { | |
347 | struct intel_engine_cs *ring = ringbuf->ring; | |
348 | struct drm_device *dev = ring->dev; | |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
350 | uint32_t cmd; | |
351 | int ret; | |
352 | ||
353 | ret = intel_logical_ring_begin(ringbuf, 4); | |
354 | if (ret) | |
355 | return ret; | |
356 | ||
357 | cmd = MI_FLUSH_DW + 1; | |
358 | ||
359 | if (ring == &dev_priv->ring[VCS]) { | |
360 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) | |
361 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | | |
362 | MI_FLUSH_DW_STORE_INDEX | | |
363 | MI_FLUSH_DW_OP_STOREDW; | |
364 | } else { | |
365 | if (invalidate_domains & I915_GEM_DOMAIN_RENDER) | |
366 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | | |
367 | MI_FLUSH_DW_OP_STOREDW; | |
368 | } | |
369 | ||
370 | intel_logical_ring_emit(ringbuf, cmd); | |
371 | intel_logical_ring_emit(ringbuf, | |
372 | I915_GEM_HWS_SCRATCH_ADDR | | |
373 | MI_FLUSH_DW_USE_GTT); | |
374 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
375 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
376 | intel_logical_ring_advance(ringbuf); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, | |
382 | u32 invalidate_domains, | |
383 | u32 flush_domains) | |
384 | { | |
385 | struct intel_engine_cs *ring = ringbuf->ring; | |
386 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
387 | u32 flags = 0; | |
388 | int ret; | |
389 | ||
390 | flags |= PIPE_CONTROL_CS_STALL; | |
391 | ||
392 | if (flush_domains) { | |
393 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
394 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
395 | } | |
396 | ||
397 | if (invalidate_domains) { | |
398 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
399 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
400 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
401 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
402 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
403 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
404 | flags |= PIPE_CONTROL_QW_WRITE; | |
405 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
406 | } | |
407 | ||
408 | ret = intel_logical_ring_begin(ringbuf, 6); | |
409 | if (ret) | |
410 | return ret; | |
411 | ||
412 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
413 | intel_logical_ring_emit(ringbuf, flags); | |
414 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
415 | intel_logical_ring_emit(ringbuf, 0); | |
416 | intel_logical_ring_emit(ringbuf, 0); | |
417 | intel_logical_ring_emit(ringbuf, 0); | |
418 | intel_logical_ring_advance(ringbuf); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
e94e37ad OM |
423 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
424 | { | |
425 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
426 | } | |
427 | ||
428 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
429 | { | |
430 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
431 | } | |
432 | ||
4da46e1e OM |
433 | static int gen8_emit_request(struct intel_ringbuffer *ringbuf) |
434 | { | |
435 | struct intel_engine_cs *ring = ringbuf->ring; | |
436 | u32 cmd; | |
437 | int ret; | |
438 | ||
439 | ret = intel_logical_ring_begin(ringbuf, 6); | |
440 | if (ret) | |
441 | return ret; | |
442 | ||
443 | cmd = MI_STORE_DWORD_IMM_GEN8; | |
444 | cmd |= MI_GLOBAL_GTT; | |
445 | ||
446 | intel_logical_ring_emit(ringbuf, cmd); | |
447 | intel_logical_ring_emit(ringbuf, | |
448 | (ring->status_page.gfx_addr + | |
449 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
450 | intel_logical_ring_emit(ringbuf, 0); | |
451 | intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno); | |
452 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); | |
453 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
454 | intel_logical_ring_advance_and_submit(ringbuf); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
454afebd OM |
459 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
460 | { | |
48d82387 OM |
461 | if (!intel_ring_initialized(ring)) |
462 | return; | |
463 | ||
464 | /* TODO: make sure the ring is stopped */ | |
465 | ring->preallocated_lazy_request = NULL; | |
466 | ring->outstanding_lazy_seqno = 0; | |
467 | ||
468 | if (ring->cleanup) | |
469 | ring->cleanup(ring); | |
470 | ||
471 | i915_cmd_parser_fini_ring(ring); | |
472 | ||
473 | if (ring->status_page.obj) { | |
474 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
475 | ring->status_page.obj = NULL; | |
476 | } | |
454afebd OM |
477 | } |
478 | ||
479 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
480 | { | |
48d82387 OM |
481 | int ret; |
482 | struct intel_context *dctx = ring->default_context; | |
483 | struct drm_i915_gem_object *dctx_obj; | |
484 | ||
485 | /* Intentionally left blank. */ | |
486 | ring->buffer = NULL; | |
487 | ||
488 | ring->dev = dev; | |
489 | INIT_LIST_HEAD(&ring->active_list); | |
490 | INIT_LIST_HEAD(&ring->request_list); | |
491 | init_waitqueue_head(&ring->irq_queue); | |
492 | ||
493 | ret = intel_lr_context_deferred_create(dctx, ring); | |
494 | if (ret) | |
495 | return ret; | |
496 | ||
497 | /* The status page is offset 0 from the context object in LRCs. */ | |
498 | dctx_obj = dctx->engine[ring->id].state; | |
499 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj); | |
500 | ring->status_page.page_addr = kmap(sg_page(dctx_obj->pages->sgl)); | |
501 | if (ring->status_page.page_addr == NULL) | |
502 | return -ENOMEM; | |
503 | ring->status_page.obj = dctx_obj; | |
504 | ||
505 | ret = i915_cmd_parser_init_ring(ring); | |
506 | if (ret) | |
507 | return ret; | |
508 | ||
509 | if (ring->init) { | |
510 | ret = ring->init(ring); | |
511 | if (ret) | |
512 | return ret; | |
513 | } | |
514 | ||
454afebd OM |
515 | return 0; |
516 | } | |
517 | ||
518 | static int logical_render_ring_init(struct drm_device *dev) | |
519 | { | |
520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
521 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
522 | ||
523 | ring->name = "render ring"; | |
524 | ring->id = RCS; | |
525 | ring->mmio_base = RENDER_RING_BASE; | |
526 | ring->irq_enable_mask = | |
527 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
528 | ||
9b1136d5 OM |
529 | ring->init = gen8_init_render_ring; |
530 | ring->cleanup = intel_fini_pipe_control; | |
e94e37ad OM |
531 | ring->get_seqno = gen8_get_seqno; |
532 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 533 | ring->emit_request = gen8_emit_request; |
4712274c | 534 | ring->emit_flush = gen8_emit_flush_render; |
9b1136d5 | 535 | |
454afebd OM |
536 | return logical_ring_init(dev, ring); |
537 | } | |
538 | ||
539 | static int logical_bsd_ring_init(struct drm_device *dev) | |
540 | { | |
541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
542 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
543 | ||
544 | ring->name = "bsd ring"; | |
545 | ring->id = VCS; | |
546 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
547 | ring->irq_enable_mask = | |
548 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
549 | ||
9b1136d5 | 550 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
551 | ring->get_seqno = gen8_get_seqno; |
552 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 553 | ring->emit_request = gen8_emit_request; |
4712274c | 554 | ring->emit_flush = gen8_emit_flush; |
9b1136d5 | 555 | |
454afebd OM |
556 | return logical_ring_init(dev, ring); |
557 | } | |
558 | ||
559 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
560 | { | |
561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
562 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
563 | ||
564 | ring->name = "bds2 ring"; | |
565 | ring->id = VCS2; | |
566 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
567 | ring->irq_enable_mask = | |
568 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
569 | ||
9b1136d5 | 570 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
571 | ring->get_seqno = gen8_get_seqno; |
572 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 573 | ring->emit_request = gen8_emit_request; |
4712274c | 574 | ring->emit_flush = gen8_emit_flush; |
9b1136d5 | 575 | |
454afebd OM |
576 | return logical_ring_init(dev, ring); |
577 | } | |
578 | ||
579 | static int logical_blt_ring_init(struct drm_device *dev) | |
580 | { | |
581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
582 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
583 | ||
584 | ring->name = "blitter ring"; | |
585 | ring->id = BCS; | |
586 | ring->mmio_base = BLT_RING_BASE; | |
587 | ring->irq_enable_mask = | |
588 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
589 | ||
9b1136d5 | 590 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
591 | ring->get_seqno = gen8_get_seqno; |
592 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 593 | ring->emit_request = gen8_emit_request; |
4712274c | 594 | ring->emit_flush = gen8_emit_flush; |
9b1136d5 | 595 | |
454afebd OM |
596 | return logical_ring_init(dev, ring); |
597 | } | |
598 | ||
599 | static int logical_vebox_ring_init(struct drm_device *dev) | |
600 | { | |
601 | struct drm_i915_private *dev_priv = dev->dev_private; | |
602 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
603 | ||
604 | ring->name = "video enhancement ring"; | |
605 | ring->id = VECS; | |
606 | ring->mmio_base = VEBOX_RING_BASE; | |
607 | ring->irq_enable_mask = | |
608 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
609 | ||
9b1136d5 | 610 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
611 | ring->get_seqno = gen8_get_seqno; |
612 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 613 | ring->emit_request = gen8_emit_request; |
4712274c | 614 | ring->emit_flush = gen8_emit_flush; |
9b1136d5 | 615 | |
454afebd OM |
616 | return logical_ring_init(dev, ring); |
617 | } | |
618 | ||
619 | int intel_logical_rings_init(struct drm_device *dev) | |
620 | { | |
621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
622 | int ret; | |
623 | ||
624 | ret = logical_render_ring_init(dev); | |
625 | if (ret) | |
626 | return ret; | |
627 | ||
628 | if (HAS_BSD(dev)) { | |
629 | ret = logical_bsd_ring_init(dev); | |
630 | if (ret) | |
631 | goto cleanup_render_ring; | |
632 | } | |
633 | ||
634 | if (HAS_BLT(dev)) { | |
635 | ret = logical_blt_ring_init(dev); | |
636 | if (ret) | |
637 | goto cleanup_bsd_ring; | |
638 | } | |
639 | ||
640 | if (HAS_VEBOX(dev)) { | |
641 | ret = logical_vebox_ring_init(dev); | |
642 | if (ret) | |
643 | goto cleanup_blt_ring; | |
644 | } | |
645 | ||
646 | if (HAS_BSD2(dev)) { | |
647 | ret = logical_bsd2_ring_init(dev); | |
648 | if (ret) | |
649 | goto cleanup_vebox_ring; | |
650 | } | |
651 | ||
652 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
653 | if (ret) | |
654 | goto cleanup_bsd2_ring; | |
655 | ||
656 | return 0; | |
657 | ||
658 | cleanup_bsd2_ring: | |
659 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
660 | cleanup_vebox_ring: | |
661 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
662 | cleanup_blt_ring: | |
663 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
664 | cleanup_bsd_ring: | |
665 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
666 | cleanup_render_ring: | |
667 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
668 | ||
669 | return ret; | |
670 | } | |
671 | ||
8670d6f9 OM |
672 | static int |
673 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
674 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
675 | { | |
676 | struct drm_i915_gem_object *ring_obj = ringbuf->obj; | |
677 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); | |
678 | struct page *page; | |
679 | uint32_t *reg_state; | |
680 | int ret; | |
681 | ||
682 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
683 | if (ret) { | |
684 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
685 | return ret; | |
686 | } | |
687 | ||
688 | ret = i915_gem_object_get_pages(ctx_obj); | |
689 | if (ret) { | |
690 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
691 | return ret; | |
692 | } | |
693 | ||
694 | i915_gem_object_pin_pages(ctx_obj); | |
695 | ||
696 | /* The second page of the context object contains some fields which must | |
697 | * be set up prior to the first execution. */ | |
698 | page = i915_gem_object_get_page(ctx_obj, 1); | |
699 | reg_state = kmap_atomic(page); | |
700 | ||
701 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
702 | * commands followed by (reg, value) pairs. The values we are setting here are | |
703 | * only for the first context restore: on a subsequent save, the GPU will | |
704 | * recreate this batchbuffer with new values (including all the missing | |
705 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
706 | if (ring->id == RCS) | |
707 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
708 | else | |
709 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
710 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
711 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
712 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
713 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); | |
714 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); | |
715 | reg_state[CTX_RING_HEAD+1] = 0; | |
716 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
717 | reg_state[CTX_RING_TAIL+1] = 0; | |
718 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
719 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); | |
720 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); | |
721 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
722 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
723 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
724 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
725 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
726 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
727 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
728 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
729 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
730 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
731 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
732 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
733 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
734 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
735 | if (ring->id == RCS) { | |
736 | /* TODO: according to BSpec, the register state context | |
737 | * for CHV does not have these. OTOH, these registers do | |
738 | * exist in CHV. I'm waiting for a clarification */ | |
739 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; | |
740 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
741 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
742 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
743 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
744 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
745 | } | |
746 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
747 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
748 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
749 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
750 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
751 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
752 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
753 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
754 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
755 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
756 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
757 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
758 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); | |
759 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); | |
760 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); | |
761 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); | |
762 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); | |
763 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); | |
764 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); | |
765 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); | |
766 | if (ring->id == RCS) { | |
767 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
768 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; | |
769 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; | |
770 | } | |
771 | ||
772 | kunmap_atomic(reg_state); | |
773 | ||
774 | ctx_obj->dirty = 1; | |
775 | set_page_dirty(page); | |
776 | i915_gem_object_unpin_pages(ctx_obj); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
ede7d42b OM |
781 | void intel_lr_context_free(struct intel_context *ctx) |
782 | { | |
8c857917 OM |
783 | int i; |
784 | ||
785 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
786 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f OM |
787 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
788 | ||
8c857917 | 789 | if (ctx_obj) { |
84c2377f OM |
790 | intel_destroy_ringbuffer_obj(ringbuf); |
791 | kfree(ringbuf); | |
8c857917 OM |
792 | i915_gem_object_ggtt_unpin(ctx_obj); |
793 | drm_gem_object_unreference(&ctx_obj->base); | |
794 | } | |
795 | } | |
796 | } | |
797 | ||
798 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
799 | { | |
800 | int ret = 0; | |
801 | ||
802 | WARN_ON(INTEL_INFO(ring->dev)->gen != 8); | |
803 | ||
804 | switch (ring->id) { | |
805 | case RCS: | |
806 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
807 | break; | |
808 | case VCS: | |
809 | case BCS: | |
810 | case VECS: | |
811 | case VCS2: | |
812 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
813 | break; | |
814 | } | |
815 | ||
816 | return ret; | |
ede7d42b OM |
817 | } |
818 | ||
819 | int intel_lr_context_deferred_create(struct intel_context *ctx, | |
820 | struct intel_engine_cs *ring) | |
821 | { | |
8c857917 OM |
822 | struct drm_device *dev = ring->dev; |
823 | struct drm_i915_gem_object *ctx_obj; | |
824 | uint32_t context_size; | |
84c2377f | 825 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
826 | int ret; |
827 | ||
ede7d42b | 828 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
48d82387 OM |
829 | if (ctx->engine[ring->id].state) |
830 | return 0; | |
ede7d42b | 831 | |
8c857917 OM |
832 | context_size = round_up(get_lr_context_size(ring), 4096); |
833 | ||
834 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); | |
835 | if (IS_ERR(ctx_obj)) { | |
836 | ret = PTR_ERR(ctx_obj); | |
837 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); | |
838 | return ret; | |
839 | } | |
840 | ||
841 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
842 | if (ret) { | |
843 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); | |
844 | drm_gem_object_unreference(&ctx_obj->base); | |
845 | return ret; | |
846 | } | |
847 | ||
84c2377f OM |
848 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
849 | if (!ringbuf) { | |
850 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
851 | ring->name); | |
852 | i915_gem_object_ggtt_unpin(ctx_obj); | |
853 | drm_gem_object_unreference(&ctx_obj->base); | |
854 | ret = -ENOMEM; | |
855 | return ret; | |
856 | } | |
857 | ||
0c7dd53b | 858 | ringbuf->ring = ring; |
84c2377f OM |
859 | ringbuf->size = 32 * PAGE_SIZE; |
860 | ringbuf->effective_size = ringbuf->size; | |
861 | ringbuf->head = 0; | |
862 | ringbuf->tail = 0; | |
863 | ringbuf->space = ringbuf->size; | |
864 | ringbuf->last_retired_head = -1; | |
865 | ||
866 | /* TODO: For now we put this in the mappable region so that we can reuse | |
867 | * the existing ringbuffer code which ioremaps it. When we start | |
868 | * creating many contexts, this will no longer work and we must switch | |
869 | * to a kmapish interface. | |
870 | */ | |
871 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
872 | if (ret) { | |
873 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", | |
874 | ring->name, ret); | |
8670d6f9 OM |
875 | goto error; |
876 | } | |
877 | ||
878 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
879 | if (ret) { | |
880 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
881 | intel_destroy_ringbuffer_obj(ringbuf); | |
882 | goto error; | |
84c2377f OM |
883 | } |
884 | ||
885 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 886 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b OM |
887 | |
888 | return 0; | |
8670d6f9 OM |
889 | |
890 | error: | |
891 | kfree(ringbuf); | |
892 | i915_gem_object_ggtt_unpin(ctx_obj); | |
893 | drm_gem_object_unreference(&ctx_obj->base); | |
894 | return ret; | |
ede7d42b | 895 | } |