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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
127f1003 | 138 | |
468c6816 | 139 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
140 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
141 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
142 | ||
e981e7b1 TD |
143 | #define RING_EXECLIST_QFULL (1 << 0x2) |
144 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
145 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
146 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
147 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
148 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
149 | ||
150 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
151 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
152 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
153 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
154 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
155 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
156 | |
157 | #define CTX_LRI_HEADER_0 0x01 | |
158 | #define CTX_CONTEXT_CONTROL 0x02 | |
159 | #define CTX_RING_HEAD 0x04 | |
160 | #define CTX_RING_TAIL 0x06 | |
161 | #define CTX_RING_BUFFER_START 0x08 | |
162 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
163 | #define CTX_BB_HEAD_U 0x0c | |
164 | #define CTX_BB_HEAD_L 0x0e | |
165 | #define CTX_BB_STATE 0x10 | |
166 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
167 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
168 | #define CTX_SECOND_BB_STATE 0x16 | |
169 | #define CTX_BB_PER_CTX_PTR 0x18 | |
170 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
171 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
172 | #define CTX_LRI_HEADER_1 0x21 | |
173 | #define CTX_CTX_TIMESTAMP 0x22 | |
174 | #define CTX_PDP3_UDW 0x24 | |
175 | #define CTX_PDP3_LDW 0x26 | |
176 | #define CTX_PDP2_UDW 0x28 | |
177 | #define CTX_PDP2_LDW 0x2a | |
178 | #define CTX_PDP1_UDW 0x2c | |
179 | #define CTX_PDP1_LDW 0x2e | |
180 | #define CTX_PDP0_UDW 0x30 | |
181 | #define CTX_PDP0_LDW 0x32 | |
182 | #define CTX_LRI_HEADER_2 0x41 | |
183 | #define CTX_R_PWR_CLK_STATE 0x42 | |
184 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
185 | ||
84b790f8 BW |
186 | #define GEN8_CTX_VALID (1<<0) |
187 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
188 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
189 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
190 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e MT |
191 | |
192 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ | |
d7b2633d | 193 | const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \ |
e5815a2e MT |
194 | ppgtt->pdp.page_directory[n]->daddr : \ |
195 | ppgtt->scratch_pd->daddr; \ | |
196 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ | |
197 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
198 | } | |
199 | ||
84b790f8 BW |
200 | enum { |
201 | ADVANCED_CONTEXT = 0, | |
202 | LEGACY_CONTEXT, | |
203 | ADVANCED_AD_CONTEXT, | |
204 | LEGACY_64B_CONTEXT | |
205 | }; | |
206 | #define GEN8_CTX_MODE_SHIFT 3 | |
207 | enum { | |
208 | FAULT_AND_HANG = 0, | |
209 | FAULT_AND_HALT, /* Debug only */ | |
210 | FAULT_AND_STREAM, | |
211 | FAULT_AND_CONTINUE /* Unsupported */ | |
212 | }; | |
213 | #define GEN8_CTX_ID_SHIFT 32 | |
17ee950d | 214 | #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
84b790f8 | 215 | |
7ba717cf TD |
216 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
217 | struct intel_context *ctx); | |
218 | ||
73e4d07f OM |
219 | /** |
220 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
221 | * @dev: DRM device. | |
222 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
223 | * | |
224 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 225 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
226 | * |
227 | * Return: 1 if Execlists is supported and has to be enabled. | |
228 | */ | |
127f1003 OM |
229 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
230 | { | |
bd84b1e9 DV |
231 | WARN_ON(i915.enable_ppgtt == -1); |
232 | ||
70ee45e1 DL |
233 | if (INTEL_INFO(dev)->gen >= 9) |
234 | return 1; | |
235 | ||
127f1003 OM |
236 | if (enable_execlists == 0) |
237 | return 0; | |
238 | ||
14bf993e OM |
239 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
240 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
241 | return 1; |
242 | ||
243 | return 0; | |
244 | } | |
ede7d42b | 245 | |
73e4d07f OM |
246 | /** |
247 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
248 | * @ctx_obj: Logical Ring Context backing object. | |
249 | * | |
250 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
251 | * here: the old context ID we pass to userspace as a handler so that | |
252 | * they can refer to a context, and the new context ID we pass to the | |
253 | * ELSP so that the GPU can inform us of the context status via | |
254 | * interrupts. | |
255 | * | |
256 | * Return: 20-bits globally unique context ID. | |
257 | */ | |
84b790f8 BW |
258 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
259 | { | |
260 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
261 | ||
262 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
263 | * are globally unique */ | |
264 | return lrca >> 12; | |
265 | } | |
266 | ||
203a571b NH |
267 | static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring, |
268 | struct drm_i915_gem_object *ctx_obj) | |
84b790f8 | 269 | { |
203a571b | 270 | struct drm_device *dev = ring->dev; |
84b790f8 BW |
271 | uint64_t desc; |
272 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
acdd884a MT |
273 | |
274 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
275 | |
276 | desc = GEN8_CTX_VALID; | |
277 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; | |
51847fb9 AS |
278 | if (IS_GEN8(ctx_obj->base.dev)) |
279 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
84b790f8 BW |
280 | desc |= GEN8_CTX_PRIVILEGE; |
281 | desc |= lrca; | |
282 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
283 | ||
284 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
285 | * signalling between Command Streamers */ | |
286 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
287 | ||
203a571b NH |
288 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
289 | if (IS_GEN9(dev) && | |
290 | INTEL_REVID(dev) <= SKL_REVID_B0 && | |
291 | (ring->id == BCS || ring->id == VCS || | |
292 | ring->id == VECS || ring->id == VCS2)) | |
293 | desc |= GEN8_CTX_FORCE_RESTORE; | |
294 | ||
84b790f8 BW |
295 | return desc; |
296 | } | |
297 | ||
298 | static void execlists_elsp_write(struct intel_engine_cs *ring, | |
299 | struct drm_i915_gem_object *ctx_obj0, | |
300 | struct drm_i915_gem_object *ctx_obj1) | |
301 | { | |
6e7cc470 TU |
302 | struct drm_device *dev = ring->dev; |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84b790f8 BW |
304 | uint64_t temp = 0; |
305 | uint32_t desc[4]; | |
306 | ||
307 | /* XXX: You must always write both descriptors in the order below. */ | |
308 | if (ctx_obj1) | |
203a571b | 309 | temp = execlists_ctx_descriptor(ring, ctx_obj1); |
84b790f8 BW |
310 | else |
311 | temp = 0; | |
312 | desc[1] = (u32)(temp >> 32); | |
313 | desc[0] = (u32)temp; | |
314 | ||
203a571b | 315 | temp = execlists_ctx_descriptor(ring, ctx_obj0); |
84b790f8 BW |
316 | desc[3] = (u32)(temp >> 32); |
317 | desc[2] = (u32)temp; | |
318 | ||
a6111f7b CW |
319 | spin_lock(&dev_priv->uncore.lock); |
320 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
321 | I915_WRITE_FW(RING_ELSP(ring), desc[1]); | |
322 | I915_WRITE_FW(RING_ELSP(ring), desc[0]); | |
323 | I915_WRITE_FW(RING_ELSP(ring), desc[3]); | |
6daccb0b | 324 | |
84b790f8 | 325 | /* The context is automatically loaded after the following */ |
a6111f7b | 326 | I915_WRITE_FW(RING_ELSP(ring), desc[2]); |
84b790f8 BW |
327 | |
328 | /* ELSP is a wo register, so use another nearby reg for posting instead */ | |
a6111f7b CW |
329 | POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); |
330 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
331 | spin_unlock(&dev_priv->uncore.lock); | |
84b790f8 BW |
332 | } |
333 | ||
7ba717cf TD |
334 | static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, |
335 | struct drm_i915_gem_object *ring_obj, | |
d7b2633d | 336 | struct i915_hw_ppgtt *ppgtt, |
7ba717cf | 337 | u32 tail) |
ae1250b9 OM |
338 | { |
339 | struct page *page; | |
340 | uint32_t *reg_state; | |
341 | ||
342 | page = i915_gem_object_get_page(ctx_obj, 1); | |
343 | reg_state = kmap_atomic(page); | |
344 | ||
345 | reg_state[CTX_RING_TAIL+1] = tail; | |
7ba717cf | 346 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); |
ae1250b9 | 347 | |
d7b2633d MT |
348 | /* True PPGTT with dynamic page allocation: update PDP registers and |
349 | * point the unallocated PDPs to the scratch page | |
350 | */ | |
351 | if (ppgtt) { | |
352 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
353 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
354 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
355 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
356 | } | |
357 | ||
ae1250b9 OM |
358 | kunmap_atomic(reg_state); |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
cd0707cb DG |
363 | static void execlists_submit_contexts(struct intel_engine_cs *ring, |
364 | struct intel_context *to0, u32 tail0, | |
365 | struct intel_context *to1, u32 tail1) | |
84b790f8 | 366 | { |
7ba717cf TD |
367 | struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; |
368 | struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; | |
84b790f8 | 369 | struct drm_i915_gem_object *ctx_obj1 = NULL; |
7ba717cf | 370 | struct intel_ringbuffer *ringbuf1 = NULL; |
84b790f8 | 371 | |
84b790f8 | 372 | BUG_ON(!ctx_obj0); |
acdd884a | 373 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); |
7ba717cf | 374 | WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj)); |
84b790f8 | 375 | |
d7b2633d | 376 | execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0); |
ae1250b9 | 377 | |
84b790f8 | 378 | if (to1) { |
7ba717cf | 379 | ringbuf1 = to1->engine[ring->id].ringbuf; |
84b790f8 BW |
380 | ctx_obj1 = to1->engine[ring->id].state; |
381 | BUG_ON(!ctx_obj1); | |
acdd884a | 382 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); |
7ba717cf | 383 | WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj)); |
ae1250b9 | 384 | |
d7b2633d | 385 | execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1); |
84b790f8 BW |
386 | } |
387 | ||
388 | execlists_elsp_write(ring, ctx_obj0, ctx_obj1); | |
84b790f8 BW |
389 | } |
390 | ||
acdd884a MT |
391 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
392 | { | |
6d3d8274 NH |
393 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
394 | struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
395 | |
396 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a | 397 | |
779949f4 PA |
398 | /* |
399 | * If irqs are not active generate a warning as batches that finish | |
400 | * without the irqs may get lost and a GPU Hang may occur. | |
401 | */ | |
402 | WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); | |
403 | ||
acdd884a MT |
404 | if (list_empty(&ring->execlist_queue)) |
405 | return; | |
406 | ||
407 | /* Try to read in pairs */ | |
408 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
409 | execlist_link) { | |
410 | if (!req0) { | |
411 | req0 = cursor; | |
6d3d8274 | 412 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
413 | /* Same ctx: ignore first request, as second request |
414 | * will update tail past first request's workload */ | |
e1fee72c | 415 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 416 | list_del(&req0->execlist_link); |
c86ee3a9 TD |
417 | list_add_tail(&req0->execlist_link, |
418 | &ring->execlist_retired_req_list); | |
acdd884a MT |
419 | req0 = cursor; |
420 | } else { | |
421 | req1 = cursor; | |
422 | break; | |
423 | } | |
424 | } | |
425 | ||
53292cdb MT |
426 | if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { |
427 | /* | |
428 | * WaIdleLiteRestore: make sure we never cause a lite | |
429 | * restore with HEAD==TAIL | |
430 | */ | |
d63f820f | 431 | if (req0->elsp_submitted) { |
53292cdb MT |
432 | /* |
433 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL | |
434 | * as we resubmit the request. See gen8_emit_request() | |
435 | * for where we prepare the padding after the end of the | |
436 | * request. | |
437 | */ | |
438 | struct intel_ringbuffer *ringbuf; | |
439 | ||
440 | ringbuf = req0->ctx->engine[ring->id].ringbuf; | |
441 | req0->tail += 8; | |
442 | req0->tail &= ringbuf->size - 1; | |
443 | } | |
444 | } | |
445 | ||
e1fee72c OM |
446 | WARN_ON(req1 && req1->elsp_submitted); |
447 | ||
6d3d8274 NH |
448 | execlists_submit_contexts(ring, req0->ctx, req0->tail, |
449 | req1 ? req1->ctx : NULL, | |
450 | req1 ? req1->tail : 0); | |
e1fee72c OM |
451 | |
452 | req0->elsp_submitted++; | |
453 | if (req1) | |
454 | req1->elsp_submitted++; | |
acdd884a MT |
455 | } |
456 | ||
e981e7b1 TD |
457 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
458 | u32 request_id) | |
459 | { | |
6d3d8274 | 460 | struct drm_i915_gem_request *head_req; |
e981e7b1 TD |
461 | |
462 | assert_spin_locked(&ring->execlist_lock); | |
463 | ||
464 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 465 | struct drm_i915_gem_request, |
e981e7b1 TD |
466 | execlist_link); |
467 | ||
468 | if (head_req != NULL) { | |
469 | struct drm_i915_gem_object *ctx_obj = | |
6d3d8274 | 470 | head_req->ctx->engine[ring->id].state; |
e981e7b1 | 471 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { |
e1fee72c OM |
472 | WARN(head_req->elsp_submitted == 0, |
473 | "Never submitted head request\n"); | |
474 | ||
475 | if (--head_req->elsp_submitted <= 0) { | |
476 | list_del(&head_req->execlist_link); | |
c86ee3a9 TD |
477 | list_add_tail(&head_req->execlist_link, |
478 | &ring->execlist_retired_req_list); | |
e1fee72c OM |
479 | return true; |
480 | } | |
e981e7b1 TD |
481 | } |
482 | } | |
483 | ||
484 | return false; | |
485 | } | |
486 | ||
73e4d07f | 487 | /** |
3f7531c3 | 488 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
73e4d07f OM |
489 | * @ring: Engine Command Streamer to handle. |
490 | * | |
491 | * Check the unread Context Status Buffers and manage the submission of new | |
492 | * contexts to the ELSP accordingly. | |
493 | */ | |
3f7531c3 | 494 | void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
e981e7b1 TD |
495 | { |
496 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
497 | u32 status_pointer; | |
498 | u8 read_pointer; | |
499 | u8 write_pointer; | |
500 | u32 status; | |
501 | u32 status_id; | |
502 | u32 submit_contexts = 0; | |
503 | ||
504 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
505 | ||
506 | read_pointer = ring->next_context_status_buffer; | |
507 | write_pointer = status_pointer & 0x07; | |
508 | if (read_pointer > write_pointer) | |
509 | write_pointer += 6; | |
510 | ||
511 | spin_lock(&ring->execlist_lock); | |
512 | ||
513 | while (read_pointer < write_pointer) { | |
514 | read_pointer++; | |
515 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
516 | (read_pointer % 6) * 8); | |
517 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
518 | (read_pointer % 6) * 8 + 4); | |
519 | ||
e1fee72c OM |
520 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
521 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
522 | if (execlists_check_remove_request(ring, status_id)) | |
523 | WARN(1, "Lite Restored request removed from queue\n"); | |
524 | } else | |
525 | WARN(1, "Preemption without Lite Restore\n"); | |
526 | } | |
527 | ||
528 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
529 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
530 | if (execlists_check_remove_request(ring, status_id)) |
531 | submit_contexts++; | |
532 | } | |
533 | } | |
534 | ||
535 | if (submit_contexts != 0) | |
536 | execlists_context_unqueue(ring); | |
537 | ||
538 | spin_unlock(&ring->execlist_lock); | |
539 | ||
540 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
541 | ring->next_context_status_buffer = write_pointer % 6; | |
542 | ||
543 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
544 | ((u32)ring->next_context_status_buffer & 0x07) << 8); | |
545 | } | |
546 | ||
ae70797d | 547 | static int execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 548 | { |
ae70797d | 549 | struct intel_engine_cs *ring = request->ring; |
6d3d8274 | 550 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 551 | int num_elements = 0; |
acdd884a | 552 | |
ae70797d JH |
553 | if (request->ctx != ring->default_context) |
554 | intel_lr_context_pin(ring, request->ctx); | |
9bb1af44 JH |
555 | |
556 | i915_gem_request_reference(request); | |
557 | ||
ae70797d | 558 | request->tail = request->ringbuf->tail; |
2d12955a | 559 | |
b5eba372 | 560 | spin_lock_irq(&ring->execlist_lock); |
acdd884a | 561 | |
f1ad5a1f OM |
562 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
563 | if (++num_elements > 2) | |
564 | break; | |
565 | ||
566 | if (num_elements > 2) { | |
6d3d8274 | 567 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f OM |
568 | |
569 | tail_req = list_last_entry(&ring->execlist_queue, | |
6d3d8274 | 570 | struct drm_i915_gem_request, |
f1ad5a1f OM |
571 | execlist_link); |
572 | ||
ae70797d | 573 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 574 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 575 | "More than 2 already-submitted reqs queued\n"); |
f1ad5a1f | 576 | list_del(&tail_req->execlist_link); |
c86ee3a9 TD |
577 | list_add_tail(&tail_req->execlist_link, |
578 | &ring->execlist_retired_req_list); | |
f1ad5a1f OM |
579 | } |
580 | } | |
581 | ||
6d3d8274 | 582 | list_add_tail(&request->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 583 | if (num_elements == 0) |
acdd884a MT |
584 | execlists_context_unqueue(ring); |
585 | ||
b5eba372 | 586 | spin_unlock_irq(&ring->execlist_lock); |
acdd884a MT |
587 | |
588 | return 0; | |
589 | } | |
590 | ||
2f20055d | 591 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 592 | { |
2f20055d | 593 | struct intel_engine_cs *ring = req->ring; |
ba8b7ccb OM |
594 | uint32_t flush_domains; |
595 | int ret; | |
596 | ||
597 | flush_domains = 0; | |
598 | if (ring->gpu_caches_dirty) | |
599 | flush_domains = I915_GEM_GPU_DOMAINS; | |
600 | ||
7deb4d39 | 601 | ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
602 | if (ret) |
603 | return ret; | |
604 | ||
605 | ring->gpu_caches_dirty = false; | |
606 | return 0; | |
607 | } | |
608 | ||
535fbe82 | 609 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
610 | struct list_head *vmas) |
611 | { | |
535fbe82 | 612 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
ba8b7ccb OM |
613 | struct i915_vma *vma; |
614 | uint32_t flush_domains = 0; | |
615 | bool flush_chipset = false; | |
616 | int ret; | |
617 | ||
618 | list_for_each_entry(vma, vmas, exec_list) { | |
619 | struct drm_i915_gem_object *obj = vma->obj; | |
620 | ||
03ade511 | 621 | if (obj->active & other_rings) { |
91af127f | 622 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
623 | if (ret) |
624 | return ret; | |
625 | } | |
ba8b7ccb OM |
626 | |
627 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
628 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
629 | ||
630 | flush_domains |= obj->base.write_domain; | |
631 | } | |
632 | ||
633 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
634 | wmb(); | |
635 | ||
636 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
637 | * any residual writes from the previous batch. | |
638 | */ | |
2f20055d | 639 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
640 | } |
641 | ||
40e895ce | 642 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 643 | { |
bc0dce3f JH |
644 | int ret; |
645 | ||
40e895ce JH |
646 | if (request->ctx != request->ring->default_context) { |
647 | ret = intel_lr_context_pin(request->ring, request->ctx); | |
6689cb2b | 648 | if (ret) |
bc0dce3f | 649 | return ret; |
bc0dce3f JH |
650 | } |
651 | ||
40e895ce | 652 | request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; |
bc0dce3f | 653 | |
bc0dce3f JH |
654 | return 0; |
655 | } | |
656 | ||
ae70797d | 657 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
595e1eeb | 658 | int bytes) |
bc0dce3f | 659 | { |
ae70797d JH |
660 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
661 | struct intel_engine_cs *ring = req->ring; | |
662 | struct drm_i915_gem_request *target; | |
b4716185 CW |
663 | unsigned space; |
664 | int ret; | |
bc0dce3f | 665 | |
29b1b415 JH |
666 | /* The whole point of reserving space is to not wait! */ |
667 | WARN_ON(ringbuf->reserved_in_use); | |
668 | ||
bc0dce3f JH |
669 | if (intel_ring_space(ringbuf) >= bytes) |
670 | return 0; | |
671 | ||
ae70797d | 672 | list_for_each_entry(target, &ring->request_list, list) { |
bc0dce3f JH |
673 | /* |
674 | * The request queue is per-engine, so can contain requests | |
675 | * from multiple ringbuffers. Here, we must ignore any that | |
676 | * aren't from the ringbuffer we're considering. | |
677 | */ | |
ae70797d | 678 | if (target->ringbuf != ringbuf) |
bc0dce3f JH |
679 | continue; |
680 | ||
681 | /* Would completion of this request free enough space? */ | |
ae70797d | 682 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
b4716185 CW |
683 | ringbuf->size); |
684 | if (space >= bytes) | |
bc0dce3f | 685 | break; |
bc0dce3f JH |
686 | } |
687 | ||
ae70797d | 688 | if (WARN_ON(&target->list == &ring->request_list)) |
bc0dce3f JH |
689 | return -ENOSPC; |
690 | ||
ae70797d | 691 | ret = i915_wait_request(target); |
bc0dce3f JH |
692 | if (ret) |
693 | return ret; | |
694 | ||
b4716185 CW |
695 | ringbuf->space = space; |
696 | return 0; | |
bc0dce3f JH |
697 | } |
698 | ||
699 | /* | |
700 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 701 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
702 | * |
703 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
704 | * really happens during submission is that the context and current tail will be placed | |
705 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
706 | * point, the tail *inside* the context is updated and the ELSP written to. | |
707 | */ | |
708 | static void | |
ae70797d | 709 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 710 | { |
ae70797d | 711 | struct intel_engine_cs *ring = request->ring; |
bc0dce3f | 712 | |
ae70797d | 713 | intel_logical_ring_advance(request->ringbuf); |
bc0dce3f JH |
714 | |
715 | if (intel_ring_stopped(ring)) | |
716 | return; | |
717 | ||
ae70797d | 718 | execlists_context_queue(request); |
bc0dce3f JH |
719 | } |
720 | ||
ae70797d | 721 | static int logical_ring_wrap_buffer(struct drm_i915_gem_request *req) |
bc0dce3f | 722 | { |
ae70797d | 723 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
bc0dce3f JH |
724 | uint32_t __iomem *virt; |
725 | int rem = ringbuf->size - ringbuf->tail; | |
726 | ||
29b1b415 JH |
727 | /* Can't wrap if space has already been reserved! */ |
728 | WARN_ON(ringbuf->reserved_in_use); | |
729 | ||
bc0dce3f | 730 | if (ringbuf->space < rem) { |
ae70797d | 731 | int ret = logical_ring_wait_for_space(req, rem); |
bc0dce3f JH |
732 | |
733 | if (ret) | |
734 | return ret; | |
735 | } | |
736 | ||
737 | virt = ringbuf->virtual_start + ringbuf->tail; | |
738 | rem /= 4; | |
739 | while (rem--) | |
740 | iowrite32(MI_NOOP, virt++); | |
741 | ||
742 | ringbuf->tail = 0; | |
743 | intel_ring_update_space(ringbuf); | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
ae70797d | 748 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
bc0dce3f | 749 | { |
ae70797d | 750 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
bc0dce3f JH |
751 | int ret; |
752 | ||
29b1b415 JH |
753 | /* |
754 | * Add on the reserved size to the request to make sure that after | |
755 | * the intended commands have been emitted, there is guaranteed to | |
756 | * still be enough free space to send them to the hardware. | |
757 | */ | |
758 | if (!ringbuf->reserved_in_use) | |
759 | bytes += ringbuf->reserved_size; | |
760 | ||
bc0dce3f | 761 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
ae70797d | 762 | ret = logical_ring_wrap_buffer(req); |
bc0dce3f JH |
763 | if (unlikely(ret)) |
764 | return ret; | |
29b1b415 JH |
765 | |
766 | if(ringbuf->reserved_size) { | |
767 | uint32_t size = ringbuf->reserved_size; | |
768 | ||
769 | intel_ring_reserved_space_cancel(ringbuf); | |
770 | intel_ring_reserved_space_reserve(ringbuf, size); | |
771 | } | |
bc0dce3f JH |
772 | } |
773 | ||
774 | if (unlikely(ringbuf->space < bytes)) { | |
ae70797d | 775 | ret = logical_ring_wait_for_space(req, bytes); |
bc0dce3f JH |
776 | if (unlikely(ret)) |
777 | return ret; | |
778 | } | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | /** | |
784 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
785 | * | |
4d616a29 | 786 | * @request: The request to start some new work for |
4d78c8dc | 787 | * @ctx: Logical ring context whose ringbuffer is being prepared. |
bc0dce3f JH |
788 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
789 | * | |
790 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
791 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
792 | * and also preallocates a request (every workload submission is still mediated through | |
793 | * requests, same as it did with legacy ringbuffer submission). | |
794 | * | |
795 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
796 | */ | |
4d616a29 JH |
797 | static int intel_logical_ring_begin(struct drm_i915_gem_request *req, |
798 | int num_dwords) | |
bc0dce3f | 799 | { |
4d616a29 | 800 | struct drm_i915_private *dev_priv; |
bc0dce3f JH |
801 | int ret; |
802 | ||
4d616a29 JH |
803 | WARN_ON(req == NULL); |
804 | dev_priv = req->ring->dev->dev_private; | |
805 | ||
bc0dce3f JH |
806 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
807 | dev_priv->mm.interruptible); | |
808 | if (ret) | |
809 | return ret; | |
810 | ||
ae70797d | 811 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
bc0dce3f JH |
812 | if (ret) |
813 | return ret; | |
814 | ||
4d616a29 | 815 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
bc0dce3f JH |
816 | return 0; |
817 | } | |
818 | ||
ccd98fe4 JH |
819 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
820 | { | |
821 | /* | |
822 | * The first call merely notes the reserve request and is common for | |
823 | * all back ends. The subsequent localised _begin() call actually | |
824 | * ensures that the reservation is available. Without the begin, if | |
825 | * the request creator immediately submitted the request without | |
826 | * adding any commands to it then there might not actually be | |
827 | * sufficient room for the submission commands. | |
828 | */ | |
829 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
830 | ||
831 | return intel_logical_ring_begin(request, 0); | |
832 | } | |
833 | ||
73e4d07f OM |
834 | /** |
835 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
836 | * @dev: DRM device. | |
837 | * @file: DRM file. | |
838 | * @ring: Engine Command Streamer to submit to. | |
839 | * @ctx: Context to employ for this submission. | |
840 | * @args: execbuffer call arguments. | |
841 | * @vmas: list of vmas. | |
842 | * @batch_obj: the batchbuffer to submit. | |
843 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 844 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
845 | * |
846 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
847 | * away the submission details of the execbuffer ioctl call. | |
848 | * | |
849 | * Return: non-zero if the submission fails. | |
850 | */ | |
5f19e2bf | 851 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 852 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 853 | struct list_head *vmas) |
454afebd | 854 | { |
5f19e2bf JH |
855 | struct drm_device *dev = params->dev; |
856 | struct intel_engine_cs *ring = params->ring; | |
ba8b7ccb | 857 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf JH |
858 | struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; |
859 | u64 exec_start; | |
ba8b7ccb OM |
860 | int instp_mode; |
861 | u32 instp_mask; | |
862 | int ret; | |
863 | ||
864 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
865 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
866 | switch (instp_mode) { | |
867 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
868 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
869 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
870 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
871 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
872 | return -EINVAL; | |
873 | } | |
874 | ||
875 | if (instp_mode != dev_priv->relative_constants_mode) { | |
876 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
877 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
878 | return -EINVAL; | |
879 | } | |
880 | ||
881 | /* The HW changed the meaning on this bit on gen6 */ | |
882 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
883 | } | |
884 | break; | |
885 | default: | |
886 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
887 | return -EINVAL; | |
888 | } | |
889 | ||
890 | if (args->num_cliprects != 0) { | |
891 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
892 | return -EINVAL; | |
893 | } else { | |
894 | if (args->DR4 == 0xffffffff) { | |
895 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
896 | args->DR4 = 0; | |
897 | } | |
898 | ||
899 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
900 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
901 | return -EINVAL; | |
902 | } | |
903 | } | |
904 | ||
905 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
906 | DRM_DEBUG("sol reset is gen7 only\n"); | |
907 | return -EINVAL; | |
908 | } | |
909 | ||
535fbe82 | 910 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
911 | if (ret) |
912 | return ret; | |
913 | ||
914 | if (ring == &dev_priv->ring[RCS] && | |
915 | instp_mode != dev_priv->relative_constants_mode) { | |
4d616a29 | 916 | ret = intel_logical_ring_begin(params->request, 4); |
ba8b7ccb OM |
917 | if (ret) |
918 | return ret; | |
919 | ||
920 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
921 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
922 | intel_logical_ring_emit(ringbuf, INSTPM); | |
923 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
924 | intel_logical_ring_advance(ringbuf); | |
925 | ||
926 | dev_priv->relative_constants_mode = instp_mode; | |
927 | } | |
928 | ||
5f19e2bf JH |
929 | exec_start = params->batch_obj_vm_offset + |
930 | args->batch_start_offset; | |
931 | ||
be795fc1 | 932 | ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
933 | if (ret) |
934 | return ret; | |
935 | ||
95c24161 | 936 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 937 | |
8a8edb59 | 938 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 939 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 940 | |
454afebd OM |
941 | return 0; |
942 | } | |
943 | ||
c86ee3a9 TD |
944 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
945 | { | |
6d3d8274 | 946 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
947 | struct list_head retired_list; |
948 | ||
949 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
950 | if (list_empty(&ring->execlist_retired_req_list)) | |
951 | return; | |
952 | ||
953 | INIT_LIST_HEAD(&retired_list); | |
b5eba372 | 954 | spin_lock_irq(&ring->execlist_lock); |
c86ee3a9 | 955 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
b5eba372 | 956 | spin_unlock_irq(&ring->execlist_lock); |
c86ee3a9 TD |
957 | |
958 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
6d3d8274 | 959 | struct intel_context *ctx = req->ctx; |
7ba717cf TD |
960 | struct drm_i915_gem_object *ctx_obj = |
961 | ctx->engine[ring->id].state; | |
962 | ||
963 | if (ctx_obj && (ctx != ring->default_context)) | |
964 | intel_lr_context_unpin(ring, ctx); | |
c86ee3a9 | 965 | list_del(&req->execlist_link); |
f8210795 | 966 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
967 | } |
968 | } | |
969 | ||
454afebd OM |
970 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
971 | { | |
9832b9da OM |
972 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
973 | int ret; | |
974 | ||
975 | if (!intel_ring_initialized(ring)) | |
976 | return; | |
977 | ||
978 | ret = intel_ring_idle(ring); | |
979 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
980 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
981 | ring->name, ret); | |
982 | ||
983 | /* TODO: Is this correct with Execlists enabled? */ | |
984 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
985 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
986 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
987 | return; | |
988 | } | |
989 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
990 | } |
991 | ||
4866d729 | 992 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 993 | { |
4866d729 | 994 | struct intel_engine_cs *ring = req->ring; |
48e29f55 OM |
995 | int ret; |
996 | ||
997 | if (!ring->gpu_caches_dirty) | |
998 | return 0; | |
999 | ||
7deb4d39 | 1000 | ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
1001 | if (ret) |
1002 | return ret; | |
1003 | ||
1004 | ring->gpu_caches_dirty = false; | |
1005 | return 0; | |
1006 | } | |
1007 | ||
dcb4c12a OM |
1008 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
1009 | struct intel_context *ctx) | |
1010 | { | |
1011 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; | |
7ba717cf | 1012 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
dcb4c12a OM |
1013 | int ret = 0; |
1014 | ||
1015 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
a7cbedec | 1016 | if (ctx->engine[ring->id].pin_count++ == 0) { |
dcb4c12a OM |
1017 | ret = i915_gem_obj_ggtt_pin(ctx_obj, |
1018 | GEN8_LR_CONTEXT_ALIGN, 0); | |
1019 | if (ret) | |
a7cbedec | 1020 | goto reset_pin_count; |
7ba717cf TD |
1021 | |
1022 | ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); | |
1023 | if (ret) | |
1024 | goto unpin_ctx_obj; | |
dcb4c12a OM |
1025 | } |
1026 | ||
7ba717cf TD |
1027 | return ret; |
1028 | ||
1029 | unpin_ctx_obj: | |
1030 | i915_gem_object_ggtt_unpin(ctx_obj); | |
a7cbedec MK |
1031 | reset_pin_count: |
1032 | ctx->engine[ring->id].pin_count = 0; | |
7ba717cf | 1033 | |
dcb4c12a OM |
1034 | return ret; |
1035 | } | |
1036 | ||
1037 | void intel_lr_context_unpin(struct intel_engine_cs *ring, | |
1038 | struct intel_context *ctx) | |
1039 | { | |
1040 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; | |
7ba717cf | 1041 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
dcb4c12a OM |
1042 | |
1043 | if (ctx_obj) { | |
1044 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
a7cbedec | 1045 | if (--ctx->engine[ring->id].pin_count == 0) { |
7ba717cf | 1046 | intel_unpin_ringbuffer_obj(ringbuf); |
dcb4c12a | 1047 | i915_gem_object_ggtt_unpin(ctx_obj); |
7ba717cf | 1048 | } |
dcb4c12a OM |
1049 | } |
1050 | } | |
1051 | ||
e2be4faf | 1052 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1053 | { |
1054 | int ret, i; | |
e2be4faf JH |
1055 | struct intel_engine_cs *ring = req->ring; |
1056 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
771b9a53 MT |
1057 | struct drm_device *dev = ring->dev; |
1058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1059 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1060 | ||
e6c1abb7 | 1061 | if (WARN_ON_ONCE(w->count == 0)) |
771b9a53 MT |
1062 | return 0; |
1063 | ||
1064 | ring->gpu_caches_dirty = true; | |
4866d729 | 1065 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1066 | if (ret) |
1067 | return ret; | |
1068 | ||
4d616a29 | 1069 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1070 | if (ret) |
1071 | return ret; | |
1072 | ||
1073 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1074 | for (i = 0; i < w->count; i++) { | |
1075 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1076 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1077 | } | |
1078 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1079 | ||
1080 | intel_logical_ring_advance(ringbuf); | |
1081 | ||
1082 | ring->gpu_caches_dirty = true; | |
4866d729 | 1083 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1084 | if (ret) |
1085 | return ret; | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
17ee950d AS |
1090 | #define wa_ctx_emit(batch, cmd) \ |
1091 | do { \ | |
1092 | if (WARN_ON(index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
1093 | return -ENOSPC; \ | |
1094 | } \ | |
1095 | batch[index++] = (cmd); \ | |
1096 | } while (0) | |
1097 | ||
1098 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, | |
1099 | uint32_t offset, | |
1100 | uint32_t start_alignment) | |
1101 | { | |
1102 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1103 | } | |
1104 | ||
1105 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1106 | uint32_t offset, | |
1107 | uint32_t size_alignment) | |
1108 | { | |
1109 | wa_ctx->size = offset - wa_ctx->offset; | |
1110 | ||
1111 | WARN(wa_ctx->size % size_alignment, | |
1112 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1113 | wa_ctx->size, size_alignment); | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | /** | |
1118 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1119 | * | |
1120 | * @ring: only applicable for RCS | |
1121 | * @wa_ctx: structure representing wa_ctx | |
1122 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1123 | * with the offset value received as input. | |
1124 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1125 | * @batch: page in which WA are loaded | |
1126 | * @offset: This field specifies the start of the batch, it should be | |
1127 | * cache-aligned otherwise it is adjusted accordingly. | |
1128 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1129 | * initialized at the beginning and shared across all contexts but this field | |
1130 | * helps us to have multiple batches at different offsets and select them based | |
1131 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1132 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1133 | * | |
1134 | * The number of WA applied are not known at the beginning; we use this field | |
1135 | * to return the no of DWORDS written. | |
4d78c8dc | 1136 | * |
17ee950d AS |
1137 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1138 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1139 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1140 | * makes a complete batch buffer. | |
1141 | * | |
1142 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1143 | */ | |
1144 | ||
1145 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, | |
1146 | struct i915_wa_ctx_bb *wa_ctx, | |
1147 | uint32_t *const batch, | |
1148 | uint32_t *offset) | |
1149 | { | |
1150 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1151 | ||
7ad00d1a AS |
1152 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
1153 | wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
17ee950d | 1154 | |
c82435bb AS |
1155 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
1156 | if (IS_BROADWELL(ring->dev)) { | |
1157 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
1158 | uint32_t l3sqc4_flush = (I915_READ(GEN8_L3SQCREG4) | | |
1159 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1160 | ||
1161 | wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1)); | |
1162 | wa_ctx_emit(batch, GEN8_L3SQCREG4); | |
1163 | wa_ctx_emit(batch, l3sqc4_flush); | |
1164 | ||
1165 | wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6)); | |
1166 | wa_ctx_emit(batch, (PIPE_CONTROL_CS_STALL | | |
1167 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1168 | wa_ctx_emit(batch, 0); | |
1169 | wa_ctx_emit(batch, 0); | |
1170 | wa_ctx_emit(batch, 0); | |
1171 | wa_ctx_emit(batch, 0); | |
1172 | ||
1173 | wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1)); | |
1174 | wa_ctx_emit(batch, GEN8_L3SQCREG4); | |
1175 | wa_ctx_emit(batch, l3sqc4_flush & ~GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1176 | } | |
1177 | ||
17ee950d AS |
1178 | /* Pad to end of cacheline */ |
1179 | while (index % CACHELINE_DWORDS) | |
1180 | wa_ctx_emit(batch, MI_NOOP); | |
1181 | ||
1182 | /* | |
1183 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1184 | * execution depends on the length specified in terms of cache lines | |
1185 | * in the register CTX_RCS_INDIRECT_CTX | |
1186 | */ | |
1187 | ||
1188 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1189 | } | |
1190 | ||
1191 | /** | |
1192 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1193 | * | |
1194 | * @ring: only applicable for RCS | |
1195 | * @wa_ctx: structure representing wa_ctx | |
1196 | * offset: specifies start of the batch, should be cache-aligned. | |
1197 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1198 | * @batch: page in which WA are loaded |
17ee950d AS |
1199 | * @offset: This field specifies the start of this batch. |
1200 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1201 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1202 | * | |
1203 | * The number of DWORDS written are returned using this field. | |
1204 | * | |
1205 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1206 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1207 | */ | |
1208 | static int gen8_init_perctx_bb(struct intel_engine_cs *ring, | |
1209 | struct i915_wa_ctx_bb *wa_ctx, | |
1210 | uint32_t *const batch, | |
1211 | uint32_t *offset) | |
1212 | { | |
1213 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1214 | ||
7ad00d1a AS |
1215 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
1216 | wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
1217 | ||
17ee950d AS |
1218 | wa_ctx_emit(batch, MI_BATCH_BUFFER_END); |
1219 | ||
1220 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1221 | } | |
1222 | ||
1223 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) | |
1224 | { | |
1225 | int ret; | |
1226 | ||
1227 | ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); | |
1228 | if (!ring->wa_ctx.obj) { | |
1229 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); | |
1230 | return -ENOMEM; | |
1231 | } | |
1232 | ||
1233 | ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); | |
1234 | if (ret) { | |
1235 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1236 | ret); | |
1237 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) | |
1245 | { | |
1246 | if (ring->wa_ctx.obj) { | |
1247 | i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); | |
1248 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1249 | ring->wa_ctx.obj = NULL; | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | static int intel_init_workaround_bb(struct intel_engine_cs *ring) | |
1254 | { | |
1255 | int ret; | |
1256 | uint32_t *batch; | |
1257 | uint32_t offset; | |
1258 | struct page *page; | |
1259 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
1260 | ||
1261 | WARN_ON(ring->id != RCS); | |
1262 | ||
5e60d790 AS |
1263 | /* update this when WA for higher Gen are added */ |
1264 | if (WARN(INTEL_INFO(ring->dev)->gen > 8, | |
1265 | "WA batch buffer is not initialized for Gen%d\n", | |
1266 | INTEL_INFO(ring->dev)->gen)) | |
1267 | return 0; | |
1268 | ||
c4db7599 AS |
1269 | /* some WA perform writes to scratch page, ensure it is valid */ |
1270 | if (ring->scratch.obj == NULL) { | |
1271 | DRM_ERROR("scratch page not allocated for %s\n", ring->name); | |
1272 | return -EINVAL; | |
1273 | } | |
1274 | ||
17ee950d AS |
1275 | ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); |
1276 | if (ret) { | |
1277 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1278 | return ret; | |
1279 | } | |
1280 | ||
1281 | page = i915_gem_object_get_page(wa_ctx->obj, 0); | |
1282 | batch = kmap_atomic(page); | |
1283 | offset = 0; | |
1284 | ||
1285 | if (INTEL_INFO(ring->dev)->gen == 8) { | |
1286 | ret = gen8_init_indirectctx_bb(ring, | |
1287 | &wa_ctx->indirect_ctx, | |
1288 | batch, | |
1289 | &offset); | |
1290 | if (ret) | |
1291 | goto out; | |
1292 | ||
1293 | ret = gen8_init_perctx_bb(ring, | |
1294 | &wa_ctx->per_ctx, | |
1295 | batch, | |
1296 | &offset); | |
1297 | if (ret) | |
1298 | goto out; | |
17ee950d AS |
1299 | } |
1300 | ||
1301 | out: | |
1302 | kunmap_atomic(batch); | |
1303 | if (ret) | |
1304 | lrc_destroy_wa_ctx_obj(ring); | |
1305 | ||
1306 | return ret; | |
1307 | } | |
1308 | ||
9b1136d5 OM |
1309 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1310 | { | |
1311 | struct drm_device *dev = ring->dev; | |
1312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1313 | ||
73d477f6 OM |
1314 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1315 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1316 | ||
9b1136d5 OM |
1317 | I915_WRITE(RING_MODE_GEN7(ring), |
1318 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1319 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1320 | POSTING_READ(RING_MODE_GEN7(ring)); | |
c0a03a2e | 1321 | ring->next_context_status_buffer = 0; |
9b1136d5 OM |
1322 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
1323 | ||
1324 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1325 | ||
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1330 | { | |
1331 | struct drm_device *dev = ring->dev; | |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1333 | int ret; | |
1334 | ||
1335 | ret = gen8_init_common_ring(ring); | |
1336 | if (ret) | |
1337 | return ret; | |
1338 | ||
1339 | /* We need to disable the AsyncFlip performance optimisations in order | |
1340 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1341 | * programmed to '1' on all products. | |
1342 | * | |
1343 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1344 | */ | |
1345 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1346 | ||
9b1136d5 OM |
1347 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1348 | ||
771b9a53 | 1349 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1350 | } |
1351 | ||
82ef822e DL |
1352 | static int gen9_init_render_ring(struct intel_engine_cs *ring) |
1353 | { | |
1354 | int ret; | |
1355 | ||
1356 | ret = gen8_init_common_ring(ring); | |
1357 | if (ret) | |
1358 | return ret; | |
1359 | ||
1360 | return init_workarounds_ring(ring); | |
1361 | } | |
1362 | ||
be795fc1 | 1363 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1364 | u64 offset, unsigned dispatch_flags) |
15648585 | 1365 | { |
be795fc1 | 1366 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1367 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1368 | int ret; |
1369 | ||
4d616a29 | 1370 | ret = intel_logical_ring_begin(req, 4); |
15648585 OM |
1371 | if (ret) |
1372 | return ret; | |
1373 | ||
1374 | /* FIXME(BDW): Address space and security selectors. */ | |
1375 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); | |
1376 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); | |
1377 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1378 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1379 | intel_logical_ring_advance(ringbuf); | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
73d477f6 OM |
1384 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1385 | { | |
1386 | struct drm_device *dev = ring->dev; | |
1387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1388 | unsigned long flags; | |
1389 | ||
7cd512f1 | 1390 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1391 | return false; |
1392 | ||
1393 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1394 | if (ring->irq_refcount++ == 0) { | |
1395 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1396 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1397 | } | |
1398 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1399 | ||
1400 | return true; | |
1401 | } | |
1402 | ||
1403 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1404 | { | |
1405 | struct drm_device *dev = ring->dev; | |
1406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1407 | unsigned long flags; | |
1408 | ||
1409 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1410 | if (--ring->irq_refcount == 0) { | |
1411 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1412 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1413 | } | |
1414 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1415 | } | |
1416 | ||
7deb4d39 | 1417 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1418 | u32 invalidate_domains, |
1419 | u32 unused) | |
1420 | { | |
7deb4d39 | 1421 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1422 | struct intel_engine_cs *ring = ringbuf->ring; |
1423 | struct drm_device *dev = ring->dev; | |
1424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1425 | uint32_t cmd; | |
1426 | int ret; | |
1427 | ||
4d616a29 | 1428 | ret = intel_logical_ring_begin(request, 4); |
4712274c OM |
1429 | if (ret) |
1430 | return ret; | |
1431 | ||
1432 | cmd = MI_FLUSH_DW + 1; | |
1433 | ||
f0a1fb10 CW |
1434 | /* We always require a command barrier so that subsequent |
1435 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1436 | * wrt the contents of the write cache being flushed to memory | |
1437 | * (and thus being coherent from the CPU). | |
1438 | */ | |
1439 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1440 | ||
1441 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1442 | cmd |= MI_INVALIDATE_TLB; | |
1443 | if (ring == &dev_priv->ring[VCS]) | |
1444 | cmd |= MI_INVALIDATE_BSD; | |
4712274c OM |
1445 | } |
1446 | ||
1447 | intel_logical_ring_emit(ringbuf, cmd); | |
1448 | intel_logical_ring_emit(ringbuf, | |
1449 | I915_GEM_HWS_SCRATCH_ADDR | | |
1450 | MI_FLUSH_DW_USE_GTT); | |
1451 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1452 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1453 | intel_logical_ring_advance(ringbuf); | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
7deb4d39 | 1458 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1459 | u32 invalidate_domains, |
1460 | u32 flush_domains) | |
1461 | { | |
7deb4d39 | 1462 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1463 | struct intel_engine_cs *ring = ringbuf->ring; |
1464 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
9647ff36 | 1465 | bool vf_flush_wa; |
4712274c OM |
1466 | u32 flags = 0; |
1467 | int ret; | |
1468 | ||
1469 | flags |= PIPE_CONTROL_CS_STALL; | |
1470 | ||
1471 | if (flush_domains) { | |
1472 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1473 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1474 | } | |
1475 | ||
1476 | if (invalidate_domains) { | |
1477 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1478 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1479 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1480 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1481 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1482 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1483 | flags |= PIPE_CONTROL_QW_WRITE; | |
1484 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1485 | } | |
1486 | ||
9647ff36 ID |
1487 | /* |
1488 | * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe | |
1489 | * control. | |
1490 | */ | |
1491 | vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && | |
1492 | flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1493 | ||
4d616a29 | 1494 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1495 | if (ret) |
1496 | return ret; | |
1497 | ||
9647ff36 ID |
1498 | if (vf_flush_wa) { |
1499 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1500 | intel_logical_ring_emit(ringbuf, 0); | |
1501 | intel_logical_ring_emit(ringbuf, 0); | |
1502 | intel_logical_ring_emit(ringbuf, 0); | |
1503 | intel_logical_ring_emit(ringbuf, 0); | |
1504 | intel_logical_ring_emit(ringbuf, 0); | |
1505 | } | |
1506 | ||
4712274c OM |
1507 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1508 | intel_logical_ring_emit(ringbuf, flags); | |
1509 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1510 | intel_logical_ring_emit(ringbuf, 0); | |
1511 | intel_logical_ring_emit(ringbuf, 0); | |
1512 | intel_logical_ring_emit(ringbuf, 0); | |
1513 | intel_logical_ring_advance(ringbuf); | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
e94e37ad OM |
1518 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1519 | { | |
1520 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1521 | } | |
1522 | ||
1523 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1524 | { | |
1525 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1526 | } | |
1527 | ||
c4e76638 | 1528 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1529 | { |
c4e76638 | 1530 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1531 | struct intel_engine_cs *ring = ringbuf->ring; |
1532 | u32 cmd; | |
1533 | int ret; | |
1534 | ||
53292cdb MT |
1535 | /* |
1536 | * Reserve space for 2 NOOPs at the end of each request to be | |
1537 | * used as a workaround for not being allowed to do lite | |
1538 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1539 | */ | |
4d616a29 | 1540 | ret = intel_logical_ring_begin(request, 8); |
4da46e1e OM |
1541 | if (ret) |
1542 | return ret; | |
1543 | ||
8edfbb8b | 1544 | cmd = MI_STORE_DWORD_IMM_GEN4; |
4da46e1e OM |
1545 | cmd |= MI_GLOBAL_GTT; |
1546 | ||
1547 | intel_logical_ring_emit(ringbuf, cmd); | |
1548 | intel_logical_ring_emit(ringbuf, | |
1549 | (ring->status_page.gfx_addr + | |
1550 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1551 | intel_logical_ring_emit(ringbuf, 0); | |
c4e76638 | 1552 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1553 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1554 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
ae70797d | 1555 | intel_logical_ring_advance_and_submit(request); |
4da46e1e | 1556 | |
53292cdb MT |
1557 | /* |
1558 | * Here we add two extra NOOPs as padding to avoid | |
1559 | * lite restore of a context with HEAD==TAIL. | |
1560 | */ | |
1561 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1562 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1563 | intel_logical_ring_advance(ringbuf); | |
1564 | ||
4da46e1e OM |
1565 | return 0; |
1566 | } | |
1567 | ||
be01363f | 1568 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1569 | { |
cef437ad | 1570 | struct render_state so; |
cef437ad DL |
1571 | int ret; |
1572 | ||
be01363f | 1573 | ret = i915_gem_render_state_prepare(req->ring, &so); |
cef437ad DL |
1574 | if (ret) |
1575 | return ret; | |
1576 | ||
1577 | if (so.rodata == NULL) | |
1578 | return 0; | |
1579 | ||
be795fc1 | 1580 | ret = req->ring->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1581 | I915_DISPATCH_SECURE); |
cef437ad DL |
1582 | if (ret) |
1583 | goto out; | |
1584 | ||
b2af0376 | 1585 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1586 | |
cef437ad DL |
1587 | out: |
1588 | i915_gem_render_state_fini(&so); | |
1589 | return ret; | |
1590 | } | |
1591 | ||
8753181e | 1592 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1593 | { |
1594 | int ret; | |
1595 | ||
e2be4faf | 1596 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1597 | if (ret) |
1598 | return ret; | |
1599 | ||
be01363f | 1600 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1601 | } |
1602 | ||
73e4d07f OM |
1603 | /** |
1604 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1605 | * | |
1606 | * @ring: Engine Command Streamer. | |
1607 | * | |
1608 | */ | |
454afebd OM |
1609 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1610 | { | |
6402c330 | 1611 | struct drm_i915_private *dev_priv; |
9832b9da | 1612 | |
48d82387 OM |
1613 | if (!intel_ring_initialized(ring)) |
1614 | return; | |
1615 | ||
6402c330 JH |
1616 | dev_priv = ring->dev->dev_private; |
1617 | ||
9832b9da OM |
1618 | intel_logical_ring_stop(ring); |
1619 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1620 | |
1621 | if (ring->cleanup) | |
1622 | ring->cleanup(ring); | |
1623 | ||
1624 | i915_cmd_parser_fini_ring(ring); | |
06fbca71 | 1625 | i915_gem_batch_pool_fini(&ring->batch_pool); |
48d82387 OM |
1626 | |
1627 | if (ring->status_page.obj) { | |
1628 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1629 | ring->status_page.obj = NULL; | |
1630 | } | |
17ee950d AS |
1631 | |
1632 | lrc_destroy_wa_ctx_obj(ring); | |
454afebd OM |
1633 | } |
1634 | ||
1635 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1636 | { | |
48d82387 | 1637 | int ret; |
48d82387 OM |
1638 | |
1639 | /* Intentionally left blank. */ | |
1640 | ring->buffer = NULL; | |
1641 | ||
1642 | ring->dev = dev; | |
1643 | INIT_LIST_HEAD(&ring->active_list); | |
1644 | INIT_LIST_HEAD(&ring->request_list); | |
06fbca71 | 1645 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
48d82387 OM |
1646 | init_waitqueue_head(&ring->irq_queue); |
1647 | ||
acdd884a | 1648 | INIT_LIST_HEAD(&ring->execlist_queue); |
c86ee3a9 | 1649 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
acdd884a MT |
1650 | spin_lock_init(&ring->execlist_lock); |
1651 | ||
48d82387 OM |
1652 | ret = i915_cmd_parser_init_ring(ring); |
1653 | if (ret) | |
1654 | return ret; | |
1655 | ||
564ddb2f OM |
1656 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
1657 | ||
1658 | return ret; | |
454afebd OM |
1659 | } |
1660 | ||
1661 | static int logical_render_ring_init(struct drm_device *dev) | |
1662 | { | |
1663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1664 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
99be1dfe | 1665 | int ret; |
454afebd OM |
1666 | |
1667 | ring->name = "render ring"; | |
1668 | ring->id = RCS; | |
1669 | ring->mmio_base = RENDER_RING_BASE; | |
1670 | ring->irq_enable_mask = | |
1671 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1672 | ring->irq_keep_mask = |
1673 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1674 | if (HAS_L3_DPF(dev)) | |
1675 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1676 | |
82ef822e DL |
1677 | if (INTEL_INFO(dev)->gen >= 9) |
1678 | ring->init_hw = gen9_init_render_ring; | |
1679 | else | |
1680 | ring->init_hw = gen8_init_render_ring; | |
e7778be1 | 1681 | ring->init_context = gen8_init_rcs_context; |
9b1136d5 | 1682 | ring->cleanup = intel_fini_pipe_control; |
e94e37ad OM |
1683 | ring->get_seqno = gen8_get_seqno; |
1684 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1685 | ring->emit_request = gen8_emit_request; |
4712274c | 1686 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1687 | ring->irq_get = gen8_logical_ring_get_irq; |
1688 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1689 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1690 | |
99be1dfe | 1691 | ring->dev = dev; |
c4db7599 AS |
1692 | |
1693 | ret = intel_init_pipe_control(ring); | |
99be1dfe DV |
1694 | if (ret) |
1695 | return ret; | |
1696 | ||
17ee950d AS |
1697 | ret = intel_init_workaround_bb(ring); |
1698 | if (ret) { | |
1699 | /* | |
1700 | * We continue even if we fail to initialize WA batch | |
1701 | * because we only expect rare glitches but nothing | |
1702 | * critical to prevent us from using GPU | |
1703 | */ | |
1704 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1705 | ret); | |
1706 | } | |
1707 | ||
c4db7599 AS |
1708 | ret = logical_ring_init(dev, ring); |
1709 | if (ret) { | |
17ee950d | 1710 | lrc_destroy_wa_ctx_obj(ring); |
c4db7599 | 1711 | } |
17ee950d AS |
1712 | |
1713 | return ret; | |
454afebd OM |
1714 | } |
1715 | ||
1716 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1717 | { | |
1718 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1719 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1720 | ||
1721 | ring->name = "bsd ring"; | |
1722 | ring->id = VCS; | |
1723 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1724 | ring->irq_enable_mask = | |
1725 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1726 | ring->irq_keep_mask = |
1727 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1728 | |
ecfe00d8 | 1729 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1730 | ring->get_seqno = gen8_get_seqno; |
1731 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1732 | ring->emit_request = gen8_emit_request; |
4712274c | 1733 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1734 | ring->irq_get = gen8_logical_ring_get_irq; |
1735 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1736 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1737 | |
454afebd OM |
1738 | return logical_ring_init(dev, ring); |
1739 | } | |
1740 | ||
1741 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
1742 | { | |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1744 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
1745 | ||
1746 | ring->name = "bds2 ring"; | |
1747 | ring->id = VCS2; | |
1748 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
1749 | ring->irq_enable_mask = | |
1750 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
1751 | ring->irq_keep_mask = |
1752 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 1753 | |
ecfe00d8 | 1754 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1755 | ring->get_seqno = gen8_get_seqno; |
1756 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1757 | ring->emit_request = gen8_emit_request; |
4712274c | 1758 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1759 | ring->irq_get = gen8_logical_ring_get_irq; |
1760 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1761 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1762 | |
454afebd OM |
1763 | return logical_ring_init(dev, ring); |
1764 | } | |
1765 | ||
1766 | static int logical_blt_ring_init(struct drm_device *dev) | |
1767 | { | |
1768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1769 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
1770 | ||
1771 | ring->name = "blitter ring"; | |
1772 | ring->id = BCS; | |
1773 | ring->mmio_base = BLT_RING_BASE; | |
1774 | ring->irq_enable_mask = | |
1775 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
1776 | ring->irq_keep_mask = |
1777 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 1778 | |
ecfe00d8 | 1779 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1780 | ring->get_seqno = gen8_get_seqno; |
1781 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1782 | ring->emit_request = gen8_emit_request; |
4712274c | 1783 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1784 | ring->irq_get = gen8_logical_ring_get_irq; |
1785 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1786 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1787 | |
454afebd OM |
1788 | return logical_ring_init(dev, ring); |
1789 | } | |
1790 | ||
1791 | static int logical_vebox_ring_init(struct drm_device *dev) | |
1792 | { | |
1793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1794 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
1795 | ||
1796 | ring->name = "video enhancement ring"; | |
1797 | ring->id = VECS; | |
1798 | ring->mmio_base = VEBOX_RING_BASE; | |
1799 | ring->irq_enable_mask = | |
1800 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
1801 | ring->irq_keep_mask = |
1802 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 1803 | |
ecfe00d8 | 1804 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1805 | ring->get_seqno = gen8_get_seqno; |
1806 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1807 | ring->emit_request = gen8_emit_request; |
4712274c | 1808 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1809 | ring->irq_get = gen8_logical_ring_get_irq; |
1810 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1811 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1812 | |
454afebd OM |
1813 | return logical_ring_init(dev, ring); |
1814 | } | |
1815 | ||
73e4d07f OM |
1816 | /** |
1817 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
1818 | * @dev: DRM device. | |
1819 | * | |
1820 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
1821 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
1822 | * those engines that are present in the hardware. | |
1823 | * | |
1824 | * Return: non-zero if the initialization failed. | |
1825 | */ | |
454afebd OM |
1826 | int intel_logical_rings_init(struct drm_device *dev) |
1827 | { | |
1828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1829 | int ret; | |
1830 | ||
1831 | ret = logical_render_ring_init(dev); | |
1832 | if (ret) | |
1833 | return ret; | |
1834 | ||
1835 | if (HAS_BSD(dev)) { | |
1836 | ret = logical_bsd_ring_init(dev); | |
1837 | if (ret) | |
1838 | goto cleanup_render_ring; | |
1839 | } | |
1840 | ||
1841 | if (HAS_BLT(dev)) { | |
1842 | ret = logical_blt_ring_init(dev); | |
1843 | if (ret) | |
1844 | goto cleanup_bsd_ring; | |
1845 | } | |
1846 | ||
1847 | if (HAS_VEBOX(dev)) { | |
1848 | ret = logical_vebox_ring_init(dev); | |
1849 | if (ret) | |
1850 | goto cleanup_blt_ring; | |
1851 | } | |
1852 | ||
1853 | if (HAS_BSD2(dev)) { | |
1854 | ret = logical_bsd2_ring_init(dev); | |
1855 | if (ret) | |
1856 | goto cleanup_vebox_ring; | |
1857 | } | |
1858 | ||
1859 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
1860 | if (ret) | |
1861 | goto cleanup_bsd2_ring; | |
1862 | ||
1863 | return 0; | |
1864 | ||
1865 | cleanup_bsd2_ring: | |
1866 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
1867 | cleanup_vebox_ring: | |
1868 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
1869 | cleanup_blt_ring: | |
1870 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
1871 | cleanup_bsd_ring: | |
1872 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
1873 | cleanup_render_ring: | |
1874 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
1875 | ||
1876 | return ret; | |
1877 | } | |
1878 | ||
0cea6502 JM |
1879 | static u32 |
1880 | make_rpcs(struct drm_device *dev) | |
1881 | { | |
1882 | u32 rpcs = 0; | |
1883 | ||
1884 | /* | |
1885 | * No explicit RPCS request is needed to ensure full | |
1886 | * slice/subslice/EU enablement prior to Gen9. | |
1887 | */ | |
1888 | if (INTEL_INFO(dev)->gen < 9) | |
1889 | return 0; | |
1890 | ||
1891 | /* | |
1892 | * Starting in Gen9, render power gating can leave | |
1893 | * slice/subslice/EU in a partially enabled state. We | |
1894 | * must make an explicit request through RPCS for full | |
1895 | * enablement. | |
1896 | */ | |
1897 | if (INTEL_INFO(dev)->has_slice_pg) { | |
1898 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
1899 | rpcs |= INTEL_INFO(dev)->slice_total << | |
1900 | GEN8_RPCS_S_CNT_SHIFT; | |
1901 | rpcs |= GEN8_RPCS_ENABLE; | |
1902 | } | |
1903 | ||
1904 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
1905 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
1906 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
1907 | GEN8_RPCS_SS_CNT_SHIFT; | |
1908 | rpcs |= GEN8_RPCS_ENABLE; | |
1909 | } | |
1910 | ||
1911 | if (INTEL_INFO(dev)->has_eu_pg) { | |
1912 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
1913 | GEN8_RPCS_EU_MIN_SHIFT; | |
1914 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
1915 | GEN8_RPCS_EU_MAX_SHIFT; | |
1916 | rpcs |= GEN8_RPCS_ENABLE; | |
1917 | } | |
1918 | ||
1919 | return rpcs; | |
1920 | } | |
1921 | ||
8670d6f9 OM |
1922 | static int |
1923 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
1924 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
1925 | { | |
2d965536 TD |
1926 | struct drm_device *dev = ring->dev; |
1927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ae6c4806 | 1928 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
1929 | struct page *page; |
1930 | uint32_t *reg_state; | |
1931 | int ret; | |
1932 | ||
2d965536 TD |
1933 | if (!ppgtt) |
1934 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1935 | ||
8670d6f9 OM |
1936 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
1937 | if (ret) { | |
1938 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1939 | return ret; | |
1940 | } | |
1941 | ||
1942 | ret = i915_gem_object_get_pages(ctx_obj); | |
1943 | if (ret) { | |
1944 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
1945 | return ret; | |
1946 | } | |
1947 | ||
1948 | i915_gem_object_pin_pages(ctx_obj); | |
1949 | ||
1950 | /* The second page of the context object contains some fields which must | |
1951 | * be set up prior to the first execution. */ | |
1952 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1953 | reg_state = kmap_atomic(page); | |
1954 | ||
1955 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1956 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1957 | * only for the first context restore: on a subsequent save, the GPU will | |
1958 | * recreate this batchbuffer with new values (including all the missing | |
1959 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
1960 | if (ring->id == RCS) | |
1961 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
1962 | else | |
1963 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
1964 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
1965 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
1966 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
5baa22c5 ZW |
1967 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
1968 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); | |
8670d6f9 OM |
1969 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
1970 | reg_state[CTX_RING_HEAD+1] = 0; | |
1971 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
1972 | reg_state[CTX_RING_TAIL+1] = 0; | |
1973 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
7ba717cf TD |
1974 | /* Ring buffer start address is not known until the buffer is pinned. |
1975 | * It is written to the context image in execlists_update_context() | |
1976 | */ | |
8670d6f9 OM |
1977 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
1978 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
1979 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
1980 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
1981 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
1982 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
1983 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
1984 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
1985 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
1986 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
1987 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
1988 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
1989 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
1990 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
1991 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
1992 | if (ring->id == RCS) { | |
8670d6f9 OM |
1993 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
1994 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
1995 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
1996 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
1997 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
1998 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
17ee950d AS |
1999 | if (ring->wa_ctx.obj) { |
2000 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
2001 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); | |
2002 | ||
2003 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2004 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2005 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2006 | ||
2007 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
2008 | CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; | |
2009 | ||
2010 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2011 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2012 | 0x01; | |
2013 | } | |
8670d6f9 OM |
2014 | } |
2015 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
2016 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
2017 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
2018 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
2019 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
2020 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
2021 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
2022 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
2023 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
2024 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
2025 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
2026 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
d7b2633d MT |
2027 | |
2028 | /* With dynamic page allocation, PDPs may not be allocated at this point, | |
2029 | * Point the unallocated PDPs to the scratch page | |
e5815a2e MT |
2030 | */ |
2031 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
2032 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
2033 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
2034 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
8670d6f9 OM |
2035 | if (ring->id == RCS) { |
2036 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
0cea6502 JM |
2037 | reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; |
2038 | reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); | |
8670d6f9 OM |
2039 | } |
2040 | ||
2041 | kunmap_atomic(reg_state); | |
2042 | ||
2043 | ctx_obj->dirty = 1; | |
2044 | set_page_dirty(page); | |
2045 | i915_gem_object_unpin_pages(ctx_obj); | |
2046 | ||
2047 | return 0; | |
2048 | } | |
2049 | ||
73e4d07f OM |
2050 | /** |
2051 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2052 | * @ctx: the LR context to free. | |
2053 | * | |
2054 | * The real context freeing is done in i915_gem_context_free: this only | |
2055 | * takes care of the bits that are LRC related: the per-engine backing | |
2056 | * objects and the logical ringbuffer. | |
2057 | */ | |
ede7d42b OM |
2058 | void intel_lr_context_free(struct intel_context *ctx) |
2059 | { | |
8c857917 OM |
2060 | int i; |
2061 | ||
2062 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2063 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f | 2064 | |
8c857917 | 2065 | if (ctx_obj) { |
dcb4c12a OM |
2066 | struct intel_ringbuffer *ringbuf = |
2067 | ctx->engine[i].ringbuf; | |
2068 | struct intel_engine_cs *ring = ringbuf->ring; | |
2069 | ||
7ba717cf TD |
2070 | if (ctx == ring->default_context) { |
2071 | intel_unpin_ringbuffer_obj(ringbuf); | |
2072 | i915_gem_object_ggtt_unpin(ctx_obj); | |
2073 | } | |
a7cbedec | 2074 | WARN_ON(ctx->engine[ring->id].pin_count); |
84c2377f OM |
2075 | intel_destroy_ringbuffer_obj(ringbuf); |
2076 | kfree(ringbuf); | |
8c857917 OM |
2077 | drm_gem_object_unreference(&ctx_obj->base); |
2078 | } | |
2079 | } | |
2080 | } | |
2081 | ||
2082 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
2083 | { | |
2084 | int ret = 0; | |
2085 | ||
468c6816 | 2086 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
2087 | |
2088 | switch (ring->id) { | |
2089 | case RCS: | |
468c6816 MN |
2090 | if (INTEL_INFO(ring->dev)->gen >= 9) |
2091 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
2092 | else | |
2093 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2094 | break; |
2095 | case VCS: | |
2096 | case BCS: | |
2097 | case VECS: | |
2098 | case VCS2: | |
2099 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2100 | break; | |
2101 | } | |
2102 | ||
2103 | return ret; | |
ede7d42b OM |
2104 | } |
2105 | ||
70b0ea86 | 2106 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1df06b75 TD |
2107 | struct drm_i915_gem_object *default_ctx_obj) |
2108 | { | |
2109 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2110 | ||
2111 | /* The status page is offset 0 from the default context object | |
2112 | * in LRC mode. */ | |
2113 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); | |
2114 | ring->status_page.page_addr = | |
2115 | kmap(sg_page(default_ctx_obj->pages->sgl)); | |
1df06b75 TD |
2116 | ring->status_page.obj = default_ctx_obj; |
2117 | ||
2118 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
2119 | (u32)ring->status_page.gfx_addr); | |
2120 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1df06b75 TD |
2121 | } |
2122 | ||
73e4d07f OM |
2123 | /** |
2124 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context | |
2125 | * @ctx: LR context to create. | |
2126 | * @ring: engine to be used with the context. | |
2127 | * | |
2128 | * This function can be called more than once, with different engines, if we plan | |
2129 | * to use the context with them. The context backing objects and the ringbuffers | |
2130 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2131 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2132 | * a given ring with the context. | |
2133 | * | |
32197aab | 2134 | * Return: non-zero on error. |
73e4d07f | 2135 | */ |
ede7d42b OM |
2136 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
2137 | struct intel_engine_cs *ring) | |
2138 | { | |
dcb4c12a | 2139 | const bool is_global_default_ctx = (ctx == ring->default_context); |
8c857917 OM |
2140 | struct drm_device *dev = ring->dev; |
2141 | struct drm_i915_gem_object *ctx_obj; | |
2142 | uint32_t context_size; | |
84c2377f | 2143 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2144 | int ret; |
2145 | ||
ede7d42b | 2146 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
bfc882b4 | 2147 | WARN_ON(ctx->engine[ring->id].state); |
ede7d42b | 2148 | |
8c857917 OM |
2149 | context_size = round_up(get_lr_context_size(ring), 4096); |
2150 | ||
149c86e7 | 2151 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2152 | if (!ctx_obj) { |
2153 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2154 | return -ENOMEM; | |
8c857917 OM |
2155 | } |
2156 | ||
dcb4c12a OM |
2157 | if (is_global_default_ctx) { |
2158 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
2159 | if (ret) { | |
2160 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", | |
2161 | ret); | |
2162 | drm_gem_object_unreference(&ctx_obj->base); | |
2163 | return ret; | |
2164 | } | |
8c857917 OM |
2165 | } |
2166 | ||
84c2377f OM |
2167 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
2168 | if (!ringbuf) { | |
2169 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2170 | ring->name); | |
84c2377f | 2171 | ret = -ENOMEM; |
7ba717cf | 2172 | goto error_unpin_ctx; |
84c2377f OM |
2173 | } |
2174 | ||
0c7dd53b | 2175 | ringbuf->ring = ring; |
582d67f0 | 2176 | |
84c2377f OM |
2177 | ringbuf->size = 32 * PAGE_SIZE; |
2178 | ringbuf->effective_size = ringbuf->size; | |
2179 | ringbuf->head = 0; | |
2180 | ringbuf->tail = 0; | |
84c2377f | 2181 | ringbuf->last_retired_head = -1; |
ebd0fd4b | 2182 | intel_ring_update_space(ringbuf); |
84c2377f | 2183 | |
7ba717cf TD |
2184 | if (ringbuf->obj == NULL) { |
2185 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
2186 | if (ret) { | |
2187 | DRM_DEBUG_DRIVER( | |
2188 | "Failed to allocate ringbuffer obj %s: %d\n", | |
84c2377f | 2189 | ring->name, ret); |
7ba717cf TD |
2190 | goto error_free_rbuf; |
2191 | } | |
2192 | ||
2193 | if (is_global_default_ctx) { | |
2194 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
2195 | if (ret) { | |
2196 | DRM_ERROR( | |
2197 | "Failed to pin and map ringbuffer %s: %d\n", | |
2198 | ring->name, ret); | |
2199 | goto error_destroy_rbuf; | |
2200 | } | |
2201 | } | |
2202 | ||
8670d6f9 OM |
2203 | } |
2204 | ||
2205 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
2206 | if (ret) { | |
2207 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
8670d6f9 | 2208 | goto error; |
84c2377f OM |
2209 | } |
2210 | ||
2211 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 2212 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 2213 | |
70b0ea86 DV |
2214 | if (ctx == ring->default_context) |
2215 | lrc_setup_hardware_status_page(ring, ctx_obj); | |
e7778be1 | 2216 | else if (ring->id == RCS && !ctx->rcs_initialized) { |
771b9a53 | 2217 | if (ring->init_context) { |
76c39168 JH |
2218 | struct drm_i915_gem_request *req; |
2219 | ||
2220 | ret = i915_gem_request_alloc(ring, ctx, &req); | |
2221 | if (ret) | |
2222 | return ret; | |
2223 | ||
8753181e | 2224 | ret = ring->init_context(req); |
e7778be1 | 2225 | if (ret) { |
771b9a53 | 2226 | DRM_ERROR("ring init context: %d\n", ret); |
76c39168 | 2227 | i915_gem_request_cancel(req); |
e7778be1 TD |
2228 | ctx->engine[ring->id].ringbuf = NULL; |
2229 | ctx->engine[ring->id].state = NULL; | |
2230 | goto error; | |
2231 | } | |
76c39168 | 2232 | |
75289874 | 2233 | i915_add_request_no_flush(req); |
771b9a53 MT |
2234 | } |
2235 | ||
564ddb2f OM |
2236 | ctx->rcs_initialized = true; |
2237 | } | |
2238 | ||
ede7d42b | 2239 | return 0; |
8670d6f9 OM |
2240 | |
2241 | error: | |
7ba717cf TD |
2242 | if (is_global_default_ctx) |
2243 | intel_unpin_ringbuffer_obj(ringbuf); | |
2244 | error_destroy_rbuf: | |
2245 | intel_destroy_ringbuffer_obj(ringbuf); | |
2246 | error_free_rbuf: | |
8670d6f9 | 2247 | kfree(ringbuf); |
7ba717cf | 2248 | error_unpin_ctx: |
dcb4c12a OM |
2249 | if (is_global_default_ctx) |
2250 | i915_gem_object_ggtt_unpin(ctx_obj); | |
8670d6f9 OM |
2251 | drm_gem_object_unreference(&ctx_obj->base); |
2252 | return ret; | |
ede7d42b | 2253 | } |
3e5b6f05 TD |
2254 | |
2255 | void intel_lr_context_reset(struct drm_device *dev, | |
2256 | struct intel_context *ctx) | |
2257 | { | |
2258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2259 | struct intel_engine_cs *ring; | |
2260 | int i; | |
2261 | ||
2262 | for_each_ring(ring, dev_priv, i) { | |
2263 | struct drm_i915_gem_object *ctx_obj = | |
2264 | ctx->engine[ring->id].state; | |
2265 | struct intel_ringbuffer *ringbuf = | |
2266 | ctx->engine[ring->id].ringbuf; | |
2267 | uint32_t *reg_state; | |
2268 | struct page *page; | |
2269 | ||
2270 | if (!ctx_obj) | |
2271 | continue; | |
2272 | ||
2273 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2274 | WARN(1, "Failed get_pages for context obj\n"); | |
2275 | continue; | |
2276 | } | |
2277 | page = i915_gem_object_get_page(ctx_obj, 1); | |
2278 | reg_state = kmap_atomic(page); | |
2279 | ||
2280 | reg_state[CTX_RING_HEAD+1] = 0; | |
2281 | reg_state[CTX_RING_TAIL+1] = 0; | |
2282 | ||
2283 | kunmap_atomic(reg_state); | |
2284 | ||
2285 | ringbuf->head = 0; | |
2286 | ringbuf->tail = 0; | |
2287 | } | |
2288 | } |