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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
127f1003 | 138 | |
468c6816 | 139 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
140 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
141 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
142 | ||
143 | #define GEN8_LR_CONTEXT_ALIGN 4096 | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
158 | |
159 | #define CTX_LRI_HEADER_0 0x01 | |
160 | #define CTX_CONTEXT_CONTROL 0x02 | |
161 | #define CTX_RING_HEAD 0x04 | |
162 | #define CTX_RING_TAIL 0x06 | |
163 | #define CTX_RING_BUFFER_START 0x08 | |
164 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
165 | #define CTX_BB_HEAD_U 0x0c | |
166 | #define CTX_BB_HEAD_L 0x0e | |
167 | #define CTX_BB_STATE 0x10 | |
168 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
169 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
170 | #define CTX_SECOND_BB_STATE 0x16 | |
171 | #define CTX_BB_PER_CTX_PTR 0x18 | |
172 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
173 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
174 | #define CTX_LRI_HEADER_1 0x21 | |
175 | #define CTX_CTX_TIMESTAMP 0x22 | |
176 | #define CTX_PDP3_UDW 0x24 | |
177 | #define CTX_PDP3_LDW 0x26 | |
178 | #define CTX_PDP2_UDW 0x28 | |
179 | #define CTX_PDP2_LDW 0x2a | |
180 | #define CTX_PDP1_UDW 0x2c | |
181 | #define CTX_PDP1_LDW 0x2e | |
182 | #define CTX_PDP0_UDW 0x30 | |
183 | #define CTX_PDP0_LDW 0x32 | |
184 | #define CTX_LRI_HEADER_2 0x41 | |
185 | #define CTX_R_PWR_CLK_STATE 0x42 | |
186 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
187 | ||
84b790f8 BW |
188 | #define GEN8_CTX_VALID (1<<0) |
189 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
190 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
191 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
192 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
193 | enum { | |
194 | ADVANCED_CONTEXT = 0, | |
195 | LEGACY_CONTEXT, | |
196 | ADVANCED_AD_CONTEXT, | |
197 | LEGACY_64B_CONTEXT | |
198 | }; | |
199 | #define GEN8_CTX_MODE_SHIFT 3 | |
200 | enum { | |
201 | FAULT_AND_HANG = 0, | |
202 | FAULT_AND_HALT, /* Debug only */ | |
203 | FAULT_AND_STREAM, | |
204 | FAULT_AND_CONTINUE /* Unsupported */ | |
205 | }; | |
206 | #define GEN8_CTX_ID_SHIFT 32 | |
207 | ||
73e4d07f OM |
208 | /** |
209 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
210 | * @dev: DRM device. | |
211 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
212 | * | |
213 | * Only certain platforms support Execlists (the prerequisites being | |
214 | * support for Logical Ring Contexts and Aliasing PPGTT or better), | |
215 | * and only when enabled via module parameter. | |
216 | * | |
217 | * Return: 1 if Execlists is supported and has to be enabled. | |
218 | */ | |
127f1003 OM |
219 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
220 | { | |
bd84b1e9 DV |
221 | WARN_ON(i915.enable_ppgtt == -1); |
222 | ||
70ee45e1 DL |
223 | if (INTEL_INFO(dev)->gen >= 9) |
224 | return 1; | |
225 | ||
127f1003 OM |
226 | if (enable_execlists == 0) |
227 | return 0; | |
228 | ||
14bf993e OM |
229 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
230 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
231 | return 1; |
232 | ||
233 | return 0; | |
234 | } | |
ede7d42b | 235 | |
73e4d07f OM |
236 | /** |
237 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
238 | * @ctx_obj: Logical Ring Context backing object. | |
239 | * | |
240 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
241 | * here: the old context ID we pass to userspace as a handler so that | |
242 | * they can refer to a context, and the new context ID we pass to the | |
243 | * ELSP so that the GPU can inform us of the context status via | |
244 | * interrupts. | |
245 | * | |
246 | * Return: 20-bits globally unique context ID. | |
247 | */ | |
84b790f8 BW |
248 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
249 | { | |
250 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
251 | ||
252 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
253 | * are globally unique */ | |
254 | return lrca >> 12; | |
255 | } | |
256 | ||
257 | static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj) | |
258 | { | |
259 | uint64_t desc; | |
260 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
acdd884a MT |
261 | |
262 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
263 | |
264 | desc = GEN8_CTX_VALID; | |
265 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; | |
266 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
267 | desc |= GEN8_CTX_PRIVILEGE; | |
268 | desc |= lrca; | |
269 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
270 | ||
271 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
272 | * signalling between Command Streamers */ | |
273 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
274 | ||
275 | return desc; | |
276 | } | |
277 | ||
278 | static void execlists_elsp_write(struct intel_engine_cs *ring, | |
279 | struct drm_i915_gem_object *ctx_obj0, | |
280 | struct drm_i915_gem_object *ctx_obj1) | |
281 | { | |
6e7cc470 TU |
282 | struct drm_device *dev = ring->dev; |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84b790f8 BW |
284 | uint64_t temp = 0; |
285 | uint32_t desc[4]; | |
e981e7b1 | 286 | unsigned long flags; |
84b790f8 BW |
287 | |
288 | /* XXX: You must always write both descriptors in the order below. */ | |
289 | if (ctx_obj1) | |
290 | temp = execlists_ctx_descriptor(ctx_obj1); | |
291 | else | |
292 | temp = 0; | |
293 | desc[1] = (u32)(temp >> 32); | |
294 | desc[0] = (u32)temp; | |
295 | ||
296 | temp = execlists_ctx_descriptor(ctx_obj0); | |
297 | desc[3] = (u32)(temp >> 32); | |
298 | desc[2] = (u32)temp; | |
299 | ||
e981e7b1 TD |
300 | /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes |
301 | * are in progress. | |
302 | * | |
303 | * The other problem is that we can't just call gen6_gt_force_wake_get() | |
304 | * because that function calls intel_runtime_pm_get(), which might sleep. | |
305 | * Instead, we do the runtime_pm_get/put when creating/destroying requests. | |
306 | */ | |
307 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); | |
6e7cc470 | 308 | if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
a01b0e94 D |
309 | if (dev_priv->uncore.fw_rendercount++ == 0) |
310 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
311 | FORCEWAKE_RENDER); | |
312 | if (dev_priv->uncore.fw_mediacount++ == 0) | |
313 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
314 | FORCEWAKE_MEDIA); | |
6e7cc470 TU |
315 | if (INTEL_INFO(dev)->gen >= 9) { |
316 | if (dev_priv->uncore.fw_blittercount++ == 0) | |
317 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
318 | FORCEWAKE_BLITTER); | |
319 | } | |
a01b0e94 D |
320 | } else { |
321 | if (dev_priv->uncore.forcewake_count++ == 0) | |
322 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
323 | FORCEWAKE_ALL); | |
324 | } | |
e981e7b1 | 325 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
84b790f8 BW |
326 | |
327 | I915_WRITE(RING_ELSP(ring), desc[1]); | |
328 | I915_WRITE(RING_ELSP(ring), desc[0]); | |
329 | I915_WRITE(RING_ELSP(ring), desc[3]); | |
330 | /* The context is automatically loaded after the following */ | |
331 | I915_WRITE(RING_ELSP(ring), desc[2]); | |
332 | ||
333 | /* ELSP is a wo register, so use another nearby reg for posting instead */ | |
334 | POSTING_READ(RING_EXECLIST_STATUS(ring)); | |
335 | ||
e981e7b1 TD |
336 | /* Release Force Wakeup (see the big comment above). */ |
337 | spin_lock_irqsave(&dev_priv->uncore.lock, flags); | |
6e7cc470 | 338 | if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) { |
a01b0e94 D |
339 | if (--dev_priv->uncore.fw_rendercount == 0) |
340 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
341 | FORCEWAKE_RENDER); | |
342 | if (--dev_priv->uncore.fw_mediacount == 0) | |
343 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
344 | FORCEWAKE_MEDIA); | |
6e7cc470 TU |
345 | if (INTEL_INFO(dev)->gen >= 9) { |
346 | if (--dev_priv->uncore.fw_blittercount == 0) | |
347 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
348 | FORCEWAKE_BLITTER); | |
349 | } | |
a01b0e94 D |
350 | } else { |
351 | if (--dev_priv->uncore.forcewake_count == 0) | |
352 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
353 | FORCEWAKE_ALL); | |
354 | } | |
355 | ||
e981e7b1 | 356 | spin_unlock_irqrestore(&dev_priv->uncore.lock, flags); |
84b790f8 BW |
357 | } |
358 | ||
ae1250b9 OM |
359 | static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail) |
360 | { | |
361 | struct page *page; | |
362 | uint32_t *reg_state; | |
363 | ||
364 | page = i915_gem_object_get_page(ctx_obj, 1); | |
365 | reg_state = kmap_atomic(page); | |
366 | ||
367 | reg_state[CTX_RING_TAIL+1] = tail; | |
368 | ||
369 | kunmap_atomic(reg_state); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
cd0707cb DG |
374 | static void execlists_submit_contexts(struct intel_engine_cs *ring, |
375 | struct intel_context *to0, u32 tail0, | |
376 | struct intel_context *to1, u32 tail1) | |
84b790f8 BW |
377 | { |
378 | struct drm_i915_gem_object *ctx_obj0; | |
379 | struct drm_i915_gem_object *ctx_obj1 = NULL; | |
380 | ||
381 | ctx_obj0 = to0->engine[ring->id].state; | |
382 | BUG_ON(!ctx_obj0); | |
acdd884a | 383 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); |
84b790f8 | 384 | |
ae1250b9 OM |
385 | execlists_ctx_write_tail(ctx_obj0, tail0); |
386 | ||
84b790f8 BW |
387 | if (to1) { |
388 | ctx_obj1 = to1->engine[ring->id].state; | |
389 | BUG_ON(!ctx_obj1); | |
acdd884a | 390 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); |
ae1250b9 OM |
391 | |
392 | execlists_ctx_write_tail(ctx_obj1, tail1); | |
84b790f8 BW |
393 | } |
394 | ||
395 | execlists_elsp_write(ring, ctx_obj0, ctx_obj1); | |
84b790f8 BW |
396 | } |
397 | ||
acdd884a MT |
398 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
399 | { | |
400 | struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL; | |
401 | struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
402 | |
403 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a MT |
404 | |
405 | if (list_empty(&ring->execlist_queue)) | |
406 | return; | |
407 | ||
408 | /* Try to read in pairs */ | |
409 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
410 | execlist_link) { | |
411 | if (!req0) { | |
412 | req0 = cursor; | |
413 | } else if (req0->ctx == cursor->ctx) { | |
414 | /* Same ctx: ignore first request, as second request | |
415 | * will update tail past first request's workload */ | |
e1fee72c | 416 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 417 | list_del(&req0->execlist_link); |
c86ee3a9 TD |
418 | list_add_tail(&req0->execlist_link, |
419 | &ring->execlist_retired_req_list); | |
acdd884a MT |
420 | req0 = cursor; |
421 | } else { | |
422 | req1 = cursor; | |
423 | break; | |
424 | } | |
425 | } | |
426 | ||
e1fee72c OM |
427 | WARN_ON(req1 && req1->elsp_submitted); |
428 | ||
cd0707cb DG |
429 | execlists_submit_contexts(ring, req0->ctx, req0->tail, |
430 | req1 ? req1->ctx : NULL, | |
431 | req1 ? req1->tail : 0); | |
e1fee72c OM |
432 | |
433 | req0->elsp_submitted++; | |
434 | if (req1) | |
435 | req1->elsp_submitted++; | |
acdd884a MT |
436 | } |
437 | ||
e981e7b1 TD |
438 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
439 | u32 request_id) | |
440 | { | |
e981e7b1 TD |
441 | struct intel_ctx_submit_request *head_req; |
442 | ||
443 | assert_spin_locked(&ring->execlist_lock); | |
444 | ||
445 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
446 | struct intel_ctx_submit_request, | |
447 | execlist_link); | |
448 | ||
449 | if (head_req != NULL) { | |
450 | struct drm_i915_gem_object *ctx_obj = | |
451 | head_req->ctx->engine[ring->id].state; | |
452 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { | |
e1fee72c OM |
453 | WARN(head_req->elsp_submitted == 0, |
454 | "Never submitted head request\n"); | |
455 | ||
456 | if (--head_req->elsp_submitted <= 0) { | |
457 | list_del(&head_req->execlist_link); | |
c86ee3a9 TD |
458 | list_add_tail(&head_req->execlist_link, |
459 | &ring->execlist_retired_req_list); | |
e1fee72c OM |
460 | return true; |
461 | } | |
e981e7b1 TD |
462 | } |
463 | } | |
464 | ||
465 | return false; | |
466 | } | |
467 | ||
73e4d07f OM |
468 | /** |
469 | * intel_execlists_handle_ctx_events() - handle Context Switch interrupts | |
470 | * @ring: Engine Command Streamer to handle. | |
471 | * | |
472 | * Check the unread Context Status Buffers and manage the submission of new | |
473 | * contexts to the ELSP accordingly. | |
474 | */ | |
e981e7b1 TD |
475 | void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring) |
476 | { | |
477 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
478 | u32 status_pointer; | |
479 | u8 read_pointer; | |
480 | u8 write_pointer; | |
481 | u32 status; | |
482 | u32 status_id; | |
483 | u32 submit_contexts = 0; | |
484 | ||
485 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
486 | ||
487 | read_pointer = ring->next_context_status_buffer; | |
488 | write_pointer = status_pointer & 0x07; | |
489 | if (read_pointer > write_pointer) | |
490 | write_pointer += 6; | |
491 | ||
492 | spin_lock(&ring->execlist_lock); | |
493 | ||
494 | while (read_pointer < write_pointer) { | |
495 | read_pointer++; | |
496 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
497 | (read_pointer % 6) * 8); | |
498 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
499 | (read_pointer % 6) * 8 + 4); | |
500 | ||
e1fee72c OM |
501 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
502 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
503 | if (execlists_check_remove_request(ring, status_id)) | |
504 | WARN(1, "Lite Restored request removed from queue\n"); | |
505 | } else | |
506 | WARN(1, "Preemption without Lite Restore\n"); | |
507 | } | |
508 | ||
509 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
510 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
511 | if (execlists_check_remove_request(ring, status_id)) |
512 | submit_contexts++; | |
513 | } | |
514 | } | |
515 | ||
516 | if (submit_contexts != 0) | |
517 | execlists_context_unqueue(ring); | |
518 | ||
519 | spin_unlock(&ring->execlist_lock); | |
520 | ||
521 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
522 | ring->next_context_status_buffer = write_pointer % 6; | |
523 | ||
524 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
525 | ((u32)ring->next_context_status_buffer & 0x07) << 8); | |
526 | } | |
527 | ||
acdd884a MT |
528 | static int execlists_context_queue(struct intel_engine_cs *ring, |
529 | struct intel_context *to, | |
530 | u32 tail) | |
531 | { | |
f1ad5a1f | 532 | struct intel_ctx_submit_request *req = NULL, *cursor; |
e981e7b1 | 533 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acdd884a | 534 | unsigned long flags; |
f1ad5a1f | 535 | int num_elements = 0; |
acdd884a MT |
536 | |
537 | req = kzalloc(sizeof(*req), GFP_KERNEL); | |
538 | if (req == NULL) | |
539 | return -ENOMEM; | |
540 | req->ctx = to; | |
541 | i915_gem_context_reference(req->ctx); | |
542 | req->ring = ring; | |
543 | req->tail = tail; | |
e981e7b1 TD |
544 | |
545 | intel_runtime_pm_get(dev_priv); | |
acdd884a MT |
546 | |
547 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
548 | ||
f1ad5a1f OM |
549 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
550 | if (++num_elements > 2) | |
551 | break; | |
552 | ||
553 | if (num_elements > 2) { | |
554 | struct intel_ctx_submit_request *tail_req; | |
555 | ||
556 | tail_req = list_last_entry(&ring->execlist_queue, | |
557 | struct intel_ctx_submit_request, | |
558 | execlist_link); | |
559 | ||
560 | if (to == tail_req->ctx) { | |
561 | WARN(tail_req->elsp_submitted != 0, | |
562 | "More than 2 already-submitted reqs queued\n"); | |
563 | list_del(&tail_req->execlist_link); | |
c86ee3a9 TD |
564 | list_add_tail(&tail_req->execlist_link, |
565 | &ring->execlist_retired_req_list); | |
f1ad5a1f OM |
566 | } |
567 | } | |
568 | ||
acdd884a | 569 | list_add_tail(&req->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 570 | if (num_elements == 0) |
acdd884a MT |
571 | execlists_context_unqueue(ring); |
572 | ||
573 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
ba8b7ccb OM |
578 | static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf) |
579 | { | |
580 | struct intel_engine_cs *ring = ringbuf->ring; | |
581 | uint32_t flush_domains; | |
582 | int ret; | |
583 | ||
584 | flush_domains = 0; | |
585 | if (ring->gpu_caches_dirty) | |
586 | flush_domains = I915_GEM_GPU_DOMAINS; | |
587 | ||
588 | ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains); | |
589 | if (ret) | |
590 | return ret; | |
591 | ||
592 | ring->gpu_caches_dirty = false; | |
593 | return 0; | |
594 | } | |
595 | ||
596 | static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, | |
597 | struct list_head *vmas) | |
598 | { | |
599 | struct intel_engine_cs *ring = ringbuf->ring; | |
600 | struct i915_vma *vma; | |
601 | uint32_t flush_domains = 0; | |
602 | bool flush_chipset = false; | |
603 | int ret; | |
604 | ||
605 | list_for_each_entry(vma, vmas, exec_list) { | |
606 | struct drm_i915_gem_object *obj = vma->obj; | |
607 | ||
608 | ret = i915_gem_object_sync(obj, ring); | |
609 | if (ret) | |
610 | return ret; | |
611 | ||
612 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
613 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
614 | ||
615 | flush_domains |= obj->base.write_domain; | |
616 | } | |
617 | ||
618 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
619 | wmb(); | |
620 | ||
621 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
622 | * any residual writes from the previous batch. | |
623 | */ | |
624 | return logical_ring_invalidate_all_caches(ringbuf); | |
625 | } | |
626 | ||
73e4d07f OM |
627 | /** |
628 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
629 | * @dev: DRM device. | |
630 | * @file: DRM file. | |
631 | * @ring: Engine Command Streamer to submit to. | |
632 | * @ctx: Context to employ for this submission. | |
633 | * @args: execbuffer call arguments. | |
634 | * @vmas: list of vmas. | |
635 | * @batch_obj: the batchbuffer to submit. | |
636 | * @exec_start: batchbuffer start virtual address pointer. | |
637 | * @flags: translated execbuffer call flags. | |
638 | * | |
639 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
640 | * away the submission details of the execbuffer ioctl call. | |
641 | * | |
642 | * Return: non-zero if the submission fails. | |
643 | */ | |
454afebd OM |
644 | int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, |
645 | struct intel_engine_cs *ring, | |
646 | struct intel_context *ctx, | |
647 | struct drm_i915_gem_execbuffer2 *args, | |
648 | struct list_head *vmas, | |
649 | struct drm_i915_gem_object *batch_obj, | |
650 | u64 exec_start, u32 flags) | |
651 | { | |
ba8b7ccb OM |
652 | struct drm_i915_private *dev_priv = dev->dev_private; |
653 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
654 | int instp_mode; | |
655 | u32 instp_mask; | |
656 | int ret; | |
657 | ||
658 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
659 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
660 | switch (instp_mode) { | |
661 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
662 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
663 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
664 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
665 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
666 | return -EINVAL; | |
667 | } | |
668 | ||
669 | if (instp_mode != dev_priv->relative_constants_mode) { | |
670 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
671 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | /* The HW changed the meaning on this bit on gen6 */ | |
676 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
677 | } | |
678 | break; | |
679 | default: | |
680 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
681 | return -EINVAL; | |
682 | } | |
683 | ||
684 | if (args->num_cliprects != 0) { | |
685 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
686 | return -EINVAL; | |
687 | } else { | |
688 | if (args->DR4 == 0xffffffff) { | |
689 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
690 | args->DR4 = 0; | |
691 | } | |
692 | ||
693 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
694 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
695 | return -EINVAL; | |
696 | } | |
697 | } | |
698 | ||
699 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
700 | DRM_DEBUG("sol reset is gen7 only\n"); | |
701 | return -EINVAL; | |
702 | } | |
703 | ||
704 | ret = execlists_move_to_gpu(ringbuf, vmas); | |
705 | if (ret) | |
706 | return ret; | |
707 | ||
708 | if (ring == &dev_priv->ring[RCS] && | |
709 | instp_mode != dev_priv->relative_constants_mode) { | |
710 | ret = intel_logical_ring_begin(ringbuf, 4); | |
711 | if (ret) | |
712 | return ret; | |
713 | ||
714 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
715 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
716 | intel_logical_ring_emit(ringbuf, INSTPM); | |
717 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
718 | intel_logical_ring_advance(ringbuf); | |
719 | ||
720 | dev_priv->relative_constants_mode = instp_mode; | |
721 | } | |
722 | ||
723 | ret = ring->emit_bb_start(ringbuf, exec_start, flags); | |
724 | if (ret) | |
725 | return ret; | |
726 | ||
727 | i915_gem_execbuffer_move_to_active(vmas, ring); | |
728 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); | |
729 | ||
454afebd OM |
730 | return 0; |
731 | } | |
732 | ||
c86ee3a9 TD |
733 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
734 | { | |
735 | struct intel_ctx_submit_request *req, *tmp; | |
736 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
737 | unsigned long flags; | |
738 | struct list_head retired_list; | |
739 | ||
740 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
741 | if (list_empty(&ring->execlist_retired_req_list)) | |
742 | return; | |
743 | ||
744 | INIT_LIST_HEAD(&retired_list); | |
745 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
746 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); | |
747 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
748 | ||
749 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
750 | intel_runtime_pm_put(dev_priv); | |
751 | i915_gem_context_unreference(req->ctx); | |
752 | list_del(&req->execlist_link); | |
753 | kfree(req); | |
754 | } | |
755 | } | |
756 | ||
454afebd OM |
757 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
758 | { | |
9832b9da OM |
759 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
760 | int ret; | |
761 | ||
762 | if (!intel_ring_initialized(ring)) | |
763 | return; | |
764 | ||
765 | ret = intel_ring_idle(ring); | |
766 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
767 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
768 | ring->name, ret); | |
769 | ||
770 | /* TODO: Is this correct with Execlists enabled? */ | |
771 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
772 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
773 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
774 | return; | |
775 | } | |
776 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
777 | } |
778 | ||
48e29f55 OM |
779 | int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf) |
780 | { | |
781 | struct intel_engine_cs *ring = ringbuf->ring; | |
782 | int ret; | |
783 | ||
784 | if (!ring->gpu_caches_dirty) | |
785 | return 0; | |
786 | ||
787 | ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS); | |
788 | if (ret) | |
789 | return ret; | |
790 | ||
791 | ring->gpu_caches_dirty = false; | |
792 | return 0; | |
793 | } | |
794 | ||
73e4d07f OM |
795 | /** |
796 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
797 | * @ringbuf: Logical Ringbuffer to advance. | |
798 | * | |
799 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
800 | * really happens during submission is that the context and current tail will be placed | |
801 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
802 | * point, the tail *inside* the context is updated and the ELSP written to. | |
803 | */ | |
82e104cc OM |
804 | void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) |
805 | { | |
84b790f8 BW |
806 | struct intel_engine_cs *ring = ringbuf->ring; |
807 | struct intel_context *ctx = ringbuf->FIXME_lrc_ctx; | |
808 | ||
82e104cc OM |
809 | intel_logical_ring_advance(ringbuf); |
810 | ||
84b790f8 | 811 | if (intel_ring_stopped(ring)) |
82e104cc OM |
812 | return; |
813 | ||
acdd884a | 814 | execlists_context_queue(ring, ctx, ringbuf->tail); |
82e104cc OM |
815 | } |
816 | ||
48e29f55 OM |
817 | static int logical_ring_alloc_seqno(struct intel_engine_cs *ring, |
818 | struct intel_context *ctx) | |
82e104cc OM |
819 | { |
820 | if (ring->outstanding_lazy_seqno) | |
821 | return 0; | |
822 | ||
823 | if (ring->preallocated_lazy_request == NULL) { | |
824 | struct drm_i915_gem_request *request; | |
825 | ||
826 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
827 | if (request == NULL) | |
828 | return -ENOMEM; | |
829 | ||
48e29f55 OM |
830 | /* Hold a reference to the context this request belongs to |
831 | * (we will need it when the time comes to emit/retire the | |
832 | * request). | |
833 | */ | |
834 | request->ctx = ctx; | |
835 | i915_gem_context_reference(request->ctx); | |
836 | ||
82e104cc OM |
837 | ring->preallocated_lazy_request = request; |
838 | } | |
839 | ||
840 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); | |
841 | } | |
842 | ||
843 | static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, | |
844 | int bytes) | |
845 | { | |
846 | struct intel_engine_cs *ring = ringbuf->ring; | |
847 | struct drm_i915_gem_request *request; | |
848 | u32 seqno = 0; | |
849 | int ret; | |
850 | ||
851 | if (ringbuf->last_retired_head != -1) { | |
852 | ringbuf->head = ringbuf->last_retired_head; | |
853 | ringbuf->last_retired_head = -1; | |
854 | ||
855 | ringbuf->space = intel_ring_space(ringbuf); | |
856 | if (ringbuf->space >= bytes) | |
857 | return 0; | |
858 | } | |
859 | ||
860 | list_for_each_entry(request, &ring->request_list, list) { | |
861 | if (__intel_ring_space(request->tail, ringbuf->tail, | |
862 | ringbuf->size) >= bytes) { | |
863 | seqno = request->seqno; | |
864 | break; | |
865 | } | |
866 | } | |
867 | ||
868 | if (seqno == 0) | |
869 | return -ENOSPC; | |
870 | ||
871 | ret = i915_wait_seqno(ring, seqno); | |
872 | if (ret) | |
873 | return ret; | |
874 | ||
82e104cc OM |
875 | i915_gem_retire_requests_ring(ring); |
876 | ringbuf->head = ringbuf->last_retired_head; | |
877 | ringbuf->last_retired_head = -1; | |
878 | ||
879 | ringbuf->space = intel_ring_space(ringbuf); | |
880 | return 0; | |
881 | } | |
882 | ||
883 | static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, | |
884 | int bytes) | |
885 | { | |
886 | struct intel_engine_cs *ring = ringbuf->ring; | |
887 | struct drm_device *dev = ring->dev; | |
888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
889 | unsigned long end; | |
890 | int ret; | |
891 | ||
892 | ret = logical_ring_wait_request(ringbuf, bytes); | |
893 | if (ret != -ENOSPC) | |
894 | return ret; | |
895 | ||
896 | /* Force the context submission in case we have been skipping it */ | |
897 | intel_logical_ring_advance_and_submit(ringbuf); | |
898 | ||
899 | /* With GEM the hangcheck timer should kick us out of the loop, | |
900 | * leaving it early runs the risk of corrupting GEM state (due | |
901 | * to running on almost untested codepaths). But on resume | |
902 | * timers don't work yet, so prevent a complete hang in that | |
903 | * case by choosing an insanely large timeout. */ | |
904 | end = jiffies + 60 * HZ; | |
905 | ||
906 | do { | |
907 | ringbuf->head = I915_READ_HEAD(ring); | |
908 | ringbuf->space = intel_ring_space(ringbuf); | |
909 | if (ringbuf->space >= bytes) { | |
910 | ret = 0; | |
911 | break; | |
912 | } | |
913 | ||
914 | msleep(1); | |
915 | ||
916 | if (dev_priv->mm.interruptible && signal_pending(current)) { | |
917 | ret = -ERESTARTSYS; | |
918 | break; | |
919 | } | |
920 | ||
921 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
922 | dev_priv->mm.interruptible); | |
923 | if (ret) | |
924 | break; | |
925 | ||
926 | if (time_after(jiffies, end)) { | |
927 | ret = -EBUSY; | |
928 | break; | |
929 | } | |
930 | } while (1); | |
931 | ||
932 | return ret; | |
933 | } | |
934 | ||
935 | static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) | |
936 | { | |
937 | uint32_t __iomem *virt; | |
938 | int rem = ringbuf->size - ringbuf->tail; | |
939 | ||
940 | if (ringbuf->space < rem) { | |
941 | int ret = logical_ring_wait_for_space(ringbuf, rem); | |
942 | ||
943 | if (ret) | |
944 | return ret; | |
945 | } | |
946 | ||
947 | virt = ringbuf->virtual_start + ringbuf->tail; | |
948 | rem /= 4; | |
949 | while (rem--) | |
950 | iowrite32(MI_NOOP, virt++); | |
951 | ||
952 | ringbuf->tail = 0; | |
953 | ringbuf->space = intel_ring_space(ringbuf); | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) | |
959 | { | |
960 | int ret; | |
961 | ||
962 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { | |
963 | ret = logical_ring_wrap_buffer(ringbuf); | |
964 | if (unlikely(ret)) | |
965 | return ret; | |
966 | } | |
967 | ||
968 | if (unlikely(ringbuf->space < bytes)) { | |
969 | ret = logical_ring_wait_for_space(ringbuf, bytes); | |
970 | if (unlikely(ret)) | |
971 | return ret; | |
972 | } | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
73e4d07f OM |
977 | /** |
978 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
979 | * | |
980 | * @ringbuf: Logical ringbuffer. | |
981 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. | |
982 | * | |
983 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
984 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
985 | * and also preallocates a request (every workload submission is still mediated through | |
986 | * requests, same as it did with legacy ringbuffer submission). | |
987 | * | |
988 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
989 | */ | |
82e104cc OM |
990 | int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) |
991 | { | |
992 | struct intel_engine_cs *ring = ringbuf->ring; | |
993 | struct drm_device *dev = ring->dev; | |
994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
995 | int ret; | |
996 | ||
997 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
998 | dev_priv->mm.interruptible); | |
999 | if (ret) | |
1000 | return ret; | |
1001 | ||
1002 | ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); | |
1003 | if (ret) | |
1004 | return ret; | |
1005 | ||
1006 | /* Preallocate the olr before touching the ring */ | |
48e29f55 | 1007 | ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx); |
82e104cc OM |
1008 | if (ret) |
1009 | return ret; | |
1010 | ||
1011 | ringbuf->space -= num_dwords * sizeof(uint32_t); | |
1012 | return 0; | |
1013 | } | |
1014 | ||
771b9a53 MT |
1015 | static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, |
1016 | struct intel_context *ctx) | |
1017 | { | |
1018 | int ret, i; | |
1019 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
1020 | struct drm_device *dev = ring->dev; | |
1021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1022 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1023 | ||
1024 | if (WARN_ON(w->count == 0)) | |
1025 | return 0; | |
1026 | ||
1027 | ring->gpu_caches_dirty = true; | |
1028 | ret = logical_ring_flush_all_caches(ringbuf); | |
1029 | if (ret) | |
1030 | return ret; | |
1031 | ||
1032 | ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2); | |
1033 | if (ret) | |
1034 | return ret; | |
1035 | ||
1036 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1037 | for (i = 0; i < w->count; i++) { | |
1038 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1039 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1040 | } | |
1041 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1042 | ||
1043 | intel_logical_ring_advance(ringbuf); | |
1044 | ||
1045 | ring->gpu_caches_dirty = true; | |
1046 | ret = logical_ring_flush_all_caches(ringbuf); | |
1047 | if (ret) | |
1048 | return ret; | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
9b1136d5 OM |
1053 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1054 | { | |
1055 | struct drm_device *dev = ring->dev; | |
1056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1057 | ||
73d477f6 OM |
1058 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1059 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1060 | ||
9b1136d5 OM |
1061 | I915_WRITE(RING_MODE_GEN7(ring), |
1062 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1063 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1064 | POSTING_READ(RING_MODE_GEN7(ring)); | |
1065 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); | |
1066 | ||
1067 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1073 | { | |
1074 | struct drm_device *dev = ring->dev; | |
1075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1076 | int ret; | |
1077 | ||
1078 | ret = gen8_init_common_ring(ring); | |
1079 | if (ret) | |
1080 | return ret; | |
1081 | ||
1082 | /* We need to disable the AsyncFlip performance optimisations in order | |
1083 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1084 | * programmed to '1' on all products. | |
1085 | * | |
1086 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1087 | */ | |
1088 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1089 | ||
1090 | ret = intel_init_pipe_control(ring); | |
1091 | if (ret) | |
1092 | return ret; | |
1093 | ||
1094 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
1095 | ||
771b9a53 | 1096 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1097 | } |
1098 | ||
15648585 OM |
1099 | static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, |
1100 | u64 offset, unsigned flags) | |
1101 | { | |
15648585 OM |
1102 | bool ppgtt = !(flags & I915_DISPATCH_SECURE); |
1103 | int ret; | |
1104 | ||
1105 | ret = intel_logical_ring_begin(ringbuf, 4); | |
1106 | if (ret) | |
1107 | return ret; | |
1108 | ||
1109 | /* FIXME(BDW): Address space and security selectors. */ | |
1110 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); | |
1111 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); | |
1112 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1113 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1114 | intel_logical_ring_advance(ringbuf); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
73d477f6 OM |
1119 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1120 | { | |
1121 | struct drm_device *dev = ring->dev; | |
1122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1123 | unsigned long flags; | |
1124 | ||
7cd512f1 | 1125 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1126 | return false; |
1127 | ||
1128 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1129 | if (ring->irq_refcount++ == 0) { | |
1130 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1131 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1132 | } | |
1133 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1134 | ||
1135 | return true; | |
1136 | } | |
1137 | ||
1138 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1139 | { | |
1140 | struct drm_device *dev = ring->dev; | |
1141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1142 | unsigned long flags; | |
1143 | ||
1144 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1145 | if (--ring->irq_refcount == 0) { | |
1146 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1147 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1148 | } | |
1149 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1150 | } | |
1151 | ||
4712274c OM |
1152 | static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
1153 | u32 invalidate_domains, | |
1154 | u32 unused) | |
1155 | { | |
1156 | struct intel_engine_cs *ring = ringbuf->ring; | |
1157 | struct drm_device *dev = ring->dev; | |
1158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1159 | uint32_t cmd; | |
1160 | int ret; | |
1161 | ||
1162 | ret = intel_logical_ring_begin(ringbuf, 4); | |
1163 | if (ret) | |
1164 | return ret; | |
1165 | ||
1166 | cmd = MI_FLUSH_DW + 1; | |
1167 | ||
1168 | if (ring == &dev_priv->ring[VCS]) { | |
1169 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) | |
1170 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | | |
1171 | MI_FLUSH_DW_STORE_INDEX | | |
1172 | MI_FLUSH_DW_OP_STOREDW; | |
1173 | } else { | |
1174 | if (invalidate_domains & I915_GEM_DOMAIN_RENDER) | |
1175 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | | |
1176 | MI_FLUSH_DW_OP_STOREDW; | |
1177 | } | |
1178 | ||
1179 | intel_logical_ring_emit(ringbuf, cmd); | |
1180 | intel_logical_ring_emit(ringbuf, | |
1181 | I915_GEM_HWS_SCRATCH_ADDR | | |
1182 | MI_FLUSH_DW_USE_GTT); | |
1183 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1184 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1185 | intel_logical_ring_advance(ringbuf); | |
1186 | ||
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, | |
1191 | u32 invalidate_domains, | |
1192 | u32 flush_domains) | |
1193 | { | |
1194 | struct intel_engine_cs *ring = ringbuf->ring; | |
1195 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
1196 | u32 flags = 0; | |
1197 | int ret; | |
1198 | ||
1199 | flags |= PIPE_CONTROL_CS_STALL; | |
1200 | ||
1201 | if (flush_domains) { | |
1202 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1203 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1204 | } | |
1205 | ||
1206 | if (invalidate_domains) { | |
1207 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1208 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1209 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1210 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1211 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1212 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1213 | flags |= PIPE_CONTROL_QW_WRITE; | |
1214 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1215 | } | |
1216 | ||
1217 | ret = intel_logical_ring_begin(ringbuf, 6); | |
1218 | if (ret) | |
1219 | return ret; | |
1220 | ||
1221 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1222 | intel_logical_ring_emit(ringbuf, flags); | |
1223 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1224 | intel_logical_ring_emit(ringbuf, 0); | |
1225 | intel_logical_ring_emit(ringbuf, 0); | |
1226 | intel_logical_ring_emit(ringbuf, 0); | |
1227 | intel_logical_ring_advance(ringbuf); | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
e94e37ad OM |
1232 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1233 | { | |
1234 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1235 | } | |
1236 | ||
1237 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1238 | { | |
1239 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1240 | } | |
1241 | ||
4da46e1e OM |
1242 | static int gen8_emit_request(struct intel_ringbuffer *ringbuf) |
1243 | { | |
1244 | struct intel_engine_cs *ring = ringbuf->ring; | |
1245 | u32 cmd; | |
1246 | int ret; | |
1247 | ||
1248 | ret = intel_logical_ring_begin(ringbuf, 6); | |
1249 | if (ret) | |
1250 | return ret; | |
1251 | ||
1252 | cmd = MI_STORE_DWORD_IMM_GEN8; | |
1253 | cmd |= MI_GLOBAL_GTT; | |
1254 | ||
1255 | intel_logical_ring_emit(ringbuf, cmd); | |
1256 | intel_logical_ring_emit(ringbuf, | |
1257 | (ring->status_page.gfx_addr + | |
1258 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1259 | intel_logical_ring_emit(ringbuf, 0); | |
1260 | intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno); | |
1261 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); | |
1262 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1263 | intel_logical_ring_advance_and_submit(ringbuf); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
73e4d07f OM |
1268 | /** |
1269 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1270 | * | |
1271 | * @ring: Engine Command Streamer. | |
1272 | * | |
1273 | */ | |
454afebd OM |
1274 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1275 | { | |
6402c330 | 1276 | struct drm_i915_private *dev_priv; |
9832b9da | 1277 | |
48d82387 OM |
1278 | if (!intel_ring_initialized(ring)) |
1279 | return; | |
1280 | ||
6402c330 JH |
1281 | dev_priv = ring->dev->dev_private; |
1282 | ||
9832b9da OM |
1283 | intel_logical_ring_stop(ring); |
1284 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1285 | ring->preallocated_lazy_request = NULL; |
1286 | ring->outstanding_lazy_seqno = 0; | |
1287 | ||
1288 | if (ring->cleanup) | |
1289 | ring->cleanup(ring); | |
1290 | ||
1291 | i915_cmd_parser_fini_ring(ring); | |
1292 | ||
1293 | if (ring->status_page.obj) { | |
1294 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1295 | ring->status_page.obj = NULL; | |
1296 | } | |
454afebd OM |
1297 | } |
1298 | ||
1299 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1300 | { | |
48d82387 | 1301 | int ret; |
48d82387 OM |
1302 | |
1303 | /* Intentionally left blank. */ | |
1304 | ring->buffer = NULL; | |
1305 | ||
1306 | ring->dev = dev; | |
1307 | INIT_LIST_HEAD(&ring->active_list); | |
1308 | INIT_LIST_HEAD(&ring->request_list); | |
1309 | init_waitqueue_head(&ring->irq_queue); | |
1310 | ||
acdd884a | 1311 | INIT_LIST_HEAD(&ring->execlist_queue); |
c86ee3a9 | 1312 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
acdd884a | 1313 | spin_lock_init(&ring->execlist_lock); |
e981e7b1 | 1314 | ring->next_context_status_buffer = 0; |
acdd884a | 1315 | |
48d82387 OM |
1316 | ret = i915_cmd_parser_init_ring(ring); |
1317 | if (ret) | |
1318 | return ret; | |
1319 | ||
1320 | if (ring->init) { | |
1321 | ret = ring->init(ring); | |
1322 | if (ret) | |
1323 | return ret; | |
1324 | } | |
1325 | ||
564ddb2f OM |
1326 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
1327 | ||
1328 | return ret; | |
454afebd OM |
1329 | } |
1330 | ||
1331 | static int logical_render_ring_init(struct drm_device *dev) | |
1332 | { | |
1333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1334 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
1335 | ||
1336 | ring->name = "render ring"; | |
1337 | ring->id = RCS; | |
1338 | ring->mmio_base = RENDER_RING_BASE; | |
1339 | ring->irq_enable_mask = | |
1340 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1341 | ring->irq_keep_mask = |
1342 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1343 | if (HAS_L3_DPF(dev)) | |
1344 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1345 | |
9b1136d5 | 1346 | ring->init = gen8_init_render_ring; |
771b9a53 | 1347 | ring->init_context = intel_logical_ring_workarounds_emit; |
9b1136d5 | 1348 | ring->cleanup = intel_fini_pipe_control; |
e94e37ad OM |
1349 | ring->get_seqno = gen8_get_seqno; |
1350 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1351 | ring->emit_request = gen8_emit_request; |
4712274c | 1352 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1353 | ring->irq_get = gen8_logical_ring_get_irq; |
1354 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1355 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1356 | |
454afebd OM |
1357 | return logical_ring_init(dev, ring); |
1358 | } | |
1359 | ||
1360 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1361 | { | |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1363 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1364 | ||
1365 | ring->name = "bsd ring"; | |
1366 | ring->id = VCS; | |
1367 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1368 | ring->irq_enable_mask = | |
1369 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1370 | ring->irq_keep_mask = |
1371 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1372 | |
9b1136d5 | 1373 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1374 | ring->get_seqno = gen8_get_seqno; |
1375 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1376 | ring->emit_request = gen8_emit_request; |
4712274c | 1377 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1378 | ring->irq_get = gen8_logical_ring_get_irq; |
1379 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1380 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1381 | |
454afebd OM |
1382 | return logical_ring_init(dev, ring); |
1383 | } | |
1384 | ||
1385 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
1386 | { | |
1387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1388 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
1389 | ||
1390 | ring->name = "bds2 ring"; | |
1391 | ring->id = VCS2; | |
1392 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
1393 | ring->irq_enable_mask = | |
1394 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
1395 | ring->irq_keep_mask = |
1396 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 1397 | |
9b1136d5 | 1398 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1399 | ring->get_seqno = gen8_get_seqno; |
1400 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1401 | ring->emit_request = gen8_emit_request; |
4712274c | 1402 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1403 | ring->irq_get = gen8_logical_ring_get_irq; |
1404 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1405 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1406 | |
454afebd OM |
1407 | return logical_ring_init(dev, ring); |
1408 | } | |
1409 | ||
1410 | static int logical_blt_ring_init(struct drm_device *dev) | |
1411 | { | |
1412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1413 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
1414 | ||
1415 | ring->name = "blitter ring"; | |
1416 | ring->id = BCS; | |
1417 | ring->mmio_base = BLT_RING_BASE; | |
1418 | ring->irq_enable_mask = | |
1419 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
1420 | ring->irq_keep_mask = |
1421 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 1422 | |
9b1136d5 | 1423 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1424 | ring->get_seqno = gen8_get_seqno; |
1425 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1426 | ring->emit_request = gen8_emit_request; |
4712274c | 1427 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1428 | ring->irq_get = gen8_logical_ring_get_irq; |
1429 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1430 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1431 | |
454afebd OM |
1432 | return logical_ring_init(dev, ring); |
1433 | } | |
1434 | ||
1435 | static int logical_vebox_ring_init(struct drm_device *dev) | |
1436 | { | |
1437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1438 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
1439 | ||
1440 | ring->name = "video enhancement ring"; | |
1441 | ring->id = VECS; | |
1442 | ring->mmio_base = VEBOX_RING_BASE; | |
1443 | ring->irq_enable_mask = | |
1444 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
1445 | ring->irq_keep_mask = |
1446 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 1447 | |
9b1136d5 | 1448 | ring->init = gen8_init_common_ring; |
e94e37ad OM |
1449 | ring->get_seqno = gen8_get_seqno; |
1450 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1451 | ring->emit_request = gen8_emit_request; |
4712274c | 1452 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1453 | ring->irq_get = gen8_logical_ring_get_irq; |
1454 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1455 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1456 | |
454afebd OM |
1457 | return logical_ring_init(dev, ring); |
1458 | } | |
1459 | ||
73e4d07f OM |
1460 | /** |
1461 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
1462 | * @dev: DRM device. | |
1463 | * | |
1464 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
1465 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
1466 | * those engines that are present in the hardware. | |
1467 | * | |
1468 | * Return: non-zero if the initialization failed. | |
1469 | */ | |
454afebd OM |
1470 | int intel_logical_rings_init(struct drm_device *dev) |
1471 | { | |
1472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1473 | int ret; | |
1474 | ||
1475 | ret = logical_render_ring_init(dev); | |
1476 | if (ret) | |
1477 | return ret; | |
1478 | ||
1479 | if (HAS_BSD(dev)) { | |
1480 | ret = logical_bsd_ring_init(dev); | |
1481 | if (ret) | |
1482 | goto cleanup_render_ring; | |
1483 | } | |
1484 | ||
1485 | if (HAS_BLT(dev)) { | |
1486 | ret = logical_blt_ring_init(dev); | |
1487 | if (ret) | |
1488 | goto cleanup_bsd_ring; | |
1489 | } | |
1490 | ||
1491 | if (HAS_VEBOX(dev)) { | |
1492 | ret = logical_vebox_ring_init(dev); | |
1493 | if (ret) | |
1494 | goto cleanup_blt_ring; | |
1495 | } | |
1496 | ||
1497 | if (HAS_BSD2(dev)) { | |
1498 | ret = logical_bsd2_ring_init(dev); | |
1499 | if (ret) | |
1500 | goto cleanup_vebox_ring; | |
1501 | } | |
1502 | ||
1503 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
1504 | if (ret) | |
1505 | goto cleanup_bsd2_ring; | |
1506 | ||
1507 | return 0; | |
1508 | ||
1509 | cleanup_bsd2_ring: | |
1510 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
1511 | cleanup_vebox_ring: | |
1512 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
1513 | cleanup_blt_ring: | |
1514 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
1515 | cleanup_bsd_ring: | |
1516 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
1517 | cleanup_render_ring: | |
1518 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
1519 | ||
1520 | return ret; | |
1521 | } | |
1522 | ||
564ddb2f OM |
1523 | int intel_lr_context_render_state_init(struct intel_engine_cs *ring, |
1524 | struct intel_context *ctx) | |
1525 | { | |
1526 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
1527 | struct render_state so; | |
1528 | struct drm_i915_file_private *file_priv = ctx->file_priv; | |
1529 | struct drm_file *file = file_priv ? file_priv->file : NULL; | |
1530 | int ret; | |
1531 | ||
1532 | ret = i915_gem_render_state_prepare(ring, &so); | |
1533 | if (ret) | |
1534 | return ret; | |
1535 | ||
1536 | if (so.rodata == NULL) | |
1537 | return 0; | |
1538 | ||
1539 | ret = ring->emit_bb_start(ringbuf, | |
1540 | so.ggtt_offset, | |
1541 | I915_DISPATCH_SECURE); | |
1542 | if (ret) | |
1543 | goto out; | |
1544 | ||
1545 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); | |
1546 | ||
1547 | ret = __i915_add_request(ring, file, so.obj, NULL); | |
1548 | /* intel_logical_ring_add_request moves object to inactive if it | |
1549 | * fails */ | |
1550 | out: | |
1551 | i915_gem_render_state_fini(&so); | |
1552 | return ret; | |
1553 | } | |
1554 | ||
8670d6f9 OM |
1555 | static int |
1556 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
1557 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
1558 | { | |
2d965536 TD |
1559 | struct drm_device *dev = ring->dev; |
1560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8670d6f9 | 1561 | struct drm_i915_gem_object *ring_obj = ringbuf->obj; |
ae6c4806 | 1562 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
1563 | struct page *page; |
1564 | uint32_t *reg_state; | |
1565 | int ret; | |
1566 | ||
2d965536 TD |
1567 | if (!ppgtt) |
1568 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1569 | ||
8670d6f9 OM |
1570 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
1571 | if (ret) { | |
1572 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1573 | return ret; | |
1574 | } | |
1575 | ||
1576 | ret = i915_gem_object_get_pages(ctx_obj); | |
1577 | if (ret) { | |
1578 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
1579 | return ret; | |
1580 | } | |
1581 | ||
1582 | i915_gem_object_pin_pages(ctx_obj); | |
1583 | ||
1584 | /* The second page of the context object contains some fields which must | |
1585 | * be set up prior to the first execution. */ | |
1586 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1587 | reg_state = kmap_atomic(page); | |
1588 | ||
1589 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1590 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1591 | * only for the first context restore: on a subsequent save, the GPU will | |
1592 | * recreate this batchbuffer with new values (including all the missing | |
1593 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
1594 | if (ring->id == RCS) | |
1595 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
1596 | else | |
1597 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
1598 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
1599 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
1600 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
1601 | _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); | |
1602 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); | |
1603 | reg_state[CTX_RING_HEAD+1] = 0; | |
1604 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
1605 | reg_state[CTX_RING_TAIL+1] = 0; | |
1606 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
1607 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); | |
1608 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); | |
1609 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
1610 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
1611 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
1612 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
1613 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
1614 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
1615 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
1616 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
1617 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
1618 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
1619 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
1620 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
1621 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
1622 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
1623 | if (ring->id == RCS) { | |
1624 | /* TODO: according to BSpec, the register state context | |
1625 | * for CHV does not have these. OTOH, these registers do | |
1626 | * exist in CHV. I'm waiting for a clarification */ | |
1627 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; | |
1628 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
1629 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
1630 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
1631 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
1632 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
1633 | } | |
1634 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
1635 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
1636 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
1637 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
1638 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
1639 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
1640 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
1641 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
1642 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
1643 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
1644 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
1645 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
1646 | reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); | |
1647 | reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); | |
1648 | reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); | |
1649 | reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); | |
1650 | reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); | |
1651 | reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); | |
1652 | reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); | |
1653 | reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); | |
1654 | if (ring->id == RCS) { | |
1655 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
1656 | reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; | |
1657 | reg_state[CTX_R_PWR_CLK_STATE+1] = 0; | |
1658 | } | |
1659 | ||
1660 | kunmap_atomic(reg_state); | |
1661 | ||
1662 | ctx_obj->dirty = 1; | |
1663 | set_page_dirty(page); | |
1664 | i915_gem_object_unpin_pages(ctx_obj); | |
1665 | ||
1666 | return 0; | |
1667 | } | |
1668 | ||
73e4d07f OM |
1669 | /** |
1670 | * intel_lr_context_free() - free the LRC specific bits of a context | |
1671 | * @ctx: the LR context to free. | |
1672 | * | |
1673 | * The real context freeing is done in i915_gem_context_free: this only | |
1674 | * takes care of the bits that are LRC related: the per-engine backing | |
1675 | * objects and the logical ringbuffer. | |
1676 | */ | |
ede7d42b OM |
1677 | void intel_lr_context_free(struct intel_context *ctx) |
1678 | { | |
8c857917 OM |
1679 | int i; |
1680 | ||
1681 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1682 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f OM |
1683 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
1684 | ||
8c857917 | 1685 | if (ctx_obj) { |
84c2377f OM |
1686 | intel_destroy_ringbuffer_obj(ringbuf); |
1687 | kfree(ringbuf); | |
8c857917 OM |
1688 | i915_gem_object_ggtt_unpin(ctx_obj); |
1689 | drm_gem_object_unreference(&ctx_obj->base); | |
1690 | } | |
1691 | } | |
1692 | } | |
1693 | ||
1694 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
1695 | { | |
1696 | int ret = 0; | |
1697 | ||
468c6816 | 1698 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
1699 | |
1700 | switch (ring->id) { | |
1701 | case RCS: | |
468c6816 MN |
1702 | if (INTEL_INFO(ring->dev)->gen >= 9) |
1703 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
1704 | else | |
1705 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
1706 | break; |
1707 | case VCS: | |
1708 | case BCS: | |
1709 | case VECS: | |
1710 | case VCS2: | |
1711 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
1712 | break; | |
1713 | } | |
1714 | ||
1715 | return ret; | |
ede7d42b OM |
1716 | } |
1717 | ||
70b0ea86 | 1718 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1df06b75 TD |
1719 | struct drm_i915_gem_object *default_ctx_obj) |
1720 | { | |
1721 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1722 | ||
1723 | /* The status page is offset 0 from the default context object | |
1724 | * in LRC mode. */ | |
1725 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); | |
1726 | ring->status_page.page_addr = | |
1727 | kmap(sg_page(default_ctx_obj->pages->sgl)); | |
1df06b75 TD |
1728 | ring->status_page.obj = default_ctx_obj; |
1729 | ||
1730 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
1731 | (u32)ring->status_page.gfx_addr); | |
1732 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1df06b75 TD |
1733 | } |
1734 | ||
73e4d07f OM |
1735 | /** |
1736 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context | |
1737 | * @ctx: LR context to create. | |
1738 | * @ring: engine to be used with the context. | |
1739 | * | |
1740 | * This function can be called more than once, with different engines, if we plan | |
1741 | * to use the context with them. The context backing objects and the ringbuffers | |
1742 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
1743 | * the creation is a deferred call: it's better to make sure first that we need to use | |
1744 | * a given ring with the context. | |
1745 | * | |
32197aab | 1746 | * Return: non-zero on error. |
73e4d07f | 1747 | */ |
ede7d42b OM |
1748 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
1749 | struct intel_engine_cs *ring) | |
1750 | { | |
8c857917 OM |
1751 | struct drm_device *dev = ring->dev; |
1752 | struct drm_i915_gem_object *ctx_obj; | |
1753 | uint32_t context_size; | |
84c2377f | 1754 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
1755 | int ret; |
1756 | ||
ede7d42b | 1757 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
48d82387 OM |
1758 | if (ctx->engine[ring->id].state) |
1759 | return 0; | |
ede7d42b | 1760 | |
8c857917 OM |
1761 | context_size = round_up(get_lr_context_size(ring), 4096); |
1762 | ||
1763 | ctx_obj = i915_gem_alloc_context_obj(dev, context_size); | |
1764 | if (IS_ERR(ctx_obj)) { | |
1765 | ret = PTR_ERR(ctx_obj); | |
1766 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); | |
1767 | return ret; | |
1768 | } | |
1769 | ||
1770 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
1771 | if (ret) { | |
1772 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); | |
1773 | drm_gem_object_unreference(&ctx_obj->base); | |
1774 | return ret; | |
1775 | } | |
1776 | ||
84c2377f OM |
1777 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
1778 | if (!ringbuf) { | |
1779 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
1780 | ring->name); | |
1781 | i915_gem_object_ggtt_unpin(ctx_obj); | |
1782 | drm_gem_object_unreference(&ctx_obj->base); | |
1783 | ret = -ENOMEM; | |
1784 | return ret; | |
1785 | } | |
1786 | ||
0c7dd53b | 1787 | ringbuf->ring = ring; |
582d67f0 OM |
1788 | ringbuf->FIXME_lrc_ctx = ctx; |
1789 | ||
84c2377f OM |
1790 | ringbuf->size = 32 * PAGE_SIZE; |
1791 | ringbuf->effective_size = ringbuf->size; | |
1792 | ringbuf->head = 0; | |
1793 | ringbuf->tail = 0; | |
1794 | ringbuf->space = ringbuf->size; | |
1795 | ringbuf->last_retired_head = -1; | |
1796 | ||
1797 | /* TODO: For now we put this in the mappable region so that we can reuse | |
1798 | * the existing ringbuffer code which ioremaps it. When we start | |
1799 | * creating many contexts, this will no longer work and we must switch | |
1800 | * to a kmapish interface. | |
1801 | */ | |
1802 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
1803 | if (ret) { | |
1804 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", | |
1805 | ring->name, ret); | |
8670d6f9 OM |
1806 | goto error; |
1807 | } | |
1808 | ||
1809 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
1810 | if (ret) { | |
1811 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
1812 | intel_destroy_ringbuffer_obj(ringbuf); | |
1813 | goto error; | |
84c2377f OM |
1814 | } |
1815 | ||
1816 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 1817 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 1818 | |
70b0ea86 DV |
1819 | if (ctx == ring->default_context) |
1820 | lrc_setup_hardware_status_page(ring, ctx_obj); | |
564ddb2f OM |
1821 | |
1822 | if (ring->id == RCS && !ctx->rcs_initialized) { | |
771b9a53 MT |
1823 | if (ring->init_context) { |
1824 | ret = ring->init_context(ring, ctx); | |
1825 | if (ret) | |
1826 | DRM_ERROR("ring init context: %d\n", ret); | |
1827 | } | |
1828 | ||
564ddb2f OM |
1829 | ret = intel_lr_context_render_state_init(ring, ctx); |
1830 | if (ret) { | |
1831 | DRM_ERROR("Init render state failed: %d\n", ret); | |
1832 | ctx->engine[ring->id].ringbuf = NULL; | |
1833 | ctx->engine[ring->id].state = NULL; | |
1834 | intel_destroy_ringbuffer_obj(ringbuf); | |
1835 | goto error; | |
1836 | } | |
1837 | ctx->rcs_initialized = true; | |
1838 | } | |
1839 | ||
ede7d42b | 1840 | return 0; |
8670d6f9 OM |
1841 | |
1842 | error: | |
1843 | kfree(ringbuf); | |
1844 | i915_gem_object_ggtt_unpin(ctx_obj); | |
1845 | drm_gem_object_unreference(&ctx_obj->base); | |
1846 | return ret; | |
ede7d42b | 1847 | } |