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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 158 | |
70c2a24d CW |
159 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
160 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
161 | GEN8_CTX_STATUS_PREEMPTED | \ | |
162 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
163 | ||
8670d6f9 OM |
164 | #define CTX_LRI_HEADER_0 0x01 |
165 | #define CTX_CONTEXT_CONTROL 0x02 | |
166 | #define CTX_RING_HEAD 0x04 | |
167 | #define CTX_RING_TAIL 0x06 | |
168 | #define CTX_RING_BUFFER_START 0x08 | |
169 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
170 | #define CTX_BB_HEAD_U 0x0c | |
171 | #define CTX_BB_HEAD_L 0x0e | |
172 | #define CTX_BB_STATE 0x10 | |
173 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
174 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
175 | #define CTX_SECOND_BB_STATE 0x16 | |
176 | #define CTX_BB_PER_CTX_PTR 0x18 | |
177 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
178 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
179 | #define CTX_LRI_HEADER_1 0x21 | |
180 | #define CTX_CTX_TIMESTAMP 0x22 | |
181 | #define CTX_PDP3_UDW 0x24 | |
182 | #define CTX_PDP3_LDW 0x26 | |
183 | #define CTX_PDP2_UDW 0x28 | |
184 | #define CTX_PDP2_LDW 0x2a | |
185 | #define CTX_PDP1_UDW 0x2c | |
186 | #define CTX_PDP1_LDW 0x2e | |
187 | #define CTX_PDP0_UDW 0x30 | |
188 | #define CTX_PDP0_LDW 0x32 | |
189 | #define CTX_LRI_HEADER_2 0x41 | |
190 | #define CTX_R_PWR_CLK_STATE 0x42 | |
191 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
192 | ||
84b790f8 BW |
193 | #define GEN8_CTX_VALID (1<<0) |
194 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
195 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
196 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
197 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 198 | |
0d925ea0 | 199 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 200 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
201 | (reg_state)[(pos)+1] = (val); \ |
202 | } while (0) | |
203 | ||
204 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 205 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
206 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
207 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 208 | } while (0) |
e5815a2e | 209 | |
9244a817 | 210 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
211 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
212 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 213 | } while (0) |
2dba3239 | 214 | |
84b790f8 BW |
215 | enum { |
216 | FAULT_AND_HANG = 0, | |
217 | FAULT_AND_HALT, /* Debug only */ | |
218 | FAULT_AND_STREAM, | |
219 | FAULT_AND_CONTINUE /* Unsupported */ | |
220 | }; | |
221 | #define GEN8_CTX_ID_SHIFT 32 | |
7069b144 | 222 | #define GEN8_CTX_ID_WIDTH 21 |
71562919 MT |
223 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
224 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 225 | |
0e93cdd4 CW |
226 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
227 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
228 | ||
a3aabe86 CW |
229 | #define WA_TAIL_DWORDS 2 |
230 | ||
e2efd130 | 231 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 232 | struct intel_engine_cs *engine); |
a3aabe86 CW |
233 | static void execlists_init_reg_state(u32 *reg_state, |
234 | struct i915_gem_context *ctx, | |
235 | struct intel_engine_cs *engine, | |
236 | struct intel_ring *ring); | |
7ba717cf | 237 | |
73e4d07f OM |
238 | /** |
239 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 240 | * @dev_priv: i915 device private |
73e4d07f OM |
241 | * @enable_execlists: value of i915.enable_execlists module parameter. |
242 | * | |
243 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 244 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
245 | * |
246 | * Return: 1 if Execlists is supported and has to be enabled. | |
247 | */ | |
c033666a | 248 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 249 | { |
a0bd6c31 ZL |
250 | /* On platforms with execlist available, vGPU will only |
251 | * support execlist mode, no ring buffer mode. | |
252 | */ | |
c033666a | 253 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
254 | return 1; |
255 | ||
c033666a | 256 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
257 | return 1; |
258 | ||
127f1003 OM |
259 | if (enable_execlists == 0) |
260 | return 0; | |
261 | ||
5a21b665 DV |
262 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
263 | USES_PPGTT(dev_priv) && | |
264 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
265 | return 1; |
266 | ||
267 | return 0; | |
268 | } | |
ede7d42b | 269 | |
ca82580c | 270 | static void |
0bc40be8 | 271 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 272 | { |
c033666a | 273 | struct drm_i915_private *dev_priv = engine->i915; |
ca82580c | 274 | |
70c2a24d | 275 | engine->disable_lite_restore_wa = |
a117f378 | 276 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && |
70c2a24d | 277 | (engine->id == VCS || engine->id == VCS2); |
ca82580c | 278 | |
0bc40be8 | 279 | engine->ctx_desc_template = GEN8_CTX_VALID; |
c033666a | 280 | if (IS_GEN8(dev_priv)) |
0bc40be8 TU |
281 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
282 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
283 | |
284 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
285 | * signalling between Command Streamers */ | |
286 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
287 | ||
288 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
289 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
290 | if (engine->disable_lite_restore_wa) |
291 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
292 | } |
293 | ||
73e4d07f | 294 | /** |
ca82580c TU |
295 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
296 | * descriptor for a pinned context | |
ca82580c | 297 | * @ctx: Context to work on |
9021ad03 | 298 | * @engine: Engine the descriptor will be used with |
73e4d07f | 299 | * |
ca82580c TU |
300 | * The context descriptor encodes various attributes of a context, |
301 | * including its GTT address and some flags. Because it's fairly | |
302 | * expensive to calculate, we'll just do it once and cache the result, | |
303 | * which remains valid until the context is unpinned. | |
304 | * | |
6e5248b5 DV |
305 | * This is what a descriptor looks like, from LSB to MSB:: |
306 | * | |
307 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) | |
308 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context | |
309 | * bits 32-52: ctx ID, a globally unique tag | |
310 | * bits 53-54: mbz, reserved for use by hardware | |
311 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 312 | */ |
ca82580c | 313 | static void |
e2efd130 | 314 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 315 | struct intel_engine_cs *engine) |
84b790f8 | 316 | { |
9021ad03 | 317 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 318 | u64 desc; |
84b790f8 | 319 | |
7069b144 | 320 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 321 | |
c01fc532 ZW |
322 | desc = ctx->desc_template; /* bits 3-4 */ |
323 | desc |= engine->ctx_desc_template; /* bits 0-11 */ | |
bde13ebd | 324 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 325 | /* bits 12-31 */ |
7069b144 | 326 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 327 | |
9021ad03 | 328 | ce->lrc_desc = desc; |
5af05fef MT |
329 | } |
330 | ||
e2efd130 | 331 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 332 | struct intel_engine_cs *engine) |
84b790f8 | 333 | { |
0bc40be8 | 334 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 335 | } |
203a571b | 336 | |
bbd6c47e CW |
337 | static inline void |
338 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
339 | unsigned long status) | |
84b790f8 | 340 | { |
bbd6c47e CW |
341 | /* |
342 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
343 | * The compiler should eliminate this function as dead-code. | |
344 | */ | |
345 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
346 | return; | |
6daccb0b | 347 | |
bbd6c47e | 348 | atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq); |
84b790f8 BW |
349 | } |
350 | ||
c6a2ac71 TU |
351 | static void |
352 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
353 | { | |
354 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
355 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
356 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
357 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
358 | } | |
359 | ||
70c2a24d | 360 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 361 | { |
70c2a24d | 362 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
05d9824b | 363 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
70c2a24d | 364 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 365 | |
caddfe71 | 366 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 367 | |
c6a2ac71 TU |
368 | /* True 32b PPGTT with dynamic page allocation: update PDP |
369 | * registers and point the unallocated PDPs to scratch page. | |
370 | * PML4 is allocated during ppgtt init, so this is not needed | |
371 | * in 48-bit mode. | |
372 | */ | |
373 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
374 | execlists_update_context_pdps(ppgtt, reg_state); | |
70c2a24d CW |
375 | |
376 | return ce->lrc_desc; | |
ae1250b9 OM |
377 | } |
378 | ||
70c2a24d | 379 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 380 | { |
70c2a24d CW |
381 | struct drm_i915_private *dev_priv = engine->i915; |
382 | struct execlist_port *port = engine->execlist_port; | |
bbd6c47e CW |
383 | u32 __iomem *elsp = |
384 | dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine)); | |
385 | u64 desc[2]; | |
386 | ||
70c2a24d CW |
387 | if (!port[0].count) |
388 | execlists_context_status_change(port[0].request, | |
389 | INTEL_CONTEXT_SCHEDULE_IN); | |
390 | desc[0] = execlists_update_context(port[0].request); | |
391 | engine->preempt_wa = port[0].count++; /* bdw only? fixed on skl? */ | |
392 | ||
393 | if (port[1].request) { | |
394 | GEM_BUG_ON(port[1].count); | |
395 | execlists_context_status_change(port[1].request, | |
396 | INTEL_CONTEXT_SCHEDULE_IN); | |
397 | desc[1] = execlists_update_context(port[1].request); | |
398 | port[1].count = 1; | |
bbd6c47e CW |
399 | } else { |
400 | desc[1] = 0; | |
401 | } | |
70c2a24d | 402 | GEM_BUG_ON(desc[0] == desc[1]); |
bbd6c47e CW |
403 | |
404 | /* You must always write both descriptors in the order below. */ | |
405 | writel(upper_32_bits(desc[1]), elsp); | |
406 | writel(lower_32_bits(desc[1]), elsp); | |
407 | ||
408 | writel(upper_32_bits(desc[0]), elsp); | |
409 | /* The context is automatically loaded after the following */ | |
410 | writel(lower_32_bits(desc[0]), elsp); | |
411 | } | |
412 | ||
70c2a24d | 413 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 414 | { |
70c2a24d CW |
415 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
416 | ctx->execlists_force_single_submission); | |
417 | } | |
84b790f8 | 418 | |
70c2a24d CW |
419 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
420 | const struct i915_gem_context *next) | |
421 | { | |
422 | if (prev != next) | |
423 | return false; | |
26720ab9 | 424 | |
70c2a24d CW |
425 | if (ctx_single_port_submission(prev)) |
426 | return false; | |
26720ab9 | 427 | |
70c2a24d | 428 | return true; |
84b790f8 BW |
429 | } |
430 | ||
70c2a24d | 431 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 432 | { |
20311bd3 | 433 | struct drm_i915_gem_request *last; |
70c2a24d | 434 | struct execlist_port *port = engine->execlist_port; |
d55ac5bf | 435 | unsigned long flags; |
20311bd3 | 436 | struct rb_node *rb; |
70c2a24d CW |
437 | bool submit = false; |
438 | ||
439 | last = port->request; | |
440 | if (last) | |
441 | /* WaIdleLiteRestore:bdw,skl | |
442 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 443 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
444 | * for where we prepare the padding after the end of the |
445 | * request. | |
446 | */ | |
447 | last->tail = last->wa_tail; | |
e981e7b1 | 448 | |
70c2a24d | 449 | GEM_BUG_ON(port[1].request); |
acdd884a | 450 | |
70c2a24d CW |
451 | /* Hardware submission is through 2 ports. Conceptually each port |
452 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
453 | * static for a context, and unique to each, so we only execute | |
454 | * requests belonging to a single context from each ring. RING_HEAD | |
455 | * is maintained by the CS in the context image, it marks the place | |
456 | * where it got up to last time, and through RING_TAIL we tell the CS | |
457 | * where we want to execute up to this time. | |
458 | * | |
459 | * In this list the requests are in order of execution. Consecutive | |
460 | * requests from the same context are adjacent in the ringbuffer. We | |
461 | * can combine these requests into a single RING_TAIL update: | |
462 | * | |
463 | * RING_HEAD...req1...req2 | |
464 | * ^- RING_TAIL | |
465 | * since to execute req2 the CS must first execute req1. | |
466 | * | |
467 | * Our goal then is to point each port to the end of a consecutive | |
468 | * sequence of requests as being the most optimal (fewest wake ups | |
469 | * and context switches) submission. | |
779949f4 | 470 | */ |
acdd884a | 471 | |
d55ac5bf | 472 | spin_lock_irqsave(&engine->timeline->lock, flags); |
20311bd3 CW |
473 | rb = engine->execlist_first; |
474 | while (rb) { | |
475 | struct drm_i915_gem_request *cursor = | |
476 | rb_entry(rb, typeof(*cursor), priotree.node); | |
477 | ||
70c2a24d CW |
478 | /* Can we combine this request with the current port? It has to |
479 | * be the same context/ringbuffer and not have any exceptions | |
480 | * (e.g. GVT saying never to combine contexts). | |
c6a2ac71 | 481 | * |
70c2a24d CW |
482 | * If we can combine the requests, we can execute both by |
483 | * updating the RING_TAIL to point to the end of the second | |
484 | * request, and so we never need to tell the hardware about | |
485 | * the first. | |
53292cdb | 486 | */ |
70c2a24d CW |
487 | if (last && !can_merge_ctx(cursor->ctx, last->ctx)) { |
488 | /* If we are on the second port and cannot combine | |
489 | * this request with the last, then we are done. | |
490 | */ | |
491 | if (port != engine->execlist_port) | |
492 | break; | |
493 | ||
494 | /* If GVT overrides us we only ever submit port[0], | |
495 | * leaving port[1] empty. Note that we also have | |
496 | * to be careful that we don't queue the same | |
497 | * context (even though a different request) to | |
498 | * the second port. | |
499 | */ | |
d7ab992c MH |
500 | if (ctx_single_port_submission(last->ctx) || |
501 | ctx_single_port_submission(cursor->ctx)) | |
70c2a24d CW |
502 | break; |
503 | ||
504 | GEM_BUG_ON(last->ctx == cursor->ctx); | |
505 | ||
506 | i915_gem_request_assign(&port->request, last); | |
507 | port++; | |
508 | } | |
d55ac5bf | 509 | |
20311bd3 CW |
510 | rb = rb_next(rb); |
511 | rb_erase(&cursor->priotree.node, &engine->execlist_queue); | |
512 | RB_CLEAR_NODE(&cursor->priotree.node); | |
513 | cursor->priotree.priority = INT_MAX; | |
514 | ||
d55ac5bf | 515 | __i915_gem_request_submit(cursor); |
70c2a24d CW |
516 | last = cursor; |
517 | submit = true; | |
518 | } | |
519 | if (submit) { | |
70c2a24d | 520 | i915_gem_request_assign(&port->request, last); |
20311bd3 | 521 | engine->execlist_first = rb; |
53292cdb | 522 | } |
d55ac5bf | 523 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
53292cdb | 524 | |
70c2a24d CW |
525 | if (submit) |
526 | execlists_submit_ports(engine); | |
acdd884a MT |
527 | } |
528 | ||
70c2a24d | 529 | static bool execlists_elsp_idle(struct intel_engine_cs *engine) |
e981e7b1 | 530 | { |
70c2a24d | 531 | return !engine->execlist_port[0].request; |
e981e7b1 TD |
532 | } |
533 | ||
0cb5670b ID |
534 | /** |
535 | * intel_execlists_idle() - Determine if all engine submission ports are idle | |
536 | * @dev_priv: i915 device private | |
537 | * | |
538 | * Return true if there are no requests pending on any of the submission ports | |
539 | * of any engines. | |
540 | */ | |
541 | bool intel_execlists_idle(struct drm_i915_private *dev_priv) | |
542 | { | |
543 | struct intel_engine_cs *engine; | |
544 | enum intel_engine_id id; | |
545 | ||
546 | if (!i915.enable_execlists) | |
547 | return true; | |
548 | ||
549 | for_each_engine(engine, dev_priv, id) | |
550 | if (!execlists_elsp_idle(engine)) | |
551 | return false; | |
552 | ||
553 | return true; | |
554 | } | |
555 | ||
70c2a24d | 556 | static bool execlists_elsp_ready(struct intel_engine_cs *engine) |
91a41032 | 557 | { |
70c2a24d | 558 | int port; |
91a41032 | 559 | |
70c2a24d CW |
560 | port = 1; /* wait for a free slot */ |
561 | if (engine->disable_lite_restore_wa || engine->preempt_wa) | |
562 | port = 0; /* wait for GPU to be idle before continuing */ | |
c6a2ac71 | 563 | |
70c2a24d | 564 | return !engine->execlist_port[port].request; |
91a41032 BW |
565 | } |
566 | ||
6e5248b5 | 567 | /* |
73e4d07f OM |
568 | * Check the unread Context Status Buffers and manage the submission of new |
569 | * contexts to the ELSP accordingly. | |
570 | */ | |
27af5eea | 571 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 572 | { |
27af5eea | 573 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 574 | struct execlist_port *port = engine->execlist_port; |
c033666a | 575 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 576 | |
3756685a | 577 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 578 | |
70c2a24d CW |
579 | if (!execlists_elsp_idle(engine)) { |
580 | u32 __iomem *csb_mmio = | |
581 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); | |
582 | u32 __iomem *buf = | |
583 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); | |
584 | unsigned int csb, head, tail; | |
585 | ||
586 | csb = readl(csb_mmio); | |
587 | head = GEN8_CSB_READ_PTR(csb); | |
588 | tail = GEN8_CSB_WRITE_PTR(csb); | |
589 | if (tail < head) | |
590 | tail += GEN8_CSB_ENTRIES; | |
591 | while (head < tail) { | |
592 | unsigned int idx = ++head % GEN8_CSB_ENTRIES; | |
593 | unsigned int status = readl(buf + 2 * idx); | |
594 | ||
595 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) | |
596 | continue; | |
597 | ||
598 | GEM_BUG_ON(port[0].count == 0); | |
599 | if (--port[0].count == 0) { | |
600 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); | |
601 | execlists_context_status_change(port[0].request, | |
602 | INTEL_CONTEXT_SCHEDULE_OUT); | |
603 | ||
604 | i915_gem_request_put(port[0].request); | |
605 | port[0] = port[1]; | |
606 | memset(&port[1], 0, sizeof(port[1])); | |
607 | ||
608 | engine->preempt_wa = false; | |
609 | } | |
26720ab9 | 610 | |
70c2a24d CW |
611 | GEM_BUG_ON(port[0].count == 0 && |
612 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); | |
e1fee72c OM |
613 | } |
614 | ||
70c2a24d CW |
615 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, |
616 | GEN8_CSB_WRITE_PTR(csb) << 8), | |
617 | csb_mmio); | |
e981e7b1 TD |
618 | } |
619 | ||
70c2a24d CW |
620 | if (execlists_elsp_ready(engine)) |
621 | execlists_dequeue(engine); | |
c6a2ac71 | 622 | |
70c2a24d | 623 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
624 | } |
625 | ||
20311bd3 CW |
626 | static bool insert_request(struct i915_priotree *pt, struct rb_root *root) |
627 | { | |
628 | struct rb_node **p, *rb; | |
629 | bool first = true; | |
630 | ||
631 | /* most positive priority is scheduled first, equal priorities fifo */ | |
632 | rb = NULL; | |
633 | p = &root->rb_node; | |
634 | while (*p) { | |
635 | struct i915_priotree *pos; | |
636 | ||
637 | rb = *p; | |
638 | pos = rb_entry(rb, typeof(*pos), node); | |
639 | if (pt->priority > pos->priority) { | |
640 | p = &rb->rb_left; | |
641 | } else { | |
642 | p = &rb->rb_right; | |
643 | first = false; | |
644 | } | |
645 | } | |
646 | rb_link_node(&pt->node, rb, p); | |
647 | rb_insert_color(&pt->node, root); | |
648 | ||
649 | return first; | |
650 | } | |
651 | ||
f4ea6bdd | 652 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 653 | { |
4a570db5 | 654 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 655 | unsigned long flags; |
acdd884a | 656 | |
663f71e7 CW |
657 | /* Will be called from irq-context when using foreign fences. */ |
658 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 659 | |
20311bd3 CW |
660 | if (insert_request(&request->priotree, &engine->execlist_queue)) |
661 | engine->execlist_first = &request->priotree.node; | |
70c2a24d CW |
662 | if (execlists_elsp_idle(engine)) |
663 | tasklet_hi_schedule(&engine->irq_tasklet); | |
acdd884a | 664 | |
663f71e7 | 665 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
666 | } |
667 | ||
20311bd3 CW |
668 | static struct intel_engine_cs * |
669 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
670 | { | |
671 | struct intel_engine_cs *engine; | |
672 | ||
673 | engine = container_of(pt, | |
674 | struct drm_i915_gem_request, | |
675 | priotree)->engine; | |
676 | if (engine != locked) { | |
677 | if (locked) | |
678 | spin_unlock_irq(&locked->timeline->lock); | |
679 | spin_lock_irq(&engine->timeline->lock); | |
680 | } | |
681 | ||
682 | return engine; | |
683 | } | |
684 | ||
685 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
686 | { | |
687 | struct intel_engine_cs *engine = NULL; | |
688 | struct i915_dependency *dep, *p; | |
689 | struct i915_dependency stack; | |
690 | LIST_HEAD(dfs); | |
691 | ||
692 | if (prio <= READ_ONCE(request->priotree.priority)) | |
693 | return; | |
694 | ||
70cd1476 CW |
695 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
696 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
697 | |
698 | stack.signaler = &request->priotree; | |
699 | list_add(&stack.dfs_link, &dfs); | |
700 | ||
701 | /* Recursively bump all dependent priorities to match the new request. | |
702 | * | |
703 | * A naive approach would be to use recursion: | |
704 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
705 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
706 | * update_priorities(dep->signal, prio) | |
707 | * insert_request(pt); | |
708 | * } | |
709 | * but that may have unlimited recursion depth and so runs a very | |
710 | * real risk of overunning the kernel stack. Instead, we build | |
711 | * a flat list of all dependencies starting with the current request. | |
712 | * As we walk the list of dependencies, we add all of its dependencies | |
713 | * to the end of the list (this may include an already visited | |
714 | * request) and continue to walk onwards onto the new dependencies. The | |
715 | * end result is a topological list of requests in reverse order, the | |
716 | * last element in the list is the request we must execute first. | |
717 | */ | |
718 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
719 | struct i915_priotree *pt = dep->signaler; | |
720 | ||
721 | list_for_each_entry(p, &pt->signalers_list, signal_link) | |
722 | if (prio > READ_ONCE(p->signaler->priority)) | |
723 | list_move_tail(&p->dfs_link, &dfs); | |
724 | ||
0798cff4 | 725 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
726 | if (!RB_EMPTY_NODE(&pt->node)) |
727 | continue; | |
728 | ||
729 | engine = pt_lock_engine(pt, engine); | |
730 | ||
731 | /* If it is not already in the rbtree, we can update the | |
732 | * priority inplace and skip over it (and its dependencies) | |
733 | * if it is referenced *again* as we descend the dfs. | |
734 | */ | |
735 | if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) { | |
736 | pt->priority = prio; | |
737 | list_del_init(&dep->dfs_link); | |
738 | } | |
739 | } | |
740 | ||
741 | /* Fifo and depth-first replacement ensure our deps execute before us */ | |
742 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
743 | struct i915_priotree *pt = dep->signaler; | |
744 | ||
745 | INIT_LIST_HEAD(&dep->dfs_link); | |
746 | ||
747 | engine = pt_lock_engine(pt, engine); | |
748 | ||
749 | if (prio <= pt->priority) | |
750 | continue; | |
751 | ||
752 | GEM_BUG_ON(RB_EMPTY_NODE(&pt->node)); | |
753 | ||
754 | pt->priority = prio; | |
755 | rb_erase(&pt->node, &engine->execlist_queue); | |
756 | if (insert_request(pt, &engine->execlist_queue)) | |
757 | engine->execlist_first = &pt->node; | |
758 | } | |
759 | ||
760 | if (engine) | |
761 | spin_unlock_irq(&engine->timeline->lock); | |
762 | ||
763 | /* XXX Do we need to preempt to make room for us and our deps? */ | |
764 | } | |
765 | ||
e8a9c58f CW |
766 | static int execlists_context_pin(struct intel_engine_cs *engine, |
767 | struct i915_gem_context *ctx) | |
dcb4c12a | 768 | { |
9021ad03 | 769 | struct intel_context *ce = &ctx->engine[engine->id]; |
7d774cac | 770 | void *vaddr; |
ca82580c | 771 | int ret; |
dcb4c12a | 772 | |
91c8a326 | 773 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 774 | |
9021ad03 | 775 | if (ce->pin_count++) |
24f1d3cc CW |
776 | return 0; |
777 | ||
e8a9c58f CW |
778 | if (!ce->state) { |
779 | ret = execlists_context_deferred_alloc(ctx, engine); | |
780 | if (ret) | |
781 | goto err; | |
782 | } | |
783 | ||
bf3783e5 CW |
784 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, |
785 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP | PIN_GLOBAL); | |
e84fe803 | 786 | if (ret) |
24f1d3cc | 787 | goto err; |
7ba717cf | 788 | |
bf3783e5 | 789 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
790 | if (IS_ERR(vaddr)) { |
791 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 792 | goto unpin_vma; |
82352e90 TU |
793 | } |
794 | ||
aad29fbb | 795 | ret = intel_ring_pin(ce->ring); |
e84fe803 | 796 | if (ret) |
7d774cac | 797 | goto unpin_map; |
d1675198 | 798 | |
0bc40be8 | 799 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 800 | |
a3aabe86 CW |
801 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
802 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 803 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 804 | |
a4f5ea64 | 805 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 806 | |
e84fe803 | 807 | /* Invalidate GuC TLB. */ |
bf3783e5 CW |
808 | if (i915.enable_guc_submission) { |
809 | struct drm_i915_private *dev_priv = ctx->i915; | |
e84fe803 | 810 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
bf3783e5 | 811 | } |
dcb4c12a | 812 | |
9a6feaf0 | 813 | i915_gem_context_get(ctx); |
24f1d3cc | 814 | return 0; |
7ba717cf | 815 | |
7d774cac | 816 | unpin_map: |
bf3783e5 CW |
817 | i915_gem_object_unpin_map(ce->state->obj); |
818 | unpin_vma: | |
819 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 820 | err: |
9021ad03 | 821 | ce->pin_count = 0; |
e84fe803 NH |
822 | return ret; |
823 | } | |
824 | ||
e8a9c58f CW |
825 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
826 | struct i915_gem_context *ctx) | |
e84fe803 | 827 | { |
9021ad03 | 828 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 829 | |
91c8a326 | 830 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 831 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 832 | |
9021ad03 | 833 | if (--ce->pin_count) |
24f1d3cc | 834 | return; |
e84fe803 | 835 | |
aad29fbb | 836 | intel_ring_unpin(ce->ring); |
dcb4c12a | 837 | |
bf3783e5 CW |
838 | i915_gem_object_unpin_map(ce->state->obj); |
839 | i915_vma_unpin(ce->state); | |
321fe304 | 840 | |
9a6feaf0 | 841 | i915_gem_context_put(ctx); |
dcb4c12a OM |
842 | } |
843 | ||
ef11c01d CW |
844 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
845 | { | |
846 | struct intel_engine_cs *engine = request->engine; | |
847 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
848 | int ret; | |
849 | ||
e8a9c58f CW |
850 | GEM_BUG_ON(!ce->pin_count); |
851 | ||
ef11c01d CW |
852 | /* Flush enough space to reduce the likelihood of waiting after |
853 | * we start building the request - in which case we will just | |
854 | * have to repeat work. | |
855 | */ | |
856 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
857 | ||
e8a9c58f | 858 | GEM_BUG_ON(!ce->ring); |
ef11c01d CW |
859 | request->ring = ce->ring; |
860 | ||
ef11c01d CW |
861 | if (i915.enable_guc_submission) { |
862 | /* | |
863 | * Check that the GuC has space for the request before | |
864 | * going any further, as the i915_add_request() call | |
865 | * later on mustn't fail ... | |
866 | */ | |
867 | ret = i915_guc_wq_reserve(request); | |
868 | if (ret) | |
e8a9c58f | 869 | goto err; |
ef11c01d CW |
870 | } |
871 | ||
872 | ret = intel_ring_begin(request, 0); | |
873 | if (ret) | |
874 | goto err_unreserve; | |
875 | ||
876 | if (!ce->initialised) { | |
877 | ret = engine->init_context(request); | |
878 | if (ret) | |
879 | goto err_unreserve; | |
880 | ||
881 | ce->initialised = true; | |
882 | } | |
883 | ||
884 | /* Note that after this point, we have committed to using | |
885 | * this request as it is being used to both track the | |
886 | * state of engine initialisation and liveness of the | |
887 | * golden renderstate above. Think twice before you try | |
888 | * to cancel/unwind this request now. | |
889 | */ | |
890 | ||
891 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
892 | return 0; | |
893 | ||
894 | err_unreserve: | |
895 | if (i915.enable_guc_submission) | |
896 | i915_guc_wq_unreserve(request); | |
e8a9c58f | 897 | err: |
ef11c01d CW |
898 | return ret; |
899 | } | |
900 | ||
e2be4faf | 901 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
902 | { |
903 | int ret, i; | |
7e37f889 | 904 | struct intel_ring *ring = req->ring; |
c033666a | 905 | struct i915_workarounds *w = &req->i915->workarounds; |
771b9a53 | 906 | |
cd7feaaa | 907 | if (w->count == 0) |
771b9a53 MT |
908 | return 0; |
909 | ||
7c9cf4e3 | 910 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
911 | if (ret) |
912 | return ret; | |
913 | ||
987046ad | 914 | ret = intel_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
915 | if (ret) |
916 | return ret; | |
917 | ||
1dae2dfb | 918 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
771b9a53 | 919 | for (i = 0; i < w->count; i++) { |
1dae2dfb CW |
920 | intel_ring_emit_reg(ring, w->reg[i].addr); |
921 | intel_ring_emit(ring, w->reg[i].value); | |
771b9a53 | 922 | } |
1dae2dfb | 923 | intel_ring_emit(ring, MI_NOOP); |
771b9a53 | 924 | |
1dae2dfb | 925 | intel_ring_advance(ring); |
771b9a53 | 926 | |
7c9cf4e3 | 927 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
928 | if (ret) |
929 | return ret; | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
83b8a982 | 934 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 935 | do { \ |
83b8a982 AS |
936 | int __index = (index)++; \ |
937 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
938 | return -ENOSPC; \ |
939 | } \ | |
83b8a982 | 940 | batch[__index] = (cmd); \ |
17ee950d AS |
941 | } while (0) |
942 | ||
8f40db77 | 943 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 944 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
945 | |
946 | /* | |
947 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
948 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
949 | * but there is a slight complication as this is applied in WA batch where the | |
950 | * values are only initialized once so we cannot take register value at the | |
951 | * beginning and reuse it further; hence we save its value to memory, upload a | |
952 | * constant value with bit21 set and then we restore it back with the saved value. | |
953 | * To simplify the WA, a constant value is formed by using the default value | |
954 | * of this register. This shouldn't be a problem because we are only modifying | |
955 | * it for a short period and this batch in non-premptible. We can ofcourse | |
956 | * use additional instructions that read the actual value of the register | |
957 | * at that time and set our bit of interest but it makes the WA complicated. | |
958 | * | |
959 | * This WA is also required for Gen9 so extracting as a function avoids | |
960 | * code duplication. | |
961 | */ | |
0bc40be8 | 962 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
6e5248b5 | 963 | uint32_t *batch, |
9e000847 AS |
964 | uint32_t index) |
965 | { | |
5e580523 | 966 | struct drm_i915_private *dev_priv = engine->i915; |
9e000847 AS |
967 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
968 | ||
a4106a78 | 969 | /* |
3be192e9 | 970 | * WaDisableLSQCROPERFforOCL:kbl |
a4106a78 AS |
971 | * This WA is implemented in skl_init_clock_gating() but since |
972 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
973 | * set this bit here to retain the WA during flush. | |
974 | */ | |
3be192e9 | 975 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) |
a4106a78 AS |
976 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
977 | ||
f1afe24f | 978 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 979 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 980 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 981 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 AS |
982 | wa_ctx_emit(batch, index, 0); |
983 | ||
984 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 985 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
986 | wa_ctx_emit(batch, index, l3sqc4_flush); |
987 | ||
988 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
989 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
990 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
991 | wa_ctx_emit(batch, index, 0); | |
992 | wa_ctx_emit(batch, index, 0); | |
993 | wa_ctx_emit(batch, index, 0); | |
994 | wa_ctx_emit(batch, index, 0); | |
995 | ||
f1afe24f | 996 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 997 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 998 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 999 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 | 1000 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
1001 | |
1002 | return index; | |
1003 | } | |
1004 | ||
17ee950d AS |
1005 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1006 | uint32_t offset, | |
1007 | uint32_t start_alignment) | |
1008 | { | |
1009 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1010 | } | |
1011 | ||
1012 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1013 | uint32_t offset, | |
1014 | uint32_t size_alignment) | |
1015 | { | |
1016 | wa_ctx->size = offset - wa_ctx->offset; | |
1017 | ||
1018 | WARN(wa_ctx->size % size_alignment, | |
1019 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1020 | wa_ctx->size, size_alignment); | |
1021 | return 0; | |
1022 | } | |
1023 | ||
6e5248b5 DV |
1024 | /* |
1025 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1026 | * initialized at the beginning and shared across all contexts but this field | |
1027 | * helps us to have multiple batches at different offsets and select them based | |
1028 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1029 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1030 | * |
6e5248b5 DV |
1031 | * The number of WA applied are not known at the beginning; we use this field |
1032 | * to return the no of DWORDS written. | |
17ee950d | 1033 | * |
6e5248b5 DV |
1034 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1035 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1036 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1037 | * makes a complete batch buffer. | |
17ee950d | 1038 | */ |
0bc40be8 | 1039 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d | 1040 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1041 | uint32_t *batch, |
17ee950d AS |
1042 | uint32_t *offset) |
1043 | { | |
0160f055 | 1044 | uint32_t scratch_addr; |
17ee950d AS |
1045 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1046 | ||
7ad00d1a | 1047 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1048 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1049 | |
c82435bb | 1050 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
c033666a | 1051 | if (IS_BROADWELL(engine->i915)) { |
0bc40be8 | 1052 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
604ef734 AH |
1053 | if (rc < 0) |
1054 | return rc; | |
1055 | index = rc; | |
c82435bb AS |
1056 | } |
1057 | ||
0160f055 AS |
1058 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1059 | /* Actual scratch location is at 128 bytes offset */ | |
bde13ebd | 1060 | scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
0160f055 | 1061 | |
83b8a982 AS |
1062 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1063 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1064 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1065 | PIPE_CONTROL_CS_STALL | | |
1066 | PIPE_CONTROL_QW_WRITE)); | |
1067 | wa_ctx_emit(batch, index, scratch_addr); | |
1068 | wa_ctx_emit(batch, index, 0); | |
1069 | wa_ctx_emit(batch, index, 0); | |
1070 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1071 | |
17ee950d AS |
1072 | /* Pad to end of cacheline */ |
1073 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1074 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1075 | |
1076 | /* | |
1077 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1078 | * execution depends on the length specified in terms of cache lines | |
1079 | * in the register CTX_RCS_INDIRECT_CTX | |
1080 | */ | |
1081 | ||
1082 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1083 | } | |
1084 | ||
6e5248b5 DV |
1085 | /* |
1086 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1087 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 1088 | * |
6e5248b5 | 1089 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
1090 | * |
1091 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1092 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1093 | */ | |
0bc40be8 | 1094 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d | 1095 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1096 | uint32_t *batch, |
17ee950d AS |
1097 | uint32_t *offset) |
1098 | { | |
1099 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1100 | ||
7ad00d1a | 1101 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1102 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1103 | |
83b8a982 | 1104 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1105 | |
1106 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1107 | } | |
1108 | ||
0bc40be8 | 1109 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1110 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1111 | uint32_t *batch, |
0504cffc AS |
1112 | uint32_t *offset) |
1113 | { | |
a4106a78 | 1114 | int ret; |
5e580523 | 1115 | struct drm_i915_private *dev_priv = engine->i915; |
0504cffc AS |
1116 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1117 | ||
9fc736e8 JN |
1118 | /* WaDisableCtxRestoreArbitration:bxt */ |
1119 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
0907c8f7 | 1120 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 1121 | |
a4106a78 | 1122 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 1123 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1124 | if (ret < 0) |
1125 | return ret; | |
1126 | index = ret; | |
1127 | ||
873e8171 MK |
1128 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ |
1129 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1130 | wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); | |
1131 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( | |
1132 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); | |
1133 | wa_ctx_emit(batch, index, MI_NOOP); | |
1134 | ||
066d4628 MK |
1135 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1136 | /* Actual scratch location is at 128 bytes offset */ | |
703d1282 | 1137 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) { |
56c0f1a7 | 1138 | u32 scratch_addr = |
bde13ebd | 1139 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
066d4628 MK |
1140 | |
1141 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1142 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1143 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1144 | PIPE_CONTROL_CS_STALL | | |
1145 | PIPE_CONTROL_QW_WRITE)); | |
1146 | wa_ctx_emit(batch, index, scratch_addr); | |
1147 | wa_ctx_emit(batch, index, 0); | |
1148 | wa_ctx_emit(batch, index, 0); | |
1149 | wa_ctx_emit(batch, index, 0); | |
1150 | } | |
3485d99e TG |
1151 | |
1152 | /* WaMediaPoolStateCmdInWABB:bxt */ | |
1153 | if (HAS_POOLED_EU(engine->i915)) { | |
1154 | /* | |
1155 | * EU pool configuration is setup along with golden context | |
1156 | * during context initialization. This value depends on | |
1157 | * device type (2x6 or 3x6) and needs to be updated based | |
1158 | * on which subslice is disabled especially for 2x6 | |
1159 | * devices, however it is safe to load default | |
1160 | * configuration of 3x6 device instead of masking off | |
1161 | * corresponding bits because HW ignores bits of a disabled | |
1162 | * subslice and drops down to appropriate config. Please | |
1163 | * see render_state_setup() in i915_gem_render_state.c for | |
1164 | * possible configurations, to avoid duplication they are | |
1165 | * not shown here again. | |
1166 | */ | |
1167 | u32 eu_pool_config = 0x00777000; | |
1168 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); | |
1169 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); | |
1170 | wa_ctx_emit(batch, index, eu_pool_config); | |
1171 | wa_ctx_emit(batch, index, 0); | |
1172 | wa_ctx_emit(batch, index, 0); | |
1173 | wa_ctx_emit(batch, index, 0); | |
1174 | } | |
1175 | ||
0504cffc AS |
1176 | /* Pad to end of cacheline */ |
1177 | while (index % CACHELINE_DWORDS) | |
1178 | wa_ctx_emit(batch, index, MI_NOOP); | |
1179 | ||
1180 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1181 | } | |
1182 | ||
0bc40be8 | 1183 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1184 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1185 | uint32_t *batch, |
0504cffc AS |
1186 | uint32_t *offset) |
1187 | { | |
1188 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1189 | ||
a117f378 JN |
1190 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */ |
1191 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) { | |
9b01435d | 1192 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1193 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1194 | wa_ctx_emit(batch, index, |
1195 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1196 | wa_ctx_emit(batch, index, MI_NOOP); | |
1197 | } | |
1198 | ||
b1e429fe | 1199 | /* WaClearTdlStateAckDirtyBits:bxt */ |
c033666a | 1200 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) { |
b1e429fe TG |
1201 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); |
1202 | ||
1203 | wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); | |
1204 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1205 | ||
1206 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); | |
1207 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1208 | ||
1209 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); | |
1210 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1211 | ||
1212 | wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); | |
1213 | /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ | |
1214 | wa_ctx_emit(batch, index, 0x0); | |
1215 | wa_ctx_emit(batch, index, MI_NOOP); | |
1216 | } | |
1217 | ||
9fc736e8 JN |
1218 | /* WaDisableCtxRestoreArbitration:bxt */ |
1219 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) | |
0907c8f7 AS |
1220 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1221 | ||
0504cffc AS |
1222 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1223 | ||
1224 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1225 | } | |
1226 | ||
0bc40be8 | 1227 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d | 1228 | { |
48bb74e4 CW |
1229 | struct drm_i915_gem_object *obj; |
1230 | struct i915_vma *vma; | |
1231 | int err; | |
17ee950d | 1232 | |
12d79d78 | 1233 | obj = i915_gem_object_create(engine->i915, PAGE_ALIGN(size)); |
48bb74e4 CW |
1234 | if (IS_ERR(obj)) |
1235 | return PTR_ERR(obj); | |
17ee950d | 1236 | |
48bb74e4 CW |
1237 | vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL); |
1238 | if (IS_ERR(vma)) { | |
1239 | err = PTR_ERR(vma); | |
1240 | goto err; | |
17ee950d AS |
1241 | } |
1242 | ||
48bb74e4 CW |
1243 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1244 | if (err) | |
1245 | goto err; | |
1246 | ||
1247 | engine->wa_ctx.vma = vma; | |
17ee950d | 1248 | return 0; |
48bb74e4 CW |
1249 | |
1250 | err: | |
1251 | i915_gem_object_put(obj); | |
1252 | return err; | |
17ee950d AS |
1253 | } |
1254 | ||
0bc40be8 | 1255 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1256 | { |
19880c4a | 1257 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1258 | } |
1259 | ||
0bc40be8 | 1260 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1261 | { |
48bb74e4 | 1262 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d AS |
1263 | uint32_t *batch; |
1264 | uint32_t offset; | |
1265 | struct page *page; | |
48bb74e4 | 1266 | int ret; |
17ee950d | 1267 | |
0bc40be8 | 1268 | WARN_ON(engine->id != RCS); |
17ee950d | 1269 | |
5e60d790 | 1270 | /* update this when WA for higher Gen are added */ |
c033666a | 1271 | if (INTEL_GEN(engine->i915) > 9) { |
0504cffc | 1272 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
c033666a | 1273 | INTEL_GEN(engine->i915)); |
5e60d790 | 1274 | return 0; |
0504cffc | 1275 | } |
5e60d790 | 1276 | |
c4db7599 | 1277 | /* some WA perform writes to scratch page, ensure it is valid */ |
56c0f1a7 | 1278 | if (!engine->scratch) { |
0bc40be8 | 1279 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); |
c4db7599 AS |
1280 | return -EINVAL; |
1281 | } | |
1282 | ||
0bc40be8 | 1283 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1284 | if (ret) { |
1285 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1286 | return ret; | |
1287 | } | |
1288 | ||
48bb74e4 | 1289 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
17ee950d AS |
1290 | batch = kmap_atomic(page); |
1291 | offset = 0; | |
1292 | ||
c033666a | 1293 | if (IS_GEN8(engine->i915)) { |
0bc40be8 | 1294 | ret = gen8_init_indirectctx_bb(engine, |
17ee950d AS |
1295 | &wa_ctx->indirect_ctx, |
1296 | batch, | |
1297 | &offset); | |
1298 | if (ret) | |
1299 | goto out; | |
1300 | ||
0bc40be8 | 1301 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1302 | &wa_ctx->per_ctx, |
1303 | batch, | |
1304 | &offset); | |
1305 | if (ret) | |
1306 | goto out; | |
c033666a | 1307 | } else if (IS_GEN9(engine->i915)) { |
0bc40be8 | 1308 | ret = gen9_init_indirectctx_bb(engine, |
0504cffc AS |
1309 | &wa_ctx->indirect_ctx, |
1310 | batch, | |
1311 | &offset); | |
1312 | if (ret) | |
1313 | goto out; | |
1314 | ||
0bc40be8 | 1315 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1316 | &wa_ctx->per_ctx, |
1317 | batch, | |
1318 | &offset); | |
1319 | if (ret) | |
1320 | goto out; | |
17ee950d AS |
1321 | } |
1322 | ||
1323 | out: | |
1324 | kunmap_atomic(batch); | |
1325 | if (ret) | |
0bc40be8 | 1326 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1327 | |
1328 | return ret; | |
1329 | } | |
1330 | ||
04794adb TU |
1331 | static void lrc_init_hws(struct intel_engine_cs *engine) |
1332 | { | |
c033666a | 1333 | struct drm_i915_private *dev_priv = engine->i915; |
04794adb TU |
1334 | |
1335 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), | |
57e88531 | 1336 | engine->status_page.ggtt_offset); |
04794adb TU |
1337 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); |
1338 | } | |
1339 | ||
0bc40be8 | 1340 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1341 | { |
c033666a | 1342 | struct drm_i915_private *dev_priv = engine->i915; |
821ed7df CW |
1343 | int ret; |
1344 | ||
1345 | ret = intel_mocs_init_engine(engine); | |
1346 | if (ret) | |
1347 | return ret; | |
9b1136d5 | 1348 | |
04794adb | 1349 | lrc_init_hws(engine); |
e84fe803 | 1350 | |
ad07dfcd | 1351 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 1352 | |
0bc40be8 | 1353 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
73d477f6 | 1354 | |
0bc40be8 | 1355 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1356 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1357 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
dfc53c5e | 1358 | |
0bc40be8 | 1359 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1360 | |
fc0768ce | 1361 | intel_engine_init_hangcheck(engine); |
9b1136d5 | 1362 | |
c87d50cc CW |
1363 | /* After a GPU reset, we may have requests to replay */ |
1364 | if (!execlists_elsp_idle(engine)) { | |
1365 | engine->execlist_port[0].count = 0; | |
1366 | engine->execlist_port[1].count = 0; | |
821ed7df | 1367 | execlists_submit_ports(engine); |
c87d50cc | 1368 | } |
821ed7df CW |
1369 | |
1370 | return 0; | |
9b1136d5 OM |
1371 | } |
1372 | ||
0bc40be8 | 1373 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1374 | { |
c033666a | 1375 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1376 | int ret; |
1377 | ||
0bc40be8 | 1378 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1379 | if (ret) |
1380 | return ret; | |
1381 | ||
1382 | /* We need to disable the AsyncFlip performance optimisations in order | |
1383 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1384 | * programmed to '1' on all products. | |
1385 | * | |
1386 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1387 | */ | |
1388 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1389 | ||
9b1136d5 OM |
1390 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1391 | ||
0bc40be8 | 1392 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1393 | } |
1394 | ||
0bc40be8 | 1395 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1396 | { |
1397 | int ret; | |
1398 | ||
0bc40be8 | 1399 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1400 | if (ret) |
1401 | return ret; | |
1402 | ||
0bc40be8 | 1403 | return init_workarounds_ring(engine); |
82ef822e DL |
1404 | } |
1405 | ||
821ed7df CW |
1406 | static void reset_common_ring(struct intel_engine_cs *engine, |
1407 | struct drm_i915_gem_request *request) | |
1408 | { | |
1409 | struct drm_i915_private *dev_priv = engine->i915; | |
1410 | struct execlist_port *port = engine->execlist_port; | |
1411 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
1412 | ||
a3aabe86 CW |
1413 | /* We want a simple context + ring to execute the breadcrumb update. |
1414 | * We cannot rely on the context being intact across the GPU hang, | |
1415 | * so clear it and rebuild just what we need for the breadcrumb. | |
1416 | * All pending requests for this context will be zapped, and any | |
1417 | * future request will be after userspace has had the opportunity | |
1418 | * to recreate its own state. | |
1419 | */ | |
1420 | execlists_init_reg_state(ce->lrc_reg_state, | |
1421 | request->ctx, engine, ce->ring); | |
1422 | ||
821ed7df | 1423 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1424 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1425 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1426 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1427 | |
821ed7df CW |
1428 | request->ring->head = request->postfix; |
1429 | request->ring->last_retired_head = -1; | |
1430 | intel_ring_update_space(request->ring); | |
1431 | ||
1432 | if (i915.enable_guc_submission) | |
1433 | return; | |
1434 | ||
1435 | /* Catch up with any missed context-switch interrupts */ | |
1436 | I915_WRITE(RING_CONTEXT_STATUS_PTR(engine), _MASKED_FIELD(0xffff, 0)); | |
1437 | if (request->ctx != port[0].request->ctx) { | |
1438 | i915_gem_request_put(port[0].request); | |
1439 | port[0] = port[1]; | |
1440 | memset(&port[1], 0, sizeof(port[1])); | |
1441 | } | |
1442 | ||
821ed7df | 1443 | GEM_BUG_ON(request->ctx != port[0].request->ctx); |
a3aabe86 CW |
1444 | |
1445 | /* Reset WaIdleLiteRestore:bdw,skl as well */ | |
1446 | request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32); | |
821ed7df CW |
1447 | } |
1448 | ||
7a01a0a2 MT |
1449 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1450 | { | |
1451 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
7e37f889 | 1452 | struct intel_ring *ring = req->ring; |
4a570db5 | 1453 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1454 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; |
1455 | int i, ret; | |
1456 | ||
987046ad | 1457 | ret = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
7a01a0a2 MT |
1458 | if (ret) |
1459 | return ret; | |
1460 | ||
b5321f30 | 1461 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds)); |
7a01a0a2 MT |
1462 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
1463 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1464 | ||
b5321f30 CW |
1465 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i)); |
1466 | intel_ring_emit(ring, upper_32_bits(pd_daddr)); | |
1467 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i)); | |
1468 | intel_ring_emit(ring, lower_32_bits(pd_daddr)); | |
7a01a0a2 MT |
1469 | } |
1470 | ||
b5321f30 CW |
1471 | intel_ring_emit(ring, MI_NOOP); |
1472 | intel_ring_advance(ring); | |
7a01a0a2 MT |
1473 | |
1474 | return 0; | |
1475 | } | |
1476 | ||
be795fc1 | 1477 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba CW |
1478 | u64 offset, u32 len, |
1479 | unsigned int dispatch_flags) | |
15648585 | 1480 | { |
7e37f889 | 1481 | struct intel_ring *ring = req->ring; |
8e004efc | 1482 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1483 | int ret; |
1484 | ||
7a01a0a2 MT |
1485 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1486 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1487 | * but we can't. Force Restore would be a second option, but | |
1488 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1489 | * not idle). PML4 is allocated during ppgtt init so this is |
1490 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1491 | if (req->ctx->ppgtt && |
666796da | 1492 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 | 1493 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
c033666a | 1494 | !intel_vgpu_active(req->i915)) { |
2dba3239 MT |
1495 | ret = intel_logical_ring_emit_pdps(req); |
1496 | if (ret) | |
1497 | return ret; | |
1498 | } | |
7a01a0a2 | 1499 | |
666796da | 1500 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1501 | } |
1502 | ||
987046ad | 1503 | ret = intel_ring_begin(req, 4); |
15648585 OM |
1504 | if (ret) |
1505 | return ret; | |
1506 | ||
1507 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 CW |
1508 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | |
1509 | (ppgtt<<8) | | |
1510 | (dispatch_flags & I915_DISPATCH_RS ? | |
1511 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
1512 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1513 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1514 | intel_ring_emit(ring, MI_NOOP); | |
1515 | intel_ring_advance(ring); | |
15648585 OM |
1516 | |
1517 | return 0; | |
1518 | } | |
1519 | ||
31bb59cc | 1520 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1521 | { |
c033666a | 1522 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1523 | I915_WRITE_IMR(engine, |
1524 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1525 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1526 | } |
1527 | ||
31bb59cc | 1528 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1529 | { |
c033666a | 1530 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1531 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1532 | } |
1533 | ||
7c9cf4e3 | 1534 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1535 | { |
7e37f889 CW |
1536 | struct intel_ring *ring = request->ring; |
1537 | u32 cmd; | |
4712274c OM |
1538 | int ret; |
1539 | ||
987046ad | 1540 | ret = intel_ring_begin(request, 4); |
4712274c OM |
1541 | if (ret) |
1542 | return ret; | |
1543 | ||
1544 | cmd = MI_FLUSH_DW + 1; | |
1545 | ||
f0a1fb10 CW |
1546 | /* We always require a command barrier so that subsequent |
1547 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1548 | * wrt the contents of the write cache being flushed to memory | |
1549 | * (and thus being coherent from the CPU). | |
1550 | */ | |
1551 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1552 | ||
7c9cf4e3 | 1553 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1554 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1555 | if (request->engine->id == VCS) |
f0a1fb10 | 1556 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1557 | } |
1558 | ||
b5321f30 CW |
1559 | intel_ring_emit(ring, cmd); |
1560 | intel_ring_emit(ring, | |
1561 | I915_GEM_HWS_SCRATCH_ADDR | | |
1562 | MI_FLUSH_DW_USE_GTT); | |
1563 | intel_ring_emit(ring, 0); /* upper addr */ | |
1564 | intel_ring_emit(ring, 0); /* value */ | |
1565 | intel_ring_advance(ring); | |
4712274c OM |
1566 | |
1567 | return 0; | |
1568 | } | |
1569 | ||
7deb4d39 | 1570 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1571 | u32 mode) |
4712274c | 1572 | { |
7e37f889 | 1573 | struct intel_ring *ring = request->ring; |
b5321f30 | 1574 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1575 | u32 scratch_addr = |
1576 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1577 | bool vf_flush_wa = false, dc_flush_wa = false; |
4712274c OM |
1578 | u32 flags = 0; |
1579 | int ret; | |
0b2d0934 | 1580 | int len; |
4712274c OM |
1581 | |
1582 | flags |= PIPE_CONTROL_CS_STALL; | |
1583 | ||
7c9cf4e3 | 1584 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1585 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1586 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1587 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1588 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1589 | } |
1590 | ||
7c9cf4e3 | 1591 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1592 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1593 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1594 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1595 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1596 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1597 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1598 | flags |= PIPE_CONTROL_QW_WRITE; | |
1599 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1600 | |
1a5a9ce7 BW |
1601 | /* |
1602 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1603 | * pipe control. | |
1604 | */ | |
c033666a | 1605 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1606 | vf_flush_wa = true; |
0b2d0934 MK |
1607 | |
1608 | /* WaForGAMHang:kbl */ | |
1609 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1610 | dc_flush_wa = true; | |
1a5a9ce7 | 1611 | } |
9647ff36 | 1612 | |
0b2d0934 MK |
1613 | len = 6; |
1614 | ||
1615 | if (vf_flush_wa) | |
1616 | len += 6; | |
1617 | ||
1618 | if (dc_flush_wa) | |
1619 | len += 12; | |
1620 | ||
1621 | ret = intel_ring_begin(request, len); | |
4712274c OM |
1622 | if (ret) |
1623 | return ret; | |
1624 | ||
9647ff36 | 1625 | if (vf_flush_wa) { |
b5321f30 CW |
1626 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1627 | intel_ring_emit(ring, 0); | |
1628 | intel_ring_emit(ring, 0); | |
1629 | intel_ring_emit(ring, 0); | |
1630 | intel_ring_emit(ring, 0); | |
1631 | intel_ring_emit(ring, 0); | |
9647ff36 ID |
1632 | } |
1633 | ||
0b2d0934 | 1634 | if (dc_flush_wa) { |
b5321f30 CW |
1635 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1636 | intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE); | |
1637 | intel_ring_emit(ring, 0); | |
1638 | intel_ring_emit(ring, 0); | |
1639 | intel_ring_emit(ring, 0); | |
1640 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1641 | } |
1642 | ||
b5321f30 CW |
1643 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1644 | intel_ring_emit(ring, flags); | |
1645 | intel_ring_emit(ring, scratch_addr); | |
1646 | intel_ring_emit(ring, 0); | |
1647 | intel_ring_emit(ring, 0); | |
1648 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1649 | |
1650 | if (dc_flush_wa) { | |
b5321f30 CW |
1651 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1652 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL); | |
1653 | intel_ring_emit(ring, 0); | |
1654 | intel_ring_emit(ring, 0); | |
1655 | intel_ring_emit(ring, 0); | |
1656 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1657 | } |
1658 | ||
b5321f30 | 1659 | intel_ring_advance(ring); |
4712274c OM |
1660 | |
1661 | return 0; | |
1662 | } | |
1663 | ||
c04e0f3b | 1664 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
319404df | 1665 | { |
319404df ID |
1666 | /* |
1667 | * On BXT A steppings there is a HW coherency issue whereby the | |
1668 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1669 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1670 | * clflushing the corresponding cacheline whenever the caller wants | |
1671 | * the coherency to be guaranteed. Note that this cacheline is known | |
1672 | * to be clean at this point, since we only write it in | |
1673 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1674 | * this clflush in practice becomes an invalidate operation. | |
1675 | */ | |
c04e0f3b | 1676 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1677 | } |
1678 | ||
7c17d377 CW |
1679 | /* |
1680 | * Reserve space for 2 NOOPs at the end of each request to be | |
1681 | * used as a workaround for not being allowed to do lite | |
1682 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1683 | */ | |
caddfe71 | 1684 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *out) |
4da46e1e | 1685 | { |
caddfe71 CW |
1686 | *out++ = MI_NOOP; |
1687 | *out++ = MI_NOOP; | |
1688 | request->wa_tail = intel_ring_offset(request->ring, out); | |
1689 | } | |
4da46e1e | 1690 | |
caddfe71 CW |
1691 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, |
1692 | u32 *out) | |
1693 | { | |
7c17d377 CW |
1694 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1695 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1696 | |
caddfe71 CW |
1697 | *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1698 | *out++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1699 | *out++ = 0; | |
1700 | *out++ = request->global_seqno; | |
1701 | *out++ = MI_USER_INTERRUPT; | |
1702 | *out++ = MI_NOOP; | |
1703 | request->tail = intel_ring_offset(request->ring, out); | |
1704 | ||
1705 | gen8_emit_wa_tail(request, out); | |
7c17d377 | 1706 | } |
4da46e1e | 1707 | |
98f29e8d CW |
1708 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1709 | ||
caddfe71 CW |
1710 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
1711 | u32 *out) | |
7c17d377 | 1712 | { |
ce81a65c MW |
1713 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1714 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1715 | ||
7c17d377 CW |
1716 | /* w/a for post sync ops following a GPGPU operation we |
1717 | * need a prior CS_STALL, which is emitted by the flush | |
1718 | * following the batch. | |
1719 | */ | |
caddfe71 CW |
1720 | *out++ = GFX_OP_PIPE_CONTROL(6); |
1721 | *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1722 | PIPE_CONTROL_CS_STALL | | |
1723 | PIPE_CONTROL_QW_WRITE); | |
1724 | *out++ = intel_hws_seqno_address(request->engine); | |
1725 | *out++ = 0; | |
1726 | *out++ = request->global_seqno; | |
ce81a65c | 1727 | /* We're thrashing one dword of HWS. */ |
caddfe71 CW |
1728 | *out++ = 0; |
1729 | *out++ = MI_USER_INTERRUPT; | |
1730 | *out++ = MI_NOOP; | |
1731 | request->tail = intel_ring_offset(request->ring, out); | |
1732 | ||
1733 | gen8_emit_wa_tail(request, out); | |
4da46e1e OM |
1734 | } |
1735 | ||
98f29e8d CW |
1736 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1737 | ||
8753181e | 1738 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1739 | { |
1740 | int ret; | |
1741 | ||
e2be4faf | 1742 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1743 | if (ret) |
1744 | return ret; | |
1745 | ||
3bbaba0c PA |
1746 | ret = intel_rcs_context_init_mocs(req); |
1747 | /* | |
1748 | * Failing to program the MOCS is non-fatal.The system will not | |
1749 | * run at peak performance. So generate an error and carry on. | |
1750 | */ | |
1751 | if (ret) | |
1752 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1753 | ||
4e50f082 | 1754 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1755 | } |
1756 | ||
73e4d07f OM |
1757 | /** |
1758 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1759 | * @engine: Engine Command Streamer. |
73e4d07f | 1760 | */ |
0bc40be8 | 1761 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1762 | { |
6402c330 | 1763 | struct drm_i915_private *dev_priv; |
9832b9da | 1764 | |
27af5eea TU |
1765 | /* |
1766 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1767 | * so this is just for documentation. | |
1768 | */ | |
1769 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1770 | tasklet_kill(&engine->irq_tasklet); | |
1771 | ||
c033666a | 1772 | dev_priv = engine->i915; |
6402c330 | 1773 | |
0bc40be8 | 1774 | if (engine->buffer) { |
0bc40be8 | 1775 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1776 | } |
48d82387 | 1777 | |
0bc40be8 TU |
1778 | if (engine->cleanup) |
1779 | engine->cleanup(engine); | |
48d82387 | 1780 | |
57e88531 CW |
1781 | if (engine->status_page.vma) { |
1782 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1783 | engine->status_page.vma = NULL; | |
48d82387 | 1784 | } |
e8a9c58f CW |
1785 | |
1786 | intel_engine_cleanup_common(engine); | |
17ee950d | 1787 | |
0bc40be8 | 1788 | lrc_destroy_wa_ctx_obj(engine); |
c033666a | 1789 | engine->i915 = NULL; |
3b3f1650 AG |
1790 | dev_priv->engine[engine->id] = NULL; |
1791 | kfree(engine); | |
454afebd OM |
1792 | } |
1793 | ||
ddd66c51 CW |
1794 | void intel_execlists_enable_submission(struct drm_i915_private *dev_priv) |
1795 | { | |
1796 | struct intel_engine_cs *engine; | |
3b3f1650 | 1797 | enum intel_engine_id id; |
ddd66c51 | 1798 | |
20311bd3 | 1799 | for_each_engine(engine, dev_priv, id) { |
f4ea6bdd | 1800 | engine->submit_request = execlists_submit_request; |
20311bd3 CW |
1801 | engine->schedule = execlists_schedule; |
1802 | } | |
ddd66c51 CW |
1803 | } |
1804 | ||
c9cacf93 | 1805 | static void |
e1382efb | 1806 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1807 | { |
1808 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1809 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1810 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1811 | |
1812 | engine->context_pin = execlists_context_pin; | |
1813 | engine->context_unpin = execlists_context_unpin; | |
1814 | ||
0bc40be8 | 1815 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1816 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1817 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
f4ea6bdd | 1818 | engine->submit_request = execlists_submit_request; |
20311bd3 | 1819 | engine->schedule = execlists_schedule; |
ddd66c51 | 1820 | |
31bb59cc CW |
1821 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1822 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1823 | engine->emit_bb_start = gen8_emit_bb_start; |
1b7744e7 | 1824 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) |
c04e0f3b | 1825 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
c9cacf93 TU |
1826 | } |
1827 | ||
d9f3af96 | 1828 | static inline void |
c2c7f240 | 1829 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1830 | { |
c2c7f240 | 1831 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1832 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1833 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1834 | } |
1835 | ||
7d774cac | 1836 | static int |
bf3783e5 | 1837 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1838 | { |
57e88531 | 1839 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1840 | void *hws; |
04794adb TU |
1841 | |
1842 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1843 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1844 | if (IS_ERR(hws)) |
1845 | return PTR_ERR(hws); | |
57e88531 CW |
1846 | |
1847 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1848 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1849 | engine->status_page.vma = vma; |
7d774cac TU |
1850 | |
1851 | return 0; | |
04794adb TU |
1852 | } |
1853 | ||
bb45438f TU |
1854 | static void |
1855 | logical_ring_setup(struct intel_engine_cs *engine) | |
1856 | { | |
1857 | struct drm_i915_private *dev_priv = engine->i915; | |
1858 | enum forcewake_domains fw_domains; | |
1859 | ||
019bf277 TU |
1860 | intel_engine_setup_common(engine); |
1861 | ||
bb45438f TU |
1862 | /* Intentionally left blank. */ |
1863 | engine->buffer = NULL; | |
1864 | ||
1865 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1866 | RING_ELSP(engine), | |
1867 | FW_REG_WRITE); | |
1868 | ||
1869 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1870 | RING_CONTEXT_STATUS_PTR(engine), | |
1871 | FW_REG_READ | FW_REG_WRITE); | |
1872 | ||
1873 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1874 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1875 | FW_REG_READ); | |
1876 | ||
1877 | engine->fw_domains = fw_domains; | |
1878 | ||
bb45438f TU |
1879 | tasklet_init(&engine->irq_tasklet, |
1880 | intel_lrc_irq_handler, (unsigned long)engine); | |
1881 | ||
1882 | logical_ring_init_platform_invariants(engine); | |
1883 | logical_ring_default_vfuncs(engine); | |
1884 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1885 | } |
1886 | ||
a19d6ff2 TU |
1887 | static int |
1888 | logical_ring_init(struct intel_engine_cs *engine) | |
1889 | { | |
1890 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1891 | int ret; | |
1892 | ||
019bf277 | 1893 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1894 | if (ret) |
1895 | goto error; | |
1896 | ||
a19d6ff2 TU |
1897 | /* And setup the hardware status page. */ |
1898 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1899 | if (ret) { | |
1900 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1901 | goto error; | |
1902 | } | |
1903 | ||
1904 | return 0; | |
1905 | ||
1906 | error: | |
1907 | intel_logical_ring_cleanup(engine); | |
1908 | return ret; | |
1909 | } | |
1910 | ||
88d2ba2e | 1911 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1912 | { |
1913 | struct drm_i915_private *dev_priv = engine->i915; | |
1914 | int ret; | |
1915 | ||
bb45438f TU |
1916 | logical_ring_setup(engine); |
1917 | ||
a19d6ff2 TU |
1918 | if (HAS_L3_DPF(dev_priv)) |
1919 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1920 | ||
1921 | /* Override some for render ring. */ | |
1922 | if (INTEL_GEN(dev_priv) >= 9) | |
1923 | engine->init_hw = gen9_init_render_ring; | |
1924 | else | |
1925 | engine->init_hw = gen8_init_render_ring; | |
1926 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1927 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1928 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1929 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1930 | |
56c0f1a7 | 1931 | ret = intel_engine_create_scratch(engine, 4096); |
a19d6ff2 TU |
1932 | if (ret) |
1933 | return ret; | |
1934 | ||
1935 | ret = intel_init_workaround_bb(engine); | |
1936 | if (ret) { | |
1937 | /* | |
1938 | * We continue even if we fail to initialize WA batch | |
1939 | * because we only expect rare glitches but nothing | |
1940 | * critical to prevent us from using GPU | |
1941 | */ | |
1942 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1943 | ret); | |
1944 | } | |
1945 | ||
d038fc7e | 1946 | return logical_ring_init(engine); |
a19d6ff2 TU |
1947 | } |
1948 | ||
88d2ba2e | 1949 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1950 | { |
1951 | logical_ring_setup(engine); | |
1952 | ||
1953 | return logical_ring_init(engine); | |
454afebd OM |
1954 | } |
1955 | ||
0cea6502 | 1956 | static u32 |
c033666a | 1957 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1958 | { |
1959 | u32 rpcs = 0; | |
1960 | ||
1961 | /* | |
1962 | * No explicit RPCS request is needed to ensure full | |
1963 | * slice/subslice/EU enablement prior to Gen9. | |
1964 | */ | |
c033666a | 1965 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1966 | return 0; |
1967 | ||
1968 | /* | |
1969 | * Starting in Gen9, render power gating can leave | |
1970 | * slice/subslice/EU in a partially enabled state. We | |
1971 | * must make an explicit request through RPCS for full | |
1972 | * enablement. | |
1973 | */ | |
43b67998 | 1974 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1975 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1976 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1977 | GEN8_RPCS_S_CNT_SHIFT; |
1978 | rpcs |= GEN8_RPCS_ENABLE; | |
1979 | } | |
1980 | ||
43b67998 | 1981 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1982 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1983 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1984 | GEN8_RPCS_SS_CNT_SHIFT; |
1985 | rpcs |= GEN8_RPCS_ENABLE; | |
1986 | } | |
1987 | ||
43b67998 ID |
1988 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1989 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1990 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1991 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1992 | GEN8_RPCS_EU_MAX_SHIFT; |
1993 | rpcs |= GEN8_RPCS_ENABLE; | |
1994 | } | |
1995 | ||
1996 | return rpcs; | |
1997 | } | |
1998 | ||
0bc40be8 | 1999 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2000 | { |
2001 | u32 indirect_ctx_offset; | |
2002 | ||
c033666a | 2003 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 2004 | default: |
c033666a | 2005 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
2006 | /* fall through */ |
2007 | case 9: | |
2008 | indirect_ctx_offset = | |
2009 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2010 | break; | |
2011 | case 8: | |
2012 | indirect_ctx_offset = | |
2013 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2014 | break; | |
2015 | } | |
2016 | ||
2017 | return indirect_ctx_offset; | |
2018 | } | |
2019 | ||
a3aabe86 CW |
2020 | static void execlists_init_reg_state(u32 *reg_state, |
2021 | struct i915_gem_context *ctx, | |
2022 | struct intel_engine_cs *engine, | |
2023 | struct intel_ring *ring) | |
8670d6f9 | 2024 | { |
a3aabe86 CW |
2025 | struct drm_i915_private *dev_priv = engine->i915; |
2026 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
8670d6f9 OM |
2027 | |
2028 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2029 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2030 | * only for the first context restore: on a subsequent save, the GPU will | |
2031 | * recreate this batchbuffer with new values (including all the missing | |
2032 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 2033 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
2034 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
2035 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
2036 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
2037 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
2038 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
c033666a | 2039 | (HAS_RESOURCE_STREAMER(dev_priv) ? |
a3aabe86 | 2040 | CTX_CTRL_RS_CTX_ENABLE : 0))); |
0bc40be8 TU |
2041 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
2042 | 0); | |
2043 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
2044 | 0); | |
0bc40be8 TU |
2045 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
2046 | RING_START(engine->mmio_base), 0); | |
2047 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
2048 | RING_CTL(engine->mmio_base), | |
62ae14b1 | 2049 | RING_CTL_SIZE(ring->size) | RING_VALID); |
0bc40be8 TU |
2050 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
2051 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
2052 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
2053 | RING_BBADDR(engine->mmio_base), 0); | |
2054 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
2055 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 2056 | RING_BB_PPGTT); |
0bc40be8 TU |
2057 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
2058 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
2059 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
2060 | RING_SBBADDR(engine->mmio_base), 0); | |
2061 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
2062 | RING_SBBSTATE(engine->mmio_base), 0); | |
2063 | if (engine->id == RCS) { | |
2064 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
2065 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
2066 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
2067 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
2068 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2069 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
48bb74e4 | 2070 | if (engine->wa_ctx.vma) { |
0bc40be8 | 2071 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 2072 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d AS |
2073 | |
2074 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2075 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2076 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2077 | ||
2078 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 2079 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
2080 | |
2081 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2082 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2083 | 0x01; | |
2084 | } | |
8670d6f9 | 2085 | } |
0d925ea0 | 2086 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
2087 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
2088 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 2089 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
2090 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
2091 | 0); | |
2092 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
2093 | 0); | |
2094 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
2095 | 0); | |
2096 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2097 | 0); | |
2098 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2099 | 0); | |
2100 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2101 | 0); | |
2102 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2103 | 0); | |
2104 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2105 | 0); | |
d7b2633d | 2106 | |
2dba3239 MT |
2107 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2108 | /* 64b PPGTT (48bit canonical) | |
2109 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2110 | * other PDP Descriptors are ignored. | |
2111 | */ | |
2112 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2113 | } else { | |
2114 | /* 32b PPGTT | |
2115 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2116 | * With dynamic page allocation, PDPs may not be allocated at | |
2117 | * this point. Point the unallocated PDPs to the scratch page | |
2118 | */ | |
c6a2ac71 | 2119 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2120 | } |
2121 | ||
0bc40be8 | 2122 | if (engine->id == RCS) { |
8670d6f9 | 2123 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 | 2124 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
c033666a | 2125 | make_rpcs(dev_priv)); |
8670d6f9 | 2126 | } |
a3aabe86 CW |
2127 | } |
2128 | ||
2129 | static int | |
2130 | populate_lr_context(struct i915_gem_context *ctx, | |
2131 | struct drm_i915_gem_object *ctx_obj, | |
2132 | struct intel_engine_cs *engine, | |
2133 | struct intel_ring *ring) | |
2134 | { | |
2135 | void *vaddr; | |
2136 | int ret; | |
2137 | ||
2138 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2139 | if (ret) { | |
2140 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2141 | return ret; | |
2142 | } | |
2143 | ||
2144 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2145 | if (IS_ERR(vaddr)) { | |
2146 | ret = PTR_ERR(vaddr); | |
2147 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2148 | return ret; | |
2149 | } | |
a4f5ea64 | 2150 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
2151 | |
2152 | /* The second page of the context object contains some fields which must | |
2153 | * be set up prior to the first execution. */ | |
2154 | ||
2155 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
2156 | ctx, engine, ring); | |
8670d6f9 | 2157 | |
7d774cac | 2158 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2159 | |
2160 | return 0; | |
2161 | } | |
2162 | ||
c5d46ee2 DG |
2163 | /** |
2164 | * intel_lr_context_size() - return the size of the context for an engine | |
14bb2c11 | 2165 | * @engine: which engine to find the context size for |
c5d46ee2 DG |
2166 | * |
2167 | * Each engine may require a different amount of space for a context image, | |
2168 | * so when allocating (or copying) an image, this function can be used to | |
2169 | * find the right size for the specific engine. | |
2170 | * | |
2171 | * Return: size (in bytes) of an engine-specific context image | |
2172 | * | |
2173 | * Note: this size includes the HWSP, which is part of the context image | |
2174 | * in LRC mode, but does not include the "shared data page" used with | |
2175 | * GuC submission. The caller should account for this if using the GuC. | |
2176 | */ | |
0bc40be8 | 2177 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2178 | { |
2179 | int ret = 0; | |
2180 | ||
c033666a | 2181 | WARN_ON(INTEL_GEN(engine->i915) < 8); |
8c857917 | 2182 | |
0bc40be8 | 2183 | switch (engine->id) { |
8c857917 | 2184 | case RCS: |
c033666a | 2185 | if (INTEL_GEN(engine->i915) >= 9) |
468c6816 MN |
2186 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2187 | else | |
2188 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2189 | break; |
2190 | case VCS: | |
2191 | case BCS: | |
2192 | case VECS: | |
2193 | case VCS2: | |
2194 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2195 | break; | |
2196 | } | |
2197 | ||
2198 | return ret; | |
ede7d42b OM |
2199 | } |
2200 | ||
e2efd130 | 2201 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2202 | struct intel_engine_cs *engine) |
ede7d42b | 2203 | { |
8c857917 | 2204 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2205 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2206 | struct i915_vma *vma; |
8c857917 | 2207 | uint32_t context_size; |
7e37f889 | 2208 | struct intel_ring *ring; |
8c857917 OM |
2209 | int ret; |
2210 | ||
9021ad03 | 2211 | WARN_ON(ce->state); |
ede7d42b | 2212 | |
0bc40be8 | 2213 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2214 | |
d1675198 AD |
2215 | /* One extra page as the sharing data between driver and GuC */ |
2216 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2217 | ||
12d79d78 | 2218 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 2219 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2220 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2221 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2222 | } |
2223 | ||
bf3783e5 CW |
2224 | vma = i915_vma_create(ctx_obj, &ctx->i915->ggtt.base, NULL); |
2225 | if (IS_ERR(vma)) { | |
2226 | ret = PTR_ERR(vma); | |
2227 | goto error_deref_obj; | |
2228 | } | |
2229 | ||
7e37f889 | 2230 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2231 | if (IS_ERR(ring)) { |
2232 | ret = PTR_ERR(ring); | |
e84fe803 | 2233 | goto error_deref_obj; |
8670d6f9 OM |
2234 | } |
2235 | ||
dca33ecc | 2236 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2237 | if (ret) { |
2238 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2239 | goto error_ring_free; |
84c2377f OM |
2240 | } |
2241 | ||
dca33ecc | 2242 | ce->ring = ring; |
bf3783e5 | 2243 | ce->state = vma; |
9021ad03 | 2244 | ce->initialised = engine->init_context == NULL; |
ede7d42b OM |
2245 | |
2246 | return 0; | |
8670d6f9 | 2247 | |
dca33ecc | 2248 | error_ring_free: |
7e37f889 | 2249 | intel_ring_free(ring); |
e84fe803 | 2250 | error_deref_obj: |
f8c417cd | 2251 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2252 | return ret; |
ede7d42b | 2253 | } |
3e5b6f05 | 2254 | |
821ed7df | 2255 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2256 | { |
e2f80391 | 2257 | struct intel_engine_cs *engine; |
bafb2f7d | 2258 | struct i915_gem_context *ctx; |
3b3f1650 | 2259 | enum intel_engine_id id; |
bafb2f7d CW |
2260 | |
2261 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2262 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2263 | * that stored in context. As we only write new commands from | |
2264 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2265 | * starts reading from its RING_HEAD from the context, it may try to | |
2266 | * execute that junk and die. | |
2267 | * | |
2268 | * So to avoid that we reset the context images upon resume. For | |
2269 | * simplicity, we just zero everything out. | |
2270 | */ | |
2271 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
3b3f1650 | 2272 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2273 | struct intel_context *ce = &ctx->engine[engine->id]; |
2274 | u32 *reg; | |
3e5b6f05 | 2275 | |
bafb2f7d CW |
2276 | if (!ce->state) |
2277 | continue; | |
7d774cac | 2278 | |
bafb2f7d CW |
2279 | reg = i915_gem_object_pin_map(ce->state->obj, |
2280 | I915_MAP_WB); | |
2281 | if (WARN_ON(IS_ERR(reg))) | |
2282 | continue; | |
3e5b6f05 | 2283 | |
bafb2f7d CW |
2284 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2285 | reg[CTX_RING_HEAD+1] = 0; | |
2286 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2287 | |
a4f5ea64 | 2288 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2289 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2290 | |
bafb2f7d CW |
2291 | ce->ring->head = ce->ring->tail = 0; |
2292 | ce->ring->last_retired_head = -1; | |
2293 | intel_ring_update_space(ce->ring); | |
2294 | } | |
3e5b6f05 TD |
2295 | } |
2296 | } |