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drm/i915: Update some flush helpers to take request structures
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_lrc.c
CommitLineData
b20385f1
OM
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
28 *
29 */
30
73e4d07f
OM
31/**
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
33 *
34 * Motivation:
b20385f1
OM
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
38 *
73e4d07f
OM
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
42 *
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
47 *
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
55 *
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
58 *
59 * LRC implementation:
60 * Regarding the creation of contexts, we have:
61 *
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
65 *
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
69 *
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
72 *
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
77 * contexts:
78 *
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
83 * so on.
84 *
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
88 *
89 * Execlists implementation:
b20385f1
OM
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
73e4d07f
OM
92 * This method works as follows:
93 *
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
101 * context itself.
102 *
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
108 *
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
114 *
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
122 *
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
132 *
b20385f1
OM
133 */
134
135#include <drm/drmP.h>
136#include <drm/i915_drm.h>
137#include "i915_drv.h"
127f1003 138
468c6816 139#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
8c857917
OM
140#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
142
e981e7b1
TD
143#define RING_EXECLIST_QFULL (1 << 0x2)
144#define RING_EXECLIST1_VALID (1 << 0x3)
145#define RING_EXECLIST0_VALID (1 << 0x4)
146#define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147#define RING_EXECLIST1_ACTIVE (1 << 0x11)
148#define RING_EXECLIST0_ACTIVE (1 << 0x12)
149
150#define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151#define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153#define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
8670d6f9
OM
156
157#define CTX_LRI_HEADER_0 0x01
158#define CTX_CONTEXT_CONTROL 0x02
159#define CTX_RING_HEAD 0x04
160#define CTX_RING_TAIL 0x06
161#define CTX_RING_BUFFER_START 0x08
162#define CTX_RING_BUFFER_CONTROL 0x0a
163#define CTX_BB_HEAD_U 0x0c
164#define CTX_BB_HEAD_L 0x0e
165#define CTX_BB_STATE 0x10
166#define CTX_SECOND_BB_HEAD_U 0x12
167#define CTX_SECOND_BB_HEAD_L 0x14
168#define CTX_SECOND_BB_STATE 0x16
169#define CTX_BB_PER_CTX_PTR 0x18
170#define CTX_RCS_INDIRECT_CTX 0x1a
171#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172#define CTX_LRI_HEADER_1 0x21
173#define CTX_CTX_TIMESTAMP 0x22
174#define CTX_PDP3_UDW 0x24
175#define CTX_PDP3_LDW 0x26
176#define CTX_PDP2_UDW 0x28
177#define CTX_PDP2_LDW 0x2a
178#define CTX_PDP1_UDW 0x2c
179#define CTX_PDP1_LDW 0x2e
180#define CTX_PDP0_UDW 0x30
181#define CTX_PDP0_LDW 0x32
182#define CTX_LRI_HEADER_2 0x41
183#define CTX_R_PWR_CLK_STATE 0x42
184#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
185
84b790f8
BW
186#define GEN8_CTX_VALID (1<<0)
187#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188#define GEN8_CTX_FORCE_RESTORE (1<<2)
189#define GEN8_CTX_L3LLC_COHERENT (1<<5)
190#define GEN8_CTX_PRIVILEGE (1<<8)
e5815a2e
MT
191
192#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
d7b2633d 193 const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
e5815a2e
MT
194 ppgtt->pdp.page_directory[n]->daddr : \
195 ppgtt->scratch_pd->daddr; \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
198}
199
84b790f8
BW
200enum {
201 ADVANCED_CONTEXT = 0,
202 LEGACY_CONTEXT,
203 ADVANCED_AD_CONTEXT,
204 LEGACY_64B_CONTEXT
205};
206#define GEN8_CTX_MODE_SHIFT 3
207enum {
208 FAULT_AND_HANG = 0,
209 FAULT_AND_HALT, /* Debug only */
210 FAULT_AND_STREAM,
211 FAULT_AND_CONTINUE /* Unsupported */
212};
213#define GEN8_CTX_ID_SHIFT 32
17ee950d 214#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
84b790f8 215
7ba717cf
TD
216static int intel_lr_context_pin(struct intel_engine_cs *ring,
217 struct intel_context *ctx);
218
73e4d07f
OM
219/**
220 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
221 * @dev: DRM device.
222 * @enable_execlists: value of i915.enable_execlists module parameter.
223 *
224 * Only certain platforms support Execlists (the prerequisites being
27401d12 225 * support for Logical Ring Contexts and Aliasing PPGTT or better).
73e4d07f
OM
226 *
227 * Return: 1 if Execlists is supported and has to be enabled.
228 */
127f1003
OM
229int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
230{
bd84b1e9
DV
231 WARN_ON(i915.enable_ppgtt == -1);
232
70ee45e1
DL
233 if (INTEL_INFO(dev)->gen >= 9)
234 return 1;
235
127f1003
OM
236 if (enable_execlists == 0)
237 return 0;
238
14bf993e
OM
239 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
240 i915.use_mmio_flip >= 0)
127f1003
OM
241 return 1;
242
243 return 0;
244}
ede7d42b 245
73e4d07f
OM
246/**
247 * intel_execlists_ctx_id() - get the Execlists Context ID
248 * @ctx_obj: Logical Ring Context backing object.
249 *
250 * Do not confuse with ctx->id! Unfortunately we have a name overload
251 * here: the old context ID we pass to userspace as a handler so that
252 * they can refer to a context, and the new context ID we pass to the
253 * ELSP so that the GPU can inform us of the context status via
254 * interrupts.
255 *
256 * Return: 20-bits globally unique context ID.
257 */
84b790f8
BW
258u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
259{
260 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
261
262 /* LRCA is required to be 4K aligned so the more significant 20 bits
263 * are globally unique */
264 return lrca >> 12;
265}
266
203a571b
NH
267static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
268 struct drm_i915_gem_object *ctx_obj)
84b790f8 269{
203a571b 270 struct drm_device *dev = ring->dev;
84b790f8
BW
271 uint64_t desc;
272 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
acdd884a
MT
273
274 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
84b790f8
BW
275
276 desc = GEN8_CTX_VALID;
277 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
51847fb9
AS
278 if (IS_GEN8(ctx_obj->base.dev))
279 desc |= GEN8_CTX_L3LLC_COHERENT;
84b790f8
BW
280 desc |= GEN8_CTX_PRIVILEGE;
281 desc |= lrca;
282 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
283
284 /* TODO: WaDisableLiteRestore when we start using semaphore
285 * signalling between Command Streamers */
286 /* desc |= GEN8_CTX_FORCE_RESTORE; */
287
203a571b
NH
288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 if (IS_GEN9(dev) &&
290 INTEL_REVID(dev) <= SKL_REVID_B0 &&
291 (ring->id == BCS || ring->id == VCS ||
292 ring->id == VECS || ring->id == VCS2))
293 desc |= GEN8_CTX_FORCE_RESTORE;
294
84b790f8
BW
295 return desc;
296}
297
298static void execlists_elsp_write(struct intel_engine_cs *ring,
299 struct drm_i915_gem_object *ctx_obj0,
300 struct drm_i915_gem_object *ctx_obj1)
301{
6e7cc470
TU
302 struct drm_device *dev = ring->dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
84b790f8
BW
304 uint64_t temp = 0;
305 uint32_t desc[4];
306
307 /* XXX: You must always write both descriptors in the order below. */
308 if (ctx_obj1)
203a571b 309 temp = execlists_ctx_descriptor(ring, ctx_obj1);
84b790f8
BW
310 else
311 temp = 0;
312 desc[1] = (u32)(temp >> 32);
313 desc[0] = (u32)temp;
314
203a571b 315 temp = execlists_ctx_descriptor(ring, ctx_obj0);
84b790f8
BW
316 desc[3] = (u32)(temp >> 32);
317 desc[2] = (u32)temp;
318
a6111f7b
CW
319 spin_lock(&dev_priv->uncore.lock);
320 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
321 I915_WRITE_FW(RING_ELSP(ring), desc[1]);
322 I915_WRITE_FW(RING_ELSP(ring), desc[0]);
323 I915_WRITE_FW(RING_ELSP(ring), desc[3]);
6daccb0b 324
84b790f8 325 /* The context is automatically loaded after the following */
a6111f7b 326 I915_WRITE_FW(RING_ELSP(ring), desc[2]);
84b790f8
BW
327
328 /* ELSP is a wo register, so use another nearby reg for posting instead */
a6111f7b
CW
329 POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
330 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
331 spin_unlock(&dev_priv->uncore.lock);
84b790f8
BW
332}
333
7ba717cf
TD
334static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
335 struct drm_i915_gem_object *ring_obj,
d7b2633d 336 struct i915_hw_ppgtt *ppgtt,
7ba717cf 337 u32 tail)
ae1250b9
OM
338{
339 struct page *page;
340 uint32_t *reg_state;
341
342 page = i915_gem_object_get_page(ctx_obj, 1);
343 reg_state = kmap_atomic(page);
344
345 reg_state[CTX_RING_TAIL+1] = tail;
7ba717cf 346 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
ae1250b9 347
d7b2633d
MT
348 /* True PPGTT with dynamic page allocation: update PDP registers and
349 * point the unallocated PDPs to the scratch page
350 */
351 if (ppgtt) {
352 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
353 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
354 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
355 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
356 }
357
ae1250b9
OM
358 kunmap_atomic(reg_state);
359
360 return 0;
361}
362
cd0707cb
DG
363static void execlists_submit_contexts(struct intel_engine_cs *ring,
364 struct intel_context *to0, u32 tail0,
365 struct intel_context *to1, u32 tail1)
84b790f8 366{
7ba717cf
TD
367 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
368 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
84b790f8 369 struct drm_i915_gem_object *ctx_obj1 = NULL;
7ba717cf 370 struct intel_ringbuffer *ringbuf1 = NULL;
84b790f8 371
84b790f8 372 BUG_ON(!ctx_obj0);
acdd884a 373 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
7ba717cf 374 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
84b790f8 375
d7b2633d 376 execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0);
ae1250b9 377
84b790f8 378 if (to1) {
7ba717cf 379 ringbuf1 = to1->engine[ring->id].ringbuf;
84b790f8
BW
380 ctx_obj1 = to1->engine[ring->id].state;
381 BUG_ON(!ctx_obj1);
acdd884a 382 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
7ba717cf 383 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
ae1250b9 384
d7b2633d 385 execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1);
84b790f8
BW
386 }
387
388 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
84b790f8
BW
389}
390
acdd884a
MT
391static void execlists_context_unqueue(struct intel_engine_cs *ring)
392{
6d3d8274
NH
393 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
394 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
e981e7b1
TD
395
396 assert_spin_locked(&ring->execlist_lock);
acdd884a 397
779949f4
PA
398 /*
399 * If irqs are not active generate a warning as batches that finish
400 * without the irqs may get lost and a GPU Hang may occur.
401 */
402 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
403
acdd884a
MT
404 if (list_empty(&ring->execlist_queue))
405 return;
406
407 /* Try to read in pairs */
408 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
409 execlist_link) {
410 if (!req0) {
411 req0 = cursor;
6d3d8274 412 } else if (req0->ctx == cursor->ctx) {
acdd884a
MT
413 /* Same ctx: ignore first request, as second request
414 * will update tail past first request's workload */
e1fee72c 415 cursor->elsp_submitted = req0->elsp_submitted;
acdd884a 416 list_del(&req0->execlist_link);
c86ee3a9
TD
417 list_add_tail(&req0->execlist_link,
418 &ring->execlist_retired_req_list);
acdd884a
MT
419 req0 = cursor;
420 } else {
421 req1 = cursor;
422 break;
423 }
424 }
425
53292cdb
MT
426 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
427 /*
428 * WaIdleLiteRestore: make sure we never cause a lite
429 * restore with HEAD==TAIL
430 */
d63f820f 431 if (req0->elsp_submitted) {
53292cdb
MT
432 /*
433 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
434 * as we resubmit the request. See gen8_emit_request()
435 * for where we prepare the padding after the end of the
436 * request.
437 */
438 struct intel_ringbuffer *ringbuf;
439
440 ringbuf = req0->ctx->engine[ring->id].ringbuf;
441 req0->tail += 8;
442 req0->tail &= ringbuf->size - 1;
443 }
444 }
445
e1fee72c
OM
446 WARN_ON(req1 && req1->elsp_submitted);
447
6d3d8274
NH
448 execlists_submit_contexts(ring, req0->ctx, req0->tail,
449 req1 ? req1->ctx : NULL,
450 req1 ? req1->tail : 0);
e1fee72c
OM
451
452 req0->elsp_submitted++;
453 if (req1)
454 req1->elsp_submitted++;
acdd884a
MT
455}
456
e981e7b1
TD
457static bool execlists_check_remove_request(struct intel_engine_cs *ring,
458 u32 request_id)
459{
6d3d8274 460 struct drm_i915_gem_request *head_req;
e981e7b1
TD
461
462 assert_spin_locked(&ring->execlist_lock);
463
464 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 465 struct drm_i915_gem_request,
e981e7b1
TD
466 execlist_link);
467
468 if (head_req != NULL) {
469 struct drm_i915_gem_object *ctx_obj =
6d3d8274 470 head_req->ctx->engine[ring->id].state;
e981e7b1 471 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
e1fee72c
OM
472 WARN(head_req->elsp_submitted == 0,
473 "Never submitted head request\n");
474
475 if (--head_req->elsp_submitted <= 0) {
476 list_del(&head_req->execlist_link);
c86ee3a9
TD
477 list_add_tail(&head_req->execlist_link,
478 &ring->execlist_retired_req_list);
e1fee72c
OM
479 return true;
480 }
e981e7b1
TD
481 }
482 }
483
484 return false;
485}
486
73e4d07f 487/**
3f7531c3 488 * intel_lrc_irq_handler() - handle Context Switch interrupts
73e4d07f
OM
489 * @ring: Engine Command Streamer to handle.
490 *
491 * Check the unread Context Status Buffers and manage the submission of new
492 * contexts to the ELSP accordingly.
493 */
3f7531c3 494void intel_lrc_irq_handler(struct intel_engine_cs *ring)
e981e7b1
TD
495{
496 struct drm_i915_private *dev_priv = ring->dev->dev_private;
497 u32 status_pointer;
498 u8 read_pointer;
499 u8 write_pointer;
500 u32 status;
501 u32 status_id;
502 u32 submit_contexts = 0;
503
504 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
505
506 read_pointer = ring->next_context_status_buffer;
507 write_pointer = status_pointer & 0x07;
508 if (read_pointer > write_pointer)
509 write_pointer += 6;
510
511 spin_lock(&ring->execlist_lock);
512
513 while (read_pointer < write_pointer) {
514 read_pointer++;
515 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
516 (read_pointer % 6) * 8);
517 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
518 (read_pointer % 6) * 8 + 4);
519
e1fee72c
OM
520 if (status & GEN8_CTX_STATUS_PREEMPTED) {
521 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
522 if (execlists_check_remove_request(ring, status_id))
523 WARN(1, "Lite Restored request removed from queue\n");
524 } else
525 WARN(1, "Preemption without Lite Restore\n");
526 }
527
528 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
529 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
e981e7b1
TD
530 if (execlists_check_remove_request(ring, status_id))
531 submit_contexts++;
532 }
533 }
534
535 if (submit_contexts != 0)
536 execlists_context_unqueue(ring);
537
538 spin_unlock(&ring->execlist_lock);
539
540 WARN(submit_contexts > 2, "More than two context complete events?\n");
541 ring->next_context_status_buffer = write_pointer % 6;
542
543 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
544 ((u32)ring->next_context_status_buffer & 0x07) << 8);
545}
546
acdd884a
MT
547static int execlists_context_queue(struct intel_engine_cs *ring,
548 struct intel_context *to,
2d12955a
NH
549 u32 tail,
550 struct drm_i915_gem_request *request)
acdd884a 551{
6d3d8274 552 struct drm_i915_gem_request *cursor;
f1ad5a1f 553 int num_elements = 0;
acdd884a 554
7ba717cf
TD
555 if (to != ring->default_context)
556 intel_lr_context_pin(ring, to);
557
2d12955a
NH
558 if (!request) {
559 /*
560 * If there isn't a request associated with this submission,
561 * create one as a temporary holder.
562 */
2d12955a
NH
563 request = kzalloc(sizeof(*request), GFP_KERNEL);
564 if (request == NULL)
565 return -ENOMEM;
2d12955a 566 request->ring = ring;
6d3d8274 567 request->ctx = to;
b3a38998 568 kref_init(&request->ref);
b3a38998 569 i915_gem_context_reference(request->ctx);
21076372 570 } else {
b3a38998 571 i915_gem_request_reference(request);
21076372 572 WARN_ON(to != request->ctx);
2d12955a 573 }
72f95afa 574 request->tail = tail;
2d12955a 575
b5eba372 576 spin_lock_irq(&ring->execlist_lock);
acdd884a 577
f1ad5a1f
OM
578 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
579 if (++num_elements > 2)
580 break;
581
582 if (num_elements > 2) {
6d3d8274 583 struct drm_i915_gem_request *tail_req;
f1ad5a1f
OM
584
585 tail_req = list_last_entry(&ring->execlist_queue,
6d3d8274 586 struct drm_i915_gem_request,
f1ad5a1f
OM
587 execlist_link);
588
6d3d8274 589 if (to == tail_req->ctx) {
f1ad5a1f 590 WARN(tail_req->elsp_submitted != 0,
7ba717cf 591 "More than 2 already-submitted reqs queued\n");
f1ad5a1f 592 list_del(&tail_req->execlist_link);
c86ee3a9
TD
593 list_add_tail(&tail_req->execlist_link,
594 &ring->execlist_retired_req_list);
f1ad5a1f
OM
595 }
596 }
597
6d3d8274 598 list_add_tail(&request->execlist_link, &ring->execlist_queue);
f1ad5a1f 599 if (num_elements == 0)
acdd884a
MT
600 execlists_context_unqueue(ring);
601
b5eba372 602 spin_unlock_irq(&ring->execlist_lock);
acdd884a
MT
603
604 return 0;
605}
606
2f20055d 607static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
ba8b7ccb 608{
2f20055d 609 struct intel_engine_cs *ring = req->ring;
ba8b7ccb
OM
610 uint32_t flush_domains;
611 int ret;
612
613 flush_domains = 0;
614 if (ring->gpu_caches_dirty)
615 flush_domains = I915_GEM_GPU_DOMAINS;
616
2f20055d 617 ret = ring->emit_flush(req->ringbuf, req->ctx,
21076372 618 I915_GEM_GPU_DOMAINS, flush_domains);
ba8b7ccb
OM
619 if (ret)
620 return ret;
621
622 ring->gpu_caches_dirty = false;
623 return 0;
624}
625
535fbe82 626static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
ba8b7ccb
OM
627 struct list_head *vmas)
628{
535fbe82 629 const unsigned other_rings = ~intel_ring_flag(req->ring);
ba8b7ccb
OM
630 struct i915_vma *vma;
631 uint32_t flush_domains = 0;
632 bool flush_chipset = false;
633 int ret;
634
635 list_for_each_entry(vma, vmas, exec_list) {
636 struct drm_i915_gem_object *obj = vma->obj;
637
03ade511 638 if (obj->active & other_rings) {
91af127f 639 ret = i915_gem_object_sync(obj, req->ring, &req);
03ade511
CW
640 if (ret)
641 return ret;
642 }
ba8b7ccb
OM
643
644 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
645 flush_chipset |= i915_gem_clflush_object(obj, false);
646
647 flush_domains |= obj->base.write_domain;
648 }
649
650 if (flush_domains & I915_GEM_DOMAIN_GTT)
651 wmb();
652
653 /* Unconditionally invalidate gpu caches and ensure that we do flush
654 * any residual writes from the previous batch.
655 */
2f20055d 656 return logical_ring_invalidate_all_caches(req);
ba8b7ccb
OM
657}
658
40e895ce 659int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
bc0dce3f 660{
bc0dce3f
JH
661 int ret;
662
40e895ce
JH
663 if (request->ctx != request->ring->default_context) {
664 ret = intel_lr_context_pin(request->ring, request->ctx);
6689cb2b 665 if (ret)
bc0dce3f 666 return ret;
bc0dce3f
JH
667 }
668
40e895ce 669 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
bc0dce3f 670
bc0dce3f
JH
671 return 0;
672}
673
595e1eeb
CW
674static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
675 struct intel_context *ctx,
676 int bytes)
bc0dce3f
JH
677{
678 struct intel_engine_cs *ring = ringbuf->ring;
679 struct drm_i915_gem_request *request;
b4716185
CW
680 unsigned space;
681 int ret;
bc0dce3f 682
29b1b415
JH
683 /* The whole point of reserving space is to not wait! */
684 WARN_ON(ringbuf->reserved_in_use);
685
bc0dce3f
JH
686 if (intel_ring_space(ringbuf) >= bytes)
687 return 0;
688
689 list_for_each_entry(request, &ring->request_list, list) {
690 /*
691 * The request queue is per-engine, so can contain requests
692 * from multiple ringbuffers. Here, we must ignore any that
693 * aren't from the ringbuffer we're considering.
694 */
b4716185 695 if (request->ringbuf != ringbuf)
bc0dce3f
JH
696 continue;
697
698 /* Would completion of this request free enough space? */
b4716185
CW
699 space = __intel_ring_space(request->postfix, ringbuf->tail,
700 ringbuf->size);
701 if (space >= bytes)
bc0dce3f 702 break;
bc0dce3f
JH
703 }
704
595e1eeb 705 if (WARN_ON(&request->list == &ring->request_list))
bc0dce3f
JH
706 return -ENOSPC;
707
708 ret = i915_wait_request(request);
709 if (ret)
710 return ret;
711
b4716185
CW
712 ringbuf->space = space;
713 return 0;
bc0dce3f
JH
714}
715
716/*
717 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
718 * @ringbuf: Logical Ringbuffer to advance.
719 *
720 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
721 * really happens during submission is that the context and current tail will be placed
722 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
723 * point, the tail *inside* the context is updated and the ELSP written to.
724 */
725static void
726intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
727 struct intel_context *ctx,
728 struct drm_i915_gem_request *request)
729{
730 struct intel_engine_cs *ring = ringbuf->ring;
731
732 intel_logical_ring_advance(ringbuf);
733
734 if (intel_ring_stopped(ring))
735 return;
736
737 execlists_context_queue(ring, ctx, ringbuf->tail, request);
738}
739
bc0dce3f
JH
740static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
741 struct intel_context *ctx)
742{
743 uint32_t __iomem *virt;
744 int rem = ringbuf->size - ringbuf->tail;
745
29b1b415
JH
746 /* Can't wrap if space has already been reserved! */
747 WARN_ON(ringbuf->reserved_in_use);
748
bc0dce3f
JH
749 if (ringbuf->space < rem) {
750 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
751
752 if (ret)
753 return ret;
754 }
755
756 virt = ringbuf->virtual_start + ringbuf->tail;
757 rem /= 4;
758 while (rem--)
759 iowrite32(MI_NOOP, virt++);
760
761 ringbuf->tail = 0;
762 intel_ring_update_space(ringbuf);
763
764 return 0;
765}
766
767static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
768 struct intel_context *ctx, int bytes)
769{
770 int ret;
771
29b1b415
JH
772 /*
773 * Add on the reserved size to the request to make sure that after
774 * the intended commands have been emitted, there is guaranteed to
775 * still be enough free space to send them to the hardware.
776 */
777 if (!ringbuf->reserved_in_use)
778 bytes += ringbuf->reserved_size;
779
bc0dce3f
JH
780 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
781 ret = logical_ring_wrap_buffer(ringbuf, ctx);
782 if (unlikely(ret))
783 return ret;
29b1b415
JH
784
785 if(ringbuf->reserved_size) {
786 uint32_t size = ringbuf->reserved_size;
787
788 intel_ring_reserved_space_cancel(ringbuf);
789 intel_ring_reserved_space_reserve(ringbuf, size);
790 }
bc0dce3f
JH
791 }
792
793 if (unlikely(ringbuf->space < bytes)) {
794 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
795 if (unlikely(ret))
796 return ret;
797 }
798
799 return 0;
800}
801
802/**
803 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
804 *
805 * @ringbuf: Logical ringbuffer.
806 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
807 *
808 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
809 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
810 * and also preallocates a request (every workload submission is still mediated through
811 * requests, same as it did with legacy ringbuffer submission).
812 *
813 * Return: non-zero if the ringbuffer is not ready to be written to.
814 */
815static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
816 struct intel_context *ctx, int num_dwords)
817{
217e46b5 818 struct drm_i915_gem_request *req;
bc0dce3f
JH
819 struct intel_engine_cs *ring = ringbuf->ring;
820 struct drm_device *dev = ring->dev;
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 int ret;
823
824 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
825 dev_priv->mm.interruptible);
826 if (ret)
827 return ret;
828
829 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
830 if (ret)
831 return ret;
832
833 /* Preallocate the olr before touching the ring */
217e46b5 834 ret = i915_gem_request_alloc(ring, ctx, &req);
bc0dce3f
JH
835 if (ret)
836 return ret;
837
838 ringbuf->space -= num_dwords * sizeof(uint32_t);
839 return 0;
840}
841
73e4d07f
OM
842/**
843 * execlists_submission() - submit a batchbuffer for execution, Execlists style
844 * @dev: DRM device.
845 * @file: DRM file.
846 * @ring: Engine Command Streamer to submit to.
847 * @ctx: Context to employ for this submission.
848 * @args: execbuffer call arguments.
849 * @vmas: list of vmas.
850 * @batch_obj: the batchbuffer to submit.
851 * @exec_start: batchbuffer start virtual address pointer.
8e004efc 852 * @dispatch_flags: translated execbuffer call flags.
73e4d07f
OM
853 *
854 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
855 * away the submission details of the execbuffer ioctl call.
856 *
857 * Return: non-zero if the submission fails.
858 */
5f19e2bf 859int intel_execlists_submission(struct i915_execbuffer_params *params,
454afebd 860 struct drm_i915_gem_execbuffer2 *args,
5f19e2bf 861 struct list_head *vmas)
454afebd 862{
5f19e2bf
JH
863 struct drm_device *dev = params->dev;
864 struct intel_engine_cs *ring = params->ring;
ba8b7ccb 865 struct drm_i915_private *dev_priv = dev->dev_private;
5f19e2bf
JH
866 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
867 u64 exec_start;
ba8b7ccb
OM
868 int instp_mode;
869 u32 instp_mask;
870 int ret;
871
872 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
873 instp_mask = I915_EXEC_CONSTANTS_MASK;
874 switch (instp_mode) {
875 case I915_EXEC_CONSTANTS_REL_GENERAL:
876 case I915_EXEC_CONSTANTS_ABSOLUTE:
877 case I915_EXEC_CONSTANTS_REL_SURFACE:
878 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
879 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
880 return -EINVAL;
881 }
882
883 if (instp_mode != dev_priv->relative_constants_mode) {
884 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
885 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
886 return -EINVAL;
887 }
888
889 /* The HW changed the meaning on this bit on gen6 */
890 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
891 }
892 break;
893 default:
894 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
895 return -EINVAL;
896 }
897
898 if (args->num_cliprects != 0) {
899 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
900 return -EINVAL;
901 } else {
902 if (args->DR4 == 0xffffffff) {
903 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
904 args->DR4 = 0;
905 }
906
907 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
908 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
909 return -EINVAL;
910 }
911 }
912
913 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
914 DRM_DEBUG("sol reset is gen7 only\n");
915 return -EINVAL;
916 }
917
535fbe82 918 ret = execlists_move_to_gpu(params->request, vmas);
ba8b7ccb
OM
919 if (ret)
920 return ret;
921
922 if (ring == &dev_priv->ring[RCS] &&
923 instp_mode != dev_priv->relative_constants_mode) {
5f19e2bf 924 ret = intel_logical_ring_begin(ringbuf, params->ctx, 4);
ba8b7ccb
OM
925 if (ret)
926 return ret;
927
928 intel_logical_ring_emit(ringbuf, MI_NOOP);
929 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
930 intel_logical_ring_emit(ringbuf, INSTPM);
931 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
932 intel_logical_ring_advance(ringbuf);
933
934 dev_priv->relative_constants_mode = instp_mode;
935 }
936
5f19e2bf
JH
937 exec_start = params->batch_obj_vm_offset +
938 args->batch_start_offset;
939
940 ret = ring->emit_bb_start(ringbuf, params->ctx, exec_start, params->dispatch_flags);
ba8b7ccb
OM
941 if (ret)
942 return ret;
943
95c24161 944 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
5e4be7bd 945
8a8edb59 946 i915_gem_execbuffer_move_to_active(vmas, params->request);
adeca76d 947 i915_gem_execbuffer_retire_commands(params);
ba8b7ccb 948
454afebd
OM
949 return 0;
950}
951
c86ee3a9
TD
952void intel_execlists_retire_requests(struct intel_engine_cs *ring)
953{
6d3d8274 954 struct drm_i915_gem_request *req, *tmp;
c86ee3a9
TD
955 struct list_head retired_list;
956
957 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
958 if (list_empty(&ring->execlist_retired_req_list))
959 return;
960
961 INIT_LIST_HEAD(&retired_list);
b5eba372 962 spin_lock_irq(&ring->execlist_lock);
c86ee3a9 963 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
b5eba372 964 spin_unlock_irq(&ring->execlist_lock);
c86ee3a9
TD
965
966 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
6d3d8274 967 struct intel_context *ctx = req->ctx;
7ba717cf
TD
968 struct drm_i915_gem_object *ctx_obj =
969 ctx->engine[ring->id].state;
970
971 if (ctx_obj && (ctx != ring->default_context))
972 intel_lr_context_unpin(ring, ctx);
c86ee3a9 973 list_del(&req->execlist_link);
f8210795 974 i915_gem_request_unreference(req);
c86ee3a9
TD
975 }
976}
977
454afebd
OM
978void intel_logical_ring_stop(struct intel_engine_cs *ring)
979{
9832b9da
OM
980 struct drm_i915_private *dev_priv = ring->dev->dev_private;
981 int ret;
982
983 if (!intel_ring_initialized(ring))
984 return;
985
986 ret = intel_ring_idle(ring);
987 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
988 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
989 ring->name, ret);
990
991 /* TODO: Is this correct with Execlists enabled? */
992 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
993 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
994 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
995 return;
996 }
997 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
454afebd
OM
998}
999
4866d729 1000int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
48e29f55 1001{
4866d729 1002 struct intel_engine_cs *ring = req->ring;
48e29f55
OM
1003 int ret;
1004
1005 if (!ring->gpu_caches_dirty)
1006 return 0;
1007
4866d729 1008 ret = ring->emit_flush(req->ringbuf, req->ctx, 0, I915_GEM_GPU_DOMAINS);
48e29f55
OM
1009 if (ret)
1010 return ret;
1011
1012 ring->gpu_caches_dirty = false;
1013 return 0;
1014}
1015
dcb4c12a
OM
1016static int intel_lr_context_pin(struct intel_engine_cs *ring,
1017 struct intel_context *ctx)
1018{
1019 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
7ba717cf 1020 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
dcb4c12a
OM
1021 int ret = 0;
1022
1023 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
a7cbedec 1024 if (ctx->engine[ring->id].pin_count++ == 0) {
dcb4c12a
OM
1025 ret = i915_gem_obj_ggtt_pin(ctx_obj,
1026 GEN8_LR_CONTEXT_ALIGN, 0);
1027 if (ret)
a7cbedec 1028 goto reset_pin_count;
7ba717cf
TD
1029
1030 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1031 if (ret)
1032 goto unpin_ctx_obj;
dcb4c12a
OM
1033 }
1034
7ba717cf
TD
1035 return ret;
1036
1037unpin_ctx_obj:
1038 i915_gem_object_ggtt_unpin(ctx_obj);
a7cbedec
MK
1039reset_pin_count:
1040 ctx->engine[ring->id].pin_count = 0;
7ba717cf 1041
dcb4c12a
OM
1042 return ret;
1043}
1044
1045void intel_lr_context_unpin(struct intel_engine_cs *ring,
1046 struct intel_context *ctx)
1047{
1048 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
7ba717cf 1049 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
dcb4c12a
OM
1050
1051 if (ctx_obj) {
1052 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
a7cbedec 1053 if (--ctx->engine[ring->id].pin_count == 0) {
7ba717cf 1054 intel_unpin_ringbuffer_obj(ringbuf);
dcb4c12a 1055 i915_gem_object_ggtt_unpin(ctx_obj);
7ba717cf 1056 }
dcb4c12a
OM
1057 }
1058}
1059
e2be4faf 1060static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
771b9a53
MT
1061{
1062 int ret, i;
e2be4faf
JH
1063 struct intel_engine_cs *ring = req->ring;
1064 struct intel_ringbuffer *ringbuf = req->ringbuf;
771b9a53
MT
1065 struct drm_device *dev = ring->dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 struct i915_workarounds *w = &dev_priv->workarounds;
1068
e6c1abb7 1069 if (WARN_ON_ONCE(w->count == 0))
771b9a53
MT
1070 return 0;
1071
1072 ring->gpu_caches_dirty = true;
4866d729 1073 ret = logical_ring_flush_all_caches(req);
771b9a53
MT
1074 if (ret)
1075 return ret;
1076
e2be4faf 1077 ret = intel_logical_ring_begin(ringbuf, req->ctx, w->count * 2 + 2);
771b9a53
MT
1078 if (ret)
1079 return ret;
1080
1081 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1082 for (i = 0; i < w->count; i++) {
1083 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1084 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1085 }
1086 intel_logical_ring_emit(ringbuf, MI_NOOP);
1087
1088 intel_logical_ring_advance(ringbuf);
1089
1090 ring->gpu_caches_dirty = true;
4866d729 1091 ret = logical_ring_flush_all_caches(req);
771b9a53
MT
1092 if (ret)
1093 return ret;
1094
1095 return 0;
1096}
1097
17ee950d
AS
1098#define wa_ctx_emit(batch, cmd) \
1099 do { \
1100 if (WARN_ON(index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1101 return -ENOSPC; \
1102 } \
1103 batch[index++] = (cmd); \
1104 } while (0)
1105
1106static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1107 uint32_t offset,
1108 uint32_t start_alignment)
1109{
1110 return wa_ctx->offset = ALIGN(offset, start_alignment);
1111}
1112
1113static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1114 uint32_t offset,
1115 uint32_t size_alignment)
1116{
1117 wa_ctx->size = offset - wa_ctx->offset;
1118
1119 WARN(wa_ctx->size % size_alignment,
1120 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1121 wa_ctx->size, size_alignment);
1122 return 0;
1123}
1124
1125/**
1126 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1127 *
1128 * @ring: only applicable for RCS
1129 * @wa_ctx: structure representing wa_ctx
1130 * offset: specifies start of the batch, should be cache-aligned. This is updated
1131 * with the offset value received as input.
1132 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1133 * @batch: page in which WA are loaded
1134 * @offset: This field specifies the start of the batch, it should be
1135 * cache-aligned otherwise it is adjusted accordingly.
1136 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1137 * initialized at the beginning and shared across all contexts but this field
1138 * helps us to have multiple batches at different offsets and select them based
1139 * on a criteria. At the moment this batch always start at the beginning of the page
1140 * and at this point we don't have multiple wa_ctx batch buffers.
1141 *
1142 * The number of WA applied are not known at the beginning; we use this field
1143 * to return the no of DWORDS written.
1144
1145 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1146 * so it adds NOOPs as padding to make it cacheline aligned.
1147 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1148 * makes a complete batch buffer.
1149 *
1150 * Return: non-zero if we exceed the PAGE_SIZE limit.
1151 */
1152
1153static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1154 struct i915_wa_ctx_bb *wa_ctx,
1155 uint32_t *const batch,
1156 uint32_t *offset)
1157{
1158 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1159
7ad00d1a
AS
1160 /* WaDisableCtxRestoreArbitration:bdw,chv */
1161 wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE);
17ee950d 1162
c82435bb
AS
1163 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1164 if (IS_BROADWELL(ring->dev)) {
1165 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1166 uint32_t l3sqc4_flush = (I915_READ(GEN8_L3SQCREG4) |
1167 GEN8_LQSC_FLUSH_COHERENT_LINES);
1168
1169 wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1));
1170 wa_ctx_emit(batch, GEN8_L3SQCREG4);
1171 wa_ctx_emit(batch, l3sqc4_flush);
1172
1173 wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6));
1174 wa_ctx_emit(batch, (PIPE_CONTROL_CS_STALL |
1175 PIPE_CONTROL_DC_FLUSH_ENABLE));
1176 wa_ctx_emit(batch, 0);
1177 wa_ctx_emit(batch, 0);
1178 wa_ctx_emit(batch, 0);
1179 wa_ctx_emit(batch, 0);
1180
1181 wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1));
1182 wa_ctx_emit(batch, GEN8_L3SQCREG4);
1183 wa_ctx_emit(batch, l3sqc4_flush & ~GEN8_LQSC_FLUSH_COHERENT_LINES);
1184 }
1185
17ee950d
AS
1186 /* Pad to end of cacheline */
1187 while (index % CACHELINE_DWORDS)
1188 wa_ctx_emit(batch, MI_NOOP);
1189
1190 /*
1191 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1192 * execution depends on the length specified in terms of cache lines
1193 * in the register CTX_RCS_INDIRECT_CTX
1194 */
1195
1196 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1197}
1198
1199/**
1200 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1201 *
1202 * @ring: only applicable for RCS
1203 * @wa_ctx: structure representing wa_ctx
1204 * offset: specifies start of the batch, should be cache-aligned.
1205 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1206 * @offset: This field specifies the start of this batch.
1207 * This batch is started immediately after indirect_ctx batch. Since we ensure
1208 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1209 *
1210 * The number of DWORDS written are returned using this field.
1211 *
1212 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1213 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1214 */
1215static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1216 struct i915_wa_ctx_bb *wa_ctx,
1217 uint32_t *const batch,
1218 uint32_t *offset)
1219{
1220 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1221
7ad00d1a
AS
1222 /* WaDisableCtxRestoreArbitration:bdw,chv */
1223 wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1224
17ee950d
AS
1225 wa_ctx_emit(batch, MI_BATCH_BUFFER_END);
1226
1227 return wa_ctx_end(wa_ctx, *offset = index, 1);
1228}
1229
1230static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1231{
1232 int ret;
1233
1234 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1235 if (!ring->wa_ctx.obj) {
1236 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1237 return -ENOMEM;
1238 }
1239
1240 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1241 if (ret) {
1242 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1243 ret);
1244 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1245 return ret;
1246 }
1247
1248 return 0;
1249}
1250
1251static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1252{
1253 if (ring->wa_ctx.obj) {
1254 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1255 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1256 ring->wa_ctx.obj = NULL;
1257 }
1258}
1259
1260static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1261{
1262 int ret;
1263 uint32_t *batch;
1264 uint32_t offset;
1265 struct page *page;
1266 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1267
1268 WARN_ON(ring->id != RCS);
1269
c4db7599
AS
1270 /* some WA perform writes to scratch page, ensure it is valid */
1271 if (ring->scratch.obj == NULL) {
1272 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1273 return -EINVAL;
1274 }
1275
17ee950d
AS
1276 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1277 if (ret) {
1278 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1279 return ret;
1280 }
1281
1282 page = i915_gem_object_get_page(wa_ctx->obj, 0);
1283 batch = kmap_atomic(page);
1284 offset = 0;
1285
1286 if (INTEL_INFO(ring->dev)->gen == 8) {
1287 ret = gen8_init_indirectctx_bb(ring,
1288 &wa_ctx->indirect_ctx,
1289 batch,
1290 &offset);
1291 if (ret)
1292 goto out;
1293
1294 ret = gen8_init_perctx_bb(ring,
1295 &wa_ctx->per_ctx,
1296 batch,
1297 &offset);
1298 if (ret)
1299 goto out;
1300 } else {
1301 WARN(INTEL_INFO(ring->dev)->gen >= 8,
1302 "WA batch buffer is not initialized for Gen%d\n",
1303 INTEL_INFO(ring->dev)->gen);
1304 lrc_destroy_wa_ctx_obj(ring);
1305 }
1306
1307out:
1308 kunmap_atomic(batch);
1309 if (ret)
1310 lrc_destroy_wa_ctx_obj(ring);
1311
1312 return ret;
1313}
1314
9b1136d5
OM
1315static int gen8_init_common_ring(struct intel_engine_cs *ring)
1316{
1317 struct drm_device *dev = ring->dev;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319
73d477f6
OM
1320 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1321 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1322
9b1136d5
OM
1323 I915_WRITE(RING_MODE_GEN7(ring),
1324 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1325 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1326 POSTING_READ(RING_MODE_GEN7(ring));
c0a03a2e 1327 ring->next_context_status_buffer = 0;
9b1136d5
OM
1328 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1329
1330 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1331
1332 return 0;
1333}
1334
1335static int gen8_init_render_ring(struct intel_engine_cs *ring)
1336{
1337 struct drm_device *dev = ring->dev;
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 int ret;
1340
1341 ret = gen8_init_common_ring(ring);
1342 if (ret)
1343 return ret;
1344
1345 /* We need to disable the AsyncFlip performance optimisations in order
1346 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1347 * programmed to '1' on all products.
1348 *
1349 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1350 */
1351 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1352
9b1136d5
OM
1353 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1354
771b9a53 1355 return init_workarounds_ring(ring);
9b1136d5
OM
1356}
1357
82ef822e
DL
1358static int gen9_init_render_ring(struct intel_engine_cs *ring)
1359{
1360 int ret;
1361
1362 ret = gen8_init_common_ring(ring);
1363 if (ret)
1364 return ret;
1365
1366 return init_workarounds_ring(ring);
1367}
1368
15648585 1369static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
21076372 1370 struct intel_context *ctx,
8e004efc 1371 u64 offset, unsigned dispatch_flags)
15648585 1372{
8e004efc 1373 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
15648585
OM
1374 int ret;
1375
21076372 1376 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
15648585
OM
1377 if (ret)
1378 return ret;
1379
1380 /* FIXME(BDW): Address space and security selectors. */
1381 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1382 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1383 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1384 intel_logical_ring_emit(ringbuf, MI_NOOP);
1385 intel_logical_ring_advance(ringbuf);
1386
1387 return 0;
1388}
1389
73d477f6
OM
1390static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1391{
1392 struct drm_device *dev = ring->dev;
1393 struct drm_i915_private *dev_priv = dev->dev_private;
1394 unsigned long flags;
1395
7cd512f1 1396 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
73d477f6
OM
1397 return false;
1398
1399 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1400 if (ring->irq_refcount++ == 0) {
1401 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1402 POSTING_READ(RING_IMR(ring->mmio_base));
1403 }
1404 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1405
1406 return true;
1407}
1408
1409static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1410{
1411 struct drm_device *dev = ring->dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 unsigned long flags;
1414
1415 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1416 if (--ring->irq_refcount == 0) {
1417 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1418 POSTING_READ(RING_IMR(ring->mmio_base));
1419 }
1420 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1421}
1422
4712274c 1423static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
21076372 1424 struct intel_context *ctx,
4712274c
OM
1425 u32 invalidate_domains,
1426 u32 unused)
1427{
1428 struct intel_engine_cs *ring = ringbuf->ring;
1429 struct drm_device *dev = ring->dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 uint32_t cmd;
1432 int ret;
1433
21076372 1434 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
4712274c
OM
1435 if (ret)
1436 return ret;
1437
1438 cmd = MI_FLUSH_DW + 1;
1439
f0a1fb10
CW
1440 /* We always require a command barrier so that subsequent
1441 * commands, such as breadcrumb interrupts, are strictly ordered
1442 * wrt the contents of the write cache being flushed to memory
1443 * (and thus being coherent from the CPU).
1444 */
1445 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1446
1447 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1448 cmd |= MI_INVALIDATE_TLB;
1449 if (ring == &dev_priv->ring[VCS])
1450 cmd |= MI_INVALIDATE_BSD;
4712274c
OM
1451 }
1452
1453 intel_logical_ring_emit(ringbuf, cmd);
1454 intel_logical_ring_emit(ringbuf,
1455 I915_GEM_HWS_SCRATCH_ADDR |
1456 MI_FLUSH_DW_USE_GTT);
1457 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1458 intel_logical_ring_emit(ringbuf, 0); /* value */
1459 intel_logical_ring_advance(ringbuf);
1460
1461 return 0;
1462}
1463
1464static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
21076372 1465 struct intel_context *ctx,
4712274c
OM
1466 u32 invalidate_domains,
1467 u32 flush_domains)
1468{
1469 struct intel_engine_cs *ring = ringbuf->ring;
1470 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
9647ff36 1471 bool vf_flush_wa;
4712274c
OM
1472 u32 flags = 0;
1473 int ret;
1474
1475 flags |= PIPE_CONTROL_CS_STALL;
1476
1477 if (flush_domains) {
1478 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1479 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1480 }
1481
1482 if (invalidate_domains) {
1483 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1484 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1485 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1486 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1487 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1488 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1489 flags |= PIPE_CONTROL_QW_WRITE;
1490 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1491 }
1492
9647ff36
ID
1493 /*
1494 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1495 * control.
1496 */
1497 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1498 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1499
1500 ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
4712274c
OM
1501 if (ret)
1502 return ret;
1503
9647ff36
ID
1504 if (vf_flush_wa) {
1505 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1506 intel_logical_ring_emit(ringbuf, 0);
1507 intel_logical_ring_emit(ringbuf, 0);
1508 intel_logical_ring_emit(ringbuf, 0);
1509 intel_logical_ring_emit(ringbuf, 0);
1510 intel_logical_ring_emit(ringbuf, 0);
1511 }
1512
4712274c
OM
1513 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1514 intel_logical_ring_emit(ringbuf, flags);
1515 intel_logical_ring_emit(ringbuf, scratch_addr);
1516 intel_logical_ring_emit(ringbuf, 0);
1517 intel_logical_ring_emit(ringbuf, 0);
1518 intel_logical_ring_emit(ringbuf, 0);
1519 intel_logical_ring_advance(ringbuf);
1520
1521 return 0;
1522}
1523
e94e37ad
OM
1524static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1525{
1526 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1527}
1528
1529static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1530{
1531 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1532}
1533
2d12955a
NH
1534static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1535 struct drm_i915_gem_request *request)
4da46e1e
OM
1536{
1537 struct intel_engine_cs *ring = ringbuf->ring;
1538 u32 cmd;
1539 int ret;
1540
53292cdb
MT
1541 /*
1542 * Reserve space for 2 NOOPs at the end of each request to be
1543 * used as a workaround for not being allowed to do lite
1544 * restore with HEAD==TAIL (WaIdleLiteRestore).
1545 */
1546 ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
4da46e1e
OM
1547 if (ret)
1548 return ret;
1549
8edfbb8b 1550 cmd = MI_STORE_DWORD_IMM_GEN4;
4da46e1e
OM
1551 cmd |= MI_GLOBAL_GTT;
1552
1553 intel_logical_ring_emit(ringbuf, cmd);
1554 intel_logical_ring_emit(ringbuf,
1555 (ring->status_page.gfx_addr +
1556 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1557 intel_logical_ring_emit(ringbuf, 0);
6259cead
JH
1558 intel_logical_ring_emit(ringbuf,
1559 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
4da46e1e
OM
1560 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1561 intel_logical_ring_emit(ringbuf, MI_NOOP);
21076372 1562 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
4da46e1e 1563
53292cdb
MT
1564 /*
1565 * Here we add two extra NOOPs as padding to avoid
1566 * lite restore of a context with HEAD==TAIL.
1567 */
1568 intel_logical_ring_emit(ringbuf, MI_NOOP);
1569 intel_logical_ring_emit(ringbuf, MI_NOOP);
1570 intel_logical_ring_advance(ringbuf);
1571
4da46e1e
OM
1572 return 0;
1573}
1574
be01363f 1575static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
cef437ad 1576{
cef437ad 1577 struct render_state so;
cef437ad
DL
1578 int ret;
1579
be01363f 1580 ret = i915_gem_render_state_prepare(req->ring, &so);
cef437ad
DL
1581 if (ret)
1582 return ret;
1583
1584 if (so.rodata == NULL)
1585 return 0;
1586
be01363f
JH
1587 ret = req->ring->emit_bb_start(req->ringbuf,
1588 req->ctx,
1589 so.ggtt_offset,
1590 I915_DISPATCH_SECURE);
cef437ad
DL
1591 if (ret)
1592 goto out;
1593
b2af0376 1594 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
cef437ad 1595
cef437ad
DL
1596out:
1597 i915_gem_render_state_fini(&so);
1598 return ret;
1599}
1600
8753181e 1601static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
e7778be1
TD
1602{
1603 int ret;
1604
e2be4faf 1605 ret = intel_logical_ring_workarounds_emit(req);
e7778be1
TD
1606 if (ret)
1607 return ret;
1608
be01363f 1609 return intel_lr_context_render_state_init(req);
e7778be1
TD
1610}
1611
73e4d07f
OM
1612/**
1613 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1614 *
1615 * @ring: Engine Command Streamer.
1616 *
1617 */
454afebd
OM
1618void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1619{
6402c330 1620 struct drm_i915_private *dev_priv;
9832b9da 1621
48d82387
OM
1622 if (!intel_ring_initialized(ring))
1623 return;
1624
6402c330
JH
1625 dev_priv = ring->dev->dev_private;
1626
9832b9da
OM
1627 intel_logical_ring_stop(ring);
1628 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
6259cead 1629 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
48d82387
OM
1630
1631 if (ring->cleanup)
1632 ring->cleanup(ring);
1633
1634 i915_cmd_parser_fini_ring(ring);
06fbca71 1635 i915_gem_batch_pool_fini(&ring->batch_pool);
48d82387
OM
1636
1637 if (ring->status_page.obj) {
1638 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1639 ring->status_page.obj = NULL;
1640 }
17ee950d
AS
1641
1642 lrc_destroy_wa_ctx_obj(ring);
454afebd
OM
1643}
1644
1645static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1646{
48d82387 1647 int ret;
48d82387
OM
1648
1649 /* Intentionally left blank. */
1650 ring->buffer = NULL;
1651
1652 ring->dev = dev;
1653 INIT_LIST_HEAD(&ring->active_list);
1654 INIT_LIST_HEAD(&ring->request_list);
06fbca71 1655 i915_gem_batch_pool_init(dev, &ring->batch_pool);
48d82387
OM
1656 init_waitqueue_head(&ring->irq_queue);
1657
acdd884a 1658 INIT_LIST_HEAD(&ring->execlist_queue);
c86ee3a9 1659 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
acdd884a
MT
1660 spin_lock_init(&ring->execlist_lock);
1661
48d82387
OM
1662 ret = i915_cmd_parser_init_ring(ring);
1663 if (ret)
1664 return ret;
1665
564ddb2f
OM
1666 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1667
1668 return ret;
454afebd
OM
1669}
1670
1671static int logical_render_ring_init(struct drm_device *dev)
1672{
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
99be1dfe 1675 int ret;
454afebd
OM
1676
1677 ring->name = "render ring";
1678 ring->id = RCS;
1679 ring->mmio_base = RENDER_RING_BASE;
1680 ring->irq_enable_mask =
1681 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
73d477f6
OM
1682 ring->irq_keep_mask =
1683 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1684 if (HAS_L3_DPF(dev))
1685 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
454afebd 1686
82ef822e
DL
1687 if (INTEL_INFO(dev)->gen >= 9)
1688 ring->init_hw = gen9_init_render_ring;
1689 else
1690 ring->init_hw = gen8_init_render_ring;
e7778be1 1691 ring->init_context = gen8_init_rcs_context;
9b1136d5 1692 ring->cleanup = intel_fini_pipe_control;
e94e37ad
OM
1693 ring->get_seqno = gen8_get_seqno;
1694 ring->set_seqno = gen8_set_seqno;
4da46e1e 1695 ring->emit_request = gen8_emit_request;
4712274c 1696 ring->emit_flush = gen8_emit_flush_render;
73d477f6
OM
1697 ring->irq_get = gen8_logical_ring_get_irq;
1698 ring->irq_put = gen8_logical_ring_put_irq;
15648585 1699 ring->emit_bb_start = gen8_emit_bb_start;
9b1136d5 1700
99be1dfe 1701 ring->dev = dev;
c4db7599
AS
1702
1703 ret = intel_init_pipe_control(ring);
99be1dfe
DV
1704 if (ret)
1705 return ret;
1706
17ee950d
AS
1707 ret = intel_init_workaround_bb(ring);
1708 if (ret) {
1709 /*
1710 * We continue even if we fail to initialize WA batch
1711 * because we only expect rare glitches but nothing
1712 * critical to prevent us from using GPU
1713 */
1714 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1715 ret);
1716 }
1717
c4db7599
AS
1718 ret = logical_ring_init(dev, ring);
1719 if (ret) {
17ee950d 1720 lrc_destroy_wa_ctx_obj(ring);
c4db7599 1721 }
17ee950d
AS
1722
1723 return ret;
454afebd
OM
1724}
1725
1726static int logical_bsd_ring_init(struct drm_device *dev)
1727{
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1730
1731 ring->name = "bsd ring";
1732 ring->id = VCS;
1733 ring->mmio_base = GEN6_BSD_RING_BASE;
1734 ring->irq_enable_mask =
1735 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
73d477f6
OM
1736 ring->irq_keep_mask =
1737 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
454afebd 1738
ecfe00d8 1739 ring->init_hw = gen8_init_common_ring;
e94e37ad
OM
1740 ring->get_seqno = gen8_get_seqno;
1741 ring->set_seqno = gen8_set_seqno;
4da46e1e 1742 ring->emit_request = gen8_emit_request;
4712274c 1743 ring->emit_flush = gen8_emit_flush;
73d477f6
OM
1744 ring->irq_get = gen8_logical_ring_get_irq;
1745 ring->irq_put = gen8_logical_ring_put_irq;
15648585 1746 ring->emit_bb_start = gen8_emit_bb_start;
9b1136d5 1747
454afebd
OM
1748 return logical_ring_init(dev, ring);
1749}
1750
1751static int logical_bsd2_ring_init(struct drm_device *dev)
1752{
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1755
1756 ring->name = "bds2 ring";
1757 ring->id = VCS2;
1758 ring->mmio_base = GEN8_BSD2_RING_BASE;
1759 ring->irq_enable_mask =
1760 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
73d477f6
OM
1761 ring->irq_keep_mask =
1762 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
454afebd 1763
ecfe00d8 1764 ring->init_hw = gen8_init_common_ring;
e94e37ad
OM
1765 ring->get_seqno = gen8_get_seqno;
1766 ring->set_seqno = gen8_set_seqno;
4da46e1e 1767 ring->emit_request = gen8_emit_request;
4712274c 1768 ring->emit_flush = gen8_emit_flush;
73d477f6
OM
1769 ring->irq_get = gen8_logical_ring_get_irq;
1770 ring->irq_put = gen8_logical_ring_put_irq;
15648585 1771 ring->emit_bb_start = gen8_emit_bb_start;
9b1136d5 1772
454afebd
OM
1773 return logical_ring_init(dev, ring);
1774}
1775
1776static int logical_blt_ring_init(struct drm_device *dev)
1777{
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1780
1781 ring->name = "blitter ring";
1782 ring->id = BCS;
1783 ring->mmio_base = BLT_RING_BASE;
1784 ring->irq_enable_mask =
1785 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
73d477f6
OM
1786 ring->irq_keep_mask =
1787 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
454afebd 1788
ecfe00d8 1789 ring->init_hw = gen8_init_common_ring;
e94e37ad
OM
1790 ring->get_seqno = gen8_get_seqno;
1791 ring->set_seqno = gen8_set_seqno;
4da46e1e 1792 ring->emit_request = gen8_emit_request;
4712274c 1793 ring->emit_flush = gen8_emit_flush;
73d477f6
OM
1794 ring->irq_get = gen8_logical_ring_get_irq;
1795 ring->irq_put = gen8_logical_ring_put_irq;
15648585 1796 ring->emit_bb_start = gen8_emit_bb_start;
9b1136d5 1797
454afebd
OM
1798 return logical_ring_init(dev, ring);
1799}
1800
1801static int logical_vebox_ring_init(struct drm_device *dev)
1802{
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1805
1806 ring->name = "video enhancement ring";
1807 ring->id = VECS;
1808 ring->mmio_base = VEBOX_RING_BASE;
1809 ring->irq_enable_mask =
1810 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
73d477f6
OM
1811 ring->irq_keep_mask =
1812 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
454afebd 1813
ecfe00d8 1814 ring->init_hw = gen8_init_common_ring;
e94e37ad
OM
1815 ring->get_seqno = gen8_get_seqno;
1816 ring->set_seqno = gen8_set_seqno;
4da46e1e 1817 ring->emit_request = gen8_emit_request;
4712274c 1818 ring->emit_flush = gen8_emit_flush;
73d477f6
OM
1819 ring->irq_get = gen8_logical_ring_get_irq;
1820 ring->irq_put = gen8_logical_ring_put_irq;
15648585 1821 ring->emit_bb_start = gen8_emit_bb_start;
9b1136d5 1822
454afebd
OM
1823 return logical_ring_init(dev, ring);
1824}
1825
73e4d07f
OM
1826/**
1827 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1828 * @dev: DRM device.
1829 *
1830 * This function inits the engines for an Execlists submission style (the equivalent in the
1831 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1832 * those engines that are present in the hardware.
1833 *
1834 * Return: non-zero if the initialization failed.
1835 */
454afebd
OM
1836int intel_logical_rings_init(struct drm_device *dev)
1837{
1838 struct drm_i915_private *dev_priv = dev->dev_private;
1839 int ret;
1840
1841 ret = logical_render_ring_init(dev);
1842 if (ret)
1843 return ret;
1844
1845 if (HAS_BSD(dev)) {
1846 ret = logical_bsd_ring_init(dev);
1847 if (ret)
1848 goto cleanup_render_ring;
1849 }
1850
1851 if (HAS_BLT(dev)) {
1852 ret = logical_blt_ring_init(dev);
1853 if (ret)
1854 goto cleanup_bsd_ring;
1855 }
1856
1857 if (HAS_VEBOX(dev)) {
1858 ret = logical_vebox_ring_init(dev);
1859 if (ret)
1860 goto cleanup_blt_ring;
1861 }
1862
1863 if (HAS_BSD2(dev)) {
1864 ret = logical_bsd2_ring_init(dev);
1865 if (ret)
1866 goto cleanup_vebox_ring;
1867 }
1868
1869 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1870 if (ret)
1871 goto cleanup_bsd2_ring;
1872
1873 return 0;
1874
1875cleanup_bsd2_ring:
1876 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1877cleanup_vebox_ring:
1878 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1879cleanup_blt_ring:
1880 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1881cleanup_bsd_ring:
1882 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1883cleanup_render_ring:
1884 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1885
1886 return ret;
1887}
1888
0cea6502
JM
1889static u32
1890make_rpcs(struct drm_device *dev)
1891{
1892 u32 rpcs = 0;
1893
1894 /*
1895 * No explicit RPCS request is needed to ensure full
1896 * slice/subslice/EU enablement prior to Gen9.
1897 */
1898 if (INTEL_INFO(dev)->gen < 9)
1899 return 0;
1900
1901 /*
1902 * Starting in Gen9, render power gating can leave
1903 * slice/subslice/EU in a partially enabled state. We
1904 * must make an explicit request through RPCS for full
1905 * enablement.
1906 */
1907 if (INTEL_INFO(dev)->has_slice_pg) {
1908 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1909 rpcs |= INTEL_INFO(dev)->slice_total <<
1910 GEN8_RPCS_S_CNT_SHIFT;
1911 rpcs |= GEN8_RPCS_ENABLE;
1912 }
1913
1914 if (INTEL_INFO(dev)->has_subslice_pg) {
1915 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1916 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
1917 GEN8_RPCS_SS_CNT_SHIFT;
1918 rpcs |= GEN8_RPCS_ENABLE;
1919 }
1920
1921 if (INTEL_INFO(dev)->has_eu_pg) {
1922 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1923 GEN8_RPCS_EU_MIN_SHIFT;
1924 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1925 GEN8_RPCS_EU_MAX_SHIFT;
1926 rpcs |= GEN8_RPCS_ENABLE;
1927 }
1928
1929 return rpcs;
1930}
1931
8670d6f9
OM
1932static int
1933populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1934 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1935{
2d965536
TD
1936 struct drm_device *dev = ring->dev;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
ae6c4806 1938 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
8670d6f9
OM
1939 struct page *page;
1940 uint32_t *reg_state;
1941 int ret;
1942
2d965536
TD
1943 if (!ppgtt)
1944 ppgtt = dev_priv->mm.aliasing_ppgtt;
1945
8670d6f9
OM
1946 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1947 if (ret) {
1948 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1949 return ret;
1950 }
1951
1952 ret = i915_gem_object_get_pages(ctx_obj);
1953 if (ret) {
1954 DRM_DEBUG_DRIVER("Could not get object pages\n");
1955 return ret;
1956 }
1957
1958 i915_gem_object_pin_pages(ctx_obj);
1959
1960 /* The second page of the context object contains some fields which must
1961 * be set up prior to the first execution. */
1962 page = i915_gem_object_get_page(ctx_obj, 1);
1963 reg_state = kmap_atomic(page);
1964
1965 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1966 * commands followed by (reg, value) pairs. The values we are setting here are
1967 * only for the first context restore: on a subsequent save, the GPU will
1968 * recreate this batchbuffer with new values (including all the missing
1969 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1970 if (ring->id == RCS)
1971 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1972 else
1973 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1974 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1975 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1976 reg_state[CTX_CONTEXT_CONTROL+1] =
5baa22c5
ZW
1977 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1978 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
8670d6f9
OM
1979 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1980 reg_state[CTX_RING_HEAD+1] = 0;
1981 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1982 reg_state[CTX_RING_TAIL+1] = 0;
1983 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
7ba717cf
TD
1984 /* Ring buffer start address is not known until the buffer is pinned.
1985 * It is written to the context image in execlists_update_context()
1986 */
8670d6f9
OM
1987 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1988 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1989 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1990 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1991 reg_state[CTX_BB_HEAD_U+1] = 0;
1992 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1993 reg_state[CTX_BB_HEAD_L+1] = 0;
1994 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1995 reg_state[CTX_BB_STATE+1] = (1<<5);
1996 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1997 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1998 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1999 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
2000 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
2001 reg_state[CTX_SECOND_BB_STATE+1] = 0;
2002 if (ring->id == RCS) {
8670d6f9
OM
2003 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
2004 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
2005 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
2006 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
2007 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
2008 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
17ee950d
AS
2009 if (ring->wa_ctx.obj) {
2010 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2011 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2012
2013 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2014 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2015 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2016
2017 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2018 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2019
2020 reg_state[CTX_BB_PER_CTX_PTR+1] =
2021 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2022 0x01;
2023 }
8670d6f9
OM
2024 }
2025 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
2026 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
2027 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
2028 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
2029 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
2030 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
2031 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
2032 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
2033 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
2034 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
2035 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
2036 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
d7b2633d
MT
2037
2038 /* With dynamic page allocation, PDPs may not be allocated at this point,
2039 * Point the unallocated PDPs to the scratch page
e5815a2e
MT
2040 */
2041 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2042 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2043 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2044 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
8670d6f9
OM
2045 if (ring->id == RCS) {
2046 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
0cea6502
JM
2047 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
2048 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
8670d6f9
OM
2049 }
2050
2051 kunmap_atomic(reg_state);
2052
2053 ctx_obj->dirty = 1;
2054 set_page_dirty(page);
2055 i915_gem_object_unpin_pages(ctx_obj);
2056
2057 return 0;
2058}
2059
73e4d07f
OM
2060/**
2061 * intel_lr_context_free() - free the LRC specific bits of a context
2062 * @ctx: the LR context to free.
2063 *
2064 * The real context freeing is done in i915_gem_context_free: this only
2065 * takes care of the bits that are LRC related: the per-engine backing
2066 * objects and the logical ringbuffer.
2067 */
ede7d42b
OM
2068void intel_lr_context_free(struct intel_context *ctx)
2069{
8c857917
OM
2070 int i;
2071
2072 for (i = 0; i < I915_NUM_RINGS; i++) {
2073 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
84c2377f 2074
8c857917 2075 if (ctx_obj) {
dcb4c12a
OM
2076 struct intel_ringbuffer *ringbuf =
2077 ctx->engine[i].ringbuf;
2078 struct intel_engine_cs *ring = ringbuf->ring;
2079
7ba717cf
TD
2080 if (ctx == ring->default_context) {
2081 intel_unpin_ringbuffer_obj(ringbuf);
2082 i915_gem_object_ggtt_unpin(ctx_obj);
2083 }
a7cbedec 2084 WARN_ON(ctx->engine[ring->id].pin_count);
84c2377f
OM
2085 intel_destroy_ringbuffer_obj(ringbuf);
2086 kfree(ringbuf);
8c857917
OM
2087 drm_gem_object_unreference(&ctx_obj->base);
2088 }
2089 }
2090}
2091
2092static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
2093{
2094 int ret = 0;
2095
468c6816 2096 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
8c857917
OM
2097
2098 switch (ring->id) {
2099 case RCS:
468c6816
MN
2100 if (INTEL_INFO(ring->dev)->gen >= 9)
2101 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2102 else
2103 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
8c857917
OM
2104 break;
2105 case VCS:
2106 case BCS:
2107 case VECS:
2108 case VCS2:
2109 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2110 break;
2111 }
2112
2113 return ret;
ede7d42b
OM
2114}
2115
70b0ea86 2116static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1df06b75
TD
2117 struct drm_i915_gem_object *default_ctx_obj)
2118{
2119 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2120
2121 /* The status page is offset 0 from the default context object
2122 * in LRC mode. */
2123 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
2124 ring->status_page.page_addr =
2125 kmap(sg_page(default_ctx_obj->pages->sgl));
1df06b75
TD
2126 ring->status_page.obj = default_ctx_obj;
2127
2128 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2129 (u32)ring->status_page.gfx_addr);
2130 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1df06b75
TD
2131}
2132
73e4d07f
OM
2133/**
2134 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2135 * @ctx: LR context to create.
2136 * @ring: engine to be used with the context.
2137 *
2138 * This function can be called more than once, with different engines, if we plan
2139 * to use the context with them. The context backing objects and the ringbuffers
2140 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2141 * the creation is a deferred call: it's better to make sure first that we need to use
2142 * a given ring with the context.
2143 *
32197aab 2144 * Return: non-zero on error.
73e4d07f 2145 */
ede7d42b
OM
2146int intel_lr_context_deferred_create(struct intel_context *ctx,
2147 struct intel_engine_cs *ring)
2148{
dcb4c12a 2149 const bool is_global_default_ctx = (ctx == ring->default_context);
8c857917
OM
2150 struct drm_device *dev = ring->dev;
2151 struct drm_i915_gem_object *ctx_obj;
2152 uint32_t context_size;
84c2377f 2153 struct intel_ringbuffer *ringbuf;
8c857917
OM
2154 int ret;
2155
ede7d42b 2156 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
bfc882b4 2157 WARN_ON(ctx->engine[ring->id].state);
ede7d42b 2158
8c857917
OM
2159 context_size = round_up(get_lr_context_size(ring), 4096);
2160
149c86e7 2161 ctx_obj = i915_gem_alloc_object(dev, context_size);
3126a660
DC
2162 if (!ctx_obj) {
2163 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2164 return -ENOMEM;
8c857917
OM
2165 }
2166
dcb4c12a
OM
2167 if (is_global_default_ctx) {
2168 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
2169 if (ret) {
2170 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2171 ret);
2172 drm_gem_object_unreference(&ctx_obj->base);
2173 return ret;
2174 }
8c857917
OM
2175 }
2176
84c2377f
OM
2177 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2178 if (!ringbuf) {
2179 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2180 ring->name);
84c2377f 2181 ret = -ENOMEM;
7ba717cf 2182 goto error_unpin_ctx;
84c2377f
OM
2183 }
2184
0c7dd53b 2185 ringbuf->ring = ring;
582d67f0 2186
84c2377f
OM
2187 ringbuf->size = 32 * PAGE_SIZE;
2188 ringbuf->effective_size = ringbuf->size;
2189 ringbuf->head = 0;
2190 ringbuf->tail = 0;
84c2377f 2191 ringbuf->last_retired_head = -1;
ebd0fd4b 2192 intel_ring_update_space(ringbuf);
84c2377f 2193
7ba717cf
TD
2194 if (ringbuf->obj == NULL) {
2195 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2196 if (ret) {
2197 DRM_DEBUG_DRIVER(
2198 "Failed to allocate ringbuffer obj %s: %d\n",
84c2377f 2199 ring->name, ret);
7ba717cf
TD
2200 goto error_free_rbuf;
2201 }
2202
2203 if (is_global_default_ctx) {
2204 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2205 if (ret) {
2206 DRM_ERROR(
2207 "Failed to pin and map ringbuffer %s: %d\n",
2208 ring->name, ret);
2209 goto error_destroy_rbuf;
2210 }
2211 }
2212
8670d6f9
OM
2213 }
2214
2215 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2216 if (ret) {
2217 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
8670d6f9 2218 goto error;
84c2377f
OM
2219 }
2220
2221 ctx->engine[ring->id].ringbuf = ringbuf;
8c857917 2222 ctx->engine[ring->id].state = ctx_obj;
ede7d42b 2223
70b0ea86
DV
2224 if (ctx == ring->default_context)
2225 lrc_setup_hardware_status_page(ring, ctx_obj);
e7778be1 2226 else if (ring->id == RCS && !ctx->rcs_initialized) {
771b9a53 2227 if (ring->init_context) {
76c39168
JH
2228 struct drm_i915_gem_request *req;
2229
2230 ret = i915_gem_request_alloc(ring, ctx, &req);
2231 if (ret)
2232 return ret;
2233
8753181e 2234 ret = ring->init_context(req);
e7778be1 2235 if (ret) {
771b9a53 2236 DRM_ERROR("ring init context: %d\n", ret);
76c39168 2237 i915_gem_request_cancel(req);
e7778be1
TD
2238 ctx->engine[ring->id].ringbuf = NULL;
2239 ctx->engine[ring->id].state = NULL;
2240 goto error;
2241 }
76c39168 2242
75289874 2243 i915_add_request_no_flush(req);
771b9a53
MT
2244 }
2245
564ddb2f
OM
2246 ctx->rcs_initialized = true;
2247 }
2248
ede7d42b 2249 return 0;
8670d6f9
OM
2250
2251error:
7ba717cf
TD
2252 if (is_global_default_ctx)
2253 intel_unpin_ringbuffer_obj(ringbuf);
2254error_destroy_rbuf:
2255 intel_destroy_ringbuffer_obj(ringbuf);
2256error_free_rbuf:
8670d6f9 2257 kfree(ringbuf);
7ba717cf 2258error_unpin_ctx:
dcb4c12a
OM
2259 if (is_global_default_ctx)
2260 i915_gem_object_ggtt_unpin(ctx_obj);
8670d6f9
OM
2261 drm_gem_object_unreference(&ctx_obj->base);
2262 return ret;
ede7d42b 2263}
3e5b6f05
TD
2264
2265void intel_lr_context_reset(struct drm_device *dev,
2266 struct intel_context *ctx)
2267{
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct intel_engine_cs *ring;
2270 int i;
2271
2272 for_each_ring(ring, dev_priv, i) {
2273 struct drm_i915_gem_object *ctx_obj =
2274 ctx->engine[ring->id].state;
2275 struct intel_ringbuffer *ringbuf =
2276 ctx->engine[ring->id].ringbuf;
2277 uint32_t *reg_state;
2278 struct page *page;
2279
2280 if (!ctx_obj)
2281 continue;
2282
2283 if (i915_gem_object_get_pages(ctx_obj)) {
2284 WARN(1, "Failed get_pages for context obj\n");
2285 continue;
2286 }
2287 page = i915_gem_object_get_page(ctx_obj, 1);
2288 reg_state = kmap_atomic(page);
2289
2290 reg_state[CTX_RING_HEAD+1] = 0;
2291 reg_state[CTX_RING_TAIL+1] = 0;
2292
2293 kunmap_atomic(reg_state);
2294
2295 ringbuf->head = 0;
2296 ringbuf->tail = 0;
2297 }
2298}