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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #ifndef _INTEL_LRC_H_ | |
25 | #define _INTEL_LRC_H_ | |
26 | ||
e73bdd20 CW |
27 | #include "intel_ringbuffer.h" |
28 | ||
dcb4c12a OM |
29 | #define GEN8_LR_CONTEXT_ALIGN 4096 |
30 | ||
4ba70e44 | 31 | /* Execlists regs */ |
bbdc070a DG |
32 | #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230) |
33 | #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234) | |
34 | #define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4) | |
35 | #define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244) | |
5baa22c5 ZW |
36 | #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) |
37 | #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) | |
6922528a | 38 | #define CTX_CTRL_RS_CTX_ENABLE (1 << 1) |
bbdc070a DG |
39 | #define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370) |
40 | #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8) | |
41 | #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4) | |
42 | #define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0) | |
4ba70e44 | 43 | |
5590a5f0 BW |
44 | /* The docs specify that the write pointer wraps around after 5h, "After status |
45 | * is written out to the last available status QW at offset 5h, this pointer | |
46 | * wraps to 0." | |
47 | * | |
48 | * Therefore, one must infer than even though there are 3 bits available, 6 and | |
49 | * 7 appear to be * reserved. | |
50 | */ | |
51 | #define GEN8_CSB_ENTRIES 6 | |
52 | #define GEN8_CSB_PTR_MASK 0x7 | |
53 | #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) | |
54 | #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) | |
55 | #define GEN8_CSB_WRITE_PTR(csb_status) \ | |
56 | (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0) | |
57 | #define GEN8_CSB_READ_PTR(csb_status) \ | |
58 | (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8) | |
59 | ||
3c7ba635 ZW |
60 | enum { |
61 | INTEL_CONTEXT_SCHEDULE_IN = 0, | |
62 | INTEL_CONTEXT_SCHEDULE_OUT, | |
63 | }; | |
64 | ||
454afebd | 65 | /* Logical Rings */ |
40e895ce | 66 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
ccd98fe4 | 67 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request); |
0bc40be8 TU |
68 | void intel_logical_ring_stop(struct intel_engine_cs *engine); |
69 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine); | |
88d2ba2e TU |
70 | int logical_render_ring_init(struct intel_engine_cs *engine); |
71 | int logical_xcs_ring_init(struct intel_engine_cs *engine); | |
72 | ||
bf9e8429 | 73 | int intel_engines_init(struct drm_i915_private *dev_priv); |
454afebd | 74 | |
ede7d42b | 75 | /* Logical Ring Contexts */ |
d1675198 AD |
76 | |
77 | /* One extra page is added before LRC for GuC as shared data */ | |
78 | #define LRC_GUCSHR_PN (0) | |
79 | #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1) | |
80 | #define LRC_STATE_PN (LRC_PPHWSP_PN + 1) | |
81 | ||
e8a9c58f | 82 | struct drm_i915_private; |
e2efd130 CW |
83 | struct i915_gem_context; |
84 | ||
0bc40be8 | 85 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine); |
7d774cac | 86 | |
821ed7df | 87 | void intel_lr_context_resume(struct drm_i915_private *dev_priv); |
e2efd130 | 88 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 89 | struct intel_engine_cs *engine); |
ede7d42b | 90 | |
127f1003 | 91 | /* Execlists */ |
c033666a CW |
92 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, |
93 | int enable_execlists); | |
ddd66c51 | 94 | void intel_execlists_enable_submission(struct drm_i915_private *dev_priv); |
0cb5670b | 95 | bool intel_execlists_idle(struct drm_i915_private *dev_priv); |
ddd66c51 | 96 | |
b20385f1 | 97 | #endif /* _INTEL_LRC_H_ */ |