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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
3fbe18d6 ZY |
52 | u32 pfit_control; |
53 | u32 pfit_pgm_ratios; | |
13c7d870 | 54 | bool is_dual_link; |
7dec0606 | 55 | u32 reg; |
788319d4 | 56 | |
62165e0d | 57 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
58 | }; |
59 | ||
29b99b48 | 60 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 61 | { |
29b99b48 | 62 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
63 | } |
64 | ||
c7362c4d | 65 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 66 | { |
c7362c4d | 67 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
68 | } |
69 | ||
b1dc332c DV |
70 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
71 | enum pipe *pipe) | |
72 | { | |
73 | struct drm_device *dev = encoder->base.dev; | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 DV |
75 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
76 | u32 tmp; | |
b1dc332c | 77 | |
7dec0606 | 78 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
79 | |
80 | if (!(tmp & LVDS_PORT_EN)) | |
81 | return false; | |
82 | ||
83 | if (HAS_PCH_CPT(dev)) | |
84 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
85 | else | |
86 | *pipe = PORT_TO_PIPE(tmp); | |
87 | ||
88 | return true; | |
89 | } | |
90 | ||
fc683091 DV |
91 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
92 | * This is an exception to the general rule that mode_set doesn't turn | |
93 | * things on. | |
94 | */ | |
95 | static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) | |
96 | { | |
97 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
98 | struct drm_device *dev = encoder->base.dev; | |
99 | struct drm_i915_private *dev_priv = dev->dev_private; | |
100 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
101 | struct drm_display_mode *fixed_mode = | |
102 | lvds_encoder->attached_connector->base.panel.fixed_mode; | |
103 | int pipe = intel_crtc->pipe; | |
104 | u32 temp; | |
105 | ||
fc683091 DV |
106 | temp = I915_READ(lvds_encoder->reg); |
107 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
108 | |
109 | if (HAS_PCH_CPT(dev)) { | |
110 | temp &= ~PORT_TRANS_SEL_MASK; | |
111 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 112 | } else { |
62810e5a DV |
113 | if (pipe == 1) { |
114 | temp |= LVDS_PIPEB_SELECT; | |
115 | } else { | |
116 | temp &= ~LVDS_PIPEB_SELECT; | |
117 | } | |
fc683091 | 118 | } |
62810e5a | 119 | |
fc683091 DV |
120 | /* set the corresponsding LVDS_BORDER bit */ |
121 | temp |= dev_priv->lvds_border_bits; | |
122 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
123 | * set the DPLLs for dual-channel mode or not. | |
124 | */ | |
125 | if (lvds_encoder->is_dual_link) | |
126 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
127 | else | |
128 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
129 | ||
130 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
131 | * appropriately here, but we need to look more thoroughly into how | |
132 | * panels behave in the two modes. | |
133 | */ | |
62810e5a DV |
134 | |
135 | /* Set the dithering flag on LVDS as needed, note that there is no | |
136 | * special lvds dither control bit on pch-split platforms, dithering is | |
137 | * only controlled through the PIPECONF reg. */ | |
138 | if (INTEL_INFO(dev)->gen == 4) { | |
fc683091 DV |
139 | if (dev_priv->lvds_dither) |
140 | temp |= LVDS_ENABLE_DITHER; | |
141 | else | |
142 | temp &= ~LVDS_ENABLE_DITHER; | |
143 | } | |
144 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
145 | if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
146 | temp |= LVDS_HSYNC_POLARITY; | |
147 | if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
148 | temp |= LVDS_VSYNC_POLARITY; | |
149 | ||
150 | I915_WRITE(lvds_encoder->reg, temp); | |
151 | } | |
152 | ||
9d6d9f19 MK |
153 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
154 | { | |
155 | struct drm_device *dev = encoder->base.dev; | |
156 | struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base); | |
157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
158 | ||
159 | if (HAS_PCH_SPLIT(dev) || !enc->pfit_control) | |
160 | return; | |
161 | ||
162 | /* | |
163 | * Enable automatic panel scaling so that non-native modes | |
164 | * fill the screen. The panel fitter should only be | |
165 | * adjusted whilst the pipe is disabled, according to | |
166 | * register description and PRM. | |
167 | */ | |
168 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
169 | enc->pfit_control, | |
170 | enc->pfit_pgm_ratios); | |
171 | ||
172 | I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios); | |
173 | I915_WRITE(PFIT_CONTROL, enc->pfit_control); | |
174 | } | |
175 | ||
79e53945 JB |
176 | /** |
177 | * Sets the power state for the panel. | |
178 | */ | |
c22834ec | 179 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 180 | { |
c22834ec | 181 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 182 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
c22834ec | 183 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 184 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 185 | u32 ctl_reg, stat_reg; |
541998a1 | 186 | |
c619eed4 | 187 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 188 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 189 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
190 | } else { |
191 | ctl_reg = PP_CONTROL; | |
de842eff | 192 | stat_reg = PP_STATUS; |
541998a1 | 193 | } |
79e53945 | 194 | |
7dec0606 | 195 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 196 | |
2a1292fd | 197 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 198 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
199 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
200 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 201 | |
24ded204 | 202 | intel_panel_enable_backlight(dev, intel_crtc->pipe); |
2a1292fd CW |
203 | } |
204 | ||
c22834ec | 205 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 206 | { |
c22834ec | 207 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 208 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2a1292fd | 209 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 210 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
211 | |
212 | if (HAS_PCH_SPLIT(dev)) { | |
213 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 214 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
215 | } else { |
216 | ctl_reg = PP_CONTROL; | |
de842eff | 217 | stat_reg = PP_STATUS; |
2a1292fd CW |
218 | } |
219 | ||
47356eb6 | 220 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
221 | |
222 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
223 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
224 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 225 | |
7dec0606 DV |
226 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
227 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
228 | } |
229 | ||
79e53945 JB |
230 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
231 | struct drm_display_mode *mode) | |
232 | { | |
dd06f90e JN |
233 | struct intel_connector *intel_connector = to_intel_connector(connector); |
234 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 235 | |
788319d4 CW |
236 | if (mode->hdisplay > fixed_mode->hdisplay) |
237 | return MODE_PANEL; | |
238 | if (mode->vdisplay > fixed_mode->vdisplay) | |
239 | return MODE_PANEL; | |
79e53945 JB |
240 | |
241 | return MODE_OK; | |
242 | } | |
243 | ||
49be663f CW |
244 | static void |
245 | centre_horizontally(struct drm_display_mode *mode, | |
246 | int width) | |
247 | { | |
248 | u32 border, sync_pos, blank_width, sync_width; | |
249 | ||
250 | /* keep the hsync and hblank widths constant */ | |
251 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
252 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
253 | sync_pos = (blank_width - sync_width + 1) / 2; | |
254 | ||
255 | border = (mode->hdisplay - width + 1) / 2; | |
256 | border += border & 1; /* make the border even */ | |
257 | ||
258 | mode->crtc_hdisplay = width; | |
259 | mode->crtc_hblank_start = width + border; | |
260 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
261 | ||
262 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
263 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
264 | } | |
265 | ||
266 | static void | |
267 | centre_vertically(struct drm_display_mode *mode, | |
268 | int height) | |
269 | { | |
270 | u32 border, sync_pos, blank_width, sync_width; | |
271 | ||
272 | /* keep the vsync and vblank widths constant */ | |
273 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
274 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
275 | sync_pos = (blank_width - sync_width + 1) / 2; | |
276 | ||
277 | border = (mode->vdisplay - height + 1) / 2; | |
278 | ||
279 | mode->crtc_vdisplay = height; | |
280 | mode->crtc_vblank_start = height + border; | |
281 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
282 | ||
283 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
284 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
285 | } | |
286 | ||
287 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
288 | { | |
289 | /* | |
290 | * Floating point operation is not supported. So the FACTOR | |
291 | * is defined, which can avoid the floating point computation | |
292 | * when calculating the panel ratio. | |
293 | */ | |
294 | #define ACCURACY 12 | |
295 | #define FACTOR (1 << ACCURACY) | |
296 | u32 ratio = source * FACTOR / target; | |
297 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
298 | } | |
299 | ||
7ae89233 DV |
300 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
301 | struct intel_crtc_config *pipe_config) | |
79e53945 | 302 | { |
7ae89233 | 303 | struct drm_device *dev = intel_encoder->base.dev; |
79e53945 | 304 | struct drm_i915_private *dev_priv = dev->dev_private; |
7ae89233 DV |
305 | struct intel_lvds_encoder *lvds_encoder = |
306 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
307 | struct intel_connector *intel_connector = |
308 | &lvds_encoder->attached_connector->base; | |
7ae89233 DV |
309 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
310 | struct drm_display_mode *mode = &pipe_config->requested_mode; | |
29b99b48 | 311 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
49be663f | 312 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
9db4a9c7 | 313 | int pipe; |
79e53945 JB |
314 | |
315 | /* Should never happen!! */ | |
a6c45cf0 | 316 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 317 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
318 | return false; |
319 | } | |
320 | ||
29b99b48 | 321 | if (intel_encoder_check_is_cloned(&lvds_encoder->base)) |
e24c5c29 | 322 | return false; |
1d8e1c75 | 323 | |
79e53945 | 324 | /* |
71677043 | 325 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
326 | * to the adjusted mode. The CRTC will be set up for this mode, |
327 | * with the panel scaling set up to source from the H/VDisplay | |
328 | * of the original mode. | |
329 | */ | |
4d891523 | 330 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 331 | adjusted_mode); |
1d8e1c75 CW |
332 | |
333 | if (HAS_PCH_SPLIT(dev)) { | |
4d891523 JN |
334 | intel_pch_panel_fitting(dev, |
335 | intel_connector->panel.fitting_mode, | |
1d8e1c75 CW |
336 | mode, adjusted_mode); |
337 | return true; | |
338 | } | |
79e53945 | 339 | |
3fbe18d6 ZY |
340 | /* Native modes don't need fitting */ |
341 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 342 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 343 | goto out; |
3fbe18d6 ZY |
344 | |
345 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 346 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
347 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
348 | PFIT_FILTER_FUZZY); | |
349 | ||
3fbe18d6 ZY |
350 | /* |
351 | * Enable automatic panel scaling for non-native modes so that they fill | |
352 | * the screen. Should be enabled before the pipe is enabled, according | |
353 | * to register description and PRM. | |
354 | * Change the value here to see the borders for debugging | |
355 | */ | |
9db4a9c7 JB |
356 | for_each_pipe(pipe) |
357 | I915_WRITE(BCLRPAT(pipe), 0); | |
3fbe18d6 | 358 | |
f9bef081 | 359 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
7ae89233 | 360 | pipe_config->timings_set = true; |
f9bef081 | 361 | |
4d891523 | 362 | switch (intel_connector->panel.fitting_mode) { |
53bd8389 | 363 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
364 | /* |
365 | * For centered modes, we have to calculate border widths & | |
366 | * heights and modify the values programmed into the CRTC. | |
367 | */ | |
49be663f CW |
368 | centre_horizontally(adjusted_mode, mode->hdisplay); |
369 | centre_vertically(adjusted_mode, mode->vdisplay); | |
370 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 371 | break; |
49be663f | 372 | |
3fbe18d6 | 373 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 374 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 375 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
376 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
377 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
378 | ||
3fbe18d6 | 379 | /* 965+ is easy, it does everything in hw */ |
49be663f | 380 | if (scaled_width > scaled_height) |
257e48f1 | 381 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 382 | else if (scaled_width < scaled_height) |
257e48f1 CW |
383 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
384 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
385 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 386 | } else { |
49be663f CW |
387 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
388 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
389 | /* |
390 | * For earlier chips we have to calculate the scaling | |
391 | * ratio by hand and program it into the | |
392 | * PFIT_PGM_RATIO register | |
393 | */ | |
49be663f CW |
394 | if (scaled_width > scaled_height) { /* pillar */ |
395 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
396 | ||
397 | border = LVDS_BORDER_ENABLE; | |
398 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
399 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
400 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
401 | bits << PFIT_VERT_SCALE_SHIFT); | |
402 | pfit_control |= (PFIT_ENABLE | | |
403 | VERT_INTERP_BILINEAR | | |
404 | HORIZ_INTERP_BILINEAR); | |
405 | } | |
406 | } else if (scaled_width < scaled_height) { /* letter */ | |
407 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
408 | ||
409 | border = LVDS_BORDER_ENABLE; | |
410 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
411 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
412 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
413 | bits << PFIT_VERT_SCALE_SHIFT); | |
414 | pfit_control |= (PFIT_ENABLE | | |
415 | VERT_INTERP_BILINEAR | | |
416 | HORIZ_INTERP_BILINEAR); | |
417 | } | |
418 | } else | |
419 | /* Aspects match, Let hw scale both directions */ | |
420 | pfit_control |= (PFIT_ENABLE | | |
421 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
422 | VERT_INTERP_BILINEAR | |
423 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
424 | } |
425 | break; | |
426 | ||
427 | case DRM_MODE_SCALE_FULLSCREEN: | |
428 | /* | |
429 | * Full scaling, even if it changes the aspect ratio. | |
430 | * Fortunately this is all done for us in hw. | |
431 | */ | |
257e48f1 CW |
432 | if (mode->vdisplay != adjusted_mode->vdisplay || |
433 | mode->hdisplay != adjusted_mode->hdisplay) { | |
434 | pfit_control |= PFIT_ENABLE; | |
435 | if (INTEL_INFO(dev)->gen >= 4) | |
436 | pfit_control |= PFIT_SCALING_AUTO; | |
437 | else | |
438 | pfit_control |= (VERT_AUTO_SCALE | | |
439 | VERT_INTERP_BILINEAR | | |
440 | HORIZ_AUTO_SCALE | | |
441 | HORIZ_INTERP_BILINEAR); | |
442 | } | |
3fbe18d6 | 443 | break; |
49be663f | 444 | |
3fbe18d6 ZY |
445 | default: |
446 | break; | |
447 | } | |
448 | ||
449 | out: | |
72389a33 | 450 | /* If not enabling scaling, be consistent and always use 0. */ |
bee17e5a CW |
451 | if ((pfit_control & PFIT_ENABLE) == 0) { |
452 | pfit_control = 0; | |
453 | pfit_pgm_ratios = 0; | |
454 | } | |
72389a33 CW |
455 | |
456 | /* Make sure pre-965 set dither correctly */ | |
457 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | |
458 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
459 | ||
29b99b48 JN |
460 | if (pfit_control != lvds_encoder->pfit_control || |
461 | pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { | |
462 | lvds_encoder->pfit_control = pfit_control; | |
463 | lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; | |
e9e331a8 | 464 | } |
49be663f CW |
465 | dev_priv->lvds_border_bits = border; |
466 | ||
79e53945 JB |
467 | /* |
468 | * XXX: It would be nice to support lower refresh rates on the | |
469 | * panels to reduce power consumption, and perhaps match the | |
470 | * user's requested refresh rate. | |
471 | */ | |
472 | ||
473 | return true; | |
474 | } | |
475 | ||
79e53945 JB |
476 | static void intel_lvds_mode_set(struct drm_encoder *encoder, |
477 | struct drm_display_mode *mode, | |
478 | struct drm_display_mode *adjusted_mode) | |
479 | { | |
79e53945 JB |
480 | /* |
481 | * The LVDS pin pair will already have been turned on in the | |
482 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
483 | * settings. | |
484 | */ | |
79e53945 JB |
485 | } |
486 | ||
487 | /** | |
488 | * Detect the LVDS connection. | |
489 | * | |
b42d4c5c JB |
490 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
491 | * connected and closed means disconnected. We also send hotplug events as | |
492 | * needed, using lid status notification from the input layer. | |
79e53945 | 493 | */ |
7b334fcb | 494 | static enum drm_connector_status |
930a9e28 | 495 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 496 | { |
7b9c5abe | 497 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 498 | enum drm_connector_status status; |
b42d4c5c | 499 | |
fe16d949 CW |
500 | status = intel_panel_detect(dev); |
501 | if (status != connector_status_unknown) | |
502 | return status; | |
01fe9dbd | 503 | |
6ee3b5a1 | 504 | return connector_status_connected; |
79e53945 JB |
505 | } |
506 | ||
507 | /** | |
508 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
509 | */ | |
510 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
511 | { | |
62165e0d | 512 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 513 | struct drm_device *dev = connector->dev; |
788319d4 | 514 | struct drm_display_mode *mode; |
79e53945 | 515 | |
9cd300e0 | 516 | /* use cached edid if we have one */ |
2aa4f099 | 517 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 518 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 519 | |
dd06f90e | 520 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 521 | if (mode == NULL) |
788319d4 | 522 | return 0; |
79e53945 | 523 | |
788319d4 CW |
524 | drm_mode_probed_add(connector, mode); |
525 | return 1; | |
79e53945 JB |
526 | } |
527 | ||
0544edfd TB |
528 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
529 | { | |
bc0daf48 | 530 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
531 | return 1; |
532 | } | |
533 | ||
534 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
535 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
536 | { | |
537 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
538 | .ident = "Toshiba Tecra A11", | |
539 | .matches = { | |
540 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
541 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
542 | }, | |
543 | }, | |
544 | ||
545 | { } /* terminating entry */ | |
546 | }; | |
547 | ||
c9354c85 | 548 | /* |
b8efb17b ZR |
549 | * Lid events. Note the use of 'modeset': |
550 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
551 | * and set it to MODESET_DONE on open | |
c9354c85 | 552 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
553 | * duplicate events where it was already properly set) |
554 | * - the suspend/resume paths will set it to | |
555 | * MODESET_SUSPENDED and ignore the lid open event, | |
556 | * because they restore the mode ("lid open"). | |
c9354c85 | 557 | */ |
c1c7af60 JB |
558 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
559 | void *unused) | |
560 | { | |
db1740a0 JN |
561 | struct intel_lvds_connector *lvds_connector = |
562 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
563 | struct drm_connector *connector = &lvds_connector->base.base; | |
564 | struct drm_device *dev = connector->dev; | |
565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 566 | |
2fb4e61d AW |
567 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
568 | return NOTIFY_OK; | |
569 | ||
b8efb17b ZR |
570 | mutex_lock(&dev_priv->modeset_restore_lock); |
571 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
572 | goto exit; | |
a2565377 ZY |
573 | /* |
574 | * check and update the status of LVDS connector after receiving | |
575 | * the LID nofication event. | |
576 | */ | |
db1740a0 | 577 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 578 | |
0544edfd TB |
579 | /* Don't force modeset on machines where it causes a GPU lockup */ |
580 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 581 | goto exit; |
c9354c85 | 582 | if (!acpi_lid_open()) { |
b8efb17b ZR |
583 | /* do modeset on next lid open event */ |
584 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
585 | goto exit; | |
06891e27 | 586 | } |
c1c7af60 | 587 | |
b8efb17b ZR |
588 | if (dev_priv->modeset_restore == MODESET_DONE) |
589 | goto exit; | |
c9354c85 | 590 | |
a0e99e68 | 591 | drm_modeset_lock_all(dev); |
45e2b5f6 | 592 | intel_modeset_setup_hw_state(dev, true); |
a0e99e68 | 593 | drm_modeset_unlock_all(dev); |
06324194 | 594 | |
b8efb17b ZR |
595 | dev_priv->modeset_restore = MODESET_DONE; |
596 | ||
597 | exit: | |
598 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
599 | return NOTIFY_OK; |
600 | } | |
601 | ||
79e53945 JB |
602 | /** |
603 | * intel_lvds_destroy - unregister and free LVDS structures | |
604 | * @connector: connector to free | |
605 | * | |
606 | * Unregister the DDC bus for this connector then free the driver private | |
607 | * structure. | |
608 | */ | |
609 | static void intel_lvds_destroy(struct drm_connector *connector) | |
610 | { | |
db1740a0 JN |
611 | struct intel_lvds_connector *lvds_connector = |
612 | to_lvds_connector(connector); | |
79e53945 | 613 | |
db1740a0 JN |
614 | if (lvds_connector->lid_notifier.notifier_call) |
615 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 616 | |
9cd300e0 JN |
617 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
618 | kfree(lvds_connector->base.edid); | |
619 | ||
db1740a0 | 620 | intel_panel_destroy_backlight(connector->dev); |
1d508706 | 621 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 622 | |
79e53945 JB |
623 | drm_sysfs_connector_remove(connector); |
624 | drm_connector_cleanup(connector); | |
625 | kfree(connector); | |
626 | } | |
627 | ||
335041ed JB |
628 | static int intel_lvds_set_property(struct drm_connector *connector, |
629 | struct drm_property *property, | |
630 | uint64_t value) | |
631 | { | |
4d891523 | 632 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 633 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 634 | |
788319d4 | 635 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 636 | struct drm_crtc *crtc; |
bb8a3560 | 637 | |
53bd8389 JB |
638 | if (value == DRM_MODE_SCALE_NONE) { |
639 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 640 | return -EINVAL; |
3fbe18d6 | 641 | } |
788319d4 | 642 | |
4d891523 | 643 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
644 | /* the LVDS scaling property is not changed */ |
645 | return 0; | |
646 | } | |
4d891523 | 647 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
648 | |
649 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
650 | if (crtc && crtc->enabled) { |
651 | /* | |
652 | * If the CRTC is enabled, the display will be changed | |
653 | * according to the new panel fitting mode. | |
654 | */ | |
c0c36b94 | 655 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
656 | } |
657 | } | |
658 | ||
335041ed JB |
659 | return 0; |
660 | } | |
661 | ||
79e53945 | 662 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
79e53945 | 663 | .mode_set = intel_lvds_mode_set, |
79e53945 JB |
664 | }; |
665 | ||
666 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
667 | .get_modes = intel_lvds_get_modes, | |
668 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 669 | .best_encoder = intel_best_encoder, |
79e53945 JB |
670 | }; |
671 | ||
672 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 673 | .dpms = intel_connector_dpms, |
79e53945 JB |
674 | .detect = intel_lvds_detect, |
675 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 676 | .set_property = intel_lvds_set_property, |
79e53945 JB |
677 | .destroy = intel_lvds_destroy, |
678 | }; | |
679 | ||
79e53945 | 680 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 681 | .destroy = intel_encoder_destroy, |
79e53945 JB |
682 | }; |
683 | ||
425d244c JW |
684 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
685 | { | |
bc0daf48 | 686 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
687 | return 1; |
688 | } | |
79e53945 | 689 | |
425d244c | 690 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 691 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
692 | { |
693 | .callback = intel_no_lvds_dmi_callback, | |
694 | .ident = "Apple Mac Mini (Core series)", | |
695 | .matches = { | |
98acd46f | 696 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
697 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
698 | }, | |
699 | }, | |
700 | { | |
701 | .callback = intel_no_lvds_dmi_callback, | |
702 | .ident = "Apple Mac Mini (Core 2 series)", | |
703 | .matches = { | |
98acd46f | 704 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
705 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
706 | }, | |
707 | }, | |
708 | { | |
709 | .callback = intel_no_lvds_dmi_callback, | |
710 | .ident = "MSI IM-945GSE-A", | |
711 | .matches = { | |
712 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
713 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
714 | }, | |
715 | }, | |
716 | { | |
717 | .callback = intel_no_lvds_dmi_callback, | |
718 | .ident = "Dell Studio Hybrid", | |
719 | .matches = { | |
720 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
721 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
722 | }, | |
723 | }, | |
70aa96ca JW |
724 | { |
725 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
726 | .ident = "Dell OptiPlex FX170", |
727 | .matches = { | |
728 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
729 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
730 | }, | |
731 | }, | |
732 | { | |
733 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
734 | .ident = "AOpen Mini PC", |
735 | .matches = { | |
736 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
737 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
738 | }, | |
739 | }, | |
ed8c754b TV |
740 | { |
741 | .callback = intel_no_lvds_dmi_callback, | |
742 | .ident = "AOpen Mini PC MP915", | |
743 | .matches = { | |
744 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
745 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
746 | }, | |
747 | }, | |
22ab70d3 KP |
748 | { |
749 | .callback = intel_no_lvds_dmi_callback, | |
750 | .ident = "AOpen i915GMm-HFS", | |
751 | .matches = { | |
752 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
753 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
754 | }, | |
755 | }, | |
e57b6886 DV |
756 | { |
757 | .callback = intel_no_lvds_dmi_callback, | |
758 | .ident = "AOpen i45GMx-I", | |
759 | .matches = { | |
760 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
761 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
762 | }, | |
763 | }, | |
fa0864b2 MC |
764 | { |
765 | .callback = intel_no_lvds_dmi_callback, | |
766 | .ident = "Aopen i945GTt-VFA", | |
767 | .matches = { | |
768 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
769 | }, | |
770 | }, | |
9875557e SB |
771 | { |
772 | .callback = intel_no_lvds_dmi_callback, | |
773 | .ident = "Clientron U800", | |
774 | .matches = { | |
775 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
776 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
777 | }, | |
778 | }, | |
6a574b5b | 779 | { |
44306ab3 JS |
780 | .callback = intel_no_lvds_dmi_callback, |
781 | .ident = "Clientron E830", | |
782 | .matches = { | |
783 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
784 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
785 | }, | |
786 | }, | |
787 | { | |
6a574b5b HG |
788 | .callback = intel_no_lvds_dmi_callback, |
789 | .ident = "Asus EeeBox PC EB1007", | |
790 | .matches = { | |
791 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
792 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
793 | }, | |
794 | }, | |
0999bbe0 AJ |
795 | { |
796 | .callback = intel_no_lvds_dmi_callback, | |
797 | .ident = "Asus AT5NM10T-I", | |
798 | .matches = { | |
799 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
800 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
801 | }, | |
802 | }, | |
33471119 JBG |
803 | { |
804 | .callback = intel_no_lvds_dmi_callback, | |
805 | .ident = "Hewlett-Packard HP t5740e Thin Client", | |
806 | .matches = { | |
807 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
808 | DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"), | |
809 | }, | |
810 | }, | |
f5b8a7ed MG |
811 | { |
812 | .callback = intel_no_lvds_dmi_callback, | |
813 | .ident = "Hewlett-Packard t5745", | |
814 | .matches = { | |
815 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 816 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
817 | }, |
818 | }, | |
819 | { | |
820 | .callback = intel_no_lvds_dmi_callback, | |
821 | .ident = "Hewlett-Packard st5747", | |
822 | .matches = { | |
823 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 824 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
825 | }, |
826 | }, | |
97effadb AA |
827 | { |
828 | .callback = intel_no_lvds_dmi_callback, | |
829 | .ident = "MSI Wind Box DC500", | |
830 | .matches = { | |
831 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
832 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
833 | }, | |
834 | }, | |
a51d4ed0 CW |
835 | { |
836 | .callback = intel_no_lvds_dmi_callback, | |
837 | .ident = "Gigabyte GA-D525TUD", | |
838 | .matches = { | |
839 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
840 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
841 | }, | |
842 | }, | |
c31407a3 CW |
843 | { |
844 | .callback = intel_no_lvds_dmi_callback, | |
845 | .ident = "Supermicro X7SPA-H", | |
846 | .matches = { | |
847 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
848 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
849 | }, | |
850 | }, | |
425d244c JW |
851 | |
852 | { } /* terminating entry */ | |
853 | }; | |
79e53945 | 854 | |
18f9ed12 ZY |
855 | /** |
856 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
857 | * @dev: drm device | |
858 | * @connector: LVDS connector | |
859 | * | |
860 | * Find the reduced downclock for LVDS in EDID. | |
861 | */ | |
862 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
863 | struct drm_display_mode *fixed_mode, |
864 | struct drm_connector *connector) | |
18f9ed12 ZY |
865 | { |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 867 | struct drm_display_mode *scan; |
18f9ed12 ZY |
868 | int temp_downclock; |
869 | ||
788319d4 | 870 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
871 | list_for_each_entry(scan, &connector->probed_modes, head) { |
872 | /* | |
873 | * If one mode has the same resolution with the fixed_panel | |
874 | * mode while they have the different refresh rate, it means | |
875 | * that the reduced downclock is found for the LVDS. In such | |
876 | * case we can set the different FPx0/1 to dynamically select | |
877 | * between low and high frequency. | |
878 | */ | |
788319d4 CW |
879 | if (scan->hdisplay == fixed_mode->hdisplay && |
880 | scan->hsync_start == fixed_mode->hsync_start && | |
881 | scan->hsync_end == fixed_mode->hsync_end && | |
882 | scan->htotal == fixed_mode->htotal && | |
883 | scan->vdisplay == fixed_mode->vdisplay && | |
884 | scan->vsync_start == fixed_mode->vsync_start && | |
885 | scan->vsync_end == fixed_mode->vsync_end && | |
886 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
887 | if (scan->clock < temp_downclock) { |
888 | /* | |
889 | * The downclock is already found. But we | |
890 | * expect to find the lower downclock. | |
891 | */ | |
892 | temp_downclock = scan->clock; | |
893 | } | |
894 | } | |
895 | } | |
788319d4 | 896 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
897 | /* We found the downclock for LVDS. */ |
898 | dev_priv->lvds_downclock_avail = 1; | |
899 | dev_priv->lvds_downclock = temp_downclock; | |
900 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
901 | "Normal clock %dKhz, downclock %dKhz\n", |
902 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 903 | } |
18f9ed12 ZY |
904 | } |
905 | ||
7cf4f69d ZY |
906 | /* |
907 | * Enumerate the child dev array parsed from VBT to check whether | |
908 | * the LVDS is present. | |
909 | * If it is present, return 1. | |
910 | * If it is not present, return false. | |
911 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 912 | */ |
270eea0f CW |
913 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
914 | u8 *i2c_pin) | |
7cf4f69d ZY |
915 | { |
916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 917 | int i; |
7cf4f69d ZY |
918 | |
919 | if (!dev_priv->child_dev_num) | |
425904dd | 920 | return true; |
7cf4f69d | 921 | |
7cf4f69d | 922 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
923 | struct child_device_config *child = dev_priv->child_dev + i; |
924 | ||
925 | /* If the device type is not LFP, continue. | |
926 | * We have to check both the new identifiers as well as the | |
927 | * old for compatibility with some BIOSes. | |
7cf4f69d | 928 | */ |
425904dd CW |
929 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
930 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
931 | continue; |
932 | ||
3bd7d909 DK |
933 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
934 | *i2c_pin = child->i2c_pin; | |
270eea0f | 935 | |
425904dd CW |
936 | /* However, we cannot trust the BIOS writers to populate |
937 | * the VBT correctly. Since LVDS requires additional | |
938 | * information from AIM blocks, a non-zero addin offset is | |
939 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 940 | */ |
425904dd CW |
941 | if (child->addin_offset) |
942 | return true; | |
943 | ||
944 | /* But even then some BIOS writers perform some black magic | |
945 | * and instantiate the device without reference to any | |
946 | * additional data. Trust that if the VBT was written into | |
947 | * the OpRegion then they have validated the LVDS's existence. | |
948 | */ | |
949 | if (dev_priv->opregion.vbt) | |
950 | return true; | |
7cf4f69d | 951 | } |
425904dd CW |
952 | |
953 | return false; | |
7cf4f69d ZY |
954 | } |
955 | ||
1974cad0 DV |
956 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
957 | { | |
958 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
959 | return 1; | |
960 | } | |
961 | ||
962 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
963 | { | |
964 | .callback = intel_dual_link_lvds_callback, | |
965 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
966 | .matches = { | |
967 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
968 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
969 | }, | |
970 | }, | |
971 | { } /* terminating entry */ | |
972 | }; | |
973 | ||
974 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
975 | { |
976 | struct intel_encoder *encoder; | |
977 | struct intel_lvds_encoder *lvds_encoder; | |
978 | ||
979 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
980 | base.head) { | |
981 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
982 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
983 | ||
984 | return lvds_encoder->is_dual_link; | |
985 | } | |
986 | } | |
987 | ||
988 | return false; | |
989 | } | |
990 | ||
7dec0606 | 991 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 992 | { |
7dec0606 | 993 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
994 | unsigned int val; |
995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
996 | |
997 | /* use the module option value if specified */ | |
998 | if (i915_lvds_channel_mode > 0) | |
999 | return i915_lvds_channel_mode == 2; | |
1000 | ||
1001 | if (dmi_check_system(intel_dual_link_lvds)) | |
1002 | return true; | |
1003 | ||
13c7d870 DV |
1004 | /* BIOS should set the proper LVDS register value at boot, but |
1005 | * in reality, it doesn't set the value when the lid is closed; | |
1006 | * we need to check "the value to be set" in VBT when LVDS | |
1007 | * register is uninitialized. | |
1008 | */ | |
7dec0606 | 1009 | val = I915_READ(lvds_encoder->reg); |
13c7d870 DV |
1010 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
1011 | val = dev_priv->bios_lvds_val; | |
1012 | ||
1974cad0 DV |
1013 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
1014 | } | |
1015 | ||
f3cfcba6 CW |
1016 | static bool intel_lvds_supported(struct drm_device *dev) |
1017 | { | |
1018 | /* With the introduction of the PCH we gained a dedicated | |
1019 | * LVDS presence pin, use it. */ | |
311e359c | 1020 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
1021 | return true; |
1022 | ||
1023 | /* Otherwise LVDS was only attached to mobile products, | |
1024 | * except for the inglorious 830gm */ | |
311e359c PZ |
1025 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
1026 | return true; | |
1027 | ||
1028 | return false; | |
f3cfcba6 CW |
1029 | } |
1030 | ||
79e53945 JB |
1031 | /** |
1032 | * intel_lvds_init - setup LVDS connectors on this device | |
1033 | * @dev: drm device | |
1034 | * | |
1035 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
1036 | * modes we can display on the LVDS panel (if present). | |
1037 | */ | |
c5d1b51d | 1038 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
1039 | { |
1040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 1041 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 1042 | struct intel_encoder *intel_encoder; |
c7362c4d | 1043 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 1044 | struct intel_connector *intel_connector; |
79e53945 JB |
1045 | struct drm_connector *connector; |
1046 | struct drm_encoder *encoder; | |
1047 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 1048 | struct drm_display_mode *fixed_mode = NULL; |
9cd300e0 | 1049 | struct edid *edid; |
79e53945 JB |
1050 | struct drm_crtc *crtc; |
1051 | u32 lvds; | |
270eea0f CW |
1052 | int pipe; |
1053 | u8 pin; | |
79e53945 | 1054 | |
f3cfcba6 CW |
1055 | if (!intel_lvds_supported(dev)) |
1056 | return false; | |
1057 | ||
425d244c JW |
1058 | /* Skip init on machines we know falsely report LVDS */ |
1059 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 1060 | return false; |
565dcd46 | 1061 | |
270eea0f CW |
1062 | pin = GMBUS_PORT_PANEL; |
1063 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 1064 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 1065 | return false; |
38b3037e | 1066 | } |
e99da35f | 1067 | |
c619eed4 | 1068 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1069 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 1070 | return false; |
5ceb0f9b | 1071 | if (dev_priv->edp.support) { |
28c97730 | 1072 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 1073 | return false; |
32f9d658 | 1074 | } |
541998a1 ZW |
1075 | } |
1076 | ||
29b99b48 JN |
1077 | lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); |
1078 | if (!lvds_encoder) | |
c5d1b51d | 1079 | return false; |
79e53945 | 1080 | |
c7362c4d JN |
1081 | lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); |
1082 | if (!lvds_connector) { | |
29b99b48 | 1083 | kfree(lvds_encoder); |
c5d1b51d | 1084 | return false; |
bb8a3560 ZW |
1085 | } |
1086 | ||
62165e0d JN |
1087 | lvds_encoder->attached_connector = lvds_connector; |
1088 | ||
e9e331a8 | 1089 | if (!HAS_PCH_SPLIT(dev)) { |
29b99b48 | 1090 | lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL); |
e9e331a8 CW |
1091 | } |
1092 | ||
29b99b48 | 1093 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1094 | encoder = &intel_encoder->base; |
c7362c4d | 1095 | intel_connector = &lvds_connector->base; |
ea5b213a | 1096 | connector = &intel_connector->base; |
bb8a3560 | 1097 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1098 | DRM_MODE_CONNECTOR_LVDS); |
1099 | ||
4ef69c7a | 1100 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
1101 | DRM_MODE_ENCODER_LVDS); |
1102 | ||
c22834ec | 1103 | intel_encoder->enable = intel_enable_lvds; |
9d6d9f19 | 1104 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
fc683091 | 1105 | intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; |
7ae89233 | 1106 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 1107 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c DV |
1108 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
1109 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
c22834ec | 1110 | |
df0e9248 | 1111 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1112 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1113 | |
66a9278e | 1114 | intel_encoder->cloneable = false; |
27f8227b JB |
1115 | if (HAS_PCH_SPLIT(dev)) |
1116 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1117 | else if (IS_GEN4(dev)) |
1118 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1119 | else |
1120 | intel_encoder->crtc_mask = (1 << 1); | |
1121 | ||
79e53945 JB |
1122 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
1123 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
1124 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1125 | connector->interlace_allowed = false; | |
1126 | connector->doublescan_allowed = false; | |
1127 | ||
7dec0606 DV |
1128 | if (HAS_PCH_SPLIT(dev)) { |
1129 | lvds_encoder->reg = PCH_LVDS; | |
1130 | } else { | |
1131 | lvds_encoder->reg = LVDS; | |
1132 | } | |
1133 | ||
3fbe18d6 ZY |
1134 | /* create the scaling mode property */ |
1135 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1136 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1137 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1138 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1139 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1140 | /* |
1141 | * LVDS discovery: | |
1142 | * 1) check for EDID on DDC | |
1143 | * 2) check for VBT data | |
1144 | * 3) check to see if LVDS is already on | |
1145 | * if none of the above, no panel | |
1146 | * 4) make sure lid is open | |
1147 | * if closed, act like it's not there for now | |
1148 | */ | |
1149 | ||
79e53945 JB |
1150 | /* |
1151 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1152 | * preferred mode is the right one. | |
1153 | */ | |
9cd300e0 JN |
1154 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1155 | if (edid) { | |
1156 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1157 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1158 | edid); |
3f8ff0e7 | 1159 | } else { |
9cd300e0 JN |
1160 | kfree(edid); |
1161 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1162 | } |
9cd300e0 JN |
1163 | } else { |
1164 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1165 | } |
9cd300e0 JN |
1166 | lvds_connector->base.edid = edid; |
1167 | ||
1168 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1169 | /* Didn't get an EDID, so |
1170 | * Set wide sync ranges so we get all modes | |
1171 | * handed to valid_mode for checking | |
1172 | */ | |
1173 | connector->display_info.min_vfreq = 0; | |
1174 | connector->display_info.max_vfreq = 200; | |
1175 | connector->display_info.min_hfreq = 0; | |
1176 | connector->display_info.max_hfreq = 200; | |
1177 | } | |
79e53945 JB |
1178 | |
1179 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1180 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1181 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1182 | drm_mode_debug_printmodeline(scan); | |
1183 | ||
dd06f90e | 1184 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 CW |
1185 | if (fixed_mode) { |
1186 | intel_find_lvds_downclock(dev, fixed_mode, | |
1187 | connector); | |
1188 | goto out; | |
1189 | } | |
79e53945 | 1190 | } |
79e53945 JB |
1191 | } |
1192 | ||
1193 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1194 | if (dev_priv->lfp_lvds_vbt_mode) { |
6a9d51b7 CW |
1195 | DRM_DEBUG_KMS("using mode from VBT: "); |
1196 | drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode); | |
1197 | ||
dd06f90e JN |
1198 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
1199 | if (fixed_mode) { | |
1200 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1201 | goto out; |
1202 | } | |
79e53945 JB |
1203 | } |
1204 | ||
1205 | /* | |
1206 | * If we didn't get EDID, try checking if the panel is already turned | |
1207 | * on. If so, assume that whatever is currently programmed is the | |
1208 | * correct mode. | |
1209 | */ | |
541998a1 | 1210 | |
f2b115e6 | 1211 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1212 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1213 | goto failed; |
1214 | ||
79e53945 JB |
1215 | lvds = I915_READ(LVDS); |
1216 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1217 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1218 | |
1219 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1220 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1221 | if (fixed_mode) { | |
6a9d51b7 CW |
1222 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1223 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1224 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1225 | goto out; |
79e53945 JB |
1226 | } |
1227 | } | |
1228 | ||
1229 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1230 | if (!fixed_mode) |
79e53945 JB |
1231 | goto failed; |
1232 | ||
79e53945 | 1233 | out: |
7dec0606 | 1234 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1235 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1236 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1237 | ||
24ded204 DV |
1238 | /* |
1239 | * Unlock registers and just | |
1240 | * leave them unlocked | |
1241 | */ | |
c619eed4 | 1242 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1243 | I915_WRITE(PCH_PP_CONTROL, |
1244 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1245 | } else { | |
ed10fca9 KP |
1246 | I915_WRITE(PP_CONTROL, |
1247 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1248 | } |
db1740a0 JN |
1249 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1250 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1251 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1252 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1253 | } |
79e53945 | 1254 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1255 | |
dd06f90e | 1256 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 1257 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1258 | |
c5d1b51d | 1259 | return true; |
79e53945 JB |
1260 | |
1261 | failed: | |
8a4c47f3 | 1262 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1263 | drm_connector_cleanup(connector); |
1991bdfa | 1264 | drm_encoder_cleanup(encoder); |
dd06f90e JN |
1265 | if (fixed_mode) |
1266 | drm_mode_destroy(dev, fixed_mode); | |
29b99b48 | 1267 | kfree(lvds_encoder); |
c7362c4d | 1268 | kfree(lvds_connector); |
c5d1b51d | 1269 | return false; |
79e53945 | 1270 | } |