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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
13c7d870 | 52 | bool is_dual_link; |
7dec0606 | 53 | u32 reg; |
788319d4 | 54 | |
62165e0d | 55 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
56 | }; |
57 | ||
29b99b48 | 58 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
29b99b48 | 60 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
61 | } |
62 | ||
c7362c4d | 63 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 64 | { |
c7362c4d | 65 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
66 | } |
67 | ||
b1dc332c DV |
68 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
69 | enum pipe *pipe) | |
70 | { | |
71 | struct drm_device *dev = encoder->base.dev; | |
72 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 DV |
73 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
74 | u32 tmp; | |
b1dc332c | 75 | |
7dec0606 | 76 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
77 | |
78 | if (!(tmp & LVDS_PORT_EN)) | |
79 | return false; | |
80 | ||
81 | if (HAS_PCH_CPT(dev)) | |
82 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
83 | else | |
84 | *pipe = PORT_TO_PIPE(tmp); | |
85 | ||
86 | return true; | |
87 | } | |
88 | ||
045ac3b5 JB |
89 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
90 | struct intel_crtc_config *pipe_config) | |
91 | { | |
92 | struct drm_device *dev = encoder->base.dev; | |
93 | struct drm_i915_private *dev_priv = dev->dev_private; | |
94 | u32 lvds_reg, tmp, flags = 0; | |
95 | ||
96 | if (HAS_PCH_SPLIT(dev)) | |
97 | lvds_reg = PCH_LVDS; | |
98 | else | |
99 | lvds_reg = LVDS; | |
100 | ||
101 | tmp = I915_READ(lvds_reg); | |
102 | if (tmp & LVDS_HSYNC_POLARITY) | |
103 | flags |= DRM_MODE_FLAG_NHSYNC; | |
104 | else | |
105 | flags |= DRM_MODE_FLAG_PHSYNC; | |
106 | if (tmp & LVDS_VSYNC_POLARITY) | |
107 | flags |= DRM_MODE_FLAG_NVSYNC; | |
108 | else | |
109 | flags |= DRM_MODE_FLAG_PVSYNC; | |
110 | ||
111 | pipe_config->adjusted_mode.flags |= flags; | |
112 | } | |
113 | ||
fc683091 DV |
114 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
115 | * This is an exception to the general rule that mode_set doesn't turn | |
116 | * things on. | |
117 | */ | |
118 | static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) | |
119 | { | |
120 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
121 | struct drm_device *dev = encoder->base.dev; | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
124 | struct drm_display_mode *fixed_mode = | |
125 | lvds_encoder->attached_connector->base.panel.fixed_mode; | |
126 | int pipe = intel_crtc->pipe; | |
127 | u32 temp; | |
128 | ||
fc683091 DV |
129 | temp = I915_READ(lvds_encoder->reg); |
130 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
131 | |
132 | if (HAS_PCH_CPT(dev)) { | |
133 | temp &= ~PORT_TRANS_SEL_MASK; | |
134 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 135 | } else { |
62810e5a DV |
136 | if (pipe == 1) { |
137 | temp |= LVDS_PIPEB_SELECT; | |
138 | } else { | |
139 | temp &= ~LVDS_PIPEB_SELECT; | |
140 | } | |
fc683091 | 141 | } |
62810e5a | 142 | |
fc683091 | 143 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 144 | temp &= ~LVDS_BORDER_ENABLE; |
68fc8742 | 145 | temp |= intel_crtc->config.gmch_pfit.lvds_border_bits; |
fc683091 DV |
146 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
147 | * set the DPLLs for dual-channel mode or not. | |
148 | */ | |
149 | if (lvds_encoder->is_dual_link) | |
150 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
151 | else | |
152 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
153 | ||
154 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
155 | * appropriately here, but we need to look more thoroughly into how | |
156 | * panels behave in the two modes. | |
157 | */ | |
62810e5a DV |
158 | |
159 | /* Set the dithering flag on LVDS as needed, note that there is no | |
160 | * special lvds dither control bit on pch-split platforms, dithering is | |
161 | * only controlled through the PIPECONF reg. */ | |
162 | if (INTEL_INFO(dev)->gen == 4) { | |
d8b32247 DV |
163 | /* Bspec wording suggests that LVDS port dithering only exists |
164 | * for 18bpp panels. */ | |
165 | if (intel_crtc->config.dither && | |
166 | intel_crtc->config.pipe_bpp == 18) | |
fc683091 DV |
167 | temp |= LVDS_ENABLE_DITHER; |
168 | else | |
169 | temp &= ~LVDS_ENABLE_DITHER; | |
170 | } | |
171 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
172 | if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
173 | temp |= LVDS_HSYNC_POLARITY; | |
174 | if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
175 | temp |= LVDS_VSYNC_POLARITY; | |
176 | ||
177 | I915_WRITE(lvds_encoder->reg, temp); | |
178 | } | |
179 | ||
79e53945 JB |
180 | /** |
181 | * Sets the power state for the panel. | |
182 | */ | |
c22834ec | 183 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 184 | { |
c22834ec | 185 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 186 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
c22834ec | 187 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 188 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 189 | u32 ctl_reg, stat_reg; |
541998a1 | 190 | |
c619eed4 | 191 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 192 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 193 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
194 | } else { |
195 | ctl_reg = PP_CONTROL; | |
de842eff | 196 | stat_reg = PP_STATUS; |
541998a1 | 197 | } |
79e53945 | 198 | |
7dec0606 | 199 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 200 | |
2a1292fd | 201 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 202 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
203 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
204 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 205 | |
24ded204 | 206 | intel_panel_enable_backlight(dev, intel_crtc->pipe); |
2a1292fd CW |
207 | } |
208 | ||
c22834ec | 209 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 210 | { |
c22834ec | 211 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 212 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2a1292fd | 213 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 214 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
215 | |
216 | if (HAS_PCH_SPLIT(dev)) { | |
217 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 218 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
219 | } else { |
220 | ctl_reg = PP_CONTROL; | |
de842eff | 221 | stat_reg = PP_STATUS; |
2a1292fd CW |
222 | } |
223 | ||
47356eb6 | 224 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
225 | |
226 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
227 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
228 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 229 | |
7dec0606 DV |
230 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
231 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
232 | } |
233 | ||
79e53945 JB |
234 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
235 | struct drm_display_mode *mode) | |
236 | { | |
dd06f90e JN |
237 | struct intel_connector *intel_connector = to_intel_connector(connector); |
238 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 239 | |
788319d4 CW |
240 | if (mode->hdisplay > fixed_mode->hdisplay) |
241 | return MODE_PANEL; | |
242 | if (mode->vdisplay > fixed_mode->vdisplay) | |
243 | return MODE_PANEL; | |
79e53945 JB |
244 | |
245 | return MODE_OK; | |
246 | } | |
247 | ||
7ae89233 DV |
248 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
249 | struct intel_crtc_config *pipe_config) | |
79e53945 | 250 | { |
7ae89233 | 251 | struct drm_device *dev = intel_encoder->base.dev; |
79e53945 | 252 | struct drm_i915_private *dev_priv = dev->dev_private; |
7ae89233 DV |
253 | struct intel_lvds_encoder *lvds_encoder = |
254 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
255 | struct intel_connector *intel_connector = |
256 | &lvds_encoder->attached_connector->base; | |
7ae89233 | 257 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
29b99b48 | 258 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
4e53c2e0 | 259 | unsigned int lvds_bpp; |
79e53945 JB |
260 | |
261 | /* Should never happen!! */ | |
a6c45cf0 | 262 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 263 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
264 | return false; |
265 | } | |
266 | ||
4e53c2e0 DV |
267 | if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == |
268 | LVDS_A3_POWER_UP) | |
269 | lvds_bpp = 8*3; | |
270 | else | |
271 | lvds_bpp = 6*3; | |
272 | ||
e29c22c0 | 273 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
274 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
275 | pipe_config->pipe_bpp, lvds_bpp); | |
276 | pipe_config->pipe_bpp = lvds_bpp; | |
277 | } | |
d8b32247 | 278 | |
79e53945 | 279 | /* |
71677043 | 280 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
281 | * to the adjusted mode. The CRTC will be set up for this mode, |
282 | * with the panel scaling set up to source from the H/VDisplay | |
283 | * of the original mode. | |
284 | */ | |
4d891523 | 285 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 286 | adjusted_mode); |
1d8e1c75 CW |
287 | |
288 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
289 | pipe_config->has_pch_encoder = true; |
290 | ||
b074cec8 JB |
291 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
292 | intel_connector->panel.fitting_mode); | |
1d8e1c75 | 293 | return true; |
2dd24552 JB |
294 | } else { |
295 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
296 | intel_connector->panel.fitting_mode); | |
1d8e1c75 | 297 | } |
79e53945 | 298 | |
f9bef081 | 299 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
7ae89233 | 300 | pipe_config->timings_set = true; |
f9bef081 | 301 | |
79e53945 JB |
302 | /* |
303 | * XXX: It would be nice to support lower refresh rates on the | |
304 | * panels to reduce power consumption, and perhaps match the | |
305 | * user's requested refresh rate. | |
306 | */ | |
307 | ||
308 | return true; | |
309 | } | |
310 | ||
79e53945 JB |
311 | static void intel_lvds_mode_set(struct drm_encoder *encoder, |
312 | struct drm_display_mode *mode, | |
313 | struct drm_display_mode *adjusted_mode) | |
314 | { | |
79e53945 JB |
315 | /* |
316 | * The LVDS pin pair will already have been turned on in the | |
317 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
318 | * settings. | |
319 | */ | |
79e53945 JB |
320 | } |
321 | ||
322 | /** | |
323 | * Detect the LVDS connection. | |
324 | * | |
b42d4c5c JB |
325 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
326 | * connected and closed means disconnected. We also send hotplug events as | |
327 | * needed, using lid status notification from the input layer. | |
79e53945 | 328 | */ |
7b334fcb | 329 | static enum drm_connector_status |
930a9e28 | 330 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 331 | { |
7b9c5abe | 332 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 333 | enum drm_connector_status status; |
b42d4c5c | 334 | |
fe16d949 CW |
335 | status = intel_panel_detect(dev); |
336 | if (status != connector_status_unknown) | |
337 | return status; | |
01fe9dbd | 338 | |
6ee3b5a1 | 339 | return connector_status_connected; |
79e53945 JB |
340 | } |
341 | ||
342 | /** | |
343 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
344 | */ | |
345 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
346 | { | |
62165e0d | 347 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 348 | struct drm_device *dev = connector->dev; |
788319d4 | 349 | struct drm_display_mode *mode; |
79e53945 | 350 | |
9cd300e0 | 351 | /* use cached edid if we have one */ |
2aa4f099 | 352 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 353 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 354 | |
dd06f90e | 355 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 356 | if (mode == NULL) |
788319d4 | 357 | return 0; |
79e53945 | 358 | |
788319d4 CW |
359 | drm_mode_probed_add(connector, mode); |
360 | return 1; | |
79e53945 JB |
361 | } |
362 | ||
0544edfd TB |
363 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
364 | { | |
bc0daf48 | 365 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
366 | return 1; |
367 | } | |
368 | ||
369 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
370 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
371 | { | |
372 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
373 | .ident = "Toshiba Tecra A11", | |
374 | .matches = { | |
375 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
376 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
377 | }, | |
378 | }, | |
379 | ||
380 | { } /* terminating entry */ | |
381 | }; | |
382 | ||
c9354c85 | 383 | /* |
b8efb17b ZR |
384 | * Lid events. Note the use of 'modeset': |
385 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
386 | * and set it to MODESET_DONE on open | |
c9354c85 | 387 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
388 | * duplicate events where it was already properly set) |
389 | * - the suspend/resume paths will set it to | |
390 | * MODESET_SUSPENDED and ignore the lid open event, | |
391 | * because they restore the mode ("lid open"). | |
c9354c85 | 392 | */ |
c1c7af60 JB |
393 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
394 | void *unused) | |
395 | { | |
db1740a0 JN |
396 | struct intel_lvds_connector *lvds_connector = |
397 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
398 | struct drm_connector *connector = &lvds_connector->base.base; | |
399 | struct drm_device *dev = connector->dev; | |
400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 401 | |
2fb4e61d AW |
402 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
403 | return NOTIFY_OK; | |
404 | ||
b8efb17b ZR |
405 | mutex_lock(&dev_priv->modeset_restore_lock); |
406 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
407 | goto exit; | |
a2565377 ZY |
408 | /* |
409 | * check and update the status of LVDS connector after receiving | |
410 | * the LID nofication event. | |
411 | */ | |
db1740a0 | 412 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 413 | |
0544edfd TB |
414 | /* Don't force modeset on machines where it causes a GPU lockup */ |
415 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 416 | goto exit; |
c9354c85 | 417 | if (!acpi_lid_open()) { |
b8efb17b ZR |
418 | /* do modeset on next lid open event */ |
419 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
420 | goto exit; | |
06891e27 | 421 | } |
c1c7af60 | 422 | |
b8efb17b ZR |
423 | if (dev_priv->modeset_restore == MODESET_DONE) |
424 | goto exit; | |
c9354c85 | 425 | |
a0e99e68 | 426 | drm_modeset_lock_all(dev); |
45e2b5f6 | 427 | intel_modeset_setup_hw_state(dev, true); |
a0e99e68 | 428 | drm_modeset_unlock_all(dev); |
06324194 | 429 | |
b8efb17b ZR |
430 | dev_priv->modeset_restore = MODESET_DONE; |
431 | ||
432 | exit: | |
433 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
434 | return NOTIFY_OK; |
435 | } | |
436 | ||
79e53945 JB |
437 | /** |
438 | * intel_lvds_destroy - unregister and free LVDS structures | |
439 | * @connector: connector to free | |
440 | * | |
441 | * Unregister the DDC bus for this connector then free the driver private | |
442 | * structure. | |
443 | */ | |
444 | static void intel_lvds_destroy(struct drm_connector *connector) | |
445 | { | |
db1740a0 JN |
446 | struct intel_lvds_connector *lvds_connector = |
447 | to_lvds_connector(connector); | |
79e53945 | 448 | |
db1740a0 JN |
449 | if (lvds_connector->lid_notifier.notifier_call) |
450 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 451 | |
9cd300e0 JN |
452 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
453 | kfree(lvds_connector->base.edid); | |
454 | ||
1d508706 | 455 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 456 | |
79e53945 JB |
457 | drm_sysfs_connector_remove(connector); |
458 | drm_connector_cleanup(connector); | |
459 | kfree(connector); | |
460 | } | |
461 | ||
335041ed JB |
462 | static int intel_lvds_set_property(struct drm_connector *connector, |
463 | struct drm_property *property, | |
464 | uint64_t value) | |
465 | { | |
4d891523 | 466 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 467 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 468 | |
788319d4 | 469 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 470 | struct drm_crtc *crtc; |
bb8a3560 | 471 | |
53bd8389 JB |
472 | if (value == DRM_MODE_SCALE_NONE) { |
473 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 474 | return -EINVAL; |
3fbe18d6 | 475 | } |
788319d4 | 476 | |
4d891523 | 477 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
478 | /* the LVDS scaling property is not changed */ |
479 | return 0; | |
480 | } | |
4d891523 | 481 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
482 | |
483 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
484 | if (crtc && crtc->enabled) { |
485 | /* | |
486 | * If the CRTC is enabled, the display will be changed | |
487 | * according to the new panel fitting mode. | |
488 | */ | |
c0c36b94 | 489 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
490 | } |
491 | } | |
492 | ||
335041ed JB |
493 | return 0; |
494 | } | |
495 | ||
79e53945 | 496 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
79e53945 | 497 | .mode_set = intel_lvds_mode_set, |
79e53945 JB |
498 | }; |
499 | ||
500 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
501 | .get_modes = intel_lvds_get_modes, | |
502 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 503 | .best_encoder = intel_best_encoder, |
79e53945 JB |
504 | }; |
505 | ||
506 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 507 | .dpms = intel_connector_dpms, |
79e53945 JB |
508 | .detect = intel_lvds_detect, |
509 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 510 | .set_property = intel_lvds_set_property, |
79e53945 JB |
511 | .destroy = intel_lvds_destroy, |
512 | }; | |
513 | ||
79e53945 | 514 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 515 | .destroy = intel_encoder_destroy, |
79e53945 JB |
516 | }; |
517 | ||
425d244c JW |
518 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
519 | { | |
bc0daf48 | 520 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
521 | return 1; |
522 | } | |
79e53945 | 523 | |
425d244c | 524 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 525 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
526 | { |
527 | .callback = intel_no_lvds_dmi_callback, | |
528 | .ident = "Apple Mac Mini (Core series)", | |
529 | .matches = { | |
98acd46f | 530 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
531 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
532 | }, | |
533 | }, | |
534 | { | |
535 | .callback = intel_no_lvds_dmi_callback, | |
536 | .ident = "Apple Mac Mini (Core 2 series)", | |
537 | .matches = { | |
98acd46f | 538 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
539 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
540 | }, | |
541 | }, | |
542 | { | |
543 | .callback = intel_no_lvds_dmi_callback, | |
544 | .ident = "MSI IM-945GSE-A", | |
545 | .matches = { | |
546 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
547 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
548 | }, | |
549 | }, | |
550 | { | |
551 | .callback = intel_no_lvds_dmi_callback, | |
552 | .ident = "Dell Studio Hybrid", | |
553 | .matches = { | |
554 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
555 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
556 | }, | |
557 | }, | |
70aa96ca JW |
558 | { |
559 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
560 | .ident = "Dell OptiPlex FX170", |
561 | .matches = { | |
562 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
563 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
564 | }, | |
565 | }, | |
566 | { | |
567 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
568 | .ident = "AOpen Mini PC", |
569 | .matches = { | |
570 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
571 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
572 | }, | |
573 | }, | |
ed8c754b TV |
574 | { |
575 | .callback = intel_no_lvds_dmi_callback, | |
576 | .ident = "AOpen Mini PC MP915", | |
577 | .matches = { | |
578 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
579 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
580 | }, | |
581 | }, | |
22ab70d3 KP |
582 | { |
583 | .callback = intel_no_lvds_dmi_callback, | |
584 | .ident = "AOpen i915GMm-HFS", | |
585 | .matches = { | |
586 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
587 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
588 | }, | |
589 | }, | |
e57b6886 DV |
590 | { |
591 | .callback = intel_no_lvds_dmi_callback, | |
592 | .ident = "AOpen i45GMx-I", | |
593 | .matches = { | |
594 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
595 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
596 | }, | |
597 | }, | |
fa0864b2 MC |
598 | { |
599 | .callback = intel_no_lvds_dmi_callback, | |
600 | .ident = "Aopen i945GTt-VFA", | |
601 | .matches = { | |
602 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
603 | }, | |
604 | }, | |
9875557e SB |
605 | { |
606 | .callback = intel_no_lvds_dmi_callback, | |
607 | .ident = "Clientron U800", | |
608 | .matches = { | |
609 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
610 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
611 | }, | |
612 | }, | |
6a574b5b | 613 | { |
44306ab3 JS |
614 | .callback = intel_no_lvds_dmi_callback, |
615 | .ident = "Clientron E830", | |
616 | .matches = { | |
617 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
618 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
619 | }, | |
620 | }, | |
621 | { | |
6a574b5b HG |
622 | .callback = intel_no_lvds_dmi_callback, |
623 | .ident = "Asus EeeBox PC EB1007", | |
624 | .matches = { | |
625 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
626 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
627 | }, | |
628 | }, | |
0999bbe0 AJ |
629 | { |
630 | .callback = intel_no_lvds_dmi_callback, | |
631 | .ident = "Asus AT5NM10T-I", | |
632 | .matches = { | |
633 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
634 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
635 | }, | |
636 | }, | |
33471119 JBG |
637 | { |
638 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 639 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
640 | .matches = { |
641 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 642 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
643 | }, |
644 | }, | |
f5b8a7ed MG |
645 | { |
646 | .callback = intel_no_lvds_dmi_callback, | |
647 | .ident = "Hewlett-Packard t5745", | |
648 | .matches = { | |
649 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 650 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
651 | }, |
652 | }, | |
653 | { | |
654 | .callback = intel_no_lvds_dmi_callback, | |
655 | .ident = "Hewlett-Packard st5747", | |
656 | .matches = { | |
657 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 658 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
659 | }, |
660 | }, | |
97effadb AA |
661 | { |
662 | .callback = intel_no_lvds_dmi_callback, | |
663 | .ident = "MSI Wind Box DC500", | |
664 | .matches = { | |
665 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
666 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
667 | }, | |
668 | }, | |
a51d4ed0 CW |
669 | { |
670 | .callback = intel_no_lvds_dmi_callback, | |
671 | .ident = "Gigabyte GA-D525TUD", | |
672 | .matches = { | |
673 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
674 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
675 | }, | |
676 | }, | |
c31407a3 CW |
677 | { |
678 | .callback = intel_no_lvds_dmi_callback, | |
679 | .ident = "Supermicro X7SPA-H", | |
680 | .matches = { | |
681 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
682 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
683 | }, | |
684 | }, | |
9e9dd0e8 CL |
685 | { |
686 | .callback = intel_no_lvds_dmi_callback, | |
687 | .ident = "Fujitsu Esprimo Q900", | |
688 | .matches = { | |
689 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
690 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
691 | }, | |
692 | }, | |
425d244c JW |
693 | |
694 | { } /* terminating entry */ | |
695 | }; | |
79e53945 | 696 | |
18f9ed12 ZY |
697 | /** |
698 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
699 | * @dev: drm device | |
700 | * @connector: LVDS connector | |
701 | * | |
702 | * Find the reduced downclock for LVDS in EDID. | |
703 | */ | |
704 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
705 | struct drm_display_mode *fixed_mode, |
706 | struct drm_connector *connector) | |
18f9ed12 ZY |
707 | { |
708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 709 | struct drm_display_mode *scan; |
18f9ed12 ZY |
710 | int temp_downclock; |
711 | ||
788319d4 | 712 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
713 | list_for_each_entry(scan, &connector->probed_modes, head) { |
714 | /* | |
715 | * If one mode has the same resolution with the fixed_panel | |
716 | * mode while they have the different refresh rate, it means | |
717 | * that the reduced downclock is found for the LVDS. In such | |
718 | * case we can set the different FPx0/1 to dynamically select | |
719 | * between low and high frequency. | |
720 | */ | |
788319d4 CW |
721 | if (scan->hdisplay == fixed_mode->hdisplay && |
722 | scan->hsync_start == fixed_mode->hsync_start && | |
723 | scan->hsync_end == fixed_mode->hsync_end && | |
724 | scan->htotal == fixed_mode->htotal && | |
725 | scan->vdisplay == fixed_mode->vdisplay && | |
726 | scan->vsync_start == fixed_mode->vsync_start && | |
727 | scan->vsync_end == fixed_mode->vsync_end && | |
728 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
729 | if (scan->clock < temp_downclock) { |
730 | /* | |
731 | * The downclock is already found. But we | |
732 | * expect to find the lower downclock. | |
733 | */ | |
734 | temp_downclock = scan->clock; | |
735 | } | |
736 | } | |
737 | } | |
788319d4 | 738 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
739 | /* We found the downclock for LVDS. */ |
740 | dev_priv->lvds_downclock_avail = 1; | |
741 | dev_priv->lvds_downclock = temp_downclock; | |
742 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
743 | "Normal clock %dKhz, downclock %dKhz\n", |
744 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 745 | } |
18f9ed12 ZY |
746 | } |
747 | ||
7cf4f69d ZY |
748 | /* |
749 | * Enumerate the child dev array parsed from VBT to check whether | |
750 | * the LVDS is present. | |
751 | * If it is present, return 1. | |
752 | * If it is not present, return false. | |
753 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 754 | */ |
270eea0f CW |
755 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
756 | u8 *i2c_pin) | |
7cf4f69d ZY |
757 | { |
758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 759 | int i; |
7cf4f69d | 760 | |
41aa3448 | 761 | if (!dev_priv->vbt.child_dev_num) |
425904dd | 762 | return true; |
7cf4f69d | 763 | |
41aa3448 RV |
764 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
765 | struct child_device_config *child = dev_priv->vbt.child_dev + i; | |
425904dd CW |
766 | |
767 | /* If the device type is not LFP, continue. | |
768 | * We have to check both the new identifiers as well as the | |
769 | * old for compatibility with some BIOSes. | |
7cf4f69d | 770 | */ |
425904dd CW |
771 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
772 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
773 | continue; |
774 | ||
3bd7d909 DK |
775 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
776 | *i2c_pin = child->i2c_pin; | |
270eea0f | 777 | |
425904dd CW |
778 | /* However, we cannot trust the BIOS writers to populate |
779 | * the VBT correctly. Since LVDS requires additional | |
780 | * information from AIM blocks, a non-zero addin offset is | |
781 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 782 | */ |
425904dd CW |
783 | if (child->addin_offset) |
784 | return true; | |
785 | ||
786 | /* But even then some BIOS writers perform some black magic | |
787 | * and instantiate the device without reference to any | |
788 | * additional data. Trust that if the VBT was written into | |
789 | * the OpRegion then they have validated the LVDS's existence. | |
790 | */ | |
791 | if (dev_priv->opregion.vbt) | |
792 | return true; | |
7cf4f69d | 793 | } |
425904dd CW |
794 | |
795 | return false; | |
7cf4f69d ZY |
796 | } |
797 | ||
1974cad0 DV |
798 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
799 | { | |
800 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
801 | return 1; | |
802 | } | |
803 | ||
804 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
805 | { | |
806 | .callback = intel_dual_link_lvds_callback, | |
807 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
808 | .matches = { | |
809 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
810 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
811 | }, | |
812 | }, | |
813 | { } /* terminating entry */ | |
814 | }; | |
815 | ||
816 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
817 | { |
818 | struct intel_encoder *encoder; | |
819 | struct intel_lvds_encoder *lvds_encoder; | |
820 | ||
821 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
822 | base.head) { | |
823 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
824 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
825 | ||
826 | return lvds_encoder->is_dual_link; | |
827 | } | |
828 | } | |
829 | ||
830 | return false; | |
831 | } | |
832 | ||
7dec0606 | 833 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 834 | { |
7dec0606 | 835 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
836 | unsigned int val; |
837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
838 | |
839 | /* use the module option value if specified */ | |
840 | if (i915_lvds_channel_mode > 0) | |
841 | return i915_lvds_channel_mode == 2; | |
842 | ||
843 | if (dmi_check_system(intel_dual_link_lvds)) | |
844 | return true; | |
845 | ||
13c7d870 DV |
846 | /* BIOS should set the proper LVDS register value at boot, but |
847 | * in reality, it doesn't set the value when the lid is closed; | |
848 | * we need to check "the value to be set" in VBT when LVDS | |
849 | * register is uninitialized. | |
850 | */ | |
7dec0606 | 851 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 852 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 853 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 854 | |
1974cad0 DV |
855 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
856 | } | |
857 | ||
f3cfcba6 CW |
858 | static bool intel_lvds_supported(struct drm_device *dev) |
859 | { | |
860 | /* With the introduction of the PCH we gained a dedicated | |
861 | * LVDS presence pin, use it. */ | |
311e359c | 862 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
863 | return true; |
864 | ||
865 | /* Otherwise LVDS was only attached to mobile products, | |
866 | * except for the inglorious 830gm */ | |
311e359c PZ |
867 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
868 | return true; | |
869 | ||
870 | return false; | |
f3cfcba6 CW |
871 | } |
872 | ||
79e53945 JB |
873 | /** |
874 | * intel_lvds_init - setup LVDS connectors on this device | |
875 | * @dev: drm device | |
876 | * | |
877 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
878 | * modes we can display on the LVDS panel (if present). | |
879 | */ | |
c9093354 | 880 | void intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
881 | { |
882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 883 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 884 | struct intel_encoder *intel_encoder; |
c7362c4d | 885 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 886 | struct intel_connector *intel_connector; |
79e53945 JB |
887 | struct drm_connector *connector; |
888 | struct drm_encoder *encoder; | |
889 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 890 | struct drm_display_mode *fixed_mode = NULL; |
9cd300e0 | 891 | struct edid *edid; |
79e53945 JB |
892 | struct drm_crtc *crtc; |
893 | u32 lvds; | |
270eea0f CW |
894 | int pipe; |
895 | u8 pin; | |
79e53945 | 896 | |
f3cfcba6 | 897 | if (!intel_lvds_supported(dev)) |
c9093354 | 898 | return; |
f3cfcba6 | 899 | |
425d244c JW |
900 | /* Skip init on machines we know falsely report LVDS */ |
901 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 902 | return; |
565dcd46 | 903 | |
270eea0f CW |
904 | pin = GMBUS_PORT_PANEL; |
905 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 906 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c9093354 | 907 | return; |
38b3037e | 908 | } |
e99da35f | 909 | |
c619eed4 | 910 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 911 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c9093354 | 912 | return; |
41aa3448 | 913 | if (dev_priv->vbt.edp_support) { |
28c97730 | 914 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 915 | return; |
32f9d658 | 916 | } |
541998a1 ZW |
917 | } |
918 | ||
29b99b48 JN |
919 | lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); |
920 | if (!lvds_encoder) | |
c9093354 | 921 | return; |
79e53945 | 922 | |
c7362c4d JN |
923 | lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); |
924 | if (!lvds_connector) { | |
29b99b48 | 925 | kfree(lvds_encoder); |
c9093354 | 926 | return; |
bb8a3560 ZW |
927 | } |
928 | ||
62165e0d JN |
929 | lvds_encoder->attached_connector = lvds_connector; |
930 | ||
29b99b48 | 931 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 932 | encoder = &intel_encoder->base; |
c7362c4d | 933 | intel_connector = &lvds_connector->base; |
ea5b213a | 934 | connector = &intel_connector->base; |
bb8a3560 | 935 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
936 | DRM_MODE_CONNECTOR_LVDS); |
937 | ||
4ef69c7a | 938 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
939 | DRM_MODE_ENCODER_LVDS); |
940 | ||
c22834ec | 941 | intel_encoder->enable = intel_enable_lvds; |
fc683091 | 942 | intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; |
7ae89233 | 943 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 944 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c | 945 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 946 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 947 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
c22834ec | 948 | |
df0e9248 | 949 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 950 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 951 | |
66a9278e | 952 | intel_encoder->cloneable = false; |
27f8227b JB |
953 | if (HAS_PCH_SPLIT(dev)) |
954 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
955 | else if (IS_GEN4(dev)) |
956 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
957 | else |
958 | intel_encoder->crtc_mask = (1 << 1); | |
959 | ||
79e53945 JB |
960 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
961 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
962 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
963 | connector->interlace_allowed = false; | |
964 | connector->doublescan_allowed = false; | |
965 | ||
7dec0606 DV |
966 | if (HAS_PCH_SPLIT(dev)) { |
967 | lvds_encoder->reg = PCH_LVDS; | |
968 | } else { | |
969 | lvds_encoder->reg = LVDS; | |
970 | } | |
971 | ||
3fbe18d6 ZY |
972 | /* create the scaling mode property */ |
973 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 974 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 975 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 976 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 977 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
978 | /* |
979 | * LVDS discovery: | |
980 | * 1) check for EDID on DDC | |
981 | * 2) check for VBT data | |
982 | * 3) check to see if LVDS is already on | |
983 | * if none of the above, no panel | |
984 | * 4) make sure lid is open | |
985 | * if closed, act like it's not there for now | |
986 | */ | |
987 | ||
79e53945 JB |
988 | /* |
989 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
990 | * preferred mode is the right one. | |
991 | */ | |
9cd300e0 JN |
992 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
993 | if (edid) { | |
994 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 995 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 996 | edid); |
3f8ff0e7 | 997 | } else { |
9cd300e0 JN |
998 | kfree(edid); |
999 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1000 | } |
9cd300e0 JN |
1001 | } else { |
1002 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1003 | } |
9cd300e0 JN |
1004 | lvds_connector->base.edid = edid; |
1005 | ||
1006 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1007 | /* Didn't get an EDID, so |
1008 | * Set wide sync ranges so we get all modes | |
1009 | * handed to valid_mode for checking | |
1010 | */ | |
1011 | connector->display_info.min_vfreq = 0; | |
1012 | connector->display_info.max_vfreq = 200; | |
1013 | connector->display_info.min_hfreq = 0; | |
1014 | connector->display_info.max_hfreq = 200; | |
1015 | } | |
79e53945 JB |
1016 | |
1017 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1018 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1019 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1020 | drm_mode_debug_printmodeline(scan); | |
1021 | ||
dd06f90e | 1022 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 CW |
1023 | if (fixed_mode) { |
1024 | intel_find_lvds_downclock(dev, fixed_mode, | |
1025 | connector); | |
1026 | goto out; | |
1027 | } | |
79e53945 | 1028 | } |
79e53945 JB |
1029 | } |
1030 | ||
1031 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1032 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1033 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1034 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1035 | |
41aa3448 | 1036 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1037 | if (fixed_mode) { |
1038 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1039 | goto out; |
1040 | } | |
79e53945 JB |
1041 | } |
1042 | ||
1043 | /* | |
1044 | * If we didn't get EDID, try checking if the panel is already turned | |
1045 | * on. If so, assume that whatever is currently programmed is the | |
1046 | * correct mode. | |
1047 | */ | |
541998a1 | 1048 | |
f2b115e6 | 1049 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1050 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1051 | goto failed; |
1052 | ||
79e53945 JB |
1053 | lvds = I915_READ(LVDS); |
1054 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1055 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1056 | |
1057 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1058 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1059 | if (fixed_mode) { | |
6a9d51b7 CW |
1060 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1061 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1062 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1063 | goto out; |
79e53945 JB |
1064 | } |
1065 | } | |
1066 | ||
1067 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1068 | if (!fixed_mode) |
79e53945 JB |
1069 | goto failed; |
1070 | ||
79e53945 | 1071 | out: |
7dec0606 | 1072 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1073 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1074 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1075 | ||
24ded204 DV |
1076 | /* |
1077 | * Unlock registers and just | |
1078 | * leave them unlocked | |
1079 | */ | |
c619eed4 | 1080 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1081 | I915_WRITE(PCH_PP_CONTROL, |
1082 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1083 | } else { | |
ed10fca9 KP |
1084 | I915_WRITE(PP_CONTROL, |
1085 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1086 | } |
db1740a0 JN |
1087 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1088 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1089 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1090 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1091 | } |
79e53945 | 1092 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1093 | |
dd06f90e | 1094 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 1095 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1096 | |
c9093354 | 1097 | return; |
79e53945 JB |
1098 | |
1099 | failed: | |
8a4c47f3 | 1100 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1101 | drm_connector_cleanup(connector); |
1991bdfa | 1102 | drm_encoder_cleanup(encoder); |
dd06f90e JN |
1103 | if (fixed_mode) |
1104 | drm_mode_destroy(dev, fixed_mode); | |
29b99b48 | 1105 | kfree(lvds_encoder); |
c7362c4d | 1106 | kfree(lvds_connector); |
c9093354 | 1107 | return; |
79e53945 | 1108 | } |