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drm/i915: Fix __wait_seqno to use true infinite timeouts
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
1fa61106 46static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 47{
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 u32 fbc_ctl;
50
51 /* Disable compression */
52 fbc_ctl = I915_READ(FBC_CONTROL);
53 if ((fbc_ctl & FBC_CTL_EN) == 0)
54 return;
55
56 fbc_ctl &= ~FBC_CTL_EN;
57 I915_WRITE(FBC_CONTROL, fbc_ctl);
58
59 /* Wait for compressing bit to clear */
60 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
61 DRM_DEBUG_KMS("FBC idle timed out\n");
62 return;
63 }
64
65 DRM_DEBUG_KMS("disabled FBC\n");
66}
67
1fa61106 68static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 69{
70 struct drm_device *dev = crtc->dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 struct drm_framebuffer *fb = crtc->fb;
73 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
74 struct drm_i915_gem_object *obj = intel_fb->obj;
75 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
76 int cfb_pitch;
77 int plane, i;
78 u32 fbc_ctl, fbc_ctl2;
79
5c3fe8b0 80 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 81 if (fb->pitches[0] < cfb_pitch)
82 cfb_pitch = fb->pitches[0];
83
84 /* FBC_CTL wants 64B units */
85 cfb_pitch = (cfb_pitch / 64) - 1;
86 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
87
88 /* Clear old tags */
89 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
90 I915_WRITE(FBC_TAG + (i * 4), 0);
91
92 /* Set it up... */
93 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
94 fbc_ctl2 |= plane;
95 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
96 I915_WRITE(FBC_FENCE_OFF, crtc->y);
97
98 /* enable it... */
99 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
100 if (IS_I945GM(dev))
101 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
102 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
103 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
104 fbc_ctl |= obj->fence_reg;
105 I915_WRITE(FBC_CONTROL, fbc_ctl);
106
84f44ce7
VS		 107 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
108 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 109}
110
1fa61106 111static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 112{
113 struct drm_i915_private *dev_priv = dev->dev_private;
114
115 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
116}
117
1fa61106 118static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 119{
120 struct drm_device *dev = crtc->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct drm_framebuffer *fb = crtc->fb;
123 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
124 struct drm_i915_gem_object *obj = intel_fb->obj;
125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
126 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
127 unsigned long stall_watermark = 200;
128 u32 dpfc_ctl;
129
130 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
131 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
132 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
133
134 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
135 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
136 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
137 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
138
139 /* enable it... */
140 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
141
84f44ce7 142 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 143}
144
1fa61106 145static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 146{
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 u32 dpfc_ctl;
149
150 /* Disable compression */
151 dpfc_ctl = I915_READ(DPFC_CONTROL);
152 if (dpfc_ctl & DPFC_CTL_EN) {
153 dpfc_ctl &= ~DPFC_CTL_EN;
154 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
155
156 DRM_DEBUG_KMS("disabled FBC\n");
157 }
158}
159
1fa61106 160static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 161{
162 struct drm_i915_private *dev_priv = dev->dev_private;
163
164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
165}
166
167static void sandybridge_blit_fbc_update(struct drm_device *dev)
168{
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u32 blt_ecoskpd;
171
172 /* Make sure blitter notifies FBC of writes */
173 gen6_gt_force_wake_get(dev_priv);
174 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
175 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
176 GEN6_BLITTER_LOCK_SHIFT;
177 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
178 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
179 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
180 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
181 GEN6_BLITTER_LOCK_SHIFT);
182 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
183 POSTING_READ(GEN6_BLITTER_ECOSKPD);
184 gen6_gt_force_wake_put(dev_priv);
185}
186
1fa61106 187static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 188{
189 struct drm_device *dev = crtc->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct drm_framebuffer *fb = crtc->fb;
192 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
193 struct drm_i915_gem_object *obj = intel_fb->obj;
194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
195 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
196 unsigned long stall_watermark = 200;
197 u32 dpfc_ctl;
198
199 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
200 dpfc_ctl &= DPFC_RESERVED;
201 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
202 /* Set persistent mode for front-buffer rendering, ala X. */
203 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
206
207 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
208 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
209 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
210 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 211 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 212 /* enable it... */
213 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
214
215 if (IS_GEN6(dev)) {
216 I915_WRITE(SNB_DPFC_CTL_SA,
217 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
218 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
219 sandybridge_blit_fbc_update(dev);
220 }
221
84f44ce7 222 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 223}
224
1fa61106 225static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 226{
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 dpfc_ctl;
229
230 /* Disable compression */
231 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
232 if (dpfc_ctl & DPFC_CTL_EN) {
233 dpfc_ctl &= ~DPFC_CTL_EN;
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
235
b74ea102 236 if (IS_IVYBRIDGE(dev))
7dd23ba0 237 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 238 I915_WRITE(ILK_DSPCLK_GATE_D,
239 I915_READ(ILK_DSPCLK_GATE_D) &
240 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
241
d89f2071 242 if (IS_HASWELL(dev))
7dd23ba0 243 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 244 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
245 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
246 ~HSW_DPFC_GATING_DISABLE);
247
85208be0
ED		 248 DRM_DEBUG_KMS("disabled FBC\n");
249 }
250}
251
1fa61106 252static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
257}
258
abe959c7
RV		 259static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
260{
261 struct drm_device *dev = crtc->dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_framebuffer *fb = crtc->fb;
264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
265 struct drm_i915_gem_object *obj = intel_fb->obj;
266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
267
f343c5f6 268 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 269
270 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
271 IVB_DPFC_CTL_FENCE_EN |
272 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
273
891348b2 274 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 275 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 276 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 277 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 278 I915_WRITE(ILK_DSPCLK_GATE_D,
279 I915_READ(ILK_DSPCLK_GATE_D) |
280 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 281 } else {
7dd23ba0 282 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 283 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
284 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 286 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
287 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
288 HSW_DPFC_GATING_DISABLE);
891348b2 289 }
b74ea102 290
abe959c7
RV		 291 I915_WRITE(SNB_DPFC_CTL_SA,
292 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
293 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
294
295 sandybridge_blit_fbc_update(dev);
296
297 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
298}
299
85208be0
ED		 300bool intel_fbc_enabled(struct drm_device *dev)
301{
302 struct drm_i915_private *dev_priv = dev->dev_private;
303
304 if (!dev_priv->display.fbc_enabled)
305 return false;
306
307 return dev_priv->display.fbc_enabled(dev);
308}
309
310static void intel_fbc_work_fn(struct work_struct *__work)
311{
312 struct intel_fbc_work *work =
313 container_of(to_delayed_work(__work),
314 struct intel_fbc_work, work);
315 struct drm_device *dev = work->crtc->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317
318 mutex_lock(&dev->struct_mutex);
5c3fe8b0 319 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 320 /* Double check that we haven't switched fb without cancelling
321 * the prior work.
322 */
323 if (work->crtc->fb == work->fb) {
324 dev_priv->display.enable_fbc(work->crtc,
325 work->interval);
326
5c3fe8b0
BW		 327 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
328 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
329 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 330 }
331
5c3fe8b0 332 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 333 }
334 mutex_unlock(&dev->struct_mutex);
335
336 kfree(work);
337}
338
339static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
340{
5c3fe8b0 341 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 342 return;
343
344 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
345
346 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 347 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 348 * entirely asynchronously.
349 */
5c3fe8b0 350 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 351 /* tasklet was killed before being run, clean up */
5c3fe8b0 352 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 353
354 /* Mark the work as no longer wanted so that if it does
355 * wake-up (because the work was already running and waiting
356 * for our mutex), it will discover that is no longer
357 * necessary to run.
358 */
5c3fe8b0 359 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 360}
361
b63fb44c 362static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 363{
364 struct intel_fbc_work *work;
365 struct drm_device *dev = crtc->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367
368 if (!dev_priv->display.enable_fbc)
369 return;
370
371 intel_cancel_fbc_work(dev_priv);
372
b14c5679 373 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 374 if (work == NULL) {
6cdcb5e7 375 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 376 dev_priv->display.enable_fbc(crtc, interval);
377 return;
378 }
379
380 work->crtc = crtc;
381 work->fb = crtc->fb;
382 work->interval = interval;
383 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
384
5c3fe8b0 385 dev_priv->fbc.fbc_work = work;
85208be0 386
85208be0
ED		 387 /* Delay the actual enabling to let pageflipping cease and the
388 * display to settle before starting the compression. Note that
389 * this delay also serves a second purpose: it allows for a
390 * vblank to pass after disabling the FBC before we attempt
391 * to modify the control registers.
392 *
393 * A more complicated solution would involve tracking vblanks
394 * following the termination of the page-flipping sequence
395 * and indeed performing the enable as a co-routine and not
396 * waiting synchronously upon the vblank.
7457d617
DL		 397 *
398 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 399 */
400 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
401}
402
403void intel_disable_fbc(struct drm_device *dev)
404{
405 struct drm_i915_private *dev_priv = dev->dev_private;
406
407 intel_cancel_fbc_work(dev_priv);
408
409 if (!dev_priv->display.disable_fbc)
410 return;
411
412 dev_priv->display.disable_fbc(dev);
5c3fe8b0 413 dev_priv->fbc.plane = -1;
85208be0
ED		 414}
415
29ebf90f
CW		 416static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
417 enum no_fbc_reason reason)
418{
419 if (dev_priv->fbc.no_fbc_reason == reason)
420 return false;
421
422 dev_priv->fbc.no_fbc_reason = reason;
423 return true;
424}
425
85208be0
ED		 426/**
427 * intel_update_fbc - enable/disable FBC as needed
428 * @dev: the drm_device
429 *
430 * Set up the framebuffer compression hardware at mode set time. We
431 * enable it if possible:
432 * - plane A only (on pre-965)
433 * - no pixel mulitply/line duplication
434 * - no alpha buffer discard
435 * - no dual wide
f85da868 436 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 437 *
438 * We can't assume that any compression will take place (worst case),
439 * so the compressed buffer has to be the same size as the uncompressed
440 * one. It also must reside (along with the line length buffer) in
441 * stolen memory.
442 *
443 * We need to enable/disable FBC on a global basis.
444 */
445void intel_update_fbc(struct drm_device *dev)
446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 struct drm_crtc *crtc = NULL, *tmp_crtc;
449 struct intel_crtc *intel_crtc;
450 struct drm_framebuffer *fb;
451 struct intel_framebuffer *intel_fb;
452 struct drm_i915_gem_object *obj;
ef644fda 453 const struct drm_display_mode *adjusted_mode;
37327abd 454 unsigned int max_width, max_height;
85208be0 455
29ebf90f
CW		 456 if (!I915_HAS_FBC(dev)) {
457 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 458 return;
29ebf90f 459 }
85208be0 460
29ebf90f
CW		 461 if (!i915_powersave) {
462 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
463 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 464 return;
29ebf90f 465 }
85208be0
ED		 466
467 /*
468 * If FBC is already on, we just have to verify that we can
469 * keep it that way...
470 * Need to disable if:
471 * - more than one pipe is active
472 * - changing FBC params (stride, fence, mode)
473 * - new fb is too large to fit in compressed buffer
474 * - going to an unsupported config (interlace, pixel multiply, etc.)
475 */
476 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 477 if (intel_crtc_active(tmp_crtc) &&
478 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0 479 if (crtc) {
29ebf90f
CW		 480 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
481 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 482 goto out_disable;
483 }
484 crtc = tmp_crtc;
485 }
486 }
487
488 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 489 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
490 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 491 goto out_disable;
492 }
493
494 intel_crtc = to_intel_crtc(crtc);
495 fb = crtc->fb;
496 intel_fb = to_intel_framebuffer(fb);
497 obj = intel_fb->obj;
ef644fda 498 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 499
8a5729a3
DL		 500 if (i915_enable_fbc < 0 &&
501 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 502 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
503 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 504 goto out_disable;
85208be0 505 }
8a5729a3 506 if (!i915_enable_fbc) {
29ebf90f
CW		 507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 509 goto out_disable;
510 }
ef644fda
VS		 511 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
512 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
514 DRM_DEBUG_KMS("mode incompatible with compression, "
515 "disabling\n");
85208be0
ED		 516 goto out_disable;
517 }
f85da868
PZ		 518
519 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 520 max_width = 4096;
521 max_height = 2048;
f85da868 522 } else {
37327abd
VS		 523 max_width = 2048;
524 max_height = 1536;
f85da868 525 }
37327abd
VS		 526 if (intel_crtc->config.pipe_src_w > max_width ||
527 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 528 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
529 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
891348b2
RV		 532 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
533 intel_crtc->plane != 0) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
535 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 536 goto out_disable;
537 }
538
539 /* The use of a CPU fence is mandatory in order to detect writes
540 * by the CPU to the scanout and trigger updates to the FBC.
541 */
542 if (obj->tiling_mode != I915_TILING_X ||
543 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 544 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
545 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 546 goto out_disable;
547 }
548
549 /* If the kernel debugger is active, always disable compression */
550 if (in_dbg_master())
551 goto out_disable;
552
11be49eb 553 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 554 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
555 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 556 goto out_disable;
557 }
558
85208be0
ED		 559 /* If the scanout has not changed, don't modify the FBC settings.
560 * Note that we make the fundamental assumption that the fb->obj
561 * cannot be unpinned (and have its GTT offset and fence revoked)
562 * without first being decoupled from the scanout and FBC disabled.
563 */
5c3fe8b0
BW		 564 if (dev_priv->fbc.plane == intel_crtc->plane &&
565 dev_priv->fbc.fb_id == fb->base.id &&
566 dev_priv->fbc.y == crtc->y)
85208be0
ED		 567 return;
568
569 if (intel_fbc_enabled(dev)) {
570 /* We update FBC along two paths, after changing fb/crtc
571 * configuration (modeswitching) and after page-flipping
572 * finishes. For the latter, we know that not only did
573 * we disable the FBC at the start of the page-flip
574 * sequence, but also more than one vblank has passed.
575 *
576 * For the former case of modeswitching, it is possible
577 * to switch between two FBC valid configurations
578 * instantaneously so we do need to disable the FBC
579 * before we can modify its control registers. We also
580 * have to wait for the next vblank for that to take
581 * effect. However, since we delay enabling FBC we can
582 * assume that a vblank has passed since disabling and
583 * that we can safely alter the registers in the deferred
584 * callback.
585 *
586 * In the scenario that we go from a valid to invalid
587 * and then back to valid FBC configuration we have
588 * no strict enforcement that a vblank occurred since
589 * disabling the FBC. However, along all current pipe
590 * disabling paths we do need to wait for a vblank at
591 * some point. And we wait before enabling FBC anyway.
592 */
593 DRM_DEBUG_KMS("disabling active FBC for update\n");
594 intel_disable_fbc(dev);
595 }
596
597 intel_enable_fbc(crtc, 500);
29ebf90f 598 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 599 return;
600
601out_disable:
602 /* Multiple disables should be harmless */
603 if (intel_fbc_enabled(dev)) {
604 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
605 intel_disable_fbc(dev);
606 }
11be49eb 607 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 608}
609
c921aba8
DV		 610static void i915_pineview_get_mem_freq(struct drm_device *dev)
611{
612 drm_i915_private_t *dev_priv = dev->dev_private;
613 u32 tmp;
614
615 tmp = I915_READ(CLKCFG);
616
617 switch (tmp & CLKCFG_FSB_MASK) {
618 case CLKCFG_FSB_533:
619 dev_priv->fsb_freq = 533; /* 133*4 */
620 break;
621 case CLKCFG_FSB_800:
622 dev_priv->fsb_freq = 800; /* 200*4 */
623 break;
624 case CLKCFG_FSB_667:
625 dev_priv->fsb_freq = 667; /* 167*4 */
626 break;
627 case CLKCFG_FSB_400:
628 dev_priv->fsb_freq = 400; /* 100*4 */
629 break;
630 }
631
632 switch (tmp & CLKCFG_MEM_MASK) {
633 case CLKCFG_MEM_533:
634 dev_priv->mem_freq = 533;
635 break;
636 case CLKCFG_MEM_667:
637 dev_priv->mem_freq = 667;
638 break;
639 case CLKCFG_MEM_800:
640 dev_priv->mem_freq = 800;
641 break;
642 }
643
644 /* detect pineview DDR3 setting */
645 tmp = I915_READ(CSHRDDR3CTL);
646 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
647}
648
649static void i915_ironlake_get_mem_freq(struct drm_device *dev)
650{
651 drm_i915_private_t *dev_priv = dev->dev_private;
652 u16 ddrpll, csipll;
653
654 ddrpll = I915_READ16(DDRMPLL1);
655 csipll = I915_READ16(CSIPLL0);
656
657 switch (ddrpll & 0xff) {
658 case 0xc:
659 dev_priv->mem_freq = 800;
660 break;
661 case 0x10:
662 dev_priv->mem_freq = 1066;
663 break;
664 case 0x14:
665 dev_priv->mem_freq = 1333;
666 break;
667 case 0x18:
668 dev_priv->mem_freq = 1600;
669 break;
670 default:
671 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
672 ddrpll & 0xff);
673 dev_priv->mem_freq = 0;
674 break;
675 }
676
20e4d407 677 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 678
679 switch (csipll & 0x3ff) {
680 case 0x00c:
681 dev_priv->fsb_freq = 3200;
682 break;
683 case 0x00e:
684 dev_priv->fsb_freq = 3733;
685 break;
686 case 0x010:
687 dev_priv->fsb_freq = 4266;
688 break;
689 case 0x012:
690 dev_priv->fsb_freq = 4800;
691 break;
692 case 0x014:
693 dev_priv->fsb_freq = 5333;
694 break;
695 case 0x016:
696 dev_priv->fsb_freq = 5866;
697 break;
698 case 0x018:
699 dev_priv->fsb_freq = 6400;
700 break;
701 default:
702 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
703 csipll & 0x3ff);
704 dev_priv->fsb_freq = 0;
705 break;
706 }
707
708 if (dev_priv->fsb_freq == 3200) {
20e4d407 709 dev_priv->ips.c_m = 0;
c921aba8 710 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 711 dev_priv->ips.c_m = 1;
c921aba8 712 } else {
20e4d407 713 dev_priv->ips.c_m = 2;
c921aba8
DV		 714 }
715}
716
b445e3b0
ED		 717static const struct cxsr_latency cxsr_latency_table[] = {
718 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
719 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
720 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
721 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
722 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
723
724 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
725 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
726 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
727 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
728 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
729
730 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
731 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
732 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
733 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
734 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
735
736 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
737 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
738 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
739 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
740 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
741
742 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
743 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
744 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
745 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
746 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
747
748 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
749 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
750 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
751 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
752 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
753};
754
63c62275 755static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 756 int is_ddr3,
757 int fsb,
758 int mem)
759{
760 const struct cxsr_latency *latency;
761 int i;
762
763 if (fsb == 0 || mem == 0)
764 return NULL;
765
766 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
767 latency = &cxsr_latency_table[i];
768 if (is_desktop == latency->is_desktop &&
769 is_ddr3 == latency->is_ddr3 &&
770 fsb == latency->fsb_freq && mem == latency->mem_freq)
771 return latency;
772 }
773
774 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
775
776 return NULL;
777}
778
1fa61106 779static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 780{
781 struct drm_i915_private *dev_priv = dev->dev_private;
782
783 /* deactivate cxsr */
784 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
785}
786
787/*
788 * Latency for FIFO fetches is dependent on several factors:
789 * - memory configuration (speed, channels)
790 * - chipset
791 * - current MCH state
792 * It can be fairly high in some situations, so here we assume a fairly
793 * pessimal value. It's a tradeoff between extra memory fetches (if we
794 * set this value too high, the FIFO will fetch frequently to stay full)
795 * and power consumption (set it too low to save power and we might see
796 * FIFO underruns and display "flicker").
797 *
798 * A value of 5us seems to be a good balance; safe for very low end
799 * platforms but not overly aggressive on lower latency configs.
800 */
801static const int latency_ns = 5000;
802
1fa61106 803static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 uint32_t dsparb = I915_READ(DSPARB);
807 int size;
808
809 size = dsparb & 0x7f;
810 if (plane)
811 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
812
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
815
816 return size;
817}
818
1fa61106 819static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 820{
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
823 int size;
824
825 size = dsparb & 0x1ff;
826 if (plane)
827 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
828 size >>= 1; /* Convert to cachelines */
829
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
832
833 return size;
834}
835
1fa61106 836static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 837{
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
840 int size;
841
842 size = dsparb & 0x7f;
843 size >>= 2; /* Convert to cachelines */
844
845 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
846 plane ? "B" : "A",
847 size);
848
849 return size;
850}
851
1fa61106 852static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 853{
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 uint32_t dsparb = I915_READ(DSPARB);
856 int size;
857
858 size = dsparb & 0x7f;
859 size >>= 1; /* Convert to cachelines */
860
861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
862 plane ? "B" : "A", size);
863
864 return size;
865}
866
867/* Pineview has different values for various configs */
868static const struct intel_watermark_params pineview_display_wm = {
869 PINEVIEW_DISPLAY_FIFO,
870 PINEVIEW_MAX_WM,
871 PINEVIEW_DFT_WM,
872 PINEVIEW_GUARD_WM,
873 PINEVIEW_FIFO_LINE_SIZE
874};
875static const struct intel_watermark_params pineview_display_hplloff_wm = {
876 PINEVIEW_DISPLAY_FIFO,
877 PINEVIEW_MAX_WM,
878 PINEVIEW_DFT_HPLLOFF_WM,
879 PINEVIEW_GUARD_WM,
880 PINEVIEW_FIFO_LINE_SIZE
881};
882static const struct intel_watermark_params pineview_cursor_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE,
888};
889static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
890 PINEVIEW_CURSOR_FIFO,
891 PINEVIEW_CURSOR_MAX_WM,
892 PINEVIEW_CURSOR_DFT_WM,
893 PINEVIEW_CURSOR_GUARD_WM,
894 PINEVIEW_FIFO_LINE_SIZE
895};
896static const struct intel_watermark_params g4x_wm_info = {
897 G4X_FIFO_SIZE,
898 G4X_MAX_WM,
899 G4X_MAX_WM,
900 2,
901 G4X_FIFO_LINE_SIZE,
902};
903static const struct intel_watermark_params g4x_cursor_wm_info = {
904 I965_CURSOR_FIFO,
905 I965_CURSOR_MAX_WM,
906 I965_CURSOR_DFT_WM,
907 2,
908 G4X_FIFO_LINE_SIZE,
909};
910static const struct intel_watermark_params valleyview_wm_info = {
911 VALLEYVIEW_FIFO_SIZE,
912 VALLEYVIEW_MAX_WM,
913 VALLEYVIEW_MAX_WM,
914 2,
915 G4X_FIFO_LINE_SIZE,
916};
917static const struct intel_watermark_params valleyview_cursor_wm_info = {
918 I965_CURSOR_FIFO,
919 VALLEYVIEW_CURSOR_MAX_WM,
920 I965_CURSOR_DFT_WM,
921 2,
922 G4X_FIFO_LINE_SIZE,
923};
924static const struct intel_watermark_params i965_cursor_wm_info = {
925 I965_CURSOR_FIFO,
926 I965_CURSOR_MAX_WM,
927 I965_CURSOR_DFT_WM,
928 2,
929 I915_FIFO_LINE_SIZE,
930};
931static const struct intel_watermark_params i945_wm_info = {
932 I945_FIFO_SIZE,
933 I915_MAX_WM,
934 1,
935 2,
936 I915_FIFO_LINE_SIZE
937};
938static const struct intel_watermark_params i915_wm_info = {
939 I915_FIFO_SIZE,
940 I915_MAX_WM,
941 1,
942 2,
943 I915_FIFO_LINE_SIZE
944};
945static const struct intel_watermark_params i855_wm_info = {
946 I855GM_FIFO_SIZE,
947 I915_MAX_WM,
948 1,
949 2,
950 I830_FIFO_LINE_SIZE
951};
952static const struct intel_watermark_params i830_wm_info = {
953 I830_FIFO_SIZE,
954 I915_MAX_WM,
955 1,
956 2,
957 I830_FIFO_LINE_SIZE
958};
959
960static const struct intel_watermark_params ironlake_display_wm_info = {
961 ILK_DISPLAY_FIFO,
962 ILK_DISPLAY_MAXWM,
963 ILK_DISPLAY_DFTWM,
964 2,
965 ILK_FIFO_LINE_SIZE
966};
967static const struct intel_watermark_params ironlake_cursor_wm_info = {
968 ILK_CURSOR_FIFO,
969 ILK_CURSOR_MAXWM,
970 ILK_CURSOR_DFTWM,
971 2,
972 ILK_FIFO_LINE_SIZE
973};
974static const struct intel_watermark_params ironlake_display_srwm_info = {
975 ILK_DISPLAY_SR_FIFO,
976 ILK_DISPLAY_MAX_SRWM,
977 ILK_DISPLAY_DFT_SRWM,
978 2,
979 ILK_FIFO_LINE_SIZE
980};
981static const struct intel_watermark_params ironlake_cursor_srwm_info = {
982 ILK_CURSOR_SR_FIFO,
983 ILK_CURSOR_MAX_SRWM,
984 ILK_CURSOR_DFT_SRWM,
985 2,
986 ILK_FIFO_LINE_SIZE
987};
988
989static const struct intel_watermark_params sandybridge_display_wm_info = {
990 SNB_DISPLAY_FIFO,
991 SNB_DISPLAY_MAXWM,
992 SNB_DISPLAY_DFTWM,
993 2,
994 SNB_FIFO_LINE_SIZE
995};
996static const struct intel_watermark_params sandybridge_cursor_wm_info = {
997 SNB_CURSOR_FIFO,
998 SNB_CURSOR_MAXWM,
999 SNB_CURSOR_DFTWM,
1000 2,
1001 SNB_FIFO_LINE_SIZE
1002};
1003static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004 SNB_DISPLAY_SR_FIFO,
1005 SNB_DISPLAY_MAX_SRWM,
1006 SNB_DISPLAY_DFT_SRWM,
1007 2,
1008 SNB_FIFO_LINE_SIZE
1009};
1010static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1011 SNB_CURSOR_SR_FIFO,
1012 SNB_CURSOR_MAX_SRWM,
1013 SNB_CURSOR_DFT_SRWM,
1014 2,
1015 SNB_FIFO_LINE_SIZE
1016};
1017
1018
1019/**
1020 * intel_calculate_wm - calculate watermark level
1021 * @clock_in_khz: pixel clock
1022 * @wm: chip FIFO params
1023 * @pixel_size: display pixel size
1024 * @latency_ns: memory latency for the platform
1025 *
1026 * Calculate the watermark level (the level at which the display plane will
1027 * start fetching from memory again). Each chip has a different display
1028 * FIFO size and allocation, so the caller needs to figure that out and pass
1029 * in the correct intel_watermark_params structure.
1030 *
1031 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032 * on the pixel size. When it reaches the watermark level, it'll start
1033 * fetching FIFO line sized based chunks from memory until the FIFO fills
1034 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1035 * will occur, and a display engine hang could result.
1036 */
1037static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038 const struct intel_watermark_params *wm,
1039 int fifo_size,
1040 int pixel_size,
1041 unsigned long latency_ns)
1042{
1043 long entries_required, wm_size;
1044
1045 /*
1046 * Note: we need to make sure we don't overflow for various clock &
1047 * latency values.
1048 * clocks go from a few thousand to several hundred thousand.
1049 * latency is usually a few thousand
1050 */
1051 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1052 1000;
1053 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1054
1055 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1056
1057 wm_size = fifo_size - (entries_required + wm->guard_size);
1058
1059 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1060
1061 /* Don't promote wm_size to unsigned... */
1062 if (wm_size > (long)wm->max_wm)
1063 wm_size = wm->max_wm;
1064 if (wm_size <= 0)
1065 wm_size = wm->default_wm;
1066 return wm_size;
1067}
1068
1069static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1070{
1071 struct drm_crtc *crtc, *enabled = NULL;
1072
1073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1074 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1075 if (enabled)
1076 return NULL;
1077 enabled = crtc;
1078 }
1079 }
1080
1081 return enabled;
1082}
1083
46ba614c 1084static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1085{
46ba614c 1086 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088 struct drm_crtc *crtc;
1089 const struct cxsr_latency *latency;
1090 u32 reg;
1091 unsigned long wm;
1092
1093 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094 dev_priv->fsb_freq, dev_priv->mem_freq);
1095 if (!latency) {
1096 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097 pineview_disable_cxsr(dev);
1098 return;
1099 }
1100
1101 crtc = single_enabled_crtc(dev);
1102 if (crtc) {
241bfc38 1103 const struct drm_display_mode *adjusted_mode;
b445e3b0 1104 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1105 int clock;
1106
1107 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1109
1110 /* Display SR */
1111 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->display_sr);
1114 reg = I915_READ(DSPFW1);
1115 reg &= ~DSPFW_SR_MASK;
1116 reg |= wm << DSPFW_SR_SHIFT;
1117 I915_WRITE(DSPFW1, reg);
1118 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1119
1120 /* cursor SR */
1121 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122 pineview_display_wm.fifo_size,
1123 pixel_size, latency->cursor_sr);
1124 reg = I915_READ(DSPFW3);
1125 reg &= ~DSPFW_CURSOR_SR_MASK;
1126 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127 I915_WRITE(DSPFW3, reg);
1128
1129 /* Display HPLL off SR */
1130 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131 pineview_display_hplloff_wm.fifo_size,
1132 pixel_size, latency->display_hpll_disable);
1133 reg = I915_READ(DSPFW3);
1134 reg &= ~DSPFW_HPLL_SR_MASK;
1135 reg |= wm & DSPFW_HPLL_SR_MASK;
1136 I915_WRITE(DSPFW3, reg);
1137
1138 /* cursor HPLL off SR */
1139 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140 pineview_display_hplloff_wm.fifo_size,
1141 pixel_size, latency->cursor_hpll_disable);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145 I915_WRITE(DSPFW3, reg);
1146 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1147
1148 /* activate cxsr */
1149 I915_WRITE(DSPFW3,
1150 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1151 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1152 } else {
1153 pineview_disable_cxsr(dev);
1154 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1155 }
1156}
1157
1158static bool g4x_compute_wm0(struct drm_device *dev,
1159 int plane,
1160 const struct intel_watermark_params *display,
1161 int display_latency_ns,
1162 const struct intel_watermark_params *cursor,
1163 int cursor_latency_ns,
1164 int *plane_wm,
1165 int *cursor_wm)
1166{
1167 struct drm_crtc *crtc;
4fe8590a 1168 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1172
1173 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1174 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1177 return false;
1178 }
1179
4fe8590a 1180 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1181 clock = adjusted_mode->crtc_clock;
4fe8590a 1182 htotal = adjusted_mode->htotal;
37327abd 1183 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1184 pixel_size = crtc->fb->bits_per_pixel / 8;
1185
1186 /* Use the small buffer method to calculate plane watermark */
1187 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1189 if (tlb_miss > 0)
1190 entries += tlb_miss;
1191 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192 *plane_wm = entries + display->guard_size;
1193 if (*plane_wm > (int)display->max_wm)
1194 *plane_wm = display->max_wm;
1195
1196 /* Use the large buffer method to calculate cursor watermark */
1197 line_time_us = ((htotal * 1000) / clock);
1198 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199 entries = line_count * 64 * pixel_size;
1200 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1201 if (tlb_miss > 0)
1202 entries += tlb_miss;
1203 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204 *cursor_wm = entries + cursor->guard_size;
1205 if (*cursor_wm > (int)cursor->max_wm)
1206 *cursor_wm = (int)cursor->max_wm;
1207
1208 return true;
1209}
1210
1211/*
1212 * Check the wm result.
1213 *
1214 * If any calculated watermark values is larger than the maximum value that
1215 * can be programmed into the associated watermark register, that watermark
1216 * must be disabled.
1217 */
1218static bool g4x_check_srwm(struct drm_device *dev,
1219 int display_wm, int cursor_wm,
1220 const struct intel_watermark_params *display,
1221 const struct intel_watermark_params *cursor)
1222{
1223 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224 display_wm, cursor_wm);
1225
1226 if (display_wm > display->max_wm) {
1227 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228 display_wm, display->max_wm);
1229 return false;
1230 }
1231
1232 if (cursor_wm > cursor->max_wm) {
1233 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234 cursor_wm, cursor->max_wm);
1235 return false;
1236 }
1237
1238 if (!(display_wm || cursor_wm)) {
1239 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1240 return false;
1241 }
1242
1243 return true;
1244}
1245
1246static bool g4x_compute_srwm(struct drm_device *dev,
1247 int plane,
1248 int latency_ns,
1249 const struct intel_watermark_params *display,
1250 const struct intel_watermark_params *cursor,
1251 int *display_wm, int *cursor_wm)
1252{
1253 struct drm_crtc *crtc;
4fe8590a 1254 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1255 int hdisplay, htotal, pixel_size, clock;
1256 unsigned long line_time_us;
1257 int line_count, line_size;
1258 int small, large;
1259 int entries;
1260
1261 if (!latency_ns) {
1262 *display_wm = *cursor_wm = 0;
1263 return false;
1264 }
1265
1266 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1267 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1268 clock = adjusted_mode->crtc_clock;
4fe8590a 1269 htotal = adjusted_mode->htotal;
37327abd 1270 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1271 pixel_size = crtc->fb->bits_per_pixel / 8;
1272
1273 line_time_us = (htotal * 1000) / clock;
1274 line_count = (latency_ns / line_time_us + 1000) / 1000;
1275 line_size = hdisplay * pixel_size;
1276
1277 /* Use the minimum of the small and large buffer method for primary */
1278 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1279 large = line_count * line_size;
1280
1281 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282 *display_wm = entries + display->guard_size;
1283
1284 /* calculate the self-refresh watermark for display cursor */
1285 entries = line_count * pixel_size * 64;
1286 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1287 *cursor_wm = entries + cursor->guard_size;
1288
1289 return g4x_check_srwm(dev,
1290 *display_wm, *cursor_wm,
1291 display, cursor);
1292}
1293
1294static bool vlv_compute_drain_latency(struct drm_device *dev,
1295 int plane,
1296 int *plane_prec_mult,
1297 int *plane_dl,
1298 int *cursor_prec_mult,
1299 int *cursor_dl)
1300{
1301 struct drm_crtc *crtc;
1302 int clock, pixel_size;
1303 int entries;
1304
1305 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1306 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1307 return false;
1308
241bfc38 1309 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1310 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1311
1312 entries = (clock / 1000) * pixel_size;
1313 *plane_prec_mult = (entries > 256) ?
1314 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1315 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1316 pixel_size);
1317
1318 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1319 *cursor_prec_mult = (entries > 256) ?
1320 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1321 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1322
1323 return true;
1324}
1325
1326/*
1327 * Update drain latency registers of memory arbiter
1328 *
1329 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1331 * latency value.
1332 */
1333
1334static void vlv_update_drain_latency(struct drm_device *dev)
1335{
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1338 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1339 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1340 either 16 or 32 */
1341
1342 /* For plane A, Cursor A */
1343 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1344 &cursor_prec_mult, &cursora_dl)) {
1345 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1347 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1348 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1349
1350 I915_WRITE(VLV_DDL1, cursora_prec |
1351 (cursora_dl << DDL_CURSORA_SHIFT) |
1352 planea_prec | planea_dl);
1353 }
1354
1355 /* For plane B, Cursor B */
1356 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1357 &cursor_prec_mult, &cursorb_dl)) {
1358 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1360 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1361 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1362
1363 I915_WRITE(VLV_DDL2, cursorb_prec |
1364 (cursorb_dl << DDL_CURSORB_SHIFT) |
1365 planeb_prec | planeb_dl);
1366 }
1367}
1368
1369#define single_plane_enabled(mask) is_power_of_2(mask)
1370
46ba614c 1371static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1372{
46ba614c 1373 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
af6c4575 1378 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1379 unsigned int enabled = 0;
1380
1381 vlv_update_drain_latency(dev);
1382
51cea1f4 1383 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1384 &valleyview_wm_info, latency_ns,
1385 &valleyview_cursor_wm_info, latency_ns,
1386 &planea_wm, &cursora_wm))
51cea1f4 1387 enabled |= 1 << PIPE_A;
b445e3b0 1388
51cea1f4 1389 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1390 &valleyview_wm_info, latency_ns,
1391 &valleyview_cursor_wm_info, latency_ns,
1392 &planeb_wm, &cursorb_wm))
51cea1f4 1393 enabled |= 1 << PIPE_B;
b445e3b0 1394
b445e3b0
ED		 1395 if (single_plane_enabled(enabled) &&
1396 g4x_compute_srwm(dev, ffs(enabled) - 1,
1397 sr_latency_ns,
1398 &valleyview_wm_info,
1399 &valleyview_cursor_wm_info,
af6c4575
CW		 1400 &plane_sr, &ignore_cursor_sr) &&
1401 g4x_compute_srwm(dev, ffs(enabled) - 1,
1402 2*sr_latency_ns,
1403 &valleyview_wm_info,
1404 &valleyview_cursor_wm_info,
52bd02d8 1405 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1406 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1407 } else {
b445e3b0
ED		 1408 I915_WRITE(FW_BLC_SELF_VLV,
1409 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1410 plane_sr = cursor_sr = 0;
1411 }
b445e3b0
ED		 1412
1413 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414 planea_wm, cursora_wm,
1415 planeb_wm, cursorb_wm,
1416 plane_sr, cursor_sr);
1417
1418 I915_WRITE(DSPFW1,
1419 (plane_sr << DSPFW_SR_SHIFT) |
1420 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1422 planea_wm);
1423 I915_WRITE(DSPFW2,
8c919b28 1424 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1425 (cursora_wm << DSPFW_CURSORA_SHIFT));
1426 I915_WRITE(DSPFW3,
8c919b28
CW		 1427 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1429}
1430
46ba614c 1431static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1432{
46ba614c 1433 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1434 static const int sr_latency_ns = 12000;
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1437 int plane_sr, cursor_sr;
1438 unsigned int enabled = 0;
1439
51cea1f4 1440 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1441 &g4x_wm_info, latency_ns,
1442 &g4x_cursor_wm_info, latency_ns,
1443 &planea_wm, &cursora_wm))
51cea1f4 1444 enabled |= 1 << PIPE_A;
b445e3b0 1445
51cea1f4 1446 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1447 &g4x_wm_info, latency_ns,
1448 &g4x_cursor_wm_info, latency_ns,
1449 &planeb_wm, &cursorb_wm))
51cea1f4 1450 enabled |= 1 << PIPE_B;
b445e3b0 1451
b445e3b0
ED		 1452 if (single_plane_enabled(enabled) &&
1453 g4x_compute_srwm(dev, ffs(enabled) - 1,
1454 sr_latency_ns,
1455 &g4x_wm_info,
1456 &g4x_cursor_wm_info,
52bd02d8 1457 &plane_sr, &cursor_sr)) {
b445e3b0 1458 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1459 } else {
b445e3b0
ED		 1460 I915_WRITE(FW_BLC_SELF,
1461 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1462 plane_sr = cursor_sr = 0;
1463 }
b445e3b0
ED		 1464
1465 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1466 planea_wm, cursora_wm,
1467 planeb_wm, cursorb_wm,
1468 plane_sr, cursor_sr);
1469
1470 I915_WRITE(DSPFW1,
1471 (plane_sr << DSPFW_SR_SHIFT) |
1472 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1473 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1474 planea_wm);
1475 I915_WRITE(DSPFW2,
8c919b28 1476 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1477 (cursora_wm << DSPFW_CURSORA_SHIFT));
1478 /* HPLL off in SR has some issues on G4x... disable it */
1479 I915_WRITE(DSPFW3,
8c919b28 1480 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1481 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1482}
1483
46ba614c 1484static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1485{
46ba614c 1486 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 struct drm_crtc *crtc;
1489 int srwm = 1;
1490 int cursor_sr = 16;
1491
1492 /* Calc sr entries for one plane configs */
1493 crtc = single_enabled_crtc(dev);
1494 if (crtc) {
1495 /* self-refresh has much higher latency */
1496 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1497 const struct drm_display_mode *adjusted_mode =
1498 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1499 int clock = adjusted_mode->crtc_clock;
4fe8590a 1500 int htotal = adjusted_mode->htotal;
37327abd 1501 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1502 int pixel_size = crtc->fb->bits_per_pixel / 8;
1503 unsigned long line_time_us;
1504 int entries;
1505
1506 line_time_us = ((htotal * 1000) / clock);
1507
1508 /* Use ns/us then divide to preserve precision */
1509 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510 pixel_size * hdisplay;
1511 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512 srwm = I965_FIFO_SIZE - entries;
1513 if (srwm < 0)
1514 srwm = 1;
1515 srwm &= 0x1ff;
1516 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1517 entries, srwm);
1518
1519 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1520 pixel_size * 64;
1521 entries = DIV_ROUND_UP(entries,
1522 i965_cursor_wm_info.cacheline_size);
1523 cursor_sr = i965_cursor_wm_info.fifo_size -
1524 (entries + i965_cursor_wm_info.guard_size);
1525
1526 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527 cursor_sr = i965_cursor_wm_info.max_wm;
1528
1529 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530 "cursor %d\n", srwm, cursor_sr);
1531
1532 if (IS_CRESTLINE(dev))
1533 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1534 } else {
1535 /* Turn off self refresh if both pipes are enabled */
1536 if (IS_CRESTLINE(dev))
1537 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1538 & ~FW_BLC_SELF_EN);
1539 }
1540
1541 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1542 srwm);
1543
1544 /* 965 has limitations... */
1545 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1546 (8 << 16) | (8 << 8) | (8 << 0));
1547 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1548 /* update cursor SR watermark */
1549 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1550}
1551
46ba614c 1552static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1553{
46ba614c 1554 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 const struct intel_watermark_params *wm_info;
1557 uint32_t fwater_lo;
1558 uint32_t fwater_hi;
1559 int cwm, srwm = 1;
1560 int fifo_size;
1561 int planea_wm, planeb_wm;
1562 struct drm_crtc *crtc, *enabled = NULL;
1563
1564 if (IS_I945GM(dev))
1565 wm_info = &i945_wm_info;
1566 else if (!IS_GEN2(dev))
1567 wm_info = &i915_wm_info;
1568 else
1569 wm_info = &i855_wm_info;
1570
1571 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1573 if (intel_crtc_active(crtc)) {
241bfc38 1574 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1575 int cpp = crtc->fb->bits_per_pixel / 8;
1576 if (IS_GEN2(dev))
1577 cpp = 4;
1578
241bfc38
DL		 1579 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1580 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1581 wm_info, fifo_size, cpp,
b445e3b0
ED		 1582 latency_ns);
1583 enabled = crtc;
1584 } else
1585 planea_wm = fifo_size - wm_info->guard_size;
1586
1587 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1588 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1589 if (intel_crtc_active(crtc)) {
241bfc38 1590 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1591 int cpp = crtc->fb->bits_per_pixel / 8;
1592 if (IS_GEN2(dev))
1593 cpp = 4;
1594
241bfc38
DL		 1595 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1596 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1597 wm_info, fifo_size, cpp,
b445e3b0
ED		 1598 latency_ns);
1599 if (enabled == NULL)
1600 enabled = crtc;
1601 else
1602 enabled = NULL;
1603 } else
1604 planeb_wm = fifo_size - wm_info->guard_size;
1605
1606 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1607
1608 /*
1609 * Overlay gets an aggressive default since video jitter is bad.
1610 */
1611 cwm = 2;
1612
1613 /* Play safe and disable self-refresh before adjusting watermarks. */
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1616 else if (IS_I915GM(dev))
1617 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1618
1619 /* Calc sr entries for one plane configs */
1620 if (HAS_FW_BLC(dev) && enabled) {
1621 /* self-refresh has much higher latency */
1622 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1623 const struct drm_display_mode *adjusted_mode =
1624 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1625 int clock = adjusted_mode->crtc_clock;
4fe8590a 1626 int htotal = adjusted_mode->htotal;
37327abd 1627 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1628 int pixel_size = enabled->fb->bits_per_pixel / 8;
1629 unsigned long line_time_us;
1630 int entries;
1631
1632 line_time_us = (htotal * 1000) / clock;
1633
1634 /* Use ns/us then divide to preserve precision */
1635 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636 pixel_size * hdisplay;
1637 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1638 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1639 srwm = wm_info->fifo_size - entries;
1640 if (srwm < 0)
1641 srwm = 1;
1642
1643 if (IS_I945G(dev) || IS_I945GM(dev))
1644 I915_WRITE(FW_BLC_SELF,
1645 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1646 else if (IS_I915GM(dev))
1647 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1648 }
1649
1650 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1651 planea_wm, planeb_wm, cwm, srwm);
1652
1653 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1654 fwater_hi = (cwm & 0x1f);
1655
1656 /* Set request length to 8 cachelines per fetch */
1657 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1658 fwater_hi = fwater_hi | (1 << 8);
1659
1660 I915_WRITE(FW_BLC, fwater_lo);
1661 I915_WRITE(FW_BLC2, fwater_hi);
1662
1663 if (HAS_FW_BLC(dev)) {
1664 if (enabled) {
1665 if (IS_I945G(dev) || IS_I945GM(dev))
1666 I915_WRITE(FW_BLC_SELF,
1667 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1668 else if (IS_I915GM(dev))
1669 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1670 DRM_DEBUG_KMS("memory self refresh enabled\n");
1671 } else
1672 DRM_DEBUG_KMS("memory self refresh disabled\n");
1673 }
1674}
1675
46ba614c 1676static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1677{
46ba614c 1678 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_crtc *crtc;
241bfc38 1681 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1682 uint32_t fwater_lo;
1683 int planea_wm;
1684
1685 crtc = single_enabled_crtc(dev);
1686 if (crtc == NULL)
1687 return;
1688
241bfc38
DL		 1689 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1691 &i830_wm_info,
b445e3b0 1692 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1693 4, latency_ns);
b445e3b0
ED		 1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1696
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699 I915_WRITE(FW_BLC, fwater_lo);
1700}
1701
b445e3b0
ED		 1702/*
1703 * Check the wm result.
1704 *
1705 * If any calculated watermark values is larger than the maximum value that
1706 * can be programmed into the associated watermark register, that watermark
1707 * must be disabled.
1708 */
1709static bool ironlake_check_srwm(struct drm_device *dev, int level,
1710 int fbc_wm, int display_wm, int cursor_wm,
1711 const struct intel_watermark_params *display,
1712 const struct intel_watermark_params *cursor)
1713{
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715
1716 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1717 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1718
1719 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1720 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1721 fbc_wm, SNB_FBC_MAX_SRWM, level);
1722
1723 /* fbc has it's own way to disable FBC WM */
1724 I915_WRITE(DISP_ARB_CTL,
1725 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1726 return false;
615aaa5f
VS		 1727 } else if (INTEL_INFO(dev)->gen >= 6) {
1728 /* enable FBC WM (except on ILK, where it must remain off) */
1729 I915_WRITE(DISP_ARB_CTL,
1730 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1731 }
1732
1733 if (display_wm > display->max_wm) {
1734 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1735 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1736 return false;
1737 }
1738
1739 if (cursor_wm > cursor->max_wm) {
1740 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1741 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1742 return false;
1743 }
1744
1745 if (!(fbc_wm || display_wm || cursor_wm)) {
1746 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1747 return false;
1748 }
1749
1750 return true;
1751}
1752
1753/*
1754 * Compute watermark values of WM[1-3],
1755 */
1756static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1757 int latency_ns,
1758 const struct intel_watermark_params *display,
1759 const struct intel_watermark_params *cursor,
1760 int *fbc_wm, int *display_wm, int *cursor_wm)
1761{
1762 struct drm_crtc *crtc;
4fe8590a 1763 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1764 unsigned long line_time_us;
1765 int hdisplay, htotal, pixel_size, clock;
1766 int line_count, line_size;
1767 int small, large;
1768 int entries;
1769
1770 if (!latency_ns) {
1771 *fbc_wm = *display_wm = *cursor_wm = 0;
1772 return false;
1773 }
1774
1775 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1776 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1777 clock = adjusted_mode->crtc_clock;
4fe8590a 1778 htotal = adjusted_mode->htotal;
37327abd 1779 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1780 pixel_size = crtc->fb->bits_per_pixel / 8;
1781
1782 line_time_us = (htotal * 1000) / clock;
1783 line_count = (latency_ns / line_time_us + 1000) / 1000;
1784 line_size = hdisplay * pixel_size;
1785
1786 /* Use the minimum of the small and large buffer method for primary */
1787 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1788 large = line_count * line_size;
1789
1790 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1791 *display_wm = entries + display->guard_size;
1792
1793 /*
1794 * Spec says:
1795 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1796 */
1797 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1798
1799 /* calculate the self-refresh watermark for display cursor */
1800 entries = line_count * pixel_size * 64;
1801 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1802 *cursor_wm = entries + cursor->guard_size;
1803
1804 return ironlake_check_srwm(dev, level,
1805 *fbc_wm, *display_wm, *cursor_wm,
1806 display, cursor);
1807}
1808
46ba614c 1809static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1810{
46ba614c 1811 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 int fbc_wm, plane_wm, cursor_wm;
1814 unsigned int enabled;
1815
1816 enabled = 0;
51cea1f4 1817 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1818 &ironlake_display_wm_info,
b0aea5dc 1819 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1820 &ironlake_cursor_wm_info,
b0aea5dc 1821 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1822 &plane_wm, &cursor_wm)) {
1823 I915_WRITE(WM0_PIPEA_ILK,
1824 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1825 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1826 " plane %d, " "cursor: %d\n",
1827 plane_wm, cursor_wm);
51cea1f4 1828 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1829 }
1830
51cea1f4 1831 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1832 &ironlake_display_wm_info,
b0aea5dc 1833 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1834 &ironlake_cursor_wm_info,
b0aea5dc 1835 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1836 &plane_wm, &cursor_wm)) {
1837 I915_WRITE(WM0_PIPEB_ILK,
1838 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1839 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1840 " plane %d, cursor: %d\n",
1841 plane_wm, cursor_wm);
51cea1f4 1842 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1843 }
1844
1845 /*
1846 * Calculate and update the self-refresh watermark only when one
1847 * display plane is used.
1848 */
1849 I915_WRITE(WM3_LP_ILK, 0);
1850 I915_WRITE(WM2_LP_ILK, 0);
1851 I915_WRITE(WM1_LP_ILK, 0);
1852
1853 if (!single_plane_enabled(enabled))
1854 return;
1855 enabled = ffs(enabled) - 1;
1856
1857 /* WM1 */
1858 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1859 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1860 &ironlake_display_srwm_info,
1861 &ironlake_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1863 return;
1864
1865 I915_WRITE(WM1_LP_ILK,
1866 WM1_LP_SR_EN |
b0aea5dc 1867 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1870 cursor_wm);
1871
1872 /* WM2 */
1873 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1874 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1875 &ironlake_display_srwm_info,
1876 &ironlake_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1878 return;
1879
1880 I915_WRITE(WM2_LP_ILK,
1881 WM2_LP_EN |
b0aea5dc 1882 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1885 cursor_wm);
1886
1887 /*
1888 * WM3 is unsupported on ILK, probably because we don't have latency
1889 * data for that power state
1890 */
1891}
1892
46ba614c 1893static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1894{
46ba614c 1895 struct drm_device *dev = crtc->dev;
b445e3b0 1896 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1897 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1898 u32 val;
1899 int fbc_wm, plane_wm, cursor_wm;
1900 unsigned int enabled;
1901
1902 enabled = 0;
51cea1f4 1903 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1904 &sandybridge_display_wm_info, latency,
1905 &sandybridge_cursor_wm_info, latency,
1906 &plane_wm, &cursor_wm)) {
1907 val = I915_READ(WM0_PIPEA_ILK);
1908 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909 I915_WRITE(WM0_PIPEA_ILK, val |
1910 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1912 " plane %d, " "cursor: %d\n",
1913 plane_wm, cursor_wm);
51cea1f4 1914 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1915 }
1916
51cea1f4 1917 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1918 &sandybridge_display_wm_info, latency,
1919 &sandybridge_cursor_wm_info, latency,
1920 &plane_wm, &cursor_wm)) {
1921 val = I915_READ(WM0_PIPEB_ILK);
1922 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923 I915_WRITE(WM0_PIPEB_ILK, val |
1924 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1926 " plane %d, cursor: %d\n",
1927 plane_wm, cursor_wm);
51cea1f4 1928 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1929 }
1930
c43d0188
CW		 1931 /*
1932 * Calculate and update the self-refresh watermark only when one
1933 * display plane is used.
1934 *
1935 * SNB support 3 levels of watermark.
1936 *
1937 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938 * and disabled in the descending order
1939 *
1940 */
1941 I915_WRITE(WM3_LP_ILK, 0);
1942 I915_WRITE(WM2_LP_ILK, 0);
1943 I915_WRITE(WM1_LP_ILK, 0);
1944
1945 if (!single_plane_enabled(enabled) ||
1946 dev_priv->sprite_scaling_enabled)
1947 return;
1948 enabled = ffs(enabled) - 1;
1949
1950 /* WM1 */
1951 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1952 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1953 &sandybridge_display_srwm_info,
1954 &sandybridge_cursor_srwm_info,
1955 &fbc_wm, &plane_wm, &cursor_wm))
1956 return;
1957
1958 I915_WRITE(WM1_LP_ILK,
1959 WM1_LP_SR_EN |
b0aea5dc 1960 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1961 (fbc_wm << WM1_LP_FBC_SHIFT) |
1962 (plane_wm << WM1_LP_SR_SHIFT) |
1963 cursor_wm);
1964
1965 /* WM2 */
1966 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1967 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1968 &sandybridge_display_srwm_info,
1969 &sandybridge_cursor_srwm_info,
1970 &fbc_wm, &plane_wm, &cursor_wm))
1971 return;
1972
1973 I915_WRITE(WM2_LP_ILK,
1974 WM2_LP_EN |
b0aea5dc 1975 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1976 (fbc_wm << WM1_LP_FBC_SHIFT) |
1977 (plane_wm << WM1_LP_SR_SHIFT) |
1978 cursor_wm);
1979
1980 /* WM3 */
1981 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1982 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1983 &sandybridge_display_srwm_info,
1984 &sandybridge_cursor_srwm_info,
1985 &fbc_wm, &plane_wm, &cursor_wm))
1986 return;
1987
1988 I915_WRITE(WM3_LP_ILK,
1989 WM3_LP_EN |
b0aea5dc 1990 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1991 (fbc_wm << WM1_LP_FBC_SHIFT) |
1992 (plane_wm << WM1_LP_SR_SHIFT) |
1993 cursor_wm);
1994}
1995
46ba614c 1996static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 1997{
46ba614c 1998 struct drm_device *dev = crtc->dev;
c43d0188 1999 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2000 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 2001 u32 val;
2002 int fbc_wm, plane_wm, cursor_wm;
2003 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2004 unsigned int enabled;
2005
2006 enabled = 0;
51cea1f4 2007 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 2008 &sandybridge_display_wm_info, latency,
2009 &sandybridge_cursor_wm_info, latency,
2010 &plane_wm, &cursor_wm)) {
2011 val = I915_READ(WM0_PIPEA_ILK);
2012 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2013 I915_WRITE(WM0_PIPEA_ILK, val |
2014 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2015 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2016 " plane %d, " "cursor: %d\n",
2017 plane_wm, cursor_wm);
51cea1f4 2018 enabled |= 1 << PIPE_A;
c43d0188
CW		 2019 }
2020
51cea1f4 2021 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2022 &sandybridge_display_wm_info, latency,
2023 &sandybridge_cursor_wm_info, latency,
2024 &plane_wm, &cursor_wm)) {
2025 val = I915_READ(WM0_PIPEB_ILK);
2026 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2027 I915_WRITE(WM0_PIPEB_ILK, val |
2028 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2029 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2030 " plane %d, cursor: %d\n",
2031 plane_wm, cursor_wm);
51cea1f4 2032 enabled |= 1 << PIPE_B;
c43d0188
CW		 2033 }
2034
51cea1f4 2035 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2036 &sandybridge_display_wm_info, latency,
2037 &sandybridge_cursor_wm_info, latency,
2038 &plane_wm, &cursor_wm)) {
2039 val = I915_READ(WM0_PIPEC_IVB);
2040 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2041 I915_WRITE(WM0_PIPEC_IVB, val |
2042 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2043 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2044 " plane %d, cursor: %d\n",
2045 plane_wm, cursor_wm);
51cea1f4 2046 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2047 }
2048
2049 /*
2050 * Calculate and update the self-refresh watermark only when one
2051 * display plane is used.
2052 *
2053 * SNB support 3 levels of watermark.
2054 *
2055 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2056 * and disabled in the descending order
2057 *
2058 */
2059 I915_WRITE(WM3_LP_ILK, 0);
2060 I915_WRITE(WM2_LP_ILK, 0);
2061 I915_WRITE(WM1_LP_ILK, 0);
2062
2063 if (!single_plane_enabled(enabled) ||
2064 dev_priv->sprite_scaling_enabled)
2065 return;
2066 enabled = ffs(enabled) - 1;
2067
2068 /* WM1 */
2069 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2070 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2071 &sandybridge_display_srwm_info,
2072 &sandybridge_cursor_srwm_info,
2073 &fbc_wm, &plane_wm, &cursor_wm))
2074 return;
2075
2076 I915_WRITE(WM1_LP_ILK,
2077 WM1_LP_SR_EN |
b0aea5dc 2078 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2079 (fbc_wm << WM1_LP_FBC_SHIFT) |
2080 (plane_wm << WM1_LP_SR_SHIFT) |
2081 cursor_wm);
2082
2083 /* WM2 */
2084 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2085 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2086 &sandybridge_display_srwm_info,
2087 &sandybridge_cursor_srwm_info,
2088 &fbc_wm, &plane_wm, &cursor_wm))
2089 return;
2090
2091 I915_WRITE(WM2_LP_ILK,
2092 WM2_LP_EN |
b0aea5dc 2093 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2094 (fbc_wm << WM1_LP_FBC_SHIFT) |
2095 (plane_wm << WM1_LP_SR_SHIFT) |
2096 cursor_wm);
2097
c43d0188 2098 /* WM3, note we have to correct the cursor latency */
b445e3b0 2099 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2100 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2101 &sandybridge_display_srwm_info,
2102 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2103 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2104 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2105 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2106 &sandybridge_display_srwm_info,
2107 &sandybridge_cursor_srwm_info,
2108 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2109 return;
2110
2111 I915_WRITE(WM3_LP_ILK,
2112 WM3_LP_EN |
b0aea5dc 2113 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2114 (fbc_wm << WM1_LP_FBC_SHIFT) |
2115 (plane_wm << WM1_LP_SR_SHIFT) |
2116 cursor_wm);
2117}
2118
3658729a
VS		 2119static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2120 struct drm_crtc *crtc)
801bcfff
PZ		 2121{
2122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2123 uint32_t pixel_rate;
801bcfff 2124
241bfc38 2125 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 2126
2127 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2128 * adjust the pixel_rate here. */
2129
fd4daa9c 2130 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2131 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2132 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2133
37327abd
VS		 2134 pipe_w = intel_crtc->config.pipe_src_w;
2135 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2136 pfit_w = (pfit_size >> 16) & 0xFFFF;
2137 pfit_h = pfit_size & 0xFFFF;
2138 if (pipe_w < pfit_w)
2139 pipe_w = pfit_w;
2140 if (pipe_h < pfit_h)
2141 pipe_h = pfit_h;
2142
2143 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2144 pfit_w * pfit_h);
2145 }
2146
2147 return pixel_rate;
2148}
2149
37126462 2150/* latency must be in 0.1us units. */
23297044 2151static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2152 uint32_t latency)
2153{
2154 uint64_t ret;
2155
3312ba65
VS		 2156 if (WARN(latency == 0, "Latency value missing\n"))
2157 return UINT_MAX;
2158
801bcfff
PZ		 2159 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2160 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2161
2162 return ret;
2163}
2164
37126462 2165/* latency must be in 0.1us units. */
23297044 2166static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2167 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2168 uint32_t latency)
2169{
2170 uint32_t ret;
2171
3312ba65
VS		 2172 if (WARN(latency == 0, "Latency value missing\n"))
2173 return UINT_MAX;
2174
801bcfff
PZ		 2175 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2176 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2177 ret = DIV_ROUND_UP(ret, 64) + 2;
2178 return ret;
2179}
2180
23297044 2181static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2182 uint8_t bytes_per_pixel)
2183{
2184 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2185}
2186
801bcfff
PZ		 2187struct hsw_pipe_wm_parameters {
2188 bool active;
801bcfff
PZ		 2189 uint32_t pipe_htotal;
2190 uint32_t pixel_rate;
c35426d2
VS		 2191 struct intel_plane_wm_parameters pri;
2192 struct intel_plane_wm_parameters spr;
2193 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2194};
2195
cca32e9a
PZ		 2196struct hsw_wm_maximums {
2197 uint16_t pri;
2198 uint16_t spr;
2199 uint16_t cur;
2200 uint16_t fbc;
2201};
2202
801bcfff
PZ		 2203struct hsw_wm_values {
2204 uint32_t wm_pipe[3];
2205 uint32_t wm_lp[3];
2206 uint32_t wm_lp_spr[3];
2207 uint32_t wm_linetime[3];
cca32e9a 2208 bool enable_fbc_wm;
801bcfff
PZ		 2209};
2210
240264f4
VS		 2211/* used in computing the new watermarks state */
2212struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
2216 bool fbc_wm_enabled;
2217};
2218
37126462
VS		 2219/*
2220 * For both WM_PIPE and WM_LP.
2221 * mem_value must be in 0.1us units.
2222 */
ac830fe1 2223static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2224 uint32_t mem_value,
2225 bool is_lp)
801bcfff 2226{
cca32e9a
PZ		 2227 uint32_t method1, method2;
2228
c35426d2 2229 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2230 return 0;
2231
23297044 2232 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2233 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2234 mem_value);
2235
2236 if (!is_lp)
2237 return method1;
2238
23297044 2239 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2240 params->pipe_htotal,
c35426d2
VS		 2241 params->pri.horiz_pixels,
2242 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2243 mem_value);
2244
2245 return min(method1, method2);
801bcfff
PZ		 2246}
2247
37126462
VS		 2248/*
2249 * For both WM_PIPE and WM_LP.
2250 * mem_value must be in 0.1us units.
2251 */
ac830fe1 2252static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2253 uint32_t mem_value)
2254{
2255 uint32_t method1, method2;
2256
c35426d2 2257 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2258 return 0;
2259
23297044 2260 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2261 params->spr.bytes_per_pixel,
801bcfff 2262 mem_value);
23297044 2263 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2264 params->pipe_htotal,
c35426d2
VS		 2265 params->spr.horiz_pixels,
2266 params->spr.bytes_per_pixel,
801bcfff
PZ		 2267 mem_value);
2268 return min(method1, method2);
2269}
2270
37126462
VS		 2271/*
2272 * For both WM_PIPE and WM_LP.
2273 * mem_value must be in 0.1us units.
2274 */
ac830fe1 2275static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2276 uint32_t mem_value)
2277{
c35426d2 2278 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2279 return 0;
2280
23297044 2281 return ilk_wm_method2(params->pixel_rate,
801bcfff 2282 params->pipe_htotal,
c35426d2
VS		 2283 params->cur.horiz_pixels,
2284 params->cur.bytes_per_pixel,
801bcfff
PZ		 2285 mem_value);
2286}
2287
cca32e9a 2288/* Only for WM_LP. */
ac830fe1 2289static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2290 uint32_t pri_val)
cca32e9a 2291{
c35426d2 2292 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2293 return 0;
2294
23297044 2295 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2296 params->pri.horiz_pixels,
2297 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2298}
2299
158ae64f
VS		 2300static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2301{
2302 if (INTEL_INFO(dev)->gen >= 7)
2303 return 768;
2304 else
2305 return 512;
2306}
2307
2308/* Calculate the maximum primary/sprite plane watermark */
2309static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2310 int level,
240264f4 2311 const struct intel_wm_config *config,
158ae64f
VS		 2312 enum intel_ddb_partitioning ddb_partitioning,
2313 bool is_sprite)
2314{
2315 unsigned int fifo_size = ilk_display_fifo_size(dev);
2316 unsigned int max;
2317
2318 /* if sprites aren't enabled, sprites get nothing */
240264f4 2319 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2320 return 0;
2321
2322 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2323 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2324 fifo_size /= INTEL_INFO(dev)->num_pipes;
2325
2326 /*
2327 * For some reason the non self refresh
2328 * FIFO size is only half of the self
2329 * refresh FIFO size on ILK/SNB.
2330 */
2331 if (INTEL_INFO(dev)->gen <= 6)
2332 fifo_size /= 2;
2333 }
2334
240264f4 2335 if (config->sprites_enabled) {
158ae64f
VS		 2336 /* level 0 is always calculated with 1:1 split */
2337 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2338 if (is_sprite)
2339 fifo_size *= 5;
2340 fifo_size /= 6;
2341 } else {
2342 fifo_size /= 2;
2343 }
2344 }
2345
2346 /* clamp to max that the registers can hold */
2347 if (INTEL_INFO(dev)->gen >= 7)
2348 /* IVB/HSW primary/sprite plane watermarks */
2349 max = level == 0 ? 127 : 1023;
2350 else if (!is_sprite)
2351 /* ILK/SNB primary plane watermarks */
2352 max = level == 0 ? 127 : 511;
2353 else
2354 /* ILK/SNB sprite plane watermarks */
2355 max = level == 0 ? 63 : 255;
2356
2357 return min(fifo_size, max);
2358}
2359
2360/* Calculate the maximum cursor plane watermark */
2361static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2362 int level,
2363 const struct intel_wm_config *config)
158ae64f
VS		 2364{
2365 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2366 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2367 return 64;
2368
2369 /* otherwise just report max that registers can hold */
2370 if (INTEL_INFO(dev)->gen >= 7)
2371 return level == 0 ? 63 : 255;
2372 else
2373 return level == 0 ? 31 : 63;
2374}
2375
2376/* Calculate the maximum FBC watermark */
2377static unsigned int ilk_fbc_wm_max(void)
2378{
2379 /* max that registers can hold */
2380 return 15;
2381}
2382
2383static void ilk_wm_max(struct drm_device *dev,
2384 int level,
240264f4 2385 const struct intel_wm_config *config,
158ae64f
VS		 2386 enum intel_ddb_partitioning ddb_partitioning,
2387 struct hsw_wm_maximums *max)
2388{
240264f4
VS		 2389 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2390 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2391 max->cur = ilk_cursor_wm_max(dev, level, config);
158ae64f
VS		 2392 max->fbc = ilk_fbc_wm_max();
2393}
2394
a9786a11
VS		 2395static bool ilk_check_wm(int level,
2396 const struct hsw_wm_maximums *max,
1fd527cc 2397 struct intel_wm_level *result)
a9786a11
VS		 2398{
2399 bool ret;
2400
2401 /* already determined to be invalid? */
2402 if (!result->enable)
2403 return false;
2404
2405 result->enable = result->pri_val <= max->pri &&
2406 result->spr_val <= max->spr &&
2407 result->cur_val <= max->cur;
2408
2409 ret = result->enable;
2410
2411 /*
2412 * HACK until we can pre-compute everything,
2413 * and thus fail gracefully if LP0 watermarks
2414 * are exceeded...
2415 */
2416 if (level == 0 && !result->enable) {
2417 if (result->pri_val > max->pri)
2418 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2419 level, result->pri_val, max->pri);
2420 if (result->spr_val > max->spr)
2421 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2422 level, result->spr_val, max->spr);
2423 if (result->cur_val > max->cur)
2424 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2425 level, result->cur_val, max->cur);
2426
2427 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2428 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2429 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2430 result->enable = true;
2431 }
2432
2433 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2434
2435 return ret;
2436}
2437
6f5ddd17
VS		 2438static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2439 int level,
ac830fe1 2440 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2441 struct intel_wm_level *result)
6f5ddd17
VS		 2442{
2443 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2444 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2445 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2446
2447 /* WM1+ latency values stored in 0.5us units */
2448 if (level > 0) {
2449 pri_latency *= 5;
2450 spr_latency *= 5;
2451 cur_latency *= 5;
2452 }
2453
2454 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2455 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2456 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2457 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2458 result->enable = true;
2459}
2460
5b77da33 2461static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
ac830fe1
VS		 2462 int level, const struct hsw_wm_maximums *max,
2463 const struct hsw_pipe_wm_parameters *params,
1fd527cc 2464 struct intel_wm_level *result)
cca32e9a
PZ		 2465{
2466 enum pipe pipe;
1fd527cc 2467 struct intel_wm_level res[3];
6f5ddd17
VS		 2468
2469 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++)
2470 ilk_compute_wm_level(dev_priv, level, &params[pipe], &res[pipe]);
cca32e9a 2471
6f5ddd17
VS		 2472 result->pri_val = max3(res[0].pri_val, res[1].pri_val, res[2].pri_val);
2473 result->spr_val = max3(res[0].spr_val, res[1].spr_val, res[2].spr_val);
2474 result->cur_val = max3(res[0].cur_val, res[1].cur_val, res[2].cur_val);
2475 result->fbc_val = max3(res[0].fbc_val, res[1].fbc_val, res[2].fbc_val);
2476 result->enable = true;
cca32e9a 2477
a9786a11 2478 return ilk_check_wm(level, max, result);
cca32e9a
PZ		 2479}
2480
8de123a5
VS		 2481
2482static uint32_t hsw_compute_wm_pipe(struct drm_device *dev,
ac830fe1 2483 const struct hsw_pipe_wm_parameters *params)
801bcfff 2484{
8de123a5
VS		 2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct intel_wm_config config = {
2487 .num_pipes_active = 1,
2488 .sprites_enabled = params->spr.enabled,
2489 .sprites_scaled = params->spr.scaled,
2490 };
2491 struct hsw_wm_maximums max;
2492 struct intel_wm_level res;
2493
2494 if (!params->active)
2495 return 0;
2496
2497 ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
801bcfff 2498
8de123a5 2499 ilk_compute_wm_level(dev_priv, 0, params, &res);
801bcfff 2500
8de123a5 2501 ilk_check_wm(0, &max, &res);
801bcfff 2502
8de123a5
VS		 2503 return (res.pri_val << WM0_PIPE_PLANE_SHIFT) |
2504 (res.spr_val << WM0_PIPE_SPRITE_SHIFT) |
2505 res.cur_val;
801bcfff
PZ		 2506}
2507
2508static uint32_t
2509hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2510{
2511 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2513 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2514 u32 linetime, ips_linetime;
1f8eeabf 2515
801bcfff
PZ		 2516 if (!intel_crtc_active(crtc))
2517 return 0;
1011d8c4 2518
1f8eeabf
ED		 2519 /* The WM are computed with base on how long it takes to fill a single
2520 * row at the given clock rate, multiplied by 8.
2521 * */
85a02deb
PZ		 2522 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2523 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2524 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2525
801bcfff
PZ		 2526 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2527 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2528}
2529
12b134df
VS		 2530static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2531{
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533
2534 if (IS_HASWELL(dev)) {
2535 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2536
2537 wm[0] = (sskpd >> 56) & 0xFF;
2538 if (wm[0] == 0)
2539 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2540 wm[1] = (sskpd >> 4) & 0xFF;
2541 wm[2] = (sskpd >> 12) & 0xFF;
2542 wm[3] = (sskpd >> 20) & 0x1FF;
2543 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2544 } else if (INTEL_INFO(dev)->gen >= 6) {
2545 uint32_t sskpd = I915_READ(MCH_SSKPD);
2546
2547 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2548 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2549 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2550 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2551 } else if (INTEL_INFO(dev)->gen >= 5) {
2552 uint32_t mltr = I915_READ(MLTR_ILK);
2553
2554 /* ILK primary LP0 latency is 700 ns */
2555 wm[0] = 7;
2556 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2557 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2558 }
2559}
2560
53615a5e
VS		 2561static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2562{
2563 /* ILK sprite LP0 latency is 1300 ns */
2564 if (INTEL_INFO(dev)->gen == 5)
2565 wm[0] = 13;
2566}
2567
2568static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2569{
2570 /* ILK cursor LP0 latency is 1300 ns */
2571 if (INTEL_INFO(dev)->gen == 5)
2572 wm[0] = 13;
2573
2574 /* WaDoubleCursorLP3Latency:ivb */
2575 if (IS_IVYBRIDGE(dev))
2576 wm[3] *= 2;
2577}
2578
ad0d6dc4 2579static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2580{
26ec971e
VS		 2581 /* how many WM levels are we expecting */
2582 if (IS_HASWELL(dev))
ad0d6dc4 2583 return 4;
26ec971e 2584 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2585 return 3;
26ec971e 2586 else
ad0d6dc4
VS		 2587 return 2;
2588}
2589
2590static void intel_print_wm_latency(struct drm_device *dev,
2591 const char *name,
2592 const uint16_t wm[5])
2593{
2594 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2595
2596 for (level = 0; level <= max_level; level++) {
2597 unsigned int latency = wm[level];
2598
2599 if (latency == 0) {
2600 DRM_ERROR("%s WM%d latency not provided\n",
2601 name, level);
2602 continue;
2603 }
2604
2605 /* WM1+ latency values in 0.5us units */
2606 if (level > 0)
2607 latency *= 5;
2608
2609 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2610 name, level, wm[level],
2611 latency / 10, latency % 10);
2612 }
2613}
2614
53615a5e
VS		 2615static void intel_setup_wm_latency(struct drm_device *dev)
2616{
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618
2619 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2620
2621 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2622 sizeof(dev_priv->wm.pri_latency));
2623 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2624 sizeof(dev_priv->wm.pri_latency));
2625
2626 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2627 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2628
2629 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2630 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2631 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2632}
2633
801bcfff
PZ		 2634static void hsw_compute_wm_parameters(struct drm_device *dev,
2635 struct hsw_pipe_wm_parameters *params,
861f3389
PZ		 2636 struct hsw_wm_maximums *lp_max_1_2,
2637 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4 2638{
1011d8c4 2639 struct drm_crtc *crtc;
801bcfff 2640 struct drm_plane *plane;
1011d8c4 2641 enum pipe pipe;
240264f4 2642 struct intel_wm_config config = {};
1011d8c4 2643
801bcfff
PZ		 2644 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2646 struct hsw_pipe_wm_parameters *p;
2647
2648 pipe = intel_crtc->pipe;
2649 p = &params[pipe];
2650
2651 p->active = intel_crtc_active(crtc);
2652 if (!p->active)
2653 continue;
2654
240264f4 2655 config.num_pipes_active++;
cca32e9a 2656
801bcfff 2657 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2658 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2659 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2660 p->cur.bytes_per_pixel = 4;
37327abd 2661 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2662 p->cur.horiz_pixels = 64;
2663 /* TODO: for now, assume primary and cursor planes are always enabled. */
2664 p->pri.enabled = true;
2665 p->cur.enabled = true;
801bcfff
PZ		 2666 }
2667
2668 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2669 struct intel_plane *intel_plane = to_intel_plane(plane);
2670 struct hsw_pipe_wm_parameters *p;
2671
2672 pipe = intel_plane->pipe;
2673 p = &params[pipe];
2674
c35426d2 2675 p->spr = intel_plane->wm;
cca32e9a 2676
c35426d2
VS		 2677 config.sprites_enabled |= p->spr.enabled;
2678 config.sprites_scaled |= p->spr.scaled;
cca32e9a
PZ		 2679 }
2680
240264f4 2681 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2);
158ae64f
VS		 2682
2683 /* 5/6 split only in single pipe config on IVB+ */
240264f4
VS		 2684 if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1)
2685 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6);
158ae64f
VS		 2686 else
2687 *lp_max_5_6 = *lp_max_1_2;
801bcfff
PZ		 2688}
2689
2690static void hsw_compute_wm_results(struct drm_device *dev,
ac830fe1
VS		 2691 const struct hsw_pipe_wm_parameters *params,
2692 const struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2693 struct hsw_wm_values *results)
2694{
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696 struct drm_crtc *crtc;
1fd527cc 2697 struct intel_wm_level lp_results[4] = {};
801bcfff 2698 enum pipe pipe;
cca32e9a
PZ		 2699 int level, max_level, wm_lp;
2700
2701 for (level = 1; level <= 4; level++)
5b77da33
VS		 2702 if (!hsw_compute_lp_wm(dev_priv, level,
2703 lp_maximums, params,
cca32e9a
PZ		 2704 &lp_results[level - 1]))
2705 break;
2706 max_level = level - 1;
2707
5c536613
VS		 2708 memset(results, 0, sizeof(*results));
2709
cca32e9a
PZ		 2710 /* The spec says it is preferred to disable FBC WMs instead of disabling
2711 * a WM level. */
2712 results->enable_fbc_wm = true;
2713 for (level = 1; level <= max_level; level++) {
16e54061 2714 if (lp_results[level - 1].fbc_val > lp_maximums->fbc) {
cca32e9a 2715 results->enable_fbc_wm = false;
71fff20f 2716 lp_results[level - 1].fbc_val = 0;
cca32e9a
PZ		 2717 }
2718 }
2719
cca32e9a 2720 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2721 const struct intel_wm_level *r;
801bcfff 2722
cca32e9a
PZ		 2723 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2724 if (level > max_level)
2725 break;
2726
2727 r = &lp_results[level - 1];
2728 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2729 r->fbc_val,
2730 r->pri_val,
2731 r->cur_val);
2732 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2733 }
801bcfff
PZ		 2734
2735 for_each_pipe(pipe)
8de123a5 2736 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev,
801bcfff 2737 &params[pipe]);
1011d8c4
PZ		 2738
2739 for_each_pipe(pipe) {
2740 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2741 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2742 }
2743}
2744
861f3389
PZ		 2745/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2746 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2747static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2748 struct hsw_wm_values *r2)
861f3389
PZ		 2749{
2750 int i, val_r1 = 0, val_r2 = 0;
2751
2752 for (i = 0; i < 3; i++) {
2753 if (r1->wm_lp[i] & WM3_LP_EN)
2754 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2755 if (r2->wm_lp[i] & WM3_LP_EN)
2756 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2757 }
2758
2759 if (val_r1 == val_r2) {
2760 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2761 return r2;
2762 else
2763 return r1;
2764 } else if (val_r1 > val_r2) {
2765 return r1;
2766 } else {
2767 return r2;
2768 }
2769}
2770
801bcfff
PZ		 2771/*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
2775static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2776 struct hsw_wm_values *results,
77c122bc 2777 enum intel_ddb_partitioning partitioning)
801bcfff
PZ		 2778{
2779 struct hsw_wm_values previous;
2780 uint32_t val;
77c122bc 2781 enum intel_ddb_partitioning prev_partitioning;
cca32e9a 2782 bool prev_enable_fbc_wm;
801bcfff
PZ		 2783
2784 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2785 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2786 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2787 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2788 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2789 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2790 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2791 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2792 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2793 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2794 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2795 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2796
2797 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
77c122bc 2798 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
801bcfff 2799
cca32e9a
PZ		 2800 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2801
801bcfff
PZ		 2802 if (memcmp(results->wm_pipe, previous.wm_pipe,
2803 sizeof(results->wm_pipe)) == 0 &&
2804 memcmp(results->wm_lp, previous.wm_lp,
2805 sizeof(results->wm_lp)) == 0 &&
2806 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2807 sizeof(results->wm_lp_spr)) == 0 &&
2808 memcmp(results->wm_linetime, previous.wm_linetime,
2809 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2810 partitioning == prev_partitioning &&
2811 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2812 return;
2813
2814 if (previous.wm_lp[2] != 0)
2815 I915_WRITE(WM3_LP_ILK, 0);
2816 if (previous.wm_lp[1] != 0)
2817 I915_WRITE(WM2_LP_ILK, 0);
2818 if (previous.wm_lp[0] != 0)
2819 I915_WRITE(WM1_LP_ILK, 0);
2820
2821 if (previous.wm_pipe[0] != results->wm_pipe[0])
2822 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2823 if (previous.wm_pipe[1] != results->wm_pipe[1])
2824 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2825 if (previous.wm_pipe[2] != results->wm_pipe[2])
2826 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2827
2828 if (previous.wm_linetime[0] != results->wm_linetime[0])
2829 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2830 if (previous.wm_linetime[1] != results->wm_linetime[1])
2831 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2832 if (previous.wm_linetime[2] != results->wm_linetime[2])
2833 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2834
2835 if (prev_partitioning != partitioning) {
2836 val = I915_READ(WM_MISC);
77c122bc 2837 if (partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2838 val &= ~WM_MISC_DATA_PARTITION_5_6;
2839 else
2840 val |= WM_MISC_DATA_PARTITION_5_6;
2841 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2842 }
2843
cca32e9a
PZ		 2844 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2845 val = I915_READ(DISP_ARB_CTL);
2846 if (results->enable_fbc_wm)
2847 val &= ~DISP_FBC_WM_DIS;
2848 else
2849 val |= DISP_FBC_WM_DIS;
2850 I915_WRITE(DISP_ARB_CTL, val);
2851 }
2852
801bcfff
PZ		 2853 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2854 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2855 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2856 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2857 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2858 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2859
2860 if (results->wm_lp[0] != 0)
2861 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2862 if (results->wm_lp[1] != 0)
2863 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2864 if (results->wm_lp[2] != 0)
2865 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2866}
2867
46ba614c 2868static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2869{
46ba614c 2870 struct drm_device *dev = crtc->dev;
801bcfff 2871 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2872 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2873 struct hsw_pipe_wm_parameters params[3];
861f3389 2874 struct hsw_wm_values results_1_2, results_5_6, *best_results;
77c122bc 2875 enum intel_ddb_partitioning partitioning;
861f3389 2876
12b134df 2877 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
861f3389 2878
53615a5e 2879 hsw_compute_wm_results(dev, params,
53615a5e 2880 &lp_max_1_2, &results_1_2);
861f3389 2881 if (lp_max_1_2.pri != lp_max_5_6.pri) {
53615a5e 2882 hsw_compute_wm_results(dev, params,
53615a5e 2883 &lp_max_5_6, &results_5_6);
861f3389
PZ		 2884 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2885 } else {
2886 best_results = &results_1_2;
2887 }
2888
2889 partitioning = (best_results == &results_1_2) ?
77c122bc 2890 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2891
861f3389 2892 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2893}
2894
adf3d35e
VS		 2895static void haswell_update_sprite_wm(struct drm_plane *plane,
2896 struct drm_crtc *crtc,
526682e9 2897 uint32_t sprite_width, int pixel_size,
bdd57d03 2898 bool enabled, bool scaled)
526682e9 2899{
adf3d35e 2900 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2901
adf3d35e
VS		 2902 intel_plane->wm.enabled = enabled;
2903 intel_plane->wm.scaled = scaled;
2904 intel_plane->wm.horiz_pixels = sprite_width;
2905 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2906
46ba614c 2907 haswell_update_wm(crtc);
526682e9
PZ		 2908}
2909
b445e3b0
ED		 2910static bool
2911sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2912 uint32_t sprite_width, int pixel_size,
2913 const struct intel_watermark_params *display,
2914 int display_latency_ns, int *sprite_wm)
2915{
2916 struct drm_crtc *crtc;
2917 int clock;
2918 int entries, tlb_miss;
2919
2920 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2921 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2922 *sprite_wm = display->guard_size;
2923 return false;
2924 }
2925
241bfc38 2926 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 2927
2928 /* Use the small buffer method to calculate the sprite watermark */
2929 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2930 tlb_miss = display->fifo_size*display->cacheline_size -
2931 sprite_width * 8;
2932 if (tlb_miss > 0)
2933 entries += tlb_miss;
2934 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2935 *sprite_wm = entries + display->guard_size;
2936 if (*sprite_wm > (int)display->max_wm)
2937 *sprite_wm = display->max_wm;
2938
2939 return true;
2940}
2941
2942static bool
2943sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2944 uint32_t sprite_width, int pixel_size,
2945 const struct intel_watermark_params *display,
2946 int latency_ns, int *sprite_wm)
2947{
2948 struct drm_crtc *crtc;
2949 unsigned long line_time_us;
2950 int clock;
2951 int line_count, line_size;
2952 int small, large;
2953 int entries;
2954
2955 if (!latency_ns) {
2956 *sprite_wm = 0;
2957 return false;
2958 }
2959
2960 crtc = intel_get_crtc_for_plane(dev, plane);
241bfc38 2961 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 2962 if (!clock) {
2963 *sprite_wm = 0;
2964 return false;
2965 }
2966
2967 line_time_us = (sprite_width * 1000) / clock;
2968 if (!line_time_us) {
2969 *sprite_wm = 0;
2970 return false;
2971 }
2972
2973 line_count = (latency_ns / line_time_us + 1000) / 1000;
2974 line_size = sprite_width * pixel_size;
2975
2976 /* Use the minimum of the small and large buffer method for primary */
2977 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2978 large = line_count * line_size;
2979
2980 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2981 *sprite_wm = entries + display->guard_size;
2982
2983 return *sprite_wm > 0x3ff ? false : true;
2984}
2985
adf3d35e
VS		 2986static void sandybridge_update_sprite_wm(struct drm_plane *plane,
2987 struct drm_crtc *crtc,
4c4ff43a 2988 uint32_t sprite_width, int pixel_size,
39db4a4d 2989 bool enabled, bool scaled)
b445e3b0 2990{
adf3d35e 2991 struct drm_device *dev = plane->dev;
b445e3b0 2992 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 2993 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 2994 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 2995 u32 val;
2996 int sprite_wm, reg;
2997 int ret;
2998
39db4a4d 2999 if (!enabled)
4c4ff43a
PZ		 3000 return;
3001
b445e3b0
ED		 3002 switch (pipe) {
3003 case 0:
3004 reg = WM0_PIPEA_ILK;
3005 break;
3006 case 1:
3007 reg = WM0_PIPEB_ILK;
3008 break;
3009 case 2:
3010 reg = WM0_PIPEC_IVB;
3011 break;
3012 default:
3013 return; /* bad pipe */
3014 }
3015
3016 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3017 &sandybridge_display_wm_info,
3018 latency, &sprite_wm);
3019 if (!ret) {
84f44ce7
VS		 3020 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3021 pipe_name(pipe));
b445e3b0
ED		 3022 return;
3023 }
3024
3025 val = I915_READ(reg);
3026 val &= ~WM0_PIPE_SPRITE_MASK;
3027 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3028 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3029
3030
3031 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3032 pixel_size,
3033 &sandybridge_display_srwm_info,
b0aea5dc 3034 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3035 &sprite_wm);
3036 if (!ret) {
84f44ce7
VS		 3037 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3038 pipe_name(pipe));
b445e3b0
ED		 3039 return;
3040 }
3041 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3042
3043 /* Only IVB has two more LP watermarks for sprite */
3044 if (!IS_IVYBRIDGE(dev))
3045 return;
3046
3047 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3048 pixel_size,
3049 &sandybridge_display_srwm_info,
b0aea5dc 3050 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3051 &sprite_wm);
3052 if (!ret) {
84f44ce7
VS		 3053 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3054 pipe_name(pipe));
b445e3b0
ED		 3055 return;
3056 }
3057 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3058
3059 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3060 pixel_size,
3061 &sandybridge_display_srwm_info,
b0aea5dc 3062 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3063 &sprite_wm);
3064 if (!ret) {
84f44ce7
VS		 3065 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3066 pipe_name(pipe));
b445e3b0
ED		 3067 return;
3068 }
3069 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3070}
3071
3072/**
3073 * intel_update_watermarks - update FIFO watermark values based on current modes
3074 *
3075 * Calculate watermark values for the various WM regs based on current mode
3076 * and plane configuration.
3077 *
3078 * There are several cases to deal with here:
3079 * - normal (i.e. non-self-refresh)
3080 * - self-refresh (SR) mode
3081 * - lines are large relative to FIFO size (buffer can hold up to 2)
3082 * - lines are small relative to FIFO size (buffer can hold more than 2
3083 * lines), so need to account for TLB latency
3084 *
3085 * The normal calculation is:
3086 * watermark = dotclock * bytes per pixel * latency
3087 * where latency is platform & configuration dependent (we assume pessimal
3088 * values here).
3089 *
3090 * The SR calculation is:
3091 * watermark = (trunc(latency/line time)+1) * surface width *
3092 * bytes per pixel
3093 * where
3094 * line time = htotal / dotclock
3095 * surface width = hdisplay for normal plane and 64 for cursor
3096 * and latency is assumed to be high, as above.
3097 *
3098 * The final value programmed to the register should always be rounded up,
3099 * and include an extra 2 entries to account for clock crossings.
3100 *
3101 * We don't use the sprite, so we can ignore that. And on Crestline we have
3102 * to set the non-SR watermarks to 8.
3103 */
46ba614c 3104void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3105{
46ba614c 3106 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3107
3108 if (dev_priv->display.update_wm)
46ba614c 3109 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3110}
3111
adf3d35e
VS		 3112void intel_update_sprite_watermarks(struct drm_plane *plane,
3113 struct drm_crtc *crtc,
4c4ff43a 3114 uint32_t sprite_width, int pixel_size,
39db4a4d 3115 bool enabled, bool scaled)
b445e3b0 3116{
adf3d35e 3117 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3118
3119 if (dev_priv->display.update_sprite_wm)
adf3d35e 3120 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3121 pixel_size, enabled, scaled);
b445e3b0
ED		 3122}
3123
2b4e57bd
ED		 3124static struct drm_i915_gem_object *
3125intel_alloc_context_page(struct drm_device *dev)
3126{
3127 struct drm_i915_gem_object *ctx;
3128 int ret;
3129
3130 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3131
3132 ctx = i915_gem_alloc_object(dev, 4096);
3133 if (!ctx) {
3134 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3135 return NULL;
3136 }
3137
c37e2204 3138 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3139 if (ret) {
3140 DRM_ERROR("failed to pin power context: %d\n", ret);
3141 goto err_unref;
3142 }
3143
3144 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3145 if (ret) {
3146 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3147 goto err_unpin;
3148 }
3149
3150 return ctx;
3151
3152err_unpin:
3153 i915_gem_object_unpin(ctx);
3154err_unref:
3155 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3156 return NULL;
3157}
3158
9270388e
DV		 3159/**
3160 * Lock protecting IPS related data structures
9270388e
DV		 3161 */
3162DEFINE_SPINLOCK(mchdev_lock);
3163
3164/* Global for IPS driver to get at the current i915 device. Protected by
3165 * mchdev_lock. */
3166static struct drm_i915_private *i915_mch_dev;
3167
2b4e57bd
ED		 3168bool ironlake_set_drps(struct drm_device *dev, u8 val)
3169{
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 u16 rgvswctl;
3172
9270388e
DV		 3173 assert_spin_locked(&mchdev_lock);
3174
2b4e57bd
ED		 3175 rgvswctl = I915_READ16(MEMSWCTL);
3176 if (rgvswctl & MEMCTL_CMD_STS) {
3177 DRM_DEBUG("gpu busy, RCS change rejected\n");
3178 return false; /* still busy with another command */
3179 }
3180
3181 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3182 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3183 I915_WRITE16(MEMSWCTL, rgvswctl);
3184 POSTING_READ16(MEMSWCTL);
3185
3186 rgvswctl |= MEMCTL_CMD_STS;
3187 I915_WRITE16(MEMSWCTL, rgvswctl);
3188
3189 return true;
3190}
3191
8090c6b9 3192static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3193{
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 u32 rgvmodectl = I915_READ(MEMMODECTL);
3196 u8 fmax, fmin, fstart, vstart;
3197
9270388e
DV		 3198 spin_lock_irq(&mchdev_lock);
3199
2b4e57bd
ED		 3200 /* Enable temp reporting */
3201 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3202 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3203
3204 /* 100ms RC evaluation intervals */
3205 I915_WRITE(RCUPEI, 100000);
3206 I915_WRITE(RCDNEI, 100000);
3207
3208 /* Set max/min thresholds to 90ms and 80ms respectively */
3209 I915_WRITE(RCBMAXAVG, 90000);
3210 I915_WRITE(RCBMINAVG, 80000);
3211
3212 I915_WRITE(MEMIHYST, 1);
3213
3214 /* Set up min, max, and cur for interrupt handling */
3215 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3216 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3217 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3218 MEMMODE_FSTART_SHIFT;
3219
3220 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3221 PXVFREQ_PX_SHIFT;
3222
20e4d407
DV		 3223 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3224 dev_priv->ips.fstart = fstart;
2b4e57bd 3225
20e4d407
DV		 3226 dev_priv->ips.max_delay = fstart;
3227 dev_priv->ips.min_delay = fmin;
3228 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3229
3230 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3231 fmax, fmin, fstart);
3232
3233 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3234
3235 /*
3236 * Interrupts will be enabled in ironlake_irq_postinstall
3237 */
3238
3239 I915_WRITE(VIDSTART, vstart);
3240 POSTING_READ(VIDSTART);
3241
3242 rgvmodectl |= MEMMODE_SWMODE_EN;
3243 I915_WRITE(MEMMODECTL, rgvmodectl);
3244
9270388e 3245 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3246 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3247 mdelay(1);
2b4e57bd
ED		 3248
3249 ironlake_set_drps(dev, fstart);
3250
20e4d407 3251 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3252 I915_READ(0x112e0);
20e4d407
DV		 3253 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3254 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3255 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3256
3257 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3258}
3259
8090c6b9 3260static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3261{
3262 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3263 u16 rgvswctl;
3264
3265 spin_lock_irq(&mchdev_lock);
3266
3267 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3268
3269 /* Ack interrupts, disable EFC interrupt */
3270 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3271 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3272 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3273 I915_WRITE(DEIIR, DE_PCU_EVENT);
3274 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3275
3276 /* Go back to the starting frequency */
20e4d407 3277 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3278 mdelay(1);
2b4e57bd
ED		 3279 rgvswctl |= MEMCTL_CMD_STS;
3280 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3281 mdelay(1);
2b4e57bd 3282
9270388e 3283 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3284}
3285
acbe9475
DV		 3286/* There's a funny hw issue where the hw returns all 0 when reading from
3287 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3288 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3289 * all limits and the gpu stuck at whatever frequency it is at atm).
3290 */
65bccb5c 3291static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3292{
7b9e0ae6 3293 u32 limits;
2b4e57bd 3294
7b9e0ae6 3295 limits = 0;
c6a828d3
DV		 3296
3297 if (*val >= dev_priv->rps.max_delay)
3298 *val = dev_priv->rps.max_delay;
3299 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3300
3301 /* Only set the down limit when we've reached the lowest level to avoid
3302 * getting more interrupts, otherwise leave this clear. This prevents a
3303 * race in the hw when coming out of rc6: There's a tiny window where
3304 * the hw runs at the minimal clock before selecting the desired
3305 * frequency, if the down threshold expires in that window we will not
3306 * receive a down interrupt. */
c6a828d3
DV		 3307 if (*val <= dev_priv->rps.min_delay) {
3308 *val = dev_priv->rps.min_delay;
3309 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3310 }
3311
3312 return limits;
3313}
3314
3315void gen6_set_rps(struct drm_device *dev, u8 val)
3316{
3317 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3318 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3319
4fc688ce 3320 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3321 WARN_ON(val > dev_priv->rps.max_delay);
3322 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3323
c6a828d3 3324 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3325 return;
3326
92bd1bf0
RV		 3327 if (IS_HASWELL(dev))
3328 I915_WRITE(GEN6_RPNSWREQ,
3329 HSW_FREQUENCY(val));
3330 else
3331 I915_WRITE(GEN6_RPNSWREQ,
3332 GEN6_FREQUENCY(val) |
3333 GEN6_OFFSET(0) |
3334 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3335
3336 /* Make sure we continue to get interrupts
3337 * until we hit the minimum or maximum frequencies.
3338 */
3339 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3340
d5570a72
BW		 3341 POSTING_READ(GEN6_RPNSWREQ);
3342
c6a828d3 3343 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3344
3345 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3346}
3347
80814ae4
VS		 3348/*
3349 * Wait until the previous freq change has completed,
3350 * or the timeout elapsed, and then update our notion
3351 * of the current GPU frequency.
3352 */
3353static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3354{
80814ae4
VS		 3355 u32 pval;
3356
3357 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3358
e8474409
VS		 3359 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3360 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3361
3362 pval >>= 8;
3363
3364 if (pval != dev_priv->rps.cur_delay)
3365 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3366 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3367 dev_priv->rps.cur_delay,
3368 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3369
3370 dev_priv->rps.cur_delay = pval;
3371}
3372
0a073b84
JB		 3373void valleyview_set_rps(struct drm_device *dev, u8 val)
3374{
3375 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3376
3377 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3378
3379 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3380 WARN_ON(val > dev_priv->rps.max_delay);
3381 WARN_ON(val < dev_priv->rps.min_delay);
3382
80814ae4
VS		 3383 vlv_update_rps_cur_delay(dev_priv);
3384
73008b98 3385 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3386 vlv_gpu_freq(dev_priv->mem_freq,
3387 dev_priv->rps.cur_delay),
73008b98
VS		 3388 dev_priv->rps.cur_delay,
3389 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3390
3391 if (val == dev_priv->rps.cur_delay)
3392 return;
3393
ae99258f 3394 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3395
80814ae4 3396 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3397
3398 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3399}
3400
44fc7d5c 3401static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3402{
3403 struct drm_i915_private *dev_priv = dev->dev_private;
3404
2b4e57bd 3405 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3406 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3407 /* Complete PM interrupt masking here doesn't race with the rps work
3408 * item again unmasking PM interrupts because that is using a different
3409 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3410 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3411
59cdb63d 3412 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3413 dev_priv->rps.pm_iir = 0;
59cdb63d 3414 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3415
4848405c 3416 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3417}
3418
44fc7d5c 3419static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3420{
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3424 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3425
44fc7d5c
DV		 3426 gen6_disable_rps_interrupts(dev);
3427}
3428
3429static void valleyview_disable_rps(struct drm_device *dev)
3430{
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3432
3433 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3434
44fc7d5c 3435 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3436
3437 if (dev_priv->vlv_pctx) {
3438 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3439 dev_priv->vlv_pctx = NULL;
3440 }
d20d4f0c
JB		 3441}
3442
2b4e57bd
ED		 3443int intel_enable_rc6(const struct drm_device *dev)
3444{
eb4926e4
DL		 3445 /* No RC6 before Ironlake */
3446 if (INTEL_INFO(dev)->gen < 5)
3447 return 0;
3448
456470eb 3449 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3450 if (i915_enable_rc6 >= 0)
3451 return i915_enable_rc6;
3452
6567d748
CW		 3453 /* Disable RC6 on Ironlake */
3454 if (INTEL_INFO(dev)->gen == 5)
3455 return 0;
2b4e57bd 3456
456470eb
DV		 3457 if (IS_HASWELL(dev)) {
3458 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3459 return INTEL_RC6_ENABLE;
456470eb 3460 }
2b4e57bd 3461
456470eb 3462 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3463 if (INTEL_INFO(dev)->gen == 6) {
3464 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3465 return INTEL_RC6_ENABLE;
3466 }
456470eb 3467
2b4e57bd
ED		 3468 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3469 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3470}
3471
44fc7d5c
DV		 3472static void gen6_enable_rps_interrupts(struct drm_device *dev)
3473{
3474 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3475 u32 enabled_intrs;
44fc7d5c
DV		 3476
3477 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3478 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3479 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3480 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3481 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3482
fd547d25 3483 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3484 enabled_intrs = GEN6_PM_RPS_EVENTS;
3485
3486 /* IVB and SNB hard hangs on looping batchbuffer
3487 * if GEN6_PM_UP_EI_EXPIRED is masked.
3488 */
3489 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3490 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3491
3492 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3493}
3494
79f5b2c7 3495static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3496{
79f5b2c7 3497 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3498 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3499 u32 rp_state_cap;
3500 u32 gt_perf_status;
31643d54 3501 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3502 u32 gtfifodbg;
2b4e57bd 3503 int rc6_mode;
42c0526c 3504 int i, ret;
2b4e57bd 3505
4fc688ce 3506 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3507
2b4e57bd
ED		 3508 /* Here begins a magic sequence of register writes to enable
3509 * auto-downclocking.
3510 *
3511 * Perhaps there might be some value in exposing these to
3512 * userspace...
3513 */
3514 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3515
3516 /* Clear the DBG now so we don't confuse earlier errors */
3517 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3518 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3519 I915_WRITE(GTFIFODBG, gtfifodbg);
3520 }
3521
3522 gen6_gt_force_wake_get(dev_priv);
3523
7b9e0ae6
CW		 3524 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3525 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3526
31c77388
BW		 3527 /* In units of 50MHz */
3528 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3529 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3530 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3531
2b4e57bd
ED		 3532 /* disable the counters and set deterministic thresholds */
3533 I915_WRITE(GEN6_RC_CONTROL, 0);
3534
3535 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3536 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3537 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3538 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3539 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3540
b4519513
CW		 3541 for_each_ring(ring, dev_priv, i)
3542 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3543
3544 I915_WRITE(GEN6_RC_SLEEP, 0);
3545 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
351aa566
SM		 3546 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3547 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3548 else
3549 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3550 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3551 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3552
5a7dc92a 3553 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3554 rc6_mode = intel_enable_rc6(dev_priv->dev);
3555 if (rc6_mode & INTEL_RC6_ENABLE)
3556 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3557
5a7dc92a
ED		 3558 /* We don't use those on Haswell */
3559 if (!IS_HASWELL(dev)) {
3560 if (rc6_mode & INTEL_RC6p_ENABLE)
3561 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3562
5a7dc92a
ED		 3563 if (rc6_mode & INTEL_RC6pp_ENABLE)
3564 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3565 }
2b4e57bd
ED		 3566
3567 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3568 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3569 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3570 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3571
3572 I915_WRITE(GEN6_RC_CONTROL,
3573 rc6_mask |
3574 GEN6_RC_CTL_EI_MODE(1) |
3575 GEN6_RC_CTL_HW_ENABLE);
3576
92bd1bf0
RV		 3577 if (IS_HASWELL(dev)) {
3578 I915_WRITE(GEN6_RPNSWREQ,
3579 HSW_FREQUENCY(10));
3580 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3581 HSW_FREQUENCY(12));
3582 } else {
3583 I915_WRITE(GEN6_RPNSWREQ,
3584 GEN6_FREQUENCY(10) |
3585 GEN6_OFFSET(0) |
3586 GEN6_AGGRESSIVE_TURBO);
3587 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3588 GEN6_FREQUENCY(12));
3589 }
2b4e57bd
ED		 3590
3591 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3592 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3593 dev_priv->rps.max_delay << 24 |
3594 dev_priv->rps.min_delay << 16);
5a7dc92a 3595
1ee9ae32
DV		 3596 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3597 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3598 I915_WRITE(GEN6_RP_UP_EI, 66000);
3599 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3600
2b4e57bd
ED		 3601 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3602 I915_WRITE(GEN6_RP_CONTROL,
3603 GEN6_RP_MEDIA_TURBO |
89ba829e 3604 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3605 GEN6_RP_MEDIA_IS_GFX |
3606 GEN6_RP_ENABLE |
3607 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3608 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3609
42c0526c 3610 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3611 if (!ret) {
42c0526c
BW		 3612 pcu_mbox = 0;
3613 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3614 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3615 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3616 (dev_priv->rps.max_delay & 0xff) * 50,
3617 (pcu_mbox & 0xff) * 50);
31c77388 3618 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3619 }
3620 } else {
3621 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3622 }
3623
7b9e0ae6 3624 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3625
44fc7d5c 3626 gen6_enable_rps_interrupts(dev);
2b4e57bd 3627
31643d54
BW		 3628 rc6vids = 0;
3629 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3630 if (IS_GEN6(dev) && ret) {
3631 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3632 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3633 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3634 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3635 rc6vids &= 0xffff00;
3636 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3637 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3638 if (ret)
3639 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3640 }
3641
2b4e57bd 3642 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3643}
3644
c67a470b 3645void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3646{
79f5b2c7 3647 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3648 int min_freq = 15;
3ebecd07
CW		 3649 unsigned int gpu_freq;
3650 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3651 int scaling_factor = 180;
3652
4fc688ce 3653 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3654
2b4e57bd
ED		 3655 max_ia_freq = cpufreq_quick_get_max(0);
3656 /*
3657 * Default to measured freq if none found, PCU will ensure we don't go
3658 * over
3659 */
3660 if (!max_ia_freq)
3661 max_ia_freq = tsc_khz;
3662
3663 /* Convert from kHz to MHz */
3664 max_ia_freq /= 1000;
3665
f6aca45c
BW		 3666 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3667 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3668 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3669
2b4e57bd
ED		 3670 /*
3671 * For each potential GPU frequency, load a ring frequency we'd like
3672 * to use for memory access. We do this by specifying the IA frequency
3673 * the PCU should use as a reference to determine the ring frequency.
3674 */
c6a828d3 3675 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3676 gpu_freq--) {
c6a828d3 3677 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3678 unsigned int ia_freq = 0, ring_freq = 0;
3679
3680 if (IS_HASWELL(dev)) {
f6aca45c 3681 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3682 ring_freq = max(min_ring_freq, ring_freq);
3683 /* leave ia_freq as the default, chosen by cpufreq */
3684 } else {
3685 /* On older processors, there is no separate ring
3686 * clock domain, so in order to boost the bandwidth
3687 * of the ring, we need to upclock the CPU (ia_freq).
3688 *
3689 * For GPU frequencies less than 750MHz,
3690 * just use the lowest ring freq.
3691 */
3692 if (gpu_freq < min_freq)
3693 ia_freq = 800;
3694 else
3695 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3696 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3697 }
2b4e57bd 3698
42c0526c
BW		 3699 sandybridge_pcode_write(dev_priv,
3700 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3701 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3702 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3703 gpu_freq);
2b4e57bd 3704 }
2b4e57bd
ED		 3705}
3706
0a073b84
JB		 3707int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3708{
3709 u32 val, rp0;
3710
64936258 3711 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3712
3713 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3714 /* Clamp to max */
3715 rp0 = min_t(u32, rp0, 0xea);
3716
3717 return rp0;
3718}
3719
3720static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3721{
3722 u32 val, rpe;
3723
64936258 3724 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3725 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3726 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3727 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3728
3729 return rpe;
3730}
3731
3732int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3733{
64936258 3734 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3735}
3736
52ceb908
JB		 3737static void vlv_rps_timer_work(struct work_struct *work)
3738{
3739 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3740 rps.vlv_work.work);
3741
3742 /*
3743 * Timer fired, we must be idle. Drop to min voltage state.
3744 * Note: we use RPe here since it should match the
3745 * Vmin we were shooting for. That should give us better
3746 * perf when we come back out of RC6 than if we used the
3747 * min freq available.
3748 */
3749 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3750 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3751 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3752 mutex_unlock(&dev_priv->rps.hw_lock);
3753}
3754
c9cddffc
JB		 3755static void valleyview_setup_pctx(struct drm_device *dev)
3756{
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 struct drm_i915_gem_object *pctx;
3759 unsigned long pctx_paddr;
3760 u32 pcbr;
3761 int pctx_size = 24*1024;
3762
3763 pcbr = I915_READ(VLV_PCBR);
3764 if (pcbr) {
3765 /* BIOS set it up already, grab the pre-alloc'd space */
3766 int pcbr_offset;
3767
3768 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3769 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3770 pcbr_offset,
190d6cd5 3771 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3772 pctx_size);
3773 goto out;
3774 }
3775
3776 /*
3777 * From the Gunit register HAS:
3778 * The Gfx driver is expected to program this register and ensure
3779 * proper allocation within Gfx stolen memory. For example, this
3780 * register should be programmed such than the PCBR range does not
3781 * overlap with other ranges, such as the frame buffer, protected
3782 * memory, or any other relevant ranges.
3783 */
3784 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3785 if (!pctx) {
3786 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3787 return;
3788 }
3789
3790 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3791 I915_WRITE(VLV_PCBR, pctx_paddr);
3792
3793out:
3794 dev_priv->vlv_pctx = pctx;
3795}
3796
0a073b84
JB		 3797static void valleyview_enable_rps(struct drm_device *dev)
3798{
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 struct intel_ring_buffer *ring;
a2b23fe0 3801 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3802 int i;
3803
3804 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3805
3806 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3807 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3808 gtfifodbg);
0a073b84
JB		 3809 I915_WRITE(GTFIFODBG, gtfifodbg);
3810 }
3811
c9cddffc
JB		 3812 valleyview_setup_pctx(dev);
3813
0a073b84
JB		 3814 gen6_gt_force_wake_get(dev_priv);
3815
3816 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3817 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3818 I915_WRITE(GEN6_RP_UP_EI, 66000);
3819 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3820
3821 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3822
3823 I915_WRITE(GEN6_RP_CONTROL,
3824 GEN6_RP_MEDIA_TURBO |
3825 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3826 GEN6_RP_MEDIA_IS_GFX |
3827 GEN6_RP_ENABLE |
3828 GEN6_RP_UP_BUSY_AVG |
3829 GEN6_RP_DOWN_IDLE_CONT);
3830
3831 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3832 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3833 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3834
3835 for_each_ring(ring, dev_priv, i)
3836 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3837
3838 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3839
3840 /* allows RC6 residency counter to work */
49798eb2
JB		 3841 I915_WRITE(VLV_COUNTER_CONTROL,
3842 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3843 VLV_MEDIA_RC6_COUNT_EN |
3844 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0
JB		 3845 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3846 rc6_mode = GEN7_RC_CTL_TO_MODE;
3847 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3848
64936258 3849 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3850 switch ((val >> 6) & 3) {
3851 case 0:
3852 case 1:
3853 dev_priv->mem_freq = 800;
3854 break;
3855 case 2:
3856 dev_priv->mem_freq = 1066;
3857 break;
3858 case 3:
3859 dev_priv->mem_freq = 1333;
3860 break;
3861 }
0a073b84
JB		 3862 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3863
3864 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3865 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3866
0a073b84 3867 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3868 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3869 vlv_gpu_freq(dev_priv->mem_freq,
3870 dev_priv->rps.cur_delay),
3871 dev_priv->rps.cur_delay);
0a073b84
JB		 3872
3873 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3874 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3875 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3876 vlv_gpu_freq(dev_priv->mem_freq,
3877 dev_priv->rps.max_delay),
3878 dev_priv->rps.max_delay);
0a073b84 3879
73008b98
VS		 3880 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3881 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3882 vlv_gpu_freq(dev_priv->mem_freq,
3883 dev_priv->rps.rpe_delay),
3884 dev_priv->rps.rpe_delay);
0a073b84 3885
73008b98
VS		 3886 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3887 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3888 vlv_gpu_freq(dev_priv->mem_freq,
3889 dev_priv->rps.min_delay),
3890 dev_priv->rps.min_delay);
0a073b84 3891
73008b98
VS		 3892 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3893 vlv_gpu_freq(dev_priv->mem_freq,
3894 dev_priv->rps.rpe_delay),
3895 dev_priv->rps.rpe_delay);
0a073b84 3896
52ceb908
JB		 3897 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3898
73008b98 3899 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3900
44fc7d5c 3901 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3902
3903 gen6_gt_force_wake_put(dev_priv);
3904}
3905
930ebb46 3906void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3907{
3908 struct drm_i915_private *dev_priv = dev->dev_private;
3909
3e373948
DV		 3910 if (dev_priv->ips.renderctx) {
3911 i915_gem_object_unpin(dev_priv->ips.renderctx);
3912 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3913 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3914 }
3915
3e373948
DV		 3916 if (dev_priv->ips.pwrctx) {
3917 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3918 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3919 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3920 }
3921}
3922
930ebb46 3923static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3924{
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926
3927 if (I915_READ(PWRCTXA)) {
3928 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3929 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3930 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3931 50);
3932
3933 I915_WRITE(PWRCTXA, 0);
3934 POSTING_READ(PWRCTXA);
3935
3936 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3937 POSTING_READ(RSTDBYCTL);
3938 }
2b4e57bd
ED		 3939}
3940
3941static int ironlake_setup_rc6(struct drm_device *dev)
3942{
3943 struct drm_i915_private *dev_priv = dev->dev_private;
3944
3e373948
DV		 3945 if (dev_priv->ips.renderctx == NULL)
3946 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3947 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3948 return -ENOMEM;
3949
3e373948
DV		 3950 if (dev_priv->ips.pwrctx == NULL)
3951 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3952 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3953 ironlake_teardown_rc6(dev);
3954 return -ENOMEM;
3955 }
3956
3957 return 0;
3958}
3959
930ebb46 3960static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3961{
3962 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3963 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3964 bool was_interruptible;
2b4e57bd
ED		 3965 int ret;
3966
3967 /* rc6 disabled by default due to repeated reports of hanging during
3968 * boot and resume.
3969 */
3970 if (!intel_enable_rc6(dev))
3971 return;
3972
79f5b2c7
DV		 3973 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3974
2b4e57bd 3975 ret = ironlake_setup_rc6(dev);
79f5b2c7 3976 if (ret)
2b4e57bd 3977 return;
2b4e57bd 3978
3e960501
CW		 3979 was_interruptible = dev_priv->mm.interruptible;
3980 dev_priv->mm.interruptible = false;
3981
2b4e57bd
ED		 3982 /*
3983 * GPU can automatically power down the render unit if given a page
3984 * to save state.
3985 */
6d90c952 3986 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3987 if (ret) {
3988 ironlake_teardown_rc6(dev);
3e960501 3989 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3990 return;
3991 }
3992
6d90c952
DV		 3993 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3994 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3995 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3996 MI_MM_SPACE_GTT |
3997 MI_SAVE_EXT_STATE_EN |
3998 MI_RESTORE_EXT_STATE_EN |
3999 MI_RESTORE_INHIBIT);
4000 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4001 intel_ring_emit(ring, MI_NOOP);
4002 intel_ring_emit(ring, MI_FLUSH);
4003 intel_ring_advance(ring);
2b4e57bd
ED		 4004
4005 /*
4006 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4007 * does an implicit flush, combined with MI_FLUSH above, it should be
4008 * safe to assume that renderctx is valid
4009 */
3e960501
CW		 4010 ret = intel_ring_idle(ring);
4011 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4012 if (ret) {
def27a58 4013 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4014 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4015 return;
4016 }
4017
f343c5f6 4018 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4019 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 4020}
4021
dde18883
ED		 4022static unsigned long intel_pxfreq(u32 vidfreq)
4023{
4024 unsigned long freq;
4025 int div = (vidfreq & 0x3f0000) >> 16;
4026 int post = (vidfreq & 0x3000) >> 12;
4027 int pre = (vidfreq & 0x7);
4028
4029 if (!pre)
4030 return 0;
4031
4032 freq = ((div * 133333) / ((1<<post) * pre));
4033
4034 return freq;
4035}
4036
eb48eb00
DV		 4037static const struct cparams {
4038 u16 i;
4039 u16 t;
4040 u16 m;
4041 u16 c;
4042} cparams[] = {
4043 { 1, 1333, 301, 28664 },
4044 { 1, 1066, 294, 24460 },
4045 { 1, 800, 294, 25192 },
4046 { 0, 1333, 276, 27605 },
4047 { 0, 1066, 276, 27605 },
4048 { 0, 800, 231, 23784 },
4049};
4050
f531dcb2 4051static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4052{
4053 u64 total_count, diff, ret;
4054 u32 count1, count2, count3, m = 0, c = 0;
4055 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4056 int i;
4057
02d71956
DV		 4058 assert_spin_locked(&mchdev_lock);
4059
20e4d407 4060 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4061
4062 /* Prevent division-by-zero if we are asking too fast.
4063 * Also, we don't get interesting results if we are polling
4064 * faster than once in 10ms, so just return the saved value
4065 * in such cases.
4066 */
4067 if (diff1 <= 10)
20e4d407 4068 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4069
4070 count1 = I915_READ(DMIEC);
4071 count2 = I915_READ(DDREC);
4072 count3 = I915_READ(CSIEC);
4073
4074 total_count = count1 + count2 + count3;
4075
4076 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4077 if (total_count < dev_priv->ips.last_count1) {
4078 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4079 diff += total_count;
4080 } else {
20e4d407 4081 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4082 }
4083
4084 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4085 if (cparams[i].i == dev_priv->ips.c_m &&
4086 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4087 m = cparams[i].m;
4088 c = cparams[i].c;
4089 break;
4090 }
4091 }
4092
4093 diff = div_u64(diff, diff1);
4094 ret = ((m * diff) + c);
4095 ret = div_u64(ret, 10);
4096
20e4d407
DV		 4097 dev_priv->ips.last_count1 = total_count;
4098 dev_priv->ips.last_time1 = now;
eb48eb00 4099
20e4d407 4100 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4101
4102 return ret;
4103}
4104
f531dcb2
CW		 4105unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4106{
4107 unsigned long val;
4108
4109 if (dev_priv->info->gen != 5)
4110 return 0;
4111
4112 spin_lock_irq(&mchdev_lock);
4113
4114 val = __i915_chipset_val(dev_priv);
4115
4116 spin_unlock_irq(&mchdev_lock);
4117
4118 return val;
4119}
4120
eb48eb00
DV		 4121unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4122{
4123 unsigned long m, x, b;
4124 u32 tsfs;
4125
4126 tsfs = I915_READ(TSFS);
4127
4128 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4129 x = I915_READ8(TR1);
4130
4131 b = tsfs & TSFS_INTR_MASK;
4132
4133 return ((m * x) / 127) - b;
4134}
4135
4136static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4137{
4138 static const struct v_table {
4139 u16 vd; /* in .1 mil */
4140 u16 vm; /* in .1 mil */
4141 } v_table[] = {
4142 { 0, 0, },
4143 { 375, 0, },
4144 { 500, 0, },
4145 { 625, 0, },
4146 { 750, 0, },
4147 { 875, 0, },
4148 { 1000, 0, },
4149 { 1125, 0, },
4150 { 4125, 3000, },
4151 { 4125, 3000, },
4152 { 4125, 3000, },
4153 { 4125, 3000, },
4154 { 4125, 3000, },
4155 { 4125, 3000, },
4156 { 4125, 3000, },
4157 { 4125, 3000, },
4158 { 4125, 3000, },
4159 { 4125, 3000, },
4160 { 4125, 3000, },
4161 { 4125, 3000, },
4162 { 4125, 3000, },
4163 { 4125, 3000, },
4164 { 4125, 3000, },
4165 { 4125, 3000, },
4166 { 4125, 3000, },
4167 { 4125, 3000, },
4168 { 4125, 3000, },
4169 { 4125, 3000, },
4170 { 4125, 3000, },
4171 { 4125, 3000, },
4172 { 4125, 3000, },
4173 { 4125, 3000, },
4174 { 4250, 3125, },
4175 { 4375, 3250, },
4176 { 4500, 3375, },
4177 { 4625, 3500, },
4178 { 4750, 3625, },
4179 { 4875, 3750, },
4180 { 5000, 3875, },
4181 { 5125, 4000, },
4182 { 5250, 4125, },
4183 { 5375, 4250, },
4184 { 5500, 4375, },
4185 { 5625, 4500, },
4186 { 5750, 4625, },
4187 { 5875, 4750, },
4188 { 6000, 4875, },
4189 { 6125, 5000, },
4190 { 6250, 5125, },
4191 { 6375, 5250, },
4192 { 6500, 5375, },
4193 { 6625, 5500, },
4194 { 6750, 5625, },
4195 { 6875, 5750, },
4196 { 7000, 5875, },
4197 { 7125, 6000, },
4198 { 7250, 6125, },
4199 { 7375, 6250, },
4200 { 7500, 6375, },
4201 { 7625, 6500, },
4202 { 7750, 6625, },
4203 { 7875, 6750, },
4204 { 8000, 6875, },
4205 { 8125, 7000, },
4206 { 8250, 7125, },
4207 { 8375, 7250, },
4208 { 8500, 7375, },
4209 { 8625, 7500, },
4210 { 8750, 7625, },
4211 { 8875, 7750, },
4212 { 9000, 7875, },
4213 { 9125, 8000, },
4214 { 9250, 8125, },
4215 { 9375, 8250, },
4216 { 9500, 8375, },
4217 { 9625, 8500, },
4218 { 9750, 8625, },
4219 { 9875, 8750, },
4220 { 10000, 8875, },
4221 { 10125, 9000, },
4222 { 10250, 9125, },
4223 { 10375, 9250, },
4224 { 10500, 9375, },
4225 { 10625, 9500, },
4226 { 10750, 9625, },
4227 { 10875, 9750, },
4228 { 11000, 9875, },
4229 { 11125, 10000, },
4230 { 11250, 10125, },
4231 { 11375, 10250, },
4232 { 11500, 10375, },
4233 { 11625, 10500, },
4234 { 11750, 10625, },
4235 { 11875, 10750, },
4236 { 12000, 10875, },
4237 { 12125, 11000, },
4238 { 12250, 11125, },
4239 { 12375, 11250, },
4240 { 12500, 11375, },
4241 { 12625, 11500, },
4242 { 12750, 11625, },
4243 { 12875, 11750, },
4244 { 13000, 11875, },
4245 { 13125, 12000, },
4246 { 13250, 12125, },
4247 { 13375, 12250, },
4248 { 13500, 12375, },
4249 { 13625, 12500, },
4250 { 13750, 12625, },
4251 { 13875, 12750, },
4252 { 14000, 12875, },
4253 { 14125, 13000, },
4254 { 14250, 13125, },
4255 { 14375, 13250, },
4256 { 14500, 13375, },
4257 { 14625, 13500, },
4258 { 14750, 13625, },
4259 { 14875, 13750, },
4260 { 15000, 13875, },
4261 { 15125, 14000, },
4262 { 15250, 14125, },
4263 { 15375, 14250, },
4264 { 15500, 14375, },
4265 { 15625, 14500, },
4266 { 15750, 14625, },
4267 { 15875, 14750, },
4268 { 16000, 14875, },
4269 { 16125, 15000, },
4270 };
4271 if (dev_priv->info->is_mobile)
4272 return v_table[pxvid].vm;
4273 else
4274 return v_table[pxvid].vd;
4275}
4276
02d71956 4277static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4278{
4279 struct timespec now, diff1;
4280 u64 diff;
4281 unsigned long diffms;
4282 u32 count;
4283
02d71956 4284 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4285
4286 getrawmonotonic(&now);
20e4d407 4287 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4288
4289 /* Don't divide by 0 */
4290 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4291 if (!diffms)
4292 return;
4293
4294 count = I915_READ(GFXEC);
4295
20e4d407
DV		 4296 if (count < dev_priv->ips.last_count2) {
4297 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4298 diff += count;
4299 } else {
20e4d407 4300 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4301 }
4302
20e4d407
DV		 4303 dev_priv->ips.last_count2 = count;
4304 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4305
4306 /* More magic constants... */
4307 diff = diff * 1181;
4308 diff = div_u64(diff, diffms * 10);
20e4d407 4309 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4310}
4311
02d71956
DV		 4312void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4313{
4314 if (dev_priv->info->gen != 5)
4315 return;
4316
9270388e 4317 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4318
4319 __i915_update_gfx_val(dev_priv);
4320
9270388e 4321 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4322}
4323
f531dcb2 4324static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4325{
4326 unsigned long t, corr, state1, corr2, state2;
4327 u32 pxvid, ext_v;
4328
02d71956
DV		 4329 assert_spin_locked(&mchdev_lock);
4330
c6a828d3 4331 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4332 pxvid = (pxvid >> 24) & 0x7f;
4333 ext_v = pvid_to_extvid(dev_priv, pxvid);
4334
4335 state1 = ext_v;
4336
4337 t = i915_mch_val(dev_priv);
4338
4339 /* Revel in the empirically derived constants */
4340
4341 /* Correction factor in 1/100000 units */
4342 if (t > 80)
4343 corr = ((t * 2349) + 135940);
4344 else if (t >= 50)
4345 corr = ((t * 964) + 29317);
4346 else /* < 50 */
4347 corr = ((t * 301) + 1004);
4348
4349 corr = corr * ((150142 * state1) / 10000 - 78642);
4350 corr /= 100000;
20e4d407 4351 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4352
4353 state2 = (corr2 * state1) / 10000;
4354 state2 /= 100; /* convert to mW */
4355
02d71956 4356 __i915_update_gfx_val(dev_priv);
eb48eb00 4357
20e4d407 4358 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4359}
4360
f531dcb2
CW		 4361unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4362{
4363 unsigned long val;
4364
4365 if (dev_priv->info->gen != 5)
4366 return 0;
4367
4368 spin_lock_irq(&mchdev_lock);
4369
4370 val = __i915_gfx_val(dev_priv);
4371
4372 spin_unlock_irq(&mchdev_lock);
4373
4374 return val;
4375}
4376
eb48eb00
DV		 4377/**
4378 * i915_read_mch_val - return value for IPS use
4379 *
4380 * Calculate and return a value for the IPS driver to use when deciding whether
4381 * we have thermal and power headroom to increase CPU or GPU power budget.
4382 */
4383unsigned long i915_read_mch_val(void)
4384{
4385 struct drm_i915_private *dev_priv;
4386 unsigned long chipset_val, graphics_val, ret = 0;
4387
9270388e 4388 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4389 if (!i915_mch_dev)
4390 goto out_unlock;
4391 dev_priv = i915_mch_dev;
4392
f531dcb2
CW		 4393 chipset_val = __i915_chipset_val(dev_priv);
4394 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4395
4396 ret = chipset_val + graphics_val;
4397
4398out_unlock:
9270388e 4399 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4400
4401 return ret;
4402}
4403EXPORT_SYMBOL_GPL(i915_read_mch_val);
4404
4405/**
4406 * i915_gpu_raise - raise GPU frequency limit
4407 *
4408 * Raise the limit; IPS indicates we have thermal headroom.
4409 */
4410bool i915_gpu_raise(void)
4411{
4412 struct drm_i915_private *dev_priv;
4413 bool ret = true;
4414
9270388e 4415 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4416 if (!i915_mch_dev) {
4417 ret = false;
4418 goto out_unlock;
4419 }
4420 dev_priv = i915_mch_dev;
4421
20e4d407
DV		 4422 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4423 dev_priv->ips.max_delay--;
eb48eb00
DV		 4424
4425out_unlock:
9270388e 4426 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4427
4428 return ret;
4429}
4430EXPORT_SYMBOL_GPL(i915_gpu_raise);
4431
4432/**
4433 * i915_gpu_lower - lower GPU frequency limit
4434 *
4435 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4436 * frequency maximum.
4437 */
4438bool i915_gpu_lower(void)
4439{
4440 struct drm_i915_private *dev_priv;
4441 bool ret = true;
4442
9270388e 4443 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4444 if (!i915_mch_dev) {
4445 ret = false;
4446 goto out_unlock;
4447 }
4448 dev_priv = i915_mch_dev;
4449
20e4d407
DV		 4450 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4451 dev_priv->ips.max_delay++;
eb48eb00
DV		 4452
4453out_unlock:
9270388e 4454 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4455
4456 return ret;
4457}
4458EXPORT_SYMBOL_GPL(i915_gpu_lower);
4459
4460/**
4461 * i915_gpu_busy - indicate GPU business to IPS
4462 *
4463 * Tell the IPS driver whether or not the GPU is busy.
4464 */
4465bool i915_gpu_busy(void)
4466{
4467 struct drm_i915_private *dev_priv;
f047e395 4468 struct intel_ring_buffer *ring;
eb48eb00 4469 bool ret = false;
f047e395 4470 int i;
eb48eb00 4471
9270388e 4472 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4473 if (!i915_mch_dev)
4474 goto out_unlock;
4475 dev_priv = i915_mch_dev;
4476
f047e395
CW		 4477 for_each_ring(ring, dev_priv, i)
4478 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4479
4480out_unlock:
9270388e 4481 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4482
4483 return ret;
4484}
4485EXPORT_SYMBOL_GPL(i915_gpu_busy);
4486
4487/**
4488 * i915_gpu_turbo_disable - disable graphics turbo
4489 *
4490 * Disable graphics turbo by resetting the max frequency and setting the
4491 * current frequency to the default.
4492 */
4493bool i915_gpu_turbo_disable(void)
4494{
4495 struct drm_i915_private *dev_priv;
4496 bool ret = true;
4497
9270388e 4498 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4499 if (!i915_mch_dev) {
4500 ret = false;
4501 goto out_unlock;
4502 }
4503 dev_priv = i915_mch_dev;
4504
20e4d407 4505 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4506
20e4d407 4507 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4508 ret = false;
4509
4510out_unlock:
9270388e 4511 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4512
4513 return ret;
4514}
4515EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4516
4517/**
4518 * Tells the intel_ips driver that the i915 driver is now loaded, if
4519 * IPS got loaded first.
4520 *
4521 * This awkward dance is so that neither module has to depend on the
4522 * other in order for IPS to do the appropriate communication of
4523 * GPU turbo limits to i915.
4524 */
4525static void
4526ips_ping_for_i915_load(void)
4527{
4528 void (*link)(void);
4529
4530 link = symbol_get(ips_link_to_i915_driver);
4531 if (link) {
4532 link();
4533 symbol_put(ips_link_to_i915_driver);
4534 }
4535}
4536
4537void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4538{
02d71956
DV		 4539 /* We only register the i915 ips part with intel-ips once everything is
4540 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4541 spin_lock_irq(&mchdev_lock);
eb48eb00 4542 i915_mch_dev = dev_priv;
9270388e 4543 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4544
4545 ips_ping_for_i915_load();
4546}
4547
4548void intel_gpu_ips_teardown(void)
4549{
9270388e 4550 spin_lock_irq(&mchdev_lock);
eb48eb00 4551 i915_mch_dev = NULL;
9270388e 4552 spin_unlock_irq(&mchdev_lock);
eb48eb00 4553}
8090c6b9 4554static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4555{
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 u32 lcfuse;
4558 u8 pxw[16];
4559 int i;
4560
4561 /* Disable to program */
4562 I915_WRITE(ECR, 0);
4563 POSTING_READ(ECR);
4564
4565 /* Program energy weights for various events */
4566 I915_WRITE(SDEW, 0x15040d00);
4567 I915_WRITE(CSIEW0, 0x007f0000);
4568 I915_WRITE(CSIEW1, 0x1e220004);
4569 I915_WRITE(CSIEW2, 0x04000004);
4570
4571 for (i = 0; i < 5; i++)
4572 I915_WRITE(PEW + (i * 4), 0);
4573 for (i = 0; i < 3; i++)
4574 I915_WRITE(DEW + (i * 4), 0);
4575
4576 /* Program P-state weights to account for frequency power adjustment */
4577 for (i = 0; i < 16; i++) {
4578 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4579 unsigned long freq = intel_pxfreq(pxvidfreq);
4580 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4581 PXVFREQ_PX_SHIFT;
4582 unsigned long val;
4583
4584 val = vid * vid;
4585 val *= (freq / 1000);
4586 val *= 255;
4587 val /= (127*127*900);
4588 if (val > 0xff)
4589 DRM_ERROR("bad pxval: %ld\n", val);
4590 pxw[i] = val;
4591 }
4592 /* Render standby states get 0 weight */
4593 pxw[14] = 0;
4594 pxw[15] = 0;
4595
4596 for (i = 0; i < 4; i++) {
4597 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4598 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4599 I915_WRITE(PXW + (i * 4), val);
4600 }
4601
4602 /* Adjust magic regs to magic values (more experimental results) */
4603 I915_WRITE(OGW0, 0);
4604 I915_WRITE(OGW1, 0);
4605 I915_WRITE(EG0, 0x00007f00);
4606 I915_WRITE(EG1, 0x0000000e);
4607 I915_WRITE(EG2, 0x000e0000);
4608 I915_WRITE(EG3, 0x68000300);
4609 I915_WRITE(EG4, 0x42000000);
4610 I915_WRITE(EG5, 0x00140031);
4611 I915_WRITE(EG6, 0);
4612 I915_WRITE(EG7, 0);
4613
4614 for (i = 0; i < 8; i++)
4615 I915_WRITE(PXWL + (i * 4), 0);
4616
4617 /* Enable PMON + select events */
4618 I915_WRITE(ECR, 0x80000019);
4619
4620 lcfuse = I915_READ(LCFUSE02);
4621
20e4d407 4622 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4623}
4624
8090c6b9
DV		 4625void intel_disable_gt_powersave(struct drm_device *dev)
4626{
1a01ab3b
JB		 4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628
fd0c0642
DV		 4629 /* Interrupts should be disabled already to avoid re-arming. */
4630 WARN_ON(dev->irq_enabled);
4631
930ebb46 4632 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4633 ironlake_disable_drps(dev);
930ebb46 4634 ironlake_disable_rc6(dev);
0a073b84 4635 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4636 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4637 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4638 if (IS_VALLEYVIEW(dev))
4639 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4640 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4641 if (IS_VALLEYVIEW(dev))
4642 valleyview_disable_rps(dev);
4643 else
4644 gen6_disable_rps(dev);
4fc688ce 4645 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4646 }
8090c6b9
DV		 4647}
4648
1a01ab3b
JB		 4649static void intel_gen6_powersave_work(struct work_struct *work)
4650{
4651 struct drm_i915_private *dev_priv =
4652 container_of(work, struct drm_i915_private,
4653 rps.delayed_resume_work.work);
4654 struct drm_device *dev = dev_priv->dev;
4655
4fc688ce 4656 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4657
4658 if (IS_VALLEYVIEW(dev)) {
4659 valleyview_enable_rps(dev);
4660 } else {
4661 gen6_enable_rps(dev);
4662 gen6_update_ring_freq(dev);
4663 }
4fc688ce 4664 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4665}
4666
8090c6b9
DV		 4667void intel_enable_gt_powersave(struct drm_device *dev)
4668{
1a01ab3b
JB		 4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
8090c6b9
DV		 4671 if (IS_IRONLAKE_M(dev)) {
4672 ironlake_enable_drps(dev);
4673 ironlake_enable_rc6(dev);
4674 intel_init_emon(dev);
0a073b84 4675 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4676 /*
4677 * PCU communication is slow and this doesn't need to be
4678 * done at any specific time, so do this out of our fast path
4679 * to make resume and init faster.
4680 */
4681 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4682 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4683 }
4684}
4685
3107bd48
DV		 4686static void ibx_init_clock_gating(struct drm_device *dev)
4687{
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4689
4690 /*
4691 * On Ibex Peak and Cougar Point, we need to disable clock
4692 * gating for the panel power sequencer or it will fail to
4693 * start up when no ports are active.
4694 */
4695 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4696}
4697
0e088b8f
VS		 4698static void g4x_disable_trickle_feed(struct drm_device *dev)
4699{
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 int pipe;
4702
4703 for_each_pipe(pipe) {
4704 I915_WRITE(DSPCNTR(pipe),
4705 I915_READ(DSPCNTR(pipe)) |
4706 DISPPLANE_TRICKLE_FEED_DISABLE);
4707 intel_flush_display_plane(dev_priv, pipe);
4708 }
4709}
4710
1fa61106 4711static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4712{
4713 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4714 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4715
f1e8fa56
DL		 4716 /*
4717 * Required for FBC
4718 * WaFbcDisableDpfcClockGating:ilk
4719 */
4d47e4f5
DL		 4720 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4721 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4722 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4723
4724 I915_WRITE(PCH_3DCGDIS0,
4725 MARIUNIT_CLOCK_GATE_DISABLE |
4726 SVSMUNIT_CLOCK_GATE_DISABLE);
4727 I915_WRITE(PCH_3DCGDIS1,
4728 VFMUNIT_CLOCK_GATE_DISABLE);
4729
6f1d69b0
ED		 4730 /*
4731 * According to the spec the following bits should be set in
4732 * order to enable memory self-refresh
4733 * The bit 22/21 of 0x42004
4734 * The bit 5 of 0x42020
4735 * The bit 15 of 0x45000
4736 */
4737 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4738 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4739 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4740 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4741 I915_WRITE(DISP_ARB_CTL,
4742 (I915_READ(DISP_ARB_CTL) |
4743 DISP_FBC_WM_DIS));
4744 I915_WRITE(WM3_LP_ILK, 0);
4745 I915_WRITE(WM2_LP_ILK, 0);
4746 I915_WRITE(WM1_LP_ILK, 0);
4747
4748 /*
4749 * Based on the document from hardware guys the following bits
4750 * should be set unconditionally in order to enable FBC.
4751 * The bit 22 of 0x42000
4752 * The bit 22 of 0x42004
4753 * The bit 7,8,9 of 0x42020.
4754 */
4755 if (IS_IRONLAKE_M(dev)) {
4bb35334 4756 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4757 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4758 I915_READ(ILK_DISPLAY_CHICKEN1) |
4759 ILK_FBCQ_DIS);
4760 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4761 I915_READ(ILK_DISPLAY_CHICKEN2) |
4762 ILK_DPARB_GATE);
6f1d69b0
ED		 4763 }
4764
4d47e4f5
DL		 4765 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4766
6f1d69b0
ED		 4767 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4768 I915_READ(ILK_DISPLAY_CHICKEN2) |
4769 ILK_ELPIN_409_SELECT);
4770 I915_WRITE(_3D_CHICKEN2,
4771 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4772 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4773
ecdb4eb7 4774 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4775 I915_WRITE(CACHE_MODE_0,
4776 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4777
0e088b8f 4778 g4x_disable_trickle_feed(dev);
bdad2b2f 4779
3107bd48
DV		 4780 ibx_init_clock_gating(dev);
4781}
4782
4783static void cpt_init_clock_gating(struct drm_device *dev)
4784{
4785 struct drm_i915_private *dev_priv = dev->dev_private;
4786 int pipe;
3f704fa2 4787 uint32_t val;
3107bd48
DV		 4788
4789 /*
4790 * On Ibex Peak and Cougar Point, we need to disable clock
4791 * gating for the panel power sequencer or it will fail to
4792 * start up when no ports are active.
4793 */
4794 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4795 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4796 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4797 /* The below fixes the weird display corruption, a few pixels shifted
4798 * downward, on (only) LVDS of some HP laptops with IVY.
4799 */
3f704fa2 4800 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4801 val = I915_READ(TRANS_CHICKEN2(pipe));
4802 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4803 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4804 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4805 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4806 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4807 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4808 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4809 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4810 }
3107bd48
DV		 4811 /* WADP0ClockGatingDisable */
4812 for_each_pipe(pipe) {
4813 I915_WRITE(TRANS_CHICKEN1(pipe),
4814 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4815 }
6f1d69b0
ED		 4816}
4817
1d7aaa0c
DV		 4818static void gen6_check_mch_setup(struct drm_device *dev)
4819{
4820 struct drm_i915_private *dev_priv = dev->dev_private;
4821 uint32_t tmp;
4822
4823 tmp = I915_READ(MCH_SSKPD);
4824 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4825 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4826 DRM_INFO("This can cause pipe underruns and display issues.\n");
4827 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4828 }
4829}
4830
1fa61106 4831static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4832{
4833 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4834 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4835
231e54f6 4836 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4837
4838 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4839 I915_READ(ILK_DISPLAY_CHICKEN2) |
4840 ILK_ELPIN_409_SELECT);
4841
ecdb4eb7 4842 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4843 I915_WRITE(_3D_CHICKEN,
4844 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4845
ecdb4eb7 4846 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4847 if (IS_SNB_GT1(dev))
4848 I915_WRITE(GEN6_GT_MODE,
4849 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4850
6f1d69b0
ED		 4851 I915_WRITE(WM3_LP_ILK, 0);
4852 I915_WRITE(WM2_LP_ILK, 0);
4853 I915_WRITE(WM1_LP_ILK, 0);
4854
6f1d69b0 4855 I915_WRITE(CACHE_MODE_0,
50743298 4856 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4857
4858 I915_WRITE(GEN6_UCGCTL1,
4859 I915_READ(GEN6_UCGCTL1) |
4860 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4861 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4862
4863 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4864 * gating disable must be set. Failure to set it results in
4865 * flickering pixels due to Z write ordering failures after
4866 * some amount of runtime in the Mesa "fire" demo, and Unigine
4867 * Sanctuary and Tropics, and apparently anything else with
4868 * alpha test or pixel discard.
4869 *
4870 * According to the spec, bit 11 (RCCUNIT) must also be set,
4871 * but we didn't debug actual testcases to find it out.
0f846f81 4872 *
ecdb4eb7
DL		 4873 * Also apply WaDisableVDSUnitClockGating:snb and
4874 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4875 */
4876 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4877 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4878 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4879 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4880
4881 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4882 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4883 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4884
4885 /*
4886 * According to the spec the following bits should be
4887 * set in order to enable memory self-refresh and fbc:
4888 * The bit21 and bit22 of 0x42000
4889 * The bit21 and bit22 of 0x42004
4890 * The bit5 and bit7 of 0x42020
4891 * The bit14 of 0x70180
4892 * The bit14 of 0x71180
4bb35334
DL		 4893 *
4894 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4895 */
4896 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4897 I915_READ(ILK_DISPLAY_CHICKEN1) |
4898 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4899 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4900 I915_READ(ILK_DISPLAY_CHICKEN2) |
4901 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4902 I915_WRITE(ILK_DSPCLK_GATE_D,
4903 I915_READ(ILK_DSPCLK_GATE_D) |
4904 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4905 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4906
0e088b8f 4907 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4908
4909 /* The default value should be 0x200 according to docs, but the two
4910 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4911 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4912 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4913
4914 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4915
4916 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4917}
4918
4919static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4920{
4921 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4922
4923 reg &= ~GEN7_FF_SCHED_MASK;
4924 reg |= GEN7_FF_TS_SCHED_HW;
4925 reg |= GEN7_FF_VS_SCHED_HW;
4926 reg |= GEN7_FF_DS_SCHED_HW;
4927
41c0b3a8
BW		 4928 if (IS_HASWELL(dev_priv->dev))
4929 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4930
6f1d69b0
ED		 4931 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4932}
4933
17a303ec
PZ		 4934static void lpt_init_clock_gating(struct drm_device *dev)
4935{
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4937
4938 /*
4939 * TODO: this bit should only be enabled when really needed, then
4940 * disabled when not needed anymore in order to save power.
4941 */
4942 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4943 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4944 I915_READ(SOUTH_DSPCLK_GATE_D) |
4945 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4946
4947 /* WADPOClockGatingDisable:hsw */
4948 I915_WRITE(_TRANSA_CHICKEN1,
4949 I915_READ(_TRANSA_CHICKEN1) |
4950 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4951}
4952
7d708ee4
ID		 4953static void lpt_suspend_hw(struct drm_device *dev)
4954{
4955 struct drm_i915_private *dev_priv = dev->dev_private;
4956
4957 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4958 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4959
4960 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4961 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4962 }
4963}
4964
cad2a2d7
ED		 4965static void haswell_init_clock_gating(struct drm_device *dev)
4966{
4967 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4968
4969 I915_WRITE(WM3_LP_ILK, 0);
4970 I915_WRITE(WM2_LP_ILK, 0);
4971 I915_WRITE(WM1_LP_ILK, 0);
4972
4973 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4974 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4975 */
4976 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4977
ecdb4eb7 4978 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4979 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4980 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4981
ecdb4eb7 4982 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4983 I915_WRITE(GEN7_L3CNTLREG1,
4984 GEN7_WA_FOR_GEN7_L3_CONTROL);
4985 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4986 GEN7_WA_L3_CHICKEN_MODE);
4987
ecdb4eb7 4988 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4989 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4990 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4991 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4992
ecdb4eb7 4993 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4994 gen7_setup_fixed_func_scheduler(dev_priv);
4995
ecdb4eb7 4996 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4997 I915_WRITE(CACHE_MODE_1,
4998 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4999
ecdb4eb7 5000 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5001 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5002
90a88643
PZ		 5003 /* WaRsPkgCStateDisplayPMReq:hsw */
5004 I915_WRITE(CHICKEN_PAR1_1,
5005 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5006
17a303ec 5007 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5008}
5009
1fa61106 5010static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5011{
5012 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5013 uint32_t snpcr;
6f1d69b0 5014
6f1d69b0
ED		 5015 I915_WRITE(WM3_LP_ILK, 0);
5016 I915_WRITE(WM2_LP_ILK, 0);
5017 I915_WRITE(WM1_LP_ILK, 0);
5018
231e54f6 5019 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5020
ecdb4eb7 5021 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5022 I915_WRITE(_3D_CHICKEN3,
5023 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5024
ecdb4eb7 5025 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5026 I915_WRITE(IVB_CHICKEN3,
5027 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5028 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5029
ecdb4eb7 5030 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5031 if (IS_IVB_GT1(dev))
5032 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5033 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5034 else
5035 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5036 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5037
ecdb4eb7 5038 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5039 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5040 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5041
ecdb4eb7 5042 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5043 I915_WRITE(GEN7_L3CNTLREG1,
5044 GEN7_WA_FOR_GEN7_L3_CONTROL);
5045 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5046 GEN7_WA_L3_CHICKEN_MODE);
5047 if (IS_IVB_GT1(dev))
5048 I915_WRITE(GEN7_ROW_CHICKEN2,
5049 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5050 else
5051 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5052 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5053
6f1d69b0 5054
ecdb4eb7 5055 /* WaForceL3Serialization:ivb */
61939d97
JB		 5056 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5057 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5058
0f846f81
JB		 5059 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5060 * gating disable must be set. Failure to set it results in
5061 * flickering pixels due to Z write ordering failures after
5062 * some amount of runtime in the Mesa "fire" demo, and Unigine
5063 * Sanctuary and Tropics, and apparently anything else with
5064 * alpha test or pixel discard.
5065 *
5066 * According to the spec, bit 11 (RCCUNIT) must also be set,
5067 * but we didn't debug actual testcases to find it out.
5068 *
5069 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5070 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5071 */
5072 I915_WRITE(GEN6_UCGCTL2,
5073 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5074 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5075
ecdb4eb7 5076 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5077 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5078 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5079 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5080
0e088b8f 5081 g4x_disable_trickle_feed(dev);
6f1d69b0 5082
ecdb4eb7 5083 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5084 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5085
ecdb4eb7 5086 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5087 I915_WRITE(CACHE_MODE_1,
5088 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5089
5090 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5091 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5092 snpcr |= GEN6_MBC_SNPCR_MED;
5093 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5094
ab5c608b
BW		 5095 if (!HAS_PCH_NOP(dev))
5096 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5097
5098 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5099}
5100
1fa61106 5101static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5102{
5103 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 5104
d7fe0cc0 5105 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5106
ecdb4eb7 5107 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5108 I915_WRITE(_3D_CHICKEN3,
5109 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5110
ecdb4eb7 5111 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5112 I915_WRITE(IVB_CHICKEN3,
5113 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5114 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5115
ecdb4eb7 5116 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5117 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5118 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5119 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5120
ecdb4eb7 5121 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5122 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5123 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5124
ecdb4eb7 5125 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5126 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5127 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5128
ecdb4eb7 5129 /* WaForceL3Serialization:vlv */
61939d97
JB		 5130 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5131 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5132
ecdb4eb7 5133 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5134 I915_WRITE(GEN7_ROW_CHICKEN2,
5135 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5136
ecdb4eb7 5137 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5138 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5139 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5140 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5141
0f846f81
JB		 5142 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5143 * gating disable must be set. Failure to set it results in
5144 * flickering pixels due to Z write ordering failures after
5145 * some amount of runtime in the Mesa "fire" demo, and Unigine
5146 * Sanctuary and Tropics, and apparently anything else with
5147 * alpha test or pixel discard.
5148 *
5149 * According to the spec, bit 11 (RCCUNIT) must also be set,
5150 * but we didn't debug actual testcases to find it out.
5151 *
5152 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5153 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5154 *
ecdb4eb7
DL		 5155 * Also apply WaDisableVDSUnitClockGating:vlv and
5156 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5157 */
5158 I915_WRITE(GEN6_UCGCTL2,
5159 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5160 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5161 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5162 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5163 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5164
e3f33d46
JB		 5165 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5166
e0d8d59b 5167 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5168
6b26c86d
DV		 5169 I915_WRITE(CACHE_MODE_1,
5170 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5171
2d809570 5172 /*
ecdb4eb7 5173 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5174 * Disable clock gating on th GCFG unit to prevent a delay
5175 * in the reporting of vblank events.
5176 */
4e8c84a5
JB		 5177 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5178
5179 /* Conservative clock gating settings for now */
5180 I915_WRITE(0x9400, 0xffffffff);
5181 I915_WRITE(0x9404, 0xffffffff);
5182 I915_WRITE(0x9408, 0xffffffff);
5183 I915_WRITE(0x940c, 0xffffffff);
5184 I915_WRITE(0x9410, 0xffffffff);
5185 I915_WRITE(0x9414, 0xffffffff);
5186 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5187}
5188
1fa61106 5189static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5190{
5191 struct drm_i915_private *dev_priv = dev->dev_private;
5192 uint32_t dspclk_gate;
5193
5194 I915_WRITE(RENCLK_GATE_D1, 0);
5195 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5196 GS_UNIT_CLOCK_GATE_DISABLE |
5197 CL_UNIT_CLOCK_GATE_DISABLE);
5198 I915_WRITE(RAMCLK_GATE_D, 0);
5199 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5200 OVRUNIT_CLOCK_GATE_DISABLE |
5201 OVCUNIT_CLOCK_GATE_DISABLE;
5202 if (IS_GM45(dev))
5203 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5204 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5205
5206 /* WaDisableRenderCachePipelinedFlush */
5207 I915_WRITE(CACHE_MODE_0,
5208 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5209
0e088b8f 5210 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5211}
5212
1fa61106 5213static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5214{
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216
5217 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5218 I915_WRITE(RENCLK_GATE_D2, 0);
5219 I915_WRITE(DSPCLK_GATE_D, 0);
5220 I915_WRITE(RAMCLK_GATE_D, 0);
5221 I915_WRITE16(DEUC, 0);
20f94967
VS		 5222 I915_WRITE(MI_ARB_STATE,
5223 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5224}
5225
1fa61106 5226static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5227{
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5229
5230 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5231 I965_RCC_CLOCK_GATE_DISABLE |
5232 I965_RCPB_CLOCK_GATE_DISABLE |
5233 I965_ISC_CLOCK_GATE_DISABLE |
5234 I965_FBC_CLOCK_GATE_DISABLE);
5235 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5236 I915_WRITE(MI_ARB_STATE,
5237 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5238}
5239
1fa61106 5240static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5241{
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243 u32 dstate = I915_READ(D_STATE);
5244
5245 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5246 DSTATE_DOT_CLOCK_GATING;
5247 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5248
5249 if (IS_PINEVIEW(dev))
5250 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5251
5252 /* IIR "flip pending" means done if this bit is set */
5253 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5254}
5255
1fa61106 5256static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5257{
5258 struct drm_i915_private *dev_priv = dev->dev_private;
5259
5260 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5261}
5262
1fa61106 5263static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5264{
5265 struct drm_i915_private *dev_priv = dev->dev_private;
5266
5267 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5268}
5269
6f1d69b0
ED		 5270void intel_init_clock_gating(struct drm_device *dev)
5271{
5272 struct drm_i915_private *dev_priv = dev->dev_private;
5273
5274 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5275}
5276
7d708ee4
ID		 5277void intel_suspend_hw(struct drm_device *dev)
5278{
5279 if (HAS_PCH_LPT(dev))
5280 lpt_suspend_hw(dev);
5281}
5282
15d199ea
PZ		 5283/**
5284 * We should only use the power well if we explicitly asked the hardware to
5285 * enable it, so check if it's enabled and also check if we've requested it to
5286 * be enabled.
5287 */
b97186f0
PZ		 5288bool intel_display_power_enabled(struct drm_device *dev,
5289 enum intel_display_power_domain domain)
15d199ea
PZ		 5290{
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292
b97186f0
PZ		 5293 if (!HAS_POWER_WELL(dev))
5294 return true;
5295
5296 switch (domain) {
5297 case POWER_DOMAIN_PIPE_A:
5298 case POWER_DOMAIN_TRANSCODER_EDP:
5299 return true;
cdf8dd7f 5300 case POWER_DOMAIN_VGA:
b97186f0
PZ		 5301 case POWER_DOMAIN_PIPE_B:
5302 case POWER_DOMAIN_PIPE_C:
5303 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5304 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5305 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5306 case POWER_DOMAIN_TRANSCODER_A:
5307 case POWER_DOMAIN_TRANSCODER_B:
5308 case POWER_DOMAIN_TRANSCODER_C:
15d199ea 5309 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6aedd1f5 5310 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
b97186f0
PZ		 5311 default:
5312 BUG();
5313 }
15d199ea
PZ		 5314}
5315
a38911a3 5316static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5317{
5318 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5319 bool is_enabled, enable_requested;
5320 uint32_t tmp;
d0d3e513 5321
fa42e23c 5322 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5323 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5324 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5325
fa42e23c
PZ		 5326 if (enable) {
5327 if (!enable_requested)
6aedd1f5
PZ		 5328 I915_WRITE(HSW_PWR_WELL_DRIVER,
5329 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5330
fa42e23c
PZ		 5331 if (!is_enabled) {
5332 DRM_DEBUG_KMS("Enabling power well\n");
5333 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5334 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5335 DRM_ERROR("Timeout enabling power well\n");
5336 }
5337 } else {
5338 if (enable_requested) {
9dbd8feb
PZ		 5339 unsigned long irqflags;
5340 enum pipe p;
5341
fa42e23c 5342 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5343 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5344 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb
PZ		 5345
5346 /*
5347 * After this, the registers on the pipes that are part
5348 * of the power well will become zero, so we have to
5349 * adjust our counters according to that.
5350 *
5351 * FIXME: Should we do this in general in
5352 * drm_vblank_post_modeset?
5353 */
5354 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5355 for_each_pipe(p)
5356 if (p != PIPE_A)
5357 dev->last_vblank[p] = 0;
5358 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
d0d3e513
ED		 5359 }
5360 }
fa42e23c 5361}
d0d3e513 5362
2d66aef5
VS		 5363static void __intel_power_well_get(struct i915_power_well *power_well)
5364{
5365 if (!power_well->count++)
5366 __intel_set_power_well(power_well->device, true);
5367}
5368
5369static void __intel_power_well_put(struct i915_power_well *power_well)
5370{
5371 WARN_ON(!power_well->count);
5372 if (!--power_well->count)
5373 __intel_set_power_well(power_well->device, false);
5374}
5375
6765625e
VS		 5376void intel_display_power_get(struct drm_device *dev,
5377 enum intel_display_power_domain domain)
5378{
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5380 struct i915_power_well *power_well = &dev_priv->power_well;
5381
5382 if (!HAS_POWER_WELL(dev))
5383 return;
5384
5385 switch (domain) {
5386 case POWER_DOMAIN_PIPE_A:
5387 case POWER_DOMAIN_TRANSCODER_EDP:
5388 return;
cdf8dd7f 5389 case POWER_DOMAIN_VGA:
6765625e
VS		 5390 case POWER_DOMAIN_PIPE_B:
5391 case POWER_DOMAIN_PIPE_C:
5392 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5393 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5394 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5395 case POWER_DOMAIN_TRANSCODER_A:
5396 case POWER_DOMAIN_TRANSCODER_B:
5397 case POWER_DOMAIN_TRANSCODER_C:
5398 spin_lock_irq(&power_well->lock);
2d66aef5 5399 __intel_power_well_get(power_well);
6765625e
VS		 5400 spin_unlock_irq(&power_well->lock);
5401 return;
5402 default:
5403 BUG();
5404 }
5405}
5406
5407void intel_display_power_put(struct drm_device *dev,
5408 enum intel_display_power_domain domain)
5409{
5410 struct drm_i915_private *dev_priv = dev->dev_private;
5411 struct i915_power_well *power_well = &dev_priv->power_well;
5412
5413 if (!HAS_POWER_WELL(dev))
5414 return;
5415
5416 switch (domain) {
5417 case POWER_DOMAIN_PIPE_A:
5418 case POWER_DOMAIN_TRANSCODER_EDP:
5419 return;
cdf8dd7f 5420 case POWER_DOMAIN_VGA:
6765625e
VS		 5421 case POWER_DOMAIN_PIPE_B:
5422 case POWER_DOMAIN_PIPE_C:
5423 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5424 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5425 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5426 case POWER_DOMAIN_TRANSCODER_A:
5427 case POWER_DOMAIN_TRANSCODER_B:
5428 case POWER_DOMAIN_TRANSCODER_C:
5429 spin_lock_irq(&power_well->lock);
2d66aef5 5430 __intel_power_well_put(power_well);
6765625e
VS		 5431 spin_unlock_irq(&power_well->lock);
5432 return;
5433 default:
5434 BUG();
5435 }
5436}
5437
a38911a3
WX		 5438static struct i915_power_well *hsw_pwr;
5439
5440/* Display audio driver power well request */
5441void i915_request_power_well(void)
5442{
5443 if (WARN_ON(!hsw_pwr))
5444 return;
5445
5446 spin_lock_irq(&hsw_pwr->lock);
2d66aef5 5447 __intel_power_well_get(hsw_pwr);
a38911a3
WX		 5448 spin_unlock_irq(&hsw_pwr->lock);
5449}
5450EXPORT_SYMBOL_GPL(i915_request_power_well);
5451
5452/* Display audio driver power well release */
5453void i915_release_power_well(void)
5454{
5455 if (WARN_ON(!hsw_pwr))
5456 return;
5457
5458 spin_lock_irq(&hsw_pwr->lock);
2d66aef5 5459 __intel_power_well_put(hsw_pwr);
a38911a3
WX		 5460 spin_unlock_irq(&hsw_pwr->lock);
5461}
5462EXPORT_SYMBOL_GPL(i915_release_power_well);
5463
5464int i915_init_power_well(struct drm_device *dev)
5465{
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467
5468 hsw_pwr = &dev_priv->power_well;
5469
5470 hsw_pwr->device = dev;
5471 spin_lock_init(&hsw_pwr->lock);
5472 hsw_pwr->count = 0;
5473
5474 return 0;
5475}
5476
5477void i915_remove_power_well(struct drm_device *dev)
5478{
5479 hsw_pwr = NULL;
5480}
5481
5482void intel_set_power_well(struct drm_device *dev, bool enable)
5483{
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485 struct i915_power_well *power_well = &dev_priv->power_well;
5486
5487 if (!HAS_POWER_WELL(dev))
5488 return;
5489
5490 if (!i915_disable_power_well && !enable)
5491 return;
5492
5493 spin_lock_irq(&power_well->lock);
9cdb826c
VS		 5494
5495 /*
5496 * This function will only ever contribute one
5497 * to the power well reference count. i915_request
5498 * is what tracks whether we have or have not
5499 * added the one to the reference count.
5500 */
5501 if (power_well->i915_request == enable)
5502 goto out;
5503
a38911a3
WX		 5504 power_well->i915_request = enable;
5505
2d66aef5
VS		 5506 if (enable)
5507 __intel_power_well_get(power_well);
5508 else
5509 __intel_power_well_put(power_well);
a38911a3 5510
9cdb826c
VS		 5511 out:
5512 spin_unlock_irq(&power_well->lock);
5513}
5514
51340990 5515static void intel_resume_power_well(struct drm_device *dev)
9cdb826c
VS		 5516{
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518 struct i915_power_well *power_well = &dev_priv->power_well;
5519
5520 if (!HAS_POWER_WELL(dev))
5521 return;
5522
5523 spin_lock_irq(&power_well->lock);
5524 __intel_set_power_well(dev, power_well->count > 0);
a38911a3
WX		 5525 spin_unlock_irq(&power_well->lock);
5526}
5527
fa42e23c
PZ		 5528/*
5529 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5530 * when not needed anymore. We have 4 registers that can request the power well
5531 * to be enabled, and it will only be disabled if none of the registers is
5532 * requesting it to be enabled.
d0d3e513 5533 */
fa42e23c 5534void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5535{
5536 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5537
86d52df6 5538 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5539 return;
5540
fa42e23c
PZ		 5541 /* For now, we need the power well to be always enabled. */
5542 intel_set_power_well(dev, true);
9cdb826c 5543 intel_resume_power_well(dev);
d0d3e513 5544
fa42e23c
PZ		 5545 /* We're taking over the BIOS, so clear any requests made by it since
5546 * the driver is in charge now. */
6aedd1f5 5547 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5548 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5549}
5550
c67a470b
PZ		 5551/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5552void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5553{
5554 hsw_disable_package_c8(dev_priv);
5555}
5556
5557void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5558{
5559 hsw_enable_package_c8(dev_priv);
5560}
5561
1fa61106
ED		 5562/* Set up chip specific power management-related functions */
5563void intel_init_pm(struct drm_device *dev)
5564{
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566
5567 if (I915_HAS_FBC(dev)) {
5568 if (HAS_PCH_SPLIT(dev)) {
5569 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5570 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5571 dev_priv->display.enable_fbc =
5572 gen7_enable_fbc;
5573 else
5574 dev_priv->display.enable_fbc =
5575 ironlake_enable_fbc;
1fa61106
ED		 5576 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5577 } else if (IS_GM45(dev)) {
5578 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5579 dev_priv->display.enable_fbc = g4x_enable_fbc;
5580 dev_priv->display.disable_fbc = g4x_disable_fbc;
5581 } else if (IS_CRESTLINE(dev)) {
5582 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5583 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5584 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5585 }
5586 /* 855GM needs testing */
5587 }
5588
c921aba8
DV		 5589 /* For cxsr */
5590 if (IS_PINEVIEW(dev))
5591 i915_pineview_get_mem_freq(dev);
5592 else if (IS_GEN5(dev))
5593 i915_ironlake_get_mem_freq(dev);
5594
1fa61106
ED		 5595 /* For FIFO watermark updates */
5596 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5597 intel_setup_wm_latency(dev);
5598
1fa61106 5599 if (IS_GEN5(dev)) {
53615a5e
VS		 5600 if (dev_priv->wm.pri_latency[1] &&
5601 dev_priv->wm.spr_latency[1] &&
5602 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5603 dev_priv->display.update_wm = ironlake_update_wm;
5604 else {
5605 DRM_DEBUG_KMS("Failed to get proper latency. "
5606 "Disable CxSR\n");
5607 dev_priv->display.update_wm = NULL;
5608 }
5609 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5610 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5611 if (dev_priv->wm.pri_latency[0] &&
5612 dev_priv->wm.spr_latency[0] &&
5613 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5614 dev_priv->display.update_wm = sandybridge_update_wm;
5615 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5616 } else {
5617 DRM_DEBUG_KMS("Failed to read display plane latency. "
5618 "Disable CxSR\n");
5619 dev_priv->display.update_wm = NULL;
5620 }
5621 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5622 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5623 if (dev_priv->wm.pri_latency[0] &&
5624 dev_priv->wm.spr_latency[0] &&
5625 dev_priv->wm.cur_latency[0]) {
c43d0188 5626 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5627 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5628 } else {
5629 DRM_DEBUG_KMS("Failed to read display plane latency. "
5630 "Disable CxSR\n");
5631 dev_priv->display.update_wm = NULL;
5632 }
5633 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5634 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5635 if (dev_priv->wm.pri_latency[0] &&
5636 dev_priv->wm.spr_latency[0] &&
5637 dev_priv->wm.cur_latency[0]) {
1011d8c4 5638 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5639 dev_priv->display.update_sprite_wm =
5640 haswell_update_sprite_wm;
6b8a5eeb
ED		 5641 } else {
5642 DRM_DEBUG_KMS("Failed to read display plane latency. "
5643 "Disable CxSR\n");
5644 dev_priv->display.update_wm = NULL;
5645 }
cad2a2d7 5646 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5647 } else
5648 dev_priv->display.update_wm = NULL;
5649 } else if (IS_VALLEYVIEW(dev)) {
5650 dev_priv->display.update_wm = valleyview_update_wm;
5651 dev_priv->display.init_clock_gating =
5652 valleyview_init_clock_gating;
1fa61106
ED		 5653 } else if (IS_PINEVIEW(dev)) {
5654 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5655 dev_priv->is_ddr3,
5656 dev_priv->fsb_freq,
5657 dev_priv->mem_freq)) {
5658 DRM_INFO("failed to find known CxSR latency "
5659 "(found ddr%s fsb freq %d, mem freq %d), "
5660 "disabling CxSR\n",
5661 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5662 dev_priv->fsb_freq, dev_priv->mem_freq);
5663 /* Disable CxSR and never update its watermark again */
5664 pineview_disable_cxsr(dev);
5665 dev_priv->display.update_wm = NULL;
5666 } else
5667 dev_priv->display.update_wm = pineview_update_wm;
5668 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5669 } else if (IS_G4X(dev)) {
5670 dev_priv->display.update_wm = g4x_update_wm;
5671 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5672 } else if (IS_GEN4(dev)) {
5673 dev_priv->display.update_wm = i965_update_wm;
5674 if (IS_CRESTLINE(dev))
5675 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5676 else if (IS_BROADWATER(dev))
5677 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5678 } else if (IS_GEN3(dev)) {
5679 dev_priv->display.update_wm = i9xx_update_wm;
5680 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5681 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5682 } else if (IS_I865G(dev)) {
5683 dev_priv->display.update_wm = i830_update_wm;
5684 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5685 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5686 } else if (IS_I85X(dev)) {
5687 dev_priv->display.update_wm = i9xx_update_wm;
5688 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5689 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5690 } else {
5691 dev_priv->display.update_wm = i830_update_wm;
5692 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5693 if (IS_845G(dev))
5694 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5695 else
5696 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5697 }
5698}
5699
42c0526c
BW		 5700int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5701{
4fc688ce 5702 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5703
5704 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5705 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5706 return -EAGAIN;
5707 }
5708
5709 I915_WRITE(GEN6_PCODE_DATA, *val);
5710 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5711
5712 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5713 500)) {
5714 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5715 return -ETIMEDOUT;
5716 }
5717
5718 *val = I915_READ(GEN6_PCODE_DATA);
5719 I915_WRITE(GEN6_PCODE_DATA, 0);
5720
5721 return 0;
5722}
5723
5724int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5725{
4fc688ce 5726 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5727
5728 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5729 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5730 return -EAGAIN;
5731 }
5732
5733 I915_WRITE(GEN6_PCODE_DATA, val);
5734 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5735
5736 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5737 500)) {
5738 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5739 return -ETIMEDOUT;
5740 }
5741
5742 I915_WRITE(GEN6_PCODE_DATA, 0);
5743
5744 return 0;
5745}
a0e4e199 5746
855ba3be
JB		 5747int vlv_gpu_freq(int ddr_freq, int val)
5748{
5749 int mult, base;
5750
5751 switch (ddr_freq) {
5752 case 800:
5753 mult = 20;
5754 base = 120;
5755 break;
5756 case 1066:
5757 mult = 22;
5758 base = 133;
5759 break;
5760 case 1333:
5761 mult = 21;
5762 base = 125;
5763 break;
5764 default:
5765 return -1;
5766 }
5767
5768 return ((val - 0xbd) * mult) + base;
5769}
5770
5771int vlv_freq_opcode(int ddr_freq, int val)
5772{
5773 int mult, base;
5774
5775 switch (ddr_freq) {
5776 case 800:
5777 mult = 20;
5778 base = 120;
5779 break;
5780 case 1066:
5781 mult = 22;
5782 base = 133;
5783 break;
5784 case 1333:
5785 mult = 21;
5786 base = 125;
5787 break;
5788 default:
5789 return -1;
5790 }
5791
5792 val /= mult;
5793 val -= base / mult;
5794 val += 0xbd;
5795
5796 if (val > 0xea)
5797 val = 0xea;
5798
5799 return val;
5800}
5801
907b28c5
CW		 5802void intel_pm_init(struct drm_device *dev)
5803{
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805
5806 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5807 intel_gen6_powersave_work);
5808}
5809
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