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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
9c2f7a9d | 29 | #include <drm/drm_plane_helper.h> |
85208be0 ED |
30 | #include "i915_drv.h" |
31 | #include "intel_drv.h" | |
eb48eb00 DV |
32 | #include "../../../platform/x86/intel_ips.h" |
33 | #include <linux/module.h> | |
c8fe32c1 | 34 | #include <drm/drm_atomic_helper.h> |
85208be0 | 35 | |
dc39fff7 | 36 | /** |
18afd443 JN |
37 | * DOC: RC6 |
38 | * | |
dc39fff7 BW |
39 | * RC6 is a special power stage which allows the GPU to enter an very |
40 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
41 | * stage is entered automatically when the GPU is idle when RC6 support is | |
42 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
43 | * | |
44 | * There are different RC6 modes available in Intel GPU, which differentiate | |
45 | * among each other with the latency required to enter and leave RC6 and | |
46 | * voltage consumed by the GPU in different states. | |
47 | * | |
48 | * The combination of the following flags define which states GPU is allowed | |
49 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
50 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
51 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
52 | * which brings the most power savings; deeper states save more power, but | |
53 | * require higher latency to switch to and wake up. | |
54 | */ | |
55 | #define INTEL_RC6_ENABLE (1<<0) | |
56 | #define INTEL_RC6p_ENABLE (1<<1) | |
57 | #define INTEL_RC6pp_ENABLE (1<<2) | |
58 | ||
46f16e63 | 59 | static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) |
a82abe43 | 60 | { |
b033bb6d | 61 | /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */ |
dc00b6a0 DV |
62 | I915_WRITE(CHICKEN_PAR1_1, |
63 | I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); | |
64 | ||
b033bb6d MK |
65 | I915_WRITE(GEN8_CONFIG0, |
66 | I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); | |
590e8ff0 | 67 | |
9fb5026f | 68 | /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ |
590e8ff0 MK |
69 | I915_WRITE(GEN8_CHICKEN_DCPR_1, |
70 | I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); | |
0f78dee6 MK |
71 | |
72 | /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ | |
9fb5026f | 73 | /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ |
303d4ea5 MK |
74 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
75 | DISP_FBC_WM_DIS | | |
76 | DISP_FBC_MEMORY_WAKE); | |
d1b4eefd MK |
77 | |
78 | /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */ | |
79 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
80 | ILK_DPFC_DISABLE_DUMMY0); | |
b033bb6d MK |
81 | } |
82 | ||
46f16e63 | 83 | static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) |
b033bb6d | 84 | { |
46f16e63 | 85 | gen9_init_clock_gating(dev_priv); |
b033bb6d | 86 | |
a7546159 NH |
87 | /* WaDisableSDEUnitClockGating:bxt */ |
88 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
89 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
90 | ||
32608ca2 ID |
91 | /* |
92 | * FIXME: | |
868434c5 | 93 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
32608ca2 | 94 | */ |
32608ca2 | 95 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
868434c5 | 96 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
d965e7ac ID |
97 | |
98 | /* | |
99 | * Wa: Backlight PWM may stop in the asserted state, causing backlight | |
100 | * to stay fully on. | |
101 | */ | |
8aeaf64c JN |
102 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | |
103 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
a82abe43 ID |
104 | } |
105 | ||
9fb5026f ACO |
106 | static void glk_init_clock_gating(struct drm_i915_private *dev_priv) |
107 | { | |
108 | gen9_init_clock_gating(dev_priv); | |
109 | ||
110 | /* | |
111 | * WaDisablePWMClockGating:glk | |
112 | * Backlight PWM may stop in the asserted state, causing backlight | |
113 | * to stay fully on. | |
114 | */ | |
115 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | | |
116 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
f4f4b59b ACO |
117 | |
118 | /* WaDDIIOTimeout:glk */ | |
119 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { | |
120 | u32 val = I915_READ(CHICKEN_MISC_2); | |
121 | val &= ~(GLK_CL0_PWR_DOWN | | |
122 | GLK_CL1_PWR_DOWN | | |
123 | GLK_CL2_PWR_DOWN); | |
124 | I915_WRITE(CHICKEN_MISC_2, val); | |
125 | } | |
126 | ||
9fb5026f ACO |
127 | } |
128 | ||
148ac1f3 | 129 | static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 130 | { |
c921aba8 DV |
131 | u32 tmp; |
132 | ||
133 | tmp = I915_READ(CLKCFG); | |
134 | ||
135 | switch (tmp & CLKCFG_FSB_MASK) { | |
136 | case CLKCFG_FSB_533: | |
137 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
138 | break; | |
139 | case CLKCFG_FSB_800: | |
140 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
141 | break; | |
142 | case CLKCFG_FSB_667: | |
143 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
144 | break; | |
145 | case CLKCFG_FSB_400: | |
146 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
147 | break; | |
148 | } | |
149 | ||
150 | switch (tmp & CLKCFG_MEM_MASK) { | |
151 | case CLKCFG_MEM_533: | |
152 | dev_priv->mem_freq = 533; | |
153 | break; | |
154 | case CLKCFG_MEM_667: | |
155 | dev_priv->mem_freq = 667; | |
156 | break; | |
157 | case CLKCFG_MEM_800: | |
158 | dev_priv->mem_freq = 800; | |
159 | break; | |
160 | } | |
161 | ||
162 | /* detect pineview DDR3 setting */ | |
163 | tmp = I915_READ(CSHRDDR3CTL); | |
164 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
165 | } | |
166 | ||
148ac1f3 | 167 | static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 168 | { |
c921aba8 DV |
169 | u16 ddrpll, csipll; |
170 | ||
171 | ddrpll = I915_READ16(DDRMPLL1); | |
172 | csipll = I915_READ16(CSIPLL0); | |
173 | ||
174 | switch (ddrpll & 0xff) { | |
175 | case 0xc: | |
176 | dev_priv->mem_freq = 800; | |
177 | break; | |
178 | case 0x10: | |
179 | dev_priv->mem_freq = 1066; | |
180 | break; | |
181 | case 0x14: | |
182 | dev_priv->mem_freq = 1333; | |
183 | break; | |
184 | case 0x18: | |
185 | dev_priv->mem_freq = 1600; | |
186 | break; | |
187 | default: | |
188 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
189 | ddrpll & 0xff); | |
190 | dev_priv->mem_freq = 0; | |
191 | break; | |
192 | } | |
193 | ||
20e4d407 | 194 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
195 | |
196 | switch (csipll & 0x3ff) { | |
197 | case 0x00c: | |
198 | dev_priv->fsb_freq = 3200; | |
199 | break; | |
200 | case 0x00e: | |
201 | dev_priv->fsb_freq = 3733; | |
202 | break; | |
203 | case 0x010: | |
204 | dev_priv->fsb_freq = 4266; | |
205 | break; | |
206 | case 0x012: | |
207 | dev_priv->fsb_freq = 4800; | |
208 | break; | |
209 | case 0x014: | |
210 | dev_priv->fsb_freq = 5333; | |
211 | break; | |
212 | case 0x016: | |
213 | dev_priv->fsb_freq = 5866; | |
214 | break; | |
215 | case 0x018: | |
216 | dev_priv->fsb_freq = 6400; | |
217 | break; | |
218 | default: | |
219 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
220 | csipll & 0x3ff); | |
221 | dev_priv->fsb_freq = 0; | |
222 | break; | |
223 | } | |
224 | ||
225 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 226 | dev_priv->ips.c_m = 0; |
c921aba8 | 227 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 228 | dev_priv->ips.c_m = 1; |
c921aba8 | 229 | } else { |
20e4d407 | 230 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
231 | } |
232 | } | |
233 | ||
b445e3b0 ED |
234 | static const struct cxsr_latency cxsr_latency_table[] = { |
235 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
236 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
237 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
238 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
239 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
240 | ||
241 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
242 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
243 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
244 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
245 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
246 | ||
247 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
248 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
249 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
250 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
251 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
252 | ||
253 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
254 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
255 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
256 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
257 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
258 | ||
259 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
260 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
261 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
262 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
263 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
264 | ||
265 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
266 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
267 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
268 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
269 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
270 | }; | |
271 | ||
44a655ca TU |
272 | static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop, |
273 | bool is_ddr3, | |
b445e3b0 ED |
274 | int fsb, |
275 | int mem) | |
276 | { | |
277 | const struct cxsr_latency *latency; | |
278 | int i; | |
279 | ||
280 | if (fsb == 0 || mem == 0) | |
281 | return NULL; | |
282 | ||
283 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
284 | latency = &cxsr_latency_table[i]; | |
285 | if (is_desktop == latency->is_desktop && | |
286 | is_ddr3 == latency->is_ddr3 && | |
287 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
288 | return latency; | |
289 | } | |
290 | ||
291 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
292 | ||
293 | return NULL; | |
294 | } | |
295 | ||
fc1ac8de VS |
296 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
297 | { | |
298 | u32 val; | |
299 | ||
300 | mutex_lock(&dev_priv->rps.hw_lock); | |
301 | ||
302 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
303 | if (enable) | |
304 | val &= ~FORCE_DDR_HIGH_FREQ; | |
305 | else | |
306 | val |= FORCE_DDR_HIGH_FREQ; | |
307 | val &= ~FORCE_DDR_LOW_FREQ; | |
308 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
309 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
310 | ||
311 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
312 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
313 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
314 | ||
315 | mutex_unlock(&dev_priv->rps.hw_lock); | |
316 | } | |
317 | ||
cfb41411 VS |
318 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
319 | { | |
320 | u32 val; | |
321 | ||
322 | mutex_lock(&dev_priv->rps.hw_lock); | |
323 | ||
324 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
325 | if (enable) | |
326 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
327 | else | |
328 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
329 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
330 | ||
331 | mutex_unlock(&dev_priv->rps.hw_lock); | |
332 | } | |
333 | ||
f4998963 VS |
334 | #define FW_WM(value, plane) \ |
335 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
336 | ||
11a85d6a | 337 | static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 338 | { |
11a85d6a | 339 | bool was_enabled; |
5209b1f4 | 340 | u32 val; |
b445e3b0 | 341 | |
920a14b2 | 342 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
11a85d6a | 343 | was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
5209b1f4 | 344 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
a7a6c498 | 345 | POSTING_READ(FW_BLC_SELF_VLV); |
c0f86832 | 346 | } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { |
11a85d6a | 347 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 | 348 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
a7a6c498 | 349 | POSTING_READ(FW_BLC_SELF); |
9b1e14f4 | 350 | } else if (IS_PINEVIEW(dev_priv)) { |
11a85d6a VS |
351 | val = I915_READ(DSPFW3); |
352 | was_enabled = val & PINEVIEW_SELF_REFRESH_EN; | |
353 | if (enable) | |
354 | val |= PINEVIEW_SELF_REFRESH_EN; | |
355 | else | |
356 | val &= ~PINEVIEW_SELF_REFRESH_EN; | |
5209b1f4 | 357 | I915_WRITE(DSPFW3, val); |
a7a6c498 | 358 | POSTING_READ(DSPFW3); |
50a0bc90 | 359 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { |
11a85d6a | 360 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 ID |
361 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
362 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
363 | I915_WRITE(FW_BLC_SELF, val); | |
a7a6c498 | 364 | POSTING_READ(FW_BLC_SELF); |
50a0bc90 | 365 | } else if (IS_I915GM(dev_priv)) { |
acb91359 VS |
366 | /* |
367 | * FIXME can't find a bit like this for 915G, and | |
368 | * and yet it does have the related watermark in | |
369 | * FW_BLC_SELF. What's going on? | |
370 | */ | |
11a85d6a | 371 | was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
5209b1f4 ID |
372 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
373 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
374 | I915_WRITE(INSTPM, val); | |
a7a6c498 | 375 | POSTING_READ(INSTPM); |
5209b1f4 | 376 | } else { |
11a85d6a | 377 | return false; |
5209b1f4 | 378 | } |
b445e3b0 | 379 | |
1489bba8 VS |
380 | trace_intel_memory_cxsr(dev_priv, was_enabled, enable); |
381 | ||
11a85d6a VS |
382 | DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n", |
383 | enableddisabled(enable), | |
384 | enableddisabled(was_enabled)); | |
385 | ||
386 | return was_enabled; | |
b445e3b0 ED |
387 | } |
388 | ||
62571fc3 VS |
389 | /** |
390 | * intel_set_memory_cxsr - Configure CxSR state | |
391 | * @dev_priv: i915 device | |
392 | * @enable: Allow vs. disallow CxSR | |
393 | * | |
394 | * Allow or disallow the system to enter a special CxSR | |
395 | * (C-state self refresh) state. What typically happens in CxSR mode | |
396 | * is that several display FIFOs may get combined into a single larger | |
397 | * FIFO for a particular plane (so called max FIFO mode) to allow the | |
398 | * system to defer memory fetches longer, and the memory will enter | |
399 | * self refresh. | |
400 | * | |
401 | * Note that enabling CxSR does not guarantee that the system enter | |
402 | * this special mode, nor does it guarantee that the system stays | |
403 | * in that mode once entered. So this just allows/disallows the system | |
404 | * to autonomously utilize the CxSR mode. Other factors such as core | |
405 | * C-states will affect when/if the system actually enters/exits the | |
406 | * CxSR mode. | |
407 | * | |
408 | * Note that on VLV/CHV this actually only controls the max FIFO mode, | |
409 | * and the system is free to enter/exit memory self refresh at any time | |
410 | * even when the use of CxSR has been disallowed. | |
411 | * | |
412 | * While the system is actually in the CxSR/max FIFO mode, some plane | |
413 | * control registers will not get latched on vblank. Thus in order to | |
414 | * guarantee the system will respond to changes in the plane registers | |
415 | * we must always disallow CxSR prior to making changes to those registers. | |
416 | * Unfortunately the system will re-evaluate the CxSR conditions at | |
417 | * frame start which happens after vblank start (which is when the plane | |
418 | * registers would get latched), so we can't proceed with the plane update | |
419 | * during the same frame where we disallowed CxSR. | |
420 | * | |
421 | * Certain platforms also have a deeper HPLL SR mode. Fortunately the | |
422 | * HPLL SR mode depends on CxSR itself, so we don't have to hand hold | |
423 | * the hardware w.r.t. HPLL SR when writing to plane registers. | |
424 | * Disallowing just CxSR is sufficient. | |
425 | */ | |
11a85d6a | 426 | bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
3d90e649 | 427 | { |
11a85d6a VS |
428 | bool ret; |
429 | ||
3d90e649 | 430 | mutex_lock(&dev_priv->wm.wm_mutex); |
11a85d6a | 431 | ret = _intel_set_memory_cxsr(dev_priv, enable); |
3d90e649 VS |
432 | dev_priv->wm.vlv.cxsr = enable; |
433 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
11a85d6a VS |
434 | |
435 | return ret; | |
3d90e649 | 436 | } |
fc1ac8de | 437 | |
b445e3b0 ED |
438 | /* |
439 | * Latency for FIFO fetches is dependent on several factors: | |
440 | * - memory configuration (speed, channels) | |
441 | * - chipset | |
442 | * - current MCH state | |
443 | * It can be fairly high in some situations, so here we assume a fairly | |
444 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
445 | * set this value too high, the FIFO will fetch frequently to stay full) | |
446 | * and power consumption (set it too low to save power and we might see | |
447 | * FIFO underruns and display "flicker"). | |
448 | * | |
449 | * A value of 5us seems to be a good balance; safe for very low end | |
450 | * platforms but not overly aggressive on lower latency configs. | |
451 | */ | |
5aef6003 | 452 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 453 | |
b5004720 VS |
454 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
455 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
456 | ||
814e7f0b | 457 | static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) |
b5004720 | 458 | { |
814e7f0b | 459 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 460 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b | 461 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
f07d43d2 VS |
462 | enum pipe pipe = crtc->pipe; |
463 | int sprite0_start, sprite1_start; | |
49845a23 | 464 | |
f07d43d2 | 465 | switch (pipe) { |
b5004720 VS |
466 | uint32_t dsparb, dsparb2, dsparb3; |
467 | case PIPE_A: | |
468 | dsparb = I915_READ(DSPARB); | |
469 | dsparb2 = I915_READ(DSPARB2); | |
470 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
471 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
472 | break; | |
473 | case PIPE_B: | |
474 | dsparb = I915_READ(DSPARB); | |
475 | dsparb2 = I915_READ(DSPARB2); | |
476 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
477 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
478 | break; | |
479 | case PIPE_C: | |
480 | dsparb2 = I915_READ(DSPARB2); | |
481 | dsparb3 = I915_READ(DSPARB3); | |
482 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
483 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
484 | break; | |
485 | default: | |
f07d43d2 VS |
486 | MISSING_CASE(pipe); |
487 | return; | |
b5004720 VS |
488 | } |
489 | ||
f07d43d2 VS |
490 | fifo_state->plane[PLANE_PRIMARY] = sprite0_start; |
491 | fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start; | |
492 | fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start; | |
493 | fifo_state->plane[PLANE_CURSOR] = 63; | |
b5004720 VS |
494 | } |
495 | ||
ef0f5e93 | 496 | static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 497 | { |
b445e3b0 ED |
498 | uint32_t dsparb = I915_READ(DSPARB); |
499 | int size; | |
500 | ||
501 | size = dsparb & 0x7f; | |
502 | if (plane) | |
503 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
504 | ||
505 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
506 | plane ? "B" : "A", size); | |
507 | ||
508 | return size; | |
509 | } | |
510 | ||
ef0f5e93 | 511 | static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 512 | { |
b445e3b0 ED |
513 | uint32_t dsparb = I915_READ(DSPARB); |
514 | int size; | |
515 | ||
516 | size = dsparb & 0x1ff; | |
517 | if (plane) | |
518 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
519 | size >>= 1; /* Convert to cachelines */ | |
520 | ||
521 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
522 | plane ? "B" : "A", size); | |
523 | ||
524 | return size; | |
525 | } | |
526 | ||
ef0f5e93 | 527 | static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 528 | { |
b445e3b0 ED |
529 | uint32_t dsparb = I915_READ(DSPARB); |
530 | int size; | |
531 | ||
532 | size = dsparb & 0x7f; | |
533 | size >>= 2; /* Convert to cachelines */ | |
534 | ||
535 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
536 | plane ? "B" : "A", | |
537 | size); | |
538 | ||
539 | return size; | |
540 | } | |
541 | ||
b445e3b0 ED |
542 | /* Pineview has different values for various configs */ |
543 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
544 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
545 | .max_wm = PINEVIEW_MAX_WM, | |
546 | .default_wm = PINEVIEW_DFT_WM, | |
547 | .guard_size = PINEVIEW_GUARD_WM, | |
548 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
549 | }; |
550 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
551 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
552 | .max_wm = PINEVIEW_MAX_WM, | |
553 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
554 | .guard_size = PINEVIEW_GUARD_WM, | |
555 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
556 | }; |
557 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
558 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
559 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
560 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
561 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
562 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
563 | }; |
564 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
565 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
566 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
567 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
568 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
569 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
570 | }; |
571 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
572 | .fifo_size = G4X_FIFO_SIZE, |
573 | .max_wm = G4X_MAX_WM, | |
574 | .default_wm = G4X_MAX_WM, | |
575 | .guard_size = 2, | |
576 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
577 | }; |
578 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
579 | .fifo_size = I965_CURSOR_FIFO, |
580 | .max_wm = I965_CURSOR_MAX_WM, | |
581 | .default_wm = I965_CURSOR_DFT_WM, | |
582 | .guard_size = 2, | |
583 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 | 584 | }; |
b445e3b0 | 585 | static const struct intel_watermark_params i965_cursor_wm_info = { |
e0f0273e VS |
586 | .fifo_size = I965_CURSOR_FIFO, |
587 | .max_wm = I965_CURSOR_MAX_WM, | |
588 | .default_wm = I965_CURSOR_DFT_WM, | |
589 | .guard_size = 2, | |
590 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
591 | }; |
592 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
593 | .fifo_size = I945_FIFO_SIZE, |
594 | .max_wm = I915_MAX_WM, | |
595 | .default_wm = 1, | |
596 | .guard_size = 2, | |
597 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
598 | }; |
599 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
600 | .fifo_size = I915_FIFO_SIZE, |
601 | .max_wm = I915_MAX_WM, | |
602 | .default_wm = 1, | |
603 | .guard_size = 2, | |
604 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 605 | }; |
9d539105 | 606 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
607 | .fifo_size = I855GM_FIFO_SIZE, |
608 | .max_wm = I915_MAX_WM, | |
609 | .default_wm = 1, | |
610 | .guard_size = 2, | |
611 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 612 | }; |
9d539105 VS |
613 | static const struct intel_watermark_params i830_bc_wm_info = { |
614 | .fifo_size = I855GM_FIFO_SIZE, | |
615 | .max_wm = I915_MAX_WM/2, | |
616 | .default_wm = 1, | |
617 | .guard_size = 2, | |
618 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
619 | }; | |
feb56b93 | 620 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
621 | .fifo_size = I830_FIFO_SIZE, |
622 | .max_wm = I915_MAX_WM, | |
623 | .default_wm = 1, | |
624 | .guard_size = 2, | |
625 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
626 | }; |
627 | ||
b445e3b0 ED |
628 | /** |
629 | * intel_calculate_wm - calculate watermark level | |
630 | * @clock_in_khz: pixel clock | |
631 | * @wm: chip FIFO params | |
ac484963 | 632 | * @cpp: bytes per pixel |
b445e3b0 ED |
633 | * @latency_ns: memory latency for the platform |
634 | * | |
635 | * Calculate the watermark level (the level at which the display plane will | |
636 | * start fetching from memory again). Each chip has a different display | |
637 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
638 | * in the correct intel_watermark_params structure. | |
639 | * | |
640 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
641 | * on the pixel size. When it reaches the watermark level, it'll start | |
642 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
643 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
644 | * will occur, and a display engine hang could result. | |
645 | */ | |
646 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
647 | const struct intel_watermark_params *wm, | |
ac484963 | 648 | int fifo_size, int cpp, |
b445e3b0 ED |
649 | unsigned long latency_ns) |
650 | { | |
651 | long entries_required, wm_size; | |
652 | ||
653 | /* | |
654 | * Note: we need to make sure we don't overflow for various clock & | |
655 | * latency values. | |
656 | * clocks go from a few thousand to several hundred thousand. | |
657 | * latency is usually a few thousand | |
658 | */ | |
ac484963 | 659 | entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) / |
b445e3b0 ED |
660 | 1000; |
661 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
662 | ||
663 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
664 | ||
665 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
666 | ||
667 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
668 | ||
669 | /* Don't promote wm_size to unsigned... */ | |
670 | if (wm_size > (long)wm->max_wm) | |
671 | wm_size = wm->max_wm; | |
672 | if (wm_size <= 0) | |
673 | wm_size = wm->default_wm; | |
d6feb196 VS |
674 | |
675 | /* | |
676 | * Bspec seems to indicate that the value shouldn't be lower than | |
677 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
678 | * Lets go for 8 which is the burst size since certain platforms | |
679 | * already use a hardcoded 8 (which is what the spec says should be | |
680 | * done). | |
681 | */ | |
682 | if (wm_size <= 8) | |
683 | wm_size = 8; | |
684 | ||
b445e3b0 ED |
685 | return wm_size; |
686 | } | |
687 | ||
6d5019b6 VS |
688 | static int intel_wm_num_levels(struct drm_i915_private *dev_priv) |
689 | { | |
690 | return dev_priv->wm.max_level + 1; | |
691 | } | |
692 | ||
24304d81 VS |
693 | static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, |
694 | const struct intel_plane_state *plane_state) | |
695 | { | |
696 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
697 | ||
698 | /* FIXME check the 'enable' instead */ | |
699 | if (!crtc_state->base.active) | |
700 | return false; | |
701 | ||
702 | /* | |
703 | * Treat cursor with fb as always visible since cursor updates | |
704 | * can happen faster than the vrefresh rate, and the current | |
705 | * watermark code doesn't handle that correctly. Cursor updates | |
706 | * which set/clear the fb or change the cursor size are going | |
707 | * to get throttled by intel_legacy_cursor_update() to work | |
708 | * around this problem with the watermark code. | |
709 | */ | |
710 | if (plane->id == PLANE_CURSOR) | |
711 | return plane_state->base.fb != NULL; | |
712 | else | |
713 | return plane_state->base.visible; | |
714 | } | |
715 | ||
ffc7a76b | 716 | static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv) |
b445e3b0 | 717 | { |
efc2611e | 718 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 719 | |
ffc7a76b | 720 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
efc2611e | 721 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
722 | if (enabled) |
723 | return NULL; | |
724 | enabled = crtc; | |
725 | } | |
726 | } | |
727 | ||
728 | return enabled; | |
729 | } | |
730 | ||
432081bc | 731 | static void pineview_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 732 | { |
ffc7a76b | 733 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 734 | struct intel_crtc *crtc; |
b445e3b0 ED |
735 | const struct cxsr_latency *latency; |
736 | u32 reg; | |
737 | unsigned long wm; | |
738 | ||
50a0bc90 TU |
739 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
740 | dev_priv->is_ddr3, | |
741 | dev_priv->fsb_freq, | |
742 | dev_priv->mem_freq); | |
b445e3b0 ED |
743 | if (!latency) { |
744 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 745 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
746 | return; |
747 | } | |
748 | ||
ffc7a76b | 749 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 | 750 | if (crtc) { |
efc2611e VS |
751 | const struct drm_display_mode *adjusted_mode = |
752 | &crtc->config->base.adjusted_mode; | |
753 | const struct drm_framebuffer *fb = | |
754 | crtc->base.primary->state->fb; | |
353c8598 | 755 | int cpp = fb->format->cpp[0]; |
7c5f93b0 | 756 | int clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
757 | |
758 | /* Display SR */ | |
759 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
760 | pineview_display_wm.fifo_size, | |
ac484963 | 761 | cpp, latency->display_sr); |
b445e3b0 ED |
762 | reg = I915_READ(DSPFW1); |
763 | reg &= ~DSPFW_SR_MASK; | |
f4998963 | 764 | reg |= FW_WM(wm, SR); |
b445e3b0 ED |
765 | I915_WRITE(DSPFW1, reg); |
766 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
767 | ||
768 | /* cursor SR */ | |
769 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
770 | pineview_display_wm.fifo_size, | |
99834b14 | 771 | 4, latency->cursor_sr); |
b445e3b0 ED |
772 | reg = I915_READ(DSPFW3); |
773 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
f4998963 | 774 | reg |= FW_WM(wm, CURSOR_SR); |
b445e3b0 ED |
775 | I915_WRITE(DSPFW3, reg); |
776 | ||
777 | /* Display HPLL off SR */ | |
778 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
779 | pineview_display_hplloff_wm.fifo_size, | |
ac484963 | 780 | cpp, latency->display_hpll_disable); |
b445e3b0 ED |
781 | reg = I915_READ(DSPFW3); |
782 | reg &= ~DSPFW_HPLL_SR_MASK; | |
f4998963 | 783 | reg |= FW_WM(wm, HPLL_SR); |
b445e3b0 ED |
784 | I915_WRITE(DSPFW3, reg); |
785 | ||
786 | /* cursor HPLL off SR */ | |
787 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
788 | pineview_display_hplloff_wm.fifo_size, | |
99834b14 | 789 | 4, latency->cursor_hpll_disable); |
b445e3b0 ED |
790 | reg = I915_READ(DSPFW3); |
791 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
f4998963 | 792 | reg |= FW_WM(wm, HPLL_CURSOR); |
b445e3b0 ED |
793 | I915_WRITE(DSPFW3, reg); |
794 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
795 | ||
5209b1f4 | 796 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 797 | } else { |
5209b1f4 | 798 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
799 | } |
800 | } | |
801 | ||
0f95ff85 VS |
802 | /* |
803 | * Documentation says: | |
804 | * "If the line size is small, the TLB fetches can get in the way of the | |
805 | * data fetches, causing some lag in the pixel data return which is not | |
806 | * accounted for in the above formulas. The following adjustment only | |
807 | * needs to be applied if eight whole lines fit in the buffer at once. | |
808 | * The WM is adjusted upwards by the difference between the FIFO size | |
809 | * and the size of 8 whole lines. This adjustment is always performed | |
810 | * in the actual pixel depth regardless of whether FBC is enabled or not." | |
811 | */ | |
812 | static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp) | |
813 | { | |
814 | int tlb_miss = fifo_size * 64 - width * cpp * 8; | |
815 | ||
816 | return max(0, tlb_miss); | |
817 | } | |
818 | ||
f0ce2310 | 819 | static bool g4x_compute_wm0(struct drm_i915_private *dev_priv, |
b445e3b0 ED |
820 | int plane, |
821 | const struct intel_watermark_params *display, | |
822 | int display_latency_ns, | |
823 | const struct intel_watermark_params *cursor, | |
824 | int cursor_latency_ns, | |
825 | int *plane_wm, | |
826 | int *cursor_wm) | |
827 | { | |
efc2611e | 828 | struct intel_crtc *crtc; |
4fe8590a | 829 | const struct drm_display_mode *adjusted_mode; |
efc2611e | 830 | const struct drm_framebuffer *fb; |
624a0ac3 | 831 | int htotal, plane_width, cursor_width, clock, cpp; |
b445e3b0 | 832 | int line_time_us, line_count; |
0f95ff85 | 833 | int entries; |
b445e3b0 | 834 | |
b91eb5cc | 835 | crtc = intel_get_crtc_for_plane(dev_priv, plane); |
efc2611e | 836 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
837 | *cursor_wm = cursor->guard_size; |
838 | *plane_wm = display->guard_size; | |
839 | return false; | |
840 | } | |
841 | ||
efc2611e VS |
842 | adjusted_mode = &crtc->config->base.adjusted_mode; |
843 | fb = crtc->base.primary->state->fb; | |
241bfc38 | 844 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 845 | htotal = adjusted_mode->crtc_htotal; |
624a0ac3 VS |
846 | plane_width = crtc->config->pipe_src_w; |
847 | cursor_width = crtc->base.cursor->state->crtc_w; | |
353c8598 | 848 | cpp = fb->format->cpp[0]; |
b445e3b0 ED |
849 | |
850 | /* Use the small buffer method to calculate plane watermark */ | |
ac484963 | 851 | entries = ((clock * cpp / 1000) * display_latency_ns) / 1000; |
0f95ff85 | 852 | entries += g4x_tlb_miss_wa(display->fifo_size, plane_width, cpp); |
b445e3b0 ED |
853 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
854 | *plane_wm = entries + display->guard_size; | |
855 | if (*plane_wm > (int)display->max_wm) | |
856 | *plane_wm = display->max_wm; | |
857 | ||
858 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 859 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 860 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
624a0ac3 | 861 | entries = line_count * cursor_width * 4; |
0f95ff85 | 862 | entries += g4x_tlb_miss_wa(cursor->fifo_size, cursor_width, 4); |
b445e3b0 ED |
863 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
864 | *cursor_wm = entries + cursor->guard_size; | |
865 | if (*cursor_wm > (int)cursor->max_wm) | |
866 | *cursor_wm = (int)cursor->max_wm; | |
867 | ||
868 | return true; | |
869 | } | |
870 | ||
871 | /* | |
872 | * Check the wm result. | |
873 | * | |
874 | * If any calculated watermark values is larger than the maximum value that | |
875 | * can be programmed into the associated watermark register, that watermark | |
876 | * must be disabled. | |
877 | */ | |
f0ce2310 | 878 | static bool g4x_check_srwm(struct drm_i915_private *dev_priv, |
b445e3b0 ED |
879 | int display_wm, int cursor_wm, |
880 | const struct intel_watermark_params *display, | |
881 | const struct intel_watermark_params *cursor) | |
882 | { | |
883 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
884 | display_wm, cursor_wm); | |
885 | ||
886 | if (display_wm > display->max_wm) { | |
ae9400ca | 887 | DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n", |
b445e3b0 ED |
888 | display_wm, display->max_wm); |
889 | return false; | |
890 | } | |
891 | ||
892 | if (cursor_wm > cursor->max_wm) { | |
ae9400ca | 893 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n", |
b445e3b0 ED |
894 | cursor_wm, cursor->max_wm); |
895 | return false; | |
896 | } | |
897 | ||
898 | if (!(display_wm || cursor_wm)) { | |
899 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
900 | return false; | |
901 | } | |
902 | ||
903 | return true; | |
904 | } | |
905 | ||
f0ce2310 | 906 | static bool g4x_compute_srwm(struct drm_i915_private *dev_priv, |
b445e3b0 ED |
907 | int plane, |
908 | int latency_ns, | |
909 | const struct intel_watermark_params *display, | |
910 | const struct intel_watermark_params *cursor, | |
911 | int *display_wm, int *cursor_wm) | |
912 | { | |
efc2611e | 913 | struct intel_crtc *crtc; |
4fe8590a | 914 | const struct drm_display_mode *adjusted_mode; |
efc2611e | 915 | const struct drm_framebuffer *fb; |
ac484963 | 916 | int hdisplay, htotal, cpp, clock; |
b445e3b0 ED |
917 | unsigned long line_time_us; |
918 | int line_count, line_size; | |
919 | int small, large; | |
920 | int entries; | |
921 | ||
922 | if (!latency_ns) { | |
923 | *display_wm = *cursor_wm = 0; | |
924 | return false; | |
925 | } | |
926 | ||
b91eb5cc | 927 | crtc = intel_get_crtc_for_plane(dev_priv, plane); |
efc2611e VS |
928 | adjusted_mode = &crtc->config->base.adjusted_mode; |
929 | fb = crtc->base.primary->state->fb; | |
241bfc38 | 930 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 931 | htotal = adjusted_mode->crtc_htotal; |
efc2611e | 932 | hdisplay = crtc->config->pipe_src_w; |
353c8598 | 933 | cpp = fb->format->cpp[0]; |
b445e3b0 | 934 | |
922044c9 | 935 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 936 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
ac484963 | 937 | line_size = hdisplay * cpp; |
b445e3b0 ED |
938 | |
939 | /* Use the minimum of the small and large buffer method for primary */ | |
ac484963 | 940 | small = ((clock * cpp / 1000) * latency_ns) / 1000; |
b445e3b0 ED |
941 | large = line_count * line_size; |
942 | ||
943 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
944 | *display_wm = entries + display->guard_size; | |
945 | ||
946 | /* calculate the self-refresh watermark for display cursor */ | |
99834b14 | 947 | entries = line_count * 4 * crtc->base.cursor->state->crtc_w; |
b445e3b0 ED |
948 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
949 | *cursor_wm = entries + cursor->guard_size; | |
950 | ||
f0ce2310 | 951 | return g4x_check_srwm(dev_priv, |
b445e3b0 ED |
952 | *display_wm, *cursor_wm, |
953 | display, cursor); | |
954 | } | |
955 | ||
15665979 VS |
956 | #define FW_WM_VLV(value, plane) \ |
957 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
958 | ||
50f4caef | 959 | static void vlv_write_wm_values(struct drm_i915_private *dev_priv, |
0018fda1 VS |
960 | const struct vlv_wm_values *wm) |
961 | { | |
50f4caef VS |
962 | enum pipe pipe; |
963 | ||
964 | for_each_pipe(dev_priv, pipe) { | |
c137d660 VS |
965 | trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); |
966 | ||
50f4caef VS |
967 | I915_WRITE(VLV_DDL(pipe), |
968 | (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | | |
969 | (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | | |
970 | (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | | |
971 | (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); | |
972 | } | |
0018fda1 | 973 | |
6fe6a7ff VS |
974 | /* |
975 | * Zero the (unused) WM1 watermarks, and also clear all the | |
976 | * high order bits so that there are no out of bounds values | |
977 | * present in the registers during the reprogramming. | |
978 | */ | |
979 | I915_WRITE(DSPHOWM, 0); | |
980 | I915_WRITE(DSPHOWM1, 0); | |
981 | I915_WRITE(DSPFW4, 0); | |
982 | I915_WRITE(DSPFW5, 0); | |
983 | I915_WRITE(DSPFW6, 0); | |
984 | ||
ae80152d | 985 | I915_WRITE(DSPFW1, |
15665979 | 986 | FW_WM(wm->sr.plane, SR) | |
1b31389c VS |
987 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | |
988 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | | |
989 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); | |
ae80152d | 990 | I915_WRITE(DSPFW2, |
1b31389c VS |
991 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | |
992 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | | |
993 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); | |
ae80152d | 994 | I915_WRITE(DSPFW3, |
15665979 | 995 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
996 | |
997 | if (IS_CHERRYVIEW(dev_priv)) { | |
998 | I915_WRITE(DSPFW7_CHV, | |
1b31389c VS |
999 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
1000 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 1001 | I915_WRITE(DSPFW8_CHV, |
1b31389c VS |
1002 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | |
1003 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); | |
ae80152d | 1004 | I915_WRITE(DSPFW9_CHV, |
1b31389c VS |
1005 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | |
1006 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); | |
ae80152d | 1007 | I915_WRITE(DSPHOWM, |
15665979 | 1008 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
1009 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | |
1010 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | | |
1011 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | | |
1012 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | | |
1013 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
1014 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
1015 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
1016 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
1017 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
1018 | } else { |
1019 | I915_WRITE(DSPFW7, | |
1b31389c VS |
1020 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
1021 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 1022 | I915_WRITE(DSPHOWM, |
15665979 | 1023 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
1024 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | |
1025 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
1026 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
1027 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
1028 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
1029 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
1030 | } |
1031 | ||
1032 | POSTING_READ(DSPFW1); | |
0018fda1 VS |
1033 | } |
1034 | ||
15665979 VS |
1035 | #undef FW_WM_VLV |
1036 | ||
262cd2e1 VS |
1037 | /* latency must be in 0.1us units. */ |
1038 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, | |
1039 | unsigned int pipe_htotal, | |
1040 | unsigned int horiz_pixels, | |
ac484963 | 1041 | unsigned int cpp, |
262cd2e1 VS |
1042 | unsigned int latency) |
1043 | { | |
1044 | unsigned int ret; | |
1045 | ||
1046 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); | |
ac484963 | 1047 | ret = (ret + 1) * horiz_pixels * cpp; |
262cd2e1 VS |
1048 | ret = DIV_ROUND_UP(ret, 64); |
1049 | ||
1050 | return ret; | |
1051 | } | |
1052 | ||
bb726519 | 1053 | static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv) |
262cd2e1 | 1054 | { |
262cd2e1 VS |
1055 | /* all latencies in usec */ |
1056 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; | |
1057 | ||
58590c14 VS |
1058 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
1059 | ||
262cd2e1 VS |
1060 | if (IS_CHERRYVIEW(dev_priv)) { |
1061 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; | |
1062 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; | |
58590c14 VS |
1063 | |
1064 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; | |
262cd2e1 VS |
1065 | } |
1066 | } | |
1067 | ||
e339d67e VS |
1068 | static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, |
1069 | const struct intel_plane_state *plane_state, | |
262cd2e1 VS |
1070 | int level) |
1071 | { | |
e339d67e | 1072 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
262cd2e1 | 1073 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
e339d67e VS |
1074 | const struct drm_display_mode *adjusted_mode = |
1075 | &crtc_state->base.adjusted_mode; | |
ac484963 | 1076 | int clock, htotal, cpp, width, wm; |
262cd2e1 VS |
1077 | |
1078 | if (dev_priv->wm.pri_latency[level] == 0) | |
1079 | return USHRT_MAX; | |
1080 | ||
a07102f1 | 1081 | if (!intel_wm_plane_visible(crtc_state, plane_state)) |
262cd2e1 VS |
1082 | return 0; |
1083 | ||
ef426c10 | 1084 | cpp = plane_state->base.fb->format->cpp[0]; |
e339d67e VS |
1085 | clock = adjusted_mode->crtc_clock; |
1086 | htotal = adjusted_mode->crtc_htotal; | |
1087 | width = crtc_state->pipe_src_w; | |
262cd2e1 VS |
1088 | if (WARN_ON(htotal == 0)) |
1089 | htotal = 1; | |
1090 | ||
709f3fc9 | 1091 | if (plane->id == PLANE_CURSOR) { |
262cd2e1 VS |
1092 | /* |
1093 | * FIXME the formula gives values that are | |
1094 | * too big for the cursor FIFO, and hence we | |
1095 | * would never be able to use cursors. For | |
1096 | * now just hardcode the watermark. | |
1097 | */ | |
1098 | wm = 63; | |
1099 | } else { | |
ac484963 | 1100 | wm = vlv_wm_method2(clock, htotal, width, cpp, |
262cd2e1 VS |
1101 | dev_priv->wm.pri_latency[level] * 10); |
1102 | } | |
1103 | ||
1104 | return min_t(int, wm, USHRT_MAX); | |
1105 | } | |
1106 | ||
1a10ae6b VS |
1107 | static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes) |
1108 | { | |
1109 | return (active_planes & (BIT(PLANE_SPRITE0) | | |
1110 | BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1); | |
1111 | } | |
1112 | ||
5012e604 | 1113 | static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) |
54f1b6e1 | 1114 | { |
855c79f5 | 1115 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
114d7dc0 | 1116 | const struct g4x_pipe_wm *raw = |
5012e604 | 1117 | &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; |
814e7f0b | 1118 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
5012e604 VS |
1119 | unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); |
1120 | int num_active_planes = hweight32(active_planes); | |
1121 | const int fifo_size = 511; | |
54f1b6e1 | 1122 | int fifo_extra, fifo_left = fifo_size; |
1a10ae6b | 1123 | int sprite0_fifo_extra = 0; |
5012e604 VS |
1124 | unsigned int total_rate; |
1125 | enum plane_id plane_id; | |
54f1b6e1 | 1126 | |
1a10ae6b VS |
1127 | /* |
1128 | * When enabling sprite0 after sprite1 has already been enabled | |
1129 | * we tend to get an underrun unless sprite0 already has some | |
1130 | * FIFO space allcoated. Hence we always allocate at least one | |
1131 | * cacheline for sprite0 whenever sprite1 is enabled. | |
1132 | * | |
1133 | * All other plane enable sequences appear immune to this problem. | |
1134 | */ | |
1135 | if (vlv_need_sprite0_fifo_workaround(active_planes)) | |
1136 | sprite0_fifo_extra = 1; | |
1137 | ||
5012e604 VS |
1138 | total_rate = raw->plane[PLANE_PRIMARY] + |
1139 | raw->plane[PLANE_SPRITE0] + | |
1a10ae6b VS |
1140 | raw->plane[PLANE_SPRITE1] + |
1141 | sprite0_fifo_extra; | |
54f1b6e1 | 1142 | |
5012e604 VS |
1143 | if (total_rate > fifo_size) |
1144 | return -EINVAL; | |
54f1b6e1 | 1145 | |
5012e604 VS |
1146 | if (total_rate == 0) |
1147 | total_rate = 1; | |
54f1b6e1 | 1148 | |
5012e604 | 1149 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1150 | unsigned int rate; |
1151 | ||
5012e604 VS |
1152 | if ((active_planes & BIT(plane_id)) == 0) { |
1153 | fifo_state->plane[plane_id] = 0; | |
54f1b6e1 VS |
1154 | continue; |
1155 | } | |
1156 | ||
5012e604 VS |
1157 | rate = raw->plane[plane_id]; |
1158 | fifo_state->plane[plane_id] = fifo_size * rate / total_rate; | |
1159 | fifo_left -= fifo_state->plane[plane_id]; | |
54f1b6e1 VS |
1160 | } |
1161 | ||
1a10ae6b VS |
1162 | fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra; |
1163 | fifo_left -= sprite0_fifo_extra; | |
1164 | ||
5012e604 VS |
1165 | fifo_state->plane[PLANE_CURSOR] = 63; |
1166 | ||
1167 | fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1); | |
54f1b6e1 VS |
1168 | |
1169 | /* spread the remainder evenly */ | |
5012e604 | 1170 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1171 | int plane_extra; |
1172 | ||
1173 | if (fifo_left == 0) | |
1174 | break; | |
1175 | ||
5012e604 | 1176 | if ((active_planes & BIT(plane_id)) == 0) |
54f1b6e1 VS |
1177 | continue; |
1178 | ||
1179 | plane_extra = min(fifo_extra, fifo_left); | |
5012e604 | 1180 | fifo_state->plane[plane_id] += plane_extra; |
54f1b6e1 VS |
1181 | fifo_left -= plane_extra; |
1182 | } | |
1183 | ||
5012e604 VS |
1184 | WARN_ON(active_planes != 0 && fifo_left != 0); |
1185 | ||
1186 | /* give it all to the first plane if none are active */ | |
1187 | if (active_planes == 0) { | |
1188 | WARN_ON(fifo_left != fifo_size); | |
1189 | fifo_state->plane[PLANE_PRIMARY] = fifo_left; | |
1190 | } | |
1191 | ||
1192 | return 0; | |
54f1b6e1 VS |
1193 | } |
1194 | ||
ff32c54e VS |
1195 | /* mark all levels starting from 'level' as invalid */ |
1196 | static void vlv_invalidate_wms(struct intel_crtc *crtc, | |
1197 | struct vlv_wm_state *wm_state, int level) | |
1198 | { | |
1199 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1200 | ||
6d5019b6 | 1201 | for (; level < intel_wm_num_levels(dev_priv); level++) { |
ff32c54e VS |
1202 | enum plane_id plane_id; |
1203 | ||
1204 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1205 | wm_state->wm[level].plane[plane_id] = USHRT_MAX; | |
1206 | ||
1207 | wm_state->sr[level].cursor = USHRT_MAX; | |
1208 | wm_state->sr[level].plane = USHRT_MAX; | |
1209 | } | |
1210 | } | |
1211 | ||
26cca0e5 VS |
1212 | static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) |
1213 | { | |
1214 | if (wm > fifo_size) | |
1215 | return USHRT_MAX; | |
1216 | else | |
1217 | return fifo_size - wm; | |
1218 | } | |
1219 | ||
ff32c54e VS |
1220 | /* |
1221 | * Starting from 'level' set all higher | |
1222 | * levels to 'value' in the "raw" watermarks. | |
1223 | */ | |
236c48e6 | 1224 | static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state, |
ff32c54e | 1225 | int level, enum plane_id plane_id, u16 value) |
262cd2e1 | 1226 | { |
ff32c54e | 1227 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
6d5019b6 | 1228 | int num_levels = intel_wm_num_levels(dev_priv); |
236c48e6 | 1229 | bool dirty = false; |
262cd2e1 | 1230 | |
ff32c54e | 1231 | for (; level < num_levels; level++) { |
114d7dc0 | 1232 | struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
262cd2e1 | 1233 | |
236c48e6 | 1234 | dirty |= raw->plane[plane_id] != value; |
ff32c54e | 1235 | raw->plane[plane_id] = value; |
262cd2e1 | 1236 | } |
236c48e6 VS |
1237 | |
1238 | return dirty; | |
262cd2e1 VS |
1239 | } |
1240 | ||
77d14ee4 VS |
1241 | static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, |
1242 | const struct intel_plane_state *plane_state) | |
262cd2e1 | 1243 | { |
ff32c54e VS |
1244 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
1245 | enum plane_id plane_id = plane->id; | |
6d5019b6 | 1246 | int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); |
262cd2e1 | 1247 | int level; |
236c48e6 | 1248 | bool dirty = false; |
262cd2e1 | 1249 | |
a07102f1 | 1250 | if (!intel_wm_plane_visible(crtc_state, plane_state)) { |
236c48e6 VS |
1251 | dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0); |
1252 | goto out; | |
ff32c54e | 1253 | } |
262cd2e1 | 1254 | |
ff32c54e | 1255 | for (level = 0; level < num_levels; level++) { |
114d7dc0 | 1256 | struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
ff32c54e VS |
1257 | int wm = vlv_compute_wm_level(crtc_state, plane_state, level); |
1258 | int max_wm = plane_id == PLANE_CURSOR ? 63 : 511; | |
262cd2e1 | 1259 | |
ff32c54e VS |
1260 | if (wm > max_wm) |
1261 | break; | |
262cd2e1 | 1262 | |
236c48e6 | 1263 | dirty |= raw->plane[plane_id] != wm; |
ff32c54e VS |
1264 | raw->plane[plane_id] = wm; |
1265 | } | |
262cd2e1 | 1266 | |
ff32c54e | 1267 | /* mark all higher levels as invalid */ |
236c48e6 | 1268 | dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); |
262cd2e1 | 1269 | |
236c48e6 VS |
1270 | out: |
1271 | if (dirty) | |
57a6528a | 1272 | DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n", |
236c48e6 VS |
1273 | plane->base.name, |
1274 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], | |
1275 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], | |
1276 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); | |
1277 | ||
1278 | return dirty; | |
ff32c54e | 1279 | } |
262cd2e1 | 1280 | |
77d14ee4 VS |
1281 | static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, |
1282 | enum plane_id plane_id, int level) | |
ff32c54e | 1283 | { |
114d7dc0 | 1284 | const struct g4x_pipe_wm *raw = |
ff32c54e VS |
1285 | &crtc_state->wm.vlv.raw[level]; |
1286 | const struct vlv_fifo_state *fifo_state = | |
1287 | &crtc_state->wm.vlv.fifo_state; | |
262cd2e1 | 1288 | |
ff32c54e VS |
1289 | return raw->plane[plane_id] <= fifo_state->plane[plane_id]; |
1290 | } | |
262cd2e1 | 1291 | |
77d14ee4 | 1292 | static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level) |
ff32c54e | 1293 | { |
77d14ee4 VS |
1294 | return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && |
1295 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && | |
1296 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) && | |
1297 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); | |
ff32c54e VS |
1298 | } |
1299 | ||
1300 | static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) | |
1301 | { | |
1302 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1303 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1304 | struct intel_atomic_state *state = | |
1305 | to_intel_atomic_state(crtc_state->base.state); | |
1306 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
1307 | const struct vlv_fifo_state *fifo_state = | |
1308 | &crtc_state->wm.vlv.fifo_state; | |
1309 | int num_active_planes = hweight32(crtc_state->active_planes & | |
1310 | ~BIT(PLANE_CURSOR)); | |
236c48e6 | 1311 | bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); |
ff32c54e VS |
1312 | struct intel_plane_state *plane_state; |
1313 | struct intel_plane *plane; | |
1314 | enum plane_id plane_id; | |
1315 | int level, ret, i; | |
236c48e6 | 1316 | unsigned int dirty = 0; |
ff32c54e VS |
1317 | |
1318 | for_each_intel_plane_in_state(state, plane, plane_state, i) { | |
1319 | const struct intel_plane_state *old_plane_state = | |
1320 | to_intel_plane_state(plane->base.state); | |
1321 | ||
1322 | if (plane_state->base.crtc != &crtc->base && | |
1323 | old_plane_state->base.crtc != &crtc->base) | |
1324 | continue; | |
262cd2e1 | 1325 | |
77d14ee4 | 1326 | if (vlv_raw_plane_wm_compute(crtc_state, plane_state)) |
236c48e6 VS |
1327 | dirty |= BIT(plane->id); |
1328 | } | |
1329 | ||
1330 | /* | |
1331 | * DSPARB registers may have been reset due to the | |
1332 | * power well being turned off. Make sure we restore | |
1333 | * them to a consistent state even if no primary/sprite | |
1334 | * planes are initially active. | |
1335 | */ | |
1336 | if (needs_modeset) | |
1337 | crtc_state->fifo_changed = true; | |
1338 | ||
1339 | if (!dirty) | |
1340 | return 0; | |
1341 | ||
1342 | /* cursor changes don't warrant a FIFO recompute */ | |
1343 | if (dirty & ~BIT(PLANE_CURSOR)) { | |
1344 | const struct intel_crtc_state *old_crtc_state = | |
1345 | to_intel_crtc_state(crtc->base.state); | |
1346 | const struct vlv_fifo_state *old_fifo_state = | |
1347 | &old_crtc_state->wm.vlv.fifo_state; | |
1348 | ||
1349 | ret = vlv_compute_fifo(crtc_state); | |
1350 | if (ret) | |
1351 | return ret; | |
1352 | ||
1353 | if (needs_modeset || | |
1354 | memcmp(old_fifo_state, fifo_state, | |
1355 | sizeof(*fifo_state)) != 0) | |
1356 | crtc_state->fifo_changed = true; | |
5012e604 | 1357 | } |
262cd2e1 | 1358 | |
ff32c54e | 1359 | /* initially allow all levels */ |
6d5019b6 | 1360 | wm_state->num_levels = intel_wm_num_levels(dev_priv); |
ff32c54e VS |
1361 | /* |
1362 | * Note that enabling cxsr with no primary/sprite planes | |
1363 | * enabled can wedge the pipe. Hence we only allow cxsr | |
1364 | * with exactly one enabled primary/sprite plane. | |
1365 | */ | |
5eeb798b | 1366 | wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; |
ff32c54e | 1367 | |
5012e604 | 1368 | for (level = 0; level < wm_state->num_levels; level++) { |
114d7dc0 | 1369 | const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
ff32c54e | 1370 | const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; |
5012e604 | 1371 | |
77d14ee4 | 1372 | if (!vlv_raw_crtc_wm_is_valid(crtc_state, level)) |
ff32c54e | 1373 | break; |
5012e604 | 1374 | |
ff32c54e VS |
1375 | for_each_plane_id_on_crtc(crtc, plane_id) { |
1376 | wm_state->wm[level].plane[plane_id] = | |
1377 | vlv_invert_wm_value(raw->plane[plane_id], | |
1378 | fifo_state->plane[plane_id]); | |
1379 | } | |
1380 | ||
1381 | wm_state->sr[level].plane = | |
1382 | vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY], | |
5012e604 | 1383 | raw->plane[PLANE_SPRITE0], |
ff32c54e VS |
1384 | raw->plane[PLANE_SPRITE1]), |
1385 | sr_fifo_size); | |
262cd2e1 | 1386 | |
ff32c54e VS |
1387 | wm_state->sr[level].cursor = |
1388 | vlv_invert_wm_value(raw->plane[PLANE_CURSOR], | |
1389 | 63); | |
262cd2e1 VS |
1390 | } |
1391 | ||
ff32c54e VS |
1392 | if (level == 0) |
1393 | return -EINVAL; | |
1394 | ||
1395 | /* limit to only levels we can actually handle */ | |
1396 | wm_state->num_levels = level; | |
1397 | ||
1398 | /* invalidate the higher levels */ | |
1399 | vlv_invalidate_wms(crtc, wm_state, level); | |
1400 | ||
1401 | return 0; | |
262cd2e1 VS |
1402 | } |
1403 | ||
54f1b6e1 VS |
1404 | #define VLV_FIFO(plane, value) \ |
1405 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) | |
1406 | ||
ff32c54e VS |
1407 | static void vlv_atomic_update_fifo(struct intel_atomic_state *state, |
1408 | struct intel_crtc_state *crtc_state) | |
54f1b6e1 | 1409 | { |
814e7f0b | 1410 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 1411 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b VS |
1412 | const struct vlv_fifo_state *fifo_state = |
1413 | &crtc_state->wm.vlv.fifo_state; | |
f07d43d2 | 1414 | int sprite0_start, sprite1_start, fifo_size; |
54f1b6e1 | 1415 | |
236c48e6 VS |
1416 | if (!crtc_state->fifo_changed) |
1417 | return; | |
1418 | ||
f07d43d2 VS |
1419 | sprite0_start = fifo_state->plane[PLANE_PRIMARY]; |
1420 | sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start; | |
1421 | fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start; | |
54f1b6e1 | 1422 | |
f07d43d2 VS |
1423 | WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63); |
1424 | WARN_ON(fifo_size != 511); | |
54f1b6e1 | 1425 | |
c137d660 VS |
1426 | trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size); |
1427 | ||
44e921d4 VS |
1428 | /* |
1429 | * uncore.lock serves a double purpose here. It allows us to | |
1430 | * use the less expensive I915_{READ,WRITE}_FW() functions, and | |
1431 | * it protects the DSPARB registers from getting clobbered by | |
1432 | * parallel updates from multiple pipes. | |
1433 | * | |
1434 | * intel_pipe_update_start() has already disabled interrupts | |
1435 | * for us, so a plain spin_lock() is sufficient here. | |
1436 | */ | |
1437 | spin_lock(&dev_priv->uncore.lock); | |
467a14d9 | 1438 | |
54f1b6e1 VS |
1439 | switch (crtc->pipe) { |
1440 | uint32_t dsparb, dsparb2, dsparb3; | |
1441 | case PIPE_A: | |
44e921d4 VS |
1442 | dsparb = I915_READ_FW(DSPARB); |
1443 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1444 | |
1445 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | | |
1446 | VLV_FIFO(SPRITEB, 0xff)); | |
1447 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | | |
1448 | VLV_FIFO(SPRITEB, sprite1_start)); | |
1449 | ||
1450 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | | |
1451 | VLV_FIFO(SPRITEB_HI, 0x1)); | |
1452 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | | |
1453 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); | |
1454 | ||
44e921d4 VS |
1455 | I915_WRITE_FW(DSPARB, dsparb); |
1456 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1457 | break; |
1458 | case PIPE_B: | |
44e921d4 VS |
1459 | dsparb = I915_READ_FW(DSPARB); |
1460 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1461 | |
1462 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | | |
1463 | VLV_FIFO(SPRITED, 0xff)); | |
1464 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | | |
1465 | VLV_FIFO(SPRITED, sprite1_start)); | |
1466 | ||
1467 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | | |
1468 | VLV_FIFO(SPRITED_HI, 0xff)); | |
1469 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | | |
1470 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); | |
1471 | ||
44e921d4 VS |
1472 | I915_WRITE_FW(DSPARB, dsparb); |
1473 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1474 | break; |
1475 | case PIPE_C: | |
44e921d4 VS |
1476 | dsparb3 = I915_READ_FW(DSPARB3); |
1477 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1478 | |
1479 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | | |
1480 | VLV_FIFO(SPRITEF, 0xff)); | |
1481 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | | |
1482 | VLV_FIFO(SPRITEF, sprite1_start)); | |
1483 | ||
1484 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | | |
1485 | VLV_FIFO(SPRITEF_HI, 0xff)); | |
1486 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | | |
1487 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); | |
1488 | ||
44e921d4 VS |
1489 | I915_WRITE_FW(DSPARB3, dsparb3); |
1490 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1491 | break; |
1492 | default: | |
1493 | break; | |
1494 | } | |
467a14d9 | 1495 | |
44e921d4 | 1496 | POSTING_READ_FW(DSPARB); |
467a14d9 | 1497 | |
44e921d4 | 1498 | spin_unlock(&dev_priv->uncore.lock); |
54f1b6e1 VS |
1499 | } |
1500 | ||
1501 | #undef VLV_FIFO | |
1502 | ||
4841da51 VS |
1503 | static int vlv_compute_intermediate_wm(struct drm_device *dev, |
1504 | struct intel_crtc *crtc, | |
1505 | struct intel_crtc_state *crtc_state) | |
1506 | { | |
1507 | struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate; | |
1508 | const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal; | |
1509 | const struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
1510 | int level; | |
1511 | ||
1512 | intermediate->num_levels = min(optimal->num_levels, active->num_levels); | |
5eeb798b VS |
1513 | intermediate->cxsr = optimal->cxsr && active->cxsr && |
1514 | !crtc_state->disable_cxsr; | |
4841da51 VS |
1515 | |
1516 | for (level = 0; level < intermediate->num_levels; level++) { | |
1517 | enum plane_id plane_id; | |
1518 | ||
1519 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
1520 | intermediate->wm[level].plane[plane_id] = | |
1521 | min(optimal->wm[level].plane[plane_id], | |
1522 | active->wm[level].plane[plane_id]); | |
1523 | } | |
1524 | ||
1525 | intermediate->sr[level].plane = min(optimal->sr[level].plane, | |
1526 | active->sr[level].plane); | |
1527 | intermediate->sr[level].cursor = min(optimal->sr[level].cursor, | |
1528 | active->sr[level].cursor); | |
1529 | } | |
1530 | ||
1531 | vlv_invalidate_wms(crtc, intermediate, level); | |
1532 | ||
1533 | /* | |
1534 | * If our intermediate WM are identical to the final WM, then we can | |
1535 | * omit the post-vblank programming; only update if it's different. | |
1536 | */ | |
5eeb798b VS |
1537 | if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0) |
1538 | crtc_state->wm.need_postvbl_update = true; | |
4841da51 VS |
1539 | |
1540 | return 0; | |
1541 | } | |
1542 | ||
7c951c00 | 1543 | static void vlv_merge_wm(struct drm_i915_private *dev_priv, |
262cd2e1 VS |
1544 | struct vlv_wm_values *wm) |
1545 | { | |
1546 | struct intel_crtc *crtc; | |
1547 | int num_active_crtcs = 0; | |
1548 | ||
7c951c00 | 1549 | wm->level = dev_priv->wm.max_level; |
262cd2e1 VS |
1550 | wm->cxsr = true; |
1551 | ||
7c951c00 | 1552 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 1553 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
1554 | |
1555 | if (!crtc->active) | |
1556 | continue; | |
1557 | ||
1558 | if (!wm_state->cxsr) | |
1559 | wm->cxsr = false; | |
1560 | ||
1561 | num_active_crtcs++; | |
1562 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); | |
1563 | } | |
1564 | ||
1565 | if (num_active_crtcs != 1) | |
1566 | wm->cxsr = false; | |
1567 | ||
6f9c784b VS |
1568 | if (num_active_crtcs > 1) |
1569 | wm->level = VLV_WM_LEVEL_PM2; | |
1570 | ||
7c951c00 | 1571 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 1572 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
1573 | enum pipe pipe = crtc->pipe; |
1574 | ||
262cd2e1 | 1575 | wm->pipe[pipe] = wm_state->wm[wm->level]; |
ff32c54e | 1576 | if (crtc->active && wm->cxsr) |
262cd2e1 VS |
1577 | wm->sr = wm_state->sr[wm->level]; |
1578 | ||
1b31389c VS |
1579 | wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; |
1580 | wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; | |
1581 | wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; | |
1582 | wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; | |
262cd2e1 VS |
1583 | } |
1584 | } | |
1585 | ||
fa292a4b VS |
1586 | static bool is_disabling(int old, int new, int threshold) |
1587 | { | |
1588 | return old >= threshold && new < threshold; | |
1589 | } | |
1590 | ||
1591 | static bool is_enabling(int old, int new, int threshold) | |
1592 | { | |
1593 | return old < threshold && new >= threshold; | |
1594 | } | |
1595 | ||
ff32c54e | 1596 | static void vlv_program_watermarks(struct drm_i915_private *dev_priv) |
262cd2e1 | 1597 | { |
fa292a4b VS |
1598 | struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; |
1599 | struct vlv_wm_values new_wm = {}; | |
262cd2e1 | 1600 | |
fa292a4b | 1601 | vlv_merge_wm(dev_priv, &new_wm); |
262cd2e1 | 1602 | |
ff32c54e | 1603 | if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) |
262cd2e1 VS |
1604 | return; |
1605 | ||
fa292a4b | 1606 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
1607 | chv_set_memory_dvfs(dev_priv, false); |
1608 | ||
fa292a4b | 1609 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
1610 | chv_set_memory_pm5(dev_priv, false); |
1611 | ||
fa292a4b | 1612 | if (is_disabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 1613 | _intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 1614 | |
fa292a4b | 1615 | vlv_write_wm_values(dev_priv, &new_wm); |
262cd2e1 | 1616 | |
fa292a4b | 1617 | if (is_enabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 1618 | _intel_set_memory_cxsr(dev_priv, true); |
262cd2e1 | 1619 | |
fa292a4b | 1620 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
1621 | chv_set_memory_pm5(dev_priv, true); |
1622 | ||
fa292a4b | 1623 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
1624 | chv_set_memory_dvfs(dev_priv, true); |
1625 | ||
fa292a4b | 1626 | *old_wm = new_wm; |
3c2777fd VS |
1627 | } |
1628 | ||
ff32c54e VS |
1629 | static void vlv_initial_watermarks(struct intel_atomic_state *state, |
1630 | struct intel_crtc_state *crtc_state) | |
1631 | { | |
1632 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1633 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1634 | ||
1635 | mutex_lock(&dev_priv->wm.wm_mutex); | |
4841da51 VS |
1636 | crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; |
1637 | vlv_program_watermarks(dev_priv); | |
1638 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1639 | } | |
1640 | ||
1641 | static void vlv_optimize_watermarks(struct intel_atomic_state *state, | |
1642 | struct intel_crtc_state *crtc_state) | |
1643 | { | |
1644 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
1646 | ||
1647 | if (!crtc_state->wm.need_postvbl_update) | |
1648 | return; | |
1649 | ||
1650 | mutex_lock(&dev_priv->wm.wm_mutex); | |
1651 | intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
ff32c54e VS |
1652 | vlv_program_watermarks(dev_priv); |
1653 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1654 | } | |
1655 | ||
ae80152d VS |
1656 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1657 | ||
432081bc | 1658 | static void g4x_update_wm(struct intel_crtc *crtc) |
b445e3b0 | 1659 | { |
b91eb5cc | 1660 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b445e3b0 | 1661 | static const int sr_latency_ns = 12000; |
b445e3b0 ED |
1662 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1663 | int plane_sr, cursor_sr; | |
1664 | unsigned int enabled = 0; | |
9858425c | 1665 | bool cxsr_enabled; |
b445e3b0 | 1666 | |
f0ce2310 | 1667 | if (g4x_compute_wm0(dev_priv, PIPE_A, |
5aef6003 CW |
1668 | &g4x_wm_info, pessimal_latency_ns, |
1669 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1670 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1671 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1672 | |
f0ce2310 | 1673 | if (g4x_compute_wm0(dev_priv, PIPE_B, |
5aef6003 CW |
1674 | &g4x_wm_info, pessimal_latency_ns, |
1675 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1676 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1677 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1678 | |
b445e3b0 | 1679 | if (single_plane_enabled(enabled) && |
f0ce2310 | 1680 | g4x_compute_srwm(dev_priv, ffs(enabled) - 1, |
b445e3b0 ED |
1681 | sr_latency_ns, |
1682 | &g4x_wm_info, | |
1683 | &g4x_cursor_wm_info, | |
52bd02d8 | 1684 | &plane_sr, &cursor_sr)) { |
9858425c | 1685 | cxsr_enabled = true; |
52bd02d8 | 1686 | } else { |
9858425c | 1687 | cxsr_enabled = false; |
5209b1f4 | 1688 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1689 | plane_sr = cursor_sr = 0; |
1690 | } | |
b445e3b0 | 1691 | |
a5043453 VS |
1692 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1693 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1694 | planea_wm, cursora_wm, |
1695 | planeb_wm, cursorb_wm, | |
1696 | plane_sr, cursor_sr); | |
1697 | ||
1698 | I915_WRITE(DSPFW1, | |
f4998963 VS |
1699 | FW_WM(plane_sr, SR) | |
1700 | FW_WM(cursorb_wm, CURSORB) | | |
1701 | FW_WM(planeb_wm, PLANEB) | | |
1702 | FW_WM(planea_wm, PLANEA)); | |
b445e3b0 | 1703 | I915_WRITE(DSPFW2, |
8c919b28 | 1704 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
f4998963 | 1705 | FW_WM(cursora_wm, CURSORA)); |
b445e3b0 ED |
1706 | /* HPLL off in SR has some issues on G4x... disable it */ |
1707 | I915_WRITE(DSPFW3, | |
8c919b28 | 1708 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
f4998963 | 1709 | FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1710 | |
1711 | if (cxsr_enabled) | |
1712 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1713 | } |
1714 | ||
432081bc | 1715 | static void i965_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 1716 | { |
ffc7a76b | 1717 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 1718 | struct intel_crtc *crtc; |
b445e3b0 ED |
1719 | int srwm = 1; |
1720 | int cursor_sr = 16; | |
9858425c | 1721 | bool cxsr_enabled; |
b445e3b0 ED |
1722 | |
1723 | /* Calc sr entries for one plane configs */ | |
ffc7a76b | 1724 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
1725 | if (crtc) { |
1726 | /* self-refresh has much higher latency */ | |
1727 | static const int sr_latency_ns = 12000; | |
efc2611e VS |
1728 | const struct drm_display_mode *adjusted_mode = |
1729 | &crtc->config->base.adjusted_mode; | |
1730 | const struct drm_framebuffer *fb = | |
1731 | crtc->base.primary->state->fb; | |
241bfc38 | 1732 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1733 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e | 1734 | int hdisplay = crtc->config->pipe_src_w; |
353c8598 | 1735 | int cpp = fb->format->cpp[0]; |
b445e3b0 ED |
1736 | unsigned long line_time_us; |
1737 | int entries; | |
1738 | ||
922044c9 | 1739 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1740 | |
1741 | /* Use ns/us then divide to preserve precision */ | |
1742 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
ac484963 | 1743 | cpp * hdisplay; |
b445e3b0 ED |
1744 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1745 | srwm = I965_FIFO_SIZE - entries; | |
1746 | if (srwm < 0) | |
1747 | srwm = 1; | |
1748 | srwm &= 0x1ff; | |
1749 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1750 | entries, srwm); | |
1751 | ||
1752 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
99834b14 | 1753 | 4 * crtc->base.cursor->state->crtc_w; |
b445e3b0 ED |
1754 | entries = DIV_ROUND_UP(entries, |
1755 | i965_cursor_wm_info.cacheline_size); | |
1756 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1757 | (entries + i965_cursor_wm_info.guard_size); | |
1758 | ||
1759 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1760 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1761 | ||
1762 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1763 | "cursor %d\n", srwm, cursor_sr); | |
1764 | ||
9858425c | 1765 | cxsr_enabled = true; |
b445e3b0 | 1766 | } else { |
9858425c | 1767 | cxsr_enabled = false; |
b445e3b0 | 1768 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1769 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1770 | } |
1771 | ||
1772 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1773 | srwm); | |
1774 | ||
1775 | /* 965 has limitations... */ | |
f4998963 VS |
1776 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
1777 | FW_WM(8, CURSORB) | | |
1778 | FW_WM(8, PLANEB) | | |
1779 | FW_WM(8, PLANEA)); | |
1780 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | | |
1781 | FW_WM(8, PLANEC_OLD)); | |
b445e3b0 | 1782 | /* update cursor SR watermark */ |
f4998963 | 1783 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1784 | |
1785 | if (cxsr_enabled) | |
1786 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1787 | } |
1788 | ||
f4998963 VS |
1789 | #undef FW_WM |
1790 | ||
432081bc | 1791 | static void i9xx_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 1792 | { |
ffc7a76b | 1793 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
b445e3b0 ED |
1794 | const struct intel_watermark_params *wm_info; |
1795 | uint32_t fwater_lo; | |
1796 | uint32_t fwater_hi; | |
1797 | int cwm, srwm = 1; | |
1798 | int fifo_size; | |
1799 | int planea_wm, planeb_wm; | |
efc2611e | 1800 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 1801 | |
a9097be4 | 1802 | if (IS_I945GM(dev_priv)) |
b445e3b0 | 1803 | wm_info = &i945_wm_info; |
5db94019 | 1804 | else if (!IS_GEN2(dev_priv)) |
b445e3b0 ED |
1805 | wm_info = &i915_wm_info; |
1806 | else | |
9d539105 | 1807 | wm_info = &i830_a_wm_info; |
b445e3b0 | 1808 | |
ef0f5e93 | 1809 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0); |
b91eb5cc | 1810 | crtc = intel_get_crtc_for_plane(dev_priv, 0); |
efc2611e VS |
1811 | if (intel_crtc_active(crtc)) { |
1812 | const struct drm_display_mode *adjusted_mode = | |
1813 | &crtc->config->base.adjusted_mode; | |
1814 | const struct drm_framebuffer *fb = | |
1815 | crtc->base.primary->state->fb; | |
1816 | int cpp; | |
1817 | ||
5db94019 | 1818 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 1819 | cpp = 4; |
efc2611e | 1820 | else |
353c8598 | 1821 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 1822 | |
241bfc38 | 1823 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1824 | wm_info, fifo_size, cpp, |
5aef6003 | 1825 | pessimal_latency_ns); |
b445e3b0 | 1826 | enabled = crtc; |
9d539105 | 1827 | } else { |
b445e3b0 | 1828 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1829 | if (planea_wm > (long)wm_info->max_wm) |
1830 | planea_wm = wm_info->max_wm; | |
1831 | } | |
1832 | ||
5db94019 | 1833 | if (IS_GEN2(dev_priv)) |
9d539105 | 1834 | wm_info = &i830_bc_wm_info; |
b445e3b0 | 1835 | |
ef0f5e93 | 1836 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1); |
b91eb5cc | 1837 | crtc = intel_get_crtc_for_plane(dev_priv, 1); |
efc2611e VS |
1838 | if (intel_crtc_active(crtc)) { |
1839 | const struct drm_display_mode *adjusted_mode = | |
1840 | &crtc->config->base.adjusted_mode; | |
1841 | const struct drm_framebuffer *fb = | |
1842 | crtc->base.primary->state->fb; | |
1843 | int cpp; | |
1844 | ||
5db94019 | 1845 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 1846 | cpp = 4; |
efc2611e | 1847 | else |
353c8598 | 1848 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 1849 | |
241bfc38 | 1850 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1851 | wm_info, fifo_size, cpp, |
5aef6003 | 1852 | pessimal_latency_ns); |
b445e3b0 ED |
1853 | if (enabled == NULL) |
1854 | enabled = crtc; | |
1855 | else | |
1856 | enabled = NULL; | |
9d539105 | 1857 | } else { |
b445e3b0 | 1858 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1859 | if (planeb_wm > (long)wm_info->max_wm) |
1860 | planeb_wm = wm_info->max_wm; | |
1861 | } | |
b445e3b0 ED |
1862 | |
1863 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1864 | ||
50a0bc90 | 1865 | if (IS_I915GM(dev_priv) && enabled) { |
2ff8fde1 | 1866 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1867 | |
efc2611e | 1868 | obj = intel_fb_obj(enabled->base.primary->state->fb); |
2ab1bc9d DV |
1869 | |
1870 | /* self-refresh seems busted with untiled */ | |
3e510a8e | 1871 | if (!i915_gem_object_is_tiled(obj)) |
2ab1bc9d DV |
1872 | enabled = NULL; |
1873 | } | |
1874 | ||
b445e3b0 ED |
1875 | /* |
1876 | * Overlay gets an aggressive default since video jitter is bad. | |
1877 | */ | |
1878 | cwm = 2; | |
1879 | ||
1880 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1881 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1882 | |
1883 | /* Calc sr entries for one plane configs */ | |
03427fcb | 1884 | if (HAS_FW_BLC(dev_priv) && enabled) { |
b445e3b0 ED |
1885 | /* self-refresh has much higher latency */ |
1886 | static const int sr_latency_ns = 6000; | |
efc2611e VS |
1887 | const struct drm_display_mode *adjusted_mode = |
1888 | &enabled->config->base.adjusted_mode; | |
1889 | const struct drm_framebuffer *fb = | |
1890 | enabled->base.primary->state->fb; | |
241bfc38 | 1891 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1892 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e VS |
1893 | int hdisplay = enabled->config->pipe_src_w; |
1894 | int cpp; | |
b445e3b0 ED |
1895 | unsigned long line_time_us; |
1896 | int entries; | |
1897 | ||
50a0bc90 | 1898 | if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) |
2d1b5056 | 1899 | cpp = 4; |
efc2611e | 1900 | else |
353c8598 | 1901 | cpp = fb->format->cpp[0]; |
2d1b5056 | 1902 | |
922044c9 | 1903 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1904 | |
1905 | /* Use ns/us then divide to preserve precision */ | |
1906 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
ac484963 | 1907 | cpp * hdisplay; |
b445e3b0 ED |
1908 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1909 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1910 | srwm = wm_info->fifo_size - entries; | |
1911 | if (srwm < 0) | |
1912 | srwm = 1; | |
1913 | ||
50a0bc90 | 1914 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
b445e3b0 ED |
1915 | I915_WRITE(FW_BLC_SELF, |
1916 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
acb91359 | 1917 | else |
b445e3b0 ED |
1918 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1919 | } | |
1920 | ||
1921 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1922 | planea_wm, planeb_wm, cwm, srwm); | |
1923 | ||
1924 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1925 | fwater_hi = (cwm & 0x1f); | |
1926 | ||
1927 | /* Set request length to 8 cachelines per fetch */ | |
1928 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1929 | fwater_hi = fwater_hi | (1 << 8); | |
1930 | ||
1931 | I915_WRITE(FW_BLC, fwater_lo); | |
1932 | I915_WRITE(FW_BLC2, fwater_hi); | |
1933 | ||
5209b1f4 ID |
1934 | if (enabled) |
1935 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1936 | } |
1937 | ||
432081bc | 1938 | static void i845_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 1939 | { |
ffc7a76b | 1940 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 1941 | struct intel_crtc *crtc; |
241bfc38 | 1942 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1943 | uint32_t fwater_lo; |
1944 | int planea_wm; | |
1945 | ||
ffc7a76b | 1946 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
1947 | if (crtc == NULL) |
1948 | return; | |
1949 | ||
efc2611e | 1950 | adjusted_mode = &crtc->config->base.adjusted_mode; |
241bfc38 | 1951 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 1952 | &i845_wm_info, |
ef0f5e93 | 1953 | dev_priv->display.get_fifo_size(dev_priv, 0), |
5aef6003 | 1954 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1955 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1956 | fwater_lo |= (3<<8) | planea_wm; | |
1957 | ||
1958 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1959 | ||
1960 | I915_WRITE(FW_BLC, fwater_lo); | |
1961 | } | |
1962 | ||
37126462 | 1963 | /* latency must be in 0.1us units. */ |
ac484963 | 1964 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) |
801bcfff PZ |
1965 | { |
1966 | uint64_t ret; | |
1967 | ||
3312ba65 VS |
1968 | if (WARN(latency == 0, "Latency value missing\n")) |
1969 | return UINT_MAX; | |
1970 | ||
ac484963 | 1971 | ret = (uint64_t) pixel_rate * cpp * latency; |
801bcfff PZ |
1972 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
1973 | ||
1974 | return ret; | |
1975 | } | |
1976 | ||
37126462 | 1977 | /* latency must be in 0.1us units. */ |
23297044 | 1978 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
ac484963 | 1979 | uint32_t horiz_pixels, uint8_t cpp, |
801bcfff PZ |
1980 | uint32_t latency) |
1981 | { | |
1982 | uint32_t ret; | |
1983 | ||
3312ba65 VS |
1984 | if (WARN(latency == 0, "Latency value missing\n")) |
1985 | return UINT_MAX; | |
15126882 MR |
1986 | if (WARN_ON(!pipe_htotal)) |
1987 | return UINT_MAX; | |
3312ba65 | 1988 | |
801bcfff | 1989 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
ac484963 | 1990 | ret = (ret + 1) * horiz_pixels * cpp; |
801bcfff PZ |
1991 | ret = DIV_ROUND_UP(ret, 64) + 2; |
1992 | return ret; | |
1993 | } | |
1994 | ||
23297044 | 1995 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
ac484963 | 1996 | uint8_t cpp) |
cca32e9a | 1997 | { |
15126882 MR |
1998 | /* |
1999 | * Neither of these should be possible since this function shouldn't be | |
2000 | * called if the CRTC is off or the plane is invisible. But let's be | |
2001 | * extra paranoid to avoid a potential divide-by-zero if we screw up | |
2002 | * elsewhere in the driver. | |
2003 | */ | |
ac484963 | 2004 | if (WARN_ON(!cpp)) |
15126882 MR |
2005 | return 0; |
2006 | if (WARN_ON(!horiz_pixels)) | |
2007 | return 0; | |
2008 | ||
ac484963 | 2009 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2; |
cca32e9a PZ |
2010 | } |
2011 | ||
820c1980 | 2012 | struct ilk_wm_maximums { |
cca32e9a PZ |
2013 | uint16_t pri; |
2014 | uint16_t spr; | |
2015 | uint16_t cur; | |
2016 | uint16_t fbc; | |
2017 | }; | |
2018 | ||
37126462 VS |
2019 | /* |
2020 | * For both WM_PIPE and WM_LP. | |
2021 | * mem_value must be in 0.1us units. | |
2022 | */ | |
7221fc33 | 2023 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2024 | const struct intel_plane_state *pstate, |
cca32e9a PZ |
2025 | uint32_t mem_value, |
2026 | bool is_lp) | |
801bcfff | 2027 | { |
cca32e9a | 2028 | uint32_t method1, method2; |
8305494e | 2029 | int cpp; |
cca32e9a | 2030 | |
24304d81 | 2031 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2032 | return 0; |
2033 | ||
353c8598 | 2034 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2035 | |
a7d1b3f4 | 2036 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
cca32e9a PZ |
2037 | |
2038 | if (!is_lp) | |
2039 | return method1; | |
2040 | ||
a7d1b3f4 | 2041 | method2 = ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 2042 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 2043 | drm_rect_width(&pstate->base.dst), |
ac484963 | 2044 | cpp, mem_value); |
cca32e9a PZ |
2045 | |
2046 | return min(method1, method2); | |
801bcfff PZ |
2047 | } |
2048 | ||
37126462 VS |
2049 | /* |
2050 | * For both WM_PIPE and WM_LP. | |
2051 | * mem_value must be in 0.1us units. | |
2052 | */ | |
7221fc33 | 2053 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2054 | const struct intel_plane_state *pstate, |
801bcfff PZ |
2055 | uint32_t mem_value) |
2056 | { | |
2057 | uint32_t method1, method2; | |
8305494e | 2058 | int cpp; |
801bcfff | 2059 | |
24304d81 | 2060 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2061 | return 0; |
2062 | ||
353c8598 | 2063 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2064 | |
a7d1b3f4 VS |
2065 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
2066 | method2 = ilk_wm_method2(cstate->pixel_rate, | |
7221fc33 | 2067 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 2068 | drm_rect_width(&pstate->base.dst), |
ac484963 | 2069 | cpp, mem_value); |
801bcfff PZ |
2070 | return min(method1, method2); |
2071 | } | |
2072 | ||
37126462 VS |
2073 | /* |
2074 | * For both WM_PIPE and WM_LP. | |
2075 | * mem_value must be in 0.1us units. | |
2076 | */ | |
7221fc33 | 2077 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2078 | const struct intel_plane_state *pstate, |
801bcfff PZ |
2079 | uint32_t mem_value) |
2080 | { | |
a5509abd VS |
2081 | int cpp; |
2082 | ||
24304d81 | 2083 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2084 | return 0; |
2085 | ||
a5509abd VS |
2086 | cpp = pstate->base.fb->format->cpp[0]; |
2087 | ||
a7d1b3f4 | 2088 | return ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 2089 | cstate->base.adjusted_mode.crtc_htotal, |
a5509abd | 2090 | pstate->base.crtc_w, cpp, mem_value); |
801bcfff PZ |
2091 | } |
2092 | ||
cca32e9a | 2093 | /* Only for WM_LP. */ |
7221fc33 | 2094 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2095 | const struct intel_plane_state *pstate, |
1fda9882 | 2096 | uint32_t pri_val) |
cca32e9a | 2097 | { |
8305494e | 2098 | int cpp; |
43d59eda | 2099 | |
24304d81 | 2100 | if (!intel_wm_plane_visible(cstate, pstate)) |
cca32e9a PZ |
2101 | return 0; |
2102 | ||
353c8598 | 2103 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2104 | |
936e71e3 | 2105 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp); |
cca32e9a PZ |
2106 | } |
2107 | ||
175fded1 TU |
2108 | static unsigned int |
2109 | ilk_display_fifo_size(const struct drm_i915_private *dev_priv) | |
158ae64f | 2110 | { |
175fded1 | 2111 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 | 2112 | return 3072; |
175fded1 | 2113 | else if (INTEL_GEN(dev_priv) >= 7) |
158ae64f VS |
2114 | return 768; |
2115 | else | |
2116 | return 512; | |
2117 | } | |
2118 | ||
175fded1 TU |
2119 | static unsigned int |
2120 | ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, | |
2121 | int level, bool is_sprite) | |
4e975081 | 2122 | { |
175fded1 | 2123 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2124 | /* BDW primary/sprite plane watermarks */ |
2125 | return level == 0 ? 255 : 2047; | |
175fded1 | 2126 | else if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2127 | /* IVB/HSW primary/sprite plane watermarks */ |
2128 | return level == 0 ? 127 : 1023; | |
2129 | else if (!is_sprite) | |
2130 | /* ILK/SNB primary plane watermarks */ | |
2131 | return level == 0 ? 127 : 511; | |
2132 | else | |
2133 | /* ILK/SNB sprite plane watermarks */ | |
2134 | return level == 0 ? 63 : 255; | |
2135 | } | |
2136 | ||
175fded1 TU |
2137 | static unsigned int |
2138 | ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) | |
4e975081 | 2139 | { |
175fded1 | 2140 | if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2141 | return level == 0 ? 63 : 255; |
2142 | else | |
2143 | return level == 0 ? 31 : 63; | |
2144 | } | |
2145 | ||
175fded1 | 2146 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) |
4e975081 | 2147 | { |
175fded1 | 2148 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2149 | return 31; |
2150 | else | |
2151 | return 15; | |
2152 | } | |
2153 | ||
158ae64f VS |
2154 | /* Calculate the maximum primary/sprite plane watermark */ |
2155 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
2156 | int level, | |
240264f4 | 2157 | const struct intel_wm_config *config, |
158ae64f VS |
2158 | enum intel_ddb_partitioning ddb_partitioning, |
2159 | bool is_sprite) | |
2160 | { | |
175fded1 TU |
2161 | struct drm_i915_private *dev_priv = to_i915(dev); |
2162 | unsigned int fifo_size = ilk_display_fifo_size(dev_priv); | |
158ae64f VS |
2163 | |
2164 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 2165 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
2166 | return 0; |
2167 | ||
2168 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 2169 | if (level == 0 || config->num_pipes_active > 1) { |
175fded1 | 2170 | fifo_size /= INTEL_INFO(dev_priv)->num_pipes; |
158ae64f VS |
2171 | |
2172 | /* | |
2173 | * For some reason the non self refresh | |
2174 | * FIFO size is only half of the self | |
2175 | * refresh FIFO size on ILK/SNB. | |
2176 | */ | |
175fded1 | 2177 | if (INTEL_GEN(dev_priv) <= 6) |
158ae64f VS |
2178 | fifo_size /= 2; |
2179 | } | |
2180 | ||
240264f4 | 2181 | if (config->sprites_enabled) { |
158ae64f VS |
2182 | /* level 0 is always calculated with 1:1 split */ |
2183 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
2184 | if (is_sprite) | |
2185 | fifo_size *= 5; | |
2186 | fifo_size /= 6; | |
2187 | } else { | |
2188 | fifo_size /= 2; | |
2189 | } | |
2190 | } | |
2191 | ||
2192 | /* clamp to max that the registers can hold */ | |
175fded1 | 2193 | return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); |
158ae64f VS |
2194 | } |
2195 | ||
2196 | /* Calculate the maximum cursor plane watermark */ | |
2197 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
2198 | int level, |
2199 | const struct intel_wm_config *config) | |
158ae64f VS |
2200 | { |
2201 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 2202 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
2203 | return 64; |
2204 | ||
2205 | /* otherwise just report max that registers can hold */ | |
175fded1 | 2206 | return ilk_cursor_wm_reg_max(to_i915(dev), level); |
158ae64f VS |
2207 | } |
2208 | ||
d34ff9c6 | 2209 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
2210 | int level, |
2211 | const struct intel_wm_config *config, | |
2212 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 2213 | struct ilk_wm_maximums *max) |
158ae64f | 2214 | { |
240264f4 VS |
2215 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
2216 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
2217 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
175fded1 | 2218 | max->fbc = ilk_fbc_wm_reg_max(to_i915(dev)); |
158ae64f VS |
2219 | } |
2220 | ||
175fded1 | 2221 | static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, |
a3cb4048 VS |
2222 | int level, |
2223 | struct ilk_wm_maximums *max) | |
2224 | { | |
175fded1 TU |
2225 | max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); |
2226 | max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); | |
2227 | max->cur = ilk_cursor_wm_reg_max(dev_priv, level); | |
2228 | max->fbc = ilk_fbc_wm_reg_max(dev_priv); | |
a3cb4048 VS |
2229 | } |
2230 | ||
d9395655 | 2231 | static bool ilk_validate_wm_level(int level, |
820c1980 | 2232 | const struct ilk_wm_maximums *max, |
d9395655 | 2233 | struct intel_wm_level *result) |
a9786a11 VS |
2234 | { |
2235 | bool ret; | |
2236 | ||
2237 | /* already determined to be invalid? */ | |
2238 | if (!result->enable) | |
2239 | return false; | |
2240 | ||
2241 | result->enable = result->pri_val <= max->pri && | |
2242 | result->spr_val <= max->spr && | |
2243 | result->cur_val <= max->cur; | |
2244 | ||
2245 | ret = result->enable; | |
2246 | ||
2247 | /* | |
2248 | * HACK until we can pre-compute everything, | |
2249 | * and thus fail gracefully if LP0 watermarks | |
2250 | * are exceeded... | |
2251 | */ | |
2252 | if (level == 0 && !result->enable) { | |
2253 | if (result->pri_val > max->pri) | |
2254 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
2255 | level, result->pri_val, max->pri); | |
2256 | if (result->spr_val > max->spr) | |
2257 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
2258 | level, result->spr_val, max->spr); | |
2259 | if (result->cur_val > max->cur) | |
2260 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
2261 | level, result->cur_val, max->cur); | |
2262 | ||
2263 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
2264 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
2265 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
2266 | result->enable = true; | |
2267 | } | |
2268 | ||
a9786a11 VS |
2269 | return ret; |
2270 | } | |
2271 | ||
d34ff9c6 | 2272 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
43d59eda | 2273 | const struct intel_crtc *intel_crtc, |
6f5ddd17 | 2274 | int level, |
7221fc33 | 2275 | struct intel_crtc_state *cstate, |
86c8bbbe MR |
2276 | struct intel_plane_state *pristate, |
2277 | struct intel_plane_state *sprstate, | |
2278 | struct intel_plane_state *curstate, | |
1fd527cc | 2279 | struct intel_wm_level *result) |
6f5ddd17 VS |
2280 | { |
2281 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
2282 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
2283 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
2284 | ||
2285 | /* WM1+ latency values stored in 0.5us units */ | |
2286 | if (level > 0) { | |
2287 | pri_latency *= 5; | |
2288 | spr_latency *= 5; | |
2289 | cur_latency *= 5; | |
2290 | } | |
2291 | ||
e3bddded ML |
2292 | if (pristate) { |
2293 | result->pri_val = ilk_compute_pri_wm(cstate, pristate, | |
2294 | pri_latency, level); | |
2295 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); | |
2296 | } | |
2297 | ||
2298 | if (sprstate) | |
2299 | result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency); | |
2300 | ||
2301 | if (curstate) | |
2302 | result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency); | |
2303 | ||
6f5ddd17 VS |
2304 | result->enable = true; |
2305 | } | |
2306 | ||
801bcfff | 2307 | static uint32_t |
532f7a7f | 2308 | hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) |
1f8eeabf | 2309 | { |
532f7a7f VS |
2310 | const struct intel_atomic_state *intel_state = |
2311 | to_intel_atomic_state(cstate->base.state); | |
ee91a159 MR |
2312 | const struct drm_display_mode *adjusted_mode = |
2313 | &cstate->base.adjusted_mode; | |
85a02deb | 2314 | u32 linetime, ips_linetime; |
1f8eeabf | 2315 | |
ee91a159 MR |
2316 | if (!cstate->base.active) |
2317 | return 0; | |
2318 | if (WARN_ON(adjusted_mode->crtc_clock == 0)) | |
2319 | return 0; | |
bb0f4aab | 2320 | if (WARN_ON(intel_state->cdclk.logical.cdclk == 0)) |
801bcfff | 2321 | return 0; |
1011d8c4 | 2322 | |
1f8eeabf ED |
2323 | /* The WM are computed with base on how long it takes to fill a single |
2324 | * row at the given clock rate, multiplied by 8. | |
2325 | * */ | |
124abe07 VS |
2326 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2327 | adjusted_mode->crtc_clock); | |
2328 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, | |
bb0f4aab | 2329 | intel_state->cdclk.logical.cdclk); |
1f8eeabf | 2330 | |
801bcfff PZ |
2331 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2332 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2333 | } |
2334 | ||
bb726519 VS |
2335 | static void intel_read_wm_latency(struct drm_i915_private *dev_priv, |
2336 | uint16_t wm[8]) | |
12b134df | 2337 | { |
5db94019 | 2338 | if (IS_GEN9(dev_priv)) { |
2af30a5c | 2339 | uint32_t val; |
4f947386 | 2340 | int ret, i; |
5db94019 | 2341 | int level, max_level = ilk_wm_max_level(dev_priv); |
2af30a5c PB |
2342 | |
2343 | /* read the first set of memory latencies[0:3] */ | |
2344 | val = 0; /* data0 to be programmed to 0 for first set */ | |
2345 | mutex_lock(&dev_priv->rps.hw_lock); | |
2346 | ret = sandybridge_pcode_read(dev_priv, | |
2347 | GEN9_PCODE_READ_MEM_LATENCY, | |
2348 | &val); | |
2349 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2350 | ||
2351 | if (ret) { | |
2352 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2353 | return; | |
2354 | } | |
2355 | ||
2356 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2357 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2358 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2359 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2360 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2361 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2362 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2363 | ||
2364 | /* read the second set of memory latencies[4:7] */ | |
2365 | val = 1; /* data0 to be programmed to 1 for second set */ | |
2366 | mutex_lock(&dev_priv->rps.hw_lock); | |
2367 | ret = sandybridge_pcode_read(dev_priv, | |
2368 | GEN9_PCODE_READ_MEM_LATENCY, | |
2369 | &val); | |
2370 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2371 | if (ret) { | |
2372 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2373 | return; | |
2374 | } | |
2375 | ||
2376 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2377 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2378 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2379 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2380 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2381 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2382 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2383 | ||
0727e40a PZ |
2384 | /* |
2385 | * If a level n (n > 1) has a 0us latency, all levels m (m >= n) | |
2386 | * need to be disabled. We make sure to sanitize the values out | |
2387 | * of the punit to satisfy this requirement. | |
2388 | */ | |
2389 | for (level = 1; level <= max_level; level++) { | |
2390 | if (wm[level] == 0) { | |
2391 | for (i = level + 1; i <= max_level; i++) | |
2392 | wm[i] = 0; | |
2393 | break; | |
2394 | } | |
2395 | } | |
2396 | ||
367294be | 2397 | /* |
9fb5026f | 2398 | * WaWmMemoryReadLatency:skl,glk |
6f97235b | 2399 | * |
367294be | 2400 | * punit doesn't take into account the read latency so we need |
0727e40a PZ |
2401 | * to add 2us to the various latency levels we retrieve from the |
2402 | * punit when level 0 response data us 0us. | |
367294be | 2403 | */ |
0727e40a PZ |
2404 | if (wm[0] == 0) { |
2405 | wm[0] += 2; | |
2406 | for (level = 1; level <= max_level; level++) { | |
2407 | if (wm[level] == 0) | |
2408 | break; | |
367294be | 2409 | wm[level] += 2; |
4f947386 | 2410 | } |
0727e40a PZ |
2411 | } |
2412 | ||
8652744b | 2413 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
12b134df VS |
2414 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2415 | ||
2416 | wm[0] = (sskpd >> 56) & 0xFF; | |
2417 | if (wm[0] == 0) | |
2418 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2419 | wm[1] = (sskpd >> 4) & 0xFF; |
2420 | wm[2] = (sskpd >> 12) & 0xFF; | |
2421 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2422 | wm[4] = (sskpd >> 32) & 0x1FF; | |
bb726519 | 2423 | } else if (INTEL_GEN(dev_priv) >= 6) { |
63cf9a13 VS |
2424 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
2425 | ||
2426 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2427 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2428 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2429 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
bb726519 | 2430 | } else if (INTEL_GEN(dev_priv) >= 5) { |
3a88d0ac VS |
2431 | uint32_t mltr = I915_READ(MLTR_ILK); |
2432 | ||
2433 | /* ILK primary LP0 latency is 700 ns */ | |
2434 | wm[0] = 7; | |
2435 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2436 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2437 | } |
2438 | } | |
2439 | ||
5db94019 TU |
2440 | static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, |
2441 | uint16_t wm[5]) | |
53615a5e VS |
2442 | { |
2443 | /* ILK sprite LP0 latency is 1300 ns */ | |
5db94019 | 2444 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2445 | wm[0] = 13; |
2446 | } | |
2447 | ||
fd6b8f43 TU |
2448 | static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, |
2449 | uint16_t wm[5]) | |
53615a5e VS |
2450 | { |
2451 | /* ILK cursor LP0 latency is 1300 ns */ | |
fd6b8f43 | 2452 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2453 | wm[0] = 13; |
2454 | ||
2455 | /* WaDoubleCursorLP3Latency:ivb */ | |
fd6b8f43 | 2456 | if (IS_IVYBRIDGE(dev_priv)) |
53615a5e VS |
2457 | wm[3] *= 2; |
2458 | } | |
2459 | ||
5db94019 | 2460 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv) |
26ec971e | 2461 | { |
26ec971e | 2462 | /* how many WM levels are we expecting */ |
8652744b | 2463 | if (INTEL_GEN(dev_priv) >= 9) |
2af30a5c | 2464 | return 7; |
8652744b | 2465 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ad0d6dc4 | 2466 | return 4; |
8652744b | 2467 | else if (INTEL_GEN(dev_priv) >= 6) |
ad0d6dc4 | 2468 | return 3; |
26ec971e | 2469 | else |
ad0d6dc4 VS |
2470 | return 2; |
2471 | } | |
7526ed79 | 2472 | |
5db94019 | 2473 | static void intel_print_wm_latency(struct drm_i915_private *dev_priv, |
ad0d6dc4 | 2474 | const char *name, |
2af30a5c | 2475 | const uint16_t wm[8]) |
ad0d6dc4 | 2476 | { |
5db94019 | 2477 | int level, max_level = ilk_wm_max_level(dev_priv); |
26ec971e VS |
2478 | |
2479 | for (level = 0; level <= max_level; level++) { | |
2480 | unsigned int latency = wm[level]; | |
2481 | ||
2482 | if (latency == 0) { | |
2483 | DRM_ERROR("%s WM%d latency not provided\n", | |
2484 | name, level); | |
2485 | continue; | |
2486 | } | |
2487 | ||
2af30a5c PB |
2488 | /* |
2489 | * - latencies are in us on gen9. | |
2490 | * - before then, WM1+ latency values are in 0.5us units | |
2491 | */ | |
5db94019 | 2492 | if (IS_GEN9(dev_priv)) |
2af30a5c PB |
2493 | latency *= 10; |
2494 | else if (level > 0) | |
26ec971e VS |
2495 | latency *= 5; |
2496 | ||
2497 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2498 | name, level, wm[level], | |
2499 | latency / 10, latency % 10); | |
2500 | } | |
2501 | } | |
2502 | ||
e95a2f75 VS |
2503 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2504 | uint16_t wm[5], uint16_t min) | |
2505 | { | |
5db94019 | 2506 | int level, max_level = ilk_wm_max_level(dev_priv); |
e95a2f75 VS |
2507 | |
2508 | if (wm[0] >= min) | |
2509 | return false; | |
2510 | ||
2511 | wm[0] = max(wm[0], min); | |
2512 | for (level = 1; level <= max_level; level++) | |
2513 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2514 | ||
2515 | return true; | |
2516 | } | |
2517 | ||
bb726519 | 2518 | static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) |
e95a2f75 | 2519 | { |
e95a2f75 VS |
2520 | bool changed; |
2521 | ||
2522 | /* | |
2523 | * The BIOS provided WM memory latency values are often | |
2524 | * inadequate for high resolution displays. Adjust them. | |
2525 | */ | |
2526 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2527 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2528 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2529 | ||
2530 | if (!changed) | |
2531 | return; | |
2532 | ||
2533 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
5db94019 TU |
2534 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2535 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2536 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2537 | } |
2538 | ||
bb726519 | 2539 | static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) |
53615a5e | 2540 | { |
bb726519 | 2541 | intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); |
53615a5e VS |
2542 | |
2543 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2544 | sizeof(dev_priv->wm.pri_latency)); | |
2545 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2546 | sizeof(dev_priv->wm.pri_latency)); | |
2547 | ||
5db94019 | 2548 | intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); |
fd6b8f43 | 2549 | intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); |
26ec971e | 2550 | |
5db94019 TU |
2551 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2552 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2553 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 | 2554 | |
5db94019 | 2555 | if (IS_GEN6(dev_priv)) |
bb726519 | 2556 | snb_wm_latency_quirk(dev_priv); |
53615a5e VS |
2557 | } |
2558 | ||
bb726519 | 2559 | static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) |
2af30a5c | 2560 | { |
bb726519 | 2561 | intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); |
5db94019 | 2562 | intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); |
2af30a5c PB |
2563 | } |
2564 | ||
ed4a6a7c MR |
2565 | static bool ilk_validate_pipe_wm(struct drm_device *dev, |
2566 | struct intel_pipe_wm *pipe_wm) | |
2567 | { | |
2568 | /* LP0 watermark maximums depend on this pipe alone */ | |
2569 | const struct intel_wm_config config = { | |
2570 | .num_pipes_active = 1, | |
2571 | .sprites_enabled = pipe_wm->sprites_enabled, | |
2572 | .sprites_scaled = pipe_wm->sprites_scaled, | |
2573 | }; | |
2574 | struct ilk_wm_maximums max; | |
2575 | ||
2576 | /* LP0 watermarks always use 1/2 DDB partitioning */ | |
2577 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2578 | ||
2579 | /* At least LP0 must be valid */ | |
2580 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { | |
2581 | DRM_DEBUG_KMS("LP0 watermark invalid\n"); | |
2582 | return false; | |
2583 | } | |
2584 | ||
2585 | return true; | |
2586 | } | |
2587 | ||
0b2ae6d7 | 2588 | /* Compute new watermarks for the pipe */ |
e3bddded | 2589 | static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) |
0b2ae6d7 | 2590 | { |
e3bddded ML |
2591 | struct drm_atomic_state *state = cstate->base.state; |
2592 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
86c8bbbe | 2593 | struct intel_pipe_wm *pipe_wm; |
e3bddded | 2594 | struct drm_device *dev = state->dev; |
fac5e23e | 2595 | const struct drm_i915_private *dev_priv = to_i915(dev); |
43d59eda | 2596 | struct intel_plane *intel_plane; |
86c8bbbe | 2597 | struct intel_plane_state *pristate = NULL; |
43d59eda | 2598 | struct intel_plane_state *sprstate = NULL; |
86c8bbbe | 2599 | struct intel_plane_state *curstate = NULL; |
5db94019 | 2600 | int level, max_level = ilk_wm_max_level(dev_priv), usable_level; |
820c1980 | 2601 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2602 | |
e8f1f02e | 2603 | pipe_wm = &cstate->wm.ilk.optimal; |
86c8bbbe | 2604 | |
43d59eda | 2605 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
e3bddded ML |
2606 | struct intel_plane_state *ps; |
2607 | ||
2608 | ps = intel_atomic_get_existing_plane_state(state, | |
2609 | intel_plane); | |
2610 | if (!ps) | |
2611 | continue; | |
86c8bbbe MR |
2612 | |
2613 | if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
e3bddded | 2614 | pristate = ps; |
86c8bbbe | 2615 | else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) |
e3bddded | 2616 | sprstate = ps; |
86c8bbbe | 2617 | else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) |
e3bddded | 2618 | curstate = ps; |
43d59eda MR |
2619 | } |
2620 | ||
ed4a6a7c | 2621 | pipe_wm->pipe_enabled = cstate->base.active; |
e3bddded | 2622 | if (sprstate) { |
936e71e3 VS |
2623 | pipe_wm->sprites_enabled = sprstate->base.visible; |
2624 | pipe_wm->sprites_scaled = sprstate->base.visible && | |
2625 | (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 || | |
2626 | drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16); | |
e3bddded ML |
2627 | } |
2628 | ||
d81f04c5 ML |
2629 | usable_level = max_level; |
2630 | ||
7b39a0b7 | 2631 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
175fded1 | 2632 | if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) |
d81f04c5 | 2633 | usable_level = 1; |
7b39a0b7 VS |
2634 | |
2635 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
ed4a6a7c | 2636 | if (pipe_wm->sprites_scaled) |
d81f04c5 | 2637 | usable_level = 0; |
7b39a0b7 | 2638 | |
86c8bbbe | 2639 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
71f0a626 ML |
2640 | pristate, sprstate, curstate, &pipe_wm->raw_wm[0]); |
2641 | ||
2642 | memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); | |
2643 | pipe_wm->wm[0] = pipe_wm->raw_wm[0]; | |
0b2ae6d7 | 2644 | |
8652744b | 2645 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
532f7a7f | 2646 | pipe_wm->linetime = hsw_compute_linetime_wm(cstate); |
0b2ae6d7 | 2647 | |
ed4a6a7c | 2648 | if (!ilk_validate_pipe_wm(dev, pipe_wm)) |
1a426d61 | 2649 | return -EINVAL; |
a3cb4048 | 2650 | |
175fded1 | 2651 | ilk_compute_wm_reg_maximums(dev_priv, 1, &max); |
a3cb4048 VS |
2652 | |
2653 | for (level = 1; level <= max_level; level++) { | |
71f0a626 | 2654 | struct intel_wm_level *wm = &pipe_wm->raw_wm[level]; |
a3cb4048 | 2655 | |
86c8bbbe | 2656 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, |
d81f04c5 | 2657 | pristate, sprstate, curstate, wm); |
a3cb4048 VS |
2658 | |
2659 | /* | |
2660 | * Disable any watermark level that exceeds the | |
2661 | * register maximums since such watermarks are | |
2662 | * always invalid. | |
2663 | */ | |
71f0a626 ML |
2664 | if (level > usable_level) |
2665 | continue; | |
2666 | ||
2667 | if (ilk_validate_wm_level(level, &max, wm)) | |
2668 | pipe_wm->wm[level] = *wm; | |
2669 | else | |
d81f04c5 | 2670 | usable_level = level; |
a3cb4048 VS |
2671 | } |
2672 | ||
86c8bbbe | 2673 | return 0; |
0b2ae6d7 VS |
2674 | } |
2675 | ||
ed4a6a7c MR |
2676 | /* |
2677 | * Build a set of 'intermediate' watermark values that satisfy both the old | |
2678 | * state and the new state. These can be programmed to the hardware | |
2679 | * immediately. | |
2680 | */ | |
2681 | static int ilk_compute_intermediate_wm(struct drm_device *dev, | |
2682 | struct intel_crtc *intel_crtc, | |
2683 | struct intel_crtc_state *newstate) | |
2684 | { | |
e8f1f02e | 2685 | struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; |
ed4a6a7c | 2686 | struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk; |
5db94019 | 2687 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
ed4a6a7c MR |
2688 | |
2689 | /* | |
2690 | * Start with the final, target watermarks, then combine with the | |
2691 | * currently active watermarks to get values that are safe both before | |
2692 | * and after the vblank. | |
2693 | */ | |
e8f1f02e | 2694 | *a = newstate->wm.ilk.optimal; |
ed4a6a7c MR |
2695 | a->pipe_enabled |= b->pipe_enabled; |
2696 | a->sprites_enabled |= b->sprites_enabled; | |
2697 | a->sprites_scaled |= b->sprites_scaled; | |
2698 | ||
2699 | for (level = 0; level <= max_level; level++) { | |
2700 | struct intel_wm_level *a_wm = &a->wm[level]; | |
2701 | const struct intel_wm_level *b_wm = &b->wm[level]; | |
2702 | ||
2703 | a_wm->enable &= b_wm->enable; | |
2704 | a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val); | |
2705 | a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val); | |
2706 | a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val); | |
2707 | a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val); | |
2708 | } | |
2709 | ||
2710 | /* | |
2711 | * We need to make sure that these merged watermark values are | |
2712 | * actually a valid configuration themselves. If they're not, | |
2713 | * there's no safe way to transition from the old state to | |
2714 | * the new state, so we need to fail the atomic transaction. | |
2715 | */ | |
2716 | if (!ilk_validate_pipe_wm(dev, a)) | |
2717 | return -EINVAL; | |
2718 | ||
2719 | /* | |
2720 | * If our intermediate WM are identical to the final WM, then we can | |
2721 | * omit the post-vblank programming; only update if it's different. | |
2722 | */ | |
5eeb798b VS |
2723 | if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0) |
2724 | newstate->wm.need_postvbl_update = true; | |
ed4a6a7c MR |
2725 | |
2726 | return 0; | |
2727 | } | |
2728 | ||
0b2ae6d7 VS |
2729 | /* |
2730 | * Merge the watermarks from all active pipes for a specific level. | |
2731 | */ | |
2732 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2733 | int level, | |
2734 | struct intel_wm_level *ret_wm) | |
2735 | { | |
2736 | const struct intel_crtc *intel_crtc; | |
2737 | ||
d52fea5b VS |
2738 | ret_wm->enable = true; |
2739 | ||
d3fcc808 | 2740 | for_each_intel_crtc(dev, intel_crtc) { |
ed4a6a7c | 2741 | const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; |
fe392efd VS |
2742 | const struct intel_wm_level *wm = &active->wm[level]; |
2743 | ||
2744 | if (!active->pipe_enabled) | |
2745 | continue; | |
0b2ae6d7 | 2746 | |
d52fea5b VS |
2747 | /* |
2748 | * The watermark values may have been used in the past, | |
2749 | * so we must maintain them in the registers for some | |
2750 | * time even if the level is now disabled. | |
2751 | */ | |
0b2ae6d7 | 2752 | if (!wm->enable) |
d52fea5b | 2753 | ret_wm->enable = false; |
0b2ae6d7 VS |
2754 | |
2755 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2756 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2757 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2758 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2759 | } | |
0b2ae6d7 VS |
2760 | } |
2761 | ||
2762 | /* | |
2763 | * Merge all low power watermarks for all active pipes. | |
2764 | */ | |
2765 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2766 | const struct intel_wm_config *config, |
820c1980 | 2767 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2768 | struct intel_pipe_wm *merged) |
2769 | { | |
fac5e23e | 2770 | struct drm_i915_private *dev_priv = to_i915(dev); |
5db94019 | 2771 | int level, max_level = ilk_wm_max_level(dev_priv); |
d52fea5b | 2772 | int last_enabled_level = max_level; |
0b2ae6d7 | 2773 | |
0ba22e26 | 2774 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
fd6b8f43 | 2775 | if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) && |
0ba22e26 | 2776 | config->num_pipes_active > 1) |
1204d5ba | 2777 | last_enabled_level = 0; |
0ba22e26 | 2778 | |
6c8b6c28 | 2779 | /* ILK: FBC WM must be disabled always */ |
175fded1 | 2780 | merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; |
0b2ae6d7 VS |
2781 | |
2782 | /* merge each WM1+ level */ | |
2783 | for (level = 1; level <= max_level; level++) { | |
2784 | struct intel_wm_level *wm = &merged->wm[level]; | |
2785 | ||
2786 | ilk_merge_wm_level(dev, level, wm); | |
2787 | ||
d52fea5b VS |
2788 | if (level > last_enabled_level) |
2789 | wm->enable = false; | |
2790 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2791 | /* make sure all following levels get disabled */ | |
2792 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2793 | |
2794 | /* | |
2795 | * The spec says it is preferred to disable | |
2796 | * FBC WMs instead of disabling a WM level. | |
2797 | */ | |
2798 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2799 | if (wm->enable) |
2800 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2801 | wm->fbc_val = 0; |
2802 | } | |
2803 | } | |
6c8b6c28 VS |
2804 | |
2805 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2806 | /* | |
2807 | * FIXME this is racy. FBC might get enabled later. | |
2808 | * What we should check here is whether FBC can be | |
2809 | * enabled sometime later. | |
2810 | */ | |
5db94019 | 2811 | if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && |
0e631adc | 2812 | intel_fbc_is_active(dev_priv)) { |
6c8b6c28 VS |
2813 | for (level = 2; level <= max_level; level++) { |
2814 | struct intel_wm_level *wm = &merged->wm[level]; | |
2815 | ||
2816 | wm->enable = false; | |
2817 | } | |
2818 | } | |
0b2ae6d7 VS |
2819 | } |
2820 | ||
b380ca3c VS |
2821 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2822 | { | |
2823 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2824 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2825 | } | |
2826 | ||
a68d68ee VS |
2827 | /* The value we need to program into the WM_LPx latency field */ |
2828 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2829 | { | |
fac5e23e | 2830 | struct drm_i915_private *dev_priv = to_i915(dev); |
a68d68ee | 2831 | |
8652744b | 2832 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
a68d68ee VS |
2833 | return 2 * level; |
2834 | else | |
2835 | return dev_priv->wm.pri_latency[level]; | |
2836 | } | |
2837 | ||
820c1980 | 2838 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2839 | const struct intel_pipe_wm *merged, |
609cedef | 2840 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2841 | struct ilk_wm_values *results) |
801bcfff | 2842 | { |
175fded1 | 2843 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b2ae6d7 VS |
2844 | struct intel_crtc *intel_crtc; |
2845 | int level, wm_lp; | |
cca32e9a | 2846 | |
0362c781 | 2847 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2848 | results->partitioning = partitioning; |
cca32e9a | 2849 | |
0b2ae6d7 | 2850 | /* LP1+ register values */ |
cca32e9a | 2851 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2852 | const struct intel_wm_level *r; |
801bcfff | 2853 | |
b380ca3c | 2854 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2855 | |
0362c781 | 2856 | r = &merged->wm[level]; |
cca32e9a | 2857 | |
d52fea5b VS |
2858 | /* |
2859 | * Maintain the watermark values even if the level is | |
2860 | * disabled. Doing otherwise could cause underruns. | |
2861 | */ | |
2862 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2863 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2864 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2865 | r->cur_val; | |
2866 | ||
d52fea5b VS |
2867 | if (r->enable) |
2868 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2869 | ||
175fded1 | 2870 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 VS |
2871 | results->wm_lp[wm_lp - 1] |= |
2872 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2873 | else | |
2874 | results->wm_lp[wm_lp - 1] |= | |
2875 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2876 | ||
d52fea5b VS |
2877 | /* |
2878 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2879 | * level is disabled. Doing otherwise could cause underruns. | |
2880 | */ | |
175fded1 | 2881 | if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { |
6cef2b8a VS |
2882 | WARN_ON(wm_lp != 1); |
2883 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2884 | } else | |
2885 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2886 | } |
801bcfff | 2887 | |
0b2ae6d7 | 2888 | /* LP0 register values */ |
d3fcc808 | 2889 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 | 2890 | enum pipe pipe = intel_crtc->pipe; |
ed4a6a7c MR |
2891 | const struct intel_wm_level *r = |
2892 | &intel_crtc->wm.active.ilk.wm[0]; | |
0b2ae6d7 VS |
2893 | |
2894 | if (WARN_ON(!r->enable)) | |
2895 | continue; | |
2896 | ||
ed4a6a7c | 2897 | results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; |
1011d8c4 | 2898 | |
0b2ae6d7 VS |
2899 | results->wm_pipe[pipe] = |
2900 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2901 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2902 | r->cur_val; | |
801bcfff PZ |
2903 | } |
2904 | } | |
2905 | ||
861f3389 PZ |
2906 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2907 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2908 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2909 | struct intel_pipe_wm *r1, |
2910 | struct intel_pipe_wm *r2) | |
861f3389 | 2911 | { |
5db94019 | 2912 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
198a1e9b | 2913 | int level1 = 0, level2 = 0; |
861f3389 | 2914 | |
198a1e9b VS |
2915 | for (level = 1; level <= max_level; level++) { |
2916 | if (r1->wm[level].enable) | |
2917 | level1 = level; | |
2918 | if (r2->wm[level].enable) | |
2919 | level2 = level; | |
861f3389 PZ |
2920 | } |
2921 | ||
198a1e9b VS |
2922 | if (level1 == level2) { |
2923 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2924 | return r2; |
2925 | else | |
2926 | return r1; | |
198a1e9b | 2927 | } else if (level1 > level2) { |
861f3389 PZ |
2928 | return r1; |
2929 | } else { | |
2930 | return r2; | |
2931 | } | |
2932 | } | |
2933 | ||
49a687c4 VS |
2934 | /* dirty bits used to track which watermarks need changes */ |
2935 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2936 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2937 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2938 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2939 | #define WM_DIRTY_FBC (1 << 24) | |
2940 | #define WM_DIRTY_DDB (1 << 25) | |
2941 | ||
055e393f | 2942 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2943 | const struct ilk_wm_values *old, |
2944 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2945 | { |
2946 | unsigned int dirty = 0; | |
2947 | enum pipe pipe; | |
2948 | int wm_lp; | |
2949 | ||
055e393f | 2950 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2951 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2952 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2953 | /* Must disable LP1+ watermarks too */ | |
2954 | dirty |= WM_DIRTY_LP_ALL; | |
2955 | } | |
2956 | ||
2957 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2958 | dirty |= WM_DIRTY_PIPE(pipe); | |
2959 | /* Must disable LP1+ watermarks too */ | |
2960 | dirty |= WM_DIRTY_LP_ALL; | |
2961 | } | |
2962 | } | |
2963 | ||
2964 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2965 | dirty |= WM_DIRTY_FBC; | |
2966 | /* Must disable LP1+ watermarks too */ | |
2967 | dirty |= WM_DIRTY_LP_ALL; | |
2968 | } | |
2969 | ||
2970 | if (old->partitioning != new->partitioning) { | |
2971 | dirty |= WM_DIRTY_DDB; | |
2972 | /* Must disable LP1+ watermarks too */ | |
2973 | dirty |= WM_DIRTY_LP_ALL; | |
2974 | } | |
2975 | ||
2976 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2977 | if (dirty & WM_DIRTY_LP_ALL) | |
2978 | return dirty; | |
2979 | ||
2980 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2981 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2982 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2983 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2984 | break; | |
2985 | } | |
2986 | ||
2987 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2988 | for (; wm_lp <= 3; wm_lp++) | |
2989 | dirty |= WM_DIRTY_LP(wm_lp); | |
2990 | ||
2991 | return dirty; | |
2992 | } | |
2993 | ||
8553c18e VS |
2994 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2995 | unsigned int dirty) | |
801bcfff | 2996 | { |
820c1980 | 2997 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2998 | bool changed = false; |
801bcfff | 2999 | |
facd619b VS |
3000 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
3001 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
3002 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 3003 | changed = true; |
facd619b VS |
3004 | } |
3005 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
3006 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
3007 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 3008 | changed = true; |
facd619b VS |
3009 | } |
3010 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
3011 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
3012 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 3013 | changed = true; |
facd619b | 3014 | } |
801bcfff | 3015 | |
facd619b VS |
3016 | /* |
3017 | * Don't touch WM1S_LP_EN here. | |
3018 | * Doing so could cause underruns. | |
3019 | */ | |
6cef2b8a | 3020 | |
8553c18e VS |
3021 | return changed; |
3022 | } | |
3023 | ||
3024 | /* | |
3025 | * The spec says we shouldn't write when we don't need, because every write | |
3026 | * causes WMs to be re-evaluated, expending some power. | |
3027 | */ | |
820c1980 ID |
3028 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
3029 | struct ilk_wm_values *results) | |
8553c18e | 3030 | { |
820c1980 | 3031 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
3032 | unsigned int dirty; |
3033 | uint32_t val; | |
3034 | ||
055e393f | 3035 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
3036 | if (!dirty) |
3037 | return; | |
3038 | ||
3039 | _ilk_disable_lp_wm(dev_priv, dirty); | |
3040 | ||
49a687c4 | 3041 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 3042 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 3043 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 3044 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 3045 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
3046 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
3047 | ||
49a687c4 | 3048 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 3049 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 3050 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 3051 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 3052 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
3053 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
3054 | ||
49a687c4 | 3055 | if (dirty & WM_DIRTY_DDB) { |
8652744b | 3056 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
ac9545fd VS |
3057 | val = I915_READ(WM_MISC); |
3058 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3059 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
3060 | else | |
3061 | val |= WM_MISC_DATA_PARTITION_5_6; | |
3062 | I915_WRITE(WM_MISC, val); | |
3063 | } else { | |
3064 | val = I915_READ(DISP_ARB_CTL2); | |
3065 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3066 | val &= ~DISP_DATA_PARTITION_5_6; | |
3067 | else | |
3068 | val |= DISP_DATA_PARTITION_5_6; | |
3069 | I915_WRITE(DISP_ARB_CTL2, val); | |
3070 | } | |
1011d8c4 PZ |
3071 | } |
3072 | ||
49a687c4 | 3073 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
3074 | val = I915_READ(DISP_ARB_CTL); |
3075 | if (results->enable_fbc_wm) | |
3076 | val &= ~DISP_FBC_WM_DIS; | |
3077 | else | |
3078 | val |= DISP_FBC_WM_DIS; | |
3079 | I915_WRITE(DISP_ARB_CTL, val); | |
3080 | } | |
3081 | ||
954911eb ID |
3082 | if (dirty & WM_DIRTY_LP(1) && |
3083 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
3084 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
3085 | ||
175fded1 | 3086 | if (INTEL_GEN(dev_priv) >= 7) { |
6cef2b8a VS |
3087 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
3088 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
3089 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
3090 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
3091 | } | |
801bcfff | 3092 | |
facd619b | 3093 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 3094 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 3095 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 3096 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 3097 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 3098 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
3099 | |
3100 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
3101 | } |
3102 | ||
ed4a6a7c | 3103 | bool ilk_disable_lp_wm(struct drm_device *dev) |
8553c18e | 3104 | { |
fac5e23e | 3105 | struct drm_i915_private *dev_priv = to_i915(dev); |
8553c18e VS |
3106 | |
3107 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
3108 | } | |
3109 | ||
656d1b89 | 3110 | #define SKL_SAGV_BLOCK_TIME 30 /* µs */ |
b9cec075 | 3111 | |
ee3d532f PZ |
3112 | /* |
3113 | * FIXME: We still don't have the proper code detect if we need to apply the WA, | |
3114 | * so assume we'll always need it in order to avoid underruns. | |
3115 | */ | |
3116 | static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) | |
3117 | { | |
3118 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
3119 | ||
b976dc53 | 3120 | if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) |
ee3d532f PZ |
3121 | return true; |
3122 | ||
3123 | return false; | |
3124 | } | |
3125 | ||
56feca91 PZ |
3126 | static bool |
3127 | intel_has_sagv(struct drm_i915_private *dev_priv) | |
3128 | { | |
6e3100ec PZ |
3129 | if (IS_KABYLAKE(dev_priv)) |
3130 | return true; | |
3131 | ||
3132 | if (IS_SKYLAKE(dev_priv) && | |
3133 | dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED) | |
3134 | return true; | |
3135 | ||
3136 | return false; | |
56feca91 PZ |
3137 | } |
3138 | ||
656d1b89 L |
3139 | /* |
3140 | * SAGV dynamically adjusts the system agent voltage and clock frequencies | |
3141 | * depending on power and performance requirements. The display engine access | |
3142 | * to system memory is blocked during the adjustment time. Because of the | |
3143 | * blocking time, having this enabled can cause full system hangs and/or pipe | |
3144 | * underruns if we don't meet all of the following requirements: | |
3145 | * | |
3146 | * - <= 1 pipe enabled | |
3147 | * - All planes can enable watermarks for latencies >= SAGV engine block time | |
3148 | * - We're not using an interlaced display configuration | |
3149 | */ | |
3150 | int | |
16dcdc4e | 3151 | intel_enable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 L |
3152 | { |
3153 | int ret; | |
3154 | ||
56feca91 PZ |
3155 | if (!intel_has_sagv(dev_priv)) |
3156 | return 0; | |
3157 | ||
3158 | if (dev_priv->sagv_status == I915_SAGV_ENABLED) | |
656d1b89 L |
3159 | return 0; |
3160 | ||
3161 | DRM_DEBUG_KMS("Enabling the SAGV\n"); | |
3162 | mutex_lock(&dev_priv->rps.hw_lock); | |
3163 | ||
3164 | ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, | |
3165 | GEN9_SAGV_ENABLE); | |
3166 | ||
3167 | /* We don't need to wait for the SAGV when enabling */ | |
3168 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3169 | ||
3170 | /* | |
3171 | * Some skl systems, pre-release machines in particular, | |
3172 | * don't actually have an SAGV. | |
3173 | */ | |
6e3100ec | 3174 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3175 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3176 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 L |
3177 | return 0; |
3178 | } else if (ret < 0) { | |
3179 | DRM_ERROR("Failed to enable the SAGV\n"); | |
3180 | return ret; | |
3181 | } | |
3182 | ||
16dcdc4e | 3183 | dev_priv->sagv_status = I915_SAGV_ENABLED; |
656d1b89 L |
3184 | return 0; |
3185 | } | |
3186 | ||
656d1b89 | 3187 | int |
16dcdc4e | 3188 | intel_disable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 | 3189 | { |
b3b8e999 | 3190 | int ret; |
656d1b89 | 3191 | |
56feca91 PZ |
3192 | if (!intel_has_sagv(dev_priv)) |
3193 | return 0; | |
3194 | ||
3195 | if (dev_priv->sagv_status == I915_SAGV_DISABLED) | |
656d1b89 L |
3196 | return 0; |
3197 | ||
3198 | DRM_DEBUG_KMS("Disabling the SAGV\n"); | |
3199 | mutex_lock(&dev_priv->rps.hw_lock); | |
3200 | ||
3201 | /* bspec says to keep retrying for at least 1 ms */ | |
b3b8e999 ID |
3202 | ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL, |
3203 | GEN9_SAGV_DISABLE, | |
3204 | GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, | |
3205 | 1); | |
656d1b89 L |
3206 | mutex_unlock(&dev_priv->rps.hw_lock); |
3207 | ||
656d1b89 L |
3208 | /* |
3209 | * Some skl systems, pre-release machines in particular, | |
3210 | * don't actually have an SAGV. | |
3211 | */ | |
b3b8e999 | 3212 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3213 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3214 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 | 3215 | return 0; |
b3b8e999 ID |
3216 | } else if (ret < 0) { |
3217 | DRM_ERROR("Failed to disable the SAGV (%d)\n", ret); | |
3218 | return ret; | |
656d1b89 L |
3219 | } |
3220 | ||
16dcdc4e | 3221 | dev_priv->sagv_status = I915_SAGV_DISABLED; |
656d1b89 L |
3222 | return 0; |
3223 | } | |
3224 | ||
16dcdc4e | 3225 | bool intel_can_enable_sagv(struct drm_atomic_state *state) |
656d1b89 L |
3226 | { |
3227 | struct drm_device *dev = state->dev; | |
3228 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3229 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
ee3d532f PZ |
3230 | struct intel_crtc *crtc; |
3231 | struct intel_plane *plane; | |
d8c0fafc | 3232 | struct intel_crtc_state *cstate; |
656d1b89 | 3233 | enum pipe pipe; |
d8c0fafc | 3234 | int level, latency; |
656d1b89 | 3235 | |
56feca91 PZ |
3236 | if (!intel_has_sagv(dev_priv)) |
3237 | return false; | |
3238 | ||
656d1b89 L |
3239 | /* |
3240 | * SKL workaround: bspec recommends we disable the SAGV when we have | |
3241 | * more then one pipe enabled | |
3242 | * | |
3243 | * If there are no active CRTCs, no additional checks need be performed | |
3244 | */ | |
3245 | if (hweight32(intel_state->active_crtcs) == 0) | |
3246 | return true; | |
3247 | else if (hweight32(intel_state->active_crtcs) > 1) | |
3248 | return false; | |
3249 | ||
3250 | /* Since we're now guaranteed to only have one active CRTC... */ | |
3251 | pipe = ffs(intel_state->active_crtcs) - 1; | |
98187836 | 3252 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
d8c0fafc | 3253 | cstate = to_intel_crtc_state(crtc->base.state); |
656d1b89 | 3254 | |
c89cadd5 | 3255 | if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
656d1b89 L |
3256 | return false; |
3257 | ||
ee3d532f | 3258 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
d5cdfdf5 VS |
3259 | struct skl_plane_wm *wm = |
3260 | &cstate->wm.skl.optimal.planes[plane->id]; | |
ee3d532f | 3261 | |
656d1b89 | 3262 | /* Skip this plane if it's not enabled */ |
d8c0fafc | 3263 | if (!wm->wm[0].plane_en) |
656d1b89 L |
3264 | continue; |
3265 | ||
3266 | /* Find the highest enabled wm level for this plane */ | |
5db94019 | 3267 | for (level = ilk_wm_max_level(dev_priv); |
d8c0fafc | 3268 | !wm->wm[level].plane_en; --level) |
656d1b89 L |
3269 | { } |
3270 | ||
ee3d532f PZ |
3271 | latency = dev_priv->wm.skl_latency[level]; |
3272 | ||
3273 | if (skl_needs_memory_bw_wa(intel_state) && | |
bae781b2 | 3274 | plane->base.state->fb->modifier == |
ee3d532f PZ |
3275 | I915_FORMAT_MOD_X_TILED) |
3276 | latency += 15; | |
3277 | ||
656d1b89 L |
3278 | /* |
3279 | * If any of the planes on this pipe don't enable wm levels | |
3280 | * that incur memory latencies higher then 30µs we can't enable | |
3281 | * the SAGV | |
3282 | */ | |
ee3d532f | 3283 | if (latency < SKL_SAGV_BLOCK_TIME) |
656d1b89 L |
3284 | return false; |
3285 | } | |
3286 | ||
3287 | return true; | |
3288 | } | |
3289 | ||
b9cec075 DL |
3290 | static void |
3291 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
024c9045 | 3292 | const struct intel_crtc_state *cstate, |
c107acfe MR |
3293 | struct skl_ddb_entry *alloc, /* out */ |
3294 | int *num_active /* out */) | |
b9cec075 | 3295 | { |
c107acfe MR |
3296 | struct drm_atomic_state *state = cstate->base.state; |
3297 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
3298 | struct drm_i915_private *dev_priv = to_i915(dev); | |
024c9045 | 3299 | struct drm_crtc *for_crtc = cstate->base.crtc; |
b9cec075 DL |
3300 | unsigned int pipe_size, ddb_size; |
3301 | int nth_active_pipe; | |
c107acfe | 3302 | |
a6d3460e | 3303 | if (WARN_ON(!state) || !cstate->base.active) { |
b9cec075 DL |
3304 | alloc->start = 0; |
3305 | alloc->end = 0; | |
a6d3460e | 3306 | *num_active = hweight32(dev_priv->active_crtcs); |
b9cec075 DL |
3307 | return; |
3308 | } | |
3309 | ||
a6d3460e MR |
3310 | if (intel_state->active_pipe_changes) |
3311 | *num_active = hweight32(intel_state->active_crtcs); | |
3312 | else | |
3313 | *num_active = hweight32(dev_priv->active_crtcs); | |
3314 | ||
6f3fff60 D |
3315 | ddb_size = INTEL_INFO(dev_priv)->ddb_size; |
3316 | WARN_ON(ddb_size == 0); | |
b9cec075 DL |
3317 | |
3318 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
3319 | ||
c107acfe | 3320 | /* |
a6d3460e MR |
3321 | * If the state doesn't change the active CRTC's, then there's |
3322 | * no need to recalculate; the existing pipe allocation limits | |
3323 | * should remain unchanged. Note that we're safe from racing | |
3324 | * commits since any racing commit that changes the active CRTC | |
3325 | * list would need to grab _all_ crtc locks, including the one | |
3326 | * we currently hold. | |
c107acfe | 3327 | */ |
a6d3460e | 3328 | if (!intel_state->active_pipe_changes) { |
512b5527 ML |
3329 | /* |
3330 | * alloc may be cleared by clear_intel_crtc_state, | |
3331 | * copy from old state to be sure | |
3332 | */ | |
3333 | *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; | |
a6d3460e | 3334 | return; |
c107acfe | 3335 | } |
a6d3460e MR |
3336 | |
3337 | nth_active_pipe = hweight32(intel_state->active_crtcs & | |
3338 | (drm_crtc_mask(for_crtc) - 1)); | |
3339 | pipe_size = ddb_size / hweight32(intel_state->active_crtcs); | |
3340 | alloc->start = nth_active_pipe * ddb_size / *num_active; | |
3341 | alloc->end = alloc->start + pipe_size; | |
b9cec075 DL |
3342 | } |
3343 | ||
c107acfe | 3344 | static unsigned int skl_cursor_allocation(int num_active) |
b9cec075 | 3345 | { |
c107acfe | 3346 | if (num_active == 1) |
b9cec075 DL |
3347 | return 32; |
3348 | ||
3349 | return 8; | |
3350 | } | |
3351 | ||
a269c583 DL |
3352 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
3353 | { | |
3354 | entry->start = reg & 0x3ff; | |
3355 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
3356 | if (entry->end) |
3357 | entry->end += 1; | |
a269c583 DL |
3358 | } |
3359 | ||
08db6652 DL |
3360 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
3361 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 3362 | { |
d5cdfdf5 | 3363 | struct intel_crtc *crtc; |
a269c583 | 3364 | |
b10f1b20 ML |
3365 | memset(ddb, 0, sizeof(*ddb)); |
3366 | ||
d5cdfdf5 | 3367 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
4d800030 | 3368 | enum intel_display_power_domain power_domain; |
d5cdfdf5 VS |
3369 | enum plane_id plane_id; |
3370 | enum pipe pipe = crtc->pipe; | |
4d800030 ID |
3371 | |
3372 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
3373 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b10f1b20 ML |
3374 | continue; |
3375 | ||
d5cdfdf5 VS |
3376 | for_each_plane_id_on_crtc(crtc, plane_id) { |
3377 | u32 val; | |
3378 | ||
3379 | if (plane_id != PLANE_CURSOR) | |
3380 | val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); | |
3381 | else | |
3382 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
a269c583 | 3383 | |
d5cdfdf5 VS |
3384 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val); |
3385 | } | |
4d800030 ID |
3386 | |
3387 | intel_display_power_put(dev_priv, power_domain); | |
a269c583 DL |
3388 | } |
3389 | } | |
3390 | ||
9c2f7a9d KM |
3391 | /* |
3392 | * Determines the downscale amount of a plane for the purposes of watermark calculations. | |
3393 | * The bspec defines downscale amount as: | |
3394 | * | |
3395 | * """ | |
3396 | * Horizontal down scale amount = maximum[1, Horizontal source size / | |
3397 | * Horizontal destination size] | |
3398 | * Vertical down scale amount = maximum[1, Vertical source size / | |
3399 | * Vertical destination size] | |
3400 | * Total down scale amount = Horizontal down scale amount * | |
3401 | * Vertical down scale amount | |
3402 | * """ | |
3403 | * | |
3404 | * Return value is provided in 16.16 fixed point form to retain fractional part. | |
3405 | * Caller should take care of dividing & rounding off the value. | |
3406 | */ | |
3407 | static uint32_t | |
93aa2a1c VS |
3408 | skl_plane_downscale_amount(const struct intel_crtc_state *cstate, |
3409 | const struct intel_plane_state *pstate) | |
9c2f7a9d | 3410 | { |
93aa2a1c | 3411 | struct intel_plane *plane = to_intel_plane(pstate->base.plane); |
9c2f7a9d KM |
3412 | uint32_t downscale_h, downscale_w; |
3413 | uint32_t src_w, src_h, dst_w, dst_h; | |
3414 | ||
93aa2a1c | 3415 | if (WARN_ON(!intel_wm_plane_visible(cstate, pstate))) |
9c2f7a9d KM |
3416 | return DRM_PLANE_HELPER_NO_SCALING; |
3417 | ||
3418 | /* n.b., src is 16.16 fixed point, dst is whole integer */ | |
93aa2a1c VS |
3419 | if (plane->id == PLANE_CURSOR) { |
3420 | src_w = pstate->base.src_w; | |
3421 | src_h = pstate->base.src_h; | |
3422 | dst_w = pstate->base.crtc_w; | |
3423 | dst_h = pstate->base.crtc_h; | |
3424 | } else { | |
3425 | src_w = drm_rect_width(&pstate->base.src); | |
3426 | src_h = drm_rect_height(&pstate->base.src); | |
3427 | dst_w = drm_rect_width(&pstate->base.dst); | |
3428 | dst_h = drm_rect_height(&pstate->base.dst); | |
3429 | } | |
3430 | ||
bd2ef25d | 3431 | if (drm_rotation_90_or_270(pstate->base.rotation)) |
9c2f7a9d KM |
3432 | swap(dst_w, dst_h); |
3433 | ||
3434 | downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING); | |
3435 | downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING); | |
3436 | ||
3437 | /* Provide result in 16.16 fixed point */ | |
3438 | return (uint64_t)downscale_w * downscale_h >> 16; | |
3439 | } | |
3440 | ||
b9cec075 | 3441 | static unsigned int |
024c9045 MR |
3442 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
3443 | const struct drm_plane_state *pstate, | |
3444 | int y) | |
b9cec075 | 3445 | { |
93aa2a1c | 3446 | struct intel_plane *plane = to_intel_plane(pstate->plane); |
a280f7dd | 3447 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); |
8d19d7d9 | 3448 | uint32_t down_scale_amount, data_rate; |
a280f7dd | 3449 | uint32_t width = 0, height = 0; |
8305494e VS |
3450 | struct drm_framebuffer *fb; |
3451 | u32 format; | |
a1de91e5 | 3452 | |
936e71e3 | 3453 | if (!intel_pstate->base.visible) |
a1de91e5 | 3454 | return 0; |
8305494e VS |
3455 | |
3456 | fb = pstate->fb; | |
438b74a5 | 3457 | format = fb->format->format; |
8305494e | 3458 | |
93aa2a1c | 3459 | if (plane->id == PLANE_CURSOR) |
a1de91e5 MR |
3460 | return 0; |
3461 | if (y && format != DRM_FORMAT_NV12) | |
3462 | return 0; | |
a280f7dd | 3463 | |
936e71e3 VS |
3464 | width = drm_rect_width(&intel_pstate->base.src) >> 16; |
3465 | height = drm_rect_height(&intel_pstate->base.src) >> 16; | |
a280f7dd | 3466 | |
bd2ef25d | 3467 | if (drm_rotation_90_or_270(pstate->rotation)) |
a280f7dd | 3468 | swap(width, height); |
2cd601c6 CK |
3469 | |
3470 | /* for planar format */ | |
a1de91e5 | 3471 | if (format == DRM_FORMAT_NV12) { |
2cd601c6 | 3472 | if (y) /* y-plane data rate */ |
8d19d7d9 | 3473 | data_rate = width * height * |
353c8598 | 3474 | fb->format->cpp[0]; |
2cd601c6 | 3475 | else /* uv-plane data rate */ |
8d19d7d9 | 3476 | data_rate = (width / 2) * (height / 2) * |
353c8598 | 3477 | fb->format->cpp[1]; |
8d19d7d9 KM |
3478 | } else { |
3479 | /* for packed formats */ | |
353c8598 | 3480 | data_rate = width * height * fb->format->cpp[0]; |
2cd601c6 CK |
3481 | } |
3482 | ||
93aa2a1c | 3483 | down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate); |
8d19d7d9 KM |
3484 | |
3485 | return (uint64_t)data_rate * down_scale_amount >> 16; | |
b9cec075 DL |
3486 | } |
3487 | ||
3488 | /* | |
3489 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
3490 | * a 8192x4096@32bpp framebuffer: | |
3491 | * 3 * 4096 * 8192 * 4 < 2^32 | |
3492 | */ | |
3493 | static unsigned int | |
1e6ee542 ML |
3494 | skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate, |
3495 | unsigned *plane_data_rate, | |
3496 | unsigned *plane_y_data_rate) | |
b9cec075 | 3497 | { |
9c74d826 MR |
3498 | struct drm_crtc_state *cstate = &intel_cstate->base; |
3499 | struct drm_atomic_state *state = cstate->state; | |
c8fe32c1 | 3500 | struct drm_plane *plane; |
c8fe32c1 | 3501 | const struct drm_plane_state *pstate; |
d5cdfdf5 | 3502 | unsigned int total_data_rate = 0; |
a6d3460e MR |
3503 | |
3504 | if (WARN_ON(!state)) | |
3505 | return 0; | |
b9cec075 | 3506 | |
a1de91e5 | 3507 | /* Calculate and cache data rate for each plane */ |
c8fe32c1 | 3508 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) { |
d5cdfdf5 VS |
3509 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3510 | unsigned int rate; | |
a6d3460e | 3511 | |
a6d3460e MR |
3512 | /* packed/uv */ |
3513 | rate = skl_plane_relative_data_rate(intel_cstate, | |
3514 | pstate, 0); | |
d5cdfdf5 | 3515 | plane_data_rate[plane_id] = rate; |
1e6ee542 ML |
3516 | |
3517 | total_data_rate += rate; | |
a6d3460e MR |
3518 | |
3519 | /* y-plane */ | |
3520 | rate = skl_plane_relative_data_rate(intel_cstate, | |
3521 | pstate, 1); | |
d5cdfdf5 | 3522 | plane_y_data_rate[plane_id] = rate; |
024c9045 | 3523 | |
1e6ee542 | 3524 | total_data_rate += rate; |
b9cec075 DL |
3525 | } |
3526 | ||
3527 | return total_data_rate; | |
3528 | } | |
3529 | ||
cbcfd14b KM |
3530 | static uint16_t |
3531 | skl_ddb_min_alloc(const struct drm_plane_state *pstate, | |
3532 | const int y) | |
3533 | { | |
3534 | struct drm_framebuffer *fb = pstate->fb; | |
3535 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); | |
3536 | uint32_t src_w, src_h; | |
3537 | uint32_t min_scanlines = 8; | |
3538 | uint8_t plane_bpp; | |
3539 | ||
3540 | if (WARN_ON(!fb)) | |
3541 | return 0; | |
3542 | ||
3543 | /* For packed formats, no y-plane, return 0 */ | |
438b74a5 | 3544 | if (y && fb->format->format != DRM_FORMAT_NV12) |
cbcfd14b KM |
3545 | return 0; |
3546 | ||
3547 | /* For Non Y-tile return 8-blocks */ | |
bae781b2 VS |
3548 | if (fb->modifier != I915_FORMAT_MOD_Y_TILED && |
3549 | fb->modifier != I915_FORMAT_MOD_Yf_TILED) | |
cbcfd14b KM |
3550 | return 8; |
3551 | ||
936e71e3 VS |
3552 | src_w = drm_rect_width(&intel_pstate->base.src) >> 16; |
3553 | src_h = drm_rect_height(&intel_pstate->base.src) >> 16; | |
cbcfd14b | 3554 | |
bd2ef25d | 3555 | if (drm_rotation_90_or_270(pstate->rotation)) |
cbcfd14b KM |
3556 | swap(src_w, src_h); |
3557 | ||
3558 | /* Halve UV plane width and height for NV12 */ | |
438b74a5 | 3559 | if (fb->format->format == DRM_FORMAT_NV12 && !y) { |
cbcfd14b KM |
3560 | src_w /= 2; |
3561 | src_h /= 2; | |
3562 | } | |
3563 | ||
438b74a5 | 3564 | if (fb->format->format == DRM_FORMAT_NV12 && !y) |
353c8598 | 3565 | plane_bpp = fb->format->cpp[1]; |
cbcfd14b | 3566 | else |
353c8598 | 3567 | plane_bpp = fb->format->cpp[0]; |
cbcfd14b | 3568 | |
bd2ef25d | 3569 | if (drm_rotation_90_or_270(pstate->rotation)) { |
cbcfd14b KM |
3570 | switch (plane_bpp) { |
3571 | case 1: | |
3572 | min_scanlines = 32; | |
3573 | break; | |
3574 | case 2: | |
3575 | min_scanlines = 16; | |
3576 | break; | |
3577 | case 4: | |
3578 | min_scanlines = 8; | |
3579 | break; | |
3580 | case 8: | |
3581 | min_scanlines = 4; | |
3582 | break; | |
3583 | default: | |
3584 | WARN(1, "Unsupported pixel depth %u for rotation", | |
3585 | plane_bpp); | |
3586 | min_scanlines = 32; | |
3587 | } | |
3588 | } | |
3589 | ||
3590 | return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3; | |
3591 | } | |
3592 | ||
49845a7a ML |
3593 | static void |
3594 | skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active, | |
3595 | uint16_t *minimum, uint16_t *y_minimum) | |
3596 | { | |
3597 | const struct drm_plane_state *pstate; | |
3598 | struct drm_plane *plane; | |
3599 | ||
3600 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) { | |
d5cdfdf5 | 3601 | enum plane_id plane_id = to_intel_plane(plane)->id; |
49845a7a | 3602 | |
d5cdfdf5 | 3603 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
3604 | continue; |
3605 | ||
3606 | if (!pstate->visible) | |
3607 | continue; | |
3608 | ||
d5cdfdf5 VS |
3609 | minimum[plane_id] = skl_ddb_min_alloc(pstate, 0); |
3610 | y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1); | |
49845a7a ML |
3611 | } |
3612 | ||
3613 | minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active); | |
3614 | } | |
3615 | ||
c107acfe | 3616 | static int |
024c9045 | 3617 | skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, |
b9cec075 DL |
3618 | struct skl_ddb_allocation *ddb /* out */) |
3619 | { | |
c107acfe | 3620 | struct drm_atomic_state *state = cstate->base.state; |
024c9045 | 3621 | struct drm_crtc *crtc = cstate->base.crtc; |
b9cec075 DL |
3622 | struct drm_device *dev = crtc->dev; |
3623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3624 | enum pipe pipe = intel_crtc->pipe; | |
ce0ba283 | 3625 | struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb; |
49845a7a | 3626 | uint16_t alloc_size, start; |
fefdd810 ML |
3627 | uint16_t minimum[I915_MAX_PLANES] = {}; |
3628 | uint16_t y_minimum[I915_MAX_PLANES] = {}; | |
b9cec075 | 3629 | unsigned int total_data_rate; |
d5cdfdf5 | 3630 | enum plane_id plane_id; |
c107acfe | 3631 | int num_active; |
1e6ee542 ML |
3632 | unsigned plane_data_rate[I915_MAX_PLANES] = {}; |
3633 | unsigned plane_y_data_rate[I915_MAX_PLANES] = {}; | |
b9cec075 | 3634 | |
5a920b85 PZ |
3635 | /* Clear the partitioning for disabled planes. */ |
3636 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
3637 | memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe])); | |
3638 | ||
a6d3460e MR |
3639 | if (WARN_ON(!state)) |
3640 | return 0; | |
3641 | ||
c107acfe | 3642 | if (!cstate->base.active) { |
ce0ba283 | 3643 | alloc->start = alloc->end = 0; |
c107acfe MR |
3644 | return 0; |
3645 | } | |
3646 | ||
a6d3460e | 3647 | skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active); |
34bb56af | 3648 | alloc_size = skl_ddb_entry_size(alloc); |
b9cec075 DL |
3649 | if (alloc_size == 0) { |
3650 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
c107acfe | 3651 | return 0; |
b9cec075 DL |
3652 | } |
3653 | ||
49845a7a | 3654 | skl_ddb_calc_min(cstate, num_active, minimum, y_minimum); |
a6d3460e | 3655 | |
49845a7a ML |
3656 | /* |
3657 | * 1. Allocate the mininum required blocks for each active plane | |
3658 | * and allocate the cursor, it doesn't require extra allocation | |
3659 | * proportional to the data rate. | |
3660 | */ | |
80958155 | 3661 | |
d5cdfdf5 VS |
3662 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
3663 | alloc_size -= minimum[plane_id]; | |
3664 | alloc_size -= y_minimum[plane_id]; | |
80958155 DL |
3665 | } |
3666 | ||
49845a7a ML |
3667 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR]; |
3668 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; | |
3669 | ||
b9cec075 | 3670 | /* |
80958155 DL |
3671 | * 2. Distribute the remaining space in proportion to the amount of |
3672 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
3673 | * |
3674 | * FIXME: we may not allocate every single block here. | |
3675 | */ | |
1e6ee542 ML |
3676 | total_data_rate = skl_get_total_relative_data_rate(cstate, |
3677 | plane_data_rate, | |
3678 | plane_y_data_rate); | |
a1de91e5 | 3679 | if (total_data_rate == 0) |
c107acfe | 3680 | return 0; |
b9cec075 | 3681 | |
34bb56af | 3682 | start = alloc->start; |
d5cdfdf5 | 3683 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
2cd601c6 CK |
3684 | unsigned int data_rate, y_data_rate; |
3685 | uint16_t plane_blocks, y_plane_blocks = 0; | |
b9cec075 | 3686 | |
d5cdfdf5 | 3687 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
3688 | continue; |
3689 | ||
d5cdfdf5 | 3690 | data_rate = plane_data_rate[plane_id]; |
b9cec075 DL |
3691 | |
3692 | /* | |
2cd601c6 | 3693 | * allocation for (packed formats) or (uv-plane part of planar format): |
b9cec075 DL |
3694 | * promote the expression to 64 bits to avoid overflowing, the |
3695 | * result is < available as data_rate / total_data_rate < 1 | |
3696 | */ | |
d5cdfdf5 | 3697 | plane_blocks = minimum[plane_id]; |
80958155 DL |
3698 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
3699 | total_data_rate); | |
b9cec075 | 3700 | |
c107acfe MR |
3701 | /* Leave disabled planes at (0,0) */ |
3702 | if (data_rate) { | |
d5cdfdf5 VS |
3703 | ddb->plane[pipe][plane_id].start = start; |
3704 | ddb->plane[pipe][plane_id].end = start + plane_blocks; | |
c107acfe | 3705 | } |
b9cec075 DL |
3706 | |
3707 | start += plane_blocks; | |
2cd601c6 CK |
3708 | |
3709 | /* | |
3710 | * allocation for y_plane part of planar format: | |
3711 | */ | |
d5cdfdf5 | 3712 | y_data_rate = plane_y_data_rate[plane_id]; |
a1de91e5 | 3713 | |
d5cdfdf5 | 3714 | y_plane_blocks = y_minimum[plane_id]; |
a1de91e5 MR |
3715 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
3716 | total_data_rate); | |
2cd601c6 | 3717 | |
c107acfe | 3718 | if (y_data_rate) { |
d5cdfdf5 VS |
3719 | ddb->y_plane[pipe][plane_id].start = start; |
3720 | ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks; | |
c107acfe | 3721 | } |
a1de91e5 MR |
3722 | |
3723 | start += y_plane_blocks; | |
b9cec075 DL |
3724 | } |
3725 | ||
c107acfe | 3726 | return 0; |
b9cec075 DL |
3727 | } |
3728 | ||
2d41c0b5 PB |
3729 | /* |
3730 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
ac484963 | 3731 | * for the read latency) and cpp should always be <= 8, so that |
2d41c0b5 PB |
3732 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
3733 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
3734 | */ | |
b95320bd MK |
3735 | static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, |
3736 | uint32_t latency) | |
2d41c0b5 | 3737 | { |
b95320bd MK |
3738 | uint32_t wm_intermediate_val; |
3739 | uint_fixed_16_16_t ret; | |
2d41c0b5 PB |
3740 | |
3741 | if (latency == 0) | |
b95320bd | 3742 | return FP_16_16_MAX; |
2d41c0b5 | 3743 | |
b95320bd MK |
3744 | wm_intermediate_val = latency * pixel_rate * cpp; |
3745 | ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512); | |
2d41c0b5 PB |
3746 | return ret; |
3747 | } | |
3748 | ||
b95320bd MK |
3749 | static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate, |
3750 | uint32_t pipe_htotal, | |
3751 | uint32_t latency, | |
3752 | uint_fixed_16_16_t plane_blocks_per_line) | |
2d41c0b5 | 3753 | { |
d4c2aa60 | 3754 | uint32_t wm_intermediate_val; |
b95320bd | 3755 | uint_fixed_16_16_t ret; |
2d41c0b5 PB |
3756 | |
3757 | if (latency == 0) | |
b95320bd | 3758 | return FP_16_16_MAX; |
2d41c0b5 | 3759 | |
2d41c0b5 | 3760 | wm_intermediate_val = latency * pixel_rate; |
b95320bd MK |
3761 | wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, |
3762 | pipe_htotal * 1000); | |
3763 | ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line); | |
2d41c0b5 PB |
3764 | return ret; |
3765 | } | |
3766 | ||
9c2f7a9d KM |
3767 | static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, |
3768 | struct intel_plane_state *pstate) | |
3769 | { | |
3770 | uint64_t adjusted_pixel_rate; | |
3771 | uint64_t downscale_amount; | |
3772 | uint64_t pixel_rate; | |
3773 | ||
3774 | /* Shouldn't reach here on disabled planes... */ | |
93aa2a1c | 3775 | if (WARN_ON(!intel_wm_plane_visible(cstate, pstate))) |
9c2f7a9d KM |
3776 | return 0; |
3777 | ||
3778 | /* | |
3779 | * Adjusted plane pixel rate is just the pipe's adjusted pixel rate | |
3780 | * with additional adjustments for plane-specific scaling. | |
3781 | */ | |
a7d1b3f4 | 3782 | adjusted_pixel_rate = cstate->pixel_rate; |
93aa2a1c | 3783 | downscale_amount = skl_plane_downscale_amount(cstate, pstate); |
9c2f7a9d KM |
3784 | |
3785 | pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; | |
3786 | WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0)); | |
3787 | ||
3788 | return pixel_rate; | |
3789 | } | |
3790 | ||
55994c2c MR |
3791 | static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
3792 | struct intel_crtc_state *cstate, | |
3793 | struct intel_plane_state *intel_pstate, | |
3794 | uint16_t ddb_allocation, | |
3795 | int level, | |
3796 | uint16_t *out_blocks, /* out */ | |
3797 | uint8_t *out_lines, /* out */ | |
3798 | bool *enabled /* out */) | |
2d41c0b5 | 3799 | { |
93aa2a1c | 3800 | struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane); |
33815fa5 MR |
3801 | struct drm_plane_state *pstate = &intel_pstate->base; |
3802 | struct drm_framebuffer *fb = pstate->fb; | |
d4c2aa60 | 3803 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
b95320bd MK |
3804 | uint_fixed_16_16_t method1, method2; |
3805 | uint_fixed_16_16_t plane_blocks_per_line; | |
3806 | uint_fixed_16_16_t selected_result; | |
3807 | uint32_t interm_pbpl; | |
3808 | uint32_t plane_bytes_per_line; | |
d4c2aa60 | 3809 | uint32_t res_blocks, res_lines; |
ac484963 | 3810 | uint8_t cpp; |
a280f7dd | 3811 | uint32_t width = 0, height = 0; |
9c2f7a9d | 3812 | uint32_t plane_pixel_rate; |
b95320bd MK |
3813 | uint_fixed_16_16_t y_tile_minimum; |
3814 | uint32_t y_min_scanlines; | |
ee3d532f PZ |
3815 | struct intel_atomic_state *state = |
3816 | to_intel_atomic_state(cstate->base.state); | |
3817 | bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); | |
ef8a4fb4 | 3818 | bool y_tiled, x_tiled; |
2d41c0b5 | 3819 | |
93aa2a1c VS |
3820 | if (latency == 0 || |
3821 | !intel_wm_plane_visible(cstate, intel_pstate)) { | |
55994c2c MR |
3822 | *enabled = false; |
3823 | return 0; | |
3824 | } | |
2d41c0b5 | 3825 | |
ef8a4fb4 MK |
3826 | y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED || |
3827 | fb->modifier == I915_FORMAT_MOD_Yf_TILED; | |
3828 | x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; | |
3829 | ||
4b7b2331 MK |
3830 | /* Display WA #1141: kbl. */ |
3831 | if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled) | |
3832 | latency += 4; | |
3833 | ||
ef8a4fb4 | 3834 | if (apply_memory_bw_wa && x_tiled) |
ee3d532f PZ |
3835 | latency += 15; |
3836 | ||
93aa2a1c VS |
3837 | if (plane->id == PLANE_CURSOR) { |
3838 | width = intel_pstate->base.crtc_w; | |
3839 | height = intel_pstate->base.crtc_h; | |
3840 | } else { | |
3841 | width = drm_rect_width(&intel_pstate->base.src) >> 16; | |
3842 | height = drm_rect_height(&intel_pstate->base.src) >> 16; | |
3843 | } | |
a280f7dd | 3844 | |
bd2ef25d | 3845 | if (drm_rotation_90_or_270(pstate->rotation)) |
a280f7dd KM |
3846 | swap(width, height); |
3847 | ||
353c8598 | 3848 | cpp = fb->format->cpp[0]; |
9c2f7a9d KM |
3849 | plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate); |
3850 | ||
61d0a04d | 3851 | if (drm_rotation_90_or_270(pstate->rotation)) { |
438b74a5 | 3852 | int cpp = (fb->format->format == DRM_FORMAT_NV12) ? |
353c8598 VS |
3853 | fb->format->cpp[1] : |
3854 | fb->format->cpp[0]; | |
1186fa85 PZ |
3855 | |
3856 | switch (cpp) { | |
3857 | case 1: | |
3858 | y_min_scanlines = 16; | |
3859 | break; | |
3860 | case 2: | |
3861 | y_min_scanlines = 8; | |
3862 | break; | |
1186fa85 PZ |
3863 | case 4: |
3864 | y_min_scanlines = 4; | |
3865 | break; | |
86a462bc PZ |
3866 | default: |
3867 | MISSING_CASE(cpp); | |
3868 | return -EINVAL; | |
1186fa85 PZ |
3869 | } |
3870 | } else { | |
3871 | y_min_scanlines = 4; | |
3872 | } | |
3873 | ||
2ef32dee PZ |
3874 | if (apply_memory_bw_wa) |
3875 | y_min_scanlines *= 2; | |
3876 | ||
7a1a8aed | 3877 | plane_bytes_per_line = width * cpp; |
ef8a4fb4 | 3878 | if (y_tiled) { |
b95320bd MK |
3879 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * |
3880 | y_min_scanlines, 512); | |
7a1a8aed | 3881 | plane_blocks_per_line = |
b95320bd | 3882 | fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines); |
ef8a4fb4 | 3883 | } else if (x_tiled) { |
b95320bd MK |
3884 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3885 | plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); | |
ef8a4fb4 | 3886 | } else { |
b95320bd MK |
3887 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1; |
3888 | plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); | |
7a1a8aed PZ |
3889 | } |
3890 | ||
9c2f7a9d KM |
3891 | method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); |
3892 | method2 = skl_wm_method2(plane_pixel_rate, | |
024c9045 | 3893 | cstate->base.adjusted_mode.crtc_htotal, |
1186fa85 | 3894 | latency, |
7a1a8aed | 3895 | plane_blocks_per_line); |
2d41c0b5 | 3896 | |
b95320bd MK |
3897 | y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines, |
3898 | plane_blocks_per_line); | |
75676ed4 | 3899 | |
ef8a4fb4 | 3900 | if (y_tiled) { |
b95320bd | 3901 | selected_result = max_fixed_16_16(method2, y_tile_minimum); |
0fda6568 | 3902 | } else { |
f1db3eaf PZ |
3903 | if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) && |
3904 | (plane_bytes_per_line / 512 < 1)) | |
3905 | selected_result = method2; | |
b95320bd MK |
3906 | else if ((ddb_allocation / |
3907 | fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1) | |
3908 | selected_result = min_fixed_16_16(method1, method2); | |
0fda6568 TU |
3909 | else |
3910 | selected_result = method1; | |
3911 | } | |
2d41c0b5 | 3912 | |
b95320bd MK |
3913 | res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1; |
3914 | res_lines = DIV_ROUND_UP(selected_result.val, | |
3915 | plane_blocks_per_line.val); | |
e6d66171 | 3916 | |
0fda6568 | 3917 | if (level >= 1 && level <= 7) { |
ef8a4fb4 | 3918 | if (y_tiled) { |
b95320bd | 3919 | res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum); |
1186fa85 | 3920 | res_lines += y_min_scanlines; |
75676ed4 | 3921 | } else { |
0fda6568 | 3922 | res_blocks++; |
75676ed4 | 3923 | } |
0fda6568 | 3924 | } |
e6d66171 | 3925 | |
55994c2c MR |
3926 | if (res_blocks >= ddb_allocation || res_lines > 31) { |
3927 | *enabled = false; | |
6b6bada7 MR |
3928 | |
3929 | /* | |
3930 | * If there are no valid level 0 watermarks, then we can't | |
3931 | * support this display configuration. | |
3932 | */ | |
3933 | if (level) { | |
3934 | return 0; | |
3935 | } else { | |
d5cdfdf5 VS |
3936 | struct drm_plane *plane = pstate->plane; |
3937 | ||
6b6bada7 | 3938 | DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n"); |
d5cdfdf5 VS |
3939 | DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n", |
3940 | plane->base.id, plane->name, | |
6b6bada7 | 3941 | res_blocks, ddb_allocation, res_lines); |
6b6bada7 MR |
3942 | return -EINVAL; |
3943 | } | |
55994c2c | 3944 | } |
e6d66171 DL |
3945 | |
3946 | *out_blocks = res_blocks; | |
3947 | *out_lines = res_lines; | |
55994c2c | 3948 | *enabled = true; |
2d41c0b5 | 3949 | |
55994c2c | 3950 | return 0; |
2d41c0b5 PB |
3951 | } |
3952 | ||
f4a96752 MR |
3953 | static int |
3954 | skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
3955 | struct skl_ddb_allocation *ddb, | |
3956 | struct intel_crtc_state *cstate, | |
a62163e9 | 3957 | struct intel_plane *intel_plane, |
f4a96752 MR |
3958 | int level, |
3959 | struct skl_wm_level *result) | |
2d41c0b5 | 3960 | { |
f4a96752 | 3961 | struct drm_atomic_state *state = cstate->base.state; |
024c9045 | 3962 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
a62163e9 L |
3963 | struct drm_plane *plane = &intel_plane->base; |
3964 | struct intel_plane_state *intel_pstate = NULL; | |
2d41c0b5 | 3965 | uint16_t ddb_blocks; |
024c9045 | 3966 | enum pipe pipe = intel_crtc->pipe; |
55994c2c | 3967 | int ret; |
a62163e9 L |
3968 | |
3969 | if (state) | |
3970 | intel_pstate = | |
3971 | intel_atomic_get_existing_plane_state(state, | |
3972 | intel_plane); | |
024c9045 | 3973 | |
f4a96752 | 3974 | /* |
a62163e9 L |
3975 | * Note: If we start supporting multiple pending atomic commits against |
3976 | * the same planes/CRTC's in the future, plane->state will no longer be | |
3977 | * the correct pre-state to use for the calculations here and we'll | |
3978 | * need to change where we get the 'unchanged' plane data from. | |
3979 | * | |
3980 | * For now this is fine because we only allow one queued commit against | |
3981 | * a CRTC. Even if the plane isn't modified by this transaction and we | |
3982 | * don't have a plane lock, we still have the CRTC's lock, so we know | |
3983 | * that no other transactions are racing with us to update it. | |
f4a96752 | 3984 | */ |
a62163e9 L |
3985 | if (!intel_pstate) |
3986 | intel_pstate = to_intel_plane_state(plane->state); | |
f4a96752 | 3987 | |
a62163e9 | 3988 | WARN_ON(!intel_pstate->base.fb); |
f4a96752 | 3989 | |
d5cdfdf5 | 3990 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); |
2d41c0b5 | 3991 | |
a62163e9 L |
3992 | ret = skl_compute_plane_wm(dev_priv, |
3993 | cstate, | |
3994 | intel_pstate, | |
3995 | ddb_blocks, | |
3996 | level, | |
3997 | &result->plane_res_b, | |
3998 | &result->plane_res_l, | |
3999 | &result->plane_en); | |
4000 | if (ret) | |
4001 | return ret; | |
f4a96752 MR |
4002 | |
4003 | return 0; | |
2d41c0b5 PB |
4004 | } |
4005 | ||
407b50f3 | 4006 | static uint32_t |
024c9045 | 4007 | skl_compute_linetime_wm(struct intel_crtc_state *cstate) |
407b50f3 | 4008 | { |
a3a8986c MK |
4009 | struct drm_atomic_state *state = cstate->base.state; |
4010 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
30d1b5fe | 4011 | uint32_t pixel_rate; |
a3a8986c | 4012 | uint32_t linetime_wm; |
30d1b5fe | 4013 | |
024c9045 | 4014 | if (!cstate->base.active) |
407b50f3 DL |
4015 | return 0; |
4016 | ||
a7d1b3f4 | 4017 | pixel_rate = cstate->pixel_rate; |
30d1b5fe PZ |
4018 | |
4019 | if (WARN_ON(pixel_rate == 0)) | |
661abfc0 | 4020 | return 0; |
407b50f3 | 4021 | |
a3a8986c MK |
4022 | linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * |
4023 | 1000, pixel_rate); | |
4024 | ||
4025 | /* Display WA #1135: bxt. */ | |
4026 | if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled) | |
4027 | linetime_wm = DIV_ROUND_UP(linetime_wm, 2); | |
4028 | ||
4029 | return linetime_wm; | |
407b50f3 DL |
4030 | } |
4031 | ||
024c9045 | 4032 | static void skl_compute_transition_wm(struct intel_crtc_state *cstate, |
9414f563 | 4033 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 4034 | { |
024c9045 | 4035 | if (!cstate->base.active) |
407b50f3 | 4036 | return; |
9414f563 DL |
4037 | |
4038 | /* Until we know more, just disable transition WMs */ | |
a62163e9 | 4039 | trans_wm->plane_en = false; |
407b50f3 DL |
4040 | } |
4041 | ||
55994c2c MR |
4042 | static int skl_build_pipe_wm(struct intel_crtc_state *cstate, |
4043 | struct skl_ddb_allocation *ddb, | |
4044 | struct skl_pipe_wm *pipe_wm) | |
2d41c0b5 | 4045 | { |
024c9045 | 4046 | struct drm_device *dev = cstate->base.crtc->dev; |
fac5e23e | 4047 | const struct drm_i915_private *dev_priv = to_i915(dev); |
a62163e9 L |
4048 | struct intel_plane *intel_plane; |
4049 | struct skl_plane_wm *wm; | |
5db94019 | 4050 | int level, max_level = ilk_wm_max_level(dev_priv); |
55994c2c | 4051 | int ret; |
2d41c0b5 | 4052 | |
a62163e9 L |
4053 | /* |
4054 | * We'll only calculate watermarks for planes that are actually | |
4055 | * enabled, so make sure all other planes are set as disabled. | |
4056 | */ | |
4057 | memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes)); | |
4058 | ||
4059 | for_each_intel_plane_mask(&dev_priv->drm, | |
4060 | intel_plane, | |
4061 | cstate->base.plane_mask) { | |
d5cdfdf5 | 4062 | wm = &pipe_wm->planes[intel_plane->id]; |
a62163e9 L |
4063 | |
4064 | for (level = 0; level <= max_level; level++) { | |
4065 | ret = skl_compute_wm_level(dev_priv, ddb, cstate, | |
4066 | intel_plane, level, | |
4067 | &wm->wm[level]); | |
4068 | if (ret) | |
4069 | return ret; | |
4070 | } | |
4071 | skl_compute_transition_wm(cstate, &wm->trans_wm); | |
2d41c0b5 | 4072 | } |
024c9045 | 4073 | pipe_wm->linetime = skl_compute_linetime_wm(cstate); |
2d41c0b5 | 4074 | |
55994c2c | 4075 | return 0; |
2d41c0b5 PB |
4076 | } |
4077 | ||
f0f59a00 VS |
4078 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, |
4079 | i915_reg_t reg, | |
16160e3d DL |
4080 | const struct skl_ddb_entry *entry) |
4081 | { | |
4082 | if (entry->end) | |
4083 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
4084 | else | |
4085 | I915_WRITE(reg, 0); | |
4086 | } | |
4087 | ||
d8c0fafc | 4088 | static void skl_write_wm_level(struct drm_i915_private *dev_priv, |
4089 | i915_reg_t reg, | |
4090 | const struct skl_wm_level *level) | |
4091 | { | |
4092 | uint32_t val = 0; | |
4093 | ||
4094 | if (level->plane_en) { | |
4095 | val |= PLANE_WM_EN; | |
4096 | val |= level->plane_res_b; | |
4097 | val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; | |
4098 | } | |
4099 | ||
4100 | I915_WRITE(reg, val); | |
4101 | } | |
4102 | ||
d9348dec VS |
4103 | static void skl_write_plane_wm(struct intel_crtc *intel_crtc, |
4104 | const struct skl_plane_wm *wm, | |
4105 | const struct skl_ddb_allocation *ddb, | |
d5cdfdf5 | 4106 | enum plane_id plane_id) |
62e0fb88 L |
4107 | { |
4108 | struct drm_crtc *crtc = &intel_crtc->base; | |
4109 | struct drm_device *dev = crtc->dev; | |
4110 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4111 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4112 | enum pipe pipe = intel_crtc->pipe; |
4113 | ||
4114 | for (level = 0; level <= max_level; level++) { | |
d5cdfdf5 | 4115 | skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), |
d8c0fafc | 4116 | &wm->wm[level]); |
62e0fb88 | 4117 | } |
d5cdfdf5 | 4118 | skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), |
d8c0fafc | 4119 | &wm->trans_wm); |
27082493 | 4120 | |
d5cdfdf5 VS |
4121 | skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), |
4122 | &ddb->plane[pipe][plane_id]); | |
4123 | skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id), | |
4124 | &ddb->y_plane[pipe][plane_id]); | |
62e0fb88 L |
4125 | } |
4126 | ||
d9348dec VS |
4127 | static void skl_write_cursor_wm(struct intel_crtc *intel_crtc, |
4128 | const struct skl_plane_wm *wm, | |
4129 | const struct skl_ddb_allocation *ddb) | |
62e0fb88 L |
4130 | { |
4131 | struct drm_crtc *crtc = &intel_crtc->base; | |
4132 | struct drm_device *dev = crtc->dev; | |
4133 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4134 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4135 | enum pipe pipe = intel_crtc->pipe; |
4136 | ||
4137 | for (level = 0; level <= max_level; level++) { | |
d8c0fafc | 4138 | skl_write_wm_level(dev_priv, CUR_WM(pipe, level), |
4139 | &wm->wm[level]); | |
62e0fb88 | 4140 | } |
d8c0fafc | 4141 | skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); |
5d374d96 | 4142 | |
27082493 | 4143 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
d8c0fafc | 4144 | &ddb->plane[pipe][PLANE_CURSOR]); |
2d41c0b5 PB |
4145 | } |
4146 | ||
45ece230 | 4147 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
4148 | const struct skl_wm_level *l2) | |
4149 | { | |
4150 | if (l1->plane_en != l2->plane_en) | |
4151 | return false; | |
4152 | ||
4153 | /* If both planes aren't enabled, the rest shouldn't matter */ | |
4154 | if (!l1->plane_en) | |
4155 | return true; | |
4156 | ||
4157 | return (l1->plane_res_l == l2->plane_res_l && | |
4158 | l1->plane_res_b == l2->plane_res_b); | |
4159 | } | |
4160 | ||
27082493 L |
4161 | static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, |
4162 | const struct skl_ddb_entry *b) | |
0e8fb7ba | 4163 | { |
27082493 | 4164 | return a->start < b->end && b->start < a->end; |
0e8fb7ba DL |
4165 | } |
4166 | ||
5eff503b ML |
4167 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, |
4168 | const struct skl_ddb_entry *ddb, | |
4169 | int ignore) | |
0e8fb7ba | 4170 | { |
ce0ba283 | 4171 | int i; |
0e8fb7ba | 4172 | |
5eff503b ML |
4173 | for (i = 0; i < I915_MAX_PIPES; i++) |
4174 | if (i != ignore && entries[i] && | |
4175 | skl_ddb_entries_overlap(ddb, entries[i])) | |
27082493 | 4176 | return true; |
0e8fb7ba | 4177 | |
27082493 | 4178 | return false; |
0e8fb7ba DL |
4179 | } |
4180 | ||
55994c2c | 4181 | static int skl_update_pipe_wm(struct drm_crtc_state *cstate, |
03af79e0 | 4182 | const struct skl_pipe_wm *old_pipe_wm, |
55994c2c | 4183 | struct skl_pipe_wm *pipe_wm, /* out */ |
03af79e0 | 4184 | struct skl_ddb_allocation *ddb, /* out */ |
55994c2c | 4185 | bool *changed /* out */) |
2d41c0b5 | 4186 | { |
f4a96752 | 4187 | struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate); |
55994c2c | 4188 | int ret; |
2d41c0b5 | 4189 | |
55994c2c MR |
4190 | ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm); |
4191 | if (ret) | |
4192 | return ret; | |
2d41c0b5 | 4193 | |
03af79e0 | 4194 | if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm))) |
55994c2c MR |
4195 | *changed = false; |
4196 | else | |
4197 | *changed = true; | |
2d41c0b5 | 4198 | |
55994c2c | 4199 | return 0; |
2d41c0b5 PB |
4200 | } |
4201 | ||
9b613022 MR |
4202 | static uint32_t |
4203 | pipes_modified(struct drm_atomic_state *state) | |
4204 | { | |
4205 | struct drm_crtc *crtc; | |
4206 | struct drm_crtc_state *cstate; | |
4207 | uint32_t i, ret = 0; | |
4208 | ||
6ebdb5a0 | 4209 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
9b613022 MR |
4210 | ret |= drm_crtc_mask(crtc); |
4211 | ||
4212 | return ret; | |
4213 | } | |
4214 | ||
bb7791bd | 4215 | static int |
7f60e200 PZ |
4216 | skl_ddb_add_affected_planes(struct intel_crtc_state *cstate) |
4217 | { | |
4218 | struct drm_atomic_state *state = cstate->base.state; | |
4219 | struct drm_device *dev = state->dev; | |
4220 | struct drm_crtc *crtc = cstate->base.crtc; | |
4221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4222 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4223 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4224 | struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
4225 | struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
4226 | struct drm_plane_state *plane_state; | |
4227 | struct drm_plane *plane; | |
4228 | enum pipe pipe = intel_crtc->pipe; | |
7f60e200 PZ |
4229 | |
4230 | WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc)); | |
4231 | ||
220b0965 | 4232 | drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) { |
d5cdfdf5 | 4233 | enum plane_id plane_id = to_intel_plane(plane)->id; |
7f60e200 | 4234 | |
d5cdfdf5 VS |
4235 | if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id], |
4236 | &new_ddb->plane[pipe][plane_id]) && | |
4237 | skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id], | |
4238 | &new_ddb->y_plane[pipe][plane_id])) | |
7f60e200 PZ |
4239 | continue; |
4240 | ||
4241 | plane_state = drm_atomic_get_plane_state(state, plane); | |
4242 | if (IS_ERR(plane_state)) | |
4243 | return PTR_ERR(plane_state); | |
4244 | } | |
4245 | ||
4246 | return 0; | |
4247 | } | |
4248 | ||
98d39494 MR |
4249 | static int |
4250 | skl_compute_ddb(struct drm_atomic_state *state) | |
4251 | { | |
4252 | struct drm_device *dev = state->dev; | |
4253 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4254 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4255 | struct intel_crtc *intel_crtc; | |
734fa01f | 4256 | struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb; |
9b613022 | 4257 | uint32_t realloc_pipes = pipes_modified(state); |
98d39494 MR |
4258 | int ret; |
4259 | ||
4260 | /* | |
4261 | * If this is our first atomic update following hardware readout, | |
4262 | * we can't trust the DDB that the BIOS programmed for us. Let's | |
4263 | * pretend that all pipes switched active status so that we'll | |
4264 | * ensure a full DDB recompute. | |
4265 | */ | |
1b54a880 MR |
4266 | if (dev_priv->wm.distrust_bios_wm) { |
4267 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, | |
4268 | state->acquire_ctx); | |
4269 | if (ret) | |
4270 | return ret; | |
4271 | ||
98d39494 MR |
4272 | intel_state->active_pipe_changes = ~0; |
4273 | ||
1b54a880 MR |
4274 | /* |
4275 | * We usually only initialize intel_state->active_crtcs if we | |
4276 | * we're doing a modeset; make sure this field is always | |
4277 | * initialized during the sanitization process that happens | |
4278 | * on the first commit too. | |
4279 | */ | |
4280 | if (!intel_state->modeset) | |
4281 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
4282 | } | |
4283 | ||
98d39494 MR |
4284 | /* |
4285 | * If the modeset changes which CRTC's are active, we need to | |
4286 | * recompute the DDB allocation for *all* active pipes, even | |
4287 | * those that weren't otherwise being modified in any way by this | |
4288 | * atomic commit. Due to the shrinking of the per-pipe allocations | |
4289 | * when new active CRTC's are added, it's possible for a pipe that | |
4290 | * we were already using and aren't changing at all here to suddenly | |
4291 | * become invalid if its DDB needs exceeds its new allocation. | |
4292 | * | |
4293 | * Note that if we wind up doing a full DDB recompute, we can't let | |
4294 | * any other display updates race with this transaction, so we need | |
4295 | * to grab the lock on *all* CRTC's. | |
4296 | */ | |
734fa01f | 4297 | if (intel_state->active_pipe_changes) { |
98d39494 | 4298 | realloc_pipes = ~0; |
734fa01f MR |
4299 | intel_state->wm_results.dirty_pipes = ~0; |
4300 | } | |
98d39494 | 4301 | |
5a920b85 PZ |
4302 | /* |
4303 | * We're not recomputing for the pipes not included in the commit, so | |
4304 | * make sure we start with the current state. | |
4305 | */ | |
4306 | memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); | |
4307 | ||
98d39494 MR |
4308 | for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { |
4309 | struct intel_crtc_state *cstate; | |
4310 | ||
4311 | cstate = intel_atomic_get_crtc_state(state, intel_crtc); | |
4312 | if (IS_ERR(cstate)) | |
4313 | return PTR_ERR(cstate); | |
4314 | ||
734fa01f | 4315 | ret = skl_allocate_pipe_ddb(cstate, ddb); |
98d39494 MR |
4316 | if (ret) |
4317 | return ret; | |
05a76d3d | 4318 | |
7f60e200 | 4319 | ret = skl_ddb_add_affected_planes(cstate); |
05a76d3d L |
4320 | if (ret) |
4321 | return ret; | |
98d39494 MR |
4322 | } |
4323 | ||
4324 | return 0; | |
4325 | } | |
4326 | ||
2722efb9 MR |
4327 | static void |
4328 | skl_copy_wm_for_pipe(struct skl_wm_values *dst, | |
4329 | struct skl_wm_values *src, | |
4330 | enum pipe pipe) | |
4331 | { | |
2722efb9 MR |
4332 | memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe], |
4333 | sizeof(dst->ddb.y_plane[pipe])); | |
4334 | memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe], | |
4335 | sizeof(dst->ddb.plane[pipe])); | |
4336 | } | |
4337 | ||
413fc530 | 4338 | static void |
4339 | skl_print_wm_changes(const struct drm_atomic_state *state) | |
4340 | { | |
4341 | const struct drm_device *dev = state->dev; | |
4342 | const struct drm_i915_private *dev_priv = to_i915(dev); | |
4343 | const struct intel_atomic_state *intel_state = | |
4344 | to_intel_atomic_state(state); | |
4345 | const struct drm_crtc *crtc; | |
4346 | const struct drm_crtc_state *cstate; | |
413fc530 | 4347 | const struct intel_plane *intel_plane; |
413fc530 | 4348 | const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; |
4349 | const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
7570498e | 4350 | int i; |
413fc530 | 4351 | |
6ebdb5a0 | 4352 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
7570498e ML |
4353 | const struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4354 | enum pipe pipe = intel_crtc->pipe; | |
413fc530 | 4355 | |
7570498e | 4356 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
d5cdfdf5 | 4357 | enum plane_id plane_id = intel_plane->id; |
413fc530 | 4358 | const struct skl_ddb_entry *old, *new; |
4359 | ||
d5cdfdf5 VS |
4360 | old = &old_ddb->plane[pipe][plane_id]; |
4361 | new = &new_ddb->plane[pipe][plane_id]; | |
413fc530 | 4362 | |
413fc530 | 4363 | if (skl_ddb_entry_equal(old, new)) |
4364 | continue; | |
4365 | ||
7570498e ML |
4366 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n", |
4367 | intel_plane->base.base.id, | |
4368 | intel_plane->base.name, | |
4369 | old->start, old->end, | |
4370 | new->start, new->end); | |
413fc530 | 4371 | } |
4372 | } | |
4373 | } | |
4374 | ||
98d39494 MR |
4375 | static int |
4376 | skl_compute_wm(struct drm_atomic_state *state) | |
4377 | { | |
4378 | struct drm_crtc *crtc; | |
4379 | struct drm_crtc_state *cstate; | |
734fa01f MR |
4380 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
4381 | struct skl_wm_values *results = &intel_state->wm_results; | |
4382 | struct skl_pipe_wm *pipe_wm; | |
98d39494 | 4383 | bool changed = false; |
734fa01f | 4384 | int ret, i; |
98d39494 MR |
4385 | |
4386 | /* | |
4387 | * If this transaction isn't actually touching any CRTC's, don't | |
4388 | * bother with watermark calculation. Note that if we pass this | |
4389 | * test, we're guaranteed to hold at least one CRTC state mutex, | |
4390 | * which means we can safely use values like dev_priv->active_crtcs | |
4391 | * since any racing commits that want to update them would need to | |
4392 | * hold _all_ CRTC state mutexes. | |
4393 | */ | |
6ebdb5a0 | 4394 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
98d39494 MR |
4395 | changed = true; |
4396 | if (!changed) | |
4397 | return 0; | |
4398 | ||
734fa01f MR |
4399 | /* Clear all dirty flags */ |
4400 | results->dirty_pipes = 0; | |
4401 | ||
98d39494 MR |
4402 | ret = skl_compute_ddb(state); |
4403 | if (ret) | |
4404 | return ret; | |
4405 | ||
734fa01f MR |
4406 | /* |
4407 | * Calculate WM's for all pipes that are part of this transaction. | |
4408 | * Note that the DDB allocation above may have added more CRTC's that | |
4409 | * weren't otherwise being modified (and set bits in dirty_pipes) if | |
4410 | * pipe allocations had to change. | |
4411 | * | |
4412 | * FIXME: Now that we're doing this in the atomic check phase, we | |
4413 | * should allow skl_update_pipe_wm() to return failure in cases where | |
4414 | * no suitable watermark values can be found. | |
4415 | */ | |
6ebdb5a0 | 4416 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
734fa01f MR |
4417 | struct intel_crtc_state *intel_cstate = |
4418 | to_intel_crtc_state(cstate); | |
03af79e0 ML |
4419 | const struct skl_pipe_wm *old_pipe_wm = |
4420 | &to_intel_crtc_state(crtc->state)->wm.skl.optimal; | |
734fa01f MR |
4421 | |
4422 | pipe_wm = &intel_cstate->wm.skl.optimal; | |
03af79e0 ML |
4423 | ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, |
4424 | &results->ddb, &changed); | |
734fa01f MR |
4425 | if (ret) |
4426 | return ret; | |
4427 | ||
4428 | if (changed) | |
4429 | results->dirty_pipes |= drm_crtc_mask(crtc); | |
4430 | ||
4431 | if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0) | |
4432 | /* This pipe's WM's did not change */ | |
4433 | continue; | |
4434 | ||
4435 | intel_cstate->update_wm_pre = true; | |
734fa01f MR |
4436 | } |
4437 | ||
413fc530 | 4438 | skl_print_wm_changes(state); |
4439 | ||
98d39494 MR |
4440 | return 0; |
4441 | } | |
4442 | ||
ccf010fb ML |
4443 | static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, |
4444 | struct intel_crtc_state *cstate) | |
4445 | { | |
4446 | struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); | |
4447 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
4448 | struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal; | |
e62929b3 | 4449 | const struct skl_ddb_allocation *ddb = &state->wm_results.ddb; |
ccf010fb | 4450 | enum pipe pipe = crtc->pipe; |
d5cdfdf5 | 4451 | enum plane_id plane_id; |
e62929b3 ML |
4452 | |
4453 | if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base))) | |
4454 | return; | |
ccf010fb ML |
4455 | |
4456 | I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); | |
e62929b3 | 4457 | |
d5cdfdf5 VS |
4458 | for_each_plane_id_on_crtc(crtc, plane_id) { |
4459 | if (plane_id != PLANE_CURSOR) | |
4460 | skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id], | |
4461 | ddb, plane_id); | |
4462 | else | |
4463 | skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id], | |
4464 | ddb); | |
4465 | } | |
ccf010fb ML |
4466 | } |
4467 | ||
e62929b3 ML |
4468 | static void skl_initial_wm(struct intel_atomic_state *state, |
4469 | struct intel_crtc_state *cstate) | |
2d41c0b5 | 4470 | { |
e62929b3 | 4471 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
432081bc | 4472 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4473 | struct drm_i915_private *dev_priv = to_i915(dev); |
e62929b3 | 4474 | struct skl_wm_values *results = &state->wm_results; |
2722efb9 | 4475 | struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw; |
27082493 | 4476 | enum pipe pipe = intel_crtc->pipe; |
adda50b8 | 4477 | |
432081bc | 4478 | if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0) |
2d41c0b5 PB |
4479 | return; |
4480 | ||
734fa01f | 4481 | mutex_lock(&dev_priv->wm.wm_mutex); |
2d41c0b5 | 4482 | |
e62929b3 ML |
4483 | if (cstate->base.active_changed) |
4484 | skl_atomic_update_crtc_wm(state, cstate); | |
27082493 L |
4485 | |
4486 | skl_copy_wm_for_pipe(hw_vals, results, pipe); | |
734fa01f MR |
4487 | |
4488 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2d41c0b5 PB |
4489 | } |
4490 | ||
d890565c VS |
4491 | static void ilk_compute_wm_config(struct drm_device *dev, |
4492 | struct intel_wm_config *config) | |
4493 | { | |
4494 | struct intel_crtc *crtc; | |
4495 | ||
4496 | /* Compute the currently _active_ config */ | |
4497 | for_each_intel_crtc(dev, crtc) { | |
4498 | const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; | |
4499 | ||
4500 | if (!wm->pipe_enabled) | |
4501 | continue; | |
4502 | ||
4503 | config->sprites_enabled |= wm->sprites_enabled; | |
4504 | config->sprites_scaled |= wm->sprites_scaled; | |
4505 | config->num_pipes_active++; | |
4506 | } | |
4507 | } | |
4508 | ||
ed4a6a7c | 4509 | static void ilk_program_watermarks(struct drm_i915_private *dev_priv) |
801bcfff | 4510 | { |
91c8a326 | 4511 | struct drm_device *dev = &dev_priv->drm; |
b9d5c839 | 4512 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
820c1980 | 4513 | struct ilk_wm_maximums max; |
d890565c | 4514 | struct intel_wm_config config = {}; |
820c1980 | 4515 | struct ilk_wm_values results = {}; |
77c122bc | 4516 | enum intel_ddb_partitioning partitioning; |
261a27d1 | 4517 | |
d890565c VS |
4518 | ilk_compute_wm_config(dev, &config); |
4519 | ||
4520 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); | |
4521 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); | |
a485bfb8 VS |
4522 | |
4523 | /* 5/6 split only in single pipe config on IVB+ */ | |
175fded1 | 4524 | if (INTEL_GEN(dev_priv) >= 7 && |
d890565c VS |
4525 | config.num_pipes_active == 1 && config.sprites_enabled) { |
4526 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); | |
4527 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); | |
0362c781 | 4528 | |
820c1980 | 4529 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 4530 | } else { |
198a1e9b | 4531 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
4532 | } |
4533 | ||
198a1e9b | 4534 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 4535 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 4536 | |
820c1980 | 4537 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 4538 | |
820c1980 | 4539 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
4540 | } |
4541 | ||
ccf010fb ML |
4542 | static void ilk_initial_watermarks(struct intel_atomic_state *state, |
4543 | struct intel_crtc_state *cstate) | |
b9d5c839 | 4544 | { |
ed4a6a7c MR |
4545 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); |
4546 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
b9d5c839 | 4547 | |
ed4a6a7c | 4548 | mutex_lock(&dev_priv->wm.wm_mutex); |
e8f1f02e | 4549 | intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate; |
ed4a6a7c MR |
4550 | ilk_program_watermarks(dev_priv); |
4551 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
4552 | } | |
bf220452 | 4553 | |
ccf010fb ML |
4554 | static void ilk_optimize_watermarks(struct intel_atomic_state *state, |
4555 | struct intel_crtc_state *cstate) | |
ed4a6a7c MR |
4556 | { |
4557 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); | |
4558 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
bf220452 | 4559 | |
ed4a6a7c MR |
4560 | mutex_lock(&dev_priv->wm.wm_mutex); |
4561 | if (cstate->wm.need_postvbl_update) { | |
e8f1f02e | 4562 | intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal; |
ed4a6a7c MR |
4563 | ilk_program_watermarks(dev_priv); |
4564 | } | |
4565 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
b9d5c839 VS |
4566 | } |
4567 | ||
d8c0fafc | 4568 | static inline void skl_wm_level_from_reg_val(uint32_t val, |
4569 | struct skl_wm_level *level) | |
3078999f | 4570 | { |
d8c0fafc | 4571 | level->plane_en = val & PLANE_WM_EN; |
4572 | level->plane_res_b = val & PLANE_WM_BLOCKS_MASK; | |
4573 | level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) & | |
4574 | PLANE_WM_LINES_MASK; | |
3078999f PB |
4575 | } |
4576 | ||
bf9d99ad | 4577 | void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, |
4578 | struct skl_pipe_wm *out) | |
3078999f | 4579 | { |
d5cdfdf5 | 4580 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
3078999f | 4581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3078999f | 4582 | enum pipe pipe = intel_crtc->pipe; |
d5cdfdf5 VS |
4583 | int level, max_level; |
4584 | enum plane_id plane_id; | |
d8c0fafc | 4585 | uint32_t val; |
3078999f | 4586 | |
5db94019 | 4587 | max_level = ilk_wm_max_level(dev_priv); |
3078999f | 4588 | |
d5cdfdf5 VS |
4589 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
4590 | struct skl_plane_wm *wm = &out->planes[plane_id]; | |
3078999f | 4591 | |
d8c0fafc | 4592 | for (level = 0; level <= max_level; level++) { |
d5cdfdf5 VS |
4593 | if (plane_id != PLANE_CURSOR) |
4594 | val = I915_READ(PLANE_WM(pipe, plane_id, level)); | |
d8c0fafc | 4595 | else |
4596 | val = I915_READ(CUR_WM(pipe, level)); | |
3078999f | 4597 | |
d8c0fafc | 4598 | skl_wm_level_from_reg_val(val, &wm->wm[level]); |
3078999f | 4599 | } |
3078999f | 4600 | |
d5cdfdf5 VS |
4601 | if (plane_id != PLANE_CURSOR) |
4602 | val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); | |
d8c0fafc | 4603 | else |
4604 | val = I915_READ(CUR_WM_TRANS(pipe)); | |
4605 | ||
4606 | skl_wm_level_from_reg_val(val, &wm->trans_wm); | |
3078999f PB |
4607 | } |
4608 | ||
d8c0fafc | 4609 | if (!intel_crtc->active) |
4610 | return; | |
4e0963c7 | 4611 | |
bf9d99ad | 4612 | out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); |
3078999f PB |
4613 | } |
4614 | ||
4615 | void skl_wm_get_hw_state(struct drm_device *dev) | |
4616 | { | |
fac5e23e | 4617 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf9d99ad | 4618 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
a269c583 | 4619 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
3078999f | 4620 | struct drm_crtc *crtc; |
bf9d99ad | 4621 | struct intel_crtc *intel_crtc; |
4622 | struct intel_crtc_state *cstate; | |
3078999f | 4623 | |
a269c583 | 4624 | skl_ddb_get_hw_state(dev_priv, ddb); |
bf9d99ad | 4625 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
4626 | intel_crtc = to_intel_crtc(crtc); | |
4627 | cstate = to_intel_crtc_state(crtc->state); | |
4628 | ||
4629 | skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal); | |
4630 | ||
03af79e0 | 4631 | if (intel_crtc->active) |
bf9d99ad | 4632 | hw->dirty_pipes |= drm_crtc_mask(crtc); |
bf9d99ad | 4633 | } |
a1de91e5 | 4634 | |
279e99d7 MR |
4635 | if (dev_priv->active_crtcs) { |
4636 | /* Fully recompute DDB on first atomic commit */ | |
4637 | dev_priv->wm.distrust_bios_wm = true; | |
4638 | } else { | |
4639 | /* Easy/common case; just sanitize DDB now if everything off */ | |
4640 | memset(ddb, 0, sizeof(*ddb)); | |
4641 | } | |
3078999f PB |
4642 | } |
4643 | ||
243e6a44 VS |
4644 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
4645 | { | |
4646 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4647 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 4648 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 | 4649 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4e0963c7 | 4650 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
e8f1f02e | 4651 | struct intel_pipe_wm *active = &cstate->wm.ilk.optimal; |
243e6a44 | 4652 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 | 4653 | static const i915_reg_t wm0_pipe_reg[] = { |
243e6a44 VS |
4654 | [PIPE_A] = WM0_PIPEA_ILK, |
4655 | [PIPE_B] = WM0_PIPEB_ILK, | |
4656 | [PIPE_C] = WM0_PIPEC_IVB, | |
4657 | }; | |
4658 | ||
4659 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
8652744b | 4660 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ce0e0713 | 4661 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 4662 | |
15606534 VS |
4663 | memset(active, 0, sizeof(*active)); |
4664 | ||
3ef00284 | 4665 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
4666 | |
4667 | if (active->pipe_enabled) { | |
243e6a44 VS |
4668 | u32 tmp = hw->wm_pipe[pipe]; |
4669 | ||
4670 | /* | |
4671 | * For active pipes LP0 watermark is marked as | |
4672 | * enabled, and LP1+ watermaks as disabled since | |
4673 | * we can't really reverse compute them in case | |
4674 | * multiple pipes are active. | |
4675 | */ | |
4676 | active->wm[0].enable = true; | |
4677 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
4678 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
4679 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
4680 | active->linetime = hw->wm_linetime[pipe]; | |
4681 | } else { | |
5db94019 | 4682 | int level, max_level = ilk_wm_max_level(dev_priv); |
243e6a44 VS |
4683 | |
4684 | /* | |
4685 | * For inactive pipes, all watermark levels | |
4686 | * should be marked as enabled but zeroed, | |
4687 | * which is what we'd compute them to. | |
4688 | */ | |
4689 | for (level = 0; level <= max_level; level++) | |
4690 | active->wm[level].enable = true; | |
4691 | } | |
4e0963c7 MR |
4692 | |
4693 | intel_crtc->wm.active.ilk = *active; | |
243e6a44 VS |
4694 | } |
4695 | ||
6eb1a681 VS |
4696 | #define _FW_WM(value, plane) \ |
4697 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) | |
4698 | #define _FW_WM_VLV(value, plane) \ | |
4699 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) | |
4700 | ||
4701 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, | |
4702 | struct vlv_wm_values *wm) | |
4703 | { | |
4704 | enum pipe pipe; | |
4705 | uint32_t tmp; | |
4706 | ||
4707 | for_each_pipe(dev_priv, pipe) { | |
4708 | tmp = I915_READ(VLV_DDL(pipe)); | |
4709 | ||
1b31389c | 4710 | wm->ddl[pipe].plane[PLANE_PRIMARY] = |
6eb1a681 | 4711 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 4712 | wm->ddl[pipe].plane[PLANE_CURSOR] = |
6eb1a681 | 4713 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 4714 | wm->ddl[pipe].plane[PLANE_SPRITE0] = |
6eb1a681 | 4715 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 4716 | wm->ddl[pipe].plane[PLANE_SPRITE1] = |
6eb1a681 VS |
4717 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
4718 | } | |
4719 | ||
4720 | tmp = I915_READ(DSPFW1); | |
4721 | wm->sr.plane = _FW_WM(tmp, SR); | |
1b31389c VS |
4722 | wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); |
4723 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); | |
4724 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); | |
6eb1a681 VS |
4725 | |
4726 | tmp = I915_READ(DSPFW2); | |
1b31389c VS |
4727 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); |
4728 | wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); | |
4729 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); | |
6eb1a681 VS |
4730 | |
4731 | tmp = I915_READ(DSPFW3); | |
4732 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
4733 | ||
4734 | if (IS_CHERRYVIEW(dev_priv)) { | |
4735 | tmp = I915_READ(DSPFW7_CHV); | |
1b31389c VS |
4736 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
4737 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
4738 | |
4739 | tmp = I915_READ(DSPFW8_CHV); | |
1b31389c VS |
4740 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); |
4741 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); | |
6eb1a681 VS |
4742 | |
4743 | tmp = I915_READ(DSPFW9_CHV); | |
1b31389c VS |
4744 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); |
4745 | wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); | |
6eb1a681 VS |
4746 | |
4747 | tmp = I915_READ(DSPHOWM); | |
4748 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
4749 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; |
4750 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; | |
4751 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; | |
4752 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
4753 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
4754 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
4755 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
4756 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
4757 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
4758 | } else { |
4759 | tmp = I915_READ(DSPFW7); | |
1b31389c VS |
4760 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
4761 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
4762 | |
4763 | tmp = I915_READ(DSPHOWM); | |
4764 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
4765 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
4766 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
4767 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
4768 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
4769 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
4770 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
4771 | } |
4772 | } | |
4773 | ||
4774 | #undef _FW_WM | |
4775 | #undef _FW_WM_VLV | |
4776 | ||
4777 | void vlv_wm_get_hw_state(struct drm_device *dev) | |
4778 | { | |
4779 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4780 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; | |
f07d43d2 | 4781 | struct intel_crtc *crtc; |
6eb1a681 VS |
4782 | u32 val; |
4783 | ||
4784 | vlv_read_wm_values(dev_priv, wm); | |
4785 | ||
6eb1a681 VS |
4786 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4787 | wm->level = VLV_WM_LEVEL_PM2; | |
4788 | ||
4789 | if (IS_CHERRYVIEW(dev_priv)) { | |
4790 | mutex_lock(&dev_priv->rps.hw_lock); | |
4791 | ||
4792 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4793 | if (val & DSP_MAXFIFO_PM5_ENABLE) | |
4794 | wm->level = VLV_WM_LEVEL_PM5; | |
4795 | ||
58590c14 VS |
4796 | /* |
4797 | * If DDR DVFS is disabled in the BIOS, Punit | |
4798 | * will never ack the request. So if that happens | |
4799 | * assume we don't have to enable/disable DDR DVFS | |
4800 | * dynamically. To test that just set the REQ_ACK | |
4801 | * bit to poke the Punit, but don't change the | |
4802 | * HIGH/LOW bits so that we don't actually change | |
4803 | * the current state. | |
4804 | */ | |
6eb1a681 | 4805 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
58590c14 VS |
4806 | val |= FORCE_DDR_FREQ_REQ_ACK; |
4807 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
4808 | ||
4809 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
4810 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { | |
4811 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " | |
4812 | "assuming DDR DVFS is disabled\n"); | |
4813 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; | |
4814 | } else { | |
4815 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
4816 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) | |
4817 | wm->level = VLV_WM_LEVEL_DDR_DVFS; | |
4818 | } | |
6eb1a681 VS |
4819 | |
4820 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4821 | } | |
4822 | ||
ff32c54e VS |
4823 | for_each_intel_crtc(dev, crtc) { |
4824 | struct intel_crtc_state *crtc_state = | |
4825 | to_intel_crtc_state(crtc->base.state); | |
4826 | struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
4827 | const struct vlv_fifo_state *fifo_state = | |
4828 | &crtc_state->wm.vlv.fifo_state; | |
4829 | enum pipe pipe = crtc->pipe; | |
4830 | enum plane_id plane_id; | |
4831 | int level; | |
4832 | ||
4833 | vlv_get_fifo_size(crtc_state); | |
4834 | ||
4835 | active->num_levels = wm->level + 1; | |
4836 | active->cxsr = wm->cxsr; | |
4837 | ||
ff32c54e | 4838 | for (level = 0; level < active->num_levels; level++) { |
114d7dc0 | 4839 | struct g4x_pipe_wm *raw = |
ff32c54e VS |
4840 | &crtc_state->wm.vlv.raw[level]; |
4841 | ||
4842 | active->sr[level].plane = wm->sr.plane; | |
4843 | active->sr[level].cursor = wm->sr.cursor; | |
4844 | ||
4845 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
4846 | active->wm[level].plane[plane_id] = | |
4847 | wm->pipe[pipe].plane[plane_id]; | |
4848 | ||
4849 | raw->plane[plane_id] = | |
4850 | vlv_invert_wm_value(active->wm[level].plane[plane_id], | |
4851 | fifo_state->plane[plane_id]); | |
4852 | } | |
4853 | } | |
4854 | ||
4855 | for_each_plane_id_on_crtc(crtc, plane_id) | |
4856 | vlv_raw_plane_wm_set(crtc_state, level, | |
4857 | plane_id, USHRT_MAX); | |
4858 | vlv_invalidate_wms(crtc, active, level); | |
4859 | ||
4860 | crtc_state->wm.vlv.optimal = *active; | |
4841da51 | 4861 | crtc_state->wm.vlv.intermediate = *active; |
ff32c54e | 4862 | |
6eb1a681 | 4863 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", |
1b31389c VS |
4864 | pipe_name(pipe), |
4865 | wm->pipe[pipe].plane[PLANE_PRIMARY], | |
4866 | wm->pipe[pipe].plane[PLANE_CURSOR], | |
4867 | wm->pipe[pipe].plane[PLANE_SPRITE0], | |
4868 | wm->pipe[pipe].plane[PLANE_SPRITE1]); | |
ff32c54e | 4869 | } |
6eb1a681 VS |
4870 | |
4871 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", | |
4872 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); | |
4873 | } | |
4874 | ||
602ae835 VS |
4875 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv) |
4876 | { | |
4877 | struct intel_plane *plane; | |
4878 | struct intel_crtc *crtc; | |
4879 | ||
4880 | mutex_lock(&dev_priv->wm.wm_mutex); | |
4881 | ||
4882 | for_each_intel_plane(&dev_priv->drm, plane) { | |
4883 | struct intel_crtc *crtc = | |
4884 | intel_get_crtc_for_pipe(dev_priv, plane->pipe); | |
4885 | struct intel_crtc_state *crtc_state = | |
4886 | to_intel_crtc_state(crtc->base.state); | |
4887 | struct intel_plane_state *plane_state = | |
4888 | to_intel_plane_state(plane->base.state); | |
4889 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
4890 | const struct vlv_fifo_state *fifo_state = | |
4891 | &crtc_state->wm.vlv.fifo_state; | |
4892 | enum plane_id plane_id = plane->id; | |
4893 | int level; | |
4894 | ||
4895 | if (plane_state->base.visible) | |
4896 | continue; | |
4897 | ||
4898 | for (level = 0; level < wm_state->num_levels; level++) { | |
114d7dc0 | 4899 | struct g4x_pipe_wm *raw = |
602ae835 VS |
4900 | &crtc_state->wm.vlv.raw[level]; |
4901 | ||
4902 | raw->plane[plane_id] = 0; | |
4903 | ||
4904 | wm_state->wm[level].plane[plane_id] = | |
4905 | vlv_invert_wm_value(raw->plane[plane_id], | |
4906 | fifo_state->plane[plane_id]); | |
4907 | } | |
4908 | } | |
4909 | ||
4910 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
4911 | struct intel_crtc_state *crtc_state = | |
4912 | to_intel_crtc_state(crtc->base.state); | |
4913 | ||
4914 | crtc_state->wm.vlv.intermediate = | |
4915 | crtc_state->wm.vlv.optimal; | |
4916 | crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
4917 | } | |
4918 | ||
4919 | vlv_program_watermarks(dev_priv); | |
4920 | ||
4921 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
4922 | } | |
4923 | ||
243e6a44 VS |
4924 | void ilk_wm_get_hw_state(struct drm_device *dev) |
4925 | { | |
fac5e23e | 4926 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 4927 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
4928 | struct drm_crtc *crtc; |
4929 | ||
70e1e0ec | 4930 | for_each_crtc(dev, crtc) |
243e6a44 VS |
4931 | ilk_pipe_wm_get_hw_state(crtc); |
4932 | ||
4933 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
4934 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
4935 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
4936 | ||
4937 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
175fded1 | 4938 | if (INTEL_GEN(dev_priv) >= 7) { |
cfa7698b VS |
4939 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
4940 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
4941 | } | |
243e6a44 | 4942 | |
8652744b | 4943 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ac9545fd VS |
4944 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
4945 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
fd6b8f43 | 4946 | else if (IS_IVYBRIDGE(dev_priv)) |
ac9545fd VS |
4947 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
4948 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
4949 | |
4950 | hw->enable_fbc_wm = | |
4951 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
4952 | } | |
4953 | ||
b445e3b0 ED |
4954 | /** |
4955 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4956 | * | |
4957 | * Calculate watermark values for the various WM regs based on current mode | |
4958 | * and plane configuration. | |
4959 | * | |
4960 | * There are several cases to deal with here: | |
4961 | * - normal (i.e. non-self-refresh) | |
4962 | * - self-refresh (SR) mode | |
4963 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4964 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4965 | * lines), so need to account for TLB latency | |
4966 | * | |
4967 | * The normal calculation is: | |
4968 | * watermark = dotclock * bytes per pixel * latency | |
4969 | * where latency is platform & configuration dependent (we assume pessimal | |
4970 | * values here). | |
4971 | * | |
4972 | * The SR calculation is: | |
4973 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4974 | * bytes per pixel | |
4975 | * where | |
4976 | * line time = htotal / dotclock | |
4977 | * surface width = hdisplay for normal plane and 64 for cursor | |
4978 | * and latency is assumed to be high, as above. | |
4979 | * | |
4980 | * The final value programmed to the register should always be rounded up, | |
4981 | * and include an extra 2 entries to account for clock crossings. | |
4982 | * | |
4983 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4984 | * to set the non-SR watermarks to 8. | |
4985 | */ | |
432081bc | 4986 | void intel_update_watermarks(struct intel_crtc *crtc) |
b445e3b0 | 4987 | { |
432081bc | 4988 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b445e3b0 ED |
4989 | |
4990 | if (dev_priv->display.update_wm) | |
46ba614c | 4991 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
4992 | } |
4993 | ||
e2828914 | 4994 | /* |
9270388e | 4995 | * Lock protecting IPS related data structures |
9270388e DV |
4996 | */ |
4997 | DEFINE_SPINLOCK(mchdev_lock); | |
4998 | ||
4999 | /* Global for IPS driver to get at the current i915 device. Protected by | |
5000 | * mchdev_lock. */ | |
5001 | static struct drm_i915_private *i915_mch_dev; | |
5002 | ||
91d14251 | 5003 | bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 5004 | { |
2b4e57bd ED |
5005 | u16 rgvswctl; |
5006 | ||
67520415 | 5007 | lockdep_assert_held(&mchdev_lock); |
9270388e | 5008 | |
2b4e57bd ED |
5009 | rgvswctl = I915_READ16(MEMSWCTL); |
5010 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5011 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5012 | return false; /* still busy with another command */ | |
5013 | } | |
5014 | ||
5015 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5016 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5017 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5018 | POSTING_READ16(MEMSWCTL); | |
5019 | ||
5020 | rgvswctl |= MEMCTL_CMD_STS; | |
5021 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5022 | ||
5023 | return true; | |
5024 | } | |
5025 | ||
91d14251 | 5026 | static void ironlake_enable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5027 | { |
84f1b20f | 5028 | u32 rgvmodectl; |
2b4e57bd ED |
5029 | u8 fmax, fmin, fstart, vstart; |
5030 | ||
9270388e DV |
5031 | spin_lock_irq(&mchdev_lock); |
5032 | ||
84f1b20f TU |
5033 | rgvmodectl = I915_READ(MEMMODECTL); |
5034 | ||
2b4e57bd ED |
5035 | /* Enable temp reporting */ |
5036 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
5037 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
5038 | ||
5039 | /* 100ms RC evaluation intervals */ | |
5040 | I915_WRITE(RCUPEI, 100000); | |
5041 | I915_WRITE(RCDNEI, 100000); | |
5042 | ||
5043 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
5044 | I915_WRITE(RCBMAXAVG, 90000); | |
5045 | I915_WRITE(RCBMINAVG, 80000); | |
5046 | ||
5047 | I915_WRITE(MEMIHYST, 1); | |
5048 | ||
5049 | /* Set up min, max, and cur for interrupt handling */ | |
5050 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
5051 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
5052 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
5053 | MEMMODE_FSTART_SHIFT; | |
5054 | ||
616847e7 | 5055 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
2b4e57bd ED |
5056 | PXVFREQ_PX_SHIFT; |
5057 | ||
20e4d407 DV |
5058 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
5059 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 5060 | |
20e4d407 DV |
5061 | dev_priv->ips.max_delay = fstart; |
5062 | dev_priv->ips.min_delay = fmin; | |
5063 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
5064 | |
5065 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
5066 | fmax, fmin, fstart); | |
5067 | ||
5068 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
5069 | ||
5070 | /* | |
5071 | * Interrupts will be enabled in ironlake_irq_postinstall | |
5072 | */ | |
5073 | ||
5074 | I915_WRITE(VIDSTART, vstart); | |
5075 | POSTING_READ(VIDSTART); | |
5076 | ||
5077 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5078 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5079 | ||
9270388e | 5080 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 5081 | DRM_ERROR("stuck trying to change perf mode\n"); |
dd92d8de | 5082 | mdelay(1); |
2b4e57bd | 5083 | |
91d14251 | 5084 | ironlake_set_drps(dev_priv, fstart); |
2b4e57bd | 5085 | |
7d81c3e0 VS |
5086 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
5087 | I915_READ(DDREC) + I915_READ(CSIEC); | |
20e4d407 | 5088 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
7d81c3e0 | 5089 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
5ed0bdf2 | 5090 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
5091 | |
5092 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
5093 | } |
5094 | ||
91d14251 | 5095 | static void ironlake_disable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5096 | { |
9270388e DV |
5097 | u16 rgvswctl; |
5098 | ||
5099 | spin_lock_irq(&mchdev_lock); | |
5100 | ||
5101 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
5102 | |
5103 | /* Ack interrupts, disable EFC interrupt */ | |
5104 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5105 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5106 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5107 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5108 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5109 | ||
5110 | /* Go back to the starting frequency */ | |
91d14251 | 5111 | ironlake_set_drps(dev_priv, dev_priv->ips.fstart); |
dd92d8de | 5112 | mdelay(1); |
2b4e57bd ED |
5113 | rgvswctl |= MEMCTL_CMD_STS; |
5114 | I915_WRITE(MEMSWCTL, rgvswctl); | |
dd92d8de | 5115 | mdelay(1); |
2b4e57bd | 5116 | |
9270388e | 5117 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
5118 | } |
5119 | ||
acbe9475 DV |
5120 | /* There's a funny hw issue where the hw returns all 0 when reading from |
5121 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
5122 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
5123 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
5124 | */ | |
74ef1173 | 5125 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 5126 | { |
7b9e0ae6 | 5127 | u32 limits; |
2b4e57bd | 5128 | |
20b46e59 DV |
5129 | /* Only set the down limit when we've reached the lowest level to avoid |
5130 | * getting more interrupts, otherwise leave this clear. This prevents a | |
5131 | * race in the hw when coming out of rc6: There's a tiny window where | |
5132 | * the hw runs at the minimal clock before selecting the desired | |
5133 | * frequency, if the down threshold expires in that window we will not | |
5134 | * receive a down interrupt. */ | |
2d1fe073 | 5135 | if (IS_GEN9(dev_priv)) { |
74ef1173 AG |
5136 | limits = (dev_priv->rps.max_freq_softlimit) << 23; |
5137 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5138 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; | |
5139 | } else { | |
5140 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
5141 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5142 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
5143 | } | |
20b46e59 DV |
5144 | |
5145 | return limits; | |
5146 | } | |
5147 | ||
dd75fdc8 CW |
5148 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
5149 | { | |
5150 | int new_power; | |
8a586437 AG |
5151 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
5152 | u32 ei_up = 0, ei_down = 0; | |
dd75fdc8 CW |
5153 | |
5154 | new_power = dev_priv->rps.power; | |
5155 | switch (dev_priv->rps.power) { | |
5156 | case LOW_POWER: | |
a72b5623 CW |
5157 | if (val > dev_priv->rps.efficient_freq + 1 && |
5158 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5159 | new_power = BETWEEN; |
5160 | break; | |
5161 | ||
5162 | case BETWEEN: | |
a72b5623 CW |
5163 | if (val <= dev_priv->rps.efficient_freq && |
5164 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 | 5165 | new_power = LOW_POWER; |
a72b5623 CW |
5166 | else if (val >= dev_priv->rps.rp0_freq && |
5167 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5168 | new_power = HIGH_POWER; |
5169 | break; | |
5170 | ||
5171 | case HIGH_POWER: | |
a72b5623 CW |
5172 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && |
5173 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5174 | new_power = BETWEEN; |
5175 | break; | |
5176 | } | |
5177 | /* Max/min bins are special */ | |
aed242ff | 5178 | if (val <= dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 5179 | new_power = LOW_POWER; |
aed242ff | 5180 | if (val >= dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
5181 | new_power = HIGH_POWER; |
5182 | if (new_power == dev_priv->rps.power) | |
5183 | return; | |
5184 | ||
5185 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
5186 | switch (new_power) { | |
5187 | case LOW_POWER: | |
5188 | /* Upclock if more than 95% busy over 16ms */ | |
8a586437 AG |
5189 | ei_up = 16000; |
5190 | threshold_up = 95; | |
dd75fdc8 CW |
5191 | |
5192 | /* Downclock if less than 85% busy over 32ms */ | |
8a586437 AG |
5193 | ei_down = 32000; |
5194 | threshold_down = 85; | |
dd75fdc8 CW |
5195 | break; |
5196 | ||
5197 | case BETWEEN: | |
5198 | /* Upclock if more than 90% busy over 13ms */ | |
8a586437 AG |
5199 | ei_up = 13000; |
5200 | threshold_up = 90; | |
dd75fdc8 CW |
5201 | |
5202 | /* Downclock if less than 75% busy over 32ms */ | |
8a586437 AG |
5203 | ei_down = 32000; |
5204 | threshold_down = 75; | |
dd75fdc8 CW |
5205 | break; |
5206 | ||
5207 | case HIGH_POWER: | |
5208 | /* Upclock if more than 85% busy over 10ms */ | |
8a586437 AG |
5209 | ei_up = 10000; |
5210 | threshold_up = 85; | |
dd75fdc8 CW |
5211 | |
5212 | /* Downclock if less than 60% busy over 32ms */ | |
8a586437 AG |
5213 | ei_down = 32000; |
5214 | threshold_down = 60; | |
dd75fdc8 CW |
5215 | break; |
5216 | } | |
5217 | ||
6067a27d MK |
5218 | /* When byt can survive without system hang with dynamic |
5219 | * sw freq adjustments, this restriction can be lifted. | |
5220 | */ | |
5221 | if (IS_VALLEYVIEW(dev_priv)) | |
5222 | goto skip_hw_write; | |
5223 | ||
8a586437 | 5224 | I915_WRITE(GEN6_RP_UP_EI, |
a72b5623 | 5225 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
8a586437 | 5226 | I915_WRITE(GEN6_RP_UP_THRESHOLD, |
a72b5623 CW |
5227 | GT_INTERVAL_FROM_US(dev_priv, |
5228 | ei_up * threshold_up / 100)); | |
8a586437 AG |
5229 | |
5230 | I915_WRITE(GEN6_RP_DOWN_EI, | |
a72b5623 | 5231 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); |
8a586437 | 5232 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, |
a72b5623 CW |
5233 | GT_INTERVAL_FROM_US(dev_priv, |
5234 | ei_down * threshold_down / 100)); | |
5235 | ||
5236 | I915_WRITE(GEN6_RP_CONTROL, | |
5237 | GEN6_RP_MEDIA_TURBO | | |
5238 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5239 | GEN6_RP_MEDIA_IS_GFX | | |
5240 | GEN6_RP_ENABLE | | |
5241 | GEN6_RP_UP_BUSY_AVG | | |
5242 | GEN6_RP_DOWN_IDLE_AVG); | |
8a586437 | 5243 | |
6067a27d | 5244 | skip_hw_write: |
dd75fdc8 | 5245 | dev_priv->rps.power = new_power; |
8fb55197 CW |
5246 | dev_priv->rps.up_threshold = threshold_up; |
5247 | dev_priv->rps.down_threshold = threshold_down; | |
dd75fdc8 CW |
5248 | dev_priv->rps.last_adj = 0; |
5249 | } | |
5250 | ||
2876ce73 CW |
5251 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
5252 | { | |
5253 | u32 mask = 0; | |
5254 | ||
e0e8c7cb | 5255 | /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ |
2876ce73 | 5256 | if (val > dev_priv->rps.min_freq_softlimit) |
e0e8c7cb | 5257 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
2876ce73 | 5258 | if (val < dev_priv->rps.max_freq_softlimit) |
6f4b12f8 | 5259 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
2876ce73 | 5260 | |
7b3c29f6 CW |
5261 | mask &= dev_priv->pm_rps_events; |
5262 | ||
59d02a1f | 5263 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
5264 | } |
5265 | ||
b8a5ff8d JM |
5266 | /* gen6_set_rps is called to update the frequency request, but should also be |
5267 | * called when the range (min_delay and max_delay) is modified so that we can | |
5268 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
9fcee2f7 | 5269 | static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) |
20b46e59 | 5270 | { |
eb64cad1 CW |
5271 | /* min/max delay may still have been modified so be sure to |
5272 | * write the limits value. | |
5273 | */ | |
5274 | if (val != dev_priv->rps.cur_freq) { | |
5275 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 5276 | |
dc97997a | 5277 | if (IS_GEN9(dev_priv)) |
5704195c AG |
5278 | I915_WRITE(GEN6_RPNSWREQ, |
5279 | GEN9_FREQUENCY(val)); | |
dc97997a | 5280 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
eb64cad1 CW |
5281 | I915_WRITE(GEN6_RPNSWREQ, |
5282 | HSW_FREQUENCY(val)); | |
5283 | else | |
5284 | I915_WRITE(GEN6_RPNSWREQ, | |
5285 | GEN6_FREQUENCY(val) | | |
5286 | GEN6_OFFSET(0) | | |
5287 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 5288 | } |
7b9e0ae6 | 5289 | |
7b9e0ae6 CW |
5290 | /* Make sure we continue to get interrupts |
5291 | * until we hit the minimum or maximum frequencies. | |
5292 | */ | |
74ef1173 | 5293 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
2876ce73 | 5294 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 5295 | |
b39fb297 | 5296 | dev_priv->rps.cur_freq = val; |
0f94592e | 5297 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
9fcee2f7 CW |
5298 | |
5299 | return 0; | |
2b4e57bd ED |
5300 | } |
5301 | ||
9fcee2f7 | 5302 | static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val) |
ffe02b40 | 5303 | { |
9fcee2f7 CW |
5304 | int err; |
5305 | ||
dc97997a | 5306 | if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1), |
ffe02b40 VS |
5307 | "Odd GPU freq value\n")) |
5308 | val &= ~1; | |
5309 | ||
cd25dd5b D |
5310 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
5311 | ||
8fb55197 | 5312 | if (val != dev_priv->rps.cur_freq) { |
9fcee2f7 CW |
5313 | err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
5314 | if (err) | |
5315 | return err; | |
5316 | ||
db4c5e0b | 5317 | gen6_set_rps_thresholds(dev_priv, val); |
8fb55197 | 5318 | } |
ffe02b40 | 5319 | |
ffe02b40 VS |
5320 | dev_priv->rps.cur_freq = val; |
5321 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
9fcee2f7 CW |
5322 | |
5323 | return 0; | |
ffe02b40 VS |
5324 | } |
5325 | ||
a7f6e231 | 5326 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
76c3552f D |
5327 | * |
5328 | * * If Gfx is Idle, then | |
a7f6e231 D |
5329 | * 1. Forcewake Media well. |
5330 | * 2. Request idle freq. | |
5331 | * 3. Release Forcewake of Media well. | |
76c3552f D |
5332 | */ |
5333 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
5334 | { | |
aed242ff | 5335 | u32 val = dev_priv->rps.idle_freq; |
9fcee2f7 | 5336 | int err; |
5549d25f | 5337 | |
aed242ff | 5338 | if (dev_priv->rps.cur_freq <= val) |
76c3552f D |
5339 | return; |
5340 | ||
c9efef7b CW |
5341 | /* The punit delays the write of the frequency and voltage until it |
5342 | * determines the GPU is awake. During normal usage we don't want to | |
5343 | * waste power changing the frequency if the GPU is sleeping (rc6). | |
5344 | * However, the GPU and driver is now idle and we do not want to delay | |
5345 | * switching to minimum voltage (reducing power whilst idle) as we do | |
5346 | * not expect to be woken in the near future and so must flush the | |
5347 | * change by waking the device. | |
5348 | * | |
5349 | * We choose to take the media powerwell (either would do to trick the | |
5350 | * punit into committing the voltage change) as that takes a lot less | |
5351 | * power than the render powerwell. | |
5352 | */ | |
a7f6e231 | 5353 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 | 5354 | err = valleyview_set_rps(dev_priv, val); |
a7f6e231 | 5355 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 CW |
5356 | |
5357 | if (err) | |
5358 | DRM_ERROR("Failed to set RPS for idle\n"); | |
76c3552f D |
5359 | } |
5360 | ||
43cf3bf0 CW |
5361 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
5362 | { | |
5363 | mutex_lock(&dev_priv->rps.hw_lock); | |
5364 | if (dev_priv->rps.enabled) { | |
bd64818d CW |
5365 | u8 freq; |
5366 | ||
e0e8c7cb | 5367 | if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) |
43cf3bf0 CW |
5368 | gen6_rps_reset_ei(dev_priv); |
5369 | I915_WRITE(GEN6_PMINTRMSK, | |
5370 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
2b83c4c4 | 5371 | |
c33d247d CW |
5372 | gen6_enable_rps_interrupts(dev_priv); |
5373 | ||
bd64818d CW |
5374 | /* Use the user's desired frequency as a guide, but for better |
5375 | * performance, jump directly to RPe as our starting frequency. | |
5376 | */ | |
5377 | freq = max(dev_priv->rps.cur_freq, | |
5378 | dev_priv->rps.efficient_freq); | |
5379 | ||
9fcee2f7 | 5380 | if (intel_set_rps(dev_priv, |
bd64818d | 5381 | clamp(freq, |
9fcee2f7 CW |
5382 | dev_priv->rps.min_freq_softlimit, |
5383 | dev_priv->rps.max_freq_softlimit))) | |
5384 | DRM_DEBUG_DRIVER("Failed to set idle frequency\n"); | |
43cf3bf0 CW |
5385 | } |
5386 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5387 | } | |
5388 | ||
b29c19b6 CW |
5389 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
5390 | { | |
c33d247d CW |
5391 | /* Flush our bottom-half so that it does not race with us |
5392 | * setting the idle frequency and so that it is bounded by | |
5393 | * our rpm wakeref. And then disable the interrupts to stop any | |
5394 | * futher RPS reclocking whilst we are asleep. | |
5395 | */ | |
5396 | gen6_disable_rps_interrupts(dev_priv); | |
5397 | ||
b29c19b6 | 5398 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 5399 | if (dev_priv->rps.enabled) { |
dc97997a | 5400 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
76c3552f | 5401 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 5402 | else |
dc97997a | 5403 | gen6_set_rps(dev_priv, dev_priv->rps.idle_freq); |
c0951f0c | 5404 | dev_priv->rps.last_adj = 0; |
12c100bf VS |
5405 | I915_WRITE(GEN6_PMINTRMSK, |
5406 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); | |
c0951f0c | 5407 | } |
8d3afd7d | 5408 | mutex_unlock(&dev_priv->rps.hw_lock); |
1854d5ca | 5409 | |
8d3afd7d | 5410 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
5411 | while (!list_empty(&dev_priv->rps.clients)) |
5412 | list_del_init(dev_priv->rps.clients.next); | |
8d3afd7d | 5413 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
5414 | } |
5415 | ||
1854d5ca | 5416 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
5417 | struct intel_rps_client *rps, |
5418 | unsigned long submitted) | |
b29c19b6 | 5419 | { |
8d3afd7d CW |
5420 | /* This is intentionally racy! We peek at the state here, then |
5421 | * validate inside the RPS worker. | |
5422 | */ | |
67d97da3 | 5423 | if (!(dev_priv->gt.awake && |
8d3afd7d | 5424 | dev_priv->rps.enabled && |
29ecd78d | 5425 | dev_priv->rps.cur_freq < dev_priv->rps.boost_freq)) |
8d3afd7d | 5426 | return; |
43cf3bf0 | 5427 | |
e61b9958 CW |
5428 | /* Force a RPS boost (and don't count it against the client) if |
5429 | * the GPU is severely congested. | |
5430 | */ | |
d0bc54f2 | 5431 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
e61b9958 CW |
5432 | rps = NULL; |
5433 | ||
8d3afd7d CW |
5434 | spin_lock(&dev_priv->rps.client_lock); |
5435 | if (rps == NULL || list_empty(&rps->link)) { | |
5436 | spin_lock_irq(&dev_priv->irq_lock); | |
5437 | if (dev_priv->rps.interrupts_enabled) { | |
5438 | dev_priv->rps.client_boost = true; | |
c33d247d | 5439 | schedule_work(&dev_priv->rps.work); |
8d3afd7d CW |
5440 | } |
5441 | spin_unlock_irq(&dev_priv->irq_lock); | |
1854d5ca | 5442 | |
2e1b8730 CW |
5443 | if (rps != NULL) { |
5444 | list_add(&rps->link, &dev_priv->rps.clients); | |
5445 | rps->boosts++; | |
1854d5ca CW |
5446 | } else |
5447 | dev_priv->rps.boosts++; | |
c0951f0c | 5448 | } |
8d3afd7d | 5449 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
5450 | } |
5451 | ||
9fcee2f7 | 5452 | int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) |
0a073b84 | 5453 | { |
9fcee2f7 CW |
5454 | int err; |
5455 | ||
cfd1c488 CW |
5456 | lockdep_assert_held(&dev_priv->rps.hw_lock); |
5457 | GEM_BUG_ON(val > dev_priv->rps.max_freq); | |
5458 | GEM_BUG_ON(val < dev_priv->rps.min_freq); | |
5459 | ||
76e4e4b5 CW |
5460 | if (!dev_priv->rps.enabled) { |
5461 | dev_priv->rps.cur_freq = val; | |
5462 | return 0; | |
5463 | } | |
5464 | ||
dc97997a | 5465 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
9fcee2f7 | 5466 | err = valleyview_set_rps(dev_priv, val); |
ffe02b40 | 5467 | else |
9fcee2f7 CW |
5468 | err = gen6_set_rps(dev_priv, val); |
5469 | ||
5470 | return err; | |
0a073b84 JB |
5471 | } |
5472 | ||
dc97997a | 5473 | static void gen9_disable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 5474 | { |
20e49366 | 5475 | I915_WRITE(GEN6_RC_CONTROL, 0); |
38c23527 | 5476 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
5477 | } |
5478 | ||
dc97997a | 5479 | static void gen9_disable_rps(struct drm_i915_private *dev_priv) |
2030d684 | 5480 | { |
2030d684 AG |
5481 | I915_WRITE(GEN6_RP_CONTROL, 0); |
5482 | } | |
5483 | ||
dc97997a | 5484 | static void gen6_disable_rps(struct drm_i915_private *dev_priv) |
d20d4f0c | 5485 | { |
d20d4f0c | 5486 | I915_WRITE(GEN6_RC_CONTROL, 0); |
44fc7d5c | 5487 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2030d684 | 5488 | I915_WRITE(GEN6_RP_CONTROL, 0); |
44fc7d5c DV |
5489 | } |
5490 | ||
dc97997a | 5491 | static void cherryview_disable_rps(struct drm_i915_private *dev_priv) |
38807746 | 5492 | { |
38807746 D |
5493 | I915_WRITE(GEN6_RC_CONTROL, 0); |
5494 | } | |
5495 | ||
dc97997a | 5496 | static void valleyview_disable_rps(struct drm_i915_private *dev_priv) |
44fc7d5c | 5497 | { |
98a2e5f9 D |
5498 | /* we're doing forcewake before Disabling RC6, |
5499 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 5500 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 5501 | |
44fc7d5c | 5502 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 5503 | |
59bad947 | 5504 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
5505 | } |
5506 | ||
dc97997a | 5507 | static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) |
dc39fff7 | 5508 | { |
dc97997a | 5509 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
91ca689a ID |
5510 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
5511 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
5512 | else | |
5513 | mode = 0; | |
5514 | } | |
dc97997a | 5515 | if (HAS_RC6p(dev_priv)) |
b99d49cc ID |
5516 | DRM_DEBUG_DRIVER("Enabling RC6 states: " |
5517 | "RC6 %s RC6p %s RC6pp %s\n", | |
5518 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE), | |
5519 | onoff(mode & GEN6_RC_CTL_RC6p_ENABLE), | |
5520 | onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE)); | |
58abf1da RV |
5521 | |
5522 | else | |
b99d49cc ID |
5523 | DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n", |
5524 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE)); | |
dc39fff7 BW |
5525 | } |
5526 | ||
dc97997a | 5527 | static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) |
274008e8 | 5528 | { |
72e96d64 | 5529 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
274008e8 SAK |
5530 | bool enable_rc6 = true; |
5531 | unsigned long rc6_ctx_base; | |
fc619841 ID |
5532 | u32 rc_ctl; |
5533 | int rc_sw_target; | |
5534 | ||
5535 | rc_ctl = I915_READ(GEN6_RC_CONTROL); | |
5536 | rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >> | |
5537 | RC_SW_TARGET_STATE_SHIFT; | |
5538 | DRM_DEBUG_DRIVER("BIOS enabled RC states: " | |
5539 | "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", | |
5540 | onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE), | |
5541 | onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), | |
5542 | rc_sw_target); | |
274008e8 SAK |
5543 | |
5544 | if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { | |
b99d49cc | 5545 | DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n"); |
274008e8 SAK |
5546 | enable_rc6 = false; |
5547 | } | |
5548 | ||
5549 | /* | |
5550 | * The exact context size is not known for BXT, so assume a page size | |
5551 | * for this check. | |
5552 | */ | |
5553 | rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; | |
72e96d64 JL |
5554 | if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) && |
5555 | (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base + | |
5556 | ggtt->stolen_reserved_size))) { | |
b99d49cc | 5557 | DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n"); |
274008e8 SAK |
5558 | enable_rc6 = false; |
5559 | } | |
5560 | ||
5561 | if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && | |
5562 | ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && | |
5563 | ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && | |
5564 | ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { | |
b99d49cc | 5565 | DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n"); |
274008e8 SAK |
5566 | enable_rc6 = false; |
5567 | } | |
5568 | ||
fc619841 ID |
5569 | if (!I915_READ(GEN8_PUSHBUS_CONTROL) || |
5570 | !I915_READ(GEN8_PUSHBUS_ENABLE) || | |
5571 | !I915_READ(GEN8_PUSHBUS_SHIFT)) { | |
5572 | DRM_DEBUG_DRIVER("Pushbus not setup properly.\n"); | |
5573 | enable_rc6 = false; | |
5574 | } | |
5575 | ||
5576 | if (!I915_READ(GEN6_GFXPAUSE)) { | |
5577 | DRM_DEBUG_DRIVER("GFX pause not setup properly.\n"); | |
5578 | enable_rc6 = false; | |
5579 | } | |
5580 | ||
5581 | if (!I915_READ(GEN8_MISC_CTRL0)) { | |
5582 | DRM_DEBUG_DRIVER("GPM control not setup properly.\n"); | |
274008e8 SAK |
5583 | enable_rc6 = false; |
5584 | } | |
5585 | ||
5586 | return enable_rc6; | |
5587 | } | |
5588 | ||
dc97997a | 5589 | int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6) |
2b4e57bd | 5590 | { |
e7d66d89 | 5591 | /* No RC6 before Ironlake and code is gone for ilk. */ |
dc97997a | 5592 | if (INTEL_INFO(dev_priv)->gen < 6) |
e6069ca8 ID |
5593 | return 0; |
5594 | ||
274008e8 SAK |
5595 | if (!enable_rc6) |
5596 | return 0; | |
5597 | ||
cc3f90f0 | 5598 | if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) { |
274008e8 SAK |
5599 | DRM_INFO("RC6 disabled by BIOS\n"); |
5600 | return 0; | |
5601 | } | |
5602 | ||
456470eb | 5603 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
5604 | if (enable_rc6 >= 0) { |
5605 | int mask; | |
5606 | ||
dc97997a | 5607 | if (HAS_RC6p(dev_priv)) |
e6069ca8 ID |
5608 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
5609 | INTEL_RC6pp_ENABLE; | |
5610 | else | |
5611 | mask = INTEL_RC6_ENABLE; | |
5612 | ||
5613 | if ((enable_rc6 & mask) != enable_rc6) | |
b99d49cc ID |
5614 | DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d " |
5615 | "(requested %d, valid %d)\n", | |
5616 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
5617 | |
5618 | return enable_rc6 & mask; | |
5619 | } | |
2b4e57bd | 5620 | |
dc97997a | 5621 | if (IS_IVYBRIDGE(dev_priv)) |
cca84a1f | 5622 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
5623 | |
5624 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
5625 | } |
5626 | ||
dc97997a | 5627 | static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) |
3280e8b0 BW |
5628 | { |
5629 | /* All of these values are in units of 50MHz */ | |
773ea9a8 | 5630 | |
93ee2920 | 5631 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
cc3f90f0 | 5632 | if (IS_GEN9_LP(dev_priv)) { |
773ea9a8 | 5633 | u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
35040562 BP |
5634 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; |
5635 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
5636 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; | |
5637 | } else { | |
773ea9a8 | 5638 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
35040562 BP |
5639 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
5640 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
5641 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
5642 | } | |
3280e8b0 | 5643 | /* hw_max = RP0 until we check for overclocking */ |
773ea9a8 | 5644 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
3280e8b0 | 5645 | |
93ee2920 | 5646 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
dc97997a | 5647 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || |
b976dc53 | 5648 | IS_GEN9_BC(dev_priv)) { |
773ea9a8 CW |
5649 | u32 ddcc_status = 0; |
5650 | ||
5651 | if (sandybridge_pcode_read(dev_priv, | |
5652 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
5653 | &ddcc_status) == 0) | |
93ee2920 | 5654 | dev_priv->rps.efficient_freq = |
46efa4ab TR |
5655 | clamp_t(u8, |
5656 | ((ddcc_status >> 8) & 0xff), | |
5657 | dev_priv->rps.min_freq, | |
5658 | dev_priv->rps.max_freq); | |
93ee2920 TR |
5659 | } |
5660 | ||
b976dc53 | 5661 | if (IS_GEN9_BC(dev_priv)) { |
c5e0688c | 5662 | /* Store the frequency values in 16.66 MHZ units, which is |
773ea9a8 CW |
5663 | * the natural hardware unit for SKL |
5664 | */ | |
c5e0688c AG |
5665 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; |
5666 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; | |
5667 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; | |
5668 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; | |
5669 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; | |
5670 | } | |
3280e8b0 BW |
5671 | } |
5672 | ||
3a45b05c | 5673 | static void reset_rps(struct drm_i915_private *dev_priv, |
9fcee2f7 | 5674 | int (*set)(struct drm_i915_private *, u8)) |
3a45b05c CW |
5675 | { |
5676 | u8 freq = dev_priv->rps.cur_freq; | |
5677 | ||
5678 | /* force a reset */ | |
5679 | dev_priv->rps.power = -1; | |
5680 | dev_priv->rps.cur_freq = -1; | |
5681 | ||
9fcee2f7 CW |
5682 | if (set(dev_priv, freq)) |
5683 | DRM_ERROR("Failed to reset RPS to initial values\n"); | |
3a45b05c CW |
5684 | } |
5685 | ||
b6fef0ef | 5686 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
dc97997a | 5687 | static void gen9_enable_rps(struct drm_i915_private *dev_priv) |
b6fef0ef | 5688 | { |
b6fef0ef JB |
5689 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
5690 | ||
0beb059a AG |
5691 | /* Program defaults and thresholds for RPS*/ |
5692 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
5693 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); | |
5694 | ||
5695 | /* 1 second timeout*/ | |
5696 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, | |
5697 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); | |
5698 | ||
b6fef0ef | 5699 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
b6fef0ef | 5700 | |
0beb059a AG |
5701 | /* Leaning on the below call to gen6_set_rps to program/setup the |
5702 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, | |
5703 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ | |
3a45b05c | 5704 | reset_rps(dev_priv, gen6_set_rps); |
b6fef0ef JB |
5705 | |
5706 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
5707 | } | |
5708 | ||
dc97997a | 5709 | static void gen9_enable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 5710 | { |
e2f80391 | 5711 | struct intel_engine_cs *engine; |
3b3f1650 | 5712 | enum intel_engine_id id; |
20e49366 | 5713 | uint32_t rc6_mask = 0; |
20e49366 ZW |
5714 | |
5715 | /* 1a: Software RC state - RC0 */ | |
5716 | I915_WRITE(GEN6_RC_STATE, 0); | |
5717 | ||
5718 | /* 1b: Get forcewake during program sequence. Although the driver | |
5719 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 5720 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
5721 | |
5722 | /* 2a: Disable RC states. */ | |
5723 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5724 | ||
5725 | /* 2b: Program RC6 thresholds.*/ | |
63a4dec2 SAK |
5726 | |
5727 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ | |
dc97997a | 5728 | if (IS_SKYLAKE(dev_priv)) |
63a4dec2 SAK |
5729 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
5730 | else | |
5731 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
20e49366 ZW |
5732 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
5733 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 5734 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 5735 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
97c322e7 | 5736 | |
1a3d1898 | 5737 | if (HAS_GUC(dev_priv)) |
97c322e7 SAK |
5738 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); |
5739 | ||
20e49366 | 5740 | I915_WRITE(GEN6_RC_SLEEP, 0); |
20e49366 | 5741 | |
38c23527 ZW |
5742 | /* 2c: Program Coarse Power Gating Policies. */ |
5743 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
5744 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
5745 | ||
20e49366 | 5746 | /* 3a: Enable RC6 */ |
dc97997a | 5747 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
20e49366 | 5748 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
87ad3212 | 5749 | DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); |
1c044f9b CW |
5750 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
5751 | I915_WRITE(GEN6_RC_CONTROL, | |
5752 | GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask); | |
20e49366 | 5753 | |
cb07bae0 SK |
5754 | /* |
5755 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. | |
f2d2fe95 | 5756 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
cb07bae0 | 5757 | */ |
dc97997a | 5758 | if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) |
f2d2fe95 SAK |
5759 | I915_WRITE(GEN9_PG_ENABLE, 0); |
5760 | else | |
5761 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
5762 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); | |
38c23527 | 5763 | |
59bad947 | 5764 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
5765 | } |
5766 | ||
dc97997a | 5767 | static void gen8_enable_rps(struct drm_i915_private *dev_priv) |
6edee7f3 | 5768 | { |
e2f80391 | 5769 | struct intel_engine_cs *engine; |
3b3f1650 | 5770 | enum intel_engine_id id; |
93ee2920 | 5771 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
5772 | |
5773 | /* 1a: Software RC state - RC0 */ | |
5774 | I915_WRITE(GEN6_RC_STATE, 0); | |
5775 | ||
5776 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
5777 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 5778 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
5779 | |
5780 | /* 2a: Disable RC states. */ | |
5781 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5782 | ||
6edee7f3 BW |
5783 | /* 2b: Program RC6 thresholds.*/ |
5784 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
5785 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
5786 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 5787 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 5788 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
6edee7f3 | 5789 | I915_WRITE(GEN6_RC_SLEEP, 0); |
dc97997a | 5790 | if (IS_BROADWELL(dev_priv)) |
0d68b25e TR |
5791 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
5792 | else | |
5793 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
5794 | |
5795 | /* 3: Enable RC6 */ | |
dc97997a | 5796 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6edee7f3 | 5797 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
dc97997a CW |
5798 | intel_print_rc6_info(dev_priv, rc6_mask); |
5799 | if (IS_BROADWELL(dev_priv)) | |
0d68b25e TR |
5800 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
5801 | GEN7_RC_CTL_TO_MODE | | |
5802 | rc6_mask); | |
5803 | else | |
5804 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
5805 | GEN6_RC_CTL_EI_MODE(1) | | |
5806 | rc6_mask); | |
6edee7f3 BW |
5807 | |
5808 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
5809 | I915_WRITE(GEN6_RPNSWREQ, |
5810 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
5811 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
5812 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
5813 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
5814 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
5815 | ||
5816 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
5817 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
5818 | dev_priv->rps.max_freq_softlimit << 24 | | |
5819 | dev_priv->rps.min_freq_softlimit << 16); | |
5820 | ||
5821 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
5822 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
5823 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
5824 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
5825 | ||
5826 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
5827 | |
5828 | /* 5: Enable RPS */ | |
7526ed79 DV |
5829 | I915_WRITE(GEN6_RP_CONTROL, |
5830 | GEN6_RP_MEDIA_TURBO | | |
5831 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5832 | GEN6_RP_MEDIA_IS_GFX | | |
5833 | GEN6_RP_ENABLE | | |
5834 | GEN6_RP_UP_BUSY_AVG | | |
5835 | GEN6_RP_DOWN_IDLE_AVG); | |
5836 | ||
5837 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
5838 | ||
3a45b05c | 5839 | reset_rps(dev_priv, gen6_set_rps); |
7526ed79 | 5840 | |
59bad947 | 5841 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
5842 | } |
5843 | ||
dc97997a | 5844 | static void gen6_enable_rps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5845 | { |
e2f80391 | 5846 | struct intel_engine_cs *engine; |
3b3f1650 | 5847 | enum intel_engine_id id; |
99ac9612 | 5848 | u32 rc6vids, rc6_mask = 0; |
2b4e57bd | 5849 | u32 gtfifodbg; |
2b4e57bd | 5850 | int rc6_mode; |
b4ac5afc | 5851 | int ret; |
2b4e57bd | 5852 | |
4fc688ce | 5853 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 5854 | |
2b4e57bd ED |
5855 | /* Here begins a magic sequence of register writes to enable |
5856 | * auto-downclocking. | |
5857 | * | |
5858 | * Perhaps there might be some value in exposing these to | |
5859 | * userspace... | |
5860 | */ | |
5861 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
5862 | |
5863 | /* Clear the DBG now so we don't confuse earlier errors */ | |
297b32ec VS |
5864 | gtfifodbg = I915_READ(GTFIFODBG); |
5865 | if (gtfifodbg) { | |
2b4e57bd ED |
5866 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
5867 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
5868 | } | |
5869 | ||
59bad947 | 5870 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
5871 | |
5872 | /* disable the counters and set deterministic thresholds */ | |
5873 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5874 | ||
5875 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
5876 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
5877 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
5878 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
5879 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
5880 | ||
3b3f1650 | 5881 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 5882 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
2b4e57bd ED |
5883 | |
5884 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
5885 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
dc97997a | 5886 | if (IS_IVYBRIDGE(dev_priv)) |
351aa566 SM |
5887 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
5888 | else | |
5889 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 5890 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
5891 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
5892 | ||
5a7dc92a | 5893 | /* Check if we are enabling RC6 */ |
dc97997a | 5894 | rc6_mode = intel_enable_rc6(); |
2b4e57bd ED |
5895 | if (rc6_mode & INTEL_RC6_ENABLE) |
5896 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
5897 | ||
5a7dc92a | 5898 | /* We don't use those on Haswell */ |
dc97997a | 5899 | if (!IS_HASWELL(dev_priv)) { |
5a7dc92a ED |
5900 | if (rc6_mode & INTEL_RC6p_ENABLE) |
5901 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 5902 | |
5a7dc92a ED |
5903 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
5904 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
5905 | } | |
2b4e57bd | 5906 | |
dc97997a | 5907 | intel_print_rc6_info(dev_priv, rc6_mask); |
2b4e57bd ED |
5908 | |
5909 | I915_WRITE(GEN6_RC_CONTROL, | |
5910 | rc6_mask | | |
5911 | GEN6_RC_CTL_EI_MODE(1) | | |
5912 | GEN6_RC_CTL_HW_ENABLE); | |
5913 | ||
dd75fdc8 CW |
5914 | /* Power down if completely idle for over 50ms */ |
5915 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 5916 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 5917 | |
3a45b05c | 5918 | reset_rps(dev_priv, gen6_set_rps); |
2b4e57bd | 5919 | |
31643d54 BW |
5920 | rc6vids = 0; |
5921 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
dc97997a | 5922 | if (IS_GEN6(dev_priv) && ret) { |
31643d54 | 5923 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
dc97997a | 5924 | } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
31643d54 BW |
5925 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
5926 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
5927 | rc6vids &= 0xffff00; | |
5928 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
5929 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
5930 | if (ret) | |
5931 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
5932 | } | |
5933 | ||
59bad947 | 5934 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
5935 | } |
5936 | ||
fb7404e8 | 5937 | static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
2b4e57bd ED |
5938 | { |
5939 | int min_freq = 15; | |
3ebecd07 CW |
5940 | unsigned int gpu_freq; |
5941 | unsigned int max_ia_freq, min_ring_freq; | |
4c8c7743 | 5942 | unsigned int max_gpu_freq, min_gpu_freq; |
2b4e57bd | 5943 | int scaling_factor = 180; |
eda79642 | 5944 | struct cpufreq_policy *policy; |
2b4e57bd | 5945 | |
4fc688ce | 5946 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 5947 | |
eda79642 BW |
5948 | policy = cpufreq_cpu_get(0); |
5949 | if (policy) { | |
5950 | max_ia_freq = policy->cpuinfo.max_freq; | |
5951 | cpufreq_cpu_put(policy); | |
5952 | } else { | |
5953 | /* | |
5954 | * Default to measured freq if none found, PCU will ensure we | |
5955 | * don't go over | |
5956 | */ | |
2b4e57bd | 5957 | max_ia_freq = tsc_khz; |
eda79642 | 5958 | } |
2b4e57bd ED |
5959 | |
5960 | /* Convert from kHz to MHz */ | |
5961 | max_ia_freq /= 1000; | |
5962 | ||
153b4b95 | 5963 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
5964 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
5965 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 5966 | |
b976dc53 | 5967 | if (IS_GEN9_BC(dev_priv)) { |
4c8c7743 AG |
5968 | /* Convert GT frequency to 50 HZ units */ |
5969 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; | |
5970 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; | |
5971 | } else { | |
5972 | min_gpu_freq = dev_priv->rps.min_freq; | |
5973 | max_gpu_freq = dev_priv->rps.max_freq; | |
5974 | } | |
5975 | ||
2b4e57bd ED |
5976 | /* |
5977 | * For each potential GPU frequency, load a ring frequency we'd like | |
5978 | * to use for memory access. We do this by specifying the IA frequency | |
5979 | * the PCU should use as a reference to determine the ring frequency. | |
5980 | */ | |
4c8c7743 AG |
5981 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
5982 | int diff = max_gpu_freq - gpu_freq; | |
3ebecd07 CW |
5983 | unsigned int ia_freq = 0, ring_freq = 0; |
5984 | ||
b976dc53 | 5985 | if (IS_GEN9_BC(dev_priv)) { |
4c8c7743 AG |
5986 | /* |
5987 | * ring_freq = 2 * GT. ring_freq is in 100MHz units | |
5988 | * No floor required for ring frequency on SKL. | |
5989 | */ | |
5990 | ring_freq = gpu_freq; | |
dc97997a | 5991 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
46c764d4 BW |
5992 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
5993 | ring_freq = max(min_ring_freq, gpu_freq); | |
dc97997a | 5994 | } else if (IS_HASWELL(dev_priv)) { |
f6aca45c | 5995 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
5996 | ring_freq = max(min_ring_freq, ring_freq); |
5997 | /* leave ia_freq as the default, chosen by cpufreq */ | |
5998 | } else { | |
5999 | /* On older processors, there is no separate ring | |
6000 | * clock domain, so in order to boost the bandwidth | |
6001 | * of the ring, we need to upclock the CPU (ia_freq). | |
6002 | * | |
6003 | * For GPU frequencies less than 750MHz, | |
6004 | * just use the lowest ring freq. | |
6005 | */ | |
6006 | if (gpu_freq < min_freq) | |
6007 | ia_freq = 800; | |
6008 | else | |
6009 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
6010 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
6011 | } | |
2b4e57bd | 6012 | |
42c0526c BW |
6013 | sandybridge_pcode_write(dev_priv, |
6014 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
6015 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
6016 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
6017 | gpu_freq); | |
2b4e57bd | 6018 | } |
2b4e57bd ED |
6019 | } |
6020 | ||
03af2045 | 6021 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
6022 | { |
6023 | u32 val, rp0; | |
6024 | ||
5b5929cb | 6025 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
2b6b3a09 | 6026 | |
43b67998 | 6027 | switch (INTEL_INFO(dev_priv)->sseu.eu_total) { |
5b5929cb JN |
6028 | case 8: |
6029 | /* (2 * 4) config */ | |
6030 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
6031 | break; | |
6032 | case 12: | |
6033 | /* (2 * 6) config */ | |
6034 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
6035 | break; | |
6036 | case 16: | |
6037 | /* (2 * 8) config */ | |
6038 | default: | |
6039 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
6040 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
6041 | break; | |
095acd5f | 6042 | } |
5b5929cb JN |
6043 | |
6044 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
6045 | ||
2b6b3a09 D |
6046 | return rp0; |
6047 | } | |
6048 | ||
6049 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
6050 | { | |
6051 | u32 val, rpe; | |
6052 | ||
6053 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
6054 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
6055 | ||
6056 | return rpe; | |
6057 | } | |
6058 | ||
7707df4a D |
6059 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
6060 | { | |
6061 | u32 val, rp1; | |
6062 | ||
5b5929cb JN |
6063 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
6064 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
6065 | ||
7707df4a D |
6066 | return rp1; |
6067 | } | |
6068 | ||
96676fe3 D |
6069 | static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
6070 | { | |
6071 | u32 val, rpn; | |
6072 | ||
6073 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); | |
6074 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & | |
6075 | FB_GFX_FREQ_FUSE_MASK); | |
6076 | ||
6077 | return rpn; | |
6078 | } | |
6079 | ||
f8f2b001 D |
6080 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
6081 | { | |
6082 | u32 val, rp1; | |
6083 | ||
6084 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
6085 | ||
6086 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
6087 | ||
6088 | return rp1; | |
6089 | } | |
6090 | ||
03af2045 | 6091 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
6092 | { |
6093 | u32 val, rp0; | |
6094 | ||
64936258 | 6095 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
6096 | |
6097 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
6098 | /* Clamp to max */ | |
6099 | rp0 = min_t(u32, rp0, 0xea); | |
6100 | ||
6101 | return rp0; | |
6102 | } | |
6103 | ||
6104 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
6105 | { | |
6106 | u32 val, rpe; | |
6107 | ||
64936258 | 6108 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 6109 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 6110 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
6111 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
6112 | ||
6113 | return rpe; | |
6114 | } | |
6115 | ||
03af2045 | 6116 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 6117 | { |
36146035 ID |
6118 | u32 val; |
6119 | ||
6120 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; | |
6121 | /* | |
6122 | * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value | |
6123 | * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on | |
6124 | * a BYT-M B0 the above register contains 0xbf. Moreover when setting | |
6125 | * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 | |
6126 | * to make sure it matches what Punit accepts. | |
6127 | */ | |
6128 | return max_t(u32, val, 0xc0); | |
0a073b84 JB |
6129 | } |
6130 | ||
ae48434c ID |
6131 | /* Check that the pctx buffer wasn't move under us. */ |
6132 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
6133 | { | |
6134 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6135 | ||
6136 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
6137 | dev_priv->vlv_pctx->stolen->start); | |
6138 | } | |
6139 | ||
38807746 D |
6140 | |
6141 | /* Check that the pcbr address is not empty. */ | |
6142 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
6143 | { | |
6144 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6145 | ||
6146 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
6147 | } | |
6148 | ||
dc97997a | 6149 | static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) |
38807746 | 6150 | { |
62106b4f | 6151 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 6152 | unsigned long pctx_paddr, paddr; |
38807746 D |
6153 | u32 pcbr; |
6154 | int pctx_size = 32*1024; | |
6155 | ||
38807746 D |
6156 | pcbr = I915_READ(VLV_PCBR); |
6157 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 6158 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 | 6159 | paddr = (dev_priv->mm.stolen_base + |
62106b4f | 6160 | (ggtt->stolen_size - pctx_size)); |
38807746 D |
6161 | |
6162 | pctx_paddr = (paddr & (~4095)); | |
6163 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6164 | } | |
ce611ef8 VS |
6165 | |
6166 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
6167 | } |
6168 | ||
dc97997a | 6169 | static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) |
c9cddffc | 6170 | { |
c9cddffc JB |
6171 | struct drm_i915_gem_object *pctx; |
6172 | unsigned long pctx_paddr; | |
6173 | u32 pcbr; | |
6174 | int pctx_size = 24*1024; | |
6175 | ||
6176 | pcbr = I915_READ(VLV_PCBR); | |
6177 | if (pcbr) { | |
6178 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
6179 | int pcbr_offset; | |
6180 | ||
6181 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
187685cb | 6182 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
c9cddffc | 6183 | pcbr_offset, |
190d6cd5 | 6184 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
6185 | pctx_size); |
6186 | goto out; | |
6187 | } | |
6188 | ||
ce611ef8 VS |
6189 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
6190 | ||
c9cddffc JB |
6191 | /* |
6192 | * From the Gunit register HAS: | |
6193 | * The Gfx driver is expected to program this register and ensure | |
6194 | * proper allocation within Gfx stolen memory. For example, this | |
6195 | * register should be programmed such than the PCBR range does not | |
6196 | * overlap with other ranges, such as the frame buffer, protected | |
6197 | * memory, or any other relevant ranges. | |
6198 | */ | |
187685cb | 6199 | pctx = i915_gem_object_create_stolen(dev_priv, pctx_size); |
c9cddffc JB |
6200 | if (!pctx) { |
6201 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
ee504898 | 6202 | goto out; |
c9cddffc JB |
6203 | } |
6204 | ||
6205 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
6206 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6207 | ||
6208 | out: | |
ce611ef8 | 6209 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
6210 | dev_priv->vlv_pctx = pctx; |
6211 | } | |
6212 | ||
dc97997a | 6213 | static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv) |
ae48434c | 6214 | { |
ae48434c ID |
6215 | if (WARN_ON(!dev_priv->vlv_pctx)) |
6216 | return; | |
6217 | ||
f0cd5182 | 6218 | i915_gem_object_put(dev_priv->vlv_pctx); |
ae48434c ID |
6219 | dev_priv->vlv_pctx = NULL; |
6220 | } | |
6221 | ||
c30fec65 VS |
6222 | static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv) |
6223 | { | |
6224 | dev_priv->rps.gpll_ref_freq = | |
6225 | vlv_get_cck_clock(dev_priv, "GPLL ref", | |
6226 | CCK_GPLL_CLOCK_CONTROL, | |
6227 | dev_priv->czclk_freq); | |
6228 | ||
6229 | DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n", | |
6230 | dev_priv->rps.gpll_ref_freq); | |
6231 | } | |
6232 | ||
dc97997a | 6233 | static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 6234 | { |
2bb25c17 | 6235 | u32 val; |
4e80519e | 6236 | |
dc97997a | 6237 | valleyview_setup_pctx(dev_priv); |
4e80519e | 6238 | |
c30fec65 VS |
6239 | vlv_init_gpll_ref_freq(dev_priv); |
6240 | ||
2bb25c17 VS |
6241 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
6242 | switch ((val >> 6) & 3) { | |
6243 | case 0: | |
6244 | case 1: | |
6245 | dev_priv->mem_freq = 800; | |
6246 | break; | |
6247 | case 2: | |
6248 | dev_priv->mem_freq = 1066; | |
6249 | break; | |
6250 | case 3: | |
6251 | dev_priv->mem_freq = 1333; | |
6252 | break; | |
6253 | } | |
80b83b62 | 6254 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 6255 | |
4e80519e ID |
6256 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
6257 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
6258 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6259 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
6260 | dev_priv->rps.max_freq); |
6261 | ||
6262 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
6263 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6264 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
6265 | dev_priv->rps.efficient_freq); |
6266 | ||
f8f2b001 D |
6267 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
6268 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6269 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
6270 | dev_priv->rps.rp1_freq); |
6271 | ||
4e80519e ID |
6272 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
6273 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6274 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e | 6275 | dev_priv->rps.min_freq); |
4e80519e ID |
6276 | } |
6277 | ||
dc97997a | 6278 | static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) |
38807746 | 6279 | { |
2bb25c17 | 6280 | u32 val; |
2b6b3a09 | 6281 | |
dc97997a | 6282 | cherryview_setup_pctx(dev_priv); |
2b6b3a09 | 6283 | |
c30fec65 VS |
6284 | vlv_init_gpll_ref_freq(dev_priv); |
6285 | ||
a580516d | 6286 | mutex_lock(&dev_priv->sb_lock); |
c6e8f39d | 6287 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
a580516d | 6288 | mutex_unlock(&dev_priv->sb_lock); |
c6e8f39d | 6289 | |
2bb25c17 | 6290 | switch ((val >> 2) & 0x7) { |
2bb25c17 | 6291 | case 3: |
2bb25c17 VS |
6292 | dev_priv->mem_freq = 2000; |
6293 | break; | |
bfa7df01 | 6294 | default: |
2bb25c17 VS |
6295 | dev_priv->mem_freq = 1600; |
6296 | break; | |
6297 | } | |
80b83b62 | 6298 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 6299 | |
2b6b3a09 D |
6300 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
6301 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
6302 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6303 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
6304 | dev_priv->rps.max_freq); |
6305 | ||
6306 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
6307 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6308 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
6309 | dev_priv->rps.efficient_freq); |
6310 | ||
7707df4a D |
6311 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
6312 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6313 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
6314 | dev_priv->rps.rp1_freq); |
6315 | ||
96676fe3 | 6316 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
2b6b3a09 | 6317 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 6318 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
6319 | dev_priv->rps.min_freq); |
6320 | ||
1c14762d VS |
6321 | WARN_ONCE((dev_priv->rps.max_freq | |
6322 | dev_priv->rps.efficient_freq | | |
6323 | dev_priv->rps.rp1_freq | | |
6324 | dev_priv->rps.min_freq) & 1, | |
6325 | "Odd GPU freq values\n"); | |
38807746 D |
6326 | } |
6327 | ||
dc97997a | 6328 | static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 6329 | { |
dc97997a | 6330 | valleyview_cleanup_pctx(dev_priv); |
4e80519e ID |
6331 | } |
6332 | ||
dc97997a | 6333 | static void cherryview_enable_rps(struct drm_i915_private *dev_priv) |
38807746 | 6334 | { |
e2f80391 | 6335 | struct intel_engine_cs *engine; |
3b3f1650 | 6336 | enum intel_engine_id id; |
2b6b3a09 | 6337 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
6338 | |
6339 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
6340 | ||
297b32ec VS |
6341 | gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | |
6342 | GT_FIFO_FREE_ENTRIES_CHV); | |
38807746 D |
6343 | if (gtfifodbg) { |
6344 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
6345 | gtfifodbg); | |
6346 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
6347 | } | |
6348 | ||
6349 | cherryview_check_pctx(dev_priv); | |
6350 | ||
6351 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
6352 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 6353 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 6354 | |
160614a2 VS |
6355 | /* Disable RC states. */ |
6356 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6357 | ||
38807746 D |
6358 | /* 2a: Program RC6 thresholds.*/ |
6359 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
6360 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
6361 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
6362 | ||
3b3f1650 | 6363 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6364 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
38807746 D |
6365 | I915_WRITE(GEN6_RC_SLEEP, 0); |
6366 | ||
f4f71c7d D |
6367 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
6368 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); | |
38807746 D |
6369 | |
6370 | /* allows RC6 residency counter to work */ | |
6371 | I915_WRITE(VLV_COUNTER_CONTROL, | |
6372 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
6373 | VLV_MEDIA_RC6_COUNT_EN | | |
6374 | VLV_RENDER_RC6_COUNT_EN)); | |
6375 | ||
6376 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
6377 | pcbr = I915_READ(VLV_PCBR); | |
6378 | ||
38807746 | 6379 | /* 3: Enable RC6 */ |
dc97997a CW |
6380 | if ((intel_enable_rc6() & INTEL_RC6_ENABLE) && |
6381 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 6382 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
6383 | |
6384 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
6385 | ||
2b6b3a09 | 6386 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 6387 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
6388 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
6389 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
6390 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
6391 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
6392 | ||
6393 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6394 | ||
6395 | /* 5: Enable RPS */ | |
6396 | I915_WRITE(GEN6_RP_CONTROL, | |
6397 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 6398 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
6399 | GEN6_RP_ENABLE | |
6400 | GEN6_RP_UP_BUSY_AVG | | |
6401 | GEN6_RP_DOWN_IDLE_AVG); | |
6402 | ||
3ef62342 D |
6403 | /* Setting Fixed Bias */ |
6404 | val = VLV_OVERRIDE_EN | | |
6405 | VLV_SOC_TDP_EN | | |
6406 | CHV_BIAS_CPU_50_SOC_50; | |
6407 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
6408 | ||
2b6b3a09 D |
6409 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
6410 | ||
8d40c3ae VS |
6411 | /* RPS code assumes GPLL is used */ |
6412 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
6413 | ||
742f491d | 6414 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
2b6b3a09 D |
6415 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
6416 | ||
3a45b05c | 6417 | reset_rps(dev_priv, valleyview_set_rps); |
2b6b3a09 | 6418 | |
59bad947 | 6419 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
6420 | } |
6421 | ||
dc97997a | 6422 | static void valleyview_enable_rps(struct drm_i915_private *dev_priv) |
0a073b84 | 6423 | { |
e2f80391 | 6424 | struct intel_engine_cs *engine; |
3b3f1650 | 6425 | enum intel_engine_id id; |
2a5913a8 | 6426 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
6427 | |
6428 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
6429 | ||
ae48434c ID |
6430 | valleyview_check_pctx(dev_priv); |
6431 | ||
297b32ec VS |
6432 | gtfifodbg = I915_READ(GTFIFODBG); |
6433 | if (gtfifodbg) { | |
f7d85c1e JB |
6434 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
6435 | gtfifodbg); | |
0a073b84 JB |
6436 | I915_WRITE(GTFIFODBG, gtfifodbg); |
6437 | } | |
6438 | ||
c8d9a590 | 6439 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 6440 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 6441 | |
160614a2 VS |
6442 | /* Disable RC states. */ |
6443 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6444 | ||
cad725fe | 6445 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
6446 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
6447 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
6448 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
6449 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
6450 | ||
6451 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6452 | ||
6453 | I915_WRITE(GEN6_RP_CONTROL, | |
6454 | GEN6_RP_MEDIA_TURBO | | |
6455 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
6456 | GEN6_RP_MEDIA_IS_GFX | | |
6457 | GEN6_RP_ENABLE | | |
6458 | GEN6_RP_UP_BUSY_AVG | | |
6459 | GEN6_RP_DOWN_IDLE_CONT); | |
6460 | ||
6461 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
6462 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
6463 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
6464 | ||
3b3f1650 | 6465 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6466 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
0a073b84 | 6467 | |
2f0aa304 | 6468 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
6469 | |
6470 | /* allows RC6 residency counter to work */ | |
49798eb2 | 6471 | I915_WRITE(VLV_COUNTER_CONTROL, |
6b7f6aa7 MK |
6472 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
6473 | VLV_MEDIA_RC0_COUNT_EN | | |
31685c25 | 6474 | VLV_RENDER_RC0_COUNT_EN | |
49798eb2 JB |
6475 | VLV_MEDIA_RC6_COUNT_EN | |
6476 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 6477 | |
dc97997a | 6478 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6b88f295 | 6479 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 | 6480 | |
dc97997a | 6481 | intel_print_rc6_info(dev_priv, rc6_mode); |
dc39fff7 | 6482 | |
a2b23fe0 | 6483 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 6484 | |
3ef62342 D |
6485 | /* Setting Fixed Bias */ |
6486 | val = VLV_OVERRIDE_EN | | |
6487 | VLV_SOC_TDP_EN | | |
6488 | VLV_BIAS_CPU_125_SOC_875; | |
6489 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
6490 | ||
64936258 | 6491 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 6492 | |
8d40c3ae VS |
6493 | /* RPS code assumes GPLL is used */ |
6494 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
6495 | ||
742f491d | 6496 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
0a073b84 JB |
6497 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
6498 | ||
3a45b05c | 6499 | reset_rps(dev_priv, valleyview_set_rps); |
0a073b84 | 6500 | |
59bad947 | 6501 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
6502 | } |
6503 | ||
dde18883 ED |
6504 | static unsigned long intel_pxfreq(u32 vidfreq) |
6505 | { | |
6506 | unsigned long freq; | |
6507 | int div = (vidfreq & 0x3f0000) >> 16; | |
6508 | int post = (vidfreq & 0x3000) >> 12; | |
6509 | int pre = (vidfreq & 0x7); | |
6510 | ||
6511 | if (!pre) | |
6512 | return 0; | |
6513 | ||
6514 | freq = ((div * 133333) / ((1<<post) * pre)); | |
6515 | ||
6516 | return freq; | |
6517 | } | |
6518 | ||
eb48eb00 DV |
6519 | static const struct cparams { |
6520 | u16 i; | |
6521 | u16 t; | |
6522 | u16 m; | |
6523 | u16 c; | |
6524 | } cparams[] = { | |
6525 | { 1, 1333, 301, 28664 }, | |
6526 | { 1, 1066, 294, 24460 }, | |
6527 | { 1, 800, 294, 25192 }, | |
6528 | { 0, 1333, 276, 27605 }, | |
6529 | { 0, 1066, 276, 27605 }, | |
6530 | { 0, 800, 231, 23784 }, | |
6531 | }; | |
6532 | ||
f531dcb2 | 6533 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
6534 | { |
6535 | u64 total_count, diff, ret; | |
6536 | u32 count1, count2, count3, m = 0, c = 0; | |
6537 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
6538 | int i; | |
6539 | ||
67520415 | 6540 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 6541 | |
20e4d407 | 6542 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
6543 | |
6544 | /* Prevent division-by-zero if we are asking too fast. | |
6545 | * Also, we don't get interesting results if we are polling | |
6546 | * faster than once in 10ms, so just return the saved value | |
6547 | * in such cases. | |
6548 | */ | |
6549 | if (diff1 <= 10) | |
20e4d407 | 6550 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
6551 | |
6552 | count1 = I915_READ(DMIEC); | |
6553 | count2 = I915_READ(DDREC); | |
6554 | count3 = I915_READ(CSIEC); | |
6555 | ||
6556 | total_count = count1 + count2 + count3; | |
6557 | ||
6558 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
6559 | if (total_count < dev_priv->ips.last_count1) { |
6560 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
6561 | diff += total_count; |
6562 | } else { | |
20e4d407 | 6563 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
6564 | } |
6565 | ||
6566 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
6567 | if (cparams[i].i == dev_priv->ips.c_m && |
6568 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
6569 | m = cparams[i].m; |
6570 | c = cparams[i].c; | |
6571 | break; | |
6572 | } | |
6573 | } | |
6574 | ||
6575 | diff = div_u64(diff, diff1); | |
6576 | ret = ((m * diff) + c); | |
6577 | ret = div_u64(ret, 10); | |
6578 | ||
20e4d407 DV |
6579 | dev_priv->ips.last_count1 = total_count; |
6580 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 6581 | |
20e4d407 | 6582 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
6583 | |
6584 | return ret; | |
6585 | } | |
6586 | ||
f531dcb2 CW |
6587 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
6588 | { | |
6589 | unsigned long val; | |
6590 | ||
dc97997a | 6591 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
6592 | return 0; |
6593 | ||
6594 | spin_lock_irq(&mchdev_lock); | |
6595 | ||
6596 | val = __i915_chipset_val(dev_priv); | |
6597 | ||
6598 | spin_unlock_irq(&mchdev_lock); | |
6599 | ||
6600 | return val; | |
6601 | } | |
6602 | ||
eb48eb00 DV |
6603 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
6604 | { | |
6605 | unsigned long m, x, b; | |
6606 | u32 tsfs; | |
6607 | ||
6608 | tsfs = I915_READ(TSFS); | |
6609 | ||
6610 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
6611 | x = I915_READ8(TR1); | |
6612 | ||
6613 | b = tsfs & TSFS_INTR_MASK; | |
6614 | ||
6615 | return ((m * x) / 127) - b; | |
6616 | } | |
6617 | ||
d972d6ee MK |
6618 | static int _pxvid_to_vd(u8 pxvid) |
6619 | { | |
6620 | if (pxvid == 0) | |
6621 | return 0; | |
6622 | ||
6623 | if (pxvid >= 8 && pxvid < 31) | |
6624 | pxvid = 31; | |
6625 | ||
6626 | return (pxvid + 2) * 125; | |
6627 | } | |
6628 | ||
6629 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 6630 | { |
d972d6ee MK |
6631 | const int vd = _pxvid_to_vd(pxvid); |
6632 | const int vm = vd - 1125; | |
6633 | ||
dc97997a | 6634 | if (INTEL_INFO(dev_priv)->is_mobile) |
d972d6ee MK |
6635 | return vm > 0 ? vm : 0; |
6636 | ||
6637 | return vd; | |
eb48eb00 DV |
6638 | } |
6639 | ||
02d71956 | 6640 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 6641 | { |
5ed0bdf2 | 6642 | u64 now, diff, diffms; |
eb48eb00 DV |
6643 | u32 count; |
6644 | ||
67520415 | 6645 | lockdep_assert_held(&mchdev_lock); |
eb48eb00 | 6646 | |
5ed0bdf2 TG |
6647 | now = ktime_get_raw_ns(); |
6648 | diffms = now - dev_priv->ips.last_time2; | |
6649 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
6650 | |
6651 | /* Don't divide by 0 */ | |
eb48eb00 DV |
6652 | if (!diffms) |
6653 | return; | |
6654 | ||
6655 | count = I915_READ(GFXEC); | |
6656 | ||
20e4d407 DV |
6657 | if (count < dev_priv->ips.last_count2) { |
6658 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
6659 | diff += count; |
6660 | } else { | |
20e4d407 | 6661 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
6662 | } |
6663 | ||
20e4d407 DV |
6664 | dev_priv->ips.last_count2 = count; |
6665 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
6666 | |
6667 | /* More magic constants... */ | |
6668 | diff = diff * 1181; | |
6669 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 6670 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
6671 | } |
6672 | ||
02d71956 DV |
6673 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
6674 | { | |
dc97997a | 6675 | if (INTEL_INFO(dev_priv)->gen != 5) |
02d71956 DV |
6676 | return; |
6677 | ||
9270388e | 6678 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
6679 | |
6680 | __i915_update_gfx_val(dev_priv); | |
6681 | ||
9270388e | 6682 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
6683 | } |
6684 | ||
f531dcb2 | 6685 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
6686 | { |
6687 | unsigned long t, corr, state1, corr2, state2; | |
6688 | u32 pxvid, ext_v; | |
6689 | ||
67520415 | 6690 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 6691 | |
616847e7 | 6692 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
eb48eb00 DV |
6693 | pxvid = (pxvid >> 24) & 0x7f; |
6694 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
6695 | ||
6696 | state1 = ext_v; | |
6697 | ||
6698 | t = i915_mch_val(dev_priv); | |
6699 | ||
6700 | /* Revel in the empirically derived constants */ | |
6701 | ||
6702 | /* Correction factor in 1/100000 units */ | |
6703 | if (t > 80) | |
6704 | corr = ((t * 2349) + 135940); | |
6705 | else if (t >= 50) | |
6706 | corr = ((t * 964) + 29317); | |
6707 | else /* < 50 */ | |
6708 | corr = ((t * 301) + 1004); | |
6709 | ||
6710 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
6711 | corr /= 100000; | |
20e4d407 | 6712 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
6713 | |
6714 | state2 = (corr2 * state1) / 10000; | |
6715 | state2 /= 100; /* convert to mW */ | |
6716 | ||
02d71956 | 6717 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 6718 | |
20e4d407 | 6719 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
6720 | } |
6721 | ||
f531dcb2 CW |
6722 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
6723 | { | |
6724 | unsigned long val; | |
6725 | ||
dc97997a | 6726 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
6727 | return 0; |
6728 | ||
6729 | spin_lock_irq(&mchdev_lock); | |
6730 | ||
6731 | val = __i915_gfx_val(dev_priv); | |
6732 | ||
6733 | spin_unlock_irq(&mchdev_lock); | |
6734 | ||
6735 | return val; | |
6736 | } | |
6737 | ||
eb48eb00 DV |
6738 | /** |
6739 | * i915_read_mch_val - return value for IPS use | |
6740 | * | |
6741 | * Calculate and return a value for the IPS driver to use when deciding whether | |
6742 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
6743 | */ | |
6744 | unsigned long i915_read_mch_val(void) | |
6745 | { | |
6746 | struct drm_i915_private *dev_priv; | |
6747 | unsigned long chipset_val, graphics_val, ret = 0; | |
6748 | ||
9270388e | 6749 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6750 | if (!i915_mch_dev) |
6751 | goto out_unlock; | |
6752 | dev_priv = i915_mch_dev; | |
6753 | ||
f531dcb2 CW |
6754 | chipset_val = __i915_chipset_val(dev_priv); |
6755 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
6756 | |
6757 | ret = chipset_val + graphics_val; | |
6758 | ||
6759 | out_unlock: | |
9270388e | 6760 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6761 | |
6762 | return ret; | |
6763 | } | |
6764 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
6765 | ||
6766 | /** | |
6767 | * i915_gpu_raise - raise GPU frequency limit | |
6768 | * | |
6769 | * Raise the limit; IPS indicates we have thermal headroom. | |
6770 | */ | |
6771 | bool i915_gpu_raise(void) | |
6772 | { | |
6773 | struct drm_i915_private *dev_priv; | |
6774 | bool ret = true; | |
6775 | ||
9270388e | 6776 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6777 | if (!i915_mch_dev) { |
6778 | ret = false; | |
6779 | goto out_unlock; | |
6780 | } | |
6781 | dev_priv = i915_mch_dev; | |
6782 | ||
20e4d407 DV |
6783 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
6784 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
6785 | |
6786 | out_unlock: | |
9270388e | 6787 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6788 | |
6789 | return ret; | |
6790 | } | |
6791 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
6792 | ||
6793 | /** | |
6794 | * i915_gpu_lower - lower GPU frequency limit | |
6795 | * | |
6796 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
6797 | * frequency maximum. | |
6798 | */ | |
6799 | bool i915_gpu_lower(void) | |
6800 | { | |
6801 | struct drm_i915_private *dev_priv; | |
6802 | bool ret = true; | |
6803 | ||
9270388e | 6804 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6805 | if (!i915_mch_dev) { |
6806 | ret = false; | |
6807 | goto out_unlock; | |
6808 | } | |
6809 | dev_priv = i915_mch_dev; | |
6810 | ||
20e4d407 DV |
6811 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
6812 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
6813 | |
6814 | out_unlock: | |
9270388e | 6815 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6816 | |
6817 | return ret; | |
6818 | } | |
6819 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
6820 | ||
6821 | /** | |
6822 | * i915_gpu_busy - indicate GPU business to IPS | |
6823 | * | |
6824 | * Tell the IPS driver whether or not the GPU is busy. | |
6825 | */ | |
6826 | bool i915_gpu_busy(void) | |
6827 | { | |
eb48eb00 DV |
6828 | bool ret = false; |
6829 | ||
9270388e | 6830 | spin_lock_irq(&mchdev_lock); |
dcff85c8 CW |
6831 | if (i915_mch_dev) |
6832 | ret = i915_mch_dev->gt.awake; | |
9270388e | 6833 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6834 | |
6835 | return ret; | |
6836 | } | |
6837 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
6838 | ||
6839 | /** | |
6840 | * i915_gpu_turbo_disable - disable graphics turbo | |
6841 | * | |
6842 | * Disable graphics turbo by resetting the max frequency and setting the | |
6843 | * current frequency to the default. | |
6844 | */ | |
6845 | bool i915_gpu_turbo_disable(void) | |
6846 | { | |
6847 | struct drm_i915_private *dev_priv; | |
6848 | bool ret = true; | |
6849 | ||
9270388e | 6850 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6851 | if (!i915_mch_dev) { |
6852 | ret = false; | |
6853 | goto out_unlock; | |
6854 | } | |
6855 | dev_priv = i915_mch_dev; | |
6856 | ||
20e4d407 | 6857 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 6858 | |
91d14251 | 6859 | if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart)) |
eb48eb00 DV |
6860 | ret = false; |
6861 | ||
6862 | out_unlock: | |
9270388e | 6863 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6864 | |
6865 | return ret; | |
6866 | } | |
6867 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
6868 | ||
6869 | /** | |
6870 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
6871 | * IPS got loaded first. | |
6872 | * | |
6873 | * This awkward dance is so that neither module has to depend on the | |
6874 | * other in order for IPS to do the appropriate communication of | |
6875 | * GPU turbo limits to i915. | |
6876 | */ | |
6877 | static void | |
6878 | ips_ping_for_i915_load(void) | |
6879 | { | |
6880 | void (*link)(void); | |
6881 | ||
6882 | link = symbol_get(ips_link_to_i915_driver); | |
6883 | if (link) { | |
6884 | link(); | |
6885 | symbol_put(ips_link_to_i915_driver); | |
6886 | } | |
6887 | } | |
6888 | ||
6889 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
6890 | { | |
02d71956 DV |
6891 | /* We only register the i915 ips part with intel-ips once everything is |
6892 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 6893 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 6894 | i915_mch_dev = dev_priv; |
9270388e | 6895 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6896 | |
6897 | ips_ping_for_i915_load(); | |
6898 | } | |
6899 | ||
6900 | void intel_gpu_ips_teardown(void) | |
6901 | { | |
9270388e | 6902 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 6903 | i915_mch_dev = NULL; |
9270388e | 6904 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 6905 | } |
76c3552f | 6906 | |
dc97997a | 6907 | static void intel_init_emon(struct drm_i915_private *dev_priv) |
dde18883 | 6908 | { |
dde18883 ED |
6909 | u32 lcfuse; |
6910 | u8 pxw[16]; | |
6911 | int i; | |
6912 | ||
6913 | /* Disable to program */ | |
6914 | I915_WRITE(ECR, 0); | |
6915 | POSTING_READ(ECR); | |
6916 | ||
6917 | /* Program energy weights for various events */ | |
6918 | I915_WRITE(SDEW, 0x15040d00); | |
6919 | I915_WRITE(CSIEW0, 0x007f0000); | |
6920 | I915_WRITE(CSIEW1, 0x1e220004); | |
6921 | I915_WRITE(CSIEW2, 0x04000004); | |
6922 | ||
6923 | for (i = 0; i < 5; i++) | |
616847e7 | 6924 | I915_WRITE(PEW(i), 0); |
dde18883 | 6925 | for (i = 0; i < 3; i++) |
616847e7 | 6926 | I915_WRITE(DEW(i), 0); |
dde18883 ED |
6927 | |
6928 | /* Program P-state weights to account for frequency power adjustment */ | |
6929 | for (i = 0; i < 16; i++) { | |
616847e7 | 6930 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
dde18883 ED |
6931 | unsigned long freq = intel_pxfreq(pxvidfreq); |
6932 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
6933 | PXVFREQ_PX_SHIFT; | |
6934 | unsigned long val; | |
6935 | ||
6936 | val = vid * vid; | |
6937 | val *= (freq / 1000); | |
6938 | val *= 255; | |
6939 | val /= (127*127*900); | |
6940 | if (val > 0xff) | |
6941 | DRM_ERROR("bad pxval: %ld\n", val); | |
6942 | pxw[i] = val; | |
6943 | } | |
6944 | /* Render standby states get 0 weight */ | |
6945 | pxw[14] = 0; | |
6946 | pxw[15] = 0; | |
6947 | ||
6948 | for (i = 0; i < 4; i++) { | |
6949 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
6950 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
616847e7 | 6951 | I915_WRITE(PXW(i), val); |
dde18883 ED |
6952 | } |
6953 | ||
6954 | /* Adjust magic regs to magic values (more experimental results) */ | |
6955 | I915_WRITE(OGW0, 0); | |
6956 | I915_WRITE(OGW1, 0); | |
6957 | I915_WRITE(EG0, 0x00007f00); | |
6958 | I915_WRITE(EG1, 0x0000000e); | |
6959 | I915_WRITE(EG2, 0x000e0000); | |
6960 | I915_WRITE(EG3, 0x68000300); | |
6961 | I915_WRITE(EG4, 0x42000000); | |
6962 | I915_WRITE(EG5, 0x00140031); | |
6963 | I915_WRITE(EG6, 0); | |
6964 | I915_WRITE(EG7, 0); | |
6965 | ||
6966 | for (i = 0; i < 8; i++) | |
616847e7 | 6967 | I915_WRITE(PXWL(i), 0); |
dde18883 ED |
6968 | |
6969 | /* Enable PMON + select events */ | |
6970 | I915_WRITE(ECR, 0x80000019); | |
6971 | ||
6972 | lcfuse = I915_READ(LCFUSE02); | |
6973 | ||
20e4d407 | 6974 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
6975 | } |
6976 | ||
dc97997a | 6977 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 6978 | { |
b268c699 ID |
6979 | /* |
6980 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
6981 | * requirement. | |
6982 | */ | |
6983 | if (!i915.enable_rc6) { | |
6984 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
6985 | intel_runtime_pm_get(dev_priv); | |
6986 | } | |
e6069ca8 | 6987 | |
b5163dbb | 6988 | mutex_lock(&dev_priv->drm.struct_mutex); |
773ea9a8 CW |
6989 | mutex_lock(&dev_priv->rps.hw_lock); |
6990 | ||
6991 | /* Initialize RPS limits (for userspace) */ | |
dc97997a CW |
6992 | if (IS_CHERRYVIEW(dev_priv)) |
6993 | cherryview_init_gt_powersave(dev_priv); | |
6994 | else if (IS_VALLEYVIEW(dev_priv)) | |
6995 | valleyview_init_gt_powersave(dev_priv); | |
2a13ae79 | 6996 | else if (INTEL_GEN(dev_priv) >= 6) |
773ea9a8 CW |
6997 | gen6_init_rps_frequencies(dev_priv); |
6998 | ||
6999 | /* Derive initial user preferences/limits from the hardware limits */ | |
7000 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; | |
7001 | dev_priv->rps.cur_freq = dev_priv->rps.idle_freq; | |
7002 | ||
7003 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
7004 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
7005 | ||
7006 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
7007 | dev_priv->rps.min_freq_softlimit = | |
7008 | max_t(int, | |
7009 | dev_priv->rps.efficient_freq, | |
7010 | intel_freq_opcode(dev_priv, 450)); | |
7011 | ||
99ac9612 CW |
7012 | /* After setting max-softlimit, find the overclock max freq */ |
7013 | if (IS_GEN6(dev_priv) || | |
7014 | IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { | |
7015 | u32 params = 0; | |
7016 | ||
7017 | sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms); | |
7018 | if (params & BIT(31)) { /* OC supported */ | |
7019 | DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n", | |
7020 | (dev_priv->rps.max_freq & 0xff) * 50, | |
7021 | (params & 0xff) * 50); | |
7022 | dev_priv->rps.max_freq = params & 0xff; | |
7023 | } | |
7024 | } | |
7025 | ||
29ecd78d CW |
7026 | /* Finally allow us to boost to max by default */ |
7027 | dev_priv->rps.boost_freq = dev_priv->rps.max_freq; | |
7028 | ||
773ea9a8 | 7029 | mutex_unlock(&dev_priv->rps.hw_lock); |
b5163dbb | 7030 | mutex_unlock(&dev_priv->drm.struct_mutex); |
54b4f68f CW |
7031 | |
7032 | intel_autoenable_gt_powersave(dev_priv); | |
ae48434c ID |
7033 | } |
7034 | ||
dc97997a | 7035 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 7036 | { |
8dac1e1f | 7037 | if (IS_VALLEYVIEW(dev_priv)) |
dc97997a | 7038 | valleyview_cleanup_gt_powersave(dev_priv); |
b268c699 ID |
7039 | |
7040 | if (!i915.enable_rc6) | |
7041 | intel_runtime_pm_put(dev_priv); | |
ae48434c ID |
7042 | } |
7043 | ||
54b4f68f CW |
7044 | /** |
7045 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
7046 | * @dev_priv: i915 device | |
7047 | * | |
7048 | * We don't want to disable RC6 or other features here, we just want | |
7049 | * to make sure any work we've queued has finished and won't bother | |
7050 | * us while we're suspended. | |
7051 | */ | |
7052 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) | |
7053 | { | |
7054 | if (INTEL_GEN(dev_priv) < 6) | |
7055 | return; | |
7056 | ||
7057 | if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) | |
7058 | intel_runtime_pm_put(dev_priv); | |
7059 | ||
7060 | /* gen6_rps_idle() will be called later to disable interrupts */ | |
7061 | } | |
7062 | ||
b7137e0c CW |
7063 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) |
7064 | { | |
7065 | dev_priv->rps.enabled = true; /* force disabling */ | |
7066 | intel_disable_gt_powersave(dev_priv); | |
54b4f68f CW |
7067 | |
7068 | gen6_reset_rps_interrupts(dev_priv); | |
156c7ca0 JB |
7069 | } |
7070 | ||
dc97997a | 7071 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) |
8090c6b9 | 7072 | { |
b7137e0c CW |
7073 | if (!READ_ONCE(dev_priv->rps.enabled)) |
7074 | return; | |
e494837a | 7075 | |
b7137e0c | 7076 | mutex_lock(&dev_priv->rps.hw_lock); |
e534770a | 7077 | |
b7137e0c CW |
7078 | if (INTEL_GEN(dev_priv) >= 9) { |
7079 | gen9_disable_rc6(dev_priv); | |
7080 | gen9_disable_rps(dev_priv); | |
7081 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
7082 | cherryview_disable_rps(dev_priv); | |
7083 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7084 | valleyview_disable_rps(dev_priv); | |
7085 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
7086 | gen6_disable_rps(dev_priv); | |
7087 | } else if (IS_IRONLAKE_M(dev_priv)) { | |
7088 | ironlake_disable_drps(dev_priv); | |
930ebb46 | 7089 | } |
b7137e0c CW |
7090 | |
7091 | dev_priv->rps.enabled = false; | |
7092 | mutex_unlock(&dev_priv->rps.hw_lock); | |
8090c6b9 DV |
7093 | } |
7094 | ||
b7137e0c | 7095 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) |
1a01ab3b | 7096 | { |
54b4f68f CW |
7097 | /* We shouldn't be disabling as we submit, so this should be less |
7098 | * racy than it appears! | |
7099 | */ | |
b7137e0c CW |
7100 | if (READ_ONCE(dev_priv->rps.enabled)) |
7101 | return; | |
1a01ab3b | 7102 | |
b7137e0c CW |
7103 | /* Powersaving is controlled by the host when inside a VM */ |
7104 | if (intel_vgpu_active(dev_priv)) | |
7105 | return; | |
0a073b84 | 7106 | |
b7137e0c | 7107 | mutex_lock(&dev_priv->rps.hw_lock); |
dc97997a CW |
7108 | |
7109 | if (IS_CHERRYVIEW(dev_priv)) { | |
7110 | cherryview_enable_rps(dev_priv); | |
7111 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7112 | valleyview_enable_rps(dev_priv); | |
b7137e0c | 7113 | } else if (INTEL_GEN(dev_priv) >= 9) { |
dc97997a CW |
7114 | gen9_enable_rc6(dev_priv); |
7115 | gen9_enable_rps(dev_priv); | |
b976dc53 | 7116 | if (IS_GEN9_BC(dev_priv)) |
fb7404e8 | 7117 | gen6_update_ring_freq(dev_priv); |
dc97997a CW |
7118 | } else if (IS_BROADWELL(dev_priv)) { |
7119 | gen8_enable_rps(dev_priv); | |
fb7404e8 | 7120 | gen6_update_ring_freq(dev_priv); |
b7137e0c | 7121 | } else if (INTEL_GEN(dev_priv) >= 6) { |
dc97997a | 7122 | gen6_enable_rps(dev_priv); |
fb7404e8 | 7123 | gen6_update_ring_freq(dev_priv); |
b7137e0c CW |
7124 | } else if (IS_IRONLAKE_M(dev_priv)) { |
7125 | ironlake_enable_drps(dev_priv); | |
7126 | intel_init_emon(dev_priv); | |
0a073b84 | 7127 | } |
aed242ff CW |
7128 | |
7129 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); | |
7130 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); | |
7131 | ||
7132 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); | |
7133 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); | |
7134 | ||
54b4f68f | 7135 | dev_priv->rps.enabled = true; |
b7137e0c CW |
7136 | mutex_unlock(&dev_priv->rps.hw_lock); |
7137 | } | |
3cc134e3 | 7138 | |
54b4f68f CW |
7139 | static void __intel_autoenable_gt_powersave(struct work_struct *work) |
7140 | { | |
7141 | struct drm_i915_private *dev_priv = | |
7142 | container_of(work, typeof(*dev_priv), rps.autoenable_work.work); | |
7143 | struct intel_engine_cs *rcs; | |
7144 | struct drm_i915_gem_request *req; | |
7145 | ||
7146 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7147 | goto out; | |
7148 | ||
3b3f1650 | 7149 | rcs = dev_priv->engine[RCS]; |
e8a9c58f | 7150 | if (rcs->last_retired_context) |
54b4f68f CW |
7151 | goto out; |
7152 | ||
7153 | if (!rcs->init_context) | |
7154 | goto out; | |
7155 | ||
7156 | mutex_lock(&dev_priv->drm.struct_mutex); | |
7157 | ||
7158 | req = i915_gem_request_alloc(rcs, dev_priv->kernel_context); | |
7159 | if (IS_ERR(req)) | |
7160 | goto unlock; | |
7161 | ||
7162 | if (!i915.enable_execlists && i915_switch_context(req) == 0) | |
7163 | rcs->init_context(req); | |
7164 | ||
7165 | /* Mark the device busy, calling intel_enable_gt_powersave() */ | |
e642c85b | 7166 | i915_add_request(req); |
54b4f68f CW |
7167 | |
7168 | unlock: | |
7169 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
7170 | out: | |
7171 | intel_runtime_pm_put(dev_priv); | |
7172 | } | |
7173 | ||
7174 | void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv) | |
7175 | { | |
7176 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7177 | return; | |
7178 | ||
7179 | if (IS_IRONLAKE_M(dev_priv)) { | |
7180 | ironlake_enable_drps(dev_priv); | |
54b4f68f | 7181 | intel_init_emon(dev_priv); |
54b4f68f CW |
7182 | } else if (INTEL_INFO(dev_priv)->gen >= 6) { |
7183 | /* | |
7184 | * PCU communication is slow and this doesn't need to be | |
7185 | * done at any specific time, so do this out of our fast path | |
7186 | * to make resume and init faster. | |
7187 | * | |
7188 | * We depend on the HW RC6 power context save/restore | |
7189 | * mechanism when entering D3 through runtime PM suspend. So | |
7190 | * disable RPM until RPS/RC6 is properly setup. We can only | |
7191 | * get here via the driver load/system resume/runtime resume | |
7192 | * paths, so the _noresume version is enough (and in case of | |
7193 | * runtime resume it's necessary). | |
7194 | */ | |
7195 | if (queue_delayed_work(dev_priv->wq, | |
7196 | &dev_priv->rps.autoenable_work, | |
7197 | round_jiffies_up_relative(HZ))) | |
7198 | intel_runtime_pm_get_noresume(dev_priv); | |
7199 | } | |
7200 | } | |
7201 | ||
46f16e63 | 7202 | static void ibx_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 7203 | { |
3107bd48 DV |
7204 | /* |
7205 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7206 | * gating for the panel power sequencer or it will fail to | |
7207 | * start up when no ports are active. | |
7208 | */ | |
7209 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
7210 | } | |
7211 | ||
46f16e63 | 7212 | static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) |
0e088b8f | 7213 | { |
b12ce1d8 | 7214 | enum pipe pipe; |
0e088b8f | 7215 | |
055e393f | 7216 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
7217 | I915_WRITE(DSPCNTR(pipe), |
7218 | I915_READ(DSPCNTR(pipe)) | | |
7219 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
b12ce1d8 VS |
7220 | |
7221 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); | |
7222 | POSTING_READ(DSPSURF(pipe)); | |
0e088b8f VS |
7223 | } |
7224 | } | |
7225 | ||
46f16e63 | 7226 | static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) |
017636cc | 7227 | { |
017636cc VS |
7228 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
7229 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
7230 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
7231 | ||
7232 | /* | |
7233 | * Don't touch WM1S_LP_EN here. | |
7234 | * Doing so could cause underruns. | |
7235 | */ | |
7236 | } | |
7237 | ||
46f16e63 | 7238 | static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7239 | { |
231e54f6 | 7240 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 7241 | |
f1e8fa56 DL |
7242 | /* |
7243 | * Required for FBC | |
7244 | * WaFbcDisableDpfcClockGating:ilk | |
7245 | */ | |
4d47e4f5 DL |
7246 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
7247 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
7248 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
7249 | |
7250 | I915_WRITE(PCH_3DCGDIS0, | |
7251 | MARIUNIT_CLOCK_GATE_DISABLE | | |
7252 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
7253 | I915_WRITE(PCH_3DCGDIS1, | |
7254 | VFMUNIT_CLOCK_GATE_DISABLE); | |
7255 | ||
6f1d69b0 ED |
7256 | /* |
7257 | * According to the spec the following bits should be set in | |
7258 | * order to enable memory self-refresh | |
7259 | * The bit 22/21 of 0x42004 | |
7260 | * The bit 5 of 0x42020 | |
7261 | * The bit 15 of 0x45000 | |
7262 | */ | |
7263 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7264 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7265 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 7266 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
7267 | I915_WRITE(DISP_ARB_CTL, |
7268 | (I915_READ(DISP_ARB_CTL) | | |
7269 | DISP_FBC_WM_DIS)); | |
017636cc | 7270 | |
46f16e63 | 7271 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 ED |
7272 | |
7273 | /* | |
7274 | * Based on the document from hardware guys the following bits | |
7275 | * should be set unconditionally in order to enable FBC. | |
7276 | * The bit 22 of 0x42000 | |
7277 | * The bit 22 of 0x42004 | |
7278 | * The bit 7,8,9 of 0x42020. | |
7279 | */ | |
50a0bc90 | 7280 | if (IS_IRONLAKE_M(dev_priv)) { |
4bb35334 | 7281 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
7282 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
7283 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7284 | ILK_FBCQ_DIS); | |
7285 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7286 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7287 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
7288 | } |
7289 | ||
4d47e4f5 DL |
7290 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
7291 | ||
6f1d69b0 ED |
7292 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
7293 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7294 | ILK_ELPIN_409_SELECT); | |
7295 | I915_WRITE(_3D_CHICKEN2, | |
7296 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
7297 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 7298 | |
ecdb4eb7 | 7299 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
7300 | I915_WRITE(CACHE_MODE_0, |
7301 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 7302 | |
4e04632e AG |
7303 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
7304 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7305 | ||
46f16e63 | 7306 | g4x_disable_trickle_feed(dev_priv); |
bdad2b2f | 7307 | |
46f16e63 | 7308 | ibx_init_clock_gating(dev_priv); |
3107bd48 DV |
7309 | } |
7310 | ||
46f16e63 | 7311 | static void cpt_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 7312 | { |
3107bd48 | 7313 | int pipe; |
3f704fa2 | 7314 | uint32_t val; |
3107bd48 DV |
7315 | |
7316 | /* | |
7317 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7318 | * gating for the panel power sequencer or it will fail to | |
7319 | * start up when no ports are active. | |
7320 | */ | |
cd664078 JB |
7321 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
7322 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
7323 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
7324 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
7325 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
7326 | /* The below fixes the weird display corruption, a few pixels shifted |
7327 | * downward, on (only) LVDS of some HP laptops with IVY. | |
7328 | */ | |
055e393f | 7329 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
7330 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
7331 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
7332 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 7333 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 7334 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
7335 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
7336 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
7337 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
7338 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
7339 | } | |
3107bd48 | 7340 | /* WADP0ClockGatingDisable */ |
055e393f | 7341 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
7342 | I915_WRITE(TRANS_CHICKEN1(pipe), |
7343 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
7344 | } | |
6f1d69b0 ED |
7345 | } |
7346 | ||
46f16e63 | 7347 | static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) |
1d7aaa0c | 7348 | { |
1d7aaa0c DV |
7349 | uint32_t tmp; |
7350 | ||
7351 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
7352 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
7353 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
7354 | tmp); | |
1d7aaa0c DV |
7355 | } |
7356 | ||
46f16e63 | 7357 | static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7358 | { |
231e54f6 | 7359 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 7360 | |
231e54f6 | 7361 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
7362 | |
7363 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7364 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7365 | ILK_ELPIN_409_SELECT); | |
7366 | ||
ecdb4eb7 | 7367 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
7368 | I915_WRITE(_3D_CHICKEN, |
7369 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
7370 | ||
4e04632e AG |
7371 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
7372 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7373 | ||
8d85d272 VS |
7374 | /* |
7375 | * BSpec recoomends 8x4 when MSAA is used, | |
7376 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
7377 | * |
7378 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7379 | * disable bit, which we don't touch here, but it's good | |
7380 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
7381 | */ |
7382 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 7383 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 7384 | |
46f16e63 | 7385 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 7386 | |
6f1d69b0 | 7387 | I915_WRITE(CACHE_MODE_0, |
50743298 | 7388 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
7389 | |
7390 | I915_WRITE(GEN6_UCGCTL1, | |
7391 | I915_READ(GEN6_UCGCTL1) | | |
7392 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
7393 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
7394 | ||
7395 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
7396 | * gating disable must be set. Failure to set it results in | |
7397 | * flickering pixels due to Z write ordering failures after | |
7398 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
7399 | * Sanctuary and Tropics, and apparently anything else with | |
7400 | * alpha test or pixel discard. | |
7401 | * | |
7402 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
7403 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 7404 | * |
ef59318c VS |
7405 | * WaDisableRCCUnitClockGating:snb |
7406 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
7407 | */ |
7408 | I915_WRITE(GEN6_UCGCTL2, | |
7409 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
7410 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
7411 | ||
5eb146dd | 7412 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
7413 | I915_WRITE(_3D_CHICKEN3, |
7414 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 7415 | |
e927ecde VS |
7416 | /* |
7417 | * Bspec says: | |
7418 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
7419 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
7420 | */ | |
7421 | I915_WRITE(_3D_CHICKEN3, | |
7422 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
7423 | ||
6f1d69b0 ED |
7424 | /* |
7425 | * According to the spec the following bits should be | |
7426 | * set in order to enable memory self-refresh and fbc: | |
7427 | * The bit21 and bit22 of 0x42000 | |
7428 | * The bit21 and bit22 of 0x42004 | |
7429 | * The bit5 and bit7 of 0x42020 | |
7430 | * The bit14 of 0x70180 | |
7431 | * The bit14 of 0x71180 | |
4bb35334 DL |
7432 | * |
7433 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
7434 | */ |
7435 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
7436 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7437 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
7438 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7439 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7440 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
7441 | I915_WRITE(ILK_DSPCLK_GATE_D, |
7442 | I915_READ(ILK_DSPCLK_GATE_D) | | |
7443 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
7444 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 7445 | |
46f16e63 | 7446 | g4x_disable_trickle_feed(dev_priv); |
f8f2ac9a | 7447 | |
46f16e63 | 7448 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 7449 | |
46f16e63 | 7450 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
7451 | } |
7452 | ||
7453 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
7454 | { | |
7455 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
7456 | ||
3aad9059 | 7457 | /* |
46680e0a | 7458 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
7459 | * |
7460 | * This actually overrides the dispatch | |
7461 | * mode for all thread types. | |
7462 | */ | |
6f1d69b0 ED |
7463 | reg &= ~GEN7_FF_SCHED_MASK; |
7464 | reg |= GEN7_FF_TS_SCHED_HW; | |
7465 | reg |= GEN7_FF_VS_SCHED_HW; | |
7466 | reg |= GEN7_FF_DS_SCHED_HW; | |
7467 | ||
7468 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
7469 | } | |
7470 | ||
46f16e63 | 7471 | static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) |
17a303ec | 7472 | { |
17a303ec PZ |
7473 | /* |
7474 | * TODO: this bit should only be enabled when really needed, then | |
7475 | * disabled when not needed anymore in order to save power. | |
7476 | */ | |
4f8036a2 | 7477 | if (HAS_PCH_LPT_LP(dev_priv)) |
17a303ec PZ |
7478 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
7479 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
7480 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
7481 | |
7482 | /* WADPOClockGatingDisable:hsw */ | |
36c0d0cf VS |
7483 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
7484 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | | |
0a790cdb | 7485 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
17a303ec PZ |
7486 | } |
7487 | ||
712bf364 | 7488 | static void lpt_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 7489 | { |
4f8036a2 | 7490 | if (HAS_PCH_LPT_LP(dev_priv)) { |
7d708ee4 ID |
7491 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
7492 | ||
7493 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7494 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7495 | } | |
7496 | } | |
7497 | ||
450174fe ID |
7498 | static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, |
7499 | int general_prio_credits, | |
7500 | int high_prio_credits) | |
7501 | { | |
7502 | u32 misccpctl; | |
7503 | ||
7504 | /* WaTempDisableDOPClkGating:bdw */ | |
7505 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
7506 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
7507 | ||
7508 | I915_WRITE(GEN8_L3SQCREG1, | |
7509 | L3_GENERAL_PRIO_CREDITS(general_prio_credits) | | |
7510 | L3_HIGH_PRIO_CREDITS(high_prio_credits)); | |
7511 | ||
7512 | /* | |
7513 | * Wait at least 100 clocks before re-enabling clock gating. | |
7514 | * See the definition of L3SQCREG1 in BSpec. | |
7515 | */ | |
7516 | POSTING_READ(GEN8_L3SQCREG1); | |
7517 | udelay(1); | |
7518 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
7519 | } | |
7520 | ||
46f16e63 | 7521 | static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) |
9498dba7 | 7522 | { |
46f16e63 | 7523 | gen9_init_clock_gating(dev_priv); |
9498dba7 MK |
7524 | |
7525 | /* WaDisableSDEUnitClockGating:kbl */ | |
7526 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
7527 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
7528 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
8aeb7f62 MK |
7529 | |
7530 | /* WaDisableGamClockGating:kbl */ | |
7531 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
7532 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
7533 | GEN6_GAMUNIT_CLOCK_GATE_DISABLE); | |
031cd8c8 MK |
7534 | |
7535 | /* WaFbcNukeOnHostModify:kbl */ | |
7536 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
7537 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
9498dba7 MK |
7538 | } |
7539 | ||
46f16e63 | 7540 | static void skylake_init_clock_gating(struct drm_i915_private *dev_priv) |
dc00b6a0 | 7541 | { |
46f16e63 | 7542 | gen9_init_clock_gating(dev_priv); |
44fff99f MK |
7543 | |
7544 | /* WAC6entrylatency:skl */ | |
7545 | I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | | |
7546 | FBC_LLC_FULLY_OPEN); | |
031cd8c8 MK |
7547 | |
7548 | /* WaFbcNukeOnHostModify:skl */ | |
7549 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
7550 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
dc00b6a0 DV |
7551 | } |
7552 | ||
46f16e63 | 7553 | static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) |
1020a5c2 | 7554 | { |
07d27e20 | 7555 | enum pipe pipe; |
1020a5c2 | 7556 | |
46f16e63 | 7557 | ilk_init_lp_watermarks(dev_priv); |
50ed5fbd | 7558 | |
ab57fff1 | 7559 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 7560 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 7561 | |
ab57fff1 | 7562 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
7563 | I915_WRITE(CHICKEN_PAR1_1, |
7564 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
7565 | ||
ab57fff1 | 7566 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 7567 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 7568 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 7569 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 7570 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 7571 | } |
63801f21 | 7572 | |
ab57fff1 BW |
7573 | /* WaVSRefCountFullforceMissDisable:bdw */ |
7574 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
7575 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
7576 | I915_READ(GEN7_FF_THREAD_MODE) & | |
7577 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 7578 | |
295e8bb7 VS |
7579 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
7580 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
7581 | |
7582 | /* WaDisableSDEUnitClockGating:bdw */ | |
7583 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
7584 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 7585 | |
450174fe ID |
7586 | /* WaProgramL3SqcReg1Default:bdw */ |
7587 | gen8_set_l3sqc_credits(dev_priv, 30, 2); | |
4d487cff | 7588 | |
6d50b065 VS |
7589 | /* |
7590 | * WaGttCachingOffByDefault:bdw | |
7591 | * GTT cache may not work with big pages, so if those | |
7592 | * are ever enabled GTT cache may need to be disabled. | |
7593 | */ | |
7594 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
7595 | ||
17e0adf0 MK |
7596 | /* WaKVMNotificationOnConfigChange:bdw */ |
7597 | I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) | |
7598 | | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); | |
7599 | ||
46f16e63 | 7600 | lpt_init_clock_gating(dev_priv); |
9cc19733 RB |
7601 | |
7602 | /* WaDisableDopClockGating:bdw | |
7603 | * | |
7604 | * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP | |
7605 | * clock gating. | |
7606 | */ | |
7607 | I915_WRITE(GEN6_UCGCTL1, | |
7608 | I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); | |
1020a5c2 BW |
7609 | } |
7610 | ||
46f16e63 | 7611 | static void haswell_init_clock_gating(struct drm_i915_private *dev_priv) |
cad2a2d7 | 7612 | { |
46f16e63 | 7613 | ilk_init_lp_watermarks(dev_priv); |
cad2a2d7 | 7614 | |
f3fc4884 FJ |
7615 | /* L3 caching of data atomics doesn't work -- disable it. */ |
7616 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
7617 | I915_WRITE(HSW_ROW_CHICKEN3, | |
7618 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
7619 | ||
ecdb4eb7 | 7620 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
7621 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
7622 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
7623 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
7624 | ||
e36ea7ff VS |
7625 | /* WaVSRefCountFullforceMissDisable:hsw */ |
7626 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
7627 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 7628 | |
4e04632e AG |
7629 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
7630 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7631 | ||
fe27c606 CW |
7632 | /* enable HiZ Raw Stall Optimization */ |
7633 | I915_WRITE(CACHE_MODE_0_GEN7, | |
7634 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
7635 | ||
ecdb4eb7 | 7636 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
7637 | I915_WRITE(CACHE_MODE_1, |
7638 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 7639 | |
a12c4967 VS |
7640 | /* |
7641 | * BSpec recommends 8x4 when MSAA is used, | |
7642 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
7643 | * |
7644 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7645 | * disable bit, which we don't touch here, but it's good | |
7646 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
7647 | */ |
7648 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 7649 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 7650 | |
94411593 KG |
7651 | /* WaSampleCChickenBitEnable:hsw */ |
7652 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
7653 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
7654 | ||
ecdb4eb7 | 7655 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
7656 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
7657 | ||
90a88643 PZ |
7658 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
7659 | I915_WRITE(CHICKEN_PAR1_1, | |
7660 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 7661 | |
46f16e63 | 7662 | lpt_init_clock_gating(dev_priv); |
cad2a2d7 ED |
7663 | } |
7664 | ||
46f16e63 | 7665 | static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7666 | { |
20848223 | 7667 | uint32_t snpcr; |
6f1d69b0 | 7668 | |
46f16e63 | 7669 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 7670 | |
231e54f6 | 7671 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 7672 | |
ecdb4eb7 | 7673 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
7674 | I915_WRITE(_3D_CHICKEN3, |
7675 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
7676 | ||
ecdb4eb7 | 7677 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
7678 | I915_WRITE(IVB_CHICKEN3, |
7679 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
7680 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
7681 | ||
ecdb4eb7 | 7682 | /* WaDisablePSDDualDispatchEnable:ivb */ |
50a0bc90 | 7683 | if (IS_IVB_GT1(dev_priv)) |
12f3382b JB |
7684 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
7685 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 7686 | |
4e04632e AG |
7687 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
7688 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7689 | ||
ecdb4eb7 | 7690 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
7691 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
7692 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
7693 | ||
ecdb4eb7 | 7694 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
7695 | I915_WRITE(GEN7_L3CNTLREG1, |
7696 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
7697 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 | 7698 | GEN7_WA_L3_CHICKEN_MODE); |
50a0bc90 | 7699 | if (IS_IVB_GT1(dev_priv)) |
8ab43976 JB |
7700 | I915_WRITE(GEN7_ROW_CHICKEN2, |
7701 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
7702 | else { |
7703 | /* must write both registers */ | |
7704 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
7705 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
7706 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
7707 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 7708 | } |
6f1d69b0 | 7709 | |
ecdb4eb7 | 7710 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
7711 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
7712 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
7713 | ||
1b80a19a | 7714 | /* |
0f846f81 | 7715 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 7716 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
7717 | */ |
7718 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 7719 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 7720 | |
ecdb4eb7 | 7721 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
7722 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
7723 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
7724 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
7725 | ||
46f16e63 | 7726 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
7727 | |
7728 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 7729 | |
22721343 CW |
7730 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
7731 | /* enable HiZ Raw Stall Optimization */ | |
7732 | I915_WRITE(CACHE_MODE_0_GEN7, | |
7733 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
7734 | } | |
116f2b6d | 7735 | |
ecdb4eb7 | 7736 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
7737 | I915_WRITE(CACHE_MODE_1, |
7738 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 7739 | |
a607c1a4 VS |
7740 | /* |
7741 | * BSpec recommends 8x4 when MSAA is used, | |
7742 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
7743 | * |
7744 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7745 | * disable bit, which we don't touch here, but it's good | |
7746 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
7747 | */ |
7748 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 7749 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 7750 | |
20848223 BW |
7751 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
7752 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
7753 | snpcr |= GEN6_MBC_SNPCR_MED; | |
7754 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 7755 | |
6e266956 | 7756 | if (!HAS_PCH_NOP(dev_priv)) |
46f16e63 | 7757 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 7758 | |
46f16e63 | 7759 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
7760 | } |
7761 | ||
46f16e63 | 7762 | static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7763 | { |
ecdb4eb7 | 7764 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
7765 | I915_WRITE(_3D_CHICKEN3, |
7766 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
7767 | ||
ecdb4eb7 | 7768 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
7769 | I915_WRITE(IVB_CHICKEN3, |
7770 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
7771 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
7772 | ||
fad7d36e | 7773 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 7774 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 7775 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
7776 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
7777 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 7778 | |
4e04632e AG |
7779 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
7780 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7781 | ||
ecdb4eb7 | 7782 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
7783 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
7784 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
7785 | ||
ecdb4eb7 | 7786 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
7787 | I915_WRITE(GEN7_ROW_CHICKEN2, |
7788 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
7789 | ||
ecdb4eb7 | 7790 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
7791 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
7792 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
7793 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
7794 | ||
46680e0a VS |
7795 | gen7_setup_fixed_func_scheduler(dev_priv); |
7796 | ||
3c0edaeb | 7797 | /* |
0f846f81 | 7798 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 7799 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
7800 | */ |
7801 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 7802 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 7803 | |
c98f5062 AG |
7804 | /* WaDisableL3Bank2xClockGate:vlv |
7805 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
7806 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
7807 | I915_WRITE(GEN7_UCGCTL4, | |
7808 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 7809 | |
afd58e79 VS |
7810 | /* |
7811 | * BSpec says this must be set, even though | |
7812 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
7813 | */ | |
6b26c86d DV |
7814 | I915_WRITE(CACHE_MODE_1, |
7815 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 7816 | |
da2518f9 VS |
7817 | /* |
7818 | * BSpec recommends 8x4 when MSAA is used, | |
7819 | * however in practice 16x4 seems fastest. | |
7820 | * | |
7821 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7822 | * disable bit, which we don't touch here, but it's good | |
7823 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
7824 | */ | |
7825 | I915_WRITE(GEN7_GT_MODE, | |
7826 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
7827 | ||
031994ee VS |
7828 | /* |
7829 | * WaIncreaseL3CreditsForVLVB0:vlv | |
7830 | * This is the hardware default actually. | |
7831 | */ | |
7832 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
7833 | ||
2d809570 | 7834 | /* |
ecdb4eb7 | 7835 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
7836 | * Disable clock gating on th GCFG unit to prevent a delay |
7837 | * in the reporting of vblank events. | |
7838 | */ | |
7a0d1eed | 7839 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
7840 | } |
7841 | ||
46f16e63 | 7842 | static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) |
a4565da8 | 7843 | { |
232ce337 VS |
7844 | /* WaVSRefCountFullforceMissDisable:chv */ |
7845 | /* WaDSRefCountFullforceMissDisable:chv */ | |
7846 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
7847 | I915_READ(GEN7_FF_THREAD_MODE) & | |
7848 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
7849 | |
7850 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
7851 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
7852 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
7853 | |
7854 | /* WaDisableCSUnitClockGating:chv */ | |
7855 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
7856 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
7857 | |
7858 | /* WaDisableSDEUnitClockGating:chv */ | |
7859 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
7860 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6d50b065 | 7861 | |
450174fe ID |
7862 | /* |
7863 | * WaProgramL3SqcReg1Default:chv | |
7864 | * See gfxspecs/Related Documents/Performance Guide/ | |
7865 | * LSQC Setting Recommendations. | |
7866 | */ | |
7867 | gen8_set_l3sqc_credits(dev_priv, 38, 2); | |
7868 | ||
6d50b065 VS |
7869 | /* |
7870 | * GTT cache may not work with big pages, so if those | |
7871 | * are ever enabled GTT cache may need to be disabled. | |
7872 | */ | |
7873 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
a4565da8 VS |
7874 | } |
7875 | ||
46f16e63 | 7876 | static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7877 | { |
6f1d69b0 ED |
7878 | uint32_t dspclk_gate; |
7879 | ||
7880 | I915_WRITE(RENCLK_GATE_D1, 0); | |
7881 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
7882 | GS_UNIT_CLOCK_GATE_DISABLE | | |
7883 | CL_UNIT_CLOCK_GATE_DISABLE); | |
7884 | I915_WRITE(RAMCLK_GATE_D, 0); | |
7885 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
7886 | OVRUNIT_CLOCK_GATE_DISABLE | | |
7887 | OVCUNIT_CLOCK_GATE_DISABLE; | |
50a0bc90 | 7888 | if (IS_GM45(dev_priv)) |
6f1d69b0 ED |
7889 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
7890 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
7891 | |
7892 | /* WaDisableRenderCachePipelinedFlush */ | |
7893 | I915_WRITE(CACHE_MODE_0, | |
7894 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 7895 | |
4e04632e AG |
7896 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
7897 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7898 | ||
46f16e63 | 7899 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
7900 | } |
7901 | ||
46f16e63 | 7902 | static void crestline_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7903 | { |
6f1d69b0 ED |
7904 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
7905 | I915_WRITE(RENCLK_GATE_D2, 0); | |
7906 | I915_WRITE(DSPCLK_GATE_D, 0); | |
7907 | I915_WRITE(RAMCLK_GATE_D, 0); | |
7908 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
7909 | I915_WRITE(MI_ARB_STATE, |
7910 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
7911 | |
7912 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
7913 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
7914 | } |
7915 | ||
46f16e63 | 7916 | static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7917 | { |
6f1d69b0 ED |
7918 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
7919 | I965_RCC_CLOCK_GATE_DISABLE | | |
7920 | I965_RCPB_CLOCK_GATE_DISABLE | | |
7921 | I965_ISC_CLOCK_GATE_DISABLE | | |
7922 | I965_FBC_CLOCK_GATE_DISABLE); | |
7923 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
7924 | I915_WRITE(MI_ARB_STATE, |
7925 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
7926 | |
7927 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
7928 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
7929 | } |
7930 | ||
46f16e63 | 7931 | static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7932 | { |
6f1d69b0 ED |
7933 | u32 dstate = I915_READ(D_STATE); |
7934 | ||
7935 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
7936 | DSTATE_DOT_CLOCK_GATING; | |
7937 | I915_WRITE(D_STATE, dstate); | |
13a86b85 | 7938 | |
9b1e14f4 | 7939 | if (IS_PINEVIEW(dev_priv)) |
13a86b85 | 7940 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
974a3b0f DV |
7941 | |
7942 | /* IIR "flip pending" means done if this bit is set */ | |
7943 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
7944 | |
7945 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 7946 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
7947 | |
7948 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
7949 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
7950 | |
7951 | I915_WRITE(MI_ARB_STATE, | |
7952 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7953 | } |
7954 | ||
46f16e63 | 7955 | static void i85x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7956 | { |
6f1d69b0 | 7957 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
54e472ae VS |
7958 | |
7959 | /* interrupts should cause a wake up from C3 */ | |
7960 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
7961 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
7962 | |
7963 | I915_WRITE(MEM_MODE, | |
7964 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7965 | } |
7966 | ||
46f16e63 | 7967 | static void i830_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7968 | { |
1038392b VS |
7969 | I915_WRITE(MEM_MODE, |
7970 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
7971 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7972 | } |
7973 | ||
46f16e63 | 7974 | void intel_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7975 | { |
46f16e63 | 7976 | dev_priv->display.init_clock_gating(dev_priv); |
6f1d69b0 ED |
7977 | } |
7978 | ||
712bf364 | 7979 | void intel_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 7980 | { |
712bf364 VS |
7981 | if (HAS_PCH_LPT(dev_priv)) |
7982 | lpt_suspend_hw(dev_priv); | |
7d708ee4 ID |
7983 | } |
7984 | ||
46f16e63 | 7985 | static void nop_init_clock_gating(struct drm_i915_private *dev_priv) |
bb400da9 ID |
7986 | { |
7987 | DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n"); | |
7988 | } | |
7989 | ||
7990 | /** | |
7991 | * intel_init_clock_gating_hooks - setup the clock gating hooks | |
7992 | * @dev_priv: device private | |
7993 | * | |
7994 | * Setup the hooks that configure which clocks of a given platform can be | |
7995 | * gated and also apply various GT and display specific workarounds for these | |
7996 | * platforms. Note that some GT specific workarounds are applied separately | |
7997 | * when GPU contexts or batchbuffers start their execution. | |
7998 | */ | |
7999 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) | |
8000 | { | |
8001 | if (IS_SKYLAKE(dev_priv)) | |
dc00b6a0 | 8002 | dev_priv->display.init_clock_gating = skylake_init_clock_gating; |
bb400da9 | 8003 | else if (IS_KABYLAKE(dev_priv)) |
9498dba7 | 8004 | dev_priv->display.init_clock_gating = kabylake_init_clock_gating; |
9fb5026f | 8005 | else if (IS_BROXTON(dev_priv)) |
bb400da9 | 8006 | dev_priv->display.init_clock_gating = bxt_init_clock_gating; |
9fb5026f ACO |
8007 | else if (IS_GEMINILAKE(dev_priv)) |
8008 | dev_priv->display.init_clock_gating = glk_init_clock_gating; | |
bb400da9 ID |
8009 | else if (IS_BROADWELL(dev_priv)) |
8010 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; | |
8011 | else if (IS_CHERRYVIEW(dev_priv)) | |
8012 | dev_priv->display.init_clock_gating = cherryview_init_clock_gating; | |
8013 | else if (IS_HASWELL(dev_priv)) | |
8014 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; | |
8015 | else if (IS_IVYBRIDGE(dev_priv)) | |
8016 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; | |
8017 | else if (IS_VALLEYVIEW(dev_priv)) | |
8018 | dev_priv->display.init_clock_gating = valleyview_init_clock_gating; | |
8019 | else if (IS_GEN6(dev_priv)) | |
8020 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; | |
8021 | else if (IS_GEN5(dev_priv)) | |
8022 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; | |
8023 | else if (IS_G4X(dev_priv)) | |
8024 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
c0f86832 | 8025 | else if (IS_I965GM(dev_priv)) |
bb400da9 | 8026 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
c0f86832 | 8027 | else if (IS_I965G(dev_priv)) |
bb400da9 ID |
8028 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
8029 | else if (IS_GEN3(dev_priv)) | |
8030 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
8031 | else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) | |
8032 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8033 | else if (IS_GEN2(dev_priv)) | |
8034 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
8035 | else { | |
8036 | MISSING_CASE(INTEL_DEVID(dev_priv)); | |
8037 | dev_priv->display.init_clock_gating = nop_init_clock_gating; | |
8038 | } | |
8039 | } | |
8040 | ||
1fa61106 | 8041 | /* Set up chip specific power management-related functions */ |
62d75df7 | 8042 | void intel_init_pm(struct drm_i915_private *dev_priv) |
1fa61106 | 8043 | { |
7ff0ebcc | 8044 | intel_fbc_init(dev_priv); |
1fa61106 | 8045 | |
c921aba8 | 8046 | /* For cxsr */ |
9b1e14f4 | 8047 | if (IS_PINEVIEW(dev_priv)) |
148ac1f3 | 8048 | i915_pineview_get_mem_freq(dev_priv); |
5db94019 | 8049 | else if (IS_GEN5(dev_priv)) |
148ac1f3 | 8050 | i915_ironlake_get_mem_freq(dev_priv); |
c921aba8 | 8051 | |
1fa61106 | 8052 | /* For FIFO watermark updates */ |
62d75df7 | 8053 | if (INTEL_GEN(dev_priv) >= 9) { |
bb726519 | 8054 | skl_setup_wm_latency(dev_priv); |
e62929b3 | 8055 | dev_priv->display.initial_watermarks = skl_initial_wm; |
ccf010fb | 8056 | dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; |
98d39494 | 8057 | dev_priv->display.compute_global_watermarks = skl_compute_wm; |
6e266956 | 8058 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bb726519 | 8059 | ilk_setup_wm_latency(dev_priv); |
53615a5e | 8060 | |
5db94019 | 8061 | if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && |
bd602544 | 8062 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
5db94019 | 8063 | (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && |
bd602544 | 8064 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
86c8bbbe | 8065 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
ed4a6a7c MR |
8066 | dev_priv->display.compute_intermediate_wm = |
8067 | ilk_compute_intermediate_wm; | |
8068 | dev_priv->display.initial_watermarks = | |
8069 | ilk_initial_watermarks; | |
8070 | dev_priv->display.optimize_watermarks = | |
8071 | ilk_optimize_watermarks; | |
bd602544 VS |
8072 | } else { |
8073 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8074 | "Disable CxSR\n"); | |
8075 | } | |
6b6b3eef | 8076 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bb726519 | 8077 | vlv_setup_wm_latency(dev_priv); |
ff32c54e | 8078 | dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm; |
4841da51 | 8079 | dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm; |
ff32c54e | 8080 | dev_priv->display.initial_watermarks = vlv_initial_watermarks; |
4841da51 | 8081 | dev_priv->display.optimize_watermarks = vlv_optimize_watermarks; |
ff32c54e | 8082 | dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo; |
9b1e14f4 | 8083 | } else if (IS_PINEVIEW(dev_priv)) { |
50a0bc90 | 8084 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
1fa61106 ED |
8085 | dev_priv->is_ddr3, |
8086 | dev_priv->fsb_freq, | |
8087 | dev_priv->mem_freq)) { | |
8088 | DRM_INFO("failed to find known CxSR latency " | |
8089 | "(found ddr%s fsb freq %d, mem freq %d), " | |
8090 | "disabling CxSR\n", | |
8091 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
8092 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
8093 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 8094 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
8095 | dev_priv->display.update_wm = NULL; |
8096 | } else | |
8097 | dev_priv->display.update_wm = pineview_update_wm; | |
9beb5fea | 8098 | } else if (IS_G4X(dev_priv)) { |
1fa61106 | 8099 | dev_priv->display.update_wm = g4x_update_wm; |
5db94019 | 8100 | } else if (IS_GEN4(dev_priv)) { |
1fa61106 | 8101 | dev_priv->display.update_wm = i965_update_wm; |
5db94019 | 8102 | } else if (IS_GEN3(dev_priv)) { |
1fa61106 ED |
8103 | dev_priv->display.update_wm = i9xx_update_wm; |
8104 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
5db94019 | 8105 | } else if (IS_GEN2(dev_priv)) { |
62d75df7 | 8106 | if (INTEL_INFO(dev_priv)->num_pipes == 1) { |
feb56b93 | 8107 | dev_priv->display.update_wm = i845_update_wm; |
1fa61106 | 8108 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
8109 | } else { |
8110 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 8111 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 | 8112 | } |
feb56b93 DV |
8113 | } else { |
8114 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
8115 | } |
8116 | } | |
8117 | ||
87660502 L |
8118 | static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv) |
8119 | { | |
8120 | uint32_t flags = | |
8121 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8122 | ||
8123 | switch (flags) { | |
8124 | case GEN6_PCODE_SUCCESS: | |
8125 | return 0; | |
8126 | case GEN6_PCODE_UNIMPLEMENTED_CMD: | |
8127 | case GEN6_PCODE_ILLEGAL_CMD: | |
8128 | return -ENXIO; | |
8129 | case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
7850d1c3 | 8130 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: |
87660502 L |
8131 | return -EOVERFLOW; |
8132 | case GEN6_PCODE_TIMEOUT: | |
8133 | return -ETIMEDOUT; | |
8134 | default: | |
f0d66153 | 8135 | MISSING_CASE(flags); |
87660502 L |
8136 | return 0; |
8137 | } | |
8138 | } | |
8139 | ||
8140 | static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv) | |
8141 | { | |
8142 | uint32_t flags = | |
8143 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8144 | ||
8145 | switch (flags) { | |
8146 | case GEN6_PCODE_SUCCESS: | |
8147 | return 0; | |
8148 | case GEN6_PCODE_ILLEGAL_CMD: | |
8149 | return -ENXIO; | |
8150 | case GEN7_PCODE_TIMEOUT: | |
8151 | return -ETIMEDOUT; | |
8152 | case GEN7_PCODE_ILLEGAL_DATA: | |
8153 | return -EINVAL; | |
8154 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
8155 | return -EOVERFLOW; | |
8156 | default: | |
8157 | MISSING_CASE(flags); | |
8158 | return 0; | |
8159 | } | |
8160 | } | |
8161 | ||
151a49d0 | 8162 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 8163 | { |
87660502 L |
8164 | int status; |
8165 | ||
4fc688ce | 8166 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8167 | |
3f5582dd CW |
8168 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8169 | * use te fw I915_READ variants to reduce the amount of work | |
8170 | * required when reading/writing. | |
8171 | */ | |
8172 | ||
8173 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
42c0526c BW |
8174 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
8175 | return -EAGAIN; | |
8176 | } | |
8177 | ||
3f5582dd CW |
8178 | I915_WRITE_FW(GEN6_PCODE_DATA, *val); |
8179 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); | |
8180 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
42c0526c | 8181 | |
e09a3036 CW |
8182 | if (__intel_wait_for_register_fw(dev_priv, |
8183 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
8184 | 500, 0, NULL)) { | |
42c0526c BW |
8185 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
8186 | return -ETIMEDOUT; | |
8187 | } | |
8188 | ||
3f5582dd CW |
8189 | *val = I915_READ_FW(GEN6_PCODE_DATA); |
8190 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); | |
42c0526c | 8191 | |
87660502 L |
8192 | if (INTEL_GEN(dev_priv) > 6) |
8193 | status = gen7_check_mailbox_status(dev_priv); | |
8194 | else | |
8195 | status = gen6_check_mailbox_status(dev_priv); | |
8196 | ||
8197 | if (status) { | |
8198 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n", | |
8199 | status); | |
8200 | return status; | |
8201 | } | |
8202 | ||
42c0526c BW |
8203 | return 0; |
8204 | } | |
8205 | ||
3f5582dd | 8206 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, |
87660502 | 8207 | u32 mbox, u32 val) |
42c0526c | 8208 | { |
87660502 L |
8209 | int status; |
8210 | ||
4fc688ce | 8211 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8212 | |
3f5582dd CW |
8213 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8214 | * use te fw I915_READ variants to reduce the amount of work | |
8215 | * required when reading/writing. | |
8216 | */ | |
8217 | ||
8218 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
42c0526c BW |
8219 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
8220 | return -EAGAIN; | |
8221 | } | |
8222 | ||
3f5582dd | 8223 | I915_WRITE_FW(GEN6_PCODE_DATA, val); |
8bf41b72 | 8224 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); |
3f5582dd | 8225 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
42c0526c | 8226 | |
e09a3036 CW |
8227 | if (__intel_wait_for_register_fw(dev_priv, |
8228 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
8229 | 500, 0, NULL)) { | |
42c0526c BW |
8230 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
8231 | return -ETIMEDOUT; | |
8232 | } | |
8233 | ||
3f5582dd | 8234 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); |
42c0526c | 8235 | |
87660502 L |
8236 | if (INTEL_GEN(dev_priv) > 6) |
8237 | status = gen7_check_mailbox_status(dev_priv); | |
8238 | else | |
8239 | status = gen6_check_mailbox_status(dev_priv); | |
8240 | ||
8241 | if (status) { | |
8242 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n", | |
8243 | status); | |
8244 | return status; | |
8245 | } | |
8246 | ||
42c0526c BW |
8247 | return 0; |
8248 | } | |
a0e4e199 | 8249 | |
a0b8a1fe ID |
8250 | static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox, |
8251 | u32 request, u32 reply_mask, u32 reply, | |
8252 | u32 *status) | |
8253 | { | |
8254 | u32 val = request; | |
8255 | ||
8256 | *status = sandybridge_pcode_read(dev_priv, mbox, &val); | |
8257 | ||
8258 | return *status || ((val & reply_mask) == reply); | |
8259 | } | |
8260 | ||
8261 | /** | |
8262 | * skl_pcode_request - send PCODE request until acknowledgment | |
8263 | * @dev_priv: device private | |
8264 | * @mbox: PCODE mailbox ID the request is targeted for | |
8265 | * @request: request ID | |
8266 | * @reply_mask: mask used to check for request acknowledgment | |
8267 | * @reply: value used to check for request acknowledgment | |
8268 | * @timeout_base_ms: timeout for polling with preemption enabled | |
8269 | * | |
8270 | * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE | |
0129936d | 8271 | * reports an error or an overall timeout of @timeout_base_ms+50 ms expires. |
a0b8a1fe ID |
8272 | * The request is acknowledged once the PCODE reply dword equals @reply after |
8273 | * applying @reply_mask. Polling is first attempted with preemption enabled | |
0129936d | 8274 | * for @timeout_base_ms and if this times out for another 50 ms with |
a0b8a1fe ID |
8275 | * preemption disabled. |
8276 | * | |
8277 | * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some | |
8278 | * other error as reported by PCODE. | |
8279 | */ | |
8280 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, | |
8281 | u32 reply_mask, u32 reply, int timeout_base_ms) | |
8282 | { | |
8283 | u32 status; | |
8284 | int ret; | |
8285 | ||
8286 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
8287 | ||
8288 | #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \ | |
8289 | &status) | |
8290 | ||
8291 | /* | |
8292 | * Prime the PCODE by doing a request first. Normally it guarantees | |
8293 | * that a subsequent request, at most @timeout_base_ms later, succeeds. | |
8294 | * _wait_for() doesn't guarantee when its passed condition is evaluated | |
8295 | * first, so send the first request explicitly. | |
8296 | */ | |
8297 | if (COND) { | |
8298 | ret = 0; | |
8299 | goto out; | |
8300 | } | |
8301 | ret = _wait_for(COND, timeout_base_ms * 1000, 10); | |
8302 | if (!ret) | |
8303 | goto out; | |
8304 | ||
8305 | /* | |
8306 | * The above can time out if the number of requests was low (2 in the | |
8307 | * worst case) _and_ PCODE was busy for some reason even after a | |
8308 | * (queued) request and @timeout_base_ms delay. As a workaround retry | |
8309 | * the poll with preemption disabled to maximize the number of | |
0129936d | 8310 | * requests. Increase the timeout from @timeout_base_ms to 50ms to |
a0b8a1fe | 8311 | * account for interrupts that could reduce the number of these |
0129936d ID |
8312 | * requests, and for any quirks of the PCODE firmware that delays |
8313 | * the request completion. | |
a0b8a1fe ID |
8314 | */ |
8315 | DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n"); | |
8316 | WARN_ON_ONCE(timeout_base_ms > 3); | |
8317 | preempt_disable(); | |
0129936d | 8318 | ret = wait_for_atomic(COND, 50); |
a0b8a1fe ID |
8319 | preempt_enable(); |
8320 | ||
8321 | out: | |
8322 | return ret ? ret : status; | |
8323 | #undef COND | |
8324 | } | |
8325 | ||
dd06f88c VS |
8326 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
8327 | { | |
c30fec65 VS |
8328 | /* |
8329 | * N = val - 0xb7 | |
8330 | * Slow = Fast = GPLL ref * N | |
8331 | */ | |
8332 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000); | |
855ba3be JB |
8333 | } |
8334 | ||
b55dd647 | 8335 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 8336 | { |
c30fec65 | 8337 | return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7; |
855ba3be JB |
8338 | } |
8339 | ||
b55dd647 | 8340 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8341 | { |
c30fec65 VS |
8342 | /* |
8343 | * N = val / 2 | |
8344 | * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 | |
8345 | */ | |
8346 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000); | |
22b1b2f8 D |
8347 | } |
8348 | ||
b55dd647 | 8349 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8350 | { |
1c14762d | 8351 | /* CHV needs even values */ |
c30fec65 | 8352 | return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2; |
22b1b2f8 D |
8353 | } |
8354 | ||
616bc820 | 8355 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8356 | { |
2d1fe073 | 8357 | if (IS_GEN9(dev_priv)) |
500a3d2e MK |
8358 | return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, |
8359 | GEN9_FREQ_SCALER); | |
2d1fe073 | 8360 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 8361 | return chv_gpu_freq(dev_priv, val); |
2d1fe073 | 8362 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
8363 | return byt_gpu_freq(dev_priv, val); |
8364 | else | |
8365 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
8366 | } |
8367 | ||
616bc820 VS |
8368 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
8369 | { | |
2d1fe073 | 8370 | if (IS_GEN9(dev_priv)) |
500a3d2e MK |
8371 | return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, |
8372 | GT_FREQUENCY_MULTIPLIER); | |
2d1fe073 | 8373 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 8374 | return chv_freq_opcode(dev_priv, val); |
2d1fe073 | 8375 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
8376 | return byt_freq_opcode(dev_priv, val); |
8377 | else | |
500a3d2e | 8378 | return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); |
616bc820 | 8379 | } |
22b1b2f8 | 8380 | |
6ad790c0 CW |
8381 | struct request_boost { |
8382 | struct work_struct work; | |
eed29a5b | 8383 | struct drm_i915_gem_request *req; |
6ad790c0 CW |
8384 | }; |
8385 | ||
8386 | static void __intel_rps_boost_work(struct work_struct *work) | |
8387 | { | |
8388 | struct request_boost *boost = container_of(work, struct request_boost, work); | |
e61b9958 | 8389 | struct drm_i915_gem_request *req = boost->req; |
6ad790c0 | 8390 | |
f69a02c9 | 8391 | if (!i915_gem_request_completed(req)) |
c033666a | 8392 | gen6_rps_boost(req->i915, NULL, req->emitted_jiffies); |
6ad790c0 | 8393 | |
e8a261ea | 8394 | i915_gem_request_put(req); |
6ad790c0 CW |
8395 | kfree(boost); |
8396 | } | |
8397 | ||
91d14251 | 8398 | void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req) |
6ad790c0 CW |
8399 | { |
8400 | struct request_boost *boost; | |
8401 | ||
91d14251 | 8402 | if (req == NULL || INTEL_GEN(req->i915) < 6) |
6ad790c0 CW |
8403 | return; |
8404 | ||
f69a02c9 | 8405 | if (i915_gem_request_completed(req)) |
e61b9958 CW |
8406 | return; |
8407 | ||
6ad790c0 CW |
8408 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
8409 | if (boost == NULL) | |
8410 | return; | |
8411 | ||
e8a261ea | 8412 | boost->req = i915_gem_request_get(req); |
6ad790c0 CW |
8413 | |
8414 | INIT_WORK(&boost->work, __intel_rps_boost_work); | |
91d14251 | 8415 | queue_work(req->i915->wq, &boost->work); |
6ad790c0 CW |
8416 | } |
8417 | ||
192aa181 | 8418 | void intel_pm_setup(struct drm_i915_private *dev_priv) |
907b28c5 | 8419 | { |
f742a552 | 8420 | mutex_init(&dev_priv->rps.hw_lock); |
8d3afd7d | 8421 | spin_lock_init(&dev_priv->rps.client_lock); |
f742a552 | 8422 | |
54b4f68f CW |
8423 | INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work, |
8424 | __intel_autoenable_gt_powersave); | |
1854d5ca | 8425 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
5d584b2e | 8426 | |
33688d95 | 8427 | dev_priv->pm.suspended = false; |
1f814dac | 8428 | atomic_set(&dev_priv->pm.wakeref_count, 0); |
907b28c5 | 8429 | } |
135bafa5 | 8430 | |
47c21d9a MK |
8431 | static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, |
8432 | const i915_reg_t reg) | |
8433 | { | |
facbecad | 8434 | u32 lower, upper, tmp; |
71cc2b18 | 8435 | int loop = 2; |
47c21d9a MK |
8436 | |
8437 | /* The register accessed do not need forcewake. We borrow | |
8438 | * uncore lock to prevent concurrent access to range reg. | |
8439 | */ | |
8440 | spin_lock_irq(&dev_priv->uncore.lock); | |
47c21d9a MK |
8441 | |
8442 | /* vlv and chv residency counters are 40 bits in width. | |
8443 | * With a control bit, we can choose between upper or lower | |
8444 | * 32bit window into this counter. | |
facbecad CW |
8445 | * |
8446 | * Although we always use the counter in high-range mode elsewhere, | |
8447 | * userspace may attempt to read the value before rc6 is initialised, | |
8448 | * before we have set the default VLV_COUNTER_CONTROL value. So always | |
8449 | * set the high bit to be safe. | |
47c21d9a | 8450 | */ |
facbecad CW |
8451 | I915_WRITE_FW(VLV_COUNTER_CONTROL, |
8452 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); | |
47c21d9a MK |
8453 | upper = I915_READ_FW(reg); |
8454 | do { | |
8455 | tmp = upper; | |
8456 | ||
8457 | I915_WRITE_FW(VLV_COUNTER_CONTROL, | |
8458 | _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); | |
8459 | lower = I915_READ_FW(reg); | |
8460 | ||
8461 | I915_WRITE_FW(VLV_COUNTER_CONTROL, | |
8462 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); | |
8463 | upper = I915_READ_FW(reg); | |
71cc2b18 | 8464 | } while (upper != tmp && --loop); |
47c21d9a | 8465 | |
facbecad CW |
8466 | /* Everywhere else we always use VLV_COUNTER_CONTROL with the |
8467 | * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set | |
8468 | * now. | |
8469 | */ | |
8470 | ||
47c21d9a MK |
8471 | spin_unlock_irq(&dev_priv->uncore.lock); |
8472 | ||
8473 | return lower | (u64)upper << 8; | |
8474 | } | |
8475 | ||
c5a0ad11 MK |
8476 | u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
8477 | const i915_reg_t reg) | |
135bafa5 | 8478 | { |
47c21d9a | 8479 | u64 time_hw, units, div; |
135bafa5 MK |
8480 | |
8481 | if (!intel_enable_rc6()) | |
8482 | return 0; | |
8483 | ||
8484 | intel_runtime_pm_get(dev_priv); | |
8485 | ||
8486 | /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ | |
8487 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
c5a0ad11 | 8488 | units = 1000; |
135bafa5 MK |
8489 | div = dev_priv->czclk_freq; |
8490 | ||
47c21d9a | 8491 | time_hw = vlv_residency_raw(dev_priv, reg); |
135bafa5 | 8492 | } else if (IS_GEN9_LP(dev_priv)) { |
c5a0ad11 | 8493 | units = 1000; |
135bafa5 | 8494 | div = 1200; /* 833.33ns */ |
135bafa5 | 8495 | |
47c21d9a MK |
8496 | time_hw = I915_READ(reg); |
8497 | } else { | |
8498 | units = 128000; /* 1.28us */ | |
8499 | div = 100000; | |
8500 | ||
8501 | time_hw = I915_READ(reg); | |
8502 | } | |
135bafa5 MK |
8503 | |
8504 | intel_runtime_pm_put(dev_priv); | |
47c21d9a | 8505 | return DIV_ROUND_UP_ULL(time_hw * units, div); |
135bafa5 | 8506 | } |