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drm/i915: Fix typo in semaphore debug message
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
46f16e63 59static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
a82abe43 60{
b033bb6d 61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
b033bb6d
MK		 65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0 67
9fb5026f 68 /* WaEnableChickenDCPR:skl,bxt,kbl,glk */
590e8ff0
MK		 69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
9fb5026f 73 /* WaFbcWakeMemOn:skl,bxt,kbl,glk */
303d4ea5
MK		 74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 81}
82
46f16e63 83static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
b033bb6d 84{
46f16e63 85 gen9_init_clock_gating(dev_priv);
b033bb6d 86
a7546159
NH		 87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
32608ca2
ID		 91 /*
92 * FIXME:
868434c5 93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 94 */
32608ca2 95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
8aeaf64c
JN		 102 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
103 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 104}
105
9fb5026f
ACO		 106static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
107{
108 gen9_init_clock_gating(dev_priv);
109
110 /*
111 * WaDisablePWMClockGating:glk
112 * Backlight PWM may stop in the asserted state, causing backlight
113 * to stay fully on.
114 */
115 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
116 PWM1_GATING_DIS | PWM2_GATING_DIS);
117}
118
148ac1f3 119static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 120{
c921aba8
DV		 121 u32 tmp;
122
123 tmp = I915_READ(CLKCFG);
124
125 switch (tmp & CLKCFG_FSB_MASK) {
126 case CLKCFG_FSB_533:
127 dev_priv->fsb_freq = 533; /* 133*4 */
128 break;
129 case CLKCFG_FSB_800:
130 dev_priv->fsb_freq = 800; /* 200*4 */
131 break;
132 case CLKCFG_FSB_667:
133 dev_priv->fsb_freq = 667; /* 167*4 */
134 break;
135 case CLKCFG_FSB_400:
136 dev_priv->fsb_freq = 400; /* 100*4 */
137 break;
138 }
139
140 switch (tmp & CLKCFG_MEM_MASK) {
141 case CLKCFG_MEM_533:
142 dev_priv->mem_freq = 533;
143 break;
144 case CLKCFG_MEM_667:
145 dev_priv->mem_freq = 667;
146 break;
147 case CLKCFG_MEM_800:
148 dev_priv->mem_freq = 800;
149 break;
150 }
151
152 /* detect pineview DDR3 setting */
153 tmp = I915_READ(CSHRDDR3CTL);
154 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
155}
156
148ac1f3 157static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 158{
c921aba8
DV		 159 u16 ddrpll, csipll;
160
161 ddrpll = I915_READ16(DDRMPLL1);
162 csipll = I915_READ16(CSIPLL0);
163
164 switch (ddrpll & 0xff) {
165 case 0xc:
166 dev_priv->mem_freq = 800;
167 break;
168 case 0x10:
169 dev_priv->mem_freq = 1066;
170 break;
171 case 0x14:
172 dev_priv->mem_freq = 1333;
173 break;
174 case 0x18:
175 dev_priv->mem_freq = 1600;
176 break;
177 default:
178 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
179 ddrpll & 0xff);
180 dev_priv->mem_freq = 0;
181 break;
182 }
183
20e4d407 184 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 185
186 switch (csipll & 0x3ff) {
187 case 0x00c:
188 dev_priv->fsb_freq = 3200;
189 break;
190 case 0x00e:
191 dev_priv->fsb_freq = 3733;
192 break;
193 case 0x010:
194 dev_priv->fsb_freq = 4266;
195 break;
196 case 0x012:
197 dev_priv->fsb_freq = 4800;
198 break;
199 case 0x014:
200 dev_priv->fsb_freq = 5333;
201 break;
202 case 0x016:
203 dev_priv->fsb_freq = 5866;
204 break;
205 case 0x018:
206 dev_priv->fsb_freq = 6400;
207 break;
208 default:
209 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
210 csipll & 0x3ff);
211 dev_priv->fsb_freq = 0;
212 break;
213 }
214
215 if (dev_priv->fsb_freq == 3200) {
20e4d407 216 dev_priv->ips.c_m = 0;
c921aba8 217 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 218 dev_priv->ips.c_m = 1;
c921aba8 219 } else {
20e4d407 220 dev_priv->ips.c_m = 2;
c921aba8
DV		 221 }
222}
223
b445e3b0
ED		 224static const struct cxsr_latency cxsr_latency_table[] = {
225 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
226 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
227 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
228 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
229 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
230
231 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
232 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
233 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
234 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
235 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
236
237 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
238 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
239 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
240 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
241 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
242
243 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
244 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
245 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
246 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
247 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
248
249 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
250 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
251 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
252 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
253 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
254
255 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
256 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
257 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
258 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
259 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
260};
261
44a655ca
TU		 262static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
263 bool is_ddr3,
b445e3b0
ED		 264 int fsb,
265 int mem)
266{
267 const struct cxsr_latency *latency;
268 int i;
269
270 if (fsb == 0 || mem == 0)
271 return NULL;
272
273 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
274 latency = &cxsr_latency_table[i];
275 if (is_desktop == latency->is_desktop &&
276 is_ddr3 == latency->is_ddr3 &&
277 fsb == latency->fsb_freq && mem == latency->mem_freq)
278 return latency;
279 }
280
281 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
282
283 return NULL;
284}
285
fc1ac8de
VS		 286static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
287{
288 u32 val;
289
290 mutex_lock(&dev_priv->rps.hw_lock);
291
292 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
293 if (enable)
294 val &= ~FORCE_DDR_HIGH_FREQ;
295 else
296 val |= FORCE_DDR_HIGH_FREQ;
297 val &= ~FORCE_DDR_LOW_FREQ;
298 val |= FORCE_DDR_FREQ_REQ_ACK;
299 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
300
301 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
302 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
303 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
304
305 mutex_unlock(&dev_priv->rps.hw_lock);
306}
307
cfb41411
VS		 308static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
309{
310 u32 val;
311
312 mutex_lock(&dev_priv->rps.hw_lock);
313
314 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
315 if (enable)
316 val |= DSP_MAXFIFO_PM5_ENABLE;
317 else
318 val &= ~DSP_MAXFIFO_PM5_ENABLE;
319 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
320
321 mutex_unlock(&dev_priv->rps.hw_lock);
322}
323
f4998963
VS		 324#define FW_WM(value, plane) \
325 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
326
11a85d6a 327static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 328{
11a85d6a 329 bool was_enabled;
5209b1f4 330 u32 val;
b445e3b0 331
920a14b2 332 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
11a85d6a 333 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5209b1f4 334 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 335 POSTING_READ(FW_BLC_SELF_VLV);
c0f86832 336 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
11a85d6a 337 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5209b1f4 338 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 339 POSTING_READ(FW_BLC_SELF);
9b1e14f4 340 } else if (IS_PINEVIEW(dev_priv)) {
11a85d6a
VS		 341 val = I915_READ(DSPFW3);
342 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
343 if (enable)
344 val |= PINEVIEW_SELF_REFRESH_EN;
345 else
346 val &= ~PINEVIEW_SELF_REFRESH_EN;
5209b1f4 347 I915_WRITE(DSPFW3, val);
a7a6c498 348 POSTING_READ(DSPFW3);
50a0bc90 349 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
11a85d6a 350 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5209b1f4
ID		 351 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
352 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
353 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 354 POSTING_READ(FW_BLC_SELF);
50a0bc90 355 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 356 /*
357 * FIXME can't find a bit like this for 915G, and
358 * and yet it does have the related watermark in
359 * FW_BLC_SELF. What's going on?
360 */
11a85d6a 361 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
5209b1f4
ID		 362 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
363 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
364 I915_WRITE(INSTPM, val);
a7a6c498 365 POSTING_READ(INSTPM);
5209b1f4 366 } else {
11a85d6a 367 return false;
5209b1f4 368 }
b445e3b0 369
11a85d6a
VS		 370 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
371 enableddisabled(enable),
372 enableddisabled(was_enabled));
373
374 return was_enabled;
b445e3b0
ED		 375}
376
11a85d6a 377bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
3d90e649 378{
11a85d6a
VS		 379 bool ret;
380
3d90e649 381 mutex_lock(&dev_priv->wm.wm_mutex);
11a85d6a 382 ret = _intel_set_memory_cxsr(dev_priv, enable);
3d90e649
VS		 383 dev_priv->wm.vlv.cxsr = enable;
384 mutex_unlock(&dev_priv->wm.wm_mutex);
11a85d6a
VS		 385
386 return ret;
3d90e649 387}
fc1ac8de 388
b445e3b0
ED		 389/*
390 * Latency for FIFO fetches is dependent on several factors:
391 * - memory configuration (speed, channels)
392 * - chipset
393 * - current MCH state
394 * It can be fairly high in some situations, so here we assume a fairly
395 * pessimal value. It's a tradeoff between extra memory fetches (if we
396 * set this value too high, the FIFO will fetch frequently to stay full)
397 * and power consumption (set it too low to save power and we might see
398 * FIFO underruns and display "flicker").
399 *
400 * A value of 5us seems to be a good balance; safe for very low end
401 * platforms but not overly aggressive on lower latency configs.
402 */
5aef6003 403static const int pessimal_latency_ns = 5000;
b445e3b0 404
b5004720
VS		 405#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
406 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
407
49845a23 408static int vlv_get_fifo_size(struct intel_plane *plane)
b5004720 409{
49845a23 410 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
b5004720
VS		 411 int sprite0_start, sprite1_start, size;
412
49845a23
VS		 413 if (plane->id == PLANE_CURSOR)
414 return 63;
415
416 switch (plane->pipe) {
b5004720
VS		 417 uint32_t dsparb, dsparb2, dsparb3;
418 case PIPE_A:
419 dsparb = I915_READ(DSPARB);
420 dsparb2 = I915_READ(DSPARB2);
421 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
422 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
423 break;
424 case PIPE_B:
425 dsparb = I915_READ(DSPARB);
426 dsparb2 = I915_READ(DSPARB2);
427 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
428 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
429 break;
430 case PIPE_C:
431 dsparb2 = I915_READ(DSPARB2);
432 dsparb3 = I915_READ(DSPARB3);
433 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
434 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
435 break;
436 default:
437 return 0;
438 }
439
49845a23
VS		 440 switch (plane->id) {
441 case PLANE_PRIMARY:
b5004720
VS		 442 size = sprite0_start;
443 break;
49845a23 444 case PLANE_SPRITE0:
b5004720
VS		 445 size = sprite1_start - sprite0_start;
446 break;
49845a23 447 case PLANE_SPRITE1:
b5004720
VS		 448 size = 512 - 1 - sprite1_start;
449 break;
450 default:
451 return 0;
452 }
453
49845a23 454 DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
b5004720
VS		 455
456 return size;
457}
458
ef0f5e93 459static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 460{
b445e3b0
ED		 461 uint32_t dsparb = I915_READ(DSPARB);
462 int size;
463
464 size = dsparb & 0x7f;
465 if (plane)
466 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
467
468 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
469 plane ? "B" : "A", size);
470
471 return size;
472}
473
ef0f5e93 474static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 475{
b445e3b0
ED		 476 uint32_t dsparb = I915_READ(DSPARB);
477 int size;
478
479 size = dsparb & 0x1ff;
480 if (plane)
481 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
482 size >>= 1; /* Convert to cachelines */
483
484 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
485 plane ? "B" : "A", size);
486
487 return size;
488}
489
ef0f5e93 490static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 491{
b445e3b0
ED		 492 uint32_t dsparb = I915_READ(DSPARB);
493 int size;
494
495 size = dsparb & 0x7f;
496 size >>= 2; /* Convert to cachelines */
497
498 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
499 plane ? "B" : "A",
500 size);
501
502 return size;
503}
504
b445e3b0
ED		 505/* Pineview has different values for various configs */
506static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 507 .fifo_size = PINEVIEW_DISPLAY_FIFO,
508 .max_wm = PINEVIEW_MAX_WM,
509 .default_wm = PINEVIEW_DFT_WM,
510 .guard_size = PINEVIEW_GUARD_WM,
511 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 512};
513static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 514 .fifo_size = PINEVIEW_DISPLAY_FIFO,
515 .max_wm = PINEVIEW_MAX_WM,
516 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
517 .guard_size = PINEVIEW_GUARD_WM,
518 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 519};
520static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 521 .fifo_size = PINEVIEW_CURSOR_FIFO,
522 .max_wm = PINEVIEW_CURSOR_MAX_WM,
523 .default_wm = PINEVIEW_CURSOR_DFT_WM,
524 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
525 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 526};
527static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 528 .fifo_size = PINEVIEW_CURSOR_FIFO,
529 .max_wm = PINEVIEW_CURSOR_MAX_WM,
530 .default_wm = PINEVIEW_CURSOR_DFT_WM,
531 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
532 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 533};
534static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 535 .fifo_size = G4X_FIFO_SIZE,
536 .max_wm = G4X_MAX_WM,
537 .default_wm = G4X_MAX_WM,
538 .guard_size = 2,
539 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 540};
541static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 542 .fifo_size = I965_CURSOR_FIFO,
543 .max_wm = I965_CURSOR_MAX_WM,
544 .default_wm = I965_CURSOR_DFT_WM,
545 .guard_size = 2,
546 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 547};
b445e3b0 548static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 549 .fifo_size = I965_CURSOR_FIFO,
550 .max_wm = I965_CURSOR_MAX_WM,
551 .default_wm = I965_CURSOR_DFT_WM,
552 .guard_size = 2,
553 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 554};
555static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 556 .fifo_size = I945_FIFO_SIZE,
557 .max_wm = I915_MAX_WM,
558 .default_wm = 1,
559 .guard_size = 2,
560 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 561};
562static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 563 .fifo_size = I915_FIFO_SIZE,
564 .max_wm = I915_MAX_WM,
565 .default_wm = 1,
566 .guard_size = 2,
567 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 568};
9d539105 569static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 570 .fifo_size = I855GM_FIFO_SIZE,
571 .max_wm = I915_MAX_WM,
572 .default_wm = 1,
573 .guard_size = 2,
574 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 575};
9d539105
VS		 576static const struct intel_watermark_params i830_bc_wm_info = {
577 .fifo_size = I855GM_FIFO_SIZE,
578 .max_wm = I915_MAX_WM/2,
579 .default_wm = 1,
580 .guard_size = 2,
581 .cacheline_size = I830_FIFO_LINE_SIZE,
582};
feb56b93 583static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 584 .fifo_size = I830_FIFO_SIZE,
585 .max_wm = I915_MAX_WM,
586 .default_wm = 1,
587 .guard_size = 2,
588 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 589};
590
b445e3b0
ED		 591/**
592 * intel_calculate_wm - calculate watermark level
593 * @clock_in_khz: pixel clock
594 * @wm: chip FIFO params
ac484963 595 * @cpp: bytes per pixel
b445e3b0
ED		 596 * @latency_ns: memory latency for the platform
597 *
598 * Calculate the watermark level (the level at which the display plane will
599 * start fetching from memory again). Each chip has a different display
600 * FIFO size and allocation, so the caller needs to figure that out and pass
601 * in the correct intel_watermark_params structure.
602 *
603 * As the pixel clock runs, the FIFO will be drained at a rate that depends
604 * on the pixel size. When it reaches the watermark level, it'll start
605 * fetching FIFO line sized based chunks from memory until the FIFO fills
606 * past the watermark point. If the FIFO drains completely, a FIFO underrun
607 * will occur, and a display engine hang could result.
608 */
609static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
610 const struct intel_watermark_params *wm,
ac484963 611 int fifo_size, int cpp,
b445e3b0
ED		 612 unsigned long latency_ns)
613{
614 long entries_required, wm_size;
615
616 /*
617 * Note: we need to make sure we don't overflow for various clock &
618 * latency values.
619 * clocks go from a few thousand to several hundred thousand.
620 * latency is usually a few thousand
621 */
ac484963 622 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 623 1000;
624 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
625
626 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
627
628 wm_size = fifo_size - (entries_required + wm->guard_size);
629
630 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
631
632 /* Don't promote wm_size to unsigned... */
633 if (wm_size > (long)wm->max_wm)
634 wm_size = wm->max_wm;
635 if (wm_size <= 0)
636 wm_size = wm->default_wm;
d6feb196
VS		 637
638 /*
639 * Bspec seems to indicate that the value shouldn't be lower than
640 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
641 * Lets go for 8 which is the burst size since certain platforms
642 * already use a hardcoded 8 (which is what the spec says should be
643 * done).
644 */
645 if (wm_size <= 8)
646 wm_size = 8;
647
b445e3b0
ED		 648 return wm_size;
649}
650
ffc7a76b 651static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
b445e3b0 652{
efc2611e 653 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 654
ffc7a76b 655 for_each_intel_crtc(&dev_priv->drm, crtc) {
efc2611e 656 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 657 if (enabled)
658 return NULL;
659 enabled = crtc;
660 }
661 }
662
663 return enabled;
664}
665
432081bc 666static void pineview_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 667{
ffc7a76b 668 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 669 struct intel_crtc *crtc;
b445e3b0
ED		 670 const struct cxsr_latency *latency;
671 u32 reg;
672 unsigned long wm;
673
50a0bc90
TU		 674 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
675 dev_priv->is_ddr3,
676 dev_priv->fsb_freq,
677 dev_priv->mem_freq);
b445e3b0
ED		 678 if (!latency) {
679 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 680 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 681 return;
682 }
683
ffc7a76b 684 crtc = single_enabled_crtc(dev_priv);
b445e3b0 685 if (crtc) {
efc2611e
VS		 686 const struct drm_display_mode *adjusted_mode =
687 &crtc->config->base.adjusted_mode;
688 const struct drm_framebuffer *fb =
689 crtc->base.primary->state->fb;
353c8598 690 int cpp = fb->format->cpp[0];
7c5f93b0 691 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 692
693 /* Display SR */
694 wm = intel_calculate_wm(clock, &pineview_display_wm,
695 pineview_display_wm.fifo_size,
ac484963 696 cpp, latency->display_sr);
b445e3b0
ED		 697 reg = I915_READ(DSPFW1);
698 reg &= ~DSPFW_SR_MASK;
f4998963 699 reg |= FW_WM(wm, SR);
b445e3b0
ED		 700 I915_WRITE(DSPFW1, reg);
701 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
702
703 /* cursor SR */
704 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
705 pineview_display_wm.fifo_size,
ac484963 706 cpp, latency->cursor_sr);
b445e3b0
ED		 707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 709 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 710 I915_WRITE(DSPFW3, reg);
711
712 /* Display HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
ac484963 715 cpp, latency->display_hpll_disable);
b445e3b0
ED		 716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 718 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 719 I915_WRITE(DSPFW3, reg);
720
721 /* cursor HPLL off SR */
722 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
723 pineview_display_hplloff_wm.fifo_size,
ac484963 724 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 725 reg = I915_READ(DSPFW3);
726 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 727 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 728 I915_WRITE(DSPFW3, reg);
729 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
730
5209b1f4 731 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 732 } else {
5209b1f4 733 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 734 }
735}
736
f0ce2310 737static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
b445e3b0
ED		 738 int plane,
739 const struct intel_watermark_params *display,
740 int display_latency_ns,
741 const struct intel_watermark_params *cursor,
742 int cursor_latency_ns,
743 int *plane_wm,
744 int *cursor_wm)
745{
efc2611e 746 struct intel_crtc *crtc;
4fe8590a 747 const struct drm_display_mode *adjusted_mode;
efc2611e 748 const struct drm_framebuffer *fb;
ac484963 749 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 750 int line_time_us, line_count;
751 int entries, tlb_miss;
752
b91eb5cc 753 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e 754 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 755 *cursor_wm = cursor->guard_size;
756 *plane_wm = display->guard_size;
757 return false;
758 }
759
efc2611e
VS		 760 adjusted_mode = &crtc->config->base.adjusted_mode;
761 fb = crtc->base.primary->state->fb;
241bfc38 762 clock = adjusted_mode->crtc_clock;
fec8cba3 763 htotal = adjusted_mode->crtc_htotal;
efc2611e 764 hdisplay = crtc->config->pipe_src_w;
353c8598 765 cpp = fb->format->cpp[0];
b445e3b0
ED		 766
767 /* Use the small buffer method to calculate plane watermark */
ac484963 768 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 769 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
770 if (tlb_miss > 0)
771 entries += tlb_miss;
772 entries = DIV_ROUND_UP(entries, display->cacheline_size);
773 *plane_wm = entries + display->guard_size;
774 if (*plane_wm > (int)display->max_wm)
775 *plane_wm = display->max_wm;
776
777 /* Use the large buffer method to calculate cursor watermark */
922044c9 778 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 779 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
efc2611e 780 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
b445e3b0
ED		 781 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
782 if (tlb_miss > 0)
783 entries += tlb_miss;
784 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
785 *cursor_wm = entries + cursor->guard_size;
786 if (*cursor_wm > (int)cursor->max_wm)
787 *cursor_wm = (int)cursor->max_wm;
788
789 return true;
790}
791
792/*
793 * Check the wm result.
794 *
795 * If any calculated watermark values is larger than the maximum value that
796 * can be programmed into the associated watermark register, that watermark
797 * must be disabled.
798 */
f0ce2310 799static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 800 int display_wm, int cursor_wm,
801 const struct intel_watermark_params *display,
802 const struct intel_watermark_params *cursor)
803{
804 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
805 display_wm, cursor_wm);
806
807 if (display_wm > display->max_wm) {
ae9400ca 808 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 809 display_wm, display->max_wm);
810 return false;
811 }
812
813 if (cursor_wm > cursor->max_wm) {
ae9400ca 814 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 815 cursor_wm, cursor->max_wm);
816 return false;
817 }
818
819 if (!(display_wm || cursor_wm)) {
820 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
821 return false;
822 }
823
824 return true;
825}
826
f0ce2310 827static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 828 int plane,
829 int latency_ns,
830 const struct intel_watermark_params *display,
831 const struct intel_watermark_params *cursor,
832 int *display_wm, int *cursor_wm)
833{
efc2611e 834 struct intel_crtc *crtc;
4fe8590a 835 const struct drm_display_mode *adjusted_mode;
efc2611e 836 const struct drm_framebuffer *fb;
ac484963 837 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 838 unsigned long line_time_us;
839 int line_count, line_size;
840 int small, large;
841 int entries;
842
843 if (!latency_ns) {
844 *display_wm = *cursor_wm = 0;
845 return false;
846 }
847
b91eb5cc 848 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e
VS		 849 adjusted_mode = &crtc->config->base.adjusted_mode;
850 fb = crtc->base.primary->state->fb;
241bfc38 851 clock = adjusted_mode->crtc_clock;
fec8cba3 852 htotal = adjusted_mode->crtc_htotal;
efc2611e 853 hdisplay = crtc->config->pipe_src_w;
353c8598 854 cpp = fb->format->cpp[0];
b445e3b0 855
922044c9 856 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 857 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 858 line_size = hdisplay * cpp;
b445e3b0
ED		 859
860 /* Use the minimum of the small and large buffer method for primary */
ac484963 861 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 862 large = line_count * line_size;
863
864 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
865 *display_wm = entries + display->guard_size;
866
867 /* calculate the self-refresh watermark for display cursor */
efc2611e 868 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 869 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
870 *cursor_wm = entries + cursor->guard_size;
871
f0ce2310 872 return g4x_check_srwm(dev_priv,
b445e3b0
ED		 873 *display_wm, *cursor_wm,
874 display, cursor);
875}
876
15665979
VS		 877#define FW_WM_VLV(value, plane) \
878 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
879
50f4caef 880static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
0018fda1
VS		 881 const struct vlv_wm_values *wm)
882{
50f4caef
VS		 883 enum pipe pipe;
884
885 for_each_pipe(dev_priv, pipe) {
886 I915_WRITE(VLV_DDL(pipe),
887 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
888 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
889 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
890 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
891 }
0018fda1 892
6fe6a7ff
VS		 893 /*
894 * Zero the (unused) WM1 watermarks, and also clear all the
895 * high order bits so that there are no out of bounds values
896 * present in the registers during the reprogramming.
897 */
898 I915_WRITE(DSPHOWM, 0);
899 I915_WRITE(DSPHOWM1, 0);
900 I915_WRITE(DSPFW4, 0);
901 I915_WRITE(DSPFW5, 0);
902 I915_WRITE(DSPFW6, 0);
903
ae80152d 904 I915_WRITE(DSPFW1,
15665979 905 FW_WM(wm->sr.plane, SR) |
1b31389c
VS		 906 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
907 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
908 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
ae80152d 909 I915_WRITE(DSPFW2,
1b31389c
VS		 910 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
911 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
912 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
ae80152d 913 I915_WRITE(DSPFW3,
15665979 914 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 915
916 if (IS_CHERRYVIEW(dev_priv)) {
917 I915_WRITE(DSPFW7_CHV,
1b31389c
VS		 918 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
919 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
ae80152d 920 I915_WRITE(DSPFW8_CHV,
1b31389c
VS		 921 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
922 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
ae80152d 923 I915_WRITE(DSPFW9_CHV,
1b31389c
VS		 924 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
925 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
ae80152d 926 I915_WRITE(DSPHOWM,
15665979 927 FW_WM(wm->sr.plane >> 9, SR_HI) |
1b31389c
VS		 928 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
929 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
930 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
931 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
932 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
933 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
934 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
935 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
936 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
ae80152d
VS		 937 } else {
938 I915_WRITE(DSPFW7,
1b31389c
VS		 939 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
940 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
ae80152d 941 I915_WRITE(DSPHOWM,
15665979 942 FW_WM(wm->sr.plane >> 9, SR_HI) |
1b31389c
VS		 943 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
944 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
945 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
946 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
947 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
948 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
ae80152d
VS		 949 }
950
951 POSTING_READ(DSPFW1);
0018fda1
VS		 952}
953
15665979
VS		 954#undef FW_WM_VLV
955
6eb1a681
VS		 956enum vlv_wm_level {
957 VLV_WM_LEVEL_PM2,
958 VLV_WM_LEVEL_PM5,
959 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 960};
961
262cd2e1
VS		 962/* latency must be in 0.1us units. */
963static unsigned int vlv_wm_method2(unsigned int pixel_rate,
964 unsigned int pipe_htotal,
965 unsigned int horiz_pixels,
ac484963 966 unsigned int cpp,
262cd2e1
VS		 967 unsigned int latency)
968{
969 unsigned int ret;
970
971 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 972 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 973 ret = DIV_ROUND_UP(ret, 64);
974
975 return ret;
976}
977
bb726519 978static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
262cd2e1 979{
262cd2e1
VS		 980 /* all latencies in usec */
981 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
982
58590c14
VS		 983 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
984
262cd2e1
VS		 985 if (IS_CHERRYVIEW(dev_priv)) {
986 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
987 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 988
989 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 990 }
991}
992
e339d67e
VS		 993static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
994 const struct intel_plane_state *plane_state,
262cd2e1
VS		 995 int level)
996{
e339d67e 997 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
262cd2e1 998 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
e339d67e
VS		 999 const struct drm_display_mode *adjusted_mode =
1000 &crtc_state->base.adjusted_mode;
ac484963 1001 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 1002
1003 if (dev_priv->wm.pri_latency[level] == 0)
1004 return USHRT_MAX;
1005
e339d67e 1006 if (!plane_state->base.visible)
262cd2e1
VS		 1007 return 0;
1008
ef426c10 1009 cpp = plane_state->base.fb->format->cpp[0];
e339d67e
VS		 1010 clock = adjusted_mode->crtc_clock;
1011 htotal = adjusted_mode->crtc_htotal;
1012 width = crtc_state->pipe_src_w;
262cd2e1
VS		 1013 if (WARN_ON(htotal == 0))
1014 htotal = 1;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017 /*
1018 * FIXME the formula gives values that are
1019 * too big for the cursor FIFO, and hence we
1020 * would never be able to use cursors. For
1021 * now just hardcode the watermark.
1022 */
1023 wm = 63;
1024 } else {
ac484963 1025 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 1026 dev_priv->wm.pri_latency[level] * 10);
1027 }
1028
1029 return min_t(int, wm, USHRT_MAX);
1030}
1031
54f1b6e1
VS		 1032static void vlv_compute_fifo(struct intel_crtc *crtc)
1033{
1034 struct drm_device *dev = crtc->base.dev;
1035 struct vlv_wm_state *wm_state = &crtc->wm_state;
1036 struct intel_plane *plane;
1037 unsigned int total_rate = 0;
1038 const int fifo_size = 512 - 1;
1039 int fifo_extra, fifo_left = fifo_size;
1040
1041 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042 struct intel_plane_state *state =
1043 to_intel_plane_state(plane->base.state);
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
936e71e3 1048 if (state->base.visible) {
54f1b6e1 1049 wm_state->num_active_planes++;
353c8598 1050 total_rate += state->base.fb->format->cpp[0];
54f1b6e1
VS		 1051 }
1052 }
1053
1054 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055 struct intel_plane_state *state =
1056 to_intel_plane_state(plane->base.state);
1057 unsigned int rate;
1058
1059 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1060 plane->wm.fifo_size = 63;
1061 continue;
1062 }
1063
936e71e3 1064 if (!state->base.visible) {
54f1b6e1
VS		 1065 plane->wm.fifo_size = 0;
1066 continue;
1067 }
1068
353c8598 1069 rate = state->base.fb->format->cpp[0];
54f1b6e1
VS		 1070 plane->wm.fifo_size = fifo_size * rate / total_rate;
1071 fifo_left -= plane->wm.fifo_size;
1072 }
1073
1074 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1075
1076 /* spread the remainder evenly */
1077 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1078 int plane_extra;
1079
1080 if (fifo_left == 0)
1081 break;
1082
1083 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1084 continue;
1085
1086 /* give it all to the first plane if none are active */
1087 if (plane->wm.fifo_size == 0 &&
1088 wm_state->num_active_planes)
1089 continue;
1090
1091 plane_extra = min(fifo_extra, fifo_left);
1092 plane->wm.fifo_size += plane_extra;
1093 fifo_left -= plane_extra;
1094 }
1095
1096 WARN_ON(fifo_left != 0);
1097}
1098
26cca0e5
VS		 1099static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1100{
1101 if (wm > fifo_size)
1102 return USHRT_MAX;
1103 else
1104 return fifo_size - wm;
1105}
1106
262cd2e1
VS		 1107static void vlv_invert_wms(struct intel_crtc *crtc)
1108{
1109 struct vlv_wm_state *wm_state = &crtc->wm_state;
1110 int level;
1111
1112 for (level = 0; level < wm_state->num_levels; level++) {
7c951c00 1113 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b7f05d4a 1114 const int sr_fifo_size =
7c951c00 1115 INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
262cd2e1
VS		 1116 struct intel_plane *plane;
1117
26cca0e5
VS		 1118 wm_state->sr[level].plane =
1119 vlv_invert_wm_value(wm_state->sr[level].plane,
1120 sr_fifo_size);
1121 wm_state->sr[level].cursor =
1122 vlv_invert_wm_value(wm_state->sr[level].cursor,
1123 63);
262cd2e1 1124
7c951c00 1125 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
26cca0e5
VS		 1126 wm_state->wm[level].plane[plane->id] =
1127 vlv_invert_wm_value(wm_state->wm[level].plane[plane->id],
1128 plane->wm.fifo_size);
262cd2e1
VS		 1129 }
1130 }
1131}
1132
26e1fe4f 1133static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1 1134{
7c951c00 1135 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
262cd2e1
VS		 1136 struct vlv_wm_state *wm_state = &crtc->wm_state;
1137 struct intel_plane *plane;
262cd2e1
VS		 1138 int level;
1139
1140 memset(wm_state, 0, sizeof(*wm_state));
1141
852eb00d 1142 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
b7f05d4a 1143 wm_state->num_levels = dev_priv->wm.max_level + 1;
262cd2e1
VS		 1144
1145 wm_state->num_active_planes = 0;
262cd2e1 1146
54f1b6e1 1147 vlv_compute_fifo(crtc);
262cd2e1
VS		 1148
1149 if (wm_state->num_active_planes != 1)
1150 wm_state->cxsr = false;
1151
7c951c00 1152 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
262cd2e1
VS		 1153 struct intel_plane_state *state =
1154 to_intel_plane_state(plane->base.state);
1b31389c 1155 int level;
262cd2e1 1156
936e71e3 1157 if (!state->base.visible)
262cd2e1
VS		 1158 continue;
1159
1160 /* normal watermarks */
1161 for (level = 0; level < wm_state->num_levels; level++) {
e339d67e 1162 int wm = vlv_compute_wm_level(crtc->config, state, level);
1be4d379 1163 int max_wm = plane->wm.fifo_size;
262cd2e1
VS		 1164
1165 /* hack */
1166 if (WARN_ON(level == 0 && wm > max_wm))
1167 wm = max_wm;
1168
1be4d379 1169 if (wm > max_wm)
262cd2e1
VS		 1170 break;
1171
1b31389c 1172 wm_state->wm[level].plane[plane->id] = wm;
262cd2e1
VS		 1173 }
1174
1175 wm_state->num_levels = level;
1176
1177 if (!wm_state->cxsr)
1178 continue;
1179
1180 /* maxfifo watermarks */
1b31389c 1181 if (plane->id == PLANE_CURSOR) {
262cd2e1
VS		 1182 for (level = 0; level < wm_state->num_levels; level++)
1183 wm_state->sr[level].cursor =
1b31389c
VS		 1184 wm_state->wm[level].plane[PLANE_CURSOR];
1185 } else {
262cd2e1
VS		 1186 for (level = 0; level < wm_state->num_levels; level++)
1187 wm_state->sr[level].plane =
50a9dd3f 1188 max(wm_state->sr[level].plane,
1b31389c 1189 wm_state->wm[level].plane[plane->id]);
262cd2e1
VS		 1190 }
1191 }
1192
1193 /* clear any (partially) filled invalid levels */
b7f05d4a 1194 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
262cd2e1
VS		 1195 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1196 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1197 }
1198
1199 vlv_invert_wms(crtc);
1200}
1201
54f1b6e1
VS		 1202#define VLV_FIFO(plane, value) \
1203 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1204
1205static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1206{
1207 struct drm_device *dev = crtc->base.dev;
1208 struct drm_i915_private *dev_priv = to_i915(dev);
1209 struct intel_plane *plane;
1210 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1211
1212 for_each_intel_plane_on_crtc(dev, crtc, plane) {
49845a23
VS		 1213 switch (plane->id) {
1214 case PLANE_PRIMARY:
54f1b6e1 1215 sprite0_start = plane->wm.fifo_size;
49845a23
VS		 1216 break;
1217 case PLANE_SPRITE0:
54f1b6e1 1218 sprite1_start = sprite0_start + plane->wm.fifo_size;
49845a23
VS		 1219 break;
1220 case PLANE_SPRITE1:
54f1b6e1 1221 fifo_size = sprite1_start + plane->wm.fifo_size;
49845a23
VS		 1222 break;
1223 case PLANE_CURSOR:
1224 WARN_ON(plane->wm.fifo_size != 63);
1225 break;
1226 default:
1227 MISSING_CASE(plane->id);
1228 break;
1229 }
54f1b6e1
VS		 1230 }
1231
1232 WARN_ON(fifo_size != 512 - 1);
1233
1234 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1235 pipe_name(crtc->pipe), sprite0_start,
1236 sprite1_start, fifo_size);
1237
467a14d9
VS		 1238 spin_lock(&dev_priv->wm.dsparb_lock);
1239
54f1b6e1
VS		 1240 switch (crtc->pipe) {
1241 uint32_t dsparb, dsparb2, dsparb3;
1242 case PIPE_A:
1243 dsparb = I915_READ(DSPARB);
1244 dsparb2 = I915_READ(DSPARB2);
1245
1246 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1247 VLV_FIFO(SPRITEB, 0xff));
1248 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1249 VLV_FIFO(SPRITEB, sprite1_start));
1250
1251 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1252 VLV_FIFO(SPRITEB_HI, 0x1));
1253 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1254 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1255
1256 I915_WRITE(DSPARB, dsparb);
1257 I915_WRITE(DSPARB2, dsparb2);
1258 break;
1259 case PIPE_B:
1260 dsparb = I915_READ(DSPARB);
1261 dsparb2 = I915_READ(DSPARB2);
1262
1263 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1264 VLV_FIFO(SPRITED, 0xff));
1265 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1266 VLV_FIFO(SPRITED, sprite1_start));
1267
1268 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1269 VLV_FIFO(SPRITED_HI, 0xff));
1270 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1271 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1272
1273 I915_WRITE(DSPARB, dsparb);
1274 I915_WRITE(DSPARB2, dsparb2);
1275 break;
1276 case PIPE_C:
1277 dsparb3 = I915_READ(DSPARB3);
1278 dsparb2 = I915_READ(DSPARB2);
1279
1280 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1281 VLV_FIFO(SPRITEF, 0xff));
1282 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1283 VLV_FIFO(SPRITEF, sprite1_start));
1284
1285 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1286 VLV_FIFO(SPRITEF_HI, 0xff));
1287 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1288 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1289
1290 I915_WRITE(DSPARB3, dsparb3);
1291 I915_WRITE(DSPARB2, dsparb2);
1292 break;
1293 default:
1294 break;
1295 }
467a14d9
VS		 1296
1297 POSTING_READ(DSPARB);
1298
1299 spin_unlock(&dev_priv->wm.dsparb_lock);
54f1b6e1
VS		 1300}
1301
1302#undef VLV_FIFO
1303
7c951c00 1304static void vlv_merge_wm(struct drm_i915_private *dev_priv,
262cd2e1
VS		 1305 struct vlv_wm_values *wm)
1306{
1307 struct intel_crtc *crtc;
1308 int num_active_crtcs = 0;
1309
7c951c00 1310 wm->level = dev_priv->wm.max_level;
262cd2e1
VS		 1311 wm->cxsr = true;
1312
7c951c00 1313 for_each_intel_crtc(&dev_priv->drm, crtc) {
262cd2e1
VS		 1314 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 if (!wm_state->cxsr)
1320 wm->cxsr = false;
1321
1322 num_active_crtcs++;
1323 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1324 }
1325
1326 if (num_active_crtcs != 1)
1327 wm->cxsr = false;
1328
6f9c784b
VS		 1329 if (num_active_crtcs > 1)
1330 wm->level = VLV_WM_LEVEL_PM2;
1331
7c951c00 1332 for_each_intel_crtc(&dev_priv->drm, crtc) {
262cd2e1
VS		 1333 struct vlv_wm_state *wm_state = &crtc->wm_state;
1334 enum pipe pipe = crtc->pipe;
1335
1336 if (!crtc->active)
1337 continue;
1338
1339 wm->pipe[pipe] = wm_state->wm[wm->level];
1340 if (wm->cxsr)
1341 wm->sr = wm_state->sr[wm->level];
1342
1b31389c
VS		 1343 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1344 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1345 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1346 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
262cd2e1
VS		 1347 }
1348}
1349
fa292a4b
VS		 1350static bool is_disabling(int old, int new, int threshold)
1351{
1352 return old >= threshold && new < threshold;
1353}
1354
1355static bool is_enabling(int old, int new, int threshold)
1356{
1357 return old < threshold && new >= threshold;
1358}
1359
432081bc 1360static void vlv_update_wm(struct intel_crtc *crtc)
262cd2e1 1361{
7c951c00 1362 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
432081bc 1363 enum pipe pipe = crtc->pipe;
fa292a4b
VS		 1364 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
1365 struct vlv_wm_values new_wm = {};
262cd2e1 1366
432081bc 1367 vlv_compute_wm(crtc);
fa292a4b 1368 vlv_merge_wm(dev_priv, &new_wm);
262cd2e1 1369
fa292a4b 1370 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
54f1b6e1 1371 /* FIXME should be part of crtc atomic commit */
432081bc 1372 vlv_pipe_set_fifo_size(crtc);
fa292a4b 1373
262cd2e1 1374 return;
54f1b6e1 1375 }
262cd2e1 1376
fa292a4b 1377 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
262cd2e1
VS		 1378 chv_set_memory_dvfs(dev_priv, false);
1379
fa292a4b 1380 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
262cd2e1
VS		 1381 chv_set_memory_pm5(dev_priv, false);
1382
fa292a4b 1383 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
3d90e649 1384 _intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1385
54f1b6e1 1386 /* FIXME should be part of crtc atomic commit */
432081bc 1387 vlv_pipe_set_fifo_size(crtc);
54f1b6e1 1388
fa292a4b 1389 vlv_write_wm_values(dev_priv, &new_wm);
262cd2e1
VS		 1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
fa292a4b
VS		 1393 pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
1394 new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
1395 new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
262cd2e1 1396
fa292a4b 1397 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
3d90e649 1398 _intel_set_memory_cxsr(dev_priv, true);
262cd2e1 1399
fa292a4b 1400 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
262cd2e1
VS		 1401 chv_set_memory_pm5(dev_priv, true);
1402
fa292a4b 1403 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
262cd2e1
VS		 1404 chv_set_memory_dvfs(dev_priv, true);
1405
fa292a4b 1406 *old_wm = new_wm;
3c2777fd
VS		 1407}
1408
ae80152d
VS		 1409#define single_plane_enabled(mask) is_power_of_2(mask)
1410
432081bc 1411static void g4x_update_wm(struct intel_crtc *crtc)
b445e3b0 1412{
b91eb5cc 1413 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0 1414 static const int sr_latency_ns = 12000;
b445e3b0
ED		 1415 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1416 int plane_sr, cursor_sr;
1417 unsigned int enabled = 0;
9858425c 1418 bool cxsr_enabled;
b445e3b0 1419
f0ce2310 1420 if (g4x_compute_wm0(dev_priv, PIPE_A,
5aef6003
CW		 1421 &g4x_wm_info, pessimal_latency_ns,
1422 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1423 &planea_wm, &cursora_wm))
51cea1f4 1424 enabled |= 1 << PIPE_A;
b445e3b0 1425
f0ce2310 1426 if (g4x_compute_wm0(dev_priv, PIPE_B,
5aef6003
CW		 1427 &g4x_wm_info, pessimal_latency_ns,
1428 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1429 &planeb_wm, &cursorb_wm))
51cea1f4 1430 enabled |= 1 << PIPE_B;
b445e3b0 1431
b445e3b0 1432 if (single_plane_enabled(enabled) &&
f0ce2310 1433 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
b445e3b0
ED		 1434 sr_latency_ns,
1435 &g4x_wm_info,
1436 &g4x_cursor_wm_info,
52bd02d8 1437 &plane_sr, &cursor_sr)) {
9858425c 1438 cxsr_enabled = true;
52bd02d8 1439 } else {
9858425c 1440 cxsr_enabled = false;
5209b1f4 1441 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1442 plane_sr = cursor_sr = 0;
1443 }
b445e3b0 1444
a5043453
VS		 1445 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1446 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1447 planea_wm, cursora_wm,
1448 planeb_wm, cursorb_wm,
1449 plane_sr, cursor_sr);
1450
1451 I915_WRITE(DSPFW1,
f4998963
VS		 1452 FW_WM(plane_sr, SR) |
1453 FW_WM(cursorb_wm, CURSORB) |
1454 FW_WM(planeb_wm, PLANEB) |
1455 FW_WM(planea_wm, PLANEA));
b445e3b0 1456 I915_WRITE(DSPFW2,
8c919b28 1457 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1458 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1459 /* HPLL off in SR has some issues on G4x... disable it */
1460 I915_WRITE(DSPFW3,
8c919b28 1461 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1462 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1463
1464 if (cxsr_enabled)
1465 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1466}
1467
432081bc 1468static void i965_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1469{
ffc7a76b 1470 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1471 struct intel_crtc *crtc;
b445e3b0
ED		 1472 int srwm = 1;
1473 int cursor_sr = 16;
9858425c 1474 bool cxsr_enabled;
b445e3b0
ED		 1475
1476 /* Calc sr entries for one plane configs */
ffc7a76b 1477 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1478 if (crtc) {
1479 /* self-refresh has much higher latency */
1480 static const int sr_latency_ns = 12000;
efc2611e
VS		 1481 const struct drm_display_mode *adjusted_mode =
1482 &crtc->config->base.adjusted_mode;
1483 const struct drm_framebuffer *fb =
1484 crtc->base.primary->state->fb;
241bfc38 1485 int clock = adjusted_mode->crtc_clock;
fec8cba3 1486 int htotal = adjusted_mode->crtc_htotal;
efc2611e 1487 int hdisplay = crtc->config->pipe_src_w;
353c8598 1488 int cpp = fb->format->cpp[0];
b445e3b0
ED		 1489 unsigned long line_time_us;
1490 int entries;
1491
922044c9 1492 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1493
1494 /* Use ns/us then divide to preserve precision */
1495 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1496 cpp * hdisplay;
b445e3b0
ED		 1497 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1498 srwm = I965_FIFO_SIZE - entries;
1499 if (srwm < 0)
1500 srwm = 1;
1501 srwm &= 0x1ff;
1502 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1503 entries, srwm);
1504
1505 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
efc2611e 1506 cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 1507 entries = DIV_ROUND_UP(entries,
1508 i965_cursor_wm_info.cacheline_size);
1509 cursor_sr = i965_cursor_wm_info.fifo_size -
1510 (entries + i965_cursor_wm_info.guard_size);
1511
1512 if (cursor_sr > i965_cursor_wm_info.max_wm)
1513 cursor_sr = i965_cursor_wm_info.max_wm;
1514
1515 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1516 "cursor %d\n", srwm, cursor_sr);
1517
9858425c 1518 cxsr_enabled = true;
b445e3b0 1519 } else {
9858425c 1520 cxsr_enabled = false;
b445e3b0 1521 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1522 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1523 }
1524
1525 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1526 srwm);
1527
1528 /* 965 has limitations... */
f4998963
VS		 1529 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1530 FW_WM(8, CURSORB) |
1531 FW_WM(8, PLANEB) |
1532 FW_WM(8, PLANEA));
1533 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1534 FW_WM(8, PLANEC_OLD));
b445e3b0 1535 /* update cursor SR watermark */
f4998963 1536 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1537
1538 if (cxsr_enabled)
1539 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1540}
1541
f4998963
VS		 1542#undef FW_WM
1543
432081bc 1544static void i9xx_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1545{
ffc7a76b 1546 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
b445e3b0
ED		 1547 const struct intel_watermark_params *wm_info;
1548 uint32_t fwater_lo;
1549 uint32_t fwater_hi;
1550 int cwm, srwm = 1;
1551 int fifo_size;
1552 int planea_wm, planeb_wm;
efc2611e 1553 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 1554
a9097be4 1555 if (IS_I945GM(dev_priv))
b445e3b0 1556 wm_info = &i945_wm_info;
5db94019 1557 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1558 wm_info = &i915_wm_info;
1559 else
9d539105 1560 wm_info = &i830_a_wm_info;
b445e3b0 1561
ef0f5e93 1562 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
b91eb5cc 1563 crtc = intel_get_crtc_for_plane(dev_priv, 0);
efc2611e
VS		 1564 if (intel_crtc_active(crtc)) {
1565 const struct drm_display_mode *adjusted_mode =
1566 &crtc->config->base.adjusted_mode;
1567 const struct drm_framebuffer *fb =
1568 crtc->base.primary->state->fb;
1569 int cpp;
1570
5db94019 1571 if (IS_GEN2(dev_priv))
b9e0bda3 1572 cpp = 4;
efc2611e 1573 else
353c8598 1574 cpp = fb->format->cpp[0];
b9e0bda3 1575
241bfc38 1576 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1577 wm_info, fifo_size, cpp,
5aef6003 1578 pessimal_latency_ns);
b445e3b0 1579 enabled = crtc;
9d539105 1580 } else {
b445e3b0 1581 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1582 if (planea_wm > (long)wm_info->max_wm)
1583 planea_wm = wm_info->max_wm;
1584 }
1585
5db94019 1586 if (IS_GEN2(dev_priv))
9d539105 1587 wm_info = &i830_bc_wm_info;
b445e3b0 1588
ef0f5e93 1589 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
b91eb5cc 1590 crtc = intel_get_crtc_for_plane(dev_priv, 1);
efc2611e
VS		 1591 if (intel_crtc_active(crtc)) {
1592 const struct drm_display_mode *adjusted_mode =
1593 &crtc->config->base.adjusted_mode;
1594 const struct drm_framebuffer *fb =
1595 crtc->base.primary->state->fb;
1596 int cpp;
1597
5db94019 1598 if (IS_GEN2(dev_priv))
b9e0bda3 1599 cpp = 4;
efc2611e 1600 else
353c8598 1601 cpp = fb->format->cpp[0];
b9e0bda3 1602
241bfc38 1603 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1604 wm_info, fifo_size, cpp,
5aef6003 1605 pessimal_latency_ns);
b445e3b0
ED		 1606 if (enabled == NULL)
1607 enabled = crtc;
1608 else
1609 enabled = NULL;
9d539105 1610 } else {
b445e3b0 1611 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1612 if (planeb_wm > (long)wm_info->max_wm)
1613 planeb_wm = wm_info->max_wm;
1614 }
b445e3b0
ED		 1615
1616 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1617
50a0bc90 1618 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1619 struct drm_i915_gem_object *obj;
2ab1bc9d 1620
efc2611e 1621 obj = intel_fb_obj(enabled->base.primary->state->fb);
2ab1bc9d
DV		 1622
1623 /* self-refresh seems busted with untiled */
3e510a8e 1624 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1625 enabled = NULL;
1626 }
1627
b445e3b0
ED		 1628 /*
1629 * Overlay gets an aggressive default since video jitter is bad.
1630 */
1631 cwm = 2;
1632
1633 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1634 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1635
1636 /* Calc sr entries for one plane configs */
03427fcb 1637 if (HAS_FW_BLC(dev_priv) && enabled) {
b445e3b0
ED		 1638 /* self-refresh has much higher latency */
1639 static const int sr_latency_ns = 6000;
efc2611e
VS		 1640 const struct drm_display_mode *adjusted_mode =
1641 &enabled->config->base.adjusted_mode;
1642 const struct drm_framebuffer *fb =
1643 enabled->base.primary->state->fb;
241bfc38 1644 int clock = adjusted_mode->crtc_clock;
fec8cba3 1645 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1646 int hdisplay = enabled->config->pipe_src_w;
1647 int cpp;
b445e3b0
ED		 1648 unsigned long line_time_us;
1649 int entries;
1650
50a0bc90 1651 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056 1652 cpp = 4;
efc2611e 1653 else
353c8598 1654 cpp = fb->format->cpp[0];
2d1b5056 1655
922044c9 1656 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1657
1658 /* Use ns/us then divide to preserve precision */
1659 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1660 cpp * hdisplay;
b445e3b0
ED		 1661 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1662 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1663 srwm = wm_info->fifo_size - entries;
1664 if (srwm < 0)
1665 srwm = 1;
1666
50a0bc90 1667 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1668 I915_WRITE(FW_BLC_SELF,
1669 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1670 else
b445e3b0
ED		 1671 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1672 }
1673
1674 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1675 planea_wm, planeb_wm, cwm, srwm);
1676
1677 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1678 fwater_hi = (cwm & 0x1f);
1679
1680 /* Set request length to 8 cachelines per fetch */
1681 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1682 fwater_hi = fwater_hi | (1 << 8);
1683
1684 I915_WRITE(FW_BLC, fwater_lo);
1685 I915_WRITE(FW_BLC2, fwater_hi);
1686
5209b1f4
ID		 1687 if (enabled)
1688 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1689}
1690
432081bc 1691static void i845_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1692{
ffc7a76b 1693 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1694 struct intel_crtc *crtc;
241bfc38 1695 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1696 uint32_t fwater_lo;
1697 int planea_wm;
1698
ffc7a76b 1699 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1700 if (crtc == NULL)
1701 return;
1702
efc2611e 1703 adjusted_mode = &crtc->config->base.adjusted_mode;
241bfc38 1704 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1705 &i845_wm_info,
ef0f5e93 1706 dev_priv->display.get_fifo_size(dev_priv, 0),
5aef6003 1707 4, pessimal_latency_ns);
b445e3b0
ED		 1708 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1709 fwater_lo |= (3<<8) | planea_wm;
1710
1711 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1712
1713 I915_WRITE(FW_BLC, fwater_lo);
1714}
1715
37126462 1716/* latency must be in 0.1us units. */
ac484963 1717static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1718{
1719 uint64_t ret;
1720
3312ba65
VS		 1721 if (WARN(latency == 0, "Latency value missing\n"))
1722 return UINT_MAX;
1723
ac484963 1724 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1725 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1726
1727 return ret;
1728}
1729
37126462 1730/* latency must be in 0.1us units. */
23297044 1731static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1732 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1733 uint32_t latency)
1734{
1735 uint32_t ret;
1736
3312ba65
VS		 1737 if (WARN(latency == 0, "Latency value missing\n"))
1738 return UINT_MAX;
15126882
MR		 1739 if (WARN_ON(!pipe_htotal))
1740 return UINT_MAX;
3312ba65 1741
801bcfff 1742 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1743 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1744 ret = DIV_ROUND_UP(ret, 64) + 2;
1745 return ret;
1746}
1747
23297044 1748static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1749 uint8_t cpp)
cca32e9a 1750{
15126882
MR		 1751 /*
1752 * Neither of these should be possible since this function shouldn't be
1753 * called if the CRTC is off or the plane is invisible. But let's be
1754 * extra paranoid to avoid a potential divide-by-zero if we screw up
1755 * elsewhere in the driver.
1756 */
ac484963 1757 if (WARN_ON(!cpp))
15126882
MR		 1758 return 0;
1759 if (WARN_ON(!horiz_pixels))
1760 return 0;
1761
ac484963 1762 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1763}
1764
820c1980 1765struct ilk_wm_maximums {
cca32e9a
PZ		 1766 uint16_t pri;
1767 uint16_t spr;
1768 uint16_t cur;
1769 uint16_t fbc;
1770};
1771
37126462
VS		 1772/*
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1775 */
7221fc33 1776static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1777 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1778 uint32_t mem_value,
1779 bool is_lp)
801bcfff 1780{
cca32e9a 1781 uint32_t method1, method2;
8305494e 1782 int cpp;
cca32e9a 1783
936e71e3 1784 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1785 return 0;
1786
353c8598 1787 cpp = pstate->base.fb->format->cpp[0];
8305494e 1788
a7d1b3f4 1789 method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
cca32e9a
PZ		 1790
1791 if (!is_lp)
1792 return method1;
1793
a7d1b3f4 1794 method2 = ilk_wm_method2(cstate->pixel_rate,
7221fc33 1795 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1796 drm_rect_width(&pstate->base.dst),
ac484963 1797 cpp, mem_value);
cca32e9a
PZ		 1798
1799 return min(method1, method2);
801bcfff
PZ		 1800}
1801
37126462
VS		 1802/*
1803 * For both WM_PIPE and WM_LP.
1804 * mem_value must be in 0.1us units.
1805 */
7221fc33 1806static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1807 const struct intel_plane_state *pstate,
801bcfff
PZ		 1808 uint32_t mem_value)
1809{
1810 uint32_t method1, method2;
8305494e 1811 int cpp;
801bcfff 1812
936e71e3 1813 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1814 return 0;
1815
353c8598 1816 cpp = pstate->base.fb->format->cpp[0];
8305494e 1817
a7d1b3f4
VS		 1818 method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
1819 method2 = ilk_wm_method2(cstate->pixel_rate,
7221fc33 1820 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1821 drm_rect_width(&pstate->base.dst),
ac484963 1822 cpp, mem_value);
801bcfff
PZ		 1823 return min(method1, method2);
1824}
1825
37126462
VS		 1826/*
1827 * For both WM_PIPE and WM_LP.
1828 * mem_value must be in 0.1us units.
1829 */
7221fc33 1830static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1831 const struct intel_plane_state *pstate,
801bcfff
PZ		 1832 uint32_t mem_value)
1833{
b2435692
MR		 1834 /*
1835 * We treat the cursor plane as always-on for the purposes of watermark
1836 * calculation. Until we have two-stage watermark programming merged,
1837 * this is necessary to avoid flickering.
1838 */
1839 int cpp = 4;
936e71e3 1840 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1841
b2435692 1842 if (!cstate->base.active)
801bcfff
PZ		 1843 return 0;
1844
a7d1b3f4 1845 return ilk_wm_method2(cstate->pixel_rate,
7221fc33 1846 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1847 width, cpp, mem_value);
801bcfff
PZ		 1848}
1849
cca32e9a 1850/* Only for WM_LP. */
7221fc33 1851static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1852 const struct intel_plane_state *pstate,
1fda9882 1853 uint32_t pri_val)
cca32e9a 1854{
8305494e 1855 int cpp;
43d59eda 1856
936e71e3 1857 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1858 return 0;
1859
353c8598 1860 cpp = pstate->base.fb->format->cpp[0];
8305494e 1861
936e71e3 1862 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1863}
1864
175fded1
TU		 1865static unsigned int
1866ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
158ae64f 1867{
175fded1 1868 if (INTEL_GEN(dev_priv) >= 8)
416f4727 1869 return 3072;
175fded1 1870 else if (INTEL_GEN(dev_priv) >= 7)
158ae64f
VS		 1871 return 768;
1872 else
1873 return 512;
1874}
1875
175fded1
TU		 1876static unsigned int
1877ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1878 int level, bool is_sprite)
4e975081 1879{
175fded1 1880 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1881 /* BDW primary/sprite plane watermarks */
1882 return level == 0 ? 255 : 2047;
175fded1 1883 else if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1884 /* IVB/HSW primary/sprite plane watermarks */
1885 return level == 0 ? 127 : 1023;
1886 else if (!is_sprite)
1887 /* ILK/SNB primary plane watermarks */
1888 return level == 0 ? 127 : 511;
1889 else
1890 /* ILK/SNB sprite plane watermarks */
1891 return level == 0 ? 63 : 255;
1892}
1893
175fded1
TU		 1894static unsigned int
1895ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
4e975081 1896{
175fded1 1897 if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1898 return level == 0 ? 63 : 255;
1899 else
1900 return level == 0 ? 31 : 63;
1901}
1902
175fded1 1903static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
4e975081 1904{
175fded1 1905 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1906 return 31;
1907 else
1908 return 15;
1909}
1910
158ae64f
VS		 1911/* Calculate the maximum primary/sprite plane watermark */
1912static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1913 int level,
240264f4 1914 const struct intel_wm_config *config,
158ae64f
VS		 1915 enum intel_ddb_partitioning ddb_partitioning,
1916 bool is_sprite)
1917{
175fded1
TU		 1918 struct drm_i915_private *dev_priv = to_i915(dev);
1919 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
158ae64f
VS		 1920
1921 /* if sprites aren't enabled, sprites get nothing */
240264f4 1922 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1923 return 0;
1924
1925 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1926 if (level == 0 || config->num_pipes_active > 1) {
175fded1 1927 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
158ae64f
VS		 1928
1929 /*
1930 * For some reason the non self refresh
1931 * FIFO size is only half of the self
1932 * refresh FIFO size on ILK/SNB.
1933 */
175fded1 1934 if (INTEL_GEN(dev_priv) <= 6)
158ae64f
VS		 1935 fifo_size /= 2;
1936 }
1937
240264f4 1938 if (config->sprites_enabled) {
158ae64f
VS		 1939 /* level 0 is always calculated with 1:1 split */
1940 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1941 if (is_sprite)
1942 fifo_size *= 5;
1943 fifo_size /= 6;
1944 } else {
1945 fifo_size /= 2;
1946 }
1947 }
1948
1949 /* clamp to max that the registers can hold */
175fded1 1950 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
158ae64f
VS		 1951}
1952
1953/* Calculate the maximum cursor plane watermark */
1954static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1955 int level,
1956 const struct intel_wm_config *config)
158ae64f
VS		 1957{
1958 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1959 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1960 return 64;
1961
1962 /* otherwise just report max that registers can hold */
175fded1 1963 return ilk_cursor_wm_reg_max(to_i915(dev), level);
158ae64f
VS		 1964}
1965
d34ff9c6 1966static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1967 int level,
1968 const struct intel_wm_config *config,
1969 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1970 struct ilk_wm_maximums *max)
158ae64f 1971{
240264f4
VS		 1972 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1973 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1974 max->cur = ilk_cursor_wm_max(dev, level, config);
175fded1 1975 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
158ae64f
VS		 1976}
1977
175fded1 1978static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
a3cb4048
VS		 1979 int level,
1980 struct ilk_wm_maximums *max)
1981{
175fded1
TU		 1982 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1983 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1984 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1985 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
a3cb4048
VS		 1986}
1987
d9395655 1988static bool ilk_validate_wm_level(int level,
820c1980 1989 const struct ilk_wm_maximums *max,
d9395655 1990 struct intel_wm_level *result)
a9786a11
VS		 1991{
1992 bool ret;
1993
1994 /* already determined to be invalid? */
1995 if (!result->enable)
1996 return false;
1997
1998 result->enable = result->pri_val <= max->pri &&
1999 result->spr_val <= max->spr &&
2000 result->cur_val <= max->cur;
2001
2002 ret = result->enable;
2003
2004 /*
2005 * HACK until we can pre-compute everything,
2006 * and thus fail gracefully if LP0 watermarks
2007 * are exceeded...
2008 */
2009 if (level == 0 && !result->enable) {
2010 if (result->pri_val > max->pri)
2011 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2012 level, result->pri_val, max->pri);
2013 if (result->spr_val > max->spr)
2014 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2015 level, result->spr_val, max->spr);
2016 if (result->cur_val > max->cur)
2017 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2018 level, result->cur_val, max->cur);
2019
2020 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2021 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2022 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2023 result->enable = true;
2024 }
2025
a9786a11
VS		 2026 return ret;
2027}
2028
d34ff9c6 2029static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2030 const struct intel_crtc *intel_crtc,
6f5ddd17 2031 int level,
7221fc33 2032 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2033 struct intel_plane_state *pristate,
2034 struct intel_plane_state *sprstate,
2035 struct intel_plane_state *curstate,
1fd527cc 2036 struct intel_wm_level *result)
6f5ddd17
VS		 2037{
2038 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2039 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2040 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2041
2042 /* WM1+ latency values stored in 0.5us units */
2043 if (level > 0) {
2044 pri_latency *= 5;
2045 spr_latency *= 5;
2046 cur_latency *= 5;
2047 }
2048
e3bddded
ML		 2049 if (pristate) {
2050 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2051 pri_latency, level);
2052 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2053 }
2054
2055 if (sprstate)
2056 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2057
2058 if (curstate)
2059 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2060
6f5ddd17
VS		 2061 result->enable = true;
2062}
2063
801bcfff 2064static uint32_t
532f7a7f 2065hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2066{
532f7a7f
VS		 2067 const struct intel_atomic_state *intel_state =
2068 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2069 const struct drm_display_mode *adjusted_mode =
2070 &cstate->base.adjusted_mode;
85a02deb 2071 u32 linetime, ips_linetime;
1f8eeabf 2072
ee91a159
MR		 2073 if (!cstate->base.active)
2074 return 0;
2075 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2076 return 0;
bb0f4aab 2077 if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
801bcfff 2078 return 0;
1011d8c4 2079
1f8eeabf
ED		 2080 /* The WM are computed with base on how long it takes to fill a single
2081 * row at the given clock rate, multiplied by 8.
2082 * */
124abe07
VS		 2083 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2084 adjusted_mode->crtc_clock);
2085 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
bb0f4aab 2086 intel_state->cdclk.logical.cdclk);
1f8eeabf 2087
801bcfff
PZ		 2088 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2089 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2090}
2091
bb726519
VS		 2092static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2093 uint16_t wm[8])
12b134df 2094{
5db94019 2095 if (IS_GEN9(dev_priv)) {
2af30a5c 2096 uint32_t val;
4f947386 2097 int ret, i;
5db94019 2098 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2099
2100 /* read the first set of memory latencies[0:3] */
2101 val = 0; /* data0 to be programmed to 0 for first set */
2102 mutex_lock(&dev_priv->rps.hw_lock);
2103 ret = sandybridge_pcode_read(dev_priv,
2104 GEN9_PCODE_READ_MEM_LATENCY,
2105 &val);
2106 mutex_unlock(&dev_priv->rps.hw_lock);
2107
2108 if (ret) {
2109 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2110 return;
2111 }
2112
2113 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2117 GEN9_MEM_LATENCY_LEVEL_MASK;
2118 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK;
2120
2121 /* read the second set of memory latencies[4:7] */
2122 val = 1; /* data0 to be programmed to 1 for second set */
2123 mutex_lock(&dev_priv->rps.hw_lock);
2124 ret = sandybridge_pcode_read(dev_priv,
2125 GEN9_PCODE_READ_MEM_LATENCY,
2126 &val);
2127 mutex_unlock(&dev_priv->rps.hw_lock);
2128 if (ret) {
2129 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2130 return;
2131 }
2132
2133 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2134 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2135 GEN9_MEM_LATENCY_LEVEL_MASK;
2136 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2137 GEN9_MEM_LATENCY_LEVEL_MASK;
2138 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2139 GEN9_MEM_LATENCY_LEVEL_MASK;
2140
0727e40a
PZ		 2141 /*
2142 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2143 * need to be disabled. We make sure to sanitize the values out
2144 * of the punit to satisfy this requirement.
2145 */
2146 for (level = 1; level <= max_level; level++) {
2147 if (wm[level] == 0) {
2148 for (i = level + 1; i <= max_level; i++)
2149 wm[i] = 0;
2150 break;
2151 }
2152 }
2153
367294be 2154 /*
9fb5026f 2155 * WaWmMemoryReadLatency:skl,glk
6f97235b 2156 *
367294be 2157 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2158 * to add 2us to the various latency levels we retrieve from the
2159 * punit when level 0 response data us 0us.
367294be 2160 */
0727e40a
PZ		 2161 if (wm[0] == 0) {
2162 wm[0] += 2;
2163 for (level = 1; level <= max_level; level++) {
2164 if (wm[level] == 0)
2165 break;
367294be 2166 wm[level] += 2;
4f947386 2167 }
0727e40a
PZ		 2168 }
2169
8652744b 2170 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2171 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> 56) & 0xFF;
2174 if (wm[0] == 0)
2175 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2176 wm[1] = (sskpd >> 4) & 0xFF;
2177 wm[2] = (sskpd >> 12) & 0xFF;
2178 wm[3] = (sskpd >> 20) & 0x1FF;
2179 wm[4] = (sskpd >> 32) & 0x1FF;
bb726519 2180 } else if (INTEL_GEN(dev_priv) >= 6) {
63cf9a13
VS		 2181 uint32_t sskpd = I915_READ(MCH_SSKPD);
2182
2183 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2184 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2185 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2186 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
bb726519 2187 } else if (INTEL_GEN(dev_priv) >= 5) {
3a88d0ac
VS		 2188 uint32_t mltr = I915_READ(MLTR_ILK);
2189
2190 /* ILK primary LP0 latency is 700 ns */
2191 wm[0] = 7;
2192 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2193 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2194 }
2195}
2196
5db94019
TU		 2197static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2198 uint16_t wm[5])
53615a5e
VS		 2199{
2200 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2201 if (IS_GEN5(dev_priv))
53615a5e
VS		 2202 wm[0] = 13;
2203}
2204
fd6b8f43
TU		 2205static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2206 uint16_t wm[5])
53615a5e
VS		 2207{
2208 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2209 if (IS_GEN5(dev_priv))
53615a5e
VS		 2210 wm[0] = 13;
2211
2212 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2213 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2214 wm[3] *= 2;
2215}
2216
5db94019 2217int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2218{
26ec971e 2219 /* how many WM levels are we expecting */
8652744b 2220 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2221 return 7;
8652744b 2222 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2223 return 4;
8652744b 2224 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2225 return 3;
26ec971e 2226 else
ad0d6dc4
VS		 2227 return 2;
2228}
7526ed79 2229
5db94019 2230static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2231 const char *name,
2af30a5c 2232 const uint16_t wm[8])
ad0d6dc4 2233{
5db94019 2234 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2235
2236 for (level = 0; level <= max_level; level++) {
2237 unsigned int latency = wm[level];
2238
2239 if (latency == 0) {
2240 DRM_ERROR("%s WM%d latency not provided\n",
2241 name, level);
2242 continue;
2243 }
2244
2af30a5c
PB		 2245 /*
2246 * - latencies are in us on gen9.
2247 * - before then, WM1+ latency values are in 0.5us units
2248 */
5db94019 2249 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2250 latency *= 10;
2251 else if (level > 0)
26ec971e
VS		 2252 latency *= 5;
2253
2254 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2255 name, level, wm[level],
2256 latency / 10, latency % 10);
2257 }
2258}
2259
e95a2f75
VS		 2260static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2261 uint16_t wm[5], uint16_t min)
2262{
5db94019 2263 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2264
2265 if (wm[0] >= min)
2266 return false;
2267
2268 wm[0] = max(wm[0], min);
2269 for (level = 1; level <= max_level; level++)
2270 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2271
2272 return true;
2273}
2274
bb726519 2275static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
e95a2f75 2276{
e95a2f75
VS		 2277 bool changed;
2278
2279 /*
2280 * The BIOS provided WM memory latency values are often
2281 * inadequate for high resolution displays. Adjust them.
2282 */
2283 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2284 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2285 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2286
2287 if (!changed)
2288 return;
2289
2290 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2291 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2292 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2293 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2294}
2295
bb726519 2296static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
53615a5e 2297{
bb726519 2298 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
53615a5e
VS		 2299
2300 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2301 sizeof(dev_priv->wm.pri_latency));
2302 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2303 sizeof(dev_priv->wm.pri_latency));
2304
5db94019 2305 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2306 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2307
5db94019
TU		 2308 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2309 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2310 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2311
5db94019 2312 if (IS_GEN6(dev_priv))
bb726519 2313 snb_wm_latency_quirk(dev_priv);
53615a5e
VS		 2314}
2315
bb726519 2316static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2af30a5c 2317{
bb726519 2318 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
5db94019 2319 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2320}
2321
ed4a6a7c
MR		 2322static bool ilk_validate_pipe_wm(struct drm_device *dev,
2323 struct intel_pipe_wm *pipe_wm)
2324{
2325 /* LP0 watermark maximums depend on this pipe alone */
2326 const struct intel_wm_config config = {
2327 .num_pipes_active = 1,
2328 .sprites_enabled = pipe_wm->sprites_enabled,
2329 .sprites_scaled = pipe_wm->sprites_scaled,
2330 };
2331 struct ilk_wm_maximums max;
2332
2333 /* LP0 watermarks always use 1/2 DDB partitioning */
2334 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2335
2336 /* At least LP0 must be valid */
2337 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2338 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2339 return false;
2340 }
2341
2342 return true;
2343}
2344
0b2ae6d7 2345/* Compute new watermarks for the pipe */
e3bddded 2346static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2347{
e3bddded
ML		 2348 struct drm_atomic_state *state = cstate->base.state;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2350 struct intel_pipe_wm *pipe_wm;
e3bddded 2351 struct drm_device *dev = state->dev;
fac5e23e 2352 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2353 struct intel_plane *intel_plane;
86c8bbbe 2354 struct intel_plane_state *pristate = NULL;
43d59eda 2355 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2356 struct intel_plane_state *curstate = NULL;
5db94019 2357 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2358 struct ilk_wm_maximums max;
0b2ae6d7 2359
e8f1f02e 2360 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2361
43d59eda 2362 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2363 struct intel_plane_state *ps;
2364
2365 ps = intel_atomic_get_existing_plane_state(state,
2366 intel_plane);
2367 if (!ps)
2368 continue;
86c8bbbe
MR		 2369
2370 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2371 pristate = ps;
86c8bbbe 2372 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2373 sprstate = ps;
86c8bbbe 2374 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2375 curstate = ps;
43d59eda
MR		 2376 }
2377
ed4a6a7c 2378 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2379 if (sprstate) {
936e71e3
VS		 2380 pipe_wm->sprites_enabled = sprstate->base.visible;
2381 pipe_wm->sprites_scaled = sprstate->base.visible &&
2382 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2383 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2384 }
2385
d81f04c5
ML		 2386 usable_level = max_level;
2387
7b39a0b7 2388 /* ILK/SNB: LP2+ watermarks only w/o sprites */
175fded1 2389 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2390 usable_level = 1;
7b39a0b7
VS		 2391
2392 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2393 if (pipe_wm->sprites_scaled)
d81f04c5 2394 usable_level = 0;
7b39a0b7 2395
86c8bbbe 2396 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2397 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2398
2399 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2400 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2401
8652744b 2402 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2403 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2404
ed4a6a7c 2405 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2406 return -EINVAL;
a3cb4048 2407
175fded1 2408 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
a3cb4048
VS		 2409
2410 for (level = 1; level <= max_level; level++) {
71f0a626 2411 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2412
86c8bbbe 2413 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2414 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2415
2416 /*
2417 * Disable any watermark level that exceeds the
2418 * register maximums since such watermarks are
2419 * always invalid.
2420 */
71f0a626
ML		 2421 if (level > usable_level)
2422 continue;
2423
2424 if (ilk_validate_wm_level(level, &max, wm))
2425 pipe_wm->wm[level] = *wm;
2426 else
d81f04c5 2427 usable_level = level;
a3cb4048
VS		 2428 }
2429
86c8bbbe 2430 return 0;
0b2ae6d7
VS		 2431}
2432
ed4a6a7c
MR		 2433/*
2434 * Build a set of 'intermediate' watermark values that satisfy both the old
2435 * state and the new state. These can be programmed to the hardware
2436 * immediately.
2437 */
2438static int ilk_compute_intermediate_wm(struct drm_device *dev,
2439 struct intel_crtc *intel_crtc,
2440 struct intel_crtc_state *newstate)
2441{
e8f1f02e 2442 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2443 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2444 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2445
2446 /*
2447 * Start with the final, target watermarks, then combine with the
2448 * currently active watermarks to get values that are safe both before
2449 * and after the vblank.
2450 */
e8f1f02e 2451 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2452 a->pipe_enabled |= b->pipe_enabled;
2453 a->sprites_enabled |= b->sprites_enabled;
2454 a->sprites_scaled |= b->sprites_scaled;
2455
2456 for (level = 0; level <= max_level; level++) {
2457 struct intel_wm_level *a_wm = &a->wm[level];
2458 const struct intel_wm_level *b_wm = &b->wm[level];
2459
2460 a_wm->enable &= b_wm->enable;
2461 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2462 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2463 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2464 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2465 }
2466
2467 /*
2468 * We need to make sure that these merged watermark values are
2469 * actually a valid configuration themselves. If they're not,
2470 * there's no safe way to transition from the old state to
2471 * the new state, so we need to fail the atomic transaction.
2472 */
2473 if (!ilk_validate_pipe_wm(dev, a))
2474 return -EINVAL;
2475
2476 /*
2477 * If our intermediate WM are identical to the final WM, then we can
2478 * omit the post-vblank programming; only update if it's different.
2479 */
e8f1f02e 2480 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2481 newstate->wm.need_postvbl_update = false;
2482
2483 return 0;
2484}
2485
0b2ae6d7
VS		 2486/*
2487 * Merge the watermarks from all active pipes for a specific level.
2488 */
2489static void ilk_merge_wm_level(struct drm_device *dev,
2490 int level,
2491 struct intel_wm_level *ret_wm)
2492{
2493 const struct intel_crtc *intel_crtc;
2494
d52fea5b
VS		 2495 ret_wm->enable = true;
2496
d3fcc808 2497 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2498 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2499 const struct intel_wm_level *wm = &active->wm[level];
2500
2501 if (!active->pipe_enabled)
2502 continue;
0b2ae6d7 2503
d52fea5b
VS		 2504 /*
2505 * The watermark values may have been used in the past,
2506 * so we must maintain them in the registers for some
2507 * time even if the level is now disabled.
2508 */
0b2ae6d7 2509 if (!wm->enable)
d52fea5b 2510 ret_wm->enable = false;
0b2ae6d7
VS		 2511
2512 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2513 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2514 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2515 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2516 }
0b2ae6d7
VS		 2517}
2518
2519/*
2520 * Merge all low power watermarks for all active pipes.
2521 */
2522static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2523 const struct intel_wm_config *config,
820c1980 2524 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2525 struct intel_pipe_wm *merged)
2526{
fac5e23e 2527 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2528 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2529 int last_enabled_level = max_level;
0b2ae6d7 2530
0ba22e26 2531 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2532 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2533 config->num_pipes_active > 1)
1204d5ba 2534 last_enabled_level = 0;
0ba22e26 2535
6c8b6c28 2536 /* ILK: FBC WM must be disabled always */
175fded1 2537 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
0b2ae6d7
VS		 2538
2539 /* merge each WM1+ level */
2540 for (level = 1; level <= max_level; level++) {
2541 struct intel_wm_level *wm = &merged->wm[level];
2542
2543 ilk_merge_wm_level(dev, level, wm);
2544
d52fea5b
VS		 2545 if (level > last_enabled_level)
2546 wm->enable = false;
2547 else if (!ilk_validate_wm_level(level, max, wm))
2548 /* make sure all following levels get disabled */
2549 last_enabled_level = level - 1;
0b2ae6d7
VS		 2550
2551 /*
2552 * The spec says it is preferred to disable
2553 * FBC WMs instead of disabling a WM level.
2554 */
2555 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2556 if (wm->enable)
2557 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2558 wm->fbc_val = 0;
2559 }
2560 }
6c8b6c28
VS		 2561
2562 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2563 /*
2564 * FIXME this is racy. FBC might get enabled later.
2565 * What we should check here is whether FBC can be
2566 * enabled sometime later.
2567 */
5db94019 2568 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2569 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2570 for (level = 2; level <= max_level; level++) {
2571 struct intel_wm_level *wm = &merged->wm[level];
2572
2573 wm->enable = false;
2574 }
2575 }
0b2ae6d7
VS		 2576}
2577
b380ca3c
VS		 2578static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2579{
2580 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2581 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2582}
2583
a68d68ee
VS		 2584/* The value we need to program into the WM_LPx latency field */
2585static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2586{
fac5e23e 2587 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2588
8652744b 2589 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2590 return 2 * level;
2591 else
2592 return dev_priv->wm.pri_latency[level];
2593}
2594
820c1980 2595static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2596 const struct intel_pipe_wm *merged,
609cedef 2597 enum intel_ddb_partitioning partitioning,
820c1980 2598 struct ilk_wm_values *results)
801bcfff 2599{
175fded1 2600 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7
VS		 2601 struct intel_crtc *intel_crtc;
2602 int level, wm_lp;
cca32e9a 2603
0362c781 2604 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2605 results->partitioning = partitioning;
cca32e9a 2606
0b2ae6d7 2607 /* LP1+ register values */
cca32e9a 2608 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2609 const struct intel_wm_level *r;
801bcfff 2610
b380ca3c 2611 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2612
0362c781 2613 r = &merged->wm[level];
cca32e9a 2614
d52fea5b
VS		 2615 /*
2616 * Maintain the watermark values even if the level is
2617 * disabled. Doing otherwise could cause underruns.
2618 */
2619 results->wm_lp[wm_lp - 1] =
a68d68ee 2620 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2621 (r->pri_val << WM1_LP_SR_SHIFT) |
2622 r->cur_val;
2623
d52fea5b
VS		 2624 if (r->enable)
2625 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2626
175fded1 2627 if (INTEL_GEN(dev_priv) >= 8)
416f4727
VS		 2628 results->wm_lp[wm_lp - 1] |=
2629 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2630 else
2631 results->wm_lp[wm_lp - 1] |=
2632 r->fbc_val << WM1_LP_FBC_SHIFT;
2633
d52fea5b
VS		 2634 /*
2635 * Always set WM1S_LP_EN when spr_val != 0, even if the
2636 * level is disabled. Doing otherwise could cause underruns.
2637 */
175fded1 2638 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
6cef2b8a
VS		 2639 WARN_ON(wm_lp != 1);
2640 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2641 } else
2642 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2643 }
801bcfff 2644
0b2ae6d7 2645 /* LP0 register values */
d3fcc808 2646 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2647 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2648 const struct intel_wm_level *r =
2649 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2650
2651 if (WARN_ON(!r->enable))
2652 continue;
2653
ed4a6a7c 2654 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2655
0b2ae6d7
VS		 2656 results->wm_pipe[pipe] =
2657 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2658 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2659 r->cur_val;
801bcfff
PZ		 2660 }
2661}
2662
861f3389
PZ		 2663/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2664 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2665static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2666 struct intel_pipe_wm *r1,
2667 struct intel_pipe_wm *r2)
861f3389 2668{
5db94019 2669 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2670 int level1 = 0, level2 = 0;
861f3389 2671
198a1e9b
VS		 2672 for (level = 1; level <= max_level; level++) {
2673 if (r1->wm[level].enable)
2674 level1 = level;
2675 if (r2->wm[level].enable)
2676 level2 = level;
861f3389
PZ		 2677 }
2678
198a1e9b
VS		 2679 if (level1 == level2) {
2680 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2681 return r2;
2682 else
2683 return r1;
198a1e9b 2684 } else if (level1 > level2) {
861f3389
PZ		 2685 return r1;
2686 } else {
2687 return r2;
2688 }
2689}
2690
49a687c4
VS		 2691/* dirty bits used to track which watermarks need changes */
2692#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2693#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2694#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2695#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2696#define WM_DIRTY_FBC (1 << 24)
2697#define WM_DIRTY_DDB (1 << 25)
2698
055e393f 2699static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2700 const struct ilk_wm_values *old,
2701 const struct ilk_wm_values *new)
49a687c4
VS		 2702{
2703 unsigned int dirty = 0;
2704 enum pipe pipe;
2705 int wm_lp;
2706
055e393f 2707 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2708 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2709 dirty |= WM_DIRTY_LINETIME(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713
2714 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2715 dirty |= WM_DIRTY_PIPE(pipe);
2716 /* Must disable LP1+ watermarks too */
2717 dirty |= WM_DIRTY_LP_ALL;
2718 }
2719 }
2720
2721 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2722 dirty |= WM_DIRTY_FBC;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 if (old->partitioning != new->partitioning) {
2728 dirty |= WM_DIRTY_DDB;
2729 /* Must disable LP1+ watermarks too */
2730 dirty |= WM_DIRTY_LP_ALL;
2731 }
2732
2733 /* LP1+ watermarks already deemed dirty, no need to continue */
2734 if (dirty & WM_DIRTY_LP_ALL)
2735 return dirty;
2736
2737 /* Find the lowest numbered LP1+ watermark in need of an update... */
2738 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2739 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2740 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2741 break;
2742 }
2743
2744 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2745 for (; wm_lp <= 3; wm_lp++)
2746 dirty |= WM_DIRTY_LP(wm_lp);
2747
2748 return dirty;
2749}
2750
8553c18e
VS		 2751static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2752 unsigned int dirty)
801bcfff 2753{
820c1980 2754 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2755 bool changed = false;
801bcfff 2756
facd619b
VS		 2757 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2758 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2760 changed = true;
facd619b
VS		 2761 }
2762 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2763 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2764 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2765 changed = true;
facd619b
VS		 2766 }
2767 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2768 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2769 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2770 changed = true;
facd619b 2771 }
801bcfff 2772
facd619b
VS		 2773 /*
2774 * Don't touch WM1S_LP_EN here.
2775 * Doing so could cause underruns.
2776 */
6cef2b8a 2777
8553c18e
VS		 2778 return changed;
2779}
2780
2781/*
2782 * The spec says we shouldn't write when we don't need, because every write
2783 * causes WMs to be re-evaluated, expending some power.
2784 */
820c1980
ID		 2785static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2786 struct ilk_wm_values *results)
8553c18e 2787{
820c1980 2788 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2789 unsigned int dirty;
2790 uint32_t val;
2791
055e393f 2792 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2793 if (!dirty)
2794 return;
2795
2796 _ilk_disable_lp_wm(dev_priv, dirty);
2797
49a687c4 2798 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2799 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2800 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2801 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2802 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2803 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2804
49a687c4 2805 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2807 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2808 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2809 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2810 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2811
49a687c4 2812 if (dirty & WM_DIRTY_DDB) {
8652744b 2813 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2814 val = I915_READ(WM_MISC);
2815 if (results->partitioning == INTEL_DDB_PART_1_2)
2816 val &= ~WM_MISC_DATA_PARTITION_5_6;
2817 else
2818 val |= WM_MISC_DATA_PARTITION_5_6;
2819 I915_WRITE(WM_MISC, val);
2820 } else {
2821 val = I915_READ(DISP_ARB_CTL2);
2822 if (results->partitioning == INTEL_DDB_PART_1_2)
2823 val &= ~DISP_DATA_PARTITION_5_6;
2824 else
2825 val |= DISP_DATA_PARTITION_5_6;
2826 I915_WRITE(DISP_ARB_CTL2, val);
2827 }
1011d8c4
PZ		 2828 }
2829
49a687c4 2830 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2831 val = I915_READ(DISP_ARB_CTL);
2832 if (results->enable_fbc_wm)
2833 val &= ~DISP_FBC_WM_DIS;
2834 else
2835 val |= DISP_FBC_WM_DIS;
2836 I915_WRITE(DISP_ARB_CTL, val);
2837 }
2838
954911eb
ID		 2839 if (dirty & WM_DIRTY_LP(1) &&
2840 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2841 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2842
175fded1 2843 if (INTEL_GEN(dev_priv) >= 7) {
6cef2b8a
VS		 2844 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2845 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2846 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2847 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2848 }
801bcfff 2849
facd619b 2850 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2851 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2852 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2853 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2854 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2855 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2856
2857 dev_priv->wm.hw = *results;
801bcfff
PZ		 2858}
2859
ed4a6a7c 2860bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2861{
fac5e23e 2862 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2863
2864 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2865}
2866
656d1b89 2867#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2868
ee3d532f
PZ		 2869/*
2870 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2871 * so assume we'll always need it in order to avoid underruns.
2872 */
2873static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2874{
2875 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2876
b976dc53 2877 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
ee3d532f
PZ		 2878 return true;
2879
2880 return false;
2881}
2882
56feca91
PZ		 2883static bool
2884intel_has_sagv(struct drm_i915_private *dev_priv)
2885{
6e3100ec
PZ		 2886 if (IS_KABYLAKE(dev_priv))
2887 return true;
2888
2889 if (IS_SKYLAKE(dev_priv) &&
2890 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2891 return true;
2892
2893 return false;
56feca91
PZ		 2894}
2895
656d1b89
L		 2896/*
2897 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2898 * depending on power and performance requirements. The display engine access
2899 * to system memory is blocked during the adjustment time. Because of the
2900 * blocking time, having this enabled can cause full system hangs and/or pipe
2901 * underruns if we don't meet all of the following requirements:
2902 *
2903 * - <= 1 pipe enabled
2904 * - All planes can enable watermarks for latencies >= SAGV engine block time
2905 * - We're not using an interlaced display configuration
2906 */
2907int
16dcdc4e 2908intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2909{
2910 int ret;
2911
56feca91
PZ		 2912 if (!intel_has_sagv(dev_priv))
2913 return 0;
2914
2915 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2916 return 0;
2917
2918 DRM_DEBUG_KMS("Enabling the SAGV\n");
2919 mutex_lock(&dev_priv->rps.hw_lock);
2920
2921 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2922 GEN9_SAGV_ENABLE);
2923
2924 /* We don't need to wait for the SAGV when enabling */
2925 mutex_unlock(&dev_priv->rps.hw_lock);
2926
2927 /*
2928 * Some skl systems, pre-release machines in particular,
2929 * don't actually have an SAGV.
2930 */
6e3100ec 2931 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2932 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2933 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2934 return 0;
2935 } else if (ret < 0) {
2936 DRM_ERROR("Failed to enable the SAGV\n");
2937 return ret;
2938 }
2939
16dcdc4e 2940 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2941 return 0;
2942}
2943
656d1b89 2944int
16dcdc4e 2945intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89 2946{
b3b8e999 2947 int ret;
656d1b89 2948
56feca91
PZ		 2949 if (!intel_has_sagv(dev_priv))
2950 return 0;
2951
2952 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2953 return 0;
2954
2955 DRM_DEBUG_KMS("Disabling the SAGV\n");
2956 mutex_lock(&dev_priv->rps.hw_lock);
2957
2958 /* bspec says to keep retrying for at least 1 ms */
b3b8e999
ID		 2959 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2960 GEN9_SAGV_DISABLE,
2961 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2962 1);
656d1b89
L		 2963 mutex_unlock(&dev_priv->rps.hw_lock);
2964
656d1b89
L		 2965 /*
2966 * Some skl systems, pre-release machines in particular,
2967 * don't actually have an SAGV.
2968 */
b3b8e999 2969 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2970 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2971 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89 2972 return 0;
b3b8e999
ID		 2973 } else if (ret < 0) {
2974 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2975 return ret;
656d1b89
L		 2976 }
2977
16dcdc4e 2978 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 2979 return 0;
2980}
2981
16dcdc4e 2982bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 2983{
2984 struct drm_device *dev = state->dev;
2985 struct drm_i915_private *dev_priv = to_i915(dev);
2986 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 2987 struct intel_crtc *crtc;
2988 struct intel_plane *plane;
d8c0fafc 2989 struct intel_crtc_state *cstate;
656d1b89 2990 enum pipe pipe;
d8c0fafc 2991 int level, latency;
656d1b89 2992
56feca91
PZ		 2993 if (!intel_has_sagv(dev_priv))
2994 return false;
2995
656d1b89
L		 2996 /*
2997 * SKL workaround: bspec recommends we disable the SAGV when we have
2998 * more then one pipe enabled
2999 *
3000 * If there are no active CRTCs, no additional checks need be performed
3001 */
3002 if (hweight32(intel_state->active_crtcs) == 0)
3003 return true;
3004 else if (hweight32(intel_state->active_crtcs) > 1)
3005 return false;
3006
3007 /* Since we're now guaranteed to only have one active CRTC... */
3008 pipe = ffs(intel_state->active_crtcs) - 1;
98187836 3009 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
d8c0fafc 3010 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3011
c89cadd5 3012 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3013 return false;
3014
ee3d532f 3015 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d5cdfdf5
VS		 3016 struct skl_plane_wm *wm =
3017 &cstate->wm.skl.optimal.planes[plane->id];
ee3d532f 3018
656d1b89 3019 /* Skip this plane if it's not enabled */
d8c0fafc 3020 if (!wm->wm[0].plane_en)
656d1b89
L		 3021 continue;
3022
3023 /* Find the highest enabled wm level for this plane */
5db94019 3024 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3025 !wm->wm[level].plane_en; --level)
656d1b89
L		 3026 { }
3027
ee3d532f
PZ		 3028 latency = dev_priv->wm.skl_latency[level];
3029
3030 if (skl_needs_memory_bw_wa(intel_state) &&
bae781b2 3031 plane->base.state->fb->modifier ==
ee3d532f
PZ		 3032 I915_FORMAT_MOD_X_TILED)
3033 latency += 15;
3034
656d1b89
L		 3035 /*
3036 * If any of the planes on this pipe don't enable wm levels
3037 * that incur memory latencies higher then 30µs we can't enable
3038 * the SAGV
3039 */
ee3d532f 3040 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3041 return false;
3042 }
3043
3044 return true;
3045}
3046
b9cec075
DL		 3047static void
3048skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3049 const struct intel_crtc_state *cstate,
c107acfe
MR		 3050 struct skl_ddb_entry *alloc, /* out */
3051 int *num_active /* out */)
b9cec075 3052{
c107acfe
MR		 3053 struct drm_atomic_state *state = cstate->base.state;
3054 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3055 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3056 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3057 unsigned int pipe_size, ddb_size;
3058 int nth_active_pipe;
c107acfe 3059
a6d3460e 3060 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3061 alloc->start = 0;
3062 alloc->end = 0;
a6d3460e 3063 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3064 return;
3065 }
3066
a6d3460e
MR		 3067 if (intel_state->active_pipe_changes)
3068 *num_active = hweight32(intel_state->active_crtcs);
3069 else
3070 *num_active = hweight32(dev_priv->active_crtcs);
3071
6f3fff60
D		 3072 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3073 WARN_ON(ddb_size == 0);
b9cec075
DL		 3074
3075 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3076
c107acfe 3077 /*
a6d3460e
MR		 3078 * If the state doesn't change the active CRTC's, then there's
3079 * no need to recalculate; the existing pipe allocation limits
3080 * should remain unchanged. Note that we're safe from racing
3081 * commits since any racing commit that changes the active CRTC
3082 * list would need to grab _all_ crtc locks, including the one
3083 * we currently hold.
c107acfe 3084 */
a6d3460e 3085 if (!intel_state->active_pipe_changes) {
512b5527
ML		 3086 /*
3087 * alloc may be cleared by clear_intel_crtc_state,
3088 * copy from old state to be sure
3089 */
3090 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
a6d3460e 3091 return;
c107acfe 3092 }
a6d3460e
MR		 3093
3094 nth_active_pipe = hweight32(intel_state->active_crtcs &
3095 (drm_crtc_mask(for_crtc) - 1));
3096 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3097 alloc->start = nth_active_pipe * ddb_size / *num_active;
3098 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3099}
3100
c107acfe 3101static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3102{
c107acfe 3103 if (num_active == 1)
b9cec075
DL		 3104 return 32;
3105
3106 return 8;
3107}
3108
a269c583
DL		 3109static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3110{
3111 entry->start = reg & 0x3ff;
3112 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3113 if (entry->end)
3114 entry->end += 1;
a269c583
DL		 3115}
3116
08db6652
DL		 3117void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3118 struct skl_ddb_allocation *ddb /* out */)
a269c583 3119{
d5cdfdf5 3120 struct intel_crtc *crtc;
a269c583 3121
b10f1b20
ML		 3122 memset(ddb, 0, sizeof(*ddb));
3123
d5cdfdf5 3124 for_each_intel_crtc(&dev_priv->drm, crtc) {
4d800030 3125 enum intel_display_power_domain power_domain;
d5cdfdf5
VS		 3126 enum plane_id plane_id;
3127 enum pipe pipe = crtc->pipe;
4d800030
ID		 3128
3129 power_domain = POWER_DOMAIN_PIPE(pipe);
3130 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3131 continue;
3132
d5cdfdf5
VS		 3133 for_each_plane_id_on_crtc(crtc, plane_id) {
3134 u32 val;
3135
3136 if (plane_id != PLANE_CURSOR)
3137 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3138 else
3139 val = I915_READ(CUR_BUF_CFG(pipe));
a269c583 3140
d5cdfdf5
VS		 3141 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3142 }
4d800030
ID		 3143
3144 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3145 }
3146}
3147
9c2f7a9d
KM		 3148/*
3149 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3150 * The bspec defines downscale amount as:
3151 *
3152 * """
3153 * Horizontal down scale amount = maximum[1, Horizontal source size /
3154 * Horizontal destination size]
3155 * Vertical down scale amount = maximum[1, Vertical source size /
3156 * Vertical destination size]
3157 * Total down scale amount = Horizontal down scale amount *
3158 * Vertical down scale amount
3159 * """
3160 *
3161 * Return value is provided in 16.16 fixed point form to retain fractional part.
3162 * Caller should take care of dividing & rounding off the value.
3163 */
3164static uint32_t
3165skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3166{
3167 uint32_t downscale_h, downscale_w;
3168 uint32_t src_w, src_h, dst_w, dst_h;
3169
936e71e3 3170 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3171 return DRM_PLANE_HELPER_NO_SCALING;
3172
3173 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3174 src_w = drm_rect_width(&pstate->base.src);
3175 src_h = drm_rect_height(&pstate->base.src);
3176 dst_w = drm_rect_width(&pstate->base.dst);
3177 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3178 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3179 swap(dst_w, dst_h);
3180
3181 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3182 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3183
3184 /* Provide result in 16.16 fixed point */
3185 return (uint64_t)downscale_w * downscale_h >> 16;
3186}
3187
b9cec075 3188static unsigned int
024c9045
MR		 3189skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3190 const struct drm_plane_state *pstate,
3191 int y)
b9cec075 3192{
a280f7dd 3193 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
8d19d7d9 3194 uint32_t down_scale_amount, data_rate;
a280f7dd 3195 uint32_t width = 0, height = 0;
8305494e
VS		 3196 struct drm_framebuffer *fb;
3197 u32 format;
a1de91e5 3198
936e71e3 3199 if (!intel_pstate->base.visible)
a1de91e5 3200 return 0;
8305494e
VS		 3201
3202 fb = pstate->fb;
438b74a5 3203 format = fb->format->format;
8305494e 3204
a1de91e5
MR		 3205 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3206 return 0;
3207 if (y && format != DRM_FORMAT_NV12)
3208 return 0;
a280f7dd 3209
936e71e3
VS		 3210 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3211 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3212
bd2ef25d 3213 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3214 swap(width, height);
2cd601c6
CK		 3215
3216 /* for planar format */
a1de91e5 3217 if (format == DRM_FORMAT_NV12) {
2cd601c6 3218 if (y) /* y-plane data rate */
8d19d7d9 3219 data_rate = width * height *
353c8598 3220 fb->format->cpp[0];
2cd601c6 3221 else /* uv-plane data rate */
8d19d7d9 3222 data_rate = (width / 2) * (height / 2) *
353c8598 3223 fb->format->cpp[1];
8d19d7d9
KM		 3224 } else {
3225 /* for packed formats */
353c8598 3226 data_rate = width * height * fb->format->cpp[0];
2cd601c6
CK		 3227 }
3228
8d19d7d9
KM		 3229 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3230
3231 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3232}
3233
3234/*
3235 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3236 * a 8192x4096@32bpp framebuffer:
3237 * 3 * 4096 * 8192 * 4 < 2^32
3238 */
3239static unsigned int
1e6ee542
ML		 3240skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3241 unsigned *plane_data_rate,
3242 unsigned *plane_y_data_rate)
b9cec075 3243{
9c74d826
MR		 3244 struct drm_crtc_state *cstate = &intel_cstate->base;
3245 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3246 struct drm_plane *plane;
c8fe32c1 3247 const struct drm_plane_state *pstate;
d5cdfdf5 3248 unsigned int total_data_rate = 0;
a6d3460e
MR		 3249
3250 if (WARN_ON(!state))
3251 return 0;
b9cec075 3252
a1de91e5 3253 /* Calculate and cache data rate for each plane */
c8fe32c1 3254 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
d5cdfdf5
VS		 3255 enum plane_id plane_id = to_intel_plane(plane)->id;
3256 unsigned int rate;
a6d3460e 3257
a6d3460e
MR		 3258 /* packed/uv */
3259 rate = skl_plane_relative_data_rate(intel_cstate,
3260 pstate, 0);
d5cdfdf5 3261 plane_data_rate[plane_id] = rate;
1e6ee542
ML		 3262
3263 total_data_rate += rate;
a6d3460e
MR		 3264
3265 /* y-plane */
3266 rate = skl_plane_relative_data_rate(intel_cstate,
3267 pstate, 1);
d5cdfdf5 3268 plane_y_data_rate[plane_id] = rate;
024c9045 3269
1e6ee542 3270 total_data_rate += rate;
b9cec075
DL		 3271 }
3272
3273 return total_data_rate;
3274}
3275
cbcfd14b
KM		 3276static uint16_t
3277skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3278 const int y)
3279{
3280 struct drm_framebuffer *fb = pstate->fb;
3281 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3282 uint32_t src_w, src_h;
3283 uint32_t min_scanlines = 8;
3284 uint8_t plane_bpp;
3285
3286 if (WARN_ON(!fb))
3287 return 0;
3288
3289 /* For packed formats, no y-plane, return 0 */
438b74a5 3290 if (y && fb->format->format != DRM_FORMAT_NV12)
cbcfd14b
KM		 3291 return 0;
3292
3293 /* For Non Y-tile return 8-blocks */
bae781b2
VS		 3294 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3295 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
cbcfd14b
KM		 3296 return 8;
3297
936e71e3
VS		 3298 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3299 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3300
bd2ef25d 3301 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3302 swap(src_w, src_h);
3303
3304 /* Halve UV plane width and height for NV12 */
438b74a5 3305 if (fb->format->format == DRM_FORMAT_NV12 && !y) {
cbcfd14b
KM		 3306 src_w /= 2;
3307 src_h /= 2;
3308 }
3309
438b74a5 3310 if (fb->format->format == DRM_FORMAT_NV12 && !y)
353c8598 3311 plane_bpp = fb->format->cpp[1];
cbcfd14b 3312 else
353c8598 3313 plane_bpp = fb->format->cpp[0];
cbcfd14b 3314
bd2ef25d 3315 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3316 switch (plane_bpp) {
3317 case 1:
3318 min_scanlines = 32;
3319 break;
3320 case 2:
3321 min_scanlines = 16;
3322 break;
3323 case 4:
3324 min_scanlines = 8;
3325 break;
3326 case 8:
3327 min_scanlines = 4;
3328 break;
3329 default:
3330 WARN(1, "Unsupported pixel depth %u for rotation",
3331 plane_bpp);
3332 min_scanlines = 32;
3333 }
3334 }
3335
3336 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3337}
3338
49845a7a
ML		 3339static void
3340skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3341 uint16_t *minimum, uint16_t *y_minimum)
3342{
3343 const struct drm_plane_state *pstate;
3344 struct drm_plane *plane;
3345
3346 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
d5cdfdf5 3347 enum plane_id plane_id = to_intel_plane(plane)->id;
49845a7a 3348
d5cdfdf5 3349 if (plane_id == PLANE_CURSOR)
49845a7a
ML		 3350 continue;
3351
3352 if (!pstate->visible)
3353 continue;
3354
d5cdfdf5
VS		 3355 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
3356 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
49845a7a
ML		 3357 }
3358
3359 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3360}
3361
c107acfe 3362static int
024c9045 3363skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3364 struct skl_ddb_allocation *ddb /* out */)
3365{
c107acfe 3366 struct drm_atomic_state *state = cstate->base.state;
024c9045 3367 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3368 struct drm_device *dev = crtc->dev;
3369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3371 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
49845a7a 3372 uint16_t alloc_size, start;
fefdd810
ML		 3373 uint16_t minimum[I915_MAX_PLANES] = {};
3374 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3375 unsigned int total_data_rate;
d5cdfdf5 3376 enum plane_id plane_id;
c107acfe 3377 int num_active;
1e6ee542
ML		 3378 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3379 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3380
5a920b85
PZ		 3381 /* Clear the partitioning for disabled planes. */
3382 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3383 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3384
a6d3460e
MR		 3385 if (WARN_ON(!state))
3386 return 0;
3387
c107acfe 3388 if (!cstate->base.active) {
ce0ba283 3389 alloc->start = alloc->end = 0;
c107acfe
MR		 3390 return 0;
3391 }
3392
a6d3460e 3393 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3394 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3395 if (alloc_size == 0) {
3396 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3397 return 0;
b9cec075
DL		 3398 }
3399
49845a7a 3400 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
a6d3460e 3401
49845a7a
ML		 3402 /*
3403 * 1. Allocate the mininum required blocks for each active plane
3404 * and allocate the cursor, it doesn't require extra allocation
3405 * proportional to the data rate.
3406 */
80958155 3407
d5cdfdf5
VS		 3408 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3409 alloc_size -= minimum[plane_id];
3410 alloc_size -= y_minimum[plane_id];
80958155
DL		 3411 }
3412
49845a7a
ML		 3413 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3414 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3415
b9cec075 3416 /*
80958155
DL		 3417 * 2. Distribute the remaining space in proportion to the amount of
3418 * data each plane needs to fetch from memory.
b9cec075
DL		 3419 *
3420 * FIXME: we may not allocate every single block here.
3421 */
1e6ee542
ML		 3422 total_data_rate = skl_get_total_relative_data_rate(cstate,
3423 plane_data_rate,
3424 plane_y_data_rate);
a1de91e5 3425 if (total_data_rate == 0)
c107acfe 3426 return 0;
b9cec075 3427
34bb56af 3428 start = alloc->start;
d5cdfdf5 3429 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
2cd601c6
CK		 3430 unsigned int data_rate, y_data_rate;
3431 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3432
d5cdfdf5 3433 if (plane_id == PLANE_CURSOR)
49845a7a
ML		 3434 continue;
3435
d5cdfdf5 3436 data_rate = plane_data_rate[plane_id];
b9cec075
DL		 3437
3438 /*
2cd601c6 3439 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3440 * promote the expression to 64 bits to avoid overflowing, the
3441 * result is < available as data_rate / total_data_rate < 1
3442 */
d5cdfdf5 3443 plane_blocks = minimum[plane_id];
80958155
DL		 3444 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3445 total_data_rate);
b9cec075 3446
c107acfe
MR		 3447 /* Leave disabled planes at (0,0) */
3448 if (data_rate) {
d5cdfdf5
VS		 3449 ddb->plane[pipe][plane_id].start = start;
3450 ddb->plane[pipe][plane_id].end = start + plane_blocks;
c107acfe 3451 }
b9cec075
DL		 3452
3453 start += plane_blocks;
2cd601c6
CK		 3454
3455 /*
3456 * allocation for y_plane part of planar format:
3457 */
d5cdfdf5 3458 y_data_rate = plane_y_data_rate[plane_id];
a1de91e5 3459
d5cdfdf5 3460 y_plane_blocks = y_minimum[plane_id];
a1de91e5
MR		 3461 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3462 total_data_rate);
2cd601c6 3463
c107acfe 3464 if (y_data_rate) {
d5cdfdf5
VS		 3465 ddb->y_plane[pipe][plane_id].start = start;
3466 ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
c107acfe 3467 }
a1de91e5
MR		 3468
3469 start += y_plane_blocks;
b9cec075
DL		 3470 }
3471
c107acfe 3472 return 0;
b9cec075
DL		 3473}
3474
2d41c0b5
PB		 3475/*
3476 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3477 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3478 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3479 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3480*/
b95320bd
MK		 3481static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
3482 uint32_t latency)
2d41c0b5 3483{
b95320bd
MK		 3484 uint32_t wm_intermediate_val;
3485 uint_fixed_16_16_t ret;
2d41c0b5
PB		 3486
3487 if (latency == 0)
b95320bd 3488 return FP_16_16_MAX;
2d41c0b5 3489
b95320bd
MK		 3490 wm_intermediate_val = latency * pixel_rate * cpp;
3491 ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
2d41c0b5
PB		 3492 return ret;
3493}
3494
b95320bd
MK		 3495static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
3496 uint32_t pipe_htotal,
3497 uint32_t latency,
3498 uint_fixed_16_16_t plane_blocks_per_line)
2d41c0b5 3499{
d4c2aa60 3500 uint32_t wm_intermediate_val;
b95320bd 3501 uint_fixed_16_16_t ret;
2d41c0b5
PB		 3502
3503 if (latency == 0)
b95320bd 3504 return FP_16_16_MAX;
2d41c0b5 3505
2d41c0b5 3506 wm_intermediate_val = latency * pixel_rate;
b95320bd
MK		 3507 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
3508 pipe_htotal * 1000);
3509 ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
2d41c0b5
PB		 3510 return ret;
3511}
3512
9c2f7a9d
KM		 3513static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3514 struct intel_plane_state *pstate)
3515{
3516 uint64_t adjusted_pixel_rate;
3517 uint64_t downscale_amount;
3518 uint64_t pixel_rate;
3519
3520 /* Shouldn't reach here on disabled planes... */
936e71e3 3521 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3522 return 0;
3523
3524 /*
3525 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3526 * with additional adjustments for plane-specific scaling.
3527 */
a7d1b3f4 3528 adjusted_pixel_rate = cstate->pixel_rate;
9c2f7a9d
KM		 3529 downscale_amount = skl_plane_downscale_amount(pstate);
3530
3531 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3532 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3533
3534 return pixel_rate;
3535}
3536
55994c2c
MR		 3537static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3538 struct intel_crtc_state *cstate,
3539 struct intel_plane_state *intel_pstate,
3540 uint16_t ddb_allocation,
3541 int level,
3542 uint16_t *out_blocks, /* out */
3543 uint8_t *out_lines, /* out */
3544 bool *enabled /* out */)
2d41c0b5 3545{
33815fa5
MR		 3546 struct drm_plane_state *pstate = &intel_pstate->base;
3547 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60 3548 uint32_t latency = dev_priv->wm.skl_latency[level];
b95320bd
MK		 3549 uint_fixed_16_16_t method1, method2;
3550 uint_fixed_16_16_t plane_blocks_per_line;
3551 uint_fixed_16_16_t selected_result;
3552 uint32_t interm_pbpl;
3553 uint32_t plane_bytes_per_line;
d4c2aa60 3554 uint32_t res_blocks, res_lines;
ac484963 3555 uint8_t cpp;
a280f7dd 3556 uint32_t width = 0, height = 0;
9c2f7a9d 3557 uint32_t plane_pixel_rate;
b95320bd
MK		 3558 uint_fixed_16_16_t y_tile_minimum;
3559 uint32_t y_min_scanlines;
ee3d532f
PZ		 3560 struct intel_atomic_state *state =
3561 to_intel_atomic_state(cstate->base.state);
3562 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
ef8a4fb4 3563 bool y_tiled, x_tiled;
2d41c0b5 3564
936e71e3 3565 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3566 *enabled = false;
3567 return 0;
3568 }
2d41c0b5 3569
ef8a4fb4
MK		 3570 y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3571 fb->modifier == I915_FORMAT_MOD_Yf_TILED;
3572 x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
3573
4b7b2331
MK		 3574 /* Display WA #1141: kbl. */
3575 if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
3576 latency += 4;
3577
ef8a4fb4 3578 if (apply_memory_bw_wa && x_tiled)
ee3d532f
PZ		 3579 latency += 15;
3580
936e71e3
VS		 3581 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3582 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3583
bd2ef25d 3584 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3585 swap(width, height);
3586
353c8598 3587 cpp = fb->format->cpp[0];
9c2f7a9d
KM		 3588 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3589
61d0a04d 3590 if (drm_rotation_90_or_270(pstate->rotation)) {
438b74a5 3591 int cpp = (fb->format->format == DRM_FORMAT_NV12) ?
353c8598
VS		 3592 fb->format->cpp[1] :
3593 fb->format->cpp[0];
1186fa85
PZ		 3594
3595 switch (cpp) {
3596 case 1:
3597 y_min_scanlines = 16;
3598 break;
3599 case 2:
3600 y_min_scanlines = 8;
3601 break;
1186fa85
PZ		 3602 case 4:
3603 y_min_scanlines = 4;
3604 break;
86a462bc
PZ		 3605 default:
3606 MISSING_CASE(cpp);
3607 return -EINVAL;
1186fa85
PZ		 3608 }
3609 } else {
3610 y_min_scanlines = 4;
3611 }
3612
2ef32dee
PZ		 3613 if (apply_memory_bw_wa)
3614 y_min_scanlines *= 2;
3615
7a1a8aed 3616 plane_bytes_per_line = width * cpp;
ef8a4fb4 3617 if (y_tiled) {
b95320bd
MK		 3618 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
3619 y_min_scanlines, 512);
7a1a8aed 3620 plane_blocks_per_line =
b95320bd 3621 fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
ef8a4fb4 3622 } else if (x_tiled) {
b95320bd
MK		 3623 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
3624 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
ef8a4fb4 3625 } else {
b95320bd
MK		 3626 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3627 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
7a1a8aed
PZ		 3628 }
3629
9c2f7a9d
KM		 3630 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3631 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3632 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3633 latency,
7a1a8aed 3634 plane_blocks_per_line);
2d41c0b5 3635
b95320bd
MK		 3636 y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
3637 plane_blocks_per_line);
75676ed4 3638
ef8a4fb4 3639 if (y_tiled) {
b95320bd 3640 selected_result = max_fixed_16_16(method2, y_tile_minimum);
0fda6568 3641 } else {
f1db3eaf
PZ		 3642 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3643 (plane_bytes_per_line / 512 < 1))
3644 selected_result = method2;
b95320bd
MK		 3645 else if ((ddb_allocation /
3646 fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
3647 selected_result = min_fixed_16_16(method1, method2);
0fda6568
TU		 3648 else
3649 selected_result = method1;
3650 }
2d41c0b5 3651
b95320bd
MK		 3652 res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
3653 res_lines = DIV_ROUND_UP(selected_result.val,
3654 plane_blocks_per_line.val);
e6d66171 3655
0fda6568 3656 if (level >= 1 && level <= 7) {
ef8a4fb4 3657 if (y_tiled) {
b95320bd 3658 res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
1186fa85 3659 res_lines += y_min_scanlines;
75676ed4 3660 } else {
0fda6568 3661 res_blocks++;
75676ed4 3662 }
0fda6568 3663 }
e6d66171 3664
55994c2c
MR		 3665 if (res_blocks >= ddb_allocation || res_lines > 31) {
3666 *enabled = false;
6b6bada7
MR		 3667
3668 /*
3669 * If there are no valid level 0 watermarks, then we can't
3670 * support this display configuration.
3671 */
3672 if (level) {
3673 return 0;
3674 } else {
d5cdfdf5
VS		 3675 struct drm_plane *plane = pstate->plane;
3676
6b6bada7 3677 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
d5cdfdf5
VS		 3678 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3679 plane->base.id, plane->name,
6b6bada7 3680 res_blocks, ddb_allocation, res_lines);
6b6bada7
MR		 3681 return -EINVAL;
3682 }
55994c2c 3683 }
e6d66171
DL		 3684
3685 *out_blocks = res_blocks;
3686 *out_lines = res_lines;
55994c2c 3687 *enabled = true;
2d41c0b5 3688
55994c2c 3689 return 0;
2d41c0b5
PB		 3690}
3691
f4a96752
MR		 3692static int
3693skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3694 struct skl_ddb_allocation *ddb,
3695 struct intel_crtc_state *cstate,
a62163e9 3696 struct intel_plane *intel_plane,
f4a96752
MR		 3697 int level,
3698 struct skl_wm_level *result)
2d41c0b5 3699{
f4a96752 3700 struct drm_atomic_state *state = cstate->base.state;
024c9045 3701 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3702 struct drm_plane *plane = &intel_plane->base;
3703 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3704 uint16_t ddb_blocks;
024c9045 3705 enum pipe pipe = intel_crtc->pipe;
55994c2c 3706 int ret;
a62163e9
L		 3707
3708 if (state)
3709 intel_pstate =
3710 intel_atomic_get_existing_plane_state(state,
3711 intel_plane);
024c9045 3712
f4a96752 3713 /*
a62163e9
L		 3714 * Note: If we start supporting multiple pending atomic commits against
3715 * the same planes/CRTC's in the future, plane->state will no longer be
3716 * the correct pre-state to use for the calculations here and we'll
3717 * need to change where we get the 'unchanged' plane data from.
3718 *
3719 * For now this is fine because we only allow one queued commit against
3720 * a CRTC. Even if the plane isn't modified by this transaction and we
3721 * don't have a plane lock, we still have the CRTC's lock, so we know
3722 * that no other transactions are racing with us to update it.
f4a96752 3723 */
a62163e9
L		 3724 if (!intel_pstate)
3725 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3726
a62163e9 3727 WARN_ON(!intel_pstate->base.fb);
f4a96752 3728
d5cdfdf5 3729 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
2d41c0b5 3730
a62163e9
L		 3731 ret = skl_compute_plane_wm(dev_priv,
3732 cstate,
3733 intel_pstate,
3734 ddb_blocks,
3735 level,
3736 &result->plane_res_b,
3737 &result->plane_res_l,
3738 &result->plane_en);
3739 if (ret)
3740 return ret;
f4a96752
MR		 3741
3742 return 0;
2d41c0b5
PB		 3743}
3744
407b50f3 3745static uint32_t
024c9045 3746skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3747{
a3a8986c
MK		 3748 struct drm_atomic_state *state = cstate->base.state;
3749 struct drm_i915_private *dev_priv = to_i915(state->dev);
30d1b5fe 3750 uint32_t pixel_rate;
a3a8986c 3751 uint32_t linetime_wm;
30d1b5fe 3752
024c9045 3753 if (!cstate->base.active)
407b50f3
DL		 3754 return 0;
3755
a7d1b3f4 3756 pixel_rate = cstate->pixel_rate;
30d1b5fe
PZ		 3757
3758 if (WARN_ON(pixel_rate == 0))
661abfc0 3759 return 0;
407b50f3 3760
a3a8986c
MK		 3761 linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
3762 1000, pixel_rate);
3763
3764 /* Display WA #1135: bxt. */
3765 if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
3766 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
3767
3768 return linetime_wm;
407b50f3
DL		 3769}
3770
024c9045 3771static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3772 struct skl_wm_level *trans_wm /* out */)
407b50f3 3773{
024c9045 3774 if (!cstate->base.active)
407b50f3 3775 return;
9414f563
DL		 3776
3777 /* Until we know more, just disable transition WMs */
a62163e9 3778 trans_wm->plane_en = false;
407b50f3
DL		 3779}
3780
55994c2c
MR		 3781static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3782 struct skl_ddb_allocation *ddb,
3783 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3784{
024c9045 3785 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3786 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3787 struct intel_plane *intel_plane;
3788 struct skl_plane_wm *wm;
5db94019 3789 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3790 int ret;
2d41c0b5 3791
a62163e9
L		 3792 /*
3793 * We'll only calculate watermarks for planes that are actually
3794 * enabled, so make sure all other planes are set as disabled.
3795 */
3796 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3797
3798 for_each_intel_plane_mask(&dev_priv->drm,
3799 intel_plane,
3800 cstate->base.plane_mask) {
d5cdfdf5 3801 wm = &pipe_wm->planes[intel_plane->id];
a62163e9
L		 3802
3803 for (level = 0; level <= max_level; level++) {
3804 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3805 intel_plane, level,
3806 &wm->wm[level]);
3807 if (ret)
3808 return ret;
3809 }
3810 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3811 }
024c9045 3812 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3813
55994c2c 3814 return 0;
2d41c0b5
PB		 3815}
3816
f0f59a00
VS		 3817static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3818 i915_reg_t reg,
16160e3d
DL		 3819 const struct skl_ddb_entry *entry)
3820{
3821 if (entry->end)
3822 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3823 else
3824 I915_WRITE(reg, 0);
3825}
3826
d8c0fafc 3827static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3828 i915_reg_t reg,
3829 const struct skl_wm_level *level)
3830{
3831 uint32_t val = 0;
3832
3833 if (level->plane_en) {
3834 val |= PLANE_WM_EN;
3835 val |= level->plane_res_b;
3836 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3837 }
3838
3839 I915_WRITE(reg, val);
3840}
3841
d9348dec
VS		 3842static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3843 const struct skl_plane_wm *wm,
3844 const struct skl_ddb_allocation *ddb,
d5cdfdf5 3845 enum plane_id plane_id)
62e0fb88
L		 3846{
3847 struct drm_crtc *crtc = &intel_crtc->base;
3848 struct drm_device *dev = crtc->dev;
3849 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3850 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3851 enum pipe pipe = intel_crtc->pipe;
3852
3853 for (level = 0; level <= max_level; level++) {
d5cdfdf5 3854 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
d8c0fafc 3855 &wm->wm[level]);
62e0fb88 3856 }
d5cdfdf5 3857 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
d8c0fafc 3858 &wm->trans_wm);
27082493 3859
d5cdfdf5
VS		 3860 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
3861 &ddb->plane[pipe][plane_id]);
3862 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
3863 &ddb->y_plane[pipe][plane_id]);
62e0fb88
L		 3864}
3865
d9348dec
VS		 3866static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3867 const struct skl_plane_wm *wm,
3868 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3869{
3870 struct drm_crtc *crtc = &intel_crtc->base;
3871 struct drm_device *dev = crtc->dev;
3872 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3873 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3874 enum pipe pipe = intel_crtc->pipe;
3875
3876 for (level = 0; level <= max_level; level++) {
d8c0fafc 3877 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3878 &wm->wm[level]);
62e0fb88 3879 }
d8c0fafc 3880 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3881
27082493 3882 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3883 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3884}
3885
45ece230 3886bool skl_wm_level_equals(const struct skl_wm_level *l1,
3887 const struct skl_wm_level *l2)
3888{
3889 if (l1->plane_en != l2->plane_en)
3890 return false;
3891
3892 /* If both planes aren't enabled, the rest shouldn't matter */
3893 if (!l1->plane_en)
3894 return true;
3895
3896 return (l1->plane_res_l == l2->plane_res_l &&
3897 l1->plane_res_b == l2->plane_res_b);
3898}
3899
27082493
L		 3900static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3901 const struct skl_ddb_entry *b)
0e8fb7ba 3902{
27082493 3903 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3904}
3905
5eff503b
ML		 3906bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3907 const struct skl_ddb_entry *ddb,
3908 int ignore)
0e8fb7ba 3909{
ce0ba283 3910 int i;
0e8fb7ba 3911
5eff503b
ML		 3912 for (i = 0; i < I915_MAX_PIPES; i++)
3913 if (i != ignore && entries[i] &&
3914 skl_ddb_entries_overlap(ddb, entries[i]))
27082493 3915 return true;
0e8fb7ba 3916
27082493 3917 return false;
0e8fb7ba
DL		 3918}
3919
55994c2c 3920static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
03af79e0 3921 const struct skl_pipe_wm *old_pipe_wm,
55994c2c 3922 struct skl_pipe_wm *pipe_wm, /* out */
03af79e0 3923 struct skl_ddb_allocation *ddb, /* out */
55994c2c 3924 bool *changed /* out */)
2d41c0b5 3925{
f4a96752 3926 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3927 int ret;
2d41c0b5 3928
55994c2c
MR		 3929 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3930 if (ret)
3931 return ret;
2d41c0b5 3932
03af79e0 3933 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3934 *changed = false;
3935 else
3936 *changed = true;
2d41c0b5 3937
55994c2c 3938 return 0;
2d41c0b5
PB		 3939}
3940
9b613022
MR		 3941static uint32_t
3942pipes_modified(struct drm_atomic_state *state)
3943{
3944 struct drm_crtc *crtc;
3945 struct drm_crtc_state *cstate;
3946 uint32_t i, ret = 0;
3947
3948 for_each_crtc_in_state(state, crtc, cstate, i)
3949 ret |= drm_crtc_mask(crtc);
3950
3951 return ret;
3952}
3953
bb7791bd 3954static int
7f60e200
PZ		 3955skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3956{
3957 struct drm_atomic_state *state = cstate->base.state;
3958 struct drm_device *dev = state->dev;
3959 struct drm_crtc *crtc = cstate->base.crtc;
3960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961 struct drm_i915_private *dev_priv = to_i915(dev);
3962 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3963 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3964 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3965 struct drm_plane_state *plane_state;
3966 struct drm_plane *plane;
3967 enum pipe pipe = intel_crtc->pipe;
7f60e200
PZ		 3968
3969 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3970
220b0965 3971 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
d5cdfdf5 3972 enum plane_id plane_id = to_intel_plane(plane)->id;
7f60e200 3973
d5cdfdf5
VS		 3974 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
3975 &new_ddb->plane[pipe][plane_id]) &&
3976 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
3977 &new_ddb->y_plane[pipe][plane_id]))
7f60e200
PZ		 3978 continue;
3979
3980 plane_state = drm_atomic_get_plane_state(state, plane);
3981 if (IS_ERR(plane_state))
3982 return PTR_ERR(plane_state);
3983 }
3984
3985 return 0;
3986}
3987
98d39494
MR		 3988static int
3989skl_compute_ddb(struct drm_atomic_state *state)
3990{
3991 struct drm_device *dev = state->dev;
3992 struct drm_i915_private *dev_priv = to_i915(dev);
3993 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3994 struct intel_crtc *intel_crtc;
734fa01f 3995 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3996 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3997 int ret;
3998
3999 /*
4000 * If this is our first atomic update following hardware readout,
4001 * we can't trust the DDB that the BIOS programmed for us. Let's
4002 * pretend that all pipes switched active status so that we'll
4003 * ensure a full DDB recompute.
4004 */
1b54a880
MR		 4005 if (dev_priv->wm.distrust_bios_wm) {
4006 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4007 state->acquire_ctx);
4008 if (ret)
4009 return ret;
4010
98d39494
MR		 4011 intel_state->active_pipe_changes = ~0;
4012
1b54a880
MR		 4013 /*
4014 * We usually only initialize intel_state->active_crtcs if we
4015 * we're doing a modeset; make sure this field is always
4016 * initialized during the sanitization process that happens
4017 * on the first commit too.
4018 */
4019 if (!intel_state->modeset)
4020 intel_state->active_crtcs = dev_priv->active_crtcs;
4021 }
4022
98d39494
MR		 4023 /*
4024 * If the modeset changes which CRTC's are active, we need to
4025 * recompute the DDB allocation for *all* active pipes, even
4026 * those that weren't otherwise being modified in any way by this
4027 * atomic commit. Due to the shrinking of the per-pipe allocations
4028 * when new active CRTC's are added, it's possible for a pipe that
4029 * we were already using and aren't changing at all here to suddenly
4030 * become invalid if its DDB needs exceeds its new allocation.
4031 *
4032 * Note that if we wind up doing a full DDB recompute, we can't let
4033 * any other display updates race with this transaction, so we need
4034 * to grab the lock on *all* CRTC's.
4035 */
734fa01f 4036 if (intel_state->active_pipe_changes) {
98d39494 4037 realloc_pipes = ~0;
734fa01f
MR		 4038 intel_state->wm_results.dirty_pipes = ~0;
4039 }
98d39494 4040
5a920b85
PZ		 4041 /*
4042 * We're not recomputing for the pipes not included in the commit, so
4043 * make sure we start with the current state.
4044 */
4045 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4046
98d39494
MR		 4047 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4048 struct intel_crtc_state *cstate;
4049
4050 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4051 if (IS_ERR(cstate))
4052 return PTR_ERR(cstate);
4053
734fa01f 4054 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4055 if (ret)
4056 return ret;
05a76d3d 4057
7f60e200 4058 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4059 if (ret)
4060 return ret;
98d39494
MR		 4061 }
4062
4063 return 0;
4064}
4065
2722efb9
MR		 4066static void
4067skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4068 struct skl_wm_values *src,
4069 enum pipe pipe)
4070{
2722efb9
MR		 4071 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4072 sizeof(dst->ddb.y_plane[pipe]));
4073 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4074 sizeof(dst->ddb.plane[pipe]));
4075}
4076
413fc530 4077static void
4078skl_print_wm_changes(const struct drm_atomic_state *state)
4079{
4080 const struct drm_device *dev = state->dev;
4081 const struct drm_i915_private *dev_priv = to_i915(dev);
4082 const struct intel_atomic_state *intel_state =
4083 to_intel_atomic_state(state);
4084 const struct drm_crtc *crtc;
4085 const struct drm_crtc_state *cstate;
413fc530 4086 const struct intel_plane *intel_plane;
413fc530 4087 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4088 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
7570498e 4089 int i;
413fc530 4090
4091 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4092 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 enum pipe pipe = intel_crtc->pipe;
413fc530 4094
7570498e 4095 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
d5cdfdf5 4096 enum plane_id plane_id = intel_plane->id;
413fc530 4097 const struct skl_ddb_entry *old, *new;
4098
d5cdfdf5
VS		 4099 old = &old_ddb->plane[pipe][plane_id];
4100 new = &new_ddb->plane[pipe][plane_id];
413fc530 4101
413fc530 4102 if (skl_ddb_entry_equal(old, new))
4103 continue;
4104
7570498e
ML		 4105 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4106 intel_plane->base.base.id,
4107 intel_plane->base.name,
4108 old->start, old->end,
4109 new->start, new->end);
413fc530 4110 }
4111 }
4112}
4113
98d39494
MR		 4114static int
4115skl_compute_wm(struct drm_atomic_state *state)
4116{
4117 struct drm_crtc *crtc;
4118 struct drm_crtc_state *cstate;
734fa01f
MR		 4119 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4120 struct skl_wm_values *results = &intel_state->wm_results;
4121 struct skl_pipe_wm *pipe_wm;
98d39494 4122 bool changed = false;
734fa01f 4123 int ret, i;
98d39494
MR		 4124
4125 /*
4126 * If this transaction isn't actually touching any CRTC's, don't
4127 * bother with watermark calculation. Note that if we pass this
4128 * test, we're guaranteed to hold at least one CRTC state mutex,
4129 * which means we can safely use values like dev_priv->active_crtcs
4130 * since any racing commits that want to update them would need to
4131 * hold _all_ CRTC state mutexes.
4132 */
4133 for_each_crtc_in_state(state, crtc, cstate, i)
4134 changed = true;
4135 if (!changed)
4136 return 0;
4137
734fa01f
MR		 4138 /* Clear all dirty flags */
4139 results->dirty_pipes = 0;
4140
98d39494
MR		 4141 ret = skl_compute_ddb(state);
4142 if (ret)
4143 return ret;
4144
734fa01f
MR		 4145 /*
4146 * Calculate WM's for all pipes that are part of this transaction.
4147 * Note that the DDB allocation above may have added more CRTC's that
4148 * weren't otherwise being modified (and set bits in dirty_pipes) if
4149 * pipe allocations had to change.
4150 *
4151 * FIXME: Now that we're doing this in the atomic check phase, we
4152 * should allow skl_update_pipe_wm() to return failure in cases where
4153 * no suitable watermark values can be found.
4154 */
4155 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4156 struct intel_crtc_state *intel_cstate =
4157 to_intel_crtc_state(cstate);
03af79e0
ML		 4158 const struct skl_pipe_wm *old_pipe_wm =
4159 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
734fa01f
MR		 4160
4161 pipe_wm = &intel_cstate->wm.skl.optimal;
03af79e0
ML		 4162 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4163 &results->ddb, &changed);
734fa01f
MR		 4164 if (ret)
4165 return ret;
4166
4167 if (changed)
4168 results->dirty_pipes |= drm_crtc_mask(crtc);
4169
4170 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4171 /* This pipe's WM's did not change */
4172 continue;
4173
4174 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4175 }
4176
413fc530 4177 skl_print_wm_changes(state);
4178
98d39494
MR		 4179 return 0;
4180}
4181
ccf010fb
ML		 4182static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4183 struct intel_crtc_state *cstate)
4184{
4185 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4186 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4187 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
e62929b3 4188 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
ccf010fb 4189 enum pipe pipe = crtc->pipe;
d5cdfdf5 4190 enum plane_id plane_id;
e62929b3
ML		 4191
4192 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4193 return;
ccf010fb
ML		 4194
4195 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
e62929b3 4196
d5cdfdf5
VS		 4197 for_each_plane_id_on_crtc(crtc, plane_id) {
4198 if (plane_id != PLANE_CURSOR)
4199 skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
4200 ddb, plane_id);
4201 else
4202 skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
4203 ddb);
4204 }
ccf010fb
ML		 4205}
4206
e62929b3
ML		 4207static void skl_initial_wm(struct intel_atomic_state *state,
4208 struct intel_crtc_state *cstate)
2d41c0b5 4209{
e62929b3 4210 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
432081bc 4211 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4212 struct drm_i915_private *dev_priv = to_i915(dev);
e62929b3 4213 struct skl_wm_values *results = &state->wm_results;
2722efb9 4214 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
27082493 4215 enum pipe pipe = intel_crtc->pipe;
adda50b8 4216
432081bc 4217 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
2d41c0b5
PB		 4218 return;
4219
734fa01f 4220 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4221
e62929b3
ML		 4222 if (cstate->base.active_changed)
4223 skl_atomic_update_crtc_wm(state, cstate);
27082493
L		 4224
4225 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4226
4227 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4228}
4229
d890565c
VS		 4230static void ilk_compute_wm_config(struct drm_device *dev,
4231 struct intel_wm_config *config)
4232{
4233 struct intel_crtc *crtc;
4234
4235 /* Compute the currently _active_ config */
4236 for_each_intel_crtc(dev, crtc) {
4237 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4238
4239 if (!wm->pipe_enabled)
4240 continue;
4241
4242 config->sprites_enabled |= wm->sprites_enabled;
4243 config->sprites_scaled |= wm->sprites_scaled;
4244 config->num_pipes_active++;
4245 }
4246}
4247
ed4a6a7c 4248static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4249{
91c8a326 4250 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4251 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4252 struct ilk_wm_maximums max;
d890565c 4253 struct intel_wm_config config = {};
820c1980 4254 struct ilk_wm_values results = {};
77c122bc 4255 enum intel_ddb_partitioning partitioning;
261a27d1 4256
d890565c
VS		 4257 ilk_compute_wm_config(dev, &config);
4258
4259 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4260 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4261
4262 /* 5/6 split only in single pipe config on IVB+ */
175fded1 4263 if (INTEL_GEN(dev_priv) >= 7 &&
d890565c
VS		 4264 config.num_pipes_active == 1 && config.sprites_enabled) {
4265 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4266 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4267
820c1980 4268 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4269 } else {
198a1e9b 4270 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4271 }
4272
198a1e9b 4273 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4274 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4275
820c1980 4276 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4277
820c1980 4278 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4279}
4280
ccf010fb
ML		 4281static void ilk_initial_watermarks(struct intel_atomic_state *state,
4282 struct intel_crtc_state *cstate)
b9d5c839 4283{
ed4a6a7c
MR		 4284 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4285 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4286
ed4a6a7c 4287 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4288 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4289 ilk_program_watermarks(dev_priv);
4290 mutex_unlock(&dev_priv->wm.wm_mutex);
4291}
bf220452 4292
ccf010fb
ML		 4293static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4294 struct intel_crtc_state *cstate)
ed4a6a7c
MR		 4295{
4296 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4297 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4298
ed4a6a7c
MR		 4299 mutex_lock(&dev_priv->wm.wm_mutex);
4300 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4301 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4302 ilk_program_watermarks(dev_priv);
4303 }
4304 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4305}
4306
d8c0fafc 4307static inline void skl_wm_level_from_reg_val(uint32_t val,
4308 struct skl_wm_level *level)
3078999f 4309{
d8c0fafc 4310 level->plane_en = val & PLANE_WM_EN;
4311 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4312 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4313 PLANE_WM_LINES_MASK;
3078999f
PB		 4314}
4315
bf9d99ad 4316void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4317 struct skl_pipe_wm *out)
3078999f 4318{
d5cdfdf5 4319 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3078999f 4320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3078999f 4321 enum pipe pipe = intel_crtc->pipe;
d5cdfdf5
VS		 4322 int level, max_level;
4323 enum plane_id plane_id;
d8c0fafc 4324 uint32_t val;
3078999f 4325
5db94019 4326 max_level = ilk_wm_max_level(dev_priv);
3078999f 4327
d5cdfdf5
VS		 4328 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4329 struct skl_plane_wm *wm = &out->planes[plane_id];
3078999f 4330
d8c0fafc 4331 for (level = 0; level <= max_level; level++) {
d5cdfdf5
VS		 4332 if (plane_id != PLANE_CURSOR)
4333 val = I915_READ(PLANE_WM(pipe, plane_id, level));
d8c0fafc 4334 else
4335 val = I915_READ(CUR_WM(pipe, level));
3078999f 4336
d8c0fafc 4337 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4338 }
3078999f 4339
d5cdfdf5
VS		 4340 if (plane_id != PLANE_CURSOR)
4341 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
d8c0fafc 4342 else
4343 val = I915_READ(CUR_WM_TRANS(pipe));
4344
4345 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4346 }
4347
d8c0fafc 4348 if (!intel_crtc->active)
4349 return;
4e0963c7 4350
bf9d99ad 4351 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4352}
4353
4354void skl_wm_get_hw_state(struct drm_device *dev)
4355{
fac5e23e 4356 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4357 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4358 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4359 struct drm_crtc *crtc;
bf9d99ad 4360 struct intel_crtc *intel_crtc;
4361 struct intel_crtc_state *cstate;
3078999f 4362
a269c583 4363 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4364 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4365 intel_crtc = to_intel_crtc(crtc);
4366 cstate = to_intel_crtc_state(crtc->state);
4367
4368 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4369
03af79e0 4370 if (intel_crtc->active)
bf9d99ad 4371 hw->dirty_pipes |= drm_crtc_mask(crtc);
bf9d99ad 4372 }
a1de91e5 4373
279e99d7
MR		 4374 if (dev_priv->active_crtcs) {
4375 /* Fully recompute DDB on first atomic commit */
4376 dev_priv->wm.distrust_bios_wm = true;
4377 } else {
4378 /* Easy/common case; just sanitize DDB now if everything off */
4379 memset(ddb, 0, sizeof(*ddb));
4380 }
3078999f
PB		 4381}
4382
243e6a44
VS		 4383static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4384{
4385 struct drm_device *dev = crtc->dev;
fac5e23e 4386 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4387 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4389 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4390 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4391 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4392 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4393 [PIPE_A] = WM0_PIPEA_ILK,
4394 [PIPE_B] = WM0_PIPEB_ILK,
4395 [PIPE_C] = WM0_PIPEC_IVB,
4396 };
4397
4398 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4399 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4400 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4401
15606534
VS		 4402 memset(active, 0, sizeof(*active));
4403
3ef00284 4404 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4405
4406 if (active->pipe_enabled) {
243e6a44
VS		 4407 u32 tmp = hw->wm_pipe[pipe];
4408
4409 /*
4410 * For active pipes LP0 watermark is marked as
4411 * enabled, and LP1+ watermaks as disabled since
4412 * we can't really reverse compute them in case
4413 * multiple pipes are active.
4414 */
4415 active->wm[0].enable = true;
4416 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4417 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4418 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4419 active->linetime = hw->wm_linetime[pipe];
4420 } else {
5db94019 4421 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4422
4423 /*
4424 * For inactive pipes, all watermark levels
4425 * should be marked as enabled but zeroed,
4426 * which is what we'd compute them to.
4427 */
4428 for (level = 0; level <= max_level; level++)
4429 active->wm[level].enable = true;
4430 }
4e0963c7
MR		 4431
4432 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4433}
4434
6eb1a681
VS		 4435#define _FW_WM(value, plane) \
4436 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4437#define _FW_WM_VLV(value, plane) \
4438 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4439
4440static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4441 struct vlv_wm_values *wm)
4442{
4443 enum pipe pipe;
4444 uint32_t tmp;
4445
4446 for_each_pipe(dev_priv, pipe) {
4447 tmp = I915_READ(VLV_DDL(pipe));
4448
1b31389c 4449 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6eb1a681 4450 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
1b31389c 4451 wm->ddl[pipe].plane[PLANE_CURSOR] =
6eb1a681 4452 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
1b31389c 4453 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6eb1a681 4454 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
1b31389c 4455 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6eb1a681
VS		 4456 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4457 }
4458
4459 tmp = I915_READ(DSPFW1);
4460 wm->sr.plane = _FW_WM(tmp, SR);
1b31389c
VS		 4461 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
4462 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
4463 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6eb1a681
VS		 4464
4465 tmp = I915_READ(DSPFW2);
1b31389c
VS		 4466 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
4467 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
4468 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6eb1a681
VS		 4469
4470 tmp = I915_READ(DSPFW3);
4471 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4472
4473 if (IS_CHERRYVIEW(dev_priv)) {
4474 tmp = I915_READ(DSPFW7_CHV);
1b31389c
VS		 4475 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4476 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6eb1a681
VS		 4477
4478 tmp = I915_READ(DSPFW8_CHV);
1b31389c
VS		 4479 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
4480 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6eb1a681
VS		 4481
4482 tmp = I915_READ(DSPFW9_CHV);
1b31389c
VS		 4483 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
4484 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6eb1a681
VS		 4485
4486 tmp = I915_READ(DSPHOWM);
4487 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
1b31389c
VS		 4488 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4489 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4490 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
4491 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4492 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4493 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4494 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4495 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4496 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6eb1a681
VS		 4497 } else {
4498 tmp = I915_READ(DSPFW7);
1b31389c
VS		 4499 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4500 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6eb1a681
VS		 4501
4502 tmp = I915_READ(DSPHOWM);
4503 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
1b31389c
VS		 4504 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4505 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4506 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4507 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4508 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4509 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6eb1a681
VS		 4510 }
4511}
4512
4513#undef _FW_WM
4514#undef _FW_WM_VLV
4515
4516void vlv_wm_get_hw_state(struct drm_device *dev)
4517{
4518 struct drm_i915_private *dev_priv = to_i915(dev);
4519 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4520 struct intel_plane *plane;
4521 enum pipe pipe;
4522 u32 val;
4523
4524 vlv_read_wm_values(dev_priv, wm);
4525
49845a23
VS		 4526 for_each_intel_plane(dev, plane)
4527 plane->wm.fifo_size = vlv_get_fifo_size(plane);
6eb1a681
VS		 4528
4529 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4530 wm->level = VLV_WM_LEVEL_PM2;
4531
4532 if (IS_CHERRYVIEW(dev_priv)) {
4533 mutex_lock(&dev_priv->rps.hw_lock);
4534
4535 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4536 if (val & DSP_MAXFIFO_PM5_ENABLE)
4537 wm->level = VLV_WM_LEVEL_PM5;
4538
58590c14
VS		 4539 /*
4540 * If DDR DVFS is disabled in the BIOS, Punit
4541 * will never ack the request. So if that happens
4542 * assume we don't have to enable/disable DDR DVFS
4543 * dynamically. To test that just set the REQ_ACK
4544 * bit to poke the Punit, but don't change the
4545 * HIGH/LOW bits so that we don't actually change
4546 * the current state.
4547 */
6eb1a681 4548 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4549 val |= FORCE_DDR_FREQ_REQ_ACK;
4550 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4551
4552 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4553 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4554 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4555 "assuming DDR DVFS is disabled\n");
4556 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4557 } else {
4558 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4559 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4560 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4561 }
6eb1a681
VS		 4562
4563 mutex_unlock(&dev_priv->rps.hw_lock);
4564 }
4565
4566 for_each_pipe(dev_priv, pipe)
4567 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
1b31389c
VS		 4568 pipe_name(pipe),
4569 wm->pipe[pipe].plane[PLANE_PRIMARY],
4570 wm->pipe[pipe].plane[PLANE_CURSOR],
4571 wm->pipe[pipe].plane[PLANE_SPRITE0],
4572 wm->pipe[pipe].plane[PLANE_SPRITE1]);
6eb1a681
VS		 4573
4574 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4575 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4576}
4577
243e6a44
VS		 4578void ilk_wm_get_hw_state(struct drm_device *dev)
4579{
fac5e23e 4580 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4581 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4582 struct drm_crtc *crtc;
4583
70e1e0ec 4584 for_each_crtc(dev, crtc)
243e6a44
VS		 4585 ilk_pipe_wm_get_hw_state(crtc);
4586
4587 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4588 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4589 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4590
4591 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
175fded1 4592 if (INTEL_GEN(dev_priv) >= 7) {
cfa7698b
VS		 4593 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4594 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4595 }
243e6a44 4596
8652744b 4597 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4598 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4599 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4600 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4601 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4602 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4603
4604 hw->enable_fbc_wm =
4605 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4606}
4607
b445e3b0
ED		 4608/**
4609 * intel_update_watermarks - update FIFO watermark values based on current modes
4610 *
4611 * Calculate watermark values for the various WM regs based on current mode
4612 * and plane configuration.
4613 *
4614 * There are several cases to deal with here:
4615 * - normal (i.e. non-self-refresh)
4616 * - self-refresh (SR) mode
4617 * - lines are large relative to FIFO size (buffer can hold up to 2)
4618 * - lines are small relative to FIFO size (buffer can hold more than 2
4619 * lines), so need to account for TLB latency
4620 *
4621 * The normal calculation is:
4622 * watermark = dotclock * bytes per pixel * latency
4623 * where latency is platform & configuration dependent (we assume pessimal
4624 * values here).
4625 *
4626 * The SR calculation is:
4627 * watermark = (trunc(latency/line time)+1) * surface width *
4628 * bytes per pixel
4629 * where
4630 * line time = htotal / dotclock
4631 * surface width = hdisplay for normal plane and 64 for cursor
4632 * and latency is assumed to be high, as above.
4633 *
4634 * The final value programmed to the register should always be rounded up,
4635 * and include an extra 2 entries to account for clock crossings.
4636 *
4637 * We don't use the sprite, so we can ignore that. And on Crestline we have
4638 * to set the non-SR watermarks to 8.
4639 */
432081bc 4640void intel_update_watermarks(struct intel_crtc *crtc)
b445e3b0 4641{
432081bc 4642 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0
ED		 4643
4644 if (dev_priv->display.update_wm)
46ba614c 4645 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4646}
4647
e2828914 4648/*
9270388e 4649 * Lock protecting IPS related data structures
9270388e
DV		 4650 */
4651DEFINE_SPINLOCK(mchdev_lock);
4652
4653/* Global for IPS driver to get at the current i915 device. Protected by
4654 * mchdev_lock. */
4655static struct drm_i915_private *i915_mch_dev;
4656
91d14251 4657bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4658{
2b4e57bd
ED		 4659 u16 rgvswctl;
4660
9270388e
DV		 4661 assert_spin_locked(&mchdev_lock);
4662
2b4e57bd
ED		 4663 rgvswctl = I915_READ16(MEMSWCTL);
4664 if (rgvswctl & MEMCTL_CMD_STS) {
4665 DRM_DEBUG("gpu busy, RCS change rejected\n");
4666 return false; /* still busy with another command */
4667 }
4668
4669 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4670 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4671 I915_WRITE16(MEMSWCTL, rgvswctl);
4672 POSTING_READ16(MEMSWCTL);
4673
4674 rgvswctl |= MEMCTL_CMD_STS;
4675 I915_WRITE16(MEMSWCTL, rgvswctl);
4676
4677 return true;
4678}
4679
91d14251 4680static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4681{
84f1b20f 4682 u32 rgvmodectl;
2b4e57bd
ED		 4683 u8 fmax, fmin, fstart, vstart;
4684
9270388e
DV		 4685 spin_lock_irq(&mchdev_lock);
4686
84f1b20f
TU		 4687 rgvmodectl = I915_READ(MEMMODECTL);
4688
2b4e57bd
ED		 4689 /* Enable temp reporting */
4690 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4691 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4692
4693 /* 100ms RC evaluation intervals */
4694 I915_WRITE(RCUPEI, 100000);
4695 I915_WRITE(RCDNEI, 100000);
4696
4697 /* Set max/min thresholds to 90ms and 80ms respectively */
4698 I915_WRITE(RCBMAXAVG, 90000);
4699 I915_WRITE(RCBMINAVG, 80000);
4700
4701 I915_WRITE(MEMIHYST, 1);
4702
4703 /* Set up min, max, and cur for interrupt handling */
4704 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4705 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4706 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4707 MEMMODE_FSTART_SHIFT;
4708
616847e7 4709 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4710 PXVFREQ_PX_SHIFT;
4711
20e4d407
DV		 4712 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4713 dev_priv->ips.fstart = fstart;
2b4e57bd 4714
20e4d407
DV		 4715 dev_priv->ips.max_delay = fstart;
4716 dev_priv->ips.min_delay = fmin;
4717 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4718
4719 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4720 fmax, fmin, fstart);
4721
4722 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4723
4724 /*
4725 * Interrupts will be enabled in ironlake_irq_postinstall
4726 */
4727
4728 I915_WRITE(VIDSTART, vstart);
4729 POSTING_READ(VIDSTART);
4730
4731 rgvmodectl |= MEMMODE_SWMODE_EN;
4732 I915_WRITE(MEMMODECTL, rgvmodectl);
4733
9270388e 4734 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4735 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4736 mdelay(1);
2b4e57bd 4737
91d14251 4738 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4739
7d81c3e0
VS		 4740 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4741 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4742 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4743 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4744 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4745
4746 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4747}
4748
91d14251 4749static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4750{
9270388e
DV		 4751 u16 rgvswctl;
4752
4753 spin_lock_irq(&mchdev_lock);
4754
4755 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4756
4757 /* Ack interrupts, disable EFC interrupt */
4758 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4759 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4760 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4761 I915_WRITE(DEIIR, DE_PCU_EVENT);
4762 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4763
4764 /* Go back to the starting frequency */
91d14251 4765 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4766 mdelay(1);
2b4e57bd
ED		 4767 rgvswctl |= MEMCTL_CMD_STS;
4768 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4769 mdelay(1);
2b4e57bd 4770
9270388e 4771 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4772}
4773
acbe9475
DV		 4774/* There's a funny hw issue where the hw returns all 0 when reading from
4775 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4776 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4777 * all limits and the gpu stuck at whatever frequency it is at atm).
4778 */
74ef1173 4779static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4780{
7b9e0ae6 4781 u32 limits;
2b4e57bd 4782
20b46e59
DV		 4783 /* Only set the down limit when we've reached the lowest level to avoid
4784 * getting more interrupts, otherwise leave this clear. This prevents a
4785 * race in the hw when coming out of rc6: There's a tiny window where
4786 * the hw runs at the minimal clock before selecting the desired
4787 * frequency, if the down threshold expires in that window we will not
4788 * receive a down interrupt. */
2d1fe073 4789 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4790 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4791 if (val <= dev_priv->rps.min_freq_softlimit)
4792 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4793 } else {
4794 limits = dev_priv->rps.max_freq_softlimit << 24;
4795 if (val <= dev_priv->rps.min_freq_softlimit)
4796 limits |= dev_priv->rps.min_freq_softlimit << 16;
4797 }
20b46e59
DV		 4798
4799 return limits;
4800}
4801
dd75fdc8
CW		 4802static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4803{
4804 int new_power;
8a586437
AG		 4805 u32 threshold_up = 0, threshold_down = 0; /* in % */
4806 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4807
4808 new_power = dev_priv->rps.power;
4809 switch (dev_priv->rps.power) {
4810 case LOW_POWER:
a72b5623
CW		 4811 if (val > dev_priv->rps.efficient_freq + 1 &&
4812 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4813 new_power = BETWEEN;
4814 break;
4815
4816 case BETWEEN:
a72b5623
CW		 4817 if (val <= dev_priv->rps.efficient_freq &&
4818 val < dev_priv->rps.cur_freq)
dd75fdc8 4819 new_power = LOW_POWER;
a72b5623
CW		 4820 else if (val >= dev_priv->rps.rp0_freq &&
4821 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4822 new_power = HIGH_POWER;
4823 break;
4824
4825 case HIGH_POWER:
a72b5623
CW		 4826 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4827 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4828 new_power = BETWEEN;
4829 break;
4830 }
4831 /* Max/min bins are special */
aed242ff 4832 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4833 new_power = LOW_POWER;
aed242ff 4834 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4835 new_power = HIGH_POWER;
4836 if (new_power == dev_priv->rps.power)
4837 return;
4838
4839 /* Note the units here are not exactly 1us, but 1280ns. */
4840 switch (new_power) {
4841 case LOW_POWER:
4842 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4843 ei_up = 16000;
4844 threshold_up = 95;
dd75fdc8
CW		 4845
4846 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4847 ei_down = 32000;
4848 threshold_down = 85;
dd75fdc8
CW		 4849 break;
4850
4851 case BETWEEN:
4852 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4853 ei_up = 13000;
4854 threshold_up = 90;
dd75fdc8
CW		 4855
4856 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4857 ei_down = 32000;
4858 threshold_down = 75;
dd75fdc8
CW		 4859 break;
4860
4861 case HIGH_POWER:
4862 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4863 ei_up = 10000;
4864 threshold_up = 85;
dd75fdc8
CW		 4865
4866 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4867 ei_down = 32000;
4868 threshold_down = 60;
dd75fdc8
CW		 4869 break;
4870 }
4871
8a586437 4872 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4873 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4874 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4875 GT_INTERVAL_FROM_US(dev_priv,
4876 ei_up * threshold_up / 100));
8a586437
AG		 4877
4878 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4879 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4880 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4881 GT_INTERVAL_FROM_US(dev_priv,
4882 ei_down * threshold_down / 100));
4883
4884 I915_WRITE(GEN6_RP_CONTROL,
4885 GEN6_RP_MEDIA_TURBO |
4886 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4887 GEN6_RP_MEDIA_IS_GFX |
4888 GEN6_RP_ENABLE |
4889 GEN6_RP_UP_BUSY_AVG |
4890 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4891
dd75fdc8 4892 dev_priv->rps.power = new_power;
8fb55197
CW		 4893 dev_priv->rps.up_threshold = threshold_up;
4894 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4895 dev_priv->rps.last_adj = 0;
4896}
4897
2876ce73
CW		 4898static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4899{
4900 u32 mask = 0;
4901
4902 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4903 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4904 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4905 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4906
7b3c29f6
CW		 4907 mask &= dev_priv->pm_rps_events;
4908
59d02a1f 4909 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4910}
4911
b8a5ff8d
JM		 4912/* gen6_set_rps is called to update the frequency request, but should also be
4913 * called when the range (min_delay and max_delay) is modified so that we can
4914 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
9fcee2f7 4915static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4916{
4fc688ce 4917 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4918 WARN_ON(val > dev_priv->rps.max_freq);
4919 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4920
eb64cad1
CW		 4921 /* min/max delay may still have been modified so be sure to
4922 * write the limits value.
4923 */
4924 if (val != dev_priv->rps.cur_freq) {
4925 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4926
dc97997a 4927 if (IS_GEN9(dev_priv))
5704195c
AG		 4928 I915_WRITE(GEN6_RPNSWREQ,
4929 GEN9_FREQUENCY(val));
dc97997a 4930 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4931 I915_WRITE(GEN6_RPNSWREQ,
4932 HSW_FREQUENCY(val));
4933 else
4934 I915_WRITE(GEN6_RPNSWREQ,
4935 GEN6_FREQUENCY(val) |
4936 GEN6_OFFSET(0) |
4937 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4938 }
7b9e0ae6 4939
7b9e0ae6
CW		 4940 /* Make sure we continue to get interrupts
4941 * until we hit the minimum or maximum frequencies.
4942 */
74ef1173 4943 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4944 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4945
d5570a72
BW		 4946 POSTING_READ(GEN6_RPNSWREQ);
4947
b39fb297 4948 dev_priv->rps.cur_freq = val;
0f94592e 4949 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
9fcee2f7
CW		 4950
4951 return 0;
2b4e57bd
ED		 4952}
4953
9fcee2f7 4954static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4955{
9fcee2f7
CW		 4956 int err;
4957
ffe02b40 4958 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4959 WARN_ON(val > dev_priv->rps.max_freq);
4960 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4961
dc97997a 4962 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4963 "Odd GPU freq value\n"))
4964 val &= ~1;
4965
cd25dd5b
D		 4966 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4967
8fb55197 4968 if (val != dev_priv->rps.cur_freq) {
9fcee2f7
CW		 4969 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4970 if (err)
4971 return err;
4972
db4c5e0b 4973 gen6_set_rps_thresholds(dev_priv, val);
8fb55197 4974 }
ffe02b40 4975
ffe02b40
VS		 4976 dev_priv->rps.cur_freq = val;
4977 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
9fcee2f7
CW		 4978
4979 return 0;
ffe02b40
VS		 4980}
4981
a7f6e231 4982/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4983 *
4984 * * If Gfx is Idle, then
a7f6e231
D		 4985 * 1. Forcewake Media well.
4986 * 2. Request idle freq.
4987 * 3. Release Forcewake of Media well.
76c3552f
D		 4988*/
4989static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4990{
aed242ff 4991 u32 val = dev_priv->rps.idle_freq;
9fcee2f7 4992 int err;
5549d25f 4993
aed242ff 4994 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4995 return;
4996
c9efef7b
CW		 4997 /* The punit delays the write of the frequency and voltage until it
4998 * determines the GPU is awake. During normal usage we don't want to
4999 * waste power changing the frequency if the GPU is sleeping (rc6).
5000 * However, the GPU and driver is now idle and we do not want to delay
5001 * switching to minimum voltage (reducing power whilst idle) as we do
5002 * not expect to be woken in the near future and so must flush the
5003 * change by waking the device.
5004 *
5005 * We choose to take the media powerwell (either would do to trick the
5006 * punit into committing the voltage change) as that takes a lot less
5007 * power than the render powerwell.
5008 */
a7f6e231 5009 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
9fcee2f7 5010 err = valleyview_set_rps(dev_priv, val);
a7f6e231 5011 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
9fcee2f7
CW		 5012
5013 if (err)
5014 DRM_ERROR("Failed to set RPS for idle\n");
76c3552f
D		 5015}
5016
43cf3bf0
CW		 5017void gen6_rps_busy(struct drm_i915_private *dev_priv)
5018{
5019 mutex_lock(&dev_priv->rps.hw_lock);
5020 if (dev_priv->rps.enabled) {
bd64818d
CW		 5021 u8 freq;
5022
43cf3bf0
CW		 5023 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5024 gen6_rps_reset_ei(dev_priv);
5025 I915_WRITE(GEN6_PMINTRMSK,
5026 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5027
c33d247d
CW		 5028 gen6_enable_rps_interrupts(dev_priv);
5029
bd64818d
CW		 5030 /* Use the user's desired frequency as a guide, but for better
5031 * performance, jump directly to RPe as our starting frequency.
5032 */
5033 freq = max(dev_priv->rps.cur_freq,
5034 dev_priv->rps.efficient_freq);
5035
9fcee2f7 5036 if (intel_set_rps(dev_priv,
bd64818d 5037 clamp(freq,
9fcee2f7
CW		 5038 dev_priv->rps.min_freq_softlimit,
5039 dev_priv->rps.max_freq_softlimit)))
5040 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
43cf3bf0
CW		 5041 }
5042 mutex_unlock(&dev_priv->rps.hw_lock);
5043}
5044
b29c19b6
CW		 5045void gen6_rps_idle(struct drm_i915_private *dev_priv)
5046{
c33d247d
CW		 5047 /* Flush our bottom-half so that it does not race with us
5048 * setting the idle frequency and so that it is bounded by
5049 * our rpm wakeref. And then disable the interrupts to stop any
5050 * futher RPS reclocking whilst we are asleep.
5051 */
5052 gen6_disable_rps_interrupts(dev_priv);
5053
b29c19b6 5054 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5055 if (dev_priv->rps.enabled) {
dc97997a 5056 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5057 vlv_set_rps_idle(dev_priv);
7526ed79 5058 else
dc97997a 5059 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5060 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5061 I915_WRITE(GEN6_PMINTRMSK,
5062 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5063 }
8d3afd7d 5064 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5065
8d3afd7d 5066 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5067 while (!list_empty(&dev_priv->rps.clients))
5068 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5069 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5070}
5071
1854d5ca 5072void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5073 struct intel_rps_client *rps,
5074 unsigned long submitted)
b29c19b6 5075{
8d3afd7d
CW		 5076 /* This is intentionally racy! We peek at the state here, then
5077 * validate inside the RPS worker.
5078 */
67d97da3 5079 if (!(dev_priv->gt.awake &&
8d3afd7d 5080 dev_priv->rps.enabled &&
29ecd78d 5081 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5082 return;
43cf3bf0 5083
e61b9958
CW		 5084 /* Force a RPS boost (and don't count it against the client) if
5085 * the GPU is severely congested.
5086 */
d0bc54f2 5087 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5088 rps = NULL;
5089
8d3afd7d
CW		 5090 spin_lock(&dev_priv->rps.client_lock);
5091 if (rps == NULL || list_empty(&rps->link)) {
5092 spin_lock_irq(&dev_priv->irq_lock);
5093 if (dev_priv->rps.interrupts_enabled) {
5094 dev_priv->rps.client_boost = true;
c33d247d 5095 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5096 }
5097 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5098
2e1b8730
CW		 5099 if (rps != NULL) {
5100 list_add(&rps->link, &dev_priv->rps.clients);
5101 rps->boosts++;
1854d5ca
CW		 5102 } else
5103 dev_priv->rps.boosts++;
c0951f0c 5104 }
8d3afd7d 5105 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5106}
5107
9fcee2f7 5108int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5109{
9fcee2f7
CW		 5110 int err;
5111
dc97997a 5112 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
9fcee2f7 5113 err = valleyview_set_rps(dev_priv, val);
ffe02b40 5114 else
9fcee2f7
CW		 5115 err = gen6_set_rps(dev_priv, val);
5116
5117 return err;
0a073b84
JB		 5118}
5119
dc97997a 5120static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5121{
20e49366 5122 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5123 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5124}
5125
dc97997a 5126static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5127{
2030d684
AG		 5128 I915_WRITE(GEN6_RP_CONTROL, 0);
5129}
5130
dc97997a 5131static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5132{
d20d4f0c 5133 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5134 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5135 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5136}
5137
dc97997a 5138static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5139{
38807746
D		 5140 I915_WRITE(GEN6_RC_CONTROL, 0);
5141}
5142
dc97997a 5143static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5144{
98a2e5f9
D		 5145 /* we're doing forcewake before Disabling RC6,
5146 * This what the BIOS expects when going into suspend */
59bad947 5147 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5148
44fc7d5c 5149 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5150
59bad947 5151 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5152}
5153
dc97997a 5154static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5155{
dc97997a 5156 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5157 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5158 mode = GEN6_RC_CTL_RC6_ENABLE;
5159 else
5160 mode = 0;
5161 }
dc97997a 5162 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5163 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5164 "RC6 %s RC6p %s RC6pp %s\n",
5165 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5166 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5167 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5168
5169 else
b99d49cc
ID		 5170 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5171 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5172}
5173
dc97997a 5174static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5175{
72e96d64 5176 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5177 bool enable_rc6 = true;
5178 unsigned long rc6_ctx_base;
fc619841
ID		 5179 u32 rc_ctl;
5180 int rc_sw_target;
5181
5182 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5183 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5184 RC_SW_TARGET_STATE_SHIFT;
5185 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5186 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5187 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5188 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5189 rc_sw_target);
274008e8
SAK		 5190
5191 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5192 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5193 enable_rc6 = false;
5194 }
5195
5196 /*
5197 * The exact context size is not known for BXT, so assume a page size
5198 * for this check.
5199 */
5200 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5201 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5202 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5203 ggtt->stolen_reserved_size))) {
b99d49cc 5204 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5205 enable_rc6 = false;
5206 }
5207
5208 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5209 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5210 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5211 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5212 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5213 enable_rc6 = false;
5214 }
5215
fc619841
ID		 5216 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5217 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5218 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5219 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5220 enable_rc6 = false;
5221 }
5222
5223 if (!I915_READ(GEN6_GFXPAUSE)) {
5224 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5225 enable_rc6 = false;
5226 }
5227
5228 if (!I915_READ(GEN8_MISC_CTRL0)) {
5229 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5230 enable_rc6 = false;
5231 }
5232
5233 return enable_rc6;
5234}
5235
dc97997a 5236int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5237{
e7d66d89 5238 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5239 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5240 return 0;
5241
274008e8
SAK		 5242 if (!enable_rc6)
5243 return 0;
5244
cc3f90f0 5245 if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5246 DRM_INFO("RC6 disabled by BIOS\n");
5247 return 0;
5248 }
5249
456470eb 5250 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5251 if (enable_rc6 >= 0) {
5252 int mask;
5253
dc97997a 5254 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5255 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5256 INTEL_RC6pp_ENABLE;
5257 else
5258 mask = INTEL_RC6_ENABLE;
5259
5260 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5261 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5262 "(requested %d, valid %d)\n",
5263 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5264
5265 return enable_rc6 & mask;
5266 }
2b4e57bd 5267
dc97997a 5268 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5269 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5270
5271 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5272}
5273
dc97997a 5274static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5275{
5276 /* All of these values are in units of 50MHz */
773ea9a8 5277
93ee2920 5278 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
cc3f90f0 5279 if (IS_GEN9_LP(dev_priv)) {
773ea9a8 5280 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5281 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5282 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5283 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5284 } else {
773ea9a8 5285 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5286 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5287 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5288 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5289 }
3280e8b0 5290 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5291 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5292
93ee2920 5293 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a 5294 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
b976dc53 5295 IS_GEN9_BC(dev_priv)) {
773ea9a8
CW		 5296 u32 ddcc_status = 0;
5297
5298 if (sandybridge_pcode_read(dev_priv,
5299 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5300 &ddcc_status) == 0)
93ee2920 5301 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5302 clamp_t(u8,
5303 ((ddcc_status >> 8) & 0xff),
5304 dev_priv->rps.min_freq,
5305 dev_priv->rps.max_freq);
93ee2920
TR		 5306 }
5307
b976dc53 5308 if (IS_GEN9_BC(dev_priv)) {
c5e0688c 5309 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5310 * the natural hardware unit for SKL
5311 */
c5e0688c
AG		 5312 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5313 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5314 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5315 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5316 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5317 }
3280e8b0
BW		 5318}
5319
3a45b05c 5320static void reset_rps(struct drm_i915_private *dev_priv,
9fcee2f7 5321 int (*set)(struct drm_i915_private *, u8))
3a45b05c
CW		 5322{
5323 u8 freq = dev_priv->rps.cur_freq;
5324
5325 /* force a reset */
5326 dev_priv->rps.power = -1;
5327 dev_priv->rps.cur_freq = -1;
5328
9fcee2f7
CW		 5329 if (set(dev_priv, freq))
5330 DRM_ERROR("Failed to reset RPS to initial values\n");
3a45b05c
CW		 5331}
5332
b6fef0ef 5333/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5334static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5335{
b6fef0ef
JB		 5336 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5337
0beb059a
AG		 5338 /* Program defaults and thresholds for RPS*/
5339 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5340 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5341
5342 /* 1 second timeout*/
5343 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5344 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5345
b6fef0ef 5346 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5347
0beb059a
AG		 5348 /* Leaning on the below call to gen6_set_rps to program/setup the
5349 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5350 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5351 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5352
5353 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5354}
5355
dc97997a 5356static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5357{
e2f80391 5358 struct intel_engine_cs *engine;
3b3f1650 5359 enum intel_engine_id id;
20e49366 5360 uint32_t rc6_mask = 0;
20e49366
ZW		 5361
5362 /* 1a: Software RC state - RC0 */
5363 I915_WRITE(GEN6_RC_STATE, 0);
5364
5365 /* 1b: Get forcewake during program sequence. Although the driver
5366 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5367 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5368
5369 /* 2a: Disable RC states. */
5370 I915_WRITE(GEN6_RC_CONTROL, 0);
5371
5372 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5373
5374 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5375 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5376 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5377 else
5378 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5379 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5380 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5381 for_each_engine(engine, dev_priv, id)
e2f80391 5382 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5383
1a3d1898 5384 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5385 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5386
20e49366 5387 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5388
38c23527
ZW		 5389 /* 2c: Program Coarse Power Gating Policies. */
5390 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5391 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5392
20e49366 5393 /* 3a: Enable RC6 */
dc97997a 5394 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5395 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5396 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
1c044f9b
CW		 5397 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5398 I915_WRITE(GEN6_RC_CONTROL,
5399 GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
20e49366 5400
cb07bae0
SK		 5401 /*
5402 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5403 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5404 */
dc97997a 5405 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5406 I915_WRITE(GEN9_PG_ENABLE, 0);
5407 else
5408 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5409 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5410
59bad947 5411 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5412}
5413
dc97997a 5414static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5415{
e2f80391 5416 struct intel_engine_cs *engine;
3b3f1650 5417 enum intel_engine_id id;
93ee2920 5418 uint32_t rc6_mask = 0;
6edee7f3
BW		 5419
5420 /* 1a: Software RC state - RC0 */
5421 I915_WRITE(GEN6_RC_STATE, 0);
5422
5423 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5424 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5425 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5426
5427 /* 2a: Disable RC states. */
5428 I915_WRITE(GEN6_RC_CONTROL, 0);
5429
6edee7f3
BW		 5430 /* 2b: Program RC6 thresholds.*/
5431 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5432 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5433 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5434 for_each_engine(engine, dev_priv, id)
e2f80391 5435 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5436 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5437 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5438 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5439 else
5440 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5441
5442 /* 3: Enable RC6 */
dc97997a 5443 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5444 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5445 intel_print_rc6_info(dev_priv, rc6_mask);
5446 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5447 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5448 GEN7_RC_CTL_TO_MODE |
5449 rc6_mask);
5450 else
5451 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5452 GEN6_RC_CTL_EI_MODE(1) |
5453 rc6_mask);
6edee7f3
BW		 5454
5455 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5456 I915_WRITE(GEN6_RPNSWREQ,
5457 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5458 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5459 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5460 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5461 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5462
5463 /* Docs recommend 900MHz, and 300 MHz respectively */
5464 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5465 dev_priv->rps.max_freq_softlimit << 24 |
5466 dev_priv->rps.min_freq_softlimit << 16);
5467
5468 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5469 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5470 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5471 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5472
5473 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5474
5475 /* 5: Enable RPS */
7526ed79
DV		 5476 I915_WRITE(GEN6_RP_CONTROL,
5477 GEN6_RP_MEDIA_TURBO |
5478 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5479 GEN6_RP_MEDIA_IS_GFX |
5480 GEN6_RP_ENABLE |
5481 GEN6_RP_UP_BUSY_AVG |
5482 GEN6_RP_DOWN_IDLE_AVG);
5483
5484 /* 6: Ring frequency + overclocking (our driver does this later */
5485
3a45b05c 5486 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5487
59bad947 5488 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5489}
5490
dc97997a 5491static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5492{
e2f80391 5493 struct intel_engine_cs *engine;
3b3f1650 5494 enum intel_engine_id id;
99ac9612 5495 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5496 u32 gtfifodbg;
2b4e57bd 5497 int rc6_mode;
b4ac5afc 5498 int ret;
2b4e57bd 5499
4fc688ce 5500 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5501
2b4e57bd
ED		 5502 /* Here begins a magic sequence of register writes to enable
5503 * auto-downclocking.
5504 *
5505 * Perhaps there might be some value in exposing these to
5506 * userspace...
5507 */
5508 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5509
5510 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5511 gtfifodbg = I915_READ(GTFIFODBG);
5512 if (gtfifodbg) {
2b4e57bd
ED		 5513 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5514 I915_WRITE(GTFIFODBG, gtfifodbg);
5515 }
5516
59bad947 5517 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5518
5519 /* disable the counters and set deterministic thresholds */
5520 I915_WRITE(GEN6_RC_CONTROL, 0);
5521
5522 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5523 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5524 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5525 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5526 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5527
3b3f1650 5528 for_each_engine(engine, dev_priv, id)
e2f80391 5529 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5530
5531 I915_WRITE(GEN6_RC_SLEEP, 0);
5532 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5533 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5534 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5535 else
5536 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5537 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5538 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5539
5a7dc92a 5540 /* Check if we are enabling RC6 */
dc97997a 5541 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5542 if (rc6_mode & INTEL_RC6_ENABLE)
5543 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5544
5a7dc92a 5545 /* We don't use those on Haswell */
dc97997a 5546 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5547 if (rc6_mode & INTEL_RC6p_ENABLE)
5548 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5549
5a7dc92a
ED		 5550 if (rc6_mode & INTEL_RC6pp_ENABLE)
5551 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5552 }
2b4e57bd 5553
dc97997a 5554 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5555
5556 I915_WRITE(GEN6_RC_CONTROL,
5557 rc6_mask |
5558 GEN6_RC_CTL_EI_MODE(1) |
5559 GEN6_RC_CTL_HW_ENABLE);
5560
dd75fdc8
CW		 5561 /* Power down if completely idle for over 50ms */
5562 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5563 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5564
3a45b05c 5565 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5566
31643d54
BW		 5567 rc6vids = 0;
5568 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5569 if (IS_GEN6(dev_priv) && ret) {
31643d54 5570 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5571 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5572 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5573 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5574 rc6vids &= 0xffff00;
5575 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5576 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5577 if (ret)
5578 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5579 }
5580
59bad947 5581 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5582}
5583
fb7404e8 5584static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5585{
5586 int min_freq = 15;
3ebecd07
CW		 5587 unsigned int gpu_freq;
5588 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5589 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5590 int scaling_factor = 180;
eda79642 5591 struct cpufreq_policy *policy;
2b4e57bd 5592
4fc688ce 5593 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5594
eda79642
BW		 5595 policy = cpufreq_cpu_get(0);
5596 if (policy) {
5597 max_ia_freq = policy->cpuinfo.max_freq;
5598 cpufreq_cpu_put(policy);
5599 } else {
5600 /*
5601 * Default to measured freq if none found, PCU will ensure we
5602 * don't go over
5603 */
2b4e57bd 5604 max_ia_freq = tsc_khz;
eda79642 5605 }
2b4e57bd
ED		 5606
5607 /* Convert from kHz to MHz */
5608 max_ia_freq /= 1000;
5609
153b4b95 5610 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5611 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5612 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5613
b976dc53 5614 if (IS_GEN9_BC(dev_priv)) {
4c8c7743
AG		 5615 /* Convert GT frequency to 50 HZ units */
5616 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5617 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5618 } else {
5619 min_gpu_freq = dev_priv->rps.min_freq;
5620 max_gpu_freq = dev_priv->rps.max_freq;
5621 }
5622
2b4e57bd
ED		 5623 /*
5624 * For each potential GPU frequency, load a ring frequency we'd like
5625 * to use for memory access. We do this by specifying the IA frequency
5626 * the PCU should use as a reference to determine the ring frequency.
5627 */
4c8c7743
AG		 5628 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5629 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5630 unsigned int ia_freq = 0, ring_freq = 0;
5631
b976dc53 5632 if (IS_GEN9_BC(dev_priv)) {
4c8c7743
AG		 5633 /*
5634 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5635 * No floor required for ring frequency on SKL.
5636 */
5637 ring_freq = gpu_freq;
dc97997a 5638 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5639 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5640 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5641 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5642 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5643 ring_freq = max(min_ring_freq, ring_freq);
5644 /* leave ia_freq as the default, chosen by cpufreq */
5645 } else {
5646 /* On older processors, there is no separate ring
5647 * clock domain, so in order to boost the bandwidth
5648 * of the ring, we need to upclock the CPU (ia_freq).
5649 *
5650 * For GPU frequencies less than 750MHz,
5651 * just use the lowest ring freq.
5652 */
5653 if (gpu_freq < min_freq)
5654 ia_freq = 800;
5655 else
5656 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5657 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5658 }
2b4e57bd 5659
42c0526c
BW		 5660 sandybridge_pcode_write(dev_priv,
5661 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5662 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5663 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5664 gpu_freq);
2b4e57bd 5665 }
2b4e57bd
ED		 5666}
5667
03af2045 5668static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5669{
5670 u32 val, rp0;
5671
5b5929cb 5672 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5673
43b67998 5674 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5675 case 8:
5676 /* (2 * 4) config */
5677 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5678 break;
5679 case 12:
5680 /* (2 * 6) config */
5681 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5682 break;
5683 case 16:
5684 /* (2 * 8) config */
5685 default:
5686 /* Setting (2 * 8) Min RP0 for any other combination */
5687 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5688 break;
095acd5f 5689 }
5b5929cb
JN		 5690
5691 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5692
2b6b3a09
D		 5693 return rp0;
5694}
5695
5696static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5697{
5698 u32 val, rpe;
5699
5700 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5701 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5702
5703 return rpe;
5704}
5705
7707df4a
D		 5706static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5707{
5708 u32 val, rp1;
5709
5b5929cb
JN		 5710 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5711 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5712
7707df4a
D		 5713 return rp1;
5714}
5715
96676fe3
D		 5716static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
5717{
5718 u32 val, rpn;
5719
5720 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
5721 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
5722 FB_GFX_FREQ_FUSE_MASK);
5723
5724 return rpn;
5725}
5726
f8f2b001
D		 5727static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5728{
5729 u32 val, rp1;
5730
5731 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5732
5733 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5734
5735 return rp1;
5736}
5737
03af2045 5738static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5739{
5740 u32 val, rp0;
5741
64936258 5742 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5743
5744 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5745 /* Clamp to max */
5746 rp0 = min_t(u32, rp0, 0xea);
5747
5748 return rp0;
5749}
5750
5751static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5752{
5753 u32 val, rpe;
5754
64936258 5755 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5756 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5757 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5758 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5759
5760 return rpe;
5761}
5762
03af2045 5763static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5764{
36146035
ID		 5765 u32 val;
5766
5767 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5768 /*
5769 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5770 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5771 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5772 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5773 * to make sure it matches what Punit accepts.
5774 */
5775 return max_t(u32, val, 0xc0);
0a073b84
JB		 5776}
5777
ae48434c
ID		 5778/* Check that the pctx buffer wasn't move under us. */
5779static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5780{
5781 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5782
5783 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5784 dev_priv->vlv_pctx->stolen->start);
5785}
5786
38807746
D		 5787
5788/* Check that the pcbr address is not empty. */
5789static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5790{
5791 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5792
5793 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5794}
5795
dc97997a 5796static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5797{
62106b4f 5798 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5799 unsigned long pctx_paddr, paddr;
38807746
D		 5800 u32 pcbr;
5801 int pctx_size = 32*1024;
5802
38807746
D		 5803 pcbr = I915_READ(VLV_PCBR);
5804 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5805 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5806 paddr = (dev_priv->mm.stolen_base +
62106b4f 5807 (ggtt->stolen_size - pctx_size));
38807746
D		 5808
5809 pctx_paddr = (paddr & (~4095));
5810 I915_WRITE(VLV_PCBR, pctx_paddr);
5811 }
ce611ef8
VS		 5812
5813 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5814}
5815
dc97997a 5816static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5817{
c9cddffc
JB		 5818 struct drm_i915_gem_object *pctx;
5819 unsigned long pctx_paddr;
5820 u32 pcbr;
5821 int pctx_size = 24*1024;
5822
5823 pcbr = I915_READ(VLV_PCBR);
5824 if (pcbr) {
5825 /* BIOS set it up already, grab the pre-alloc'd space */
5826 int pcbr_offset;
5827
5828 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
187685cb 5829 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
c9cddffc 5830 pcbr_offset,
190d6cd5 5831 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5832 pctx_size);
5833 goto out;
5834 }
5835
ce611ef8
VS		 5836 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5837
c9cddffc
JB		 5838 /*
5839 * From the Gunit register HAS:
5840 * The Gfx driver is expected to program this register and ensure
5841 * proper allocation within Gfx stolen memory. For example, this
5842 * register should be programmed such than the PCBR range does not
5843 * overlap with other ranges, such as the frame buffer, protected
5844 * memory, or any other relevant ranges.
5845 */
187685cb 5846 pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
c9cddffc
JB		 5847 if (!pctx) {
5848 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5849 goto out;
c9cddffc
JB		 5850 }
5851
5852 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5853 I915_WRITE(VLV_PCBR, pctx_paddr);
5854
5855out:
ce611ef8 5856 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5857 dev_priv->vlv_pctx = pctx;
5858}
5859
dc97997a 5860static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5861{
ae48434c
ID		 5862 if (WARN_ON(!dev_priv->vlv_pctx))
5863 return;
5864
f0cd5182 5865 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5866 dev_priv->vlv_pctx = NULL;
5867}
5868
c30fec65
VS		 5869static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5870{
5871 dev_priv->rps.gpll_ref_freq =
5872 vlv_get_cck_clock(dev_priv, "GPLL ref",
5873 CCK_GPLL_CLOCK_CONTROL,
5874 dev_priv->czclk_freq);
5875
5876 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5877 dev_priv->rps.gpll_ref_freq);
5878}
5879
dc97997a 5880static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5881{
2bb25c17 5882 u32 val;
4e80519e 5883
dc97997a 5884 valleyview_setup_pctx(dev_priv);
4e80519e 5885
c30fec65
VS		 5886 vlv_init_gpll_ref_freq(dev_priv);
5887
2bb25c17
VS		 5888 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5889 switch ((val >> 6) & 3) {
5890 case 0:
5891 case 1:
5892 dev_priv->mem_freq = 800;
5893 break;
5894 case 2:
5895 dev_priv->mem_freq = 1066;
5896 break;
5897 case 3:
5898 dev_priv->mem_freq = 1333;
5899 break;
5900 }
80b83b62 5901 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5902
4e80519e
ID		 5903 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5904 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5905 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5906 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5907 dev_priv->rps.max_freq);
5908
5909 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5910 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5911 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5912 dev_priv->rps.efficient_freq);
5913
f8f2b001
D		 5914 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5915 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5916 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5917 dev_priv->rps.rp1_freq);
5918
4e80519e
ID		 5919 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5920 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5921 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5922 dev_priv->rps.min_freq);
4e80519e
ID		 5923}
5924
dc97997a 5925static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5926{
2bb25c17 5927 u32 val;
2b6b3a09 5928
dc97997a 5929 cherryview_setup_pctx(dev_priv);
2b6b3a09 5930
c30fec65
VS		 5931 vlv_init_gpll_ref_freq(dev_priv);
5932
a580516d 5933 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5934 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5935 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5936
2bb25c17 5937 switch ((val >> 2) & 0x7) {
2bb25c17 5938 case 3:
2bb25c17
VS		 5939 dev_priv->mem_freq = 2000;
5940 break;
bfa7df01 5941 default:
2bb25c17
VS		 5942 dev_priv->mem_freq = 1600;
5943 break;
5944 }
80b83b62 5945 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5946
2b6b3a09
D		 5947 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5948 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5949 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5950 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5951 dev_priv->rps.max_freq);
5952
5953 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5954 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5955 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5956 dev_priv->rps.efficient_freq);
5957
7707df4a
D		 5958 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5959 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5960 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5961 dev_priv->rps.rp1_freq);
5962
96676fe3 5963 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
2b6b3a09 5964 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5965 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5966 dev_priv->rps.min_freq);
5967
1c14762d
VS		 5968 WARN_ONCE((dev_priv->rps.max_freq |
5969 dev_priv->rps.efficient_freq |
5970 dev_priv->rps.rp1_freq |
5971 dev_priv->rps.min_freq) & 1,
5972 "Odd GPU freq values\n");
38807746
D		 5973}
5974
dc97997a 5975static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5976{
dc97997a 5977 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5978}
5979
dc97997a 5980static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5981{
e2f80391 5982 struct intel_engine_cs *engine;
3b3f1650 5983 enum intel_engine_id id;
2b6b3a09 5984 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5985
5986 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5987
297b32ec
VS		 5988 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5989 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5990 if (gtfifodbg) {
5991 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5992 gtfifodbg);
5993 I915_WRITE(GTFIFODBG, gtfifodbg);
5994 }
5995
5996 cherryview_check_pctx(dev_priv);
5997
5998 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5999 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6000 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6001
160614a2
VS		 6002 /* Disable RC states. */
6003 I915_WRITE(GEN6_RC_CONTROL, 0);
6004
38807746
D		 6005 /* 2a: Program RC6 thresholds.*/
6006 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6007 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6008 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6009
3b3f1650 6010 for_each_engine(engine, dev_priv, id)
e2f80391 6011 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6012 I915_WRITE(GEN6_RC_SLEEP, 0);
6013
f4f71c7d
D		 6014 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6015 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6016
6017 /* allows RC6 residency counter to work */
6018 I915_WRITE(VLV_COUNTER_CONTROL,
6019 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6020 VLV_MEDIA_RC6_COUNT_EN |
6021 VLV_RENDER_RC6_COUNT_EN));
6022
6023 /* For now we assume BIOS is allocating and populating the PCBR */
6024 pcbr = I915_READ(VLV_PCBR);
6025
38807746 6026 /* 3: Enable RC6 */
dc97997a
CW		 6027 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6028 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6029 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6030
6031 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6032
2b6b3a09 6033 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6034 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6035 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6036 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6037 I915_WRITE(GEN6_RP_UP_EI, 66000);
6038 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6039
6040 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6041
6042 /* 5: Enable RPS */
6043 I915_WRITE(GEN6_RP_CONTROL,
6044 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6045 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6046 GEN6_RP_ENABLE |
6047 GEN6_RP_UP_BUSY_AVG |
6048 GEN6_RP_DOWN_IDLE_AVG);
6049
3ef62342
D		 6050 /* Setting Fixed Bias */
6051 val = VLV_OVERRIDE_EN |
6052 VLV_SOC_TDP_EN |
6053 CHV_BIAS_CPU_50_SOC_50;
6054 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6055
2b6b3a09
D		 6056 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6057
8d40c3ae
VS		 6058 /* RPS code assumes GPLL is used */
6059 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6060
742f491d 6061 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6062 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6063
3a45b05c 6064 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6065
59bad947 6066 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6067}
6068
dc97997a 6069static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6070{
e2f80391 6071 struct intel_engine_cs *engine;
3b3f1650 6072 enum intel_engine_id id;
2a5913a8 6073 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6074
6075 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6076
ae48434c
ID		 6077 valleyview_check_pctx(dev_priv);
6078
297b32ec
VS		 6079 gtfifodbg = I915_READ(GTFIFODBG);
6080 if (gtfifodbg) {
f7d85c1e
JB		 6081 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6082 gtfifodbg);
0a073b84
JB		 6083 I915_WRITE(GTFIFODBG, gtfifodbg);
6084 }
6085
c8d9a590 6086 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6087 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6088
160614a2
VS		 6089 /* Disable RC states. */
6090 I915_WRITE(GEN6_RC_CONTROL, 0);
6091
cad725fe 6092 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6093 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6094 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6095 I915_WRITE(GEN6_RP_UP_EI, 66000);
6096 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6097
6098 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6099
6100 I915_WRITE(GEN6_RP_CONTROL,
6101 GEN6_RP_MEDIA_TURBO |
6102 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6103 GEN6_RP_MEDIA_IS_GFX |
6104 GEN6_RP_ENABLE |
6105 GEN6_RP_UP_BUSY_AVG |
6106 GEN6_RP_DOWN_IDLE_CONT);
6107
6108 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6109 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6110 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6111
3b3f1650 6112 for_each_engine(engine, dev_priv, id)
e2f80391 6113 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6114
2f0aa304 6115 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6116
6117 /* allows RC6 residency counter to work */
49798eb2 6118 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6119 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6120 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6121 VLV_MEDIA_RC6_COUNT_EN |
6122 VLV_RENDER_RC6_COUNT_EN));
31685c25 6123
dc97997a 6124 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6125 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6126
dc97997a 6127 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6128
a2b23fe0 6129 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6130
3ef62342
D		 6131 /* Setting Fixed Bias */
6132 val = VLV_OVERRIDE_EN |
6133 VLV_SOC_TDP_EN |
6134 VLV_BIAS_CPU_125_SOC_875;
6135 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6136
64936258 6137 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6138
8d40c3ae
VS		 6139 /* RPS code assumes GPLL is used */
6140 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6141
742f491d 6142 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6143 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6144
3a45b05c 6145 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6146
59bad947 6147 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6148}
6149
dde18883
ED		 6150static unsigned long intel_pxfreq(u32 vidfreq)
6151{
6152 unsigned long freq;
6153 int div = (vidfreq & 0x3f0000) >> 16;
6154 int post = (vidfreq & 0x3000) >> 12;
6155 int pre = (vidfreq & 0x7);
6156
6157 if (!pre)
6158 return 0;
6159
6160 freq = ((div * 133333) / ((1<<post) * pre));
6161
6162 return freq;
6163}
6164
eb48eb00
DV		 6165static const struct cparams {
6166 u16 i;
6167 u16 t;
6168 u16 m;
6169 u16 c;
6170} cparams[] = {
6171 { 1, 1333, 301, 28664 },
6172 { 1, 1066, 294, 24460 },
6173 { 1, 800, 294, 25192 },
6174 { 0, 1333, 276, 27605 },
6175 { 0, 1066, 276, 27605 },
6176 { 0, 800, 231, 23784 },
6177};
6178
f531dcb2 6179static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6180{
6181 u64 total_count, diff, ret;
6182 u32 count1, count2, count3, m = 0, c = 0;
6183 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6184 int i;
6185
02d71956
DV		 6186 assert_spin_locked(&mchdev_lock);
6187
20e4d407 6188 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6189
6190 /* Prevent division-by-zero if we are asking too fast.
6191 * Also, we don't get interesting results if we are polling
6192 * faster than once in 10ms, so just return the saved value
6193 * in such cases.
6194 */
6195 if (diff1 <= 10)
20e4d407 6196 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6197
6198 count1 = I915_READ(DMIEC);
6199 count2 = I915_READ(DDREC);
6200 count3 = I915_READ(CSIEC);
6201
6202 total_count = count1 + count2 + count3;
6203
6204 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6205 if (total_count < dev_priv->ips.last_count1) {
6206 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6207 diff += total_count;
6208 } else {
20e4d407 6209 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6210 }
6211
6212 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6213 if (cparams[i].i == dev_priv->ips.c_m &&
6214 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6215 m = cparams[i].m;
6216 c = cparams[i].c;
6217 break;
6218 }
6219 }
6220
6221 diff = div_u64(diff, diff1);
6222 ret = ((m * diff) + c);
6223 ret = div_u64(ret, 10);
6224
20e4d407
DV		 6225 dev_priv->ips.last_count1 = total_count;
6226 dev_priv->ips.last_time1 = now;
eb48eb00 6227
20e4d407 6228 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6229
6230 return ret;
6231}
6232
f531dcb2
CW		 6233unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6234{
6235 unsigned long val;
6236
dc97997a 6237 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6238 return 0;
6239
6240 spin_lock_irq(&mchdev_lock);
6241
6242 val = __i915_chipset_val(dev_priv);
6243
6244 spin_unlock_irq(&mchdev_lock);
6245
6246 return val;
6247}
6248
eb48eb00
DV		 6249unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6250{
6251 unsigned long m, x, b;
6252 u32 tsfs;
6253
6254 tsfs = I915_READ(TSFS);
6255
6256 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6257 x = I915_READ8(TR1);
6258
6259 b = tsfs & TSFS_INTR_MASK;
6260
6261 return ((m * x) / 127) - b;
6262}
6263
d972d6ee
MK		 6264static int _pxvid_to_vd(u8 pxvid)
6265{
6266 if (pxvid == 0)
6267 return 0;
6268
6269 if (pxvid >= 8 && pxvid < 31)
6270 pxvid = 31;
6271
6272 return (pxvid + 2) * 125;
6273}
6274
6275static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6276{
d972d6ee
MK		 6277 const int vd = _pxvid_to_vd(pxvid);
6278 const int vm = vd - 1125;
6279
dc97997a 6280 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6281 return vm > 0 ? vm : 0;
6282
6283 return vd;
eb48eb00
DV		 6284}
6285
02d71956 6286static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6287{
5ed0bdf2 6288 u64 now, diff, diffms;
eb48eb00
DV		 6289 u32 count;
6290
02d71956 6291 assert_spin_locked(&mchdev_lock);
eb48eb00 6292
5ed0bdf2
TG		 6293 now = ktime_get_raw_ns();
6294 diffms = now - dev_priv->ips.last_time2;
6295 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6296
6297 /* Don't divide by 0 */
eb48eb00
DV		 6298 if (!diffms)
6299 return;
6300
6301 count = I915_READ(GFXEC);
6302
20e4d407
DV		 6303 if (count < dev_priv->ips.last_count2) {
6304 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6305 diff += count;
6306 } else {
20e4d407 6307 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6308 }
6309
20e4d407
DV		 6310 dev_priv->ips.last_count2 = count;
6311 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6312
6313 /* More magic constants... */
6314 diff = diff * 1181;
6315 diff = div_u64(diff, diffms * 10);
20e4d407 6316 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6317}
6318
02d71956
DV		 6319void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6320{
dc97997a 6321 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6322 return;
6323
9270388e 6324 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6325
6326 __i915_update_gfx_val(dev_priv);
6327
9270388e 6328 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6329}
6330
f531dcb2 6331static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6332{
6333 unsigned long t, corr, state1, corr2, state2;
6334 u32 pxvid, ext_v;
6335
02d71956
DV		 6336 assert_spin_locked(&mchdev_lock);
6337
616847e7 6338 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6339 pxvid = (pxvid >> 24) & 0x7f;
6340 ext_v = pvid_to_extvid(dev_priv, pxvid);
6341
6342 state1 = ext_v;
6343
6344 t = i915_mch_val(dev_priv);
6345
6346 /* Revel in the empirically derived constants */
6347
6348 /* Correction factor in 1/100000 units */
6349 if (t > 80)
6350 corr = ((t * 2349) + 135940);
6351 else if (t >= 50)
6352 corr = ((t * 964) + 29317);
6353 else /* < 50 */
6354 corr = ((t * 301) + 1004);
6355
6356 corr = corr * ((150142 * state1) / 10000 - 78642);
6357 corr /= 100000;
20e4d407 6358 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6359
6360 state2 = (corr2 * state1) / 10000;
6361 state2 /= 100; /* convert to mW */
6362
02d71956 6363 __i915_update_gfx_val(dev_priv);
eb48eb00 6364
20e4d407 6365 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6366}
6367
f531dcb2
CW		 6368unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6369{
6370 unsigned long val;
6371
dc97997a 6372 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6373 return 0;
6374
6375 spin_lock_irq(&mchdev_lock);
6376
6377 val = __i915_gfx_val(dev_priv);
6378
6379 spin_unlock_irq(&mchdev_lock);
6380
6381 return val;
6382}
6383
eb48eb00
DV		 6384/**
6385 * i915_read_mch_val - return value for IPS use
6386 *
6387 * Calculate and return a value for the IPS driver to use when deciding whether
6388 * we have thermal and power headroom to increase CPU or GPU power budget.
6389 */
6390unsigned long i915_read_mch_val(void)
6391{
6392 struct drm_i915_private *dev_priv;
6393 unsigned long chipset_val, graphics_val, ret = 0;
6394
9270388e 6395 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6396 if (!i915_mch_dev)
6397 goto out_unlock;
6398 dev_priv = i915_mch_dev;
6399
f531dcb2
CW		 6400 chipset_val = __i915_chipset_val(dev_priv);
6401 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6402
6403 ret = chipset_val + graphics_val;
6404
6405out_unlock:
9270388e 6406 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6407
6408 return ret;
6409}
6410EXPORT_SYMBOL_GPL(i915_read_mch_val);
6411
6412/**
6413 * i915_gpu_raise - raise GPU frequency limit
6414 *
6415 * Raise the limit; IPS indicates we have thermal headroom.
6416 */
6417bool i915_gpu_raise(void)
6418{
6419 struct drm_i915_private *dev_priv;
6420 bool ret = true;
6421
9270388e 6422 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6423 if (!i915_mch_dev) {
6424 ret = false;
6425 goto out_unlock;
6426 }
6427 dev_priv = i915_mch_dev;
6428
20e4d407
DV		 6429 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6430 dev_priv->ips.max_delay--;
eb48eb00
DV		 6431
6432out_unlock:
9270388e 6433 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6434
6435 return ret;
6436}
6437EXPORT_SYMBOL_GPL(i915_gpu_raise);
6438
6439/**
6440 * i915_gpu_lower - lower GPU frequency limit
6441 *
6442 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6443 * frequency maximum.
6444 */
6445bool i915_gpu_lower(void)
6446{
6447 struct drm_i915_private *dev_priv;
6448 bool ret = true;
6449
9270388e 6450 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6451 if (!i915_mch_dev) {
6452 ret = false;
6453 goto out_unlock;
6454 }
6455 dev_priv = i915_mch_dev;
6456
20e4d407
DV		 6457 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6458 dev_priv->ips.max_delay++;
eb48eb00
DV		 6459
6460out_unlock:
9270388e 6461 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6462
6463 return ret;
6464}
6465EXPORT_SYMBOL_GPL(i915_gpu_lower);
6466
6467/**
6468 * i915_gpu_busy - indicate GPU business to IPS
6469 *
6470 * Tell the IPS driver whether or not the GPU is busy.
6471 */
6472bool i915_gpu_busy(void)
6473{
eb48eb00
DV		 6474 bool ret = false;
6475
9270388e 6476 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6477 if (i915_mch_dev)
6478 ret = i915_mch_dev->gt.awake;
9270388e 6479 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6480
6481 return ret;
6482}
6483EXPORT_SYMBOL_GPL(i915_gpu_busy);
6484
6485/**
6486 * i915_gpu_turbo_disable - disable graphics turbo
6487 *
6488 * Disable graphics turbo by resetting the max frequency and setting the
6489 * current frequency to the default.
6490 */
6491bool i915_gpu_turbo_disable(void)
6492{
6493 struct drm_i915_private *dev_priv;
6494 bool ret = true;
6495
9270388e 6496 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6497 if (!i915_mch_dev) {
6498 ret = false;
6499 goto out_unlock;
6500 }
6501 dev_priv = i915_mch_dev;
6502
20e4d407 6503 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6504
91d14251 6505 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6506 ret = false;
6507
6508out_unlock:
9270388e 6509 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6510
6511 return ret;
6512}
6513EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6514
6515/**
6516 * Tells the intel_ips driver that the i915 driver is now loaded, if
6517 * IPS got loaded first.
6518 *
6519 * This awkward dance is so that neither module has to depend on the
6520 * other in order for IPS to do the appropriate communication of
6521 * GPU turbo limits to i915.
6522 */
6523static void
6524ips_ping_for_i915_load(void)
6525{
6526 void (*link)(void);
6527
6528 link = symbol_get(ips_link_to_i915_driver);
6529 if (link) {
6530 link();
6531 symbol_put(ips_link_to_i915_driver);
6532 }
6533}
6534
6535void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6536{
02d71956
DV		 6537 /* We only register the i915 ips part with intel-ips once everything is
6538 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6539 spin_lock_irq(&mchdev_lock);
eb48eb00 6540 i915_mch_dev = dev_priv;
9270388e 6541 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6542
6543 ips_ping_for_i915_load();
6544}
6545
6546void intel_gpu_ips_teardown(void)
6547{
9270388e 6548 spin_lock_irq(&mchdev_lock);
eb48eb00 6549 i915_mch_dev = NULL;
9270388e 6550 spin_unlock_irq(&mchdev_lock);
eb48eb00 6551}
76c3552f 6552
dc97997a 6553static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6554{
dde18883
ED		 6555 u32 lcfuse;
6556 u8 pxw[16];
6557 int i;
6558
6559 /* Disable to program */
6560 I915_WRITE(ECR, 0);
6561 POSTING_READ(ECR);
6562
6563 /* Program energy weights for various events */
6564 I915_WRITE(SDEW, 0x15040d00);
6565 I915_WRITE(CSIEW0, 0x007f0000);
6566 I915_WRITE(CSIEW1, 0x1e220004);
6567 I915_WRITE(CSIEW2, 0x04000004);
6568
6569 for (i = 0; i < 5; i++)
616847e7 6570 I915_WRITE(PEW(i), 0);
dde18883 6571 for (i = 0; i < 3; i++)
616847e7 6572 I915_WRITE(DEW(i), 0);
dde18883
ED		 6573
6574 /* Program P-state weights to account for frequency power adjustment */
6575 for (i = 0; i < 16; i++) {
616847e7 6576 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6577 unsigned long freq = intel_pxfreq(pxvidfreq);
6578 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6579 PXVFREQ_PX_SHIFT;
6580 unsigned long val;
6581
6582 val = vid * vid;
6583 val *= (freq / 1000);
6584 val *= 255;
6585 val /= (127*127*900);
6586 if (val > 0xff)
6587 DRM_ERROR("bad pxval: %ld\n", val);
6588 pxw[i] = val;
6589 }
6590 /* Render standby states get 0 weight */
6591 pxw[14] = 0;
6592 pxw[15] = 0;
6593
6594 for (i = 0; i < 4; i++) {
6595 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6596 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6597 I915_WRITE(PXW(i), val);
dde18883
ED		 6598 }
6599
6600 /* Adjust magic regs to magic values (more experimental results) */
6601 I915_WRITE(OGW0, 0);
6602 I915_WRITE(OGW1, 0);
6603 I915_WRITE(EG0, 0x00007f00);
6604 I915_WRITE(EG1, 0x0000000e);
6605 I915_WRITE(EG2, 0x000e0000);
6606 I915_WRITE(EG3, 0x68000300);
6607 I915_WRITE(EG4, 0x42000000);
6608 I915_WRITE(EG5, 0x00140031);
6609 I915_WRITE(EG6, 0);
6610 I915_WRITE(EG7, 0);
6611
6612 for (i = 0; i < 8; i++)
616847e7 6613 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6614
6615 /* Enable PMON + select events */
6616 I915_WRITE(ECR, 0x80000019);
6617
6618 lcfuse = I915_READ(LCFUSE02);
6619
20e4d407 6620 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6621}
6622
dc97997a 6623void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6624{
b268c699
ID		 6625 /*
6626 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6627 * requirement.
6628 */
6629 if (!i915.enable_rc6) {
6630 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6631 intel_runtime_pm_get(dev_priv);
6632 }
e6069ca8 6633
b5163dbb 6634 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6635 mutex_lock(&dev_priv->rps.hw_lock);
6636
6637 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6638 if (IS_CHERRYVIEW(dev_priv))
6639 cherryview_init_gt_powersave(dev_priv);
6640 else if (IS_VALLEYVIEW(dev_priv))
6641 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6642 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6643 gen6_init_rps_frequencies(dev_priv);
6644
6645 /* Derive initial user preferences/limits from the hardware limits */
6646 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6647 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6648
6649 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6650 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6651
6652 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6653 dev_priv->rps.min_freq_softlimit =
6654 max_t(int,
6655 dev_priv->rps.efficient_freq,
6656 intel_freq_opcode(dev_priv, 450));
6657
99ac9612
CW		 6658 /* After setting max-softlimit, find the overclock max freq */
6659 if (IS_GEN6(dev_priv) ||
6660 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6661 u32 params = 0;
6662
6663 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6664 if (params & BIT(31)) { /* OC supported */
6665 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6666 (dev_priv->rps.max_freq & 0xff) * 50,
6667 (params & 0xff) * 50);
6668 dev_priv->rps.max_freq = params & 0xff;
6669 }
6670 }
6671
29ecd78d
CW		 6672 /* Finally allow us to boost to max by default */
6673 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6674
773ea9a8 6675 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6676 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6677
6678 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6679}
6680
dc97997a 6681void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6682{
8dac1e1f 6683 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6684 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6685
6686 if (!i915.enable_rc6)
6687 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6688}
6689
54b4f68f
CW		 6690/**
6691 * intel_suspend_gt_powersave - suspend PM work and helper threads
6692 * @dev_priv: i915 device
6693 *
6694 * We don't want to disable RC6 or other features here, we just want
6695 * to make sure any work we've queued has finished and won't bother
6696 * us while we're suspended.
6697 */
6698void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6699{
6700 if (INTEL_GEN(dev_priv) < 6)
6701 return;
6702
6703 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6704 intel_runtime_pm_put(dev_priv);
6705
6706 /* gen6_rps_idle() will be called later to disable interrupts */
6707}
6708
b7137e0c
CW		 6709void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6710{
6711 dev_priv->rps.enabled = true; /* force disabling */
6712 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6713
6714 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6715}
6716
dc97997a 6717void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6718{
b7137e0c
CW		 6719 if (!READ_ONCE(dev_priv->rps.enabled))
6720 return;
e494837a 6721
b7137e0c 6722 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6723
b7137e0c
CW		 6724 if (INTEL_GEN(dev_priv) >= 9) {
6725 gen9_disable_rc6(dev_priv);
6726 gen9_disable_rps(dev_priv);
6727 } else if (IS_CHERRYVIEW(dev_priv)) {
6728 cherryview_disable_rps(dev_priv);
6729 } else if (IS_VALLEYVIEW(dev_priv)) {
6730 valleyview_disable_rps(dev_priv);
6731 } else if (INTEL_GEN(dev_priv) >= 6) {
6732 gen6_disable_rps(dev_priv);
6733 } else if (IS_IRONLAKE_M(dev_priv)) {
6734 ironlake_disable_drps(dev_priv);
930ebb46 6735 }
b7137e0c
CW		 6736
6737 dev_priv->rps.enabled = false;
6738 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6739}
6740
b7137e0c 6741void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6742{
54b4f68f
CW		 6743 /* We shouldn't be disabling as we submit, so this should be less
6744 * racy than it appears!
6745 */
b7137e0c
CW		 6746 if (READ_ONCE(dev_priv->rps.enabled))
6747 return;
1a01ab3b 6748
b7137e0c
CW		 6749 /* Powersaving is controlled by the host when inside a VM */
6750 if (intel_vgpu_active(dev_priv))
6751 return;
0a073b84 6752
b7137e0c 6753 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6754
6755 if (IS_CHERRYVIEW(dev_priv)) {
6756 cherryview_enable_rps(dev_priv);
6757 } else if (IS_VALLEYVIEW(dev_priv)) {
6758 valleyview_enable_rps(dev_priv);
b7137e0c 6759 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6760 gen9_enable_rc6(dev_priv);
6761 gen9_enable_rps(dev_priv);
b976dc53 6762 if (IS_GEN9_BC(dev_priv))
fb7404e8 6763 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6764 } else if (IS_BROADWELL(dev_priv)) {
6765 gen8_enable_rps(dev_priv);
fb7404e8 6766 gen6_update_ring_freq(dev_priv);
b7137e0c 6767 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6768 gen6_enable_rps(dev_priv);
fb7404e8 6769 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6770 } else if (IS_IRONLAKE_M(dev_priv)) {
6771 ironlake_enable_drps(dev_priv);
6772 intel_init_emon(dev_priv);
0a073b84 6773 }
aed242ff
CW		 6774
6775 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6776 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6777
6778 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6779 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6780
54b4f68f 6781 dev_priv->rps.enabled = true;
b7137e0c
CW		 6782 mutex_unlock(&dev_priv->rps.hw_lock);
6783}
3cc134e3 6784
54b4f68f
CW		 6785static void __intel_autoenable_gt_powersave(struct work_struct *work)
6786{
6787 struct drm_i915_private *dev_priv =
6788 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6789 struct intel_engine_cs *rcs;
6790 struct drm_i915_gem_request *req;
6791
6792 if (READ_ONCE(dev_priv->rps.enabled))
6793 goto out;
6794
3b3f1650 6795 rcs = dev_priv->engine[RCS];
e8a9c58f 6796 if (rcs->last_retired_context)
54b4f68f
CW		 6797 goto out;
6798
6799 if (!rcs->init_context)
6800 goto out;
6801
6802 mutex_lock(&dev_priv->drm.struct_mutex);
6803
6804 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6805 if (IS_ERR(req))
6806 goto unlock;
6807
6808 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6809 rcs->init_context(req);
6810
6811 /* Mark the device busy, calling intel_enable_gt_powersave() */
6812 i915_add_request_no_flush(req);
6813
6814unlock:
6815 mutex_unlock(&dev_priv->drm.struct_mutex);
6816out:
6817 intel_runtime_pm_put(dev_priv);
6818}
6819
6820void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6821{
6822 if (READ_ONCE(dev_priv->rps.enabled))
6823 return;
6824
6825 if (IS_IRONLAKE_M(dev_priv)) {
6826 ironlake_enable_drps(dev_priv);
54b4f68f 6827 intel_init_emon(dev_priv);
54b4f68f
CW		 6828 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6829 /*
6830 * PCU communication is slow and this doesn't need to be
6831 * done at any specific time, so do this out of our fast path
6832 * to make resume and init faster.
6833 *
6834 * We depend on the HW RC6 power context save/restore
6835 * mechanism when entering D3 through runtime PM suspend. So
6836 * disable RPM until RPS/RC6 is properly setup. We can only
6837 * get here via the driver load/system resume/runtime resume
6838 * paths, so the _noresume version is enough (and in case of
6839 * runtime resume it's necessary).
6840 */
6841 if (queue_delayed_work(dev_priv->wq,
6842 &dev_priv->rps.autoenable_work,
6843 round_jiffies_up_relative(HZ)))
6844 intel_runtime_pm_get_noresume(dev_priv);
6845 }
6846}
6847
46f16e63 6848static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6849{
3107bd48
DV		 6850 /*
6851 * On Ibex Peak and Cougar Point, we need to disable clock
6852 * gating for the panel power sequencer or it will fail to
6853 * start up when no ports are active.
6854 */
6855 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6856}
6857
46f16e63 6858static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
0e088b8f 6859{
b12ce1d8 6860 enum pipe pipe;
0e088b8f 6861
055e393f 6862 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6863 I915_WRITE(DSPCNTR(pipe),
6864 I915_READ(DSPCNTR(pipe)) |
6865 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6866
6867 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6868 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6869 }
6870}
6871
46f16e63 6872static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
017636cc 6873{
017636cc
VS		 6874 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6875 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6876 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6877
6878 /*
6879 * Don't touch WM1S_LP_EN here.
6880 * Doing so could cause underruns.
6881 */
6882}
6883
46f16e63 6884static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 6885{
231e54f6 6886 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6887
f1e8fa56
DL		 6888 /*
6889 * Required for FBC
6890 * WaFbcDisableDpfcClockGating:ilk
6891 */
4d47e4f5
DL		 6892 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6893 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6894 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6895
6896 I915_WRITE(PCH_3DCGDIS0,
6897 MARIUNIT_CLOCK_GATE_DISABLE |
6898 SVSMUNIT_CLOCK_GATE_DISABLE);
6899 I915_WRITE(PCH_3DCGDIS1,
6900 VFMUNIT_CLOCK_GATE_DISABLE);
6901
6f1d69b0
ED		 6902 /*
6903 * According to the spec the following bits should be set in
6904 * order to enable memory self-refresh
6905 * The bit 22/21 of 0x42004
6906 * The bit 5 of 0x42020
6907 * The bit 15 of 0x45000
6908 */
6909 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6910 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6911 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6912 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6913 I915_WRITE(DISP_ARB_CTL,
6914 (I915_READ(DISP_ARB_CTL) |
6915 DISP_FBC_WM_DIS));
017636cc 6916
46f16e63 6917 ilk_init_lp_watermarks(dev_priv);
6f1d69b0
ED		 6918
6919 /*
6920 * Based on the document from hardware guys the following bits
6921 * should be set unconditionally in order to enable FBC.
6922 * The bit 22 of 0x42000
6923 * The bit 22 of 0x42004
6924 * The bit 7,8,9 of 0x42020.
6925 */
50a0bc90 6926 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6927 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6928 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6929 I915_READ(ILK_DISPLAY_CHICKEN1) |
6930 ILK_FBCQ_DIS);
6931 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6932 I915_READ(ILK_DISPLAY_CHICKEN2) |
6933 ILK_DPARB_GATE);
6f1d69b0
ED		 6934 }
6935
4d47e4f5
DL		 6936 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6937
6f1d69b0
ED		 6938 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6939 I915_READ(ILK_DISPLAY_CHICKEN2) |
6940 ILK_ELPIN_409_SELECT);
6941 I915_WRITE(_3D_CHICKEN2,
6942 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6943 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6944
ecdb4eb7 6945 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6946 I915_WRITE(CACHE_MODE_0,
6947 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6948
4e04632e
AG		 6949 /* WaDisable_RenderCache_OperationalFlush:ilk */
6950 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6951
46f16e63 6952 g4x_disable_trickle_feed(dev_priv);
bdad2b2f 6953
46f16e63 6954 ibx_init_clock_gating(dev_priv);
3107bd48
DV		 6955}
6956
46f16e63 6957static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6958{
3107bd48 6959 int pipe;
3f704fa2 6960 uint32_t val;
3107bd48
DV		 6961
6962 /*
6963 * On Ibex Peak and Cougar Point, we need to disable clock
6964 * gating for the panel power sequencer or it will fail to
6965 * start up when no ports are active.
6966 */
cd664078
JB		 6967 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6968 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6969 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6970 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6971 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6972 /* The below fixes the weird display corruption, a few pixels shifted
6973 * downward, on (only) LVDS of some HP laptops with IVY.
6974 */
055e393f 6975 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6976 val = I915_READ(TRANS_CHICKEN2(pipe));
6977 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6978 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6979 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6980 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6981 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6982 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6983 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6984 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6985 }
3107bd48 6986 /* WADP0ClockGatingDisable */
055e393f 6987 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6988 I915_WRITE(TRANS_CHICKEN1(pipe),
6989 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6990 }
6f1d69b0
ED		 6991}
6992
46f16e63 6993static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
1d7aaa0c 6994{
1d7aaa0c
DV		 6995 uint32_t tmp;
6996
6997 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6998 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6999 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7000 tmp);
1d7aaa0c
DV		 7001}
7002
46f16e63 7003static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7004{
231e54f6 7005 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7006
231e54f6 7007 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7008
7009 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7010 I915_READ(ILK_DISPLAY_CHICKEN2) |
7011 ILK_ELPIN_409_SELECT);
7012
ecdb4eb7 7013 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7014 I915_WRITE(_3D_CHICKEN,
7015 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7016
4e04632e
AG		 7017 /* WaDisable_RenderCache_OperationalFlush:snb */
7018 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7019
8d85d272
VS		 7020 /*
7021 * BSpec recoomends 8x4 when MSAA is used,
7022 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7023 *
7024 * Note that PS/WM thread counts depend on the WIZ hashing
7025 * disable bit, which we don't touch here, but it's good
7026 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7027 */
7028 I915_WRITE(GEN6_GT_MODE,
98533251 7029 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7030
46f16e63 7031 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7032
6f1d69b0 7033 I915_WRITE(CACHE_MODE_0,
50743298 7034 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7035
7036 I915_WRITE(GEN6_UCGCTL1,
7037 I915_READ(GEN6_UCGCTL1) |
7038 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7039 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7040
7041 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7042 * gating disable must be set. Failure to set it results in
7043 * flickering pixels due to Z write ordering failures after
7044 * some amount of runtime in the Mesa "fire" demo, and Unigine
7045 * Sanctuary and Tropics, and apparently anything else with
7046 * alpha test or pixel discard.
7047 *
7048 * According to the spec, bit 11 (RCCUNIT) must also be set,
7049 * but we didn't debug actual testcases to find it out.
0f846f81 7050 *
ef59318c
VS		 7051 * WaDisableRCCUnitClockGating:snb
7052 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7053 */
7054 I915_WRITE(GEN6_UCGCTL2,
7055 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7056 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7057
5eb146dd 7058 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7059 I915_WRITE(_3D_CHICKEN3,
7060 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7061
e927ecde
VS		 7062 /*
7063 * Bspec says:
7064 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7065 * 3DSTATE_SF number of SF output attributes is more than 16."
7066 */
7067 I915_WRITE(_3D_CHICKEN3,
7068 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7069
6f1d69b0
ED		 7070 /*
7071 * According to the spec the following bits should be
7072 * set in order to enable memory self-refresh and fbc:
7073 * The bit21 and bit22 of 0x42000
7074 * The bit21 and bit22 of 0x42004
7075 * The bit5 and bit7 of 0x42020
7076 * The bit14 of 0x70180
7077 * The bit14 of 0x71180
4bb35334
DL		 7078 *
7079 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7080 */
7081 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7082 I915_READ(ILK_DISPLAY_CHICKEN1) |
7083 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7084 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7085 I915_READ(ILK_DISPLAY_CHICKEN2) |
7086 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7087 I915_WRITE(ILK_DSPCLK_GATE_D,
7088 I915_READ(ILK_DSPCLK_GATE_D) |
7089 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7090 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7091
46f16e63 7092 g4x_disable_trickle_feed(dev_priv);
f8f2ac9a 7093
46f16e63 7094 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7095
46f16e63 7096 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7097}
7098
7099static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7100{
7101 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7102
3aad9059 7103 /*
46680e0a 7104 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7105 *
7106 * This actually overrides the dispatch
7107 * mode for all thread types.
7108 */
6f1d69b0
ED		 7109 reg &= ~GEN7_FF_SCHED_MASK;
7110 reg |= GEN7_FF_TS_SCHED_HW;
7111 reg |= GEN7_FF_VS_SCHED_HW;
7112 reg |= GEN7_FF_DS_SCHED_HW;
7113
7114 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7115}
7116
46f16e63 7117static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
17a303ec 7118{
17a303ec
PZ		 7119 /*
7120 * TODO: this bit should only be enabled when really needed, then
7121 * disabled when not needed anymore in order to save power.
7122 */
4f8036a2 7123 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7124 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7125 I915_READ(SOUTH_DSPCLK_GATE_D) |
7126 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7127
7128 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7129 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7130 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7131 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7132}
7133
712bf364 7134static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7135{
4f8036a2 7136 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7137 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7138
7139 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7140 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7141 }
7142}
7143
450174fe
ID		 7144static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7145 int general_prio_credits,
7146 int high_prio_credits)
7147{
7148 u32 misccpctl;
7149
7150 /* WaTempDisableDOPClkGating:bdw */
7151 misccpctl = I915_READ(GEN7_MISCCPCTL);
7152 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7153
7154 I915_WRITE(GEN8_L3SQCREG1,
7155 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7156 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7157
7158 /*
7159 * Wait at least 100 clocks before re-enabling clock gating.
7160 * See the definition of L3SQCREG1 in BSpec.
7161 */
7162 POSTING_READ(GEN8_L3SQCREG1);
7163 udelay(1);
7164 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7165}
7166
46f16e63 7167static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
9498dba7 7168{
46f16e63 7169 gen9_init_clock_gating(dev_priv);
9498dba7
MK		 7170
7171 /* WaDisableSDEUnitClockGating:kbl */
7172 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7173 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7174 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7175
7176 /* WaDisableGamClockGating:kbl */
7177 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7178 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7179 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7180
7181 /* WaFbcNukeOnHostModify:kbl */
7182 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7183 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7184}
7185
46f16e63 7186static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
dc00b6a0 7187{
46f16e63 7188 gen9_init_clock_gating(dev_priv);
44fff99f
MK		 7189
7190 /* WAC6entrylatency:skl */
7191 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7192 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7193
7194 /* WaFbcNukeOnHostModify:skl */
7195 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7196 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7197}
7198
46f16e63 7199static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
1020a5c2 7200{
07d27e20 7201 enum pipe pipe;
1020a5c2 7202
46f16e63 7203 ilk_init_lp_watermarks(dev_priv);
50ed5fbd 7204
ab57fff1 7205 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7206 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7207
ab57fff1 7208 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7209 I915_WRITE(CHICKEN_PAR1_1,
7210 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7211
ab57fff1 7212 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7213 for_each_pipe(dev_priv, pipe) {
07d27e20 7214 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7215 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7216 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7217 }
63801f21 7218
ab57fff1
BW		 7219 /* WaVSRefCountFullforceMissDisable:bdw */
7220 /* WaDSRefCountFullforceMissDisable:bdw */
7221 I915_WRITE(GEN7_FF_THREAD_MODE,
7222 I915_READ(GEN7_FF_THREAD_MODE) &
7223 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7224
295e8bb7
VS		 7225 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7226 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7227
7228 /* WaDisableSDEUnitClockGating:bdw */
7229 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7230 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7231
450174fe
ID		 7232 /* WaProgramL3SqcReg1Default:bdw */
7233 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7234
6d50b065
VS		 7235 /*
7236 * WaGttCachingOffByDefault:bdw
7237 * GTT cache may not work with big pages, so if those
7238 * are ever enabled GTT cache may need to be disabled.
7239 */
7240 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7241
17e0adf0
MK		 7242 /* WaKVMNotificationOnConfigChange:bdw */
7243 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7244 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7245
46f16e63 7246 lpt_init_clock_gating(dev_priv);
9cc19733
RB		 7247
7248 /* WaDisableDopClockGating:bdw
7249 *
7250 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7251 * clock gating.
7252 */
7253 I915_WRITE(GEN6_UCGCTL1,
7254 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
1020a5c2
BW		 7255}
7256
46f16e63 7257static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
cad2a2d7 7258{
46f16e63 7259 ilk_init_lp_watermarks(dev_priv);
cad2a2d7 7260
f3fc4884
FJ		 7261 /* L3 caching of data atomics doesn't work -- disable it. */
7262 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7263 I915_WRITE(HSW_ROW_CHICKEN3,
7264 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7265
ecdb4eb7 7266 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7267 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7268 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7269 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7270
e36ea7ff
VS		 7271 /* WaVSRefCountFullforceMissDisable:hsw */
7272 I915_WRITE(GEN7_FF_THREAD_MODE,
7273 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7274
4e04632e
AG		 7275 /* WaDisable_RenderCache_OperationalFlush:hsw */
7276 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7277
fe27c606
CW		 7278 /* enable HiZ Raw Stall Optimization */
7279 I915_WRITE(CACHE_MODE_0_GEN7,
7280 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7281
ecdb4eb7 7282 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7283 I915_WRITE(CACHE_MODE_1,
7284 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7285
a12c4967
VS		 7286 /*
7287 * BSpec recommends 8x4 when MSAA is used,
7288 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7289 *
7290 * Note that PS/WM thread counts depend on the WIZ hashing
7291 * disable bit, which we don't touch here, but it's good
7292 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7293 */
7294 I915_WRITE(GEN7_GT_MODE,
98533251 7295 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7296
94411593
KG		 7297 /* WaSampleCChickenBitEnable:hsw */
7298 I915_WRITE(HALF_SLICE_CHICKEN3,
7299 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7300
ecdb4eb7 7301 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7302 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7303
90a88643
PZ		 7304 /* WaRsPkgCStateDisplayPMReq:hsw */
7305 I915_WRITE(CHICKEN_PAR1_1,
7306 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7307
46f16e63 7308 lpt_init_clock_gating(dev_priv);
cad2a2d7
ED		 7309}
7310
46f16e63 7311static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7312{
20848223 7313 uint32_t snpcr;
6f1d69b0 7314
46f16e63 7315 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7316
231e54f6 7317 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7318
ecdb4eb7 7319 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7320 I915_WRITE(_3D_CHICKEN3,
7321 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7322
ecdb4eb7 7323 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7324 I915_WRITE(IVB_CHICKEN3,
7325 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7326 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7327
ecdb4eb7 7328 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7329 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7330 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7331 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7332
4e04632e
AG		 7333 /* WaDisable_RenderCache_OperationalFlush:ivb */
7334 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7335
ecdb4eb7 7336 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7337 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7338 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7339
ecdb4eb7 7340 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7341 I915_WRITE(GEN7_L3CNTLREG1,
7342 GEN7_WA_FOR_GEN7_L3_CONTROL);
7343 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7344 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7345 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7346 I915_WRITE(GEN7_ROW_CHICKEN2,
7347 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7348 else {
7349 /* must write both registers */
7350 I915_WRITE(GEN7_ROW_CHICKEN2,
7351 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7352 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7353 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7354 }
6f1d69b0 7355
ecdb4eb7 7356 /* WaForceL3Serialization:ivb */
61939d97
JB		 7357 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7358 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7359
1b80a19a 7360 /*
0f846f81 7361 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7362 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7363 */
7364 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7365 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7366
ecdb4eb7 7367 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7368 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7369 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7370 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7371
46f16e63 7372 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7373
7374 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7375
22721343
CW		 7376 if (0) { /* causes HiZ corruption on ivb:gt1 */
7377 /* enable HiZ Raw Stall Optimization */
7378 I915_WRITE(CACHE_MODE_0_GEN7,
7379 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7380 }
116f2b6d 7381
ecdb4eb7 7382 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7383 I915_WRITE(CACHE_MODE_1,
7384 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7385
a607c1a4
VS		 7386 /*
7387 * BSpec recommends 8x4 when MSAA is used,
7388 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7389 *
7390 * Note that PS/WM thread counts depend on the WIZ hashing
7391 * disable bit, which we don't touch here, but it's good
7392 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7393 */
7394 I915_WRITE(GEN7_GT_MODE,
98533251 7395 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7396
20848223
BW		 7397 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7398 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7399 snpcr |= GEN6_MBC_SNPCR_MED;
7400 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7401
6e266956 7402 if (!HAS_PCH_NOP(dev_priv))
46f16e63 7403 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7404
46f16e63 7405 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7406}
7407
46f16e63 7408static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7409{
ecdb4eb7 7410 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7411 I915_WRITE(_3D_CHICKEN3,
7412 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7413
ecdb4eb7 7414 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7415 I915_WRITE(IVB_CHICKEN3,
7416 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7417 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7418
fad7d36e 7419 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7420 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7421 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7422 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7423 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7424
4e04632e
AG		 7425 /* WaDisable_RenderCache_OperationalFlush:vlv */
7426 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7427
ecdb4eb7 7428 /* WaForceL3Serialization:vlv */
61939d97
JB		 7429 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7430 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7431
ecdb4eb7 7432 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7433 I915_WRITE(GEN7_ROW_CHICKEN2,
7434 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7435
ecdb4eb7 7436 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7437 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7438 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7439 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7440
46680e0a
VS		 7441 gen7_setup_fixed_func_scheduler(dev_priv);
7442
3c0edaeb 7443 /*
0f846f81 7444 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7445 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7446 */
7447 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7448 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7449
c98f5062
AG		 7450 /* WaDisableL3Bank2xClockGate:vlv
7451 * Disabling L3 clock gating- MMIO 940c[25] = 1
7452 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7453 I915_WRITE(GEN7_UCGCTL4,
7454 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7455
afd58e79
VS		 7456 /*
7457 * BSpec says this must be set, even though
7458 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7459 */
6b26c86d
DV		 7460 I915_WRITE(CACHE_MODE_1,
7461 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7462
da2518f9
VS		 7463 /*
7464 * BSpec recommends 8x4 when MSAA is used,
7465 * however in practice 16x4 seems fastest.
7466 *
7467 * Note that PS/WM thread counts depend on the WIZ hashing
7468 * disable bit, which we don't touch here, but it's good
7469 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7470 */
7471 I915_WRITE(GEN7_GT_MODE,
7472 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7473
031994ee
VS		 7474 /*
7475 * WaIncreaseL3CreditsForVLVB0:vlv
7476 * This is the hardware default actually.
7477 */
7478 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7479
2d809570 7480 /*
ecdb4eb7 7481 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7482 * Disable clock gating on th GCFG unit to prevent a delay
7483 * in the reporting of vblank events.
7484 */
7a0d1eed 7485 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7486}
7487
46f16e63 7488static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
a4565da8 7489{
232ce337
VS		 7490 /* WaVSRefCountFullforceMissDisable:chv */
7491 /* WaDSRefCountFullforceMissDisable:chv */
7492 I915_WRITE(GEN7_FF_THREAD_MODE,
7493 I915_READ(GEN7_FF_THREAD_MODE) &
7494 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7495
7496 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7497 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7498 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7499
7500 /* WaDisableCSUnitClockGating:chv */
7501 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7502 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7503
7504 /* WaDisableSDEUnitClockGating:chv */
7505 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7506 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7507
450174fe
ID		 7508 /*
7509 * WaProgramL3SqcReg1Default:chv
7510 * See gfxspecs/Related Documents/Performance Guide/
7511 * LSQC Setting Recommendations.
7512 */
7513 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7514
6d50b065
VS		 7515 /*
7516 * GTT cache may not work with big pages, so if those
7517 * are ever enabled GTT cache may need to be disabled.
7518 */
7519 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7520}
7521
46f16e63 7522static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7523{
6f1d69b0
ED		 7524 uint32_t dspclk_gate;
7525
7526 I915_WRITE(RENCLK_GATE_D1, 0);
7527 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7528 GS_UNIT_CLOCK_GATE_DISABLE |
7529 CL_UNIT_CLOCK_GATE_DISABLE);
7530 I915_WRITE(RAMCLK_GATE_D, 0);
7531 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7532 OVRUNIT_CLOCK_GATE_DISABLE |
7533 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7534 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7535 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7536 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7537
7538 /* WaDisableRenderCachePipelinedFlush */
7539 I915_WRITE(CACHE_MODE_0,
7540 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7541
4e04632e
AG		 7542 /* WaDisable_RenderCache_OperationalFlush:g4x */
7543 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7544
46f16e63 7545 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7546}
7547
46f16e63 7548static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7549{
6f1d69b0
ED		 7550 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7551 I915_WRITE(RENCLK_GATE_D2, 0);
7552 I915_WRITE(DSPCLK_GATE_D, 0);
7553 I915_WRITE(RAMCLK_GATE_D, 0);
7554 I915_WRITE16(DEUC, 0);
20f94967
VS		 7555 I915_WRITE(MI_ARB_STATE,
7556 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7557
7558 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7559 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7560}
7561
46f16e63 7562static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7563{
6f1d69b0
ED		 7564 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7565 I965_RCC_CLOCK_GATE_DISABLE |
7566 I965_RCPB_CLOCK_GATE_DISABLE |
7567 I965_ISC_CLOCK_GATE_DISABLE |
7568 I965_FBC_CLOCK_GATE_DISABLE);
7569 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7570 I915_WRITE(MI_ARB_STATE,
7571 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7572
7573 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7574 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7575}
7576
46f16e63 7577static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7578{
6f1d69b0
ED		 7579 u32 dstate = I915_READ(D_STATE);
7580
7581 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7582 DSTATE_DOT_CLOCK_GATING;
7583 I915_WRITE(D_STATE, dstate);
13a86b85 7584
9b1e14f4 7585 if (IS_PINEVIEW(dev_priv))
13a86b85 7586 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7587
7588 /* IIR "flip pending" means done if this bit is set */
7589 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7590
7591 /* interrupts should cause a wake up from C3 */
3299254f 7592 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7593
7594 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7595 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7596
7597 I915_WRITE(MI_ARB_STATE,
7598 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7599}
7600
46f16e63 7601static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7602{
6f1d69b0 7603 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7604
7605 /* interrupts should cause a wake up from C3 */
7606 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7607 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7608
7609 I915_WRITE(MEM_MODE,
7610 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7611}
7612
46f16e63 7613static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7614{
1038392b
VS		 7615 I915_WRITE(MEM_MODE,
7616 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7617 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7618}
7619
46f16e63 7620void intel_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7621{
46f16e63 7622 dev_priv->display.init_clock_gating(dev_priv);
6f1d69b0
ED		 7623}
7624
712bf364 7625void intel_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7626{
712bf364
VS		 7627 if (HAS_PCH_LPT(dev_priv))
7628 lpt_suspend_hw(dev_priv);
7d708ee4
ID		 7629}
7630
46f16e63 7631static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
bb400da9
ID		 7632{
7633 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7634}
7635
7636/**
7637 * intel_init_clock_gating_hooks - setup the clock gating hooks
7638 * @dev_priv: device private
7639 *
7640 * Setup the hooks that configure which clocks of a given platform can be
7641 * gated and also apply various GT and display specific workarounds for these
7642 * platforms. Note that some GT specific workarounds are applied separately
7643 * when GPU contexts or batchbuffers start their execution.
7644 */
7645void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7646{
7647 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7648 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7649 else if (IS_KABYLAKE(dev_priv))
9498dba7 7650 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
9fb5026f 7651 else if (IS_BROXTON(dev_priv))
bb400da9 7652 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
9fb5026f
ACO		 7653 else if (IS_GEMINILAKE(dev_priv))
7654 dev_priv->display.init_clock_gating = glk_init_clock_gating;
bb400da9
ID		 7655 else if (IS_BROADWELL(dev_priv))
7656 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7657 else if (IS_CHERRYVIEW(dev_priv))
7658 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7659 else if (IS_HASWELL(dev_priv))
7660 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7661 else if (IS_IVYBRIDGE(dev_priv))
7662 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7663 else if (IS_VALLEYVIEW(dev_priv))
7664 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7665 else if (IS_GEN6(dev_priv))
7666 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7667 else if (IS_GEN5(dev_priv))
7668 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7669 else if (IS_G4X(dev_priv))
7670 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
c0f86832 7671 else if (IS_I965GM(dev_priv))
bb400da9 7672 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
c0f86832 7673 else if (IS_I965G(dev_priv))
bb400da9
ID		 7674 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7675 else if (IS_GEN3(dev_priv))
7676 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7677 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7678 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7679 else if (IS_GEN2(dev_priv))
7680 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7681 else {
7682 MISSING_CASE(INTEL_DEVID(dev_priv));
7683 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7684 }
7685}
7686
1fa61106 7687/* Set up chip specific power management-related functions */
62d75df7 7688void intel_init_pm(struct drm_i915_private *dev_priv)
1fa61106 7689{
7ff0ebcc 7690 intel_fbc_init(dev_priv);
1fa61106 7691
c921aba8 7692 /* For cxsr */
9b1e14f4 7693 if (IS_PINEVIEW(dev_priv))
148ac1f3 7694 i915_pineview_get_mem_freq(dev_priv);
5db94019 7695 else if (IS_GEN5(dev_priv))
148ac1f3 7696 i915_ironlake_get_mem_freq(dev_priv);
c921aba8 7697
1fa61106 7698 /* For FIFO watermark updates */
62d75df7 7699 if (INTEL_GEN(dev_priv) >= 9) {
bb726519 7700 skl_setup_wm_latency(dev_priv);
e62929b3 7701 dev_priv->display.initial_watermarks = skl_initial_wm;
ccf010fb 7702 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
98d39494 7703 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7704 } else if (HAS_PCH_SPLIT(dev_priv)) {
bb726519 7705 ilk_setup_wm_latency(dev_priv);
53615a5e 7706
5db94019 7707 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7708 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7709 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7710 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7711 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7712 dev_priv->display.compute_intermediate_wm =
7713 ilk_compute_intermediate_wm;
7714 dev_priv->display.initial_watermarks =
7715 ilk_initial_watermarks;
7716 dev_priv->display.optimize_watermarks =
7717 ilk_optimize_watermarks;
bd602544
VS		 7718 } else {
7719 DRM_DEBUG_KMS("Failed to read display plane latency. "
7720 "Disable CxSR\n");
7721 }
6b6b3eef 7722 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
bb726519 7723 vlv_setup_wm_latency(dev_priv);
26e1fe4f 7724 dev_priv->display.update_wm = vlv_update_wm;
9b1e14f4 7725 } else if (IS_PINEVIEW(dev_priv)) {
50a0bc90 7726 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7727 dev_priv->is_ddr3,
7728 dev_priv->fsb_freq,
7729 dev_priv->mem_freq)) {
7730 DRM_INFO("failed to find known CxSR latency "
7731 "(found ddr%s fsb freq %d, mem freq %d), "
7732 "disabling CxSR\n",
7733 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7734 dev_priv->fsb_freq, dev_priv->mem_freq);
7735 /* Disable CxSR and never update its watermark again */
5209b1f4 7736 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7737 dev_priv->display.update_wm = NULL;
7738 } else
7739 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7740 } else if (IS_G4X(dev_priv)) {
1fa61106 7741 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7742 } else if (IS_GEN4(dev_priv)) {
1fa61106 7743 dev_priv->display.update_wm = i965_update_wm;
5db94019 7744 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7745 dev_priv->display.update_wm = i9xx_update_wm;
7746 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7747 } else if (IS_GEN2(dev_priv)) {
62d75df7 7748 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
feb56b93 7749 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7750 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7751 } else {
7752 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7753 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7754 }
feb56b93
DV		 7755 } else {
7756 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7757 }
7758}
7759
87660502
L		 7760static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7761{
7762 uint32_t flags =
7763 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7764
7765 switch (flags) {
7766 case GEN6_PCODE_SUCCESS:
7767 return 0;
7768 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7769 case GEN6_PCODE_ILLEGAL_CMD:
7770 return -ENXIO;
7771 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7772 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7773 return -EOVERFLOW;
7774 case GEN6_PCODE_TIMEOUT:
7775 return -ETIMEDOUT;
7776 default:
7777 MISSING_CASE(flags)
7778 return 0;
7779 }
7780}
7781
7782static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7783{
7784 uint32_t flags =
7785 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7786
7787 switch (flags) {
7788 case GEN6_PCODE_SUCCESS:
7789 return 0;
7790 case GEN6_PCODE_ILLEGAL_CMD:
7791 return -ENXIO;
7792 case GEN7_PCODE_TIMEOUT:
7793 return -ETIMEDOUT;
7794 case GEN7_PCODE_ILLEGAL_DATA:
7795 return -EINVAL;
7796 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7797 return -EOVERFLOW;
7798 default:
7799 MISSING_CASE(flags);
7800 return 0;
7801 }
7802}
7803
151a49d0 7804int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7805{
87660502
L		 7806 int status;
7807
4fc688ce 7808 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7809
3f5582dd
CW		 7810 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7811 * use te fw I915_READ variants to reduce the amount of work
7812 * required when reading/writing.
7813 */
7814
7815 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7816 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7817 return -EAGAIN;
7818 }
7819
3f5582dd
CW		 7820 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7821 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7822 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7823
3f5582dd
CW		 7824 if (intel_wait_for_register_fw(dev_priv,
7825 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7826 500)) {
42c0526c
BW		 7827 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7828 return -ETIMEDOUT;
7829 }
7830
3f5582dd
CW		 7831 *val = I915_READ_FW(GEN6_PCODE_DATA);
7832 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7833
87660502
L		 7834 if (INTEL_GEN(dev_priv) > 6)
7835 status = gen7_check_mailbox_status(dev_priv);
7836 else
7837 status = gen6_check_mailbox_status(dev_priv);
7838
7839 if (status) {
7840 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7841 status);
7842 return status;
7843 }
7844
42c0526c
BW		 7845 return 0;
7846}
7847
3f5582dd 7848int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7849 u32 mbox, u32 val)
42c0526c 7850{
87660502
L		 7851 int status;
7852
4fc688ce 7853 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7854
3f5582dd
CW		 7855 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7856 * use te fw I915_READ variants to reduce the amount of work
7857 * required when reading/writing.
7858 */
7859
7860 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7861 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7862 return -EAGAIN;
7863 }
7864
3f5582dd 7865 I915_WRITE_FW(GEN6_PCODE_DATA, val);
8bf41b72 7866 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
3f5582dd 7867 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7868
3f5582dd
CW		 7869 if (intel_wait_for_register_fw(dev_priv,
7870 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7871 500)) {
42c0526c
BW		 7872 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7873 return -ETIMEDOUT;
7874 }
7875
3f5582dd 7876 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7877
87660502
L		 7878 if (INTEL_GEN(dev_priv) > 6)
7879 status = gen7_check_mailbox_status(dev_priv);
7880 else
7881 status = gen6_check_mailbox_status(dev_priv);
7882
7883 if (status) {
7884 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7885 status);
7886 return status;
7887 }
7888
42c0526c
BW		 7889 return 0;
7890}
a0e4e199 7891
a0b8a1fe
ID		 7892static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7893 u32 request, u32 reply_mask, u32 reply,
7894 u32 *status)
7895{
7896 u32 val = request;
7897
7898 *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7899
7900 return *status || ((val & reply_mask) == reply);
7901}
7902
7903/**
7904 * skl_pcode_request - send PCODE request until acknowledgment
7905 * @dev_priv: device private
7906 * @mbox: PCODE mailbox ID the request is targeted for
7907 * @request: request ID
7908 * @reply_mask: mask used to check for request acknowledgment
7909 * @reply: value used to check for request acknowledgment
7910 * @timeout_base_ms: timeout for polling with preemption enabled
7911 *
7912 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7913 * reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
7914 * The request is acknowledged once the PCODE reply dword equals @reply after
7915 * applying @reply_mask. Polling is first attempted with preemption enabled
7916 * for @timeout_base_ms and if this times out for another 10 ms with
7917 * preemption disabled.
7918 *
7919 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7920 * other error as reported by PCODE.
7921 */
7922int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7923 u32 reply_mask, u32 reply, int timeout_base_ms)
7924{
7925 u32 status;
7926 int ret;
7927
7928 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7929
7930#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7931 &status)
7932
7933 /*
7934 * Prime the PCODE by doing a request first. Normally it guarantees
7935 * that a subsequent request, at most @timeout_base_ms later, succeeds.
7936 * _wait_for() doesn't guarantee when its passed condition is evaluated
7937 * first, so send the first request explicitly.
7938 */
7939 if (COND) {
7940 ret = 0;
7941 goto out;
7942 }
7943 ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7944 if (!ret)
7945 goto out;
7946
7947 /*
7948 * The above can time out if the number of requests was low (2 in the
7949 * worst case) _and_ PCODE was busy for some reason even after a
7950 * (queued) request and @timeout_base_ms delay. As a workaround retry
7951 * the poll with preemption disabled to maximize the number of
7952 * requests. Increase the timeout from @timeout_base_ms to 10ms to
7953 * account for interrupts that could reduce the number of these
7954 * requests.
7955 */
7956 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7957 WARN_ON_ONCE(timeout_base_ms > 3);
7958 preempt_disable();
7959 ret = wait_for_atomic(COND, 10);
7960 preempt_enable();
7961
7962out:
7963 return ret ? ret : status;
7964#undef COND
7965}
7966
dd06f88c
VS		 7967static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7968{
c30fec65
VS		 7969 /*
7970 * N = val - 0xb7
7971 * Slow = Fast = GPLL ref * N
7972 */
7973 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7974}
7975
b55dd647 7976static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7977{
c30fec65 7978 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7979}
7980
b55dd647 7981static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7982{
c30fec65
VS		 7983 /*
7984 * N = val / 2
7985 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7986 */
7987 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7988}
7989
b55dd647 7990static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7991{
1c14762d 7992 /* CHV needs even values */
c30fec65 7993 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7994}
7995
616bc820 7996int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7997{
2d1fe073 7998 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7999 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
8000 GEN9_FREQ_SCALER);
2d1fe073 8001 else if (IS_CHERRYVIEW(dev_priv))
616bc820 8002 return chv_gpu_freq(dev_priv, val);
2d1fe073 8003 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 8004 return byt_gpu_freq(dev_priv, val);
8005 else
8006 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 8007}
8008
616bc820
VS		 8009int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8010{
2d1fe073 8011 if (IS_GEN9(dev_priv))
500a3d2e
MK		 8012 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8013 GT_FREQUENCY_MULTIPLIER);
2d1fe073 8014 else if (IS_CHERRYVIEW(dev_priv))
616bc820 8015 return chv_freq_opcode(dev_priv, val);
2d1fe073 8016 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 8017 return byt_freq_opcode(dev_priv, val);
8018 else
500a3d2e 8019 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 8020}
22b1b2f8 8021
6ad790c0
CW		 8022struct request_boost {
8023 struct work_struct work;
eed29a5b 8024 struct drm_i915_gem_request *req;
6ad790c0
CW		 8025};
8026
8027static void __intel_rps_boost_work(struct work_struct *work)
8028{
8029 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 8030 struct drm_i915_gem_request *req = boost->req;
6ad790c0 8031
f69a02c9 8032 if (!i915_gem_request_completed(req))
c033666a 8033 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 8034
e8a261ea 8035 i915_gem_request_put(req);
6ad790c0
CW		 8036 kfree(boost);
8037}
8038
91d14251 8039void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8040{
8041 struct request_boost *boost;
8042
91d14251 8043 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8044 return;
8045
f69a02c9 8046 if (i915_gem_request_completed(req))
e61b9958
CW		 8047 return;
8048
6ad790c0
CW		 8049 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8050 if (boost == NULL)
8051 return;
8052
e8a261ea 8053 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8054
8055 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8056 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8057}
8058
192aa181 8059void intel_pm_setup(struct drm_i915_private *dev_priv)
907b28c5 8060{
f742a552 8061 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8062 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8063
54b4f68f
CW		 8064 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8065 __intel_autoenable_gt_powersave);
1854d5ca 8066 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8067
33688d95 8068 dev_priv->pm.suspended = false;
1f814dac 8069 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 8070}
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