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drm/i915: Pass dev_priv to intel_get_crtc_for_pipe()
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
b033bb6d 59static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 60{
32608ca2
ID		 61 struct drm_i915_private *dev_priv = dev->dev_private;
62
b033bb6d 63 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 64 I915_WRITE(CHICKEN_PAR1_1,
65 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
66
b033bb6d
MK		 67 I915_WRITE(GEN8_CONFIG0,
68 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 69
70 /* WaEnableChickenDCPR:skl,bxt,kbl */
71 I915_WRITE(GEN8_CHICKEN_DCPR_1,
72 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 73
74 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 75 /* WaFbcWakeMemOn:skl,bxt,kbl */
76 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
77 DISP_FBC_WM_DIS |
78 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 79
80 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
81 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
82 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 83}
84
85static void bxt_init_clock_gating(struct drm_device *dev)
86{
fac5e23e 87 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 88
89 gen9_init_clock_gating(dev);
90
a7546159
NH		 91 /* WaDisableSDEUnitClockGating:bxt */
92 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
93 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
94
32608ca2
ID		 95 /*
96 * FIXME:
868434c5 97 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 98 */
32608ca2 99 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 100 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 101
102 /*
103 * Wa: Backlight PWM may stop in the asserted state, causing backlight
104 * to stay fully on.
105 */
106 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
107 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
108 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 109}
110
c921aba8
DV		 111static void i915_pineview_get_mem_freq(struct drm_device *dev)
112{
fac5e23e 113 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 114 u32 tmp;
115
116 tmp = I915_READ(CLKCFG);
117
118 switch (tmp & CLKCFG_FSB_MASK) {
119 case CLKCFG_FSB_533:
120 dev_priv->fsb_freq = 533; /* 133*4 */
121 break;
122 case CLKCFG_FSB_800:
123 dev_priv->fsb_freq = 800; /* 200*4 */
124 break;
125 case CLKCFG_FSB_667:
126 dev_priv->fsb_freq = 667; /* 167*4 */
127 break;
128 case CLKCFG_FSB_400:
129 dev_priv->fsb_freq = 400; /* 100*4 */
130 break;
131 }
132
133 switch (tmp & CLKCFG_MEM_MASK) {
134 case CLKCFG_MEM_533:
135 dev_priv->mem_freq = 533;
136 break;
137 case CLKCFG_MEM_667:
138 dev_priv->mem_freq = 667;
139 break;
140 case CLKCFG_MEM_800:
141 dev_priv->mem_freq = 800;
142 break;
143 }
144
145 /* detect pineview DDR3 setting */
146 tmp = I915_READ(CSHRDDR3CTL);
147 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
148}
149
150static void i915_ironlake_get_mem_freq(struct drm_device *dev)
151{
fac5e23e 152 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 153 u16 ddrpll, csipll;
154
155 ddrpll = I915_READ16(DDRMPLL1);
156 csipll = I915_READ16(CSIPLL0);
157
158 switch (ddrpll & 0xff) {
159 case 0xc:
160 dev_priv->mem_freq = 800;
161 break;
162 case 0x10:
163 dev_priv->mem_freq = 1066;
164 break;
165 case 0x14:
166 dev_priv->mem_freq = 1333;
167 break;
168 case 0x18:
169 dev_priv->mem_freq = 1600;
170 break;
171 default:
172 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
173 ddrpll & 0xff);
174 dev_priv->mem_freq = 0;
175 break;
176 }
177
20e4d407 178 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 179
180 switch (csipll & 0x3ff) {
181 case 0x00c:
182 dev_priv->fsb_freq = 3200;
183 break;
184 case 0x00e:
185 dev_priv->fsb_freq = 3733;
186 break;
187 case 0x010:
188 dev_priv->fsb_freq = 4266;
189 break;
190 case 0x012:
191 dev_priv->fsb_freq = 4800;
192 break;
193 case 0x014:
194 dev_priv->fsb_freq = 5333;
195 break;
196 case 0x016:
197 dev_priv->fsb_freq = 5866;
198 break;
199 case 0x018:
200 dev_priv->fsb_freq = 6400;
201 break;
202 default:
203 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
204 csipll & 0x3ff);
205 dev_priv->fsb_freq = 0;
206 break;
207 }
208
209 if (dev_priv->fsb_freq == 3200) {
20e4d407 210 dev_priv->ips.c_m = 0;
c921aba8 211 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 212 dev_priv->ips.c_m = 1;
c921aba8 213 } else {
20e4d407 214 dev_priv->ips.c_m = 2;
c921aba8
DV		 215 }
216}
217
b445e3b0
ED		 218static const struct cxsr_latency cxsr_latency_table[] = {
219 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
220 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
221 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
222 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
223 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
224
225 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
226 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
227 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
228 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
229 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
230
231 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
232 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
233 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
234 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
235 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
236
237 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
238 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
239 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
240 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
241 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
242
243 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
244 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
245 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
246 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
247 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
248
249 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
250 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
251 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
252 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
253 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
254};
255
44a655ca
TU		 256static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
257 bool is_ddr3,
b445e3b0
ED		 258 int fsb,
259 int mem)
260{
261 const struct cxsr_latency *latency;
262 int i;
263
264 if (fsb == 0 || mem == 0)
265 return NULL;
266
267 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
268 latency = &cxsr_latency_table[i];
269 if (is_desktop == latency->is_desktop &&
270 is_ddr3 == latency->is_ddr3 &&
271 fsb == latency->fsb_freq && mem == latency->mem_freq)
272 return latency;
273 }
274
275 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
276
277 return NULL;
278}
279
fc1ac8de
VS		 280static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
281{
282 u32 val;
283
284 mutex_lock(&dev_priv->rps.hw_lock);
285
286 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
287 if (enable)
288 val &= ~FORCE_DDR_HIGH_FREQ;
289 else
290 val |= FORCE_DDR_HIGH_FREQ;
291 val &= ~FORCE_DDR_LOW_FREQ;
292 val |= FORCE_DDR_FREQ_REQ_ACK;
293 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
294
295 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
296 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
297 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
298
299 mutex_unlock(&dev_priv->rps.hw_lock);
300}
301
cfb41411
VS		 302static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
303{
304 u32 val;
305
306 mutex_lock(&dev_priv->rps.hw_lock);
307
308 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
309 if (enable)
310 val |= DSP_MAXFIFO_PM5_ENABLE;
311 else
312 val &= ~DSP_MAXFIFO_PM5_ENABLE;
313 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
314
315 mutex_unlock(&dev_priv->rps.hw_lock);
316}
317
f4998963
VS		 318#define FW_WM(value, plane) \
319 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
320
5209b1f4 321void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 322{
91c8a326 323 struct drm_device *dev = &dev_priv->drm;
5209b1f4 324 u32 val;
b445e3b0 325
920a14b2 326 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 327 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 328 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 329 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 330 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 331 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 332 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 333 } else if (IS_PINEVIEW(dev)) {
334 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
335 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
336 I915_WRITE(DSPFW3, val);
a7a6c498 337 POSTING_READ(DSPFW3);
50a0bc90 338 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 339 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
340 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
341 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 342 POSTING_READ(FW_BLC_SELF);
50a0bc90 343 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 344 /*
345 * FIXME can't find a bit like this for 915G, and
346 * and yet it does have the related watermark in
347 * FW_BLC_SELF. What's going on?
348 */
5209b1f4
ID		 349 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
350 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
351 I915_WRITE(INSTPM, val);
a7a6c498 352 POSTING_READ(INSTPM);
5209b1f4
ID		 353 } else {
354 return;
355 }
b445e3b0 356
5209b1f4
ID		 357 DRM_DEBUG_KMS("memory self-refresh is %s\n",
358 enable ? "enabled" : "disabled");
b445e3b0
ED		 359}
360
fc1ac8de 361
b445e3b0
ED		 362/*
363 * Latency for FIFO fetches is dependent on several factors:
364 * - memory configuration (speed, channels)
365 * - chipset
366 * - current MCH state
367 * It can be fairly high in some situations, so here we assume a fairly
368 * pessimal value. It's a tradeoff between extra memory fetches (if we
369 * set this value too high, the FIFO will fetch frequently to stay full)
370 * and power consumption (set it too low to save power and we might see
371 * FIFO underruns and display "flicker").
372 *
373 * A value of 5us seems to be a good balance; safe for very low end
374 * platforms but not overly aggressive on lower latency configs.
375 */
5aef6003 376static const int pessimal_latency_ns = 5000;
b445e3b0 377
b5004720
VS		 378#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
379 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
380
381static int vlv_get_fifo_size(struct drm_device *dev,
382 enum pipe pipe, int plane)
383{
fac5e23e 384 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 385 int sprite0_start, sprite1_start, size;
386
387 switch (pipe) {
388 uint32_t dsparb, dsparb2, dsparb3;
389 case PIPE_A:
390 dsparb = I915_READ(DSPARB);
391 dsparb2 = I915_READ(DSPARB2);
392 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
393 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
394 break;
395 case PIPE_B:
396 dsparb = I915_READ(DSPARB);
397 dsparb2 = I915_READ(DSPARB2);
398 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
399 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
400 break;
401 case PIPE_C:
402 dsparb2 = I915_READ(DSPARB2);
403 dsparb3 = I915_READ(DSPARB3);
404 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
405 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
406 break;
407 default:
408 return 0;
409 }
410
411 switch (plane) {
412 case 0:
413 size = sprite0_start;
414 break;
415 case 1:
416 size = sprite1_start - sprite0_start;
417 break;
418 case 2:
419 size = 512 - 1 - sprite1_start;
420 break;
421 default:
422 return 0;
423 }
424
425 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
426 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
427 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
428 size);
429
430 return size;
431}
432
1fa61106 433static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 434{
fac5e23e 435 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 436 uint32_t dsparb = I915_READ(DSPARB);
437 int size;
438
439 size = dsparb & 0x7f;
440 if (plane)
441 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
442
443 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
444 plane ? "B" : "A", size);
445
446 return size;
447}
448
feb56b93 449static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 450{
fac5e23e 451 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 452 uint32_t dsparb = I915_READ(DSPARB);
453 int size;
454
455 size = dsparb & 0x1ff;
456 if (plane)
457 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
458 size >>= 1; /* Convert to cachelines */
459
460 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
461 plane ? "B" : "A", size);
462
463 return size;
464}
465
1fa61106 466static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 467{
fac5e23e 468 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 469 uint32_t dsparb = I915_READ(DSPARB);
470 int size;
471
472 size = dsparb & 0x7f;
473 size >>= 2; /* Convert to cachelines */
474
475 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
476 plane ? "B" : "A",
477 size);
478
479 return size;
480}
481
b445e3b0
ED		 482/* Pineview has different values for various configs */
483static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 484 .fifo_size = PINEVIEW_DISPLAY_FIFO,
485 .max_wm = PINEVIEW_MAX_WM,
486 .default_wm = PINEVIEW_DFT_WM,
487 .guard_size = PINEVIEW_GUARD_WM,
488 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 489};
490static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 491 .fifo_size = PINEVIEW_DISPLAY_FIFO,
492 .max_wm = PINEVIEW_MAX_WM,
493 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
494 .guard_size = PINEVIEW_GUARD_WM,
495 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 498 .fifo_size = PINEVIEW_CURSOR_FIFO,
499 .max_wm = PINEVIEW_CURSOR_MAX_WM,
500 .default_wm = PINEVIEW_CURSOR_DFT_WM,
501 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
502 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 505 .fifo_size = PINEVIEW_CURSOR_FIFO,
506 .max_wm = PINEVIEW_CURSOR_MAX_WM,
507 .default_wm = PINEVIEW_CURSOR_DFT_WM,
508 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
509 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 510};
511static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 512 .fifo_size = G4X_FIFO_SIZE,
513 .max_wm = G4X_MAX_WM,
514 .default_wm = G4X_MAX_WM,
515 .guard_size = 2,
516 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 517};
518static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 519 .fifo_size = I965_CURSOR_FIFO,
520 .max_wm = I965_CURSOR_MAX_WM,
521 .default_wm = I965_CURSOR_DFT_WM,
522 .guard_size = 2,
523 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 524};
b445e3b0 525static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 526 .fifo_size = I965_CURSOR_FIFO,
527 .max_wm = I965_CURSOR_MAX_WM,
528 .default_wm = I965_CURSOR_DFT_WM,
529 .guard_size = 2,
530 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 533 .fifo_size = I945_FIFO_SIZE,
534 .max_wm = I915_MAX_WM,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 538};
539static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 540 .fifo_size = I915_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 545};
9d539105 546static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 547 .fifo_size = I855GM_FIFO_SIZE,
548 .max_wm = I915_MAX_WM,
549 .default_wm = 1,
550 .guard_size = 2,
551 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 552};
9d539105
VS		 553static const struct intel_watermark_params i830_bc_wm_info = {
554 .fifo_size = I855GM_FIFO_SIZE,
555 .max_wm = I915_MAX_WM/2,
556 .default_wm = 1,
557 .guard_size = 2,
558 .cacheline_size = I830_FIFO_LINE_SIZE,
559};
feb56b93 560static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 561 .fifo_size = I830_FIFO_SIZE,
562 .max_wm = I915_MAX_WM,
563 .default_wm = 1,
564 .guard_size = 2,
565 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 566};
567
b445e3b0
ED		 568/**
569 * intel_calculate_wm - calculate watermark level
570 * @clock_in_khz: pixel clock
571 * @wm: chip FIFO params
ac484963 572 * @cpp: bytes per pixel
b445e3b0
ED		 573 * @latency_ns: memory latency for the platform
574 *
575 * Calculate the watermark level (the level at which the display plane will
576 * start fetching from memory again). Each chip has a different display
577 * FIFO size and allocation, so the caller needs to figure that out and pass
578 * in the correct intel_watermark_params structure.
579 *
580 * As the pixel clock runs, the FIFO will be drained at a rate that depends
581 * on the pixel size. When it reaches the watermark level, it'll start
582 * fetching FIFO line sized based chunks from memory until the FIFO fills
583 * past the watermark point. If the FIFO drains completely, a FIFO underrun
584 * will occur, and a display engine hang could result.
585 */
586static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
587 const struct intel_watermark_params *wm,
ac484963 588 int fifo_size, int cpp,
b445e3b0
ED		 589 unsigned long latency_ns)
590{
591 long entries_required, wm_size;
592
593 /*
594 * Note: we need to make sure we don't overflow for various clock &
595 * latency values.
596 * clocks go from a few thousand to several hundred thousand.
597 * latency is usually a few thousand
598 */
ac484963 599 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 600 1000;
601 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
602
603 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
604
605 wm_size = fifo_size - (entries_required + wm->guard_size);
606
607 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
608
609 /* Don't promote wm_size to unsigned... */
610 if (wm_size > (long)wm->max_wm)
611 wm_size = wm->max_wm;
612 if (wm_size <= 0)
613 wm_size = wm->default_wm;
d6feb196
VS		 614
615 /*
616 * Bspec seems to indicate that the value shouldn't be lower than
617 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
618 * Lets go for 8 which is the burst size since certain platforms
619 * already use a hardcoded 8 (which is what the spec says should be
620 * done).
621 */
622 if (wm_size <= 8)
623 wm_size = 8;
624
b445e3b0
ED		 625 return wm_size;
626}
627
efc2611e 628static struct intel_crtc *single_enabled_crtc(struct drm_device *dev)
b445e3b0 629{
efc2611e 630 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 631
efc2611e
VS		 632 for_each_intel_crtc(dev, crtc) {
633 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 634 if (enabled)
635 return NULL;
636 enabled = crtc;
637 }
638 }
639
640 return enabled;
641}
642
432081bc 643static void pineview_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 644{
432081bc 645 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 646 struct drm_i915_private *dev_priv = to_i915(dev);
efc2611e 647 struct intel_crtc *crtc;
b445e3b0
ED		 648 const struct cxsr_latency *latency;
649 u32 reg;
650 unsigned long wm;
651
50a0bc90
TU		 652 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
653 dev_priv->is_ddr3,
654 dev_priv->fsb_freq,
655 dev_priv->mem_freq);
b445e3b0
ED		 656 if (!latency) {
657 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 658 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 659 return;
660 }
661
662 crtc = single_enabled_crtc(dev);
663 if (crtc) {
efc2611e
VS		 664 const struct drm_display_mode *adjusted_mode =
665 &crtc->config->base.adjusted_mode;
666 const struct drm_framebuffer *fb =
667 crtc->base.primary->state->fb;
668 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
7c5f93b0 669 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 670
671 /* Display SR */
672 wm = intel_calculate_wm(clock, &pineview_display_wm,
673 pineview_display_wm.fifo_size,
ac484963 674 cpp, latency->display_sr);
b445e3b0
ED		 675 reg = I915_READ(DSPFW1);
676 reg &= ~DSPFW_SR_MASK;
f4998963 677 reg |= FW_WM(wm, SR);
b445e3b0
ED		 678 I915_WRITE(DSPFW1, reg);
679 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
680
681 /* cursor SR */
682 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
683 pineview_display_wm.fifo_size,
ac484963 684 cpp, latency->cursor_sr);
b445e3b0
ED		 685 reg = I915_READ(DSPFW3);
686 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 687 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 688 I915_WRITE(DSPFW3, reg);
689
690 /* Display HPLL off SR */
691 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
692 pineview_display_hplloff_wm.fifo_size,
ac484963 693 cpp, latency->display_hpll_disable);
b445e3b0
ED		 694 reg = I915_READ(DSPFW3);
695 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 696 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 697 I915_WRITE(DSPFW3, reg);
698
699 /* cursor HPLL off SR */
700 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
701 pineview_display_hplloff_wm.fifo_size,
ac484963 702 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 703 reg = I915_READ(DSPFW3);
704 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 705 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 706 I915_WRITE(DSPFW3, reg);
707 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
708
5209b1f4 709 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 710 } else {
5209b1f4 711 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 712 }
713}
714
f0ce2310 715static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
b445e3b0
ED		 716 int plane,
717 const struct intel_watermark_params *display,
718 int display_latency_ns,
719 const struct intel_watermark_params *cursor,
720 int cursor_latency_ns,
721 int *plane_wm,
722 int *cursor_wm)
723{
efc2611e 724 struct intel_crtc *crtc;
4fe8590a 725 const struct drm_display_mode *adjusted_mode;
efc2611e 726 const struct drm_framebuffer *fb;
ac484963 727 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 728 int line_time_us, line_count;
729 int entries, tlb_miss;
730
b91eb5cc 731 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e 732 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 733 *cursor_wm = cursor->guard_size;
734 *plane_wm = display->guard_size;
735 return false;
736 }
737
efc2611e
VS		 738 adjusted_mode = &crtc->config->base.adjusted_mode;
739 fb = crtc->base.primary->state->fb;
241bfc38 740 clock = adjusted_mode->crtc_clock;
fec8cba3 741 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 742 hdisplay = crtc->config->pipe_src_w;
743 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 744
745 /* Use the small buffer method to calculate plane watermark */
ac484963 746 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 747 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
748 if (tlb_miss > 0)
749 entries += tlb_miss;
750 entries = DIV_ROUND_UP(entries, display->cacheline_size);
751 *plane_wm = entries + display->guard_size;
752 if (*plane_wm > (int)display->max_wm)
753 *plane_wm = display->max_wm;
754
755 /* Use the large buffer method to calculate cursor watermark */
922044c9 756 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 757 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
efc2611e 758 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
b445e3b0
ED		 759 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
760 if (tlb_miss > 0)
761 entries += tlb_miss;
762 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
763 *cursor_wm = entries + cursor->guard_size;
764 if (*cursor_wm > (int)cursor->max_wm)
765 *cursor_wm = (int)cursor->max_wm;
766
767 return true;
768}
769
770/*
771 * Check the wm result.
772 *
773 * If any calculated watermark values is larger than the maximum value that
774 * can be programmed into the associated watermark register, that watermark
775 * must be disabled.
776 */
f0ce2310 777static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 778 int display_wm, int cursor_wm,
779 const struct intel_watermark_params *display,
780 const struct intel_watermark_params *cursor)
781{
782 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
783 display_wm, cursor_wm);
784
785 if (display_wm > display->max_wm) {
ae9400ca 786 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 787 display_wm, display->max_wm);
788 return false;
789 }
790
791 if (cursor_wm > cursor->max_wm) {
ae9400ca 792 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 793 cursor_wm, cursor->max_wm);
794 return false;
795 }
796
797 if (!(display_wm || cursor_wm)) {
798 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
799 return false;
800 }
801
802 return true;
803}
804
f0ce2310 805static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 806 int plane,
807 int latency_ns,
808 const struct intel_watermark_params *display,
809 const struct intel_watermark_params *cursor,
810 int *display_wm, int *cursor_wm)
811{
efc2611e 812 struct intel_crtc *crtc;
4fe8590a 813 const struct drm_display_mode *adjusted_mode;
efc2611e 814 const struct drm_framebuffer *fb;
ac484963 815 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 816 unsigned long line_time_us;
817 int line_count, line_size;
818 int small, large;
819 int entries;
820
821 if (!latency_ns) {
822 *display_wm = *cursor_wm = 0;
823 return false;
824 }
825
b91eb5cc 826 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e
VS		 827 adjusted_mode = &crtc->config->base.adjusted_mode;
828 fb = crtc->base.primary->state->fb;
241bfc38 829 clock = adjusted_mode->crtc_clock;
fec8cba3 830 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 831 hdisplay = crtc->config->pipe_src_w;
832 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0 833
922044c9 834 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 835 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 836 line_size = hdisplay * cpp;
b445e3b0
ED		 837
838 /* Use the minimum of the small and large buffer method for primary */
ac484963 839 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 840 large = line_count * line_size;
841
842 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
843 *display_wm = entries + display->guard_size;
844
845 /* calculate the self-refresh watermark for display cursor */
efc2611e 846 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 847 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
848 *cursor_wm = entries + cursor->guard_size;
849
f0ce2310 850 return g4x_check_srwm(dev_priv,
b445e3b0
ED		 851 *display_wm, *cursor_wm,
852 display, cursor);
853}
854
15665979
VS		 855#define FW_WM_VLV(value, plane) \
856 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
857
0018fda1
VS		 858static void vlv_write_wm_values(struct intel_crtc *crtc,
859 const struct vlv_wm_values *wm)
860{
861 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
862 enum pipe pipe = crtc->pipe;
863
864 I915_WRITE(VLV_DDL(pipe),
865 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
866 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
867 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
868 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
869
ae80152d 870 I915_WRITE(DSPFW1,
15665979
VS		 871 FW_WM(wm->sr.plane, SR) |
872 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
873 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
874 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 875 I915_WRITE(DSPFW2,
15665979
VS		 876 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
877 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
878 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 879 I915_WRITE(DSPFW3,
15665979 880 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 881
882 if (IS_CHERRYVIEW(dev_priv)) {
883 I915_WRITE(DSPFW7_CHV,
15665979
VS		 884 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
885 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 886 I915_WRITE(DSPFW8_CHV,
15665979
VS		 887 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
888 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 889 I915_WRITE(DSPFW9_CHV,
15665979
VS		 890 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
891 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 892 I915_WRITE(DSPHOWM,
15665979
VS		 893 FW_WM(wm->sr.plane >> 9, SR_HI) |
894 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
895 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
896 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
897 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
898 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
899 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
900 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
901 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
902 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 903 } else {
904 I915_WRITE(DSPFW7,
15665979
VS		 905 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
906 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 907 I915_WRITE(DSPHOWM,
15665979
VS		 908 FW_WM(wm->sr.plane >> 9, SR_HI) |
909 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
910 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
911 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
912 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
913 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
914 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 915 }
916
2cb389b7
VS		 917 /* zero (unused) WM1 watermarks */
918 I915_WRITE(DSPFW4, 0);
919 I915_WRITE(DSPFW5, 0);
920 I915_WRITE(DSPFW6, 0);
921 I915_WRITE(DSPHOWM1, 0);
922
ae80152d 923 POSTING_READ(DSPFW1);
0018fda1
VS		 924}
925
15665979
VS		 926#undef FW_WM_VLV
927
6eb1a681
VS		 928enum vlv_wm_level {
929 VLV_WM_LEVEL_PM2,
930 VLV_WM_LEVEL_PM5,
931 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 932};
933
262cd2e1
VS		 934/* latency must be in 0.1us units. */
935static unsigned int vlv_wm_method2(unsigned int pixel_rate,
936 unsigned int pipe_htotal,
937 unsigned int horiz_pixels,
ac484963 938 unsigned int cpp,
262cd2e1
VS		 939 unsigned int latency)
940{
941 unsigned int ret;
942
943 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 944 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 945 ret = DIV_ROUND_UP(ret, 64);
946
947 return ret;
948}
949
950static void vlv_setup_wm_latency(struct drm_device *dev)
951{
fac5e23e 952 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 953
954 /* all latencies in usec */
955 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
956
58590c14
VS		 957 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
958
262cd2e1
VS		 959 if (IS_CHERRYVIEW(dev_priv)) {
960 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
961 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 962
963 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 964 }
965}
966
967static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
968 struct intel_crtc *crtc,
969 const struct intel_plane_state *state,
970 int level)
971{
972 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 973 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 974
975 if (dev_priv->wm.pri_latency[level] == 0)
976 return USHRT_MAX;
977
936e71e3 978 if (!state->base.visible)
262cd2e1
VS		 979 return 0;
980
ac484963 981 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 982 clock = crtc->config->base.adjusted_mode.crtc_clock;
983 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
984 width = crtc->config->pipe_src_w;
985 if (WARN_ON(htotal == 0))
986 htotal = 1;
987
988 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
989 /*
990 * FIXME the formula gives values that are
991 * too big for the cursor FIFO, and hence we
992 * would never be able to use cursors. For
993 * now just hardcode the watermark.
994 */
995 wm = 63;
996 } else {
ac484963 997 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 998 dev_priv->wm.pri_latency[level] * 10);
999 }
1000
1001 return min_t(int, wm, USHRT_MAX);
1002}
1003
54f1b6e1
VS		 1004static void vlv_compute_fifo(struct intel_crtc *crtc)
1005{
1006 struct drm_device *dev = crtc->base.dev;
1007 struct vlv_wm_state *wm_state = &crtc->wm_state;
1008 struct intel_plane *plane;
1009 unsigned int total_rate = 0;
1010 const int fifo_size = 512 - 1;
1011 int fifo_extra, fifo_left = fifo_size;
1012
1013 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1014 struct intel_plane_state *state =
1015 to_intel_plane_state(plane->base.state);
1016
1017 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1018 continue;
1019
936e71e3 1020 if (state->base.visible) {
54f1b6e1
VS		 1021 wm_state->num_active_planes++;
1022 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1023 }
1024 }
1025
1026 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1027 struct intel_plane_state *state =
1028 to_intel_plane_state(plane->base.state);
1029 unsigned int rate;
1030
1031 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1032 plane->wm.fifo_size = 63;
1033 continue;
1034 }
1035
936e71e3 1036 if (!state->base.visible) {
54f1b6e1
VS		 1037 plane->wm.fifo_size = 0;
1038 continue;
1039 }
1040
1041 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1042 plane->wm.fifo_size = fifo_size * rate / total_rate;
1043 fifo_left -= plane->wm.fifo_size;
1044 }
1045
1046 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1047
1048 /* spread the remainder evenly */
1049 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1050 int plane_extra;
1051
1052 if (fifo_left == 0)
1053 break;
1054
1055 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1056 continue;
1057
1058 /* give it all to the first plane if none are active */
1059 if (plane->wm.fifo_size == 0 &&
1060 wm_state->num_active_planes)
1061 continue;
1062
1063 plane_extra = min(fifo_extra, fifo_left);
1064 plane->wm.fifo_size += plane_extra;
1065 fifo_left -= plane_extra;
1066 }
1067
1068 WARN_ON(fifo_left != 0);
1069}
1070
262cd2e1
VS		 1071static void vlv_invert_wms(struct intel_crtc *crtc)
1072{
1073 struct vlv_wm_state *wm_state = &crtc->wm_state;
1074 int level;
1075
1076 for (level = 0; level < wm_state->num_levels; level++) {
1077 struct drm_device *dev = crtc->base.dev;
1078 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1079 struct intel_plane *plane;
1080
1081 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1082 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1083
1084 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1085 switch (plane->base.type) {
1086 int sprite;
1087 case DRM_PLANE_TYPE_CURSOR:
1088 wm_state->wm[level].cursor = plane->wm.fifo_size -
1089 wm_state->wm[level].cursor;
1090 break;
1091 case DRM_PLANE_TYPE_PRIMARY:
1092 wm_state->wm[level].primary = plane->wm.fifo_size -
1093 wm_state->wm[level].primary;
1094 break;
1095 case DRM_PLANE_TYPE_OVERLAY:
1096 sprite = plane->plane;
1097 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1098 wm_state->wm[level].sprite[sprite];
1099 break;
1100 }
1101 }
1102 }
1103}
1104
26e1fe4f 1105static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1106{
1107 struct drm_device *dev = crtc->base.dev;
1108 struct vlv_wm_state *wm_state = &crtc->wm_state;
1109 struct intel_plane *plane;
1110 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1111 int level;
1112
1113 memset(wm_state, 0, sizeof(*wm_state));
1114
852eb00d 1115 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1116 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1117
1118 wm_state->num_active_planes = 0;
262cd2e1 1119
54f1b6e1 1120 vlv_compute_fifo(crtc);
262cd2e1
VS		 1121
1122 if (wm_state->num_active_planes != 1)
1123 wm_state->cxsr = false;
1124
1125 if (wm_state->cxsr) {
1126 for (level = 0; level < wm_state->num_levels; level++) {
1127 wm_state->sr[level].plane = sr_fifo_size;
1128 wm_state->sr[level].cursor = 63;
1129 }
1130 }
1131
1132 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1133 struct intel_plane_state *state =
1134 to_intel_plane_state(plane->base.state);
1135
936e71e3 1136 if (!state->base.visible)
262cd2e1
VS		 1137 continue;
1138
1139 /* normal watermarks */
1140 for (level = 0; level < wm_state->num_levels; level++) {
1141 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1142 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1143
1144 /* hack */
1145 if (WARN_ON(level == 0 && wm > max_wm))
1146 wm = max_wm;
1147
1148 if (wm > plane->wm.fifo_size)
1149 break;
1150
1151 switch (plane->base.type) {
1152 int sprite;
1153 case DRM_PLANE_TYPE_CURSOR:
1154 wm_state->wm[level].cursor = wm;
1155 break;
1156 case DRM_PLANE_TYPE_PRIMARY:
1157 wm_state->wm[level].primary = wm;
1158 break;
1159 case DRM_PLANE_TYPE_OVERLAY:
1160 sprite = plane->plane;
1161 wm_state->wm[level].sprite[sprite] = wm;
1162 break;
1163 }
1164 }
1165
1166 wm_state->num_levels = level;
1167
1168 if (!wm_state->cxsr)
1169 continue;
1170
1171 /* maxfifo watermarks */
1172 switch (plane->base.type) {
1173 int sprite, level;
1174 case DRM_PLANE_TYPE_CURSOR:
1175 for (level = 0; level < wm_state->num_levels; level++)
1176 wm_state->sr[level].cursor =
5a37ed0a 1177 wm_state->wm[level].cursor;
262cd2e1
VS		 1178 break;
1179 case DRM_PLANE_TYPE_PRIMARY:
1180 for (level = 0; level < wm_state->num_levels; level++)
1181 wm_state->sr[level].plane =
1182 min(wm_state->sr[level].plane,
1183 wm_state->wm[level].primary);
1184 break;
1185 case DRM_PLANE_TYPE_OVERLAY:
1186 sprite = plane->plane;
1187 for (level = 0; level < wm_state->num_levels; level++)
1188 wm_state->sr[level].plane =
1189 min(wm_state->sr[level].plane,
1190 wm_state->wm[level].sprite[sprite]);
1191 break;
1192 }
1193 }
1194
1195 /* clear any (partially) filled invalid levels */
58590c14 1196 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1197 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1198 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1199 }
1200
1201 vlv_invert_wms(crtc);
1202}
1203
54f1b6e1
VS		 1204#define VLV_FIFO(plane, value) \
1205 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1206
1207static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1208{
1209 struct drm_device *dev = crtc->base.dev;
1210 struct drm_i915_private *dev_priv = to_i915(dev);
1211 struct intel_plane *plane;
1212 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1213
1214 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1215 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1216 WARN_ON(plane->wm.fifo_size != 63);
1217 continue;
1218 }
1219
1220 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1221 sprite0_start = plane->wm.fifo_size;
1222 else if (plane->plane == 0)
1223 sprite1_start = sprite0_start + plane->wm.fifo_size;
1224 else
1225 fifo_size = sprite1_start + plane->wm.fifo_size;
1226 }
1227
1228 WARN_ON(fifo_size != 512 - 1);
1229
1230 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1231 pipe_name(crtc->pipe), sprite0_start,
1232 sprite1_start, fifo_size);
1233
1234 switch (crtc->pipe) {
1235 uint32_t dsparb, dsparb2, dsparb3;
1236 case PIPE_A:
1237 dsparb = I915_READ(DSPARB);
1238 dsparb2 = I915_READ(DSPARB2);
1239
1240 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1241 VLV_FIFO(SPRITEB, 0xff));
1242 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1243 VLV_FIFO(SPRITEB, sprite1_start));
1244
1245 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1246 VLV_FIFO(SPRITEB_HI, 0x1));
1247 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1248 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1249
1250 I915_WRITE(DSPARB, dsparb);
1251 I915_WRITE(DSPARB2, dsparb2);
1252 break;
1253 case PIPE_B:
1254 dsparb = I915_READ(DSPARB);
1255 dsparb2 = I915_READ(DSPARB2);
1256
1257 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1258 VLV_FIFO(SPRITED, 0xff));
1259 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1260 VLV_FIFO(SPRITED, sprite1_start));
1261
1262 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1263 VLV_FIFO(SPRITED_HI, 0xff));
1264 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1265 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1266
1267 I915_WRITE(DSPARB, dsparb);
1268 I915_WRITE(DSPARB2, dsparb2);
1269 break;
1270 case PIPE_C:
1271 dsparb3 = I915_READ(DSPARB3);
1272 dsparb2 = I915_READ(DSPARB2);
1273
1274 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1275 VLV_FIFO(SPRITEF, 0xff));
1276 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1277 VLV_FIFO(SPRITEF, sprite1_start));
1278
1279 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1280 VLV_FIFO(SPRITEF_HI, 0xff));
1281 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1282 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1283
1284 I915_WRITE(DSPARB3, dsparb3);
1285 I915_WRITE(DSPARB2, dsparb2);
1286 break;
1287 default:
1288 break;
1289 }
1290}
1291
1292#undef VLV_FIFO
1293
262cd2e1
VS		 1294static void vlv_merge_wm(struct drm_device *dev,
1295 struct vlv_wm_values *wm)
1296{
1297 struct intel_crtc *crtc;
1298 int num_active_crtcs = 0;
1299
58590c14 1300 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1301 wm->cxsr = true;
1302
1303 for_each_intel_crtc(dev, crtc) {
1304 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1305
1306 if (!crtc->active)
1307 continue;
1308
1309 if (!wm_state->cxsr)
1310 wm->cxsr = false;
1311
1312 num_active_crtcs++;
1313 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1314 }
1315
1316 if (num_active_crtcs != 1)
1317 wm->cxsr = false;
1318
6f9c784b
VS		 1319 if (num_active_crtcs > 1)
1320 wm->level = VLV_WM_LEVEL_PM2;
1321
262cd2e1
VS		 1322 for_each_intel_crtc(dev, crtc) {
1323 struct vlv_wm_state *wm_state = &crtc->wm_state;
1324 enum pipe pipe = crtc->pipe;
1325
1326 if (!crtc->active)
1327 continue;
1328
1329 wm->pipe[pipe] = wm_state->wm[wm->level];
1330 if (wm->cxsr)
1331 wm->sr = wm_state->sr[wm->level];
1332
1333 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1334 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1335 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1336 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1337 }
1338}
1339
432081bc 1340static void vlv_update_wm(struct intel_crtc *crtc)
262cd2e1 1341{
432081bc 1342 struct drm_device *dev = crtc->base.dev;
fac5e23e 1343 struct drm_i915_private *dev_priv = to_i915(dev);
432081bc 1344 enum pipe pipe = crtc->pipe;
262cd2e1
VS		 1345 struct vlv_wm_values wm = {};
1346
432081bc 1347 vlv_compute_wm(crtc);
262cd2e1
VS		 1348 vlv_merge_wm(dev, &wm);
1349
54f1b6e1
VS		 1350 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1351 /* FIXME should be part of crtc atomic commit */
432081bc 1352 vlv_pipe_set_fifo_size(crtc);
262cd2e1 1353 return;
54f1b6e1 1354 }
262cd2e1
VS		 1355
1356 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1357 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1358 chv_set_memory_dvfs(dev_priv, false);
1359
1360 if (wm.level < VLV_WM_LEVEL_PM5 &&
1361 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1362 chv_set_memory_pm5(dev_priv, false);
1363
852eb00d 1364 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1365 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1366
54f1b6e1 1367 /* FIXME should be part of crtc atomic commit */
432081bc 1368 vlv_pipe_set_fifo_size(crtc);
54f1b6e1 1369
432081bc 1370 vlv_write_wm_values(crtc, &wm);
262cd2e1
VS		 1371
1372 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1373 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1374 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1375 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1376 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1377
852eb00d 1378 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1379 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1380
1381 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1382 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1383 chv_set_memory_pm5(dev_priv, true);
1384
1385 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1386 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1387 chv_set_memory_dvfs(dev_priv, true);
1388
1389 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1390}
1391
ae80152d
VS		 1392#define single_plane_enabled(mask) is_power_of_2(mask)
1393
432081bc 1394static void g4x_update_wm(struct intel_crtc *crtc)
b445e3b0 1395{
b91eb5cc 1396 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0 1397 static const int sr_latency_ns = 12000;
b445e3b0
ED		 1398 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1399 int plane_sr, cursor_sr;
1400 unsigned int enabled = 0;
9858425c 1401 bool cxsr_enabled;
b445e3b0 1402
f0ce2310 1403 if (g4x_compute_wm0(dev_priv, PIPE_A,
5aef6003
CW		 1404 &g4x_wm_info, pessimal_latency_ns,
1405 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1406 &planea_wm, &cursora_wm))
51cea1f4 1407 enabled |= 1 << PIPE_A;
b445e3b0 1408
f0ce2310 1409 if (g4x_compute_wm0(dev_priv, PIPE_B,
5aef6003
CW		 1410 &g4x_wm_info, pessimal_latency_ns,
1411 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1412 &planeb_wm, &cursorb_wm))
51cea1f4 1413 enabled |= 1 << PIPE_B;
b445e3b0 1414
b445e3b0 1415 if (single_plane_enabled(enabled) &&
f0ce2310 1416 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
b445e3b0
ED		 1417 sr_latency_ns,
1418 &g4x_wm_info,
1419 &g4x_cursor_wm_info,
52bd02d8 1420 &plane_sr, &cursor_sr)) {
9858425c 1421 cxsr_enabled = true;
52bd02d8 1422 } else {
9858425c 1423 cxsr_enabled = false;
5209b1f4 1424 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1425 plane_sr = cursor_sr = 0;
1426 }
b445e3b0 1427
a5043453
VS		 1428 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1429 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1430 planea_wm, cursora_wm,
1431 planeb_wm, cursorb_wm,
1432 plane_sr, cursor_sr);
1433
1434 I915_WRITE(DSPFW1,
f4998963
VS		 1435 FW_WM(plane_sr, SR) |
1436 FW_WM(cursorb_wm, CURSORB) |
1437 FW_WM(planeb_wm, PLANEB) |
1438 FW_WM(planea_wm, PLANEA));
b445e3b0 1439 I915_WRITE(DSPFW2,
8c919b28 1440 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1441 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1442 /* HPLL off in SR has some issues on G4x... disable it */
1443 I915_WRITE(DSPFW3,
8c919b28 1444 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1445 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1446
1447 if (cxsr_enabled)
1448 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1449}
1450
432081bc 1451static void i965_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1452{
432081bc 1453 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1454 struct drm_i915_private *dev_priv = to_i915(dev);
efc2611e 1455 struct intel_crtc *crtc;
b445e3b0
ED		 1456 int srwm = 1;
1457 int cursor_sr = 16;
9858425c 1458 bool cxsr_enabled;
b445e3b0
ED		 1459
1460 /* Calc sr entries for one plane configs */
1461 crtc = single_enabled_crtc(dev);
1462 if (crtc) {
1463 /* self-refresh has much higher latency */
1464 static const int sr_latency_ns = 12000;
efc2611e
VS		 1465 const struct drm_display_mode *adjusted_mode =
1466 &crtc->config->base.adjusted_mode;
1467 const struct drm_framebuffer *fb =
1468 crtc->base.primary->state->fb;
241bfc38 1469 int clock = adjusted_mode->crtc_clock;
fec8cba3 1470 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1471 int hdisplay = crtc->config->pipe_src_w;
1472 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 1473 unsigned long line_time_us;
1474 int entries;
1475
922044c9 1476 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1477
1478 /* Use ns/us then divide to preserve precision */
1479 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1480 cpp * hdisplay;
b445e3b0
ED		 1481 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1482 srwm = I965_FIFO_SIZE - entries;
1483 if (srwm < 0)
1484 srwm = 1;
1485 srwm &= 0x1ff;
1486 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1487 entries, srwm);
1488
1489 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
efc2611e 1490 cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 1491 entries = DIV_ROUND_UP(entries,
1492 i965_cursor_wm_info.cacheline_size);
1493 cursor_sr = i965_cursor_wm_info.fifo_size -
1494 (entries + i965_cursor_wm_info.guard_size);
1495
1496 if (cursor_sr > i965_cursor_wm_info.max_wm)
1497 cursor_sr = i965_cursor_wm_info.max_wm;
1498
1499 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1500 "cursor %d\n", srwm, cursor_sr);
1501
9858425c 1502 cxsr_enabled = true;
b445e3b0 1503 } else {
9858425c 1504 cxsr_enabled = false;
b445e3b0 1505 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1506 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1507 }
1508
1509 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1510 srwm);
1511
1512 /* 965 has limitations... */
f4998963
VS		 1513 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1514 FW_WM(8, CURSORB) |
1515 FW_WM(8, PLANEB) |
1516 FW_WM(8, PLANEA));
1517 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1518 FW_WM(8, PLANEC_OLD));
b445e3b0 1519 /* update cursor SR watermark */
f4998963 1520 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1521
1522 if (cxsr_enabled)
1523 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1524}
1525
f4998963
VS		 1526#undef FW_WM
1527
432081bc 1528static void i9xx_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1529{
432081bc 1530 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1531 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1532 const struct intel_watermark_params *wm_info;
1533 uint32_t fwater_lo;
1534 uint32_t fwater_hi;
1535 int cwm, srwm = 1;
1536 int fifo_size;
1537 int planea_wm, planeb_wm;
efc2611e 1538 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0
ED		 1539
1540 if (IS_I945GM(dev))
1541 wm_info = &i945_wm_info;
5db94019 1542 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1543 wm_info = &i915_wm_info;
1544 else
9d539105 1545 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1546
1547 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
b91eb5cc 1548 crtc = intel_get_crtc_for_plane(dev_priv, 0);
efc2611e
VS		 1549 if (intel_crtc_active(crtc)) {
1550 const struct drm_display_mode *adjusted_mode =
1551 &crtc->config->base.adjusted_mode;
1552 const struct drm_framebuffer *fb =
1553 crtc->base.primary->state->fb;
1554 int cpp;
1555
5db94019 1556 if (IS_GEN2(dev_priv))
b9e0bda3 1557 cpp = 4;
efc2611e
VS		 1558 else
1559 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1560
241bfc38 1561 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1562 wm_info, fifo_size, cpp,
5aef6003 1563 pessimal_latency_ns);
b445e3b0 1564 enabled = crtc;
9d539105 1565 } else {
b445e3b0 1566 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1567 if (planea_wm > (long)wm_info->max_wm)
1568 planea_wm = wm_info->max_wm;
1569 }
1570
5db94019 1571 if (IS_GEN2(dev_priv))
9d539105 1572 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1573
1574 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
b91eb5cc 1575 crtc = intel_get_crtc_for_plane(dev_priv, 1);
efc2611e
VS		 1576 if (intel_crtc_active(crtc)) {
1577 const struct drm_display_mode *adjusted_mode =
1578 &crtc->config->base.adjusted_mode;
1579 const struct drm_framebuffer *fb =
1580 crtc->base.primary->state->fb;
1581 int cpp;
1582
5db94019 1583 if (IS_GEN2(dev_priv))
b9e0bda3 1584 cpp = 4;
efc2611e
VS		 1585 else
1586 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1587
241bfc38 1588 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1589 wm_info, fifo_size, cpp,
5aef6003 1590 pessimal_latency_ns);
b445e3b0
ED		 1591 if (enabled == NULL)
1592 enabled = crtc;
1593 else
1594 enabled = NULL;
9d539105 1595 } else {
b445e3b0 1596 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1597 if (planeb_wm > (long)wm_info->max_wm)
1598 planeb_wm = wm_info->max_wm;
1599 }
b445e3b0
ED		 1600
1601 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1602
50a0bc90 1603 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1604 struct drm_i915_gem_object *obj;
2ab1bc9d 1605
efc2611e 1606 obj = intel_fb_obj(enabled->base.primary->state->fb);
2ab1bc9d
DV		 1607
1608 /* self-refresh seems busted with untiled */
3e510a8e 1609 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1610 enabled = NULL;
1611 }
1612
b445e3b0
ED		 1613 /*
1614 * Overlay gets an aggressive default since video jitter is bad.
1615 */
1616 cwm = 2;
1617
1618 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1619 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1620
1621 /* Calc sr entries for one plane configs */
1622 if (HAS_FW_BLC(dev) && enabled) {
1623 /* self-refresh has much higher latency */
1624 static const int sr_latency_ns = 6000;
efc2611e
VS		 1625 const struct drm_display_mode *adjusted_mode =
1626 &enabled->config->base.adjusted_mode;
1627 const struct drm_framebuffer *fb =
1628 enabled->base.primary->state->fb;
241bfc38 1629 int clock = adjusted_mode->crtc_clock;
fec8cba3 1630 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1631 int hdisplay = enabled->config->pipe_src_w;
1632 int cpp;
b445e3b0
ED		 1633 unsigned long line_time_us;
1634 int entries;
1635
50a0bc90 1636 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056 1637 cpp = 4;
efc2611e
VS		 1638 else
1639 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2d1b5056 1640
922044c9 1641 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1642
1643 /* Use ns/us then divide to preserve precision */
1644 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1645 cpp * hdisplay;
b445e3b0
ED		 1646 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1647 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1648 srwm = wm_info->fifo_size - entries;
1649 if (srwm < 0)
1650 srwm = 1;
1651
50a0bc90 1652 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1653 I915_WRITE(FW_BLC_SELF,
1654 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1655 else
b445e3b0
ED		 1656 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1657 }
1658
1659 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1660 planea_wm, planeb_wm, cwm, srwm);
1661
1662 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1663 fwater_hi = (cwm & 0x1f);
1664
1665 /* Set request length to 8 cachelines per fetch */
1666 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1667 fwater_hi = fwater_hi | (1 << 8);
1668
1669 I915_WRITE(FW_BLC, fwater_lo);
1670 I915_WRITE(FW_BLC2, fwater_hi);
1671
5209b1f4
ID		 1672 if (enabled)
1673 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1674}
1675
432081bc 1676static void i845_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1677{
432081bc 1678 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1679 struct drm_i915_private *dev_priv = to_i915(dev);
efc2611e 1680 struct intel_crtc *crtc;
241bfc38 1681 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1682 uint32_t fwater_lo;
1683 int planea_wm;
1684
1685 crtc = single_enabled_crtc(dev);
1686 if (crtc == NULL)
1687 return;
1688
efc2611e 1689 adjusted_mode = &crtc->config->base.adjusted_mode;
241bfc38 1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1691 &i845_wm_info,
b445e3b0 1692 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1693 4, pessimal_latency_ns);
b445e3b0
ED		 1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1696
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699 I915_WRITE(FW_BLC, fwater_lo);
1700}
1701
8cfb3407 1702uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1703{
fd4daa9c 1704 uint32_t pixel_rate;
801bcfff 1705
8cfb3407 1706 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1707
1708 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1709 * adjust the pixel_rate here. */
1710
8cfb3407 1711 if (pipe_config->pch_pfit.enabled) {
801bcfff 1712 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1713 uint32_t pfit_size = pipe_config->pch_pfit.size;
1714
1715 pipe_w = pipe_config->pipe_src_w;
1716 pipe_h = pipe_config->pipe_src_h;
801bcfff 1717
801bcfff
PZ		 1718 pfit_w = (pfit_size >> 16) & 0xFFFF;
1719 pfit_h = pfit_size & 0xFFFF;
1720 if (pipe_w < pfit_w)
1721 pipe_w = pfit_w;
1722 if (pipe_h < pfit_h)
1723 pipe_h = pfit_h;
1724
15126882
MR		 1725 if (WARN_ON(!pfit_w || !pfit_h))
1726 return pixel_rate;
1727
801bcfff
PZ		 1728 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1729 pfit_w * pfit_h);
1730 }
1731
1732 return pixel_rate;
1733}
1734
37126462 1735/* latency must be in 0.1us units. */
ac484963 1736static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1737{
1738 uint64_t ret;
1739
3312ba65
VS		 1740 if (WARN(latency == 0, "Latency value missing\n"))
1741 return UINT_MAX;
1742
ac484963 1743 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1744 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1745
1746 return ret;
1747}
1748
37126462 1749/* latency must be in 0.1us units. */
23297044 1750static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1751 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1752 uint32_t latency)
1753{
1754 uint32_t ret;
1755
3312ba65
VS		 1756 if (WARN(latency == 0, "Latency value missing\n"))
1757 return UINT_MAX;
15126882
MR		 1758 if (WARN_ON(!pipe_htotal))
1759 return UINT_MAX;
3312ba65 1760
801bcfff 1761 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1762 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1763 ret = DIV_ROUND_UP(ret, 64) + 2;
1764 return ret;
1765}
1766
23297044 1767static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1768 uint8_t cpp)
cca32e9a 1769{
15126882
MR		 1770 /*
1771 * Neither of these should be possible since this function shouldn't be
1772 * called if the CRTC is off or the plane is invisible. But let's be
1773 * extra paranoid to avoid a potential divide-by-zero if we screw up
1774 * elsewhere in the driver.
1775 */
ac484963 1776 if (WARN_ON(!cpp))
15126882
MR		 1777 return 0;
1778 if (WARN_ON(!horiz_pixels))
1779 return 0;
1780
ac484963 1781 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1782}
1783
820c1980 1784struct ilk_wm_maximums {
cca32e9a
PZ		 1785 uint16_t pri;
1786 uint16_t spr;
1787 uint16_t cur;
1788 uint16_t fbc;
1789};
1790
37126462
VS		 1791/*
1792 * For both WM_PIPE and WM_LP.
1793 * mem_value must be in 0.1us units.
1794 */
7221fc33 1795static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1796 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1797 uint32_t mem_value,
1798 bool is_lp)
801bcfff 1799{
ac484963
VS		 1800 int cpp = pstate->base.fb ?
1801 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1802 uint32_t method1, method2;
1803
936e71e3 1804 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1805 return 0;
1806
ac484963 1807 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1808
1809 if (!is_lp)
1810 return method1;
1811
7221fc33
MR		 1812 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1813 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1814 drm_rect_width(&pstate->base.dst),
ac484963 1815 cpp, mem_value);
cca32e9a
PZ		 1816
1817 return min(method1, method2);
801bcfff
PZ		 1818}
1819
37126462
VS		 1820/*
1821 * For both WM_PIPE and WM_LP.
1822 * mem_value must be in 0.1us units.
1823 */
7221fc33 1824static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1825 const struct intel_plane_state *pstate,
801bcfff
PZ		 1826 uint32_t mem_value)
1827{
ac484963
VS		 1828 int cpp = pstate->base.fb ?
1829 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1830 uint32_t method1, method2;
1831
936e71e3 1832 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1833 return 0;
1834
ac484963 1835 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1836 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1838 drm_rect_width(&pstate->base.dst),
ac484963 1839 cpp, mem_value);
801bcfff
PZ		 1840 return min(method1, method2);
1841}
1842
37126462
VS		 1843/*
1844 * For both WM_PIPE and WM_LP.
1845 * mem_value must be in 0.1us units.
1846 */
7221fc33 1847static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1848 const struct intel_plane_state *pstate,
801bcfff
PZ		 1849 uint32_t mem_value)
1850{
b2435692
MR		 1851 /*
1852 * We treat the cursor plane as always-on for the purposes of watermark
1853 * calculation. Until we have two-stage watermark programming merged,
1854 * this is necessary to avoid flickering.
1855 */
1856 int cpp = 4;
936e71e3 1857 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1858
b2435692 1859 if (!cstate->base.active)
801bcfff
PZ		 1860 return 0;
1861
7221fc33
MR		 1862 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1863 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1864 width, cpp, mem_value);
801bcfff
PZ		 1865}
1866
cca32e9a 1867/* Only for WM_LP. */
7221fc33 1868static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1869 const struct intel_plane_state *pstate,
1fda9882 1870 uint32_t pri_val)
cca32e9a 1871{
ac484963
VS		 1872 int cpp = pstate->base.fb ?
1873 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1874
936e71e3 1875 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1876 return 0;
1877
936e71e3 1878 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1879}
1880
158ae64f
VS		 1881static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1882{
416f4727
VS		 1883 if (INTEL_INFO(dev)->gen >= 8)
1884 return 3072;
1885 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1886 return 768;
1887 else
1888 return 512;
1889}
1890
4e975081
VS		 1891static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1892 int level, bool is_sprite)
1893{
1894 if (INTEL_INFO(dev)->gen >= 8)
1895 /* BDW primary/sprite plane watermarks */
1896 return level == 0 ? 255 : 2047;
1897 else if (INTEL_INFO(dev)->gen >= 7)
1898 /* IVB/HSW primary/sprite plane watermarks */
1899 return level == 0 ? 127 : 1023;
1900 else if (!is_sprite)
1901 /* ILK/SNB primary plane watermarks */
1902 return level == 0 ? 127 : 511;
1903 else
1904 /* ILK/SNB sprite plane watermarks */
1905 return level == 0 ? 63 : 255;
1906}
1907
1908static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1909 int level)
1910{
1911 if (INTEL_INFO(dev)->gen >= 7)
1912 return level == 0 ? 63 : 255;
1913 else
1914 return level == 0 ? 31 : 63;
1915}
1916
1917static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1918{
1919 if (INTEL_INFO(dev)->gen >= 8)
1920 return 31;
1921 else
1922 return 15;
1923}
1924
158ae64f
VS		 1925/* Calculate the maximum primary/sprite plane watermark */
1926static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1927 int level,
240264f4 1928 const struct intel_wm_config *config,
158ae64f
VS		 1929 enum intel_ddb_partitioning ddb_partitioning,
1930 bool is_sprite)
1931{
1932 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1933
1934 /* if sprites aren't enabled, sprites get nothing */
240264f4 1935 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1936 return 0;
1937
1938 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1939 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1940 fifo_size /= INTEL_INFO(dev)->num_pipes;
1941
1942 /*
1943 * For some reason the non self refresh
1944 * FIFO size is only half of the self
1945 * refresh FIFO size on ILK/SNB.
1946 */
1947 if (INTEL_INFO(dev)->gen <= 6)
1948 fifo_size /= 2;
1949 }
1950
240264f4 1951 if (config->sprites_enabled) {
158ae64f
VS		 1952 /* level 0 is always calculated with 1:1 split */
1953 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1954 if (is_sprite)
1955 fifo_size *= 5;
1956 fifo_size /= 6;
1957 } else {
1958 fifo_size /= 2;
1959 }
1960 }
1961
1962 /* clamp to max that the registers can hold */
4e975081 1963 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1964}
1965
1966/* Calculate the maximum cursor plane watermark */
1967static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1968 int level,
1969 const struct intel_wm_config *config)
158ae64f
VS		 1970{
1971 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1972 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1973 return 64;
1974
1975 /* otherwise just report max that registers can hold */
4e975081 1976 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1977}
1978
d34ff9c6 1979static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1980 int level,
1981 const struct intel_wm_config *config,
1982 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1983 struct ilk_wm_maximums *max)
158ae64f 1984{
240264f4
VS		 1985 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1986 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1987 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1988 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1989}
1990
a3cb4048
VS		 1991static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1992 int level,
1993 struct ilk_wm_maximums *max)
1994{
1995 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1996 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1997 max->cur = ilk_cursor_wm_reg_max(dev, level);
1998 max->fbc = ilk_fbc_wm_reg_max(dev);
1999}
2000
d9395655 2001static bool ilk_validate_wm_level(int level,
820c1980 2002 const struct ilk_wm_maximums *max,
d9395655 2003 struct intel_wm_level *result)
a9786a11
VS		 2004{
2005 bool ret;
2006
2007 /* already determined to be invalid? */
2008 if (!result->enable)
2009 return false;
2010
2011 result->enable = result->pri_val <= max->pri &&
2012 result->spr_val <= max->spr &&
2013 result->cur_val <= max->cur;
2014
2015 ret = result->enable;
2016
2017 /*
2018 * HACK until we can pre-compute everything,
2019 * and thus fail gracefully if LP0 watermarks
2020 * are exceeded...
2021 */
2022 if (level == 0 && !result->enable) {
2023 if (result->pri_val > max->pri)
2024 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2025 level, result->pri_val, max->pri);
2026 if (result->spr_val > max->spr)
2027 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2028 level, result->spr_val, max->spr);
2029 if (result->cur_val > max->cur)
2030 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2031 level, result->cur_val, max->cur);
2032
2033 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2034 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2035 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2036 result->enable = true;
2037 }
2038
a9786a11
VS		 2039 return ret;
2040}
2041
d34ff9c6 2042static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2043 const struct intel_crtc *intel_crtc,
6f5ddd17 2044 int level,
7221fc33 2045 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2046 struct intel_plane_state *pristate,
2047 struct intel_plane_state *sprstate,
2048 struct intel_plane_state *curstate,
1fd527cc 2049 struct intel_wm_level *result)
6f5ddd17
VS		 2050{
2051 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2052 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2053 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2054
2055 /* WM1+ latency values stored in 0.5us units */
2056 if (level > 0) {
2057 pri_latency *= 5;
2058 spr_latency *= 5;
2059 cur_latency *= 5;
2060 }
2061
e3bddded
ML		 2062 if (pristate) {
2063 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2064 pri_latency, level);
2065 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2066 }
2067
2068 if (sprstate)
2069 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2070
2071 if (curstate)
2072 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2073
6f5ddd17
VS		 2074 result->enable = true;
2075}
2076
801bcfff 2077static uint32_t
532f7a7f 2078hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2079{
532f7a7f
VS		 2080 const struct intel_atomic_state *intel_state =
2081 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2082 const struct drm_display_mode *adjusted_mode =
2083 &cstate->base.adjusted_mode;
85a02deb 2084 u32 linetime, ips_linetime;
1f8eeabf 2085
ee91a159
MR		 2086 if (!cstate->base.active)
2087 return 0;
2088 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2089 return 0;
532f7a7f 2090 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2091 return 0;
1011d8c4 2092
1f8eeabf
ED		 2093 /* The WM are computed with base on how long it takes to fill a single
2094 * row at the given clock rate, multiplied by 8.
2095 * */
124abe07
VS		 2096 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2097 adjusted_mode->crtc_clock);
2098 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2099 intel_state->cdclk);
1f8eeabf 2100
801bcfff
PZ		 2101 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2102 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2103}
2104
2af30a5c 2105static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2106{
fac5e23e 2107 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2108
5db94019 2109 if (IS_GEN9(dev_priv)) {
2af30a5c 2110 uint32_t val;
4f947386 2111 int ret, i;
5db94019 2112 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2113
2114 /* read the first set of memory latencies[0:3] */
2115 val = 0; /* data0 to be programmed to 0 for first set */
2116 mutex_lock(&dev_priv->rps.hw_lock);
2117 ret = sandybridge_pcode_read(dev_priv,
2118 GEN9_PCODE_READ_MEM_LATENCY,
2119 &val);
2120 mutex_unlock(&dev_priv->rps.hw_lock);
2121
2122 if (ret) {
2123 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2124 return;
2125 }
2126
2127 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2131 GEN9_MEM_LATENCY_LEVEL_MASK;
2132 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2133 GEN9_MEM_LATENCY_LEVEL_MASK;
2134
2135 /* read the second set of memory latencies[4:7] */
2136 val = 1; /* data0 to be programmed to 1 for second set */
2137 mutex_lock(&dev_priv->rps.hw_lock);
2138 ret = sandybridge_pcode_read(dev_priv,
2139 GEN9_PCODE_READ_MEM_LATENCY,
2140 &val);
2141 mutex_unlock(&dev_priv->rps.hw_lock);
2142 if (ret) {
2143 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2144 return;
2145 }
2146
2147 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2148 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2149 GEN9_MEM_LATENCY_LEVEL_MASK;
2150 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2151 GEN9_MEM_LATENCY_LEVEL_MASK;
2152 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2153 GEN9_MEM_LATENCY_LEVEL_MASK;
2154
0727e40a
PZ		 2155 /*
2156 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2157 * need to be disabled. We make sure to sanitize the values out
2158 * of the punit to satisfy this requirement.
2159 */
2160 for (level = 1; level <= max_level; level++) {
2161 if (wm[level] == 0) {
2162 for (i = level + 1; i <= max_level; i++)
2163 wm[i] = 0;
2164 break;
2165 }
2166 }
2167
367294be 2168 /*
6f97235b
DL		 2169 * WaWmMemoryReadLatency:skl
2170 *
367294be 2171 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2172 * to add 2us to the various latency levels we retrieve from the
2173 * punit when level 0 response data us 0us.
367294be 2174 */
0727e40a
PZ		 2175 if (wm[0] == 0) {
2176 wm[0] += 2;
2177 for (level = 1; level <= max_level; level++) {
2178 if (wm[level] == 0)
2179 break;
367294be 2180 wm[level] += 2;
4f947386 2181 }
0727e40a
PZ		 2182 }
2183
8652744b 2184 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2185 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2186
2187 wm[0] = (sskpd >> 56) & 0xFF;
2188 if (wm[0] == 0)
2189 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2190 wm[1] = (sskpd >> 4) & 0xFF;
2191 wm[2] = (sskpd >> 12) & 0xFF;
2192 wm[3] = (sskpd >> 20) & 0x1FF;
2193 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2194 } else if (INTEL_INFO(dev)->gen >= 6) {
2195 uint32_t sskpd = I915_READ(MCH_SSKPD);
2196
2197 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2198 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2199 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2200 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2201 } else if (INTEL_INFO(dev)->gen >= 5) {
2202 uint32_t mltr = I915_READ(MLTR_ILK);
2203
2204 /* ILK primary LP0 latency is 700 ns */
2205 wm[0] = 7;
2206 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2207 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2208 }
2209}
2210
5db94019
TU		 2211static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2212 uint16_t wm[5])
53615a5e
VS		 2213{
2214 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2215 if (IS_GEN5(dev_priv))
53615a5e
VS		 2216 wm[0] = 13;
2217}
2218
fd6b8f43
TU		 2219static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2220 uint16_t wm[5])
53615a5e
VS		 2221{
2222 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2223 if (IS_GEN5(dev_priv))
53615a5e
VS		 2224 wm[0] = 13;
2225
2226 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2227 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2228 wm[3] *= 2;
2229}
2230
5db94019 2231int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2232{
26ec971e 2233 /* how many WM levels are we expecting */
8652744b 2234 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2235 return 7;
8652744b 2236 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2237 return 4;
8652744b 2238 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2239 return 3;
26ec971e 2240 else
ad0d6dc4
VS		 2241 return 2;
2242}
7526ed79 2243
5db94019 2244static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2245 const char *name,
2af30a5c 2246 const uint16_t wm[8])
ad0d6dc4 2247{
5db94019 2248 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2249
2250 for (level = 0; level <= max_level; level++) {
2251 unsigned int latency = wm[level];
2252
2253 if (latency == 0) {
2254 DRM_ERROR("%s WM%d latency not provided\n",
2255 name, level);
2256 continue;
2257 }
2258
2af30a5c
PB		 2259 /*
2260 * - latencies are in us on gen9.
2261 * - before then, WM1+ latency values are in 0.5us units
2262 */
5db94019 2263 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2264 latency *= 10;
2265 else if (level > 0)
26ec971e
VS		 2266 latency *= 5;
2267
2268 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2269 name, level, wm[level],
2270 latency / 10, latency % 10);
2271 }
2272}
2273
e95a2f75
VS		 2274static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2275 uint16_t wm[5], uint16_t min)
2276{
5db94019 2277 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2278
2279 if (wm[0] >= min)
2280 return false;
2281
2282 wm[0] = max(wm[0], min);
2283 for (level = 1; level <= max_level; level++)
2284 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2285
2286 return true;
2287}
2288
2289static void snb_wm_latency_quirk(struct drm_device *dev)
2290{
fac5e23e 2291 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2292 bool changed;
2293
2294 /*
2295 * The BIOS provided WM memory latency values are often
2296 * inadequate for high resolution displays. Adjust them.
2297 */
2298 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2299 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2300 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2301
2302 if (!changed)
2303 return;
2304
2305 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2306 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2307 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2308 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2309}
2310
fa50ad61 2311static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2312{
fac5e23e 2313 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2314
2315 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2316
2317 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2318 sizeof(dev_priv->wm.pri_latency));
2319 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2320 sizeof(dev_priv->wm.pri_latency));
2321
5db94019 2322 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2323 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2324
5db94019
TU		 2325 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2326 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2327 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2328
5db94019 2329 if (IS_GEN6(dev_priv))
e95a2f75 2330 snb_wm_latency_quirk(dev);
53615a5e
VS		 2331}
2332
2af30a5c
PB		 2333static void skl_setup_wm_latency(struct drm_device *dev)
2334{
fac5e23e 2335 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2336
2337 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
5db94019 2338 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2339}
2340
ed4a6a7c
MR		 2341static bool ilk_validate_pipe_wm(struct drm_device *dev,
2342 struct intel_pipe_wm *pipe_wm)
2343{
2344 /* LP0 watermark maximums depend on this pipe alone */
2345 const struct intel_wm_config config = {
2346 .num_pipes_active = 1,
2347 .sprites_enabled = pipe_wm->sprites_enabled,
2348 .sprites_scaled = pipe_wm->sprites_scaled,
2349 };
2350 struct ilk_wm_maximums max;
2351
2352 /* LP0 watermarks always use 1/2 DDB partitioning */
2353 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2354
2355 /* At least LP0 must be valid */
2356 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2357 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2358 return false;
2359 }
2360
2361 return true;
2362}
2363
0b2ae6d7 2364/* Compute new watermarks for the pipe */
e3bddded 2365static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2366{
e3bddded
ML		 2367 struct drm_atomic_state *state = cstate->base.state;
2368 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2369 struct intel_pipe_wm *pipe_wm;
e3bddded 2370 struct drm_device *dev = state->dev;
fac5e23e 2371 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2372 struct intel_plane *intel_plane;
86c8bbbe 2373 struct intel_plane_state *pristate = NULL;
43d59eda 2374 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2375 struct intel_plane_state *curstate = NULL;
5db94019 2376 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2377 struct ilk_wm_maximums max;
0b2ae6d7 2378
e8f1f02e 2379 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2380
43d59eda 2381 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2382 struct intel_plane_state *ps;
2383
2384 ps = intel_atomic_get_existing_plane_state(state,
2385 intel_plane);
2386 if (!ps)
2387 continue;
86c8bbbe
MR		 2388
2389 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2390 pristate = ps;
86c8bbbe 2391 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2392 sprstate = ps;
86c8bbbe 2393 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2394 curstate = ps;
43d59eda
MR		 2395 }
2396
ed4a6a7c 2397 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2398 if (sprstate) {
936e71e3
VS		 2399 pipe_wm->sprites_enabled = sprstate->base.visible;
2400 pipe_wm->sprites_scaled = sprstate->base.visible &&
2401 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2402 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2403 }
2404
d81f04c5
ML		 2405 usable_level = max_level;
2406
7b39a0b7 2407 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2408 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2409 usable_level = 1;
7b39a0b7
VS		 2410
2411 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2412 if (pipe_wm->sprites_scaled)
d81f04c5 2413 usable_level = 0;
7b39a0b7 2414
86c8bbbe 2415 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2416 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2417
2418 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2419 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2420
8652744b 2421 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2422 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2423
ed4a6a7c 2424 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2425 return -EINVAL;
a3cb4048
VS		 2426
2427 ilk_compute_wm_reg_maximums(dev, 1, &max);
2428
2429 for (level = 1; level <= max_level; level++) {
71f0a626 2430 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2431
86c8bbbe 2432 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2433 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2434
2435 /*
2436 * Disable any watermark level that exceeds the
2437 * register maximums since such watermarks are
2438 * always invalid.
2439 */
71f0a626
ML		 2440 if (level > usable_level)
2441 continue;
2442
2443 if (ilk_validate_wm_level(level, &max, wm))
2444 pipe_wm->wm[level] = *wm;
2445 else
d81f04c5 2446 usable_level = level;
a3cb4048
VS		 2447 }
2448
86c8bbbe 2449 return 0;
0b2ae6d7
VS		 2450}
2451
ed4a6a7c
MR		 2452/*
2453 * Build a set of 'intermediate' watermark values that satisfy both the old
2454 * state and the new state. These can be programmed to the hardware
2455 * immediately.
2456 */
2457static int ilk_compute_intermediate_wm(struct drm_device *dev,
2458 struct intel_crtc *intel_crtc,
2459 struct intel_crtc_state *newstate)
2460{
e8f1f02e 2461 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2462 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2463 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2464
2465 /*
2466 * Start with the final, target watermarks, then combine with the
2467 * currently active watermarks to get values that are safe both before
2468 * and after the vblank.
2469 */
e8f1f02e 2470 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2471 a->pipe_enabled |= b->pipe_enabled;
2472 a->sprites_enabled |= b->sprites_enabled;
2473 a->sprites_scaled |= b->sprites_scaled;
2474
2475 for (level = 0; level <= max_level; level++) {
2476 struct intel_wm_level *a_wm = &a->wm[level];
2477 const struct intel_wm_level *b_wm = &b->wm[level];
2478
2479 a_wm->enable &= b_wm->enable;
2480 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2481 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2482 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2483 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2484 }
2485
2486 /*
2487 * We need to make sure that these merged watermark values are
2488 * actually a valid configuration themselves. If they're not,
2489 * there's no safe way to transition from the old state to
2490 * the new state, so we need to fail the atomic transaction.
2491 */
2492 if (!ilk_validate_pipe_wm(dev, a))
2493 return -EINVAL;
2494
2495 /*
2496 * If our intermediate WM are identical to the final WM, then we can
2497 * omit the post-vblank programming; only update if it's different.
2498 */
e8f1f02e 2499 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2500 newstate->wm.need_postvbl_update = false;
2501
2502 return 0;
2503}
2504
0b2ae6d7
VS		 2505/*
2506 * Merge the watermarks from all active pipes for a specific level.
2507 */
2508static void ilk_merge_wm_level(struct drm_device *dev,
2509 int level,
2510 struct intel_wm_level *ret_wm)
2511{
2512 const struct intel_crtc *intel_crtc;
2513
d52fea5b
VS		 2514 ret_wm->enable = true;
2515
d3fcc808 2516 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2517 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2518 const struct intel_wm_level *wm = &active->wm[level];
2519
2520 if (!active->pipe_enabled)
2521 continue;
0b2ae6d7 2522
d52fea5b
VS		 2523 /*
2524 * The watermark values may have been used in the past,
2525 * so we must maintain them in the registers for some
2526 * time even if the level is now disabled.
2527 */
0b2ae6d7 2528 if (!wm->enable)
d52fea5b 2529 ret_wm->enable = false;
0b2ae6d7
VS		 2530
2531 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2532 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2533 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2534 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2535 }
0b2ae6d7
VS		 2536}
2537
2538/*
2539 * Merge all low power watermarks for all active pipes.
2540 */
2541static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2542 const struct intel_wm_config *config,
820c1980 2543 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2544 struct intel_pipe_wm *merged)
2545{
fac5e23e 2546 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2547 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2548 int last_enabled_level = max_level;
0b2ae6d7 2549
0ba22e26 2550 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2551 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2552 config->num_pipes_active > 1)
1204d5ba 2553 last_enabled_level = 0;
0ba22e26 2554
6c8b6c28
VS		 2555 /* ILK: FBC WM must be disabled always */
2556 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2557
2558 /* merge each WM1+ level */
2559 for (level = 1; level <= max_level; level++) {
2560 struct intel_wm_level *wm = &merged->wm[level];
2561
2562 ilk_merge_wm_level(dev, level, wm);
2563
d52fea5b
VS		 2564 if (level > last_enabled_level)
2565 wm->enable = false;
2566 else if (!ilk_validate_wm_level(level, max, wm))
2567 /* make sure all following levels get disabled */
2568 last_enabled_level = level - 1;
0b2ae6d7
VS		 2569
2570 /*
2571 * The spec says it is preferred to disable
2572 * FBC WMs instead of disabling a WM level.
2573 */
2574 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2575 if (wm->enable)
2576 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2577 wm->fbc_val = 0;
2578 }
2579 }
6c8b6c28
VS		 2580
2581 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2582 /*
2583 * FIXME this is racy. FBC might get enabled later.
2584 * What we should check here is whether FBC can be
2585 * enabled sometime later.
2586 */
5db94019 2587 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2588 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2589 for (level = 2; level <= max_level; level++) {
2590 struct intel_wm_level *wm = &merged->wm[level];
2591
2592 wm->enable = false;
2593 }
2594 }
0b2ae6d7
VS		 2595}
2596
b380ca3c
VS		 2597static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2598{
2599 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2600 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2601}
2602
a68d68ee
VS		 2603/* The value we need to program into the WM_LPx latency field */
2604static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2605{
fac5e23e 2606 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2607
8652744b 2608 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2609 return 2 * level;
2610 else
2611 return dev_priv->wm.pri_latency[level];
2612}
2613
820c1980 2614static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2615 const struct intel_pipe_wm *merged,
609cedef 2616 enum intel_ddb_partitioning partitioning,
820c1980 2617 struct ilk_wm_values *results)
801bcfff 2618{
0b2ae6d7
VS		 2619 struct intel_crtc *intel_crtc;
2620 int level, wm_lp;
cca32e9a 2621
0362c781 2622 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2623 results->partitioning = partitioning;
cca32e9a 2624
0b2ae6d7 2625 /* LP1+ register values */
cca32e9a 2626 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2627 const struct intel_wm_level *r;
801bcfff 2628
b380ca3c 2629 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2630
0362c781 2631 r = &merged->wm[level];
cca32e9a 2632
d52fea5b
VS		 2633 /*
2634 * Maintain the watermark values even if the level is
2635 * disabled. Doing otherwise could cause underruns.
2636 */
2637 results->wm_lp[wm_lp - 1] =
a68d68ee 2638 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2639 (r->pri_val << WM1_LP_SR_SHIFT) |
2640 r->cur_val;
2641
d52fea5b
VS		 2642 if (r->enable)
2643 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2644
416f4727
VS		 2645 if (INTEL_INFO(dev)->gen >= 8)
2646 results->wm_lp[wm_lp - 1] |=
2647 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2648 else
2649 results->wm_lp[wm_lp - 1] |=
2650 r->fbc_val << WM1_LP_FBC_SHIFT;
2651
d52fea5b
VS		 2652 /*
2653 * Always set WM1S_LP_EN when spr_val != 0, even if the
2654 * level is disabled. Doing otherwise could cause underruns.
2655 */
6cef2b8a
VS		 2656 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2657 WARN_ON(wm_lp != 1);
2658 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2659 } else
2660 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2661 }
801bcfff 2662
0b2ae6d7 2663 /* LP0 register values */
d3fcc808 2664 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2665 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2666 const struct intel_wm_level *r =
2667 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2668
2669 if (WARN_ON(!r->enable))
2670 continue;
2671
ed4a6a7c 2672 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2673
0b2ae6d7
VS		 2674 results->wm_pipe[pipe] =
2675 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2676 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2677 r->cur_val;
801bcfff
PZ		 2678 }
2679}
2680
861f3389
PZ		 2681/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2682 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2683static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2684 struct intel_pipe_wm *r1,
2685 struct intel_pipe_wm *r2)
861f3389 2686{
5db94019 2687 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2688 int level1 = 0, level2 = 0;
861f3389 2689
198a1e9b
VS		 2690 for (level = 1; level <= max_level; level++) {
2691 if (r1->wm[level].enable)
2692 level1 = level;
2693 if (r2->wm[level].enable)
2694 level2 = level;
861f3389
PZ		 2695 }
2696
198a1e9b
VS		 2697 if (level1 == level2) {
2698 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2699 return r2;
2700 else
2701 return r1;
198a1e9b 2702 } else if (level1 > level2) {
861f3389
PZ		 2703 return r1;
2704 } else {
2705 return r2;
2706 }
2707}
2708
49a687c4
VS		 2709/* dirty bits used to track which watermarks need changes */
2710#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2711#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2712#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2713#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2714#define WM_DIRTY_FBC (1 << 24)
2715#define WM_DIRTY_DDB (1 << 25)
2716
055e393f 2717static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2718 const struct ilk_wm_values *old,
2719 const struct ilk_wm_values *new)
49a687c4
VS		 2720{
2721 unsigned int dirty = 0;
2722 enum pipe pipe;
2723 int wm_lp;
2724
055e393f 2725 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2726 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2727 dirty |= WM_DIRTY_LINETIME(pipe);
2728 /* Must disable LP1+ watermarks too */
2729 dirty |= WM_DIRTY_LP_ALL;
2730 }
2731
2732 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2733 dirty |= WM_DIRTY_PIPE(pipe);
2734 /* Must disable LP1+ watermarks too */
2735 dirty |= WM_DIRTY_LP_ALL;
2736 }
2737 }
2738
2739 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2740 dirty |= WM_DIRTY_FBC;
2741 /* Must disable LP1+ watermarks too */
2742 dirty |= WM_DIRTY_LP_ALL;
2743 }
2744
2745 if (old->partitioning != new->partitioning) {
2746 dirty |= WM_DIRTY_DDB;
2747 /* Must disable LP1+ watermarks too */
2748 dirty |= WM_DIRTY_LP_ALL;
2749 }
2750
2751 /* LP1+ watermarks already deemed dirty, no need to continue */
2752 if (dirty & WM_DIRTY_LP_ALL)
2753 return dirty;
2754
2755 /* Find the lowest numbered LP1+ watermark in need of an update... */
2756 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2757 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2758 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2759 break;
2760 }
2761
2762 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2763 for (; wm_lp <= 3; wm_lp++)
2764 dirty |= WM_DIRTY_LP(wm_lp);
2765
2766 return dirty;
2767}
2768
8553c18e
VS		 2769static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2770 unsigned int dirty)
801bcfff 2771{
820c1980 2772 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2773 bool changed = false;
801bcfff 2774
facd619b
VS		 2775 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2776 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2777 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2778 changed = true;
facd619b
VS		 2779 }
2780 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2781 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2782 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2783 changed = true;
facd619b
VS		 2784 }
2785 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2786 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2787 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2788 changed = true;
facd619b 2789 }
801bcfff 2790
facd619b
VS		 2791 /*
2792 * Don't touch WM1S_LP_EN here.
2793 * Doing so could cause underruns.
2794 */
6cef2b8a 2795
8553c18e
VS		 2796 return changed;
2797}
2798
2799/*
2800 * The spec says we shouldn't write when we don't need, because every write
2801 * causes WMs to be re-evaluated, expending some power.
2802 */
820c1980
ID		 2803static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2804 struct ilk_wm_values *results)
8553c18e 2805{
91c8a326 2806 struct drm_device *dev = &dev_priv->drm;
820c1980 2807 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2808 unsigned int dirty;
2809 uint32_t val;
2810
055e393f 2811 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2812 if (!dirty)
2813 return;
2814
2815 _ilk_disable_lp_wm(dev_priv, dirty);
2816
49a687c4 2817 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2818 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2819 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2820 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2821 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2822 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2823
49a687c4 2824 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2825 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2826 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2827 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2828 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2829 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2830
49a687c4 2831 if (dirty & WM_DIRTY_DDB) {
8652744b 2832 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2833 val = I915_READ(WM_MISC);
2834 if (results->partitioning == INTEL_DDB_PART_1_2)
2835 val &= ~WM_MISC_DATA_PARTITION_5_6;
2836 else
2837 val |= WM_MISC_DATA_PARTITION_5_6;
2838 I915_WRITE(WM_MISC, val);
2839 } else {
2840 val = I915_READ(DISP_ARB_CTL2);
2841 if (results->partitioning == INTEL_DDB_PART_1_2)
2842 val &= ~DISP_DATA_PARTITION_5_6;
2843 else
2844 val |= DISP_DATA_PARTITION_5_6;
2845 I915_WRITE(DISP_ARB_CTL2, val);
2846 }
1011d8c4
PZ		 2847 }
2848
49a687c4 2849 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2850 val = I915_READ(DISP_ARB_CTL);
2851 if (results->enable_fbc_wm)
2852 val &= ~DISP_FBC_WM_DIS;
2853 else
2854 val |= DISP_FBC_WM_DIS;
2855 I915_WRITE(DISP_ARB_CTL, val);
2856 }
2857
954911eb
ID		 2858 if (dirty & WM_DIRTY_LP(1) &&
2859 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2860 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2861
2862 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2863 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2864 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2865 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2866 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2867 }
801bcfff 2868
facd619b 2869 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2870 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2871 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2872 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2873 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2874 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2875
2876 dev_priv->wm.hw = *results;
801bcfff
PZ		 2877}
2878
ed4a6a7c 2879bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2880{
fac5e23e 2881 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2882
2883 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2884}
2885
656d1b89 2886#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2887
024c9045
MR		 2888/*
2889 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2890 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2891 * other universal planes are in indices 1..n. Note that this may leave unused
2892 * indices between the top "sprite" plane and the cursor.
2893 */
2894static int
2895skl_wm_plane_id(const struct intel_plane *plane)
2896{
2897 switch (plane->base.type) {
2898 case DRM_PLANE_TYPE_PRIMARY:
2899 return 0;
2900 case DRM_PLANE_TYPE_CURSOR:
2901 return PLANE_CURSOR;
2902 case DRM_PLANE_TYPE_OVERLAY:
2903 return plane->plane + 1;
2904 default:
2905 MISSING_CASE(plane->base.type);
2906 return plane->plane;
2907 }
2908}
2909
ee3d532f
PZ		 2910/*
2911 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2912 * so assume we'll always need it in order to avoid underruns.
2913 */
2914static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2915{
2916 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2917
2918 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2919 IS_KABYLAKE(dev_priv))
2920 return true;
2921
2922 return false;
2923}
2924
56feca91
PZ		 2925static bool
2926intel_has_sagv(struct drm_i915_private *dev_priv)
2927{
6e3100ec
PZ		 2928 if (IS_KABYLAKE(dev_priv))
2929 return true;
2930
2931 if (IS_SKYLAKE(dev_priv) &&
2932 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2933 return true;
2934
2935 return false;
56feca91
PZ		 2936}
2937
656d1b89
L		 2938/*
2939 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2940 * depending on power and performance requirements. The display engine access
2941 * to system memory is blocked during the adjustment time. Because of the
2942 * blocking time, having this enabled can cause full system hangs and/or pipe
2943 * underruns if we don't meet all of the following requirements:
2944 *
2945 * - <= 1 pipe enabled
2946 * - All planes can enable watermarks for latencies >= SAGV engine block time
2947 * - We're not using an interlaced display configuration
2948 */
2949int
16dcdc4e 2950intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2951{
2952 int ret;
2953
56feca91
PZ		 2954 if (!intel_has_sagv(dev_priv))
2955 return 0;
2956
2957 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2958 return 0;
2959
2960 DRM_DEBUG_KMS("Enabling the SAGV\n");
2961 mutex_lock(&dev_priv->rps.hw_lock);
2962
2963 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2964 GEN9_SAGV_ENABLE);
2965
2966 /* We don't need to wait for the SAGV when enabling */
2967 mutex_unlock(&dev_priv->rps.hw_lock);
2968
2969 /*
2970 * Some skl systems, pre-release machines in particular,
2971 * don't actually have an SAGV.
2972 */
6e3100ec 2973 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2974 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2975 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2976 return 0;
2977 } else if (ret < 0) {
2978 DRM_ERROR("Failed to enable the SAGV\n");
2979 return ret;
2980 }
2981
16dcdc4e 2982 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2983 return 0;
2984}
2985
2986static int
16dcdc4e 2987intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2988{
2989 int ret;
2990 uint32_t temp = GEN9_SAGV_DISABLE;
2991
2992 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2993 &temp);
2994 if (ret)
2995 return ret;
2996 else
2997 return temp & GEN9_SAGV_IS_DISABLED;
2998}
2999
3000int
16dcdc4e 3001intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 3002{
3003 int ret, result;
3004
56feca91
PZ		 3005 if (!intel_has_sagv(dev_priv))
3006 return 0;
3007
3008 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 3009 return 0;
3010
3011 DRM_DEBUG_KMS("Disabling the SAGV\n");
3012 mutex_lock(&dev_priv->rps.hw_lock);
3013
3014 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 3015 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 3016 mutex_unlock(&dev_priv->rps.hw_lock);
3017
3018 if (ret == -ETIMEDOUT) {
3019 DRM_ERROR("Request to disable SAGV timed out\n");
3020 return -ETIMEDOUT;
3021 }
3022
3023 /*
3024 * Some skl systems, pre-release machines in particular,
3025 * don't actually have an SAGV.
3026 */
6e3100ec 3027 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 3028 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3029 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3030 return 0;
3031 } else if (result < 0) {
3032 DRM_ERROR("Failed to disable the SAGV\n");
3033 return result;
3034 }
3035
16dcdc4e 3036 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3037 return 0;
3038}
3039
16dcdc4e 3040bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3041{
3042 struct drm_device *dev = state->dev;
3043 struct drm_i915_private *dev_priv = to_i915(dev);
3044 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3045 struct intel_crtc *crtc;
3046 struct intel_plane *plane;
d8c0fafc 3047 struct intel_crtc_state *cstate;
3048 struct skl_plane_wm *wm;
656d1b89 3049 enum pipe pipe;
d8c0fafc 3050 int level, latency;
656d1b89 3051
56feca91
PZ		 3052 if (!intel_has_sagv(dev_priv))
3053 return false;
3054
656d1b89
L		 3055 /*
3056 * SKL workaround: bspec recommends we disable the SAGV when we have
3057 * more then one pipe enabled
3058 *
3059 * If there are no active CRTCs, no additional checks need be performed
3060 */
3061 if (hweight32(intel_state->active_crtcs) == 0)
3062 return true;
3063 else if (hweight32(intel_state->active_crtcs) > 1)
3064 return false;
3065
3066 /* Since we're now guaranteed to only have one active CRTC... */
3067 pipe = ffs(intel_state->active_crtcs) - 1;
e2af48c6 3068 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
d8c0fafc 3069 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3070
c89cadd5 3071 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3072 return false;
3073
ee3d532f 3074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d8c0fafc 3075 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
ee3d532f 3076
656d1b89 3077 /* Skip this plane if it's not enabled */
d8c0fafc 3078 if (!wm->wm[0].plane_en)
656d1b89
L		 3079 continue;
3080
3081 /* Find the highest enabled wm level for this plane */
5db94019 3082 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3083 !wm->wm[level].plane_en; --level)
656d1b89
L		 3084 { }
3085
ee3d532f
PZ		 3086 latency = dev_priv->wm.skl_latency[level];
3087
3088 if (skl_needs_memory_bw_wa(intel_state) &&
3089 plane->base.state->fb->modifier[0] ==
3090 I915_FORMAT_MOD_X_TILED)
3091 latency += 15;
3092
656d1b89
L		 3093 /*
3094 * If any of the planes on this pipe don't enable wm levels
3095 * that incur memory latencies higher then 30µs we can't enable
3096 * the SAGV
3097 */
ee3d532f 3098 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3099 return false;
3100 }
3101
3102 return true;
3103}
3104
b9cec075
DL		 3105static void
3106skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3107 const struct intel_crtc_state *cstate,
c107acfe
MR		 3108 struct skl_ddb_entry *alloc, /* out */
3109 int *num_active /* out */)
b9cec075 3110{
c107acfe
MR		 3111 struct drm_atomic_state *state = cstate->base.state;
3112 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3113 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3114 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3115 unsigned int pipe_size, ddb_size;
3116 int nth_active_pipe;
c107acfe 3117
a6d3460e 3118 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3119 alloc->start = 0;
3120 alloc->end = 0;
a6d3460e 3121 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3122 return;
3123 }
3124
a6d3460e
MR		 3125 if (intel_state->active_pipe_changes)
3126 *num_active = hweight32(intel_state->active_crtcs);
3127 else
3128 *num_active = hweight32(dev_priv->active_crtcs);
3129
6f3fff60
D		 3130 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3131 WARN_ON(ddb_size == 0);
b9cec075
DL		 3132
3133 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3134
c107acfe 3135 /*
a6d3460e
MR		 3136 * If the state doesn't change the active CRTC's, then there's
3137 * no need to recalculate; the existing pipe allocation limits
3138 * should remain unchanged. Note that we're safe from racing
3139 * commits since any racing commit that changes the active CRTC
3140 * list would need to grab _all_ crtc locks, including the one
3141 * we currently hold.
c107acfe 3142 */
a6d3460e 3143 if (!intel_state->active_pipe_changes) {
ce0ba283 3144 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
a6d3460e 3145 return;
c107acfe 3146 }
a6d3460e
MR		 3147
3148 nth_active_pipe = hweight32(intel_state->active_crtcs &
3149 (drm_crtc_mask(for_crtc) - 1));
3150 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3151 alloc->start = nth_active_pipe * ddb_size / *num_active;
3152 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3153}
3154
c107acfe 3155static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3156{
c107acfe 3157 if (num_active == 1)
b9cec075
DL		 3158 return 32;
3159
3160 return 8;
3161}
3162
a269c583
DL		 3163static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3164{
3165 entry->start = reg & 0x3ff;
3166 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3167 if (entry->end)
3168 entry->end += 1;
a269c583
DL		 3169}
3170
08db6652
DL		 3171void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3172 struct skl_ddb_allocation *ddb /* out */)
a269c583 3173{
a269c583
DL		 3174 enum pipe pipe;
3175 int plane;
3176 u32 val;
3177
b10f1b20
ML		 3178 memset(ddb, 0, sizeof(*ddb));
3179
a269c583 3180 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3181 enum intel_display_power_domain power_domain;
3182
3183 power_domain = POWER_DOMAIN_PIPE(pipe);
3184 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3185 continue;
3186
8b364b41 3187 for_each_universal_plane(dev_priv, pipe, plane) {
a269c583
DL		 3188 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3189 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3190 val);
3191 }
3192
3193 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3194 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3195 val);
4d800030
ID		 3196
3197 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3198 }
3199}
3200
9c2f7a9d
KM		 3201/*
3202 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3203 * The bspec defines downscale amount as:
3204 *
3205 * """
3206 * Horizontal down scale amount = maximum[1, Horizontal source size /
3207 * Horizontal destination size]
3208 * Vertical down scale amount = maximum[1, Vertical source size /
3209 * Vertical destination size]
3210 * Total down scale amount = Horizontal down scale amount *
3211 * Vertical down scale amount
3212 * """
3213 *
3214 * Return value is provided in 16.16 fixed point form to retain fractional part.
3215 * Caller should take care of dividing & rounding off the value.
3216 */
3217static uint32_t
3218skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3219{
3220 uint32_t downscale_h, downscale_w;
3221 uint32_t src_w, src_h, dst_w, dst_h;
3222
936e71e3 3223 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3224 return DRM_PLANE_HELPER_NO_SCALING;
3225
3226 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3227 src_w = drm_rect_width(&pstate->base.src);
3228 src_h = drm_rect_height(&pstate->base.src);
3229 dst_w = drm_rect_width(&pstate->base.dst);
3230 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3231 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3232 swap(dst_w, dst_h);
3233
3234 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3235 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3236
3237 /* Provide result in 16.16 fixed point */
3238 return (uint64_t)downscale_w * downscale_h >> 16;
3239}
3240
b9cec075 3241static unsigned int
024c9045
MR		 3242skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3243 const struct drm_plane_state *pstate,
3244 int y)
b9cec075 3245{
a280f7dd 3246 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3247 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3248 uint32_t down_scale_amount, data_rate;
a280f7dd 3249 uint32_t width = 0, height = 0;
a1de91e5
MR		 3250 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3251
936e71e3 3252 if (!intel_pstate->base.visible)
a1de91e5
MR		 3253 return 0;
3254 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3255 return 0;
3256 if (y && format != DRM_FORMAT_NV12)
3257 return 0;
a280f7dd 3258
936e71e3
VS		 3259 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3260 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3261
bd2ef25d 3262 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3263 swap(width, height);
2cd601c6
CK		 3264
3265 /* for planar format */
a1de91e5 3266 if (format == DRM_FORMAT_NV12) {
2cd601c6 3267 if (y) /* y-plane data rate */
8d19d7d9 3268 data_rate = width * height *
a1de91e5 3269 drm_format_plane_cpp(format, 0);
2cd601c6 3270 else /* uv-plane data rate */
8d19d7d9 3271 data_rate = (width / 2) * (height / 2) *
a1de91e5 3272 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3273 } else {
3274 /* for packed formats */
3275 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3276 }
3277
8d19d7d9
KM		 3278 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3279
3280 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3281}
3282
3283/*
3284 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3285 * a 8192x4096@32bpp framebuffer:
3286 * 3 * 4096 * 8192 * 4 < 2^32
3287 */
3288static unsigned int
1e6ee542
ML		 3289skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3290 unsigned *plane_data_rate,
3291 unsigned *plane_y_data_rate)
b9cec075 3292{
9c74d826
MR		 3293 struct drm_crtc_state *cstate = &intel_cstate->base;
3294 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3295 struct drm_plane *plane;
024c9045 3296 const struct intel_plane *intel_plane;
c8fe32c1 3297 const struct drm_plane_state *pstate;
a1de91e5 3298 unsigned int rate, total_data_rate = 0;
9c74d826 3299 int id;
a6d3460e
MR		 3300
3301 if (WARN_ON(!state))
3302 return 0;
b9cec075 3303
a1de91e5 3304 /* Calculate and cache data rate for each plane */
c8fe32c1 3305 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
a6d3460e
MR		 3306 id = skl_wm_plane_id(to_intel_plane(plane));
3307 intel_plane = to_intel_plane(plane);
3308
a6d3460e
MR		 3309 /* packed/uv */
3310 rate = skl_plane_relative_data_rate(intel_cstate,
3311 pstate, 0);
1e6ee542
ML		 3312 plane_data_rate[id] = rate;
3313
3314 total_data_rate += rate;
a6d3460e
MR		 3315
3316 /* y-plane */
3317 rate = skl_plane_relative_data_rate(intel_cstate,
3318 pstate, 1);
1e6ee542 3319 plane_y_data_rate[id] = rate;
024c9045 3320
1e6ee542 3321 total_data_rate += rate;
b9cec075
DL		 3322 }
3323
3324 return total_data_rate;
3325}
3326
cbcfd14b
KM		 3327static uint16_t
3328skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3329 const int y)
3330{
3331 struct drm_framebuffer *fb = pstate->fb;
3332 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3333 uint32_t src_w, src_h;
3334 uint32_t min_scanlines = 8;
3335 uint8_t plane_bpp;
3336
3337 if (WARN_ON(!fb))
3338 return 0;
3339
3340 /* For packed formats, no y-plane, return 0 */
3341 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3342 return 0;
3343
3344 /* For Non Y-tile return 8-blocks */
3345 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3346 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3347 return 8;
3348
936e71e3
VS		 3349 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3350 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3351
bd2ef25d 3352 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3353 swap(src_w, src_h);
3354
3355 /* Halve UV plane width and height for NV12 */
3356 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3357 src_w /= 2;
3358 src_h /= 2;
3359 }
3360
3361 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3362 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3363 else
3364 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3365
bd2ef25d 3366 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3367 switch (plane_bpp) {
3368 case 1:
3369 min_scanlines = 32;
3370 break;
3371 case 2:
3372 min_scanlines = 16;
3373 break;
3374 case 4:
3375 min_scanlines = 8;
3376 break;
3377 case 8:
3378 min_scanlines = 4;
3379 break;
3380 default:
3381 WARN(1, "Unsupported pixel depth %u for rotation",
3382 plane_bpp);
3383 min_scanlines = 32;
3384 }
3385 }
3386
3387 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3388}
3389
49845a7a
ML		 3390static void
3391skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3392 uint16_t *minimum, uint16_t *y_minimum)
3393{
3394 const struct drm_plane_state *pstate;
3395 struct drm_plane *plane;
3396
3397 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3398 struct intel_plane *intel_plane = to_intel_plane(plane);
3399 int id = skl_wm_plane_id(intel_plane);
3400
3401 if (id == PLANE_CURSOR)
3402 continue;
3403
3404 if (!pstate->visible)
3405 continue;
3406
3407 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3408 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3409 }
3410
3411 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3412}
3413
c107acfe 3414static int
024c9045 3415skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3416 struct skl_ddb_allocation *ddb /* out */)
3417{
c107acfe 3418 struct drm_atomic_state *state = cstate->base.state;
024c9045 3419 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3420 struct drm_device *dev = crtc->dev;
3421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3422 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3423 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
49845a7a 3424 uint16_t alloc_size, start;
fefdd810
ML		 3425 uint16_t minimum[I915_MAX_PLANES] = {};
3426 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3427 unsigned int total_data_rate;
c107acfe
MR		 3428 int num_active;
3429 int id, i;
1e6ee542
ML		 3430 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3431 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3432
5a920b85
PZ		 3433 /* Clear the partitioning for disabled planes. */
3434 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3435 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3436
a6d3460e
MR		 3437 if (WARN_ON(!state))
3438 return 0;
3439
c107acfe 3440 if (!cstate->base.active) {
ce0ba283 3441 alloc->start = alloc->end = 0;
c107acfe
MR		 3442 return 0;
3443 }
3444
a6d3460e 3445 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3446 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3447 if (alloc_size == 0) {
3448 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3449 return 0;
b9cec075
DL		 3450 }
3451
49845a7a 3452 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
a6d3460e 3453
49845a7a
ML		 3454 /*
3455 * 1. Allocate the mininum required blocks for each active plane
3456 * and allocate the cursor, it doesn't require extra allocation
3457 * proportional to the data rate.
3458 */
80958155 3459
49845a7a 3460 for (i = 0; i < I915_MAX_PLANES; i++) {
c107acfe
MR		 3461 alloc_size -= minimum[i];
3462 alloc_size -= y_minimum[i];
80958155
DL		 3463 }
3464
49845a7a
ML		 3465 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3466 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3467
b9cec075 3468 /*
80958155
DL		 3469 * 2. Distribute the remaining space in proportion to the amount of
3470 * data each plane needs to fetch from memory.
b9cec075
DL		 3471 *
3472 * FIXME: we may not allocate every single block here.
3473 */
1e6ee542
ML		 3474 total_data_rate = skl_get_total_relative_data_rate(cstate,
3475 plane_data_rate,
3476 plane_y_data_rate);
a1de91e5 3477 if (total_data_rate == 0)
c107acfe 3478 return 0;
b9cec075 3479
34bb56af 3480 start = alloc->start;
1e6ee542 3481 for (id = 0; id < I915_MAX_PLANES; id++) {
2cd601c6
CK		 3482 unsigned int data_rate, y_data_rate;
3483 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3484
49845a7a
ML		 3485 if (id == PLANE_CURSOR)
3486 continue;
3487
1e6ee542 3488 data_rate = plane_data_rate[id];
b9cec075
DL		 3489
3490 /*
2cd601c6 3491 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3492 * promote the expression to 64 bits to avoid overflowing, the
3493 * result is < available as data_rate / total_data_rate < 1
3494 */
024c9045 3495 plane_blocks = minimum[id];
80958155
DL		 3496 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3497 total_data_rate);
b9cec075 3498
c107acfe
MR		 3499 /* Leave disabled planes at (0,0) */
3500 if (data_rate) {
3501 ddb->plane[pipe][id].start = start;
3502 ddb->plane[pipe][id].end = start + plane_blocks;
3503 }
b9cec075
DL		 3504
3505 start += plane_blocks;
2cd601c6
CK		 3506
3507 /*
3508 * allocation for y_plane part of planar format:
3509 */
1e6ee542 3510 y_data_rate = plane_y_data_rate[id];
a1de91e5
MR		 3511
3512 y_plane_blocks = y_minimum[id];
3513 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3514 total_data_rate);
2cd601c6 3515
c107acfe
MR		 3516 if (y_data_rate) {
3517 ddb->y_plane[pipe][id].start = start;
3518 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3519 }
a1de91e5
MR		 3520
3521 start += y_plane_blocks;
b9cec075
DL		 3522 }
3523
c107acfe 3524 return 0;
b9cec075
DL		 3525}
3526
2d41c0b5
PB		 3527/*
3528 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3529 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3530 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3531 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3532*/
ac484963 3533static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3534{
3535 uint32_t wm_intermediate_val, ret;
3536
3537 if (latency == 0)
3538 return UINT_MAX;
3539
ac484963 3540 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3541 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3542
3543 return ret;
3544}
3545
3546static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3547 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3548{
d4c2aa60 3549 uint32_t ret;
d4c2aa60 3550 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3551
3552 if (latency == 0)
3553 return UINT_MAX;
3554
2d41c0b5
PB		 3555 wm_intermediate_val = latency * pixel_rate;
3556 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3557 plane_blocks_per_line;
2d41c0b5
PB		 3558
3559 return ret;
3560}
3561
9c2f7a9d
KM		 3562static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3563 struct intel_plane_state *pstate)
3564{
3565 uint64_t adjusted_pixel_rate;
3566 uint64_t downscale_amount;
3567 uint64_t pixel_rate;
3568
3569 /* Shouldn't reach here on disabled planes... */
936e71e3 3570 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3571 return 0;
3572
3573 /*
3574 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3575 * with additional adjustments for plane-specific scaling.
3576 */
cfd7e3a2 3577 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
9c2f7a9d
KM		 3578 downscale_amount = skl_plane_downscale_amount(pstate);
3579
3580 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3581 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3582
3583 return pixel_rate;
3584}
3585
55994c2c
MR		 3586static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3587 struct intel_crtc_state *cstate,
3588 struct intel_plane_state *intel_pstate,
3589 uint16_t ddb_allocation,
3590 int level,
3591 uint16_t *out_blocks, /* out */
3592 uint8_t *out_lines, /* out */
3593 bool *enabled /* out */)
2d41c0b5 3594{
33815fa5
MR		 3595 struct drm_plane_state *pstate = &intel_pstate->base;
3596 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3597 uint32_t latency = dev_priv->wm.skl_latency[level];
3598 uint32_t method1, method2;
3599 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3600 uint32_t res_blocks, res_lines;
3601 uint32_t selected_result;
ac484963 3602 uint8_t cpp;
a280f7dd 3603 uint32_t width = 0, height = 0;
9c2f7a9d 3604 uint32_t plane_pixel_rate;
75676ed4 3605 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3606 struct intel_atomic_state *state =
3607 to_intel_atomic_state(cstate->base.state);
3608 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3609
936e71e3 3610 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3611 *enabled = false;
3612 return 0;
3613 }
2d41c0b5 3614
ee3d532f
PZ		 3615 if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3616 latency += 15;
3617
936e71e3
VS		 3618 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3619 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3620
bd2ef25d 3621 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3622 swap(width, height);
3623
ac484963 3624 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3625 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3626
61d0a04d 3627 if (drm_rotation_90_or_270(pstate->rotation)) {
1186fa85
PZ		 3628 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3629 drm_format_plane_cpp(fb->pixel_format, 1) :
3630 drm_format_plane_cpp(fb->pixel_format, 0);
3631
3632 switch (cpp) {
3633 case 1:
3634 y_min_scanlines = 16;
3635 break;
3636 case 2:
3637 y_min_scanlines = 8;
3638 break;
1186fa85
PZ		 3639 case 4:
3640 y_min_scanlines = 4;
3641 break;
86a462bc
PZ		 3642 default:
3643 MISSING_CASE(cpp);
3644 return -EINVAL;
1186fa85
PZ		 3645 }
3646 } else {
3647 y_min_scanlines = 4;
3648 }
3649
7a1a8aed
PZ		 3650 plane_bytes_per_line = width * cpp;
3651 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3652 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3653 plane_blocks_per_line =
3654 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3655 plane_blocks_per_line /= y_min_scanlines;
3656 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3657 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3658 + 1;
3659 } else {
3660 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3661 }
3662
9c2f7a9d
KM		 3663 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3664 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3665 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3666 latency,
7a1a8aed 3667 plane_blocks_per_line);
2d41c0b5 3668
75676ed4 3669 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
ee3d532f
PZ		 3670 if (apply_memory_bw_wa)
3671 y_tile_minimum *= 2;
75676ed4 3672
024c9045
MR		 3673 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3674 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3675 selected_result = max(method2, y_tile_minimum);
3676 } else {
f1db3eaf
PZ		 3677 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3678 (plane_bytes_per_line / 512 < 1))
3679 selected_result = method2;
3680 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3681 selected_result = min(method1, method2);
3682 else
3683 selected_result = method1;
3684 }
2d41c0b5 3685
d4c2aa60
TU		 3686 res_blocks = selected_result + 1;
3687 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3688
0fda6568 3689 if (level >= 1 && level <= 7) {
024c9045 3690 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3691 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3692 res_blocks += y_tile_minimum;
1186fa85 3693 res_lines += y_min_scanlines;
75676ed4 3694 } else {
0fda6568 3695 res_blocks++;
75676ed4 3696 }
0fda6568 3697 }
e6d66171 3698
55994c2c
MR		 3699 if (res_blocks >= ddb_allocation || res_lines > 31) {
3700 *enabled = false;
6b6bada7
MR		 3701
3702 /*
3703 * If there are no valid level 0 watermarks, then we can't
3704 * support this display configuration.
3705 */
3706 if (level) {
3707 return 0;
3708 } else {
3709 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3710 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3711 to_intel_crtc(cstate->base.crtc)->pipe,
3712 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3713 res_blocks, ddb_allocation, res_lines);
3714
3715 return -EINVAL;
3716 }
55994c2c 3717 }
e6d66171
DL		 3718
3719 *out_blocks = res_blocks;
3720 *out_lines = res_lines;
55994c2c 3721 *enabled = true;
2d41c0b5 3722
55994c2c 3723 return 0;
2d41c0b5
PB		 3724}
3725
f4a96752
MR		 3726static int
3727skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3728 struct skl_ddb_allocation *ddb,
3729 struct intel_crtc_state *cstate,
a62163e9 3730 struct intel_plane *intel_plane,
f4a96752
MR		 3731 int level,
3732 struct skl_wm_level *result)
2d41c0b5 3733{
f4a96752 3734 struct drm_atomic_state *state = cstate->base.state;
024c9045 3735 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3736 struct drm_plane *plane = &intel_plane->base;
3737 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3738 uint16_t ddb_blocks;
024c9045 3739 enum pipe pipe = intel_crtc->pipe;
55994c2c 3740 int ret;
a62163e9
L		 3741 int i = skl_wm_plane_id(intel_plane);
3742
3743 if (state)
3744 intel_pstate =
3745 intel_atomic_get_existing_plane_state(state,
3746 intel_plane);
024c9045 3747
f4a96752 3748 /*
a62163e9
L		 3749 * Note: If we start supporting multiple pending atomic commits against
3750 * the same planes/CRTC's in the future, plane->state will no longer be
3751 * the correct pre-state to use for the calculations here and we'll
3752 * need to change where we get the 'unchanged' plane data from.
3753 *
3754 * For now this is fine because we only allow one queued commit against
3755 * a CRTC. Even if the plane isn't modified by this transaction and we
3756 * don't have a plane lock, we still have the CRTC's lock, so we know
3757 * that no other transactions are racing with us to update it.
f4a96752 3758 */
a62163e9
L		 3759 if (!intel_pstate)
3760 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3761
a62163e9 3762 WARN_ON(!intel_pstate->base.fb);
f4a96752 3763
a62163e9 3764 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2d41c0b5 3765
a62163e9
L		 3766 ret = skl_compute_plane_wm(dev_priv,
3767 cstate,
3768 intel_pstate,
3769 ddb_blocks,
3770 level,
3771 &result->plane_res_b,
3772 &result->plane_res_l,
3773 &result->plane_en);
3774 if (ret)
3775 return ret;
f4a96752
MR		 3776
3777 return 0;
2d41c0b5
PB		 3778}
3779
407b50f3 3780static uint32_t
024c9045 3781skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3782{
30d1b5fe
PZ		 3783 uint32_t pixel_rate;
3784
024c9045 3785 if (!cstate->base.active)
407b50f3
DL		 3786 return 0;
3787
30d1b5fe
PZ		 3788 pixel_rate = ilk_pipe_pixel_rate(cstate);
3789
3790 if (WARN_ON(pixel_rate == 0))
661abfc0 3791 return 0;
407b50f3 3792
024c9045 3793 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
30d1b5fe 3794 pixel_rate);
407b50f3
DL		 3795}
3796
024c9045 3797static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3798 struct skl_wm_level *trans_wm /* out */)
407b50f3 3799{
024c9045 3800 if (!cstate->base.active)
407b50f3 3801 return;
9414f563
DL		 3802
3803 /* Until we know more, just disable transition WMs */
a62163e9 3804 trans_wm->plane_en = false;
407b50f3
DL		 3805}
3806
55994c2c
MR		 3807static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3808 struct skl_ddb_allocation *ddb,
3809 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3810{
024c9045 3811 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3812 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3813 struct intel_plane *intel_plane;
3814 struct skl_plane_wm *wm;
5db94019 3815 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3816 int ret;
2d41c0b5 3817
a62163e9
L		 3818 /*
3819 * We'll only calculate watermarks for planes that are actually
3820 * enabled, so make sure all other planes are set as disabled.
3821 */
3822 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3823
3824 for_each_intel_plane_mask(&dev_priv->drm,
3825 intel_plane,
3826 cstate->base.plane_mask) {
3827 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3828
3829 for (level = 0; level <= max_level; level++) {
3830 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3831 intel_plane, level,
3832 &wm->wm[level]);
3833 if (ret)
3834 return ret;
3835 }
3836 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3837 }
024c9045 3838 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3839
55994c2c 3840 return 0;
2d41c0b5
PB		 3841}
3842
f0f59a00
VS		 3843static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3844 i915_reg_t reg,
16160e3d
DL		 3845 const struct skl_ddb_entry *entry)
3846{
3847 if (entry->end)
3848 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3849 else
3850 I915_WRITE(reg, 0);
3851}
3852
d8c0fafc 3853static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3854 i915_reg_t reg,
3855 const struct skl_wm_level *level)
3856{
3857 uint32_t val = 0;
3858
3859 if (level->plane_en) {
3860 val |= PLANE_WM_EN;
3861 val |= level->plane_res_b;
3862 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3863 }
3864
3865 I915_WRITE(reg, val);
3866}
3867
62e0fb88 3868void skl_write_plane_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3869 const struct skl_plane_wm *wm,
3870 const struct skl_ddb_allocation *ddb,
62e0fb88
L		 3871 int plane)
3872{
3873 struct drm_crtc *crtc = &intel_crtc->base;
3874 struct drm_device *dev = crtc->dev;
3875 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3876 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3877 enum pipe pipe = intel_crtc->pipe;
3878
3879 for (level = 0; level <= max_level; level++) {
d8c0fafc 3880 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3881 &wm->wm[level]);
62e0fb88 3882 }
d8c0fafc 3883 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3884 &wm->trans_wm);
27082493
L		 3885
3886 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
d8c0fafc 3887 &ddb->plane[pipe][plane]);
27082493 3888 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
d8c0fafc 3889 &ddb->y_plane[pipe][plane]);
62e0fb88
L		 3890}
3891
3892void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3893 const struct skl_plane_wm *wm,
3894 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3895{
3896 struct drm_crtc *crtc = &intel_crtc->base;
3897 struct drm_device *dev = crtc->dev;
3898 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3899 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3900 enum pipe pipe = intel_crtc->pipe;
3901
3902 for (level = 0; level <= max_level; level++) {
d8c0fafc 3903 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3904 &wm->wm[level]);
62e0fb88 3905 }
d8c0fafc 3906 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3907
27082493 3908 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3909 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3910}
3911
45ece230 3912bool skl_wm_level_equals(const struct skl_wm_level *l1,
3913 const struct skl_wm_level *l2)
3914{
3915 if (l1->plane_en != l2->plane_en)
3916 return false;
3917
3918 /* If both planes aren't enabled, the rest shouldn't matter */
3919 if (!l1->plane_en)
3920 return true;
3921
3922 return (l1->plane_res_l == l2->plane_res_l &&
3923 l1->plane_res_b == l2->plane_res_b);
3924}
3925
27082493
L		 3926static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3927 const struct skl_ddb_entry *b)
0e8fb7ba 3928{
27082493 3929 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3930}
3931
27082493 3932bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
ce0ba283 3933 struct intel_crtc *intel_crtc)
0e8fb7ba 3934{
ce0ba283
L		 3935 struct drm_crtc *other_crtc;
3936 struct drm_crtc_state *other_cstate;
3937 struct intel_crtc *other_intel_crtc;
3938 const struct skl_ddb_entry *ddb =
3939 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3940 int i;
0e8fb7ba 3941
ce0ba283
L		 3942 for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3943 other_intel_crtc = to_intel_crtc(other_crtc);
0e8fb7ba 3944
ce0ba283 3945 if (other_intel_crtc == intel_crtc)
0e8fb7ba
DL		 3946 continue;
3947
ce0ba283 3948 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
27082493 3949 return true;
0e8fb7ba
DL		 3950 }
3951
27082493 3952 return false;
0e8fb7ba
DL		 3953}
3954
55994c2c 3955static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
03af79e0 3956 const struct skl_pipe_wm *old_pipe_wm,
55994c2c 3957 struct skl_pipe_wm *pipe_wm, /* out */
03af79e0 3958 struct skl_ddb_allocation *ddb, /* out */
55994c2c 3959 bool *changed /* out */)
2d41c0b5 3960{
f4a96752 3961 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3962 int ret;
2d41c0b5 3963
55994c2c
MR		 3964 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3965 if (ret)
3966 return ret;
2d41c0b5 3967
03af79e0 3968 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3969 *changed = false;
3970 else
3971 *changed = true;
2d41c0b5 3972
55994c2c 3973 return 0;
2d41c0b5
PB		 3974}
3975
9b613022
MR		 3976static uint32_t
3977pipes_modified(struct drm_atomic_state *state)
3978{
3979 struct drm_crtc *crtc;
3980 struct drm_crtc_state *cstate;
3981 uint32_t i, ret = 0;
3982
3983 for_each_crtc_in_state(state, crtc, cstate, i)
3984 ret |= drm_crtc_mask(crtc);
3985
3986 return ret;
3987}
3988
bb7791bd 3989static int
7f60e200
PZ		 3990skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3991{
3992 struct drm_atomic_state *state = cstate->base.state;
3993 struct drm_device *dev = state->dev;
3994 struct drm_crtc *crtc = cstate->base.crtc;
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 struct drm_i915_private *dev_priv = to_i915(dev);
3997 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3998 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3999 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4000 struct drm_plane_state *plane_state;
4001 struct drm_plane *plane;
4002 enum pipe pipe = intel_crtc->pipe;
4003 int id;
4004
4005 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4006
220b0965 4007 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
7f60e200
PZ		 4008 id = skl_wm_plane_id(to_intel_plane(plane));
4009
4010 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
4011 &new_ddb->plane[pipe][id]) &&
4012 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
4013 &new_ddb->y_plane[pipe][id]))
4014 continue;
4015
4016 plane_state = drm_atomic_get_plane_state(state, plane);
4017 if (IS_ERR(plane_state))
4018 return PTR_ERR(plane_state);
4019 }
4020
4021 return 0;
4022}
4023
98d39494
MR		 4024static int
4025skl_compute_ddb(struct drm_atomic_state *state)
4026{
4027 struct drm_device *dev = state->dev;
4028 struct drm_i915_private *dev_priv = to_i915(dev);
4029 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4030 struct intel_crtc *intel_crtc;
734fa01f 4031 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4032 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4033 int ret;
4034
4035 /*
4036 * If this is our first atomic update following hardware readout,
4037 * we can't trust the DDB that the BIOS programmed for us. Let's
4038 * pretend that all pipes switched active status so that we'll
4039 * ensure a full DDB recompute.
4040 */
1b54a880
MR		 4041 if (dev_priv->wm.distrust_bios_wm) {
4042 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4043 state->acquire_ctx);
4044 if (ret)
4045 return ret;
4046
98d39494
MR		 4047 intel_state->active_pipe_changes = ~0;
4048
1b54a880
MR		 4049 /*
4050 * We usually only initialize intel_state->active_crtcs if we
4051 * we're doing a modeset; make sure this field is always
4052 * initialized during the sanitization process that happens
4053 * on the first commit too.
4054 */
4055 if (!intel_state->modeset)
4056 intel_state->active_crtcs = dev_priv->active_crtcs;
4057 }
4058
98d39494
MR		 4059 /*
4060 * If the modeset changes which CRTC's are active, we need to
4061 * recompute the DDB allocation for *all* active pipes, even
4062 * those that weren't otherwise being modified in any way by this
4063 * atomic commit. Due to the shrinking of the per-pipe allocations
4064 * when new active CRTC's are added, it's possible for a pipe that
4065 * we were already using and aren't changing at all here to suddenly
4066 * become invalid if its DDB needs exceeds its new allocation.
4067 *
4068 * Note that if we wind up doing a full DDB recompute, we can't let
4069 * any other display updates race with this transaction, so we need
4070 * to grab the lock on *all* CRTC's.
4071 */
734fa01f 4072 if (intel_state->active_pipe_changes) {
98d39494 4073 realloc_pipes = ~0;
734fa01f
MR		 4074 intel_state->wm_results.dirty_pipes = ~0;
4075 }
98d39494 4076
5a920b85
PZ		 4077 /*
4078 * We're not recomputing for the pipes not included in the commit, so
4079 * make sure we start with the current state.
4080 */
4081 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4082
98d39494
MR		 4083 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4084 struct intel_crtc_state *cstate;
4085
4086 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4087 if (IS_ERR(cstate))
4088 return PTR_ERR(cstate);
4089
734fa01f 4090 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4091 if (ret)
4092 return ret;
05a76d3d 4093
7f60e200 4094 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4095 if (ret)
4096 return ret;
98d39494
MR		 4097 }
4098
4099 return 0;
4100}
4101
2722efb9
MR		 4102static void
4103skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4104 struct skl_wm_values *src,
4105 enum pipe pipe)
4106{
2722efb9
MR		 4107 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4108 sizeof(dst->ddb.y_plane[pipe]));
4109 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4110 sizeof(dst->ddb.plane[pipe]));
4111}
4112
413fc530 4113static void
4114skl_print_wm_changes(const struct drm_atomic_state *state)
4115{
4116 const struct drm_device *dev = state->dev;
4117 const struct drm_i915_private *dev_priv = to_i915(dev);
4118 const struct intel_atomic_state *intel_state =
4119 to_intel_atomic_state(state);
4120 const struct drm_crtc *crtc;
4121 const struct drm_crtc_state *cstate;
413fc530 4122 const struct intel_plane *intel_plane;
413fc530 4123 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4124 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
413fc530 4125 int id;
7570498e 4126 int i;
413fc530 4127
4128 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4129 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4130 enum pipe pipe = intel_crtc->pipe;
413fc530 4131
7570498e 4132 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
413fc530 4133 const struct skl_ddb_entry *old, *new;
4134
413fc530 4135 id = skl_wm_plane_id(intel_plane);
4136 old = &old_ddb->plane[pipe][id];
4137 new = &new_ddb->plane[pipe][id];
4138
413fc530 4139 if (skl_ddb_entry_equal(old, new))
4140 continue;
4141
7570498e
ML		 4142 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4143 intel_plane->base.base.id,
4144 intel_plane->base.name,
4145 old->start, old->end,
4146 new->start, new->end);
413fc530 4147 }
4148 }
4149}
4150
98d39494
MR		 4151static int
4152skl_compute_wm(struct drm_atomic_state *state)
4153{
4154 struct drm_crtc *crtc;
4155 struct drm_crtc_state *cstate;
734fa01f
MR		 4156 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4157 struct skl_wm_values *results = &intel_state->wm_results;
4158 struct skl_pipe_wm *pipe_wm;
98d39494 4159 bool changed = false;
734fa01f 4160 int ret, i;
98d39494
MR		 4161
4162 /*
4163 * If this transaction isn't actually touching any CRTC's, don't
4164 * bother with watermark calculation. Note that if we pass this
4165 * test, we're guaranteed to hold at least one CRTC state mutex,
4166 * which means we can safely use values like dev_priv->active_crtcs
4167 * since any racing commits that want to update them would need to
4168 * hold _all_ CRTC state mutexes.
4169 */
4170 for_each_crtc_in_state(state, crtc, cstate, i)
4171 changed = true;
4172 if (!changed)
4173 return 0;
4174
734fa01f
MR		 4175 /* Clear all dirty flags */
4176 results->dirty_pipes = 0;
4177
98d39494
MR		 4178 ret = skl_compute_ddb(state);
4179 if (ret)
4180 return ret;
4181
734fa01f
MR		 4182 /*
4183 * Calculate WM's for all pipes that are part of this transaction.
4184 * Note that the DDB allocation above may have added more CRTC's that
4185 * weren't otherwise being modified (and set bits in dirty_pipes) if
4186 * pipe allocations had to change.
4187 *
4188 * FIXME: Now that we're doing this in the atomic check phase, we
4189 * should allow skl_update_pipe_wm() to return failure in cases where
4190 * no suitable watermark values can be found.
4191 */
4192 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4193 struct intel_crtc_state *intel_cstate =
4194 to_intel_crtc_state(cstate);
03af79e0
ML		 4195 const struct skl_pipe_wm *old_pipe_wm =
4196 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
734fa01f
MR		 4197
4198 pipe_wm = &intel_cstate->wm.skl.optimal;
03af79e0
ML		 4199 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4200 &results->ddb, &changed);
734fa01f
MR		 4201 if (ret)
4202 return ret;
4203
4204 if (changed)
4205 results->dirty_pipes |= drm_crtc_mask(crtc);
4206
4207 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4208 /* This pipe's WM's did not change */
4209 continue;
4210
4211 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4212 }
4213
413fc530 4214 skl_print_wm_changes(state);
4215
98d39494
MR		 4216 return 0;
4217}
4218
432081bc 4219static void skl_update_wm(struct intel_crtc *intel_crtc)
2d41c0b5 4220{
432081bc 4221 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4222 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4223 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4224 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
432081bc 4225 struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
e8f1f02e 4226 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4227 enum pipe pipe = intel_crtc->pipe;
adda50b8 4228
432081bc 4229 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
2d41c0b5
PB		 4230 return;
4231
734fa01f 4232 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4233
2722efb9 4234 /*
27082493
L		 4235 * If this pipe isn't active already, we're going to be enabling it
4236 * very soon. Since it's safe to update a pipe's ddb allocation while
4237 * the pipe's shut off, just do so here. Already active pipes will have
4238 * their watermarks updated once we update their planes.
2722efb9 4239 */
432081bc 4240 if (intel_crtc->base.state->active_changed) {
27082493
L		 4241 int plane;
4242
2c4b49a0 4243 for_each_universal_plane(dev_priv, pipe, plane)
d8c0fafc 4244 skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4245 &results->ddb, plane);
27082493 4246
d8c0fafc 4247 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4248 &results->ddb);
27082493
L		 4249 }
4250
4251 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f 4252
ce0ba283
L		 4253 intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4254
734fa01f 4255 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4256}
4257
d890565c
VS		 4258static void ilk_compute_wm_config(struct drm_device *dev,
4259 struct intel_wm_config *config)
4260{
4261 struct intel_crtc *crtc;
4262
4263 /* Compute the currently _active_ config */
4264 for_each_intel_crtc(dev, crtc) {
4265 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4266
4267 if (!wm->pipe_enabled)
4268 continue;
4269
4270 config->sprites_enabled |= wm->sprites_enabled;
4271 config->sprites_scaled |= wm->sprites_scaled;
4272 config->num_pipes_active++;
4273 }
4274}
4275
ed4a6a7c 4276static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4277{
91c8a326 4278 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4279 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4280 struct ilk_wm_maximums max;
d890565c 4281 struct intel_wm_config config = {};
820c1980 4282 struct ilk_wm_values results = {};
77c122bc 4283 enum intel_ddb_partitioning partitioning;
261a27d1 4284
d890565c
VS		 4285 ilk_compute_wm_config(dev, &config);
4286
4287 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4288 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4289
4290 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4291 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4292 config.num_pipes_active == 1 && config.sprites_enabled) {
4293 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4294 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4295
820c1980 4296 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4297 } else {
198a1e9b 4298 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4299 }
4300
198a1e9b 4301 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4302 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4303
820c1980 4304 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4305
820c1980 4306 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4307}
4308
ed4a6a7c 4309static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4310{
ed4a6a7c
MR		 4311 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4312 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4313
ed4a6a7c 4314 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4315 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4316 ilk_program_watermarks(dev_priv);
4317 mutex_unlock(&dev_priv->wm.wm_mutex);
4318}
bf220452 4319
ed4a6a7c
MR		 4320static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4321{
4322 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4323 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4324
ed4a6a7c
MR		 4325 mutex_lock(&dev_priv->wm.wm_mutex);
4326 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4327 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4328 ilk_program_watermarks(dev_priv);
4329 }
4330 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4331}
4332
d8c0fafc 4333static inline void skl_wm_level_from_reg_val(uint32_t val,
4334 struct skl_wm_level *level)
3078999f 4335{
d8c0fafc 4336 level->plane_en = val & PLANE_WM_EN;
4337 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4338 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4339 PLANE_WM_LINES_MASK;
3078999f
PB		 4340}
4341
bf9d99ad 4342void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4343 struct skl_pipe_wm *out)
3078999f
PB		 4344{
4345 struct drm_device *dev = crtc->dev;
fac5e23e 4346 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f 4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d8c0fafc 4348 struct intel_plane *intel_plane;
d8c0fafc 4349 struct skl_plane_wm *wm;
3078999f 4350 enum pipe pipe = intel_crtc->pipe;
d8c0fafc 4351 int level, id, max_level;
4352 uint32_t val;
3078999f 4353
5db94019 4354 max_level = ilk_wm_max_level(dev_priv);
3078999f 4355
d8c0fafc 4356 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4357 id = skl_wm_plane_id(intel_plane);
bf9d99ad 4358 wm = &out->planes[id];
3078999f 4359
d8c0fafc 4360 for (level = 0; level <= max_level; level++) {
4361 if (id != PLANE_CURSOR)
4362 val = I915_READ(PLANE_WM(pipe, id, level));
4363 else
4364 val = I915_READ(CUR_WM(pipe, level));
3078999f 4365
d8c0fafc 4366 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4367 }
3078999f 4368
d8c0fafc 4369 if (id != PLANE_CURSOR)
4370 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4371 else
4372 val = I915_READ(CUR_WM_TRANS(pipe));
4373
4374 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4375 }
4376
d8c0fafc 4377 if (!intel_crtc->active)
4378 return;
4e0963c7 4379
bf9d99ad 4380 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4381}
4382
4383void skl_wm_get_hw_state(struct drm_device *dev)
4384{
fac5e23e 4385 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4386 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4387 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4388 struct drm_crtc *crtc;
bf9d99ad 4389 struct intel_crtc *intel_crtc;
4390 struct intel_crtc_state *cstate;
3078999f 4391
a269c583 4392 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4393 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4394 intel_crtc = to_intel_crtc(crtc);
4395 cstate = to_intel_crtc_state(crtc->state);
4396
4397 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4398
03af79e0 4399 if (intel_crtc->active)
bf9d99ad 4400 hw->dirty_pipes |= drm_crtc_mask(crtc);
bf9d99ad 4401 }
a1de91e5 4402
279e99d7
MR		 4403 if (dev_priv->active_crtcs) {
4404 /* Fully recompute DDB on first atomic commit */
4405 dev_priv->wm.distrust_bios_wm = true;
4406 } else {
4407 /* Easy/common case; just sanitize DDB now if everything off */
4408 memset(ddb, 0, sizeof(*ddb));
4409 }
3078999f
PB		 4410}
4411
243e6a44
VS		 4412static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4413{
4414 struct drm_device *dev = crtc->dev;
fac5e23e 4415 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4416 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4418 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4419 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4420 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4421 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4422 [PIPE_A] = WM0_PIPEA_ILK,
4423 [PIPE_B] = WM0_PIPEB_ILK,
4424 [PIPE_C] = WM0_PIPEC_IVB,
4425 };
4426
4427 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4428 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4429 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4430
15606534
VS		 4431 memset(active, 0, sizeof(*active));
4432
3ef00284 4433 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4434
4435 if (active->pipe_enabled) {
243e6a44
VS		 4436 u32 tmp = hw->wm_pipe[pipe];
4437
4438 /*
4439 * For active pipes LP0 watermark is marked as
4440 * enabled, and LP1+ watermaks as disabled since
4441 * we can't really reverse compute them in case
4442 * multiple pipes are active.
4443 */
4444 active->wm[0].enable = true;
4445 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4446 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4447 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4448 active->linetime = hw->wm_linetime[pipe];
4449 } else {
5db94019 4450 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4451
4452 /*
4453 * For inactive pipes, all watermark levels
4454 * should be marked as enabled but zeroed,
4455 * which is what we'd compute them to.
4456 */
4457 for (level = 0; level <= max_level; level++)
4458 active->wm[level].enable = true;
4459 }
4e0963c7
MR		 4460
4461 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4462}
4463
6eb1a681
VS		 4464#define _FW_WM(value, plane) \
4465 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4466#define _FW_WM_VLV(value, plane) \
4467 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4468
4469static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4470 struct vlv_wm_values *wm)
4471{
4472 enum pipe pipe;
4473 uint32_t tmp;
4474
4475 for_each_pipe(dev_priv, pipe) {
4476 tmp = I915_READ(VLV_DDL(pipe));
4477
4478 wm->ddl[pipe].primary =
4479 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4480 wm->ddl[pipe].cursor =
4481 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4482 wm->ddl[pipe].sprite[0] =
4483 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4484 wm->ddl[pipe].sprite[1] =
4485 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4486 }
4487
4488 tmp = I915_READ(DSPFW1);
4489 wm->sr.plane = _FW_WM(tmp, SR);
4490 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4491 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4492 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4493
4494 tmp = I915_READ(DSPFW2);
4495 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4496 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4497 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4498
4499 tmp = I915_READ(DSPFW3);
4500 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4501
4502 if (IS_CHERRYVIEW(dev_priv)) {
4503 tmp = I915_READ(DSPFW7_CHV);
4504 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4505 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4506
4507 tmp = I915_READ(DSPFW8_CHV);
4508 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4509 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4510
4511 tmp = I915_READ(DSPFW9_CHV);
4512 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4513 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4514
4515 tmp = I915_READ(DSPHOWM);
4516 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4517 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4518 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4519 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4520 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4521 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4522 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4523 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4524 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4525 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4526 } else {
4527 tmp = I915_READ(DSPFW7);
4528 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4529 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4530
4531 tmp = I915_READ(DSPHOWM);
4532 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4533 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4534 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4535 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4536 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4537 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4538 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4539 }
4540}
4541
4542#undef _FW_WM
4543#undef _FW_WM_VLV
4544
4545void vlv_wm_get_hw_state(struct drm_device *dev)
4546{
4547 struct drm_i915_private *dev_priv = to_i915(dev);
4548 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4549 struct intel_plane *plane;
4550 enum pipe pipe;
4551 u32 val;
4552
4553 vlv_read_wm_values(dev_priv, wm);
4554
4555 for_each_intel_plane(dev, plane) {
4556 switch (plane->base.type) {
4557 int sprite;
4558 case DRM_PLANE_TYPE_CURSOR:
4559 plane->wm.fifo_size = 63;
4560 break;
4561 case DRM_PLANE_TYPE_PRIMARY:
4562 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4563 break;
4564 case DRM_PLANE_TYPE_OVERLAY:
4565 sprite = plane->plane;
4566 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4567 break;
4568 }
4569 }
4570
4571 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4572 wm->level = VLV_WM_LEVEL_PM2;
4573
4574 if (IS_CHERRYVIEW(dev_priv)) {
4575 mutex_lock(&dev_priv->rps.hw_lock);
4576
4577 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4578 if (val & DSP_MAXFIFO_PM5_ENABLE)
4579 wm->level = VLV_WM_LEVEL_PM5;
4580
58590c14
VS		 4581 /*
4582 * If DDR DVFS is disabled in the BIOS, Punit
4583 * will never ack the request. So if that happens
4584 * assume we don't have to enable/disable DDR DVFS
4585 * dynamically. To test that just set the REQ_ACK
4586 * bit to poke the Punit, but don't change the
4587 * HIGH/LOW bits so that we don't actually change
4588 * the current state.
4589 */
6eb1a681 4590 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4591 val |= FORCE_DDR_FREQ_REQ_ACK;
4592 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4593
4594 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4595 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4596 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4597 "assuming DDR DVFS is disabled\n");
4598 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4599 } else {
4600 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4601 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4602 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4603 }
6eb1a681
VS		 4604
4605 mutex_unlock(&dev_priv->rps.hw_lock);
4606 }
4607
4608 for_each_pipe(dev_priv, pipe)
4609 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4610 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4611 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4612
4613 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4614 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4615}
4616
243e6a44
VS		 4617void ilk_wm_get_hw_state(struct drm_device *dev)
4618{
fac5e23e 4619 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4620 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4621 struct drm_crtc *crtc;
4622
70e1e0ec 4623 for_each_crtc(dev, crtc)
243e6a44
VS		 4624 ilk_pipe_wm_get_hw_state(crtc);
4625
4626 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4627 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4628 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4629
4630 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4631 if (INTEL_INFO(dev)->gen >= 7) {
4632 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4633 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4634 }
243e6a44 4635
8652744b 4636 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4637 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4638 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4639 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4640 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4641 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4642
4643 hw->enable_fbc_wm =
4644 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4645}
4646
b445e3b0
ED		 4647/**
4648 * intel_update_watermarks - update FIFO watermark values based on current modes
4649 *
4650 * Calculate watermark values for the various WM regs based on current mode
4651 * and plane configuration.
4652 *
4653 * There are several cases to deal with here:
4654 * - normal (i.e. non-self-refresh)
4655 * - self-refresh (SR) mode
4656 * - lines are large relative to FIFO size (buffer can hold up to 2)
4657 * - lines are small relative to FIFO size (buffer can hold more than 2
4658 * lines), so need to account for TLB latency
4659 *
4660 * The normal calculation is:
4661 * watermark = dotclock * bytes per pixel * latency
4662 * where latency is platform & configuration dependent (we assume pessimal
4663 * values here).
4664 *
4665 * The SR calculation is:
4666 * watermark = (trunc(latency/line time)+1) * surface width *
4667 * bytes per pixel
4668 * where
4669 * line time = htotal / dotclock
4670 * surface width = hdisplay for normal plane and 64 for cursor
4671 * and latency is assumed to be high, as above.
4672 *
4673 * The final value programmed to the register should always be rounded up,
4674 * and include an extra 2 entries to account for clock crossings.
4675 *
4676 * We don't use the sprite, so we can ignore that. And on Crestline we have
4677 * to set the non-SR watermarks to 8.
4678 */
432081bc 4679void intel_update_watermarks(struct intel_crtc *crtc)
b445e3b0 4680{
432081bc 4681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0
ED		 4682
4683 if (dev_priv->display.update_wm)
46ba614c 4684 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4685}
4686
e2828914 4687/*
9270388e 4688 * Lock protecting IPS related data structures
9270388e
DV		 4689 */
4690DEFINE_SPINLOCK(mchdev_lock);
4691
4692/* Global for IPS driver to get at the current i915 device. Protected by
4693 * mchdev_lock. */
4694static struct drm_i915_private *i915_mch_dev;
4695
91d14251 4696bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4697{
2b4e57bd
ED		 4698 u16 rgvswctl;
4699
9270388e
DV		 4700 assert_spin_locked(&mchdev_lock);
4701
2b4e57bd
ED		 4702 rgvswctl = I915_READ16(MEMSWCTL);
4703 if (rgvswctl & MEMCTL_CMD_STS) {
4704 DRM_DEBUG("gpu busy, RCS change rejected\n");
4705 return false; /* still busy with another command */
4706 }
4707
4708 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4709 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4710 I915_WRITE16(MEMSWCTL, rgvswctl);
4711 POSTING_READ16(MEMSWCTL);
4712
4713 rgvswctl |= MEMCTL_CMD_STS;
4714 I915_WRITE16(MEMSWCTL, rgvswctl);
4715
4716 return true;
4717}
4718
91d14251 4719static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4720{
84f1b20f 4721 u32 rgvmodectl;
2b4e57bd
ED		 4722 u8 fmax, fmin, fstart, vstart;
4723
9270388e
DV		 4724 spin_lock_irq(&mchdev_lock);
4725
84f1b20f
TU		 4726 rgvmodectl = I915_READ(MEMMODECTL);
4727
2b4e57bd
ED		 4728 /* Enable temp reporting */
4729 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4730 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4731
4732 /* 100ms RC evaluation intervals */
4733 I915_WRITE(RCUPEI, 100000);
4734 I915_WRITE(RCDNEI, 100000);
4735
4736 /* Set max/min thresholds to 90ms and 80ms respectively */
4737 I915_WRITE(RCBMAXAVG, 90000);
4738 I915_WRITE(RCBMINAVG, 80000);
4739
4740 I915_WRITE(MEMIHYST, 1);
4741
4742 /* Set up min, max, and cur for interrupt handling */
4743 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4744 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4745 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4746 MEMMODE_FSTART_SHIFT;
4747
616847e7 4748 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4749 PXVFREQ_PX_SHIFT;
4750
20e4d407
DV		 4751 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4752 dev_priv->ips.fstart = fstart;
2b4e57bd 4753
20e4d407
DV		 4754 dev_priv->ips.max_delay = fstart;
4755 dev_priv->ips.min_delay = fmin;
4756 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4757
4758 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4759 fmax, fmin, fstart);
4760
4761 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4762
4763 /*
4764 * Interrupts will be enabled in ironlake_irq_postinstall
4765 */
4766
4767 I915_WRITE(VIDSTART, vstart);
4768 POSTING_READ(VIDSTART);
4769
4770 rgvmodectl |= MEMMODE_SWMODE_EN;
4771 I915_WRITE(MEMMODECTL, rgvmodectl);
4772
9270388e 4773 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4774 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4775 mdelay(1);
2b4e57bd 4776
91d14251 4777 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4778
7d81c3e0
VS		 4779 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4780 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4781 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4782 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4783 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4784
4785 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4786}
4787
91d14251 4788static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4789{
9270388e
DV		 4790 u16 rgvswctl;
4791
4792 spin_lock_irq(&mchdev_lock);
4793
4794 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4795
4796 /* Ack interrupts, disable EFC interrupt */
4797 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4798 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4799 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4800 I915_WRITE(DEIIR, DE_PCU_EVENT);
4801 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4802
4803 /* Go back to the starting frequency */
91d14251 4804 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4805 mdelay(1);
2b4e57bd
ED		 4806 rgvswctl |= MEMCTL_CMD_STS;
4807 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4808 mdelay(1);
2b4e57bd 4809
9270388e 4810 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4811}
4812
acbe9475
DV		 4813/* There's a funny hw issue where the hw returns all 0 when reading from
4814 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4815 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4816 * all limits and the gpu stuck at whatever frequency it is at atm).
4817 */
74ef1173 4818static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4819{
7b9e0ae6 4820 u32 limits;
2b4e57bd 4821
20b46e59
DV		 4822 /* Only set the down limit when we've reached the lowest level to avoid
4823 * getting more interrupts, otherwise leave this clear. This prevents a
4824 * race in the hw when coming out of rc6: There's a tiny window where
4825 * the hw runs at the minimal clock before selecting the desired
4826 * frequency, if the down threshold expires in that window we will not
4827 * receive a down interrupt. */
2d1fe073 4828 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4829 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4830 if (val <= dev_priv->rps.min_freq_softlimit)
4831 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4832 } else {
4833 limits = dev_priv->rps.max_freq_softlimit << 24;
4834 if (val <= dev_priv->rps.min_freq_softlimit)
4835 limits |= dev_priv->rps.min_freq_softlimit << 16;
4836 }
20b46e59
DV		 4837
4838 return limits;
4839}
4840
dd75fdc8
CW		 4841static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4842{
4843 int new_power;
8a586437
AG		 4844 u32 threshold_up = 0, threshold_down = 0; /* in % */
4845 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4846
4847 new_power = dev_priv->rps.power;
4848 switch (dev_priv->rps.power) {
4849 case LOW_POWER:
a72b5623
CW		 4850 if (val > dev_priv->rps.efficient_freq + 1 &&
4851 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4852 new_power = BETWEEN;
4853 break;
4854
4855 case BETWEEN:
a72b5623
CW		 4856 if (val <= dev_priv->rps.efficient_freq &&
4857 val < dev_priv->rps.cur_freq)
dd75fdc8 4858 new_power = LOW_POWER;
a72b5623
CW		 4859 else if (val >= dev_priv->rps.rp0_freq &&
4860 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4861 new_power = HIGH_POWER;
4862 break;
4863
4864 case HIGH_POWER:
a72b5623
CW		 4865 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4866 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4867 new_power = BETWEEN;
4868 break;
4869 }
4870 /* Max/min bins are special */
aed242ff 4871 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4872 new_power = LOW_POWER;
aed242ff 4873 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4874 new_power = HIGH_POWER;
4875 if (new_power == dev_priv->rps.power)
4876 return;
4877
4878 /* Note the units here are not exactly 1us, but 1280ns. */
4879 switch (new_power) {
4880 case LOW_POWER:
4881 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4882 ei_up = 16000;
4883 threshold_up = 95;
dd75fdc8
CW		 4884
4885 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4886 ei_down = 32000;
4887 threshold_down = 85;
dd75fdc8
CW		 4888 break;
4889
4890 case BETWEEN:
4891 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4892 ei_up = 13000;
4893 threshold_up = 90;
dd75fdc8
CW		 4894
4895 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4896 ei_down = 32000;
4897 threshold_down = 75;
dd75fdc8
CW		 4898 break;
4899
4900 case HIGH_POWER:
4901 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4902 ei_up = 10000;
4903 threshold_up = 85;
dd75fdc8
CW		 4904
4905 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4906 ei_down = 32000;
4907 threshold_down = 60;
dd75fdc8
CW		 4908 break;
4909 }
4910
8a586437 4911 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4912 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4913 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4914 GT_INTERVAL_FROM_US(dev_priv,
4915 ei_up * threshold_up / 100));
8a586437
AG		 4916
4917 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4918 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4919 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4920 GT_INTERVAL_FROM_US(dev_priv,
4921 ei_down * threshold_down / 100));
4922
4923 I915_WRITE(GEN6_RP_CONTROL,
4924 GEN6_RP_MEDIA_TURBO |
4925 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4926 GEN6_RP_MEDIA_IS_GFX |
4927 GEN6_RP_ENABLE |
4928 GEN6_RP_UP_BUSY_AVG |
4929 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4930
dd75fdc8 4931 dev_priv->rps.power = new_power;
8fb55197
CW		 4932 dev_priv->rps.up_threshold = threshold_up;
4933 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4934 dev_priv->rps.last_adj = 0;
4935}
4936
2876ce73
CW		 4937static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4938{
4939 u32 mask = 0;
4940
4941 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4942 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4943 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4944 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4945
7b3c29f6
CW		 4946 mask &= dev_priv->pm_rps_events;
4947
59d02a1f 4948 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4949}
4950
b8a5ff8d
JM		 4951/* gen6_set_rps is called to update the frequency request, but should also be
4952 * called when the range (min_delay and max_delay) is modified so that we can
4953 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4954static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4955{
23eafea6 4956 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4957 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4958 return;
4959
4fc688ce 4960 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4961 WARN_ON(val > dev_priv->rps.max_freq);
4962 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4963
eb64cad1
CW		 4964 /* min/max delay may still have been modified so be sure to
4965 * write the limits value.
4966 */
4967 if (val != dev_priv->rps.cur_freq) {
4968 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4969
dc97997a 4970 if (IS_GEN9(dev_priv))
5704195c
AG		 4971 I915_WRITE(GEN6_RPNSWREQ,
4972 GEN9_FREQUENCY(val));
dc97997a 4973 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4974 I915_WRITE(GEN6_RPNSWREQ,
4975 HSW_FREQUENCY(val));
4976 else
4977 I915_WRITE(GEN6_RPNSWREQ,
4978 GEN6_FREQUENCY(val) |
4979 GEN6_OFFSET(0) |
4980 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4981 }
7b9e0ae6 4982
7b9e0ae6
CW		 4983 /* Make sure we continue to get interrupts
4984 * until we hit the minimum or maximum frequencies.
4985 */
74ef1173 4986 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4987 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4988
d5570a72
BW		 4989 POSTING_READ(GEN6_RPNSWREQ);
4990
b39fb297 4991 dev_priv->rps.cur_freq = val;
0f94592e 4992 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4993}
4994
dc97997a 4995static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4996{
ffe02b40 4997 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4998 WARN_ON(val > dev_priv->rps.max_freq);
4999 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 5000
dc97997a 5001 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 5002 "Odd GPU freq value\n"))
5003 val &= ~1;
5004
cd25dd5b
D		 5005 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
5006
8fb55197 5007 if (val != dev_priv->rps.cur_freq) {
ffe02b40 5008 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 5009 if (!IS_CHERRYVIEW(dev_priv))
5010 gen6_set_rps_thresholds(dev_priv, val);
5011 }
ffe02b40 5012
ffe02b40
VS		 5013 dev_priv->rps.cur_freq = val;
5014 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5015}
5016
a7f6e231 5017/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5018 *
5019 * * If Gfx is Idle, then
a7f6e231
D		 5020 * 1. Forcewake Media well.
5021 * 2. Request idle freq.
5022 * 3. Release Forcewake of Media well.
76c3552f
D		 5023*/
5024static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5025{
aed242ff 5026 u32 val = dev_priv->rps.idle_freq;
5549d25f 5027
aed242ff 5028 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5029 return;
5030
a7f6e231
D		 5031 /* Wake up the media well, as that takes a lot less
5032 * power than the Render well. */
5033 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5034 valleyview_set_rps(dev_priv, val);
a7f6e231 5035 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5036}
5037
43cf3bf0
CW		 5038void gen6_rps_busy(struct drm_i915_private *dev_priv)
5039{
5040 mutex_lock(&dev_priv->rps.hw_lock);
5041 if (dev_priv->rps.enabled) {
5042 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5043 gen6_rps_reset_ei(dev_priv);
5044 I915_WRITE(GEN6_PMINTRMSK,
5045 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5046
c33d247d
CW		 5047 gen6_enable_rps_interrupts(dev_priv);
5048
2b83c4c4
MW		 5049 /* Ensure we start at the user's desired frequency */
5050 intel_set_rps(dev_priv,
5051 clamp(dev_priv->rps.cur_freq,
5052 dev_priv->rps.min_freq_softlimit,
5053 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5054 }
5055 mutex_unlock(&dev_priv->rps.hw_lock);
5056}
5057
b29c19b6
CW		 5058void gen6_rps_idle(struct drm_i915_private *dev_priv)
5059{
c33d247d
CW		 5060 /* Flush our bottom-half so that it does not race with us
5061 * setting the idle frequency and so that it is bounded by
5062 * our rpm wakeref. And then disable the interrupts to stop any
5063 * futher RPS reclocking whilst we are asleep.
5064 */
5065 gen6_disable_rps_interrupts(dev_priv);
5066
b29c19b6 5067 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5068 if (dev_priv->rps.enabled) {
dc97997a 5069 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5070 vlv_set_rps_idle(dev_priv);
7526ed79 5071 else
dc97997a 5072 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5073 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5074 I915_WRITE(GEN6_PMINTRMSK,
5075 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5076 }
8d3afd7d 5077 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5078
8d3afd7d 5079 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5080 while (!list_empty(&dev_priv->rps.clients))
5081 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5082 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5083}
5084
1854d5ca 5085void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5086 struct intel_rps_client *rps,
5087 unsigned long submitted)
b29c19b6 5088{
8d3afd7d
CW		 5089 /* This is intentionally racy! We peek at the state here, then
5090 * validate inside the RPS worker.
5091 */
67d97da3 5092 if (!(dev_priv->gt.awake &&
8d3afd7d 5093 dev_priv->rps.enabled &&
29ecd78d 5094 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5095 return;
43cf3bf0 5096
e61b9958
CW		 5097 /* Force a RPS boost (and don't count it against the client) if
5098 * the GPU is severely congested.
5099 */
d0bc54f2 5100 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5101 rps = NULL;
5102
8d3afd7d
CW		 5103 spin_lock(&dev_priv->rps.client_lock);
5104 if (rps == NULL || list_empty(&rps->link)) {
5105 spin_lock_irq(&dev_priv->irq_lock);
5106 if (dev_priv->rps.interrupts_enabled) {
5107 dev_priv->rps.client_boost = true;
c33d247d 5108 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5109 }
5110 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5111
2e1b8730
CW		 5112 if (rps != NULL) {
5113 list_add(&rps->link, &dev_priv->rps.clients);
5114 rps->boosts++;
1854d5ca
CW		 5115 } else
5116 dev_priv->rps.boosts++;
c0951f0c 5117 }
8d3afd7d 5118 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5119}
5120
dc97997a 5121void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5122{
dc97997a
CW		 5123 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5124 valleyview_set_rps(dev_priv, val);
ffe02b40 5125 else
dc97997a 5126 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5127}
5128
dc97997a 5129static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5130{
20e49366 5131 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5132 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5133}
5134
dc97997a 5135static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5136{
2030d684
AG		 5137 I915_WRITE(GEN6_RP_CONTROL, 0);
5138}
5139
dc97997a 5140static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5141{
d20d4f0c 5142 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5143 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5144 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5145}
5146
dc97997a 5147static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5148{
38807746
D		 5149 I915_WRITE(GEN6_RC_CONTROL, 0);
5150}
5151
dc97997a 5152static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5153{
98a2e5f9
D		 5154 /* we're doing forcewake before Disabling RC6,
5155 * This what the BIOS expects when going into suspend */
59bad947 5156 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5157
44fc7d5c 5158 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5159
59bad947 5160 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5161}
5162
dc97997a 5163static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5164{
dc97997a 5165 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5166 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5167 mode = GEN6_RC_CTL_RC6_ENABLE;
5168 else
5169 mode = 0;
5170 }
dc97997a 5171 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5172 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5173 "RC6 %s RC6p %s RC6pp %s\n",
5174 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5175 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5176 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5177
5178 else
b99d49cc
ID		 5179 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5180 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5181}
5182
dc97997a 5183static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5184{
72e96d64 5185 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5186 bool enable_rc6 = true;
5187 unsigned long rc6_ctx_base;
fc619841
ID		 5188 u32 rc_ctl;
5189 int rc_sw_target;
5190
5191 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5192 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5193 RC_SW_TARGET_STATE_SHIFT;
5194 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5195 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5196 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5197 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5198 rc_sw_target);
274008e8
SAK		 5199
5200 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5201 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5202 enable_rc6 = false;
5203 }
5204
5205 /*
5206 * The exact context size is not known for BXT, so assume a page size
5207 * for this check.
5208 */
5209 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5210 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5211 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5212 ggtt->stolen_reserved_size))) {
b99d49cc 5213 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5214 enable_rc6 = false;
5215 }
5216
5217 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5218 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5219 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5220 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5221 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5222 enable_rc6 = false;
5223 }
5224
fc619841
ID		 5225 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5226 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5227 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5228 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5229 enable_rc6 = false;
5230 }
5231
5232 if (!I915_READ(GEN6_GFXPAUSE)) {
5233 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5234 enable_rc6 = false;
5235 }
5236
5237 if (!I915_READ(GEN8_MISC_CTRL0)) {
5238 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5239 enable_rc6 = false;
5240 }
5241
5242 return enable_rc6;
5243}
5244
dc97997a 5245int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5246{
e7d66d89 5247 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5248 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5249 return 0;
5250
274008e8
SAK		 5251 if (!enable_rc6)
5252 return 0;
5253
dc97997a 5254 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5255 DRM_INFO("RC6 disabled by BIOS\n");
5256 return 0;
5257 }
5258
456470eb 5259 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5260 if (enable_rc6 >= 0) {
5261 int mask;
5262
dc97997a 5263 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5264 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5265 INTEL_RC6pp_ENABLE;
5266 else
5267 mask = INTEL_RC6_ENABLE;
5268
5269 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5270 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5271 "(requested %d, valid %d)\n",
5272 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5273
5274 return enable_rc6 & mask;
5275 }
2b4e57bd 5276
dc97997a 5277 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5278 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5279
5280 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5281}
5282
dc97997a 5283static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5284{
5285 /* All of these values are in units of 50MHz */
773ea9a8 5286
93ee2920 5287 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5288 if (IS_BROXTON(dev_priv)) {
773ea9a8 5289 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5290 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5291 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5292 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5293 } else {
773ea9a8 5294 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5295 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5296 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5297 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5298 }
3280e8b0 5299 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5300 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5301
93ee2920 5302 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5303 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5304 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5305 u32 ddcc_status = 0;
5306
5307 if (sandybridge_pcode_read(dev_priv,
5308 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5309 &ddcc_status) == 0)
93ee2920 5310 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5311 clamp_t(u8,
5312 ((ddcc_status >> 8) & 0xff),
5313 dev_priv->rps.min_freq,
5314 dev_priv->rps.max_freq);
93ee2920
TR		 5315 }
5316
dc97997a 5317 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5318 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5319 * the natural hardware unit for SKL
5320 */
c5e0688c
AG		 5321 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5322 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5323 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5324 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5325 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5326 }
3280e8b0
BW		 5327}
5328
3a45b05c
CW		 5329static void reset_rps(struct drm_i915_private *dev_priv,
5330 void (*set)(struct drm_i915_private *, u8))
5331{
5332 u8 freq = dev_priv->rps.cur_freq;
5333
5334 /* force a reset */
5335 dev_priv->rps.power = -1;
5336 dev_priv->rps.cur_freq = -1;
5337
5338 set(dev_priv, freq);
5339}
5340
b6fef0ef 5341/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5342static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5343{
b6fef0ef
JB		 5344 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5345
23eafea6 5346 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5347 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5348 /*
5349 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5350 * clear out the Control register just to avoid inconsitency
5351 * with debugfs interface, which will show Turbo as enabled
5352 * only and that is not expected by the User after adding the
5353 * WaGsvDisableTurbo. Apart from this there is no problem even
5354 * if the Turbo is left enabled in the Control register, as the
5355 * Up/Down interrupts would remain masked.
5356 */
dc97997a 5357 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5358 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5359 return;
5360 }
5361
0beb059a
AG		 5362 /* Program defaults and thresholds for RPS*/
5363 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5364 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5365
5366 /* 1 second timeout*/
5367 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5368 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5369
b6fef0ef 5370 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5371
0beb059a
AG		 5372 /* Leaning on the below call to gen6_set_rps to program/setup the
5373 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5374 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5375 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5376
5377 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5378}
5379
dc97997a 5380static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5381{
e2f80391 5382 struct intel_engine_cs *engine;
3b3f1650 5383 enum intel_engine_id id;
20e49366 5384 uint32_t rc6_mask = 0;
20e49366
ZW		 5385
5386 /* 1a: Software RC state - RC0 */
5387 I915_WRITE(GEN6_RC_STATE, 0);
5388
5389 /* 1b: Get forcewake during program sequence. Although the driver
5390 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5391 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5392
5393 /* 2a: Disable RC states. */
5394 I915_WRITE(GEN6_RC_CONTROL, 0);
5395
5396 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5397
5398 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5399 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5400 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5401 else
5402 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5403 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5404 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5405 for_each_engine(engine, dev_priv, id)
e2f80391 5406 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5407
1a3d1898 5408 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5409 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5410
20e49366 5411 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5412
38c23527
ZW		 5413 /* 2c: Program Coarse Power Gating Policies. */
5414 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5415 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5416
20e49366 5417 /* 3a: Enable RC6 */
dc97997a 5418 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5419 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5420 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5421 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5422 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5423 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5424 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5425 GEN7_RC_CTL_TO_MODE |
5426 rc6_mask);
3e7732a0
SAK		 5427 } else {
5428 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5429 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5430 GEN6_RC_CTL_EI_MODE(1) |
5431 rc6_mask);
3e7732a0 5432 }
20e49366 5433
cb07bae0
SK		 5434 /*
5435 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5436 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5437 */
dc97997a 5438 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5439 I915_WRITE(GEN9_PG_ENABLE, 0);
5440 else
5441 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5442 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5443
59bad947 5444 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5445}
5446
dc97997a 5447static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5448{
e2f80391 5449 struct intel_engine_cs *engine;
3b3f1650 5450 enum intel_engine_id id;
93ee2920 5451 uint32_t rc6_mask = 0;
6edee7f3
BW		 5452
5453 /* 1a: Software RC state - RC0 */
5454 I915_WRITE(GEN6_RC_STATE, 0);
5455
5456 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5457 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5458 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5459
5460 /* 2a: Disable RC states. */
5461 I915_WRITE(GEN6_RC_CONTROL, 0);
5462
6edee7f3
BW		 5463 /* 2b: Program RC6 thresholds.*/
5464 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5465 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5466 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5467 for_each_engine(engine, dev_priv, id)
e2f80391 5468 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5469 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5470 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5471 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5472 else
5473 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5474
5475 /* 3: Enable RC6 */
dc97997a 5476 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5477 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5478 intel_print_rc6_info(dev_priv, rc6_mask);
5479 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5480 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5481 GEN7_RC_CTL_TO_MODE |
5482 rc6_mask);
5483 else
5484 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5485 GEN6_RC_CTL_EI_MODE(1) |
5486 rc6_mask);
6edee7f3
BW		 5487
5488 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5489 I915_WRITE(GEN6_RPNSWREQ,
5490 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5491 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5492 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5493 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5494 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5495
5496 /* Docs recommend 900MHz, and 300 MHz respectively */
5497 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5498 dev_priv->rps.max_freq_softlimit << 24 |
5499 dev_priv->rps.min_freq_softlimit << 16);
5500
5501 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5502 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5503 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5504 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5505
5506 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5507
5508 /* 5: Enable RPS */
7526ed79
DV		 5509 I915_WRITE(GEN6_RP_CONTROL,
5510 GEN6_RP_MEDIA_TURBO |
5511 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5512 GEN6_RP_MEDIA_IS_GFX |
5513 GEN6_RP_ENABLE |
5514 GEN6_RP_UP_BUSY_AVG |
5515 GEN6_RP_DOWN_IDLE_AVG);
5516
5517 /* 6: Ring frequency + overclocking (our driver does this later */
5518
3a45b05c 5519 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5520
59bad947 5521 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5522}
5523
dc97997a 5524static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5525{
e2f80391 5526 struct intel_engine_cs *engine;
3b3f1650 5527 enum intel_engine_id id;
99ac9612 5528 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5529 u32 gtfifodbg;
2b4e57bd 5530 int rc6_mode;
b4ac5afc 5531 int ret;
2b4e57bd 5532
4fc688ce 5533 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5534
2b4e57bd
ED		 5535 /* Here begins a magic sequence of register writes to enable
5536 * auto-downclocking.
5537 *
5538 * Perhaps there might be some value in exposing these to
5539 * userspace...
5540 */
5541 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5542
5543 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5544 gtfifodbg = I915_READ(GTFIFODBG);
5545 if (gtfifodbg) {
2b4e57bd
ED		 5546 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5547 I915_WRITE(GTFIFODBG, gtfifodbg);
5548 }
5549
59bad947 5550 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5551
5552 /* disable the counters and set deterministic thresholds */
5553 I915_WRITE(GEN6_RC_CONTROL, 0);
5554
5555 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5556 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5557 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5558 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5559 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5560
3b3f1650 5561 for_each_engine(engine, dev_priv, id)
e2f80391 5562 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5563
5564 I915_WRITE(GEN6_RC_SLEEP, 0);
5565 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5566 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5567 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5568 else
5569 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5570 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5571 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5572
5a7dc92a 5573 /* Check if we are enabling RC6 */
dc97997a 5574 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5575 if (rc6_mode & INTEL_RC6_ENABLE)
5576 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5577
5a7dc92a 5578 /* We don't use those on Haswell */
dc97997a 5579 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5580 if (rc6_mode & INTEL_RC6p_ENABLE)
5581 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5582
5a7dc92a
ED		 5583 if (rc6_mode & INTEL_RC6pp_ENABLE)
5584 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5585 }
2b4e57bd 5586
dc97997a 5587 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5588
5589 I915_WRITE(GEN6_RC_CONTROL,
5590 rc6_mask |
5591 GEN6_RC_CTL_EI_MODE(1) |
5592 GEN6_RC_CTL_HW_ENABLE);
5593
dd75fdc8
CW		 5594 /* Power down if completely idle for over 50ms */
5595 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5596 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5597
3a45b05c 5598 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5599
31643d54
BW		 5600 rc6vids = 0;
5601 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5602 if (IS_GEN6(dev_priv) && ret) {
31643d54 5603 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5604 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5605 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5606 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5607 rc6vids &= 0xffff00;
5608 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5609 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5610 if (ret)
5611 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5612 }
5613
59bad947 5614 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5615}
5616
fb7404e8 5617static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5618{
5619 int min_freq = 15;
3ebecd07
CW		 5620 unsigned int gpu_freq;
5621 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5622 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5623 int scaling_factor = 180;
eda79642 5624 struct cpufreq_policy *policy;
2b4e57bd 5625
4fc688ce 5626 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5627
eda79642
BW		 5628 policy = cpufreq_cpu_get(0);
5629 if (policy) {
5630 max_ia_freq = policy->cpuinfo.max_freq;
5631 cpufreq_cpu_put(policy);
5632 } else {
5633 /*
5634 * Default to measured freq if none found, PCU will ensure we
5635 * don't go over
5636 */
2b4e57bd 5637 max_ia_freq = tsc_khz;
eda79642 5638 }
2b4e57bd
ED		 5639
5640 /* Convert from kHz to MHz */
5641 max_ia_freq /= 1000;
5642
153b4b95 5643 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5644 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5645 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5646
dc97997a 5647 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5648 /* Convert GT frequency to 50 HZ units */
5649 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5650 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5651 } else {
5652 min_gpu_freq = dev_priv->rps.min_freq;
5653 max_gpu_freq = dev_priv->rps.max_freq;
5654 }
5655
2b4e57bd
ED		 5656 /*
5657 * For each potential GPU frequency, load a ring frequency we'd like
5658 * to use for memory access. We do this by specifying the IA frequency
5659 * the PCU should use as a reference to determine the ring frequency.
5660 */
4c8c7743
AG		 5661 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5662 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5663 unsigned int ia_freq = 0, ring_freq = 0;
5664
dc97997a 5665 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5666 /*
5667 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5668 * No floor required for ring frequency on SKL.
5669 */
5670 ring_freq = gpu_freq;
dc97997a 5671 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5672 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5673 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5674 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5675 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5676 ring_freq = max(min_ring_freq, ring_freq);
5677 /* leave ia_freq as the default, chosen by cpufreq */
5678 } else {
5679 /* On older processors, there is no separate ring
5680 * clock domain, so in order to boost the bandwidth
5681 * of the ring, we need to upclock the CPU (ia_freq).
5682 *
5683 * For GPU frequencies less than 750MHz,
5684 * just use the lowest ring freq.
5685 */
5686 if (gpu_freq < min_freq)
5687 ia_freq = 800;
5688 else
5689 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5690 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5691 }
2b4e57bd 5692
42c0526c
BW		 5693 sandybridge_pcode_write(dev_priv,
5694 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5695 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5696 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5697 gpu_freq);
2b4e57bd 5698 }
2b4e57bd
ED		 5699}
5700
03af2045 5701static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5702{
5703 u32 val, rp0;
5704
5b5929cb 5705 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5706
43b67998 5707 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5708 case 8:
5709 /* (2 * 4) config */
5710 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5711 break;
5712 case 12:
5713 /* (2 * 6) config */
5714 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5715 break;
5716 case 16:
5717 /* (2 * 8) config */
5718 default:
5719 /* Setting (2 * 8) Min RP0 for any other combination */
5720 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5721 break;
095acd5f 5722 }
5b5929cb
JN		 5723
5724 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5725
2b6b3a09
D		 5726 return rp0;
5727}
5728
5729static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5730{
5731 u32 val, rpe;
5732
5733 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5734 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5735
5736 return rpe;
5737}
5738
7707df4a
D		 5739static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5740{
5741 u32 val, rp1;
5742
5b5929cb
JN		 5743 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5744 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5745
7707df4a
D		 5746 return rp1;
5747}
5748
f8f2b001
D		 5749static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5750{
5751 u32 val, rp1;
5752
5753 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5754
5755 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5756
5757 return rp1;
5758}
5759
03af2045 5760static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5761{
5762 u32 val, rp0;
5763
64936258 5764 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5765
5766 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5767 /* Clamp to max */
5768 rp0 = min_t(u32, rp0, 0xea);
5769
5770 return rp0;
5771}
5772
5773static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5774{
5775 u32 val, rpe;
5776
64936258 5777 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5778 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5779 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5780 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5781
5782 return rpe;
5783}
5784
03af2045 5785static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5786{
36146035
ID		 5787 u32 val;
5788
5789 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5790 /*
5791 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5792 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5793 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5794 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5795 * to make sure it matches what Punit accepts.
5796 */
5797 return max_t(u32, val, 0xc0);
0a073b84
JB		 5798}
5799
ae48434c
ID		 5800/* Check that the pctx buffer wasn't move under us. */
5801static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5802{
5803 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5804
5805 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5806 dev_priv->vlv_pctx->stolen->start);
5807}
5808
38807746
D		 5809
5810/* Check that the pcbr address is not empty. */
5811static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5812{
5813 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5814
5815 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5816}
5817
dc97997a 5818static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5819{
62106b4f 5820 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5821 unsigned long pctx_paddr, paddr;
38807746
D		 5822 u32 pcbr;
5823 int pctx_size = 32*1024;
5824
38807746
D		 5825 pcbr = I915_READ(VLV_PCBR);
5826 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5827 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5828 paddr = (dev_priv->mm.stolen_base +
62106b4f 5829 (ggtt->stolen_size - pctx_size));
38807746
D		 5830
5831 pctx_paddr = (paddr & (~4095));
5832 I915_WRITE(VLV_PCBR, pctx_paddr);
5833 }
ce611ef8
VS		 5834
5835 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5836}
5837
dc97997a 5838static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5839{
c9cddffc
JB		 5840 struct drm_i915_gem_object *pctx;
5841 unsigned long pctx_paddr;
5842 u32 pcbr;
5843 int pctx_size = 24*1024;
5844
5845 pcbr = I915_READ(VLV_PCBR);
5846 if (pcbr) {
5847 /* BIOS set it up already, grab the pre-alloc'd space */
5848 int pcbr_offset;
5849
5850 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5851 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5852 pcbr_offset,
190d6cd5 5853 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5854 pctx_size);
5855 goto out;
5856 }
5857
ce611ef8
VS		 5858 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5859
c9cddffc
JB		 5860 /*
5861 * From the Gunit register HAS:
5862 * The Gfx driver is expected to program this register and ensure
5863 * proper allocation within Gfx stolen memory. For example, this
5864 * register should be programmed such than the PCBR range does not
5865 * overlap with other ranges, such as the frame buffer, protected
5866 * memory, or any other relevant ranges.
5867 */
91c8a326 5868 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5869 if (!pctx) {
5870 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5871 goto out;
c9cddffc
JB		 5872 }
5873
5874 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5875 I915_WRITE(VLV_PCBR, pctx_paddr);
5876
5877out:
ce611ef8 5878 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5879 dev_priv->vlv_pctx = pctx;
5880}
5881
dc97997a 5882static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5883{
ae48434c
ID		 5884 if (WARN_ON(!dev_priv->vlv_pctx))
5885 return;
5886
f0cd5182 5887 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5888 dev_priv->vlv_pctx = NULL;
5889}
5890
c30fec65
VS		 5891static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5892{
5893 dev_priv->rps.gpll_ref_freq =
5894 vlv_get_cck_clock(dev_priv, "GPLL ref",
5895 CCK_GPLL_CLOCK_CONTROL,
5896 dev_priv->czclk_freq);
5897
5898 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5899 dev_priv->rps.gpll_ref_freq);
5900}
5901
dc97997a 5902static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5903{
2bb25c17 5904 u32 val;
4e80519e 5905
dc97997a 5906 valleyview_setup_pctx(dev_priv);
4e80519e 5907
c30fec65
VS		 5908 vlv_init_gpll_ref_freq(dev_priv);
5909
2bb25c17
VS		 5910 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5911 switch ((val >> 6) & 3) {
5912 case 0:
5913 case 1:
5914 dev_priv->mem_freq = 800;
5915 break;
5916 case 2:
5917 dev_priv->mem_freq = 1066;
5918 break;
5919 case 3:
5920 dev_priv->mem_freq = 1333;
5921 break;
5922 }
80b83b62 5923 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5924
4e80519e
ID		 5925 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5926 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5927 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5928 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5929 dev_priv->rps.max_freq);
5930
5931 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5932 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5933 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5934 dev_priv->rps.efficient_freq);
5935
f8f2b001
D		 5936 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5937 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5938 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5939 dev_priv->rps.rp1_freq);
5940
4e80519e
ID		 5941 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5942 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5943 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5944 dev_priv->rps.min_freq);
4e80519e
ID		 5945}
5946
dc97997a 5947static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5948{
2bb25c17 5949 u32 val;
2b6b3a09 5950
dc97997a 5951 cherryview_setup_pctx(dev_priv);
2b6b3a09 5952
c30fec65
VS		 5953 vlv_init_gpll_ref_freq(dev_priv);
5954
a580516d 5955 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5956 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5957 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5958
2bb25c17 5959 switch ((val >> 2) & 0x7) {
2bb25c17 5960 case 3:
2bb25c17
VS		 5961 dev_priv->mem_freq = 2000;
5962 break;
bfa7df01 5963 default:
2bb25c17
VS		 5964 dev_priv->mem_freq = 1600;
5965 break;
5966 }
80b83b62 5967 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5968
2b6b3a09
D		 5969 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5970 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5971 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5972 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5973 dev_priv->rps.max_freq);
5974
5975 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5976 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5977 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5978 dev_priv->rps.efficient_freq);
5979
7707df4a
D		 5980 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5981 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5982 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5983 dev_priv->rps.rp1_freq);
5984
5b7c91b7
D		 5985 /* PUnit validated range is only [RPe, RP0] */
5986 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5987 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5988 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5989 dev_priv->rps.min_freq);
5990
1c14762d
VS		 5991 WARN_ONCE((dev_priv->rps.max_freq |
5992 dev_priv->rps.efficient_freq |
5993 dev_priv->rps.rp1_freq |
5994 dev_priv->rps.min_freq) & 1,
5995 "Odd GPU freq values\n");
38807746
D		 5996}
5997
dc97997a 5998static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5999{
dc97997a 6000 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 6001}
6002
dc97997a 6003static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 6004{
e2f80391 6005 struct intel_engine_cs *engine;
3b3f1650 6006 enum intel_engine_id id;
2b6b3a09 6007 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 6008
6009 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6010
297b32ec
VS		 6011 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6012 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 6013 if (gtfifodbg) {
6014 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6015 gtfifodbg);
6016 I915_WRITE(GTFIFODBG, gtfifodbg);
6017 }
6018
6019 cherryview_check_pctx(dev_priv);
6020
6021 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6022 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6023 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6024
160614a2
VS		 6025 /* Disable RC states. */
6026 I915_WRITE(GEN6_RC_CONTROL, 0);
6027
38807746
D		 6028 /* 2a: Program RC6 thresholds.*/
6029 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6030 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6031 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6032
3b3f1650 6033 for_each_engine(engine, dev_priv, id)
e2f80391 6034 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6035 I915_WRITE(GEN6_RC_SLEEP, 0);
6036
f4f71c7d
D		 6037 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6038 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6039
6040 /* allows RC6 residency counter to work */
6041 I915_WRITE(VLV_COUNTER_CONTROL,
6042 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6043 VLV_MEDIA_RC6_COUNT_EN |
6044 VLV_RENDER_RC6_COUNT_EN));
6045
6046 /* For now we assume BIOS is allocating and populating the PCBR */
6047 pcbr = I915_READ(VLV_PCBR);
6048
38807746 6049 /* 3: Enable RC6 */
dc97997a
CW		 6050 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6051 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6052 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6053
6054 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6055
2b6b3a09 6056 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6057 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6058 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6059 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6060 I915_WRITE(GEN6_RP_UP_EI, 66000);
6061 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6062
6063 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6064
6065 /* 5: Enable RPS */
6066 I915_WRITE(GEN6_RP_CONTROL,
6067 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6068 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6069 GEN6_RP_ENABLE |
6070 GEN6_RP_UP_BUSY_AVG |
6071 GEN6_RP_DOWN_IDLE_AVG);
6072
3ef62342
D		 6073 /* Setting Fixed Bias */
6074 val = VLV_OVERRIDE_EN |
6075 VLV_SOC_TDP_EN |
6076 CHV_BIAS_CPU_50_SOC_50;
6077 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6078
2b6b3a09
D		 6079 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6080
8d40c3ae
VS		 6081 /* RPS code assumes GPLL is used */
6082 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6083
742f491d 6084 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6085 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6086
3a45b05c 6087 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6088
59bad947 6089 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6090}
6091
dc97997a 6092static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6093{
e2f80391 6094 struct intel_engine_cs *engine;
3b3f1650 6095 enum intel_engine_id id;
2a5913a8 6096 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6097
6098 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6099
ae48434c
ID		 6100 valleyview_check_pctx(dev_priv);
6101
297b32ec
VS		 6102 gtfifodbg = I915_READ(GTFIFODBG);
6103 if (gtfifodbg) {
f7d85c1e
JB		 6104 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6105 gtfifodbg);
0a073b84
JB		 6106 I915_WRITE(GTFIFODBG, gtfifodbg);
6107 }
6108
c8d9a590 6109 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6110 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6111
160614a2
VS		 6112 /* Disable RC states. */
6113 I915_WRITE(GEN6_RC_CONTROL, 0);
6114
cad725fe 6115 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6116 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6117 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6118 I915_WRITE(GEN6_RP_UP_EI, 66000);
6119 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6120
6121 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6122
6123 I915_WRITE(GEN6_RP_CONTROL,
6124 GEN6_RP_MEDIA_TURBO |
6125 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6126 GEN6_RP_MEDIA_IS_GFX |
6127 GEN6_RP_ENABLE |
6128 GEN6_RP_UP_BUSY_AVG |
6129 GEN6_RP_DOWN_IDLE_CONT);
6130
6131 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6132 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6133 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6134
3b3f1650 6135 for_each_engine(engine, dev_priv, id)
e2f80391 6136 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6137
2f0aa304 6138 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6139
6140 /* allows RC6 residency counter to work */
49798eb2 6141 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6142 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6143 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6144 VLV_MEDIA_RC6_COUNT_EN |
6145 VLV_RENDER_RC6_COUNT_EN));
31685c25 6146
dc97997a 6147 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6148 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6149
dc97997a 6150 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6151
a2b23fe0 6152 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6153
3ef62342
D		 6154 /* Setting Fixed Bias */
6155 val = VLV_OVERRIDE_EN |
6156 VLV_SOC_TDP_EN |
6157 VLV_BIAS_CPU_125_SOC_875;
6158 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6159
64936258 6160 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6161
8d40c3ae
VS		 6162 /* RPS code assumes GPLL is used */
6163 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6164
742f491d 6165 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6166 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6167
3a45b05c 6168 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6169
59bad947 6170 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6171}
6172
dde18883
ED		 6173static unsigned long intel_pxfreq(u32 vidfreq)
6174{
6175 unsigned long freq;
6176 int div = (vidfreq & 0x3f0000) >> 16;
6177 int post = (vidfreq & 0x3000) >> 12;
6178 int pre = (vidfreq & 0x7);
6179
6180 if (!pre)
6181 return 0;
6182
6183 freq = ((div * 133333) / ((1<<post) * pre));
6184
6185 return freq;
6186}
6187
eb48eb00
DV		 6188static const struct cparams {
6189 u16 i;
6190 u16 t;
6191 u16 m;
6192 u16 c;
6193} cparams[] = {
6194 { 1, 1333, 301, 28664 },
6195 { 1, 1066, 294, 24460 },
6196 { 1, 800, 294, 25192 },
6197 { 0, 1333, 276, 27605 },
6198 { 0, 1066, 276, 27605 },
6199 { 0, 800, 231, 23784 },
6200};
6201
f531dcb2 6202static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6203{
6204 u64 total_count, diff, ret;
6205 u32 count1, count2, count3, m = 0, c = 0;
6206 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6207 int i;
6208
02d71956
DV		 6209 assert_spin_locked(&mchdev_lock);
6210
20e4d407 6211 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6212
6213 /* Prevent division-by-zero if we are asking too fast.
6214 * Also, we don't get interesting results if we are polling
6215 * faster than once in 10ms, so just return the saved value
6216 * in such cases.
6217 */
6218 if (diff1 <= 10)
20e4d407 6219 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6220
6221 count1 = I915_READ(DMIEC);
6222 count2 = I915_READ(DDREC);
6223 count3 = I915_READ(CSIEC);
6224
6225 total_count = count1 + count2 + count3;
6226
6227 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6228 if (total_count < dev_priv->ips.last_count1) {
6229 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6230 diff += total_count;
6231 } else {
20e4d407 6232 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6233 }
6234
6235 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6236 if (cparams[i].i == dev_priv->ips.c_m &&
6237 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6238 m = cparams[i].m;
6239 c = cparams[i].c;
6240 break;
6241 }
6242 }
6243
6244 diff = div_u64(diff, diff1);
6245 ret = ((m * diff) + c);
6246 ret = div_u64(ret, 10);
6247
20e4d407
DV		 6248 dev_priv->ips.last_count1 = total_count;
6249 dev_priv->ips.last_time1 = now;
eb48eb00 6250
20e4d407 6251 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6252
6253 return ret;
6254}
6255
f531dcb2
CW		 6256unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6257{
6258 unsigned long val;
6259
dc97997a 6260 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6261 return 0;
6262
6263 spin_lock_irq(&mchdev_lock);
6264
6265 val = __i915_chipset_val(dev_priv);
6266
6267 spin_unlock_irq(&mchdev_lock);
6268
6269 return val;
6270}
6271
eb48eb00
DV		 6272unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6273{
6274 unsigned long m, x, b;
6275 u32 tsfs;
6276
6277 tsfs = I915_READ(TSFS);
6278
6279 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6280 x = I915_READ8(TR1);
6281
6282 b = tsfs & TSFS_INTR_MASK;
6283
6284 return ((m * x) / 127) - b;
6285}
6286
d972d6ee
MK		 6287static int _pxvid_to_vd(u8 pxvid)
6288{
6289 if (pxvid == 0)
6290 return 0;
6291
6292 if (pxvid >= 8 && pxvid < 31)
6293 pxvid = 31;
6294
6295 return (pxvid + 2) * 125;
6296}
6297
6298static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6299{
d972d6ee
MK		 6300 const int vd = _pxvid_to_vd(pxvid);
6301 const int vm = vd - 1125;
6302
dc97997a 6303 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6304 return vm > 0 ? vm : 0;
6305
6306 return vd;
eb48eb00
DV		 6307}
6308
02d71956 6309static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6310{
5ed0bdf2 6311 u64 now, diff, diffms;
eb48eb00
DV		 6312 u32 count;
6313
02d71956 6314 assert_spin_locked(&mchdev_lock);
eb48eb00 6315
5ed0bdf2
TG		 6316 now = ktime_get_raw_ns();
6317 diffms = now - dev_priv->ips.last_time2;
6318 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6319
6320 /* Don't divide by 0 */
eb48eb00
DV		 6321 if (!diffms)
6322 return;
6323
6324 count = I915_READ(GFXEC);
6325
20e4d407
DV		 6326 if (count < dev_priv->ips.last_count2) {
6327 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6328 diff += count;
6329 } else {
20e4d407 6330 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6331 }
6332
20e4d407
DV		 6333 dev_priv->ips.last_count2 = count;
6334 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6335
6336 /* More magic constants... */
6337 diff = diff * 1181;
6338 diff = div_u64(diff, diffms * 10);
20e4d407 6339 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6340}
6341
02d71956
DV		 6342void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6343{
dc97997a 6344 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6345 return;
6346
9270388e 6347 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6348
6349 __i915_update_gfx_val(dev_priv);
6350
9270388e 6351 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6352}
6353
f531dcb2 6354static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6355{
6356 unsigned long t, corr, state1, corr2, state2;
6357 u32 pxvid, ext_v;
6358
02d71956
DV		 6359 assert_spin_locked(&mchdev_lock);
6360
616847e7 6361 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6362 pxvid = (pxvid >> 24) & 0x7f;
6363 ext_v = pvid_to_extvid(dev_priv, pxvid);
6364
6365 state1 = ext_v;
6366
6367 t = i915_mch_val(dev_priv);
6368
6369 /* Revel in the empirically derived constants */
6370
6371 /* Correction factor in 1/100000 units */
6372 if (t > 80)
6373 corr = ((t * 2349) + 135940);
6374 else if (t >= 50)
6375 corr = ((t * 964) + 29317);
6376 else /* < 50 */
6377 corr = ((t * 301) + 1004);
6378
6379 corr = corr * ((150142 * state1) / 10000 - 78642);
6380 corr /= 100000;
20e4d407 6381 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6382
6383 state2 = (corr2 * state1) / 10000;
6384 state2 /= 100; /* convert to mW */
6385
02d71956 6386 __i915_update_gfx_val(dev_priv);
eb48eb00 6387
20e4d407 6388 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6389}
6390
f531dcb2
CW		 6391unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6392{
6393 unsigned long val;
6394
dc97997a 6395 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6396 return 0;
6397
6398 spin_lock_irq(&mchdev_lock);
6399
6400 val = __i915_gfx_val(dev_priv);
6401
6402 spin_unlock_irq(&mchdev_lock);
6403
6404 return val;
6405}
6406
eb48eb00
DV		 6407/**
6408 * i915_read_mch_val - return value for IPS use
6409 *
6410 * Calculate and return a value for the IPS driver to use when deciding whether
6411 * we have thermal and power headroom to increase CPU or GPU power budget.
6412 */
6413unsigned long i915_read_mch_val(void)
6414{
6415 struct drm_i915_private *dev_priv;
6416 unsigned long chipset_val, graphics_val, ret = 0;
6417
9270388e 6418 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6419 if (!i915_mch_dev)
6420 goto out_unlock;
6421 dev_priv = i915_mch_dev;
6422
f531dcb2
CW		 6423 chipset_val = __i915_chipset_val(dev_priv);
6424 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6425
6426 ret = chipset_val + graphics_val;
6427
6428out_unlock:
9270388e 6429 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6430
6431 return ret;
6432}
6433EXPORT_SYMBOL_GPL(i915_read_mch_val);
6434
6435/**
6436 * i915_gpu_raise - raise GPU frequency limit
6437 *
6438 * Raise the limit; IPS indicates we have thermal headroom.
6439 */
6440bool i915_gpu_raise(void)
6441{
6442 struct drm_i915_private *dev_priv;
6443 bool ret = true;
6444
9270388e 6445 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6446 if (!i915_mch_dev) {
6447 ret = false;
6448 goto out_unlock;
6449 }
6450 dev_priv = i915_mch_dev;
6451
20e4d407
DV		 6452 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6453 dev_priv->ips.max_delay--;
eb48eb00
DV		 6454
6455out_unlock:
9270388e 6456 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6457
6458 return ret;
6459}
6460EXPORT_SYMBOL_GPL(i915_gpu_raise);
6461
6462/**
6463 * i915_gpu_lower - lower GPU frequency limit
6464 *
6465 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6466 * frequency maximum.
6467 */
6468bool i915_gpu_lower(void)
6469{
6470 struct drm_i915_private *dev_priv;
6471 bool ret = true;
6472
9270388e 6473 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6474 if (!i915_mch_dev) {
6475 ret = false;
6476 goto out_unlock;
6477 }
6478 dev_priv = i915_mch_dev;
6479
20e4d407
DV		 6480 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6481 dev_priv->ips.max_delay++;
eb48eb00
DV		 6482
6483out_unlock:
9270388e 6484 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6485
6486 return ret;
6487}
6488EXPORT_SYMBOL_GPL(i915_gpu_lower);
6489
6490/**
6491 * i915_gpu_busy - indicate GPU business to IPS
6492 *
6493 * Tell the IPS driver whether or not the GPU is busy.
6494 */
6495bool i915_gpu_busy(void)
6496{
eb48eb00
DV		 6497 bool ret = false;
6498
9270388e 6499 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6500 if (i915_mch_dev)
6501 ret = i915_mch_dev->gt.awake;
9270388e 6502 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6503
6504 return ret;
6505}
6506EXPORT_SYMBOL_GPL(i915_gpu_busy);
6507
6508/**
6509 * i915_gpu_turbo_disable - disable graphics turbo
6510 *
6511 * Disable graphics turbo by resetting the max frequency and setting the
6512 * current frequency to the default.
6513 */
6514bool i915_gpu_turbo_disable(void)
6515{
6516 struct drm_i915_private *dev_priv;
6517 bool ret = true;
6518
9270388e 6519 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6520 if (!i915_mch_dev) {
6521 ret = false;
6522 goto out_unlock;
6523 }
6524 dev_priv = i915_mch_dev;
6525
20e4d407 6526 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6527
91d14251 6528 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6529 ret = false;
6530
6531out_unlock:
9270388e 6532 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6533
6534 return ret;
6535}
6536EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6537
6538/**
6539 * Tells the intel_ips driver that the i915 driver is now loaded, if
6540 * IPS got loaded first.
6541 *
6542 * This awkward dance is so that neither module has to depend on the
6543 * other in order for IPS to do the appropriate communication of
6544 * GPU turbo limits to i915.
6545 */
6546static void
6547ips_ping_for_i915_load(void)
6548{
6549 void (*link)(void);
6550
6551 link = symbol_get(ips_link_to_i915_driver);
6552 if (link) {
6553 link();
6554 symbol_put(ips_link_to_i915_driver);
6555 }
6556}
6557
6558void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6559{
02d71956
DV		 6560 /* We only register the i915 ips part with intel-ips once everything is
6561 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6562 spin_lock_irq(&mchdev_lock);
eb48eb00 6563 i915_mch_dev = dev_priv;
9270388e 6564 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6565
6566 ips_ping_for_i915_load();
6567}
6568
6569void intel_gpu_ips_teardown(void)
6570{
9270388e 6571 spin_lock_irq(&mchdev_lock);
eb48eb00 6572 i915_mch_dev = NULL;
9270388e 6573 spin_unlock_irq(&mchdev_lock);
eb48eb00 6574}
76c3552f 6575
dc97997a 6576static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6577{
dde18883
ED		 6578 u32 lcfuse;
6579 u8 pxw[16];
6580 int i;
6581
6582 /* Disable to program */
6583 I915_WRITE(ECR, 0);
6584 POSTING_READ(ECR);
6585
6586 /* Program energy weights for various events */
6587 I915_WRITE(SDEW, 0x15040d00);
6588 I915_WRITE(CSIEW0, 0x007f0000);
6589 I915_WRITE(CSIEW1, 0x1e220004);
6590 I915_WRITE(CSIEW2, 0x04000004);
6591
6592 for (i = 0; i < 5; i++)
616847e7 6593 I915_WRITE(PEW(i), 0);
dde18883 6594 for (i = 0; i < 3; i++)
616847e7 6595 I915_WRITE(DEW(i), 0);
dde18883
ED		 6596
6597 /* Program P-state weights to account for frequency power adjustment */
6598 for (i = 0; i < 16; i++) {
616847e7 6599 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6600 unsigned long freq = intel_pxfreq(pxvidfreq);
6601 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6602 PXVFREQ_PX_SHIFT;
6603 unsigned long val;
6604
6605 val = vid * vid;
6606 val *= (freq / 1000);
6607 val *= 255;
6608 val /= (127*127*900);
6609 if (val > 0xff)
6610 DRM_ERROR("bad pxval: %ld\n", val);
6611 pxw[i] = val;
6612 }
6613 /* Render standby states get 0 weight */
6614 pxw[14] = 0;
6615 pxw[15] = 0;
6616
6617 for (i = 0; i < 4; i++) {
6618 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6619 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6620 I915_WRITE(PXW(i), val);
dde18883
ED		 6621 }
6622
6623 /* Adjust magic regs to magic values (more experimental results) */
6624 I915_WRITE(OGW0, 0);
6625 I915_WRITE(OGW1, 0);
6626 I915_WRITE(EG0, 0x00007f00);
6627 I915_WRITE(EG1, 0x0000000e);
6628 I915_WRITE(EG2, 0x000e0000);
6629 I915_WRITE(EG3, 0x68000300);
6630 I915_WRITE(EG4, 0x42000000);
6631 I915_WRITE(EG5, 0x00140031);
6632 I915_WRITE(EG6, 0);
6633 I915_WRITE(EG7, 0);
6634
6635 for (i = 0; i < 8; i++)
616847e7 6636 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6637
6638 /* Enable PMON + select events */
6639 I915_WRITE(ECR, 0x80000019);
6640
6641 lcfuse = I915_READ(LCFUSE02);
6642
20e4d407 6643 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6644}
6645
dc97997a 6646void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6647{
b268c699
ID		 6648 /*
6649 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6650 * requirement.
6651 */
6652 if (!i915.enable_rc6) {
6653 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6654 intel_runtime_pm_get(dev_priv);
6655 }
e6069ca8 6656
b5163dbb 6657 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6658 mutex_lock(&dev_priv->rps.hw_lock);
6659
6660 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6661 if (IS_CHERRYVIEW(dev_priv))
6662 cherryview_init_gt_powersave(dev_priv);
6663 else if (IS_VALLEYVIEW(dev_priv))
6664 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6665 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6666 gen6_init_rps_frequencies(dev_priv);
6667
6668 /* Derive initial user preferences/limits from the hardware limits */
6669 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6670 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6671
6672 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6673 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6674
6675 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6676 dev_priv->rps.min_freq_softlimit =
6677 max_t(int,
6678 dev_priv->rps.efficient_freq,
6679 intel_freq_opcode(dev_priv, 450));
6680
99ac9612
CW		 6681 /* After setting max-softlimit, find the overclock max freq */
6682 if (IS_GEN6(dev_priv) ||
6683 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6684 u32 params = 0;
6685
6686 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6687 if (params & BIT(31)) { /* OC supported */
6688 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6689 (dev_priv->rps.max_freq & 0xff) * 50,
6690 (params & 0xff) * 50);
6691 dev_priv->rps.max_freq = params & 0xff;
6692 }
6693 }
6694
29ecd78d
CW		 6695 /* Finally allow us to boost to max by default */
6696 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6697
773ea9a8 6698 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6699 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6700
6701 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6702}
6703
dc97997a 6704void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6705{
8dac1e1f 6706 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6707 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6708
6709 if (!i915.enable_rc6)
6710 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6711}
6712
54b4f68f
CW		 6713/**
6714 * intel_suspend_gt_powersave - suspend PM work and helper threads
6715 * @dev_priv: i915 device
6716 *
6717 * We don't want to disable RC6 or other features here, we just want
6718 * to make sure any work we've queued has finished and won't bother
6719 * us while we're suspended.
6720 */
6721void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6722{
6723 if (INTEL_GEN(dev_priv) < 6)
6724 return;
6725
6726 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6727 intel_runtime_pm_put(dev_priv);
6728
6729 /* gen6_rps_idle() will be called later to disable interrupts */
6730}
6731
b7137e0c
CW		 6732void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6733{
6734 dev_priv->rps.enabled = true; /* force disabling */
6735 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6736
6737 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6738}
6739
dc97997a 6740void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6741{
b7137e0c
CW		 6742 if (!READ_ONCE(dev_priv->rps.enabled))
6743 return;
e494837a 6744
b7137e0c 6745 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6746
b7137e0c
CW		 6747 if (INTEL_GEN(dev_priv) >= 9) {
6748 gen9_disable_rc6(dev_priv);
6749 gen9_disable_rps(dev_priv);
6750 } else if (IS_CHERRYVIEW(dev_priv)) {
6751 cherryview_disable_rps(dev_priv);
6752 } else if (IS_VALLEYVIEW(dev_priv)) {
6753 valleyview_disable_rps(dev_priv);
6754 } else if (INTEL_GEN(dev_priv) >= 6) {
6755 gen6_disable_rps(dev_priv);
6756 } else if (IS_IRONLAKE_M(dev_priv)) {
6757 ironlake_disable_drps(dev_priv);
930ebb46 6758 }
b7137e0c
CW		 6759
6760 dev_priv->rps.enabled = false;
6761 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6762}
6763
b7137e0c 6764void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6765{
54b4f68f
CW		 6766 /* We shouldn't be disabling as we submit, so this should be less
6767 * racy than it appears!
6768 */
b7137e0c
CW		 6769 if (READ_ONCE(dev_priv->rps.enabled))
6770 return;
1a01ab3b 6771
b7137e0c
CW		 6772 /* Powersaving is controlled by the host when inside a VM */
6773 if (intel_vgpu_active(dev_priv))
6774 return;
0a073b84 6775
b7137e0c 6776 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6777
6778 if (IS_CHERRYVIEW(dev_priv)) {
6779 cherryview_enable_rps(dev_priv);
6780 } else if (IS_VALLEYVIEW(dev_priv)) {
6781 valleyview_enable_rps(dev_priv);
b7137e0c 6782 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6783 gen9_enable_rc6(dev_priv);
6784 gen9_enable_rps(dev_priv);
6785 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6786 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6787 } else if (IS_BROADWELL(dev_priv)) {
6788 gen8_enable_rps(dev_priv);
fb7404e8 6789 gen6_update_ring_freq(dev_priv);
b7137e0c 6790 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6791 gen6_enable_rps(dev_priv);
fb7404e8 6792 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6793 } else if (IS_IRONLAKE_M(dev_priv)) {
6794 ironlake_enable_drps(dev_priv);
6795 intel_init_emon(dev_priv);
0a073b84 6796 }
aed242ff
CW		 6797
6798 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6799 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6800
6801 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6802 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6803
54b4f68f 6804 dev_priv->rps.enabled = true;
b7137e0c
CW		 6805 mutex_unlock(&dev_priv->rps.hw_lock);
6806}
3cc134e3 6807
54b4f68f
CW		 6808static void __intel_autoenable_gt_powersave(struct work_struct *work)
6809{
6810 struct drm_i915_private *dev_priv =
6811 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6812 struct intel_engine_cs *rcs;
6813 struct drm_i915_gem_request *req;
6814
6815 if (READ_ONCE(dev_priv->rps.enabled))
6816 goto out;
6817
3b3f1650 6818 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6819 if (rcs->last_context)
6820 goto out;
6821
6822 if (!rcs->init_context)
6823 goto out;
6824
6825 mutex_lock(&dev_priv->drm.struct_mutex);
6826
6827 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6828 if (IS_ERR(req))
6829 goto unlock;
6830
6831 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6832 rcs->init_context(req);
6833
6834 /* Mark the device busy, calling intel_enable_gt_powersave() */
6835 i915_add_request_no_flush(req);
6836
6837unlock:
6838 mutex_unlock(&dev_priv->drm.struct_mutex);
6839out:
6840 intel_runtime_pm_put(dev_priv);
6841}
6842
6843void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6844{
6845 if (READ_ONCE(dev_priv->rps.enabled))
6846 return;
6847
6848 if (IS_IRONLAKE_M(dev_priv)) {
6849 ironlake_enable_drps(dev_priv);
54b4f68f 6850 intel_init_emon(dev_priv);
54b4f68f
CW		 6851 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6852 /*
6853 * PCU communication is slow and this doesn't need to be
6854 * done at any specific time, so do this out of our fast path
6855 * to make resume and init faster.
6856 *
6857 * We depend on the HW RC6 power context save/restore
6858 * mechanism when entering D3 through runtime PM suspend. So
6859 * disable RPM until RPS/RC6 is properly setup. We can only
6860 * get here via the driver load/system resume/runtime resume
6861 * paths, so the _noresume version is enough (and in case of
6862 * runtime resume it's necessary).
6863 */
6864 if (queue_delayed_work(dev_priv->wq,
6865 &dev_priv->rps.autoenable_work,
6866 round_jiffies_up_relative(HZ)))
6867 intel_runtime_pm_get_noresume(dev_priv);
6868 }
6869}
6870
3107bd48
DV		 6871static void ibx_init_clock_gating(struct drm_device *dev)
6872{
fac5e23e 6873 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6874
6875 /*
6876 * On Ibex Peak and Cougar Point, we need to disable clock
6877 * gating for the panel power sequencer or it will fail to
6878 * start up when no ports are active.
6879 */
6880 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6881}
6882
0e088b8f
VS		 6883static void g4x_disable_trickle_feed(struct drm_device *dev)
6884{
fac5e23e 6885 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6886 enum pipe pipe;
0e088b8f 6887
055e393f 6888 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6889 I915_WRITE(DSPCNTR(pipe),
6890 I915_READ(DSPCNTR(pipe)) |
6891 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6892
6893 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6894 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6895 }
6896}
6897
017636cc
VS		 6898static void ilk_init_lp_watermarks(struct drm_device *dev)
6899{
fac5e23e 6900 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6901
6902 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6903 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6904 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6905
6906 /*
6907 * Don't touch WM1S_LP_EN here.
6908 * Doing so could cause underruns.
6909 */
6910}
6911
1fa61106 6912static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6913{
fac5e23e 6914 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6915 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6916
f1e8fa56
DL		 6917 /*
6918 * Required for FBC
6919 * WaFbcDisableDpfcClockGating:ilk
6920 */
4d47e4f5
DL		 6921 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6922 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6923 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6924
6925 I915_WRITE(PCH_3DCGDIS0,
6926 MARIUNIT_CLOCK_GATE_DISABLE |
6927 SVSMUNIT_CLOCK_GATE_DISABLE);
6928 I915_WRITE(PCH_3DCGDIS1,
6929 VFMUNIT_CLOCK_GATE_DISABLE);
6930
6f1d69b0
ED		 6931 /*
6932 * According to the spec the following bits should be set in
6933 * order to enable memory self-refresh
6934 * The bit 22/21 of 0x42004
6935 * The bit 5 of 0x42020
6936 * The bit 15 of 0x45000
6937 */
6938 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6939 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6940 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6941 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6942 I915_WRITE(DISP_ARB_CTL,
6943 (I915_READ(DISP_ARB_CTL) |
6944 DISP_FBC_WM_DIS));
017636cc
VS		 6945
6946 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6947
6948 /*
6949 * Based on the document from hardware guys the following bits
6950 * should be set unconditionally in order to enable FBC.
6951 * The bit 22 of 0x42000
6952 * The bit 22 of 0x42004
6953 * The bit 7,8,9 of 0x42020.
6954 */
50a0bc90 6955 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6956 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6957 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6958 I915_READ(ILK_DISPLAY_CHICKEN1) |
6959 ILK_FBCQ_DIS);
6960 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6961 I915_READ(ILK_DISPLAY_CHICKEN2) |
6962 ILK_DPARB_GATE);
6f1d69b0
ED		 6963 }
6964
4d47e4f5
DL		 6965 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6966
6f1d69b0
ED		 6967 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6968 I915_READ(ILK_DISPLAY_CHICKEN2) |
6969 ILK_ELPIN_409_SELECT);
6970 I915_WRITE(_3D_CHICKEN2,
6971 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6972 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6973
ecdb4eb7 6974 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6975 I915_WRITE(CACHE_MODE_0,
6976 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6977
4e04632e
AG		 6978 /* WaDisable_RenderCache_OperationalFlush:ilk */
6979 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6980
0e088b8f 6981 g4x_disable_trickle_feed(dev);
bdad2b2f 6982
3107bd48
DV		 6983 ibx_init_clock_gating(dev);
6984}
6985
6986static void cpt_init_clock_gating(struct drm_device *dev)
6987{
fac5e23e 6988 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6989 int pipe;
3f704fa2 6990 uint32_t val;
3107bd48
DV		 6991
6992 /*
6993 * On Ibex Peak and Cougar Point, we need to disable clock
6994 * gating for the panel power sequencer or it will fail to
6995 * start up when no ports are active.
6996 */
cd664078
JB		 6997 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6998 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6999 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 7000 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7001 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 7002 /* The below fixes the weird display corruption, a few pixels shifted
7003 * downward, on (only) LVDS of some HP laptops with IVY.
7004 */
055e393f 7005 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 7006 val = I915_READ(TRANS_CHICKEN2(pipe));
7007 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7008 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 7009 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 7010 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 7011 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7012 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7013 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 7014 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7015 }
3107bd48 7016 /* WADP0ClockGatingDisable */
055e393f 7017 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7018 I915_WRITE(TRANS_CHICKEN1(pipe),
7019 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7020 }
6f1d69b0
ED		 7021}
7022
1d7aaa0c
DV		 7023static void gen6_check_mch_setup(struct drm_device *dev)
7024{
fac5e23e 7025 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7026 uint32_t tmp;
7027
7028 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7029 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7030 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7031 tmp);
1d7aaa0c
DV		 7032}
7033
1fa61106 7034static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7035{
fac5e23e 7036 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7037 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7038
231e54f6 7039 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7040
7041 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7042 I915_READ(ILK_DISPLAY_CHICKEN2) |
7043 ILK_ELPIN_409_SELECT);
7044
ecdb4eb7 7045 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7046 I915_WRITE(_3D_CHICKEN,
7047 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7048
4e04632e
AG		 7049 /* WaDisable_RenderCache_OperationalFlush:snb */
7050 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7051
8d85d272
VS		 7052 /*
7053 * BSpec recoomends 8x4 when MSAA is used,
7054 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7055 *
7056 * Note that PS/WM thread counts depend on the WIZ hashing
7057 * disable bit, which we don't touch here, but it's good
7058 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7059 */
7060 I915_WRITE(GEN6_GT_MODE,
98533251 7061 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7062
017636cc 7063 ilk_init_lp_watermarks(dev);
6f1d69b0 7064
6f1d69b0 7065 I915_WRITE(CACHE_MODE_0,
50743298 7066 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7067
7068 I915_WRITE(GEN6_UCGCTL1,
7069 I915_READ(GEN6_UCGCTL1) |
7070 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7071 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7072
7073 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7074 * gating disable must be set. Failure to set it results in
7075 * flickering pixels due to Z write ordering failures after
7076 * some amount of runtime in the Mesa "fire" demo, and Unigine
7077 * Sanctuary and Tropics, and apparently anything else with
7078 * alpha test or pixel discard.
7079 *
7080 * According to the spec, bit 11 (RCCUNIT) must also be set,
7081 * but we didn't debug actual testcases to find it out.
0f846f81 7082 *
ef59318c
VS		 7083 * WaDisableRCCUnitClockGating:snb
7084 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7085 */
7086 I915_WRITE(GEN6_UCGCTL2,
7087 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7088 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7089
5eb146dd 7090 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7091 I915_WRITE(_3D_CHICKEN3,
7092 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7093
e927ecde
VS		 7094 /*
7095 * Bspec says:
7096 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7097 * 3DSTATE_SF number of SF output attributes is more than 16."
7098 */
7099 I915_WRITE(_3D_CHICKEN3,
7100 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7101
6f1d69b0
ED		 7102 /*
7103 * According to the spec the following bits should be
7104 * set in order to enable memory self-refresh and fbc:
7105 * The bit21 and bit22 of 0x42000
7106 * The bit21 and bit22 of 0x42004
7107 * The bit5 and bit7 of 0x42020
7108 * The bit14 of 0x70180
7109 * The bit14 of 0x71180
4bb35334
DL		 7110 *
7111 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7112 */
7113 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7114 I915_READ(ILK_DISPLAY_CHICKEN1) |
7115 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7116 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7117 I915_READ(ILK_DISPLAY_CHICKEN2) |
7118 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7119 I915_WRITE(ILK_DSPCLK_GATE_D,
7120 I915_READ(ILK_DSPCLK_GATE_D) |
7121 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7122 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7123
0e088b8f 7124 g4x_disable_trickle_feed(dev);
f8f2ac9a 7125
3107bd48 7126 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7127
7128 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7129}
7130
7131static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7132{
7133 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7134
3aad9059 7135 /*
46680e0a 7136 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7137 *
7138 * This actually overrides the dispatch
7139 * mode for all thread types.
7140 */
6f1d69b0
ED		 7141 reg &= ~GEN7_FF_SCHED_MASK;
7142 reg |= GEN7_FF_TS_SCHED_HW;
7143 reg |= GEN7_FF_VS_SCHED_HW;
7144 reg |= GEN7_FF_DS_SCHED_HW;
7145
7146 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7147}
7148
17a303ec
PZ		 7149static void lpt_init_clock_gating(struct drm_device *dev)
7150{
fac5e23e 7151 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7152
7153 /*
7154 * TODO: this bit should only be enabled when really needed, then
7155 * disabled when not needed anymore in order to save power.
7156 */
4f8036a2 7157 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7158 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7159 I915_READ(SOUTH_DSPCLK_GATE_D) |
7160 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7161
7162 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7163 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7164 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7165 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7166}
7167
7d708ee4
ID		 7168static void lpt_suspend_hw(struct drm_device *dev)
7169{
fac5e23e 7170 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7171
4f8036a2 7172 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7173 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7174
7175 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7176 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7177 }
7178}
7179
450174fe
ID		 7180static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7181 int general_prio_credits,
7182 int high_prio_credits)
7183{
7184 u32 misccpctl;
7185
7186 /* WaTempDisableDOPClkGating:bdw */
7187 misccpctl = I915_READ(GEN7_MISCCPCTL);
7188 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7189
7190 I915_WRITE(GEN8_L3SQCREG1,
7191 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7192 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7193
7194 /*
7195 * Wait at least 100 clocks before re-enabling clock gating.
7196 * See the definition of L3SQCREG1 in BSpec.
7197 */
7198 POSTING_READ(GEN8_L3SQCREG1);
7199 udelay(1);
7200 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7201}
7202
9498dba7
MK		 7203static void kabylake_init_clock_gating(struct drm_device *dev)
7204{
9146f308 7205 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7206
b033bb6d 7207 gen9_init_clock_gating(dev);
9498dba7
MK		 7208
7209 /* WaDisableSDEUnitClockGating:kbl */
7210 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7211 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7212 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7213
7214 /* WaDisableGamClockGating:kbl */
7215 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7216 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7217 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7218
7219 /* WaFbcNukeOnHostModify:kbl */
7220 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7221 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7222}
7223
dc00b6a0
DV		 7224static void skylake_init_clock_gating(struct drm_device *dev)
7225{
c584e2d3 7226 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7227
b033bb6d 7228 gen9_init_clock_gating(dev);
44fff99f
MK		 7229
7230 /* WAC6entrylatency:skl */
7231 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7232 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7233
7234 /* WaFbcNukeOnHostModify:skl */
7235 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7236 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7237}
7238
47c2bd97 7239static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7240{
fac5e23e 7241 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7242 enum pipe pipe;
1020a5c2 7243
7ad0dbab 7244 ilk_init_lp_watermarks(dev);
50ed5fbd 7245
ab57fff1 7246 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7247 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7248
ab57fff1 7249 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7250 I915_WRITE(CHICKEN_PAR1_1,
7251 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7252
ab57fff1 7253 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7254 for_each_pipe(dev_priv, pipe) {
07d27e20 7255 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7256 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7257 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7258 }
63801f21 7259
ab57fff1
BW		 7260 /* WaVSRefCountFullforceMissDisable:bdw */
7261 /* WaDSRefCountFullforceMissDisable:bdw */
7262 I915_WRITE(GEN7_FF_THREAD_MODE,
7263 I915_READ(GEN7_FF_THREAD_MODE) &
7264 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7265
295e8bb7
VS		 7266 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7267 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7268
7269 /* WaDisableSDEUnitClockGating:bdw */
7270 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7271 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7272
450174fe
ID		 7273 /* WaProgramL3SqcReg1Default:bdw */
7274 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7275
6d50b065
VS		 7276 /*
7277 * WaGttCachingOffByDefault:bdw
7278 * GTT cache may not work with big pages, so if those
7279 * are ever enabled GTT cache may need to be disabled.
7280 */
7281 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7282
17e0adf0
MK		 7283 /* WaKVMNotificationOnConfigChange:bdw */
7284 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7285 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7286
89d6b2b8 7287 lpt_init_clock_gating(dev);
1020a5c2
BW		 7288}
7289
cad2a2d7
ED		 7290static void haswell_init_clock_gating(struct drm_device *dev)
7291{
fac5e23e 7292 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7293
017636cc 7294 ilk_init_lp_watermarks(dev);
cad2a2d7 7295
f3fc4884
FJ		 7296 /* L3 caching of data atomics doesn't work -- disable it. */
7297 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7298 I915_WRITE(HSW_ROW_CHICKEN3,
7299 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7300
ecdb4eb7 7301 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7302 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7303 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7304 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7305
e36ea7ff
VS		 7306 /* WaVSRefCountFullforceMissDisable:hsw */
7307 I915_WRITE(GEN7_FF_THREAD_MODE,
7308 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7309
4e04632e
AG		 7310 /* WaDisable_RenderCache_OperationalFlush:hsw */
7311 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7312
fe27c606
CW		 7313 /* enable HiZ Raw Stall Optimization */
7314 I915_WRITE(CACHE_MODE_0_GEN7,
7315 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7316
ecdb4eb7 7317 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7318 I915_WRITE(CACHE_MODE_1,
7319 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7320
a12c4967
VS		 7321 /*
7322 * BSpec recommends 8x4 when MSAA is used,
7323 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7324 *
7325 * Note that PS/WM thread counts depend on the WIZ hashing
7326 * disable bit, which we don't touch here, but it's good
7327 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7328 */
7329 I915_WRITE(GEN7_GT_MODE,
98533251 7330 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7331
94411593
KG		 7332 /* WaSampleCChickenBitEnable:hsw */
7333 I915_WRITE(HALF_SLICE_CHICKEN3,
7334 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7335
ecdb4eb7 7336 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7337 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7338
90a88643
PZ		 7339 /* WaRsPkgCStateDisplayPMReq:hsw */
7340 I915_WRITE(CHICKEN_PAR1_1,
7341 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7342
17a303ec 7343 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7344}
7345
1fa61106 7346static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7347{
fac5e23e 7348 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7349 uint32_t snpcr;
6f1d69b0 7350
017636cc 7351 ilk_init_lp_watermarks(dev);
6f1d69b0 7352
231e54f6 7353 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7354
ecdb4eb7 7355 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7356 I915_WRITE(_3D_CHICKEN3,
7357 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7358
ecdb4eb7 7359 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7360 I915_WRITE(IVB_CHICKEN3,
7361 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7362 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7363
ecdb4eb7 7364 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7365 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7366 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7367 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7368
4e04632e
AG		 7369 /* WaDisable_RenderCache_OperationalFlush:ivb */
7370 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7371
ecdb4eb7 7372 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7373 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7374 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7375
ecdb4eb7 7376 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7377 I915_WRITE(GEN7_L3CNTLREG1,
7378 GEN7_WA_FOR_GEN7_L3_CONTROL);
7379 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7380 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7381 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7382 I915_WRITE(GEN7_ROW_CHICKEN2,
7383 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7384 else {
7385 /* must write both registers */
7386 I915_WRITE(GEN7_ROW_CHICKEN2,
7387 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7388 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7389 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7390 }
6f1d69b0 7391
ecdb4eb7 7392 /* WaForceL3Serialization:ivb */
61939d97
JB		 7393 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7394 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7395
1b80a19a 7396 /*
0f846f81 7397 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7398 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7399 */
7400 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7401 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7402
ecdb4eb7 7403 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7404 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7405 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7406 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7407
0e088b8f 7408 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7409
7410 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7411
22721343
CW		 7412 if (0) { /* causes HiZ corruption on ivb:gt1 */
7413 /* enable HiZ Raw Stall Optimization */
7414 I915_WRITE(CACHE_MODE_0_GEN7,
7415 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7416 }
116f2b6d 7417
ecdb4eb7 7418 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7419 I915_WRITE(CACHE_MODE_1,
7420 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7421
a607c1a4
VS		 7422 /*
7423 * BSpec recommends 8x4 when MSAA is used,
7424 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7425 *
7426 * Note that PS/WM thread counts depend on the WIZ hashing
7427 * disable bit, which we don't touch here, but it's good
7428 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7429 */
7430 I915_WRITE(GEN7_GT_MODE,
98533251 7431 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7432
20848223
BW		 7433 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7434 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7435 snpcr |= GEN6_MBC_SNPCR_MED;
7436 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7437
6e266956 7438 if (!HAS_PCH_NOP(dev_priv))
ab5c608b 7439 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7440
7441 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7442}
7443
1fa61106 7444static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7445{
fac5e23e 7446 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7447
ecdb4eb7 7448 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7449 I915_WRITE(_3D_CHICKEN3,
7450 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7451
ecdb4eb7 7452 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7453 I915_WRITE(IVB_CHICKEN3,
7454 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7455 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7456
fad7d36e 7457 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7458 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7459 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7460 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7461 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7462
4e04632e
AG		 7463 /* WaDisable_RenderCache_OperationalFlush:vlv */
7464 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7465
ecdb4eb7 7466 /* WaForceL3Serialization:vlv */
61939d97
JB		 7467 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7468 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7469
ecdb4eb7 7470 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7471 I915_WRITE(GEN7_ROW_CHICKEN2,
7472 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7473
ecdb4eb7 7474 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7475 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7476 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7477 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7478
46680e0a
VS		 7479 gen7_setup_fixed_func_scheduler(dev_priv);
7480
3c0edaeb 7481 /*
0f846f81 7482 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7483 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7484 */
7485 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7486 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7487
c98f5062
AG		 7488 /* WaDisableL3Bank2xClockGate:vlv
7489 * Disabling L3 clock gating- MMIO 940c[25] = 1
7490 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7491 I915_WRITE(GEN7_UCGCTL4,
7492 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7493
afd58e79
VS		 7494 /*
7495 * BSpec says this must be set, even though
7496 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7497 */
6b26c86d
DV		 7498 I915_WRITE(CACHE_MODE_1,
7499 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7500
da2518f9
VS		 7501 /*
7502 * BSpec recommends 8x4 when MSAA is used,
7503 * however in practice 16x4 seems fastest.
7504 *
7505 * Note that PS/WM thread counts depend on the WIZ hashing
7506 * disable bit, which we don't touch here, but it's good
7507 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7508 */
7509 I915_WRITE(GEN7_GT_MODE,
7510 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7511
031994ee
VS		 7512 /*
7513 * WaIncreaseL3CreditsForVLVB0:vlv
7514 * This is the hardware default actually.
7515 */
7516 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7517
2d809570 7518 /*
ecdb4eb7 7519 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7520 * Disable clock gating on th GCFG unit to prevent a delay
7521 * in the reporting of vblank events.
7522 */
7a0d1eed 7523 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7524}
7525
a4565da8
VS		 7526static void cherryview_init_clock_gating(struct drm_device *dev)
7527{
fac5e23e 7528 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7529
232ce337
VS		 7530 /* WaVSRefCountFullforceMissDisable:chv */
7531 /* WaDSRefCountFullforceMissDisable:chv */
7532 I915_WRITE(GEN7_FF_THREAD_MODE,
7533 I915_READ(GEN7_FF_THREAD_MODE) &
7534 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7535
7536 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7537 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7538 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7539
7540 /* WaDisableCSUnitClockGating:chv */
7541 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7542 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7543
7544 /* WaDisableSDEUnitClockGating:chv */
7545 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7546 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7547
450174fe
ID		 7548 /*
7549 * WaProgramL3SqcReg1Default:chv
7550 * See gfxspecs/Related Documents/Performance Guide/
7551 * LSQC Setting Recommendations.
7552 */
7553 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7554
6d50b065
VS		 7555 /*
7556 * GTT cache may not work with big pages, so if those
7557 * are ever enabled GTT cache may need to be disabled.
7558 */
7559 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7560}
7561
1fa61106 7562static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7563{
fac5e23e 7564 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7565 uint32_t dspclk_gate;
7566
7567 I915_WRITE(RENCLK_GATE_D1, 0);
7568 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7569 GS_UNIT_CLOCK_GATE_DISABLE |
7570 CL_UNIT_CLOCK_GATE_DISABLE);
7571 I915_WRITE(RAMCLK_GATE_D, 0);
7572 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7573 OVRUNIT_CLOCK_GATE_DISABLE |
7574 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7575 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7576 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7577 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7578
7579 /* WaDisableRenderCachePipelinedFlush */
7580 I915_WRITE(CACHE_MODE_0,
7581 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7582
4e04632e
AG		 7583 /* WaDisable_RenderCache_OperationalFlush:g4x */
7584 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7585
0e088b8f 7586 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7587}
7588
1fa61106 7589static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7590{
fac5e23e 7591 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7592
7593 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7594 I915_WRITE(RENCLK_GATE_D2, 0);
7595 I915_WRITE(DSPCLK_GATE_D, 0);
7596 I915_WRITE(RAMCLK_GATE_D, 0);
7597 I915_WRITE16(DEUC, 0);
20f94967
VS		 7598 I915_WRITE(MI_ARB_STATE,
7599 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7600
7601 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7602 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7603}
7604
1fa61106 7605static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7606{
fac5e23e 7607 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7608
7609 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7610 I965_RCC_CLOCK_GATE_DISABLE |
7611 I965_RCPB_CLOCK_GATE_DISABLE |
7612 I965_ISC_CLOCK_GATE_DISABLE |
7613 I965_FBC_CLOCK_GATE_DISABLE);
7614 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7615 I915_WRITE(MI_ARB_STATE,
7616 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7617
7618 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7619 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7620}
7621
1fa61106 7622static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7623{
fac5e23e 7624 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7625 u32 dstate = I915_READ(D_STATE);
7626
7627 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7628 DSTATE_DOT_CLOCK_GATING;
7629 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7630
7631 if (IS_PINEVIEW(dev))
7632 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7633
7634 /* IIR "flip pending" means done if this bit is set */
7635 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7636
7637 /* interrupts should cause a wake up from C3 */
3299254f 7638 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7639
7640 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7641 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7642
7643 I915_WRITE(MI_ARB_STATE,
7644 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7645}
7646
1fa61106 7647static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7648{
fac5e23e 7649 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7650
7651 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7652
7653 /* interrupts should cause a wake up from C3 */
7654 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7655 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7656
7657 I915_WRITE(MEM_MODE,
7658 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7659}
7660
1fa61106 7661static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7662{
fac5e23e 7663 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7664
7665 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7666
7667 I915_WRITE(MEM_MODE,
7668 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7669 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7670}
7671
6f1d69b0
ED		 7672void intel_init_clock_gating(struct drm_device *dev)
7673{
fac5e23e 7674 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7675
bb400da9 7676 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7677}
7678
7d708ee4
ID		 7679void intel_suspend_hw(struct drm_device *dev)
7680{
6e266956 7681 if (HAS_PCH_LPT(to_i915(dev)))
7d708ee4
ID		 7682 lpt_suspend_hw(dev);
7683}
7684
bb400da9
ID		 7685static void nop_init_clock_gating(struct drm_device *dev)
7686{
7687 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7688}
7689
7690/**
7691 * intel_init_clock_gating_hooks - setup the clock gating hooks
7692 * @dev_priv: device private
7693 *
7694 * Setup the hooks that configure which clocks of a given platform can be
7695 * gated and also apply various GT and display specific workarounds for these
7696 * platforms. Note that some GT specific workarounds are applied separately
7697 * when GPU contexts or batchbuffers start their execution.
7698 */
7699void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7700{
7701 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7702 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7703 else if (IS_KABYLAKE(dev_priv))
9498dba7 7704 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7705 else if (IS_BROXTON(dev_priv))
7706 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7707 else if (IS_BROADWELL(dev_priv))
7708 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7709 else if (IS_CHERRYVIEW(dev_priv))
7710 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7711 else if (IS_HASWELL(dev_priv))
7712 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7713 else if (IS_IVYBRIDGE(dev_priv))
7714 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7715 else if (IS_VALLEYVIEW(dev_priv))
7716 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7717 else if (IS_GEN6(dev_priv))
7718 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7719 else if (IS_GEN5(dev_priv))
7720 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7721 else if (IS_G4X(dev_priv))
7722 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7723 else if (IS_CRESTLINE(dev_priv))
7724 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7725 else if (IS_BROADWATER(dev_priv))
7726 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7727 else if (IS_GEN3(dev_priv))
7728 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7729 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7730 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7731 else if (IS_GEN2(dev_priv))
7732 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7733 else {
7734 MISSING_CASE(INTEL_DEVID(dev_priv));
7735 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7736 }
7737}
7738
1fa61106
ED		 7739/* Set up chip specific power management-related functions */
7740void intel_init_pm(struct drm_device *dev)
7741{
fac5e23e 7742 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7743
7ff0ebcc 7744 intel_fbc_init(dev_priv);
1fa61106 7745
c921aba8
DV		 7746 /* For cxsr */
7747 if (IS_PINEVIEW(dev))
7748 i915_pineview_get_mem_freq(dev);
5db94019 7749 else if (IS_GEN5(dev_priv))
c921aba8
DV		 7750 i915_ironlake_get_mem_freq(dev);
7751
1fa61106 7752 /* For FIFO watermark updates */
f5ed50cb 7753 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7754 skl_setup_wm_latency(dev);
2d41c0b5 7755 dev_priv->display.update_wm = skl_update_wm;
98d39494 7756 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7757 } else if (HAS_PCH_SPLIT(dev_priv)) {
fa50ad61 7758 ilk_setup_wm_latency(dev);
53615a5e 7759
5db94019 7760 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7761 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7762 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7763 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7764 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7765 dev_priv->display.compute_intermediate_wm =
7766 ilk_compute_intermediate_wm;
7767 dev_priv->display.initial_watermarks =
7768 ilk_initial_watermarks;
7769 dev_priv->display.optimize_watermarks =
7770 ilk_optimize_watermarks;
bd602544
VS		 7771 } else {
7772 DRM_DEBUG_KMS("Failed to read display plane latency. "
7773 "Disable CxSR\n");
7774 }
920a14b2 7775 } else if (IS_CHERRYVIEW(dev_priv)) {
262cd2e1 7776 vlv_setup_wm_latency(dev);
262cd2e1 7777 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7778 } else if (IS_VALLEYVIEW(dev_priv)) {
26e1fe4f 7779 vlv_setup_wm_latency(dev);
26e1fe4f 7780 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7781 } else if (IS_PINEVIEW(dev)) {
50a0bc90 7782 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7783 dev_priv->is_ddr3,
7784 dev_priv->fsb_freq,
7785 dev_priv->mem_freq)) {
7786 DRM_INFO("failed to find known CxSR latency "
7787 "(found ddr%s fsb freq %d, mem freq %d), "
7788 "disabling CxSR\n",
7789 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7790 dev_priv->fsb_freq, dev_priv->mem_freq);
7791 /* Disable CxSR and never update its watermark again */
5209b1f4 7792 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7793 dev_priv->display.update_wm = NULL;
7794 } else
7795 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7796 } else if (IS_G4X(dev_priv)) {
1fa61106 7797 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7798 } else if (IS_GEN4(dev_priv)) {
1fa61106 7799 dev_priv->display.update_wm = i965_update_wm;
5db94019 7800 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7801 dev_priv->display.update_wm = i9xx_update_wm;
7802 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7803 } else if (IS_GEN2(dev_priv)) {
feb56b93
DV		 7804 if (INTEL_INFO(dev)->num_pipes == 1) {
7805 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7806 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7807 } else {
7808 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7809 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7810 }
feb56b93
DV		 7811 } else {
7812 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7813 }
7814}
7815
87660502
L		 7816static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7817{
7818 uint32_t flags =
7819 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7820
7821 switch (flags) {
7822 case GEN6_PCODE_SUCCESS:
7823 return 0;
7824 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7825 case GEN6_PCODE_ILLEGAL_CMD:
7826 return -ENXIO;
7827 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7828 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7829 return -EOVERFLOW;
7830 case GEN6_PCODE_TIMEOUT:
7831 return -ETIMEDOUT;
7832 default:
7833 MISSING_CASE(flags)
7834 return 0;
7835 }
7836}
7837
7838static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7839{
7840 uint32_t flags =
7841 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7842
7843 switch (flags) {
7844 case GEN6_PCODE_SUCCESS:
7845 return 0;
7846 case GEN6_PCODE_ILLEGAL_CMD:
7847 return -ENXIO;
7848 case GEN7_PCODE_TIMEOUT:
7849 return -ETIMEDOUT;
7850 case GEN7_PCODE_ILLEGAL_DATA:
7851 return -EINVAL;
7852 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7853 return -EOVERFLOW;
7854 default:
7855 MISSING_CASE(flags);
7856 return 0;
7857 }
7858}
7859
151a49d0 7860int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7861{
87660502
L		 7862 int status;
7863
4fc688ce 7864 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7865
3f5582dd
CW		 7866 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7867 * use te fw I915_READ variants to reduce the amount of work
7868 * required when reading/writing.
7869 */
7870
7871 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7872 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7873 return -EAGAIN;
7874 }
7875
3f5582dd
CW		 7876 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7877 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7878 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7879
3f5582dd
CW		 7880 if (intel_wait_for_register_fw(dev_priv,
7881 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7882 500)) {
42c0526c
BW		 7883 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7884 return -ETIMEDOUT;
7885 }
7886
3f5582dd
CW		 7887 *val = I915_READ_FW(GEN6_PCODE_DATA);
7888 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7889
87660502
L		 7890 if (INTEL_GEN(dev_priv) > 6)
7891 status = gen7_check_mailbox_status(dev_priv);
7892 else
7893 status = gen6_check_mailbox_status(dev_priv);
7894
7895 if (status) {
7896 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7897 status);
7898 return status;
7899 }
7900
42c0526c
BW		 7901 return 0;
7902}
7903
3f5582dd 7904int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7905 u32 mbox, u32 val)
42c0526c 7906{
87660502
L		 7907 int status;
7908
4fc688ce 7909 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7910
3f5582dd
CW		 7911 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7912 * use te fw I915_READ variants to reduce the amount of work
7913 * required when reading/writing.
7914 */
7915
7916 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7917 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7918 return -EAGAIN;
7919 }
7920
3f5582dd
CW		 7921 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7922 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7923
3f5582dd
CW		 7924 if (intel_wait_for_register_fw(dev_priv,
7925 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7926 500)) {
42c0526c
BW		 7927 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7928 return -ETIMEDOUT;
7929 }
7930
3f5582dd 7931 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7932
87660502
L		 7933 if (INTEL_GEN(dev_priv) > 6)
7934 status = gen7_check_mailbox_status(dev_priv);
7935 else
7936 status = gen6_check_mailbox_status(dev_priv);
7937
7938 if (status) {
7939 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7940 status);
7941 return status;
7942 }
7943
42c0526c
BW		 7944 return 0;
7945}
a0e4e199 7946
dd06f88c
VS		 7947static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7948{
c30fec65
VS		 7949 /*
7950 * N = val - 0xb7
7951 * Slow = Fast = GPLL ref * N
7952 */
7953 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7954}
7955
b55dd647 7956static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7957{
c30fec65 7958 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7959}
7960
b55dd647 7961static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7962{
c30fec65
VS		 7963 /*
7964 * N = val / 2
7965 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7966 */
7967 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7968}
7969
b55dd647 7970static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7971{
1c14762d 7972 /* CHV needs even values */
c30fec65 7973 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7974}
7975
616bc820 7976int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7977{
2d1fe073 7978 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7979 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7980 GEN9_FREQ_SCALER);
2d1fe073 7981 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7982 return chv_gpu_freq(dev_priv, val);
2d1fe073 7983 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7984 return byt_gpu_freq(dev_priv, val);
7985 else
7986 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7987}
7988
616bc820
VS		 7989int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7990{
2d1fe073 7991 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7992 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7993 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7994 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7995 return chv_freq_opcode(dev_priv, val);
2d1fe073 7996 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7997 return byt_freq_opcode(dev_priv, val);
7998 else
500a3d2e 7999 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 8000}
22b1b2f8 8001
6ad790c0
CW		 8002struct request_boost {
8003 struct work_struct work;
eed29a5b 8004 struct drm_i915_gem_request *req;
6ad790c0
CW		 8005};
8006
8007static void __intel_rps_boost_work(struct work_struct *work)
8008{
8009 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 8010 struct drm_i915_gem_request *req = boost->req;
6ad790c0 8011
f69a02c9 8012 if (!i915_gem_request_completed(req))
c033666a 8013 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 8014
e8a261ea 8015 i915_gem_request_put(req);
6ad790c0
CW		 8016 kfree(boost);
8017}
8018
91d14251 8019void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8020{
8021 struct request_boost *boost;
8022
91d14251 8023 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8024 return;
8025
f69a02c9 8026 if (i915_gem_request_completed(req))
e61b9958
CW		 8027 return;
8028
6ad790c0
CW		 8029 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8030 if (boost == NULL)
8031 return;
8032
e8a261ea 8033 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8034
8035 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8036 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8037}
8038
f742a552 8039void intel_pm_setup(struct drm_device *dev)
907b28c5 8040{
fac5e23e 8041 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8042
f742a552 8043 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8044 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8045
54b4f68f
CW		 8046 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8047 __intel_autoenable_gt_powersave);
1854d5ca 8048 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8049
33688d95 8050 dev_priv->pm.suspended = false;
1f814dac 8051 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 8052}
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