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drm/i915/skl: Retrieve the Rpe value from Pcode
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
669506e7 70 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 78
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 82 }
8bc0ccf6 83
2caa3b26 84 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
2caa3b26
DL		 89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 91 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 92 }
81e231af 93
8bc0ccf6
DL		 94 if (INTEL_REVID(dev) <= SKL_REVID_E0)
95 /* WaDisableLSQCROPERFforOCL:skl */
96 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
97 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 98}
99
a82abe43
ID		 100static void bxt_init_clock_gating(struct drm_device *dev)
101{
32608ca2
ID		 102 struct drm_i915_private *dev_priv = dev->dev_private;
103
a82abe43 104 gen9_init_clock_gating(dev);
32608ca2
ID		 105
106 /*
107 * FIXME:
108 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 109 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID		 110 */
111 /* WaDisableSDEUnitClockGating:bxt */
112 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW		 113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 115
e3a29055
RB		 116 /* FIXME: apply on A0 only */
117 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
a82abe43
ID		 118}
119
c921aba8
DV		 120static void i915_pineview_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u32 tmp;
124
125 tmp = I915_READ(CLKCFG);
126
127 switch (tmp & CLKCFG_FSB_MASK) {
128 case CLKCFG_FSB_533:
129 dev_priv->fsb_freq = 533; /* 133*4 */
130 break;
131 case CLKCFG_FSB_800:
132 dev_priv->fsb_freq = 800; /* 200*4 */
133 break;
134 case CLKCFG_FSB_667:
135 dev_priv->fsb_freq = 667; /* 167*4 */
136 break;
137 case CLKCFG_FSB_400:
138 dev_priv->fsb_freq = 400; /* 100*4 */
139 break;
140 }
141
142 switch (tmp & CLKCFG_MEM_MASK) {
143 case CLKCFG_MEM_533:
144 dev_priv->mem_freq = 533;
145 break;
146 case CLKCFG_MEM_667:
147 dev_priv->mem_freq = 667;
148 break;
149 case CLKCFG_MEM_800:
150 dev_priv->mem_freq = 800;
151 break;
152 }
153
154 /* detect pineview DDR3 setting */
155 tmp = I915_READ(CSHRDDR3CTL);
156 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
157}
158
159static void i915_ironlake_get_mem_freq(struct drm_device *dev)
160{
50227e1c 161 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 162 u16 ddrpll, csipll;
163
164 ddrpll = I915_READ16(DDRMPLL1);
165 csipll = I915_READ16(CSIPLL0);
166
167 switch (ddrpll & 0xff) {
168 case 0xc:
169 dev_priv->mem_freq = 800;
170 break;
171 case 0x10:
172 dev_priv->mem_freq = 1066;
173 break;
174 case 0x14:
175 dev_priv->mem_freq = 1333;
176 break;
177 case 0x18:
178 dev_priv->mem_freq = 1600;
179 break;
180 default:
181 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
182 ddrpll & 0xff);
183 dev_priv->mem_freq = 0;
184 break;
185 }
186
20e4d407 187 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 188
189 switch (csipll & 0x3ff) {
190 case 0x00c:
191 dev_priv->fsb_freq = 3200;
192 break;
193 case 0x00e:
194 dev_priv->fsb_freq = 3733;
195 break;
196 case 0x010:
197 dev_priv->fsb_freq = 4266;
198 break;
199 case 0x012:
200 dev_priv->fsb_freq = 4800;
201 break;
202 case 0x014:
203 dev_priv->fsb_freq = 5333;
204 break;
205 case 0x016:
206 dev_priv->fsb_freq = 5866;
207 break;
208 case 0x018:
209 dev_priv->fsb_freq = 6400;
210 break;
211 default:
212 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
213 csipll & 0x3ff);
214 dev_priv->fsb_freq = 0;
215 break;
216 }
217
218 if (dev_priv->fsb_freq == 3200) {
20e4d407 219 dev_priv->ips.c_m = 0;
c921aba8 220 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 221 dev_priv->ips.c_m = 1;
c921aba8 222 } else {
20e4d407 223 dev_priv->ips.c_m = 2;
c921aba8
DV		 224 }
225}
226
b445e3b0
ED		 227static const struct cxsr_latency cxsr_latency_table[] = {
228 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
229 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
230 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
231 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
232 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
233
234 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
235 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
236 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
237 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
238 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
239
240 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
241 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
242 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
243 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
244 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
245
246 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
247 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
248 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
249 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
250 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
251
252 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
253 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
254 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
255 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
256 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
257
258 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
259 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
260 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
261 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
262 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
263};
264
63c62275 265static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 266 int is_ddr3,
267 int fsb,
268 int mem)
269{
270 const struct cxsr_latency *latency;
271 int i;
272
273 if (fsb == 0 || mem == 0)
274 return NULL;
275
276 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
277 latency = &cxsr_latency_table[i];
278 if (is_desktop == latency->is_desktop &&
279 is_ddr3 == latency->is_ddr3 &&
280 fsb == latency->fsb_freq && mem == latency->mem_freq)
281 return latency;
282 }
283
284 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
285
286 return NULL;
287}
288
fc1ac8de
VS		 289static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
290{
291 u32 val;
292
293 mutex_lock(&dev_priv->rps.hw_lock);
294
295 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
296 if (enable)
297 val &= ~FORCE_DDR_HIGH_FREQ;
298 else
299 val |= FORCE_DDR_HIGH_FREQ;
300 val &= ~FORCE_DDR_LOW_FREQ;
301 val |= FORCE_DDR_FREQ_REQ_ACK;
302 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
303
304 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
305 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
306 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
307
308 mutex_unlock(&dev_priv->rps.hw_lock);
309}
310
cfb41411
VS		 311static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
312{
313 u32 val;
314
315 mutex_lock(&dev_priv->rps.hw_lock);
316
317 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
318 if (enable)
319 val |= DSP_MAXFIFO_PM5_ENABLE;
320 else
321 val &= ~DSP_MAXFIFO_PM5_ENABLE;
322 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
323
324 mutex_unlock(&dev_priv->rps.hw_lock);
325}
326
f4998963
VS		 327#define FW_WM(value, plane) \
328 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
329
5209b1f4 330void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 331{
5209b1f4
ID		 332 struct drm_device *dev = dev_priv->dev;
333 u32 val;
b445e3b0 334
5209b1f4
ID		 335 if (IS_VALLEYVIEW(dev)) {
336 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 337 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 338 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 339 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
340 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 342 } else if (IS_PINEVIEW(dev)) {
343 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
344 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
345 I915_WRITE(DSPFW3, val);
a7a6c498 346 POSTING_READ(DSPFW3);
5209b1f4
ID		 347 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
348 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
349 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
350 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 351 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 352 } else if (IS_I915GM(dev)) {
353 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
354 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
355 I915_WRITE(INSTPM, val);
a7a6c498 356 POSTING_READ(INSTPM);
5209b1f4
ID		 357 } else {
358 return;
359 }
b445e3b0 360
5209b1f4
ID		 361 DRM_DEBUG_KMS("memory self-refresh is %s\n",
362 enable ? "enabled" : "disabled");
b445e3b0
ED		 363}
364
fc1ac8de 365
b445e3b0
ED		 366/*
367 * Latency for FIFO fetches is dependent on several factors:
368 * - memory configuration (speed, channels)
369 * - chipset
370 * - current MCH state
371 * It can be fairly high in some situations, so here we assume a fairly
372 * pessimal value. It's a tradeoff between extra memory fetches (if we
373 * set this value too high, the FIFO will fetch frequently to stay full)
374 * and power consumption (set it too low to save power and we might see
375 * FIFO underruns and display "flicker").
376 *
377 * A value of 5us seems to be a good balance; safe for very low end
378 * platforms but not overly aggressive on lower latency configs.
379 */
5aef6003 380static const int pessimal_latency_ns = 5000;
b445e3b0 381
b5004720
VS		 382#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
383 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
384
385static int vlv_get_fifo_size(struct drm_device *dev,
386 enum pipe pipe, int plane)
387{
388 struct drm_i915_private *dev_priv = dev->dev_private;
389 int sprite0_start, sprite1_start, size;
390
391 switch (pipe) {
392 uint32_t dsparb, dsparb2, dsparb3;
393 case PIPE_A:
394 dsparb = I915_READ(DSPARB);
395 dsparb2 = I915_READ(DSPARB2);
396 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
397 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
398 break;
399 case PIPE_B:
400 dsparb = I915_READ(DSPARB);
401 dsparb2 = I915_READ(DSPARB2);
402 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
403 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
404 break;
405 case PIPE_C:
406 dsparb2 = I915_READ(DSPARB2);
407 dsparb3 = I915_READ(DSPARB3);
408 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
409 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
410 break;
411 default:
412 return 0;
413 }
414
415 switch (plane) {
416 case 0:
417 size = sprite0_start;
418 break;
419 case 1:
420 size = sprite1_start - sprite0_start;
421 break;
422 case 2:
423 size = 512 - 1 - sprite1_start;
424 break;
425 default:
426 return 0;
427 }
428
429 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
430 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
431 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
432 size);
433
434 return size;
435}
436
1fa61106 437static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 438{
439 struct drm_i915_private *dev_priv = dev->dev_private;
440 uint32_t dsparb = I915_READ(DSPARB);
441 int size;
442
443 size = dsparb & 0x7f;
444 if (plane)
445 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
446
447 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
448 plane ? "B" : "A", size);
449
450 return size;
451}
452
feb56b93 453static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t dsparb = I915_READ(DSPARB);
457 int size;
458
459 size = dsparb & 0x1ff;
460 if (plane)
461 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
462 size >>= 1; /* Convert to cachelines */
463
464 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
465 plane ? "B" : "A", size);
466
467 return size;
468}
469
1fa61106 470static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 471{
472 struct drm_i915_private *dev_priv = dev->dev_private;
473 uint32_t dsparb = I915_READ(DSPARB);
474 int size;
475
476 size = dsparb & 0x7f;
477 size >>= 2; /* Convert to cachelines */
478
479 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
480 plane ? "B" : "A",
481 size);
482
483 return size;
484}
485
b445e3b0
ED		 486/* Pineview has different values for various configs */
487static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 488 .fifo_size = PINEVIEW_DISPLAY_FIFO,
489 .max_wm = PINEVIEW_MAX_WM,
490 .default_wm = PINEVIEW_DFT_WM,
491 .guard_size = PINEVIEW_GUARD_WM,
492 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 493};
494static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 495 .fifo_size = PINEVIEW_DISPLAY_FIFO,
496 .max_wm = PINEVIEW_MAX_WM,
497 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
498 .guard_size = PINEVIEW_GUARD_WM,
499 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 500};
501static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 502 .fifo_size = PINEVIEW_CURSOR_FIFO,
503 .max_wm = PINEVIEW_CURSOR_MAX_WM,
504 .default_wm = PINEVIEW_CURSOR_DFT_WM,
505 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
506 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 507};
508static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 509 .fifo_size = PINEVIEW_CURSOR_FIFO,
510 .max_wm = PINEVIEW_CURSOR_MAX_WM,
511 .default_wm = PINEVIEW_CURSOR_DFT_WM,
512 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
513 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 514};
515static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 516 .fifo_size = G4X_FIFO_SIZE,
517 .max_wm = G4X_MAX_WM,
518 .default_wm = G4X_MAX_WM,
519 .guard_size = 2,
520 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 521};
522static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 523 .fifo_size = I965_CURSOR_FIFO,
524 .max_wm = I965_CURSOR_MAX_WM,
525 .default_wm = I965_CURSOR_DFT_WM,
526 .guard_size = 2,
527 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 528};
529static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 530 .fifo_size = VALLEYVIEW_FIFO_SIZE,
531 .max_wm = VALLEYVIEW_MAX_WM,
532 .default_wm = VALLEYVIEW_MAX_WM,
533 .guard_size = 2,
534 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 535};
536static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 537 .fifo_size = I965_CURSOR_FIFO,
538 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
539 .default_wm = I965_CURSOR_DFT_WM,
540 .guard_size = 2,
541 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 542};
543static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 544 .fifo_size = I965_CURSOR_FIFO,
545 .max_wm = I965_CURSOR_MAX_WM,
546 .default_wm = I965_CURSOR_DFT_WM,
547 .guard_size = 2,
548 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 549};
550static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 551 .fifo_size = I945_FIFO_SIZE,
552 .max_wm = I915_MAX_WM,
553 .default_wm = 1,
554 .guard_size = 2,
555 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 556};
557static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 558 .fifo_size = I915_FIFO_SIZE,
559 .max_wm = I915_MAX_WM,
560 .default_wm = 1,
561 .guard_size = 2,
562 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 563};
9d539105 564static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 565 .fifo_size = I855GM_FIFO_SIZE,
566 .max_wm = I915_MAX_WM,
567 .default_wm = 1,
568 .guard_size = 2,
569 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 570};
9d539105
VS		 571static const struct intel_watermark_params i830_bc_wm_info = {
572 .fifo_size = I855GM_FIFO_SIZE,
573 .max_wm = I915_MAX_WM/2,
574 .default_wm = 1,
575 .guard_size = 2,
576 .cacheline_size = I830_FIFO_LINE_SIZE,
577};
feb56b93 578static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 579 .fifo_size = I830_FIFO_SIZE,
580 .max_wm = I915_MAX_WM,
581 .default_wm = 1,
582 .guard_size = 2,
583 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 584};
585
b445e3b0
ED		 586/**
587 * intel_calculate_wm - calculate watermark level
588 * @clock_in_khz: pixel clock
589 * @wm: chip FIFO params
590 * @pixel_size: display pixel size
591 * @latency_ns: memory latency for the platform
592 *
593 * Calculate the watermark level (the level at which the display plane will
594 * start fetching from memory again). Each chip has a different display
595 * FIFO size and allocation, so the caller needs to figure that out and pass
596 * in the correct intel_watermark_params structure.
597 *
598 * As the pixel clock runs, the FIFO will be drained at a rate that depends
599 * on the pixel size. When it reaches the watermark level, it'll start
600 * fetching FIFO line sized based chunks from memory until the FIFO fills
601 * past the watermark point. If the FIFO drains completely, a FIFO underrun
602 * will occur, and a display engine hang could result.
603 */
604static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
605 const struct intel_watermark_params *wm,
606 int fifo_size,
607 int pixel_size,
608 unsigned long latency_ns)
609{
610 long entries_required, wm_size;
611
612 /*
613 * Note: we need to make sure we don't overflow for various clock &
614 * latency values.
615 * clocks go from a few thousand to several hundred thousand.
616 * latency is usually a few thousand
617 */
618 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
619 1000;
620 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
621
622 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
623
624 wm_size = fifo_size - (entries_required + wm->guard_size);
625
626 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
627
628 /* Don't promote wm_size to unsigned... */
629 if (wm_size > (long)wm->max_wm)
630 wm_size = wm->max_wm;
631 if (wm_size <= 0)
632 wm_size = wm->default_wm;
d6feb196
VS		 633
634 /*
635 * Bspec seems to indicate that the value shouldn't be lower than
636 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
637 * Lets go for 8 which is the burst size since certain platforms
638 * already use a hardcoded 8 (which is what the spec says should be
639 * done).
640 */
641 if (wm_size <= 8)
642 wm_size = 8;
643
b445e3b0
ED		 644 return wm_size;
645}
646
647static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
648{
649 struct drm_crtc *crtc, *enabled = NULL;
650
70e1e0ec 651 for_each_crtc(dev, crtc) {
3490ea5d 652 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 653 if (enabled)
654 return NULL;
655 enabled = crtc;
656 }
657 }
658
659 return enabled;
660}
661
46ba614c 662static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 663{
46ba614c 664 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 665 struct drm_i915_private *dev_priv = dev->dev_private;
666 struct drm_crtc *crtc;
667 const struct cxsr_latency *latency;
668 u32 reg;
669 unsigned long wm;
670
671 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
672 dev_priv->fsb_freq, dev_priv->mem_freq);
673 if (!latency) {
674 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 675 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 676 return;
677 }
678
679 crtc = single_enabled_crtc(dev);
680 if (crtc) {
241bfc38 681 const struct drm_display_mode *adjusted_mode;
59bea882 682 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 683 int clock;
684
6e3c9717 685 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 686 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 687
688 /* Display SR */
689 wm = intel_calculate_wm(clock, &pineview_display_wm,
690 pineview_display_wm.fifo_size,
691 pixel_size, latency->display_sr);
692 reg = I915_READ(DSPFW1);
693 reg &= ~DSPFW_SR_MASK;
f4998963 694 reg |= FW_WM(wm, SR);
b445e3b0
ED		 695 I915_WRITE(DSPFW1, reg);
696 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
697
698 /* cursor SR */
699 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
700 pineview_display_wm.fifo_size,
701 pixel_size, latency->cursor_sr);
702 reg = I915_READ(DSPFW3);
703 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 704 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 705 I915_WRITE(DSPFW3, reg);
706
707 /* Display HPLL off SR */
708 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
709 pineview_display_hplloff_wm.fifo_size,
710 pixel_size, latency->display_hpll_disable);
711 reg = I915_READ(DSPFW3);
712 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 713 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 714 I915_WRITE(DSPFW3, reg);
715
716 /* cursor HPLL off SR */
717 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
718 pineview_display_hplloff_wm.fifo_size,
719 pixel_size, latency->cursor_hpll_disable);
720 reg = I915_READ(DSPFW3);
721 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 722 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 723 I915_WRITE(DSPFW3, reg);
724 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
725
5209b1f4 726 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 727 } else {
5209b1f4 728 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 729 }
730}
731
732static bool g4x_compute_wm0(struct drm_device *dev,
733 int plane,
734 const struct intel_watermark_params *display,
735 int display_latency_ns,
736 const struct intel_watermark_params *cursor,
737 int cursor_latency_ns,
738 int *plane_wm,
739 int *cursor_wm)
740{
741 struct drm_crtc *crtc;
4fe8590a 742 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 743 int htotal, hdisplay, clock, pixel_size;
744 int line_time_us, line_count;
745 int entries, tlb_miss;
746
747 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 748 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 749 *cursor_wm = cursor->guard_size;
750 *plane_wm = display->guard_size;
751 return false;
752 }
753
6e3c9717 754 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 755 clock = adjusted_mode->crtc_clock;
fec8cba3 756 htotal = adjusted_mode->crtc_htotal;
6e3c9717 757 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 758 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 759
760 /* Use the small buffer method to calculate plane watermark */
761 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
762 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
763 if (tlb_miss > 0)
764 entries += tlb_miss;
765 entries = DIV_ROUND_UP(entries, display->cacheline_size);
766 *plane_wm = entries + display->guard_size;
767 if (*plane_wm > (int)display->max_wm)
768 *plane_wm = display->max_wm;
769
770 /* Use the large buffer method to calculate cursor watermark */
922044c9 771 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 772 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 773 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 774 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
775 if (tlb_miss > 0)
776 entries += tlb_miss;
777 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
778 *cursor_wm = entries + cursor->guard_size;
779 if (*cursor_wm > (int)cursor->max_wm)
780 *cursor_wm = (int)cursor->max_wm;
781
782 return true;
783}
784
785/*
786 * Check the wm result.
787 *
788 * If any calculated watermark values is larger than the maximum value that
789 * can be programmed into the associated watermark register, that watermark
790 * must be disabled.
791 */
792static bool g4x_check_srwm(struct drm_device *dev,
793 int display_wm, int cursor_wm,
794 const struct intel_watermark_params *display,
795 const struct intel_watermark_params *cursor)
796{
797 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
798 display_wm, cursor_wm);
799
800 if (display_wm > display->max_wm) {
801 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
802 display_wm, display->max_wm);
803 return false;
804 }
805
806 if (cursor_wm > cursor->max_wm) {
807 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
808 cursor_wm, cursor->max_wm);
809 return false;
810 }
811
812 if (!(display_wm || cursor_wm)) {
813 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
814 return false;
815 }
816
817 return true;
818}
819
820static bool g4x_compute_srwm(struct drm_device *dev,
821 int plane,
822 int latency_ns,
823 const struct intel_watermark_params *display,
824 const struct intel_watermark_params *cursor,
825 int *display_wm, int *cursor_wm)
826{
827 struct drm_crtc *crtc;
4fe8590a 828 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 829 int hdisplay, htotal, pixel_size, clock;
830 unsigned long line_time_us;
831 int line_count, line_size;
832 int small, large;
833 int entries;
834
835 if (!latency_ns) {
836 *display_wm = *cursor_wm = 0;
837 return false;
838 }
839
840 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 841 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 842 clock = adjusted_mode->crtc_clock;
fec8cba3 843 htotal = adjusted_mode->crtc_htotal;
6e3c9717 844 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 845 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 846
922044c9 847 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 848 line_count = (latency_ns / line_time_us + 1000) / 1000;
849 line_size = hdisplay * pixel_size;
850
851 /* Use the minimum of the small and large buffer method for primary */
852 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
853 large = line_count * line_size;
854
855 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
856 *display_wm = entries + display->guard_size;
857
858 /* calculate the self-refresh watermark for display cursor */
3dd512fb 859 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 860 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
861 *cursor_wm = entries + cursor->guard_size;
862
863 return g4x_check_srwm(dev,
864 *display_wm, *cursor_wm,
865 display, cursor);
866}
867
15665979
VS		 868#define FW_WM_VLV(value, plane) \
869 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
870
0018fda1
VS		 871static void vlv_write_wm_values(struct intel_crtc *crtc,
872 const struct vlv_wm_values *wm)
873{
874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
875 enum pipe pipe = crtc->pipe;
876
877 I915_WRITE(VLV_DDL(pipe),
878 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
879 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
880 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
881 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
882
ae80152d 883 I915_WRITE(DSPFW1,
15665979
VS		 884 FW_WM(wm->sr.plane, SR) |
885 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
886 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
887 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 888 I915_WRITE(DSPFW2,
15665979
VS		 889 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
890 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
891 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 892 I915_WRITE(DSPFW3,
15665979 893 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 894
895 if (IS_CHERRYVIEW(dev_priv)) {
896 I915_WRITE(DSPFW7_CHV,
15665979
VS		 897 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
898 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 899 I915_WRITE(DSPFW8_CHV,
15665979
VS		 900 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
901 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 902 I915_WRITE(DSPFW9_CHV,
15665979
VS		 903 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
904 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 905 I915_WRITE(DSPHOWM,
15665979
VS		 906 FW_WM(wm->sr.plane >> 9, SR_HI) |
907 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
908 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
909 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
910 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
911 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
912 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
913 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
914 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
915 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 916 } else {
917 I915_WRITE(DSPFW7,
15665979
VS		 918 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
919 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 920 I915_WRITE(DSPHOWM,
15665979
VS		 921 FW_WM(wm->sr.plane >> 9, SR_HI) |
922 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
923 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
924 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
925 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
926 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
927 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 928 }
929
2cb389b7
VS		 930 /* zero (unused) WM1 watermarks */
931 I915_WRITE(DSPFW4, 0);
932 I915_WRITE(DSPFW5, 0);
933 I915_WRITE(DSPFW6, 0);
934 I915_WRITE(DSPHOWM1, 0);
935
ae80152d 936 POSTING_READ(DSPFW1);
0018fda1
VS		 937}
938
15665979
VS		 939#undef FW_WM_VLV
940
6eb1a681
VS		 941enum vlv_wm_level {
942 VLV_WM_LEVEL_PM2,
943 VLV_WM_LEVEL_PM5,
944 VLV_WM_LEVEL_DDR_DVFS,
945 CHV_WM_NUM_LEVELS,
946 VLV_WM_NUM_LEVELS = 1,
947};
948
262cd2e1
VS		 949/* latency must be in 0.1us units. */
950static unsigned int vlv_wm_method2(unsigned int pixel_rate,
951 unsigned int pipe_htotal,
952 unsigned int horiz_pixels,
953 unsigned int bytes_per_pixel,
954 unsigned int latency)
955{
956 unsigned int ret;
957
958 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
959 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
960 ret = DIV_ROUND_UP(ret, 64);
961
962 return ret;
963}
964
965static void vlv_setup_wm_latency(struct drm_device *dev)
966{
967 struct drm_i915_private *dev_priv = dev->dev_private;
968
969 /* all latencies in usec */
970 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
971
972 if (IS_CHERRYVIEW(dev_priv)) {
973 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
974 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
975 }
976}
977
978static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
979 struct intel_crtc *crtc,
980 const struct intel_plane_state *state,
981 int level)
982{
983 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
984 int clock, htotal, pixel_size, width, wm;
985
986 if (dev_priv->wm.pri_latency[level] == 0)
987 return USHRT_MAX;
988
989 if (!state->visible)
990 return 0;
991
992 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
993 clock = crtc->config->base.adjusted_mode.crtc_clock;
994 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
995 width = crtc->config->pipe_src_w;
996 if (WARN_ON(htotal == 0))
997 htotal = 1;
998
999 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1000 /*
1001 * FIXME the formula gives values that are
1002 * too big for the cursor FIFO, and hence we
1003 * would never be able to use cursors. For
1004 * now just hardcode the watermark.
1005 */
1006 wm = 63;
1007 } else {
1008 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1009 dev_priv->wm.pri_latency[level] * 10);
1010 }
1011
1012 return min_t(int, wm, USHRT_MAX);
1013}
1014
54f1b6e1
VS		 1015static void vlv_compute_fifo(struct intel_crtc *crtc)
1016{
1017 struct drm_device *dev = crtc->base.dev;
1018 struct vlv_wm_state *wm_state = &crtc->wm_state;
1019 struct intel_plane *plane;
1020 unsigned int total_rate = 0;
1021 const int fifo_size = 512 - 1;
1022 int fifo_extra, fifo_left = fifo_size;
1023
1024 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1025 struct intel_plane_state *state =
1026 to_intel_plane_state(plane->base.state);
1027
1028 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1029 continue;
1030
1031 if (state->visible) {
1032 wm_state->num_active_planes++;
1033 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1034 }
1035 }
1036
1037 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1038 struct intel_plane_state *state =
1039 to_intel_plane_state(plane->base.state);
1040 unsigned int rate;
1041
1042 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1043 plane->wm.fifo_size = 63;
1044 continue;
1045 }
1046
1047 if (!state->visible) {
1048 plane->wm.fifo_size = 0;
1049 continue;
1050 }
1051
1052 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1053 plane->wm.fifo_size = fifo_size * rate / total_rate;
1054 fifo_left -= plane->wm.fifo_size;
1055 }
1056
1057 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1058
1059 /* spread the remainder evenly */
1060 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1061 int plane_extra;
1062
1063 if (fifo_left == 0)
1064 break;
1065
1066 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1067 continue;
1068
1069 /* give it all to the first plane if none are active */
1070 if (plane->wm.fifo_size == 0 &&
1071 wm_state->num_active_planes)
1072 continue;
1073
1074 plane_extra = min(fifo_extra, fifo_left);
1075 plane->wm.fifo_size += plane_extra;
1076 fifo_left -= plane_extra;
1077 }
1078
1079 WARN_ON(fifo_left != 0);
1080}
1081
262cd2e1
VS		 1082static void vlv_invert_wms(struct intel_crtc *crtc)
1083{
1084 struct vlv_wm_state *wm_state = &crtc->wm_state;
1085 int level;
1086
1087 for (level = 0; level < wm_state->num_levels; level++) {
1088 struct drm_device *dev = crtc->base.dev;
1089 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1090 struct intel_plane *plane;
1091
1092 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1093 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1094
1095 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1096 switch (plane->base.type) {
1097 int sprite;
1098 case DRM_PLANE_TYPE_CURSOR:
1099 wm_state->wm[level].cursor = plane->wm.fifo_size -
1100 wm_state->wm[level].cursor;
1101 break;
1102 case DRM_PLANE_TYPE_PRIMARY:
1103 wm_state->wm[level].primary = plane->wm.fifo_size -
1104 wm_state->wm[level].primary;
1105 break;
1106 case DRM_PLANE_TYPE_OVERLAY:
1107 sprite = plane->plane;
1108 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1109 wm_state->wm[level].sprite[sprite];
1110 break;
1111 }
1112 }
1113 }
1114}
1115
26e1fe4f 1116static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1117{
1118 struct drm_device *dev = crtc->base.dev;
1119 struct vlv_wm_state *wm_state = &crtc->wm_state;
1120 struct intel_plane *plane;
1121 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1122 int level;
1123
1124 memset(wm_state, 0, sizeof(*wm_state));
1125
852eb00d 1126 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
262cd2e1
VS		 1127 if (IS_CHERRYVIEW(dev))
1128 wm_state->num_levels = CHV_WM_NUM_LEVELS;
1129 else
1130 wm_state->num_levels = VLV_WM_NUM_LEVELS;
1131
1132 wm_state->num_active_planes = 0;
262cd2e1 1133
54f1b6e1 1134 vlv_compute_fifo(crtc);
262cd2e1
VS		 1135
1136 if (wm_state->num_active_planes != 1)
1137 wm_state->cxsr = false;
1138
1139 if (wm_state->cxsr) {
1140 for (level = 0; level < wm_state->num_levels; level++) {
1141 wm_state->sr[level].plane = sr_fifo_size;
1142 wm_state->sr[level].cursor = 63;
1143 }
1144 }
1145
1146 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1147 struct intel_plane_state *state =
1148 to_intel_plane_state(plane->base.state);
1149
1150 if (!state->visible)
1151 continue;
1152
1153 /* normal watermarks */
1154 for (level = 0; level < wm_state->num_levels; level++) {
1155 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1156 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1157
1158 /* hack */
1159 if (WARN_ON(level == 0 && wm > max_wm))
1160 wm = max_wm;
1161
1162 if (wm > plane->wm.fifo_size)
1163 break;
1164
1165 switch (plane->base.type) {
1166 int sprite;
1167 case DRM_PLANE_TYPE_CURSOR:
1168 wm_state->wm[level].cursor = wm;
1169 break;
1170 case DRM_PLANE_TYPE_PRIMARY:
1171 wm_state->wm[level].primary = wm;
1172 break;
1173 case DRM_PLANE_TYPE_OVERLAY:
1174 sprite = plane->plane;
1175 wm_state->wm[level].sprite[sprite] = wm;
1176 break;
1177 }
1178 }
1179
1180 wm_state->num_levels = level;
1181
1182 if (!wm_state->cxsr)
1183 continue;
1184
1185 /* maxfifo watermarks */
1186 switch (plane->base.type) {
1187 int sprite, level;
1188 case DRM_PLANE_TYPE_CURSOR:
1189 for (level = 0; level < wm_state->num_levels; level++)
1190 wm_state->sr[level].cursor =
1191 wm_state->sr[level].cursor;
1192 break;
1193 case DRM_PLANE_TYPE_PRIMARY:
1194 for (level = 0; level < wm_state->num_levels; level++)
1195 wm_state->sr[level].plane =
1196 min(wm_state->sr[level].plane,
1197 wm_state->wm[level].primary);
1198 break;
1199 case DRM_PLANE_TYPE_OVERLAY:
1200 sprite = plane->plane;
1201 for (level = 0; level < wm_state->num_levels; level++)
1202 wm_state->sr[level].plane =
1203 min(wm_state->sr[level].plane,
1204 wm_state->wm[level].sprite[sprite]);
1205 break;
1206 }
1207 }
1208
1209 /* clear any (partially) filled invalid levels */
1210 for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
1211 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1212 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1213 }
1214
1215 vlv_invert_wms(crtc);
1216}
1217
54f1b6e1
VS		 1218#define VLV_FIFO(plane, value) \
1219 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1220
1221static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1222{
1223 struct drm_device *dev = crtc->base.dev;
1224 struct drm_i915_private *dev_priv = to_i915(dev);
1225 struct intel_plane *plane;
1226 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1227
1228 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1229 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1230 WARN_ON(plane->wm.fifo_size != 63);
1231 continue;
1232 }
1233
1234 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1235 sprite0_start = plane->wm.fifo_size;
1236 else if (plane->plane == 0)
1237 sprite1_start = sprite0_start + plane->wm.fifo_size;
1238 else
1239 fifo_size = sprite1_start + plane->wm.fifo_size;
1240 }
1241
1242 WARN_ON(fifo_size != 512 - 1);
1243
1244 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1245 pipe_name(crtc->pipe), sprite0_start,
1246 sprite1_start, fifo_size);
1247
1248 switch (crtc->pipe) {
1249 uint32_t dsparb, dsparb2, dsparb3;
1250 case PIPE_A:
1251 dsparb = I915_READ(DSPARB);
1252 dsparb2 = I915_READ(DSPARB2);
1253
1254 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1255 VLV_FIFO(SPRITEB, 0xff));
1256 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1257 VLV_FIFO(SPRITEB, sprite1_start));
1258
1259 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1260 VLV_FIFO(SPRITEB_HI, 0x1));
1261 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1262 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1263
1264 I915_WRITE(DSPARB, dsparb);
1265 I915_WRITE(DSPARB2, dsparb2);
1266 break;
1267 case PIPE_B:
1268 dsparb = I915_READ(DSPARB);
1269 dsparb2 = I915_READ(DSPARB2);
1270
1271 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1272 VLV_FIFO(SPRITED, 0xff));
1273 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1274 VLV_FIFO(SPRITED, sprite1_start));
1275
1276 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1277 VLV_FIFO(SPRITED_HI, 0xff));
1278 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1279 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1280
1281 I915_WRITE(DSPARB, dsparb);
1282 I915_WRITE(DSPARB2, dsparb2);
1283 break;
1284 case PIPE_C:
1285 dsparb3 = I915_READ(DSPARB3);
1286 dsparb2 = I915_READ(DSPARB2);
1287
1288 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1289 VLV_FIFO(SPRITEF, 0xff));
1290 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1291 VLV_FIFO(SPRITEF, sprite1_start));
1292
1293 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1294 VLV_FIFO(SPRITEF_HI, 0xff));
1295 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1296 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1297
1298 I915_WRITE(DSPARB3, dsparb3);
1299 I915_WRITE(DSPARB2, dsparb2);
1300 break;
1301 default:
1302 break;
1303 }
1304}
1305
1306#undef VLV_FIFO
1307
262cd2e1
VS		 1308static void vlv_merge_wm(struct drm_device *dev,
1309 struct vlv_wm_values *wm)
1310{
1311 struct intel_crtc *crtc;
1312 int num_active_crtcs = 0;
1313
1314 if (IS_CHERRYVIEW(dev))
1315 wm->level = VLV_WM_LEVEL_DDR_DVFS;
1316 else
1317 wm->level = VLV_WM_LEVEL_PM2;
1318 wm->cxsr = true;
1319
1320 for_each_intel_crtc(dev, crtc) {
1321 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1322
1323 if (!crtc->active)
1324 continue;
1325
1326 if (!wm_state->cxsr)
1327 wm->cxsr = false;
1328
1329 num_active_crtcs++;
1330 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1331 }
1332
1333 if (num_active_crtcs != 1)
1334 wm->cxsr = false;
1335
6f9c784b
VS		 1336 if (num_active_crtcs > 1)
1337 wm->level = VLV_WM_LEVEL_PM2;
1338
262cd2e1
VS		 1339 for_each_intel_crtc(dev, crtc) {
1340 struct vlv_wm_state *wm_state = &crtc->wm_state;
1341 enum pipe pipe = crtc->pipe;
1342
1343 if (!crtc->active)
1344 continue;
1345
1346 wm->pipe[pipe] = wm_state->wm[wm->level];
1347 if (wm->cxsr)
1348 wm->sr = wm_state->sr[wm->level];
1349
1350 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1351 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1352 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1353 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1354 }
1355}
1356
1357static void vlv_update_wm(struct drm_crtc *crtc)
1358{
1359 struct drm_device *dev = crtc->dev;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1362 enum pipe pipe = intel_crtc->pipe;
1363 struct vlv_wm_values wm = {};
1364
26e1fe4f 1365 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1366 vlv_merge_wm(dev, &wm);
1367
54f1b6e1
VS		 1368 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1369 /* FIXME should be part of crtc atomic commit */
1370 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1371 return;
54f1b6e1 1372 }
262cd2e1
VS		 1373
1374 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1375 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1376 chv_set_memory_dvfs(dev_priv, false);
1377
1378 if (wm.level < VLV_WM_LEVEL_PM5 &&
1379 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1380 chv_set_memory_pm5(dev_priv, false);
1381
852eb00d 1382 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1383 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1384
54f1b6e1
VS		 1385 /* FIXME should be part of crtc atomic commit */
1386 vlv_pipe_set_fifo_size(intel_crtc);
1387
262cd2e1
VS		 1388 vlv_write_wm_values(intel_crtc, &wm);
1389
1390 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1391 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1392 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1393 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1394 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1395
852eb00d 1396 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1397 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1398
1399 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1400 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1401 chv_set_memory_pm5(dev_priv, true);
1402
1403 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1404 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1405 chv_set_memory_dvfs(dev_priv, true);
1406
1407 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1408}
1409
ae80152d
VS		 1410#define single_plane_enabled(mask) is_power_of_2(mask)
1411
46ba614c 1412static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1413{
46ba614c 1414 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1415 static const int sr_latency_ns = 12000;
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1418 int plane_sr, cursor_sr;
1419 unsigned int enabled = 0;
9858425c 1420 bool cxsr_enabled;
b445e3b0 1421
51cea1f4 1422 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1423 &g4x_wm_info, pessimal_latency_ns,
1424 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1425 &planea_wm, &cursora_wm))
51cea1f4 1426 enabled |= 1 << PIPE_A;
b445e3b0 1427
51cea1f4 1428 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1429 &g4x_wm_info, pessimal_latency_ns,
1430 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1431 &planeb_wm, &cursorb_wm))
51cea1f4 1432 enabled |= 1 << PIPE_B;
b445e3b0 1433
b445e3b0
ED		 1434 if (single_plane_enabled(enabled) &&
1435 g4x_compute_srwm(dev, ffs(enabled) - 1,
1436 sr_latency_ns,
1437 &g4x_wm_info,
1438 &g4x_cursor_wm_info,
52bd02d8 1439 &plane_sr, &cursor_sr)) {
9858425c 1440 cxsr_enabled = true;
52bd02d8 1441 } else {
9858425c 1442 cxsr_enabled = false;
5209b1f4 1443 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1444 plane_sr = cursor_sr = 0;
1445 }
b445e3b0 1446
a5043453
VS		 1447 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1448 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1449 planea_wm, cursora_wm,
1450 planeb_wm, cursorb_wm,
1451 plane_sr, cursor_sr);
1452
1453 I915_WRITE(DSPFW1,
f4998963
VS		 1454 FW_WM(plane_sr, SR) |
1455 FW_WM(cursorb_wm, CURSORB) |
1456 FW_WM(planeb_wm, PLANEB) |
1457 FW_WM(planea_wm, PLANEA));
b445e3b0 1458 I915_WRITE(DSPFW2,
8c919b28 1459 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1460 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1461 /* HPLL off in SR has some issues on G4x... disable it */
1462 I915_WRITE(DSPFW3,
8c919b28 1463 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1464 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1465
1466 if (cxsr_enabled)
1467 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1468}
1469
46ba614c 1470static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1471{
46ba614c 1472 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1473 struct drm_i915_private *dev_priv = dev->dev_private;
1474 struct drm_crtc *crtc;
1475 int srwm = 1;
1476 int cursor_sr = 16;
9858425c 1477 bool cxsr_enabled;
b445e3b0
ED		 1478
1479 /* Calc sr entries for one plane configs */
1480 crtc = single_enabled_crtc(dev);
1481 if (crtc) {
1482 /* self-refresh has much higher latency */
1483 static const int sr_latency_ns = 12000;
4fe8590a 1484 const struct drm_display_mode *adjusted_mode =
6e3c9717 1485 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1486 int clock = adjusted_mode->crtc_clock;
fec8cba3 1487 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1488 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1489 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1490 unsigned long line_time_us;
1491 int entries;
1492
922044c9 1493 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1494
1495 /* Use ns/us then divide to preserve precision */
1496 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497 pixel_size * hdisplay;
1498 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499 srwm = I965_FIFO_SIZE - entries;
1500 if (srwm < 0)
1501 srwm = 1;
1502 srwm &= 0x1ff;
1503 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504 entries, srwm);
1505
1506 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1507 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1508 entries = DIV_ROUND_UP(entries,
1509 i965_cursor_wm_info.cacheline_size);
1510 cursor_sr = i965_cursor_wm_info.fifo_size -
1511 (entries + i965_cursor_wm_info.guard_size);
1512
1513 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514 cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517 "cursor %d\n", srwm, cursor_sr);
1518
9858425c 1519 cxsr_enabled = true;
b445e3b0 1520 } else {
9858425c 1521 cxsr_enabled = false;
b445e3b0 1522 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1523 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1524 }
1525
1526 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527 srwm);
1528
1529 /* 965 has limitations... */
f4998963
VS		 1530 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531 FW_WM(8, CURSORB) |
1532 FW_WM(8, PLANEB) |
1533 FW_WM(8, PLANEA));
1534 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535 FW_WM(8, PLANEC_OLD));
b445e3b0 1536 /* update cursor SR watermark */
f4998963 1537 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1538
1539 if (cxsr_enabled)
1540 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1541}
1542
f4998963
VS		 1543#undef FW_WM
1544
46ba614c 1545static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1546{
46ba614c 1547 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 const struct intel_watermark_params *wm_info;
1550 uint32_t fwater_lo;
1551 uint32_t fwater_hi;
1552 int cwm, srwm = 1;
1553 int fifo_size;
1554 int planea_wm, planeb_wm;
1555 struct drm_crtc *crtc, *enabled = NULL;
1556
1557 if (IS_I945GM(dev))
1558 wm_info = &i945_wm_info;
1559 else if (!IS_GEN2(dev))
1560 wm_info = &i915_wm_info;
1561 else
9d539105 1562 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1563
1564 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1566 if (intel_crtc_active(crtc)) {
241bfc38 1567 const struct drm_display_mode *adjusted_mode;
59bea882 1568 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1569 if (IS_GEN2(dev))
1570 cpp = 4;
1571
6e3c9717 1572 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1573 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1574 wm_info, fifo_size, cpp,
5aef6003 1575 pessimal_latency_ns);
b445e3b0 1576 enabled = crtc;
9d539105 1577 } else {
b445e3b0 1578 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1579 if (planea_wm > (long)wm_info->max_wm)
1580 planea_wm = wm_info->max_wm;
1581 }
1582
1583 if (IS_GEN2(dev))
1584 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1585
1586 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1588 if (intel_crtc_active(crtc)) {
241bfc38 1589 const struct drm_display_mode *adjusted_mode;
59bea882 1590 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1591 if (IS_GEN2(dev))
1592 cpp = 4;
1593
6e3c9717 1594 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1595 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1596 wm_info, fifo_size, cpp,
5aef6003 1597 pessimal_latency_ns);
b445e3b0
ED		 1598 if (enabled == NULL)
1599 enabled = crtc;
1600 else
1601 enabled = NULL;
9d539105 1602 } else {
b445e3b0 1603 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1604 if (planeb_wm > (long)wm_info->max_wm)
1605 planeb_wm = wm_info->max_wm;
1606 }
b445e3b0
ED		 1607
1608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
2ab1bc9d 1610 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1611 struct drm_i915_gem_object *obj;
2ab1bc9d 1612
59bea882 1613 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1614
1615 /* self-refresh seems busted with untiled */
2ff8fde1 1616 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1617 enabled = NULL;
1618 }
1619
b445e3b0
ED		 1620 /*
1621 * Overlay gets an aggressive default since video jitter is bad.
1622 */
1623 cwm = 2;
1624
1625 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1626 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1627
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev) && enabled) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns = 6000;
4fe8590a 1632 const struct drm_display_mode *adjusted_mode =
6e3c9717 1633 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1634 int clock = adjusted_mode->crtc_clock;
fec8cba3 1635 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1636 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1637 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1638 unsigned long line_time_us;
1639 int entries;
1640
922044c9 1641 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1642
1643 /* Use ns/us then divide to preserve precision */
1644 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1645 pixel_size * hdisplay;
1646 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1647 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1648 srwm = wm_info->fifo_size - entries;
1649 if (srwm < 0)
1650 srwm = 1;
1651
1652 if (IS_I945G(dev) || IS_I945GM(dev))
1653 I915_WRITE(FW_BLC_SELF,
1654 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1655 else if (IS_I915GM(dev))
1656 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1657 }
1658
1659 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1660 planea_wm, planeb_wm, cwm, srwm);
1661
1662 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1663 fwater_hi = (cwm & 0x1f);
1664
1665 /* Set request length to 8 cachelines per fetch */
1666 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1667 fwater_hi = fwater_hi | (1 << 8);
1668
1669 I915_WRITE(FW_BLC, fwater_lo);
1670 I915_WRITE(FW_BLC2, fwater_hi);
1671
5209b1f4
ID		 1672 if (enabled)
1673 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1674}
1675
feb56b93 1676static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1677{
46ba614c 1678 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_crtc *crtc;
241bfc38 1681 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1682 uint32_t fwater_lo;
1683 int planea_wm;
1684
1685 crtc = single_enabled_crtc(dev);
1686 if (crtc == NULL)
1687 return;
1688
6e3c9717 1689 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1691 &i845_wm_info,
b445e3b0 1692 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1693 4, pessimal_latency_ns);
b445e3b0
ED		 1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1696
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699 I915_WRITE(FW_BLC, fwater_lo);
1700}
1701
8cfb3407 1702uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1703{
fd4daa9c 1704 uint32_t pixel_rate;
801bcfff 1705
8cfb3407 1706 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1707
1708 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1709 * adjust the pixel_rate here. */
1710
8cfb3407 1711 if (pipe_config->pch_pfit.enabled) {
801bcfff 1712 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1713 uint32_t pfit_size = pipe_config->pch_pfit.size;
1714
1715 pipe_w = pipe_config->pipe_src_w;
1716 pipe_h = pipe_config->pipe_src_h;
801bcfff 1717
801bcfff
PZ		 1718 pfit_w = (pfit_size >> 16) & 0xFFFF;
1719 pfit_h = pfit_size & 0xFFFF;
1720 if (pipe_w < pfit_w)
1721 pipe_w = pfit_w;
1722 if (pipe_h < pfit_h)
1723 pipe_h = pfit_h;
1724
1725 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1726 pfit_w * pfit_h);
1727 }
1728
1729 return pixel_rate;
1730}
1731
37126462 1732/* latency must be in 0.1us units. */
23297044 1733static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1734 uint32_t latency)
1735{
1736 uint64_t ret;
1737
3312ba65
VS		 1738 if (WARN(latency == 0, "Latency value missing\n"))
1739 return UINT_MAX;
1740
801bcfff
PZ		 1741 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1742 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1743
1744 return ret;
1745}
1746
37126462 1747/* latency must be in 0.1us units. */
23297044 1748static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1749 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1750 uint32_t latency)
1751{
1752 uint32_t ret;
1753
3312ba65
VS		 1754 if (WARN(latency == 0, "Latency value missing\n"))
1755 return UINT_MAX;
1756
801bcfff
PZ		 1757 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1758 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1759 ret = DIV_ROUND_UP(ret, 64) + 2;
1760 return ret;
1761}
1762
23297044 1763static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1764 uint8_t bytes_per_pixel)
1765{
1766 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1767}
1768
2ac96d2a
PB		 1769struct skl_pipe_wm_parameters {
1770 bool active;
1771 uint32_t pipe_htotal;
1772 uint32_t pixel_rate; /* in KHz */
1773 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1774 struct intel_plane_wm_parameters cursor;
1775};
1776
820c1980 1777struct ilk_pipe_wm_parameters {
801bcfff 1778 bool active;
801bcfff
PZ		 1779 uint32_t pipe_htotal;
1780 uint32_t pixel_rate;
c35426d2
VS		 1781 struct intel_plane_wm_parameters pri;
1782 struct intel_plane_wm_parameters spr;
1783 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1784};
1785
820c1980 1786struct ilk_wm_maximums {
cca32e9a
PZ		 1787 uint16_t pri;
1788 uint16_t spr;
1789 uint16_t cur;
1790 uint16_t fbc;
1791};
1792
240264f4
VS		 1793/* used in computing the new watermarks state */
1794struct intel_wm_config {
1795 unsigned int num_pipes_active;
1796 bool sprites_enabled;
1797 bool sprites_scaled;
240264f4
VS		 1798};
1799
37126462
VS		 1800/*
1801 * For both WM_PIPE and WM_LP.
1802 * mem_value must be in 0.1us units.
1803 */
820c1980 1804static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1805 uint32_t mem_value,
1806 bool is_lp)
801bcfff 1807{
cca32e9a
PZ		 1808 uint32_t method1, method2;
1809
c35426d2 1810 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1811 return 0;
1812
23297044 1813 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1814 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1815 mem_value);
1816
1817 if (!is_lp)
1818 return method1;
1819
23297044 1820 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1821 params->pipe_htotal,
c35426d2
VS		 1822 params->pri.horiz_pixels,
1823 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1824 mem_value);
1825
1826 return min(method1, method2);
801bcfff
PZ		 1827}
1828
37126462
VS		 1829/*
1830 * For both WM_PIPE and WM_LP.
1831 * mem_value must be in 0.1us units.
1832 */
820c1980 1833static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1834 uint32_t mem_value)
1835{
1836 uint32_t method1, method2;
1837
c35426d2 1838 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1839 return 0;
1840
23297044 1841 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1842 params->spr.bytes_per_pixel,
801bcfff 1843 mem_value);
23297044 1844 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1845 params->pipe_htotal,
c35426d2
VS		 1846 params->spr.horiz_pixels,
1847 params->spr.bytes_per_pixel,
801bcfff
PZ		 1848 mem_value);
1849 return min(method1, method2);
1850}
1851
37126462
VS		 1852/*
1853 * For both WM_PIPE and WM_LP.
1854 * mem_value must be in 0.1us units.
1855 */
820c1980 1856static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1857 uint32_t mem_value)
1858{
c35426d2 1859 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1860 return 0;
1861
23297044 1862 return ilk_wm_method2(params->pixel_rate,
801bcfff 1863 params->pipe_htotal,
c35426d2
VS		 1864 params->cur.horiz_pixels,
1865 params->cur.bytes_per_pixel,
801bcfff
PZ		 1866 mem_value);
1867}
1868
cca32e9a 1869/* Only for WM_LP. */
820c1980 1870static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1871 uint32_t pri_val)
cca32e9a 1872{
c35426d2 1873 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1874 return 0;
1875
23297044 1876 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1877 params->pri.horiz_pixels,
1878 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1879}
1880
158ae64f
VS		 1881static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1882{
416f4727
VS		 1883 if (INTEL_INFO(dev)->gen >= 8)
1884 return 3072;
1885 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1886 return 768;
1887 else
1888 return 512;
1889}
1890
4e975081
VS		 1891static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1892 int level, bool is_sprite)
1893{
1894 if (INTEL_INFO(dev)->gen >= 8)
1895 /* BDW primary/sprite plane watermarks */
1896 return level == 0 ? 255 : 2047;
1897 else if (INTEL_INFO(dev)->gen >= 7)
1898 /* IVB/HSW primary/sprite plane watermarks */
1899 return level == 0 ? 127 : 1023;
1900 else if (!is_sprite)
1901 /* ILK/SNB primary plane watermarks */
1902 return level == 0 ? 127 : 511;
1903 else
1904 /* ILK/SNB sprite plane watermarks */
1905 return level == 0 ? 63 : 255;
1906}
1907
1908static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1909 int level)
1910{
1911 if (INTEL_INFO(dev)->gen >= 7)
1912 return level == 0 ? 63 : 255;
1913 else
1914 return level == 0 ? 31 : 63;
1915}
1916
1917static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1918{
1919 if (INTEL_INFO(dev)->gen >= 8)
1920 return 31;
1921 else
1922 return 15;
1923}
1924
158ae64f
VS		 1925/* Calculate the maximum primary/sprite plane watermark */
1926static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1927 int level,
240264f4 1928 const struct intel_wm_config *config,
158ae64f
VS		 1929 enum intel_ddb_partitioning ddb_partitioning,
1930 bool is_sprite)
1931{
1932 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1933
1934 /* if sprites aren't enabled, sprites get nothing */
240264f4 1935 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1936 return 0;
1937
1938 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1939 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1940 fifo_size /= INTEL_INFO(dev)->num_pipes;
1941
1942 /*
1943 * For some reason the non self refresh
1944 * FIFO size is only half of the self
1945 * refresh FIFO size on ILK/SNB.
1946 */
1947 if (INTEL_INFO(dev)->gen <= 6)
1948 fifo_size /= 2;
1949 }
1950
240264f4 1951 if (config->sprites_enabled) {
158ae64f
VS		 1952 /* level 0 is always calculated with 1:1 split */
1953 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1954 if (is_sprite)
1955 fifo_size *= 5;
1956 fifo_size /= 6;
1957 } else {
1958 fifo_size /= 2;
1959 }
1960 }
1961
1962 /* clamp to max that the registers can hold */
4e975081 1963 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1964}
1965
1966/* Calculate the maximum cursor plane watermark */
1967static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1968 int level,
1969 const struct intel_wm_config *config)
158ae64f
VS		 1970{
1971 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1972 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1973 return 64;
1974
1975 /* otherwise just report max that registers can hold */
4e975081 1976 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1977}
1978
d34ff9c6 1979static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1980 int level,
1981 const struct intel_wm_config *config,
1982 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1983 struct ilk_wm_maximums *max)
158ae64f 1984{
240264f4
VS		 1985 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1986 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1987 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1988 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1989}
1990
a3cb4048
VS		 1991static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1992 int level,
1993 struct ilk_wm_maximums *max)
1994{
1995 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1996 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1997 max->cur = ilk_cursor_wm_reg_max(dev, level);
1998 max->fbc = ilk_fbc_wm_reg_max(dev);
1999}
2000
d9395655 2001static bool ilk_validate_wm_level(int level,
820c1980 2002 const struct ilk_wm_maximums *max,
d9395655 2003 struct intel_wm_level *result)
a9786a11
VS		 2004{
2005 bool ret;
2006
2007 /* already determined to be invalid? */
2008 if (!result->enable)
2009 return false;
2010
2011 result->enable = result->pri_val <= max->pri &&
2012 result->spr_val <= max->spr &&
2013 result->cur_val <= max->cur;
2014
2015 ret = result->enable;
2016
2017 /*
2018 * HACK until we can pre-compute everything,
2019 * and thus fail gracefully if LP0 watermarks
2020 * are exceeded...
2021 */
2022 if (level == 0 && !result->enable) {
2023 if (result->pri_val > max->pri)
2024 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2025 level, result->pri_val, max->pri);
2026 if (result->spr_val > max->spr)
2027 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2028 level, result->spr_val, max->spr);
2029 if (result->cur_val > max->cur)
2030 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2031 level, result->cur_val, max->cur);
2032
2033 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2034 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2035 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2036 result->enable = true;
2037 }
2038
a9786a11
VS		 2039 return ret;
2040}
2041
d34ff9c6 2042static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2043 int level,
820c1980 2044 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2045 struct intel_wm_level *result)
6f5ddd17
VS		 2046{
2047 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2048 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2049 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2050
2051 /* WM1+ latency values stored in 0.5us units */
2052 if (level > 0) {
2053 pri_latency *= 5;
2054 spr_latency *= 5;
2055 cur_latency *= 5;
2056 }
2057
2058 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2059 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2060 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2061 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2062 result->enable = true;
2063}
2064
801bcfff
PZ		 2065static uint32_t
2066hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2067{
2068 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 2070 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2071 u32 linetime, ips_linetime;
1f8eeabf 2072
3ef00284 2073 if (!intel_crtc->active)
801bcfff 2074 return 0;
1011d8c4 2075
1f8eeabf
ED		 2076 /* The WM are computed with base on how long it takes to fill a single
2077 * row at the given clock rate, multiplied by 8.
2078 * */
fec8cba3
JB		 2079 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2080 mode->crtc_clock);
2081 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
05024da3 2082 dev_priv->cdclk_freq);
1f8eeabf 2083
801bcfff
PZ		 2084 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2085 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2086}
2087
2af30a5c 2088static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2089{
2090 struct drm_i915_private *dev_priv = dev->dev_private;
2091
2af30a5c
PB		 2092 if (IS_GEN9(dev)) {
2093 uint32_t val;
4f947386 2094 int ret, i;
367294be 2095 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2096
2097 /* read the first set of memory latencies[0:3] */
2098 val = 0; /* data0 to be programmed to 0 for first set */
2099 mutex_lock(&dev_priv->rps.hw_lock);
2100 ret = sandybridge_pcode_read(dev_priv,
2101 GEN9_PCODE_READ_MEM_LATENCY,
2102 &val);
2103 mutex_unlock(&dev_priv->rps.hw_lock);
2104
2105 if (ret) {
2106 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2107 return;
2108 }
2109
2110 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2111 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2112 GEN9_MEM_LATENCY_LEVEL_MASK;
2113 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2114 GEN9_MEM_LATENCY_LEVEL_MASK;
2115 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2116 GEN9_MEM_LATENCY_LEVEL_MASK;
2117
2118 /* read the second set of memory latencies[4:7] */
2119 val = 1; /* data0 to be programmed to 1 for second set */
2120 mutex_lock(&dev_priv->rps.hw_lock);
2121 ret = sandybridge_pcode_read(dev_priv,
2122 GEN9_PCODE_READ_MEM_LATENCY,
2123 &val);
2124 mutex_unlock(&dev_priv->rps.hw_lock);
2125 if (ret) {
2126 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2127 return;
2128 }
2129
2130 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2131 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2132 GEN9_MEM_LATENCY_LEVEL_MASK;
2133 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2134 GEN9_MEM_LATENCY_LEVEL_MASK;
2135 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2136 GEN9_MEM_LATENCY_LEVEL_MASK;
2137
367294be 2138 /*
6f97235b
DL		 2139 * WaWmMemoryReadLatency:skl
2140 *
367294be
VK		 2141 * punit doesn't take into account the read latency so we need
2142 * to add 2us to the various latency levels we retrieve from
2143 * the punit.
2144 * - W0 is a bit special in that it's the only level that
2145 * can't be disabled if we want to have display working, so
2146 * we always add 2us there.
2147 * - For levels >=1, punit returns 0us latency when they are
2148 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2149 *
2150 * Additionally, if a level n (n > 1) has a 0us latency, all
2151 * levels m (m >= n) need to be disabled. We make sure to
2152 * sanitize the values out of the punit to satisfy this
2153 * requirement.
367294be
VK		 2154 */
2155 wm[0] += 2;
2156 for (level = 1; level <= max_level; level++)
2157 if (wm[level] != 0)
2158 wm[level] += 2;
4f947386
VK		 2159 else {
2160 for (i = level + 1; i <= max_level; i++)
2161 wm[i] = 0;
367294be 2162
4f947386
VK		 2163 break;
2164 }
2af30a5c 2165 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2166 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2167
2168 wm[0] = (sskpd >> 56) & 0xFF;
2169 if (wm[0] == 0)
2170 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2171 wm[1] = (sskpd >> 4) & 0xFF;
2172 wm[2] = (sskpd >> 12) & 0xFF;
2173 wm[3] = (sskpd >> 20) & 0x1FF;
2174 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2175 } else if (INTEL_INFO(dev)->gen >= 6) {
2176 uint32_t sskpd = I915_READ(MCH_SSKPD);
2177
2178 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2179 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2180 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2181 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2182 } else if (INTEL_INFO(dev)->gen >= 5) {
2183 uint32_t mltr = I915_READ(MLTR_ILK);
2184
2185 /* ILK primary LP0 latency is 700 ns */
2186 wm[0] = 7;
2187 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2188 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2189 }
2190}
2191
53615a5e
VS		 2192static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194 /* ILK sprite LP0 latency is 1300 ns */
2195 if (INTEL_INFO(dev)->gen == 5)
2196 wm[0] = 13;
2197}
2198
2199static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2200{
2201 /* ILK cursor LP0 latency is 1300 ns */
2202 if (INTEL_INFO(dev)->gen == 5)
2203 wm[0] = 13;
2204
2205 /* WaDoubleCursorLP3Latency:ivb */
2206 if (IS_IVYBRIDGE(dev))
2207 wm[3] *= 2;
2208}
2209
546c81fd 2210int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2211{
26ec971e 2212 /* how many WM levels are we expecting */
b6e742f6 2213 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2214 return 7;
2215 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2216 return 4;
26ec971e 2217 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2218 return 3;
26ec971e 2219 else
ad0d6dc4
VS		 2220 return 2;
2221}
7526ed79 2222
ad0d6dc4
VS		 2223static void intel_print_wm_latency(struct drm_device *dev,
2224 const char *name,
2af30a5c 2225 const uint16_t wm[8])
ad0d6dc4
VS		 2226{
2227 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2228
2229 for (level = 0; level <= max_level; level++) {
2230 unsigned int latency = wm[level];
2231
2232 if (latency == 0) {
2233 DRM_ERROR("%s WM%d latency not provided\n",
2234 name, level);
2235 continue;
2236 }
2237
2af30a5c
PB		 2238 /*
2239 * - latencies are in us on gen9.
2240 * - before then, WM1+ latency values are in 0.5us units
2241 */
2242 if (IS_GEN9(dev))
2243 latency *= 10;
2244 else if (level > 0)
26ec971e
VS		 2245 latency *= 5;
2246
2247 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2248 name, level, wm[level],
2249 latency / 10, latency % 10);
2250 }
2251}
2252
e95a2f75
VS		 2253static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2254 uint16_t wm[5], uint16_t min)
2255{
2256 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2257
2258 if (wm[0] >= min)
2259 return false;
2260
2261 wm[0] = max(wm[0], min);
2262 for (level = 1; level <= max_level; level++)
2263 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2264
2265 return true;
2266}
2267
2268static void snb_wm_latency_quirk(struct drm_device *dev)
2269{
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 bool changed;
2272
2273 /*
2274 * The BIOS provided WM memory latency values are often
2275 * inadequate for high resolution displays. Adjust them.
2276 */
2277 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2278 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2279 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2280
2281 if (!changed)
2282 return;
2283
2284 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2285 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2286 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2287 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2288}
2289
fa50ad61 2290static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2291{
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2293
2294 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2295
2296 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2297 sizeof(dev_priv->wm.pri_latency));
2298 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2299 sizeof(dev_priv->wm.pri_latency));
2300
2301 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2302 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2303
2304 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2305 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2306 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2307
2308 if (IS_GEN6(dev))
2309 snb_wm_latency_quirk(dev);
53615a5e
VS		 2310}
2311
2af30a5c
PB		 2312static void skl_setup_wm_latency(struct drm_device *dev)
2313{
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315
2316 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2317 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2318}
2319
820c1980 2320static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2321 struct ilk_pipe_wm_parameters *p)
1011d8c4 2322{
7c4a395f
VS		 2323 struct drm_device *dev = crtc->dev;
2324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2325 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2326 struct drm_plane *plane;
1011d8c4 2327
3ef00284 2328 if (!intel_crtc->active)
2a44b76b 2329 return;
801bcfff 2330
2a44b76b 2331 p->active = true;
6e3c9717 2332 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2333 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2334
54da691d 2335 if (crtc->primary->state->fb)
c9f038a1
MR		 2336 p->pri.bytes_per_pixel =
2337 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG		 2338 else
2339 p->pri.bytes_per_pixel = 4;
2340
2341 p->cur.bytes_per_pixel = 4;
2342 /*
2343 * TODO: for now, assume primary and cursor planes are always enabled.
2344 * Setting them to false makes the screen flicker.
2345 */
2346 p->pri.enabled = true;
2347 p->cur.enabled = true;
c9f038a1 2348
6e3c9717 2349 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2350 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2351
af2b653b 2352 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2353 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2354
2a44b76b 2355 if (intel_plane->pipe == pipe) {
7c4a395f 2356 p->spr = intel_plane->wm;
2a44b76b
VS		 2357 break;
2358 }
2359 }
2360}
2361
2362static void ilk_compute_wm_config(struct drm_device *dev,
2363 struct intel_wm_config *config)
2364{
2365 struct intel_crtc *intel_crtc;
2366
2367 /* Compute the currently _active_ config */
d3fcc808 2368 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2369 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2370
2a44b76b
VS		 2371 if (!wm->pipe_enabled)
2372 continue;
cca32e9a 2373
2a44b76b
VS		 2374 config->sprites_enabled |= wm->sprites_enabled;
2375 config->sprites_scaled |= wm->sprites_scaled;
2376 config->num_pipes_active++;
cca32e9a 2377 }
801bcfff
PZ		 2378}
2379
0b2ae6d7
VS		 2380/* Compute new watermarks for the pipe */
2381static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2382 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2383 struct intel_pipe_wm *pipe_wm)
2384{
2385 struct drm_device *dev = crtc->dev;
d34ff9c6 2386 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2387 int level, max_level = ilk_wm_max_level(dev);
2388 /* LP0 watermark maximums depend on this pipe alone */
2389 struct intel_wm_config config = {
2390 .num_pipes_active = 1,
2391 .sprites_enabled = params->spr.enabled,
2392 .sprites_scaled = params->spr.scaled,
2393 };
820c1980 2394 struct ilk_wm_maximums max;
0b2ae6d7 2395
2a44b76b
VS		 2396 pipe_wm->pipe_enabled = params->active;
2397 pipe_wm->sprites_enabled = params->spr.enabled;
2398 pipe_wm->sprites_scaled = params->spr.scaled;
2399
7b39a0b7
VS		 2400 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2401 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2402 max_level = 1;
2403
2404 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2405 if (params->spr.scaled)
2406 max_level = 0;
2407
a3cb4048 2408 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2409
a42a5719 2410 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2411 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2412
a3cb4048
VS		 2413 /* LP0 watermarks always use 1/2 DDB partitioning */
2414 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2415
0b2ae6d7 2416 /* At least LP0 must be valid */
a3cb4048
VS		 2417 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2418 return false;
2419
2420 ilk_compute_wm_reg_maximums(dev, 1, &max);
2421
2422 for (level = 1; level <= max_level; level++) {
2423 struct intel_wm_level wm = {};
2424
2425 ilk_compute_wm_level(dev_priv, level, params, &wm);
2426
2427 /*
2428 * Disable any watermark level that exceeds the
2429 * register maximums since such watermarks are
2430 * always invalid.
2431 */
2432 if (!ilk_validate_wm_level(level, &max, &wm))
2433 break;
2434
2435 pipe_wm->wm[level] = wm;
2436 }
2437
2438 return true;
0b2ae6d7
VS		 2439}
2440
2441/*
2442 * Merge the watermarks from all active pipes for a specific level.
2443 */
2444static void ilk_merge_wm_level(struct drm_device *dev,
2445 int level,
2446 struct intel_wm_level *ret_wm)
2447{
2448 const struct intel_crtc *intel_crtc;
2449
d52fea5b
VS		 2450 ret_wm->enable = true;
2451
d3fcc808 2452 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2453 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2454 const struct intel_wm_level *wm = &active->wm[level];
2455
2456 if (!active->pipe_enabled)
2457 continue;
0b2ae6d7 2458
d52fea5b
VS		 2459 /*
2460 * The watermark values may have been used in the past,
2461 * so we must maintain them in the registers for some
2462 * time even if the level is now disabled.
2463 */
0b2ae6d7 2464 if (!wm->enable)
d52fea5b 2465 ret_wm->enable = false;
0b2ae6d7
VS		 2466
2467 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2468 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2469 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2470 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2471 }
0b2ae6d7
VS		 2472}
2473
2474/*
2475 * Merge all low power watermarks for all active pipes.
2476 */
2477static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2478 const struct intel_wm_config *config,
820c1980 2479 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2480 struct intel_pipe_wm *merged)
2481{
7733b49b 2482 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2483 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2484 int last_enabled_level = max_level;
0b2ae6d7 2485
0ba22e26
VS		 2486 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2487 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2488 config->num_pipes_active > 1)
2489 return;
2490
6c8b6c28
VS		 2491 /* ILK: FBC WM must be disabled always */
2492 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2493
2494 /* merge each WM1+ level */
2495 for (level = 1; level <= max_level; level++) {
2496 struct intel_wm_level *wm = &merged->wm[level];
2497
2498 ilk_merge_wm_level(dev, level, wm);
2499
d52fea5b
VS		 2500 if (level > last_enabled_level)
2501 wm->enable = false;
2502 else if (!ilk_validate_wm_level(level, max, wm))
2503 /* make sure all following levels get disabled */
2504 last_enabled_level = level - 1;
0b2ae6d7
VS		 2505
2506 /*
2507 * The spec says it is preferred to disable
2508 * FBC WMs instead of disabling a WM level.
2509 */
2510 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2511 if (wm->enable)
2512 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2513 wm->fbc_val = 0;
2514 }
2515 }
6c8b6c28
VS		 2516
2517 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2518 /*
2519 * FIXME this is racy. FBC might get enabled later.
2520 * What we should check here is whether FBC can be
2521 * enabled sometime later.
2522 */
7733b49b
PZ		 2523 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2524 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2525 for (level = 2; level <= max_level; level++) {
2526 struct intel_wm_level *wm = &merged->wm[level];
2527
2528 wm->enable = false;
2529 }
2530 }
0b2ae6d7
VS		 2531}
2532
b380ca3c
VS		 2533static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2534{
2535 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2536 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2537}
2538
a68d68ee
VS		 2539/* The value we need to program into the WM_LPx latency field */
2540static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2541{
2542 struct drm_i915_private *dev_priv = dev->dev_private;
2543
a42a5719 2544 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2545 return 2 * level;
2546 else
2547 return dev_priv->wm.pri_latency[level];
2548}
2549
820c1980 2550static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2551 const struct intel_pipe_wm *merged,
609cedef 2552 enum intel_ddb_partitioning partitioning,
820c1980 2553 struct ilk_wm_values *results)
801bcfff 2554{
0b2ae6d7
VS		 2555 struct intel_crtc *intel_crtc;
2556 int level, wm_lp;
cca32e9a 2557
0362c781 2558 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2559 results->partitioning = partitioning;
cca32e9a 2560
0b2ae6d7 2561 /* LP1+ register values */
cca32e9a 2562 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2563 const struct intel_wm_level *r;
801bcfff 2564
b380ca3c 2565 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2566
0362c781 2567 r = &merged->wm[level];
cca32e9a 2568
d52fea5b
VS		 2569 /*
2570 * Maintain the watermark values even if the level is
2571 * disabled. Doing otherwise could cause underruns.
2572 */
2573 results->wm_lp[wm_lp - 1] =
a68d68ee 2574 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2575 (r->pri_val << WM1_LP_SR_SHIFT) |
2576 r->cur_val;
2577
d52fea5b
VS		 2578 if (r->enable)
2579 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2580
416f4727
VS		 2581 if (INTEL_INFO(dev)->gen >= 8)
2582 results->wm_lp[wm_lp - 1] |=
2583 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2584 else
2585 results->wm_lp[wm_lp - 1] |=
2586 r->fbc_val << WM1_LP_FBC_SHIFT;
2587
d52fea5b
VS		 2588 /*
2589 * Always set WM1S_LP_EN when spr_val != 0, even if the
2590 * level is disabled. Doing otherwise could cause underruns.
2591 */
6cef2b8a
VS		 2592 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2593 WARN_ON(wm_lp != 1);
2594 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2595 } else
2596 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2597 }
801bcfff 2598
0b2ae6d7 2599 /* LP0 register values */
d3fcc808 2600 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2601 enum pipe pipe = intel_crtc->pipe;
2602 const struct intel_wm_level *r =
2603 &intel_crtc->wm.active.wm[0];
2604
2605 if (WARN_ON(!r->enable))
2606 continue;
2607
2608 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2609
0b2ae6d7
VS		 2610 results->wm_pipe[pipe] =
2611 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2612 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2613 r->cur_val;
801bcfff
PZ		 2614 }
2615}
2616
861f3389
PZ		 2617/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2618 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2619static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2620 struct intel_pipe_wm *r1,
2621 struct intel_pipe_wm *r2)
861f3389 2622{
198a1e9b
VS		 2623 int level, max_level = ilk_wm_max_level(dev);
2624 int level1 = 0, level2 = 0;
861f3389 2625
198a1e9b
VS		 2626 for (level = 1; level <= max_level; level++) {
2627 if (r1->wm[level].enable)
2628 level1 = level;
2629 if (r2->wm[level].enable)
2630 level2 = level;
861f3389
PZ		 2631 }
2632
198a1e9b
VS		 2633 if (level1 == level2) {
2634 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2635 return r2;
2636 else
2637 return r1;
198a1e9b 2638 } else if (level1 > level2) {
861f3389
PZ		 2639 return r1;
2640 } else {
2641 return r2;
2642 }
2643}
2644
49a687c4
VS		 2645/* dirty bits used to track which watermarks need changes */
2646#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2647#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2648#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2649#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2650#define WM_DIRTY_FBC (1 << 24)
2651#define WM_DIRTY_DDB (1 << 25)
2652
055e393f 2653static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2654 const struct ilk_wm_values *old,
2655 const struct ilk_wm_values *new)
49a687c4
VS		 2656{
2657 unsigned int dirty = 0;
2658 enum pipe pipe;
2659 int wm_lp;
2660
055e393f 2661 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2662 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2663 dirty |= WM_DIRTY_LINETIME(pipe);
2664 /* Must disable LP1+ watermarks too */
2665 dirty |= WM_DIRTY_LP_ALL;
2666 }
2667
2668 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2669 dirty |= WM_DIRTY_PIPE(pipe);
2670 /* Must disable LP1+ watermarks too */
2671 dirty |= WM_DIRTY_LP_ALL;
2672 }
2673 }
2674
2675 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2676 dirty |= WM_DIRTY_FBC;
2677 /* Must disable LP1+ watermarks too */
2678 dirty |= WM_DIRTY_LP_ALL;
2679 }
2680
2681 if (old->partitioning != new->partitioning) {
2682 dirty |= WM_DIRTY_DDB;
2683 /* Must disable LP1+ watermarks too */
2684 dirty |= WM_DIRTY_LP_ALL;
2685 }
2686
2687 /* LP1+ watermarks already deemed dirty, no need to continue */
2688 if (dirty & WM_DIRTY_LP_ALL)
2689 return dirty;
2690
2691 /* Find the lowest numbered LP1+ watermark in need of an update... */
2692 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2693 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2694 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2695 break;
2696 }
2697
2698 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2699 for (; wm_lp <= 3; wm_lp++)
2700 dirty |= WM_DIRTY_LP(wm_lp);
2701
2702 return dirty;
2703}
2704
8553c18e
VS		 2705static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2706 unsigned int dirty)
801bcfff 2707{
820c1980 2708 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2709 bool changed = false;
801bcfff 2710
facd619b
VS		 2711 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2712 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2713 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2714 changed = true;
facd619b
VS		 2715 }
2716 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2717 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2718 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2719 changed = true;
facd619b
VS		 2720 }
2721 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2722 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2723 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2724 changed = true;
facd619b 2725 }
801bcfff 2726
facd619b
VS		 2727 /*
2728 * Don't touch WM1S_LP_EN here.
2729 * Doing so could cause underruns.
2730 */
6cef2b8a 2731
8553c18e
VS		 2732 return changed;
2733}
2734
2735/*
2736 * The spec says we shouldn't write when we don't need, because every write
2737 * causes WMs to be re-evaluated, expending some power.
2738 */
820c1980
ID		 2739static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2740 struct ilk_wm_values *results)
8553c18e
VS		 2741{
2742 struct drm_device *dev = dev_priv->dev;
820c1980 2743 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2744 unsigned int dirty;
2745 uint32_t val;
2746
055e393f 2747 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2748 if (!dirty)
2749 return;
2750
2751 _ilk_disable_lp_wm(dev_priv, dirty);
2752
49a687c4 2753 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2754 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2755 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2756 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2757 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2758 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2759
49a687c4 2760 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2761 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2762 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2763 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2764 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2765 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2766
49a687c4 2767 if (dirty & WM_DIRTY_DDB) {
a42a5719 2768 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2769 val = I915_READ(WM_MISC);
2770 if (results->partitioning == INTEL_DDB_PART_1_2)
2771 val &= ~WM_MISC_DATA_PARTITION_5_6;
2772 else
2773 val |= WM_MISC_DATA_PARTITION_5_6;
2774 I915_WRITE(WM_MISC, val);
2775 } else {
2776 val = I915_READ(DISP_ARB_CTL2);
2777 if (results->partitioning == INTEL_DDB_PART_1_2)
2778 val &= ~DISP_DATA_PARTITION_5_6;
2779 else
2780 val |= DISP_DATA_PARTITION_5_6;
2781 I915_WRITE(DISP_ARB_CTL2, val);
2782 }
1011d8c4
PZ		 2783 }
2784
49a687c4 2785 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2786 val = I915_READ(DISP_ARB_CTL);
2787 if (results->enable_fbc_wm)
2788 val &= ~DISP_FBC_WM_DIS;
2789 else
2790 val |= DISP_FBC_WM_DIS;
2791 I915_WRITE(DISP_ARB_CTL, val);
2792 }
2793
954911eb
ID		 2794 if (dirty & WM_DIRTY_LP(1) &&
2795 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2796 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2797
2798 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2799 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2800 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2801 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2802 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2803 }
801bcfff 2804
facd619b 2805 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2806 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2807 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2808 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2809 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2810 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2811
2812 dev_priv->wm.hw = *results;
801bcfff
PZ		 2813}
2814
8553c18e
VS		 2815static bool ilk_disable_lp_wm(struct drm_device *dev)
2816{
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818
2819 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2820}
2821
b9cec075
DL		 2822/*
2823 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2824 * different active planes.
2825 */
2826
2827#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2828#define BXT_DDB_SIZE 512
b9cec075
DL		 2829
2830static void
2831skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2832 struct drm_crtc *for_crtc,
2833 const struct intel_wm_config *config,
2834 const struct skl_pipe_wm_parameters *params,
2835 struct skl_ddb_entry *alloc /* out */)
2836{
2837 struct drm_crtc *crtc;
2838 unsigned int pipe_size, ddb_size;
2839 int nth_active_pipe;
2840
2841 if (!params->active) {
2842 alloc->start = 0;
2843 alloc->end = 0;
2844 return;
2845 }
2846
43d735a6
DL		 2847 if (IS_BROXTON(dev))
2848 ddb_size = BXT_DDB_SIZE;
2849 else
2850 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2851
2852 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2853
2854 nth_active_pipe = 0;
2855 for_each_crtc(dev, crtc) {
3ef00284 2856 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2857 continue;
2858
2859 if (crtc == for_crtc)
2860 break;
2861
2862 nth_active_pipe++;
2863 }
2864
2865 pipe_size = ddb_size / config->num_pipes_active;
2866 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2867 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2868}
2869
2870static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2871{
2872 if (config->num_pipes_active == 1)
2873 return 32;
2874
2875 return 8;
2876}
2877
a269c583
DL		 2878static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2879{
2880 entry->start = reg & 0x3ff;
2881 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2882 if (entry->end)
2883 entry->end += 1;
a269c583
DL		 2884}
2885
08db6652
DL		 2886void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2887 struct skl_ddb_allocation *ddb /* out */)
a269c583 2888{
a269c583
DL		 2889 enum pipe pipe;
2890 int plane;
2891 u32 val;
2892
2893 for_each_pipe(dev_priv, pipe) {
dd740780 2894 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2895 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2896 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2897 val);
2898 }
2899
2900 val = I915_READ(CUR_BUF_CFG(pipe));
2901 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2902 }
2903}
2904
b9cec075 2905static unsigned int
2cd601c6 2906skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2907{
2cd601c6
CK		 2908
2909 /* for planar format */
2910 if (p->y_bytes_per_pixel) {
2911 if (y) /* y-plane data rate */
2912 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2913 else /* uv-plane data rate */
2914 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2915 }
2916
2917 /* for packed formats */
b9cec075
DL		 2918 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2919}
2920
2921/*
2922 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2923 * a 8192x4096@32bpp framebuffer:
2924 * 3 * 4096 * 8192 * 4 < 2^32
2925 */
2926static unsigned int
2927skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2928 const struct skl_pipe_wm_parameters *params)
2929{
2930 unsigned int total_data_rate = 0;
2931 int plane;
2932
2933 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2934 const struct intel_plane_wm_parameters *p;
2935
2936 p = &params->plane[plane];
2937 if (!p->enabled)
2938 continue;
2939
2cd601c6
CK		 2940 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2941 if (p->y_bytes_per_pixel) {
2942 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2943 }
b9cec075
DL		 2944 }
2945
2946 return total_data_rate;
2947}
2948
2949static void
2950skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2951 const struct intel_wm_config *config,
2952 const struct skl_pipe_wm_parameters *params,
2953 struct skl_ddb_allocation *ddb /* out */)
2954{
2955 struct drm_device *dev = crtc->dev;
dd740780 2956 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2958 enum pipe pipe = intel_crtc->pipe;
34bb56af 2959 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2960 uint16_t alloc_size, start, cursor_blocks;
80958155 2961 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2962 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2963 unsigned int total_data_rate;
2964 int plane;
2965
34bb56af
DL		 2966 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2967 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2968 if (alloc_size == 0) {
2969 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2970 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2971 return;
2972 }
2973
2974 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2975 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2976 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2977
2978 alloc_size -= cursor_blocks;
34bb56af 2979 alloc->end -= cursor_blocks;
b9cec075 2980
80958155 2981 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2982 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2983 const struct intel_plane_wm_parameters *p;
2984
2985 p = &params->plane[plane];
2986 if (!p->enabled)
2987 continue;
2988
2989 minimum[plane] = 8;
2990 alloc_size -= minimum[plane];
2cd601c6
CK		 2991 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2992 alloc_size -= y_minimum[plane];
80958155
DL		 2993 }
2994
b9cec075 2995 /*
80958155
DL		 2996 * 2. Distribute the remaining space in proportion to the amount of
2997 * data each plane needs to fetch from memory.
b9cec075
DL		 2998 *
2999 * FIXME: we may not allocate every single block here.
3000 */
3001 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3002
34bb56af 3003 start = alloc->start;
b9cec075
DL		 3004 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3005 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 3006 unsigned int data_rate, y_data_rate;
3007 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 3008
3009 p = &params->plane[plane];
3010 if (!p->enabled)
3011 continue;
3012
2cd601c6 3013 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 3014
3015 /*
2cd601c6 3016 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3017 * promote the expression to 64 bits to avoid overflowing, the
3018 * result is < available as data_rate / total_data_rate < 1
3019 */
80958155
DL		 3020 plane_blocks = minimum[plane];
3021 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3022 total_data_rate);
b9cec075
DL		 3023
3024 ddb->plane[pipe][plane].start = start;
16160e3d 3025 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3026
3027 start += plane_blocks;
2cd601c6
CK		 3028
3029 /*
3030 * allocation for y_plane part of planar format:
3031 */
3032 if (p->y_bytes_per_pixel) {
3033 y_data_rate = skl_plane_relative_data_rate(p, 1);
3034 y_plane_blocks = y_minimum[plane];
3035 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3036 total_data_rate);
3037
3038 ddb->y_plane[pipe][plane].start = start;
3039 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3040
3041 start += y_plane_blocks;
3042 }
3043
b9cec075
DL		 3044 }
3045
3046}
3047
5cec258b 3048static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3049{
3050 /* TODO: Take into account the scalers once we support them */
2d112de7 3051 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3052}
3053
3054/*
3055 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3056 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3057 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3058 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3059*/
3060static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3061 uint32_t latency)
3062{
3063 uint32_t wm_intermediate_val, ret;
3064
3065 if (latency == 0)
3066 return UINT_MAX;
3067
d4c2aa60 3068 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3069 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3070
3071 return ret;
3072}
3073
3074static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3075 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3076 uint64_t tiling, uint32_t latency)
2d41c0b5 3077{
d4c2aa60
TU		 3078 uint32_t ret;
3079 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3080 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3081
3082 if (latency == 0)
3083 return UINT_MAX;
3084
3085 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3086
3087 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3088 tiling == I915_FORMAT_MOD_Yf_TILED) {
3089 plane_bytes_per_line *= 4;
3090 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3091 plane_blocks_per_line /= 4;
3092 } else {
3093 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3094 }
3095
2d41c0b5
PB		 3096 wm_intermediate_val = latency * pixel_rate;
3097 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3098 plane_blocks_per_line;
2d41c0b5
PB		 3099
3100 return ret;
3101}
3102
2d41c0b5
PB		 3103static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3104 const struct intel_crtc *intel_crtc)
3105{
3106 struct drm_device *dev = intel_crtc->base.dev;
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3109 enum pipe pipe = intel_crtc->pipe;
3110
3111 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3112 sizeof(new_ddb->plane[pipe])))
3113 return true;
3114
3115 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3116 sizeof(new_ddb->cursor[pipe])))
3117 return true;
3118
3119 return false;
3120}
3121
3122static void skl_compute_wm_global_parameters(struct drm_device *dev,
3123 struct intel_wm_config *config)
3124{
3125 struct drm_crtc *crtc;
3126 struct drm_plane *plane;
3127
3128 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 3129 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 3130
3131 /* FIXME: I don't think we need those two global parameters on SKL */
3132 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3133 struct intel_plane *intel_plane = to_intel_plane(plane);
3134
3135 config->sprites_enabled |= intel_plane->wm.enabled;
3136 config->sprites_scaled |= intel_plane->wm.scaled;
3137 }
3138}
3139
3140static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3141 struct skl_pipe_wm_parameters *p)
3142{
3143 struct drm_device *dev = crtc->dev;
3144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3145 enum pipe pipe = intel_crtc->pipe;
3146 struct drm_plane *plane;
0fda6568 3147 struct drm_framebuffer *fb;
2d41c0b5
PB		 3148 int i = 1; /* Index for sprite planes start */
3149
3ef00284 3150 p->active = intel_crtc->active;
2d41c0b5 3151 if (p->active) {
6e3c9717
ACO		 3152 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3153 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 3154
0fda6568 3155 fb = crtc->primary->state->fb;
2cd601c6 3156 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 3157 if (fb) {
3158 p->plane[0].enabled = true;
2cd601c6
CK		 3159 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3160 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
3161 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3162 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 3163 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 3164 } else {
3165 p->plane[0].enabled = false;
3166 p->plane[0].bytes_per_pixel = 0;
2cd601c6 3167 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 3168 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3169 }
3170 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3171 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 3172 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 3173
c9f038a1 3174 fb = crtc->cursor->state->fb;
2cd601c6 3175 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 3176 if (fb) {
3177 p->cursor.enabled = true;
3178 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3179 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3180 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3181 } else {
3182 p->cursor.enabled = false;
3183 p->cursor.bytes_per_pixel = 0;
3184 p->cursor.horiz_pixels = 64;
3185 p->cursor.vert_pixels = 64;
3186 }
2d41c0b5
PB		 3187 }
3188
3189 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3190 struct intel_plane *intel_plane = to_intel_plane(plane);
3191
a712f8eb
SJ		 3192 if (intel_plane->pipe == pipe &&
3193 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 3194 p->plane[i++] = intel_plane->wm;
3195 }
3196}
3197
d4c2aa60
TU		 3198static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3199 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 3200 struct intel_plane_wm_parameters *p_params,
3201 uint16_t ddb_allocation,
d4c2aa60 3202 int level,
afb024aa
DL		 3203 uint16_t *out_blocks, /* out */
3204 uint8_t *out_lines /* out */)
2d41c0b5 3205{
d4c2aa60
TU		 3206 uint32_t latency = dev_priv->wm.skl_latency[level];
3207 uint32_t method1, method2;
3208 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3209 uint32_t res_blocks, res_lines;
3210 uint32_t selected_result;
2cd601c6 3211 uint8_t bytes_per_pixel;
2d41c0b5 3212
d4c2aa60 3213 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3214 return false;
3215
2cd601c6
CK		 3216 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3217 p_params->y_bytes_per_pixel :
3218 p_params->bytes_per_pixel;
2d41c0b5 3219 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 3220 bytes_per_pixel,
d4c2aa60 3221 latency);
2d41c0b5
PB		 3222 method2 = skl_wm_method2(p->pixel_rate,
3223 p->pipe_htotal,
3224 p_params->horiz_pixels,
2cd601c6 3225 bytes_per_pixel,
0fda6568 3226 p_params->tiling,
d4c2aa60 3227 latency);
2d41c0b5 3228
2cd601c6 3229 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 3230 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3231
0fda6568
TU		 3232 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3233 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3234 uint32_t min_scanlines = 4;
3235 uint32_t y_tile_minimum;
3236 if (intel_rotation_90_or_270(p_params->rotation)) {
3237 switch (p_params->bytes_per_pixel) {
3238 case 1:
3239 min_scanlines = 16;
3240 break;
3241 case 2:
3242 min_scanlines = 8;
3243 break;
3244 case 8:
3245 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3246 }
1fc0a8f7
TU		 3247 }
3248 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3249 selected_result = max(method2, y_tile_minimum);
3250 } else {
3251 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3252 selected_result = min(method1, method2);
3253 else
3254 selected_result = method1;
3255 }
2d41c0b5 3256
d4c2aa60
TU		 3257 res_blocks = selected_result + 1;
3258 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3259
0fda6568
TU		 3260 if (level >= 1 && level <= 7) {
3261 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3262 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3263 res_lines += 4;
3264 else
3265 res_blocks++;
3266 }
e6d66171 3267
d4c2aa60 3268 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3269 return false;
3270
3271 *out_blocks = res_blocks;
3272 *out_lines = res_lines;
2d41c0b5
PB		 3273
3274 return true;
3275}
3276
3277static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3278 struct skl_ddb_allocation *ddb,
3279 struct skl_pipe_wm_parameters *p,
3280 enum pipe pipe,
3281 int level,
3282 int num_planes,
3283 struct skl_wm_level *result)
3284{
2d41c0b5
PB		 3285 uint16_t ddb_blocks;
3286 int i;
3287
3288 for (i = 0; i < num_planes; i++) {
3289 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3290
d4c2aa60
TU		 3291 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3292 p, &p->plane[i],
2d41c0b5 3293 ddb_blocks,
d4c2aa60 3294 level,
2d41c0b5
PB		 3295 &result->plane_res_b[i],
3296 &result->plane_res_l[i]);
3297 }
3298
3299 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3300 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3301 ddb_blocks, level,
3302 &result->cursor_res_b,
2d41c0b5
PB		 3303 &result->cursor_res_l);
3304}
3305
407b50f3
DL		 3306static uint32_t
3307skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3308{
3ef00284 3309 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3310 return 0;
3311
3312 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3313
3314}
3315
3316static void skl_compute_transition_wm(struct drm_crtc *crtc,
3317 struct skl_pipe_wm_parameters *params,
9414f563 3318 struct skl_wm_level *trans_wm /* out */)
407b50f3 3319{
9414f563
DL		 3320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3321 int i;
3322
407b50f3
DL		 3323 if (!params->active)
3324 return;
9414f563
DL		 3325
3326 /* Until we know more, just disable transition WMs */
3327 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3328 trans_wm->plane_en[i] = false;
3329 trans_wm->cursor_en = false;
407b50f3
DL		 3330}
3331
2d41c0b5
PB		 3332static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3333 struct skl_ddb_allocation *ddb,
3334 struct skl_pipe_wm_parameters *params,
3335 struct skl_pipe_wm *pipe_wm)
3336{
3337 struct drm_device *dev = crtc->dev;
3338 const struct drm_i915_private *dev_priv = dev->dev_private;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 int level, max_level = ilk_wm_max_level(dev);
3341
3342 for (level = 0; level <= max_level; level++) {
3343 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3344 level, intel_num_planes(intel_crtc),
3345 &pipe_wm->wm[level]);
3346 }
3347 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3348
9414f563 3349 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3350}
3351
3352static void skl_compute_wm_results(struct drm_device *dev,
3353 struct skl_pipe_wm_parameters *p,
3354 struct skl_pipe_wm *p_wm,
3355 struct skl_wm_values *r,
3356 struct intel_crtc *intel_crtc)
3357{
3358 int level, max_level = ilk_wm_max_level(dev);
3359 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3360 uint32_t temp;
3361 int i;
2d41c0b5
PB		 3362
3363 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3364 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3365 temp = 0;
2d41c0b5
PB		 3366
3367 temp |= p_wm->wm[level].plane_res_l[i] <<
3368 PLANE_WM_LINES_SHIFT;
3369 temp |= p_wm->wm[level].plane_res_b[i];
3370 if (p_wm->wm[level].plane_en[i])
3371 temp |= PLANE_WM_EN;
3372
3373 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3374 }
3375
3376 temp = 0;
2d41c0b5
PB		 3377
3378 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3379 temp |= p_wm->wm[level].cursor_res_b;
3380
3381 if (p_wm->wm[level].cursor_en)
3382 temp |= PLANE_WM_EN;
3383
3384 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3385
3386 }
3387
9414f563
DL		 3388 /* transition WMs */
3389 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3390 temp = 0;
3391 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3392 temp |= p_wm->trans_wm.plane_res_b[i];
3393 if (p_wm->trans_wm.plane_en[i])
3394 temp |= PLANE_WM_EN;
3395
3396 r->plane_trans[pipe][i] = temp;
3397 }
3398
3399 temp = 0;
3400 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3401 temp |= p_wm->trans_wm.cursor_res_b;
3402 if (p_wm->trans_wm.cursor_en)
3403 temp |= PLANE_WM_EN;
3404
3405 r->cursor_trans[pipe] = temp;
3406
2d41c0b5
PB		 3407 r->wm_linetime[pipe] = p_wm->linetime;
3408}
3409
16160e3d
DL		 3410static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3411 const struct skl_ddb_entry *entry)
3412{
3413 if (entry->end)
3414 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3415 else
3416 I915_WRITE(reg, 0);
3417}
3418
2d41c0b5
PB		 3419static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3420 const struct skl_wm_values *new)
3421{
3422 struct drm_device *dev = dev_priv->dev;
3423 struct intel_crtc *crtc;
3424
3425 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3426 int i, level, max_level = ilk_wm_max_level(dev);
3427 enum pipe pipe = crtc->pipe;
3428
5d374d96
DL		 3429 if (!new->dirty[pipe])
3430 continue;
8211bd5b 3431
5d374d96 3432 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3433
5d374d96
DL		 3434 for (level = 0; level <= max_level; level++) {
3435 for (i = 0; i < intel_num_planes(crtc); i++)
3436 I915_WRITE(PLANE_WM(pipe, i, level),
3437 new->plane[pipe][i][level]);
3438 I915_WRITE(CUR_WM(pipe, level),
3439 new->cursor[pipe][level]);
2d41c0b5 3440 }
5d374d96
DL		 3441 for (i = 0; i < intel_num_planes(crtc); i++)
3442 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3443 new->plane_trans[pipe][i]);
3444 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3445
2cd601c6 3446 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3447 skl_ddb_entry_write(dev_priv,
3448 PLANE_BUF_CFG(pipe, i),
3449 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3450 skl_ddb_entry_write(dev_priv,
3451 PLANE_NV12_BUF_CFG(pipe, i),
3452 &new->ddb.y_plane[pipe][i]);
3453 }
5d374d96
DL		 3454
3455 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3456 &new->ddb.cursor[pipe]);
2d41c0b5 3457 }
2d41c0b5
PB		 3458}
3459
0e8fb7ba
DL		 3460/*
3461 * When setting up a new DDB allocation arrangement, we need to correctly
3462 * sequence the times at which the new allocations for the pipes are taken into
3463 * account or we'll have pipes fetching from space previously allocated to
3464 * another pipe.
3465 *
3466 * Roughly the sequence looks like:
3467 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3468 * overlapping with a previous light-up pipe (another way to put it is:
3469 * pipes with their new allocation strickly included into their old ones).
3470 * 2. re-allocate the other pipes that get their allocation reduced
3471 * 3. allocate the pipes having their allocation increased
3472 *
3473 * Steps 1. and 2. are here to take care of the following case:
3474 * - Initially DDB looks like this:
3475 * | B | C |
3476 * - enable pipe A.
3477 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3478 * allocation
3479 * | A | B | C |
3480 *
3481 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3482 */
3483
d21b795c
DL		 3484static void
3485skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3486{
0e8fb7ba
DL		 3487 int plane;
3488
d21b795c
DL		 3489 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3490
dd740780 3491 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3492 I915_WRITE(PLANE_SURF(pipe, plane),
3493 I915_READ(PLANE_SURF(pipe, plane)));
3494 }
3495 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3496}
3497
3498static bool
3499skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3500 const struct skl_ddb_allocation *new,
3501 enum pipe pipe)
3502{
3503 uint16_t old_size, new_size;
3504
3505 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3506 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3507
3508 return old_size != new_size &&
3509 new->pipe[pipe].start >= old->pipe[pipe].start &&
3510 new->pipe[pipe].end <= old->pipe[pipe].end;
3511}
3512
3513static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3514 struct skl_wm_values *new_values)
3515{
3516 struct drm_device *dev = dev_priv->dev;
3517 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3518 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3519 struct intel_crtc *crtc;
3520 enum pipe pipe;
3521
3522 new_ddb = &new_values->ddb;
3523 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3524
3525 /*
3526 * First pass: flush the pipes with the new allocation contained into
3527 * the old space.
3528 *
3529 * We'll wait for the vblank on those pipes to ensure we can safely
3530 * re-allocate the freed space without this pipe fetching from it.
3531 */
3532 for_each_intel_crtc(dev, crtc) {
3533 if (!crtc->active)
3534 continue;
3535
3536 pipe = crtc->pipe;
3537
3538 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3539 continue;
3540
d21b795c 3541 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3542 intel_wait_for_vblank(dev, pipe);
3543
3544 reallocated[pipe] = true;
3545 }
3546
3547
3548 /*
3549 * Second pass: flush the pipes that are having their allocation
3550 * reduced, but overlapping with a previous allocation.
3551 *
3552 * Here as well we need to wait for the vblank to make sure the freed
3553 * space is not used anymore.
3554 */
3555 for_each_intel_crtc(dev, crtc) {
3556 if (!crtc->active)
3557 continue;
3558
3559 pipe = crtc->pipe;
3560
3561 if (reallocated[pipe])
3562 continue;
3563
3564 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3565 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3566 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3567 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3568 reallocated[pipe] = true;
0e8fb7ba 3569 }
0e8fb7ba
DL		 3570 }
3571
3572 /*
3573 * Third pass: flush the pipes that got more space allocated.
3574 *
3575 * We don't need to actively wait for the update here, next vblank
3576 * will just get more DDB space with the correct WM values.
3577 */
3578 for_each_intel_crtc(dev, crtc) {
3579 if (!crtc->active)
3580 continue;
3581
3582 pipe = crtc->pipe;
3583
3584 /*
3585 * At this point, only the pipes more space than before are
3586 * left to re-allocate.
3587 */
3588 if (reallocated[pipe])
3589 continue;
3590
d21b795c 3591 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3592 }
3593}
3594
2d41c0b5
PB		 3595static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3596 struct skl_pipe_wm_parameters *params,
3597 struct intel_wm_config *config,
3598 struct skl_ddb_allocation *ddb, /* out */
3599 struct skl_pipe_wm *pipe_wm /* out */)
3600{
3601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3602
3603 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3604 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3605 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3606
3607 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3608 return false;
3609
3610 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3611
2d41c0b5
PB		 3612 return true;
3613}
3614
3615static void skl_update_other_pipe_wm(struct drm_device *dev,
3616 struct drm_crtc *crtc,
3617 struct intel_wm_config *config,
3618 struct skl_wm_values *r)
3619{
3620 struct intel_crtc *intel_crtc;
3621 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3622
3623 /*
3624 * If the WM update hasn't changed the allocation for this_crtc (the
3625 * crtc we are currently computing the new WM values for), other
3626 * enabled crtcs will keep the same allocation and we don't need to
3627 * recompute anything for them.
3628 */
3629 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3630 return;
3631
3632 /*
3633 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3634 * other active pipes need new DDB allocation and WM values.
3635 */
3636 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3637 base.head) {
3638 struct skl_pipe_wm_parameters params = {};
3639 struct skl_pipe_wm pipe_wm = {};
3640 bool wm_changed;
3641
3642 if (this_crtc->pipe == intel_crtc->pipe)
3643 continue;
3644
3645 if (!intel_crtc->active)
3646 continue;
3647
3648 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3649 &params, config,
3650 &r->ddb, &pipe_wm);
3651
3652 /*
3653 * If we end up re-computing the other pipe WM values, it's
3654 * because it was really needed, so we expect the WM values to
3655 * be different.
3656 */
3657 WARN_ON(!wm_changed);
3658
3659 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3660 r->dirty[intel_crtc->pipe] = true;
3661 }
3662}
3663
3664static void skl_update_wm(struct drm_crtc *crtc)
3665{
3666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3667 struct drm_device *dev = crtc->dev;
3668 struct drm_i915_private *dev_priv = dev->dev_private;
3669 struct skl_pipe_wm_parameters params = {};
3670 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3671 struct skl_pipe_wm pipe_wm = {};
3672 struct intel_wm_config config = {};
3673
3674 memset(results, 0, sizeof(*results));
3675
3676 skl_compute_wm_global_parameters(dev, &config);
3677
3678 if (!skl_update_pipe_wm(crtc, &params, &config,
3679 &results->ddb, &pipe_wm))
3680 return;
3681
3682 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3683 results->dirty[intel_crtc->pipe] = true;
3684
3685 skl_update_other_pipe_wm(dev, crtc, &config, results);
3686 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3687 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3688
3689 /* store the new configuration */
3690 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3691}
3692
3693static void
3694skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3695 uint32_t sprite_width, uint32_t sprite_height,
3696 int pixel_size, bool enabled, bool scaled)
3697{
3698 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3699 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3700
3701 intel_plane->wm.enabled = enabled;
3702 intel_plane->wm.scaled = scaled;
3703 intel_plane->wm.horiz_pixels = sprite_width;
3704 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3705 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3706
3707 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3708 intel_plane->wm.bytes_per_pixel =
3709 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3710 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3711 intel_plane->wm.y_bytes_per_pixel =
3712 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3713 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3714
0fda6568
TU		 3715 /*
3716 * Framebuffer can be NULL on plane disable, but it does not
3717 * matter for watermarks if we assume no tiling in that case.
3718 */
3719 if (fb)
3720 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3721 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3722
3723 skl_update_wm(crtc);
3724}
3725
820c1980 3726static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3727{
7c4a395f 3728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3729 struct drm_device *dev = crtc->dev;
801bcfff 3730 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3731 struct ilk_wm_maximums max;
3732 struct ilk_pipe_wm_parameters params = {};
3733 struct ilk_wm_values results = {};
77c122bc 3734 enum intel_ddb_partitioning partitioning;
7c4a395f 3735 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3736 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3737 struct intel_wm_config config = {};
7c4a395f 3738
2a44b76b 3739 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3740
3741 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3742
3743 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3744 return;
861f3389 3745
7c4a395f 3746 intel_crtc->wm.active = pipe_wm;
861f3389 3747
2a44b76b
VS		 3748 ilk_compute_wm_config(dev, &config);
3749
34982fe1 3750 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3751 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3752
3753 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3754 if (INTEL_INFO(dev)->gen >= 7 &&
3755 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3756 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3757 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3758
820c1980 3759 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3760 } else {
198a1e9b 3761 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3762 }
3763
198a1e9b 3764 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3765 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3766
820c1980 3767 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3768
820c1980 3769 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3770}
3771
ed57cb8a
DL		 3772static void
3773ilk_update_sprite_wm(struct drm_plane *plane,
3774 struct drm_crtc *crtc,
3775 uint32_t sprite_width, uint32_t sprite_height,
3776 int pixel_size, bool enabled, bool scaled)
526682e9 3777{
8553c18e 3778 struct drm_device *dev = plane->dev;
adf3d35e 3779 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3780
adf3d35e
VS		 3781 intel_plane->wm.enabled = enabled;
3782 intel_plane->wm.scaled = scaled;
3783 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3784 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3785 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3786
8553c18e
VS		 3787 /*
3788 * IVB workaround: must disable low power watermarks for at least
3789 * one frame before enabling scaling. LP watermarks can be re-enabled
3790 * when scaling is disabled.
3791 *
3792 * WaCxSRDisabledForSpriteScaling:ivb
3793 */
3794 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3795 intel_wait_for_vblank(dev, intel_plane->pipe);
3796
820c1980 3797 ilk_update_wm(crtc);
526682e9
PZ		 3798}
3799
3078999f
PB		 3800static void skl_pipe_wm_active_state(uint32_t val,
3801 struct skl_pipe_wm *active,
3802 bool is_transwm,
3803 bool is_cursor,
3804 int i,
3805 int level)
3806{
3807 bool is_enabled = (val & PLANE_WM_EN) != 0;
3808
3809 if (!is_transwm) {
3810 if (!is_cursor) {
3811 active->wm[level].plane_en[i] = is_enabled;
3812 active->wm[level].plane_res_b[i] =
3813 val & PLANE_WM_BLOCKS_MASK;
3814 active->wm[level].plane_res_l[i] =
3815 (val >> PLANE_WM_LINES_SHIFT) &
3816 PLANE_WM_LINES_MASK;
3817 } else {
3818 active->wm[level].cursor_en = is_enabled;
3819 active->wm[level].cursor_res_b =
3820 val & PLANE_WM_BLOCKS_MASK;
3821 active->wm[level].cursor_res_l =
3822 (val >> PLANE_WM_LINES_SHIFT) &
3823 PLANE_WM_LINES_MASK;
3824 }
3825 } else {
3826 if (!is_cursor) {
3827 active->trans_wm.plane_en[i] = is_enabled;
3828 active->trans_wm.plane_res_b[i] =
3829 val & PLANE_WM_BLOCKS_MASK;
3830 active->trans_wm.plane_res_l[i] =
3831 (val >> PLANE_WM_LINES_SHIFT) &
3832 PLANE_WM_LINES_MASK;
3833 } else {
3834 active->trans_wm.cursor_en = is_enabled;
3835 active->trans_wm.cursor_res_b =
3836 val & PLANE_WM_BLOCKS_MASK;
3837 active->trans_wm.cursor_res_l =
3838 (val >> PLANE_WM_LINES_SHIFT) &
3839 PLANE_WM_LINES_MASK;
3840 }
3841 }
3842}
3843
3844static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_private *dev_priv = dev->dev_private;
3848 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3850 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3851 enum pipe pipe = intel_crtc->pipe;
3852 int level, i, max_level;
3853 uint32_t temp;
3854
3855 max_level = ilk_wm_max_level(dev);
3856
3857 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3858
3859 for (level = 0; level <= max_level; level++) {
3860 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3861 hw->plane[pipe][i][level] =
3862 I915_READ(PLANE_WM(pipe, i, level));
3863 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3864 }
3865
3866 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3867 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3868 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3869
3ef00284 3870 if (!intel_crtc->active)
3078999f
PB		 3871 return;
3872
3873 hw->dirty[pipe] = true;
3874
3875 active->linetime = hw->wm_linetime[pipe];
3876
3877 for (level = 0; level <= max_level; level++) {
3878 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3879 temp = hw->plane[pipe][i][level];
3880 skl_pipe_wm_active_state(temp, active, false,
3881 false, i, level);
3882 }
3883 temp = hw->cursor[pipe][level];
3884 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3885 }
3886
3887 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3888 temp = hw->plane_trans[pipe][i];
3889 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3890 }
3891
3892 temp = hw->cursor_trans[pipe];
3893 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3894}
3895
3896void skl_wm_get_hw_state(struct drm_device *dev)
3897{
a269c583
DL		 3898 struct drm_i915_private *dev_priv = dev->dev_private;
3899 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3900 struct drm_crtc *crtc;
3901
a269c583 3902 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3903 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3904 skl_pipe_wm_get_hw_state(crtc);
3905}
3906
243e6a44
VS		 3907static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3908{
3909 struct drm_device *dev = crtc->dev;
3910 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3911 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3913 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3914 enum pipe pipe = intel_crtc->pipe;
3915 static const unsigned int wm0_pipe_reg[] = {
3916 [PIPE_A] = WM0_PIPEA_ILK,
3917 [PIPE_B] = WM0_PIPEB_ILK,
3918 [PIPE_C] = WM0_PIPEC_IVB,
3919 };
3920
3921 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3922 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3923 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3924
3ef00284 3925 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3926
3927 if (active->pipe_enabled) {
243e6a44
VS		 3928 u32 tmp = hw->wm_pipe[pipe];
3929
3930 /*
3931 * For active pipes LP0 watermark is marked as
3932 * enabled, and LP1+ watermaks as disabled since
3933 * we can't really reverse compute them in case
3934 * multiple pipes are active.
3935 */
3936 active->wm[0].enable = true;
3937 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3938 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3939 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3940 active->linetime = hw->wm_linetime[pipe];
3941 } else {
3942 int level, max_level = ilk_wm_max_level(dev);
3943
3944 /*
3945 * For inactive pipes, all watermark levels
3946 * should be marked as enabled but zeroed,
3947 * which is what we'd compute them to.
3948 */
3949 for (level = 0; level <= max_level; level++)
3950 active->wm[level].enable = true;
3951 }
3952}
3953
6eb1a681
VS		 3954#define _FW_WM(value, plane) \
3955 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3956#define _FW_WM_VLV(value, plane) \
3957 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3958
3959static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3960 struct vlv_wm_values *wm)
3961{
3962 enum pipe pipe;
3963 uint32_t tmp;
3964
3965 for_each_pipe(dev_priv, pipe) {
3966 tmp = I915_READ(VLV_DDL(pipe));
3967
3968 wm->ddl[pipe].primary =
3969 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3970 wm->ddl[pipe].cursor =
3971 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3972 wm->ddl[pipe].sprite[0] =
3973 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3974 wm->ddl[pipe].sprite[1] =
3975 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3976 }
3977
3978 tmp = I915_READ(DSPFW1);
3979 wm->sr.plane = _FW_WM(tmp, SR);
3980 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3981 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3982 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3983
3984 tmp = I915_READ(DSPFW2);
3985 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3986 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3987 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3988
3989 tmp = I915_READ(DSPFW3);
3990 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3991
3992 if (IS_CHERRYVIEW(dev_priv)) {
3993 tmp = I915_READ(DSPFW7_CHV);
3994 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3995 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3996
3997 tmp = I915_READ(DSPFW8_CHV);
3998 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3999 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4000
4001 tmp = I915_READ(DSPFW9_CHV);
4002 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4003 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4004
4005 tmp = I915_READ(DSPHOWM);
4006 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4007 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4008 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4009 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4010 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4011 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4012 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4013 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4014 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4015 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4016 } else {
4017 tmp = I915_READ(DSPFW7);
4018 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4019 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4020
4021 tmp = I915_READ(DSPHOWM);
4022 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4023 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4024 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4025 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4026 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4027 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4028 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4029 }
4030}
4031
4032#undef _FW_WM
4033#undef _FW_WM_VLV
4034
4035void vlv_wm_get_hw_state(struct drm_device *dev)
4036{
4037 struct drm_i915_private *dev_priv = to_i915(dev);
4038 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4039 struct intel_plane *plane;
4040 enum pipe pipe;
4041 u32 val;
4042
4043 vlv_read_wm_values(dev_priv, wm);
4044
4045 for_each_intel_plane(dev, plane) {
4046 switch (plane->base.type) {
4047 int sprite;
4048 case DRM_PLANE_TYPE_CURSOR:
4049 plane->wm.fifo_size = 63;
4050 break;
4051 case DRM_PLANE_TYPE_PRIMARY:
4052 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4053 break;
4054 case DRM_PLANE_TYPE_OVERLAY:
4055 sprite = plane->plane;
4056 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4057 break;
4058 }
4059 }
4060
4061 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4062 wm->level = VLV_WM_LEVEL_PM2;
4063
4064 if (IS_CHERRYVIEW(dev_priv)) {
4065 mutex_lock(&dev_priv->rps.hw_lock);
4066
4067 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4068 if (val & DSP_MAXFIFO_PM5_ENABLE)
4069 wm->level = VLV_WM_LEVEL_PM5;
4070
4071 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4072 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4073 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4074
4075 mutex_unlock(&dev_priv->rps.hw_lock);
4076 }
4077
4078 for_each_pipe(dev_priv, pipe)
4079 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4080 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4081 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4082
4083 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4084 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4085}
4086
243e6a44
VS		 4087void ilk_wm_get_hw_state(struct drm_device *dev)
4088{
4089 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4090 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4091 struct drm_crtc *crtc;
4092
70e1e0ec 4093 for_each_crtc(dev, crtc)
243e6a44
VS		 4094 ilk_pipe_wm_get_hw_state(crtc);
4095
4096 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4097 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4098 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4099
4100 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4101 if (INTEL_INFO(dev)->gen >= 7) {
4102 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4103 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4104 }
243e6a44 4105
a42a5719 4106 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4107 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4108 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4109 else if (IS_IVYBRIDGE(dev))
4110 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4111 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4112
4113 hw->enable_fbc_wm =
4114 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4115}
4116
b445e3b0
ED		 4117/**
4118 * intel_update_watermarks - update FIFO watermark values based on current modes
4119 *
4120 * Calculate watermark values for the various WM regs based on current mode
4121 * and plane configuration.
4122 *
4123 * There are several cases to deal with here:
4124 * - normal (i.e. non-self-refresh)
4125 * - self-refresh (SR) mode
4126 * - lines are large relative to FIFO size (buffer can hold up to 2)
4127 * - lines are small relative to FIFO size (buffer can hold more than 2
4128 * lines), so need to account for TLB latency
4129 *
4130 * The normal calculation is:
4131 * watermark = dotclock * bytes per pixel * latency
4132 * where latency is platform & configuration dependent (we assume pessimal
4133 * values here).
4134 *
4135 * The SR calculation is:
4136 * watermark = (trunc(latency/line time)+1) * surface width *
4137 * bytes per pixel
4138 * where
4139 * line time = htotal / dotclock
4140 * surface width = hdisplay for normal plane and 64 for cursor
4141 * and latency is assumed to be high, as above.
4142 *
4143 * The final value programmed to the register should always be rounded up,
4144 * and include an extra 2 entries to account for clock crossings.
4145 *
4146 * We don't use the sprite, so we can ignore that. And on Crestline we have
4147 * to set the non-SR watermarks to 8.
4148 */
46ba614c 4149void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4150{
46ba614c 4151 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4152
4153 if (dev_priv->display.update_wm)
46ba614c 4154 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4155}
4156
adf3d35e
VS		 4157void intel_update_sprite_watermarks(struct drm_plane *plane,
4158 struct drm_crtc *crtc,
ed57cb8a
DL		 4159 uint32_t sprite_width,
4160 uint32_t sprite_height,
4161 int pixel_size,
39db4a4d 4162 bool enabled, bool scaled)
b445e3b0 4163{
adf3d35e 4164 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 4165
4166 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 4167 dev_priv->display.update_sprite_wm(plane, crtc,
4168 sprite_width, sprite_height,
39db4a4d 4169 pixel_size, enabled, scaled);
b445e3b0
ED		 4170}
4171
9270388e
DV		 4172/**
4173 * Lock protecting IPS related data structures
9270388e
DV		 4174 */
4175DEFINE_SPINLOCK(mchdev_lock);
4176
4177/* Global for IPS driver to get at the current i915 device. Protected by
4178 * mchdev_lock. */
4179static struct drm_i915_private *i915_mch_dev;
4180
2b4e57bd
ED		 4181bool ironlake_set_drps(struct drm_device *dev, u8 val)
4182{
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 u16 rgvswctl;
4185
9270388e
DV		 4186 assert_spin_locked(&mchdev_lock);
4187
2b4e57bd
ED		 4188 rgvswctl = I915_READ16(MEMSWCTL);
4189 if (rgvswctl & MEMCTL_CMD_STS) {
4190 DRM_DEBUG("gpu busy, RCS change rejected\n");
4191 return false; /* still busy with another command */
4192 }
4193
4194 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4195 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4196 I915_WRITE16(MEMSWCTL, rgvswctl);
4197 POSTING_READ16(MEMSWCTL);
4198
4199 rgvswctl |= MEMCTL_CMD_STS;
4200 I915_WRITE16(MEMSWCTL, rgvswctl);
4201
4202 return true;
4203}
4204
8090c6b9 4205static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4206{
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 u32 rgvmodectl = I915_READ(MEMMODECTL);
4209 u8 fmax, fmin, fstart, vstart;
4210
9270388e
DV		 4211 spin_lock_irq(&mchdev_lock);
4212
2b4e57bd
ED		 4213 /* Enable temp reporting */
4214 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4215 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4216
4217 /* 100ms RC evaluation intervals */
4218 I915_WRITE(RCUPEI, 100000);
4219 I915_WRITE(RCDNEI, 100000);
4220
4221 /* Set max/min thresholds to 90ms and 80ms respectively */
4222 I915_WRITE(RCBMAXAVG, 90000);
4223 I915_WRITE(RCBMINAVG, 80000);
4224
4225 I915_WRITE(MEMIHYST, 1);
4226
4227 /* Set up min, max, and cur for interrupt handling */
4228 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4229 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4230 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4231 MEMMODE_FSTART_SHIFT;
4232
4233 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4234 PXVFREQ_PX_SHIFT;
4235
20e4d407
DV		 4236 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4237 dev_priv->ips.fstart = fstart;
2b4e57bd 4238
20e4d407
DV		 4239 dev_priv->ips.max_delay = fstart;
4240 dev_priv->ips.min_delay = fmin;
4241 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4242
4243 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4244 fmax, fmin, fstart);
4245
4246 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4247
4248 /*
4249 * Interrupts will be enabled in ironlake_irq_postinstall
4250 */
4251
4252 I915_WRITE(VIDSTART, vstart);
4253 POSTING_READ(VIDSTART);
4254
4255 rgvmodectl |= MEMMODE_SWMODE_EN;
4256 I915_WRITE(MEMMODECTL, rgvmodectl);
4257
9270388e 4258 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4259 DRM_ERROR("stuck trying to change perf mode\n");
6adfb1ef 4260 msleep(1);
2b4e57bd
ED		 4261
4262 ironlake_set_drps(dev, fstart);
4263
20e4d407 4264 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 4265 I915_READ(0x112e0);
20e4d407
DV		 4266 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4267 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 4268 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4269
4270 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4271}
4272
8090c6b9 4273static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4274{
4275 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4276 u16 rgvswctl;
4277
4278 spin_lock_irq(&mchdev_lock);
4279
4280 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4281
4282 /* Ack interrupts, disable EFC interrupt */
4283 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4284 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4285 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4286 I915_WRITE(DEIIR, DE_PCU_EVENT);
4287 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4288
4289 /* Go back to the starting frequency */
20e4d407 4290 ironlake_set_drps(dev, dev_priv->ips.fstart);
6adfb1ef 4291 msleep(1);
2b4e57bd
ED		 4292 rgvswctl |= MEMCTL_CMD_STS;
4293 I915_WRITE(MEMSWCTL, rgvswctl);
6adfb1ef 4294 msleep(1);
2b4e57bd 4295
9270388e 4296 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4297}
4298
acbe9475
DV		 4299/* There's a funny hw issue where the hw returns all 0 when reading from
4300 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4301 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4302 * all limits and the gpu stuck at whatever frequency it is at atm).
4303 */
74ef1173 4304static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4305{
7b9e0ae6 4306 u32 limits;
2b4e57bd 4307
20b46e59
DV		 4308 /* Only set the down limit when we've reached the lowest level to avoid
4309 * getting more interrupts, otherwise leave this clear. This prevents a
4310 * race in the hw when coming out of rc6: There's a tiny window where
4311 * the hw runs at the minimal clock before selecting the desired
4312 * frequency, if the down threshold expires in that window we will not
4313 * receive a down interrupt. */
74ef1173
AG		 4314 if (IS_GEN9(dev_priv->dev)) {
4315 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4316 if (val <= dev_priv->rps.min_freq_softlimit)
4317 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4318 } else {
4319 limits = dev_priv->rps.max_freq_softlimit << 24;
4320 if (val <= dev_priv->rps.min_freq_softlimit)
4321 limits |= dev_priv->rps.min_freq_softlimit << 16;
4322 }
20b46e59
DV		 4323
4324 return limits;
4325}
4326
dd75fdc8
CW		 4327static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4328{
4329 int new_power;
8a586437
AG		 4330 u32 threshold_up = 0, threshold_down = 0; /* in % */
4331 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4332
4333 new_power = dev_priv->rps.power;
4334 switch (dev_priv->rps.power) {
4335 case LOW_POWER:
b39fb297 4336 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4337 new_power = BETWEEN;
4338 break;
4339
4340 case BETWEEN:
b39fb297 4341 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4342 new_power = LOW_POWER;
b39fb297 4343 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4344 new_power = HIGH_POWER;
4345 break;
4346
4347 case HIGH_POWER:
b39fb297 4348 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4349 new_power = BETWEEN;
4350 break;
4351 }
4352 /* Max/min bins are special */
aed242ff 4353 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4354 new_power = LOW_POWER;
aed242ff 4355 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4356 new_power = HIGH_POWER;
4357 if (new_power == dev_priv->rps.power)
4358 return;
4359
4360 /* Note the units here are not exactly 1us, but 1280ns. */
4361 switch (new_power) {
4362 case LOW_POWER:
4363 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4364 ei_up = 16000;
4365 threshold_up = 95;
dd75fdc8
CW		 4366
4367 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4368 ei_down = 32000;
4369 threshold_down = 85;
dd75fdc8
CW		 4370 break;
4371
4372 case BETWEEN:
4373 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4374 ei_up = 13000;
4375 threshold_up = 90;
dd75fdc8
CW		 4376
4377 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4378 ei_down = 32000;
4379 threshold_down = 75;
dd75fdc8
CW		 4380 break;
4381
4382 case HIGH_POWER:
4383 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4384 ei_up = 10000;
4385 threshold_up = 85;
dd75fdc8
CW		 4386
4387 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4388 ei_down = 32000;
4389 threshold_down = 60;
dd75fdc8
CW		 4390 break;
4391 }
4392
8a586437
AG		 4393 I915_WRITE(GEN6_RP_UP_EI,
4394 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4395 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4396 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4397
4398 I915_WRITE(GEN6_RP_DOWN_EI,
4399 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4400 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4401 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4402
4403 I915_WRITE(GEN6_RP_CONTROL,
4404 GEN6_RP_MEDIA_TURBO |
4405 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4406 GEN6_RP_MEDIA_IS_GFX |
4407 GEN6_RP_ENABLE |
4408 GEN6_RP_UP_BUSY_AVG |
4409 GEN6_RP_DOWN_IDLE_AVG);
4410
dd75fdc8 4411 dev_priv->rps.power = new_power;
8fb55197
CW		 4412 dev_priv->rps.up_threshold = threshold_up;
4413 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4414 dev_priv->rps.last_adj = 0;
4415}
4416
2876ce73
CW		 4417static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4418{
4419 u32 mask = 0;
4420
4421 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4422 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4423 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4424 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4425
7b3c29f6
CW		 4426 mask &= dev_priv->pm_rps_events;
4427
59d02a1f 4428 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4429}
4430
b8a5ff8d
JM		 4431/* gen6_set_rps is called to update the frequency request, but should also be
4432 * called when the range (min_delay and max_delay) is modified so that we can
4433 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4434static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4435{
4436 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4437
4fc688ce 4438 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4439 WARN_ON(val > dev_priv->rps.max_freq);
4440 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4441
eb64cad1
CW		 4442 /* min/max delay may still have been modified so be sure to
4443 * write the limits value.
4444 */
4445 if (val != dev_priv->rps.cur_freq) {
4446 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4447
5704195c
AG		 4448 if (IS_GEN9(dev))
4449 I915_WRITE(GEN6_RPNSWREQ,
4450 GEN9_FREQUENCY(val));
4451 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4452 I915_WRITE(GEN6_RPNSWREQ,
4453 HSW_FREQUENCY(val));
4454 else
4455 I915_WRITE(GEN6_RPNSWREQ,
4456 GEN6_FREQUENCY(val) |
4457 GEN6_OFFSET(0) |
4458 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4459 }
7b9e0ae6 4460
7b9e0ae6
CW		 4461 /* Make sure we continue to get interrupts
4462 * until we hit the minimum or maximum frequencies.
4463 */
74ef1173 4464 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4465 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4466
d5570a72
BW		 4467 POSTING_READ(GEN6_RPNSWREQ);
4468
b39fb297 4469 dev_priv->rps.cur_freq = val;
be2cde9a 4470 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4471}
4472
ffe02b40
VS		 4473static void valleyview_set_rps(struct drm_device *dev, u8 val)
4474{
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476
4477 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4478 WARN_ON(val > dev_priv->rps.max_freq);
4479 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4480
4481 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4482 "Odd GPU freq value\n"))
4483 val &= ~1;
4484
8fb55197 4485 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4486 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4487 if (!IS_CHERRYVIEW(dev_priv))
4488 gen6_set_rps_thresholds(dev_priv, val);
4489 }
ffe02b40
VS		 4490
4491 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4492
4493 dev_priv->rps.cur_freq = val;
4494 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4495}
4496
a7f6e231 4497/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4498 *
4499 * * If Gfx is Idle, then
a7f6e231
D		 4500 * 1. Forcewake Media well.
4501 * 2. Request idle freq.
4502 * 3. Release Forcewake of Media well.
76c3552f
D		 4503*/
4504static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4505{
aed242ff 4506 u32 val = dev_priv->rps.idle_freq;
5549d25f 4507
aed242ff 4508 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4509 return;
4510
a7f6e231
D		 4511 /* Wake up the media well, as that takes a lot less
4512 * power than the Render well. */
4513 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4514 valleyview_set_rps(dev_priv->dev, val);
4515 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4516}
4517
43cf3bf0
CW		 4518void gen6_rps_busy(struct drm_i915_private *dev_priv)
4519{
4520 mutex_lock(&dev_priv->rps.hw_lock);
4521 if (dev_priv->rps.enabled) {
4522 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4523 gen6_rps_reset_ei(dev_priv);
4524 I915_WRITE(GEN6_PMINTRMSK,
4525 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4526 }
4527 mutex_unlock(&dev_priv->rps.hw_lock);
4528}
4529
b29c19b6
CW		 4530void gen6_rps_idle(struct drm_i915_private *dev_priv)
4531{
691bb717
DL		 4532 struct drm_device *dev = dev_priv->dev;
4533
b29c19b6 4534 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4535 if (dev_priv->rps.enabled) {
21a11fff 4536 if (IS_VALLEYVIEW(dev))
76c3552f 4537 vlv_set_rps_idle(dev_priv);
7526ed79 4538 else
aed242ff 4539 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4540 dev_priv->rps.last_adj = 0;
43cf3bf0 4541 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4542 }
8d3afd7d 4543 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4544
8d3afd7d 4545 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4546 while (!list_empty(&dev_priv->rps.clients))
4547 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4548 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4549}
4550
1854d5ca 4551void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4552 struct intel_rps_client *rps,
4553 unsigned long submitted)
b29c19b6 4554{
8d3afd7d
CW		 4555 /* This is intentionally racy! We peek at the state here, then
4556 * validate inside the RPS worker.
4557 */
4558 if (!(dev_priv->mm.busy &&
4559 dev_priv->rps.enabled &&
4560 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4561 return;
43cf3bf0 4562
e61b9958
CW		 4563 /* Force a RPS boost (and don't count it against the client) if
4564 * the GPU is severely congested.
4565 */
d0bc54f2 4566 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4567 rps = NULL;
4568
8d3afd7d
CW		 4569 spin_lock(&dev_priv->rps.client_lock);
4570 if (rps == NULL || list_empty(&rps->link)) {
4571 spin_lock_irq(&dev_priv->irq_lock);
4572 if (dev_priv->rps.interrupts_enabled) {
4573 dev_priv->rps.client_boost = true;
4574 queue_work(dev_priv->wq, &dev_priv->rps.work);
4575 }
4576 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4577
2e1b8730
CW		 4578 if (rps != NULL) {
4579 list_add(&rps->link, &dev_priv->rps.clients);
4580 rps->boosts++;
1854d5ca
CW		 4581 } else
4582 dev_priv->rps.boosts++;
c0951f0c 4583 }
8d3afd7d 4584 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4585}
4586
ffe02b40 4587void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4588{
ffe02b40
VS		 4589 if (IS_VALLEYVIEW(dev))
4590 valleyview_set_rps(dev, val);
4591 else
4592 gen6_set_rps(dev, val);
0a073b84
JB		 4593}
4594
20e49366
ZW		 4595static void gen9_disable_rps(struct drm_device *dev)
4596{
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598
4599 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4600 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4601}
4602
44fc7d5c 4603static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4604{
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606
4607 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4608 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4609}
4610
38807746
D		 4611static void cherryview_disable_rps(struct drm_device *dev)
4612{
4613 struct drm_i915_private *dev_priv = dev->dev_private;
4614
4615 I915_WRITE(GEN6_RC_CONTROL, 0);
4616}
4617
44fc7d5c
DV		 4618static void valleyview_disable_rps(struct drm_device *dev)
4619{
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621
98a2e5f9
D		 4622 /* we're doing forcewake before Disabling RC6,
4623 * This what the BIOS expects when going into suspend */
59bad947 4624 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4625
44fc7d5c 4626 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4627
59bad947 4628 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4629}
4630
dc39fff7
BW		 4631static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4632{
91ca689a
ID		 4633 if (IS_VALLEYVIEW(dev)) {
4634 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4635 mode = GEN6_RC_CTL_RC6_ENABLE;
4636 else
4637 mode = 0;
4638 }
58abf1da
RV		 4639 if (HAS_RC6p(dev))
4640 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4641 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4642 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4643 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4644
4645 else
4646 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4647 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4648}
4649
e6069ca8 4650static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4651{
e7d66d89
DV		 4652 /* No RC6 before Ironlake and code is gone for ilk. */
4653 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4654 return 0;
4655
456470eb 4656 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4657 if (enable_rc6 >= 0) {
4658 int mask;
4659
58abf1da 4660 if (HAS_RC6p(dev))
e6069ca8
ID		 4661 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4662 INTEL_RC6pp_ENABLE;
4663 else
4664 mask = INTEL_RC6_ENABLE;
4665
4666 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4667 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4668 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4669
4670 return enable_rc6 & mask;
4671 }
2b4e57bd 4672
8bade1ad 4673 if (IS_IVYBRIDGE(dev))
cca84a1f 4674 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4675
4676 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4677}
4678
e6069ca8
ID		 4679int intel_enable_rc6(const struct drm_device *dev)
4680{
4681 return i915.enable_rc6;
4682}
4683
93ee2920 4684static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4685{
93ee2920
TR		 4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687 uint32_t rp_state_cap;
4688 u32 ddcc_status = 0;
4689 int ret;
4690
3280e8b0
BW		 4691 /* All of these values are in units of 50MHz */
4692 dev_priv->rps.cur_freq = 0;
93ee2920 4693 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4694 if (IS_BROXTON(dev)) {
4695 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4696 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4697 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4698 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4699 } else {
4700 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4701 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4702 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4703 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4704 }
4705
3280e8b0
BW		 4706 /* hw_max = RP0 until we check for overclocking */
4707 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4708
93ee2920 4709 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4710 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4711 ret = sandybridge_pcode_read(dev_priv,
4712 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4713 &ddcc_status);
4714 if (0 == ret)
4715 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4716 clamp_t(u8,
4717 ((ddcc_status >> 8) & 0xff),
4718 dev_priv->rps.min_freq,
4719 dev_priv->rps.max_freq);
93ee2920
TR		 4720 }
4721
c5e0688c
AG		 4722 if (IS_SKYLAKE(dev)) {
4723 /* Store the frequency values in 16.66 MHZ units, which is
4724 the natural hardware unit for SKL */
4725 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4726 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4727 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4728 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4729 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4730 }
4731
aed242ff
CW		 4732 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4733
3280e8b0
BW		 4734 /* Preserve min/max settings in case of re-init */
4735 if (dev_priv->rps.max_freq_softlimit == 0)
4736 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4737
93ee2920
TR		 4738 if (dev_priv->rps.min_freq_softlimit == 0) {
4739 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4740 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4741 max_t(int, dev_priv->rps.efficient_freq,
4742 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4743 else
4744 dev_priv->rps.min_freq_softlimit =
4745 dev_priv->rps.min_freq;
4746 }
3280e8b0
BW		 4747}
4748
b6fef0ef 4749/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4750static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4751{
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753
4754 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4755
ba1c554c
DL		 4756 gen6_init_rps_frequencies(dev);
4757
0beb059a
AG		 4758 /* Program defaults and thresholds for RPS*/
4759 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4760 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4761
4762 /* 1 second timeout*/
4763 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4764 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4765
b6fef0ef 4766 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4767
0beb059a
AG		 4768 /* Leaning on the below call to gen6_set_rps to program/setup the
4769 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4770 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4771 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4772 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4773
4774 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4775}
4776
4777static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4778{
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4780 struct intel_engine_cs *ring;
4781 uint32_t rc6_mask = 0;
4782 int unused;
4783
4784 /* 1a: Software RC state - RC0 */
4785 I915_WRITE(GEN6_RC_STATE, 0);
4786
4787 /* 1b: Get forcewake during program sequence. Although the driver
4788 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4789 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4790
4791 /* 2a: Disable RC states. */
4792 I915_WRITE(GEN6_RC_CONTROL, 0);
4793
4794 /* 2b: Program RC6 thresholds.*/
4795 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4796 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4797 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4798 for_each_ring(ring, dev_priv, unused)
4799 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4800 I915_WRITE(GEN6_RC_SLEEP, 0);
4801 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4802
38c23527
ZW		 4803 /* 2c: Program Coarse Power Gating Policies. */
4804 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4805 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4806
20e49366
ZW		 4807 /* 3a: Enable RC6 */
4808 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4809 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4810 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4811 "on" : "off");
4812 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4813 GEN6_RC_CTL_EI_MODE(1) |
4814 rc6_mask);
4815
cb07bae0
SK		 4816 /*
4817 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4818 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4819 */
a4104c55 4820 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
cb07bae0 4821 GEN9_MEDIA_PG_ENABLE : 0);
a4104c55 4822
38c23527 4823
59bad947 4824 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4825
4826}
4827
6edee7f3
BW		 4828static void gen8_enable_rps(struct drm_device *dev)
4829{
4830 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4831 struct intel_engine_cs *ring;
93ee2920 4832 uint32_t rc6_mask = 0;
6edee7f3
BW		 4833 int unused;
4834
4835 /* 1a: Software RC state - RC0 */
4836 I915_WRITE(GEN6_RC_STATE, 0);
4837
4838 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4839 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4840 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4841
4842 /* 2a: Disable RC states. */
4843 I915_WRITE(GEN6_RC_CONTROL, 0);
4844
93ee2920
TR		 4845 /* Initialize rps frequencies */
4846 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4847
4848 /* 2b: Program RC6 thresholds.*/
4849 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4850 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4851 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4852 for_each_ring(ring, dev_priv, unused)
4853 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4854 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4855 if (IS_BROADWELL(dev))
4856 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4857 else
4858 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4859
4860 /* 3: Enable RC6 */
4861 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4862 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4863 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4864 if (IS_BROADWELL(dev))
4865 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4866 GEN7_RC_CTL_TO_MODE |
4867 rc6_mask);
4868 else
4869 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4870 GEN6_RC_CTL_EI_MODE(1) |
4871 rc6_mask);
6edee7f3
BW		 4872
4873 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4874 I915_WRITE(GEN6_RPNSWREQ,
4875 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4876 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4877 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4878 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4879 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4880
4881 /* Docs recommend 900MHz, and 300 MHz respectively */
4882 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4883 dev_priv->rps.max_freq_softlimit << 24 |
4884 dev_priv->rps.min_freq_softlimit << 16);
4885
4886 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4887 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4888 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4889 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4890
4891 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4892
4893 /* 5: Enable RPS */
7526ed79
DV		 4894 I915_WRITE(GEN6_RP_CONTROL,
4895 GEN6_RP_MEDIA_TURBO |
4896 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4897 GEN6_RP_MEDIA_IS_GFX |
4898 GEN6_RP_ENABLE |
4899 GEN6_RP_UP_BUSY_AVG |
4900 GEN6_RP_DOWN_IDLE_AVG);
4901
4902 /* 6: Ring frequency + overclocking (our driver does this later */
4903
c7f3153a 4904 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4905 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4906
59bad947 4907 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4908}
4909
79f5b2c7 4910static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4911{
79f5b2c7 4912 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4913 struct intel_engine_cs *ring;
d060c169 4914 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4915 u32 gtfifodbg;
2b4e57bd 4916 int rc6_mode;
42c0526c 4917 int i, ret;
2b4e57bd 4918
4fc688ce 4919 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4920
2b4e57bd
ED		 4921 /* Here begins a magic sequence of register writes to enable
4922 * auto-downclocking.
4923 *
4924 * Perhaps there might be some value in exposing these to
4925 * userspace...
4926 */
4927 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4928
4929 /* Clear the DBG now so we don't confuse earlier errors */
4930 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4931 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4932 I915_WRITE(GTFIFODBG, gtfifodbg);
4933 }
4934
59bad947 4935 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4936
93ee2920
TR		 4937 /* Initialize rps frequencies */
4938 gen6_init_rps_frequencies(dev);
dd0a1aa1 4939
2b4e57bd
ED		 4940 /* disable the counters and set deterministic thresholds */
4941 I915_WRITE(GEN6_RC_CONTROL, 0);
4942
4943 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4944 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4945 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4946 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4947 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4948
b4519513
CW		 4949 for_each_ring(ring, dev_priv, i)
4950 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4951
4952 I915_WRITE(GEN6_RC_SLEEP, 0);
4953 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4954 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4955 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4956 else
4957 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4958 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4959 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4960
5a7dc92a 4961 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4962 rc6_mode = intel_enable_rc6(dev_priv->dev);
4963 if (rc6_mode & INTEL_RC6_ENABLE)
4964 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4965
5a7dc92a
ED		 4966 /* We don't use those on Haswell */
4967 if (!IS_HASWELL(dev)) {
4968 if (rc6_mode & INTEL_RC6p_ENABLE)
4969 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4970
5a7dc92a
ED		 4971 if (rc6_mode & INTEL_RC6pp_ENABLE)
4972 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4973 }
2b4e57bd 4974
dc39fff7 4975 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4976
4977 I915_WRITE(GEN6_RC_CONTROL,
4978 rc6_mask |
4979 GEN6_RC_CTL_EI_MODE(1) |
4980 GEN6_RC_CTL_HW_ENABLE);
4981
dd75fdc8
CW		 4982 /* Power down if completely idle for over 50ms */
4983 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4984 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4985
42c0526c 4986 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4987 if (ret)
42c0526c 4988 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4989
4990 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4991 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4992 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4993 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4994 (pcu_mbox & 0xff) * 50);
b39fb297 4995 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4996 }
4997
dd75fdc8 4998 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4999 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5000
31643d54
BW		 5001 rc6vids = 0;
5002 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5003 if (IS_GEN6(dev) && ret) {
5004 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5005 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5006 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5007 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5008 rc6vids &= 0xffff00;
5009 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5010 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5011 if (ret)
5012 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5013 }
5014
59bad947 5015 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5016}
5017
c2bc2fc5 5018static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5019{
79f5b2c7 5020 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5021 int min_freq = 15;
3ebecd07
CW		 5022 unsigned int gpu_freq;
5023 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 5024 int scaling_factor = 180;
eda79642 5025 struct cpufreq_policy *policy;
2b4e57bd 5026
4fc688ce 5027 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5028
eda79642
BW		 5029 policy = cpufreq_cpu_get(0);
5030 if (policy) {
5031 max_ia_freq = policy->cpuinfo.max_freq;
5032 cpufreq_cpu_put(policy);
5033 } else {
5034 /*
5035 * Default to measured freq if none found, PCU will ensure we
5036 * don't go over
5037 */
2b4e57bd 5038 max_ia_freq = tsc_khz;
eda79642 5039 }
2b4e57bd
ED		 5040
5041 /* Convert from kHz to MHz */
5042 max_ia_freq /= 1000;
5043
153b4b95 5044 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5045 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5046 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5047
2b4e57bd
ED		 5048 /*
5049 * For each potential GPU frequency, load a ring frequency we'd like
5050 * to use for memory access. We do this by specifying the IA frequency
5051 * the PCU should use as a reference to determine the ring frequency.
5052 */
6985b352 5053 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 5054 gpu_freq--) {
6985b352 5055 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 5056 unsigned int ia_freq = 0, ring_freq = 0;
5057
46c764d4
BW		 5058 if (INTEL_INFO(dev)->gen >= 8) {
5059 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5060 ring_freq = max(min_ring_freq, gpu_freq);
5061 } else if (IS_HASWELL(dev)) {
f6aca45c 5062 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5063 ring_freq = max(min_ring_freq, ring_freq);
5064 /* leave ia_freq as the default, chosen by cpufreq */
5065 } else {
5066 /* On older processors, there is no separate ring
5067 * clock domain, so in order to boost the bandwidth
5068 * of the ring, we need to upclock the CPU (ia_freq).
5069 *
5070 * For GPU frequencies less than 750MHz,
5071 * just use the lowest ring freq.
5072 */
5073 if (gpu_freq < min_freq)
5074 ia_freq = 800;
5075 else
5076 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5077 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5078 }
2b4e57bd 5079
42c0526c
BW		 5080 sandybridge_pcode_write(dev_priv,
5081 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5082 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5083 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5084 gpu_freq);
2b4e57bd 5085 }
2b4e57bd
ED		 5086}
5087
c2bc2fc5
ID		 5088void gen6_update_ring_freq(struct drm_device *dev)
5089{
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091
5092 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
5093 return;
5094
5095 mutex_lock(&dev_priv->rps.hw_lock);
5096 __gen6_update_ring_freq(dev);
5097 mutex_unlock(&dev_priv->rps.hw_lock);
5098}
5099
03af2045 5100static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5101{
095acd5f 5102 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5103 u32 val, rp0;
5104
095acd5f
D		 5105 if (dev->pdev->revision >= 0x20) {
5106 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5107
095acd5f
D		 5108 switch (INTEL_INFO(dev)->eu_total) {
5109 case 8:
5110 /* (2 * 4) config */
5111 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5112 break;
5113 case 12:
5114 /* (2 * 6) config */
5115 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5116 break;
5117 case 16:
5118 /* (2 * 8) config */
5119 default:
5120 /* Setting (2 * 8) Min RP0 for any other combination */
5121 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5122 break;
5123 }
5124 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5125 } else {
5126 /* For pre-production hardware */
5127 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5128 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5129 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5130 }
2b6b3a09
D		 5131 return rp0;
5132}
5133
5134static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5135{
5136 u32 val, rpe;
5137
5138 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5139 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5140
5141 return rpe;
5142}
5143
7707df4a
D		 5144static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5145{
095acd5f 5146 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5147 u32 val, rp1;
5148
095acd5f
D		 5149 if (dev->pdev->revision >= 0x20) {
5150 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5151 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5152 } else {
5153 /* For pre-production hardware */
5154 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5155 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5156 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5157 }
7707df4a
D		 5158 return rp1;
5159}
5160
f8f2b001
D		 5161static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5162{
5163 u32 val, rp1;
5164
5165 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5166
5167 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5168
5169 return rp1;
5170}
5171
03af2045 5172static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5173{
5174 u32 val, rp0;
5175
64936258 5176 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5177
5178 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5179 /* Clamp to max */
5180 rp0 = min_t(u32, rp0, 0xea);
5181
5182 return rp0;
5183}
5184
5185static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5186{
5187 u32 val, rpe;
5188
64936258 5189 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5190 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5191 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5192 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5193
5194 return rpe;
5195}
5196
03af2045 5197static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5198{
64936258 5199 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5200}
5201
ae48434c
ID		 5202/* Check that the pctx buffer wasn't move under us. */
5203static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5204{
5205 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5206
5207 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5208 dev_priv->vlv_pctx->stolen->start);
5209}
5210
38807746
D		 5211
5212/* Check that the pcbr address is not empty. */
5213static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5214{
5215 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5216
5217 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5218}
5219
5220static void cherryview_setup_pctx(struct drm_device *dev)
5221{
5222 struct drm_i915_private *dev_priv = dev->dev_private;
5223 unsigned long pctx_paddr, paddr;
5224 struct i915_gtt *gtt = &dev_priv->gtt;
5225 u32 pcbr;
5226 int pctx_size = 32*1024;
5227
5228 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5229
5230 pcbr = I915_READ(VLV_PCBR);
5231 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5232 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5233 paddr = (dev_priv->mm.stolen_base +
5234 (gtt->stolen_size - pctx_size));
5235
5236 pctx_paddr = (paddr & (~4095));
5237 I915_WRITE(VLV_PCBR, pctx_paddr);
5238 }
ce611ef8
VS		 5239
5240 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5241}
5242
c9cddffc
JB		 5243static void valleyview_setup_pctx(struct drm_device *dev)
5244{
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 struct drm_i915_gem_object *pctx;
5247 unsigned long pctx_paddr;
5248 u32 pcbr;
5249 int pctx_size = 24*1024;
5250
17b0c1f7
ID		 5251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5252
c9cddffc
JB		 5253 pcbr = I915_READ(VLV_PCBR);
5254 if (pcbr) {
5255 /* BIOS set it up already, grab the pre-alloc'd space */
5256 int pcbr_offset;
5257
5258 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5259 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5260 pcbr_offset,
190d6cd5 5261 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5262 pctx_size);
5263 goto out;
5264 }
5265
ce611ef8
VS		 5266 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5267
c9cddffc
JB		 5268 /*
5269 * From the Gunit register HAS:
5270 * The Gfx driver is expected to program this register and ensure
5271 * proper allocation within Gfx stolen memory. For example, this
5272 * register should be programmed such than the PCBR range does not
5273 * overlap with other ranges, such as the frame buffer, protected
5274 * memory, or any other relevant ranges.
5275 */
5276 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5277 if (!pctx) {
5278 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5279 return;
5280 }
5281
5282 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5283 I915_WRITE(VLV_PCBR, pctx_paddr);
5284
5285out:
ce611ef8 5286 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5287 dev_priv->vlv_pctx = pctx;
5288}
5289
ae48434c
ID		 5290static void valleyview_cleanup_pctx(struct drm_device *dev)
5291{
5292 struct drm_i915_private *dev_priv = dev->dev_private;
5293
5294 if (WARN_ON(!dev_priv->vlv_pctx))
5295 return;
5296
5297 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5298 dev_priv->vlv_pctx = NULL;
5299}
5300
4e80519e
ID		 5301static void valleyview_init_gt_powersave(struct drm_device *dev)
5302{
5303 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5304 u32 val;
4e80519e
ID		 5305
5306 valleyview_setup_pctx(dev);
5307
5308 mutex_lock(&dev_priv->rps.hw_lock);
5309
2bb25c17
VS		 5310 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5311 switch ((val >> 6) & 3) {
5312 case 0:
5313 case 1:
5314 dev_priv->mem_freq = 800;
5315 break;
5316 case 2:
5317 dev_priv->mem_freq = 1066;
5318 break;
5319 case 3:
5320 dev_priv->mem_freq = 1333;
5321 break;
5322 }
80b83b62 5323 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5324
4e80519e
ID		 5325 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5326 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5327 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5328 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5329 dev_priv->rps.max_freq);
5330
5331 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5332 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5333 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5334 dev_priv->rps.efficient_freq);
5335
f8f2b001
D		 5336 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5337 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5338 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5339 dev_priv->rps.rp1_freq);
5340
4e80519e
ID		 5341 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5342 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5343 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5344 dev_priv->rps.min_freq);
5345
aed242ff
CW		 5346 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5347
4e80519e
ID		 5348 /* Preserve min/max settings in case of re-init */
5349 if (dev_priv->rps.max_freq_softlimit == 0)
5350 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5351
5352 if (dev_priv->rps.min_freq_softlimit == 0)
5353 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5354
5355 mutex_unlock(&dev_priv->rps.hw_lock);
5356}
5357
38807746
D		 5358static void cherryview_init_gt_powersave(struct drm_device *dev)
5359{
2b6b3a09 5360 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5361 u32 val;
2b6b3a09 5362
38807746 5363 cherryview_setup_pctx(dev);
2b6b3a09
D		 5364
5365 mutex_lock(&dev_priv->rps.hw_lock);
5366
a580516d 5367 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5368 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5369 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5370
2bb25c17
VS		 5371 switch ((val >> 2) & 0x7) {
5372 case 0:
5373 case 1:
5374 dev_priv->rps.cz_freq = 200;
5375 dev_priv->mem_freq = 1600;
5376 break;
5377 case 2:
5378 dev_priv->rps.cz_freq = 267;
5379 dev_priv->mem_freq = 1600;
5380 break;
5381 case 3:
5382 dev_priv->rps.cz_freq = 333;
5383 dev_priv->mem_freq = 2000;
5384 break;
5385 case 4:
5386 dev_priv->rps.cz_freq = 320;
5387 dev_priv->mem_freq = 1600;
5388 break;
5389 case 5:
5390 dev_priv->rps.cz_freq = 400;
5391 dev_priv->mem_freq = 1600;
5392 break;
5393 }
80b83b62 5394 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5395
2b6b3a09
D		 5396 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5397 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5398 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5399 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5400 dev_priv->rps.max_freq);
5401
5402 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5403 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5404 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5405 dev_priv->rps.efficient_freq);
5406
7707df4a
D		 5407 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5408 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5409 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5410 dev_priv->rps.rp1_freq);
5411
5b7c91b7
D		 5412 /* PUnit validated range is only [RPe, RP0] */
5413 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5414 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5415 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5416 dev_priv->rps.min_freq);
5417
1c14762d
VS		 5418 WARN_ONCE((dev_priv->rps.max_freq |
5419 dev_priv->rps.efficient_freq |
5420 dev_priv->rps.rp1_freq |
5421 dev_priv->rps.min_freq) & 1,
5422 "Odd GPU freq values\n");
5423
aed242ff
CW		 5424 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5425
2b6b3a09
D		 5426 /* Preserve min/max settings in case of re-init */
5427 if (dev_priv->rps.max_freq_softlimit == 0)
5428 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5429
5430 if (dev_priv->rps.min_freq_softlimit == 0)
5431 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5432
5433 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5434}
5435
4e80519e
ID		 5436static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5437{
5438 valleyview_cleanup_pctx(dev);
5439}
5440
38807746
D		 5441static void cherryview_enable_rps(struct drm_device *dev)
5442{
5443 struct drm_i915_private *dev_priv = dev->dev_private;
5444 struct intel_engine_cs *ring;
2b6b3a09 5445 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5446 int i;
5447
5448 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5449
5450 gtfifodbg = I915_READ(GTFIFODBG);
5451 if (gtfifodbg) {
5452 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5453 gtfifodbg);
5454 I915_WRITE(GTFIFODBG, gtfifodbg);
5455 }
5456
5457 cherryview_check_pctx(dev_priv);
5458
5459 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5460 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5461 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5462
160614a2
VS		 5463 /* Disable RC states. */
5464 I915_WRITE(GEN6_RC_CONTROL, 0);
5465
38807746
D		 5466 /* 2a: Program RC6 thresholds.*/
5467 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5468 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5469 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5470
5471 for_each_ring(ring, dev_priv, i)
5472 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5473 I915_WRITE(GEN6_RC_SLEEP, 0);
5474
f4f71c7d
D		 5475 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5476 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5477
5478 /* allows RC6 residency counter to work */
5479 I915_WRITE(VLV_COUNTER_CONTROL,
5480 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5481 VLV_MEDIA_RC6_COUNT_EN |
5482 VLV_RENDER_RC6_COUNT_EN));
5483
5484 /* For now we assume BIOS is allocating and populating the PCBR */
5485 pcbr = I915_READ(VLV_PCBR);
5486
38807746
D		 5487 /* 3: Enable RC6 */
5488 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5489 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5490 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5491
5492 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5493
2b6b3a09 5494 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5495 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5496 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5497 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5498 I915_WRITE(GEN6_RP_UP_EI, 66000);
5499 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5500
5501 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5502
5503 /* 5: Enable RPS */
5504 I915_WRITE(GEN6_RP_CONTROL,
5505 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5506 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5507 GEN6_RP_ENABLE |
5508 GEN6_RP_UP_BUSY_AVG |
5509 GEN6_RP_DOWN_IDLE_AVG);
5510
3ef62342
D		 5511 /* Setting Fixed Bias */
5512 val = VLV_OVERRIDE_EN |
5513 VLV_SOC_TDP_EN |
5514 CHV_BIAS_CPU_50_SOC_50;
5515 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5516
2b6b3a09
D		 5517 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5518
8d40c3ae
VS		 5519 /* RPS code assumes GPLL is used */
5520 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5521
c8e9627d 5522 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5523 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5524
5525 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5526 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5527 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5528 dev_priv->rps.cur_freq);
5529
5530 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5531 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5532 dev_priv->rps.efficient_freq);
5533
5534 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5535
59bad947 5536 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5537}
5538
0a073b84
JB		 5539static void valleyview_enable_rps(struct drm_device *dev)
5540{
5541 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5542 struct intel_engine_cs *ring;
2a5913a8 5543 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5544 int i;
5545
5546 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5547
ae48434c
ID		 5548 valleyview_check_pctx(dev_priv);
5549
0a073b84 5550 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5551 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5552 gtfifodbg);
0a073b84
JB		 5553 I915_WRITE(GTFIFODBG, gtfifodbg);
5554 }
5555
c8d9a590 5556 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5557 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5558
160614a2
VS		 5559 /* Disable RC states. */
5560 I915_WRITE(GEN6_RC_CONTROL, 0);
5561
cad725fe 5562 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5563 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5564 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5565 I915_WRITE(GEN6_RP_UP_EI, 66000);
5566 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5567
5568 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5569
5570 I915_WRITE(GEN6_RP_CONTROL,
5571 GEN6_RP_MEDIA_TURBO |
5572 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5573 GEN6_RP_MEDIA_IS_GFX |
5574 GEN6_RP_ENABLE |
5575 GEN6_RP_UP_BUSY_AVG |
5576 GEN6_RP_DOWN_IDLE_CONT);
5577
5578 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5579 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5580 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5581
5582 for_each_ring(ring, dev_priv, i)
5583 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5584
2f0aa304 5585 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5586
5587 /* allows RC6 residency counter to work */
49798eb2 5588 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5589 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5590 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5591 VLV_MEDIA_RC6_COUNT_EN |
5592 VLV_RENDER_RC6_COUNT_EN));
31685c25 5593
a2b23fe0 5594 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5595 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5596
5597 intel_print_rc6_info(dev, rc6_mode);
5598
a2b23fe0 5599 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5600
3ef62342
D		 5601 /* Setting Fixed Bias */
5602 val = VLV_OVERRIDE_EN |
5603 VLV_SOC_TDP_EN |
5604 VLV_BIAS_CPU_125_SOC_875;
5605 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5606
64936258 5607 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5608
8d40c3ae
VS		 5609 /* RPS code assumes GPLL is used */
5610 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5611
c8e9627d 5612 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5613 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5614
b39fb297 5615 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5616 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5617 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5618 dev_priv->rps.cur_freq);
0a073b84 5619
73008b98 5620 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5621 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5622 dev_priv->rps.efficient_freq);
0a073b84 5623
b39fb297 5624 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5625
59bad947 5626 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5627}
5628
dde18883
ED		 5629static unsigned long intel_pxfreq(u32 vidfreq)
5630{
5631 unsigned long freq;
5632 int div = (vidfreq & 0x3f0000) >> 16;
5633 int post = (vidfreq & 0x3000) >> 12;
5634 int pre = (vidfreq & 0x7);
5635
5636 if (!pre)
5637 return 0;
5638
5639 freq = ((div * 133333) / ((1<<post) * pre));
5640
5641 return freq;
5642}
5643
eb48eb00
DV		 5644static const struct cparams {
5645 u16 i;
5646 u16 t;
5647 u16 m;
5648 u16 c;
5649} cparams[] = {
5650 { 1, 1333, 301, 28664 },
5651 { 1, 1066, 294, 24460 },
5652 { 1, 800, 294, 25192 },
5653 { 0, 1333, 276, 27605 },
5654 { 0, 1066, 276, 27605 },
5655 { 0, 800, 231, 23784 },
5656};
5657
f531dcb2 5658static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5659{
5660 u64 total_count, diff, ret;
5661 u32 count1, count2, count3, m = 0, c = 0;
5662 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5663 int i;
5664
02d71956
DV		 5665 assert_spin_locked(&mchdev_lock);
5666
20e4d407 5667 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5668
5669 /* Prevent division-by-zero if we are asking too fast.
5670 * Also, we don't get interesting results if we are polling
5671 * faster than once in 10ms, so just return the saved value
5672 * in such cases.
5673 */
5674 if (diff1 <= 10)
20e4d407 5675 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5676
5677 count1 = I915_READ(DMIEC);
5678 count2 = I915_READ(DDREC);
5679 count3 = I915_READ(CSIEC);
5680
5681 total_count = count1 + count2 + count3;
5682
5683 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5684 if (total_count < dev_priv->ips.last_count1) {
5685 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5686 diff += total_count;
5687 } else {
20e4d407 5688 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5689 }
5690
5691 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5692 if (cparams[i].i == dev_priv->ips.c_m &&
5693 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5694 m = cparams[i].m;
5695 c = cparams[i].c;
5696 break;
5697 }
5698 }
5699
5700 diff = div_u64(diff, diff1);
5701 ret = ((m * diff) + c);
5702 ret = div_u64(ret, 10);
5703
20e4d407
DV		 5704 dev_priv->ips.last_count1 = total_count;
5705 dev_priv->ips.last_time1 = now;
eb48eb00 5706
20e4d407 5707 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5708
5709 return ret;
5710}
5711
f531dcb2
CW		 5712unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5713{
3d13ef2e 5714 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5715 unsigned long val;
5716
3d13ef2e 5717 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5718 return 0;
5719
5720 spin_lock_irq(&mchdev_lock);
5721
5722 val = __i915_chipset_val(dev_priv);
5723
5724 spin_unlock_irq(&mchdev_lock);
5725
5726 return val;
5727}
5728
eb48eb00
DV		 5729unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5730{
5731 unsigned long m, x, b;
5732 u32 tsfs;
5733
5734 tsfs = I915_READ(TSFS);
5735
5736 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5737 x = I915_READ8(TR1);
5738
5739 b = tsfs & TSFS_INTR_MASK;
5740
5741 return ((m * x) / 127) - b;
5742}
5743
d972d6ee
MK		 5744static int _pxvid_to_vd(u8 pxvid)
5745{
5746 if (pxvid == 0)
5747 return 0;
5748
5749 if (pxvid >= 8 && pxvid < 31)
5750 pxvid = 31;
5751
5752 return (pxvid + 2) * 125;
5753}
5754
5755static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5756{
3d13ef2e 5757 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5758 const int vd = _pxvid_to_vd(pxvid);
5759 const int vm = vd - 1125;
5760
3d13ef2e 5761 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5762 return vm > 0 ? vm : 0;
5763
5764 return vd;
eb48eb00
DV		 5765}
5766
02d71956 5767static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5768{
5ed0bdf2 5769 u64 now, diff, diffms;
eb48eb00
DV		 5770 u32 count;
5771
02d71956 5772 assert_spin_locked(&mchdev_lock);
eb48eb00 5773
5ed0bdf2
TG		 5774 now = ktime_get_raw_ns();
5775 diffms = now - dev_priv->ips.last_time2;
5776 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5777
5778 /* Don't divide by 0 */
eb48eb00
DV		 5779 if (!diffms)
5780 return;
5781
5782 count = I915_READ(GFXEC);
5783
20e4d407
DV		 5784 if (count < dev_priv->ips.last_count2) {
5785 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5786 diff += count;
5787 } else {
20e4d407 5788 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5789 }
5790
20e4d407
DV		 5791 dev_priv->ips.last_count2 = count;
5792 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5793
5794 /* More magic constants... */
5795 diff = diff * 1181;
5796 diff = div_u64(diff, diffms * 10);
20e4d407 5797 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5798}
5799
02d71956
DV		 5800void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5801{
3d13ef2e
DL		 5802 struct drm_device *dev = dev_priv->dev;
5803
5804 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5805 return;
5806
9270388e 5807 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5808
5809 __i915_update_gfx_val(dev_priv);
5810
9270388e 5811 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5812}
5813
f531dcb2 5814static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5815{
5816 unsigned long t, corr, state1, corr2, state2;
5817 u32 pxvid, ext_v;
5818
02d71956
DV		 5819 assert_spin_locked(&mchdev_lock);
5820
b39fb297 5821 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5822 pxvid = (pxvid >> 24) & 0x7f;
5823 ext_v = pvid_to_extvid(dev_priv, pxvid);
5824
5825 state1 = ext_v;
5826
5827 t = i915_mch_val(dev_priv);
5828
5829 /* Revel in the empirically derived constants */
5830
5831 /* Correction factor in 1/100000 units */
5832 if (t > 80)
5833 corr = ((t * 2349) + 135940);
5834 else if (t >= 50)
5835 corr = ((t * 964) + 29317);
5836 else /* < 50 */
5837 corr = ((t * 301) + 1004);
5838
5839 corr = corr * ((150142 * state1) / 10000 - 78642);
5840 corr /= 100000;
20e4d407 5841 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5842
5843 state2 = (corr2 * state1) / 10000;
5844 state2 /= 100; /* convert to mW */
5845
02d71956 5846 __i915_update_gfx_val(dev_priv);
eb48eb00 5847
20e4d407 5848 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5849}
5850
f531dcb2
CW		 5851unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5852{
3d13ef2e 5853 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5854 unsigned long val;
5855
3d13ef2e 5856 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5857 return 0;
5858
5859 spin_lock_irq(&mchdev_lock);
5860
5861 val = __i915_gfx_val(dev_priv);
5862
5863 spin_unlock_irq(&mchdev_lock);
5864
5865 return val;
5866}
5867
eb48eb00
DV		 5868/**
5869 * i915_read_mch_val - return value for IPS use
5870 *
5871 * Calculate and return a value for the IPS driver to use when deciding whether
5872 * we have thermal and power headroom to increase CPU or GPU power budget.
5873 */
5874unsigned long i915_read_mch_val(void)
5875{
5876 struct drm_i915_private *dev_priv;
5877 unsigned long chipset_val, graphics_val, ret = 0;
5878
9270388e 5879 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5880 if (!i915_mch_dev)
5881 goto out_unlock;
5882 dev_priv = i915_mch_dev;
5883
f531dcb2
CW		 5884 chipset_val = __i915_chipset_val(dev_priv);
5885 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5886
5887 ret = chipset_val + graphics_val;
5888
5889out_unlock:
9270388e 5890 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5891
5892 return ret;
5893}
5894EXPORT_SYMBOL_GPL(i915_read_mch_val);
5895
5896/**
5897 * i915_gpu_raise - raise GPU frequency limit
5898 *
5899 * Raise the limit; IPS indicates we have thermal headroom.
5900 */
5901bool i915_gpu_raise(void)
5902{
5903 struct drm_i915_private *dev_priv;
5904 bool ret = true;
5905
9270388e 5906 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5907 if (!i915_mch_dev) {
5908 ret = false;
5909 goto out_unlock;
5910 }
5911 dev_priv = i915_mch_dev;
5912
20e4d407
DV		 5913 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5914 dev_priv->ips.max_delay--;
eb48eb00
DV		 5915
5916out_unlock:
9270388e 5917 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5918
5919 return ret;
5920}
5921EXPORT_SYMBOL_GPL(i915_gpu_raise);
5922
5923/**
5924 * i915_gpu_lower - lower GPU frequency limit
5925 *
5926 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5927 * frequency maximum.
5928 */
5929bool i915_gpu_lower(void)
5930{
5931 struct drm_i915_private *dev_priv;
5932 bool ret = true;
5933
9270388e 5934 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5935 if (!i915_mch_dev) {
5936 ret = false;
5937 goto out_unlock;
5938 }
5939 dev_priv = i915_mch_dev;
5940
20e4d407
DV		 5941 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5942 dev_priv->ips.max_delay++;
eb48eb00
DV		 5943
5944out_unlock:
9270388e 5945 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5946
5947 return ret;
5948}
5949EXPORT_SYMBOL_GPL(i915_gpu_lower);
5950
5951/**
5952 * i915_gpu_busy - indicate GPU business to IPS
5953 *
5954 * Tell the IPS driver whether or not the GPU is busy.
5955 */
5956bool i915_gpu_busy(void)
5957{
5958 struct drm_i915_private *dev_priv;
a4872ba6 5959 struct intel_engine_cs *ring;
eb48eb00 5960 bool ret = false;
f047e395 5961 int i;
eb48eb00 5962
9270388e 5963 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5964 if (!i915_mch_dev)
5965 goto out_unlock;
5966 dev_priv = i915_mch_dev;
5967
f047e395
CW		 5968 for_each_ring(ring, dev_priv, i)
5969 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5970
5971out_unlock:
9270388e 5972 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5973
5974 return ret;
5975}
5976EXPORT_SYMBOL_GPL(i915_gpu_busy);
5977
5978/**
5979 * i915_gpu_turbo_disable - disable graphics turbo
5980 *
5981 * Disable graphics turbo by resetting the max frequency and setting the
5982 * current frequency to the default.
5983 */
5984bool i915_gpu_turbo_disable(void)
5985{
5986 struct drm_i915_private *dev_priv;
5987 bool ret = true;
5988
9270388e 5989 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5990 if (!i915_mch_dev) {
5991 ret = false;
5992 goto out_unlock;
5993 }
5994 dev_priv = i915_mch_dev;
5995
20e4d407 5996 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5997
20e4d407 5998 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5999 ret = false;
6000
6001out_unlock:
9270388e 6002 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6003
6004 return ret;
6005}
6006EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6007
6008/**
6009 * Tells the intel_ips driver that the i915 driver is now loaded, if
6010 * IPS got loaded first.
6011 *
6012 * This awkward dance is so that neither module has to depend on the
6013 * other in order for IPS to do the appropriate communication of
6014 * GPU turbo limits to i915.
6015 */
6016static void
6017ips_ping_for_i915_load(void)
6018{
6019 void (*link)(void);
6020
6021 link = symbol_get(ips_link_to_i915_driver);
6022 if (link) {
6023 link();
6024 symbol_put(ips_link_to_i915_driver);
6025 }
6026}
6027
6028void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6029{
02d71956
DV		 6030 /* We only register the i915 ips part with intel-ips once everything is
6031 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6032 spin_lock_irq(&mchdev_lock);
eb48eb00 6033 i915_mch_dev = dev_priv;
9270388e 6034 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6035
6036 ips_ping_for_i915_load();
6037}
6038
6039void intel_gpu_ips_teardown(void)
6040{
9270388e 6041 spin_lock_irq(&mchdev_lock);
eb48eb00 6042 i915_mch_dev = NULL;
9270388e 6043 spin_unlock_irq(&mchdev_lock);
eb48eb00 6044}
76c3552f 6045
8090c6b9 6046static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6047{
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049 u32 lcfuse;
6050 u8 pxw[16];
6051 int i;
6052
6053 /* Disable to program */
6054 I915_WRITE(ECR, 0);
6055 POSTING_READ(ECR);
6056
6057 /* Program energy weights for various events */
6058 I915_WRITE(SDEW, 0x15040d00);
6059 I915_WRITE(CSIEW0, 0x007f0000);
6060 I915_WRITE(CSIEW1, 0x1e220004);
6061 I915_WRITE(CSIEW2, 0x04000004);
6062
6063 for (i = 0; i < 5; i++)
6064 I915_WRITE(PEW + (i * 4), 0);
6065 for (i = 0; i < 3; i++)
6066 I915_WRITE(DEW + (i * 4), 0);
6067
6068 /* Program P-state weights to account for frequency power adjustment */
6069 for (i = 0; i < 16; i++) {
6070 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6071 unsigned long freq = intel_pxfreq(pxvidfreq);
6072 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6073 PXVFREQ_PX_SHIFT;
6074 unsigned long val;
6075
6076 val = vid * vid;
6077 val *= (freq / 1000);
6078 val *= 255;
6079 val /= (127*127*900);
6080 if (val > 0xff)
6081 DRM_ERROR("bad pxval: %ld\n", val);
6082 pxw[i] = val;
6083 }
6084 /* Render standby states get 0 weight */
6085 pxw[14] = 0;
6086 pxw[15] = 0;
6087
6088 for (i = 0; i < 4; i++) {
6089 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6090 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6091 I915_WRITE(PXW + (i * 4), val);
6092 }
6093
6094 /* Adjust magic regs to magic values (more experimental results) */
6095 I915_WRITE(OGW0, 0);
6096 I915_WRITE(OGW1, 0);
6097 I915_WRITE(EG0, 0x00007f00);
6098 I915_WRITE(EG1, 0x0000000e);
6099 I915_WRITE(EG2, 0x000e0000);
6100 I915_WRITE(EG3, 0x68000300);
6101 I915_WRITE(EG4, 0x42000000);
6102 I915_WRITE(EG5, 0x00140031);
6103 I915_WRITE(EG6, 0);
6104 I915_WRITE(EG7, 0);
6105
6106 for (i = 0; i < 8; i++)
6107 I915_WRITE(PXWL + (i * 4), 0);
6108
6109 /* Enable PMON + select events */
6110 I915_WRITE(ECR, 0x80000019);
6111
6112 lcfuse = I915_READ(LCFUSE02);
6113
20e4d407 6114 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6115}
6116
ae48434c
ID		 6117void intel_init_gt_powersave(struct drm_device *dev)
6118{
e6069ca8
ID		 6119 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6120
38807746
D		 6121 if (IS_CHERRYVIEW(dev))
6122 cherryview_init_gt_powersave(dev);
6123 else if (IS_VALLEYVIEW(dev))
4e80519e 6124 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6125}
6126
6127void intel_cleanup_gt_powersave(struct drm_device *dev)
6128{
38807746
D		 6129 if (IS_CHERRYVIEW(dev))
6130 return;
6131 else if (IS_VALLEYVIEW(dev))
4e80519e 6132 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6133}
6134
dbea3cea
ID		 6135static void gen6_suspend_rps(struct drm_device *dev)
6136{
6137 struct drm_i915_private *dev_priv = dev->dev_private;
6138
6139 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6140
4c2a8897 6141 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6142}
6143
156c7ca0
JB		 6144/**
6145 * intel_suspend_gt_powersave - suspend PM work and helper threads
6146 * @dev: drm device
6147 *
6148 * We don't want to disable RC6 or other features here, we just want
6149 * to make sure any work we've queued has finished and won't bother
6150 * us while we're suspended.
6151 */
6152void intel_suspend_gt_powersave(struct drm_device *dev)
6153{
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155
d4d70aa5
ID		 6156 if (INTEL_INFO(dev)->gen < 6)
6157 return;
6158
dbea3cea 6159 gen6_suspend_rps(dev);
b47adc17
D		 6160
6161 /* Force GPU to min freq during suspend */
6162 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6163}
6164
8090c6b9
DV		 6165void intel_disable_gt_powersave(struct drm_device *dev)
6166{
1a01ab3b
JB		 6167 struct drm_i915_private *dev_priv = dev->dev_private;
6168
930ebb46 6169 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6170 ironlake_disable_drps(dev);
38807746 6171 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6172 intel_suspend_gt_powersave(dev);
e494837a 6173
4fc688ce 6174 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6175 if (INTEL_INFO(dev)->gen >= 9)
6176 gen9_disable_rps(dev);
6177 else if (IS_CHERRYVIEW(dev))
38807746
D		 6178 cherryview_disable_rps(dev);
6179 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6180 valleyview_disable_rps(dev);
6181 else
6182 gen6_disable_rps(dev);
e534770a 6183
c0951f0c 6184 dev_priv->rps.enabled = false;
4fc688ce 6185 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6186 }
8090c6b9
DV		 6187}
6188
1a01ab3b
JB		 6189static void intel_gen6_powersave_work(struct work_struct *work)
6190{
6191 struct drm_i915_private *dev_priv =
6192 container_of(work, struct drm_i915_private,
6193 rps.delayed_resume_work.work);
6194 struct drm_device *dev = dev_priv->dev;
6195
4fc688ce 6196 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6197
4c2a8897 6198 gen6_reset_rps_interrupts(dev);
3cc134e3 6199
38807746
D		 6200 if (IS_CHERRYVIEW(dev)) {
6201 cherryview_enable_rps(dev);
6202 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6203 valleyview_enable_rps(dev);
20e49366 6204 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6205 gen9_enable_rc6(dev);
20e49366 6206 gen9_enable_rps(dev);
b6fef0ef 6207 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6208 } else if (IS_BROADWELL(dev)) {
6209 gen8_enable_rps(dev);
c2bc2fc5 6210 __gen6_update_ring_freq(dev);
0a073b84
JB		 6211 } else {
6212 gen6_enable_rps(dev);
c2bc2fc5 6213 __gen6_update_ring_freq(dev);
0a073b84 6214 }
aed242ff
CW		 6215
6216 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6217 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6218
6219 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6220 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6221
c0951f0c 6222 dev_priv->rps.enabled = true;
3cc134e3 6223
4c2a8897 6224 gen6_enable_rps_interrupts(dev);
3cc134e3 6225
4fc688ce 6226 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6227
6228 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6229}
6230
8090c6b9
DV		 6231void intel_enable_gt_powersave(struct drm_device *dev)
6232{
1a01ab3b
JB		 6233 struct drm_i915_private *dev_priv = dev->dev_private;
6234
f61018b1
YZ		 6235 /* Powersaving is controlled by the host when inside a VM */
6236 if (intel_vgpu_active(dev))
6237 return;
6238
8090c6b9 6239 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6240 mutex_lock(&dev->struct_mutex);
8090c6b9 6241 ironlake_enable_drps(dev);
8090c6b9 6242 intel_init_emon(dev);
dc1d0136 6243 mutex_unlock(&dev->struct_mutex);
38807746 6244 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6245 /*
6246 * PCU communication is slow and this doesn't need to be
6247 * done at any specific time, so do this out of our fast path
6248 * to make resume and init faster.
c6df39b5
ID		 6249 *
6250 * We depend on the HW RC6 power context save/restore
6251 * mechanism when entering D3 through runtime PM suspend. So
6252 * disable RPM until RPS/RC6 is properly setup. We can only
6253 * get here via the driver load/system resume/runtime resume
6254 * paths, so the _noresume version is enough (and in case of
6255 * runtime resume it's necessary).
1a01ab3b 6256 */
c6df39b5
ID		 6257 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6258 round_jiffies_up_relative(HZ)))
6259 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6260 }
6261}
6262
c6df39b5
ID		 6263void intel_reset_gt_powersave(struct drm_device *dev)
6264{
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266
dbea3cea
ID		 6267 if (INTEL_INFO(dev)->gen < 6)
6268 return;
6269
6270 gen6_suspend_rps(dev);
c6df39b5 6271 dev_priv->rps.enabled = false;
c6df39b5
ID		 6272}
6273
3107bd48
DV		 6274static void ibx_init_clock_gating(struct drm_device *dev)
6275{
6276 struct drm_i915_private *dev_priv = dev->dev_private;
6277
6278 /*
6279 * On Ibex Peak and Cougar Point, we need to disable clock
6280 * gating for the panel power sequencer or it will fail to
6281 * start up when no ports are active.
6282 */
6283 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6284}
6285
0e088b8f
VS		 6286static void g4x_disable_trickle_feed(struct drm_device *dev)
6287{
6288 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6289 enum pipe pipe;
0e088b8f 6290
055e393f 6291 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6292 I915_WRITE(DSPCNTR(pipe),
6293 I915_READ(DSPCNTR(pipe)) |
6294 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6295
6296 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6297 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6298 }
6299}
6300
017636cc
VS		 6301static void ilk_init_lp_watermarks(struct drm_device *dev)
6302{
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304
6305 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6306 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6307 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6308
6309 /*
6310 * Don't touch WM1S_LP_EN here.
6311 * Doing so could cause underruns.
6312 */
6313}
6314
1fa61106 6315static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6316{
6317 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6318 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6319
f1e8fa56
DL		 6320 /*
6321 * Required for FBC
6322 * WaFbcDisableDpfcClockGating:ilk
6323 */
4d47e4f5
DL		 6324 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6325 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6326 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6327
6328 I915_WRITE(PCH_3DCGDIS0,
6329 MARIUNIT_CLOCK_GATE_DISABLE |
6330 SVSMUNIT_CLOCK_GATE_DISABLE);
6331 I915_WRITE(PCH_3DCGDIS1,
6332 VFMUNIT_CLOCK_GATE_DISABLE);
6333
6f1d69b0
ED		 6334 /*
6335 * According to the spec the following bits should be set in
6336 * order to enable memory self-refresh
6337 * The bit 22/21 of 0x42004
6338 * The bit 5 of 0x42020
6339 * The bit 15 of 0x45000
6340 */
6341 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6342 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6343 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6344 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6345 I915_WRITE(DISP_ARB_CTL,
6346 (I915_READ(DISP_ARB_CTL) |
6347 DISP_FBC_WM_DIS));
017636cc
VS		 6348
6349 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6350
6351 /*
6352 * Based on the document from hardware guys the following bits
6353 * should be set unconditionally in order to enable FBC.
6354 * The bit 22 of 0x42000
6355 * The bit 22 of 0x42004
6356 * The bit 7,8,9 of 0x42020.
6357 */
6358 if (IS_IRONLAKE_M(dev)) {
4bb35334 6359 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6360 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6361 I915_READ(ILK_DISPLAY_CHICKEN1) |
6362 ILK_FBCQ_DIS);
6363 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6364 I915_READ(ILK_DISPLAY_CHICKEN2) |
6365 ILK_DPARB_GATE);
6f1d69b0
ED		 6366 }
6367
4d47e4f5
DL		 6368 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6369
6f1d69b0
ED		 6370 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6371 I915_READ(ILK_DISPLAY_CHICKEN2) |
6372 ILK_ELPIN_409_SELECT);
6373 I915_WRITE(_3D_CHICKEN2,
6374 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6375 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6376
ecdb4eb7 6377 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6378 I915_WRITE(CACHE_MODE_0,
6379 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6380
4e04632e
AG		 6381 /* WaDisable_RenderCache_OperationalFlush:ilk */
6382 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6383
0e088b8f 6384 g4x_disable_trickle_feed(dev);
bdad2b2f 6385
3107bd48
DV		 6386 ibx_init_clock_gating(dev);
6387}
6388
6389static void cpt_init_clock_gating(struct drm_device *dev)
6390{
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6392 int pipe;
3f704fa2 6393 uint32_t val;
3107bd48
DV		 6394
6395 /*
6396 * On Ibex Peak and Cougar Point, we need to disable clock
6397 * gating for the panel power sequencer or it will fail to
6398 * start up when no ports are active.
6399 */
cd664078
JB		 6400 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6401 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6402 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6403 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6404 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6405 /* The below fixes the weird display corruption, a few pixels shifted
6406 * downward, on (only) LVDS of some HP laptops with IVY.
6407 */
055e393f 6408 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6409 val = I915_READ(TRANS_CHICKEN2(pipe));
6410 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6411 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6412 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6413 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6414 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6415 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6416 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6417 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6418 }
3107bd48 6419 /* WADP0ClockGatingDisable */
055e393f 6420 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6421 I915_WRITE(TRANS_CHICKEN1(pipe),
6422 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6423 }
6f1d69b0
ED		 6424}
6425
1d7aaa0c
DV		 6426static void gen6_check_mch_setup(struct drm_device *dev)
6427{
6428 struct drm_i915_private *dev_priv = dev->dev_private;
6429 uint32_t tmp;
6430
6431 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6432 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6433 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6434 tmp);
1d7aaa0c
DV		 6435}
6436
1fa61106 6437static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6438{
6439 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6440 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6441
231e54f6 6442 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6443
6444 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6445 I915_READ(ILK_DISPLAY_CHICKEN2) |
6446 ILK_ELPIN_409_SELECT);
6447
ecdb4eb7 6448 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6449 I915_WRITE(_3D_CHICKEN,
6450 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6451
4e04632e
AG		 6452 /* WaDisable_RenderCache_OperationalFlush:snb */
6453 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6454
8d85d272
VS		 6455 /*
6456 * BSpec recoomends 8x4 when MSAA is used,
6457 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6458 *
6459 * Note that PS/WM thread counts depend on the WIZ hashing
6460 * disable bit, which we don't touch here, but it's good
6461 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6462 */
6463 I915_WRITE(GEN6_GT_MODE,
98533251 6464 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6465
017636cc 6466 ilk_init_lp_watermarks(dev);
6f1d69b0 6467
6f1d69b0 6468 I915_WRITE(CACHE_MODE_0,
50743298 6469 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6470
6471 I915_WRITE(GEN6_UCGCTL1,
6472 I915_READ(GEN6_UCGCTL1) |
6473 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6474 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6475
6476 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6477 * gating disable must be set. Failure to set it results in
6478 * flickering pixels due to Z write ordering failures after
6479 * some amount of runtime in the Mesa "fire" demo, and Unigine
6480 * Sanctuary and Tropics, and apparently anything else with
6481 * alpha test or pixel discard.
6482 *
6483 * According to the spec, bit 11 (RCCUNIT) must also be set,
6484 * but we didn't debug actual testcases to find it out.
0f846f81 6485 *
ef59318c
VS		 6486 * WaDisableRCCUnitClockGating:snb
6487 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6488 */
6489 I915_WRITE(GEN6_UCGCTL2,
6490 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6491 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6492
5eb146dd 6493 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6494 I915_WRITE(_3D_CHICKEN3,
6495 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6496
e927ecde
VS		 6497 /*
6498 * Bspec says:
6499 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6500 * 3DSTATE_SF number of SF output attributes is more than 16."
6501 */
6502 I915_WRITE(_3D_CHICKEN3,
6503 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6504
6f1d69b0
ED		 6505 /*
6506 * According to the spec the following bits should be
6507 * set in order to enable memory self-refresh and fbc:
6508 * The bit21 and bit22 of 0x42000
6509 * The bit21 and bit22 of 0x42004
6510 * The bit5 and bit7 of 0x42020
6511 * The bit14 of 0x70180
6512 * The bit14 of 0x71180
4bb35334
DL		 6513 *
6514 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6515 */
6516 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6517 I915_READ(ILK_DISPLAY_CHICKEN1) |
6518 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6519 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6520 I915_READ(ILK_DISPLAY_CHICKEN2) |
6521 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6522 I915_WRITE(ILK_DSPCLK_GATE_D,
6523 I915_READ(ILK_DSPCLK_GATE_D) |
6524 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6525 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6526
0e088b8f 6527 g4x_disable_trickle_feed(dev);
f8f2ac9a 6528
3107bd48 6529 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6530
6531 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6532}
6533
6534static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6535{
6536 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6537
3aad9059 6538 /*
46680e0a 6539 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6540 *
6541 * This actually overrides the dispatch
6542 * mode for all thread types.
6543 */
6f1d69b0
ED		 6544 reg &= ~GEN7_FF_SCHED_MASK;
6545 reg |= GEN7_FF_TS_SCHED_HW;
6546 reg |= GEN7_FF_VS_SCHED_HW;
6547 reg |= GEN7_FF_DS_SCHED_HW;
6548
6549 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6550}
6551
17a303ec
PZ		 6552static void lpt_init_clock_gating(struct drm_device *dev)
6553{
6554 struct drm_i915_private *dev_priv = dev->dev_private;
6555
6556 /*
6557 * TODO: this bit should only be enabled when really needed, then
6558 * disabled when not needed anymore in order to save power.
6559 */
6560 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6561 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6562 I915_READ(SOUTH_DSPCLK_GATE_D) |
6563 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6564
6565 /* WADPOClockGatingDisable:hsw */
6566 I915_WRITE(_TRANSA_CHICKEN1,
6567 I915_READ(_TRANSA_CHICKEN1) |
6568 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6569}
6570
7d708ee4
ID		 6571static void lpt_suspend_hw(struct drm_device *dev)
6572{
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6574
6575 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6576 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6577
6578 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6579 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6580 }
6581}
6582
47c2bd97 6583static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6584{
6585 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6586 enum pipe pipe;
4d487cff 6587 uint32_t misccpctl;
1020a5c2 6588
7ad0dbab 6589 ilk_init_lp_watermarks(dev);
50ed5fbd 6590
ab57fff1 6591 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6592 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6593
ab57fff1 6594 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6595 I915_WRITE(CHICKEN_PAR1_1,
6596 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6597
ab57fff1 6598 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6599 for_each_pipe(dev_priv, pipe) {
07d27e20 6600 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6601 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6602 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6603 }
63801f21 6604
ab57fff1
BW		 6605 /* WaVSRefCountFullforceMissDisable:bdw */
6606 /* WaDSRefCountFullforceMissDisable:bdw */
6607 I915_WRITE(GEN7_FF_THREAD_MODE,
6608 I915_READ(GEN7_FF_THREAD_MODE) &
6609 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6610
295e8bb7
VS		 6611 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6612 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6613
6614 /* WaDisableSDEUnitClockGating:bdw */
6615 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6616 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6617
4d487cff
VS		 6618 /*
6619 * WaProgramL3SqcReg1Default:bdw
6620 * WaTempDisableDOPClkGating:bdw
6621 */
6622 misccpctl = I915_READ(GEN7_MISCCPCTL);
6623 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6624 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6625 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6626
6d50b065
VS		 6627 /*
6628 * WaGttCachingOffByDefault:bdw
6629 * GTT cache may not work with big pages, so if those
6630 * are ever enabled GTT cache may need to be disabled.
6631 */
6632 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6633
89d6b2b8 6634 lpt_init_clock_gating(dev);
1020a5c2
BW		 6635}
6636
cad2a2d7
ED		 6637static void haswell_init_clock_gating(struct drm_device *dev)
6638{
6639 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6640
017636cc 6641 ilk_init_lp_watermarks(dev);
cad2a2d7 6642
f3fc4884
FJ		 6643 /* L3 caching of data atomics doesn't work -- disable it. */
6644 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6645 I915_WRITE(HSW_ROW_CHICKEN3,
6646 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6647
ecdb4eb7 6648 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6649 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6650 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6651 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6652
e36ea7ff
VS		 6653 /* WaVSRefCountFullforceMissDisable:hsw */
6654 I915_WRITE(GEN7_FF_THREAD_MODE,
6655 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6656
4e04632e
AG		 6657 /* WaDisable_RenderCache_OperationalFlush:hsw */
6658 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6659
fe27c606
CW		 6660 /* enable HiZ Raw Stall Optimization */
6661 I915_WRITE(CACHE_MODE_0_GEN7,
6662 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6663
ecdb4eb7 6664 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6665 I915_WRITE(CACHE_MODE_1,
6666 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6667
a12c4967
VS		 6668 /*
6669 * BSpec recommends 8x4 when MSAA is used,
6670 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6671 *
6672 * Note that PS/WM thread counts depend on the WIZ hashing
6673 * disable bit, which we don't touch here, but it's good
6674 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6675 */
6676 I915_WRITE(GEN7_GT_MODE,
98533251 6677 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6678
94411593
KG		 6679 /* WaSampleCChickenBitEnable:hsw */
6680 I915_WRITE(HALF_SLICE_CHICKEN3,
6681 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6682
ecdb4eb7 6683 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6684 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6685
90a88643
PZ		 6686 /* WaRsPkgCStateDisplayPMReq:hsw */
6687 I915_WRITE(CHICKEN_PAR1_1,
6688 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6689
17a303ec 6690 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6691}
6692
1fa61106 6693static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6694{
6695 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6696 uint32_t snpcr;
6f1d69b0 6697
017636cc 6698 ilk_init_lp_watermarks(dev);
6f1d69b0 6699
231e54f6 6700 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6701
ecdb4eb7 6702 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6703 I915_WRITE(_3D_CHICKEN3,
6704 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6705
ecdb4eb7 6706 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6707 I915_WRITE(IVB_CHICKEN3,
6708 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6709 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6710
ecdb4eb7 6711 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6712 if (IS_IVB_GT1(dev))
6713 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6714 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6715
4e04632e
AG		 6716 /* WaDisable_RenderCache_OperationalFlush:ivb */
6717 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6718
ecdb4eb7 6719 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6720 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6721 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6722
ecdb4eb7 6723 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6724 I915_WRITE(GEN7_L3CNTLREG1,
6725 GEN7_WA_FOR_GEN7_L3_CONTROL);
6726 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6727 GEN7_WA_L3_CHICKEN_MODE);
6728 if (IS_IVB_GT1(dev))
6729 I915_WRITE(GEN7_ROW_CHICKEN2,
6730 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6731 else {
6732 /* must write both registers */
6733 I915_WRITE(GEN7_ROW_CHICKEN2,
6734 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6735 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6736 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6737 }
6f1d69b0 6738
ecdb4eb7 6739 /* WaForceL3Serialization:ivb */
61939d97
JB		 6740 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6741 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6742
1b80a19a 6743 /*
0f846f81 6744 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6745 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6746 */
6747 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6748 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6749
ecdb4eb7 6750 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6751 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6752 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6753 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6754
0e088b8f 6755 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6756
6757 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6758
22721343
CW		 6759 if (0) { /* causes HiZ corruption on ivb:gt1 */
6760 /* enable HiZ Raw Stall Optimization */
6761 I915_WRITE(CACHE_MODE_0_GEN7,
6762 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6763 }
116f2b6d 6764
ecdb4eb7 6765 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6766 I915_WRITE(CACHE_MODE_1,
6767 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6768
a607c1a4
VS		 6769 /*
6770 * BSpec recommends 8x4 when MSAA is used,
6771 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6772 *
6773 * Note that PS/WM thread counts depend on the WIZ hashing
6774 * disable bit, which we don't touch here, but it's good
6775 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6776 */
6777 I915_WRITE(GEN7_GT_MODE,
98533251 6778 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6779
20848223
BW		 6780 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6781 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6782 snpcr |= GEN6_MBC_SNPCR_MED;
6783 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6784
ab5c608b
BW		 6785 if (!HAS_PCH_NOP(dev))
6786 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6787
6788 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6789}
6790
c6beb13e
VS		 6791static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6792{
6793 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6794
6795 /*
6796 * Disable trickle feed and enable pnd deadline calculation
6797 */
6798 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6799 I915_WRITE(CBR1_VLV, 0);
6800}
6801
1fa61106 6802static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6803{
6804 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6805
c6beb13e 6806 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6807
ecdb4eb7 6808 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6809 I915_WRITE(_3D_CHICKEN3,
6810 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6811
ecdb4eb7 6812 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6813 I915_WRITE(IVB_CHICKEN3,
6814 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6815 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6816
fad7d36e 6817 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6818 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6819 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6820 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6821 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6822
4e04632e
AG		 6823 /* WaDisable_RenderCache_OperationalFlush:vlv */
6824 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6825
ecdb4eb7 6826 /* WaForceL3Serialization:vlv */
61939d97
JB		 6827 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6828 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6829
ecdb4eb7 6830 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6831 I915_WRITE(GEN7_ROW_CHICKEN2,
6832 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6833
ecdb4eb7 6834 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6835 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6836 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6837 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6838
46680e0a
VS		 6839 gen7_setup_fixed_func_scheduler(dev_priv);
6840
3c0edaeb 6841 /*
0f846f81 6842 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6843 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6844 */
6845 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6846 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6847
c98f5062
AG		 6848 /* WaDisableL3Bank2xClockGate:vlv
6849 * Disabling L3 clock gating- MMIO 940c[25] = 1
6850 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6851 I915_WRITE(GEN7_UCGCTL4,
6852 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6853
afd58e79
VS		 6854 /*
6855 * BSpec says this must be set, even though
6856 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6857 */
6b26c86d
DV		 6858 I915_WRITE(CACHE_MODE_1,
6859 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6860
da2518f9
VS		 6861 /*
6862 * BSpec recommends 8x4 when MSAA is used,
6863 * however in practice 16x4 seems fastest.
6864 *
6865 * Note that PS/WM thread counts depend on the WIZ hashing
6866 * disable bit, which we don't touch here, but it's good
6867 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6868 */
6869 I915_WRITE(GEN7_GT_MODE,
6870 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6871
031994ee
VS		 6872 /*
6873 * WaIncreaseL3CreditsForVLVB0:vlv
6874 * This is the hardware default actually.
6875 */
6876 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6877
2d809570 6878 /*
ecdb4eb7 6879 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6880 * Disable clock gating on th GCFG unit to prevent a delay
6881 * in the reporting of vblank events.
6882 */
7a0d1eed 6883 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6884}
6885
a4565da8
VS		 6886static void cherryview_init_clock_gating(struct drm_device *dev)
6887{
6888 struct drm_i915_private *dev_priv = dev->dev_private;
6889
c6beb13e 6890 vlv_init_display_clock_gating(dev_priv);
dd811e70 6891
232ce337
VS		 6892 /* WaVSRefCountFullforceMissDisable:chv */
6893 /* WaDSRefCountFullforceMissDisable:chv */
6894 I915_WRITE(GEN7_FF_THREAD_MODE,
6895 I915_READ(GEN7_FF_THREAD_MODE) &
6896 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6897
6898 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6899 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6900 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6901
6902 /* WaDisableCSUnitClockGating:chv */
6903 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6904 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6905
6906 /* WaDisableSDEUnitClockGating:chv */
6907 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6908 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6909
6910 /*
6911 * GTT cache may not work with big pages, so if those
6912 * are ever enabled GTT cache may need to be disabled.
6913 */
6914 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6915}
6916
1fa61106 6917static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6918{
6919 struct drm_i915_private *dev_priv = dev->dev_private;
6920 uint32_t dspclk_gate;
6921
6922 I915_WRITE(RENCLK_GATE_D1, 0);
6923 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6924 GS_UNIT_CLOCK_GATE_DISABLE |
6925 CL_UNIT_CLOCK_GATE_DISABLE);
6926 I915_WRITE(RAMCLK_GATE_D, 0);
6927 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6928 OVRUNIT_CLOCK_GATE_DISABLE |
6929 OVCUNIT_CLOCK_GATE_DISABLE;
6930 if (IS_GM45(dev))
6931 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6932 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6933
6934 /* WaDisableRenderCachePipelinedFlush */
6935 I915_WRITE(CACHE_MODE_0,
6936 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6937
4e04632e
AG		 6938 /* WaDisable_RenderCache_OperationalFlush:g4x */
6939 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6940
0e088b8f 6941 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6942}
6943
1fa61106 6944static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6945{
6946 struct drm_i915_private *dev_priv = dev->dev_private;
6947
6948 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6949 I915_WRITE(RENCLK_GATE_D2, 0);
6950 I915_WRITE(DSPCLK_GATE_D, 0);
6951 I915_WRITE(RAMCLK_GATE_D, 0);
6952 I915_WRITE16(DEUC, 0);
20f94967
VS		 6953 I915_WRITE(MI_ARB_STATE,
6954 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6955
6956 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6957 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6958}
6959
1fa61106 6960static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6961{
6962 struct drm_i915_private *dev_priv = dev->dev_private;
6963
6964 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6965 I965_RCC_CLOCK_GATE_DISABLE |
6966 I965_RCPB_CLOCK_GATE_DISABLE |
6967 I965_ISC_CLOCK_GATE_DISABLE |
6968 I965_FBC_CLOCK_GATE_DISABLE);
6969 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6970 I915_WRITE(MI_ARB_STATE,
6971 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6972
6973 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6974 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6975}
6976
1fa61106 6977static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6978{
6979 struct drm_i915_private *dev_priv = dev->dev_private;
6980 u32 dstate = I915_READ(D_STATE);
6981
6982 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6983 DSTATE_DOT_CLOCK_GATING;
6984 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6985
6986 if (IS_PINEVIEW(dev))
6987 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6988
6989 /* IIR "flip pending" means done if this bit is set */
6990 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6991
6992 /* interrupts should cause a wake up from C3 */
3299254f 6993 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6994
6995 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6996 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6997
6998 I915_WRITE(MI_ARB_STATE,
6999 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7000}
7001
1fa61106 7002static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7003{
7004 struct drm_i915_private *dev_priv = dev->dev_private;
7005
7006 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7007
7008 /* interrupts should cause a wake up from C3 */
7009 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7010 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7011
7012 I915_WRITE(MEM_MODE,
7013 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7014}
7015
1fa61106 7016static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7017{
7018 struct drm_i915_private *dev_priv = dev->dev_private;
7019
7020 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7021
7022 I915_WRITE(MEM_MODE,
7023 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7024 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7025}
7026
6f1d69b0
ED		 7027void intel_init_clock_gating(struct drm_device *dev)
7028{
7029 struct drm_i915_private *dev_priv = dev->dev_private;
7030
c57e3551
DL		 7031 if (dev_priv->display.init_clock_gating)
7032 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7033}
7034
7d708ee4
ID		 7035void intel_suspend_hw(struct drm_device *dev)
7036{
7037 if (HAS_PCH_LPT(dev))
7038 lpt_suspend_hw(dev);
7039}
7040
1fa61106
ED		 7041/* Set up chip specific power management-related functions */
7042void intel_init_pm(struct drm_device *dev)
7043{
7044 struct drm_i915_private *dev_priv = dev->dev_private;
7045
7ff0ebcc 7046 intel_fbc_init(dev_priv);
1fa61106 7047
c921aba8
DV		 7048 /* For cxsr */
7049 if (IS_PINEVIEW(dev))
7050 i915_pineview_get_mem_freq(dev);
7051 else if (IS_GEN5(dev))
7052 i915_ironlake_get_mem_freq(dev);
7053
1fa61106 7054 /* For FIFO watermark updates */
f5ed50cb 7055 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7056 skl_setup_wm_latency(dev);
7057
a82abe43
ID		 7058 if (IS_BROXTON(dev))
7059 dev_priv->display.init_clock_gating =
7060 bxt_init_clock_gating;
7061 else if (IS_SKYLAKE(dev))
7062 dev_priv->display.init_clock_gating =
7063 skl_init_clock_gating;
2d41c0b5
PB		 7064 dev_priv->display.update_wm = skl_update_wm;
7065 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 7066 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7067 ilk_setup_wm_latency(dev);
53615a5e 7068
bd602544
VS		 7069 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7070 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7071 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7072 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7073 dev_priv->display.update_wm = ilk_update_wm;
7074 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7075 } else {
7076 DRM_DEBUG_KMS("Failed to read display plane latency. "
7077 "Disable CxSR\n");
7078 }
7079
7080 if (IS_GEN5(dev))
1fa61106 7081 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7082 else if (IS_GEN6(dev))
1fa61106 7083 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7084 else if (IS_IVYBRIDGE(dev))
1fa61106 7085 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7086 else if (IS_HASWELL(dev))
cad2a2d7 7087 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7088 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7089 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7090 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7091 vlv_setup_wm_latency(dev);
7092
7093 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7094 dev_priv->display.init_clock_gating =
7095 cherryview_init_clock_gating;
1fa61106 7096 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7097 vlv_setup_wm_latency(dev);
7098
7099 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7100 dev_priv->display.init_clock_gating =
7101 valleyview_init_clock_gating;
1fa61106
ED		 7102 } else if (IS_PINEVIEW(dev)) {
7103 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7104 dev_priv->is_ddr3,
7105 dev_priv->fsb_freq,
7106 dev_priv->mem_freq)) {
7107 DRM_INFO("failed to find known CxSR latency "
7108 "(found ddr%s fsb freq %d, mem freq %d), "
7109 "disabling CxSR\n",
7110 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7111 dev_priv->fsb_freq, dev_priv->mem_freq);
7112 /* Disable CxSR and never update its watermark again */
5209b1f4 7113 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7114 dev_priv->display.update_wm = NULL;
7115 } else
7116 dev_priv->display.update_wm = pineview_update_wm;
7117 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7118 } else if (IS_G4X(dev)) {
7119 dev_priv->display.update_wm = g4x_update_wm;
7120 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7121 } else if (IS_GEN4(dev)) {
7122 dev_priv->display.update_wm = i965_update_wm;
7123 if (IS_CRESTLINE(dev))
7124 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7125 else if (IS_BROADWATER(dev))
7126 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7127 } else if (IS_GEN3(dev)) {
7128 dev_priv->display.update_wm = i9xx_update_wm;
7129 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7130 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7131 } else if (IS_GEN2(dev)) {
7132 if (INTEL_INFO(dev)->num_pipes == 1) {
7133 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7134 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7135 } else {
7136 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7137 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7138 }
7139
7140 if (IS_I85X(dev) || IS_I865G(dev))
7141 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7142 else
7143 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7144 } else {
7145 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7146 }
7147}
7148
151a49d0 7149int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7150{
4fc688ce 7151 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7152
7153 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7154 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7155 return -EAGAIN;
7156 }
7157
7158 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7159 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7160 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7161
7162 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7163 500)) {
7164 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7165 return -ETIMEDOUT;
7166 }
7167
7168 *val = I915_READ(GEN6_PCODE_DATA);
7169 I915_WRITE(GEN6_PCODE_DATA, 0);
7170
7171 return 0;
7172}
7173
151a49d0 7174int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7175{
4fc688ce 7176 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7177
7178 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7179 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7180 return -EAGAIN;
7181 }
7182
7183 I915_WRITE(GEN6_PCODE_DATA, val);
7184 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7185
7186 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7187 500)) {
7188 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7189 return -ETIMEDOUT;
7190 }
7191
7192 I915_WRITE(GEN6_PCODE_DATA, 0);
7193
7194 return 0;
7195}
a0e4e199 7196
dd06f88c 7197static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7198{
dd06f88c
VS		 7199 switch (czclk_freq) {
7200 case 200:
7201 return 10;
7202 case 267:
7203 return 12;
7204 case 320:
7205 case 333:
dd06f88c 7206 return 16;
ab3fb157
VS		 7207 case 400:
7208 return 20;
855ba3be
JB		 7209 default:
7210 return -1;
7211 }
dd06f88c 7212}
855ba3be 7213
dd06f88c
VS		 7214static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7215{
7216 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7217
7218 div = vlv_gpu_freq_div(czclk_freq);
7219 if (div < 0)
7220 return div;
7221
7222 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7223}
7224
b55dd647 7225static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7226{
dd06f88c 7227 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 7228
dd06f88c
VS		 7229 mul = vlv_gpu_freq_div(czclk_freq);
7230 if (mul < 0)
7231 return mul;
855ba3be 7232
dd06f88c 7233 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7234}
7235
b55dd647 7236static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7237{
dd06f88c 7238 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7239
dd06f88c
VS		 7240 div = vlv_gpu_freq_div(czclk_freq) / 2;
7241 if (div < 0)
7242 return div;
22b1b2f8 7243
dd06f88c 7244 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7245}
7246
b55dd647 7247static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7248{
dd06f88c 7249 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7250
dd06f88c
VS		 7251 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7252 if (mul < 0)
7253 return mul;
22b1b2f8 7254
1c14762d 7255 /* CHV needs even values */
dd06f88c 7256 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7257}
7258
616bc820 7259int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7260{
80b6dda4
AG		 7261 if (IS_GEN9(dev_priv->dev))
7262 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7263 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7264 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7265 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7266 return byt_gpu_freq(dev_priv, val);
7267 else
7268 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7269}
7270
616bc820
VS		 7271int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7272{
80b6dda4
AG		 7273 if (IS_GEN9(dev_priv->dev))
7274 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7275 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7276 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7277 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7278 return byt_freq_opcode(dev_priv, val);
7279 else
7280 return val / GT_FREQUENCY_MULTIPLIER;
7281}
22b1b2f8 7282
6ad790c0
CW		 7283struct request_boost {
7284 struct work_struct work;
eed29a5b 7285 struct drm_i915_gem_request *req;
6ad790c0
CW		 7286};
7287
7288static void __intel_rps_boost_work(struct work_struct *work)
7289{
7290 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7291 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7292
e61b9958
CW		 7293 if (!i915_gem_request_completed(req, true))
7294 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7295 req->emitted_jiffies);
6ad790c0 7296
e61b9958 7297 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7298 kfree(boost);
7299}
7300
7301void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7302 struct drm_i915_gem_request *req)
6ad790c0
CW		 7303{
7304 struct request_boost *boost;
7305
eed29a5b 7306 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7307 return;
7308
e61b9958
CW		 7309 if (i915_gem_request_completed(req, true))
7310 return;
7311
6ad790c0
CW		 7312 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7313 if (boost == NULL)
7314 return;
7315
eed29a5b
DV		 7316 i915_gem_request_reference(req);
7317 boost->req = req;
6ad790c0
CW		 7318
7319 INIT_WORK(&boost->work, __intel_rps_boost_work);
7320 queue_work(to_i915(dev)->wq, &boost->work);
7321}
7322
f742a552 7323void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7324{
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326
f742a552 7327 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7328 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7329
907b28c5
CW		 7330 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7331 intel_gen6_powersave_work);
1854d5ca 7332 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7333 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7334 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7335
33688d95 7336 dev_priv->pm.suspended = false;
907b28c5 7337}
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