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drm/i915/gen9: look for adjusted_mode in the SAGV check for interlaced
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
44a655ca
TU		 255static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
256 bool is_ddr3,
b445e3b0
ED		 257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
920a14b2 325 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 329 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
50a0bc90 337 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
50a0bc90 342 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
50a0bc90
TU		 651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
652 dev_priv->is_ddr3,
653 dev_priv->fsb_freq,
654 dev_priv->mem_freq);
b445e3b0
ED		 655 if (!latency) {
656 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 657 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 658 return;
659 }
660
661 crtc = single_enabled_crtc(dev);
662 if (crtc) {
7c5f93b0 663 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 664 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 665 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 666
667 /* Display SR */
668 wm = intel_calculate_wm(clock, &pineview_display_wm,
669 pineview_display_wm.fifo_size,
ac484963 670 cpp, latency->display_sr);
b445e3b0
ED		 671 reg = I915_READ(DSPFW1);
672 reg &= ~DSPFW_SR_MASK;
f4998963 673 reg |= FW_WM(wm, SR);
b445e3b0
ED		 674 I915_WRITE(DSPFW1, reg);
675 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
676
677 /* cursor SR */
678 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
679 pineview_display_wm.fifo_size,
ac484963 680 cpp, latency->cursor_sr);
b445e3b0
ED		 681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 683 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 684 I915_WRITE(DSPFW3, reg);
685
686 /* Display HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
ac484963 689 cpp, latency->display_hpll_disable);
b445e3b0
ED		 690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 692 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 693 I915_WRITE(DSPFW3, reg);
694
695 /* cursor HPLL off SR */
696 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
697 pineview_display_hplloff_wm.fifo_size,
ac484963 698 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 699 reg = I915_READ(DSPFW3);
700 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 701 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 702 I915_WRITE(DSPFW3, reg);
703 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
704
5209b1f4 705 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 706 } else {
5209b1f4 707 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 708 }
709}
710
711static bool g4x_compute_wm0(struct drm_device *dev,
712 int plane,
713 const struct intel_watermark_params *display,
714 int display_latency_ns,
715 const struct intel_watermark_params *cursor,
716 int cursor_latency_ns,
717 int *plane_wm,
718 int *cursor_wm)
719{
720 struct drm_crtc *crtc;
4fe8590a 721 const struct drm_display_mode *adjusted_mode;
ac484963 722 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 723 int line_time_us, line_count;
724 int entries, tlb_miss;
725
726 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 727 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 728 *cursor_wm = cursor->guard_size;
729 *plane_wm = display->guard_size;
730 return false;
731 }
732
6e3c9717 733 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 734 clock = adjusted_mode->crtc_clock;
fec8cba3 735 htotal = adjusted_mode->crtc_htotal;
6e3c9717 736 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 737 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 738
739 /* Use the small buffer method to calculate plane watermark */
ac484963 740 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 741 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
742 if (tlb_miss > 0)
743 entries += tlb_miss;
744 entries = DIV_ROUND_UP(entries, display->cacheline_size);
745 *plane_wm = entries + display->guard_size;
746 if (*plane_wm > (int)display->max_wm)
747 *plane_wm = display->max_wm;
748
749 /* Use the large buffer method to calculate cursor watermark */
922044c9 750 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 751 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 752 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 753 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
754 if (tlb_miss > 0)
755 entries += tlb_miss;
756 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
757 *cursor_wm = entries + cursor->guard_size;
758 if (*cursor_wm > (int)cursor->max_wm)
759 *cursor_wm = (int)cursor->max_wm;
760
761 return true;
762}
763
764/*
765 * Check the wm result.
766 *
767 * If any calculated watermark values is larger than the maximum value that
768 * can be programmed into the associated watermark register, that watermark
769 * must be disabled.
770 */
771static bool g4x_check_srwm(struct drm_device *dev,
772 int display_wm, int cursor_wm,
773 const struct intel_watermark_params *display,
774 const struct intel_watermark_params *cursor)
775{
776 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
777 display_wm, cursor_wm);
778
779 if (display_wm > display->max_wm) {
ae9400ca 780 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 781 display_wm, display->max_wm);
782 return false;
783 }
784
785 if (cursor_wm > cursor->max_wm) {
ae9400ca 786 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 787 cursor_wm, cursor->max_wm);
788 return false;
789 }
790
791 if (!(display_wm || cursor_wm)) {
792 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
793 return false;
794 }
795
796 return true;
797}
798
799static bool g4x_compute_srwm(struct drm_device *dev,
800 int plane,
801 int latency_ns,
802 const struct intel_watermark_params *display,
803 const struct intel_watermark_params *cursor,
804 int *display_wm, int *cursor_wm)
805{
806 struct drm_crtc *crtc;
4fe8590a 807 const struct drm_display_mode *adjusted_mode;
ac484963 808 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 809 unsigned long line_time_us;
810 int line_count, line_size;
811 int small, large;
812 int entries;
813
814 if (!latency_ns) {
815 *display_wm = *cursor_wm = 0;
816 return false;
817 }
818
819 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 820 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 821 clock = adjusted_mode->crtc_clock;
fec8cba3 822 htotal = adjusted_mode->crtc_htotal;
6e3c9717 823 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 824 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 825
922044c9 826 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 827 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 828 line_size = hdisplay * cpp;
b445e3b0
ED		 829
830 /* Use the minimum of the small and large buffer method for primary */
ac484963 831 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 832 large = line_count * line_size;
833
834 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
835 *display_wm = entries + display->guard_size;
836
837 /* calculate the self-refresh watermark for display cursor */
ac484963 838 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 839 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
840 *cursor_wm = entries + cursor->guard_size;
841
842 return g4x_check_srwm(dev,
843 *display_wm, *cursor_wm,
844 display, cursor);
845}
846
15665979
VS		 847#define FW_WM_VLV(value, plane) \
848 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
849
0018fda1
VS		 850static void vlv_write_wm_values(struct intel_crtc *crtc,
851 const struct vlv_wm_values *wm)
852{
853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
854 enum pipe pipe = crtc->pipe;
855
856 I915_WRITE(VLV_DDL(pipe),
857 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
858 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
859 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
860 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
861
ae80152d 862 I915_WRITE(DSPFW1,
15665979
VS		 863 FW_WM(wm->sr.plane, SR) |
864 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
865 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
866 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 867 I915_WRITE(DSPFW2,
15665979
VS		 868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
869 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
870 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 871 I915_WRITE(DSPFW3,
15665979 872 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 873
874 if (IS_CHERRYVIEW(dev_priv)) {
875 I915_WRITE(DSPFW7_CHV,
15665979
VS		 876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
877 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 878 I915_WRITE(DSPFW8_CHV,
15665979
VS		 879 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
880 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 881 I915_WRITE(DSPFW9_CHV,
15665979
VS		 882 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
883 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 884 I915_WRITE(DSPHOWM,
15665979
VS		 885 FW_WM(wm->sr.plane >> 9, SR_HI) |
886 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
887 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
888 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
890 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
891 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
892 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
893 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
894 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 895 } else {
896 I915_WRITE(DSPFW7,
15665979
VS		 897 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
898 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 899 I915_WRITE(DSPHOWM,
15665979
VS		 900 FW_WM(wm->sr.plane >> 9, SR_HI) |
901 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
902 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
903 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
904 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
905 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
906 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 907 }
908
2cb389b7
VS		 909 /* zero (unused) WM1 watermarks */
910 I915_WRITE(DSPFW4, 0);
911 I915_WRITE(DSPFW5, 0);
912 I915_WRITE(DSPFW6, 0);
913 I915_WRITE(DSPHOWM1, 0);
914
ae80152d 915 POSTING_READ(DSPFW1);
0018fda1
VS		 916}
917
15665979
VS		 918#undef FW_WM_VLV
919
6eb1a681
VS		 920enum vlv_wm_level {
921 VLV_WM_LEVEL_PM2,
922 VLV_WM_LEVEL_PM5,
923 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 924};
925
262cd2e1
VS		 926/* latency must be in 0.1us units. */
927static unsigned int vlv_wm_method2(unsigned int pixel_rate,
928 unsigned int pipe_htotal,
929 unsigned int horiz_pixels,
ac484963 930 unsigned int cpp,
262cd2e1
VS		 931 unsigned int latency)
932{
933 unsigned int ret;
934
935 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 936 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 937 ret = DIV_ROUND_UP(ret, 64);
938
939 return ret;
940}
941
942static void vlv_setup_wm_latency(struct drm_device *dev)
943{
fac5e23e 944 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 945
946 /* all latencies in usec */
947 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
948
58590c14
VS		 949 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
950
262cd2e1
VS		 951 if (IS_CHERRYVIEW(dev_priv)) {
952 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
953 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 954
955 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 956 }
957}
958
959static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
960 struct intel_crtc *crtc,
961 const struct intel_plane_state *state,
962 int level)
963{
964 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 965 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 966
967 if (dev_priv->wm.pri_latency[level] == 0)
968 return USHRT_MAX;
969
936e71e3 970 if (!state->base.visible)
262cd2e1
VS		 971 return 0;
972
ac484963 973 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 974 clock = crtc->config->base.adjusted_mode.crtc_clock;
975 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
976 width = crtc->config->pipe_src_w;
977 if (WARN_ON(htotal == 0))
978 htotal = 1;
979
980 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
981 /*
982 * FIXME the formula gives values that are
983 * too big for the cursor FIFO, and hence we
984 * would never be able to use cursors. For
985 * now just hardcode the watermark.
986 */
987 wm = 63;
988 } else {
ac484963 989 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 990 dev_priv->wm.pri_latency[level] * 10);
991 }
992
993 return min_t(int, wm, USHRT_MAX);
994}
995
54f1b6e1
VS		 996static void vlv_compute_fifo(struct intel_crtc *crtc)
997{
998 struct drm_device *dev = crtc->base.dev;
999 struct vlv_wm_state *wm_state = &crtc->wm_state;
1000 struct intel_plane *plane;
1001 unsigned int total_rate = 0;
1002 const int fifo_size = 512 - 1;
1003 int fifo_extra, fifo_left = fifo_size;
1004
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 struct intel_plane_state *state =
1007 to_intel_plane_state(plane->base.state);
1008
1009 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1010 continue;
1011
936e71e3 1012 if (state->base.visible) {
54f1b6e1
VS		 1013 wm_state->num_active_planes++;
1014 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1015 }
1016 }
1017
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 struct intel_plane_state *state =
1020 to_intel_plane_state(plane->base.state);
1021 unsigned int rate;
1022
1023 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1024 plane->wm.fifo_size = 63;
1025 continue;
1026 }
1027
936e71e3 1028 if (!state->base.visible) {
54f1b6e1
VS		 1029 plane->wm.fifo_size = 0;
1030 continue;
1031 }
1032
1033 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1034 plane->wm.fifo_size = fifo_size * rate / total_rate;
1035 fifo_left -= plane->wm.fifo_size;
1036 }
1037
1038 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1039
1040 /* spread the remainder evenly */
1041 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042 int plane_extra;
1043
1044 if (fifo_left == 0)
1045 break;
1046
1047 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1048 continue;
1049
1050 /* give it all to the first plane if none are active */
1051 if (plane->wm.fifo_size == 0 &&
1052 wm_state->num_active_planes)
1053 continue;
1054
1055 plane_extra = min(fifo_extra, fifo_left);
1056 plane->wm.fifo_size += plane_extra;
1057 fifo_left -= plane_extra;
1058 }
1059
1060 WARN_ON(fifo_left != 0);
1061}
1062
262cd2e1
VS		 1063static void vlv_invert_wms(struct intel_crtc *crtc)
1064{
1065 struct vlv_wm_state *wm_state = &crtc->wm_state;
1066 int level;
1067
1068 for (level = 0; level < wm_state->num_levels; level++) {
1069 struct drm_device *dev = crtc->base.dev;
1070 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1071 struct intel_plane *plane;
1072
1073 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1074 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1075
1076 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1077 switch (plane->base.type) {
1078 int sprite;
1079 case DRM_PLANE_TYPE_CURSOR:
1080 wm_state->wm[level].cursor = plane->wm.fifo_size -
1081 wm_state->wm[level].cursor;
1082 break;
1083 case DRM_PLANE_TYPE_PRIMARY:
1084 wm_state->wm[level].primary = plane->wm.fifo_size -
1085 wm_state->wm[level].primary;
1086 break;
1087 case DRM_PLANE_TYPE_OVERLAY:
1088 sprite = plane->plane;
1089 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1090 wm_state->wm[level].sprite[sprite];
1091 break;
1092 }
1093 }
1094 }
1095}
1096
26e1fe4f 1097static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1098{
1099 struct drm_device *dev = crtc->base.dev;
1100 struct vlv_wm_state *wm_state = &crtc->wm_state;
1101 struct intel_plane *plane;
1102 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1103 int level;
1104
1105 memset(wm_state, 0, sizeof(*wm_state));
1106
852eb00d 1107 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1108 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1109
1110 wm_state->num_active_planes = 0;
262cd2e1 1111
54f1b6e1 1112 vlv_compute_fifo(crtc);
262cd2e1
VS		 1113
1114 if (wm_state->num_active_planes != 1)
1115 wm_state->cxsr = false;
1116
1117 if (wm_state->cxsr) {
1118 for (level = 0; level < wm_state->num_levels; level++) {
1119 wm_state->sr[level].plane = sr_fifo_size;
1120 wm_state->sr[level].cursor = 63;
1121 }
1122 }
1123
1124 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1125 struct intel_plane_state *state =
1126 to_intel_plane_state(plane->base.state);
1127
936e71e3 1128 if (!state->base.visible)
262cd2e1
VS		 1129 continue;
1130
1131 /* normal watermarks */
1132 for (level = 0; level < wm_state->num_levels; level++) {
1133 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1134 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1135
1136 /* hack */
1137 if (WARN_ON(level == 0 && wm > max_wm))
1138 wm = max_wm;
1139
1140 if (wm > plane->wm.fifo_size)
1141 break;
1142
1143 switch (plane->base.type) {
1144 int sprite;
1145 case DRM_PLANE_TYPE_CURSOR:
1146 wm_state->wm[level].cursor = wm;
1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 wm_state->wm[level].primary = wm;
1150 break;
1151 case DRM_PLANE_TYPE_OVERLAY:
1152 sprite = plane->plane;
1153 wm_state->wm[level].sprite[sprite] = wm;
1154 break;
1155 }
1156 }
1157
1158 wm_state->num_levels = level;
1159
1160 if (!wm_state->cxsr)
1161 continue;
1162
1163 /* maxfifo watermarks */
1164 switch (plane->base.type) {
1165 int sprite, level;
1166 case DRM_PLANE_TYPE_CURSOR:
1167 for (level = 0; level < wm_state->num_levels; level++)
1168 wm_state->sr[level].cursor =
5a37ed0a 1169 wm_state->wm[level].cursor;
262cd2e1
VS		 1170 break;
1171 case DRM_PLANE_TYPE_PRIMARY:
1172 for (level = 0; level < wm_state->num_levels; level++)
1173 wm_state->sr[level].plane =
1174 min(wm_state->sr[level].plane,
1175 wm_state->wm[level].primary);
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 for (level = 0; level < wm_state->num_levels; level++)
1180 wm_state->sr[level].plane =
1181 min(wm_state->sr[level].plane,
1182 wm_state->wm[level].sprite[sprite]);
1183 break;
1184 }
1185 }
1186
1187 /* clear any (partially) filled invalid levels */
58590c14 1188 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1189 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1190 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1191 }
1192
1193 vlv_invert_wms(crtc);
1194}
1195
54f1b6e1
VS		 1196#define VLV_FIFO(plane, value) \
1197 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1198
1199static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1200{
1201 struct drm_device *dev = crtc->base.dev;
1202 struct drm_i915_private *dev_priv = to_i915(dev);
1203 struct intel_plane *plane;
1204 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1205
1206 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1207 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1208 WARN_ON(plane->wm.fifo_size != 63);
1209 continue;
1210 }
1211
1212 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1213 sprite0_start = plane->wm.fifo_size;
1214 else if (plane->plane == 0)
1215 sprite1_start = sprite0_start + plane->wm.fifo_size;
1216 else
1217 fifo_size = sprite1_start + plane->wm.fifo_size;
1218 }
1219
1220 WARN_ON(fifo_size != 512 - 1);
1221
1222 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223 pipe_name(crtc->pipe), sprite0_start,
1224 sprite1_start, fifo_size);
1225
1226 switch (crtc->pipe) {
1227 uint32_t dsparb, dsparb2, dsparb3;
1228 case PIPE_A:
1229 dsparb = I915_READ(DSPARB);
1230 dsparb2 = I915_READ(DSPARB2);
1231
1232 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1233 VLV_FIFO(SPRITEB, 0xff));
1234 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1235 VLV_FIFO(SPRITEB, sprite1_start));
1236
1237 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1238 VLV_FIFO(SPRITEB_HI, 0x1));
1239 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1240 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1241
1242 I915_WRITE(DSPARB, dsparb);
1243 I915_WRITE(DSPARB2, dsparb2);
1244 break;
1245 case PIPE_B:
1246 dsparb = I915_READ(DSPARB);
1247 dsparb2 = I915_READ(DSPARB2);
1248
1249 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1250 VLV_FIFO(SPRITED, 0xff));
1251 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1252 VLV_FIFO(SPRITED, sprite1_start));
1253
1254 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1255 VLV_FIFO(SPRITED_HI, 0xff));
1256 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1257 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1258
1259 I915_WRITE(DSPARB, dsparb);
1260 I915_WRITE(DSPARB2, dsparb2);
1261 break;
1262 case PIPE_C:
1263 dsparb3 = I915_READ(DSPARB3);
1264 dsparb2 = I915_READ(DSPARB2);
1265
1266 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1267 VLV_FIFO(SPRITEF, 0xff));
1268 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1269 VLV_FIFO(SPRITEF, sprite1_start));
1270
1271 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1272 VLV_FIFO(SPRITEF_HI, 0xff));
1273 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1274 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1275
1276 I915_WRITE(DSPARB3, dsparb3);
1277 I915_WRITE(DSPARB2, dsparb2);
1278 break;
1279 default:
1280 break;
1281 }
1282}
1283
1284#undef VLV_FIFO
1285
262cd2e1
VS		 1286static void vlv_merge_wm(struct drm_device *dev,
1287 struct vlv_wm_values *wm)
1288{
1289 struct intel_crtc *crtc;
1290 int num_active_crtcs = 0;
1291
58590c14 1292 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1293 wm->cxsr = true;
1294
1295 for_each_intel_crtc(dev, crtc) {
1296 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1297
1298 if (!crtc->active)
1299 continue;
1300
1301 if (!wm_state->cxsr)
1302 wm->cxsr = false;
1303
1304 num_active_crtcs++;
1305 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1306 }
1307
1308 if (num_active_crtcs != 1)
1309 wm->cxsr = false;
1310
6f9c784b
VS		 1311 if (num_active_crtcs > 1)
1312 wm->level = VLV_WM_LEVEL_PM2;
1313
262cd2e1
VS		 1314 for_each_intel_crtc(dev, crtc) {
1315 struct vlv_wm_state *wm_state = &crtc->wm_state;
1316 enum pipe pipe = crtc->pipe;
1317
1318 if (!crtc->active)
1319 continue;
1320
1321 wm->pipe[pipe] = wm_state->wm[wm->level];
1322 if (wm->cxsr)
1323 wm->sr = wm_state->sr[wm->level];
1324
1325 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1327 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1328 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1329 }
1330}
1331
1332static void vlv_update_wm(struct drm_crtc *crtc)
1333{
1334 struct drm_device *dev = crtc->dev;
fac5e23e 1335 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1337 enum pipe pipe = intel_crtc->pipe;
1338 struct vlv_wm_values wm = {};
1339
26e1fe4f 1340 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1341 vlv_merge_wm(dev, &wm);
1342
54f1b6e1
VS		 1343 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1344 /* FIXME should be part of crtc atomic commit */
1345 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1346 return;
54f1b6e1 1347 }
262cd2e1
VS		 1348
1349 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1350 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1351 chv_set_memory_dvfs(dev_priv, false);
1352
1353 if (wm.level < VLV_WM_LEVEL_PM5 &&
1354 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1355 chv_set_memory_pm5(dev_priv, false);
1356
852eb00d 1357 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1358 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1359
54f1b6e1
VS		 1360 /* FIXME should be part of crtc atomic commit */
1361 vlv_pipe_set_fifo_size(intel_crtc);
1362
262cd2e1
VS		 1363 vlv_write_wm_values(intel_crtc, &wm);
1364
1365 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1366 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1367 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1368 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1369 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1370
852eb00d 1371 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1372 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1373
1374 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1375 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1376 chv_set_memory_pm5(dev_priv, true);
1377
1378 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1379 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1380 chv_set_memory_dvfs(dev_priv, true);
1381
1382 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1383}
1384
ae80152d
VS		 1385#define single_plane_enabled(mask) is_power_of_2(mask)
1386
46ba614c 1387static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1388{
46ba614c 1389 struct drm_device *dev = crtc->dev;
b445e3b0 1390 static const int sr_latency_ns = 12000;
fac5e23e 1391 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1392 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1393 int plane_sr, cursor_sr;
1394 unsigned int enabled = 0;
9858425c 1395 bool cxsr_enabled;
b445e3b0 1396
51cea1f4 1397 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1398 &g4x_wm_info, pessimal_latency_ns,
1399 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1400 &planea_wm, &cursora_wm))
51cea1f4 1401 enabled |= 1 << PIPE_A;
b445e3b0 1402
51cea1f4 1403 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1404 &g4x_wm_info, pessimal_latency_ns,
1405 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1406 &planeb_wm, &cursorb_wm))
51cea1f4 1407 enabled |= 1 << PIPE_B;
b445e3b0 1408
b445e3b0
ED		 1409 if (single_plane_enabled(enabled) &&
1410 g4x_compute_srwm(dev, ffs(enabled) - 1,
1411 sr_latency_ns,
1412 &g4x_wm_info,
1413 &g4x_cursor_wm_info,
52bd02d8 1414 &plane_sr, &cursor_sr)) {
9858425c 1415 cxsr_enabled = true;
52bd02d8 1416 } else {
9858425c 1417 cxsr_enabled = false;
5209b1f4 1418 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1419 plane_sr = cursor_sr = 0;
1420 }
b445e3b0 1421
a5043453
VS		 1422 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1423 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1424 planea_wm, cursora_wm,
1425 planeb_wm, cursorb_wm,
1426 plane_sr, cursor_sr);
1427
1428 I915_WRITE(DSPFW1,
f4998963
VS		 1429 FW_WM(plane_sr, SR) |
1430 FW_WM(cursorb_wm, CURSORB) |
1431 FW_WM(planeb_wm, PLANEB) |
1432 FW_WM(planea_wm, PLANEA));
b445e3b0 1433 I915_WRITE(DSPFW2,
8c919b28 1434 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1435 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1436 /* HPLL off in SR has some issues on G4x... disable it */
1437 I915_WRITE(DSPFW3,
8c919b28 1438 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1439 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1440
1441 if (cxsr_enabled)
1442 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1443}
1444
46ba614c 1445static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1446{
46ba614c 1447 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1448 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1449 struct drm_crtc *crtc;
1450 int srwm = 1;
1451 int cursor_sr = 16;
9858425c 1452 bool cxsr_enabled;
b445e3b0
ED		 1453
1454 /* Calc sr entries for one plane configs */
1455 crtc = single_enabled_crtc(dev);
1456 if (crtc) {
1457 /* self-refresh has much higher latency */
1458 static const int sr_latency_ns = 12000;
124abe07 1459 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1460 int clock = adjusted_mode->crtc_clock;
fec8cba3 1461 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1462 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1463 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1464 unsigned long line_time_us;
1465 int entries;
1466
922044c9 1467 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1468
1469 /* Use ns/us then divide to preserve precision */
1470 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1471 cpp * hdisplay;
b445e3b0
ED		 1472 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1473 srwm = I965_FIFO_SIZE - entries;
1474 if (srwm < 0)
1475 srwm = 1;
1476 srwm &= 0x1ff;
1477 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1478 entries, srwm);
1479
1480 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1481 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1482 entries = DIV_ROUND_UP(entries,
1483 i965_cursor_wm_info.cacheline_size);
1484 cursor_sr = i965_cursor_wm_info.fifo_size -
1485 (entries + i965_cursor_wm_info.guard_size);
1486
1487 if (cursor_sr > i965_cursor_wm_info.max_wm)
1488 cursor_sr = i965_cursor_wm_info.max_wm;
1489
1490 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1491 "cursor %d\n", srwm, cursor_sr);
1492
9858425c 1493 cxsr_enabled = true;
b445e3b0 1494 } else {
9858425c 1495 cxsr_enabled = false;
b445e3b0 1496 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1497 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1498 }
1499
1500 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1501 srwm);
1502
1503 /* 965 has limitations... */
f4998963
VS		 1504 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1505 FW_WM(8, CURSORB) |
1506 FW_WM(8, PLANEB) |
1507 FW_WM(8, PLANEA));
1508 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1509 FW_WM(8, PLANEC_OLD));
b445e3b0 1510 /* update cursor SR watermark */
f4998963 1511 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1512
1513 if (cxsr_enabled)
1514 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1515}
1516
f4998963
VS		 1517#undef FW_WM
1518
46ba614c 1519static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1520{
46ba614c 1521 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1522 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1523 const struct intel_watermark_params *wm_info;
1524 uint32_t fwater_lo;
1525 uint32_t fwater_hi;
1526 int cwm, srwm = 1;
1527 int fifo_size;
1528 int planea_wm, planeb_wm;
1529 struct drm_crtc *crtc, *enabled = NULL;
1530
1531 if (IS_I945GM(dev))
1532 wm_info = &i945_wm_info;
5db94019 1533 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1534 wm_info = &i915_wm_info;
1535 else
9d539105 1536 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1539 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1540 if (intel_crtc_active(crtc)) {
241bfc38 1541 const struct drm_display_mode *adjusted_mode;
ac484963 1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1543 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1544 cpp = 4;
1545
6e3c9717 1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1547 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1548 wm_info, fifo_size, cpp,
5aef6003 1549 pessimal_latency_ns);
b445e3b0 1550 enabled = crtc;
9d539105 1551 } else {
b445e3b0 1552 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1553 if (planea_wm > (long)wm_info->max_wm)
1554 planea_wm = wm_info->max_wm;
1555 }
1556
5db94019 1557 if (IS_GEN2(dev_priv))
9d539105 1558 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1559
1560 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1561 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1562 if (intel_crtc_active(crtc)) {
241bfc38 1563 const struct drm_display_mode *adjusted_mode;
ac484963 1564 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1565 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1566 cpp = 4;
1567
6e3c9717 1568 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1569 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
5aef6003 1571 pessimal_latency_ns);
b445e3b0
ED		 1572 if (enabled == NULL)
1573 enabled = crtc;
1574 else
1575 enabled = NULL;
9d539105 1576 } else {
b445e3b0 1577 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1578 if (planeb_wm > (long)wm_info->max_wm)
1579 planeb_wm = wm_info->max_wm;
1580 }
b445e3b0
ED		 1581
1582 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1583
50a0bc90 1584 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1585 struct drm_i915_gem_object *obj;
2ab1bc9d 1586
59bea882 1587 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1588
1589 /* self-refresh seems busted with untiled */
3e510a8e 1590 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1591 enabled = NULL;
1592 }
1593
b445e3b0
ED		 1594 /*
1595 * Overlay gets an aggressive default since video jitter is bad.
1596 */
1597 cwm = 2;
1598
1599 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1600 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1601
1602 /* Calc sr entries for one plane configs */
1603 if (HAS_FW_BLC(dev) && enabled) {
1604 /* self-refresh has much higher latency */
1605 static const int sr_latency_ns = 6000;
124abe07 1606 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1607 int clock = adjusted_mode->crtc_clock;
fec8cba3 1608 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1609 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1610 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1611 unsigned long line_time_us;
1612 int entries;
1613
50a0bc90 1614 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056
VS		 1615 cpp = 4;
1616
922044c9 1617 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1621 cpp * hdisplay;
b445e3b0
ED		 1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
50a0bc90 1628 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1631 else
b445e3b0
ED		 1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
5209b1f4
ID		 1648 if (enabled)
1649 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1650}
1651
feb56b93 1652static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1653{
46ba614c 1654 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1655 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1656 struct drm_crtc *crtc;
241bfc38 1657 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1658 uint32_t fwater_lo;
1659 int planea_wm;
1660
1661 crtc = single_enabled_crtc(dev);
1662 if (crtc == NULL)
1663 return;
1664
6e3c9717 1665 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1666 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1667 &i845_wm_info,
b445e3b0 1668 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1669 4, pessimal_latency_ns);
b445e3b0
ED		 1670 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1671 fwater_lo |= (3<<8) | planea_wm;
1672
1673 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1674
1675 I915_WRITE(FW_BLC, fwater_lo);
1676}
1677
8cfb3407 1678uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1679{
fd4daa9c 1680 uint32_t pixel_rate;
801bcfff 1681
8cfb3407 1682 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1683
1684 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1685 * adjust the pixel_rate here. */
1686
8cfb3407 1687 if (pipe_config->pch_pfit.enabled) {
801bcfff 1688 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1689 uint32_t pfit_size = pipe_config->pch_pfit.size;
1690
1691 pipe_w = pipe_config->pipe_src_w;
1692 pipe_h = pipe_config->pipe_src_h;
801bcfff 1693
801bcfff
PZ		 1694 pfit_w = (pfit_size >> 16) & 0xFFFF;
1695 pfit_h = pfit_size & 0xFFFF;
1696 if (pipe_w < pfit_w)
1697 pipe_w = pfit_w;
1698 if (pipe_h < pfit_h)
1699 pipe_h = pfit_h;
1700
15126882
MR		 1701 if (WARN_ON(!pfit_w || !pfit_h))
1702 return pixel_rate;
1703
801bcfff
PZ		 1704 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1705 pfit_w * pfit_h);
1706 }
1707
1708 return pixel_rate;
1709}
1710
37126462 1711/* latency must be in 0.1us units. */
ac484963 1712static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1713{
1714 uint64_t ret;
1715
3312ba65
VS		 1716 if (WARN(latency == 0, "Latency value missing\n"))
1717 return UINT_MAX;
1718
ac484963 1719 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1720 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1721
1722 return ret;
1723}
1724
37126462 1725/* latency must be in 0.1us units. */
23297044 1726static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1727 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1728 uint32_t latency)
1729{
1730 uint32_t ret;
1731
3312ba65
VS		 1732 if (WARN(latency == 0, "Latency value missing\n"))
1733 return UINT_MAX;
15126882
MR		 1734 if (WARN_ON(!pipe_htotal))
1735 return UINT_MAX;
3312ba65 1736
801bcfff 1737 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1738 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1739 ret = DIV_ROUND_UP(ret, 64) + 2;
1740 return ret;
1741}
1742
23297044 1743static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1744 uint8_t cpp)
cca32e9a 1745{
15126882
MR		 1746 /*
1747 * Neither of these should be possible since this function shouldn't be
1748 * called if the CRTC is off or the plane is invisible. But let's be
1749 * extra paranoid to avoid a potential divide-by-zero if we screw up
1750 * elsewhere in the driver.
1751 */
ac484963 1752 if (WARN_ON(!cpp))
15126882
MR		 1753 return 0;
1754 if (WARN_ON(!horiz_pixels))
1755 return 0;
1756
ac484963 1757 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1758}
1759
820c1980 1760struct ilk_wm_maximums {
cca32e9a
PZ		 1761 uint16_t pri;
1762 uint16_t spr;
1763 uint16_t cur;
1764 uint16_t fbc;
1765};
1766
37126462
VS		 1767/*
1768 * For both WM_PIPE and WM_LP.
1769 * mem_value must be in 0.1us units.
1770 */
7221fc33 1771static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1772 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1773 uint32_t mem_value,
1774 bool is_lp)
801bcfff 1775{
ac484963
VS		 1776 int cpp = pstate->base.fb ?
1777 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1778 uint32_t method1, method2;
1779
936e71e3 1780 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1781 return 0;
1782
ac484963 1783 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1784
1785 if (!is_lp)
1786 return method1;
1787
7221fc33
MR		 1788 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1790 drm_rect_width(&pstate->base.dst),
ac484963 1791 cpp, mem_value);
cca32e9a
PZ		 1792
1793 return min(method1, method2);
801bcfff
PZ		 1794}
1795
37126462
VS		 1796/*
1797 * For both WM_PIPE and WM_LP.
1798 * mem_value must be in 0.1us units.
1799 */
7221fc33 1800static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1801 const struct intel_plane_state *pstate,
801bcfff
PZ		 1802 uint32_t mem_value)
1803{
ac484963
VS		 1804 int cpp = pstate->base.fb ?
1805 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1806 uint32_t method1, method2;
1807
936e71e3 1808 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1809 return 0;
1810
ac484963 1811 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1812 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1813 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1814 drm_rect_width(&pstate->base.dst),
ac484963 1815 cpp, mem_value);
801bcfff
PZ		 1816 return min(method1, method2);
1817}
1818
37126462
VS		 1819/*
1820 * For both WM_PIPE and WM_LP.
1821 * mem_value must be in 0.1us units.
1822 */
7221fc33 1823static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1824 const struct intel_plane_state *pstate,
801bcfff
PZ		 1825 uint32_t mem_value)
1826{
b2435692
MR		 1827 /*
1828 * We treat the cursor plane as always-on for the purposes of watermark
1829 * calculation. Until we have two-stage watermark programming merged,
1830 * this is necessary to avoid flickering.
1831 */
1832 int cpp = 4;
936e71e3 1833 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1834
b2435692 1835 if (!cstate->base.active)
801bcfff
PZ		 1836 return 0;
1837
7221fc33
MR		 1838 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1839 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1840 width, cpp, mem_value);
801bcfff
PZ		 1841}
1842
cca32e9a 1843/* Only for WM_LP. */
7221fc33 1844static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1845 const struct intel_plane_state *pstate,
1fda9882 1846 uint32_t pri_val)
cca32e9a 1847{
ac484963
VS		 1848 int cpp = pstate->base.fb ?
1849 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1850
936e71e3 1851 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1852 return 0;
1853
936e71e3 1854 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1855}
1856
158ae64f
VS		 1857static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1858{
416f4727
VS		 1859 if (INTEL_INFO(dev)->gen >= 8)
1860 return 3072;
1861 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1862 return 768;
1863 else
1864 return 512;
1865}
1866
4e975081
VS		 1867static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1868 int level, bool is_sprite)
1869{
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 /* BDW primary/sprite plane watermarks */
1872 return level == 0 ? 255 : 2047;
1873 else if (INTEL_INFO(dev)->gen >= 7)
1874 /* IVB/HSW primary/sprite plane watermarks */
1875 return level == 0 ? 127 : 1023;
1876 else if (!is_sprite)
1877 /* ILK/SNB primary plane watermarks */
1878 return level == 0 ? 127 : 511;
1879 else
1880 /* ILK/SNB sprite plane watermarks */
1881 return level == 0 ? 63 : 255;
1882}
1883
1884static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1885 int level)
1886{
1887 if (INTEL_INFO(dev)->gen >= 7)
1888 return level == 0 ? 63 : 255;
1889 else
1890 return level == 0 ? 31 : 63;
1891}
1892
1893static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1894{
1895 if (INTEL_INFO(dev)->gen >= 8)
1896 return 31;
1897 else
1898 return 15;
1899}
1900
158ae64f
VS		 1901/* Calculate the maximum primary/sprite plane watermark */
1902static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1903 int level,
240264f4 1904 const struct intel_wm_config *config,
158ae64f
VS		 1905 enum intel_ddb_partitioning ddb_partitioning,
1906 bool is_sprite)
1907{
1908 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1909
1910 /* if sprites aren't enabled, sprites get nothing */
240264f4 1911 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1912 return 0;
1913
1914 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1915 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1916 fifo_size /= INTEL_INFO(dev)->num_pipes;
1917
1918 /*
1919 * For some reason the non self refresh
1920 * FIFO size is only half of the self
1921 * refresh FIFO size on ILK/SNB.
1922 */
1923 if (INTEL_INFO(dev)->gen <= 6)
1924 fifo_size /= 2;
1925 }
1926
240264f4 1927 if (config->sprites_enabled) {
158ae64f
VS		 1928 /* level 0 is always calculated with 1:1 split */
1929 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1930 if (is_sprite)
1931 fifo_size *= 5;
1932 fifo_size /= 6;
1933 } else {
1934 fifo_size /= 2;
1935 }
1936 }
1937
1938 /* clamp to max that the registers can hold */
4e975081 1939 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1940}
1941
1942/* Calculate the maximum cursor plane watermark */
1943static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1944 int level,
1945 const struct intel_wm_config *config)
158ae64f
VS		 1946{
1947 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1948 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1949 return 64;
1950
1951 /* otherwise just report max that registers can hold */
4e975081 1952 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1953}
1954
d34ff9c6 1955static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1956 int level,
1957 const struct intel_wm_config *config,
1958 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1959 struct ilk_wm_maximums *max)
158ae64f 1960{
240264f4
VS		 1961 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1962 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1963 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1964 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1965}
1966
a3cb4048
VS		 1967static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1968 int level,
1969 struct ilk_wm_maximums *max)
1970{
1971 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1972 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1973 max->cur = ilk_cursor_wm_reg_max(dev, level);
1974 max->fbc = ilk_fbc_wm_reg_max(dev);
1975}
1976
d9395655 1977static bool ilk_validate_wm_level(int level,
820c1980 1978 const struct ilk_wm_maximums *max,
d9395655 1979 struct intel_wm_level *result)
a9786a11
VS		 1980{
1981 bool ret;
1982
1983 /* already determined to be invalid? */
1984 if (!result->enable)
1985 return false;
1986
1987 result->enable = result->pri_val <= max->pri &&
1988 result->spr_val <= max->spr &&
1989 result->cur_val <= max->cur;
1990
1991 ret = result->enable;
1992
1993 /*
1994 * HACK until we can pre-compute everything,
1995 * and thus fail gracefully if LP0 watermarks
1996 * are exceeded...
1997 */
1998 if (level == 0 && !result->enable) {
1999 if (result->pri_val > max->pri)
2000 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2001 level, result->pri_val, max->pri);
2002 if (result->spr_val > max->spr)
2003 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2004 level, result->spr_val, max->spr);
2005 if (result->cur_val > max->cur)
2006 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2007 level, result->cur_val, max->cur);
2008
2009 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2010 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2011 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2012 result->enable = true;
2013 }
2014
a9786a11
VS		 2015 return ret;
2016}
2017
d34ff9c6 2018static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2019 const struct intel_crtc *intel_crtc,
6f5ddd17 2020 int level,
7221fc33 2021 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2022 struct intel_plane_state *pristate,
2023 struct intel_plane_state *sprstate,
2024 struct intel_plane_state *curstate,
1fd527cc 2025 struct intel_wm_level *result)
6f5ddd17
VS		 2026{
2027 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2028 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2029 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2030
2031 /* WM1+ latency values stored in 0.5us units */
2032 if (level > 0) {
2033 pri_latency *= 5;
2034 spr_latency *= 5;
2035 cur_latency *= 5;
2036 }
2037
e3bddded
ML		 2038 if (pristate) {
2039 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2040 pri_latency, level);
2041 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2042 }
2043
2044 if (sprstate)
2045 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2046
2047 if (curstate)
2048 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2049
6f5ddd17
VS		 2050 result->enable = true;
2051}
2052
801bcfff 2053static uint32_t
532f7a7f 2054hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2055{
532f7a7f
VS		 2056 const struct intel_atomic_state *intel_state =
2057 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2058 const struct drm_display_mode *adjusted_mode =
2059 &cstate->base.adjusted_mode;
85a02deb 2060 u32 linetime, ips_linetime;
1f8eeabf 2061
ee91a159
MR		 2062 if (!cstate->base.active)
2063 return 0;
2064 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2065 return 0;
532f7a7f 2066 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2067 return 0;
1011d8c4 2068
1f8eeabf
ED		 2069 /* The WM are computed with base on how long it takes to fill a single
2070 * row at the given clock rate, multiplied by 8.
2071 * */
124abe07
VS		 2072 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073 adjusted_mode->crtc_clock);
2074 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2075 intel_state->cdclk);
1f8eeabf 2076
801bcfff
PZ		 2077 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2078 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2079}
2080
2af30a5c 2081static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2082{
fac5e23e 2083 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2084
5db94019 2085 if (IS_GEN9(dev_priv)) {
2af30a5c 2086 uint32_t val;
4f947386 2087 int ret, i;
5db94019 2088 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2089
2090 /* read the first set of memory latencies[0:3] */
2091 val = 0; /* data0 to be programmed to 0 for first set */
2092 mutex_lock(&dev_priv->rps.hw_lock);
2093 ret = sandybridge_pcode_read(dev_priv,
2094 GEN9_PCODE_READ_MEM_LATENCY,
2095 &val);
2096 mutex_unlock(&dev_priv->rps.hw_lock);
2097
2098 if (ret) {
2099 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2100 return;
2101 }
2102
2103 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2109 GEN9_MEM_LATENCY_LEVEL_MASK;
2110
2111 /* read the second set of memory latencies[4:7] */
2112 val = 1; /* data0 to be programmed to 1 for second set */
2113 mutex_lock(&dev_priv->rps.hw_lock);
2114 ret = sandybridge_pcode_read(dev_priv,
2115 GEN9_PCODE_READ_MEM_LATENCY,
2116 &val);
2117 mutex_unlock(&dev_priv->rps.hw_lock);
2118 if (ret) {
2119 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120 return;
2121 }
2122
2123 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
0727e40a
PZ		 2131 /*
2132 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2133 * need to be disabled. We make sure to sanitize the values out
2134 * of the punit to satisfy this requirement.
2135 */
2136 for (level = 1; level <= max_level; level++) {
2137 if (wm[level] == 0) {
2138 for (i = level + 1; i <= max_level; i++)
2139 wm[i] = 0;
2140 break;
2141 }
2142 }
2143
367294be 2144 /*
6f97235b
DL		 2145 * WaWmMemoryReadLatency:skl
2146 *
367294be 2147 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2148 * to add 2us to the various latency levels we retrieve from the
2149 * punit when level 0 response data us 0us.
367294be 2150 */
0727e40a
PZ		 2151 if (wm[0] == 0) {
2152 wm[0] += 2;
2153 for (level = 1; level <= max_level; level++) {
2154 if (wm[level] == 0)
2155 break;
367294be 2156 wm[level] += 2;
4f947386 2157 }
0727e40a
PZ		 2158 }
2159
8652744b 2160 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2161 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2162
2163 wm[0] = (sskpd >> 56) & 0xFF;
2164 if (wm[0] == 0)
2165 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2166 wm[1] = (sskpd >> 4) & 0xFF;
2167 wm[2] = (sskpd >> 12) & 0xFF;
2168 wm[3] = (sskpd >> 20) & 0x1FF;
2169 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2170 } else if (INTEL_INFO(dev)->gen >= 6) {
2171 uint32_t sskpd = I915_READ(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2174 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2175 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2176 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2177 } else if (INTEL_INFO(dev)->gen >= 5) {
2178 uint32_t mltr = I915_READ(MLTR_ILK);
2179
2180 /* ILK primary LP0 latency is 700 ns */
2181 wm[0] = 7;
2182 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2183 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2184 }
2185}
2186
5db94019
TU		 2187static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2188 uint16_t wm[5])
53615a5e
VS		 2189{
2190 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2191 if (IS_GEN5(dev_priv))
53615a5e
VS		 2192 wm[0] = 13;
2193}
2194
fd6b8f43
TU		 2195static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2196 uint16_t wm[5])
53615a5e
VS		 2197{
2198 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2199 if (IS_GEN5(dev_priv))
53615a5e
VS		 2200 wm[0] = 13;
2201
2202 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2203 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2204 wm[3] *= 2;
2205}
2206
5db94019 2207int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2208{
26ec971e 2209 /* how many WM levels are we expecting */
8652744b 2210 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2211 return 7;
8652744b 2212 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2213 return 4;
8652744b 2214 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2215 return 3;
26ec971e 2216 else
ad0d6dc4
VS		 2217 return 2;
2218}
7526ed79 2219
5db94019 2220static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2221 const char *name,
2af30a5c 2222 const uint16_t wm[8])
ad0d6dc4 2223{
5db94019 2224 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2225
2226 for (level = 0; level <= max_level; level++) {
2227 unsigned int latency = wm[level];
2228
2229 if (latency == 0) {
2230 DRM_ERROR("%s WM%d latency not provided\n",
2231 name, level);
2232 continue;
2233 }
2234
2af30a5c
PB		 2235 /*
2236 * - latencies are in us on gen9.
2237 * - before then, WM1+ latency values are in 0.5us units
2238 */
5db94019 2239 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2240 latency *= 10;
2241 else if (level > 0)
26ec971e
VS		 2242 latency *= 5;
2243
2244 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2245 name, level, wm[level],
2246 latency / 10, latency % 10);
2247 }
2248}
2249
e95a2f75
VS		 2250static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2251 uint16_t wm[5], uint16_t min)
2252{
5db94019 2253 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2254
2255 if (wm[0] >= min)
2256 return false;
2257
2258 wm[0] = max(wm[0], min);
2259 for (level = 1; level <= max_level; level++)
2260 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2261
2262 return true;
2263}
2264
2265static void snb_wm_latency_quirk(struct drm_device *dev)
2266{
fac5e23e 2267 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2268 bool changed;
2269
2270 /*
2271 * The BIOS provided WM memory latency values are often
2272 * inadequate for high resolution displays. Adjust them.
2273 */
2274 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2275 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2276 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2277
2278 if (!changed)
2279 return;
2280
2281 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2282 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2283 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2284 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2285}
2286
fa50ad61 2287static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2288{
fac5e23e 2289 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2290
2291 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2292
2293 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2294 sizeof(dev_priv->wm.pri_latency));
2295 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2296 sizeof(dev_priv->wm.pri_latency));
2297
5db94019 2298 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2299 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2300
5db94019
TU		 2301 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2302 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2303 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2304
5db94019 2305 if (IS_GEN6(dev_priv))
e95a2f75 2306 snb_wm_latency_quirk(dev);
53615a5e
VS		 2307}
2308
2af30a5c
PB		 2309static void skl_setup_wm_latency(struct drm_device *dev)
2310{
fac5e23e 2311 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2312
2313 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
5db94019 2314 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2315}
2316
ed4a6a7c
MR		 2317static bool ilk_validate_pipe_wm(struct drm_device *dev,
2318 struct intel_pipe_wm *pipe_wm)
2319{
2320 /* LP0 watermark maximums depend on this pipe alone */
2321 const struct intel_wm_config config = {
2322 .num_pipes_active = 1,
2323 .sprites_enabled = pipe_wm->sprites_enabled,
2324 .sprites_scaled = pipe_wm->sprites_scaled,
2325 };
2326 struct ilk_wm_maximums max;
2327
2328 /* LP0 watermarks always use 1/2 DDB partitioning */
2329 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2330
2331 /* At least LP0 must be valid */
2332 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2333 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2334 return false;
2335 }
2336
2337 return true;
2338}
2339
0b2ae6d7 2340/* Compute new watermarks for the pipe */
e3bddded 2341static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2342{
e3bddded
ML		 2343 struct drm_atomic_state *state = cstate->base.state;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2345 struct intel_pipe_wm *pipe_wm;
e3bddded 2346 struct drm_device *dev = state->dev;
fac5e23e 2347 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2348 struct intel_plane *intel_plane;
86c8bbbe 2349 struct intel_plane_state *pristate = NULL;
43d59eda 2350 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2351 struct intel_plane_state *curstate = NULL;
5db94019 2352 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2353 struct ilk_wm_maximums max;
0b2ae6d7 2354
e8f1f02e 2355 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2356
43d59eda 2357 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2358 struct intel_plane_state *ps;
2359
2360 ps = intel_atomic_get_existing_plane_state(state,
2361 intel_plane);
2362 if (!ps)
2363 continue;
86c8bbbe
MR		 2364
2365 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2366 pristate = ps;
86c8bbbe 2367 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2368 sprstate = ps;
86c8bbbe 2369 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2370 curstate = ps;
43d59eda
MR		 2371 }
2372
ed4a6a7c 2373 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2374 if (sprstate) {
936e71e3
VS		 2375 pipe_wm->sprites_enabled = sprstate->base.visible;
2376 pipe_wm->sprites_scaled = sprstate->base.visible &&
2377 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2378 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2379 }
2380
d81f04c5
ML		 2381 usable_level = max_level;
2382
7b39a0b7 2383 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2384 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2385 usable_level = 1;
7b39a0b7
VS		 2386
2387 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2388 if (pipe_wm->sprites_scaled)
d81f04c5 2389 usable_level = 0;
7b39a0b7 2390
86c8bbbe 2391 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2392 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2393
2394 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2395 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2396
8652744b 2397 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2398 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2399
ed4a6a7c 2400 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2401 return -EINVAL;
a3cb4048
VS		 2402
2403 ilk_compute_wm_reg_maximums(dev, 1, &max);
2404
2405 for (level = 1; level <= max_level; level++) {
71f0a626 2406 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2407
86c8bbbe 2408 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2409 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2410
2411 /*
2412 * Disable any watermark level that exceeds the
2413 * register maximums since such watermarks are
2414 * always invalid.
2415 */
71f0a626
ML		 2416 if (level > usable_level)
2417 continue;
2418
2419 if (ilk_validate_wm_level(level, &max, wm))
2420 pipe_wm->wm[level] = *wm;
2421 else
d81f04c5 2422 usable_level = level;
a3cb4048
VS		 2423 }
2424
86c8bbbe 2425 return 0;
0b2ae6d7
VS		 2426}
2427
ed4a6a7c
MR		 2428/*
2429 * Build a set of 'intermediate' watermark values that satisfy both the old
2430 * state and the new state. These can be programmed to the hardware
2431 * immediately.
2432 */
2433static int ilk_compute_intermediate_wm(struct drm_device *dev,
2434 struct intel_crtc *intel_crtc,
2435 struct intel_crtc_state *newstate)
2436{
e8f1f02e 2437 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2438 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2439 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2440
2441 /*
2442 * Start with the final, target watermarks, then combine with the
2443 * currently active watermarks to get values that are safe both before
2444 * and after the vblank.
2445 */
e8f1f02e 2446 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2447 a->pipe_enabled |= b->pipe_enabled;
2448 a->sprites_enabled |= b->sprites_enabled;
2449 a->sprites_scaled |= b->sprites_scaled;
2450
2451 for (level = 0; level <= max_level; level++) {
2452 struct intel_wm_level *a_wm = &a->wm[level];
2453 const struct intel_wm_level *b_wm = &b->wm[level];
2454
2455 a_wm->enable &= b_wm->enable;
2456 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2457 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2458 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2459 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2460 }
2461
2462 /*
2463 * We need to make sure that these merged watermark values are
2464 * actually a valid configuration themselves. If they're not,
2465 * there's no safe way to transition from the old state to
2466 * the new state, so we need to fail the atomic transaction.
2467 */
2468 if (!ilk_validate_pipe_wm(dev, a))
2469 return -EINVAL;
2470
2471 /*
2472 * If our intermediate WM are identical to the final WM, then we can
2473 * omit the post-vblank programming; only update if it's different.
2474 */
e8f1f02e 2475 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2476 newstate->wm.need_postvbl_update = false;
2477
2478 return 0;
2479}
2480
0b2ae6d7
VS		 2481/*
2482 * Merge the watermarks from all active pipes for a specific level.
2483 */
2484static void ilk_merge_wm_level(struct drm_device *dev,
2485 int level,
2486 struct intel_wm_level *ret_wm)
2487{
2488 const struct intel_crtc *intel_crtc;
2489
d52fea5b
VS		 2490 ret_wm->enable = true;
2491
d3fcc808 2492 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2493 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2494 const struct intel_wm_level *wm = &active->wm[level];
2495
2496 if (!active->pipe_enabled)
2497 continue;
0b2ae6d7 2498
d52fea5b
VS		 2499 /*
2500 * The watermark values may have been used in the past,
2501 * so we must maintain them in the registers for some
2502 * time even if the level is now disabled.
2503 */
0b2ae6d7 2504 if (!wm->enable)
d52fea5b 2505 ret_wm->enable = false;
0b2ae6d7
VS		 2506
2507 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2508 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2509 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2510 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2511 }
0b2ae6d7
VS		 2512}
2513
2514/*
2515 * Merge all low power watermarks for all active pipes.
2516 */
2517static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2518 const struct intel_wm_config *config,
820c1980 2519 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2520 struct intel_pipe_wm *merged)
2521{
fac5e23e 2522 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2523 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2524 int last_enabled_level = max_level;
0b2ae6d7 2525
0ba22e26 2526 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2527 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2528 config->num_pipes_active > 1)
1204d5ba 2529 last_enabled_level = 0;
0ba22e26 2530
6c8b6c28
VS		 2531 /* ILK: FBC WM must be disabled always */
2532 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2533
2534 /* merge each WM1+ level */
2535 for (level = 1; level <= max_level; level++) {
2536 struct intel_wm_level *wm = &merged->wm[level];
2537
2538 ilk_merge_wm_level(dev, level, wm);
2539
d52fea5b
VS		 2540 if (level > last_enabled_level)
2541 wm->enable = false;
2542 else if (!ilk_validate_wm_level(level, max, wm))
2543 /* make sure all following levels get disabled */
2544 last_enabled_level = level - 1;
0b2ae6d7
VS		 2545
2546 /*
2547 * The spec says it is preferred to disable
2548 * FBC WMs instead of disabling a WM level.
2549 */
2550 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2551 if (wm->enable)
2552 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2553 wm->fbc_val = 0;
2554 }
2555 }
6c8b6c28
VS		 2556
2557 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2558 /*
2559 * FIXME this is racy. FBC might get enabled later.
2560 * What we should check here is whether FBC can be
2561 * enabled sometime later.
2562 */
5db94019 2563 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2564 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2565 for (level = 2; level <= max_level; level++) {
2566 struct intel_wm_level *wm = &merged->wm[level];
2567
2568 wm->enable = false;
2569 }
2570 }
0b2ae6d7
VS		 2571}
2572
b380ca3c
VS		 2573static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2574{
2575 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2576 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2577}
2578
a68d68ee
VS		 2579/* The value we need to program into the WM_LPx latency field */
2580static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2581{
fac5e23e 2582 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2583
8652744b 2584 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2585 return 2 * level;
2586 else
2587 return dev_priv->wm.pri_latency[level];
2588}
2589
820c1980 2590static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2591 const struct intel_pipe_wm *merged,
609cedef 2592 enum intel_ddb_partitioning partitioning,
820c1980 2593 struct ilk_wm_values *results)
801bcfff 2594{
0b2ae6d7
VS		 2595 struct intel_crtc *intel_crtc;
2596 int level, wm_lp;
cca32e9a 2597
0362c781 2598 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2599 results->partitioning = partitioning;
cca32e9a 2600
0b2ae6d7 2601 /* LP1+ register values */
cca32e9a 2602 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2603 const struct intel_wm_level *r;
801bcfff 2604
b380ca3c 2605 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2606
0362c781 2607 r = &merged->wm[level];
cca32e9a 2608
d52fea5b
VS		 2609 /*
2610 * Maintain the watermark values even if the level is
2611 * disabled. Doing otherwise could cause underruns.
2612 */
2613 results->wm_lp[wm_lp - 1] =
a68d68ee 2614 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2615 (r->pri_val << WM1_LP_SR_SHIFT) |
2616 r->cur_val;
2617
d52fea5b
VS		 2618 if (r->enable)
2619 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2620
416f4727
VS		 2621 if (INTEL_INFO(dev)->gen >= 8)
2622 results->wm_lp[wm_lp - 1] |=
2623 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2624 else
2625 results->wm_lp[wm_lp - 1] |=
2626 r->fbc_val << WM1_LP_FBC_SHIFT;
2627
d52fea5b
VS		 2628 /*
2629 * Always set WM1S_LP_EN when spr_val != 0, even if the
2630 * level is disabled. Doing otherwise could cause underruns.
2631 */
6cef2b8a
VS		 2632 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2633 WARN_ON(wm_lp != 1);
2634 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2635 } else
2636 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2637 }
801bcfff 2638
0b2ae6d7 2639 /* LP0 register values */
d3fcc808 2640 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2641 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2642 const struct intel_wm_level *r =
2643 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2644
2645 if (WARN_ON(!r->enable))
2646 continue;
2647
ed4a6a7c 2648 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2649
0b2ae6d7
VS		 2650 results->wm_pipe[pipe] =
2651 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2652 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2653 r->cur_val;
801bcfff
PZ		 2654 }
2655}
2656
861f3389
PZ		 2657/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2658 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2659static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2660 struct intel_pipe_wm *r1,
2661 struct intel_pipe_wm *r2)
861f3389 2662{
5db94019 2663 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2664 int level1 = 0, level2 = 0;
861f3389 2665
198a1e9b
VS		 2666 for (level = 1; level <= max_level; level++) {
2667 if (r1->wm[level].enable)
2668 level1 = level;
2669 if (r2->wm[level].enable)
2670 level2 = level;
861f3389
PZ		 2671 }
2672
198a1e9b
VS		 2673 if (level1 == level2) {
2674 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2675 return r2;
2676 else
2677 return r1;
198a1e9b 2678 } else if (level1 > level2) {
861f3389
PZ		 2679 return r1;
2680 } else {
2681 return r2;
2682 }
2683}
2684
49a687c4
VS		 2685/* dirty bits used to track which watermarks need changes */
2686#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2687#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2688#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2689#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2690#define WM_DIRTY_FBC (1 << 24)
2691#define WM_DIRTY_DDB (1 << 25)
2692
055e393f 2693static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2694 const struct ilk_wm_values *old,
2695 const struct ilk_wm_values *new)
49a687c4
VS		 2696{
2697 unsigned int dirty = 0;
2698 enum pipe pipe;
2699 int wm_lp;
2700
055e393f 2701 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2702 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2703 dirty |= WM_DIRTY_LINETIME(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707
2708 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2709 dirty |= WM_DIRTY_PIPE(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713 }
2714
2715 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2716 dirty |= WM_DIRTY_FBC;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 if (old->partitioning != new->partitioning) {
2722 dirty |= WM_DIRTY_DDB;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 /* LP1+ watermarks already deemed dirty, no need to continue */
2728 if (dirty & WM_DIRTY_LP_ALL)
2729 return dirty;
2730
2731 /* Find the lowest numbered LP1+ watermark in need of an update... */
2732 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2734 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2735 break;
2736 }
2737
2738 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2739 for (; wm_lp <= 3; wm_lp++)
2740 dirty |= WM_DIRTY_LP(wm_lp);
2741
2742 return dirty;
2743}
2744
8553c18e
VS		 2745static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2746 unsigned int dirty)
801bcfff 2747{
820c1980 2748 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2749 bool changed = false;
801bcfff 2750
facd619b
VS		 2751 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2752 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2753 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2754 changed = true;
facd619b
VS		 2755 }
2756 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2757 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2758 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2759 changed = true;
facd619b
VS		 2760 }
2761 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2762 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2763 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2764 changed = true;
facd619b 2765 }
801bcfff 2766
facd619b
VS		 2767 /*
2768 * Don't touch WM1S_LP_EN here.
2769 * Doing so could cause underruns.
2770 */
6cef2b8a 2771
8553c18e
VS		 2772 return changed;
2773}
2774
2775/*
2776 * The spec says we shouldn't write when we don't need, because every write
2777 * causes WMs to be re-evaluated, expending some power.
2778 */
820c1980
ID		 2779static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2780 struct ilk_wm_values *results)
8553c18e 2781{
91c8a326 2782 struct drm_device *dev = &dev_priv->drm;
820c1980 2783 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2784 unsigned int dirty;
2785 uint32_t val;
2786
055e393f 2787 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2788 if (!dirty)
2789 return;
2790
2791 _ilk_disable_lp_wm(dev_priv, dirty);
2792
49a687c4 2793 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2794 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2795 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2796 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2797 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2798 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2799
49a687c4 2800 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2801 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2802 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2803 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2804 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2805 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2806
49a687c4 2807 if (dirty & WM_DIRTY_DDB) {
8652744b 2808 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2809 val = I915_READ(WM_MISC);
2810 if (results->partitioning == INTEL_DDB_PART_1_2)
2811 val &= ~WM_MISC_DATA_PARTITION_5_6;
2812 else
2813 val |= WM_MISC_DATA_PARTITION_5_6;
2814 I915_WRITE(WM_MISC, val);
2815 } else {
2816 val = I915_READ(DISP_ARB_CTL2);
2817 if (results->partitioning == INTEL_DDB_PART_1_2)
2818 val &= ~DISP_DATA_PARTITION_5_6;
2819 else
2820 val |= DISP_DATA_PARTITION_5_6;
2821 I915_WRITE(DISP_ARB_CTL2, val);
2822 }
1011d8c4
PZ		 2823 }
2824
49a687c4 2825 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2826 val = I915_READ(DISP_ARB_CTL);
2827 if (results->enable_fbc_wm)
2828 val &= ~DISP_FBC_WM_DIS;
2829 else
2830 val |= DISP_FBC_WM_DIS;
2831 I915_WRITE(DISP_ARB_CTL, val);
2832 }
2833
954911eb
ID		 2834 if (dirty & WM_DIRTY_LP(1) &&
2835 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2836 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2837
2838 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2839 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2840 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2841 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2842 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2843 }
801bcfff 2844
facd619b 2845 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2846 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2847 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2848 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2849 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2850 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2851
2852 dev_priv->wm.hw = *results;
801bcfff
PZ		 2853}
2854
ed4a6a7c 2855bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2856{
fac5e23e 2857 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2858
2859 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2860}
2861
656d1b89 2862#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2863
024c9045
MR		 2864/*
2865 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2866 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2867 * other universal planes are in indices 1..n. Note that this may leave unused
2868 * indices between the top "sprite" plane and the cursor.
2869 */
2870static int
2871skl_wm_plane_id(const struct intel_plane *plane)
2872{
2873 switch (plane->base.type) {
2874 case DRM_PLANE_TYPE_PRIMARY:
2875 return 0;
2876 case DRM_PLANE_TYPE_CURSOR:
2877 return PLANE_CURSOR;
2878 case DRM_PLANE_TYPE_OVERLAY:
2879 return plane->plane + 1;
2880 default:
2881 MISSING_CASE(plane->base.type);
2882 return plane->plane;
2883 }
2884}
2885
ee3d532f
PZ		 2886/*
2887 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2888 * so assume we'll always need it in order to avoid underruns.
2889 */
2890static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2891{
2892 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2893
2894 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2895 IS_KABYLAKE(dev_priv))
2896 return true;
2897
2898 return false;
2899}
2900
56feca91
PZ		 2901static bool
2902intel_has_sagv(struct drm_i915_private *dev_priv)
2903{
6e3100ec
PZ		 2904 if (IS_KABYLAKE(dev_priv))
2905 return true;
2906
2907 if (IS_SKYLAKE(dev_priv) &&
2908 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2909 return true;
2910
2911 return false;
56feca91
PZ		 2912}
2913
656d1b89
L		 2914/*
2915 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2916 * depending on power and performance requirements. The display engine access
2917 * to system memory is blocked during the adjustment time. Because of the
2918 * blocking time, having this enabled can cause full system hangs and/or pipe
2919 * underruns if we don't meet all of the following requirements:
2920 *
2921 * - <= 1 pipe enabled
2922 * - All planes can enable watermarks for latencies >= SAGV engine block time
2923 * - We're not using an interlaced display configuration
2924 */
2925int
16dcdc4e 2926intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2927{
2928 int ret;
2929
56feca91
PZ		 2930 if (!intel_has_sagv(dev_priv))
2931 return 0;
2932
2933 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2934 return 0;
2935
2936 DRM_DEBUG_KMS("Enabling the SAGV\n");
2937 mutex_lock(&dev_priv->rps.hw_lock);
2938
2939 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2940 GEN9_SAGV_ENABLE);
2941
2942 /* We don't need to wait for the SAGV when enabling */
2943 mutex_unlock(&dev_priv->rps.hw_lock);
2944
2945 /*
2946 * Some skl systems, pre-release machines in particular,
2947 * don't actually have an SAGV.
2948 */
6e3100ec 2949 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2950 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2951 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2952 return 0;
2953 } else if (ret < 0) {
2954 DRM_ERROR("Failed to enable the SAGV\n");
2955 return ret;
2956 }
2957
16dcdc4e 2958 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2959 return 0;
2960}
2961
2962static int
16dcdc4e 2963intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2964{
2965 int ret;
2966 uint32_t temp = GEN9_SAGV_DISABLE;
2967
2968 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2969 &temp);
2970 if (ret)
2971 return ret;
2972 else
2973 return temp & GEN9_SAGV_IS_DISABLED;
2974}
2975
2976int
16dcdc4e 2977intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2978{
2979 int ret, result;
2980
56feca91
PZ		 2981 if (!intel_has_sagv(dev_priv))
2982 return 0;
2983
2984 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2985 return 0;
2986
2987 DRM_DEBUG_KMS("Disabling the SAGV\n");
2988 mutex_lock(&dev_priv->rps.hw_lock);
2989
2990 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2991 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2992 mutex_unlock(&dev_priv->rps.hw_lock);
2993
2994 if (ret == -ETIMEDOUT) {
2995 DRM_ERROR("Request to disable SAGV timed out\n");
2996 return -ETIMEDOUT;
2997 }
2998
2999 /*
3000 * Some skl systems, pre-release machines in particular,
3001 * don't actually have an SAGV.
3002 */
6e3100ec 3003 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 3004 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3005 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3006 return 0;
3007 } else if (result < 0) {
3008 DRM_ERROR("Failed to disable the SAGV\n");
3009 return result;
3010 }
3011
16dcdc4e 3012 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3013 return 0;
3014}
3015
16dcdc4e 3016bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3017{
3018 struct drm_device *dev = state->dev;
3019 struct drm_i915_private *dev_priv = to_i915(dev);
3020 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3021 struct intel_crtc *crtc;
3022 struct intel_plane *plane;
656d1b89 3023 enum pipe pipe;
ee3d532f 3024 int level, id, latency;
656d1b89 3025
56feca91
PZ		 3026 if (!intel_has_sagv(dev_priv))
3027 return false;
3028
656d1b89
L		 3029 /*
3030 * SKL workaround: bspec recommends we disable the SAGV when we have
3031 * more then one pipe enabled
3032 *
3033 * If there are no active CRTCs, no additional checks need be performed
3034 */
3035 if (hweight32(intel_state->active_crtcs) == 0)
3036 return true;
3037 else if (hweight32(intel_state->active_crtcs) > 1)
3038 return false;
3039
3040 /* Since we're now guaranteed to only have one active CRTC... */
3041 pipe = ffs(intel_state->active_crtcs) - 1;
ee3d532f 3042 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
656d1b89 3043
c89cadd5 3044 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3045 return false;
3046
ee3d532f
PZ		 3047 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3048 id = skl_wm_plane_id(plane);
3049
656d1b89 3050 /* Skip this plane if it's not enabled */
ee3d532f 3051 if (intel_state->wm_results.plane[pipe][id][0] == 0)
656d1b89
L		 3052 continue;
3053
3054 /* Find the highest enabled wm level for this plane */
5db94019 3055 for (level = ilk_wm_max_level(dev_priv);
ee3d532f 3056 intel_state->wm_results.plane[pipe][id][level] == 0; --level)
656d1b89
L		 3057 { }
3058
ee3d532f
PZ		 3059 latency = dev_priv->wm.skl_latency[level];
3060
3061 if (skl_needs_memory_bw_wa(intel_state) &&
3062 plane->base.state->fb->modifier[0] ==
3063 I915_FORMAT_MOD_X_TILED)
3064 latency += 15;
3065
656d1b89
L		 3066 /*
3067 * If any of the planes on this pipe don't enable wm levels
3068 * that incur memory latencies higher then 30µs we can't enable
3069 * the SAGV
3070 */
ee3d532f 3071 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3072 return false;
3073 }
3074
3075 return true;
3076}
3077
b9cec075
DL		 3078static void
3079skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3080 const struct intel_crtc_state *cstate,
c107acfe
MR		 3081 struct skl_ddb_entry *alloc, /* out */
3082 int *num_active /* out */)
b9cec075 3083{
c107acfe
MR		 3084 struct drm_atomic_state *state = cstate->base.state;
3085 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3086 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3087 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3088 unsigned int pipe_size, ddb_size;
3089 int nth_active_pipe;
c107acfe 3090
a6d3460e 3091 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3092 alloc->start = 0;
3093 alloc->end = 0;
a6d3460e 3094 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3095 return;
3096 }
3097
a6d3460e
MR		 3098 if (intel_state->active_pipe_changes)
3099 *num_active = hweight32(intel_state->active_crtcs);
3100 else
3101 *num_active = hweight32(dev_priv->active_crtcs);
3102
6f3fff60
D		 3103 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3104 WARN_ON(ddb_size == 0);
b9cec075
DL		 3105
3106 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3107
c107acfe 3108 /*
a6d3460e
MR		 3109 * If the state doesn't change the active CRTC's, then there's
3110 * no need to recalculate; the existing pipe allocation limits
3111 * should remain unchanged. Note that we're safe from racing
3112 * commits since any racing commit that changes the active CRTC
3113 * list would need to grab _all_ crtc locks, including the one
3114 * we currently hold.
c107acfe 3115 */
a6d3460e 3116 if (!intel_state->active_pipe_changes) {
ce0ba283 3117 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
a6d3460e 3118 return;
c107acfe 3119 }
a6d3460e
MR		 3120
3121 nth_active_pipe = hweight32(intel_state->active_crtcs &
3122 (drm_crtc_mask(for_crtc) - 1));
3123 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3124 alloc->start = nth_active_pipe * ddb_size / *num_active;
3125 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3126}
3127
c107acfe 3128static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3129{
c107acfe 3130 if (num_active == 1)
b9cec075
DL		 3131 return 32;
3132
3133 return 8;
3134}
3135
a269c583
DL		 3136static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3137{
3138 entry->start = reg & 0x3ff;
3139 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3140 if (entry->end)
3141 entry->end += 1;
a269c583
DL		 3142}
3143
08db6652
DL		 3144void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3145 struct skl_ddb_allocation *ddb /* out */)
a269c583 3146{
a269c583
DL		 3147 enum pipe pipe;
3148 int plane;
3149 u32 val;
3150
b10f1b20
ML		 3151 memset(ddb, 0, sizeof(*ddb));
3152
a269c583 3153 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3154 enum intel_display_power_domain power_domain;
3155
3156 power_domain = POWER_DOMAIN_PIPE(pipe);
3157 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3158 continue;
3159
dd740780 3160 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3161 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3162 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3163 val);
3164 }
3165
3166 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3167 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3168 val);
4d800030
ID		 3169
3170 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3171 }
3172}
3173
9c2f7a9d
KM		 3174/*
3175 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3176 * The bspec defines downscale amount as:
3177 *
3178 * """
3179 * Horizontal down scale amount = maximum[1, Horizontal source size /
3180 * Horizontal destination size]
3181 * Vertical down scale amount = maximum[1, Vertical source size /
3182 * Vertical destination size]
3183 * Total down scale amount = Horizontal down scale amount *
3184 * Vertical down scale amount
3185 * """
3186 *
3187 * Return value is provided in 16.16 fixed point form to retain fractional part.
3188 * Caller should take care of dividing & rounding off the value.
3189 */
3190static uint32_t
3191skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3192{
3193 uint32_t downscale_h, downscale_w;
3194 uint32_t src_w, src_h, dst_w, dst_h;
3195
936e71e3 3196 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3197 return DRM_PLANE_HELPER_NO_SCALING;
3198
3199 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3200 src_w = drm_rect_width(&pstate->base.src);
3201 src_h = drm_rect_height(&pstate->base.src);
3202 dst_w = drm_rect_width(&pstate->base.dst);
3203 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3204 if (intel_rotation_90_or_270(pstate->base.rotation))
3205 swap(dst_w, dst_h);
3206
3207 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3208 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3209
3210 /* Provide result in 16.16 fixed point */
3211 return (uint64_t)downscale_w * downscale_h >> 16;
3212}
3213
b9cec075 3214static unsigned int
024c9045
MR		 3215skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3216 const struct drm_plane_state *pstate,
3217 int y)
b9cec075 3218{
a280f7dd 3219 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3220 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3221 uint32_t down_scale_amount, data_rate;
a280f7dd 3222 uint32_t width = 0, height = 0;
a1de91e5
MR		 3223 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3224
936e71e3 3225 if (!intel_pstate->base.visible)
a1de91e5
MR		 3226 return 0;
3227 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3228 return 0;
3229 if (y && format != DRM_FORMAT_NV12)
3230 return 0;
a280f7dd 3231
936e71e3
VS		 3232 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3233 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3234
3235 if (intel_rotation_90_or_270(pstate->rotation))
3236 swap(width, height);
2cd601c6
CK		 3237
3238 /* for planar format */
a1de91e5 3239 if (format == DRM_FORMAT_NV12) {
2cd601c6 3240 if (y) /* y-plane data rate */
8d19d7d9 3241 data_rate = width * height *
a1de91e5 3242 drm_format_plane_cpp(format, 0);
2cd601c6 3243 else /* uv-plane data rate */
8d19d7d9 3244 data_rate = (width / 2) * (height / 2) *
a1de91e5 3245 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3246 } else {
3247 /* for packed formats */
3248 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3249 }
3250
8d19d7d9
KM		 3251 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3252
3253 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3254}
3255
3256/*
3257 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3258 * a 8192x4096@32bpp framebuffer:
3259 * 3 * 4096 * 8192 * 4 < 2^32
3260 */
3261static unsigned int
9c74d826 3262skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3263{
9c74d826
MR		 3264 struct drm_crtc_state *cstate = &intel_cstate->base;
3265 struct drm_atomic_state *state = cstate->state;
3266 struct drm_crtc *crtc = cstate->crtc;
3267 struct drm_device *dev = crtc->dev;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3269 const struct drm_plane *plane;
024c9045 3270 const struct intel_plane *intel_plane;
a6d3460e 3271 struct drm_plane_state *pstate;
a1de91e5 3272 unsigned int rate, total_data_rate = 0;
9c74d826 3273 int id;
a6d3460e
MR		 3274 int i;
3275
3276 if (WARN_ON(!state))
3277 return 0;
b9cec075 3278
a1de91e5 3279 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3280 for_each_plane_in_state(state, plane, pstate, i) {
3281 id = skl_wm_plane_id(to_intel_plane(plane));
3282 intel_plane = to_intel_plane(plane);
3283
3284 if (intel_plane->pipe != intel_crtc->pipe)
3285 continue;
3286
3287 /* packed/uv */
3288 rate = skl_plane_relative_data_rate(intel_cstate,
3289 pstate, 0);
3290 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3291
3292 /* y-plane */
3293 rate = skl_plane_relative_data_rate(intel_cstate,
3294 pstate, 1);
3295 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3296 }
024c9045 3297
a1de91e5
MR		 3298 /* Calculate CRTC's total data rate from cached values */
3299 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3300 int id = skl_wm_plane_id(intel_plane);
024c9045 3301
a1de91e5 3302 /* packed/uv */
9c74d826
MR		 3303 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3304 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3305 }
3306
3307 return total_data_rate;
3308}
3309
cbcfd14b
KM		 3310static uint16_t
3311skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3312 const int y)
3313{
3314 struct drm_framebuffer *fb = pstate->fb;
3315 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3316 uint32_t src_w, src_h;
3317 uint32_t min_scanlines = 8;
3318 uint8_t plane_bpp;
3319
3320 if (WARN_ON(!fb))
3321 return 0;
3322
3323 /* For packed formats, no y-plane, return 0 */
3324 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3325 return 0;
3326
3327 /* For Non Y-tile return 8-blocks */
3328 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3329 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3330 return 8;
3331
936e71e3
VS		 3332 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3333 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3334
3335 if (intel_rotation_90_or_270(pstate->rotation))
3336 swap(src_w, src_h);
3337
3338 /* Halve UV plane width and height for NV12 */
3339 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3340 src_w /= 2;
3341 src_h /= 2;
3342 }
3343
3344 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3345 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3346 else
3347 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3348
3349 if (intel_rotation_90_or_270(pstate->rotation)) {
3350 switch (plane_bpp) {
3351 case 1:
3352 min_scanlines = 32;
3353 break;
3354 case 2:
3355 min_scanlines = 16;
3356 break;
3357 case 4:
3358 min_scanlines = 8;
3359 break;
3360 case 8:
3361 min_scanlines = 4;
3362 break;
3363 default:
3364 WARN(1, "Unsupported pixel depth %u for rotation",
3365 plane_bpp);
3366 min_scanlines = 32;
3367 }
3368 }
3369
3370 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3371}
3372
c107acfe 3373static int
024c9045 3374skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3375 struct skl_ddb_allocation *ddb /* out */)
3376{
c107acfe 3377 struct drm_atomic_state *state = cstate->base.state;
024c9045 3378 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3379 struct drm_device *dev = crtc->dev;
3380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3381 struct intel_plane *intel_plane;
c107acfe
MR		 3382 struct drm_plane *plane;
3383 struct drm_plane_state *pstate;
b9cec075 3384 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3385 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
b9cec075 3386 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3387 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3388 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3389 unsigned int total_data_rate;
c107acfe
MR		 3390 int num_active;
3391 int id, i;
b9cec075 3392
5a920b85
PZ		 3393 /* Clear the partitioning for disabled planes. */
3394 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3395 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3396
a6d3460e
MR		 3397 if (WARN_ON(!state))
3398 return 0;
3399
c107acfe 3400 if (!cstate->base.active) {
ce0ba283 3401 alloc->start = alloc->end = 0;
c107acfe
MR		 3402 return 0;
3403 }
3404
a6d3460e 3405 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3406 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3407 if (alloc_size == 0) {
3408 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3409 return 0;
b9cec075
DL		 3410 }
3411
c107acfe 3412 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3413 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3414 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3415
3416 alloc_size -= cursor_blocks;
b9cec075 3417
80958155 3418 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3419 for_each_plane_in_state(state, plane, pstate, i) {
3420 intel_plane = to_intel_plane(plane);
3421 id = skl_wm_plane_id(intel_plane);
c107acfe 3422
a6d3460e
MR		 3423 if (intel_plane->pipe != pipe)
3424 continue;
c107acfe 3425
936e71e3 3426 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3427 minimum[id] = 0;
3428 y_minimum[id] = 0;
3429 continue;
3430 }
3431 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3432 minimum[id] = 0;
3433 y_minimum[id] = 0;
3434 continue;
c107acfe 3435 }
a6d3460e 3436
cbcfd14b
KM		 3437 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3438 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3439 }
80958155 3440
c107acfe
MR		 3441 for (i = 0; i < PLANE_CURSOR; i++) {
3442 alloc_size -= minimum[i];
3443 alloc_size -= y_minimum[i];
80958155
DL		 3444 }
3445
b9cec075 3446 /*
80958155
DL		 3447 * 2. Distribute the remaining space in proportion to the amount of
3448 * data each plane needs to fetch from memory.
b9cec075
DL		 3449 *
3450 * FIXME: we may not allocate every single block here.
3451 */
024c9045 3452 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3453 if (total_data_rate == 0)
c107acfe 3454 return 0;
b9cec075 3455
34bb56af 3456 start = alloc->start;
024c9045 3457 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3458 unsigned int data_rate, y_data_rate;
3459 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3460 int id = skl_wm_plane_id(intel_plane);
b9cec075 3461
a1de91e5 3462 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3463
3464 /*
2cd601c6 3465 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3466 * promote the expression to 64 bits to avoid overflowing, the
3467 * result is < available as data_rate / total_data_rate < 1
3468 */
024c9045 3469 plane_blocks = minimum[id];
80958155
DL		 3470 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3471 total_data_rate);
b9cec075 3472
c107acfe
MR		 3473 /* Leave disabled planes at (0,0) */
3474 if (data_rate) {
3475 ddb->plane[pipe][id].start = start;
3476 ddb->plane[pipe][id].end = start + plane_blocks;
3477 }
b9cec075
DL		 3478
3479 start += plane_blocks;
2cd601c6
CK		 3480
3481 /*
3482 * allocation for y_plane part of planar format:
3483 */
a1de91e5
MR		 3484 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3485
3486 y_plane_blocks = y_minimum[id];
3487 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3488 total_data_rate);
2cd601c6 3489
c107acfe
MR		 3490 if (y_data_rate) {
3491 ddb->y_plane[pipe][id].start = start;
3492 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3493 }
a1de91e5
MR		 3494
3495 start += y_plane_blocks;
b9cec075
DL		 3496 }
3497
c107acfe 3498 return 0;
b9cec075
DL		 3499}
3500
5cec258b 3501static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3502{
3503 /* TODO: Take into account the scalers once we support them */
2d112de7 3504 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3505}
3506
3507/*
3508 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3509 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3510 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3511 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3512*/
ac484963 3513static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3514{
3515 uint32_t wm_intermediate_val, ret;
3516
3517 if (latency == 0)
3518 return UINT_MAX;
3519
ac484963 3520 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3521 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3522
3523 return ret;
3524}
3525
3526static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3527 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3528{
d4c2aa60 3529 uint32_t ret;
d4c2aa60 3530 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3531
3532 if (latency == 0)
3533 return UINT_MAX;
3534
2d41c0b5
PB		 3535 wm_intermediate_val = latency * pixel_rate;
3536 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3537 plane_blocks_per_line;
2d41c0b5
PB		 3538
3539 return ret;
3540}
3541
9c2f7a9d
KM		 3542static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3543 struct intel_plane_state *pstate)
3544{
3545 uint64_t adjusted_pixel_rate;
3546 uint64_t downscale_amount;
3547 uint64_t pixel_rate;
3548
3549 /* Shouldn't reach here on disabled planes... */
936e71e3 3550 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3551 return 0;
3552
3553 /*
3554 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3555 * with additional adjustments for plane-specific scaling.
3556 */
3557 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3558 downscale_amount = skl_plane_downscale_amount(pstate);
3559
3560 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3561 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3562
3563 return pixel_rate;
3564}
3565
55994c2c
MR		 3566static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3567 struct intel_crtc_state *cstate,
3568 struct intel_plane_state *intel_pstate,
3569 uint16_t ddb_allocation,
3570 int level,
3571 uint16_t *out_blocks, /* out */
3572 uint8_t *out_lines, /* out */
3573 bool *enabled /* out */)
2d41c0b5 3574{
33815fa5
MR		 3575 struct drm_plane_state *pstate = &intel_pstate->base;
3576 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3577 uint32_t latency = dev_priv->wm.skl_latency[level];
3578 uint32_t method1, method2;
3579 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3580 uint32_t res_blocks, res_lines;
3581 uint32_t selected_result;
ac484963 3582 uint8_t cpp;
a280f7dd 3583 uint32_t width = 0, height = 0;
9c2f7a9d 3584 uint32_t plane_pixel_rate;
75676ed4 3585 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3586 struct intel_atomic_state *state =
3587 to_intel_atomic_state(cstate->base.state);
3588 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3589
936e71e3 3590 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3591 *enabled = false;
3592 return 0;
3593 }
2d41c0b5 3594
ee3d532f
PZ		 3595 if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3596 latency += 15;
3597
936e71e3
VS		 3598 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3599 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3600
33815fa5 3601 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3602 swap(width, height);
3603
ac484963 3604 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3605 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3606
1186fa85
PZ		 3607 if (intel_rotation_90_or_270(pstate->rotation)) {
3608 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3609 drm_format_plane_cpp(fb->pixel_format, 1) :
3610 drm_format_plane_cpp(fb->pixel_format, 0);
3611
3612 switch (cpp) {
3613 case 1:
3614 y_min_scanlines = 16;
3615 break;
3616 case 2:
3617 y_min_scanlines = 8;
3618 break;
1186fa85
PZ		 3619 case 4:
3620 y_min_scanlines = 4;
3621 break;
86a462bc
PZ		 3622 default:
3623 MISSING_CASE(cpp);
3624 return -EINVAL;
1186fa85
PZ		 3625 }
3626 } else {
3627 y_min_scanlines = 4;
3628 }
3629
7a1a8aed
PZ		 3630 plane_bytes_per_line = width * cpp;
3631 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3632 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3633 plane_blocks_per_line =
3634 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3635 plane_blocks_per_line /= y_min_scanlines;
3636 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3637 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3638 + 1;
3639 } else {
3640 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3641 }
3642
9c2f7a9d
KM		 3643 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3644 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3645 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3646 latency,
7a1a8aed 3647 plane_blocks_per_line);
2d41c0b5 3648
75676ed4 3649 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
ee3d532f
PZ		 3650 if (apply_memory_bw_wa)
3651 y_tile_minimum *= 2;
75676ed4 3652
024c9045
MR		 3653 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3654 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3655 selected_result = max(method2, y_tile_minimum);
3656 } else {
f1db3eaf
PZ		 3657 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3658 (plane_bytes_per_line / 512 < 1))
3659 selected_result = method2;
3660 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3661 selected_result = min(method1, method2);
3662 else
3663 selected_result = method1;
3664 }
2d41c0b5 3665
d4c2aa60
TU		 3666 res_blocks = selected_result + 1;
3667 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3668
0fda6568 3669 if (level >= 1 && level <= 7) {
024c9045 3670 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3671 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3672 res_blocks += y_tile_minimum;
1186fa85 3673 res_lines += y_min_scanlines;
75676ed4 3674 } else {
0fda6568 3675 res_blocks++;
75676ed4 3676 }
0fda6568 3677 }
e6d66171 3678
55994c2c
MR		 3679 if (res_blocks >= ddb_allocation || res_lines > 31) {
3680 *enabled = false;
6b6bada7
MR		 3681
3682 /*
3683 * If there are no valid level 0 watermarks, then we can't
3684 * support this display configuration.
3685 */
3686 if (level) {
3687 return 0;
3688 } else {
3689 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3690 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3691 to_intel_crtc(cstate->base.crtc)->pipe,
3692 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3693 res_blocks, ddb_allocation, res_lines);
3694
3695 return -EINVAL;
3696 }
55994c2c 3697 }
e6d66171
DL		 3698
3699 *out_blocks = res_blocks;
3700 *out_lines = res_lines;
55994c2c 3701 *enabled = true;
2d41c0b5 3702
55994c2c 3703 return 0;
2d41c0b5
PB		 3704}
3705
f4a96752
MR		 3706static int
3707skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3708 struct skl_ddb_allocation *ddb,
3709 struct intel_crtc_state *cstate,
a62163e9 3710 struct intel_plane *intel_plane,
f4a96752
MR		 3711 int level,
3712 struct skl_wm_level *result)
2d41c0b5 3713{
f4a96752 3714 struct drm_atomic_state *state = cstate->base.state;
024c9045 3715 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3716 struct drm_plane *plane = &intel_plane->base;
3717 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3718 uint16_t ddb_blocks;
024c9045 3719 enum pipe pipe = intel_crtc->pipe;
55994c2c 3720 int ret;
a62163e9
L		 3721 int i = skl_wm_plane_id(intel_plane);
3722
3723 if (state)
3724 intel_pstate =
3725 intel_atomic_get_existing_plane_state(state,
3726 intel_plane);
024c9045 3727
f4a96752 3728 /*
a62163e9
L		 3729 * Note: If we start supporting multiple pending atomic commits against
3730 * the same planes/CRTC's in the future, plane->state will no longer be
3731 * the correct pre-state to use for the calculations here and we'll
3732 * need to change where we get the 'unchanged' plane data from.
3733 *
3734 * For now this is fine because we only allow one queued commit against
3735 * a CRTC. Even if the plane isn't modified by this transaction and we
3736 * don't have a plane lock, we still have the CRTC's lock, so we know
3737 * that no other transactions are racing with us to update it.
f4a96752 3738 */
a62163e9
L		 3739 if (!intel_pstate)
3740 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3741
a62163e9 3742 WARN_ON(!intel_pstate->base.fb);
f4a96752 3743
a62163e9 3744 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2d41c0b5 3745
a62163e9
L		 3746 ret = skl_compute_plane_wm(dev_priv,
3747 cstate,
3748 intel_pstate,
3749 ddb_blocks,
3750 level,
3751 &result->plane_res_b,
3752 &result->plane_res_l,
3753 &result->plane_en);
3754 if (ret)
3755 return ret;
f4a96752
MR		 3756
3757 return 0;
2d41c0b5
PB		 3758}
3759
407b50f3 3760static uint32_t
024c9045 3761skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3762{
024c9045 3763 if (!cstate->base.active)
407b50f3
DL		 3764 return 0;
3765
024c9045 3766 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3767 return 0;
407b50f3 3768
024c9045
MR		 3769 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3770 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3771}
3772
024c9045 3773static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3774 struct skl_wm_level *trans_wm /* out */)
407b50f3 3775{
024c9045 3776 if (!cstate->base.active)
407b50f3 3777 return;
9414f563
DL		 3778
3779 /* Until we know more, just disable transition WMs */
a62163e9 3780 trans_wm->plane_en = false;
407b50f3
DL		 3781}
3782
55994c2c
MR		 3783static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3784 struct skl_ddb_allocation *ddb,
3785 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3786{
024c9045 3787 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3788 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3789 struct intel_plane *intel_plane;
3790 struct skl_plane_wm *wm;
5db94019 3791 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3792 int ret;
2d41c0b5 3793
a62163e9
L		 3794 /*
3795 * We'll only calculate watermarks for planes that are actually
3796 * enabled, so make sure all other planes are set as disabled.
3797 */
3798 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3799
3800 for_each_intel_plane_mask(&dev_priv->drm,
3801 intel_plane,
3802 cstate->base.plane_mask) {
3803 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3804
3805 for (level = 0; level <= max_level; level++) {
3806 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3807 intel_plane, level,
3808 &wm->wm[level]);
3809 if (ret)
3810 return ret;
3811 }
3812 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3813 }
024c9045 3814 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3815
55994c2c 3816 return 0;
2d41c0b5
PB		 3817}
3818
3819static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3820 struct skl_pipe_wm *p_wm,
3821 struct skl_wm_values *r,
3822 struct intel_crtc *intel_crtc)
3823{
5db94019 3824 int level, max_level = ilk_wm_max_level(to_i915(dev));
a62163e9 3825 struct skl_plane_wm *plane_wm;
2d41c0b5 3826 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3827 uint32_t temp;
3828 int i;
2d41c0b5 3829
a62163e9
L		 3830 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3831 plane_wm = &p_wm->planes[i];
3832
3833 for (level = 0; level <= max_level; level++) {
2d41c0b5 3834 temp = 0;
2d41c0b5 3835
a62163e9 3836 temp |= plane_wm->wm[level].plane_res_l <<
2d41c0b5 3837 PLANE_WM_LINES_SHIFT;
a62163e9
L		 3838 temp |= plane_wm->wm[level].plane_res_b;
3839 if (plane_wm->wm[level].plane_en)
2d41c0b5
PB		 3840 temp |= PLANE_WM_EN;
3841
3842 r->plane[pipe][i][level] = temp;
2d41c0b5 3843 }
a62163e9 3844 }
2d41c0b5 3845
a62163e9
L		 3846 for (level = 0; level <= max_level; level++) {
3847 plane_wm = &p_wm->planes[PLANE_CURSOR];
2d41c0b5 3848 temp = 0;
a62163e9
L		 3849 temp |= plane_wm->wm[level].plane_res_l << PLANE_WM_LINES_SHIFT;
3850 temp |= plane_wm->wm[level].plane_res_b;
3851 if (plane_wm->wm[level].plane_en)
2d41c0b5
PB		 3852 temp |= PLANE_WM_EN;
3853
4969d33e 3854 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3855 }
3856
9414f563
DL		 3857 /* transition WMs */
3858 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
a62163e9 3859 plane_wm = &p_wm->planes[i];
9414f563 3860 temp = 0;
a62163e9
L		 3861 temp |= plane_wm->trans_wm.plane_res_l << PLANE_WM_LINES_SHIFT;
3862 temp |= plane_wm->trans_wm.plane_res_b;
3863 if (plane_wm->trans_wm.plane_en)
9414f563
DL		 3864 temp |= PLANE_WM_EN;
3865
3866 r->plane_trans[pipe][i] = temp;
3867 }
3868
a62163e9 3869 plane_wm = &p_wm->planes[PLANE_CURSOR];
9414f563 3870 temp = 0;
a62163e9
L		 3871 temp |= plane_wm->trans_wm.plane_res_l << PLANE_WM_LINES_SHIFT;
3872 temp |= plane_wm->trans_wm.plane_res_b;
3873 if (plane_wm->trans_wm.plane_en)
9414f563
DL		 3874 temp |= PLANE_WM_EN;
3875
4969d33e 3876 r->plane_trans[pipe][PLANE_CURSOR] = temp;
2d41c0b5
PB		 3877}
3878
f0f59a00
VS		 3879static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3880 i915_reg_t reg,
16160e3d
DL		 3881 const struct skl_ddb_entry *entry)
3882{
3883 if (entry->end)
3884 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3885 else
3886 I915_WRITE(reg, 0);
3887}
3888
62e0fb88
L		 3889void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3890 const struct skl_wm_values *wm,
3891 int plane)
3892{
3893 struct drm_crtc *crtc = &intel_crtc->base;
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3896 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3897 enum pipe pipe = intel_crtc->pipe;
3898
3899 for (level = 0; level <= max_level; level++) {
3900 I915_WRITE(PLANE_WM(pipe, plane, level),
3901 wm->plane[pipe][plane][level]);
3902 }
3903 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
27082493
L		 3904
3905 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3906 &wm->ddb.plane[pipe][plane]);
3907 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3908 &wm->ddb.y_plane[pipe][plane]);
62e0fb88
L		 3909}
3910
3911void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3912 const struct skl_wm_values *wm)
3913{
3914 struct drm_crtc *crtc = &intel_crtc->base;
3915 struct drm_device *dev = crtc->dev;
3916 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3917 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3918 enum pipe pipe = intel_crtc->pipe;
3919
3920 for (level = 0; level <= max_level; level++) {
3921 I915_WRITE(CUR_WM(pipe, level),
3922 wm->plane[pipe][PLANE_CURSOR][level]);
3923 }
3924 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3925
27082493
L		 3926 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3927 &wm->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3928}
3929
27082493
L		 3930static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3931 const struct skl_ddb_entry *b)
0e8fb7ba 3932{
27082493 3933 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3934}
3935
27082493 3936bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
ce0ba283 3937 struct intel_crtc *intel_crtc)
0e8fb7ba 3938{
ce0ba283
L		 3939 struct drm_crtc *other_crtc;
3940 struct drm_crtc_state *other_cstate;
3941 struct intel_crtc *other_intel_crtc;
3942 const struct skl_ddb_entry *ddb =
3943 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3944 int i;
0e8fb7ba 3945
ce0ba283
L		 3946 for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3947 other_intel_crtc = to_intel_crtc(other_crtc);
0e8fb7ba 3948
ce0ba283 3949 if (other_intel_crtc == intel_crtc)
0e8fb7ba
DL		 3950 continue;
3951
ce0ba283 3952 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
27082493 3953 return true;
0e8fb7ba
DL		 3954 }
3955
27082493 3956 return false;
0e8fb7ba
DL		 3957}
3958
55994c2c
MR		 3959static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3960 struct skl_ddb_allocation *ddb, /* out */
3961 struct skl_pipe_wm *pipe_wm, /* out */
3962 bool *changed /* out */)
2d41c0b5 3963{
f4a96752
MR		 3964 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3965 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3966 int ret;
2d41c0b5 3967
55994c2c
MR		 3968 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3969 if (ret)
3970 return ret;
2d41c0b5 3971
4e0963c7 3972 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3973 *changed = false;
3974 else
3975 *changed = true;
2d41c0b5 3976
55994c2c 3977 return 0;
2d41c0b5
PB		 3978}
3979
9b613022
MR		 3980static uint32_t
3981pipes_modified(struct drm_atomic_state *state)
3982{
3983 struct drm_crtc *crtc;
3984 struct drm_crtc_state *cstate;
3985 uint32_t i, ret = 0;
3986
3987 for_each_crtc_in_state(state, crtc, cstate, i)
3988 ret |= drm_crtc_mask(crtc);
3989
3990 return ret;
3991}
3992
bb7791bd 3993static int
7f60e200
PZ		 3994skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3995{
3996 struct drm_atomic_state *state = cstate->base.state;
3997 struct drm_device *dev = state->dev;
3998 struct drm_crtc *crtc = cstate->base.crtc;
3999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4000 struct drm_i915_private *dev_priv = to_i915(dev);
4001 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4002 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4003 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4004 struct drm_plane_state *plane_state;
4005 struct drm_plane *plane;
4006 enum pipe pipe = intel_crtc->pipe;
4007 int id;
4008
4009 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4010
4011 drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
4012 id = skl_wm_plane_id(to_intel_plane(plane));
4013
4014 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
4015 &new_ddb->plane[pipe][id]) &&
4016 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
4017 &new_ddb->y_plane[pipe][id]))
4018 continue;
4019
4020 plane_state = drm_atomic_get_plane_state(state, plane);
4021 if (IS_ERR(plane_state))
4022 return PTR_ERR(plane_state);
4023 }
4024
4025 return 0;
4026}
4027
98d39494
MR		 4028static int
4029skl_compute_ddb(struct drm_atomic_state *state)
4030{
4031 struct drm_device *dev = state->dev;
4032 struct drm_i915_private *dev_priv = to_i915(dev);
4033 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4034 struct intel_crtc *intel_crtc;
734fa01f 4035 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4036 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4037 int ret;
4038
4039 /*
4040 * If this is our first atomic update following hardware readout,
4041 * we can't trust the DDB that the BIOS programmed for us. Let's
4042 * pretend that all pipes switched active status so that we'll
4043 * ensure a full DDB recompute.
4044 */
1b54a880
MR		 4045 if (dev_priv->wm.distrust_bios_wm) {
4046 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4047 state->acquire_ctx);
4048 if (ret)
4049 return ret;
4050
98d39494
MR		 4051 intel_state->active_pipe_changes = ~0;
4052
1b54a880
MR		 4053 /*
4054 * We usually only initialize intel_state->active_crtcs if we
4055 * we're doing a modeset; make sure this field is always
4056 * initialized during the sanitization process that happens
4057 * on the first commit too.
4058 */
4059 if (!intel_state->modeset)
4060 intel_state->active_crtcs = dev_priv->active_crtcs;
4061 }
4062
98d39494
MR		 4063 /*
4064 * If the modeset changes which CRTC's are active, we need to
4065 * recompute the DDB allocation for *all* active pipes, even
4066 * those that weren't otherwise being modified in any way by this
4067 * atomic commit. Due to the shrinking of the per-pipe allocations
4068 * when new active CRTC's are added, it's possible for a pipe that
4069 * we were already using and aren't changing at all here to suddenly
4070 * become invalid if its DDB needs exceeds its new allocation.
4071 *
4072 * Note that if we wind up doing a full DDB recompute, we can't let
4073 * any other display updates race with this transaction, so we need
4074 * to grab the lock on *all* CRTC's.
4075 */
734fa01f 4076 if (intel_state->active_pipe_changes) {
98d39494 4077 realloc_pipes = ~0;
734fa01f
MR		 4078 intel_state->wm_results.dirty_pipes = ~0;
4079 }
98d39494 4080
5a920b85
PZ		 4081 /*
4082 * We're not recomputing for the pipes not included in the commit, so
4083 * make sure we start with the current state.
4084 */
4085 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4086
98d39494
MR		 4087 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4088 struct intel_crtc_state *cstate;
4089
4090 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4091 if (IS_ERR(cstate))
4092 return PTR_ERR(cstate);
4093
734fa01f 4094 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4095 if (ret)
4096 return ret;
05a76d3d 4097
7f60e200 4098 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4099 if (ret)
4100 return ret;
98d39494
MR		 4101 }
4102
4103 return 0;
4104}
4105
2722efb9
MR		 4106static void
4107skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4108 struct skl_wm_values *src,
4109 enum pipe pipe)
4110{
2722efb9
MR		 4111 memcpy(dst->plane[pipe], src->plane[pipe],
4112 sizeof(dst->plane[pipe]));
4113 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4114 sizeof(dst->plane_trans[pipe]));
4115
2722efb9
MR		 4116 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4117 sizeof(dst->ddb.y_plane[pipe]));
4118 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4119 sizeof(dst->ddb.plane[pipe]));
4120}
4121
98d39494
MR		 4122static int
4123skl_compute_wm(struct drm_atomic_state *state)
4124{
4125 struct drm_crtc *crtc;
4126 struct drm_crtc_state *cstate;
734fa01f
MR		 4127 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4128 struct skl_wm_values *results = &intel_state->wm_results;
4129 struct skl_pipe_wm *pipe_wm;
98d39494 4130 bool changed = false;
734fa01f 4131 int ret, i;
98d39494
MR		 4132
4133 /*
4134 * If this transaction isn't actually touching any CRTC's, don't
4135 * bother with watermark calculation. Note that if we pass this
4136 * test, we're guaranteed to hold at least one CRTC state mutex,
4137 * which means we can safely use values like dev_priv->active_crtcs
4138 * since any racing commits that want to update them would need to
4139 * hold _all_ CRTC state mutexes.
4140 */
4141 for_each_crtc_in_state(state, crtc, cstate, i)
4142 changed = true;
4143 if (!changed)
4144 return 0;
4145
734fa01f
MR		 4146 /* Clear all dirty flags */
4147 results->dirty_pipes = 0;
4148
98d39494
MR		 4149 ret = skl_compute_ddb(state);
4150 if (ret)
4151 return ret;
4152
734fa01f
MR		 4153 /*
4154 * Calculate WM's for all pipes that are part of this transaction.
4155 * Note that the DDB allocation above may have added more CRTC's that
4156 * weren't otherwise being modified (and set bits in dirty_pipes) if
4157 * pipe allocations had to change.
4158 *
4159 * FIXME: Now that we're doing this in the atomic check phase, we
4160 * should allow skl_update_pipe_wm() to return failure in cases where
4161 * no suitable watermark values can be found.
4162 */
4163 for_each_crtc_in_state(state, crtc, cstate, i) {
4164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4165 struct intel_crtc_state *intel_cstate =
4166 to_intel_crtc_state(cstate);
4167
4168 pipe_wm = &intel_cstate->wm.skl.optimal;
4169 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4170 &changed);
4171 if (ret)
4172 return ret;
4173
4174 if (changed)
4175 results->dirty_pipes |= drm_crtc_mask(crtc);
4176
4177 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4178 /* This pipe's WM's did not change */
4179 continue;
4180
4181 intel_cstate->update_wm_pre = true;
4182 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4183 }
4184
98d39494
MR		 4185 return 0;
4186}
4187
2d41c0b5
PB		 4188static void skl_update_wm(struct drm_crtc *crtc)
4189{
4190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4191 struct drm_device *dev = crtc->dev;
fac5e23e 4192 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4193 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4194 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4195 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4196 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4197 enum pipe pipe = intel_crtc->pipe;
adda50b8 4198
734fa01f 4199 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4200 return;
4201
734fa01f
MR		 4202 intel_crtc->wm.active.skl = *pipe_wm;
4203
4204 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4205
2722efb9 4206 /*
27082493
L		 4207 * If this pipe isn't active already, we're going to be enabling it
4208 * very soon. Since it's safe to update a pipe's ddb allocation while
4209 * the pipe's shut off, just do so here. Already active pipes will have
4210 * their watermarks updated once we update their planes.
2722efb9 4211 */
27082493
L		 4212 if (crtc->state->active_changed) {
4213 int plane;
4214
4215 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4216 skl_write_plane_wm(intel_crtc, results, plane);
4217
4218 skl_write_cursor_wm(intel_crtc, results);
4219 }
4220
4221 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f 4222
ce0ba283
L		 4223 intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4224
734fa01f 4225 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4226}
4227
d890565c
VS		 4228static void ilk_compute_wm_config(struct drm_device *dev,
4229 struct intel_wm_config *config)
4230{
4231 struct intel_crtc *crtc;
4232
4233 /* Compute the currently _active_ config */
4234 for_each_intel_crtc(dev, crtc) {
4235 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4236
4237 if (!wm->pipe_enabled)
4238 continue;
4239
4240 config->sprites_enabled |= wm->sprites_enabled;
4241 config->sprites_scaled |= wm->sprites_scaled;
4242 config->num_pipes_active++;
4243 }
4244}
4245
ed4a6a7c 4246static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4247{
91c8a326 4248 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4249 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4250 struct ilk_wm_maximums max;
d890565c 4251 struct intel_wm_config config = {};
820c1980 4252 struct ilk_wm_values results = {};
77c122bc 4253 enum intel_ddb_partitioning partitioning;
261a27d1 4254
d890565c
VS		 4255 ilk_compute_wm_config(dev, &config);
4256
4257 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4258 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4259
4260 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4261 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4262 config.num_pipes_active == 1 && config.sprites_enabled) {
4263 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4264 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4265
820c1980 4266 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4267 } else {
198a1e9b 4268 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4269 }
4270
198a1e9b 4271 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4272 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4273
820c1980 4274 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4275
820c1980 4276 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4277}
4278
ed4a6a7c 4279static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4280{
ed4a6a7c
MR		 4281 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4282 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4283
ed4a6a7c 4284 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4285 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4286 ilk_program_watermarks(dev_priv);
4287 mutex_unlock(&dev_priv->wm.wm_mutex);
4288}
bf220452 4289
ed4a6a7c
MR		 4290static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4291{
4292 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4293 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4294
ed4a6a7c
MR		 4295 mutex_lock(&dev_priv->wm.wm_mutex);
4296 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4297 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4298 ilk_program_watermarks(dev_priv);
4299 }
4300 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4301}
4302
3078999f
PB		 4303static void skl_pipe_wm_active_state(uint32_t val,
4304 struct skl_pipe_wm *active,
4305 bool is_transwm,
3078999f
PB		 4306 int i,
4307 int level)
4308{
1bab7502 4309 struct skl_plane_wm *plane_wm = &active->planes[i];
3078999f
PB		 4310 bool is_enabled = (val & PLANE_WM_EN) != 0;
4311
4312 if (!is_transwm) {
1bab7502
L		 4313 plane_wm->wm[level].plane_en = is_enabled;
4314 plane_wm->wm[level].plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4315 plane_wm->wm[level].plane_res_l =
4316 (val >> PLANE_WM_LINES_SHIFT) & PLANE_WM_LINES_MASK;
3078999f 4317 } else {
1bab7502
L		 4318 plane_wm->trans_wm.plane_en = is_enabled;
4319 plane_wm->trans_wm.plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4320 plane_wm->trans_wm.plane_res_l =
4321 (val >> PLANE_WM_LINES_SHIFT) & PLANE_WM_LINES_MASK;
3078999f
PB		 4322 }
4323}
4324
4325static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4326{
4327 struct drm_device *dev = crtc->dev;
fac5e23e 4328 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4329 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4331 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4332 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4333 enum pipe pipe = intel_crtc->pipe;
4334 int level, i, max_level;
4335 uint32_t temp;
4336
5db94019 4337 max_level = ilk_wm_max_level(dev_priv);
3078999f 4338
3078999f
PB		 4339 for (level = 0; level <= max_level; level++) {
4340 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4341 hw->plane[pipe][i][level] =
4342 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4343 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4344 }
4345
4346 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4347 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4348 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4349
3ef00284 4350 if (!intel_crtc->active)
3078999f
PB		 4351 return;
4352
2b4b9f35 4353 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f 4354
b707aa50 4355 active->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4356
4357 for (level = 0; level <= max_level; level++) {
4358 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4359 temp = hw->plane[pipe][i][level];
1bab7502 4360 skl_pipe_wm_active_state(temp, active, false, i, level);
3078999f 4361 }
4969d33e 4362 temp = hw->plane[pipe][PLANE_CURSOR][level];
1bab7502
L		 4363 skl_pipe_wm_active_state(temp, active, false, PLANE_CURSOR,
4364 level);
3078999f
PB		 4365 }
4366
4367 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4368 temp = hw->plane_trans[pipe][i];
1bab7502 4369 skl_pipe_wm_active_state(temp, active, true, i, 0);
3078999f
PB		 4370 }
4371
4969d33e 4372 temp = hw->plane_trans[pipe][PLANE_CURSOR];
1bab7502 4373 skl_pipe_wm_active_state(temp, active, true, PLANE_CURSOR, 0);
4e0963c7
MR		 4374
4375 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4376}
4377
4378void skl_wm_get_hw_state(struct drm_device *dev)
4379{
fac5e23e 4380 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4381 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4382 struct drm_crtc *crtc;
4383
a269c583 4384 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4385 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4386 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4387
279e99d7
MR		 4388 if (dev_priv->active_crtcs) {
4389 /* Fully recompute DDB on first atomic commit */
4390 dev_priv->wm.distrust_bios_wm = true;
4391 } else {
4392 /* Easy/common case; just sanitize DDB now if everything off */
4393 memset(ddb, 0, sizeof(*ddb));
4394 }
3078999f
PB		 4395}
4396
243e6a44
VS		 4397static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4398{
4399 struct drm_device *dev = crtc->dev;
fac5e23e 4400 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4401 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4403 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4404 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4405 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4406 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4407 [PIPE_A] = WM0_PIPEA_ILK,
4408 [PIPE_B] = WM0_PIPEB_ILK,
4409 [PIPE_C] = WM0_PIPEC_IVB,
4410 };
4411
4412 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4413 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4414 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4415
15606534
VS		 4416 memset(active, 0, sizeof(*active));
4417
3ef00284 4418 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4419
4420 if (active->pipe_enabled) {
243e6a44
VS		 4421 u32 tmp = hw->wm_pipe[pipe];
4422
4423 /*
4424 * For active pipes LP0 watermark is marked as
4425 * enabled, and LP1+ watermaks as disabled since
4426 * we can't really reverse compute them in case
4427 * multiple pipes are active.
4428 */
4429 active->wm[0].enable = true;
4430 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4431 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4432 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4433 active->linetime = hw->wm_linetime[pipe];
4434 } else {
5db94019 4435 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4436
4437 /*
4438 * For inactive pipes, all watermark levels
4439 * should be marked as enabled but zeroed,
4440 * which is what we'd compute them to.
4441 */
4442 for (level = 0; level <= max_level; level++)
4443 active->wm[level].enable = true;
4444 }
4e0963c7
MR		 4445
4446 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4447}
4448
6eb1a681
VS		 4449#define _FW_WM(value, plane) \
4450 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4451#define _FW_WM_VLV(value, plane) \
4452 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4453
4454static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4455 struct vlv_wm_values *wm)
4456{
4457 enum pipe pipe;
4458 uint32_t tmp;
4459
4460 for_each_pipe(dev_priv, pipe) {
4461 tmp = I915_READ(VLV_DDL(pipe));
4462
4463 wm->ddl[pipe].primary =
4464 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4465 wm->ddl[pipe].cursor =
4466 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4467 wm->ddl[pipe].sprite[0] =
4468 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4469 wm->ddl[pipe].sprite[1] =
4470 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4471 }
4472
4473 tmp = I915_READ(DSPFW1);
4474 wm->sr.plane = _FW_WM(tmp, SR);
4475 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4476 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4477 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4478
4479 tmp = I915_READ(DSPFW2);
4480 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4481 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4482 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4483
4484 tmp = I915_READ(DSPFW3);
4485 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4486
4487 if (IS_CHERRYVIEW(dev_priv)) {
4488 tmp = I915_READ(DSPFW7_CHV);
4489 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4490 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4491
4492 tmp = I915_READ(DSPFW8_CHV);
4493 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4494 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4495
4496 tmp = I915_READ(DSPFW9_CHV);
4497 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4498 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4499
4500 tmp = I915_READ(DSPHOWM);
4501 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4502 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4503 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4504 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4505 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4506 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4507 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4508 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4509 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4510 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4511 } else {
4512 tmp = I915_READ(DSPFW7);
4513 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4514 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4515
4516 tmp = I915_READ(DSPHOWM);
4517 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4518 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4519 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4520 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4521 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4522 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4523 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4524 }
4525}
4526
4527#undef _FW_WM
4528#undef _FW_WM_VLV
4529
4530void vlv_wm_get_hw_state(struct drm_device *dev)
4531{
4532 struct drm_i915_private *dev_priv = to_i915(dev);
4533 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4534 struct intel_plane *plane;
4535 enum pipe pipe;
4536 u32 val;
4537
4538 vlv_read_wm_values(dev_priv, wm);
4539
4540 for_each_intel_plane(dev, plane) {
4541 switch (plane->base.type) {
4542 int sprite;
4543 case DRM_PLANE_TYPE_CURSOR:
4544 plane->wm.fifo_size = 63;
4545 break;
4546 case DRM_PLANE_TYPE_PRIMARY:
4547 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4548 break;
4549 case DRM_PLANE_TYPE_OVERLAY:
4550 sprite = plane->plane;
4551 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4552 break;
4553 }
4554 }
4555
4556 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4557 wm->level = VLV_WM_LEVEL_PM2;
4558
4559 if (IS_CHERRYVIEW(dev_priv)) {
4560 mutex_lock(&dev_priv->rps.hw_lock);
4561
4562 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4563 if (val & DSP_MAXFIFO_PM5_ENABLE)
4564 wm->level = VLV_WM_LEVEL_PM5;
4565
58590c14
VS		 4566 /*
4567 * If DDR DVFS is disabled in the BIOS, Punit
4568 * will never ack the request. So if that happens
4569 * assume we don't have to enable/disable DDR DVFS
4570 * dynamically. To test that just set the REQ_ACK
4571 * bit to poke the Punit, but don't change the
4572 * HIGH/LOW bits so that we don't actually change
4573 * the current state.
4574 */
6eb1a681 4575 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4576 val |= FORCE_DDR_FREQ_REQ_ACK;
4577 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4578
4579 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4580 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4581 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4582 "assuming DDR DVFS is disabled\n");
4583 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4584 } else {
4585 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4586 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4587 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4588 }
6eb1a681
VS		 4589
4590 mutex_unlock(&dev_priv->rps.hw_lock);
4591 }
4592
4593 for_each_pipe(dev_priv, pipe)
4594 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4595 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4596 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4597
4598 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4599 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4600}
4601
243e6a44
VS		 4602void ilk_wm_get_hw_state(struct drm_device *dev)
4603{
fac5e23e 4604 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4605 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4606 struct drm_crtc *crtc;
4607
70e1e0ec 4608 for_each_crtc(dev, crtc)
243e6a44
VS		 4609 ilk_pipe_wm_get_hw_state(crtc);
4610
4611 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4612 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4613 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4614
4615 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4616 if (INTEL_INFO(dev)->gen >= 7) {
4617 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4618 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4619 }
243e6a44 4620
8652744b 4621 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4622 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4623 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4624 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4625 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4626 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4627
4628 hw->enable_fbc_wm =
4629 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4630}
4631
b445e3b0
ED		 4632/**
4633 * intel_update_watermarks - update FIFO watermark values based on current modes
4634 *
4635 * Calculate watermark values for the various WM regs based on current mode
4636 * and plane configuration.
4637 *
4638 * There are several cases to deal with here:
4639 * - normal (i.e. non-self-refresh)
4640 * - self-refresh (SR) mode
4641 * - lines are large relative to FIFO size (buffer can hold up to 2)
4642 * - lines are small relative to FIFO size (buffer can hold more than 2
4643 * lines), so need to account for TLB latency
4644 *
4645 * The normal calculation is:
4646 * watermark = dotclock * bytes per pixel * latency
4647 * where latency is platform & configuration dependent (we assume pessimal
4648 * values here).
4649 *
4650 * The SR calculation is:
4651 * watermark = (trunc(latency/line time)+1) * surface width *
4652 * bytes per pixel
4653 * where
4654 * line time = htotal / dotclock
4655 * surface width = hdisplay for normal plane and 64 for cursor
4656 * and latency is assumed to be high, as above.
4657 *
4658 * The final value programmed to the register should always be rounded up,
4659 * and include an extra 2 entries to account for clock crossings.
4660 *
4661 * We don't use the sprite, so we can ignore that. And on Crestline we have
4662 * to set the non-SR watermarks to 8.
4663 */
46ba614c 4664void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4665{
fac5e23e 4666 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4667
4668 if (dev_priv->display.update_wm)
46ba614c 4669 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4670}
4671
e2828914 4672/*
9270388e 4673 * Lock protecting IPS related data structures
9270388e
DV		 4674 */
4675DEFINE_SPINLOCK(mchdev_lock);
4676
4677/* Global for IPS driver to get at the current i915 device. Protected by
4678 * mchdev_lock. */
4679static struct drm_i915_private *i915_mch_dev;
4680
91d14251 4681bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4682{
2b4e57bd
ED		 4683 u16 rgvswctl;
4684
9270388e
DV		 4685 assert_spin_locked(&mchdev_lock);
4686
2b4e57bd
ED		 4687 rgvswctl = I915_READ16(MEMSWCTL);
4688 if (rgvswctl & MEMCTL_CMD_STS) {
4689 DRM_DEBUG("gpu busy, RCS change rejected\n");
4690 return false; /* still busy with another command */
4691 }
4692
4693 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4694 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4695 I915_WRITE16(MEMSWCTL, rgvswctl);
4696 POSTING_READ16(MEMSWCTL);
4697
4698 rgvswctl |= MEMCTL_CMD_STS;
4699 I915_WRITE16(MEMSWCTL, rgvswctl);
4700
4701 return true;
4702}
4703
91d14251 4704static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4705{
84f1b20f 4706 u32 rgvmodectl;
2b4e57bd
ED		 4707 u8 fmax, fmin, fstart, vstart;
4708
9270388e
DV		 4709 spin_lock_irq(&mchdev_lock);
4710
84f1b20f
TU		 4711 rgvmodectl = I915_READ(MEMMODECTL);
4712
2b4e57bd
ED		 4713 /* Enable temp reporting */
4714 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4715 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4716
4717 /* 100ms RC evaluation intervals */
4718 I915_WRITE(RCUPEI, 100000);
4719 I915_WRITE(RCDNEI, 100000);
4720
4721 /* Set max/min thresholds to 90ms and 80ms respectively */
4722 I915_WRITE(RCBMAXAVG, 90000);
4723 I915_WRITE(RCBMINAVG, 80000);
4724
4725 I915_WRITE(MEMIHYST, 1);
4726
4727 /* Set up min, max, and cur for interrupt handling */
4728 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4729 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4730 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4731 MEMMODE_FSTART_SHIFT;
4732
616847e7 4733 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4734 PXVFREQ_PX_SHIFT;
4735
20e4d407
DV		 4736 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4737 dev_priv->ips.fstart = fstart;
2b4e57bd 4738
20e4d407
DV		 4739 dev_priv->ips.max_delay = fstart;
4740 dev_priv->ips.min_delay = fmin;
4741 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4742
4743 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4744 fmax, fmin, fstart);
4745
4746 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4747
4748 /*
4749 * Interrupts will be enabled in ironlake_irq_postinstall
4750 */
4751
4752 I915_WRITE(VIDSTART, vstart);
4753 POSTING_READ(VIDSTART);
4754
4755 rgvmodectl |= MEMMODE_SWMODE_EN;
4756 I915_WRITE(MEMMODECTL, rgvmodectl);
4757
9270388e 4758 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4759 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4760 mdelay(1);
2b4e57bd 4761
91d14251 4762 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4763
7d81c3e0
VS		 4764 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4765 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4766 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4767 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4768 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4769
4770 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4771}
4772
91d14251 4773static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4774{
9270388e
DV		 4775 u16 rgvswctl;
4776
4777 spin_lock_irq(&mchdev_lock);
4778
4779 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4780
4781 /* Ack interrupts, disable EFC interrupt */
4782 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4783 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4784 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4785 I915_WRITE(DEIIR, DE_PCU_EVENT);
4786 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4787
4788 /* Go back to the starting frequency */
91d14251 4789 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4790 mdelay(1);
2b4e57bd
ED		 4791 rgvswctl |= MEMCTL_CMD_STS;
4792 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4793 mdelay(1);
2b4e57bd 4794
9270388e 4795 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4796}
4797
acbe9475
DV		 4798/* There's a funny hw issue where the hw returns all 0 when reading from
4799 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4800 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4801 * all limits and the gpu stuck at whatever frequency it is at atm).
4802 */
74ef1173 4803static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4804{
7b9e0ae6 4805 u32 limits;
2b4e57bd 4806
20b46e59
DV		 4807 /* Only set the down limit when we've reached the lowest level to avoid
4808 * getting more interrupts, otherwise leave this clear. This prevents a
4809 * race in the hw when coming out of rc6: There's a tiny window where
4810 * the hw runs at the minimal clock before selecting the desired
4811 * frequency, if the down threshold expires in that window we will not
4812 * receive a down interrupt. */
2d1fe073 4813 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4814 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4815 if (val <= dev_priv->rps.min_freq_softlimit)
4816 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4817 } else {
4818 limits = dev_priv->rps.max_freq_softlimit << 24;
4819 if (val <= dev_priv->rps.min_freq_softlimit)
4820 limits |= dev_priv->rps.min_freq_softlimit << 16;
4821 }
20b46e59
DV		 4822
4823 return limits;
4824}
4825
dd75fdc8
CW		 4826static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4827{
4828 int new_power;
8a586437
AG		 4829 u32 threshold_up = 0, threshold_down = 0; /* in % */
4830 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4831
4832 new_power = dev_priv->rps.power;
4833 switch (dev_priv->rps.power) {
4834 case LOW_POWER:
a72b5623
CW		 4835 if (val > dev_priv->rps.efficient_freq + 1 &&
4836 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4837 new_power = BETWEEN;
4838 break;
4839
4840 case BETWEEN:
a72b5623
CW		 4841 if (val <= dev_priv->rps.efficient_freq &&
4842 val < dev_priv->rps.cur_freq)
dd75fdc8 4843 new_power = LOW_POWER;
a72b5623
CW		 4844 else if (val >= dev_priv->rps.rp0_freq &&
4845 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4846 new_power = HIGH_POWER;
4847 break;
4848
4849 case HIGH_POWER:
a72b5623
CW		 4850 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4851 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4852 new_power = BETWEEN;
4853 break;
4854 }
4855 /* Max/min bins are special */
aed242ff 4856 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4857 new_power = LOW_POWER;
aed242ff 4858 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4859 new_power = HIGH_POWER;
4860 if (new_power == dev_priv->rps.power)
4861 return;
4862
4863 /* Note the units here are not exactly 1us, but 1280ns. */
4864 switch (new_power) {
4865 case LOW_POWER:
4866 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4867 ei_up = 16000;
4868 threshold_up = 95;
dd75fdc8
CW		 4869
4870 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4871 ei_down = 32000;
4872 threshold_down = 85;
dd75fdc8
CW		 4873 break;
4874
4875 case BETWEEN:
4876 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4877 ei_up = 13000;
4878 threshold_up = 90;
dd75fdc8
CW		 4879
4880 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4881 ei_down = 32000;
4882 threshold_down = 75;
dd75fdc8
CW		 4883 break;
4884
4885 case HIGH_POWER:
4886 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4887 ei_up = 10000;
4888 threshold_up = 85;
dd75fdc8
CW		 4889
4890 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4891 ei_down = 32000;
4892 threshold_down = 60;
dd75fdc8
CW		 4893 break;
4894 }
4895
8a586437 4896 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4897 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4898 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4899 GT_INTERVAL_FROM_US(dev_priv,
4900 ei_up * threshold_up / 100));
8a586437
AG		 4901
4902 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4903 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4904 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4905 GT_INTERVAL_FROM_US(dev_priv,
4906 ei_down * threshold_down / 100));
4907
4908 I915_WRITE(GEN6_RP_CONTROL,
4909 GEN6_RP_MEDIA_TURBO |
4910 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4911 GEN6_RP_MEDIA_IS_GFX |
4912 GEN6_RP_ENABLE |
4913 GEN6_RP_UP_BUSY_AVG |
4914 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4915
dd75fdc8 4916 dev_priv->rps.power = new_power;
8fb55197
CW		 4917 dev_priv->rps.up_threshold = threshold_up;
4918 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4919 dev_priv->rps.last_adj = 0;
4920}
4921
2876ce73
CW		 4922static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4923{
4924 u32 mask = 0;
4925
4926 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4927 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4928 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4929 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4930
7b3c29f6
CW		 4931 mask &= dev_priv->pm_rps_events;
4932
59d02a1f 4933 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4934}
4935
b8a5ff8d
JM		 4936/* gen6_set_rps is called to update the frequency request, but should also be
4937 * called when the range (min_delay and max_delay) is modified so that we can
4938 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4939static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4940{
23eafea6 4941 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4942 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4943 return;
4944
4fc688ce 4945 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4946 WARN_ON(val > dev_priv->rps.max_freq);
4947 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4948
eb64cad1
CW		 4949 /* min/max delay may still have been modified so be sure to
4950 * write the limits value.
4951 */
4952 if (val != dev_priv->rps.cur_freq) {
4953 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4954
dc97997a 4955 if (IS_GEN9(dev_priv))
5704195c
AG		 4956 I915_WRITE(GEN6_RPNSWREQ,
4957 GEN9_FREQUENCY(val));
dc97997a 4958 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4959 I915_WRITE(GEN6_RPNSWREQ,
4960 HSW_FREQUENCY(val));
4961 else
4962 I915_WRITE(GEN6_RPNSWREQ,
4963 GEN6_FREQUENCY(val) |
4964 GEN6_OFFSET(0) |
4965 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4966 }
7b9e0ae6 4967
7b9e0ae6
CW		 4968 /* Make sure we continue to get interrupts
4969 * until we hit the minimum or maximum frequencies.
4970 */
74ef1173 4971 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4972 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4973
d5570a72
BW		 4974 POSTING_READ(GEN6_RPNSWREQ);
4975
b39fb297 4976 dev_priv->rps.cur_freq = val;
0f94592e 4977 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4978}
4979
dc97997a 4980static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4981{
ffe02b40 4982 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4983 WARN_ON(val > dev_priv->rps.max_freq);
4984 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4985
dc97997a 4986 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4987 "Odd GPU freq value\n"))
4988 val &= ~1;
4989
cd25dd5b
D		 4990 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4991
8fb55197 4992 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4993 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4994 if (!IS_CHERRYVIEW(dev_priv))
4995 gen6_set_rps_thresholds(dev_priv, val);
4996 }
ffe02b40 4997
ffe02b40
VS		 4998 dev_priv->rps.cur_freq = val;
4999 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5000}
5001
a7f6e231 5002/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5003 *
5004 * * If Gfx is Idle, then
a7f6e231
D		 5005 * 1. Forcewake Media well.
5006 * 2. Request idle freq.
5007 * 3. Release Forcewake of Media well.
76c3552f
D		 5008*/
5009static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5010{
aed242ff 5011 u32 val = dev_priv->rps.idle_freq;
5549d25f 5012
aed242ff 5013 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5014 return;
5015
a7f6e231
D		 5016 /* Wake up the media well, as that takes a lot less
5017 * power than the Render well. */
5018 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5019 valleyview_set_rps(dev_priv, val);
a7f6e231 5020 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5021}
5022
43cf3bf0
CW		 5023void gen6_rps_busy(struct drm_i915_private *dev_priv)
5024{
5025 mutex_lock(&dev_priv->rps.hw_lock);
5026 if (dev_priv->rps.enabled) {
5027 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5028 gen6_rps_reset_ei(dev_priv);
5029 I915_WRITE(GEN6_PMINTRMSK,
5030 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5031
c33d247d
CW		 5032 gen6_enable_rps_interrupts(dev_priv);
5033
2b83c4c4
MW		 5034 /* Ensure we start at the user's desired frequency */
5035 intel_set_rps(dev_priv,
5036 clamp(dev_priv->rps.cur_freq,
5037 dev_priv->rps.min_freq_softlimit,
5038 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5039 }
5040 mutex_unlock(&dev_priv->rps.hw_lock);
5041}
5042
b29c19b6
CW		 5043void gen6_rps_idle(struct drm_i915_private *dev_priv)
5044{
c33d247d
CW		 5045 /* Flush our bottom-half so that it does not race with us
5046 * setting the idle frequency and so that it is bounded by
5047 * our rpm wakeref. And then disable the interrupts to stop any
5048 * futher RPS reclocking whilst we are asleep.
5049 */
5050 gen6_disable_rps_interrupts(dev_priv);
5051
b29c19b6 5052 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5053 if (dev_priv->rps.enabled) {
dc97997a 5054 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5055 vlv_set_rps_idle(dev_priv);
7526ed79 5056 else
dc97997a 5057 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5058 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5059 I915_WRITE(GEN6_PMINTRMSK,
5060 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5061 }
8d3afd7d 5062 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5063
8d3afd7d 5064 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5065 while (!list_empty(&dev_priv->rps.clients))
5066 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5067 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5068}
5069
1854d5ca 5070void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5071 struct intel_rps_client *rps,
5072 unsigned long submitted)
b29c19b6 5073{
8d3afd7d
CW		 5074 /* This is intentionally racy! We peek at the state here, then
5075 * validate inside the RPS worker.
5076 */
67d97da3 5077 if (!(dev_priv->gt.awake &&
8d3afd7d 5078 dev_priv->rps.enabled &&
29ecd78d 5079 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5080 return;
43cf3bf0 5081
e61b9958
CW		 5082 /* Force a RPS boost (and don't count it against the client) if
5083 * the GPU is severely congested.
5084 */
d0bc54f2 5085 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5086 rps = NULL;
5087
8d3afd7d
CW		 5088 spin_lock(&dev_priv->rps.client_lock);
5089 if (rps == NULL || list_empty(&rps->link)) {
5090 spin_lock_irq(&dev_priv->irq_lock);
5091 if (dev_priv->rps.interrupts_enabled) {
5092 dev_priv->rps.client_boost = true;
c33d247d 5093 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5094 }
5095 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5096
2e1b8730
CW		 5097 if (rps != NULL) {
5098 list_add(&rps->link, &dev_priv->rps.clients);
5099 rps->boosts++;
1854d5ca
CW		 5100 } else
5101 dev_priv->rps.boosts++;
c0951f0c 5102 }
8d3afd7d 5103 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5104}
5105
dc97997a 5106void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5107{
dc97997a
CW		 5108 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5109 valleyview_set_rps(dev_priv, val);
ffe02b40 5110 else
dc97997a 5111 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5112}
5113
dc97997a 5114static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5115{
20e49366 5116 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5117 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5118}
5119
dc97997a 5120static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5121{
2030d684
AG		 5122 I915_WRITE(GEN6_RP_CONTROL, 0);
5123}
5124
dc97997a 5125static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5126{
d20d4f0c 5127 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5128 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5129 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5130}
5131
dc97997a 5132static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5133{
38807746
D		 5134 I915_WRITE(GEN6_RC_CONTROL, 0);
5135}
5136
dc97997a 5137static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5138{
98a2e5f9
D		 5139 /* we're doing forcewake before Disabling RC6,
5140 * This what the BIOS expects when going into suspend */
59bad947 5141 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5142
44fc7d5c 5143 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5144
59bad947 5145 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5146}
5147
dc97997a 5148static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5149{
dc97997a 5150 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5151 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5152 mode = GEN6_RC_CTL_RC6_ENABLE;
5153 else
5154 mode = 0;
5155 }
dc97997a 5156 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5157 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5158 "RC6 %s RC6p %s RC6pp %s\n",
5159 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5160 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5161 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5162
5163 else
b99d49cc
ID		 5164 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5165 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5166}
5167
dc97997a 5168static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5169{
72e96d64 5170 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5171 bool enable_rc6 = true;
5172 unsigned long rc6_ctx_base;
fc619841
ID		 5173 u32 rc_ctl;
5174 int rc_sw_target;
5175
5176 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5177 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5178 RC_SW_TARGET_STATE_SHIFT;
5179 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5180 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5181 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5182 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5183 rc_sw_target);
274008e8
SAK		 5184
5185 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5186 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5187 enable_rc6 = false;
5188 }
5189
5190 /*
5191 * The exact context size is not known for BXT, so assume a page size
5192 * for this check.
5193 */
5194 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5195 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5196 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5197 ggtt->stolen_reserved_size))) {
b99d49cc 5198 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5199 enable_rc6 = false;
5200 }
5201
5202 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5203 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5204 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5205 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5206 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5207 enable_rc6 = false;
5208 }
5209
fc619841
ID		 5210 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5211 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5212 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5213 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5214 enable_rc6 = false;
5215 }
5216
5217 if (!I915_READ(GEN6_GFXPAUSE)) {
5218 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5219 enable_rc6 = false;
5220 }
5221
5222 if (!I915_READ(GEN8_MISC_CTRL0)) {
5223 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5224 enable_rc6 = false;
5225 }
5226
5227 return enable_rc6;
5228}
5229
dc97997a 5230int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5231{
e7d66d89 5232 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5233 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5234 return 0;
5235
274008e8
SAK		 5236 if (!enable_rc6)
5237 return 0;
5238
dc97997a 5239 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5240 DRM_INFO("RC6 disabled by BIOS\n");
5241 return 0;
5242 }
5243
456470eb 5244 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5245 if (enable_rc6 >= 0) {
5246 int mask;
5247
dc97997a 5248 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5249 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5250 INTEL_RC6pp_ENABLE;
5251 else
5252 mask = INTEL_RC6_ENABLE;
5253
5254 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5255 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5256 "(requested %d, valid %d)\n",
5257 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5258
5259 return enable_rc6 & mask;
5260 }
2b4e57bd 5261
dc97997a 5262 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5263 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5264
5265 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5266}
5267
dc97997a 5268static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5269{
5270 /* All of these values are in units of 50MHz */
773ea9a8 5271
93ee2920 5272 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5273 if (IS_BROXTON(dev_priv)) {
773ea9a8 5274 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5275 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5276 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5277 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5278 } else {
773ea9a8 5279 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5280 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5281 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5282 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5283 }
3280e8b0 5284 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5285 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5286
93ee2920 5287 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5288 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5289 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5290 u32 ddcc_status = 0;
5291
5292 if (sandybridge_pcode_read(dev_priv,
5293 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5294 &ddcc_status) == 0)
93ee2920 5295 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5296 clamp_t(u8,
5297 ((ddcc_status >> 8) & 0xff),
5298 dev_priv->rps.min_freq,
5299 dev_priv->rps.max_freq);
93ee2920
TR		 5300 }
5301
dc97997a 5302 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5303 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5304 * the natural hardware unit for SKL
5305 */
c5e0688c
AG		 5306 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5307 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5308 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5309 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5310 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5311 }
3280e8b0
BW		 5312}
5313
3a45b05c
CW		 5314static void reset_rps(struct drm_i915_private *dev_priv,
5315 void (*set)(struct drm_i915_private *, u8))
5316{
5317 u8 freq = dev_priv->rps.cur_freq;
5318
5319 /* force a reset */
5320 dev_priv->rps.power = -1;
5321 dev_priv->rps.cur_freq = -1;
5322
5323 set(dev_priv, freq);
5324}
5325
b6fef0ef 5326/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5327static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5328{
b6fef0ef
JB		 5329 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5330
23eafea6 5331 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5332 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5333 /*
5334 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5335 * clear out the Control register just to avoid inconsitency
5336 * with debugfs interface, which will show Turbo as enabled
5337 * only and that is not expected by the User after adding the
5338 * WaGsvDisableTurbo. Apart from this there is no problem even
5339 * if the Turbo is left enabled in the Control register, as the
5340 * Up/Down interrupts would remain masked.
5341 */
dc97997a 5342 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5343 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5344 return;
5345 }
5346
0beb059a
AG		 5347 /* Program defaults and thresholds for RPS*/
5348 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5349 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5350
5351 /* 1 second timeout*/
5352 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5353 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5354
b6fef0ef 5355 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5356
0beb059a
AG		 5357 /* Leaning on the below call to gen6_set_rps to program/setup the
5358 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5359 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5360 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5361
5362 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5363}
5364
dc97997a 5365static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5366{
e2f80391 5367 struct intel_engine_cs *engine;
3b3f1650 5368 enum intel_engine_id id;
20e49366 5369 uint32_t rc6_mask = 0;
20e49366
ZW		 5370
5371 /* 1a: Software RC state - RC0 */
5372 I915_WRITE(GEN6_RC_STATE, 0);
5373
5374 /* 1b: Get forcewake during program sequence. Although the driver
5375 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5376 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5377
5378 /* 2a: Disable RC states. */
5379 I915_WRITE(GEN6_RC_CONTROL, 0);
5380
5381 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5382
5383 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5384 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5385 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5386 else
5387 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5388 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5389 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5390 for_each_engine(engine, dev_priv, id)
e2f80391 5391 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5392
1a3d1898 5393 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5394 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5395
20e49366 5396 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5397
38c23527
ZW		 5398 /* 2c: Program Coarse Power Gating Policies. */
5399 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5400 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5401
20e49366 5402 /* 3a: Enable RC6 */
dc97997a 5403 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5404 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5405 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5406 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5407 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5408 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5409 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5410 GEN7_RC_CTL_TO_MODE |
5411 rc6_mask);
3e7732a0
SAK		 5412 } else {
5413 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5414 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5415 GEN6_RC_CTL_EI_MODE(1) |
5416 rc6_mask);
3e7732a0 5417 }
20e49366 5418
cb07bae0
SK		 5419 /*
5420 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5421 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5422 */
dc97997a 5423 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5424 I915_WRITE(GEN9_PG_ENABLE, 0);
5425 else
5426 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5427 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5428
59bad947 5429 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5430}
5431
dc97997a 5432static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5433{
e2f80391 5434 struct intel_engine_cs *engine;
3b3f1650 5435 enum intel_engine_id id;
93ee2920 5436 uint32_t rc6_mask = 0;
6edee7f3
BW		 5437
5438 /* 1a: Software RC state - RC0 */
5439 I915_WRITE(GEN6_RC_STATE, 0);
5440
5441 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5442 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5443 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5444
5445 /* 2a: Disable RC states. */
5446 I915_WRITE(GEN6_RC_CONTROL, 0);
5447
6edee7f3
BW		 5448 /* 2b: Program RC6 thresholds.*/
5449 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5450 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5451 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5452 for_each_engine(engine, dev_priv, id)
e2f80391 5453 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5454 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5455 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5456 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5457 else
5458 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5459
5460 /* 3: Enable RC6 */
dc97997a 5461 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5462 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5463 intel_print_rc6_info(dev_priv, rc6_mask);
5464 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5465 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5466 GEN7_RC_CTL_TO_MODE |
5467 rc6_mask);
5468 else
5469 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5470 GEN6_RC_CTL_EI_MODE(1) |
5471 rc6_mask);
6edee7f3
BW		 5472
5473 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5474 I915_WRITE(GEN6_RPNSWREQ,
5475 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5476 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5477 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5478 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5479 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5480
5481 /* Docs recommend 900MHz, and 300 MHz respectively */
5482 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5483 dev_priv->rps.max_freq_softlimit << 24 |
5484 dev_priv->rps.min_freq_softlimit << 16);
5485
5486 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5487 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5488 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5489 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5490
5491 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5492
5493 /* 5: Enable RPS */
7526ed79
DV		 5494 I915_WRITE(GEN6_RP_CONTROL,
5495 GEN6_RP_MEDIA_TURBO |
5496 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5497 GEN6_RP_MEDIA_IS_GFX |
5498 GEN6_RP_ENABLE |
5499 GEN6_RP_UP_BUSY_AVG |
5500 GEN6_RP_DOWN_IDLE_AVG);
5501
5502 /* 6: Ring frequency + overclocking (our driver does this later */
5503
3a45b05c 5504 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5505
59bad947 5506 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5507}
5508
dc97997a 5509static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5510{
e2f80391 5511 struct intel_engine_cs *engine;
3b3f1650 5512 enum intel_engine_id id;
99ac9612 5513 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5514 u32 gtfifodbg;
2b4e57bd 5515 int rc6_mode;
b4ac5afc 5516 int ret;
2b4e57bd 5517
4fc688ce 5518 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5519
2b4e57bd
ED		 5520 /* Here begins a magic sequence of register writes to enable
5521 * auto-downclocking.
5522 *
5523 * Perhaps there might be some value in exposing these to
5524 * userspace...
5525 */
5526 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5527
5528 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5529 gtfifodbg = I915_READ(GTFIFODBG);
5530 if (gtfifodbg) {
2b4e57bd
ED		 5531 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5532 I915_WRITE(GTFIFODBG, gtfifodbg);
5533 }
5534
59bad947 5535 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5536
5537 /* disable the counters and set deterministic thresholds */
5538 I915_WRITE(GEN6_RC_CONTROL, 0);
5539
5540 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5541 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5542 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5543 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5544 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5545
3b3f1650 5546 for_each_engine(engine, dev_priv, id)
e2f80391 5547 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5548
5549 I915_WRITE(GEN6_RC_SLEEP, 0);
5550 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5551 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5552 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5553 else
5554 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5555 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5556 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5557
5a7dc92a 5558 /* Check if we are enabling RC6 */
dc97997a 5559 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5560 if (rc6_mode & INTEL_RC6_ENABLE)
5561 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5562
5a7dc92a 5563 /* We don't use those on Haswell */
dc97997a 5564 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5565 if (rc6_mode & INTEL_RC6p_ENABLE)
5566 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5567
5a7dc92a
ED		 5568 if (rc6_mode & INTEL_RC6pp_ENABLE)
5569 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5570 }
2b4e57bd 5571
dc97997a 5572 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5573
5574 I915_WRITE(GEN6_RC_CONTROL,
5575 rc6_mask |
5576 GEN6_RC_CTL_EI_MODE(1) |
5577 GEN6_RC_CTL_HW_ENABLE);
5578
dd75fdc8
CW		 5579 /* Power down if completely idle for over 50ms */
5580 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5581 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5582
42c0526c 5583 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5584 if (ret)
42c0526c 5585 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5586
3a45b05c 5587 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5588
31643d54
BW		 5589 rc6vids = 0;
5590 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5591 if (IS_GEN6(dev_priv) && ret) {
31643d54 5592 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5593 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5594 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5595 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5596 rc6vids &= 0xffff00;
5597 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5598 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5599 if (ret)
5600 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5601 }
5602
59bad947 5603 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5604}
5605
fb7404e8 5606static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5607{
5608 int min_freq = 15;
3ebecd07
CW		 5609 unsigned int gpu_freq;
5610 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5611 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5612 int scaling_factor = 180;
eda79642 5613 struct cpufreq_policy *policy;
2b4e57bd 5614
4fc688ce 5615 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5616
eda79642
BW		 5617 policy = cpufreq_cpu_get(0);
5618 if (policy) {
5619 max_ia_freq = policy->cpuinfo.max_freq;
5620 cpufreq_cpu_put(policy);
5621 } else {
5622 /*
5623 * Default to measured freq if none found, PCU will ensure we
5624 * don't go over
5625 */
2b4e57bd 5626 max_ia_freq = tsc_khz;
eda79642 5627 }
2b4e57bd
ED		 5628
5629 /* Convert from kHz to MHz */
5630 max_ia_freq /= 1000;
5631
153b4b95 5632 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5633 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5634 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5635
dc97997a 5636 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5637 /* Convert GT frequency to 50 HZ units */
5638 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5639 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5640 } else {
5641 min_gpu_freq = dev_priv->rps.min_freq;
5642 max_gpu_freq = dev_priv->rps.max_freq;
5643 }
5644
2b4e57bd
ED		 5645 /*
5646 * For each potential GPU frequency, load a ring frequency we'd like
5647 * to use for memory access. We do this by specifying the IA frequency
5648 * the PCU should use as a reference to determine the ring frequency.
5649 */
4c8c7743
AG		 5650 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5651 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5652 unsigned int ia_freq = 0, ring_freq = 0;
5653
dc97997a 5654 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5655 /*
5656 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5657 * No floor required for ring frequency on SKL.
5658 */
5659 ring_freq = gpu_freq;
dc97997a 5660 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5661 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5662 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5663 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5664 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5665 ring_freq = max(min_ring_freq, ring_freq);
5666 /* leave ia_freq as the default, chosen by cpufreq */
5667 } else {
5668 /* On older processors, there is no separate ring
5669 * clock domain, so in order to boost the bandwidth
5670 * of the ring, we need to upclock the CPU (ia_freq).
5671 *
5672 * For GPU frequencies less than 750MHz,
5673 * just use the lowest ring freq.
5674 */
5675 if (gpu_freq < min_freq)
5676 ia_freq = 800;
5677 else
5678 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5679 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5680 }
2b4e57bd 5681
42c0526c
BW		 5682 sandybridge_pcode_write(dev_priv,
5683 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5684 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5685 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5686 gpu_freq);
2b4e57bd 5687 }
2b4e57bd
ED		 5688}
5689
03af2045 5690static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5691{
5692 u32 val, rp0;
5693
5b5929cb 5694 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5695
43b67998 5696 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5697 case 8:
5698 /* (2 * 4) config */
5699 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5700 break;
5701 case 12:
5702 /* (2 * 6) config */
5703 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5704 break;
5705 case 16:
5706 /* (2 * 8) config */
5707 default:
5708 /* Setting (2 * 8) Min RP0 for any other combination */
5709 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5710 break;
095acd5f 5711 }
5b5929cb
JN		 5712
5713 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5714
2b6b3a09
D		 5715 return rp0;
5716}
5717
5718static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5719{
5720 u32 val, rpe;
5721
5722 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5723 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5724
5725 return rpe;
5726}
5727
7707df4a
D		 5728static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5729{
5730 u32 val, rp1;
5731
5b5929cb
JN		 5732 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5733 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5734
7707df4a
D		 5735 return rp1;
5736}
5737
f8f2b001
D		 5738static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5739{
5740 u32 val, rp1;
5741
5742 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5743
5744 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5745
5746 return rp1;
5747}
5748
03af2045 5749static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5750{
5751 u32 val, rp0;
5752
64936258 5753 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5754
5755 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5756 /* Clamp to max */
5757 rp0 = min_t(u32, rp0, 0xea);
5758
5759 return rp0;
5760}
5761
5762static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5763{
5764 u32 val, rpe;
5765
64936258 5766 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5767 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5768 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5769 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5770
5771 return rpe;
5772}
5773
03af2045 5774static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5775{
36146035
ID		 5776 u32 val;
5777
5778 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5779 /*
5780 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5781 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5782 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5783 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5784 * to make sure it matches what Punit accepts.
5785 */
5786 return max_t(u32, val, 0xc0);
0a073b84
JB		 5787}
5788
ae48434c
ID		 5789/* Check that the pctx buffer wasn't move under us. */
5790static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5791{
5792 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5793
5794 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5795 dev_priv->vlv_pctx->stolen->start);
5796}
5797
38807746
D		 5798
5799/* Check that the pcbr address is not empty. */
5800static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5801{
5802 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5803
5804 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5805}
5806
dc97997a 5807static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5808{
62106b4f 5809 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5810 unsigned long pctx_paddr, paddr;
38807746
D		 5811 u32 pcbr;
5812 int pctx_size = 32*1024;
5813
38807746
D		 5814 pcbr = I915_READ(VLV_PCBR);
5815 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5816 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5817 paddr = (dev_priv->mm.stolen_base +
62106b4f 5818 (ggtt->stolen_size - pctx_size));
38807746
D		 5819
5820 pctx_paddr = (paddr & (~4095));
5821 I915_WRITE(VLV_PCBR, pctx_paddr);
5822 }
ce611ef8
VS		 5823
5824 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5825}
5826
dc97997a 5827static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5828{
c9cddffc
JB		 5829 struct drm_i915_gem_object *pctx;
5830 unsigned long pctx_paddr;
5831 u32 pcbr;
5832 int pctx_size = 24*1024;
5833
5834 pcbr = I915_READ(VLV_PCBR);
5835 if (pcbr) {
5836 /* BIOS set it up already, grab the pre-alloc'd space */
5837 int pcbr_offset;
5838
5839 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5840 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5841 pcbr_offset,
190d6cd5 5842 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5843 pctx_size);
5844 goto out;
5845 }
5846
ce611ef8
VS		 5847 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5848
c9cddffc
JB		 5849 /*
5850 * From the Gunit register HAS:
5851 * The Gfx driver is expected to program this register and ensure
5852 * proper allocation within Gfx stolen memory. For example, this
5853 * register should be programmed such than the PCBR range does not
5854 * overlap with other ranges, such as the frame buffer, protected
5855 * memory, or any other relevant ranges.
5856 */
91c8a326 5857 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5858 if (!pctx) {
5859 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5860 goto out;
c9cddffc
JB		 5861 }
5862
5863 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5864 I915_WRITE(VLV_PCBR, pctx_paddr);
5865
5866out:
ce611ef8 5867 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5868 dev_priv->vlv_pctx = pctx;
5869}
5870
dc97997a 5871static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5872{
ae48434c
ID		 5873 if (WARN_ON(!dev_priv->vlv_pctx))
5874 return;
5875
34911fd3 5876 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5877 dev_priv->vlv_pctx = NULL;
5878}
5879
c30fec65
VS		 5880static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5881{
5882 dev_priv->rps.gpll_ref_freq =
5883 vlv_get_cck_clock(dev_priv, "GPLL ref",
5884 CCK_GPLL_CLOCK_CONTROL,
5885 dev_priv->czclk_freq);
5886
5887 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5888 dev_priv->rps.gpll_ref_freq);
5889}
5890
dc97997a 5891static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5892{
2bb25c17 5893 u32 val;
4e80519e 5894
dc97997a 5895 valleyview_setup_pctx(dev_priv);
4e80519e 5896
c30fec65
VS		 5897 vlv_init_gpll_ref_freq(dev_priv);
5898
2bb25c17
VS		 5899 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5900 switch ((val >> 6) & 3) {
5901 case 0:
5902 case 1:
5903 dev_priv->mem_freq = 800;
5904 break;
5905 case 2:
5906 dev_priv->mem_freq = 1066;
5907 break;
5908 case 3:
5909 dev_priv->mem_freq = 1333;
5910 break;
5911 }
80b83b62 5912 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5913
4e80519e
ID		 5914 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5915 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5916 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5917 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5918 dev_priv->rps.max_freq);
5919
5920 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5921 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5922 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5923 dev_priv->rps.efficient_freq);
5924
f8f2b001
D		 5925 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5926 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5927 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5928 dev_priv->rps.rp1_freq);
5929
4e80519e
ID		 5930 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5931 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5932 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5933 dev_priv->rps.min_freq);
4e80519e
ID		 5934}
5935
dc97997a 5936static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5937{
2bb25c17 5938 u32 val;
2b6b3a09 5939
dc97997a 5940 cherryview_setup_pctx(dev_priv);
2b6b3a09 5941
c30fec65
VS		 5942 vlv_init_gpll_ref_freq(dev_priv);
5943
a580516d 5944 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5945 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5946 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5947
2bb25c17 5948 switch ((val >> 2) & 0x7) {
2bb25c17 5949 case 3:
2bb25c17
VS		 5950 dev_priv->mem_freq = 2000;
5951 break;
bfa7df01 5952 default:
2bb25c17
VS		 5953 dev_priv->mem_freq = 1600;
5954 break;
5955 }
80b83b62 5956 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5957
2b6b3a09
D		 5958 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5959 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5960 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5961 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5962 dev_priv->rps.max_freq);
5963
5964 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5965 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5966 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5967 dev_priv->rps.efficient_freq);
5968
7707df4a
D		 5969 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5970 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5971 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5972 dev_priv->rps.rp1_freq);
5973
5b7c91b7
D		 5974 /* PUnit validated range is only [RPe, RP0] */
5975 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5976 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5977 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5978 dev_priv->rps.min_freq);
5979
1c14762d
VS		 5980 WARN_ONCE((dev_priv->rps.max_freq |
5981 dev_priv->rps.efficient_freq |
5982 dev_priv->rps.rp1_freq |
5983 dev_priv->rps.min_freq) & 1,
5984 "Odd GPU freq values\n");
38807746
D		 5985}
5986
dc97997a 5987static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5988{
dc97997a 5989 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5990}
5991
dc97997a 5992static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5993{
e2f80391 5994 struct intel_engine_cs *engine;
3b3f1650 5995 enum intel_engine_id id;
2b6b3a09 5996 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5997
5998 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5999
297b32ec
VS		 6000 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6001 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 6002 if (gtfifodbg) {
6003 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6004 gtfifodbg);
6005 I915_WRITE(GTFIFODBG, gtfifodbg);
6006 }
6007
6008 cherryview_check_pctx(dev_priv);
6009
6010 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6011 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6012 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6013
160614a2
VS		 6014 /* Disable RC states. */
6015 I915_WRITE(GEN6_RC_CONTROL, 0);
6016
38807746
D		 6017 /* 2a: Program RC6 thresholds.*/
6018 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6019 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6020 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6021
3b3f1650 6022 for_each_engine(engine, dev_priv, id)
e2f80391 6023 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6024 I915_WRITE(GEN6_RC_SLEEP, 0);
6025
f4f71c7d
D		 6026 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6027 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6028
6029 /* allows RC6 residency counter to work */
6030 I915_WRITE(VLV_COUNTER_CONTROL,
6031 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6032 VLV_MEDIA_RC6_COUNT_EN |
6033 VLV_RENDER_RC6_COUNT_EN));
6034
6035 /* For now we assume BIOS is allocating and populating the PCBR */
6036 pcbr = I915_READ(VLV_PCBR);
6037
38807746 6038 /* 3: Enable RC6 */
dc97997a
CW		 6039 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6040 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6041 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6042
6043 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6044
2b6b3a09 6045 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6046 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6047 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6048 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6049 I915_WRITE(GEN6_RP_UP_EI, 66000);
6050 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6051
6052 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6053
6054 /* 5: Enable RPS */
6055 I915_WRITE(GEN6_RP_CONTROL,
6056 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6057 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6058 GEN6_RP_ENABLE |
6059 GEN6_RP_UP_BUSY_AVG |
6060 GEN6_RP_DOWN_IDLE_AVG);
6061
3ef62342
D		 6062 /* Setting Fixed Bias */
6063 val = VLV_OVERRIDE_EN |
6064 VLV_SOC_TDP_EN |
6065 CHV_BIAS_CPU_50_SOC_50;
6066 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6067
2b6b3a09
D		 6068 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6069
8d40c3ae
VS		 6070 /* RPS code assumes GPLL is used */
6071 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6072
742f491d 6073 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6074 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6075
3a45b05c 6076 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6077
59bad947 6078 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6079}
6080
dc97997a 6081static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6082{
e2f80391 6083 struct intel_engine_cs *engine;
3b3f1650 6084 enum intel_engine_id id;
2a5913a8 6085 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6086
6087 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6088
ae48434c
ID		 6089 valleyview_check_pctx(dev_priv);
6090
297b32ec
VS		 6091 gtfifodbg = I915_READ(GTFIFODBG);
6092 if (gtfifodbg) {
f7d85c1e
JB		 6093 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6094 gtfifodbg);
0a073b84
JB		 6095 I915_WRITE(GTFIFODBG, gtfifodbg);
6096 }
6097
c8d9a590 6098 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6099 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6100
160614a2
VS		 6101 /* Disable RC states. */
6102 I915_WRITE(GEN6_RC_CONTROL, 0);
6103
cad725fe 6104 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6105 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6106 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6107 I915_WRITE(GEN6_RP_UP_EI, 66000);
6108 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6109
6110 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6111
6112 I915_WRITE(GEN6_RP_CONTROL,
6113 GEN6_RP_MEDIA_TURBO |
6114 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6115 GEN6_RP_MEDIA_IS_GFX |
6116 GEN6_RP_ENABLE |
6117 GEN6_RP_UP_BUSY_AVG |
6118 GEN6_RP_DOWN_IDLE_CONT);
6119
6120 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6121 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6122 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6123
3b3f1650 6124 for_each_engine(engine, dev_priv, id)
e2f80391 6125 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6126
2f0aa304 6127 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6128
6129 /* allows RC6 residency counter to work */
49798eb2 6130 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6131 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6132 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6133 VLV_MEDIA_RC6_COUNT_EN |
6134 VLV_RENDER_RC6_COUNT_EN));
31685c25 6135
dc97997a 6136 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6137 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6138
dc97997a 6139 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6140
a2b23fe0 6141 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6142
3ef62342
D		 6143 /* Setting Fixed Bias */
6144 val = VLV_OVERRIDE_EN |
6145 VLV_SOC_TDP_EN |
6146 VLV_BIAS_CPU_125_SOC_875;
6147 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6148
64936258 6149 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6150
8d40c3ae
VS		 6151 /* RPS code assumes GPLL is used */
6152 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6153
742f491d 6154 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6155 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6156
3a45b05c 6157 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6158
59bad947 6159 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6160}
6161
dde18883
ED		 6162static unsigned long intel_pxfreq(u32 vidfreq)
6163{
6164 unsigned long freq;
6165 int div = (vidfreq & 0x3f0000) >> 16;
6166 int post = (vidfreq & 0x3000) >> 12;
6167 int pre = (vidfreq & 0x7);
6168
6169 if (!pre)
6170 return 0;
6171
6172 freq = ((div * 133333) / ((1<<post) * pre));
6173
6174 return freq;
6175}
6176
eb48eb00
DV		 6177static const struct cparams {
6178 u16 i;
6179 u16 t;
6180 u16 m;
6181 u16 c;
6182} cparams[] = {
6183 { 1, 1333, 301, 28664 },
6184 { 1, 1066, 294, 24460 },
6185 { 1, 800, 294, 25192 },
6186 { 0, 1333, 276, 27605 },
6187 { 0, 1066, 276, 27605 },
6188 { 0, 800, 231, 23784 },
6189};
6190
f531dcb2 6191static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6192{
6193 u64 total_count, diff, ret;
6194 u32 count1, count2, count3, m = 0, c = 0;
6195 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6196 int i;
6197
02d71956
DV		 6198 assert_spin_locked(&mchdev_lock);
6199
20e4d407 6200 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6201
6202 /* Prevent division-by-zero if we are asking too fast.
6203 * Also, we don't get interesting results if we are polling
6204 * faster than once in 10ms, so just return the saved value
6205 * in such cases.
6206 */
6207 if (diff1 <= 10)
20e4d407 6208 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6209
6210 count1 = I915_READ(DMIEC);
6211 count2 = I915_READ(DDREC);
6212 count3 = I915_READ(CSIEC);
6213
6214 total_count = count1 + count2 + count3;
6215
6216 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6217 if (total_count < dev_priv->ips.last_count1) {
6218 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6219 diff += total_count;
6220 } else {
20e4d407 6221 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6222 }
6223
6224 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6225 if (cparams[i].i == dev_priv->ips.c_m &&
6226 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6227 m = cparams[i].m;
6228 c = cparams[i].c;
6229 break;
6230 }
6231 }
6232
6233 diff = div_u64(diff, diff1);
6234 ret = ((m * diff) + c);
6235 ret = div_u64(ret, 10);
6236
20e4d407
DV		 6237 dev_priv->ips.last_count1 = total_count;
6238 dev_priv->ips.last_time1 = now;
eb48eb00 6239
20e4d407 6240 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6241
6242 return ret;
6243}
6244
f531dcb2
CW		 6245unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6246{
6247 unsigned long val;
6248
dc97997a 6249 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6250 return 0;
6251
6252 spin_lock_irq(&mchdev_lock);
6253
6254 val = __i915_chipset_val(dev_priv);
6255
6256 spin_unlock_irq(&mchdev_lock);
6257
6258 return val;
6259}
6260
eb48eb00
DV		 6261unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6262{
6263 unsigned long m, x, b;
6264 u32 tsfs;
6265
6266 tsfs = I915_READ(TSFS);
6267
6268 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6269 x = I915_READ8(TR1);
6270
6271 b = tsfs & TSFS_INTR_MASK;
6272
6273 return ((m * x) / 127) - b;
6274}
6275
d972d6ee
MK		 6276static int _pxvid_to_vd(u8 pxvid)
6277{
6278 if (pxvid == 0)
6279 return 0;
6280
6281 if (pxvid >= 8 && pxvid < 31)
6282 pxvid = 31;
6283
6284 return (pxvid + 2) * 125;
6285}
6286
6287static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6288{
d972d6ee
MK		 6289 const int vd = _pxvid_to_vd(pxvid);
6290 const int vm = vd - 1125;
6291
dc97997a 6292 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6293 return vm > 0 ? vm : 0;
6294
6295 return vd;
eb48eb00
DV		 6296}
6297
02d71956 6298static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6299{
5ed0bdf2 6300 u64 now, diff, diffms;
eb48eb00
DV		 6301 u32 count;
6302
02d71956 6303 assert_spin_locked(&mchdev_lock);
eb48eb00 6304
5ed0bdf2
TG		 6305 now = ktime_get_raw_ns();
6306 diffms = now - dev_priv->ips.last_time2;
6307 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6308
6309 /* Don't divide by 0 */
eb48eb00
DV		 6310 if (!diffms)
6311 return;
6312
6313 count = I915_READ(GFXEC);
6314
20e4d407
DV		 6315 if (count < dev_priv->ips.last_count2) {
6316 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6317 diff += count;
6318 } else {
20e4d407 6319 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6320 }
6321
20e4d407
DV		 6322 dev_priv->ips.last_count2 = count;
6323 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6324
6325 /* More magic constants... */
6326 diff = diff * 1181;
6327 diff = div_u64(diff, diffms * 10);
20e4d407 6328 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6329}
6330
02d71956
DV		 6331void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6332{
dc97997a 6333 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6334 return;
6335
9270388e 6336 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6337
6338 __i915_update_gfx_val(dev_priv);
6339
9270388e 6340 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6341}
6342
f531dcb2 6343static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6344{
6345 unsigned long t, corr, state1, corr2, state2;
6346 u32 pxvid, ext_v;
6347
02d71956
DV		 6348 assert_spin_locked(&mchdev_lock);
6349
616847e7 6350 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6351 pxvid = (pxvid >> 24) & 0x7f;
6352 ext_v = pvid_to_extvid(dev_priv, pxvid);
6353
6354 state1 = ext_v;
6355
6356 t = i915_mch_val(dev_priv);
6357
6358 /* Revel in the empirically derived constants */
6359
6360 /* Correction factor in 1/100000 units */
6361 if (t > 80)
6362 corr = ((t * 2349) + 135940);
6363 else if (t >= 50)
6364 corr = ((t * 964) + 29317);
6365 else /* < 50 */
6366 corr = ((t * 301) + 1004);
6367
6368 corr = corr * ((150142 * state1) / 10000 - 78642);
6369 corr /= 100000;
20e4d407 6370 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6371
6372 state2 = (corr2 * state1) / 10000;
6373 state2 /= 100; /* convert to mW */
6374
02d71956 6375 __i915_update_gfx_val(dev_priv);
eb48eb00 6376
20e4d407 6377 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6378}
6379
f531dcb2
CW		 6380unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6381{
6382 unsigned long val;
6383
dc97997a 6384 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6385 return 0;
6386
6387 spin_lock_irq(&mchdev_lock);
6388
6389 val = __i915_gfx_val(dev_priv);
6390
6391 spin_unlock_irq(&mchdev_lock);
6392
6393 return val;
6394}
6395
eb48eb00
DV		 6396/**
6397 * i915_read_mch_val - return value for IPS use
6398 *
6399 * Calculate and return a value for the IPS driver to use when deciding whether
6400 * we have thermal and power headroom to increase CPU or GPU power budget.
6401 */
6402unsigned long i915_read_mch_val(void)
6403{
6404 struct drm_i915_private *dev_priv;
6405 unsigned long chipset_val, graphics_val, ret = 0;
6406
9270388e 6407 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6408 if (!i915_mch_dev)
6409 goto out_unlock;
6410 dev_priv = i915_mch_dev;
6411
f531dcb2
CW		 6412 chipset_val = __i915_chipset_val(dev_priv);
6413 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6414
6415 ret = chipset_val + graphics_val;
6416
6417out_unlock:
9270388e 6418 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6419
6420 return ret;
6421}
6422EXPORT_SYMBOL_GPL(i915_read_mch_val);
6423
6424/**
6425 * i915_gpu_raise - raise GPU frequency limit
6426 *
6427 * Raise the limit; IPS indicates we have thermal headroom.
6428 */
6429bool i915_gpu_raise(void)
6430{
6431 struct drm_i915_private *dev_priv;
6432 bool ret = true;
6433
9270388e 6434 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6435 if (!i915_mch_dev) {
6436 ret = false;
6437 goto out_unlock;
6438 }
6439 dev_priv = i915_mch_dev;
6440
20e4d407
DV		 6441 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6442 dev_priv->ips.max_delay--;
eb48eb00
DV		 6443
6444out_unlock:
9270388e 6445 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6446
6447 return ret;
6448}
6449EXPORT_SYMBOL_GPL(i915_gpu_raise);
6450
6451/**
6452 * i915_gpu_lower - lower GPU frequency limit
6453 *
6454 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6455 * frequency maximum.
6456 */
6457bool i915_gpu_lower(void)
6458{
6459 struct drm_i915_private *dev_priv;
6460 bool ret = true;
6461
9270388e 6462 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6463 if (!i915_mch_dev) {
6464 ret = false;
6465 goto out_unlock;
6466 }
6467 dev_priv = i915_mch_dev;
6468
20e4d407
DV		 6469 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6470 dev_priv->ips.max_delay++;
eb48eb00
DV		 6471
6472out_unlock:
9270388e 6473 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6474
6475 return ret;
6476}
6477EXPORT_SYMBOL_GPL(i915_gpu_lower);
6478
6479/**
6480 * i915_gpu_busy - indicate GPU business to IPS
6481 *
6482 * Tell the IPS driver whether or not the GPU is busy.
6483 */
6484bool i915_gpu_busy(void)
6485{
eb48eb00
DV		 6486 bool ret = false;
6487
9270388e 6488 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6489 if (i915_mch_dev)
6490 ret = i915_mch_dev->gt.awake;
9270388e 6491 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6492
6493 return ret;
6494}
6495EXPORT_SYMBOL_GPL(i915_gpu_busy);
6496
6497/**
6498 * i915_gpu_turbo_disable - disable graphics turbo
6499 *
6500 * Disable graphics turbo by resetting the max frequency and setting the
6501 * current frequency to the default.
6502 */
6503bool i915_gpu_turbo_disable(void)
6504{
6505 struct drm_i915_private *dev_priv;
6506 bool ret = true;
6507
9270388e 6508 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6509 if (!i915_mch_dev) {
6510 ret = false;
6511 goto out_unlock;
6512 }
6513 dev_priv = i915_mch_dev;
6514
20e4d407 6515 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6516
91d14251 6517 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6518 ret = false;
6519
6520out_unlock:
9270388e 6521 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6522
6523 return ret;
6524}
6525EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6526
6527/**
6528 * Tells the intel_ips driver that the i915 driver is now loaded, if
6529 * IPS got loaded first.
6530 *
6531 * This awkward dance is so that neither module has to depend on the
6532 * other in order for IPS to do the appropriate communication of
6533 * GPU turbo limits to i915.
6534 */
6535static void
6536ips_ping_for_i915_load(void)
6537{
6538 void (*link)(void);
6539
6540 link = symbol_get(ips_link_to_i915_driver);
6541 if (link) {
6542 link();
6543 symbol_put(ips_link_to_i915_driver);
6544 }
6545}
6546
6547void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6548{
02d71956
DV		 6549 /* We only register the i915 ips part with intel-ips once everything is
6550 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6551 spin_lock_irq(&mchdev_lock);
eb48eb00 6552 i915_mch_dev = dev_priv;
9270388e 6553 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6554
6555 ips_ping_for_i915_load();
6556}
6557
6558void intel_gpu_ips_teardown(void)
6559{
9270388e 6560 spin_lock_irq(&mchdev_lock);
eb48eb00 6561 i915_mch_dev = NULL;
9270388e 6562 spin_unlock_irq(&mchdev_lock);
eb48eb00 6563}
76c3552f 6564
dc97997a 6565static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6566{
dde18883
ED		 6567 u32 lcfuse;
6568 u8 pxw[16];
6569 int i;
6570
6571 /* Disable to program */
6572 I915_WRITE(ECR, 0);
6573 POSTING_READ(ECR);
6574
6575 /* Program energy weights for various events */
6576 I915_WRITE(SDEW, 0x15040d00);
6577 I915_WRITE(CSIEW0, 0x007f0000);
6578 I915_WRITE(CSIEW1, 0x1e220004);
6579 I915_WRITE(CSIEW2, 0x04000004);
6580
6581 for (i = 0; i < 5; i++)
616847e7 6582 I915_WRITE(PEW(i), 0);
dde18883 6583 for (i = 0; i < 3; i++)
616847e7 6584 I915_WRITE(DEW(i), 0);
dde18883
ED		 6585
6586 /* Program P-state weights to account for frequency power adjustment */
6587 for (i = 0; i < 16; i++) {
616847e7 6588 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6589 unsigned long freq = intel_pxfreq(pxvidfreq);
6590 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6591 PXVFREQ_PX_SHIFT;
6592 unsigned long val;
6593
6594 val = vid * vid;
6595 val *= (freq / 1000);
6596 val *= 255;
6597 val /= (127*127*900);
6598 if (val > 0xff)
6599 DRM_ERROR("bad pxval: %ld\n", val);
6600 pxw[i] = val;
6601 }
6602 /* Render standby states get 0 weight */
6603 pxw[14] = 0;
6604 pxw[15] = 0;
6605
6606 for (i = 0; i < 4; i++) {
6607 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6608 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6609 I915_WRITE(PXW(i), val);
dde18883
ED		 6610 }
6611
6612 /* Adjust magic regs to magic values (more experimental results) */
6613 I915_WRITE(OGW0, 0);
6614 I915_WRITE(OGW1, 0);
6615 I915_WRITE(EG0, 0x00007f00);
6616 I915_WRITE(EG1, 0x0000000e);
6617 I915_WRITE(EG2, 0x000e0000);
6618 I915_WRITE(EG3, 0x68000300);
6619 I915_WRITE(EG4, 0x42000000);
6620 I915_WRITE(EG5, 0x00140031);
6621 I915_WRITE(EG6, 0);
6622 I915_WRITE(EG7, 0);
6623
6624 for (i = 0; i < 8; i++)
616847e7 6625 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6626
6627 /* Enable PMON + select events */
6628 I915_WRITE(ECR, 0x80000019);
6629
6630 lcfuse = I915_READ(LCFUSE02);
6631
20e4d407 6632 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6633}
6634
dc97997a 6635void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6636{
b268c699
ID		 6637 /*
6638 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6639 * requirement.
6640 */
6641 if (!i915.enable_rc6) {
6642 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6643 intel_runtime_pm_get(dev_priv);
6644 }
e6069ca8 6645
b5163dbb 6646 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6647 mutex_lock(&dev_priv->rps.hw_lock);
6648
6649 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6650 if (IS_CHERRYVIEW(dev_priv))
6651 cherryview_init_gt_powersave(dev_priv);
6652 else if (IS_VALLEYVIEW(dev_priv))
6653 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6654 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6655 gen6_init_rps_frequencies(dev_priv);
6656
6657 /* Derive initial user preferences/limits from the hardware limits */
6658 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6659 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6660
6661 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6662 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6663
6664 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6665 dev_priv->rps.min_freq_softlimit =
6666 max_t(int,
6667 dev_priv->rps.efficient_freq,
6668 intel_freq_opcode(dev_priv, 450));
6669
99ac9612
CW		 6670 /* After setting max-softlimit, find the overclock max freq */
6671 if (IS_GEN6(dev_priv) ||
6672 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6673 u32 params = 0;
6674
6675 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6676 if (params & BIT(31)) { /* OC supported */
6677 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6678 (dev_priv->rps.max_freq & 0xff) * 50,
6679 (params & 0xff) * 50);
6680 dev_priv->rps.max_freq = params & 0xff;
6681 }
6682 }
6683
29ecd78d
CW		 6684 /* Finally allow us to boost to max by default */
6685 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6686
773ea9a8 6687 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6688 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6689
6690 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6691}
6692
dc97997a 6693void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6694{
8dac1e1f 6695 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6696 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6697
6698 if (!i915.enable_rc6)
6699 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6700}
6701
54b4f68f
CW		 6702/**
6703 * intel_suspend_gt_powersave - suspend PM work and helper threads
6704 * @dev_priv: i915 device
6705 *
6706 * We don't want to disable RC6 or other features here, we just want
6707 * to make sure any work we've queued has finished and won't bother
6708 * us while we're suspended.
6709 */
6710void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6711{
6712 if (INTEL_GEN(dev_priv) < 6)
6713 return;
6714
6715 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6716 intel_runtime_pm_put(dev_priv);
6717
6718 /* gen6_rps_idle() will be called later to disable interrupts */
6719}
6720
b7137e0c
CW		 6721void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6722{
6723 dev_priv->rps.enabled = true; /* force disabling */
6724 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6725
6726 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6727}
6728
dc97997a 6729void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6730{
b7137e0c
CW		 6731 if (!READ_ONCE(dev_priv->rps.enabled))
6732 return;
e494837a 6733
b7137e0c 6734 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6735
b7137e0c
CW		 6736 if (INTEL_GEN(dev_priv) >= 9) {
6737 gen9_disable_rc6(dev_priv);
6738 gen9_disable_rps(dev_priv);
6739 } else if (IS_CHERRYVIEW(dev_priv)) {
6740 cherryview_disable_rps(dev_priv);
6741 } else if (IS_VALLEYVIEW(dev_priv)) {
6742 valleyview_disable_rps(dev_priv);
6743 } else if (INTEL_GEN(dev_priv) >= 6) {
6744 gen6_disable_rps(dev_priv);
6745 } else if (IS_IRONLAKE_M(dev_priv)) {
6746 ironlake_disable_drps(dev_priv);
930ebb46 6747 }
b7137e0c
CW		 6748
6749 dev_priv->rps.enabled = false;
6750 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6751}
6752
b7137e0c 6753void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6754{
54b4f68f
CW		 6755 /* We shouldn't be disabling as we submit, so this should be less
6756 * racy than it appears!
6757 */
b7137e0c
CW		 6758 if (READ_ONCE(dev_priv->rps.enabled))
6759 return;
1a01ab3b 6760
b7137e0c
CW		 6761 /* Powersaving is controlled by the host when inside a VM */
6762 if (intel_vgpu_active(dev_priv))
6763 return;
0a073b84 6764
b7137e0c 6765 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6766
6767 if (IS_CHERRYVIEW(dev_priv)) {
6768 cherryview_enable_rps(dev_priv);
6769 } else if (IS_VALLEYVIEW(dev_priv)) {
6770 valleyview_enable_rps(dev_priv);
b7137e0c 6771 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6772 gen9_enable_rc6(dev_priv);
6773 gen9_enable_rps(dev_priv);
6774 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6775 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6776 } else if (IS_BROADWELL(dev_priv)) {
6777 gen8_enable_rps(dev_priv);
fb7404e8 6778 gen6_update_ring_freq(dev_priv);
b7137e0c 6779 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6780 gen6_enable_rps(dev_priv);
fb7404e8 6781 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6782 } else if (IS_IRONLAKE_M(dev_priv)) {
6783 ironlake_enable_drps(dev_priv);
6784 intel_init_emon(dev_priv);
0a073b84 6785 }
aed242ff
CW		 6786
6787 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6788 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6789
6790 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6791 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6792
54b4f68f 6793 dev_priv->rps.enabled = true;
b7137e0c
CW		 6794 mutex_unlock(&dev_priv->rps.hw_lock);
6795}
3cc134e3 6796
54b4f68f
CW		 6797static void __intel_autoenable_gt_powersave(struct work_struct *work)
6798{
6799 struct drm_i915_private *dev_priv =
6800 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6801 struct intel_engine_cs *rcs;
6802 struct drm_i915_gem_request *req;
6803
6804 if (READ_ONCE(dev_priv->rps.enabled))
6805 goto out;
6806
3b3f1650 6807 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6808 if (rcs->last_context)
6809 goto out;
6810
6811 if (!rcs->init_context)
6812 goto out;
6813
6814 mutex_lock(&dev_priv->drm.struct_mutex);
6815
6816 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6817 if (IS_ERR(req))
6818 goto unlock;
6819
6820 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6821 rcs->init_context(req);
6822
6823 /* Mark the device busy, calling intel_enable_gt_powersave() */
6824 i915_add_request_no_flush(req);
6825
6826unlock:
6827 mutex_unlock(&dev_priv->drm.struct_mutex);
6828out:
6829 intel_runtime_pm_put(dev_priv);
6830}
6831
6832void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6833{
6834 if (READ_ONCE(dev_priv->rps.enabled))
6835 return;
6836
6837 if (IS_IRONLAKE_M(dev_priv)) {
6838 ironlake_enable_drps(dev_priv);
54b4f68f 6839 intel_init_emon(dev_priv);
54b4f68f
CW		 6840 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6841 /*
6842 * PCU communication is slow and this doesn't need to be
6843 * done at any specific time, so do this out of our fast path
6844 * to make resume and init faster.
6845 *
6846 * We depend on the HW RC6 power context save/restore
6847 * mechanism when entering D3 through runtime PM suspend. So
6848 * disable RPM until RPS/RC6 is properly setup. We can only
6849 * get here via the driver load/system resume/runtime resume
6850 * paths, so the _noresume version is enough (and in case of
6851 * runtime resume it's necessary).
6852 */
6853 if (queue_delayed_work(dev_priv->wq,
6854 &dev_priv->rps.autoenable_work,
6855 round_jiffies_up_relative(HZ)))
6856 intel_runtime_pm_get_noresume(dev_priv);
6857 }
6858}
6859
3107bd48
DV		 6860static void ibx_init_clock_gating(struct drm_device *dev)
6861{
fac5e23e 6862 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6863
6864 /*
6865 * On Ibex Peak and Cougar Point, we need to disable clock
6866 * gating for the panel power sequencer or it will fail to
6867 * start up when no ports are active.
6868 */
6869 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6870}
6871
0e088b8f
VS		 6872static void g4x_disable_trickle_feed(struct drm_device *dev)
6873{
fac5e23e 6874 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6875 enum pipe pipe;
0e088b8f 6876
055e393f 6877 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6878 I915_WRITE(DSPCNTR(pipe),
6879 I915_READ(DSPCNTR(pipe)) |
6880 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6881
6882 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6883 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6884 }
6885}
6886
017636cc
VS		 6887static void ilk_init_lp_watermarks(struct drm_device *dev)
6888{
fac5e23e 6889 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6890
6891 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6892 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6893 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6894
6895 /*
6896 * Don't touch WM1S_LP_EN here.
6897 * Doing so could cause underruns.
6898 */
6899}
6900
1fa61106 6901static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6902{
fac5e23e 6903 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6904 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6905
f1e8fa56
DL		 6906 /*
6907 * Required for FBC
6908 * WaFbcDisableDpfcClockGating:ilk
6909 */
4d47e4f5
DL		 6910 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6911 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6912 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6913
6914 I915_WRITE(PCH_3DCGDIS0,
6915 MARIUNIT_CLOCK_GATE_DISABLE |
6916 SVSMUNIT_CLOCK_GATE_DISABLE);
6917 I915_WRITE(PCH_3DCGDIS1,
6918 VFMUNIT_CLOCK_GATE_DISABLE);
6919
6f1d69b0
ED		 6920 /*
6921 * According to the spec the following bits should be set in
6922 * order to enable memory self-refresh
6923 * The bit 22/21 of 0x42004
6924 * The bit 5 of 0x42020
6925 * The bit 15 of 0x45000
6926 */
6927 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6928 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6929 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6930 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6931 I915_WRITE(DISP_ARB_CTL,
6932 (I915_READ(DISP_ARB_CTL) |
6933 DISP_FBC_WM_DIS));
017636cc
VS		 6934
6935 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6936
6937 /*
6938 * Based on the document from hardware guys the following bits
6939 * should be set unconditionally in order to enable FBC.
6940 * The bit 22 of 0x42000
6941 * The bit 22 of 0x42004
6942 * The bit 7,8,9 of 0x42020.
6943 */
50a0bc90 6944 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6945 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6946 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6947 I915_READ(ILK_DISPLAY_CHICKEN1) |
6948 ILK_FBCQ_DIS);
6949 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6950 I915_READ(ILK_DISPLAY_CHICKEN2) |
6951 ILK_DPARB_GATE);
6f1d69b0
ED		 6952 }
6953
4d47e4f5
DL		 6954 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6955
6f1d69b0
ED		 6956 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6957 I915_READ(ILK_DISPLAY_CHICKEN2) |
6958 ILK_ELPIN_409_SELECT);
6959 I915_WRITE(_3D_CHICKEN2,
6960 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6961 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6962
ecdb4eb7 6963 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6964 I915_WRITE(CACHE_MODE_0,
6965 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6966
4e04632e
AG		 6967 /* WaDisable_RenderCache_OperationalFlush:ilk */
6968 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6969
0e088b8f 6970 g4x_disable_trickle_feed(dev);
bdad2b2f 6971
3107bd48
DV		 6972 ibx_init_clock_gating(dev);
6973}
6974
6975static void cpt_init_clock_gating(struct drm_device *dev)
6976{
fac5e23e 6977 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6978 int pipe;
3f704fa2 6979 uint32_t val;
3107bd48
DV		 6980
6981 /*
6982 * On Ibex Peak and Cougar Point, we need to disable clock
6983 * gating for the panel power sequencer or it will fail to
6984 * start up when no ports are active.
6985 */
cd664078
JB		 6986 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6987 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6988 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6989 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6990 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6991 /* The below fixes the weird display corruption, a few pixels shifted
6992 * downward, on (only) LVDS of some HP laptops with IVY.
6993 */
055e393f 6994 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6995 val = I915_READ(TRANS_CHICKEN2(pipe));
6996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6997 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6998 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6999 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 7000 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7001 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7002 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 7003 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7004 }
3107bd48 7005 /* WADP0ClockGatingDisable */
055e393f 7006 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7007 I915_WRITE(TRANS_CHICKEN1(pipe),
7008 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7009 }
6f1d69b0
ED		 7010}
7011
1d7aaa0c
DV		 7012static void gen6_check_mch_setup(struct drm_device *dev)
7013{
fac5e23e 7014 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7015 uint32_t tmp;
7016
7017 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7018 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7019 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7020 tmp);
1d7aaa0c
DV		 7021}
7022
1fa61106 7023static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7024{
fac5e23e 7025 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7026 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7027
231e54f6 7028 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7029
7030 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7031 I915_READ(ILK_DISPLAY_CHICKEN2) |
7032 ILK_ELPIN_409_SELECT);
7033
ecdb4eb7 7034 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7035 I915_WRITE(_3D_CHICKEN,
7036 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7037
4e04632e
AG		 7038 /* WaDisable_RenderCache_OperationalFlush:snb */
7039 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7040
8d85d272
VS		 7041 /*
7042 * BSpec recoomends 8x4 when MSAA is used,
7043 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7044 *
7045 * Note that PS/WM thread counts depend on the WIZ hashing
7046 * disable bit, which we don't touch here, but it's good
7047 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7048 */
7049 I915_WRITE(GEN6_GT_MODE,
98533251 7050 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7051
017636cc 7052 ilk_init_lp_watermarks(dev);
6f1d69b0 7053
6f1d69b0 7054 I915_WRITE(CACHE_MODE_0,
50743298 7055 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7056
7057 I915_WRITE(GEN6_UCGCTL1,
7058 I915_READ(GEN6_UCGCTL1) |
7059 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7060 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7061
7062 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7063 * gating disable must be set. Failure to set it results in
7064 * flickering pixels due to Z write ordering failures after
7065 * some amount of runtime in the Mesa "fire" demo, and Unigine
7066 * Sanctuary and Tropics, and apparently anything else with
7067 * alpha test or pixel discard.
7068 *
7069 * According to the spec, bit 11 (RCCUNIT) must also be set,
7070 * but we didn't debug actual testcases to find it out.
0f846f81 7071 *
ef59318c
VS		 7072 * WaDisableRCCUnitClockGating:snb
7073 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7074 */
7075 I915_WRITE(GEN6_UCGCTL2,
7076 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7077 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7078
5eb146dd 7079 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7080 I915_WRITE(_3D_CHICKEN3,
7081 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7082
e927ecde
VS		 7083 /*
7084 * Bspec says:
7085 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7086 * 3DSTATE_SF number of SF output attributes is more than 16."
7087 */
7088 I915_WRITE(_3D_CHICKEN3,
7089 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7090
6f1d69b0
ED		 7091 /*
7092 * According to the spec the following bits should be
7093 * set in order to enable memory self-refresh and fbc:
7094 * The bit21 and bit22 of 0x42000
7095 * The bit21 and bit22 of 0x42004
7096 * The bit5 and bit7 of 0x42020
7097 * The bit14 of 0x70180
7098 * The bit14 of 0x71180
4bb35334
DL		 7099 *
7100 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7101 */
7102 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7103 I915_READ(ILK_DISPLAY_CHICKEN1) |
7104 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7105 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7106 I915_READ(ILK_DISPLAY_CHICKEN2) |
7107 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7108 I915_WRITE(ILK_DSPCLK_GATE_D,
7109 I915_READ(ILK_DSPCLK_GATE_D) |
7110 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7111 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7112
0e088b8f 7113 g4x_disable_trickle_feed(dev);
f8f2ac9a 7114
3107bd48 7115 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7116
7117 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7118}
7119
7120static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7121{
7122 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7123
3aad9059 7124 /*
46680e0a 7125 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7126 *
7127 * This actually overrides the dispatch
7128 * mode for all thread types.
7129 */
6f1d69b0
ED		 7130 reg &= ~GEN7_FF_SCHED_MASK;
7131 reg |= GEN7_FF_TS_SCHED_HW;
7132 reg |= GEN7_FF_VS_SCHED_HW;
7133 reg |= GEN7_FF_DS_SCHED_HW;
7134
7135 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7136}
7137
17a303ec
PZ		 7138static void lpt_init_clock_gating(struct drm_device *dev)
7139{
fac5e23e 7140 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7141
7142 /*
7143 * TODO: this bit should only be enabled when really needed, then
7144 * disabled when not needed anymore in order to save power.
7145 */
4f8036a2 7146 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7147 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7148 I915_READ(SOUTH_DSPCLK_GATE_D) |
7149 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7150
7151 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7152 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7153 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7154 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7155}
7156
7d708ee4
ID		 7157static void lpt_suspend_hw(struct drm_device *dev)
7158{
fac5e23e 7159 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7160
4f8036a2 7161 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7162 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7163
7164 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7165 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7166 }
7167}
7168
450174fe
ID		 7169static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7170 int general_prio_credits,
7171 int high_prio_credits)
7172{
7173 u32 misccpctl;
7174
7175 /* WaTempDisableDOPClkGating:bdw */
7176 misccpctl = I915_READ(GEN7_MISCCPCTL);
7177 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7178
7179 I915_WRITE(GEN8_L3SQCREG1,
7180 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7181 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7182
7183 /*
7184 * Wait at least 100 clocks before re-enabling clock gating.
7185 * See the definition of L3SQCREG1 in BSpec.
7186 */
7187 POSTING_READ(GEN8_L3SQCREG1);
7188 udelay(1);
7189 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7190}
7191
9498dba7
MK		 7192static void kabylake_init_clock_gating(struct drm_device *dev)
7193{
9146f308 7194 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7195
b033bb6d 7196 gen9_init_clock_gating(dev);
9498dba7
MK		 7197
7198 /* WaDisableSDEUnitClockGating:kbl */
7199 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7200 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7201 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7202
7203 /* WaDisableGamClockGating:kbl */
7204 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7205 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7206 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7207
7208 /* WaFbcNukeOnHostModify:kbl */
7209 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7210 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7211}
7212
dc00b6a0
DV		 7213static void skylake_init_clock_gating(struct drm_device *dev)
7214{
c584e2d3 7215 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7216
b033bb6d 7217 gen9_init_clock_gating(dev);
44fff99f
MK		 7218
7219 /* WAC6entrylatency:skl */
7220 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7221 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7222
7223 /* WaFbcNukeOnHostModify:skl */
7224 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7225 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7226}
7227
47c2bd97 7228static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7229{
fac5e23e 7230 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7231 enum pipe pipe;
1020a5c2 7232
7ad0dbab 7233 ilk_init_lp_watermarks(dev);
50ed5fbd 7234
ab57fff1 7235 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7236 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7237
ab57fff1 7238 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7239 I915_WRITE(CHICKEN_PAR1_1,
7240 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7241
ab57fff1 7242 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7243 for_each_pipe(dev_priv, pipe) {
07d27e20 7244 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7245 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7246 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7247 }
63801f21 7248
ab57fff1
BW		 7249 /* WaVSRefCountFullforceMissDisable:bdw */
7250 /* WaDSRefCountFullforceMissDisable:bdw */
7251 I915_WRITE(GEN7_FF_THREAD_MODE,
7252 I915_READ(GEN7_FF_THREAD_MODE) &
7253 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7254
295e8bb7
VS		 7255 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7256 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7257
7258 /* WaDisableSDEUnitClockGating:bdw */
7259 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7260 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7261
450174fe
ID		 7262 /* WaProgramL3SqcReg1Default:bdw */
7263 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7264
6d50b065
VS		 7265 /*
7266 * WaGttCachingOffByDefault:bdw
7267 * GTT cache may not work with big pages, so if those
7268 * are ever enabled GTT cache may need to be disabled.
7269 */
7270 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7271
17e0adf0
MK		 7272 /* WaKVMNotificationOnConfigChange:bdw */
7273 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7274 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7275
89d6b2b8 7276 lpt_init_clock_gating(dev);
1020a5c2
BW		 7277}
7278
cad2a2d7
ED		 7279static void haswell_init_clock_gating(struct drm_device *dev)
7280{
fac5e23e 7281 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7282
017636cc 7283 ilk_init_lp_watermarks(dev);
cad2a2d7 7284
f3fc4884
FJ		 7285 /* L3 caching of data atomics doesn't work -- disable it. */
7286 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7287 I915_WRITE(HSW_ROW_CHICKEN3,
7288 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7289
ecdb4eb7 7290 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7291 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7292 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7293 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7294
e36ea7ff
VS		 7295 /* WaVSRefCountFullforceMissDisable:hsw */
7296 I915_WRITE(GEN7_FF_THREAD_MODE,
7297 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7298
4e04632e
AG		 7299 /* WaDisable_RenderCache_OperationalFlush:hsw */
7300 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7301
fe27c606
CW		 7302 /* enable HiZ Raw Stall Optimization */
7303 I915_WRITE(CACHE_MODE_0_GEN7,
7304 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7305
ecdb4eb7 7306 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7307 I915_WRITE(CACHE_MODE_1,
7308 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7309
a12c4967
VS		 7310 /*
7311 * BSpec recommends 8x4 when MSAA is used,
7312 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7313 *
7314 * Note that PS/WM thread counts depend on the WIZ hashing
7315 * disable bit, which we don't touch here, but it's good
7316 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7317 */
7318 I915_WRITE(GEN7_GT_MODE,
98533251 7319 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7320
94411593
KG		 7321 /* WaSampleCChickenBitEnable:hsw */
7322 I915_WRITE(HALF_SLICE_CHICKEN3,
7323 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7324
ecdb4eb7 7325 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7326 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7327
90a88643
PZ		 7328 /* WaRsPkgCStateDisplayPMReq:hsw */
7329 I915_WRITE(CHICKEN_PAR1_1,
7330 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7331
17a303ec 7332 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7333}
7334
1fa61106 7335static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7336{
fac5e23e 7337 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7338 uint32_t snpcr;
6f1d69b0 7339
017636cc 7340 ilk_init_lp_watermarks(dev);
6f1d69b0 7341
231e54f6 7342 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7343
ecdb4eb7 7344 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7345 I915_WRITE(_3D_CHICKEN3,
7346 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7347
ecdb4eb7 7348 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7349 I915_WRITE(IVB_CHICKEN3,
7350 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7351 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7352
ecdb4eb7 7353 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7354 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7355 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7356 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7357
4e04632e
AG		 7358 /* WaDisable_RenderCache_OperationalFlush:ivb */
7359 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7360
ecdb4eb7 7361 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7362 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7363 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7364
ecdb4eb7 7365 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7366 I915_WRITE(GEN7_L3CNTLREG1,
7367 GEN7_WA_FOR_GEN7_L3_CONTROL);
7368 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7369 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7370 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7371 I915_WRITE(GEN7_ROW_CHICKEN2,
7372 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7373 else {
7374 /* must write both registers */
7375 I915_WRITE(GEN7_ROW_CHICKEN2,
7376 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7377 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7378 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7379 }
6f1d69b0 7380
ecdb4eb7 7381 /* WaForceL3Serialization:ivb */
61939d97
JB		 7382 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7383 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7384
1b80a19a 7385 /*
0f846f81 7386 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7387 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7388 */
7389 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7390 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7391
ecdb4eb7 7392 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7393 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7394 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7395 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7396
0e088b8f 7397 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7398
7399 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7400
22721343
CW		 7401 if (0) { /* causes HiZ corruption on ivb:gt1 */
7402 /* enable HiZ Raw Stall Optimization */
7403 I915_WRITE(CACHE_MODE_0_GEN7,
7404 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7405 }
116f2b6d 7406
ecdb4eb7 7407 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7408 I915_WRITE(CACHE_MODE_1,
7409 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7410
a607c1a4
VS		 7411 /*
7412 * BSpec recommends 8x4 when MSAA is used,
7413 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7414 *
7415 * Note that PS/WM thread counts depend on the WIZ hashing
7416 * disable bit, which we don't touch here, but it's good
7417 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7418 */
7419 I915_WRITE(GEN7_GT_MODE,
98533251 7420 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7421
20848223
BW		 7422 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7423 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7424 snpcr |= GEN6_MBC_SNPCR_MED;
7425 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7426
6e266956 7427 if (!HAS_PCH_NOP(dev_priv))
ab5c608b 7428 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7429
7430 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7431}
7432
1fa61106 7433static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7434{
fac5e23e 7435 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7436
ecdb4eb7 7437 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7438 I915_WRITE(_3D_CHICKEN3,
7439 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7440
ecdb4eb7 7441 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7442 I915_WRITE(IVB_CHICKEN3,
7443 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7444 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7445
fad7d36e 7446 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7447 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7448 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7449 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7450 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7451
4e04632e
AG		 7452 /* WaDisable_RenderCache_OperationalFlush:vlv */
7453 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7454
ecdb4eb7 7455 /* WaForceL3Serialization:vlv */
61939d97
JB		 7456 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7457 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7458
ecdb4eb7 7459 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7460 I915_WRITE(GEN7_ROW_CHICKEN2,
7461 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7462
ecdb4eb7 7463 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7464 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7465 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7466 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7467
46680e0a
VS		 7468 gen7_setup_fixed_func_scheduler(dev_priv);
7469
3c0edaeb 7470 /*
0f846f81 7471 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7472 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7473 */
7474 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7475 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7476
c98f5062
AG		 7477 /* WaDisableL3Bank2xClockGate:vlv
7478 * Disabling L3 clock gating- MMIO 940c[25] = 1
7479 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7480 I915_WRITE(GEN7_UCGCTL4,
7481 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7482
afd58e79
VS		 7483 /*
7484 * BSpec says this must be set, even though
7485 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7486 */
6b26c86d
DV		 7487 I915_WRITE(CACHE_MODE_1,
7488 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7489
da2518f9
VS		 7490 /*
7491 * BSpec recommends 8x4 when MSAA is used,
7492 * however in practice 16x4 seems fastest.
7493 *
7494 * Note that PS/WM thread counts depend on the WIZ hashing
7495 * disable bit, which we don't touch here, but it's good
7496 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7497 */
7498 I915_WRITE(GEN7_GT_MODE,
7499 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7500
031994ee
VS		 7501 /*
7502 * WaIncreaseL3CreditsForVLVB0:vlv
7503 * This is the hardware default actually.
7504 */
7505 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7506
2d809570 7507 /*
ecdb4eb7 7508 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7509 * Disable clock gating on th GCFG unit to prevent a delay
7510 * in the reporting of vblank events.
7511 */
7a0d1eed 7512 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7513}
7514
a4565da8
VS		 7515static void cherryview_init_clock_gating(struct drm_device *dev)
7516{
fac5e23e 7517 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7518
232ce337
VS		 7519 /* WaVSRefCountFullforceMissDisable:chv */
7520 /* WaDSRefCountFullforceMissDisable:chv */
7521 I915_WRITE(GEN7_FF_THREAD_MODE,
7522 I915_READ(GEN7_FF_THREAD_MODE) &
7523 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7524
7525 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7526 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7527 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7528
7529 /* WaDisableCSUnitClockGating:chv */
7530 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7531 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7532
7533 /* WaDisableSDEUnitClockGating:chv */
7534 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7535 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7536
450174fe
ID		 7537 /*
7538 * WaProgramL3SqcReg1Default:chv
7539 * See gfxspecs/Related Documents/Performance Guide/
7540 * LSQC Setting Recommendations.
7541 */
7542 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7543
6d50b065
VS		 7544 /*
7545 * GTT cache may not work with big pages, so if those
7546 * are ever enabled GTT cache may need to be disabled.
7547 */
7548 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7549}
7550
1fa61106 7551static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7552{
fac5e23e 7553 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7554 uint32_t dspclk_gate;
7555
7556 I915_WRITE(RENCLK_GATE_D1, 0);
7557 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7558 GS_UNIT_CLOCK_GATE_DISABLE |
7559 CL_UNIT_CLOCK_GATE_DISABLE);
7560 I915_WRITE(RAMCLK_GATE_D, 0);
7561 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7562 OVRUNIT_CLOCK_GATE_DISABLE |
7563 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7564 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7565 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7566 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7567
7568 /* WaDisableRenderCachePipelinedFlush */
7569 I915_WRITE(CACHE_MODE_0,
7570 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7571
4e04632e
AG		 7572 /* WaDisable_RenderCache_OperationalFlush:g4x */
7573 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7574
0e088b8f 7575 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7576}
7577
1fa61106 7578static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7579{
fac5e23e 7580 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7581
7582 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7583 I915_WRITE(RENCLK_GATE_D2, 0);
7584 I915_WRITE(DSPCLK_GATE_D, 0);
7585 I915_WRITE(RAMCLK_GATE_D, 0);
7586 I915_WRITE16(DEUC, 0);
20f94967
VS		 7587 I915_WRITE(MI_ARB_STATE,
7588 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7589
7590 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7591 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7592}
7593
1fa61106 7594static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7595{
fac5e23e 7596 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7597
7598 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7599 I965_RCC_CLOCK_GATE_DISABLE |
7600 I965_RCPB_CLOCK_GATE_DISABLE |
7601 I965_ISC_CLOCK_GATE_DISABLE |
7602 I965_FBC_CLOCK_GATE_DISABLE);
7603 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7604 I915_WRITE(MI_ARB_STATE,
7605 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7606
7607 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7608 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7609}
7610
1fa61106 7611static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7612{
fac5e23e 7613 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7614 u32 dstate = I915_READ(D_STATE);
7615
7616 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7617 DSTATE_DOT_CLOCK_GATING;
7618 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7619
7620 if (IS_PINEVIEW(dev))
7621 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7622
7623 /* IIR "flip pending" means done if this bit is set */
7624 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7625
7626 /* interrupts should cause a wake up from C3 */
3299254f 7627 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7628
7629 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7630 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7631
7632 I915_WRITE(MI_ARB_STATE,
7633 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7634}
7635
1fa61106 7636static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7637{
fac5e23e 7638 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7639
7640 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7641
7642 /* interrupts should cause a wake up from C3 */
7643 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7644 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7645
7646 I915_WRITE(MEM_MODE,
7647 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7648}
7649
1fa61106 7650static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7651{
fac5e23e 7652 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7653
7654 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7655
7656 I915_WRITE(MEM_MODE,
7657 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7658 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7659}
7660
6f1d69b0
ED		 7661void intel_init_clock_gating(struct drm_device *dev)
7662{
fac5e23e 7663 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7664
bb400da9 7665 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7666}
7667
7d708ee4
ID		 7668void intel_suspend_hw(struct drm_device *dev)
7669{
6e266956 7670 if (HAS_PCH_LPT(to_i915(dev)))
7d708ee4
ID		 7671 lpt_suspend_hw(dev);
7672}
7673
bb400da9
ID		 7674static void nop_init_clock_gating(struct drm_device *dev)
7675{
7676 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7677}
7678
7679/**
7680 * intel_init_clock_gating_hooks - setup the clock gating hooks
7681 * @dev_priv: device private
7682 *
7683 * Setup the hooks that configure which clocks of a given platform can be
7684 * gated and also apply various GT and display specific workarounds for these
7685 * platforms. Note that some GT specific workarounds are applied separately
7686 * when GPU contexts or batchbuffers start their execution.
7687 */
7688void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7689{
7690 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7691 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7692 else if (IS_KABYLAKE(dev_priv))
9498dba7 7693 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7694 else if (IS_BROXTON(dev_priv))
7695 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7696 else if (IS_BROADWELL(dev_priv))
7697 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7698 else if (IS_CHERRYVIEW(dev_priv))
7699 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7700 else if (IS_HASWELL(dev_priv))
7701 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7702 else if (IS_IVYBRIDGE(dev_priv))
7703 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7704 else if (IS_VALLEYVIEW(dev_priv))
7705 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7706 else if (IS_GEN6(dev_priv))
7707 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7708 else if (IS_GEN5(dev_priv))
7709 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7710 else if (IS_G4X(dev_priv))
7711 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7712 else if (IS_CRESTLINE(dev_priv))
7713 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7714 else if (IS_BROADWATER(dev_priv))
7715 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7716 else if (IS_GEN3(dev_priv))
7717 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7718 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7719 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7720 else if (IS_GEN2(dev_priv))
7721 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7722 else {
7723 MISSING_CASE(INTEL_DEVID(dev_priv));
7724 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7725 }
7726}
7727
1fa61106
ED		 7728/* Set up chip specific power management-related functions */
7729void intel_init_pm(struct drm_device *dev)
7730{
fac5e23e 7731 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7732
7ff0ebcc 7733 intel_fbc_init(dev_priv);
1fa61106 7734
c921aba8
DV		 7735 /* For cxsr */
7736 if (IS_PINEVIEW(dev))
7737 i915_pineview_get_mem_freq(dev);
5db94019 7738 else if (IS_GEN5(dev_priv))
c921aba8
DV		 7739 i915_ironlake_get_mem_freq(dev);
7740
1fa61106 7741 /* For FIFO watermark updates */
f5ed50cb 7742 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7743 skl_setup_wm_latency(dev);
2d41c0b5 7744 dev_priv->display.update_wm = skl_update_wm;
98d39494 7745 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7746 } else if (HAS_PCH_SPLIT(dev_priv)) {
fa50ad61 7747 ilk_setup_wm_latency(dev);
53615a5e 7748
5db94019 7749 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7750 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7751 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7752 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7753 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7754 dev_priv->display.compute_intermediate_wm =
7755 ilk_compute_intermediate_wm;
7756 dev_priv->display.initial_watermarks =
7757 ilk_initial_watermarks;
7758 dev_priv->display.optimize_watermarks =
7759 ilk_optimize_watermarks;
bd602544
VS		 7760 } else {
7761 DRM_DEBUG_KMS("Failed to read display plane latency. "
7762 "Disable CxSR\n");
7763 }
920a14b2 7764 } else if (IS_CHERRYVIEW(dev_priv)) {
262cd2e1 7765 vlv_setup_wm_latency(dev);
262cd2e1 7766 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7767 } else if (IS_VALLEYVIEW(dev_priv)) {
26e1fe4f 7768 vlv_setup_wm_latency(dev);
26e1fe4f 7769 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7770 } else if (IS_PINEVIEW(dev)) {
50a0bc90 7771 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7772 dev_priv->is_ddr3,
7773 dev_priv->fsb_freq,
7774 dev_priv->mem_freq)) {
7775 DRM_INFO("failed to find known CxSR latency "
7776 "(found ddr%s fsb freq %d, mem freq %d), "
7777 "disabling CxSR\n",
7778 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7779 dev_priv->fsb_freq, dev_priv->mem_freq);
7780 /* Disable CxSR and never update its watermark again */
5209b1f4 7781 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7782 dev_priv->display.update_wm = NULL;
7783 } else
7784 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7785 } else if (IS_G4X(dev_priv)) {
1fa61106 7786 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7787 } else if (IS_GEN4(dev_priv)) {
1fa61106 7788 dev_priv->display.update_wm = i965_update_wm;
5db94019 7789 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7790 dev_priv->display.update_wm = i9xx_update_wm;
7791 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7792 } else if (IS_GEN2(dev_priv)) {
feb56b93
DV		 7793 if (INTEL_INFO(dev)->num_pipes == 1) {
7794 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7795 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7796 } else {
7797 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7798 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7799 }
feb56b93
DV		 7800 } else {
7801 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7802 }
7803}
7804
87660502
L		 7805static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7806{
7807 uint32_t flags =
7808 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7809
7810 switch (flags) {
7811 case GEN6_PCODE_SUCCESS:
7812 return 0;
7813 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7814 case GEN6_PCODE_ILLEGAL_CMD:
7815 return -ENXIO;
7816 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7817 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7818 return -EOVERFLOW;
7819 case GEN6_PCODE_TIMEOUT:
7820 return -ETIMEDOUT;
7821 default:
7822 MISSING_CASE(flags)
7823 return 0;
7824 }
7825}
7826
7827static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7828{
7829 uint32_t flags =
7830 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7831
7832 switch (flags) {
7833 case GEN6_PCODE_SUCCESS:
7834 return 0;
7835 case GEN6_PCODE_ILLEGAL_CMD:
7836 return -ENXIO;
7837 case GEN7_PCODE_TIMEOUT:
7838 return -ETIMEDOUT;
7839 case GEN7_PCODE_ILLEGAL_DATA:
7840 return -EINVAL;
7841 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7842 return -EOVERFLOW;
7843 default:
7844 MISSING_CASE(flags);
7845 return 0;
7846 }
7847}
7848
151a49d0 7849int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7850{
87660502
L		 7851 int status;
7852
4fc688ce 7853 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7854
3f5582dd
CW		 7855 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7856 * use te fw I915_READ variants to reduce the amount of work
7857 * required when reading/writing.
7858 */
7859
7860 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7861 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7862 return -EAGAIN;
7863 }
7864
3f5582dd
CW		 7865 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7866 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7867 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7868
3f5582dd
CW		 7869 if (intel_wait_for_register_fw(dev_priv,
7870 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7871 500)) {
42c0526c
BW		 7872 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7873 return -ETIMEDOUT;
7874 }
7875
3f5582dd
CW		 7876 *val = I915_READ_FW(GEN6_PCODE_DATA);
7877 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7878
87660502
L		 7879 if (INTEL_GEN(dev_priv) > 6)
7880 status = gen7_check_mailbox_status(dev_priv);
7881 else
7882 status = gen6_check_mailbox_status(dev_priv);
7883
7884 if (status) {
7885 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7886 status);
7887 return status;
7888 }
7889
42c0526c
BW		 7890 return 0;
7891}
7892
3f5582dd 7893int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7894 u32 mbox, u32 val)
42c0526c 7895{
87660502
L		 7896 int status;
7897
4fc688ce 7898 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7899
3f5582dd
CW		 7900 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7901 * use te fw I915_READ variants to reduce the amount of work
7902 * required when reading/writing.
7903 */
7904
7905 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7906 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7907 return -EAGAIN;
7908 }
7909
3f5582dd
CW		 7910 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7911 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7912
3f5582dd
CW		 7913 if (intel_wait_for_register_fw(dev_priv,
7914 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7915 500)) {
42c0526c
BW		 7916 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7917 return -ETIMEDOUT;
7918 }
7919
3f5582dd 7920 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7921
87660502
L		 7922 if (INTEL_GEN(dev_priv) > 6)
7923 status = gen7_check_mailbox_status(dev_priv);
7924 else
7925 status = gen6_check_mailbox_status(dev_priv);
7926
7927 if (status) {
7928 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7929 status);
7930 return status;
7931 }
7932
42c0526c
BW		 7933 return 0;
7934}
a0e4e199 7935
dd06f88c
VS		 7936static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7937{
c30fec65
VS		 7938 /*
7939 * N = val - 0xb7
7940 * Slow = Fast = GPLL ref * N
7941 */
7942 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7943}
7944
b55dd647 7945static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7946{
c30fec65 7947 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7948}
7949
b55dd647 7950static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7951{
c30fec65
VS		 7952 /*
7953 * N = val / 2
7954 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7955 */
7956 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7957}
7958
b55dd647 7959static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7960{
1c14762d 7961 /* CHV needs even values */
c30fec65 7962 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7963}
7964
616bc820 7965int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7966{
2d1fe073 7967 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7968 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7969 GEN9_FREQ_SCALER);
2d1fe073 7970 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7971 return chv_gpu_freq(dev_priv, val);
2d1fe073 7972 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7973 return byt_gpu_freq(dev_priv, val);
7974 else
7975 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7976}
7977
616bc820
VS		 7978int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7979{
2d1fe073 7980 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7981 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7982 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7983 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7984 return chv_freq_opcode(dev_priv, val);
2d1fe073 7985 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7986 return byt_freq_opcode(dev_priv, val);
7987 else
500a3d2e 7988 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7989}
22b1b2f8 7990
6ad790c0
CW		 7991struct request_boost {
7992 struct work_struct work;
eed29a5b 7993 struct drm_i915_gem_request *req;
6ad790c0
CW		 7994};
7995
7996static void __intel_rps_boost_work(struct work_struct *work)
7997{
7998 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7999 struct drm_i915_gem_request *req = boost->req;
6ad790c0 8000
f69a02c9 8001 if (!i915_gem_request_completed(req))
c033666a 8002 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 8003
e8a261ea 8004 i915_gem_request_put(req);
6ad790c0
CW		 8005 kfree(boost);
8006}
8007
91d14251 8008void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8009{
8010 struct request_boost *boost;
8011
91d14251 8012 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8013 return;
8014
f69a02c9 8015 if (i915_gem_request_completed(req))
e61b9958
CW		 8016 return;
8017
6ad790c0
CW		 8018 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8019 if (boost == NULL)
8020 return;
8021
e8a261ea 8022 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8023
8024 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8025 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8026}
8027
f742a552 8028void intel_pm_setup(struct drm_device *dev)
907b28c5 8029{
fac5e23e 8030 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8031
f742a552 8032 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8033 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8034
54b4f68f
CW		 8035 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8036 __intel_autoenable_gt_powersave);
1854d5ca 8037 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8038
33688d95 8039 dev_priv->pm.suspended = false;
1f814dac 8040 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 8041 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 8042}
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